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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2004 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [125:0] a;
wire q;
sub sub (
.q (q),
.a (a),
.clk (clk));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= 126'b1000;
end
if (cyc==2) begin
a <= 126'h1001;
end
if (cyc==3) begin
a <= 126'h1010;
end
if (cyc==4) begin
a <= 126'h1111;
if (q !== 1'b0) $stop;
end
if (cyc==5) begin
if (q !== 1'b1) $stop;
end
if (cyc==6) begin
if (q !== 1'b0) $stop;
end
if (cyc==7) begin
if (q !== 1'b0) $stop;
end
if (cyc==8) begin
if (q !== 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (
input clk,
input [125:0] a,
output reg q
);
// verilator public_module
reg [125:0] g_r;
wire [127:0] g_extend = { g_r, 1'b1, 1'b0 };
reg [6:0] sel;
wire g_sel = g_extend[sel];
always @ (posedge clk) begin
g_r <= a;
sel <= a[6:0];
q <= g_sel;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O211AI_PP_BLACKBOX_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o211ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_PP_BLACKBOX_V
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
module alt_mem_ddrx_wdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 16,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 5,
CFG_DATA_ID_WIDTH = 4,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_TBP_NUM = 8,
CFG_BUFFER_ADDR_WIDTH = 10,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_WDATA_REG = 0,
CFG_PARTIAL_BE_PER_WORD_ENABLE = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_enable_ecc_code_overwrites,
cfg_interface_width,
// command generator & TBP command load interface / cmd update interface
wdatap_free_id_valid,
wdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
tbp_load_index,
proc_size,
// input interface data channel / buffer write interface
wr_data_mem_full,
write_data_en,
write_data,
byte_en,
// notify TBP interface
data_complete,
data_rmw_complete,
data_partial_be,
// AFI interface / buffer read interface
doing_write,
dataid,
dataid_vector,
rdwr_data_valid,
rmw_correct,
rmw_partial,
doing_write_first,
dataid_first,
dataid_vector_first,
rdwr_data_valid_first,
rmw_correct_first,
rmw_partial_first,
doing_write_first_vector,
rdwr_data_valid_first_vector,
doing_write_last,
dataid_last,
dataid_vector_last,
rdwr_data_valid_last,
rmw_correct_last,
rmw_partial_last,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_dm,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
// RMW fifo interface, from rdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_BURSTCOUNT_TRACKING_WIDTH = CFG_BUFFER_ADDR_WIDTH+1;
localparam CFG_RMWFIFO_ECC_DBE_WIDTH = CFG_ECC_MULTIPLES;
localparam CFG_RMWFIFO_ECC_CODE_WIDTH = CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RMWFIFO_ECC_DBE_WIDTH + CFG_RMWFIFO_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_ADDR_WIDTH = (CFG_INT_SIZE_WIDTH == 1) ? CFG_INT_SIZE_WIDTH : CFG_INT_SIZE_WIDTH-1;
localparam CFG_LOCAL_BE_WIDTH = CFG_LOCAL_DATA_WIDTH / 8;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS; // to get the correct DM width based on x4 or x8 mode
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
localparam CFG_WR_DATA_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DATA_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
localparam CFG_WR_DM_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DM_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
// -----------------------------
// port declaration
// -----------------------------
// clock and reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
output wdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
// command generator & TBP command load interface / cmd update interface
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_write;
input [CFG_TBP_NUM-1:0] tbp_load_index;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
output wr_data_mem_full;
input write_data_en;
input [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
input [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
output [CFG_TBP_NUM-1:0] data_complete;
output data_rmw_complete; // broadcast to TBP's
output data_partial_be;
// AFI interface / buffer read interface
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
input doing_write_first;
input [CFG_DATA_ID_WIDTH-1:0] dataid_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_first;
input rdwr_data_valid_first;
input rmw_correct_first;
input rmw_partial_first;
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write_first_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid_first_vector;
input doing_write_last;
input [CFG_DATA_ID_WIDTH-1:0] dataid_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_last;
input rdwr_data_valid_last;
input rmw_correct_last;
input rmw_partial_last;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
output wdatap_rmw_partial;
output wdatap_rmw_correct;
output [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
output [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
input rmwfifo_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
input [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
wire [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
wire wdatap_free_id_valid;
wire wdatap_int_free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_free_id_dataid_vector;
// command generator & TBP command load interface / cmd update interface
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire [CFG_TBP_NUM-1:0] tbp_load_index;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
wire wr_data_mem_full;
wire write_data_en;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
// AFI interface / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
reg [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// signal declaration
// -----------------------------
// configuration
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
// command generator & TBP command load interface / cmd update interface
wire wdatap_cmdload_ready;
wire wdatap_cmdload_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_cmdload_dataid;
wire [CFG_TBP_NUM-1:0] wdatap_cmdload_tbp_index;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_cmdload_burstcount;
// input interface data channel / buffer write interface
wire wdatap_datawrite_ready;
wire wdatap_datawrite_valid;
wire wdatap_datawrite_accepted;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_datawrite_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] wdatap_datawrite_be;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_datawrite_dm;
reg [CFG_LOCAL_DM_WIDTH-1:0] int_datawrite_dm;
wire wdatap_datawrite_partial_dm;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_datawrite_address;
reg [CFG_ECC_MULTIPLES-1:0] int_datawrite_partial_dm;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] wdatap_tbp_data_ready;
wire wdatap_tbp_data_partial_be;
// AFI interface data channel / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_r;
wire wdatap_dataread_valid_first;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_first;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid_first_vector;
wire wdatap_dataread_valid_last;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_last;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_datavalid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_correct_data;
reg wdatap_dataread_rmw_partial;
reg wdatap_dataread_rmw_correct;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_dm;
wire [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_dataread_address;
wire wdatap_dataread_done;
wire wdatap_dataread_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_buffer_data;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_buffer_dm;
wire wdatap_free_id_get_ready;
wire wdatap_allocated_put_ready;
wire wdatap_allocated_put_valid;
wire wdatap_update_data_dataid_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_update_data_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_update_data_dataid_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_next_burstcount;
wire wdatap_notify_data_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_notify_data_burstcount_consumed;
// buffer read/write signals
wire wdatap_buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffwrite_address;
wire wdatap_buffread_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffread_address;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_input;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_output;
wire rmwfifo_output_read;
wire rmwfifo_output_valid;
reg rmwfifo_output_valid_r;
wire rmwfifo_output_valid_pulse;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_output_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_output_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_output_ecc_code;
reg [CFG_LOCAL_DATA_WIDTH-1:0] rmw_merged_data;
reg rmw_correct_r;
reg rmw_partial_r;
wire rmwfifo_ready;
// debug signals, for assertions
wire err_rmwfifo_overflow;
// -----------------------------
// module definition
// -----------------------------
// renaming port names to more meaningfull internal names
assign wdatap_cmdload_valid = ~proc_busy & proc_load & proc_write & proc_load_dataid;
assign wdatap_cmdload_tbp_index = tbp_load_index;
assign wdatap_cmdload_burstcount = proc_size;
assign wdatap_cmdload_dataid = wdatap_free_id_dataid;
assign wr_data_mem_full = ~wdatap_datawrite_ready;
assign wdatap_datawrite_valid = write_data_en;
assign wdatap_datawrite_data = write_data;
assign wdatap_datawrite_be = byte_en; // we need to replicate
assign data_complete = wdatap_tbp_data_ready;
assign data_rmw_complete = rmwfifo_output_valid_pulse; // broadcast to all TBP's
assign data_partial_be = wdatap_tbp_data_partial_be;
assign wdatap_dataread_valid = doing_write & rdwr_data_valid & ~rmw_correct;
assign wdatap_dataread_dataid = dataid;
assign wdatap_dataread_dataid_vector = dataid_vector;
assign wdatap_dataread_valid_first = doing_write_first & rdwr_data_valid_first & ~rmw_correct_first;
assign wdatap_dataread_dataid_first = dataid_first;
assign wdatap_dataread_dataid_vector_first = dataid_vector_first;
assign wdatap_dataread_valid_first_vector = rdwr_data_valid_first_vector;
assign wdatap_dataread_valid_last = doing_write_last & rdwr_data_valid_last & ~rmw_correct_last ;
assign wdatap_dataread_dataid_last = dataid_last;
assign wdatap_dataread_dataid_vector_last = dataid_vector_last;
assign wdatap_data = wdatap_dataread_data;
assign wdatap_rmw_partial_data = wdatap_dataread_rmw_partial_data;
assign wdatap_rmw_correct_data = wdatap_dataread_rmw_correct_data;
assign wdatap_rmw_partial = wdatap_dataread_rmw_partial;
assign wdatap_rmw_correct = wdatap_dataread_rmw_correct;
assign wdatap_dm = wdatap_dataread_dm;
// internal signals
// flow control between free list & allocated list
assign wdatap_free_id_get_ready = wdatap_cmdload_valid;
assign wdatap_allocated_put_valid= wdatap_free_id_get_ready & wdatap_free_id_valid;
assign wdatap_free_id_valid = wdatap_int_free_id_valid & wdatap_cmdload_ready;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
cfg_dram_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH; // SPR:362973
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
//reset state ...
wdatap_dataread_dataid_r <= 0;
end
else
begin
//active state ...
wdatap_dataread_dataid_r <= wdatap_dataread_dataid;
end
end
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
wdatap_list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_free_id_get_ready),
.list_get_entry_valid (wdatap_int_free_id_valid),
.list_get_entry_id (wdatap_free_id_dataid),
.list_get_entry_id_vector (wdatap_free_id_dataid_vector),
// wdatap_dataread_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_dataread_ready),
.list_put_entry_valid (wdatap_dataread_done),
.list_put_entry_id (wdatap_dataread_dataid_r)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
wdatap_list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_notify_data_valid),
.list_get_entry_valid (wdatap_update_data_dataid_valid),
.list_get_entry_id (wdatap_update_data_dataid),
.list_get_entry_id_vector (wdatap_update_data_dataid_vector),
// wdatap_allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_allocated_put_ready),
.list_put_entry_valid (wdatap_allocated_put_valid),
.list_put_entry_id (wdatap_free_id_dataid)
);
alt_mem_ddrx_burst_tracking
# (
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH)
)
wdatap_burst_tracking_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// data burst interface
.burst_ready (wdatap_datawrite_ready),
.burst_valid (wdatap_datawrite_valid),
// burstcount counter sent to data_id_manager
.burst_pending_burstcount (wdatap_update_data_burstcount),
.burst_next_pending_burstcount (wdatap_update_data_next_burstcount),
// burstcount consumed by data_id_manager
.burst_consumed_valid (wdatap_notify_data_valid),
.burst_counsumed_burstcount (wdatap_notify_data_burstcount_consumed)
);
alt_mem_ddrx_dataid_manager
# (
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH),
.CFG_TBP_NUM (CFG_TBP_NUM),
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO)
)
wdatap_dataid_manager_inst
(
// clock & reset
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// configuration signals
.cfg_burst_length (cfg_burst_length),
.cfg_enable_ecc (cfg_enable_ecc),
.cfg_enable_auto_corr (cfg_enable_auto_corr),
.cfg_enable_no_dm (cfg_enable_no_dm),
// update cmd interface
.update_cmd_if_ready (wdatap_cmdload_ready),
.update_cmd_if_valid (wdatap_cmdload_valid),
.update_cmd_if_data_id (wdatap_cmdload_dataid),
.update_cmd_if_burstcount (wdatap_cmdload_burstcount),
.update_cmd_if_tbp_id (wdatap_cmdload_tbp_index),
// update data interface
.update_data_if_valid (wdatap_update_data_dataid_valid),
.update_data_if_data_id (wdatap_update_data_dataid),
.update_data_if_data_id_vector (wdatap_update_data_dataid_vector),
.update_data_if_burstcount (wdatap_update_data_burstcount),
.update_data_if_next_burstcount (wdatap_update_data_next_burstcount),
// notify data interface
.notify_data_if_valid (wdatap_notify_data_valid),
.notify_data_if_burstcount (wdatap_notify_data_burstcount_consumed),
// notify tbp interface
.notify_tbp_data_ready (wdatap_tbp_data_ready),
.notify_tbp_data_partial_be (wdatap_tbp_data_partial_be),
// buffer write address generate interface
.write_data_if_ready (wdatap_datawrite_ready),
.write_data_if_valid (wdatap_datawrite_valid),
.write_data_if_accepted (wdatap_datawrite_accepted),
.write_data_if_address (wdatap_datawrite_address),
.write_data_if_partial_dm (wdatap_datawrite_partial_dm),
// read data interface
.read_data_if_valid (wdatap_dataread_valid),
.read_data_if_data_id (wdatap_dataread_dataid),
.read_data_if_data_id_vector (wdatap_dataread_dataid_vector),
.read_data_if_valid_first (wdatap_dataread_valid_first),
.read_data_if_data_id_first (wdatap_dataread_dataid_first),
.read_data_if_data_id_vector_first (wdatap_dataread_dataid_vector_first),
.read_data_if_valid_first_vector (wdatap_dataread_valid_first_vector),
.read_data_if_valid_last (wdatap_dataread_valid_last),
.read_data_if_data_id_last (wdatap_dataread_dataid_last),
.read_data_if_data_id_vector_last (wdatap_dataread_dataid_vector_last),
.read_data_if_address (wdatap_dataread_address),
.read_data_if_datavalid (wdatap_dataread_datavalid),
.read_data_if_done (wdatap_dataread_done) // use with wdatap_dataread_dataid_r
);
genvar wdatap_m;
genvar wdatap_n;
generate
for (wdatap_m = 0;wdatap_m < CFG_DWIDTH_RATIO;wdatap_m = wdatap_m + 1)
begin : wdata_buffer_per_dwidth_ratio
for (wdatap_n = 0;wdatap_n < CFG_LOCAL_WLAT_GROUP;wdatap_n = wdatap_n + 1)
begin : wdata_buffer_per_dqs_group
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DATA_WIDTH_PER_DQS_GROUP)
)
wdatap_buffer_data_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (wdatap_datawrite_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)])
);
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DM_WIDTH_PER_DQS_GROUP)
)
wdatap_buffer_be_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (int_datawrite_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)])
);
end
end
endgenerate
//
// byteenables analysis & generation
//
// - generate partial byteenable signal, per DQ word or per local word
// - set unused interface width byteenables to either 0 or 1
//
genvar wdatap_j, wdatap_k;
generate
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1 [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0 [CFG_ECC_MULTIPLES-1:0];
assign wdatap_datawrite_partial_dm = |int_datawrite_partial_dm;
for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
begin : local_dm
always @ (*)
begin
if (CFG_MEM_IF_DQ_PER_DQS == 4)
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
end
else
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
end
end
end
for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1)
begin : gen_partial_be
wire dm_all_ones = &int_datawrite_dm_unused1[wdatap_j];
wire dm_all_zeros = ~(|int_datawrite_dm_unused0[wdatap_j]);
always @ (*)
begin
wdatap_datawrite_dm_widthratio [wdatap_j] = wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
end
for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
begin : gen_dm_unused_bits
always @ (*)
begin
if (wdatap_k < cfg_dram_dm_width)
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
end
else
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = {1'b1};
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = {1'b0};
end
end
end
always @ (*)
begin
// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
if (cfg_enable_no_dm)
begin
int_datawrite_partial_dm[wdatap_j] = ~dm_all_ones;
end
else
begin
int_datawrite_partial_dm[wdatap_j] = ~( dm_all_ones | dm_all_zeros );
end
if (cfg_enable_ecc)
begin
if (dm_all_zeros)
begin
// no ECC code will be written
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
else
begin
// higher unused be bit will be used for ECC word
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
end
end
else
begin
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
end
end
endgenerate
//
// rmw data fifo
//
// assume rmw data for 2 commands doesn't came back to back, causing rmwfifo_output_valid_pulse not to be generated for 2nd commands data
assign rmwfifo_output_valid_pulse = rmwfifo_output_valid & ~rmwfifo_output_valid_r;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rmwfifo_output_valid_r <= 1'b0;
rmw_correct_r <= 1'b0;
rmw_partial_r <= 1'b0;
end
else
begin
rmwfifo_output_valid_r <= rmwfifo_output_valid;
rmw_correct_r <= rmw_correct;
rmw_partial_r <= rmw_partial;
end
end
assign rmwfifo_input = {rmwfifo_ecc_code, rmwfifo_ecc_dbe, rmwfifo_data};
assign {rmwfifo_output_ecc_code, rmwfifo_output_ecc_dbe, rmwfifo_output_data} = rmwfifo_output;
assign rmwfifo_output_read = rmw_correct_r | (&wdatap_dataread_datavalid & rmw_partial_r); // wdatap_dataread_datavalid must be all high together in ECC case (afi_wlat same for all DQS group), limitation in 11.0sp1
assign err_rmwfifo_overflow = rmwfifo_data_valid & ~rmwfifo_ready;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_RMWDATA_FIFO_DATA_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_RMWDATA_FIFO_ADDR_WIDTH)
)
rmw_data_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rmwfifo_output_read),
.get_valid (rmwfifo_output_valid),
.get_data (rmwfifo_output),
.put_ready (rmwfifo_ready),
.put_valid (rmwfifo_data_valid),
.put_data (rmwfifo_input)
);
//
// rmw data merge block
//
genvar wdatap_i;
generate
for (wdatap_i = 0; wdatap_i < ((CFG_LOCAL_DM_WIDTH)); wdatap_i = wdatap_i + 1)
begin : gen_rmw_data_merge
always @ (*)
begin
if (wdatap_dataread_buffer_dm[wdatap_i])
begin
// data from wdatap buffer
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = wdatap_dataread_buffer_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
else
begin
// data from rmwfifo
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
end
end
endgenerate
//
// wdata output mux
//
// drives wdatap_data & wdatap_be from either of
// if cfg_enabled etc ?
// - wdatap buffer (~rmw_correct & ~rmw_partial)
// - rmwfifo (rmw_correct)
// - merged wdatap buffer & rmwfifo (rmw_partial)
//
generate
if (CFG_WDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_dataread_dm <= 0;
wdatap_dataread_data <= 0;
wdatap_dataread_rmw_partial_data <= 0;
wdatap_dataread_rmw_correct_data <= 0;
wdatap_dataread_rmw_partial <= 0;
wdatap_dataread_rmw_correct <= 0;
end
else
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data <= wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data <= rmw_merged_data;
wdatap_dataread_rmw_correct_data <= rmwfifo_output_data;
wdatap_dataread_rmw_partial <= rmw_partial_r;
wdatap_dataread_rmw_correct <= rmw_correct_r;
if (rmw_correct_r | rmw_partial_r)
begin
wdatap_dataread_dm <= {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm <= wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm <= wdatap_dataread_buffer_dm;
wdatap_dataread_data <= wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data <= 0;
wdatap_dataread_rmw_correct_data <= 0;
wdatap_dataread_rmw_partial <= 1'b0;
wdatap_dataread_rmw_correct <= 1'b0;
end
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_ecc_code <= 0;
wdatap_ecc_code_overwrite <= 0;
end
else
begin
wdatap_ecc_code <= rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r)
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = rmw_merged_data;
wdatap_dataread_rmw_correct_data = rmwfifo_output_data;
wdatap_dataread_rmw_partial = rmw_partial_r;
wdatap_dataread_rmw_correct = rmw_correct_r;
if (rmw_correct_r | rmw_partial_r)
begin
wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = 0;
wdatap_dataread_rmw_correct_data = 0;
wdatap_dataread_rmw_partial = 1'b0;
wdatap_dataread_rmw_correct = 1'b0;
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (*)
begin
wdatap_ecc_code = rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r)
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// Author: Yu-Sheng Lin [email protected]
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
int cyc;
reg rstn;
parameter real fst_gparam_real = 1.23;
localparam real fst_lparam_real = 4.56;
real fst_real = 1.23;
integer fst_integer;
bit fst_bit;
logic fst_logic;
int fst_int;
shortint fst_shortint;
longint fst_longint;
byte fst_byte;
parameter fst_parameter = 123;
localparam fst_lparam = 456;
supply0 fst_supply0;
supply1 fst_supply1;
tri0 fst_tri0;
tri1 fst_tri1;
tri fst_tri;
wire fst_wire;
logic [4:0] state;
Test test (/*AUTOINST*/
// Outputs
.state (state[4:0]),
// Inputs
.clk (clk),
.rstn (rstn));
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
rstn <= ~'1;
end
else if (cyc<10) begin
rstn <= ~'1;
end
else if (cyc<90) begin
rstn <= ~'0;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (
input clk,
input rstn,
output logic [4:0] state
);
logic [4:0] state_w;
logic [4:0] state_array [3];
assign state = state_array[0];
always_comb begin
state_w[4] = state_array[2][0];
state_w[3] = state_array[2][4];
state_w[2] = state_array[2][3] ^ state_array[2][0];
state_w[1] = state_array[2][2];
state_w[0] = state_array[2][1];
end
always_ff @(posedge clk or negedge rstn) begin
if (!rstn) begin
for (int i = 0; i < 3; i++)
state_array[i] <= 'b1;
end
else begin
for (int i = 0; i < 2; i++)
state_array[i] <= state_array[i+1];
state_array[2] <= state_w;
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 6,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dadd_3_full_dsp_64 ANN_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/*
* .--------------. .----------------. .------------.
* | .------------. | .--------------. | .----------. |
* | | ____ ____ | | | ____ ____ | | | ______ | |
* | ||_ || _|| | ||_ \ / _|| | | .' ___ || |
* ___ _ __ ___ _ __ | | | |__| | | | | | \/ | | | |/ .' \_|| |
* / _ \| '_ \ / _ \ '_ \ | | | __ | | | | | |\ /| | | | || | | |
* (_) | |_) | __/ | | || | _| | | |_ | | | _| |_\/_| |_ | | |\ `.___.'\| |
* \___/| .__/ \___|_| |_|| ||____||____|| | ||_____||_____|| | | `._____.'| |
* | | | | | | | | | | | |
* |_| | '------------' | '--------------' | '----------' |
* '--------------' '----------------' '------------'
*
* openHMC - An Open Source Hybrid Memory Cube Controller
* (C) Copyright 2014 Computer Architecture Group - University of Heidelberg
* www.ziti.uni-heidelberg.de
* B6, 26
* 68159 Mannheim
* Germany
*
* Contact: [email protected]
* http://ra.ziti.uni-heidelberg.de/openhmc
*
* This source file is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This source file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this source file. If not, see <http://www.gnu.org/licenses/>.
*
*
* Module name: openhmc_sync_fifo_reg_stage
*
*/
`default_nettype none
module openhmc_sync_fifo_reg_stage #(parameter DWIDTH = 8)(
input wire clk,
input wire res_n,
input wire [DWIDTH-1:0] d_in,
input wire [DWIDTH-1:0] d_in_p,
input wire p_full, // full signal from the previous stage
input wire n_full, // full signal from the next stage
input wire si,
input wire so,
output reg full, // full = '1' -> this stage has a valid entry
output reg [DWIDTH-1:0] d_out
);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------WIRING AND SIGNAL STUFF---------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
wire en, muxi;
assign en = (si & so & full) // so and si, shift through
| (si & ~so & ~full && n_full) // shift in new value
| (~si & so & p_full); // shift through
assign muxi = (si & ~so) | (si & so & ~p_full & full);
//=====================================================================================================
//-----------------------------------------------------------------------------------------------------
//---------LOGIC STARTS HERE---------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------------
//=====================================================================================================
always @ (posedge clk or negedge res_n) begin
if (!res_n) begin
full <= 1'b0;
d_out <= {DWIDTH{1'b0}};
end else begin
if (en) begin
if (muxi) begin
d_out <= d_in; // enter new value when enabled
end else begin
d_out <= d_in_p; // shift through
end
end
full <= (full & si) // stay full while si to other stage
| (full & ~si & ~so) // hold full
| (~si & so & p_full) // keep full as long as prev stage is full
| (si & ~so & n_full); // fill this stage by si
end
end
endmodule
`default_nettype wire
|
/*
* Copyright (c) 2015 Steven Stallion
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
`timescale 1ns / 10ps
module addr_decode(input [3:0] addr,
output r, s, t, x, y, z);
assign x = !(addr <= 4'b0111); // X 0x0000 0x7FFF RAM
assign t = !(addr == 4'b1010); // T 0xA000 0xAFFF
assign s = !(addr == 4'b1011); // S 0xB000 0xBFFF
assign r = !(addr == 4'b1100); // R 0xC000 0xCFFF
assign z = !(addr == 4'b1101); // Z 0xD000 0xDFFF PIA
assign y = !(addr >= 4'b1110); // Y 0xE000 0xFFFF EEPROM
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes an active-high asynchronous reset signal to a given clock by
* using a pipeline of N registers.
*/
module sync_reset #(
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire rst,
output wire sync_reset_out
);
reg [N-1:0] sync_reg = {N{1'b1}};
assign sync_reset_out = sync_reg[N-1];
always @(posedge clk or posedge rst) begin
if (rst)
sync_reg <= {N{1'b1}};
else
sync_reg <= {sync_reg[N-2:0], 1'b0};
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/17/2016 05:20:59 PM
// Design Name:
// Module Name: Priority_Codec_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Priority_Codec_32(
input wire [25:0] Data_Dec_i,
output reg [4:0] Data_Bin_o
);
always @(Data_Dec_i)
begin
if(~Data_Dec_i[25]) begin Data_Bin_o = 5'b00000;//0
end else if(~Data_Dec_i[24]) begin Data_Bin_o = 5'b00001;//1
end else if(~Data_Dec_i[23]) begin Data_Bin_o = 5'b00010;//2
end else if(~Data_Dec_i[22]) begin Data_Bin_o = 5'b00011;//3
end else if(~Data_Dec_i[21]) begin Data_Bin_o = 5'b00100;//4
end else if(~Data_Dec_i[20]) begin Data_Bin_o = 5'b00101;//5
end else if(~Data_Dec_i[19]) begin Data_Bin_o = 5'b00110;//6
end else if(~Data_Dec_i[18]) begin Data_Bin_o = 5'b00111;//7
end else if(~Data_Dec_i[17]) begin Data_Bin_o = 5'b01000;//8
end else if(~Data_Dec_i[16]) begin Data_Bin_o = 5'b01001;//9
end else if(~Data_Dec_i[15]) begin Data_Bin_o = 5'b01010;//10
end else if(~Data_Dec_i[14]) begin Data_Bin_o = 5'b01011;//11
end else if(~Data_Dec_i[13]) begin Data_Bin_o = 5'b01100;//12
end else if(~Data_Dec_i[12]) begin Data_Bin_o = 5'b01101;//13
end else if(~Data_Dec_i[11]) begin Data_Bin_o = 5'b01110;//14
end else if(~Data_Dec_i[10]) begin Data_Bin_o = 5'b01111;//15
end else if(~Data_Dec_i[9]) begin Data_Bin_o = 5'b10000;//16
end else if(~Data_Dec_i[8]) begin Data_Bin_o = 5'b10001;//17
end else if(~Data_Dec_i[7]) begin Data_Bin_o = 5'b10010;//18
end else if(~Data_Dec_i[6]) begin Data_Bin_o = 5'b10011;//19
end else if(~Data_Dec_i[5]) begin Data_Bin_o = 5'b10100;//20
end else if(~Data_Dec_i[4]) begin Data_Bin_o = 5'b10101;//21
end else if(~Data_Dec_i[3]) begin Data_Bin_o = 5'b10110;//22
end else if(~Data_Dec_i[2]) begin Data_Bin_o = 5'b10111;//23
end else if(~Data_Dec_i[1]) begin Data_Bin_o = 5'b11000;//24
end else if(~Data_Dec_i[0]) begin Data_Bin_o = 5'b10101;//25
end
else Data_Bin_o = 5'b00000;//zero value
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks.
// SPDX-License-Identifier: CC0-1.0
`define WIDTH 2
module top (
input OE1,
input OE2,
input [`WIDTH-1:0] A1,
input [`WIDTH-1:0] A2,
output [`WIDTH-1:0] Y1,
output [`WIDTH-1:0] Y2,
output [`WIDTH-1:0] Y3,
output [`WIDTH**2-1:0] W);
assign W[A1] = (OE2) ? A2[0] : 1'bz;
assign W[A2] = (OE1) ? A2[1] : 1'bz;
// have 2 different 'chips' drive the PAD to act like a bi-directional bus
wire [`WIDTH-1:0] PAD;
io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD));
io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD));
assign Y3 = PAD;
pullup p1(PAD);
// pulldown p1(PAD);
wire [5:0] fill = { 4'b0, A1 };
endmodule
module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD);
io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD));
endmodule
module io (input OE, input I, output O, inout PAD);
assign O = PAD;
assign PAD = OE ? I : 1'bz;
endmodule
|
(** * Basics: Functional Programming and Reasoning About Programs *)
(* ###################################################################### *)
(** * Enumerated Types *)
(** In Coq's programming language, almost nothing is built
in -- not even booleans or numbers! Instead, it provides powerful
tools for defining new types of data and functions that process
and transform them. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** Let's start with a very simple example. The following
declaration tells Coq that we are defining a new set of data
values -- a "type." The type is called [day], and its members are
[monday], [tuesday], etc. The lines of the definition can be read
"[monday] is a [day], [tuesday] is a [day], etc." *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval simpl] to evaluate a
compound expression involving [next_weekday]. Uncomment the
following and see what they do. *)
Eval simpl in (next_weekday friday).
Eval simpl in (next_weekday (next_weekday saturday)).
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [simpl] ("simplify") tells Coq precisely how to
evaluate the expression we give it. For the moment, [simpl] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality are the same after simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We won't have space to dig further into this topic,
but more information can be found in the Coq'Art book by Bertot
and Castéran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. simpl. reflexivity. Qed.
Example test_orb3: (orb false true ) = true.
Proof. simpl. reflexivity. Qed.
Example test_orb4: (orb true true ) = true.
Proof. simpl. reflexivity. Qed.
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The following bit of Coq hackery defines a magic value
called [admit] that can fill a hole in an incomplete definition or
proof. We'll use it in the definition of [nandb] in the following
exercise. In general, your job in the exercises is to replace
[admit] or [Admitted] with real definitions or proofs. *)
Definition admit {T: Type} : T. Admitted.
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below each can be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool := negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. simpl. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool := (andb b1 (andb b2 b3)).
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called function types, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly fancy module system,
to aid in organizing large developments. In this course, we won't
need most of its features, but one of them is useful: if we
enclose a collection of declarations between [Module X] and [End
X] markers, then, in the remainder of the file after the [End],
all these definitions will be referred to by names like [X.foo]
instead of just [foo]. This means that the new definition will
not clash with the unqualified name [foo] later, which would
otherwise be an error (a name can only be defined once in a given
scope). Here, we use this feature to introduce the definition of
the type [nat] in an inner module so that it does not shadow the
one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([weekday], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat]. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, predecessor: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval simpl in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to
yield a number. However, there is a fundamental difference:
functions like [pred] and [minustwo] come with _computation rules_
-- e.g., the definition of [pred] says that [pred n] can be
simplified to [match n with | O => O | S m' => m' end] -- while
the definition of [S] has no such behavior attached. Although it
is a function in the sense that it can be applied to an argument,
it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** When Coq checks this definition, it notes that [evenb] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ (or _primitive recursion_)
over the argument [n] -- i.e., that we make recursive calls only
on strictly smaller values of [n]. This implies that all calls to
[evenb] will eventually terminate. Coq demands that some argument
of _every_ [Fixpoint] definition is decreasing. *)
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be easier to work with later: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. simpl. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. simpl. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. *)
(* Once again, a module to avoid polluting the namespace. *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval simpl in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match] *)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. The _ avoids the need to make up a bogus
name in this case. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. simpl. reflexivity. Qed.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => S O
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. simpl. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. simpl. reflexivity. Qed.
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y) (at level 50, left associativity) : nat_scope.
Notation "x - y" := (minus x y) (at level 50, left associativity) : nat_scope.
Notation "x * y" := (mult x y) (at level 40, left associativity) : nat_scope.
Check ((0 + 1) + 1).
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y].
Each notation-symbol in Coq is active in a _notation scope_. Coq
tries to guess what scope you mean, so when you write [S(O*O)] it
guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. simpl. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. simpl. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. simpl. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool := (andb (negb (beq_nat n m)) (ble_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. simpl. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. simpl. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. simpl. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof By Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use the
function's definition to simplify the expressions on both sides of
the [=] and notice that they become identical.
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, since the definition of [+] is recursive in its first
argument. *)
Theorem plus_O_n : forall n:nat, 0 + n = n.
Proof.
simpl. reflexivity. Qed.
(** The [reflexivity] command implicitly simplifies both sides of the
equality before testing to see if they are the same, so we can
shorten the proof a little. *)
(** (It will be useful later to know that [reflexivity] actually
does somwhat more than [simpl] -- for example, it tries
"unfolding" defined terms, replacing them with their right-hand
sides. The reason for this difference is that, when reflexivity
succeeds, the whole goal is finished and we don't need to look at
whatever expanded expressions [reflexivity] has found; by
contrast, [simpl] is used in situations where we may have to read
and understand the new goal, so we would not want it blindly
expanding definitions.) *)
Theorem plus_O_n' : forall n:nat, 0 + n = n.
Proof.
reflexivity. Qed.
(** The form of this theorem and proof are almost exactly the
same as the examples above: the only differences are that we've
added the quantifier [forall n:nat] and that we've used the
keyword [Theorem] instead of [Example]. Indeed, the latter
difference is purely a matter of style; the keywords [Example] and
[Theorem] (and a few others, including [Lemma], [Fact], and
[Remark]) mean exactly the same thing to Coq.
The keywords [simpl] and [reflexivity] are examples of _tactics_.
A tactic is a command that is used between [Proof] and [Qed] to
tell Coq how it should check the correctness of some claim we are
making. We will see several more tactics in the rest of this
lecture, and yet more in future lectures. *)
(** **** Exercise: 1 star, optional (simpl_plus) *)
(** What will Coq print in response to this query? *)
(* Eval simpl in (forall n:nat, n + 0 = n). *)
(** What about this one? *)
(* Eval simpl in (forall n:nat, 0 + n = n). *)
(** Explain the difference. [] *)
(* ###################################################################### *)
(** * The [intros] Tactic *)
(** Aside from unit tests, which apply functions to particular
arguments, most of the properties we will be interested in proving
about programs will begin with some quantifiers (e.g., "for all
numbers [n], ...") and/or hypothesis ("assuming [m=n], ..."). In
such situations, we will need to be able to reason by _assuming
the hypothesis_ -- i.e., we start by saying "OK, suppose [n] is
some arbitrary number," or "OK, suppose [m=n]."
The [intros] tactic permits us to do this by moving one or more
quantifiers or hypotheses from the goal to a "context" of current
assumptions.
For example, here is a slightly different proof of the same theorem. *)
Theorem plus_O_n'' : forall n:nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** Step through this proof in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the name [H].
The third tells Coq to rewrite the current goal ([n + n = m + m])
by replacing the left side of the equality hypothesis [H] with the
right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o.
intros H1.
rewrite -> H1.
intros H2.
rewrite -> H2.
reflexivity.
Qed.
(** [] *)
(** The [Admitted] command tells Coq that we want to give up
trying to prove this theorem and just accept it as a given. This
can be useful for developing longer proofs, since we can state
subsidiary facts that we believe will be useful for making some
larger argument, use [Admitted] to accept them on faith for the
moment, and continue thinking about the larger argument until we
are sure it makes sense; then we can go back and fill in the
proofs we skipped. Be careful, though: every time you say [admit]
or [Admitted] you are leaving a door open for total nonsense to
enter Coq's nice, rigorous, formally checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars, recommended (mult_1_plus) *)
Theorem mult_1_plus : forall n m : nat,
(1 + n) * m = m + (n * m).
Proof.
intros n m.
simpl.
reflexivity.
Qed.
Theorem mult_1_plus' : forall n m : nat,
(1 + n) * m = m + (n * m).
Proof.
intros n m.
rewrite -> plus_1_l.
simpl.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can show up in the "head position"
of functions that we want to reason about, blocking
simplification. For example, if we try to prove the following
fact using the [simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. simpl. (* does nothing! *)
Admitted.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an "intro pattern." It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written "[as [|]]", or "[as []]".) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n. destruct n.
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Naming Cases *)
(** The fact that there is no explicit command for moving from
one branch of a case analysis to the next can make proof scripts
rather hard to read. In larger proofs, with nested case analyses,
it can even become hard to stay oriented when you're sitting with
Coq and stepping through the proof. (Imagine trying to remember
that the first five subgoals belong to the inner case analysis and
the remaining seven cases are what remains of the outer one...)
Disciplined use of indentation and comments can help, but a better
way is to use the [Case] tactic.
[Case] is not built into Coq: we need to define it ourselves.
There is no need to understand how it works -- just skip over the
definition to the example that follows. It uses some facilities
of Coq that we have not discussed -- the string library (just for
the concrete syntax of quoted strings) and the [Ltac] command,
which allows us to declare custom tactics. Kudos to Aaron
Bohannon for this nice hack! *)
Require String. Open Scope string_scope.
Ltac move_to_top x :=
match reverse goal with
| H : _ |- _ => try move x after H
end.
Tactic Notation "assert_eq" ident(x) constr(v) :=
let H := fresh in
assert (x = v) as H by reflexivity;
clear H.
Tactic Notation "Case_aux" ident(x) constr(name) :=
first [
set (x := name); move_to_top x
| assert_eq x name; move_to_top x
| fail 1 "because we are working on a different case" ].
Tactic Notation "Case" constr(name) := Case_aux Case name.
Tactic Notation "SCase" constr(name) := Case_aux SCase name.
Tactic Notation "SSCase" constr(name) := Case_aux SSCase name.
Tactic Notation "SSSCase" constr(name) := Case_aux SSSCase name.
Tactic Notation "SSSSCase" constr(name) := Case_aux SSSSCase name.
Tactic Notation "SSSSSCase" constr(name) := Case_aux SSSSSCase name.
Tactic Notation "SSSSSSCase" constr(name) := Case_aux SSSSSSCase name.
Tactic Notation "SSSSSSSCase" constr(name) := Case_aux SSSSSSSCase name.
(** Here's an example of how [Case] is used. Step through the
following proof and observe how the context changes. *)
Theorem andb_true_elim1 : forall b c : bool,
andb b c = true -> b = true.
Proof.
intros b c H.
destruct b.
Case "b = true".
reflexivity.
Case "b = false".
rewrite <- H. reflexivity. Qed.
(** [Case] does something very trivial: It simply adds a string
that we choose (tagged with the identifier "Case") to the context
for the current goal. When subgoals are generated, this string is
carried over into their contexts. When the last of these subgoals
is finally proved and the next top-level goal (a sibling of the
current one) becomes active, this string will no longer appear in
the context and we will be able to see that the case where we
introduced it is complete. Also, as a sanity check, if we try to
execute a new [Case] tactic while the string left by the previous
one is still in the context, we get a nice clear error message.
For nested case analyses (i.e., when we want to use a [destruct]
to solve a goal that has itself been generated by a [destruct]),
there is an [SCase] ("subcase") tactic. *)
(** **** Exercise: 2 stars (andb_true_elim2) *)
(** Prove [andb_true_elim2], marking cases (and subcases) when
you use [destruct]. *)
Theorem andb_true_elim2 : forall b c : bool,
andb b c = true -> c = true.
Proof.
intros b c H.
destruct b.
Case "b = true".
destruct c.
SCase "c = true".
reflexivity.
SCase "c = false".
rewrite <- H. reflexivity.
Case "b = false".
destruct c.
reflexivity.
rewrite <- H.
reflexivity.
Qed.
(** [] *)
(** There are no hard and fast rules for how proofs should be
formatted in Coq -- in particular, where lines should be broken
and how sections of the proof should be indented to indicate their
nested structure. However, if the places where multiple subgoals
are generated are marked with explicit [Case] tactics placed at
the beginning of lines, then the proof will be readable almost no
matter what choices are made about other aspects of layout.
This is a good place to mention one other piece of (possibly
obvious) advice about line lengths. Beginning Coq users sometimes
tend to the extremes, either writing each tactic on its own line
or entire proofs on one line. Good style lies somewhere in the
middle. In particular, one reasonable convention is to limit
yourself to 80-character lines. Lines longer than this are hard
to read and can be inconvenient to display and print. Many
editors have features that help enforce this. *)
(* ###################################################################### *)
(** * Induction *)
(** We proved above that [0] is a neutral element for [+] on
the left using a simple partial evaluation argument. The fact
that it is also a neutral element on the _right_... *)
Theorem plus_0_r_firsttry : forall n:nat,
n + 0 = n.
(** ... cannot be proved in the same simple way. Just applying
[reflexivity] doesn't work: the [n] in [n + 0] is an arbitrary
unknown number, so the [match] in the definition of [+] can't be
simplified. And reasoning by cases using [destruct n] doesn't get
us much further: the branch of the case analysis where we assume [n
= 0] goes through, but in the branch where [n = S n'] for some [n']
we get stuck in exactly the same way. We could use [destruct n'] to
get one step further, but since [n] can be arbitrarily large, if we
try to keep on going this way we'll never be done. *)
Proof.
intros n.
simpl. (* Does nothing! *)
Admitted.
(** Case analysis gets us a little further, but not all the way: *)
Theorem plus_0_r_secondtry : forall n:nat,
n + 0 = n.
Proof.
intros n. destruct n as [| n'].
Case "n = 0".
reflexivity. (* so far so good... *)
Case "n = S n'".
simpl. (* ...but here we are stuck again *)
Admitted.
(** To prove such facts -- indeed, to prove most interesting
facts about numbers, lists, and other inductively defined sets --
we need a more powerful reasoning principle: _induction_.
Recall (from high school) the principle of induction over natural
numbers: If [P(n)] is some proposition involving a natural number
[n] and we want to show that P holds for _all_ numbers [n], we can
reason like this:
- show that [P(O)] holds;
- show that, for any [n'], if [P(n')] holds, then so does
[P(S n')];
- conclude that [P(n)] holds for all [n].
In Coq, the steps are the same but the order is backwards: we
begin with the goal of proving [P(n)] for all [n] and break it
down (by applying the [induction] tactic) into two separate
subgoals: first showing [P(O)] and then showing [P(n') -> P(S
n')]. Here's how this works for the theorem we are trying to
prove at the moment: *)
Theorem plus_0_r : forall n:nat, n + 0 = n.
Proof.
intros n. induction n as [| n'].
Case "n = 0". reflexivity.
Case "n = S n'". simpl. rewrite -> IHn'. reflexivity. Qed.
(** Like [destruct], the [induction] tactic takes an [as...]
clause that specifies the names of the variables to be introduced
in the subgoals. In the first branch, [n] is replaced by [0] and
the goal becomes [0 + 0 = 0], which follows by simplification. In
the second, [n] is replaced by [S n'] and the assumption [n' + 0 =
n'] is added to the context (with the name [IHn'], i.e., the
Induction Hypothesis for [n']). The goal in this case becomes [(S
n') + 0 = S n'], which simplifies to [S (n' + 0) = S n'], which in
turn follows from the induction hypothesis. *)
Theorem minus_diag : forall n,
minus n n = 0.
Proof.
(* WORKED IN CLASS *)
intros n. induction n as [| n'].
Case "n = 0".
simpl. reflexivity.
Case "n = S n'".
simpl. rewrite -> IHn'. reflexivity. Qed.
(** **** Exercise: 2 stars, recommended (basic_induction) *)
Theorem mult_0_r : forall n:nat,
n * 0 = 0.
Proof.
intros n. induction n as [| n'].
Case "n = 0".
simpl. reflexivity.
Case "n = S n'".
simpl. rewrite -> IHn'. reflexivity. Qed.
Theorem plus_n_Sm : forall n m : nat,
S (n + m) = n + (S m).
Proof.
intros n m. induction n as [| n'].
Case "n = 0".
simpl. reflexivity.
Case "n = S n'".
simpl.
rewrite <- IHn'. reflexivity. Qed.
Theorem plus_comm : forall n m : nat,
n + m = m + n.
Proof.
intros n m. induction n as [| n'].
Case "n = 0".
simpl.
rewrite plus_0_r. reflexivity.
Case "n = S n'".
simpl.
rewrite -> IHn'. rewrite plus_n_Sm. reflexivity. Qed.
(** [] *)
Fixpoint double (n:nat) :=
match n with
| O => O
| S n' => S (S (double n'))
end.
(** **** Exercise: 2 stars (double_plus) *)
Lemma double_plus : forall n, double n = n + n .
Proof.
intros n. induction n as [| n'].
Case "n = 0". simpl. reflexivity.
Case "n = S n'".
simpl.
rewrite -> IHn'. rewrite plus_n_Sm. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (destruct_induction) *)
(** Briefly explain the difference between the tactics
[destruct] and [induction].
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################################### *)
(** * Formal vs. Informal Proof *)
(** "Informal proofs are algorithms; formal proofs are code." *)
(** The question of what, exactly, constitutes a "proof" of a
mathematical claim has challenged philosophers for millenia. A
rough and ready definition, though, could be this: a proof of a
mathematical proposition [P] is a written (or spoken) text that
instills in the reader or hearer the certainty that [P] is true.
That is, a proof is an act of communication.
Now, acts of communication may involve different sorts of readers.
On one hand, the "reader" can be a program like Coq, in which case
the "belief" that is instilled is a simple mechanical check that
[P] can be derived from a certain set of formal logical rules, and
the proof is a recipe that guides the program in performing this
check. Such recipes are _formal_ proofs.
Alternatively, the reader can be a human being, in which case the
proof will be written in English or some other natural language,
thus necessarily _informal_. Here, the criteria for success are
less clearly specified. A "good" proof is one that makes the
reader believe [P]. But the same proof may be read by many
different readers, some of whom may be convinced by a particular
way of phrasing the argument, while others may not be. One reader
may be particularly pedantic, inexperienced, or just plain
thick-headed; the only way to convince them will be to make the
argument in painstaking detail. But another reader, more familiar
in the area, may find all this detail so overwhelming that they
lose the overall thread. All they want is to be told the main
ideas, because it is easier to fill in the details for themselves.
Ultimately, there is no universal standard, because there is no
single way of writing an informal proof that is guaranteed to
convince every conceivable reader. In practice, however,
mathematicians have developed a rich set of conventions and idioms
for writing about complex mathematical objects that, within a
certain community, make communication fairly reliable. The
conventions of this stylized form of communication give a fairly
clear standard for judging proofs good or bad.
Because we are using Coq in this course, we will be working
heavily with formal proofs. But this doesn't mean we can ignore
the informal ones! Formal proofs are useful in many ways, but
they are _not_ very efficient ways of communicating ideas between
human beings. *)
(** For example, here is a proof that addition is associative: *)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof. intros n m p. induction n as [| n']. reflexivity.
simpl. rewrite -> IHn'. reflexivity. Qed.
(** Coq is perfectly happy with this as a proof. For a human,
however, it is difficult to make much sense of it. If you're used
to Coq you can probably step through the tactics one after the
other in your mind and imagine the state of the context and goal
stack at each point, but if the proof were even a little bit more
complicated this would be next to impossible. Instead, a
mathematician mighty write it like this: *)
(** - _Theorem_: For any [n], [m] and [p],
[[
n + (m + p) = (n + m) + p.
]]
_Proof_: By induction on [n].
- First, suppose [n = 0]. We must show
[[
0 + (m + p) = (0 + m) + p.
]]
This follows directly from the definition of [+].
- Next, suppose [n = S n'], where
[[
n' + (m + p) = (n' + m) + p.
]]
We must show
[[
(S n') + (m + p) = ((S n') + m) + p.
]]
By the definition of [+], this follows from
[[
S (n' + (m + p)) = S ((n' + m) + p),
]]
which is immediate from the induction hypothesis. [] *)
(** The overall form of the proof is basically similar. This is
no accident, of course: Coq has been designed so that its
[induction] tactic generates the same sub-goals, in the same
order, as the bullet points that a mathematician would write. But
there are significant differences of detail: the formal proof is
much more explicit in some ways (e.g., the use of [reflexivity])
but much less explicit in others; in particular, the "proof state"
at any given point in the Coq proof is completely implicit,
whereas the informal proof reminds the reader several times where
things stand. *)
(** Here is a formal proof that shows the structure more
clearly: *)
Theorem plus_assoc : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
intros n m p. induction n as [| n'].
Case "n = 0".
reflexivity.
Case "n = S n'".
simpl. rewrite -> IHn'. reflexivity. Qed.
(** **** Exercise: 2 stars (plus_comm_informal) *)
(** Translate your solution for [plus_comm] into an informal proof. *)
(** Theorem: Addition is commutative.
Proof: (* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars, optional (beq_nat_refl_informal) *)
(** Write an informal proof of the following theorem, using the
informal proof of [plus_assoc] as a model. Don't just
paraphrase the Coq tactics into English!
Theorem: [true = beq_nat n n] for any [n].
Proof: (* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional (beq_nat_refl) *)
Theorem beq_nat_refl : forall n : nat,
true = beq_nat n n.
Proof.
intros n. induction n as [| n'].
Case "n = 0".
simpl.
reflexivity.
Case "n = S n'".
simpl.
rewrite -> IHn'. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proofs Within Proofs *)
(** In Coq, as in informal mathematics, large proofs are very
often broken into a sequence of theorems, with later proofs
referring to earlier theorems. Occasionally, however, a proof
will need some miscellaneous fact that is too trivial (and of too
little general interest) to bother giving it its own top-level
name. In such cases, it is convenient to be able to simply state
and prove the needed "sub-theorem" right at the point where it is
used. The [assert] tactic allows us to do this. For example, our
earlier proof of the [mult_0_plus] theorem referred to a previous
theorem named [plus_O_n]. We can also use [assert] to state and
prove [plus_O_n] in-line: *)
Theorem mult_0_plus' : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
assert (H: 0 + n = n).
Case "Proof of assertion". reflexivity.
rewrite -> H.
reflexivity. Qed.
(** The [assert] tactic introduces two sub-goals. The first is
the assertion itself; by prefixing it with [H:] we name the
assertion [H]. (Note that we could also name the assertion with
[as] just as we did above with [destruct] and [induction], i.e.,
[assert (0 + n = n) as H]. Also note that we mark the proof of
this assertion with a [Case], both for readability and so that,
when using Coq interactively, we can see when we're finished
proving the assertion by observing when the ["Proof of assertion"]
string disappears from the context.) The second goal is the same
as the one at the point where we invoke [assert], except that, in
the context, we have the assumption [H] that [0 + n = n]. That
is, [assert] generates one subgoal where we must prove the
asserted fact and a second subgoal where we can use the asserted
fact to make progress on whatever we were trying to prove in the
first place. *)
(** Actually, [assert] will turn out to be handy in many sorts of
situations. For example, suppose we want to prove that [(n + m)
+ (p + q) = (m + n) + (p + q)]. The only difference between the
two sides of the [=] is that the arguments [m] and [n] to the
first inner [+] are swapped, so it seems we should be able to
use the commutativity of addition ([plus_comm]) to rewrite one
into the other. However, the [rewrite] tactic is a little stupid
about _where_ it applies the rewrite. There are three uses of
[+] here, and it turns out that doing [rewrite -> plus_comm]
will affect only the _outer_ one. *)
Theorem plus_rearrange_firsttry : forall n m p q : nat,
(n + m) + (p + q) = (m + n) + (p + q).
Proof.
intros n m p q.
(* We just need to swap (n + m) for (m + n)...
it seems like plus_comm should do the trick! *)
rewrite -> plus_comm.
(* Doesn't work...Coq rewrote the wrong plus! *)
Admitted.
(** To get [plus_comm] to apply at the point where we want it, we can
introduce a local lemma stating that [n + m = m + n] (for
the particular [m] and [n] that we are talking about here), prove
this lemma using [plus_comm], and then use this lemma to do the
desired rewrite. *)
Theorem plus_rearrange : forall n m p q : nat,
(n + m) + (p + q) = (m + n) + (p + q).
Proof.
intros n m p q.
assert (H: n + m = m + n).
Case "Proof of assertion".
rewrite -> plus_comm. reflexivity.
rewrite -> H. reflexivity. Qed.
(** **** Exercise: 4 stars (mult_comm) *)
(** Use [assert] to help prove this theorem. You shouldn't need to
use induction. *)
Theorem mult_1_l : forall n : nat, n = 1 * n.
induction n as [| n'].
Case "n = 0".
rewrite mult_0_r.
reflexivity.
Case "n = S n'".
rewrite IHn'.
simpl.
rewrite plus_0_r.
rewrite plus_0_r.
reflexivity.
Qed.
Theorem mult_1n_n1 : forall n : nat, 1 * n = n * 1.
intros n.
induction n as [| n'].
Case "n = 0".
rewrite mult_0_l.
rewrite mult_0_r.
reflexivity.
Case "n = S n'".
simpl.
rewrite <- IHn'.
rewrite plus_0_r.
rewrite <- mult_1_l.
reflexivity.
Qed.
Theorem mult_1_r : forall n : nat, n = n * 1.
intros n. induction n as [| n'].
reflexivity.
rewrite <- mult_1n_n1.
rewrite <- mult_1_l.
reflexivity.
Qed.
(**
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
*)
Theorem plus_swap : forall n m p : nat,
n + (m + p) = m + (n + p).
Proof.
intros n m p.
assert (H: n + p = p + n).
Case "Proof of assertion".
rewrite -> plus_comm. reflexivity.
rewrite -> H.
rewrite -> plus_comm.
rewrite <- plus_assoc.
reflexivity.
Qed.
(** Now prove commutativity of multiplication. (You will probably
need to define and prove a separate subsidiary theorem to be used
in the proof of this one.) You may find that [plus_swap] comes in
handy.
*)
Theorem mult_comm_helper : forall m n : nat, m + (m * n) = m * S n.
intros n m.
induction n as [| n'].
Case "m = 0".
simpl.
reflexivity.
Case "m = S m'".
simpl.
rewrite <- IHn'.
rewrite plus_swap.
reflexivity.
Qed.
Theorem mult_comm : forall m n : nat, m * n = n * m.
Proof.
intros n m. induction n as [| n'].
Case "n = 0".
simpl.
rewrite mult_0_r.
reflexivity.
Case "n = S n'".
simpl.
rewrite -> IHn'.
rewrite <- mult_comm_helper.
reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (evenb_n__oddb_Sn)
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
*)
Theorem evenb_n__oddb_Sn : forall n : nat,
evenb n = negb (evenb (S n)).
Proof.
intros n.
induction n as [| n'].
Case "0".
simpl. reflexivity.
Case "n = S n'".
simpl.
rewrite IHn'.
simpl.
rewrite negb_involutive.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 3 stars, optional (more_exercises) *)
(** Take a piece of paper. For each of the following theorems, first
_think_ about whether (a) it can be proved using only
simplification and rewriting, (b) it also requires case
analysis ([destruct]), or (c) it also requires induction. Write
down your prediction. Then fill in the proof. (There is no need
to turn in your piece of paper; this is just to encourage you to
reflect before hacking!) *)
Theorem ble_nat_refl : forall n:nat,
true = ble_nat n n.
Proof.
intros n. induction n as [| n'].
reflexivity.
simpl. rewrite IHn'. reflexivity.
Qed.
Theorem zero_nbeq_S : forall n:nat,
beq_nat 0 (S n) = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
simpl. reflexivity.
Qed.
Theorem andb_false_r : forall b : bool,
andb b false = false.
Proof.
intros b. destruct b.
reflexivity. reflexivity.
Qed.
Theorem plus_ble_compat_l : forall n m p : nat,
ble_nat n m = true -> ble_nat (p + n) (p + m) = true.
Proof.
intros n m p.
intros H.
induction p as [| p'].
Case "p = 0".
rewrite plus_O_n. rewrite plus_O_n.
rewrite <- H.
reflexivity.
Case "p = S p'".
simpl. rewrite <- IHp'. reflexivity.
Qed.
Theorem S_nbeq_0 : forall n:nat,
beq_nat (S n) 0 = false.
Proof.
intros n. destruct n as [|n'].
reflexivity.
reflexivity. Qed.
Theorem mult_1_l_again : forall n:nat, 1 * n = n.
Proof.
intros n.
rewrite mult_comm. rewrite mult_1_r. reflexivity. Qed.
Theorem all3_spec : forall b c : bool,
orb
(andb b c)
(orb (negb b)
(negb c))
= true.
Proof.
intros b c.
destruct b.
destruct c.
simpl. reflexivity. simpl. reflexivity. simpl. reflexivity. Qed.
Theorem mult_plus_distr_r : forall n m p : nat,
(n + m) * p = (n * p) + (m * p).
Proof.
intros n m p.
induction n as [|n'].
Case "n = 0".
simpl.
reflexivity.
Case "n = S n'".
simpl.
rewrite IHn'.
rewrite plus_assoc.
reflexivity.
Qed.
Theorem mult_assoc : forall n m p : nat,
n * (m * p) = (n * m) * p.
Proof.
intros n m p.
induction n as [|n'].
Case "n = 0".
simpl.
reflexivity.
Case "n = S n'".
simpl.
rewrite IHn'.
rewrite mult_plus_distr_r.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (plus_swap') *)
(** The [replace] tactic allows you to specify a particular subterm to
rewrite and what you want it rewritten to. More precisely,
[replace (t) with (u)] replaces (all copies of) expression [t] in
the goal by expression [u], and generates [t = u] as an additional
subgoal. This is often useful when a plain [rewrite] acts on the wrong
part of the goal.
Use the [replace] tactic to do a proof of [plus_swap'], just like
[plus_swap] but without needing [assert (n + m = m + n)].
*)
Theorem plus_swap' : forall n m p : nat,
n + (m + p) = m + (n + p).
Proof.
intros n m p.
replace (n + p) with (p + n).
rewrite <- plus_comm.
rewrite <- plus_assoc.
reflexivity.
rewrite plus_comm.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, recommended (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: recall that the definition of [nat] from class,
[[
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
]]
says nothing about what [O] and [S] "mean". It just says "[O] is
a nat (whatever that is), and if [n] is a nat then so is [S n]".
The interpretation of [O] as zero and [S] as successor/plus one
comes from the way that we use nat values, by writing functions to
do things with them, proving things about them, and so on. Your
definition of [bin] should be correspondingly simple; it is the
functions you will write next that will give it mathematical
meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Finally, prove that your increment and binary-to-unary
functions commute: that is, incrementing a binary number and
then converting it to unary yields the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| B0 : bin
| B2 : bin -> bin
| B21 : bin -> bin.
Fixpoint inc (b:bin) : bin :=
match b with
| B0 => B21 B0
| B2 b' => B21 b'
| B21 b' => B2 (inc b')
end.
SearchAbout plus.
Fixpoint bintonat (b:bin) : nat :=
match b with
| B0 => 0
| B2 b' => 2 * bintonat b'
| B21 b' => 1 + 2 * bintonat b'
end.
Theorem bin_inc_inc_bin : forall b : bin,
bintonat (inc b) = S (bintonat b).
Proof.
intros b.
induction b as [|b'|b'].
Case "Mt".
simpl. reflexivity.
Case "B20 b'".
simpl.
rewrite plus_0_r.
reflexivity.
Case "B21 b'".
simpl.
rewrite IHb'.
simpl.
rewrite <- plus_n_Sm.
reflexivity.
Qed.
(** **** Exercise: 5 stars (binary_inverse) *)
(** This exercise is a continuation of the previous exercise about
binary numbers. You will need your definitions and theorems from
the previous exercise to complete this one.
(a) First, write a function to convert natural numbers to binary
numbers. Then prove that starting with any natural number,
converting to binary, then converting back yields the same
natural number you started with.
(b) You might naturally think that we should also prove the
opposite direction: that starting with a binary number,
converting to a natural, and then back to binary yields the
same number we started with. However, it is not true!
Explain what the problem is.
(c) Define a function [normalize] from binary numbers to binary
numbers such that for any binary number b, converting to a
natural and then back to binary yields [(normalize b)]. Prove
it.
*)
Fixpoint nattobin (n:nat) : bin :=
match n with
| O => B0
| S n' => inc (nattobin n')
end.
Theorem nat_to_bin_to_nat : forall n : nat, bintonat (nattobin n) = n.
Proof.
intros n.
induction n as [|n'].
Case "0".
reflexivity.
Case "S n'".
simpl.
rewrite bin_inc_inc_bin.
rewrite IHn'.
reflexivity.
Qed.
Fixpoint normalize (b:bin) : bin := nattobin (bintonat b).
(* match b with
| B0 => B0
| B2 b' => B0
| B21 b' => B0
end.
*)
Theorem bin_to_nat_to_bin: forall b : bin, nattobin (bintonat b) = normalize (b).
Proof.
intros b.
(** **** Exercise: 2 stars, optional (decreasing) *)
(** The requirement that some argument to each function be
"decreasing" is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways.
To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_nfa_forward_buckets_if/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_ARUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 32,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
// write request
wire write_ready;
wire write_valid;
wire [31:0] write_address;
wire [31:0] write_length;
wire [C_USER_DATA_WIDTH-1:0] write_data;
// read request
wire read_ready;
wire read_valid;
wire [31:0] read_address;
wire [31:0] read_length;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_nfa_forward_buckets_request_preprocessor
nfa_accept_samples_generic_hw_nfa_forward_buckets_request_preprocessor #(
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) request_preprocessor (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.USER_dataout ( USER_dataout ),
.USER_address ( USER_address ),
.USER_size ( USER_size ),
.USER_req_din ( USER_req_din ),
.USER_req_full_n ( USER_req_full_n ),
.USER_req_write ( USER_req_write ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length )
);
// nfa_accept_samples_generic_hw_nfa_forward_buckets_write
nfa_accept_samples_generic_hw_nfa_forward_buckets_write #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_AWUSER_WIDTH ( C_AWUSER_WIDTH ),
.C_WUSER_WIDTH ( C_WUSER_WIDTH ),
.C_BUSER_WIDTH ( C_BUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_write (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.AWID ( AWID ),
.AWADDR ( AWADDR ),
.AWLEN ( AWLEN ),
.AWSIZE ( AWSIZE ),
.AWBURST ( AWBURST ),
.AWLOCK ( AWLOCK ),
.AWCACHE ( AWCACHE ),
.AWPROT ( AWPROT ),
.AWQOS ( AWQOS ),
.AWUSER ( AWUSER ),
.AWVALID ( AWVALID ),
.AWREADY ( AWREADY ),
.WDATA ( WDATA ),
.WSTRB ( WSTRB ),
.WLAST ( WLAST ),
.WUSER ( WUSER ),
.WVALID ( WVALID ),
.WREADY ( WREADY ),
.BID ( BID ),
.BRESP ( BRESP ),
.BUSER ( BUSER ),
.BVALID ( BVALID ),
.BREADY ( BREADY ),
.write_ready ( write_ready ),
.write_valid ( write_valid ),
.write_address ( write_address ),
.write_length ( write_length ),
.write_data ( write_data )
);
// nfa_accept_samples_generic_hw_nfa_forward_buckets_read
nfa_accept_samples_generic_hw_nfa_forward_buckets_read #(
.C_ID_WIDTH ( C_ID_WIDTH ),
.C_ADDR_WIDTH ( C_ADDR_WIDTH ),
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_ARUSER_WIDTH ( C_ARUSER_WIDTH ),
.C_RUSER_WIDTH ( C_RUSER_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH ),
.C_TARGET_ADDR ( C_TARGET_ADDR ),
.C_USER_VALUE ( C_USER_VALUE ),
.C_PROT_VALUE ( C_PROT_VALUE ),
.C_CACHE_VALUE ( C_CACHE_VALUE )
) bus_read (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.ARID ( ARID ),
.ARADDR ( ARADDR ),
.ARLEN ( ARLEN ),
.ARSIZE ( ARSIZE ),
.ARBURST ( ARBURST ),
.ARLOCK ( ARLOCK ),
.ARCACHE ( ARCACHE ),
.ARPROT ( ARPROT ),
.ARQOS ( ARQOS ),
.ARUSER ( ARUSER ),
.ARVALID ( ARVALID ),
.ARREADY ( ARREADY ),
.RID ( RID ),
.RDATA ( RDATA ),
.RRESP ( RRESP ),
.RLAST ( RLAST ),
.RUSER ( RUSER ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.read_ready ( read_ready ),
.read_valid ( read_valid ),
.read_address ( read_address ),
.read_length ( read_length ),
.USER_datain ( USER_datain ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.USER_rsp_read ( USER_rsp_read )
);
//------------------------Body---------------------------
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_nfa_forward_buckets_request_preprocessor/*{{{*/
#(parameter
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// user ports
input wire [C_USER_DATA_WIDTH-1:0] USER_dataout,
input wire [31:0] USER_address,
input wire [31:0] USER_size,
input wire USER_req_din,
output wire USER_req_full_n,
input wire USER_req_write,
// write request
input wire write_ready,
output wire write_valid,
output wire [31:0] write_address,
output wire [31:0] write_length,
output wire [C_USER_DATA_WIDTH-1:0] write_data,
// read request
input wire read_ready,
output wire read_valid,
output wire [31:0] read_address,
output wire [31:0] read_length
);
//------------------------Parameter----------------------
localparam
REQUEST_WIDTH = 1 + 32 + 32 + C_USER_DATA_WIDTH,
MAX_REQUEST = 32;
//------------------------Local signal-------------------
// request fifo
wire req_empty_n;
wire req_full_n;
wire req_rdreq;
wire req_wrreq;
wire [REQUEST_WIDTH-1:0] req_data;
wire [REQUEST_WIDTH-1:0] req_q;
wire [31:0] tmp_size;
wire tmp_type; // 0 - read, 1 - write
wire [31:0] tmp_address; // start address of read/write request
wire [31:0] tmp_length; // length of read/write request
wire [C_USER_DATA_WIDTH-1:0] tmp_data; // data of write request
//------------------------Task and function--------------
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_nfa_forward_buckets_fifo
nfa_accept_samples_generic_hw_nfa_forward_buckets_fifo #(
.DATA_BITS ( REQUEST_WIDTH ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) req_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( req_empty_n ),
.full_n ( req_full_n ),
.rdreq ( req_rdreq ),
.wrreq ( req_wrreq ),
.q ( req_q ),
.data ( req_data )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++user ports+++++++++++++++++++++
assign USER_req_full_n = req_full_n;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
assign write_valid = req_empty_n & tmp_type;
assign write_address = tmp_address;
assign write_length = tmp_length;
assign write_data = tmp_data;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_valid = req_empty_n & ~tmp_type;
assign read_address = tmp_address;
assign read_length = tmp_length;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++request fifo+++++++++++++++++++
assign req_rdreq = (read_valid & read_ready) | (write_valid & write_ready);
assign req_wrreq = USER_req_write;
assign req_data = {USER_req_din, USER_address, tmp_size, USER_dataout};
assign tmp_size = (USER_size==1'b0)? 1'b1 : USER_size;
assign tmp_type = req_q[REQUEST_WIDTH-1];
assign tmp_address = req_q[C_USER_DATA_WIDTH+63:C_USER_DATA_WIDTH+32];
assign tmp_length = req_q[C_USER_DATA_WIDTH+31:C_USER_DATA_WIDTH];
assign tmp_data = req_q[C_USER_DATA_WIDTH-1:0];
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_nfa_forward_buckets_write/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_AWUSER_WIDTH = 1,
C_WUSER_WIDTH = 1,
C_BUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// write address channel
output wire [C_ID_WIDTH-1:0] AWID,
output wire [C_ADDR_WIDTH-1:0] AWADDR,
output wire [7:0] AWLEN,
output wire [2:0] AWSIZE,
output wire [1:0] AWBURST,
output wire [1:0] AWLOCK,
output wire [3:0] AWCACHE,
output wire [2:0] AWPROT,
output wire [3:0] AWQOS,
output wire [C_AWUSER_WIDTH-1:0] AWUSER,
output wire AWVALID,
input wire AWREADY,
// write data channel
output wire [C_DATA_WIDTH-1:0] WDATA,
output wire [C_DATA_WIDTH/8-1:0] WSTRB,
output wire WLAST,
output wire [C_WUSER_WIDTH-1:0] WUSER,
output wire WVALID,
input wire WREADY,
// write response channel
input wire [C_ID_WIDTH-1:0] BID,
input wire [1:0] BRESP,
input wire [C_BUSER_WIDTH-1:0] BUSER,
input wire BVALID,
output wire BREADY,
// write request
output wire write_ready,
input wire write_valid,
input wire [31:0] write_address,
input wire [31:0] write_length,
input wire [C_USER_DATA_WIDTH-1:0] write_data
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_BYTES = USER_DATA_BYTES > BUS_DATA_BYTES?
USER_DATA_BYTES : BUS_DATA_BYTES,
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
DATA = 4'd3,
LOOP = 4'd4;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg enough_data;
reg [DATA_BUF_BYTES*8-1:0] data_buf;
reg [DATA_BUF_BYTES-1:0] data_valid;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
reg [BUS_ADDR_ALIGN-1:0] tmp_bytes;
reg [BUS_ADDR_ALIGN-1:0] head_bytes;
reg [BUS_ADDR_ALIGN-1:0] tail_bytes;
reg add_head;
reg add_tail;
reg first_beat;
reg last_beat;
// axi4 bus
wire [BUS_DATA_BYTES-1:0] wstrb0;
wire [BUS_DATA_BYTES-1:0] wstrb1;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (write_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (AWREADY)
next = DATA;
else
next = ADDR;
DATA:
if (WVALID && WREADY && loop_beats==1'b1)
next = LOOP;
else
next = DATA;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (write_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && AWREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
len_buf <= write_length - 1'b1;
else if (write_ready && write_valid)
len_buf <= len_buf - 1'b1;
end
// enough_data
always @(posedge ACLK) begin
if (state==IDLE && write_valid) begin
if (write_length == 1'b1)
enough_data <= 1'b1;
else
enough_data <= 1'b0;
end
else if (write_ready && write_valid && len_buf==1'b1)
enough_data <= 1'b1;
end
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : wide_to_narrow
assign wstrb0 = {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= write_data;
else if (WREADY & WVALID)
data_buf <= data_buf >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (write_ready & write_valid)
data_valid <= {DATA_BUF_BYTES{1'b1}};
else if (WREADY & WVALID)
data_valid <= data_valid >> BUS_DATA_BYTES;
end
// tmp_bytes, head_bytes, tail_bytes, add_head, add_tail
// first_beat, last_beat
always @(*) begin
// these signals are useless if user data width is
// greater than bus data width
tmp_bytes = 1'b0;
head_bytes = 1'b0;
tail_bytes = 1'b0;
add_head = 1'b0;
add_tail = 1'b0;
first_beat = 1'b0;
last_beat = 1'b0;
end
end
else begin : narrow_to_wide
assign wstrb0 = first_beat? {BUS_DATA_BYTES{1'b1}} << head_bytes : {BUS_DATA_BYTES{1'b1}};
assign wstrb1 = last_beat? {BUS_DATA_BYTES{1'b1}} >> tail_bytes : {BUS_DATA_BYTES{1'b1}};
// data_buf
always @(posedge ACLK) begin
if (write_ready & write_valid)
data_buf <= {write_data, data_buf} >> USER_DATA_WIDTH;
else if (state==DATA && add_tail)
data_buf <= data_buf >> (tail_bytes * 8);
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (WREADY & WVALID)
data_valid <= {USER_DATA_BYTES{write_ready & write_valid}} << (DATA_BUF_BYTES-USER_DATA_BYTES);
else if (write_ready & write_valid)
data_valid <= {{USER_DATA_BYTES{1'b1}}, data_valid} >> USER_DATA_BYTES;
else if (add_head)
data_valid <= (data_valid >> head_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> head_bytes);
else if (state==DATA && add_tail)
data_valid <= (data_valid >> tail_bytes) | ~({DATA_BUF_BYTES{1'b1}} >> tail_bytes);
end
// tmp_bytes
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
tmp_bytes <= write_length[BUS_ADDR_ALIGN-1:0] << USER_ADDR_ALIGN;
end
// head_bytes
always @(posedge ACLK) begin
if (state==PREP)
head_bytes <= addr_buf[BUS_ADDR_ALIGN-1:0];
end
// tail_bytes
always @(posedge ACLK) begin
if (state==PREP)
tail_bytes <= BUS_DATA_BYTES - addr_buf[BUS_ADDR_ALIGN-1:0] - tmp_bytes;
end
// add_head
always @(posedge ACLK) begin
if (state==PREP)
add_head <= 1'b1;
else
add_head <= 1'b0;
end
// add_tail
always @(posedge ACLK) begin
if (write_ready && write_valid && (write_length== 1'b1 || len_buf==1'b1))
add_tail <= 1'b1;
else if (state==DATA)
add_tail <= 1'b0;
end
// first_beat
always @(posedge ACLK) begin
if (state==PREP)
first_beat <= 1'b1;
else if (WREADY & WVALID)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if ((state==PREP || state==LOOP) && total_beats==1'b1)
last_beat <= 1'b1;
else if (WREADY & WVALID) begin
if (total_beats==1'b0 && loop_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end
endgenerate
// total_beats
always @(posedge ACLK) begin
if (state==IDLE && write_valid)
total_beats <= ((write_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && AWREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
else if (WVALID & WREADY)
loop_beats <= loop_beats - 1'b1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++axi4 bus+++++++++++++++++++++++
// write address channel
assign AWID = 1'b0;
assign AWADDR = addr_buf;
assign AWLEN = loop_beats - 1'b1;
assign AWSIZE = BUS_ADDR_ALIGN[2:0];
assign AWBURST = 2'b01;
assign AWLOCK = 2'b00;
assign AWCACHE = C_CACHE_VALUE;
assign AWPROT = C_PROT_VALUE;
assign AWQOS = 4'b0000;
assign AWUSER = C_USER_VALUE;
assign AWVALID = (state==ADDR);
// write data channel
assign WDATA = data_buf[BUS_DATA_WIDTH-1:0];
assign WSTRB = wstrb0 & wstrb1;
assign WLAST = WVALID & (loop_beats==1'b1);
assign WUSER = C_USER_VALUE;
assign WVALID = (state==DATA) & data_valid[0];
// write response channel
assign BREADY = 1'b1; // we don't handle write response
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++write request++++++++++++++++++
generate
if (USER_DATA_BYTES <= BUS_DATA_BYTES) begin : gen_write_ready_0
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(~data_valid[0] | WREADY));
end
else begin : gen_write_ready_1
assign write_ready = (state==IDLE) | ((state==DATA) & ~enough_data &
(data_valid[DATA_BUF_BYTES-1:BUS_DATA_BYTES]==1'b0) &
(~data_valid[0] | WREADY));
end
endgenerate
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_nfa_forward_buckets_read/*{{{*/
#(parameter
C_ID_WIDTH = 1,
C_ADDR_WIDTH = 32,
C_DATA_WIDTH = 32,
C_ARUSER_WIDTH = 1,
C_RUSER_WIDTH = 1,
C_USER_DATA_WIDTH = 8,
C_TARGET_ADDR = 32'h00000000,
C_USER_VALUE = 1'b0,
C_PROT_VALUE = 3'b000,
C_CACHE_VALUE = 4'b0011
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read address channel
output wire [C_ID_WIDTH-1:0] ARID,
output wire [C_ADDR_WIDTH-1:0] ARADDR,
output wire [7:0] ARLEN,
output wire [2:0] ARSIZE,
output wire [1:0] ARBURST,
output wire [1:0] ARLOCK,
output wire [3:0] ARCACHE,
output wire [2:0] ARPROT,
output wire [3:0] ARQOS,
output wire [C_ARUSER_WIDTH-1:0] ARUSER,
output wire ARVALID,
input wire ARREADY,
// read data channel
input wire [C_ID_WIDTH-1:0] RID,
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire [1:0] RRESP,
input wire RLAST,
input wire [C_RUSER_WIDTH-1:0] RUSER,
input wire RVALID,
output wire RREADY,
// read request
output wire read_ready,
input wire read_valid,
input wire [31:0] read_address,
input wire [31:0] read_length,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read
);
//------------------------Parameter----------------------
localparam
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
// target address must be aligned to user data width
TARGET_ADDR = C_TARGET_ADDR & (32'hffffffff << USER_ADDR_ALIGN);
localparam [3:0]
IDLE = 4'd0,
PREP = 4'd1,
ADDR = 4'd2,
LOOP = 4'd3;
localparam
MAX_BEATS = 9'd256,
BOUNDARY = 16'h1000 >> BUS_ADDR_ALIGN;
//------------------------Local signal-------------------
// fsm
reg [3:0] state;
reg [3:0] next;
// translate request
wire [USER_ADDR_ALIGN+31:0] start_addr;
reg [USER_ADDR_ALIGN+31:0] addr_buf;
reg [31:0] len_buf;
reg [31:0] total_beats;
reg [8:0] loop_beats;
wire [11-BUS_ADDR_ALIGN:0] start_beat;
wire [8:0] tmp_beats0;
wire [8:0] tmp_beats1;
// data align
wire align_ready;
wire align_valid;
wire [31:0] align_beats;
wire [31:0] align_address;
wire [31:0] align_length;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_nfa_forward_buckets_read_data_align
nfa_accept_samples_generic_hw_nfa_forward_buckets_read_data_align #(
.C_DATA_WIDTH ( C_DATA_WIDTH ),
.C_USER_DATA_WIDTH ( C_USER_DATA_WIDTH )
) data_align (
.ACLK ( ACLK ),
.ARESETN ( ARESETN ),
.RDATA ( RDATA ),
.RVALID ( RVALID ),
.RREADY ( RREADY ),
.USER_datain ( USER_datain ),
.USER_rsp_read ( USER_rsp_read ),
.USER_rsp_empty_n ( USER_rsp_empty_n ),
.align_ready ( align_ready ),
.align_valid ( align_valid ),
.align_beats ( align_beats ),
.align_address ( align_address ),
.align_length ( align_length )
);
//------------------------Body---------------------------
//++++++++++++++++++++++++fsm++++++++++++++++++++++++++++
// state
always @(posedge ACLK) begin
if (~ARESETN)
state <= IDLE;
else
state <= next;
end
// next
always @(*) begin
case (state)
IDLE:
if (align_ready & read_valid)
next = PREP;
else
next = IDLE;
PREP:
next = ADDR;
ADDR:
if (ARREADY)
next = LOOP;
else
next = ADDR;
LOOP:
if (total_beats==1'b0)
next = IDLE;
else
next = ADDR;
default:
next = IDLE;
endcase
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++translate request++++++++++++++
assign start_addr = TARGET_ADDR + (read_address << USER_ADDR_ALIGN);
assign start_beat = addr_buf[11:BUS_ADDR_ALIGN];
assign tmp_beats0 = (total_beats < MAX_BEATS)? total_beats : MAX_BEATS;
assign tmp_beats1 = (tmp_beats0 < BOUNDARY - start_beat)? tmp_beats0 : BOUNDARY - start_beat;
// addr_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
addr_buf <= start_addr;
else if (state==PREP)
addr_buf[BUS_ADDR_ALIGN-1:0] <= 1'b0;
else if (state==ADDR && ARREADY)
addr_buf <= addr_buf + (loop_beats << BUS_ADDR_ALIGN);
end
// len_buf
always @(posedge ACLK) begin
if (read_ready & read_valid)
len_buf <= read_length;
end
// total_beats
always @(posedge ACLK) begin
if (read_ready & read_valid)
total_beats <= ((read_length << USER_ADDR_ALIGN) + start_addr[BUS_ADDR_ALIGN-1:0] +
{BUS_ADDR_ALIGN{1'b1}}) >> BUS_ADDR_ALIGN;
else if (state==ADDR && ARREADY)
total_beats <= total_beats - loop_beats;
end
// loop_beats
always @(posedge ACLK) begin
if (state==PREP || state==LOOP)
loop_beats <= tmp_beats1;
end
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read address channel+++++++++++
assign ARID = 1'b0;
assign ARADDR = addr_buf;
assign ARLEN = loop_beats - 1'b1;
assign ARSIZE = BUS_ADDR_ALIGN[2:0];
assign ARBURST = 2'b01;
assign ARLOCK = 2'b00;
assign ARCACHE = C_CACHE_VALUE;
assign ARPROT = C_PROT_VALUE;
assign ARQOS = 4'b0000;
assign ARUSER = C_USER_VALUE;
assign ARVALID = (state==ADDR);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++data align+++++++++++++++++++++
assign align_valid = (state==PREP);
assign align_beats = total_beats;
assign align_address = addr_buf;
assign align_length = len_buf;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
//++++++++++++++++++++++++read request+++++++++++++++++++
assign read_ready = (state==IDLE) & align_ready;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_nfa_forward_buckets_read_data_align/*{{{*/
#(parameter
C_DATA_WIDTH = 32,
C_USER_DATA_WIDTH = 8
)(
// system signal
input wire ACLK,
input wire ARESETN,
// read data channel
input wire [C_DATA_WIDTH-1:0] RDATA,
input wire RVALID,
output wire RREADY,
// user ports
output wire [C_USER_DATA_WIDTH-1:0] USER_datain,
output wire USER_rsp_empty_n,
input wire USER_rsp_read,
// data align
output wire align_ready,
input wire align_valid,
input wire [31:0] align_beats,
input wire [31:0] align_address,
input wire [31:0] align_length
);
//------------------------Parameter----------------------
localparam
DATA_FIFO_DEPTH = 32,
USER_DATA_WIDTH = calc_data_width(C_USER_DATA_WIDTH),
USER_DATA_BYTES = USER_DATA_WIDTH / 8,
USER_ADDR_ALIGN = log2(USER_DATA_BYTES),
BUS_DATA_WIDTH = C_DATA_WIDTH,
BUS_DATA_BYTES = BUS_DATA_WIDTH / 8,
BUS_ADDR_ALIGN = log2(BUS_DATA_BYTES),
DATA_BUF_WIDTH = USER_DATA_WIDTH > BUS_DATA_WIDTH?
USER_DATA_WIDTH : BUS_DATA_WIDTH,
DATA_VALID_BITS = USER_DATA_BYTES > BUS_DATA_BYTES ?
USER_DATA_BYTES / BUS_DATA_BYTES :
BUS_DATA_BYTES / USER_DATA_BYTES;
//------------------------Task and function--------------
function integer calc_data_width;
input integer x;
integer y;
begin
y = 8;
while (y < x) y = y * 2;
calc_data_width = y;
end
endfunction
function integer log2;
input integer x;
integer n, m;
begin
n = 0;
m = 1;
while (m < x) begin
n = n + 1;
m = m * 2;
end
log2 = n;
end
endfunction
//------------------------Local signal-------------------
reg [DATA_BUF_WIDTH-1:0] data_buf;
reg [DATA_VALID_BITS-1:0] data_valid;
reg [31:0] total_beats;
reg ready_buf;
wire [BUS_DATA_WIDTH-1:0] rs0_data;
wire rs0_valid;
wire rs0_ready;
wire fifo_empty_n;
wire fifo_full_n;
wire fifo_rdreq;
wire fifo_wrreq;
wire [C_USER_DATA_WIDTH-1:0] fifo_q;
wire [C_USER_DATA_WIDTH-1:0] fifo_data;
wire fifo_push;
//------------------------Instantiation------------------
// nfa_accept_samples_generic_hw_nfa_forward_buckets_reg_slice
nfa_accept_samples_generic_hw_nfa_forward_buckets_reg_slice #(
.N ( BUS_DATA_WIDTH )
) rs0 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( RDATA ),
.s_valid ( RVALID ),
.s_ready ( RREADY ),
.m_data ( rs0_data ),
.m_valid ( rs0_valid ),
.m_ready ( rs0_ready )
);
// nfa_accept_samples_generic_hw_nfa_forward_buckets_fifo
nfa_accept_samples_generic_hw_nfa_forward_buckets_fifo #(
.DATA_BITS ( C_USER_DATA_WIDTH ),
.DEPTH ( DATA_FIFO_DEPTH ),
.DEPTH_BITS ( log2(DATA_FIFO_DEPTH) )
) data_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( fifo_empty_n ),
.full_n ( fifo_full_n ),
.rdreq ( fifo_rdreq ),
.wrreq ( fifo_wrreq ),
.q ( fifo_q ),
.data ( fifo_data )
);
// nfa_accept_samples_generic_hw_nfa_forward_buckets_reg_slice
nfa_accept_samples_generic_hw_nfa_forward_buckets_reg_slice #(
.N ( C_USER_DATA_WIDTH )
) rs1 (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.s_data ( fifo_q ),
.s_valid ( fifo_empty_n ),
.s_ready ( fifo_rdreq ),
.m_data ( USER_datain ),
.m_valid ( USER_rsp_empty_n ),
.m_ready ( USER_rsp_read )
);
//------------------------Body---------------------------
assign fifo_data = data_buf[C_USER_DATA_WIDTH-1:0];
assign fifo_wrreq = data_valid[0];
assign fifo_push = fifo_full_n & fifo_wrreq;
generate
if (USER_DATA_BYTES >= BUS_DATA_BYTES) begin : narrow_to_wide
/*
* user data width is greater than or equal to bus data width
* so all bytes of bus data are valid
*/
assign align_ready = 1'b1;
assign rs0_ready = ~align_valid & ready_buf & (~data_valid[0] | fifo_push);
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= {rs0_data, data_buf} >> BUS_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (fifo_push)
data_valid <= (rs0_ready & rs0_valid) << (DATA_VALID_BITS-1);
else if (rs0_ready & rs0_valid)
data_valid <= {1'b1, data_valid} >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (~ARESETN)
total_beats <= 1'b0;
else if (align_valid)
total_beats <= total_beats + align_beats; // may overflow
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (align_valid)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
end // end of narrow_to_wide
else begin : wide_to_narrow
/*
* user data width is less than bus data width
* so we have to remove the padding bytes
*/
localparam
PADDING_BITS = log2(DATA_VALID_BITS),
MAX_REQUEST = 32,
DATA_BITS = PADDING_BITS * 2 + 32;
wire [31:0] end_address;
wire [PADDING_BITS-1:0] head_tmp;
wire [PADDING_BITS-1:0] tail_tmp;
reg [PADDING_BITS-1:0] head_padding;
reg [PADDING_BITS-1:0] tail_padding;
reg first_beat;
reg last_beat;
wire request_fifo_empty_n;
wire request_fifo_full_n;
wire request_fifo_rdreq;
wire request_fifo_wrreq;
wire [DATA_BITS-1:0] request_fifo_q;
wire [DATA_BITS-1:0] request_fifo_data;
// nfa_accept_samples_generic_hw_nfa_forward_buckets_fifo
nfa_accept_samples_generic_hw_nfa_forward_buckets_fifo #(
.DATA_BITS ( DATA_BITS ),
.DEPTH ( MAX_REQUEST ),
.DEPTH_BITS ( log2(MAX_REQUEST) )
) request_fifo (
.sclk ( ACLK ),
.reset_n ( ARESETN ),
.empty_n ( request_fifo_empty_n ),
.full_n ( request_fifo_full_n ),
.rdreq ( request_fifo_rdreq ),
.wrreq ( request_fifo_wrreq ),
.q ( request_fifo_q ),
.data ( request_fifo_data )
);
assign align_ready = request_fifo_full_n;
assign rs0_ready = ready_buf & (data_valid==1'b0 || (data_valid==1'b1 && fifo_push));
assign end_address = align_address + align_length * USER_DATA_BYTES;
assign head_tmp = align_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN];
assign tail_tmp = ~end_address[BUS_ADDR_ALIGN-1:USER_ADDR_ALIGN] + 1'b1;
assign request_fifo_rdreq = request_fifo_empty_n & ~ready_buf;
assign request_fifo_wrreq = align_valid;
assign request_fifo_data = {head_tmp, tail_tmp, align_beats};
// data_buf
always @(posedge ACLK) begin
if (rs0_ready & rs0_valid)
data_buf <= rs0_data >> (first_beat? head_padding * USER_DATA_WIDTH : 0);
else if (fifo_push)
data_buf <= data_buf >> USER_DATA_WIDTH;
end
// data_valid
always @(posedge ACLK) begin
if (~ARESETN)
data_valid <= 1'b0;
else if (rs0_ready & rs0_valid)
data_valid <= ({DATA_VALID_BITS{1'b1}} >> (last_beat? tail_padding : 0))
>> (first_beat? head_padding : 0);
else if (fifo_push)
data_valid <= data_valid >> 1;
end
// total_beats
always @(posedge ACLK) begin
if (request_fifo_rdreq)
total_beats <= request_fifo_q[31:0];
else if (rs0_ready & rs0_valid)
total_beats <= total_beats - 1'b1;
end
// ready_buf
always @(posedge ACLK) begin
if (~ARESETN)
ready_buf <= 1'b0;
else if (request_fifo_rdreq)
ready_buf <= 1'b1;
else if (rs0_ready && rs0_valid && total_beats==1'b1)
ready_buf <= 1'b0;
end
// head_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
head_padding <= request_fifo_q[31+PADDING_BITS*2:32+PADDING_BITS];
end
// tail_padding
always @(posedge ACLK) begin
if (request_fifo_rdreq)
tail_padding <= request_fifo_q[31+PADDING_BITS:32];
end
// first_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq)
first_beat <= 1'b1;
else if (rs0_ready & rs0_valid)
first_beat <= 1'b0;
end
// last_beat
always @(posedge ACLK) begin
if (request_fifo_rdreq && request_fifo_q[31:0]==1'b1)
last_beat <= 1'b1;
else if (rs0_ready & rs0_valid) begin
if (total_beats==2'd2)
last_beat <= 1'b1;
else
last_beat <= 1'b0;
end
end
end // end of wide_to_narrow
endgenerate
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_nfa_forward_buckets_fifo/*{{{*/
#(parameter
DATA_BITS = 8,
DEPTH = 16,
DEPTH_BITS = 4
)(
input wire sclk,
input wire reset_n,
output reg empty_n,
output reg full_n,
input wire rdreq,
input wire wrreq,
output wire [DATA_BITS-1:0] q,
input wire [DATA_BITS-1:0] data
);
//------------------------Parameter----------------------
//------------------------Local signal-------------------
wire push;
wire pop;
reg [DEPTH_BITS-1:0] pout;
reg [DATA_BITS-1:0] mem[0:DEPTH-1];
//------------------------Body---------------------------
assign push = full_n & wrreq;
assign pop = empty_n & rdreq;
assign q = mem[pout];
// empty_n
always @(posedge sclk) begin
if (~reset_n)
empty_n <= 1'b0;
else if (push)
empty_n <= 1'b1;
else if (~push && pop && pout == 1'b0)
empty_n <= 1'b0;
end
// full_n
always @(posedge sclk) begin
if (~reset_n)
full_n <= 1'b1;
else if (rdreq)
full_n <= 1'b1;
else if (push && ~pop && pout == DEPTH - 2)
full_n <= 1'b0;
end
// pout
always @(posedge sclk) begin
if (~reset_n)
pout <= 1'b0;
else if (push & ~pop & empty_n)
pout <= pout + 1'b1;
else if (~push && pop && pout != 1'b0)
pout <= pout - 1'b1;
end
integer i;
always @(posedge sclk) begin
if (push) begin
for (i = 0; i < DEPTH - 1; i = i + 1) begin
mem[i+1] <= mem[i];
end
mem[0] <= data;
end
end
endmodule/*}}}*/
`timescale 1ns/1ps
module nfa_accept_samples_generic_hw_nfa_forward_buckets_reg_slice/*{{{*/
#(parameter
N = 8 // data width
) (
// system signals
input wire sclk,
input wire reset_n,
// slave side
input wire [N-1:0] s_data,
input wire s_valid,
output wire s_ready,
// master side
output wire [N-1:0] m_data,
output wire m_valid,
input wire m_ready
);
//------------------------Parameter----------------------
// state
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
//------------------------Local signal-------------------
reg [N-1:0] data_p1;
reg [N-1:0] data_p2;
wire load_p1;
wire load_p2;
wire load_p1_from_p2;
reg s_ready_t;
reg [1:0] state;
reg [1:0] next;
//------------------------Body---------------------------
assign s_ready = s_ready_t;
assign m_data = data_p1;
assign m_valid = state[0];
assign load_p1 = (state == ZERO && s_valid) ||
(state == ONE && s_valid && m_ready) ||
(state == TWO && m_ready);
assign load_p2 = s_valid & s_ready;
assign load_p1_from_p2 = (state == TWO);
// data_p1
always @(posedge sclk) begin
if (load_p1) begin
if (load_p1_from_p2)
data_p1 <= data_p2;
else
data_p1 <= s_data;
end
end
// data_p2
always @(posedge sclk) begin
if (load_p2) data_p2 <= s_data;
end
// s_ready_t
always @(posedge sclk) begin
if (~reset_n)
s_ready_t <= 1'b0;
else if (state == ZERO)
s_ready_t <= 1'b1;
else if (state == ONE && next == TWO)
s_ready_t <= 1'b0;
else if (state == TWO && next == ONE)
s_ready_t <= 1'b1;
end
// state
always @(posedge sclk) begin
if (~reset_n)
state <= ZERO;
else
state <= next;
end
// next
always @(*) begin
case (state)
ZERO:
if (s_valid & s_ready)
next = ONE;
else
next = ZERO;
ONE:
if (~s_valid & m_ready)
next = ZERO;
else if (s_valid & ~m_ready)
next = TWO;
else
next = ONE;
TWO:
if (m_ready)
next = ONE;
else
next = TWO;
default:
next = ZERO;
endcase
end
endmodule/*}}}*/
// vim:ts=4 sw=4 et fdm=marker:
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:06:19 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_selector_A, FSM_selector_C, FSM_selector_B_1_,
exp_oper_result_8_, Exp_module_Overflow_flag_A, n168, n170, n171,
n172, n173, n174, n175, n176, n177, n178, n179, n180, n181, n182,
n183, n184, n185, n186, n187, n188, n189, n190, n191, n192, n193,
n194, n195, n196, n197, n198, n199, n200, n202, n203, n204, n205,
n206, n208, n222, n225, n226, n227, n228, n229, n230, n231, n232,
n233, n234, n235, n238, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n285,
n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296,
n297, n298, n299, n300, n301, n302, n303, n304, n305, n306, n307,
n308, n309, n310, n311, n312, n313, n314, n316, n317, n318, n319,
n321, n323, n324, n325, n327, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n348, n349, n350, n352,
n353, n354, n355, n356, n357, n358, n360, n362, n363, n364, n365,
n366, n367, n368, n369, n370, n371, n372, n373, n374, n375, n376,
n377, n378, n380, n381, mult_x_19_n1805, mult_x_19_n1801,
mult_x_19_n1800, mult_x_19_n1797, mult_x_19_n1791, mult_x_19_n1777,
mult_x_19_n1775, mult_x_19_n1773, mult_x_19_n1753, mult_x_19_n1751,
mult_x_19_n1749, mult_x_19_n1697, mult_x_19_n1687, mult_x_19_n1678,
mult_x_19_n1677, mult_x_19_n1676, mult_x_19_n1674, mult_x_19_n1656,
mult_x_19_n1635, mult_x_19_n1617, mult_x_19_n1610, mult_x_19_n1603,
mult_x_19_n1587, mult_x_19_n1585, mult_x_19_n1556, mult_x_19_n1552,
mult_x_19_n1542, mult_x_19_n1010, mult_x_19_n995, mult_x_19_n994,
mult_x_19_n977, mult_x_19_n976, mult_x_19_n960, mult_x_19_n959,
mult_x_19_n958, mult_x_19_n943, mult_x_19_n941, mult_x_19_n940,
mult_x_19_n923, mult_x_19_n921, mult_x_19_n897, mult_x_19_n896,
mult_x_19_n875, mult_x_19_n874, mult_x_19_n853, mult_x_19_n852,
mult_x_19_n851, mult_x_19_n832, mult_x_19_n830, mult_x_19_n829,
mult_x_19_n810, mult_x_19_n808, mult_x_19_n807, mult_x_19_n788,
mult_x_19_n786, mult_x_19_n764, mult_x_19_n763, mult_x_19_n744,
mult_x_19_n743, mult_x_19_n726, mult_x_19_n725, mult_x_19_n723,
mult_x_19_n708, mult_x_19_n707, mult_x_19_n692, mult_x_19_n691,
mult_x_19_n689, mult_x_19_n676, mult_x_19_n675, mult_x_19_n662,
mult_x_19_n661, mult_x_19_n651, mult_x_19_n649, mult_x_19_n648,
mult_x_19_n647, mult_x_19_n639, mult_x_19_n638, mult_x_19_n637,
mult_x_19_n633, mult_x_19_n626, mult_x_19_n614, mult_x_19_n613,
mult_x_19_n611, mult_x_19_n604, mult_x_19_n593, mult_x_19_n579,
mult_x_19_n555, mult_x_19_n525, mult_x_19_n524, mult_x_19_n480,
mult_x_19_n474, mult_x_19_n471, mult_x_19_n466, mult_x_19_n465,
mult_x_19_n459, mult_x_19_n458, mult_x_19_n453, mult_x_19_n451,
mult_x_19_n439, mult_x_19_n430, mult_x_19_n424, mult_x_19_n423,
mult_x_19_n421, mult_x_19_n418, mult_x_19_n267, mult_x_19_n211,
mult_x_19_n198, mult_x_19_n197, mult_x_19_n181, mult_x_19_n179,
mult_x_19_n166, mult_x_19_n165, mult_x_19_n146, mult_x_19_n145,
mult_x_19_n135, mult_x_19_n115, mult_x_19_n114, mult_x_19_n113,
mult_x_19_n112, mult_x_19_n111, mult_x_19_n110, mult_x_19_n109,
mult_x_19_n108, mult_x_19_n82, mult_x_19_n58, mult_x_19_n52,
mult_x_19_n49, mult_x_19_n43, mult_x_19_n28, mult_x_19_n19,
mult_x_19_n7, mult_x_19_n4, n397, n398, n399, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n416, n417, n418, n419, n420,
n421, n422, n423, n424, n425, n426, n427, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508,
n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n525, n526, n527, n528, n529, n530,
n531, n532, n533, n534, n535, n536, n537, n538, n539, n540, n541,
n542, n543, n544, n545, n546, n547, n548, n549, n550, n551, n552,
n553, n554, n555, n556, n557, n558, n559, n560, n561, n562, n563,
n564, n565, n566, n567, n568, n569, n570, n571, n572, n573, n574,
n575, n576, n577, n578, n579, n580, n581, n582, n583, n584, n585,
n586, n587, n588, n589, n590, n591, n592, n593, n594, n595, n596,
n597, n598, n599, n600, n601, n602, n603, n604, n605, n606, n607,
n608, n609, n610, n611, n612, n613, n614, n615, n616, n617, n618,
n619, n620, n621, n622, n623, n624, n625, n626, n627, n628, n629,
n630, n631, n632, n633, n634, n635, n636, n637, n638, n639, n640,
n641, n642, n643, n644, n645, n646, n647, n648, n649, n650, n651,
n652, n653, n654, n655, n656, n657, n658, n659, n660, n661, n662,
n663, n664, n665, n666, n667, n668, n669, n670, n671, n672, n673,
n674, n675, n676, n677, n678, n679, n680, n681, n682, n683, n684,
n685, n686, n687, n688, n689, n690, n691, n692, n693, n694, n695,
n696, n697, n698, n699, n700, n701, n702, n703, n704, n705, n706,
n707, n708, n709, n710, n711, n712, n713, n714, n715, n716, n717,
n718, n719, n720, n721, n722, n723, n724, n725, n726, n727, n728,
n729, n730, n731, n732, n733, n734, n735, n736, n737, n738, n739,
n740, n741, n742, n743, n744, n745, n746, n747, n748, n749, n750,
n751, n752, n753, n754, n755, n756, n757, n758, n759, n760, n761,
n762, n763, n764, n765, n766, n767, n768, n769, n770, n771, n772,
n773, n774, n775, n776, n777, n778, n779, n780, n781, n782, n783,
n784, n785, n786, n787, n788, n789, n790, n791, n792, n793, n794,
n795, n796, n797, n798, n799, n800, n801, n802, n803, n804, n805,
n806, n807, n808, n809, n810, n811, n812, n813, n815, n816, n817,
n818, n819, n820, n821, n822, n823, n824, n825, n826, n827, n828,
n829, n830, n831, n832, n833, n834, n835, n836, n837, n838, n839,
n840, n841, n842, n843, n844, n845, n846, n847, n848, n849, n850,
n851, n852, n853, n854, n855, n856, n857, n858, n859, n860, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2878, n2879, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3360, n3361;
wire [6:0] P_Sgf;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [23:0] Add_result;
wire [20:0] Sgf_normalized_result;
wire [3:1] FS_Module_state_reg;
wire [9:7] Sgf_operation_Result;
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(clk), .RN(n3156), .Q(
FS_Module_state_reg[1]), .QN(n3139) );
DFFRX4TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(clk), .RN(n3158), .Q(
FS_Module_state_reg[2]), .QN(n3119) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(clk), .RN(n3088), .Q(
FS_Module_state_reg[3]), .QN(n3120) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n376), .CK(clk), .RN(n3154), .Q(FSM_selector_A),
.QN(n3121) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n3155), .Q(Op_MX[25]), .QN(n3117) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n3285), .Q(Op_MX[24]), .QN(n997) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(clk), .RN(n3164),
.Q(Add_result[18]), .QN(n3125) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(clk), .RN(n3284),
.Q(Add_result[9]), .QN(n3133) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(clk), .RN(n788),
.Q(Add_result[8]), .QN(n3142) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(clk), .RN(n3165),
.Q(Add_result[7]), .QN(n3144) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(clk), .RN(n815),
.Q(Add_result[6]), .QN(n3143) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(clk), .RN(n3167),
.Q(Add_result[5]), .QN(n3145) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(clk), .RN(n3075),
.Q(Add_result[3]), .QN(n3146) );
DFFRX2TS R_510 ( .D(mult_x_19_n1775), .CK(clk), .RN(n3281), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n778), .Q(Op_MY[5]), .QN(n696) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n235), .CK(clk), .RN(n773), .Q(
FSM_selector_B_1_), .QN(n3118) );
DFFSX1TS R_2 ( .D(n3325), .CK(clk), .SN(n3161), .Q(n3272) );
DFFSX1TS R_5 ( .D(n3321), .CK(clk), .SN(n3161), .Q(n3271) );
DFFSX1TS R_8 ( .D(n3297), .CK(clk), .SN(n3158), .Q(n3270) );
DFFSX1TS R_11 ( .D(n3296), .CK(clk), .SN(n3161), .Q(n3269) );
DFFSX1TS R_12 ( .D(n3275), .CK(clk), .SN(n3159), .Q(n3268) );
DFFSX1TS R_15 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3266) );
DFFSX1TS R_17 ( .D(n3337), .CK(clk), .SN(n3159), .Q(n3265) );
DFFSX1TS R_20 ( .D(n3313), .CK(clk), .SN(n3080), .Q(n3264) );
DFFSX1TS R_23 ( .D(n3309), .CK(clk), .SN(n3162), .Q(n3263) );
DFFSX1TS R_26 ( .D(n3305), .CK(clk), .SN(n3161), .Q(n3262) );
DFFSX1TS R_29 ( .D(n3301), .CK(clk), .SN(n3158), .Q(n3261) );
DFFSX1TS R_30 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3260) );
DFFSX1TS R_33 ( .D(n3275), .CK(clk), .SN(n3086), .Q(n3258) );
DFFSX1TS R_35 ( .D(n3317), .CK(clk), .SN(n3162), .Q(n3257) );
DFFSX1TS R_36 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3256) );
DFFSX1TS R_38 ( .D(n3329), .CK(clk), .SN(n3160), .Q(n3255) );
DFFSX1TS R_44 ( .D(n3292), .CK(clk), .SN(n3161), .Q(n3252) );
DFFSX1TS R_47 ( .D(n3288), .CK(clk), .SN(n3360), .Q(n3251) );
DFFSX1TS R_50 ( .D(n3286), .CK(clk), .SN(n3360), .Q(n3250) );
DFFRXLTS R_52 ( .D(n258), .CK(clk), .RN(n3277), .Q(n3249) );
DFFSX1TS R_54 ( .D(n3275), .CK(clk), .SN(n3160), .Q(n3248) );
DFFRXLTS R_58 ( .D(n266), .CK(clk), .RN(n3159), .Q(n3246) );
DFFRXLTS R_95 ( .D(n265), .CK(clk), .RN(n3159), .Q(n3245) );
DFFRXLTS R_98 ( .D(n267), .CK(clk), .RN(n3159), .Q(n3244) );
DFFRXLTS R_101 ( .D(n264), .CK(clk), .RN(n3159), .Q(n3243) );
DFFRXLTS R_104 ( .D(n262), .CK(clk), .RN(n3162), .Q(n3242) );
DFFRXLTS R_107 ( .D(n261), .CK(clk), .RN(n3277), .Q(n3241) );
DFFRXLTS R_110 ( .D(n263), .CK(clk), .RN(n3159), .Q(n3240) );
DFFRXLTS R_113 ( .D(n260), .CK(clk), .RN(n3081), .Q(n3239) );
DFFRXLTS R_121 ( .D(n259), .CK(clk), .RN(n794), .Q(n3237) );
DFFRXLTS R_158 ( .D(n254), .CK(clk), .RN(n3157), .Q(n3236) );
DFFRXLTS R_237 ( .D(n256), .CK(clk), .RN(n3157), .Q(n3235) );
DFFRXLTS R_278 ( .D(n252), .CK(clk), .RN(n3157), .Q(n3234) );
DFFRXLTS R_299 ( .D(n255), .CK(clk), .RN(n3157), .Q(n3233) );
DFFRXLTS R_302 ( .D(n253), .CK(clk), .RN(n3157), .Q(n3232) );
DFFRXLTS R_118 ( .D(n257), .CK(clk), .RN(n3081), .Q(n3238) );
DFFSX4TS R_911 ( .D(n3353), .CK(clk), .SN(n3156), .Q(n3217) );
DFFSX4TS R_912 ( .D(n3354), .CK(clk), .SN(n3156), .Q(n3216) );
DFFSX4TS R_981 ( .D(n3348), .CK(clk), .SN(n815), .Q(n3188) );
DFFSX4TS R_1026 ( .D(n3355), .CK(clk), .SN(n3282), .Q(n3182) );
DFFSX4TS R_1039 ( .D(n3351), .CK(clk), .SN(n3154), .Q(n3180) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(clk), .RN(n3163),
.Q(Add_result[20]), .QN(n3123) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(clk), .RN(n773), .Q(final_result_ieee[31]), .QN(n3152) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(clk), .RN(n3282), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(clk), .RN(n788), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(clk), .RN(n778), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(clk), .RN(n778), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n817), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(clk), .RN(n815), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(clk), .RN(n3361), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n788), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n3361), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(clk), .RN(n788), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n788), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(clk), .RN(n788), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(clk), .RN(n3361), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(clk), .RN(n3361), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n788), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(clk), .RN(n3361), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(clk), .RN(n795), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(clk), .RN(n795), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(clk), .RN(n795), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(clk), .RN(n795), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n795), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n795), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n795), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(clk), .RN(n795), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(clk), .RN(n795), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(clk), .RN(n795), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(clk), .RN(n3278), .Q(final_result_ieee[30]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(clk), .RN(n3163),
.Q(Add_result[19]), .QN(n3124) );
DFFRXLTS R_437 ( .D(mult_x_19_n1773), .CK(clk), .RN(n3164), .Q(Op_MY[21]),
.QN(n3110) );
DFFRXLTS R_448 ( .D(mult_x_19_n579), .CK(clk), .RN(n3155), .Q(Op_MY[20]),
.QN(n3111) );
DFFRXLTS R_1037 ( .D(mult_x_19_n633), .CK(clk), .RN(n3281), .Q(Op_MY[14]),
.QN(n3109) );
DFFRXLTS R_913 ( .D(mult_x_19_n611), .CK(clk), .RN(n3281), .Q(Op_MY[16]),
.QN(n3150) );
DFFSX1TS R_866 ( .D(n3287), .CK(clk), .SN(n817), .Q(n3220) );
DFFRXLTS R_867 ( .D(n310), .CK(clk), .RN(n817), .Q(n3219) );
DFFSX2TS R_868 ( .D(n3273), .CK(clk), .SN(n817), .Q(n3218) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n3155), .Q(
Exp_module_Overflow_flag_A), .QN(n3151) );
DFFRXLTS R_545 ( .D(n364), .CK(clk), .RN(n771), .Q(Op_MX[20]), .QN(n409) );
DFFRX2TS R_483 ( .D(n357), .CK(clk), .RN(n815), .Q(Op_MX[13]) );
DFFRX2TS R_471 ( .D(n352), .CK(clk), .RN(n771), .Q(Op_MX[8]) );
DFFRX2TS R_321 ( .D(n354), .CK(clk), .RN(n773), .Q(Op_MX[10]) );
DFFRX2TS R_169 ( .D(mult_x_19_n19), .CK(clk), .RN(n3285), .Q(Op_MX[7]) );
DFFRX2TS R_377 ( .D(n350), .CK(clk), .RN(n772), .Q(Op_MX[6]) );
DFFRX2TS R_427 ( .D(n356), .CK(clk), .RN(n3166), .Q(Op_MX[12]) );
DFFRX2TS R_320 ( .D(n353), .CK(clk), .RN(n772), .Q(Op_MX[9]) );
DFFRX2TS R_199 ( .D(n365), .CK(clk), .RN(n3167), .Q(Op_MX[21]) );
DFFRX2TS R_200 ( .D(n366), .CK(clk), .RN(n816), .Q(Op_MX[22]) );
DFFRX2TS R_204 ( .D(n349), .CK(clk), .RN(n3285), .Q(Op_MX[5]) );
DFFSX1TS R_727 ( .D(Sgf_operation_Result[8]), .CK(clk), .SN(n3084), .Q(n3228) );
DFFSX1TS R_1067 ( .D(Sgf_operation_Result[7]), .CK(clk), .SN(n3161), .Q(
n3172) );
DFFRXLTS R_745 ( .D(n247), .CK(clk), .RN(n3160), .Q(n3224) );
DFFSX1TS R_852 ( .D(n3294), .CK(clk), .SN(n816), .Q(n3222) );
DFFSX1TS R_919 ( .D(n3307), .CK(clk), .SN(n3165), .Q(n3214) );
DFFSX1TS R_964 ( .D(n3331), .CK(clk), .SN(n3167), .Q(n3205) );
DFFSX1TS R_967 ( .D(n3315), .CK(clk), .SN(n3166), .Q(n3202) );
DFFSX1TS R_976 ( .D(n3335), .CK(clk), .SN(n3076), .Q(n3193) );
DFFSX1TS R_1071 ( .D(n3299), .CK(clk), .SN(n817), .Q(n3169) );
DFFSX2TS R_851 ( .D(n3295), .CK(clk), .SN(n816), .Q(n3223) );
DFFSX2TS R_918 ( .D(n3308), .CK(clk), .SN(n3283), .Q(n3215) );
DFFSX2TS R_963 ( .D(n3332), .CK(clk), .SN(n3167), .Q(n3206) );
DFFSX2TS R_966 ( .D(n3316), .CK(clk), .SN(n3167), .Q(n3203) );
DFFSX2TS R_975 ( .D(n3336), .CK(clk), .SN(n3163), .Q(n3194) );
DFFSX2TS R_1070 ( .D(n3300), .CK(clk), .SN(n816), .Q(n3170) );
DFFSX1TS R_853 ( .D(n3293), .CK(clk), .SN(n817), .Q(n3221) );
DFFSX1TS R_920 ( .D(n3306), .CK(clk), .SN(n3165), .Q(n3213) );
DFFSX1TS R_965 ( .D(n3330), .CK(clk), .SN(n3166), .Q(n3204) );
DFFSX1TS R_977 ( .D(n3334), .CK(clk), .SN(n3165), .Q(n3192) );
DFFSX1TS R_1072 ( .D(n3298), .CK(clk), .SN(n816), .Q(n3168) );
DFFSX1TS R_950 ( .D(n3327), .CK(clk), .SN(n3283), .Q(n3211) );
DFFSX1TS R_958 ( .D(n3303), .CK(clk), .SN(n3167), .Q(n3208) );
DFFSX1TS R_970 ( .D(n3323), .CK(clk), .SN(n3167), .Q(n3199) );
DFFSX1TS R_973 ( .D(n3319), .CK(clk), .SN(n3361), .Q(n3196) );
DFFSX1TS R_982 ( .D(n3347), .CK(clk), .SN(n778), .Q(n3187) );
DFFSX1TS R_992 ( .D(n3290), .CK(clk), .SN(n816), .Q(n3184) );
DFFSX1TS R_1061 ( .D(n3339), .CK(clk), .SN(n3165), .Q(n3174) );
DFFSX2TS R_949 ( .D(n3328), .CK(clk), .SN(n3075), .Q(n3212) );
DFFSX2TS R_957 ( .D(n3304), .CK(clk), .SN(n3166), .Q(n3209) );
DFFSX2TS R_969 ( .D(n3324), .CK(clk), .SN(n3166), .Q(n3200) );
DFFSX2TS R_972 ( .D(n3320), .CK(clk), .SN(n403), .Q(n3197) );
DFFSX2TS R_991 ( .D(n3291), .CK(clk), .SN(n817), .Q(n3185) );
DFFSX2TS R_1060 ( .D(n3340), .CK(clk), .SN(n3166), .Q(n3175) );
DFFSX1TS R_951 ( .D(n3326), .CK(clk), .SN(n3079), .Q(n3210) );
DFFSX1TS R_959 ( .D(n3302), .CK(clk), .SN(n3361), .Q(n3207) );
DFFSX1TS R_971 ( .D(n3322), .CK(clk), .SN(n3166), .Q(n3198) );
DFFSX1TS R_974 ( .D(n3318), .CK(clk), .SN(n3361), .Q(n3195) );
DFFSX1TS R_983 ( .D(n3346), .CK(clk), .SN(n817), .Q(n3186) );
DFFSX1TS R_993 ( .D(n3289), .CK(clk), .SN(n816), .Q(n3183) );
DFFSX1TS R_1062 ( .D(n3338), .CK(clk), .SN(n3165), .Q(n3173) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(clk),
.RN(n3153), .Q(Sgf_normalized_result[3]), .QN(n3138) );
DFFSX1TS R_1048 ( .D(n3357), .CK(clk), .SN(n3164), .Q(n3177) );
DFFSX1TS mult_x_19_R_773 ( .D(mult_x_19_n976), .CK(clk), .SN(n3091), .Q(
n2975) );
DFFSX2TS mult_x_19_R_656 ( .D(mult_x_19_n692), .CK(clk), .SN(n3084), .Q(
n2964) );
DFFRX1TS mult_x_19_R_829 ( .D(mult_x_19_n763), .CK(clk), .RN(n794), .Q(n2988) );
DFFSX2TS mult_x_19_R_845 ( .D(mult_x_19_n763), .CK(clk), .SN(n3083), .Q(
n2995) );
DFFSX2TS mult_x_19_R_846 ( .D(mult_x_19_n744), .CK(clk), .SN(n3083), .Q(
n2996) );
DFFRX1TS mult_x_19_R_850 ( .D(mult_x_19_n725), .CK(clk), .RN(n794), .Q(n2997) );
DFFSX2TS mult_x_19_R_998 ( .D(mult_x_19_n661), .CK(clk), .SN(n3087), .Q(
n3034) );
DFFSX2TS mult_x_19_R_997 ( .D(mult_x_19_n648), .CK(clk), .SN(n3087), .Q(
n3033) );
DFFRX1TS mult_x_19_R_1077 ( .D(mult_x_19_n994), .CK(clk), .RN(n3091), .Q(
n3061) );
DFFSX1TS mult_x_19_R_1138 ( .D(mult_x_19_n480), .CK(clk), .SN(n3089), .Q(
n3072) );
DFFSX2TS mult_x_19_R_531 ( .D(n2925), .CK(clk), .SN(n2575), .Q(n2899) );
DFFRX1TS mult_x_19_R_960_RW_0 ( .D(mult_x_19_n267), .CK(clk), .RN(n3086),
.QN(n3100) );
DFFSX2TS mult_x_19_R_1136 ( .D(n3071), .CK(clk), .SN(n3078), .Q(
mult_x_19_n1556) );
DFFSX2TS mult_x_19_R_478 ( .D(n2926), .CK(clk), .SN(n3078), .Q(n2888) );
DFFSX2TS mult_x_19_R_523 ( .D(n2942), .CK(clk), .SN(n3280), .Q(
mult_x_19_n1676) );
DFFSX2TS mult_x_19_R_1083 ( .D(n3063), .CK(clk), .SN(n815), .Q(
mult_x_19_n1656) );
DFFSX2TS mult_x_19_R_1058 ( .D(n3054), .CK(clk), .SN(n3078), .Q(
mult_x_19_n1587) );
DFFSX2TS mult_x_19_R_1055 ( .D(n3053), .CK(clk), .SN(n3282), .Q(
mult_x_19_n1687) );
DFFRX4TS mult_x_19_R_1120 ( .D(n2913), .CK(clk), .RN(n3090), .QN(n3093) );
DFFSX1TS mult_x_19_R_1106 ( .D(n3067), .CK(clk), .SN(n3155), .Q(
mult_x_19_n1610) );
DFFRX4TS mult_x_19_R_1127 ( .D(n357), .CK(clk), .RN(n404), .Q(n2890), .QN(
n779) );
DFFSX1TS mult_x_19_R_1087 ( .D(n3064), .CK(clk), .SN(n3076), .Q(
mult_x_19_n1674) );
DFFRXLTS mult_x_19_R_870_RW_1 ( .D(mult_x_19_n958), .CK(clk), .RN(n2576),
.Q(n3004) );
DFFRX4TS mult_x_19_R_1118 ( .D(n3050), .CK(clk), .RN(n3079), .Q(n2905), .QN(
n3098) );
DFFRX4TS mult_x_19_R_1054 ( .D(mult_x_19_n19), .CK(clk), .RN(n402), .Q(n2898), .QN(n629) );
DFFSX1TS mult_x_19_R_1036 ( .D(n3049), .CK(clk), .SN(n3074), .Q(
mult_x_19_n1751) );
DFFSX1TS mult_x_19_R_1033 ( .D(mult_x_19_n179), .CK(clk), .SN(n3085), .Q(
n3048) );
DFFSX1TS mult_x_19_R_1022 ( .D(n3045), .CK(clk), .SN(n3278), .Q(
mult_x_19_n1635) );
DFFSX1TS mult_x_19_R_1013 ( .D(mult_x_19_n198), .CK(clk), .SN(n3083), .Q(
n3044) );
DFFSX1TS mult_x_19_R_1012 ( .D(mult_x_19_n525), .CK(clk), .SN(n3083), .Q(
n3043) );
DFFSX1TS mult_x_19_R_722_RW_1 ( .D(mult_x_19_n421), .CK(clk), .SN(n3088),
.Q(n2970) );
DFFRX2TS mult_x_19_R_1000 ( .D(mult_x_19_n676), .CK(clk), .RN(n3086), .Q(
n3035) );
DFFSX4TS mult_x_19_R_988 ( .D(mult_x_19_n788), .CK(clk), .SN(n3086), .Q(
n3030) );
DFFRXLTS mult_x_19_R_986 ( .D(mult_x_19_n198), .CK(clk), .RN(n3086), .Q(
n3029) );
DFFRX4TS mult_x_19_R_961 ( .D(n312), .CK(clk), .RN(n3283), .Q(n2904), .QN(
n749) );
DFFSX1TS mult_x_19_R_948 ( .D(mult_x_19_n424), .CK(clk), .SN(n3091), .Q(
n3027) );
DFFSX2TS mult_x_19_R_947 ( .D(mult_x_19_n423), .CK(clk), .SN(n3087), .Q(
n3026) );
DFFRXLTS mult_x_19_R_943 ( .D(mult_x_19_n145), .CK(clk), .RN(n3082), .Q(
n3025) );
DFFRXLTS mult_x_19_R_842_RW_0 ( .D(mult_x_19_n897), .CK(clk), .RN(n3277),
.Q(n2994) );
DFFSX4TS mult_x_19_R_930 ( .D(mult_x_19_n940), .CK(clk), .SN(n3087), .Q(
n3021) );
DFFSX4TS mult_x_19_R_928 ( .D(n2934), .CK(clk), .SN(n3278), .Q(n2915), .QN(
n608) );
DFFRXLTS mult_x_19_R_927 ( .D(mult_x_19_n614), .CK(clk), .RN(n3082), .Q(
n3019) );
DFFSX4TS mult_x_19_R_925 ( .D(mult_x_19_n637), .CK(clk), .SN(n3082), .Q(
n3017) );
DFFRX4TS mult_x_19_R_926 ( .D(mult_x_19_n626), .CK(clk), .RN(n3082), .Q(
n3018) );
DFFSX1TS mult_x_19_R_909 ( .D(n3012), .CK(clk), .SN(n3074), .Q(
mult_x_19_n1753) );
DFFRX4TS mult_x_19_R_910 ( .D(n345), .CK(clk), .RN(n3076), .Q(n2947), .QN(
n630) );
DFFSX4TS mult_x_19_R_897 ( .D(mult_x_19_n832), .CK(clk), .SN(n794), .Q(n3006) );
DFFSX1TS mult_x_19_R_703_RW_0 ( .D(mult_x_19_n146), .CK(clk), .SN(n3161),
.Q(n2968) );
DFFSX4TS mult_x_19_R_857 ( .D(mult_x_19_n651), .CK(clk), .SN(n3082), .Q(
n3000) );
DFFSX4TS mult_x_19_R_858 ( .D(mult_x_19_n649), .CK(clk), .SN(n3082), .Q(
n3001) );
DFFSX2TS mult_x_19_R_803 ( .D(n634), .CK(clk), .SN(n3089), .Q(n2981) );
DFFSX4TS mult_x_19_R_796 ( .D(n2927), .CK(clk), .SN(n3279), .Q(n2914), .QN(
n774) );
DFFSX1TS mult_x_19_R_788 ( .D(mult_x_19_n958), .CK(clk), .SN(n3091), .Q(
n2977) );
DFFSX1TS mult_x_19_R_776 ( .D(mult_x_19_n430), .CK(clk), .SN(n3089), .Q(
n2976) );
DFFSX1TS mult_x_19_R_770 ( .D(mult_x_19_n614), .CK(clk), .SN(n3081), .Q(
n2974) );
DFFSX1TS mult_x_19_R_767 ( .D(n462), .CK(clk), .SN(n3089), .Q(n2972) );
DFFSX2TS mult_x_19_R_758 ( .D(mult_x_19_n874), .CK(clk), .SN(n3085), .Q(
n2971) );
DFFSX1TS mult_x_19_R_702 ( .D(mult_x_19_n145), .CK(clk), .SN(n3091), .Q(
n2967) );
DFFSX4TS mult_x_19_R_666 ( .D(n2966), .CK(clk), .SN(n3284), .Q(mult_x_19_n52), .QN(n701) );
DFFSX2TS mult_x_19_R_662 ( .D(mult_x_19_n676), .CK(clk), .SN(n3081), .Q(
n2965) );
DFFRX4TS mult_x_19_R_1081 ( .D(n353), .CK(clk), .RN(n3075), .Q(n2895), .QN(
n3013) );
DFFSX4TS mult_x_19_R_637 ( .D(n2943), .CK(clk), .SN(n3278), .Q(n2894), .QN(
n705) );
DFFSX4TS mult_x_19_R_615 ( .D(n2961), .CK(clk), .SN(n3284), .Q(mult_x_19_n58), .QN(n561) );
DFFSX4TS mult_x_19_R_1130 ( .D(n2932), .CK(clk), .SN(n3078), .Q(n2885), .QN(
n797) );
DFFRX4TS mult_x_19_R_603 ( .D(n2960), .CK(clk), .RN(n3078), .Q(
mult_x_19_n1797) );
DFFRX4TS mult_x_19_R_1034 ( .D(n345), .CK(clk), .RN(n2575), .Q(n2948), .QN(
n702) );
DFFSX1TS mult_x_19_R_581 ( .D(mult_x_19_n108), .CK(clk), .SN(n3089), .Q(
n2956) );
DFFSX1TS mult_x_19_R_528 ( .D(n2944), .CK(clk), .SN(n3078), .Q(
mult_x_19_n1585) );
DFFSX2TS mult_x_19_R_1078 ( .D(n2939), .CK(clk), .SN(n2575), .Q(n2889) );
DFFRX4TS mult_x_19_R_1105 ( .D(mult_x_19_n689), .CK(clk), .RN(n3282), .Q(
n2908), .QN(n2950) );
DFFSX4TS R_1163 ( .D(n2937), .CK(clk), .SN(n772), .Q(mult_x_19_n28) );
DFFSX1TS mult_x_19_R_455 ( .D(mult_x_19_n135), .CK(clk), .SN(n3091), .Q(
n2936) );
DFFRX4TS mult_x_19_R_537 ( .D(mult_x_19_n579), .CK(clk), .RN(n3281), .Q(
n2906), .QN(n3095) );
DFFSX2TS mult_x_19_R_607 ( .D(n2932), .CK(clk), .SN(n3078), .Q(n2884) );
DFFSX1TS mult_x_19_R_332 ( .D(n2928), .CK(clk), .SN(n3153), .Q(
mult_x_19_n1552) );
DFFSX4TS mult_x_19_R_1134 ( .D(n2929), .CK(clk), .SN(n3078), .Q(n2887) );
DFFSX2TS mult_x_19_R_335 ( .D(n2929), .CK(clk), .SN(n3153), .Q(n2886) );
DFFRX4TS R_1161 ( .D(mult_x_19_n593), .CK(clk), .RN(n3281), .Q(n2907), .QN(
n3066) );
DFFSX4TS mult_x_19_R_325 ( .D(n2923), .CK(clk), .SN(n3285), .Q(n2901), .QN(
n688) );
DFFSX4TS mult_x_19_R_1044 ( .D(n2922), .CK(clk), .SN(n3278), .Q(n2897) );
DFFSX2TS mult_x_19_R_207 ( .D(n2923), .CK(clk), .SN(n3074), .Q(n2900) );
DFFSX2TS mult_x_19_R_197 ( .D(n2922), .CK(clk), .SN(n2575), .Q(n2896) );
DFFSX1TS mult_x_19_R_151 ( .D(mult_x_19_n166), .CK(clk), .SN(n3083), .Q(
n2921) );
DFFSX1TS mult_x_19_R_75 ( .D(n2912), .CK(clk), .SN(n3091), .QN(n421) );
DFFSX1TS mult_x_19_R_69 ( .D(n2909), .CK(clk), .SN(n3085), .Q(n2917) );
DFFRXLTS mult_x_19_R_67 ( .D(mult_x_19_n82), .CK(clk), .RN(n3086), .Q(n2916)
);
DFFSX2TS R_980 ( .D(n3342), .CK(clk), .SN(n3167), .Q(n3189) );
DFFRX4TS mult_x_19_R_1064 ( .D(mult_x_19_n960), .CK(clk), .RN(n2576), .Q(
n3056) );
DFFSX2TS mult_x_19_R_838 ( .D(mult_x_19_n994), .CK(clk), .SN(n3091), .Q(
n2992) );
DFFRX2TS mult_x_19_R_830 ( .D(mult_x_19_n744), .CK(clk), .RN(n794), .Q(n2989) );
DFFSX2TS R_979 ( .D(n3343), .CK(clk), .SN(n3165), .Q(n3190) );
DFFSX4TS mult_x_19_R_859 ( .D(mult_x_19_n638), .CK(clk), .SN(n3082), .Q(
n3002) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(clk), .RN(n3283),
.QN(n3103) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(clk), .RN(n778),
.QN(n3104) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(clk), .RN(n3282),
.QN(n3113) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(clk), .RN(n3155),
.QN(n3114) );
DFFRX4TS mult_x_19_R_902 ( .D(mult_x_19_n829), .CK(clk), .RN(n2576), .Q(
n3010) );
DFFSX4TS mult_x_19_R_898 ( .D(mult_x_19_n853), .CK(clk), .SN(n794), .Q(n3007) );
DFFSX2TS mult_x_19_R_790 ( .D(mult_x_19_n725), .CK(clk), .SN(n3083), .Q(
n2978) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n3280), .Q(Op_MY[29]) );
DFFSX4TS mult_x_19_R_1074 ( .D(mult_x_19_n453), .CK(clk), .SN(n3087), .Q(
n3059) );
DFFRX2TS mult_x_19_R_863 ( .D(mult_x_19_n662), .CK(clk), .RN(n3086), .Q(
n3003) );
DFFRX2TS mult_x_19_R_990 ( .D(mult_x_19_n786), .CK(clk), .RN(n794), .Q(n3032) );
DFFSX4TS mult_x_19_R_924 ( .D(mult_x_19_n639), .CK(clk), .SN(n3082), .Q(
n3016) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(clk), .RN(n3285),
.Q(Add_result[2]), .QN(n3147) );
DFFRHQX1TS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n3154),
.Q(Add_result[0]) );
DFFRHQX1TS R_426 ( .D(n355), .CK(clk), .RN(n772), .Q(Op_MX[11]) );
DFFRHQX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n771), .Q(zero_flag) );
DFFRHQX1TS R_330 ( .D(mult_x_19_n49), .CK(clk), .RN(n772), .Q(Op_MX[17]) );
DFFRHQX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(clk), .RN(n773),
.Q(Add_result[4]) );
DFFRHQX2TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(clk), .RN(n773),
.Q(n2878) );
DFFSX4TS mult_x_19_R_493 ( .D(n2931), .CK(clk), .SN(n771), .Q(n2903), .QN(
n2949) );
DFFRHQX4TS mult_x_19_R_520 ( .D(n2941), .CK(clk), .RN(n3285), .Q(
mult_x_19_n1801) );
DFFRHQX8TS mult_x_19_R_660_IP ( .D(n1001), .CK(clk), .RN(n773), .Q(n3102) );
DFFRHQX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(clk), .RN(n3285), .Q(Add_result[10]) );
DFFRX4TS mult_x_19_R_635 ( .D(mult_x_19_n7), .CK(clk), .RN(n771), .Q(n2902),
.QN(n2951) );
DFFSX4TS mult_x_19_R_1046 ( .D(n2924), .CK(clk), .SN(n773), .QN(n2946) );
DFFSX1TS R_744 ( .D(Sgf_operation_Result[9]), .CK(clk), .SN(n3276), .Q(n3225) );
DFFRX2TS mult_x_19_R_873 ( .D(mult_x_19_n976), .CK(clk), .RN(n3276), .Q(
n3005) );
DFFRX4TS mult_x_19_R_935 ( .D(n3023), .CK(clk), .RN(n3076), .Q(
mult_x_19_n1800) );
DFFRX4TS mult_x_19_R_636 ( .D(n2963), .CK(clk), .RN(n2575), .Q(
mult_x_19_n1805) );
DFFSX4TS mult_x_19_R_929 ( .D(mult_x_19_n923), .CK(clk), .SN(n3162), .Q(
n3020) );
DFFSX4TS mult_x_19_R_1063 ( .D(mult_x_19_n943), .CK(clk), .SN(n3161), .Q(
n3055) );
DFFSX4TS mult_x_19_R_931 ( .D(mult_x_19_n921), .CK(clk), .SN(n3162), .Q(
n3022) );
DFFRX4TS mult_x_19_R_1065 ( .D(mult_x_19_n941), .CK(clk), .RN(n2576), .Q(
n3057) );
DFFSX4TS mult_x_19_R_1073 ( .D(n3101), .CK(clk), .SN(n3087), .Q(n3058) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(clk),
.RN(n815), .Q(Sgf_normalized_result[20]), .QN(n3141) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n815), .Q(FSM_selector_C),
.QN(n998) );
DFFRX1TS mult_x_19_R_917 ( .D(mult_x_19_n466), .CK(clk), .RN(n3090), .Q(
n3015) );
DFFRX4TS R_338 ( .D(n345), .CK(clk), .RN(n3163), .Q(Op_MX[1]) );
DFFSX2TS R_32 ( .D(n3341), .CK(clk), .SN(n3160), .Q(n3259) );
DFFSX2TS mult_x_19_R_814 ( .D(n3094), .CK(clk), .SN(n3081), .Q(n2983) );
DFFRX1TS R_434 ( .D(n346), .CK(clk), .RN(n3163), .Q(Op_MX[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(clk), .RN(n3163),
.Q(Add_result[22]), .QN(n3122) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(clk), .RN(n3163),
.Q(Add_result[21]), .QN(n3134) );
DFFRX4TS Sgf_operation_finalreg_Q_reg_1_ ( .D(n3140), .CK(clk), .RN(n3080),
.Q(P_Sgf[1]) );
DFFRX1TS R_209 ( .D(mult_x_19_n43), .CK(clk), .RN(n3166), .Q(Op_MX[15]) );
DFFRX1TS R_665 ( .D(n360), .CK(clk), .RN(n3165), .Q(Op_MX[16]) );
DFFRX1TS R_344 ( .D(n363), .CK(clk), .RN(n3075), .Q(Op_MX[19]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(clk), .RN(n816),
.Q(exp_oper_result_8_), .QN(n3106) );
DFFRX4TS R_195 ( .D(mult_x_19_n7), .CK(clk), .RN(n3164), .Q(Op_MX[3]) );
DFFRX4TS Sgf_operation_finalreg_Q_reg_2_ ( .D(n240), .CK(clk), .RN(n3276),
.Q(P_Sgf[2]) );
DFFRX4TS Sgf_operation_finalreg_Q_reg_3_ ( .D(n241), .CK(clk), .RN(n3276),
.Q(P_Sgf[3]) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(clk), .RN(n778), .Q(final_result_ieee[0]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n3164), .Q(Op_MX[23]), .QN(n3136) );
DFFSX2TS mult_x_19_R_1025 ( .D(n3046), .CK(clk), .SN(n3280), .Q(n2891), .QN(
n775) );
DFFSX2TS mult_x_19_R_833 ( .D(mult_x_19_n743), .CK(clk), .SN(n3091), .Q(
n2990) );
DFFRHQX4TS mult_x_19_R_1023 ( .D(n355), .CK(clk), .RN(n405), .Q(n758) );
DFFRHQX8TS mult_x_19_R_1035 ( .D(mult_x_19_n1775), .CK(clk), .RN(n3281), .Q(
n755) );
DFFRHQX8TS mult_x_19_R_914 ( .D(mult_x_19_n611), .CK(clk), .RN(n3279), .Q(
n754) );
DFFRHQX8TS mult_x_19_R_1137 ( .D(mult_x_19_n49), .CK(clk), .RN(n3078), .Q(
n753) );
DFFSX1TS R_923 ( .D(n3310), .CK(clk), .SN(n3165), .QN(n752) );
DFFSX2TS R_922 ( .D(n3311), .CK(clk), .SN(n3165), .QN(n751) );
DFFSX1TS R_921 ( .D(n3312), .CK(clk), .SN(n3166), .QN(n750) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(clk), .RN(n815),
.QN(n3105) );
DFFSX4TS mult_x_19_R_1008 ( .D(mult_x_19_n995), .CK(clk), .SN(n3088), .Q(
n3040) );
DFFSX2TS mult_x_19_R_585 ( .D(mult_x_19_n439), .CK(clk), .SN(n3089), .QN(
n703) );
DFFSX2TS mult_x_19_R_1117 ( .D(n3068), .CK(clk), .SN(n3076), .Q(
mult_x_19_n1603), .QN(n607) );
DFFSHQX8TS mult_x_19_R_546 ( .D(n2953), .CK(clk), .SN(n3284), .Q(n744) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n3283), .Q(n736) );
DFFSHQX8TS mult_x_19_R_934 ( .D(n2935), .CK(clk), .SN(n3074), .Q(n734) );
DFFRHQX8TS mult_x_19_R_1086 ( .D(mult_x_19_n1773), .CK(clk), .RN(n3281), .Q(
n732) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(clk), .RN(n815),
.Q(n731), .QN(n3108) );
DFFRX2TS Sgf_operation_finalreg_Q_reg_6_ ( .D(n244), .CK(clk), .RN(n3080),
.Q(P_Sgf[6]) );
DFFRX2TS R_954 ( .D(n312), .CK(clk), .RN(n3283), .Q(Op_MY[0]) );
DFFRX2TS R_489 ( .D(mult_x_19_n689), .CK(clk), .RN(n3285), .Q(Op_MY[10]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n3163), .Q(Op_MX[31]) );
DFFRX2TS R_632 ( .D(n344), .CK(clk), .RN(n3163), .Q(Op_MX[0]) );
DFFRX4TS R_906 ( .D(mult_x_19_n1777), .CK(clk), .RN(n402), .Q(Op_MY[17]) );
DFFRX2TS R_602 ( .D(n362), .CK(clk), .RN(n3283), .Q(Op_MX[18]) );
DFFSX2TS mult_x_19_R_579 ( .D(mult_x_19_n110), .CK(clk), .SN(n3089), .Q(
n2955) );
DFFSX4TS mult_x_19_R_1075 ( .D(n697), .CK(clk), .SN(n3087), .Q(n3060) );
DFFSHQX8TS mult_x_19_R_1119 ( .D(n2924), .CK(clk), .SN(n3078), .Q(n695) );
DFFRHQX8TS mult_x_19_R_1107 ( .D(n357), .CK(clk), .RN(n3076), .Q(n693) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n3154), .Q(n691) );
DFFRHQX8TS mult_x_19_R_1085 ( .D(mult_x_19_n19), .CK(clk), .RN(n403), .Q(
n690) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n3076), .Q(n686) );
DFFRX1TS mult_x_19_R_1007 ( .D(mult_x_19_n418), .CK(clk), .RN(n3090), .Q(
n3039) );
DFFSHQX8TS mult_x_19_R_485 ( .D(n2938), .CK(clk), .SN(n3153), .Q(n679) );
DFFRX4TS mult_x_19_R_901 ( .D(mult_x_19_n810), .CK(clk), .RN(n3087), .Q(
n3009) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n3283), .Q(n673) );
DFFRHQX8TS mult_x_19_R_1128 ( .D(mult_x_19_n723), .CK(clk), .RN(n404), .Q(
n671) );
DFFRHQX4TS mult_x_19_R_477 ( .D(n348), .CK(clk), .RN(n2575), .Q(n670) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n3280), .Q(n668) );
DFFRHQX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(clk),
.RN(n3279), .Q(n664) );
DFFSX2TS mult_x_19_R_337 ( .D(mult_x_19_n109), .CK(clk), .SN(n3089), .Q(
n2930) );
DFFRHQX4TS mult_x_19_R_379 ( .D(n350), .CK(clk), .RN(n3076), .Q(n659) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(clk), .RN(n815),
.QN(n3107) );
DFFRHQX8TS mult_x_19_R_647 ( .D(n345), .CK(clk), .RN(n3075), .Q(n727) );
DFFRHQX8TS mult_x_19_R_1135 ( .D(mult_x_19_n633), .CK(clk), .RN(n405), .Q(
n654) );
DFFRHQX8TS mult_x_19_R_1116 ( .D(mult_x_19_n1777), .CK(clk), .RN(n3281), .Q(
n650) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n3361), .Q(n648) );
DFFSX2TS mult_x_19_R_800 ( .D(mult_x_19_n896), .CK(clk), .SN(n3084), .Q(
n2979) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n3281), .Q(n646) );
DFFSX2TS mult_x_19_R_518 ( .D(mult_x_19_n267), .CK(clk), .SN(n3083), .Q(
n2940) );
DFFRX1TS mult_x_19_R_835_RW_0 ( .D(mult_x_19_n647), .CK(clk), .RN(n3082),
.Q(n2991) );
DFFSX2TS mult_x_19_R_712 ( .D(mult_x_19_n647), .CK(clk), .SN(n3084), .Q(
n2969) );
DFFRHQX8TS mult_x_19_R_1133 ( .D(n363), .CK(clk), .RN(n3079), .Q(n645) );
DFFRHQX8TS mult_x_19_R_529 ( .D(mult_x_19_n43), .CK(clk), .RN(n3079), .Q(
n644) );
DFFRHQX8TS mult_x_19_R_1131 ( .D(mult_x_19_n1791), .CK(clk), .RN(n403), .Q(
n638) );
DFFRHQX2TS mult_x_19_R_547 ( .D(n364), .CK(clk), .RN(n3079), .Q(n635) );
DFFSHQX8TS mult_x_19_R_622 ( .D(n2925), .CK(clk), .SN(n3075), .Q(n627) );
DFFRXLTS R_311 ( .D(n250), .CK(clk), .RN(n3157), .Q(n3231) );
DFFRXLTS R_314 ( .D(n251), .CK(clk), .RN(n3157), .Q(n3230) );
DFFRXLTS R_576 ( .D(n249), .CK(clk), .RN(n3158), .Q(n3229) );
DFFRXLTS R_734 ( .D(n248), .CK(clk), .RN(n3161), .Q(n3226) );
DFFRX1TS R_728 ( .D(n246), .CK(clk), .RN(n3161), .Q(n3227) );
DFFRX1TS R_1068 ( .D(n245), .CK(clk), .RN(n3360), .Q(n3171) );
DFFRHQX2TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(clk), .RN(
n772), .Q(n2875) );
DFFSX2TS mult_x_19_R_1003 ( .D(mult_x_19_n458), .CK(clk), .SN(n3088), .Q(
n3037) );
DFFRHQX4TS mult_x_19_R_487 ( .D(n358), .CK(clk), .RN(n3075), .Q(n740) );
DFFSX4TS R_1028 ( .D(n2723), .CK(clk), .SN(n3279), .Q(n3181) );
DFFRHQX8TS mult_x_19_R_962 ( .D(n312), .CK(clk), .RN(n3155), .Q(n626) );
DFFRHQX2TS mult_x_19_R_667 ( .D(n360), .CK(clk), .RN(n3079), .Q(n625) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n3283), .Q(n623) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n3281), .Q(n621) );
DFFRHQX8TS mult_x_19_R_614 ( .D(mult_x_19_n49), .CK(clk), .RN(n3079), .Q(
n618) );
DFFRHQX4TS mult_x_19_R_623 ( .D(n349), .CK(clk), .RN(n3076), .Q(n698) );
DFFSX4TS mult_x_19_R_824 ( .D(mult_x_19_n613), .CK(clk), .SN(n3080), .Q(
n2985) );
DFFSX4TS mult_x_19_R_825 ( .D(mult_x_19_n604), .CK(clk), .SN(n3080), .Q(
n2986) );
DFFRX1TS mult_x_19_R_828_RW_0 ( .D(mult_x_19_n896), .CK(clk), .RN(n3087),
.Q(n2987) );
DFFRHQX8TS mult_x_19_R_956 ( .D(n312), .CK(clk), .RN(n3282), .Q(n612) );
DFFRHQX8TS mult_x_19_R_1059 ( .D(mult_x_19_n43), .CK(clk), .RN(n3079), .Q(
n604) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n3285), .Q(n600) );
DFFRHQX4TS mult_x_19_R_634 ( .D(n344), .CK(clk), .RN(n2575), .Q(n599) );
DFFSX2TS mult_x_19_R_593 ( .D(n2957), .CK(clk), .SN(n3074), .Q(
mult_x_19_n1749) );
DFFSX2TS R_1156 ( .D(n950), .CK(clk), .SN(n3083), .Q(n598) );
DFFRX2TS R_1157 ( .D(n2105), .CK(clk), .RN(n3276), .Q(n597) );
DFFSX2TS R_1162 ( .D(n596), .CK(clk), .SN(n404), .Q(n1324) );
DFFRX2TS R_1160 ( .D(n349), .CK(clk), .RN(n402), .Q(mult_x_19_n1697) );
DFFSX4TS mult_x_19_R_587 ( .D(n2943), .CK(clk), .SN(n3282), .Q(n2893), .QN(
n593) );
DFFSX4TS mult_x_19_R_1024 ( .D(n3046), .CK(clk), .SN(n3164), .Q(n2892), .QN(
n706) );
DFFSX2TS R_1183 ( .D(n3274), .CK(clk), .SN(n3277), .Q(n589), .QN(n420) );
DFFSX4TS R_1184 ( .D(n424), .CK(clk), .SN(n3088), .Q(n588) );
DFFSX2TS R_1185 ( .D(n425), .CK(clk), .SN(n3162), .Q(n587) );
DFFSX2TS R_1187 ( .D(n424), .CK(clk), .SN(n3160), .Q(n586), .QN(n418) );
DFFSX2TS R_1188 ( .D(n425), .CK(clk), .SN(n3156), .Q(n585) );
DFFSX2TS R_1189 ( .D(mult_x_19_n524), .CK(clk), .SN(n3080), .Q(n584) );
DFFSX2TS R_1190 ( .D(mult_x_19_n211), .CK(clk), .SN(n3085), .Q(n583) );
DFFSX2TS R_1191 ( .D(mult_x_19_n474), .CK(clk), .SN(n3088), .Q(n582) );
DFFSX2TS R_1192 ( .D(n3092), .CK(clk), .SN(n3081), .Q(n581) );
DFFSX2TS R_1194 ( .D(mult_x_19_n708), .CK(clk), .SN(n3085), .Q(n579) );
DFFSX2TS R_1195 ( .D(mult_x_19_n851), .CK(clk), .SN(n794), .Q(n578) );
DFFSX2TS R_1197 ( .D(mult_x_19_n726), .CK(clk), .SN(n3276), .Q(n576) );
DFFSX2TS R_1198 ( .D(mult_x_19_n197), .CK(clk), .SN(n3360), .Q(n575) );
DFFSX2TS R_1199 ( .D(mult_x_19_n959), .CK(clk), .SN(n3277), .Q(n574) );
DFFSX4TS R_1200 ( .D(mult_x_19_n977), .CK(clk), .SN(n3091), .Q(n573) );
DFFSX2TS R_1202 ( .D(mult_x_19_n181), .CK(clk), .SN(n3081), .Q(n571) );
DFFSX2TS R_1203 ( .D(n3096), .CK(clk), .SN(n3080), .Q(n570) );
DFFSX2TS R_1204 ( .D(mult_x_19_n875), .CK(clk), .SN(n2576), .Q(n569) );
DFFSX2TS R_1205 ( .D(mult_x_19_n691), .CK(clk), .SN(n3084), .Q(n568) );
DFFSX2TS R_1206 ( .D(mult_x_19_n418), .CK(clk), .SN(n3085), .Q(n567), .QN(
n566) );
DFFSX2TS R_1207 ( .D(mult_x_19_n165), .CK(clk), .SN(n3081), .Q(n565) );
DFFSX4TS R_1208 ( .D(n3356), .CK(clk), .SN(n778), .Q(n564) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n3282), .Q(n563) );
DFFSX2TS R_968 ( .D(n3314), .CK(clk), .SN(n3166), .Q(n3201) );
DFFRX1TS mult_x_19_R_805_RW_0 ( .D(mult_x_19_n874), .CK(clk), .RN(n2576),
.Q(n2982) );
DFFSX1TS R_1196 ( .D(mult_x_19_n852), .CK(clk), .SN(n794), .Q(n577) );
DFFSX4TS R_1158 ( .D(n2962), .CK(clk), .SN(n3074), .Q(mult_x_19_n4), .QN(
n3097) );
DFFSX4TS R_1164 ( .D(n595), .CK(clk), .SN(n3075), .Q(n1091) );
DFFSX2TS mult_x_19_R_1132 ( .D(n3070), .CK(clk), .SN(n3154), .Q(
mult_x_19_n1542) );
DFFRX4TS mult_x_19_R_899_RW_0 ( .D(mult_x_19_n830), .CK(clk), .RN(n3087),
.Q(n3008) );
DFFSX2TS mult_x_19_R_1103 ( .D(n3065), .CK(clk), .SN(n3075), .Q(
mult_x_19_n1617) );
DFFSX2TS mult_x_19_R_1053 ( .D(n3052), .CK(clk), .SN(n3167), .Q(
mult_x_19_n1678) );
DFFSX2TS R_978 ( .D(n3344), .CK(clk), .SN(n3279), .Q(n3191) );
DFFSX1TS R_1049 ( .D(n3358), .CK(clk), .SN(n816), .Q(n3176) );
DFFRX1TS R_484 ( .D(n358), .CK(clk), .RN(n3164), .Q(Op_MX[14]) );
DFFSX1TS mult_x_19_R_840 ( .D(mult_x_19_n114), .CK(clk), .SN(n3089), .Q(
n2993) );
DFFSX1TS mult_x_19_R_1004 ( .D(mult_x_19_n459), .CK(clk), .SN(n3088), .Q(
n3038) );
DFFRX1TS mult_x_19_R_1011 ( .D(mult_x_19_n743), .CK(clk), .RN(n3086), .Q(
n3042) );
DFFRHQX4TS mult_x_19_R_202 ( .D(n365), .CK(clk), .RN(n3079), .Q(n759) );
DFFSX4TS mult_x_19_R_1002 ( .D(n614), .CK(clk), .SN(n3088), .Q(n3036) );
DFFSX4TS R_1159 ( .D(n2962), .CK(clk), .SN(n3074), .Q(n862), .QN(n552) );
DFFRX4TS mult_x_19_R_953 ( .D(mult_x_19_n692), .CK(clk), .RN(n3086), .Q(
n3028) );
DFFRX4TS mult_x_19_R_903 ( .D(mult_x_19_n808), .CK(clk), .RN(n3158), .Q(
n3011) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(clk),
.RN(n817), .Q(Sgf_normalized_result[0]) );
DFFSX2TS R_1041 ( .D(n3349), .CK(clk), .SN(n3153), .Q(n3178) );
DFFSX2TS mult_x_19_R_1009 ( .D(mult_x_19_n1010), .CK(clk), .SN(n3088), .Q(
n3041) );
DFFRHQX4TS mult_x_19_R_664 ( .D(mult_x_19_n43), .CK(clk), .RN(n3079), .Q(
n684) );
DFFSHQX4TS mult_x_19_R_1080 ( .D(n3062), .CK(clk), .SN(n3284), .Q(n689) );
DFFSX1TS mult_x_19_R_936 ( .D(mult_x_19_n662), .CK(clk), .SN(n3277), .Q(
n3024) );
DFFSX2TS R_1201 ( .D(mult_x_19_n675), .CK(clk), .SN(n3277), .Q(n572) );
DFFRX2TS mult_x_19_R_989 ( .D(mult_x_19_n807), .CK(clk), .RN(n794), .Q(n3031) );
DFFRHQX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n771), .Q(Op_MY[26]) );
DFFSRHQX2TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk),
.SN(1'b1), .RN(n772), .Q(Op_MY[23]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n3280), .Q(Op_MY[24]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n3280), .Q(Op_MY[25]) );
DFFSX1TS mult_x_19_R_816_RW_0 ( .D(mult_x_19_n897), .CK(clk), .SN(n3080),
.Q(n2984) );
DFFSX2TS R_1193 ( .D(mult_x_19_n707), .CK(clk), .SN(n3084), .Q(n580) );
DFFSHQX8TS mult_x_19_R_987 ( .D(n2933), .CK(clk), .SN(n3278), .Q(n633) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n3280), .Q(Op_MY[27]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n3280), .Q(Op_MY[28]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n3154), .Q(Op_MX[26]), .QN(n996) );
DFFRX1TS mult_x_19_R_856 ( .D(mult_x_19_n471), .CK(clk), .RN(n3090), .Q(
n2999) );
DFFRX2TS mult_x_19_R_855 ( .D(mult_x_19_n555), .CK(clk), .RN(n3090), .Q(
n2998) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n3155), .Q(Op_MX[28]), .QN(n3115) );
DFFSX2TS mult_x_19_R_1031 ( .D(n3047), .CK(clk), .SN(n3153), .Q(
mult_x_19_n1677) );
DFFSX2TS mult_x_19_R_538 ( .D(n2945), .CK(clk), .SN(n3285), .Q(n419), .QN(
n704) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n3154), .Q(Op_MX[27]), .QN(n3116) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n3155), .Q(Op_MX[29]), .QN(n3135) );
DFFSRHQX2TS mult_x_19_R_1020_IP ( .D(n3046), .CK(clk), .SN(n772), .RN(1'b1),
.Q(n2952) );
DFFRX1TS mult_x_19_R_1129 ( .D(n3069), .CK(clk), .RN(n3075), .Q(n602), .QN(
n700) );
DFFRX1TS mult_x_19_R_596 ( .D(mult_x_19_n113), .CK(clk), .RN(n3090), .Q(
n2958) );
DFFSX2TS mult_x_19_R_1139 ( .D(mult_x_19_n115), .CK(clk), .SN(n3088), .Q(
n3073) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n3280), .Q(Op_MY[30]), .QN(n3137) );
DFFRXLTS mult_x_19_R_768 ( .D(mult_x_19_n451), .CK(clk), .RN(n3090), .Q(
n2973) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_5_ ( .D(n243), .CK(clk), .RN(n3080),
.Q(P_Sgf[5]) );
DFFRX1TS mult_x_19_R_916 ( .D(mult_x_19_n465), .CK(clk), .RN(n3090), .Q(
n3014) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n3155), .Q(Op_MX[30]) );
DFFSX1TS mult_x_19_R_802 ( .D(n3099), .CK(clk), .SN(n3089), .Q(n2980) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_4_ ( .D(n242), .CK(clk), .RN(n3083),
.Q(P_Sgf[4]) );
DFFSX2TS R_1040 ( .D(n3350), .CK(clk), .SN(n816), .Q(n3179) );
DFFSRHQX2TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk),
.SN(1'b1), .RN(n773), .Q(Op_MY[31]) );
DFFRXLTS mult_x_19_R_598 ( .D(mult_x_19_n112), .CK(clk), .RN(n3090), .Q(
n2959) );
DFFRXLTS mult_x_19_R_565 ( .D(mult_x_19_n111), .CK(clk), .RN(n3090), .Q(
n2954) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(clk),
.RN(n788), .Q(Sgf_normalized_result[2]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(clk),
.RN(n3284), .Q(Sgf_normalized_result[6]), .QN(n3148) );
DFFRHQX4TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(clk),
.RN(n3154), .Q(n640) );
DFFSRHQX2TS mult_x_19_R_1082_IP ( .D(n2879), .CK(clk), .SN(n3154), .RN(1'b1),
.Q(n3051) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(n3083),
.Q(P_Sgf[0]) );
DFFSRHQX2TS R_327 ( .D(mult_x_19_n593), .CK(clk), .SN(1'b1), .RN(n3154), .Q(
Op_MY[18]) );
DFFSX1TS mult_x_19_R_73 ( .D(n2911), .CK(clk), .SN(n3081), .Q(n2919) );
DFFRX1TS R_1042 ( .D(mult_x_19_n723), .CK(clk), .RN(n3283), .Q(Op_MY[8]) );
DFFRX1TS R_1102 ( .D(mult_x_19_n1791), .CK(clk), .RN(n778), .Q(n3112), .QN(
n3149) );
DFFRX1TS R_475 ( .D(n348), .CK(clk), .RN(n3164), .Q(Op_MX[4]) );
DFFSX1TS R_39 ( .D(n3275), .CK(clk), .SN(n3156), .Q(n3254) );
DFFSRHQX2TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(clk), .SN(1'b1),
.RN(n771), .Q(Add_result[1]) );
DFFSX1TS R_56 ( .D(n3345), .CK(clk), .SN(n3160), .Q(n3247) );
DFFSX2TS R_41 ( .D(n3352), .CK(clk), .SN(n3156), .Q(n3253) );
DFFSX1TS mult_x_19_R_71 ( .D(n2910), .CK(clk), .SN(n3081), .Q(n2918) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(clk), .RN(n771),
.Q(Add_result[23]) );
DFFSX2TS R_14 ( .D(n3333), .CK(clk), .SN(n3160), .Q(n3267) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(clk), .RN(n3279),
.Q(Add_result[16]), .QN(n3127) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(clk), .RN(n3284),
.Q(Add_result[11]), .QN(n3132) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(clk), .RN(n3284),
.Q(Add_result[17]), .QN(n3126) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(clk), .RN(n3284),
.Q(Add_result[14]), .QN(n3129) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(clk), .RN(n3164),
.Q(Add_result[15]), .QN(n3128) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(clk), .RN(n3279),
.Q(Add_result[13]), .QN(n3130) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(clk), .RN(n3164),
.Q(Add_result[12]), .QN(n3131) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(clk), .RN(n3282), .Q(final_result_ieee[7]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(clk), .RN(n3282), .Q(final_result_ieee[5]) );
DFFRX1TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(clk), .RN(n778), .Q(final_result_ieee[2]) );
INVX2TS U406 ( .A(mult_x_19_n197), .Y(mult_x_19_n525) );
INVX2TS U407 ( .A(n2532), .Y(mult_x_19_n524) );
CLKMX2X2TS U408 ( .A(Data_MY[5]), .B(n429), .S0(n2795), .Y(n317) );
OAI21X2TS U409 ( .A0(mult_x_19_n179), .A1(n2538), .B0(n2537), .Y(
mult_x_19_n166) );
CLKMX2X2TS U410 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n2795), .Y(n336) );
NAND2X2TS U411 ( .A(mult_x_19_n613), .B(mult_x_19_n604), .Y(mult_x_19_n211)
);
CLKINVX1TS U412 ( .A(n401), .Y(n404) );
CLKMX2X2TS U413 ( .A(n2803), .B(P_Sgf[0]), .S0(n424), .Y(n238) );
AND2X4TS U414 ( .A(n2257), .B(n2287), .Y(n3096) );
CLKINVX6TS U415 ( .A(n2282), .Y(mult_x_19_n471) );
BUFX3TS U416 ( .A(n3276), .Y(n3087) );
NAND2X4TS U417 ( .A(n936), .B(n933), .Y(mult_x_19_n474) );
CLKBUFX3TS U418 ( .A(n3163), .Y(n3074) );
CLKINVX1TS U419 ( .A(n401), .Y(n402) );
ADDFHX2TS U420 ( .A(n2464), .B(n2463), .CI(n2462), .CO(mult_x_19_n807), .S(
mult_x_19_n808) );
ADDFHX2TS U421 ( .A(n2167), .B(n2166), .CI(n2165), .CO(mult_x_19_n707), .S(
mult_x_19_n708) );
ADDFHX2TS U422 ( .A(n2513), .B(n2512), .CI(n2511), .CO(mult_x_19_n829), .S(
mult_x_19_n830) );
NOR2X6TS U423 ( .A(n2534), .B(n2533), .Y(mult_x_19_n197) );
INVX2TS U424 ( .A(n2835), .Y(n2852) );
NAND2X1TS U425 ( .A(n776), .B(P_Sgf[6]), .Y(n926) );
NOR2X4TS U426 ( .A(n2535), .B(n2536), .Y(n2532) );
XOR2X2TS U427 ( .A(n2299), .B(n2298), .Y(n829) );
INVX3TS U428 ( .A(n2835), .Y(n2849) );
BUFX3TS U429 ( .A(n3279), .Y(n3163) );
BUFX3TS U430 ( .A(n2835), .Y(n2834) );
INVX4TS U431 ( .A(n425), .Y(n424) );
NOR2X6TS U432 ( .A(n935), .B(n934), .Y(n933) );
ADDFHX2TS U433 ( .A(n2510), .B(n2509), .CI(n2508), .CO(n2511), .S(n1902) );
BUFX4TS U434 ( .A(n2723), .Y(n2757) );
ADDFHX2TS U435 ( .A(n2507), .B(n2506), .CI(n2505), .CO(n2464), .S(n2512) );
XOR2X2TS U436 ( .A(n2296), .B(n2295), .Y(n875) );
NAND2X2TS U437 ( .A(n514), .B(n513), .Y(n2557) );
ADDFHX2TS U438 ( .A(n2522), .B(n2521), .CI(n2520), .CO(n2523), .S(n2432) );
ADDFHX2TS U439 ( .A(n2429), .B(n2428), .CI(n2427), .CO(mult_x_19_n960), .S(
n2430) );
NAND2X2TS U440 ( .A(n1981), .B(n1966), .Y(n1967) );
XOR2X1TS U441 ( .A(n2354), .B(n2353), .Y(n858) );
CLKMX2X2TS U442 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n2791), .Y(
mult_x_19_n579) );
OAI22X1TS U443 ( .A0(n427), .A1(zero_flag), .B0(n1938), .B1(
FS_Module_state_reg[2]), .Y(n526) );
NOR2X4TS U444 ( .A(n2640), .B(n853), .Y(n527) );
INVX2TS U445 ( .A(n3077), .Y(n401) );
NAND2X1TS U446 ( .A(n1524), .B(n1525), .Y(n1526) );
AOI2BB2X2TS U447 ( .B0(n1483), .B1(n262), .A0N(n805), .A1N(n2787), .Y(n2613)
);
BUFX4TS U448 ( .A(n2873), .Y(n796) );
INVX3TS U449 ( .A(mult_x_19_n145), .Y(n2541) );
INVX16TS U450 ( .A(n461), .Y(n3101) );
AND2X6TS U451 ( .A(n1957), .B(n1956), .Y(n634) );
AND2X6TS U452 ( .A(n1971), .B(n1970), .Y(n697) );
INVX2TS U453 ( .A(n1523), .Y(n2283) );
NOR2X4TS U454 ( .A(n2266), .B(n1981), .Y(n935) );
CLKMX2X4TS U455 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n2568), .Y(n365) );
NOR2X4TS U456 ( .A(n2191), .B(n2190), .Y(n2281) );
NAND2X4TS U457 ( .A(n1172), .B(n1171), .Y(n2436) );
OAI21X2TS U458 ( .A0(n2378), .A1(n2379), .B0(n2377), .Y(n943) );
NAND2X1TS U459 ( .A(n2735), .B(n2725), .Y(n2726) );
NAND2X4TS U460 ( .A(n2213), .B(n1362), .Y(n2723) );
INVX4TS U461 ( .A(n2783), .Y(n806) );
NAND2X4TS U462 ( .A(n494), .B(n830), .Y(n2105) );
BUFX3TS U463 ( .A(n3360), .Y(n3276) );
CLKMX2X4TS U464 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n2263), .Y(n352) );
NAND2X1TS U465 ( .A(n2552), .B(n518), .Y(n513) );
INVX3TS U466 ( .A(n2783), .Y(n807) );
CLKINVX6TS U467 ( .A(n2267), .Y(n934) );
ADDFHX2TS U468 ( .A(n2135), .B(n2134), .CI(n2133), .CO(n2167), .S(n2136) );
INVX6TS U469 ( .A(n425), .Y(n2873) );
OAI2BB1X1TS U470 ( .A0N(n516), .A1N(n515), .B0(n2551), .Y(n514) );
CLKINVX6TS U471 ( .A(n1669), .Y(n2700) );
AO22X2TS U472 ( .A0(n1002), .A1(n711), .B0(n647), .B1(n710), .Y(n2555) );
NOR2BX1TS U473 ( .AN(n2259), .B(FS_Module_state_reg[1]), .Y(n964) );
CLKBUFX2TS U474 ( .A(n2575), .Y(n3077) );
CLKINVX6TS U475 ( .A(n1669), .Y(n2784) );
INVX2TS U476 ( .A(n1647), .Y(n2701) );
BUFX3TS U477 ( .A(n1899), .Y(n658) );
INVX2TS U478 ( .A(n2605), .Y(n2599) );
NAND2BXLTS U479 ( .AN(n647), .B(n713), .Y(n711) );
XOR2X2TS U480 ( .A(n2551), .B(n517), .Y(n2405) );
AND2X6TS U481 ( .A(n524), .B(n1524), .Y(n938) );
NAND2X6TS U482 ( .A(n1098), .B(n1097), .Y(n1981) );
NAND2XLTS U483 ( .A(n2659), .B(n2662), .Y(n1630) );
NAND2X2TS U484 ( .A(n2299), .B(n2298), .Y(n830) );
NAND2XLTS U485 ( .A(n2646), .B(n2645), .Y(n2647) );
ADDFHX2TS U486 ( .A(n1840), .B(n1839), .CI(n1838), .CO(n2133), .S(n2010) );
NAND2X2TS U487 ( .A(n1400), .B(n427), .Y(n1401) );
NAND2X2TS U488 ( .A(n1391), .B(n427), .Y(n1392) );
ADDFHX2TS U489 ( .A(n1560), .B(n1559), .CI(n1558), .CO(n2404), .S(n1578) );
NOR2X2TS U490 ( .A(n2741), .B(n3141), .Y(n2742) );
NAND2BX2TS U491 ( .AN(n2603), .B(n1444), .Y(n1445) );
ADDFHX2TS U492 ( .A(n2452), .B(n2451), .CI(n2450), .CO(n2506), .S(n2503) );
ADDFHX2TS U493 ( .A(n2130), .B(n2129), .CI(n2128), .CO(n2540), .S(n1615) );
OR2X6TS U494 ( .A(n2186), .B(n2187), .Y(n823) );
OAI21X2TS U495 ( .A0(n2112), .A1(n2108), .B0(n2109), .Y(n1012) );
OAI2BB1X2TS U496 ( .A0N(n870), .A1N(n1868), .B0(n903), .Y(n2451) );
NAND2BX1TS U497 ( .AN(n1892), .B(n914), .Y(n913) );
NAND2X1TS U498 ( .A(n1458), .B(n1457), .Y(n1470) );
NOR2X6TS U499 ( .A(n1486), .B(n793), .Y(n1483) );
NAND2X6TS U500 ( .A(n1523), .B(n1525), .Y(n524) );
OAI21X1TS U501 ( .A0(n947), .A1(n1865), .B0(n1864), .Y(n948) );
INVX2TS U502 ( .A(n2252), .Y(n1916) );
XNOR2X2TS U503 ( .A(n1469), .B(n1407), .Y(n1408) );
ADDFHX2TS U504 ( .A(n1601), .B(n1600), .CI(n1599), .CO(n2529), .S(n2527) );
NOR2X2TS U505 ( .A(n1449), .B(n1452), .Y(n1454) );
NAND2X4TS U506 ( .A(n1079), .B(n1080), .Y(n1524) );
CMPR32X2TS U507 ( .A(n2476), .B(n786), .C(n2475), .CO(n2489), .S(n2548) );
NAND2X2TS U508 ( .A(n2248), .B(n2251), .Y(n2254) );
OAI22X2TS U509 ( .A0(n407), .A1(n1540), .B0(n2469), .B1(n2468), .Y(n2543) );
ADDFHX2TS U510 ( .A(n1587), .B(n1586), .CI(n1585), .CO(n1580), .S(n2175) );
ADDFHX2TS U511 ( .A(n495), .B(n1551), .CI(n1550), .CO(n1559), .S(n1581) );
NAND2X2TS U512 ( .A(n2661), .B(n1531), .Y(n1533) );
OAI22X2TS U513 ( .A0(n676), .A1(mult_x_19_n1552), .B0(n1541), .B1(n2471),
.Y(n1566) );
OR2X6TS U514 ( .A(n1078), .B(n1077), .Y(n2284) );
AO21X2TS U515 ( .A0(n2041), .A1(n2479), .B0(n2884), .Y(n1613) );
INVX2TS U516 ( .A(n957), .Y(n955) );
AO21X2TS U517 ( .A0(n760), .A1(n1674), .B0(n2888), .Y(n1507) );
OAI22X1TS U518 ( .A0(n551), .A1(n863), .B0(n695), .B1(n787), .Y(n2132) );
INVX6TS U519 ( .A(n2788), .Y(n427) );
NAND3X2TS U520 ( .A(n3185), .B(n3184), .C(n3183), .Y(n2854) );
OAI22X1TS U521 ( .A0(n676), .A1(n1552), .B0(mult_x_19_n1552), .B1(n2322),
.Y(n1553) );
CLKBUFX2TS U522 ( .A(n2950), .Y(n495) );
BUFX4TS U523 ( .A(n1866), .Y(n947) );
INVX1TS U524 ( .A(n1389), .Y(n1383) );
CLKXOR2X2TS U525 ( .A(n988), .B(n525), .Y(n871) );
AO21XLTS U526 ( .A0(n678), .A1(n799), .B0(n2886), .Y(n1594) );
ADDFHX2TS U527 ( .A(n2181), .B(n2179), .CI(n2180), .CO(n1591), .S(n2270) );
CLKBUFX2TS U528 ( .A(FSM_selector_C), .Y(n793) );
INVX3TS U529 ( .A(n1052), .Y(n488) );
OAI22X2TS U530 ( .A0(n784), .A1(n2480), .B0(n1505), .B1(n2479), .Y(n2466) );
OAI21X2TS U531 ( .A0(n1249), .A1(n1451), .B0(n1248), .Y(n1250) );
NAND2BX1TS U532 ( .AN(n723), .B(n2146), .Y(n719) );
NOR2X4TS U533 ( .A(n1940), .B(n1529), .Y(n1531) );
INVX2TS U534 ( .A(n606), .Y(n1782) );
CLKXOR2X2TS U535 ( .A(n1439), .B(n1438), .Y(n1440) );
OAI22X2TS U536 ( .A0(n1504), .A1(n509), .B0(n970), .B1(n1502), .Y(n1512) );
CLKXOR2X2TS U537 ( .A(n1415), .B(n1414), .Y(n1419) );
NAND2BX2TS U538 ( .AN(n1597), .B(n974), .Y(n973) );
INVX2TS U539 ( .A(n723), .Y(n721) );
AO22X2TS U540 ( .A0(n2474), .A1(n622), .B0(n2946), .B1(n2238), .Y(n2478) );
OAI22X1TS U541 ( .A0(n677), .A1(n1884), .B0(n2471), .B1(n2886), .Y(n1515) );
BUFX3TS U542 ( .A(n887), .Y(n844) );
OAI22X1TS U543 ( .A0(n1796), .A1(n1322), .B0(n1302), .B1(n757), .Y(n1334) );
INVX2TS U544 ( .A(n775), .Y(n498) );
OA21X2TS U545 ( .A0(n558), .A1(n1939), .B0(n1942), .Y(n1528) );
OAI2BB1X2TS U546 ( .A0N(n1291), .A1N(n941), .B0(n940), .Y(n1879) );
XNOR2X2TS U547 ( .A(n791), .B(n879), .Y(n1504) );
INVX2TS U548 ( .A(n1634), .Y(n1660) );
NAND2X2TS U549 ( .A(n2258), .B(n1481), .Y(n1482) );
AOI21X2TS U550 ( .A0(n2121), .A1(n2003), .B0(n566), .Y(n1859) );
NOR2X2TS U551 ( .A(n1940), .B(n1494), .Y(n1496) );
NOR2X6TS U552 ( .A(n1274), .B(FS_Module_state_reg[1]), .Y(n2788) );
INVX2TS U553 ( .A(n1429), .Y(n1426) );
NAND2X4TS U554 ( .A(n559), .B(n1848), .Y(n1529) );
NOR2X4TS U555 ( .A(n1269), .B(n699), .Y(n1456) );
NAND2X1TS U556 ( .A(n1999), .B(n2116), .Y(n2000) );
INVX3TS U557 ( .A(n636), .Y(n1450) );
NAND2BX2TS U558 ( .AN(n2484), .B(n974), .Y(n925) );
MX2X4TS U559 ( .A(n2127), .B(n3237), .S0(n589), .Y(n259) );
OAI21X1TS U560 ( .A0(n1948), .A1(n1494), .B0(n2654), .Y(n1495) );
ADDFHX2TS U561 ( .A(n1160), .B(n1159), .CI(n1158), .CO(n1914), .S(n1168) );
INVX6TS U562 ( .A(n1619), .Y(n2661) );
NAND2X2TS U563 ( .A(n1394), .B(n1464), .Y(n1398) );
ADDFHX2TS U564 ( .A(n2102), .B(n2103), .CI(n2104), .CO(n2293), .S(n2294) );
NAND2X2TS U565 ( .A(n1382), .B(n1381), .Y(n1389) );
XNOR2X2TS U566 ( .A(n883), .B(n755), .Y(n1541) );
OAI22X2TS U567 ( .A0(n667), .A1(n1774), .B0(n1779), .B1(n744), .Y(n1776) );
NAND2BX2TS U568 ( .AN(n2483), .B(n972), .Y(n971) );
XNOR2X2TS U569 ( .A(n883), .B(n650), .Y(n1552) );
XNOR2X2TS U570 ( .A(n792), .B(n884), .Y(n1543) );
ADDFHX2TS U571 ( .A(n2302), .B(n2301), .CI(n2300), .CO(n2344), .S(n2349) );
ADDFX2TS U572 ( .A(n781), .B(n884), .CI(n1503), .CO(n1517), .S(n1511) );
NAND2X2TS U573 ( .A(n699), .B(n1269), .Y(n1457) );
NAND2X2TS U574 ( .A(Sgf_normalized_result[20]), .B(n2856), .Y(n2753) );
INVX2TS U575 ( .A(n2184), .Y(n958) );
INVX2TS U576 ( .A(n667), .Y(n974) );
NOR2BX2TS U577 ( .AN(n789), .B(n2307), .Y(n1129) );
INVX1TS U578 ( .A(n1855), .Y(n1857) );
INVX2TS U579 ( .A(n558), .Y(n1945) );
INVX2TS U580 ( .A(n683), .Y(n1338) );
NOR2X6TS U581 ( .A(n1051), .B(n1050), .Y(n2607) );
INVX2TS U582 ( .A(n622), .Y(n781) );
AND2X4TS U583 ( .A(n616), .B(n2655), .Y(n559) );
INVX4TS U584 ( .A(n2650), .Y(n1948) );
OAI22X1TS U585 ( .A0(n676), .A1(n1359), .B0(n1353), .B1(n2471), .Y(n2341) );
NAND2X4TS U586 ( .A(n1047), .B(n1046), .Y(n2863) );
NOR2X4TS U587 ( .A(n1049), .B(n1048), .Y(n2605) );
OAI21X2TS U588 ( .A0(n2198), .A1(n2972), .B0(n2973), .Y(n2195) );
XNOR2X2TS U589 ( .A(n2013), .B(n650), .Y(n2075) );
NOR2X4TS U590 ( .A(n916), .B(n915), .Y(n914) );
NAND3X4TS U591 ( .A(n3197), .B(n3196), .C(n3195), .Y(n2842) );
NAND3X4TS U592 ( .A(n3191), .B(n3190), .C(n3189), .Y(n2838) );
OAI21X2TS U593 ( .A0(n2221), .A1(n714), .B0(n716), .Y(n1787) );
XNOR2X2TS U594 ( .A(n604), .B(n638), .Y(n2228) );
XNOR2X2TS U595 ( .A(n969), .B(n863), .Y(n1597) );
NAND2X2TS U596 ( .A(n1266), .B(n1265), .Y(n1381) );
INVX2TS U597 ( .A(n1921), .Y(n1922) );
XNOR2X2TS U598 ( .A(n791), .B(n650), .Y(n2483) );
XOR2X2TS U599 ( .A(n828), .B(n737), .Y(n836) );
XNOR2X2TS U600 ( .A(n2241), .B(n686), .Y(n981) );
XNOR2X2TS U601 ( .A(n883), .B(n668), .Y(n1506) );
ADDFHX2TS U602 ( .A(n1065), .B(n1064), .CI(n1063), .CO(n1095), .S(n1073) );
NAND2X4TS U603 ( .A(n1364), .B(n2584), .Y(n1274) );
BUFX8TS U604 ( .A(n763), .Y(n407) );
OAI22X2TS U605 ( .A0(n803), .A1(n1784), .B0(n1821), .B1(n2314), .Y(n1837) );
XNOR2X2TS U606 ( .A(n792), .B(n881), .Y(n2484) );
INVX2TS U607 ( .A(n1209), .Y(n2654) );
NOR4X1TS U608 ( .A(P_Sgf[4]), .B(P_Sgf[3]), .C(P_Sgf[2]), .D(P_Sgf[1]), .Y(
n2209) );
OAI22X2TS U609 ( .A0(n523), .A1(n900), .B0(n553), .B1(n1102), .Y(n1143) );
INVX4TS U610 ( .A(n2006), .Y(n2198) );
NOR2X1TS U611 ( .A(n2327), .B(mult_x_19_n1677), .Y(n915) );
CLKBUFX2TS U612 ( .A(n2013), .Y(n445) );
INVX1TS U613 ( .A(n2659), .Y(n2663) );
NOR2X4TS U614 ( .A(n1266), .B(n1265), .Y(n1380) );
OR2X2TS U615 ( .A(n2223), .B(mult_x_19_n1656), .Y(n653) );
INVX2TS U616 ( .A(n1433), .Y(n1435) );
OR2X4TS U617 ( .A(n804), .B(mult_x_19_n1656), .Y(n609) );
BUFX3TS U618 ( .A(n2905), .Y(n435) );
OAI22X2TS U619 ( .A0(n2318), .A1(n2052), .B0(n756), .B1(n2900), .Y(n2085) );
OR2X4TS U620 ( .A(n1039), .B(n1038), .Y(n2779) );
XNOR2X2TS U621 ( .A(n2052), .B(n2319), .Y(n1105) );
INVX6TS U622 ( .A(n1481), .Y(n1364) );
NOR2BX2TS U623 ( .AN(n612), .B(mult_x_19_n52), .Y(n1755) );
XNOR2X2TS U624 ( .A(n1090), .B(n762), .Y(n1102) );
INVX2TS U625 ( .A(n1849), .Y(n1942) );
CLKAND2X2TS U626 ( .A(n789), .B(n592), .Y(n1089) );
INVX2TS U627 ( .A(n621), .Y(n622) );
OAI22X2TS U628 ( .A0(n1762), .A1(n1058), .B0(n1083), .B1(n756), .Y(n1086) );
INVX4TS U629 ( .A(n1848), .Y(n1939) );
NOR2X4TS U630 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n2264) );
XNOR2X2TS U631 ( .A(n881), .B(n644), .Y(n1812) );
NAND2BX2TS U632 ( .AN(n452), .B(n2387), .Y(n448) );
CMPR22X2TS U633 ( .A(n1294), .B(n1295), .CO(n1880), .S(n1285) );
CMPR22X2TS U634 ( .A(n1701), .B(n1700), .CO(n1752), .S(n1698) );
XNOR2X2TS U635 ( .A(n753), .B(n736), .Y(n2220) );
NAND2X6TS U636 ( .A(n703), .B(n2006), .Y(n963) );
INVX12TS U637 ( .A(n1938), .Y(n2584) );
OAI22X2TS U638 ( .A0(n406), .A1(n917), .B0(n556), .B1(n1686), .Y(n1720) );
OAI22X2TS U639 ( .A0(n1705), .A1(n548), .B0(n556), .B1(n1760), .Y(n1753) );
OAI21X2TS U640 ( .A0(n406), .A1(mult_x_19_n1751), .B0(n549), .Y(n2303) );
ADDFHX2TS U641 ( .A(n2091), .B(n2092), .CI(n2090), .CO(n2446), .S(n2453) );
ADDFHX2TS U642 ( .A(n2095), .B(n2094), .CI(n2093), .CO(n2445), .S(n2454) );
OAI22X2TS U643 ( .A0(n841), .A1(n1060), .B0(n1082), .B1(n2327), .Y(n1085) );
OAI22X2TS U644 ( .A0(n406), .A1(n942), .B0(n900), .B1(n556), .Y(n1087) );
NAND2X6TS U645 ( .A(n1049), .B(n1048), .Y(n2604) );
OR2X6TS U646 ( .A(n3119), .B(FS_Module_state_reg[3]), .Y(n1481) );
INVX2TS U647 ( .A(n1050), .Y(n485) );
BUFX4TS U648 ( .A(n684), .Y(n433) );
BUFX4TS U649 ( .A(n744), .Y(n2151) );
NAND2X2TS U650 ( .A(n1186), .B(n1185), .Y(n1924) );
XNOR2X2TS U651 ( .A(n617), .B(n2793), .Y(n1081) );
BUFX16TS U652 ( .A(n1300), .Y(n2310) );
NAND2X2TS U653 ( .A(n1260), .B(n1259), .Y(n1424) );
NAND2X1TS U654 ( .A(n406), .B(n555), .Y(n954) );
INVX8TS U655 ( .A(n592), .Y(n590) );
XNOR2X2TS U656 ( .A(n644), .B(n2794), .Y(n1743) );
OR2X4TS U657 ( .A(n899), .B(n1762), .Y(n446) );
NAND2X4TS U658 ( .A(n1258), .B(n1257), .Y(n1434) );
BUFX12TS U659 ( .A(n2330), .Y(n841) );
OAI22X2TS U660 ( .A0(n1887), .A1(n2312), .B0(n2054), .B1(n1026), .Y(n2090)
);
BUFX16TS U661 ( .A(n855), .Y(n800) );
NOR2X6TS U662 ( .A(n1237), .B(n1259), .Y(n1239) );
NAND2X4TS U663 ( .A(n1235), .B(n1226), .Y(n1268) );
CLKINVX12TS U664 ( .A(n1853), .Y(n2121) );
XOR2X2TS U665 ( .A(n1090), .B(n672), .Y(n900) );
BUFX12TS U666 ( .A(n847), .Y(n2307) );
NAND2X4TS U667 ( .A(n1817), .B(mult_x_19_n1800), .Y(n743) );
NOR2X6TS U668 ( .A(n1256), .B(n1255), .Y(n1411) );
NOR2X6TS U669 ( .A(n1257), .B(n1258), .Y(n1433) );
NAND2BX2TS U670 ( .AN(n419), .B(n3097), .Y(n549) );
INVX2TS U671 ( .A(n2875), .Y(n2697) );
XNOR2X2TS U672 ( .A(n623), .B(n645), .Y(n975) );
XNOR2X2TS U673 ( .A(n644), .B(n646), .Y(n2072) );
XNOR2X2TS U674 ( .A(n617), .B(n638), .Y(n1055) );
NAND2X2TS U675 ( .A(n1237), .B(n1259), .Y(n1238) );
NOR2X2TS U676 ( .A(n902), .B(n1032), .Y(n2773) );
NAND2X2TS U677 ( .A(n902), .B(n1032), .Y(n2774) );
XNOR2X2TS U678 ( .A(n464), .B(n668), .Y(n1583) );
XOR2X2TS U679 ( .A(n464), .B(n2238), .Y(n2049) );
XOR2X2TS U680 ( .A(n2241), .B(n669), .Y(n2053) );
OAI22X2TS U681 ( .A0(n764), .A1(n2888), .B0(n2468), .B1(n1683), .Y(n1700) );
NAND2X2TS U682 ( .A(n828), .B(n737), .Y(n831) );
MXI2X4TS U683 ( .A(n3116), .B(n2588), .S0(n434), .Y(n1264) );
CLKXOR2X2TS U684 ( .A(n2241), .B(n655), .Y(n976) );
INVX12TS U685 ( .A(n675), .Y(n676) );
NAND2X6TS U686 ( .A(n1235), .B(n1225), .Y(n1266) );
INVX2TS U687 ( .A(n2878), .Y(n2588) );
BUFX8TS U688 ( .A(n594), .Y(n803) );
INVX6TS U689 ( .A(n2801), .Y(n761) );
INVX8TS U690 ( .A(n901), .Y(n790) );
INVX2TS U691 ( .A(n648), .Y(n649) );
BUFX16TS U692 ( .A(n1300), .Y(n2051) );
INVX12TS U693 ( .A(n2470), .Y(n764) );
BUFX4TS U694 ( .A(n633), .Y(n2327) );
XNOR2X2TS U695 ( .A(n604), .B(n2793), .Y(n2326) );
NAND2X2TS U696 ( .A(n1184), .B(n1183), .Y(n1664) );
NOR2X2TS U697 ( .A(n1938), .B(n3120), .Y(n1174) );
XNOR2X2TS U698 ( .A(n693), .B(n2476), .Y(n2036) );
INVX3TS U699 ( .A(n604), .Y(n605) );
BUFX16TS U700 ( .A(n2237), .Y(n492) );
INVX2TS U701 ( .A(n736), .Y(n737) );
BUFX12TS U702 ( .A(n1674), .Y(n2227) );
INVX1TS U703 ( .A(n645), .Y(n542) );
XNOR2X2TS U704 ( .A(n644), .B(n601), .Y(n2073) );
INVX12TS U705 ( .A(n675), .Y(n678) );
INVX2TS U706 ( .A(n691), .Y(n692) );
NOR2BX2TS U707 ( .AN(n612), .B(n1674), .Y(n1689) );
INVX4TS U708 ( .A(n2115), .Y(n2118) );
BUFX6TS U709 ( .A(n2319), .Y(n839) );
BUFX12TS U710 ( .A(n505), .Y(n509) );
NAND2X4TS U711 ( .A(n1235), .B(n1224), .Y(n1263) );
BUFX8TS U712 ( .A(n1500), .Y(n715) );
NAND2X2TS U713 ( .A(n568), .B(n3035), .Y(n2664) );
BUFX12TS U714 ( .A(n763), .Y(n760) );
INVX6TS U715 ( .A(n480), .Y(n1853) );
INVX6TS U716 ( .A(n671), .Y(n672) );
NOR2BX1TS U717 ( .AN(n612), .B(n633), .Y(n1068) );
NAND2X2TS U718 ( .A(n3097), .B(n2949), .Y(n709) );
XNOR2X2TS U719 ( .A(n645), .B(n671), .Y(n2039) );
CLKXOR2X4TS U720 ( .A(n753), .B(n2238), .Y(n1582) );
XNOR2X2TS U721 ( .A(n969), .B(n691), .Y(n726) );
BUFX8TS U722 ( .A(n1500), .Y(n714) );
BUFX6TS U723 ( .A(n1293), .Y(n2318) );
NAND2X2TS U724 ( .A(n1690), .B(n1691), .Y(n544) );
NAND2X6TS U725 ( .A(n1235), .B(n1234), .Y(n1260) );
INVX12TS U726 ( .A(n2486), .Y(n767) );
BUFX3TS U727 ( .A(n633), .Y(n1813) );
AND2X6TS U728 ( .A(n1205), .B(n2991), .Y(n1209) );
CLKBUFX2TS U729 ( .A(n1733), .Y(n430) );
NOR2X2TS U730 ( .A(n2323), .B(n2322), .Y(n453) );
INVX12TS U731 ( .A(n1281), .Y(n792) );
BUFX16TS U732 ( .A(n621), .Y(n1869) );
INVX8TS U733 ( .A(n754), .Y(n2238) );
INVX12TS U734 ( .A(n901), .Y(n2330) );
BUFX6TS U735 ( .A(mult_x_19_n28), .Y(n2223) );
INVX12TS U736 ( .A(n2486), .Y(n768) );
AND2X4TS U737 ( .A(n1211), .B(n3019), .Y(n1849) );
INVX2TS U738 ( .A(n464), .Y(n465) );
BUFX16TS U739 ( .A(n1817), .Y(n842) );
NAND2X6TS U740 ( .A(n729), .B(n730), .Y(n1691) );
BUFX12TS U741 ( .A(n673), .Y(n2319) );
NAND2BX2TS U742 ( .AN(n612), .B(n780), .Y(n1151) );
NAND2X2TS U743 ( .A(n569), .B(n2987), .Y(n1991) );
NAND2X6TS U744 ( .A(n1229), .B(n1235), .Y(n1254) );
NOR2X4TS U745 ( .A(n1642), .B(n1638), .Y(n1181) );
XNOR2X2TS U746 ( .A(n464), .B(n736), .Y(n1115) );
NAND2X2TS U747 ( .A(n577), .B(n2982), .Y(n1643) );
BUFX6TS U748 ( .A(n744), .Y(n970) );
BUFX6TS U749 ( .A(n679), .Y(n1674) );
XNOR2X2TS U750 ( .A(n694), .B(n749), .Y(n1150) );
BUFX6TS U751 ( .A(n1300), .Y(n437) );
NAND3X6TS U752 ( .A(n637), .B(n2124), .C(n480), .Y(n479) );
NOR2X4TS U753 ( .A(n677), .B(n2324), .Y(n454) );
NOR2X4TS U754 ( .A(n1634), .B(n1663), .Y(n1176) );
BUFX16TS U755 ( .A(n691), .Y(n2221) );
BUFX6TS U756 ( .A(n600), .Y(n601) );
INVX4TS U757 ( .A(n552), .Y(n553) );
BUFX12TS U758 ( .A(n754), .Y(n881) );
BUFX16TS U759 ( .A(n686), .Y(n2476) );
BUFX12TS U760 ( .A(n654), .Y(n884) );
INVX12TS U761 ( .A(n897), .Y(n406) );
BUFX16TS U762 ( .A(n646), .Y(n786) );
NOR2X6TS U763 ( .A(mult_x_19_n764), .B(n1187), .Y(n1932) );
XNOR2X2TS U764 ( .A(n1761), .B(n870), .Y(n1036) );
BUFX8TS U765 ( .A(n600), .Y(n2313) );
INVX8TS U766 ( .A(n554), .Y(n556) );
INVX8TS U767 ( .A(n613), .Y(n789) );
INVX8TS U768 ( .A(n554), .Y(n555) );
BUFX12TS U769 ( .A(n1293), .Y(n1762) );
NOR2X6TS U770 ( .A(n580), .B(n2964), .Y(n1199) );
NAND2X2TS U771 ( .A(n574), .B(n3005), .Y(n2116) );
NAND2X2TS U772 ( .A(n576), .B(n3042), .Y(n1734) );
XNOR2X2TS U773 ( .A(n728), .B(n639), .Y(n1033) );
XNOR2X2TS U774 ( .A(n1090), .B(n798), .Y(n1027) );
BUFX8TS U775 ( .A(mult_x_19_n52), .Y(n2322) );
BUFX12TS U776 ( .A(mult_x_19_n28), .Y(n2314) );
XNOR2X2TS U777 ( .A(n753), .B(n2794), .Y(n2324) );
OR2X4TS U778 ( .A(n1300), .B(n1162), .Y(n745) );
NAND2X4TS U779 ( .A(n1213), .B(n1848), .Y(n1215) );
NAND2X2TS U780 ( .A(n3118), .B(Op_MY[26]), .Y(n1234) );
NOR2X6TS U781 ( .A(n579), .B(n2978), .Y(n1197) );
BUFX12TS U782 ( .A(n548), .Y(n523) );
INVX12TS U783 ( .A(n918), .Y(n666) );
BUFX4TS U784 ( .A(n727), .Y(n1090) );
BUFX16TS U785 ( .A(n594), .Y(n804) );
INVX4TS U786 ( .A(n624), .Y(n798) );
BUFX12TS U787 ( .A(n623), .Y(n2793) );
NOR2X6TS U788 ( .A(n574), .B(n2975), .Y(n2117) );
OR2X4TS U789 ( .A(n3033), .B(n3034), .Y(n2671) );
BUFX12TS U790 ( .A(n847), .Y(n2048) );
NAND2X4TS U791 ( .A(n2006), .B(n2970), .Y(n474) );
NOR2X4TS U792 ( .A(n1941), .B(n575), .Y(n1213) );
BUFX12TS U793 ( .A(n738), .Y(n548) );
INVX8TS U794 ( .A(n1761), .Y(n2239) );
BUFX6TS U795 ( .A(n1091), .Y(n594) );
INVX12TS U796 ( .A(n627), .Y(n2241) );
INVX12TS U797 ( .A(n2801), .Y(n762) );
INVX6TS U798 ( .A(n638), .Y(n639) );
CLKINVX6TS U799 ( .A(n627), .Y(n628) );
BUFX12TS U800 ( .A(n679), .Y(n2468) );
INVX6TS U801 ( .A(n563), .Y(n2801) );
OAI22X2TS U802 ( .A0(n695), .A1(n2476), .B0(n715), .B1(n786), .Y(n1557) );
ADDFHX2TS U803 ( .A(n2489), .B(n2488), .CI(n2487), .CO(n2498), .S(n2493) );
NAND2X6TS U804 ( .A(n2284), .B(n2283), .Y(n2285) );
AND2X6TS U805 ( .A(n2287), .B(n2286), .Y(n2909) );
ADDFHX4TS U806 ( .A(n2043), .B(n2044), .CI(n2042), .CO(n2089), .S(n2103) );
NOR2X2TS U807 ( .A(n2532), .B(n2538), .Y(mult_x_19_n165) );
NAND2X8TS U808 ( .A(n2536), .B(n2535), .Y(mult_x_19_n179) );
NAND2X4TS U809 ( .A(n2681), .B(n266), .Y(n3349) );
OAI22X2TS U810 ( .A0(n677), .A1(n2473), .B0(n2472), .B1(n799), .Y(n2549) );
OAI22X2TS U811 ( .A0(n2041), .A1(n1514), .B0(n801), .B1(n645), .Y(n1595) );
ADDFHX4TS U812 ( .A(n2440), .B(n2439), .CI(n2438), .CO(n2461), .S(n2508) );
OAI2BB1X4TS U813 ( .A0N(n913), .A1N(n1891), .B0(n912), .Y(n2439) );
MX2X4TS U814 ( .A(n2601), .B(P_Sgf[5]), .S0(n424), .Y(n243) );
NAND2X4TS U815 ( .A(n776), .B(n2680), .Y(n3333) );
NAND2X4TS U816 ( .A(n2734), .B(n2690), .Y(n2691) );
NOR2X4TS U817 ( .A(n2716), .B(n2689), .Y(n2690) );
NAND2X8TS U818 ( .A(n531), .B(n3267), .Y(n2680) );
XOR2X4TS U819 ( .A(n2761), .B(n2760), .Y(n2762) );
NAND2X6TS U820 ( .A(n532), .B(n3268), .Y(n531) );
NAND2X8TS U821 ( .A(n455), .B(n3264), .Y(n2678) );
NAND2X8TS U822 ( .A(n501), .B(n3257), .Y(n2685) );
NAND2X8TS U823 ( .A(n441), .B(n3271), .Y(n2684) );
NAND2X6TS U824 ( .A(n2658), .B(n3258), .Y(n501) );
AOI2BB2X4TS U825 ( .B0(n2700), .B1(n263), .A0N(n805), .A1N(n1995), .Y(n1997)
);
MX2X6TS U826 ( .A(n1646), .B(n3240), .S0(n586), .Y(n263) );
NAND2X4TS U827 ( .A(mult_x_19_n555), .B(n2282), .Y(mult_x_19_n114) );
OAI22X2TS U828 ( .A0(n1786), .A1(n2051), .B0(n2307), .B1(n1823), .Y(n1829)
);
NAND3X6TS U829 ( .A(n3180), .B(n3179), .C(n3178), .Y(n2851) );
XOR2X4TS U830 ( .A(n2756), .B(n2755), .Y(n2758) );
XNOR2X4TS U831 ( .A(n615), .B(n2285), .Y(Sgf_operation_Result[7]) );
MXI2X8TS U832 ( .A(n3135), .B(n3107), .S0(n434), .Y(n1267) );
AOI2BB2X4TS U833 ( .B0(n2784), .B1(n267), .A0N(n807), .A1N(n3145), .Y(n3350)
);
ADDFHX4TS U834 ( .A(n1509), .B(n1508), .CI(n1507), .CO(n1522), .S(n2491) );
CLKINVX12TS U835 ( .A(n680), .Y(n1508) );
OAI2BB1X4TS U836 ( .A0N(n2189), .A1N(n2188), .B0(n919), .Y(mult_x_19_n691)
);
ADDFHX2TS U837 ( .A(n1512), .B(n1511), .CI(n1510), .CO(n2501), .S(n2490) );
AO22X4TS U838 ( .A0(n2946), .A1(n622), .B0(n2474), .B1(n3051), .Y(n2475) );
NAND2X4TS U839 ( .A(n2946), .B(n2801), .Y(n483) );
AO22X4TS U840 ( .A0(n2474), .A1(n3095), .B0(n2946), .B1(n733), .Y(n1611) );
INVX8TS U841 ( .A(n462), .Y(n707) );
OAI22X4TS U842 ( .A0(n2312), .A1(n2899), .B0(n1026), .B1(n1016), .Y(n1021)
);
OAI21X2TS U843 ( .A0(n2258), .A1(n2260), .B0(n2214), .Y(n378) );
MXI2X8TS U844 ( .A(n996), .B(n3113), .S0(n434), .Y(n1259) );
BUFX20TS U845 ( .A(FSM_selector_A), .Y(n434) );
NAND2X2TS U846 ( .A(n776), .B(n2640), .Y(n3352) );
NAND2X8TS U847 ( .A(n2640), .B(n502), .Y(n2687) );
AOI21X4TS U848 ( .A0(n2121), .A1(n2120), .B0(n2119), .Y(n2126) );
INVX6TS U849 ( .A(n1968), .Y(n1969) );
OAI21X2TS U850 ( .A0(n766), .A1(n2254), .B0(n2253), .Y(n2255) );
NAND2X8TS U851 ( .A(n1393), .B(n1392), .Y(n2192) );
OAI22X2TS U852 ( .A0(n784), .A1(n1501), .B0(n1514), .B1(n800), .Y(n1519) );
OAI21X4TS U853 ( .A0(n766), .A1(n2653), .B0(n2652), .Y(n2657) );
OAI22X4TS U854 ( .A0(n784), .A1(n1505), .B0(n1501), .B1(n801), .Y(n1509) );
INVX16TS U855 ( .A(n2312), .Y(n989) );
OAI22X4TS U856 ( .A0(n804), .A1(n1092), .B0(n1103), .B1(n2314), .Y(n1126) );
XNOR2X4TS U857 ( .A(n878), .B(n2904), .Y(n1092) );
NAND2X8TS U858 ( .A(n2651), .B(n1217), .Y(n1219) );
OAI22X4TS U859 ( .A0(n1762), .A1(n1028), .B0(n1022), .B1(n757), .Y(n1023) );
NAND2X8TS U860 ( .A(n1402), .B(n1401), .Y(n1968) );
INVX6TS U861 ( .A(n818), .Y(n1586) );
NAND2X2TS U862 ( .A(n2681), .B(n265), .Y(n1671) );
NAND2X4TS U863 ( .A(n1039), .B(n1038), .Y(n2778) );
NAND3X8TS U864 ( .A(n564), .B(n3181), .C(n3182), .Y(n2686) );
NOR2X4TS U865 ( .A(n1197), .B(n1199), .Y(n1201) );
INVX8TS U866 ( .A(n1219), .Y(n432) );
ADDFHX2TS U867 ( .A(n2495), .B(n2494), .CI(n2493), .CO(n2496), .S(
mult_x_19_n626) );
ADDFHX4TS U868 ( .A(n2516), .B(n2515), .CI(n2514), .CO(n2354), .S(n2525) );
NOR2X4TS U869 ( .A(n2281), .B(n2433), .Y(mult_x_19_n465) );
NAND2X8TS U870 ( .A(n528), .B(n3250), .Y(n2638) );
NAND3X4TS U871 ( .A(n2627), .B(n2626), .C(n2625), .Y(n205) );
NAND2X4TS U872 ( .A(mult_x_19_n451), .B(n707), .Y(mult_x_19_n111) );
INVX4TS U873 ( .A(n765), .Y(n1621) );
NAND2X4TS U874 ( .A(n2248), .B(n1369), .Y(n1371) );
OAI21X4TS U875 ( .A0(n2188), .A1(n2189), .B0(n540), .Y(n919) );
NOR2X6TS U876 ( .A(n1259), .B(n1260), .Y(n1423) );
NAND2X4TS U877 ( .A(n2110), .B(n2109), .Y(n2111) );
OAI21X4TS U878 ( .A0(n1847), .A1(n765), .B0(n1846), .Y(n1851) );
INVX8TS U879 ( .A(mult_x_19_n453), .Y(mult_x_19_n451) );
INVX6TS U880 ( .A(n1420), .Y(n1437) );
AOI21X2TS U881 ( .A0(n1929), .A1(n1921), .B0(n1923), .Y(n1652) );
OAI22X4TS U882 ( .A0(n804), .A1(n1103), .B0(n1109), .B1(n2314), .Y(n1141) );
OAI22X2TS U883 ( .A0(n1502), .A1(n667), .B0(n970), .B1(n1513), .Y(n1518) );
NAND2X4TS U884 ( .A(n2265), .B(n3099), .Y(mult_x_19_n109) );
INVX6TS U885 ( .A(n634), .Y(n2265) );
INVX16TS U886 ( .A(n1917), .Y(n2248) );
OAI21X2TS U887 ( .A0(n2118), .A1(n2117), .B0(n2116), .Y(n2119) );
OAI22X2TS U888 ( .A0(n1894), .A1(n509), .B0(n2038), .B1(n744), .Y(n2079) );
ADDFHX4TS U889 ( .A(n2368), .B(n2367), .CI(n2366), .CO(n2413), .S(n2391) );
ADDFHX4TS U890 ( .A(n2420), .B(n2419), .CI(n2418), .CO(n2521), .S(n2412) );
INVX6TS U891 ( .A(n2192), .Y(n2193) );
INVX6TS U892 ( .A(n960), .Y(n982) );
INVX16TS U893 ( .A(n669), .Y(n787) );
OR2X8TS U894 ( .A(n2312), .B(n1161), .Y(n729) );
NAND2X2TS U895 ( .A(n1053), .B(n2598), .Y(n487) );
NAND2X4TS U896 ( .A(n463), .B(n3099), .Y(mult_x_19_n430) );
ADDFHX2TS U897 ( .A(n1132), .B(n1131), .CI(n1130), .CO(n1145), .S(n1977) );
NAND2X4TS U898 ( .A(n519), .B(n632), .Y(mult_x_19_n108) );
NAND2X2TS U899 ( .A(n3102), .B(n978), .Y(n977) );
OAI22X2TS U900 ( .A0(n2051), .A1(n1583), .B0(n499), .B1(n706), .Y(n1590) );
OAI22X2TS U901 ( .A0(n499), .A1(n498), .B0(n2051), .B1(n706), .Y(n1550) );
INVX2TS U902 ( .A(n1493), .Y(n397) );
NAND3BX4TS U903 ( .AN(n397), .B(n1492), .C(n1491), .Y(n222) );
NAND2X4TS U904 ( .A(n2248), .B(n565), .Y(n1484) );
BUFX8TS U905 ( .A(n399), .Y(n429) );
BUFX12TS U906 ( .A(n791), .Y(n969) );
ADDFHX2TS U907 ( .A(n1890), .B(n1888), .CI(n1889), .CO(n2440), .S(n1871) );
CLKINVX12TS U908 ( .A(Op_MY[5]), .Y(n848) );
INVX12TS U909 ( .A(n848), .Y(n398) );
INVX12TS U910 ( .A(n848), .Y(n399) );
INVX2TS U911 ( .A(n401), .Y(n403) );
CLKINVX1TS U912 ( .A(n401), .Y(n405) );
OAI22X2TS U913 ( .A0(n406), .A1(n1110), .B0(n555), .B1(n917), .Y(n1152) );
INVX16TS U914 ( .A(n738), .Y(n897) );
OAI22X4TS U915 ( .A0(n760), .A1(mult_x_19_n1585), .B0(n2073), .B1(n2468),
.Y(n2092) );
OA21X1TS U916 ( .A0(n2664), .A1(n2663), .B0(n2662), .Y(n2665) );
INVX2TS U917 ( .A(n2665), .Y(n408) );
INVX2TS U918 ( .A(n409), .Y(n410) );
NAND2X6TS U919 ( .A(n442), .B(n587), .Y(n441) );
NAND2X6TS U920 ( .A(n456), .B(n587), .Y(n455) );
AO21X1TS U921 ( .A0(n1367), .A1(n581), .B0(n2936), .Y(n1368) );
XNOR2X1TS U922 ( .A(n628), .B(n870), .Y(n1018) );
INVX2TS U923 ( .A(n673), .Y(n674) );
XNOR2X2TS U924 ( .A(n693), .B(n2794), .Y(n1703) );
NAND2X2TS U925 ( .A(n1923), .B(n1189), .Y(n482) );
NOR2X2TS U926 ( .A(n2117), .B(n428), .Y(n637) );
NOR2BX2TS U927 ( .AN(n789), .B(n757), .Y(n1032) );
INVX4TS U928 ( .A(n701), .Y(n799) );
AO21X1TS U929 ( .A0(n768), .A1(n2485), .B0(n2889), .Y(n2545) );
NAND2X1TS U930 ( .A(n3358), .B(n2831), .Y(n2587) );
INVX6TS U931 ( .A(n660), .Y(n519) );
NAND2BX1TS U932 ( .AN(n3151), .B(n2873), .Y(n1277) );
NAND2BX1TS U933 ( .AN(n418), .B(n3242), .Y(n503) );
OA21X4TS U934 ( .A0(n2122), .A1(n2116), .B0(n2123), .Y(n416) );
OR2X8TS U935 ( .A(n510), .B(n505), .Y(n417) );
AND2X8TS U936 ( .A(n1525), .B(n2284), .Y(n422) );
AND2X8TS U937 ( .A(n1410), .B(n1409), .Y(n423) );
NOR2X4TS U938 ( .A(n527), .B(n526), .Y(n3353) );
NAND2X2TS U939 ( .A(n2681), .B(n2680), .Y(n3334) );
NAND2X2TS U940 ( .A(n776), .B(n2684), .Y(n3321) );
NAND2X2TS U941 ( .A(n2679), .B(n2678), .Y(n3314) );
NAND2X2TS U942 ( .A(n2684), .B(n2701), .Y(n3322) );
NAND2X2TS U943 ( .A(n796), .B(n2674), .Y(n3301) );
NAND2X2TS U944 ( .A(n2673), .B(n796), .Y(n3341) );
NAND2X2TS U945 ( .A(n776), .B(n2683), .Y(n3325) );
NAND2X2TS U946 ( .A(n2701), .B(n2673), .Y(n3342) );
NAND2X2TS U947 ( .A(n2681), .B(n2676), .Y(n3338) );
NAND2X2TS U948 ( .A(n2681), .B(n2674), .Y(n3302) );
NAND2X2TS U949 ( .A(n2681), .B(n2683), .Y(n3326) );
NAND2X2TS U950 ( .A(n796), .B(n2676), .Y(n3337) );
NAND2X2TS U951 ( .A(n776), .B(n2699), .Y(n3345) );
NAND2X2TS U952 ( .A(n2679), .B(n2699), .Y(n3346) );
NAND2X6TS U953 ( .A(n439), .B(n438), .Y(n260) );
NAND2X4TS U954 ( .A(n2113), .B(n420), .Y(n439) );
INVX2TS U955 ( .A(n2286), .Y(n1617) );
INVX4TS U956 ( .A(n2537), .Y(n1618) );
NAND2X4TS U957 ( .A(n484), .B(n1051), .Y(n490) );
INVX8TS U958 ( .A(n1647), .Y(n2679) );
OR2X4TS U959 ( .A(n2564), .B(n2563), .Y(n3092) );
INVX8TS U960 ( .A(n1647), .Y(n2681) );
INVX6TS U961 ( .A(n2611), .Y(n2792) );
NOR2X4TS U962 ( .A(n2540), .B(n2539), .Y(mult_x_19_n145) );
MX2X2TS U963 ( .A(n2762), .B(Add_result[22]), .S0(n2771), .Y(n287) );
BUFX20TS U964 ( .A(n425), .Y(n3275) );
MX2X2TS U965 ( .A(n2767), .B(n808), .S0(n2771), .Y(n291) );
MX2X2TS U966 ( .A(n2745), .B(n811), .S0(n2771), .Y(n288) );
MX2X2TS U967 ( .A(n2772), .B(n810), .S0(n2771), .Y(n289) );
INVX8TS U968 ( .A(n425), .Y(n3274) );
MX2X2TS U969 ( .A(n2752), .B(n812), .S0(n2771), .Y(n290) );
INVX4TS U970 ( .A(n353), .Y(n2943) );
BUFX8TS U971 ( .A(n2839), .Y(n2853) );
INVX4TS U972 ( .A(n363), .Y(n2932) );
INVX4TS U973 ( .A(n452), .Y(n450) );
INVX4TS U974 ( .A(mult_x_19_n49), .Y(n2929) );
INVX4TS U975 ( .A(mult_x_19_n19), .Y(n2922) );
INVX4TS U976 ( .A(n344), .Y(n2962) );
BUFX4TS U977 ( .A(n2839), .Y(n2829) );
XNOR2X1TS U978 ( .A(n349), .B(mult_x_19_n593), .Y(n596) );
XOR2X1TS U979 ( .A(mult_x_19_n7), .B(n346), .Y(n2963) );
MX2X2TS U980 ( .A(n2620), .B(Add_result[7]), .S0(n2757), .Y(n302) );
INVX4TS U981 ( .A(n349), .Y(n2925) );
NAND2X8TS U982 ( .A(n535), .B(FS_Module_state_reg[1]), .Y(n1486) );
OR4X4TS U983 ( .A(n252), .B(n253), .C(n254), .D(n251), .Y(n562) );
NAND2X4TS U984 ( .A(n832), .B(n831), .Y(n2046) );
INVX8TS U985 ( .A(n478), .Y(n476) );
INVX6TS U986 ( .A(n1263), .Y(n1242) );
MX2X6TS U987 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n2263), .Y(n349) );
MX2X2TS U988 ( .A(n2196), .B(n3232), .S0(n588), .Y(n253) );
MX2X6TS U989 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n2568), .Y(n363) );
BUFX12TS U990 ( .A(n771), .Y(n3278) );
NAND2X4TS U991 ( .A(n1196), .B(n1274), .Y(n535) );
NAND2X4TS U992 ( .A(n971), .B(n925), .Y(n2546) );
CLKMX2X3TS U993 ( .A(Data_MY[2]), .B(n828), .S0(n2795), .Y(n314) );
CLKMX2X3TS U994 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n2800), .Y(n342) );
CLKMX2X3TS U995 ( .A(Data_MY[4]), .B(n798), .S0(n2795), .Y(n316) );
CLKMX2X3TS U996 ( .A(Data_MY[9]), .B(n762), .S0(n2802), .Y(n321) );
MX2X2TS U997 ( .A(n2597), .B(Add_result[6]), .S0(n2757), .Y(n303) );
NAND2X6TS U998 ( .A(n1175), .B(n1274), .Y(n1003) );
MX2X6TS U999 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n2263), .Y(n355) );
NOR2X4TS U1000 ( .A(n2799), .B(n793), .Y(n534) );
CLKMX2X3TS U1001 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n2800), .Y(n367) );
NAND2X4TS U1002 ( .A(n1256), .B(n1255), .Y(n1412) );
NAND2X4TS U1003 ( .A(n924), .B(n972), .Y(n923) );
MX2X2TS U1004 ( .A(n2194), .B(n3234), .S0(n588), .Y(n252) );
OAI22X2TS U1005 ( .A0(n2219), .A1(n1813), .B0(n2330), .B1(n1744), .Y(n663)
);
NAND2X4TS U1006 ( .A(n896), .B(n709), .Y(n905) );
NAND2X6TS U1007 ( .A(n559), .B(n1944), .Y(n1947) );
NOR2X1TS U1008 ( .A(n2719), .B(n2716), .Y(n2705) );
OAI21X1TS U1009 ( .A0(n2858), .A1(n2617), .B0(n2616), .Y(n2619) );
NAND2X4TS U1010 ( .A(n954), .B(n953), .Y(n2078) );
BUFX4TS U1011 ( .A(n2797), .Y(n2798) );
INVX4TS U1012 ( .A(n1195), .Y(n1196) );
OAI21X1TS U1013 ( .A0(n2858), .A1(n2859), .B0(n2631), .Y(n2596) );
INVX2TS U1014 ( .A(n1923), .Y(n1926) );
AND2X2TS U1015 ( .A(n2213), .B(n1364), .Y(n502) );
INVX8TS U1016 ( .A(n3361), .Y(n770) );
NAND2X2TS U1017 ( .A(n1654), .B(n1924), .Y(n1655) );
INVX2TS U1018 ( .A(n560), .Y(n2373) );
INVX3TS U1019 ( .A(n1325), .Y(n978) );
NAND2X8TS U1020 ( .A(n3119), .B(n1174), .Y(n2258) );
INVX2TS U1021 ( .A(n2108), .Y(n2110) );
INVX2TS U1022 ( .A(n2577), .Y(n2579) );
MX2X2TS U1023 ( .A(n2202), .B(n3230), .S0(n588), .Y(n251) );
INVX2TS U1024 ( .A(n2831), .Y(overflow_flag) );
NAND2X4TS U1025 ( .A(n2842), .B(n2840), .Y(n2689) );
INVX2TS U1026 ( .A(n2843), .Y(n2736) );
NAND2X6TS U1027 ( .A(n2838), .B(n2848), .Y(n2728) );
INVX2TS U1028 ( .A(n2836), .Y(n2729) );
NAND2X4TS U1029 ( .A(n2836), .B(n2845), .Y(n2688) );
NAND2X4TS U1030 ( .A(n2851), .B(n640), .Y(n2631) );
INVX2TS U1031 ( .A(n2854), .Y(n2760) );
INVX2TS U1032 ( .A(n2662), .Y(n1202) );
CLKBUFX2TS U1033 ( .A(Add_result[9]), .Y(n809) );
INVX2TS U1034 ( .A(n2989), .Y(n440) );
NOR2X6TS U1035 ( .A(n3040), .B(n3041), .Y(n1854) );
CLKBUFX2TS U1036 ( .A(Add_result[18]), .Y(n808) );
OR3X6TS U1037 ( .A(n750), .B(n751), .C(n752), .Y(n2847) );
INVX2TS U1038 ( .A(n640), .Y(n641) );
NAND3X4TS U1039 ( .A(n3200), .B(n3199), .C(n3198), .Y(n2850) );
NAND3X4TS U1040 ( .A(n3212), .B(n3211), .C(n3210), .Y(n2843) );
NOR2X4TS U1041 ( .A(exp_oper_result_8_), .B(Exp_module_Overflow_flag_A), .Y(
n2831) );
NAND2X2TS U1042 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n2590) );
CLKBUFX2TS U1043 ( .A(Add_result[20]), .Y(n810) );
NOR2X4TS U1044 ( .A(n576), .B(n2990), .Y(n1733) );
MX2X4TS U1045 ( .A(n731), .B(Op_MX[30]), .S0(n3121), .Y(n699) );
INVX2TS U1046 ( .A(n2903), .Y(n953) );
INVX8TS U1047 ( .A(n612), .Y(n613) );
BUFX8TS U1048 ( .A(n732), .Y(n863) );
INVX2TS U1049 ( .A(n618), .Y(n619) );
INVX6TS U1050 ( .A(n774), .Y(n499) );
CLKBUFX2TS U1051 ( .A(Add_result[19]), .Y(n812) );
NAND2X2TS U1052 ( .A(n2687), .B(n2686), .Y(n3355) );
NAND2X4TS U1053 ( .A(n2260), .B(n964), .Y(n2261) );
INVX8TS U1054 ( .A(mult_x_19_n439), .Y(n463) );
NAND2X2TS U1055 ( .A(n2679), .B(n2628), .Y(n3293) );
NAND3X4TS U1056 ( .A(n1986), .B(n1480), .C(n1739), .Y(n3357) );
NAND2X2TS U1057 ( .A(n776), .B(n2685), .Y(n3317) );
NAND2X2TS U1058 ( .A(n2679), .B(n2685), .Y(n3318) );
NAND2X6TS U1059 ( .A(n938), .B(n939), .Y(n1982) );
NAND2X2TS U1060 ( .A(n2701), .B(n2675), .Y(n3306) );
NAND2X2TS U1061 ( .A(n796), .B(n2639), .Y(n3296) );
NAND3X2TS U1062 ( .A(n1998), .B(n1997), .C(n1996), .Y(n203) );
NAND2X4TS U1063 ( .A(n681), .B(n2679), .Y(n1491) );
NAND2X6TS U1064 ( .A(mult_x_19_n648), .B(mult_x_19_n661), .Y(mult_x_19_n267)
);
NAND2X6TS U1065 ( .A(n472), .B(n585), .Y(n471) );
NAND2X4TS U1066 ( .A(n529), .B(n585), .Y(n528) );
NAND2X6TS U1067 ( .A(n488), .B(n487), .Y(n486) );
NAND2X4TS U1068 ( .A(n1397), .B(n2788), .Y(n1402) );
NAND2X2TS U1069 ( .A(n2268), .B(n2267), .Y(mult_x_19_n115) );
NAND2X2TS U1070 ( .A(mult_x_19_n465), .B(n2437), .Y(mult_x_19_n458) );
INVX4TS U1071 ( .A(mult_x_19_n179), .Y(mult_x_19_n181) );
INVX4TS U1072 ( .A(n2281), .Y(mult_x_19_n555) );
INVX8TS U1073 ( .A(n1966), .Y(n1978) );
XOR2X2TS U1074 ( .A(n875), .B(n2294), .Y(mult_x_19_n810) );
AND2X2TS U1075 ( .A(n2541), .B(mult_x_19_n146), .Y(n2910) );
NAND2X6TS U1076 ( .A(n823), .B(n2185), .Y(n822) );
MX2X4TS U1077 ( .A(n1637), .B(n3243), .S0(n586), .Y(n264) );
NAND2X6TS U1078 ( .A(n490), .B(n489), .Y(n1052) );
MX2X2TS U1079 ( .A(n2867), .B(P_Sgf[4]), .S0(n424), .Y(n242) );
NAND2X4TS U1080 ( .A(n2701), .B(n267), .Y(n2702) );
MX2X2TS U1081 ( .A(n2758), .B(Add_result[23]), .S0(n2757), .Y(n286) );
INVX2TS U1082 ( .A(n2607), .Y(n2609) );
INVX6TS U1083 ( .A(n2598), .Y(n2606) );
AND2X2TS U1084 ( .A(n3092), .B(n2566), .Y(n2911) );
NAND2X6TS U1085 ( .A(n930), .B(n436), .Y(n2348) );
NAND2X6TS U1086 ( .A(n827), .B(n826), .Y(n2296) );
NAND2X2TS U1087 ( .A(n2564), .B(n2563), .Y(n2566) );
MX2X2TS U1088 ( .A(n2782), .B(P_Sgf[3]), .S0(n424), .Y(n241) );
NAND2X6TS U1089 ( .A(n2604), .B(n485), .Y(n484) );
ADDFHX2TS U1090 ( .A(n2402), .B(n2401), .CI(n2400), .CO(mult_x_19_n651), .S(
n1572) );
NAND2X2TS U1091 ( .A(n2540), .B(n2539), .Y(mult_x_19_n146) );
NAND2BX2TS U1092 ( .AN(n591), .B(n2937), .Y(n595) );
NAND2X2TS U1093 ( .A(n720), .B(n719), .Y(n2176) );
INVX8TS U1094 ( .A(n2611), .Y(n2827) );
OAI2BB1X2TS U1095 ( .A0N(n947), .A1N(n1865), .B0(n948), .Y(n2504) );
NAND2X6TS U1096 ( .A(n449), .B(n448), .Y(n2411) );
INVX12TS U1097 ( .A(n3275), .Y(n776) );
INVX8TS U1098 ( .A(n2611), .Y(n2828) );
NAND2X6TS U1099 ( .A(n432), .B(n2667), .Y(n431) );
INVX2TS U1100 ( .A(n1376), .Y(n1379) );
NAND2X4TS U1101 ( .A(n1435), .B(n1434), .Y(n1438) );
INVX4TS U1102 ( .A(n1428), .Y(n1439) );
INVX2TS U1103 ( .A(n1377), .Y(n1378) );
NAND2X6TS U1104 ( .A(n1486), .B(n534), .Y(n1647) );
NAND2X6TS U1105 ( .A(n545), .B(n544), .Y(n739) );
AO22X2TS U1106 ( .A0(n2853), .A1(n2837), .B0(final_result_ieee[7]), .B1(
n2849), .Y(n193) );
AO22X2TS U1107 ( .A0(n2829), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n2855), .Y(n200) );
XOR2X1TS U1108 ( .A(n2939), .B(mult_x_19_n1791), .Y(n3065) );
ADDFHX2TS U1109 ( .A(n1089), .B(n1088), .CI(n1087), .CO(n1144), .S(n1096) );
MX2X2TS U1110 ( .A(n2724), .B(Add_result[15]), .S0(n2771), .Y(n294) );
MX2X2TS U1111 ( .A(n2738), .B(Add_result[12]), .S0(n2757), .Y(n297) );
MX2X2TS U1112 ( .A(n2733), .B(Add_result[11]), .S0(n2757), .Y(n298) );
MX2X2TS U1113 ( .A(n2715), .B(Add_result[13]), .S0(n2757), .Y(n296) );
MX2X2TS U1114 ( .A(n2708), .B(Add_result[14]), .S0(n2757), .Y(n295) );
XOR2X1TS U1115 ( .A(n357), .B(n2567), .Y(n3068) );
AO22X2TS U1116 ( .A0(n2829), .A1(n2846), .B0(final_result_ieee[17]), .B1(
n2849), .Y(n183) );
INVX2TS U1117 ( .A(n1380), .Y(n1382) );
AO22X2TS U1118 ( .A0(n2829), .A1(n2840), .B0(final_result_ieee[15]), .B1(
n2855), .Y(n185) );
AO22X2TS U1119 ( .A0(n2829), .A1(n2842), .B0(final_result_ieee[14]), .B1(
n2849), .Y(n186) );
AO22X2TS U1120 ( .A0(n2829), .A1(n2850), .B0(final_result_ieee[13]), .B1(
n2849), .Y(n187) );
AO22X2TS U1121 ( .A0(n2829), .A1(n2843), .B0(final_result_ieee[12]), .B1(
n2849), .Y(n188) );
AO22X2TS U1122 ( .A0(n2829), .A1(n2845), .B0(final_result_ieee[11]), .B1(
n2849), .Y(n189) );
AO22X2TS U1123 ( .A0(n2853), .A1(n2836), .B0(final_result_ieee[10]), .B1(
n2849), .Y(n190) );
AO22X2TS U1124 ( .A0(n2853), .A1(n2848), .B0(final_result_ieee[9]), .B1(
n2849), .Y(n191) );
AO22X2TS U1125 ( .A0(n2853), .A1(n2838), .B0(final_result_ieee[8]), .B1(
n2849), .Y(n192) );
AO22X2TS U1126 ( .A0(n2853), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n2849), .Y(n194) );
AO22X2TS U1127 ( .A0(n2853), .A1(n664), .B0(final_result_ieee[1]), .B1(n2852), .Y(n199) );
AND2X2TS U1128 ( .A(n2574), .B(n2573), .Y(n2912) );
MX2X2TS U1129 ( .A(n2748), .B(Add_result[17]), .S0(n2771), .Y(n292) );
XOR2X2TS U1130 ( .A(n2707), .B(n2706), .Y(n2708) );
XOR2X2TS U1131 ( .A(n2732), .B(n2731), .Y(n2733) );
OR2X2TS U1132 ( .A(n2572), .B(n2571), .Y(n2574) );
XOR2X2TS U1133 ( .A(n2744), .B(n2743), .Y(n2745) );
INVX6TS U1134 ( .A(n1266), .Y(n1243) );
MX2X2TS U1135 ( .A(n2740), .B(Add_result[16]), .S0(n2771), .Y(n293) );
XOR2X2TS U1136 ( .A(n2710), .B(n2709), .Y(n2711) );
XOR2X2TS U1137 ( .A(n2722), .B(n2721), .Y(n2724) );
XOR2X2TS U1138 ( .A(n2770), .B(n3141), .Y(n2772) );
XOR2X2TS U1139 ( .A(n2714), .B(n2713), .Y(n2715) );
INVX3TS U1140 ( .A(mult_x_19_n7), .Y(n2923) );
NAND2X6TS U1141 ( .A(n979), .B(n977), .Y(n988) );
ADDFHX2TS U1142 ( .A(n1829), .B(n1828), .CI(n1827), .CO(n2135), .S(n1824) );
AO22X2TS U1143 ( .A0(n2839), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[20]), .B1(n2855), .Y(n180) );
AO22X2TS U1144 ( .A0(n2839), .A1(n2844), .B0(final_result_ieee[19]), .B1(
n2855), .Y(n181) );
AO22X2TS U1145 ( .A0(n2839), .A1(n2841), .B0(final_result_ieee[18]), .B1(
n2855), .Y(n182) );
AO22X2TS U1146 ( .A0(n2839), .A1(n2847), .B0(final_result_ieee[16]), .B1(
n2855), .Y(n184) );
INVX2TS U1147 ( .A(n1403), .Y(n1388) );
XOR2X2TS U1148 ( .A(n2747), .B(n2746), .Y(n2748) );
OR2X6TS U1149 ( .A(n3278), .B(beg_FSM), .Y(n2581) );
MX2X4TS U1150 ( .A(Data_MY[3]), .B(n3112), .S0(n2795), .Y(mult_x_19_n1791)
);
MX2X4TS U1151 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n2802), .Y(mult_x_19_n723)
);
MX2X4TS U1152 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n2791), .Y(n344) );
MX2X4TS U1153 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n2568), .Y(n358) );
INVX2TS U1154 ( .A(n2773), .Y(n2775) );
INVX6TS U1155 ( .A(n1256), .Y(n1230) );
NOR2X2TS U1156 ( .A(n2799), .B(n998), .Y(n1485) );
MX2X4TS U1157 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n2791), .Y(n346) );
CLKMX2X3TS U1158 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n2795), .Y(n343) );
INVX3TS U1159 ( .A(n748), .Y(n2759) );
MX2X6TS U1160 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n2568), .Y(n357) );
INVX2TS U1161 ( .A(n1470), .Y(n1459) );
NAND3X1TS U1162 ( .A(n2723), .B(n3356), .C(FSM_selector_B_1_), .Y(n1374) );
MX2X4TS U1163 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n2263), .Y(mult_x_19_n7)
);
MX2X4TS U1164 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n2791), .Y(
mult_x_19_n593) );
CLKMX2X3TS U1165 ( .A(n2583), .B(Add_result[1]), .S0(n2723), .Y(n308) );
NOR2X8TS U1166 ( .A(n2855), .B(n2587), .Y(n2839) );
CLKMX2X3TS U1167 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n2795), .Y(n381) );
ADDFHX2TS U1168 ( .A(n2238), .B(n1516), .CI(n1515), .CO(n1600), .S(n1521) );
CLKMX2X3TS U1169 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n2795), .Y(n335) );
MX2X4TS U1170 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n2568), .Y(n362) );
MX2X4TS U1171 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n2263), .Y(n350) );
MX2X4TS U1172 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n2795), .Y(n312) );
MX2X4TS U1173 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n2263), .Y(n356) );
MX2X4TS U1174 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n2263), .Y(n353) );
MX2X4TS U1175 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n2568), .Y(n366) );
ADDHX2TS U1176 ( .A(n1069), .B(n1070), .CO(n1084), .S(n1071) );
MX2X4TS U1177 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n2791), .Y(
mult_x_19_n1773) );
MX2X4TS U1178 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n2802), .Y(
mult_x_19_n633) );
CLKMX2X4TS U1179 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n2791), .Y(
mult_x_19_n611) );
CLKMX2X3TS U1180 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n2800), .Y(n338) );
CLKMX2X2TS U1181 ( .A(n2826), .B(zero_flag), .S0(n3356), .Y(n311) );
BUFX8TS U1182 ( .A(n2799), .Y(n777) );
CLKMX2X3TS U1183 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n2798), .Y(n374) );
CLKMX2X3TS U1184 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n2798), .Y(n373) );
CLKMX2X3TS U1185 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n2798), .Y(n372) );
CLKMX2X3TS U1186 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n2798), .Y(n371) );
CLKMX2X3TS U1187 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n2800), .Y(n370) );
CLKMX2X3TS U1188 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n2800), .Y(n369) );
CLKMX2X3TS U1189 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n2800), .Y(n368) );
ADDFHX2TS U1190 ( .A(n1566), .B(n1564), .CI(n1565), .CO(n2402), .S(n1574) );
CLKMX2X3TS U1191 ( .A(Data_MY[12]), .B(n646), .S0(n2802), .Y(n324) );
MX2X4TS U1192 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n2802), .Y(
mult_x_19_n689) );
CLKMX2X3TS U1193 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n2800), .Y(n341) );
CLKMX2X3TS U1194 ( .A(Data_MY[11]), .B(n601), .S0(n2802), .Y(n323) );
CLKMX2X3TS U1195 ( .A(Data_MY[1]), .B(n736), .S0(n2795), .Y(n313) );
CLKMX2X3TS U1196 ( .A(Data_MY[15]), .B(n781), .S0(n2802), .Y(n327) );
BUFX20TS U1197 ( .A(n1003), .Y(n425) );
CLKMX2X3TS U1198 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n2800), .Y(n337) );
CLKMX2X3TS U1199 ( .A(Data_MY[7]), .B(n673), .S0(n2802), .Y(n319) );
CLKMX2X3TS U1200 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n2800), .Y(n340) );
CLKMX2X3TS U1201 ( .A(Data_MY[13]), .B(n686), .S0(n2802), .Y(n325) );
CLKMX2X3TS U1202 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n2800), .Y(n339) );
CLKMX2X3TS U1203 ( .A(Data_MY[6]), .B(n691), .S0(n2802), .Y(n318) );
BUFX12TS U1204 ( .A(n2797), .Y(n2802) );
BUFX16TS U1205 ( .A(n2797), .Y(n2263) );
BUFX16TS U1206 ( .A(n2797), .Y(n2568) );
INVX2TS U1207 ( .A(n661), .Y(n1989) );
NOR2X1TS U1208 ( .A(n2719), .B(n2736), .Y(n2712) );
NOR2X1TS U1209 ( .A(n2719), .B(n2718), .Y(n2720) );
XNOR2X2TS U1210 ( .A(n2195), .B(n2955), .Y(n2196) );
NOR2X6TS U1211 ( .A(n2741), .B(n2753), .Y(n748) );
NAND2BX2TS U1212 ( .AN(ack_FSM), .B(ready), .Y(n2582) );
INVX12TS U1213 ( .A(n770), .Y(n771) );
INVX12TS U1214 ( .A(n666), .Y(n505) );
INVX12TS U1215 ( .A(n1651), .Y(n426) );
NAND2X4TS U1216 ( .A(n509), .B(n744), .Y(n929) );
BUFX16TS U1217 ( .A(n2797), .Y(n2791) );
BUFX8TS U1218 ( .A(n2797), .Y(n2795) );
INVX2TS U1219 ( .A(n2552), .Y(n515) );
INVX2TS U1220 ( .A(n1793), .Y(n851) );
NAND2X4TS U1221 ( .A(n1195), .B(FS_Module_state_reg[1]), .Y(n1175) );
NAND2X6TS U1222 ( .A(n652), .B(n653), .Y(n1354) );
BUFX12TS U1223 ( .A(n1176), .Y(n1921) );
NAND2X1TS U1224 ( .A(n2213), .B(n1364), .Y(n853) );
NAND2X6TS U1225 ( .A(n609), .B(n610), .Y(n1342) );
INVX1TS U1226 ( .A(n2258), .Y(n2259) );
AND2X2TS U1227 ( .A(n2769), .B(n2695), .Y(n2696) );
INVX4TS U1228 ( .A(n2734), .Y(n2719) );
INVX4TS U1229 ( .A(n2769), .Y(n2741) );
NAND2X4TS U1230 ( .A(n2264), .B(n1363), .Y(n3356) );
NAND2X8TS U1231 ( .A(n2213), .B(n2264), .Y(n2797) );
NAND2X6TS U1232 ( .A(n447), .B(n446), .Y(n2235) );
INVX2TS U1233 ( .A(n2641), .Y(n2644) );
OA21X4TS U1234 ( .A0(n1932), .A1(n1924), .B0(n1933), .Y(n1188) );
INVX3TS U1235 ( .A(n1269), .Y(n1247) );
AOI2BB1X2TS U1236 ( .A0N(round_mode[0]), .A1N(round_mode[1]), .B0(n2212),
.Y(n965) );
INVX3TS U1237 ( .A(n1319), .Y(n980) );
INVX8TS U1238 ( .A(n550), .Y(n551) );
NOR2X1TS U1239 ( .A(n2593), .B(Sgf_normalized_result[2]), .Y(n2594) );
INVX6TS U1240 ( .A(n1497), .Y(n1208) );
INVX4TS U1241 ( .A(underflow_flag), .Y(n3358) );
INVX2TS U1242 ( .A(n2716), .Y(n2717) );
INVX2TS U1243 ( .A(n1545), .Y(n1538) );
NOR2X1TS U1244 ( .A(n2729), .B(n2728), .Y(n2730) );
INVX2TS U1245 ( .A(n1925), .Y(n1654) );
NOR2X1TS U1246 ( .A(n2765), .B(n2763), .Y(n2749) );
NOR2X1TS U1247 ( .A(n2753), .B(n2694), .Y(n2695) );
NOR2X4TS U1248 ( .A(n2584), .B(n3120), .Y(n2585) );
INVX2TS U1249 ( .A(n1658), .Y(n1659) );
NAND2X6TS U1250 ( .A(n2264), .B(n2577), .Y(n3361) );
INVX2TS U1251 ( .A(n2642), .Y(n2643) );
INVX2TS U1252 ( .A(n1663), .Y(n1665) );
NAND2X2TS U1253 ( .A(n1193), .B(n1198), .Y(n1194) );
NAND2X4TS U1254 ( .A(n491), .B(n2241), .Y(n1016) );
NAND2X6TS U1255 ( .A(n898), .B(mult_x_19_n4), .Y(n738) );
CLKMX2X2TS U1256 ( .A(round_mode[1]), .B(round_mode[0]), .S0(n2830), .Y(
n2212) );
INVX8TS U1257 ( .A(n2686), .Y(n1228) );
OA21X4TS U1258 ( .A0(n2197), .A1(n3026), .B0(n3027), .Y(n1004) );
NAND2X6TS U1259 ( .A(n1059), .B(n2068), .Y(n662) );
INVX2TS U1260 ( .A(n1854), .Y(n2003) );
CLKINVX6TS U1261 ( .A(n2114), .Y(n428) );
INVX2TS U1262 ( .A(n2117), .Y(n1999) );
NOR2X4TS U1263 ( .A(FS_Module_state_reg[1]), .B(n1938), .Y(n2577) );
INVX2TS U1264 ( .A(n1475), .Y(n1476) );
NAND2X6TS U1265 ( .A(n1182), .B(n578), .Y(n1658) );
INVX12TS U1266 ( .A(n521), .Y(n1642) );
NOR4X2TS U1267 ( .A(n246), .B(n245), .C(P_Sgf[5]), .D(P_Sgf[6]), .Y(n2210)
);
INVX2TS U1268 ( .A(n1197), .Y(n2646) );
INVX6TS U1269 ( .A(n740), .Y(n685) );
NAND3X4TS U1270 ( .A(n3170), .B(n3169), .C(n3168), .Y(n2844) );
NOR2X4TS U1271 ( .A(n568), .B(n2965), .Y(n2660) );
MX2X2TS U1272 ( .A(n3220), .B(n3219), .S0(n3218), .Y(n310) );
NAND3X4TS U1273 ( .A(n3203), .B(n3202), .C(n3201), .Y(n2840) );
BUFX16TS U1274 ( .A(n626), .Y(n870) );
INVX4TS U1275 ( .A(n654), .Y(n655) );
NAND2X4TS U1276 ( .A(n2995), .B(n2996), .Y(n1732) );
INVX6TS U1277 ( .A(n623), .Y(n624) );
NAND3X4TS U1278 ( .A(n3175), .B(n3174), .C(n3173), .Y(n2848) );
INVX2TS U1279 ( .A(Add_result[1]), .Y(n1995) );
NAND2X2TS U1280 ( .A(n580), .B(n3028), .Y(n1198) );
NAND3X4TS U1281 ( .A(n3194), .B(n3193), .C(n3192), .Y(n2836) );
INVX2TS U1282 ( .A(Op_MY[18]), .Y(n2809) );
NAND3X4TS U1283 ( .A(n3209), .B(n3208), .C(n3207), .Y(n2841) );
NAND3X4TS U1284 ( .A(n3215), .B(n3214), .C(n3213), .Y(n2846) );
NAND2X2TS U1285 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n2578) );
NAND3X4TS U1286 ( .A(n3188), .B(n3187), .C(n3186), .Y(n2837) );
OR2X6TS U1287 ( .A(n3024), .B(n572), .Y(n2659) );
AOI21X2TS U1288 ( .A0(n2667), .A1(n2666), .B0(n408), .Y(n2668) );
OR2X8TS U1289 ( .A(n1207), .B(n1206), .Y(n616) );
AOI21X4TS U1290 ( .A0(n2252), .A1(n584), .B0(n571), .Y(n1487) );
NAND2X8TS U1291 ( .A(n1218), .B(n431), .Y(n2252) );
NAND2BX2TS U1292 ( .AN(n2211), .B(n2207), .Y(n967) );
OAI2BB1X4TS U1293 ( .A0N(n1000), .A1N(n1931), .B0(n1930), .Y(n1936) );
XNOR2X4TS U1294 ( .A(n644), .B(n2904), .Y(n1682) );
INVX16TS U1295 ( .A(n2892), .Y(n2237) );
OAI21X4TS U1296 ( .A0(n2296), .A1(n2295), .B0(n2294), .Y(n874) );
OAI21X4TS U1297 ( .A0(n2348), .A1(n2349), .B0(n2347), .Y(n538) );
NAND2X2TS U1298 ( .A(n2422), .B(n2423), .Y(n436) );
OAI22X2TS U1299 ( .A0(n767), .A1(n2036), .B0(n2035), .B1(n2034), .Y(n2098)
);
INVX12TS U1300 ( .A(n2894), .Y(n2013) );
XOR2X4TS U1301 ( .A(n2894), .B(n2221), .Y(n1692) );
NAND2X4TS U1302 ( .A(n2257), .B(n2537), .Y(mult_x_19_n82) );
BUFX20TS U1303 ( .A(n1814), .Y(n500) );
NAND2BX2TS U1304 ( .AN(n914), .B(n1892), .Y(n912) );
OAI21X4TS U1305 ( .A0(n1466), .A1(n1465), .B0(n1464), .Y(n1467) );
OAI22X2TS U1306 ( .A0(n466), .A1(n2048), .B0(n1806), .B1(n2051), .Y(n1805)
);
XNOR2X4TS U1307 ( .A(n492), .B(n2907), .Y(n466) );
NAND2BX4TS U1308 ( .AN(n420), .B(n3239), .Y(n438) );
OAI22X4TS U1309 ( .A0(n2051), .A1(n2050), .B0(n2049), .B1(n2048), .Y(n2086)
);
OAI22X4TS U1310 ( .A0(n1164), .A1(n756), .B0(n1116), .B1(n1796), .Y(n1156)
);
INVX6TS U1311 ( .A(n2122), .Y(n2124) );
OAI21X4TS U1312 ( .A0(n1728), .A1(n1727), .B0(n1726), .Y(n872) );
NOR2X8TS U1313 ( .A(n2621), .B(n430), .Y(n2641) );
NOR2BX4TS U1314 ( .AN(n440), .B(n2988), .Y(n2621) );
XNOR2X4TS U1315 ( .A(n443), .B(n2672), .Y(n442) );
OAI21X4TS U1316 ( .A0(n766), .A1(n2669), .B0(n2668), .Y(n443) );
INVX12TS U1317 ( .A(n2905), .Y(n1807) );
OAI21X4TS U1318 ( .A0(n714), .A1(n2793), .B0(n444), .Y(n1808) );
NAND2X2TS U1319 ( .A(n696), .B(n2905), .Y(n444) );
OAI21X4TS U1320 ( .A0(n1732), .A1(n1733), .B0(n1734), .Y(n2642) );
XOR2X4TS U1321 ( .A(n2235), .B(n887), .Y(n886) );
OAI22X4TS U1322 ( .A0(n1759), .A1(n804), .B0(n2224), .B1(n2223), .Y(n887) );
XOR2X4TS U1323 ( .A(n2894), .B(n762), .Y(n2224) );
XNOR2X4TS U1324 ( .A(n688), .B(n654), .Y(n899) );
OR2X8TS U1325 ( .A(n2240), .B(n734), .Y(n447) );
XNOR2X4TS U1326 ( .A(n688), .B(n1869), .Y(n2240) );
OAI21X4TS U1327 ( .A0(n2387), .A1(n450), .B0(n2386), .Y(n449) );
XNOR2X4TS U1328 ( .A(n451), .B(n2386), .Y(n2407) );
XOR2X4TS U1329 ( .A(n2387), .B(n452), .Y(n451) );
NOR2X8TS U1330 ( .A(n454), .B(n453), .Y(n452) );
XNOR2X4TS U1331 ( .A(n457), .B(n1499), .Y(n456) );
OAI21X4TS U1332 ( .A0(n765), .A1(n459), .B0(n458), .Y(n457) );
AOI21X4TS U1333 ( .A0(n2667), .A1(n1496), .B0(n1495), .Y(n458) );
NAND2X2TS U1334 ( .A(n2661), .B(n1496), .Y(n459) );
XOR2X4TS U1335 ( .A(n2894), .B(n671), .Y(n1759) );
AOI21X4TS U1336 ( .A0(mult_x_19_n453), .A1(n3101), .B0(n697), .Y(n2913) );
OAI21X4TS U1337 ( .A0(n1764), .A1(n1765), .B0(n1763), .Y(n952) );
OAI22X4TS U1338 ( .A0(n1108), .A1(n804), .B0(n460), .B1(n2223), .Y(n1153) );
OAI22X4TS U1339 ( .A0(n1693), .A1(n2314), .B0(n460), .B1(n838), .Y(n546) );
XOR2X4TS U1340 ( .A(n2894), .B(n2793), .Y(n460) );
NAND2X8TS U1341 ( .A(n707), .B(n3101), .Y(mult_x_19_n439) );
NOR2X8TS U1342 ( .A(n1971), .B(n1970), .Y(n461) );
NOR2X8TS U1343 ( .A(n1965), .B(n1964), .Y(n462) );
BUFX12TS U1344 ( .A(n758), .Y(n464) );
XOR2X4TS U1345 ( .A(n2904), .B(n465), .Y(n1099) );
OAI22X4TS U1346 ( .A0(n2051), .A1(n466), .B0(n1786), .B1(n499), .Y(n1789) );
OAI2BB1X4TS U1347 ( .A0N(n2018), .A1N(n469), .B0(n467), .Y(n1791) );
OAI21X4TS U1348 ( .A0(n2018), .A1(n469), .B0(n2017), .Y(n467) );
XOR2X4TS U1349 ( .A(n468), .B(n2017), .Y(n2088) );
XOR2X4TS U1350 ( .A(n2018), .B(n469), .Y(n468) );
OAI22X4TS U1351 ( .A0(n678), .A1(n2016), .B0(n2322), .B1(n1772), .Y(n469) );
NAND2X8TS U1352 ( .A(mult_x_19_n52), .B(n470), .Y(n1283) );
XOR2X4TS U1353 ( .A(n625), .B(n618), .Y(n470) );
OAI21X4TS U1354 ( .A0(n766), .A1(n1484), .B0(n820), .Y(n473) );
NAND2X8TS U1355 ( .A(n471), .B(n3252), .Y(n2628) );
XOR2X4TS U1356 ( .A(n473), .B(n2917), .Y(n472) );
NAND2X8TS U1357 ( .A(n474), .B(n1004), .Y(n480) );
NAND2X6TS U1358 ( .A(n1006), .B(n2115), .Y(n481) );
NAND4X8TS U1359 ( .A(n477), .B(n1188), .C(n475), .D(n482), .Y(n2670) );
NAND3X8TS U1360 ( .A(n426), .B(n476), .C(n1931), .Y(n475) );
NAND3X8TS U1361 ( .A(n479), .B(n416), .C(n481), .Y(n1931) );
OR2X8TS U1362 ( .A(n1632), .B(n478), .Y(n477) );
NAND2X8TS U1363 ( .A(n1921), .B(n1189), .Y(n478) );
AOI21X4TS U1364 ( .A0(n1988), .A1(n1181), .B0(n1180), .Y(n1632) );
NAND2X8TS U1365 ( .A(n1987), .B(n1181), .Y(n1651) );
OAI21X4TS U1366 ( .A0(n715), .A1(n671), .B0(n483), .Y(n2156) );
NAND2X8TS U1367 ( .A(n486), .B(n422), .Y(n939) );
OR2X8TS U1368 ( .A(n1080), .B(n1079), .Y(n1525) );
NAND2X1TS U1369 ( .A(n1051), .B(n1050), .Y(n2608) );
NAND3X2TS U1370 ( .A(n1049), .B(n1048), .C(n1050), .Y(n489) );
NOR2X8TS U1371 ( .A(n2607), .B(n2605), .Y(n1053) );
CLKINVX6TS U1372 ( .A(n2904), .Y(n491) );
OAI2BB1X4TS U1373 ( .A0N(n2107), .A1N(n2106), .B0(n493), .Y(mult_x_19_n763)
);
OAI21X4TS U1374 ( .A0(n2106), .A1(n2107), .B0(n2105), .Y(n493) );
OAI21X4TS U1375 ( .A0(n2298), .A1(n2299), .B0(n2297), .Y(n494) );
NAND2BX4TS U1376 ( .AN(n967), .B(n496), .Y(n966) );
NOR3X6TS U1377 ( .A(n260), .B(P_Sgf[0]), .C(n259), .Y(n496) );
OAI22X4TS U1378 ( .A0(n543), .A1(n2048), .B0(n1684), .B1(n1300), .Y(n1688)
);
XNOR2X4TS U1379 ( .A(n2237), .B(n2793), .Y(n543) );
OAI21X4TS U1380 ( .A0(n1782), .A1(n1781), .B0(n891), .Y(n889) );
NOR2X4TS U1381 ( .A(n2579), .B(n2578), .Y(ready) );
OAI21X2TS U1382 ( .A0(n3354), .A1(n3119), .B0(FS_Module_state_reg[3]), .Y(
n2790) );
BUFX12TS U1383 ( .A(n797), .Y(n497) );
XNOR2X4TS U1384 ( .A(n867), .B(n1761), .Y(n1164) );
XOR2X4TS U1385 ( .A(n630), .B(n621), .Y(n1705) );
OAI22X4TS U1386 ( .A0(n2309), .A1(n2310), .B0(n2308), .B1(n2307), .Y(n2364)
);
NAND4BX4TS U1387 ( .AN(n423), .B(n1447), .C(n1968), .D(n2192), .Y(n1480) );
NAND2X8TS U1388 ( .A(n854), .B(n3253), .Y(n2640) );
XOR2X4TS U1389 ( .A(n2422), .B(n2423), .Y(n931) );
AOI21X4TS U1390 ( .A0(n1469), .A1(n1461), .B0(n1463), .Y(n1399) );
OAI21X4TS U1391 ( .A0(n504), .A1(n586), .B0(n503), .Y(n262) );
XOR2X4TS U1392 ( .A(n1994), .B(n1993), .Y(n504) );
INVX16TS U1393 ( .A(n1283), .Y(n675) );
NAND3X4TS U1394 ( .A(n2614), .B(n2613), .C(n2612), .Y(n202) );
OAI22X4TS U1395 ( .A0(n2151), .A1(n1289), .B0(n1282), .B1(n505), .Y(n1286)
);
NAND2X8TS U1396 ( .A(n506), .B(n744), .Y(n918) );
XOR2X4TS U1397 ( .A(n635), .B(n759), .Y(n506) );
OAI2BB1X4TS U1398 ( .A0N(n1298), .A1N(n1297), .B0(n507), .Y(n611) );
OAI21X4TS U1399 ( .A0(n1297), .A1(n1298), .B0(n1296), .Y(n507) );
XOR2X4TS U1400 ( .A(n508), .B(n1291), .Y(n1296) );
XOR2X4TS U1401 ( .A(n1290), .B(n941), .Y(n508) );
OAI22X4TS U1402 ( .A0(n1308), .A1(n548), .B0(n555), .B1(n2947), .Y(n941) );
XNOR2X4TS U1403 ( .A(n3095), .B(n511), .Y(n1513) );
OAI22X4TS U1404 ( .A0(n505), .A1(n991), .B0(n2151), .B1(n1543), .Y(n1554) );
OAI22X4TS U1405 ( .A0(n1556), .A1(n2151), .B0(n509), .B1(n1543), .Y(n1565)
);
OAI22X4TS U1406 ( .A0(n1556), .A1(n505), .B0(n2151), .B1(n2484), .Y(n518) );
OAI22X4TS U1407 ( .A0(n1504), .A1(n2151), .B0(n509), .B1(n2483), .Y(n2467)
);
OAI22X4TS U1408 ( .A0(n2152), .A1(n2151), .B0(n505), .B1(n2153), .Y(n922) );
OAI22X4TS U1409 ( .A0(n726), .A1(n970), .B0(n509), .B1(n2038), .Y(n2097) );
OAI22X4TS U1410 ( .A0(n1597), .A1(n970), .B0(n1513), .B1(n509), .Y(n1596) );
OAI22X4TS U1411 ( .A0(n744), .A1(n510), .B0(n505), .B1(n1779), .Y(n1833) );
XOR2X4TS U1412 ( .A(n867), .B(n511), .Y(n510) );
INVX12TS U1413 ( .A(n791), .Y(n511) );
XOR2X4TS U1414 ( .A(n2182), .B(n512), .Y(n2169) );
XOR2X4TS U1415 ( .A(n2183), .B(n2184), .Y(n512) );
INVX2TS U1416 ( .A(n518), .Y(n516) );
XOR2X4TS U1417 ( .A(n2552), .B(n518), .Y(n517) );
NAND2X4TS U1418 ( .A(n2348), .B(n2349), .Y(n537) );
NOR2X8TS U1419 ( .A(n520), .B(n1215), .Y(n1217) );
NOR2X2TS U1420 ( .A(n1940), .B(n520), .Y(n1845) );
OAI21X1TS U1421 ( .A0(n1948), .A1(n520), .B0(n558), .Y(n1844) );
NAND2X8TS U1422 ( .A(n2655), .B(n616), .Y(n520) );
OR2X8TS U1423 ( .A(n2971), .B(n577), .Y(n521) );
AOI21X4TS U1424 ( .A0(n1498), .A1(n1209), .B0(n1208), .Y(n1210) );
NAND2X4TS U1425 ( .A(n1206), .B(n1207), .Y(n1497) );
NAND2BX4TS U1426 ( .AN(n1207), .B(n522), .Y(n1498) );
CLKINVX6TS U1427 ( .A(n1206), .Y(n522) );
OAI22X4TS U1428 ( .A0(n406), .A1(n1054), .B0(n556), .B1(n942), .Y(n1065) );
OAI22X4TS U1429 ( .A0(n523), .A1(n1033), .B0(n553), .B1(n1027), .Y(n1042) );
OAI22X4TS U1430 ( .A0(n1111), .A1(n523), .B0(n556), .B1(n1110), .Y(n1112) );
OAI22X4TS U1431 ( .A0(n1111), .A1(n553), .B0(n523), .B1(n1102), .Y(n1127) );
AND2X8TS U1432 ( .A(n1078), .B(n1077), .Y(n1523) );
OR2X6TS U1433 ( .A(n988), .B(n525), .Y(n708) );
NAND2X2TS U1434 ( .A(n988), .B(n525), .Y(n987) );
OAI22X4TS U1435 ( .A0(n764), .A1(n992), .B0(n993), .B1(n1674), .Y(n525) );
AOI2BB2X4TS U1436 ( .B0(n2638), .B1(n2700), .A0N(n806), .A1N(n3122), .Y(
n3290) );
XOR2X4TS U1437 ( .A(n530), .B(n2919), .Y(n529) );
OAI21X4TS U1438 ( .A0(n766), .A1(n1221), .B0(n1220), .Y(n530) );
OAI21X4TS U1439 ( .A0(n3098), .A1(n870), .B0(n715), .Y(n1295) );
OAI21X4TS U1440 ( .A0(n1663), .A1(n1658), .B0(n1664), .Y(n1923) );
NOR2X8TS U1441 ( .A(n1184), .B(n1183), .Y(n1663) );
XOR2X4TS U1442 ( .A(n2890), .B(n2801), .Y(n894) );
AOI2BB2X4TS U1443 ( .B0(n2680), .B1(n1483), .A0N(n807), .A1N(n3133), .Y(
n3339) );
XNOR2X4TS U1444 ( .A(n533), .B(n1194), .Y(n532) );
OAI21X4TS U1445 ( .A0(n766), .A1(n1192), .B0(n1191), .Y(n533) );
NOR2X8TS U1446 ( .A(n1186), .B(n1185), .Y(n1925) );
NAND2X8TS U1447 ( .A(n1482), .B(FS_Module_state_reg[1]), .Y(n2799) );
OAI2BB1X4TS U1448 ( .A0N(n2354), .A1N(n2353), .B0(n536), .Y(n2359) );
OAI21X4TS U1449 ( .A0(n2353), .A1(n2354), .B0(n857), .Y(n536) );
NAND2X6TS U1450 ( .A(n538), .B(n537), .Y(n857) );
XNOR2X4TS U1451 ( .A(n539), .B(n2378), .Y(n620) );
XNOR2X4TS U1452 ( .A(n2377), .B(n2379), .Y(n539) );
XOR2X4TS U1453 ( .A(n540), .B(n2189), .Y(n920) );
NAND2X8TS U1454 ( .A(n822), .B(n846), .Y(n540) );
OAI22X4TS U1455 ( .A0(n783), .A1(n541), .B0(n1883), .B1(n2479), .Y(n1892) );
OAI22X4TS U1456 ( .A0(n783), .A1(n975), .B0(n2479), .B1(n541), .Y(n1291) );
XOR2X4TS U1457 ( .A(n398), .B(n542), .Y(n541) );
OAI22X4TS U1458 ( .A0(n1704), .A1(n2307), .B0(n437), .B1(n543), .Y(n1709) );
OAI21X4TS U1459 ( .A0(n1690), .A1(n1691), .B0(n546), .Y(n545) );
XOR2X4TS U1460 ( .A(n547), .B(n546), .Y(n1909) );
XOR2X4TS U1461 ( .A(n1690), .B(n1691), .Y(n547) );
XNOR2X4TS U1462 ( .A(n706), .B(n839), .Y(n944) );
OAI2BB1X1TS U1463 ( .A0N(n658), .A1N(n1898), .B0(n946), .Y(mult_x_19_n853)
);
ADDHX4TS U1464 ( .A(n1357), .B(n1358), .CO(n1312), .S(n2301) );
OAI21X4TS U1465 ( .A0(n1306), .A1(n667), .B0(n923), .Y(n1358) );
INVX6TS U1466 ( .A(n1305), .Y(n924) );
NOR2BX4TS U1467 ( .AN(n789), .B(n2485), .Y(n1154) );
NAND2X4TS U1468 ( .A(n1008), .B(n1007), .Y(n1178) );
CLKINVX6TS U1469 ( .A(n1500), .Y(n550) );
OAI22X2TS U1470 ( .A0(n804), .A1(n1675), .B0(n1759), .B1(n590), .Y(n1757) );
OAI22X2TS U1471 ( .A0(n804), .A1(n2224), .B0(n2321), .B1(n2314), .Y(n2368)
);
XNOR2X4TS U1472 ( .A(n2052), .B(n671), .Y(n1117) );
NOR2X6TS U1473 ( .A(n562), .B(n966), .Y(n860) );
AOI21X4TS U1474 ( .A0(n2671), .A1(n1202), .B0(n3100), .Y(n1203) );
CLKINVX12TS U1475 ( .A(n862), .Y(n554) );
ADDFHX2TS U1476 ( .A(n1902), .B(n1901), .CI(n1900), .CO(mult_x_19_n851), .S(
mult_x_19_n852) );
OR2X4TS U1477 ( .A(n970), .B(n2153), .Y(n557) );
NAND2X8TS U1478 ( .A(n417), .B(n557), .Y(n2160) );
INVX2TS U1479 ( .A(n1987), .Y(n1990) );
NOR2X6TS U1480 ( .A(n2108), .B(n1179), .Y(n1987) );
AOI21X4TS U1481 ( .A0(n1209), .A1(n1498), .B0(n1208), .Y(n558) );
XNOR2X4TS U1482 ( .A(n2898), .B(n839), .Y(n1714) );
XNOR2X4TS U1483 ( .A(n1372), .B(n421), .Y(n1373) );
NAND2X4TS U1484 ( .A(n850), .B(n849), .Y(n2012) );
OAI21X2TS U1485 ( .A0(n2112), .A1(n1641), .B0(n1640), .Y(n1645) );
AOI21X2TS U1486 ( .A0(n661), .A1(n1992), .B0(n1639), .Y(n1640) );
ADDFHX4TS U1487 ( .A(n1725), .B(n1724), .CI(n1723), .CO(n1717), .S(n1911) );
NAND2BX2TS U1488 ( .AN(n613), .B(n561), .Y(n560) );
BUFX16TS U1489 ( .A(mult_x_19_n58), .Y(n855) );
OAI22X4TS U1490 ( .A0(n1714), .A1(n790), .B0(mult_x_19_n1687), .B1(n1813),
.Y(n1724) );
OAI22X4TS U1491 ( .A0(n2055), .A1(n1713), .B0(n1712), .B1(n1014), .Y(n1725)
);
OAI22X4TS U1492 ( .A0(n803), .A1(n2321), .B0(n2320), .B1(n2223), .Y(n2387)
);
OAI22X2TS U1493 ( .A0(n760), .A1(n2326), .B0(n2325), .B1(n1674), .Y(n2386)
);
NAND2X4TS U1494 ( .A(mult_x_19_n995), .B(mult_x_19_n1010), .Y(mult_x_19_n418) );
NAND2X4TS U1495 ( .A(n572), .B(n3003), .Y(n2662) );
OAI21X1TS U1496 ( .A0(n583), .A1(n575), .B0(n3029), .Y(n1212) );
NOR2X6TS U1497 ( .A(n1182), .B(n578), .Y(n1634) );
XNOR2X1TS U1498 ( .A(n582), .B(n2993), .Y(n2205) );
NAND2X2TS U1499 ( .A(n1534), .B(n583), .Y(n1535) );
NAND2X1TS U1500 ( .A(n584), .B(n3048), .Y(n1918) );
XOR2X4TS U1501 ( .A(n765), .B(n2623), .Y(n2624) );
CLKMX2X2TS U1502 ( .A(n3228), .B(n3227), .S0(n588), .Y(n246) );
CLKMX2X2TS U1503 ( .A(n3172), .B(n3171), .S0(n588), .Y(n245) );
CLKMX2X4TS U1504 ( .A(n1860), .B(n3238), .S0(n589), .Y(n257) );
CLKMX2X2TS U1505 ( .A(n2200), .B(n3236), .S0(n589), .Y(n254) );
CLKMX2X2TS U1506 ( .A(n2005), .B(n3235), .S0(n589), .Y(n256) );
CLKMX2X2TS U1507 ( .A(n2009), .B(n3233), .S0(n589), .Y(n255) );
CLKMX2X2TS U1508 ( .A(n1013), .B(n3241), .S0(n589), .Y(n261) );
CLKMX2X4TS U1509 ( .A(n2002), .B(n3249), .S0(n589), .Y(n258) );
NAND2X4TS U1510 ( .A(n2534), .B(n2533), .Y(mult_x_19_n198) );
NAND2X2TS U1511 ( .A(mult_x_19_n764), .B(n1187), .Y(n1933) );
NOR2X6TS U1512 ( .A(n2985), .B(n2986), .Y(n1941) );
NAND2X1TS U1513 ( .A(n2622), .B(n1732), .Y(n2623) );
OAI21X4TS U1514 ( .A0(n765), .A1(n2621), .B0(n1732), .Y(n1737) );
INVX2TS U1515 ( .A(n2621), .Y(n2622) );
XNOR2X4TS U1516 ( .A(n2237), .B(n732), .Y(n1822) );
XOR2X4TS U1517 ( .A(n692), .B(n2237), .Y(n945) );
XNOR2X4TS U1518 ( .A(n2237), .B(n650), .Y(n1806) );
INVX4TS U1519 ( .A(n650), .Y(n651) );
OAI22X4TS U1520 ( .A0(n1300), .A1(n2308), .B0(mult_x_19_n1635), .B1(n2307),
.Y(n2336) );
OR2X4TS U1521 ( .A(n1684), .B(n2048), .Y(n746) );
XNOR2X4TS U1522 ( .A(n706), .B(n671), .Y(n2309) );
INVX4TS U1523 ( .A(n355), .Y(n3046) );
NAND2BX2TS U1524 ( .AN(n2904), .B(n706), .Y(n1100) );
CLKINVX12TS U1525 ( .A(mult_x_19_n28), .Y(n592) );
XOR2X2TS U1526 ( .A(n2943), .B(n352), .Y(n591) );
XNOR2X4TS U1527 ( .A(mult_x_19_n19), .B(n352), .Y(n2937) );
OAI2BB2X2TS U1528 ( .B0(n594), .B1(n705), .A0N(n592), .A1N(n593), .Y(n2157)
);
BUFX16TS U1529 ( .A(n804), .Y(n838) );
OAI22X4TS U1530 ( .A0(n803), .A1(n1821), .B0(n590), .B1(n445), .Y(n2149) );
OAI2BB1X1TS U1531 ( .A0N(n594), .A1N(n2314), .B0(n593), .Y(n1585) );
OAI22X4TS U1532 ( .A0(n1685), .A1(n785), .B0(n1705), .B1(n555), .Y(n1679) );
OAI22X4TS U1533 ( .A0(n1019), .A1(n406), .B0(n1054), .B1(n555), .Y(n1067) );
ADDFHX4TS U1534 ( .A(n2246), .B(n2245), .CI(n2244), .CO(n2377), .S(n1985) );
OAI2BB2X4TS U1535 ( .B0(n556), .B1(mult_x_19_n1749), .A0N(n704), .A1N(n897),
.Y(n1314) );
XNOR2X4TS U1536 ( .A(n878), .B(n881), .Y(n1867) );
BUFX20TS U1537 ( .A(n2895), .Y(n878) );
BUFX4TS U1538 ( .A(n1861), .Y(n682) );
XOR2X2TS U1539 ( .A(n464), .B(n647), .Y(n1301) );
INVX16TS U1540 ( .A(n714), .Y(n2474) );
OAI21X4TS U1541 ( .A0(n766), .A1(n1629), .B0(n1628), .Y(n999) );
AOI21X2TS U1542 ( .A0(n2667), .A1(n1627), .B0(n1626), .Y(n1628) );
OAI22X4TS U1543 ( .A0(n1100), .A1(n499), .B0(n2891), .B1(n2051), .Y(n1120)
);
OAI22X4TS U1544 ( .A0(n2330), .A1(n2896), .B0(n2068), .B1(n1062), .Y(n1069)
);
OAI22X4TS U1545 ( .A0(n768), .A1(mult_x_19_n1603), .B0(n1819), .B1(n2034),
.Y(n1835) );
OAI21X4TS U1546 ( .A0(n766), .A1(n1952), .B0(n1951), .Y(n1954) );
OAI22X2TS U1547 ( .A0(n1807), .A1(n600), .B0(n715), .B1(n2908), .Y(n1549) );
OR2X6TS U1548 ( .A(n1713), .B(n1014), .Y(n730) );
OAI2BB2X4TS U1549 ( .B0(n769), .B1(n2332), .A0N(n602), .A1N(n608), .Y(n2337)
);
OAI22X2TS U1550 ( .A0(n743), .A1(n1819), .B0(n1818), .B1(n842), .Y(n2142) );
AND2X8TS U1551 ( .A(n939), .B(n938), .Y(n603) );
NAND2X2TS U1552 ( .A(n776), .B(n2677), .Y(n3329) );
INVX12TS U1553 ( .A(n735), .Y(n756) );
AOI2BB2X4TS U1554 ( .B0(n607), .B1(n608), .A0N(n986), .A1N(n742), .Y(n606)
);
OR2X4TS U1555 ( .A(n2314), .B(n1344), .Y(n610) );
NAND2X4TS U1556 ( .A(n3004), .B(n1005), .Y(n2123) );
AOI21X4TS U1557 ( .A0(n2121), .A1(n2114), .B0(n2115), .Y(n2001) );
NOR2X8TS U1558 ( .A(n1855), .B(n1854), .Y(n2114) );
NAND2X2TS U1559 ( .A(n2681), .B(n2677), .Y(n3330) );
INVX12TS U1560 ( .A(n759), .Y(n1281) );
NOR2X4TS U1561 ( .A(n1797), .B(n744), .Y(n643) );
ADDFHX4TS U1562 ( .A(n2376), .B(n2374), .CI(n2375), .CO(n2418), .S(n2381) );
OAI22X2TS U1563 ( .A0(n1762), .A1(n2240), .B0(n2306), .B1(n757), .Y(n2375)
);
ADDHX4TS U1564 ( .A(n1044), .B(n1045), .CO(n1046), .S(n1039) );
OAI22X4TS U1565 ( .A0(n1762), .A1(n1036), .B0(n1035), .B1(n757), .Y(n1044)
);
AND2X8TS U1566 ( .A(n936), .B(n933), .Y(n614) );
AO21X4TS U1567 ( .A0(n2598), .A1(n1053), .B0(n1052), .Y(n615) );
BUFX20TS U1568 ( .A(n1288), .Y(n2312) );
NAND2X8TS U1569 ( .A(n1015), .B(n1014), .Y(n1288) );
AOI21X2TS U1570 ( .A0(n2667), .A1(n1845), .B0(n1844), .Y(n1846) );
XOR2X4TS U1571 ( .A(n1859), .B(n1858), .Y(n1860) );
BUFX20TS U1572 ( .A(n698), .Y(n617) );
XNOR2X2TS U1573 ( .A(n464), .B(n755), .Y(n1786) );
XNOR2X2TS U1574 ( .A(n758), .B(n2476), .Y(n1345) );
XNOR2X2TS U1575 ( .A(n758), .B(n1869), .Y(n2050) );
OAI21X2TS U1576 ( .A0(n2146), .A1(n721), .B0(n2145), .Y(n720) );
NAND2X2TS U1577 ( .A(n2609), .B(n2608), .Y(n2610) );
AOI2BB2X2TS U1578 ( .B0(n2700), .B1(n2639), .A0N(n807), .A1N(n3124), .Y(
n3299) );
NAND2X4TS U1579 ( .A(n702), .B(n897), .Y(n896) );
ADDFHX4TS U1580 ( .A(n1590), .B(n1589), .CI(n1588), .CO(n1593), .S(n2174) );
ADDFHX2TS U1581 ( .A(n1086), .B(n1085), .CI(n1084), .CO(n1976), .S(n1094) );
XNOR2X4TS U1582 ( .A(n2052), .B(n691), .Y(n1083) );
OAI22X4TS U1583 ( .A0(n2318), .A1(n2306), .B0(n2317), .B1(n757), .Y(n2365)
);
ADDFHX4TS U1584 ( .A(n2305), .B(n2304), .CI(n2303), .CO(n2300), .S(n2423) );
NOR2X6TS U1585 ( .A(n1925), .B(n1932), .Y(n1189) );
NAND2XLTS U1586 ( .A(n616), .B(n1497), .Y(n1499) );
NOR2X8TS U1587 ( .A(n2969), .B(n1205), .Y(n1494) );
ADDFHX4TS U1588 ( .A(n1141), .B(n1140), .CI(n1139), .CO(n1134), .S(n1974) );
OAI22X2TS U1589 ( .A0(n1796), .A1(n1105), .B0(n1117), .B1(n734), .Y(n1139)
);
INVX16TS U1590 ( .A(n675), .Y(n677) );
OAI22X4TS U1591 ( .A0(n676), .A1(n1582), .B0(n799), .B1(n1552), .Y(n1587) );
OAI22X4TS U1592 ( .A0(n2041), .A1(n2039), .B0(n2015), .B1(n2479), .Y(n2043)
);
BUFX20TS U1593 ( .A(n783), .Y(n2041) );
MXI2X8TS U1594 ( .A(n1479), .B(n1478), .S0(n427), .Y(n1739) );
NOR2X4TS U1595 ( .A(n1376), .B(n1245), .Y(n1448) );
NAND2X2TS U1596 ( .A(n3118), .B(Op_MY[24]), .Y(n1227) );
INVX2TS U1597 ( .A(n991), .Y(n819) );
NAND2X2TS U1598 ( .A(n3118), .B(Op_MY[27]), .Y(n1224) );
NAND2X2TS U1599 ( .A(n3118), .B(Op_MY[28]), .Y(n1225) );
INVX2TS U1600 ( .A(n1366), .Y(n1369) );
CLKINVX12TS U1601 ( .A(n662), .Y(n901) );
INVX6TS U1602 ( .A(n686), .Y(n687) );
NOR2X2TS U1603 ( .A(FS_Module_state_reg[2]), .B(n3120), .Y(n1362) );
NAND2X2TS U1604 ( .A(n3118), .B(Op_MY[25]), .Y(n1233) );
ADDFHX2TS U1605 ( .A(n638), .B(n2796), .CI(n1808), .CO(n1803), .S(n2045) );
INVX2TS U1606 ( .A(n1463), .Y(n1466) );
NAND2X2TS U1607 ( .A(n1243), .B(n1265), .Y(n1244) );
NOR2X4TS U1608 ( .A(n1263), .B(n1264), .Y(n1387) );
NAND2X2TS U1609 ( .A(n3118), .B(Op_MY[29]), .Y(n1226) );
NOR2X4TS U1610 ( .A(n1246), .B(n1267), .Y(n1452) );
NAND2X4TS U1611 ( .A(n1254), .B(n1442), .Y(n1416) );
INVX2TS U1612 ( .A(n1411), .Y(n1413) );
NOR2X2TS U1613 ( .A(mult_x_19_n1678), .B(n790), .Y(n916) );
INVX2TS U1614 ( .A(n2182), .Y(n956) );
OAI21X2TS U1615 ( .A0(n970), .A1(n1607), .B0(n973), .Y(n1606) );
OAI22X2TS U1616 ( .A0(n990), .A1(n2055), .B0(n2311), .B1(n981), .Y(n2243) );
OAI22X2TS U1617 ( .A0(n769), .A1(n700), .B0(n2485), .B1(n894), .Y(n2302) );
NAND2X4TS U1618 ( .A(n1616), .B(n1615), .Y(n2286) );
NAND2X2TS U1619 ( .A(n929), .B(n969), .Y(n2561) );
NAND3X4TS U1620 ( .A(n1673), .B(n1672), .C(n1671), .Y(n206) );
NAND2X2TS U1621 ( .A(n2768), .B(n2754), .Y(n2756) );
INVX4TS U1622 ( .A(n1258), .Y(n1236) );
INVX2TS U1623 ( .A(n693), .Y(n694) );
NOR2X6TS U1624 ( .A(n667), .B(n2037), .Y(n642) );
OAI22X2TS U1625 ( .A0(n2051), .A1(n1301), .B0(n1345), .B1(n2048), .Y(n1287)
);
INVX2TS U1626 ( .A(n753), .Y(n657) );
INVX2TS U1627 ( .A(n2804), .Y(n2807) );
INVX2TS U1628 ( .A(n1423), .Y(n1425) );
ADDFHX2TS U1629 ( .A(n1555), .B(n1554), .CI(n1553), .CO(n1558), .S(n1579) );
OAI22X2TS U1630 ( .A0(n1796), .A1(n2316), .B0(n757), .B1(n1323), .Y(n1313)
);
NOR2BX2TS U1631 ( .AN(n612), .B(n3098), .Y(n1337) );
OAI21X2TS U1632 ( .A0(n1868), .A1(n870), .B0(n905), .Y(n903) );
OAI22X2TS U1633 ( .A0(n2219), .A1(n841), .B0(n2329), .B1(n2327), .Y(n2385)
);
OAI22X2TS U1634 ( .A0(n802), .A1(n1712), .B0(n1676), .B1(n1014), .Y(n1677)
);
NOR2X4TS U1635 ( .A(n2322), .B(n1582), .Y(n724) );
NOR2X4TS U1636 ( .A(n678), .B(n1816), .Y(n725) );
INVX2TS U1637 ( .A(n1792), .Y(n852) );
NAND2X4TS U1638 ( .A(n674), .B(n2905), .Y(n716) );
OAI22X2TS U1639 ( .A0(n2311), .A1(n994), .B0(n802), .B1(n976), .Y(n2363) );
OAI22X2TS U1640 ( .A0(n841), .A1(n2328), .B0(n1321), .B1(n2327), .Y(n2416)
);
INVX2TS U1641 ( .A(n1465), .Y(n1394) );
AOI21X2TS U1642 ( .A0(n1469), .A1(n1468), .B0(n1467), .Y(n1471) );
NOR2X2TS U1643 ( .A(n1462), .B(n1465), .Y(n1468) );
INVX2TS U1644 ( .A(n1461), .Y(n1462) );
INVX2TS U1645 ( .A(n1456), .Y(n1458) );
OAI21X2TS U1646 ( .A0(n636), .A1(n1452), .B0(n1451), .Y(n1453) );
INVX2TS U1647 ( .A(n1448), .Y(n1449) );
NOR2X4TS U1648 ( .A(n1268), .B(n1267), .Y(n1465) );
NOR2X4TS U1649 ( .A(n2117), .B(n2122), .Y(n1006) );
INVX2TS U1650 ( .A(n2660), .Y(n1627) );
NAND2X1TS U1651 ( .A(n2661), .B(n1627), .Y(n1629) );
INVX2TS U1652 ( .A(n1417), .Y(n1415) );
INVX2TS U1653 ( .A(n1438), .Y(n1436) );
OAI21X1TS U1654 ( .A0(n922), .A1(n2178), .B0(n2177), .Y(n921) );
OAI21X2TS U1655 ( .A0(n2236), .A1(n844), .B0(n2235), .Y(n885) );
INVX2TS U1656 ( .A(n1638), .Y(n1992) );
INVX4TS U1657 ( .A(n1929), .Y(n1633) );
INVX2TS U1658 ( .A(n2591), .Y(n2593) );
INVX2TS U1659 ( .A(n2841), .Y(n2765) );
INVX2TS U1660 ( .A(n965), .Y(n859) );
INVX2TS U1661 ( .A(n697), .Y(n2262) );
INVX2TS U1662 ( .A(n2862), .Y(n2864) );
INVX2TS U1663 ( .A(mult_x_19_n723), .Y(n2565) );
XOR2X1TS U1664 ( .A(n357), .B(n356), .Y(n3023) );
XOR2X1TS U1665 ( .A(n355), .B(n354), .Y(n2941) );
INVX2TS U1666 ( .A(n345), .Y(n2931) );
INVX2TS U1667 ( .A(mult_x_19_n633), .Y(n2879) );
INVX2TS U1668 ( .A(n713), .Y(n710) );
CLKBUFX3TS U1669 ( .A(n3360), .Y(n3081) );
ADDFHX2TS U1670 ( .A(n2405), .B(n2404), .CI(n2403), .CO(mult_x_19_n649), .S(
n1570) );
ADDFHX2TS U1671 ( .A(n2525), .B(n2524), .CI(n2523), .CO(mult_x_19_n940), .S(
mult_x_19_n941) );
CLKBUFX3TS U1672 ( .A(n3360), .Y(n3277) );
CLKBUFX3TS U1673 ( .A(n3360), .Y(n3082) );
INVX2TS U1674 ( .A(n2924), .Y(n3050) );
BUFX3TS U1675 ( .A(n3157), .Y(n3090) );
BUFX3TS U1676 ( .A(n3167), .Y(n3280) );
CLKBUFX3TS U1677 ( .A(n3157), .Y(n3089) );
CLKBUFX3TS U1678 ( .A(n2576), .Y(n3083) );
CLKINVX3TS U1679 ( .A(rst), .Y(n794) );
CLKBUFX2TS U1680 ( .A(n2576), .Y(n3085) );
CLKBUFX3TS U1681 ( .A(n3157), .Y(n3088) );
CLKBUFX3TS U1682 ( .A(n3085), .Y(n3091) );
CLKBUFX3TS U1683 ( .A(n2575), .Y(n3076) );
CLKBUFX3TS U1684 ( .A(n3279), .Y(n3166) );
AND2X2TS U1685 ( .A(n1477), .B(n1475), .Y(n1275) );
NAND2X4TS U1686 ( .A(n1486), .B(n1222), .Y(n3287) );
CLKINVX3TS U1687 ( .A(n770), .Y(n795) );
CLKINVX3TS U1688 ( .A(n770), .Y(n817) );
CLKINVX3TS U1689 ( .A(n770), .Y(n816) );
BUFX3TS U1690 ( .A(n3276), .Y(n3157) );
OAI21X2TS U1691 ( .A0(n1662), .A1(n2112), .B0(n1661), .Y(n1667) );
NAND2X2TS U1692 ( .A(n796), .B(n2629), .Y(n3288) );
INVX2TS U1693 ( .A(rst), .Y(n3360) );
NAND2X2TS U1694 ( .A(n796), .B(n2628), .Y(n3292) );
NAND2X2TS U1695 ( .A(n776), .B(n2678), .Y(n3313) );
CLKBUFX3TS U1696 ( .A(n3276), .Y(n3160) );
CLKBUFX2TS U1697 ( .A(n3277), .Y(n3158) );
CLKBUFX3TS U1698 ( .A(n2576), .Y(n3086) );
CLKBUFX3TS U1699 ( .A(n3277), .Y(n3161) );
BUFX3TS U1700 ( .A(n3153), .Y(n3282) );
BUFX3TS U1701 ( .A(n3155), .Y(n3281) );
CLKBUFX3TS U1702 ( .A(n773), .Y(n3167) );
CLKINVX3TS U1703 ( .A(n770), .Y(n815) );
INVX6TS U1704 ( .A(n1632), .Y(n1929) );
XOR2X4TS U1705 ( .A(n2203), .B(n2958), .Y(n2204) );
AOI21X4TS U1706 ( .A0(n582), .A1(n2998), .B0(n2999), .Y(n2203) );
OAI22X2TS U1707 ( .A0(n437), .A1(n1870), .B0(n2050), .B1(n2048), .Y(n2076)
);
OAI2BB1X2TS U1708 ( .A0N(n1782), .A1N(n1781), .B0(n889), .Y(n1826) );
XOR2X4TS U1709 ( .A(n629), .B(n761), .Y(n1702) );
XNOR2X4TS U1710 ( .A(n891), .B(n606), .Y(n890) );
OR2X8TS U1711 ( .A(n1770), .B(n1769), .Y(n631) );
OR2X8TS U1712 ( .A(n1770), .B(n1769), .Y(n632) );
NOR2X4TS U1713 ( .A(n2632), .B(n2859), .Y(n2634) );
NOR2X4TS U1714 ( .A(n2632), .B(n2631), .Y(n2633) );
NAND2X4TS U1715 ( .A(Sgf_normalized_result[6]), .B(n2837), .Y(n2632) );
OA21X4TS U1716 ( .A0(n1245), .A1(n1377), .B0(n1244), .Y(n636) );
OAI22X2TS U1717 ( .A0(n2330), .A1(n1320), .B0(n1299), .B1(n2327), .Y(n1356)
);
OAI22X4TS U1718 ( .A0(n2330), .A1(n1118), .B0(n1163), .B1(n1813), .Y(n1157)
);
NAND3X4TS U1719 ( .A(n2704), .B(n2703), .C(n2702), .Y(n208) );
AOI2BB2X4TS U1720 ( .B0(n2700), .B1(n2699), .A0N(n805), .A1N(n3143), .Y(
n2703) );
NOR2X8TS U1721 ( .A(n573), .B(n2992), .Y(n1855) );
ADDFHX4TS U1722 ( .A(n1801), .B(n1800), .CI(n1799), .CO(n1811), .S(n2019) );
OAI22X4TS U1723 ( .A0(n2041), .A1(n2015), .B0(n1771), .B1(n800), .Y(n1799)
);
CLKBUFX3TS U1724 ( .A(n1988), .Y(n661) );
OAI21X4TS U1725 ( .A0(n1239), .A1(n1421), .B0(n1238), .Y(n1240) );
AND2X6TS U1726 ( .A(n1770), .B(n1769), .Y(n660) );
OR2X8TS U1727 ( .A(n642), .B(n643), .Y(n2057) );
NOR2X4TS U1728 ( .A(n1422), .B(n1239), .Y(n1241) );
BUFX4TS U1729 ( .A(n1875), .Y(n656) );
INVX8TS U1730 ( .A(n1620), .Y(n2667) );
INVX8TS U1731 ( .A(n646), .Y(n647) );
OAI22X2TS U1732 ( .A0(n803), .A1(n1785), .B0(n1784), .B1(n2314), .Y(n1788)
);
XNOR2X4TS U1733 ( .A(n878), .B(n824), .Y(n1785) );
OR2X8TS U1734 ( .A(n803), .B(n968), .Y(n652) );
OAI2BB1X2TS U1735 ( .A0N(n852), .A1N(n851), .B0(n1791), .Y(n850) );
ADDFHX2TS U1736 ( .A(n2149), .B(n2148), .CI(n2147), .CO(n2171), .S(n2139) );
OAI22X2TS U1737 ( .A0(n677), .A1(n2886), .B0(n2471), .B1(n1746), .Y(n2225)
);
XOR2X4TS U1738 ( .A(n1884), .B(n696), .Y(n1353) );
OAI22X4TS U1739 ( .A0(n838), .A1(n2014), .B0(n1785), .B1(n590), .Y(n2017) );
XNOR2X4TS U1740 ( .A(n657), .B(n647), .Y(n1772) );
OAI22X2TS U1741 ( .A0(n678), .A1(n1353), .B0(n2471), .B1(n985), .Y(n1326) );
XOR2X4TS U1742 ( .A(n1814), .B(n2950), .Y(n1771) );
XNOR2X2TS U1743 ( .A(n2241), .B(n648), .Y(n1056) );
ADDFHX4TS U1744 ( .A(n1129), .B(n1128), .CI(n1127), .CO(n1135), .S(n1146) );
OAI22X4TS U1745 ( .A0(n784), .A1(n2481), .B0(n2480), .B1(n800), .Y(n2547) );
XNOR2X4TS U1746 ( .A(n1814), .B(n755), .Y(n2480) );
NAND2X2TS U1747 ( .A(n2248), .B(n1365), .Y(n1221) );
ADDFHX4TS U1748 ( .A(n2086), .B(n2085), .CI(n2084), .CO(n2101), .S(n2441) );
INVX16TS U1749 ( .A(n666), .Y(n667) );
XNOR2X4TS U1750 ( .A(n644), .B(n1869), .Y(n951) );
ADDFHX2TS U1751 ( .A(n2012), .B(n2011), .CI(n2010), .CO(n1843), .S(n2033) );
AOI21X4TS U1752 ( .A0(n1217), .A1(n2650), .B0(n1216), .Y(n1218) );
NAND2X8TS U1753 ( .A(n2191), .B(n2190), .Y(n2282) );
CLKXOR2X2TS U1754 ( .A(n2290), .B(n2289), .Y(n877) );
NAND2X6TS U1755 ( .A(n1373), .B(n3254), .Y(n854) );
ADDFHX4TS U1756 ( .A(n2144), .B(n2143), .CI(n2142), .CO(n2173), .S(n2140) );
OAI22X2TS U1757 ( .A0(n2041), .A1(n1780), .B0(n1815), .B1(n2479), .Y(n1832)
);
OAI21X4TS U1758 ( .A0(n766), .A1(n1533), .B0(n1532), .Y(n1536) );
OAI21X2TS U1759 ( .A0(n1948), .A1(n1529), .B0(n1528), .Y(n1530) );
OAI21X1TS U1760 ( .A0(n658), .A1(n1898), .B0(n892), .Y(n946) );
BUFX12TS U1761 ( .A(n633), .Y(n2068) );
NAND2X2TS U1762 ( .A(n2679), .B(n2629), .Y(n3289) );
XNOR2X2TS U1763 ( .A(n2218), .B(n626), .Y(n1061) );
XNOR2X1TS U1764 ( .A(n792), .B(n626), .Y(n1306) );
NAND2X4TS U1765 ( .A(n1979), .B(n1980), .Y(n2267) );
NOR2X8TS U1766 ( .A(n1957), .B(n1956), .Y(n665) );
INVX16TS U1767 ( .A(n665), .Y(n3099) );
ADDFHX4TS U1768 ( .A(n2083), .B(n2082), .CI(n2081), .CO(n2458), .S(n2442) );
INVX16TS U1769 ( .A(n668), .Y(n669) );
XNOR2X4TS U1770 ( .A(n690), .B(n824), .Y(n2069) );
NAND2X2TS U1771 ( .A(n2681), .B(n2630), .Y(n3298) );
OAI22X4TS U1772 ( .A0(n803), .A1(n2074), .B0(n2014), .B1(n590), .Y(n2044) );
XNOR2X4TS U1773 ( .A(n878), .B(n755), .Y(n2014) );
NOR3X4TS U1774 ( .A(n3137), .B(FSM_selector_B_1_), .C(n2686), .Y(n1269) );
NOR2X4TS U1775 ( .A(n1230), .B(n1255), .Y(n1232) );
OAI22X2TS U1776 ( .A0(n1796), .A1(n1117), .B0(n1116), .B1(n756), .Y(n1124)
);
OAI21X4TS U1777 ( .A0(n1948), .A1(n1947), .B0(n1946), .Y(n1949) );
AOI21X4TS U1778 ( .A0(n1945), .A1(n1944), .B0(n1943), .Y(n1946) );
XNOR2X4TS U1779 ( .A(n1361), .B(n960), .Y(n984) );
OAI22X2TS U1780 ( .A0(n767), .A1(n1893), .B0(n2036), .B1(n2034), .Y(n2080)
);
OA22X2TS U1781 ( .A0(n676), .A1(n1506), .B0(n2471), .B1(n1884), .Y(n680) );
BUFX20TS U1782 ( .A(n1288), .Y(n2055) );
CMPR22X2TS U1783 ( .A(n1021), .B(n1020), .CO(n1075), .S(n1024) );
NAND2X4TS U1784 ( .A(n989), .B(n980), .Y(n979) );
OAI2BB1X4TS U1785 ( .A0N(n587), .A1N(n1490), .B0(n3269), .Y(n681) );
XOR2X4TS U1786 ( .A(n644), .B(n687), .Y(n1802) );
ADDFHX4TS U1787 ( .A(n2336), .B(n2335), .CI(n2334), .CO(n2519), .S(n2409) );
ADDFHX2TS U1788 ( .A(n1068), .B(n1067), .CI(n1066), .CO(n1072), .S(n1074) );
OA22X4TS U1789 ( .A0(n2312), .A1(n1325), .B0(n1324), .B1(n1026), .Y(n683) );
INVX12TS U1790 ( .A(n1494), .Y(n2655) );
NAND2X4TS U1791 ( .A(n2248), .B(n584), .Y(n1488) );
XNOR2X4TS U1792 ( .A(n684), .B(n685), .Y(n1279) );
OAI22X4TS U1793 ( .A0(n676), .A1(n2323), .B0(n1359), .B1(n2322), .Y(n2304)
);
NAND2BX2TS U1794 ( .AN(n789), .B(n645), .Y(n1318) );
INVX16TS U1795 ( .A(n782), .Y(n784) );
NOR2X4TS U1796 ( .A(n1008), .B(n1007), .Y(n2108) );
OAI21X4TS U1797 ( .A0(n1863), .A1(n682), .B0(n1862), .Y(n893) );
OAI22X2TS U1798 ( .A0(n803), .A1(n2893), .B0(n590), .B1(n1093), .Y(n1125) );
OAI22X1TS U1799 ( .A0(n783), .A1(n645), .B0(n2479), .B1(n2884), .Y(n1602) );
ADDFHX4TS U1800 ( .A(n1755), .B(n1754), .CI(n1753), .CO(n2234), .S(n1750) );
XNOR2X2TS U1801 ( .A(n645), .B(n2319), .Y(n2040) );
OAI22X2TS U1802 ( .A0(n2318), .A1(n1886), .B0(n757), .B1(n2052), .Y(n2091)
);
OAI22X4TS U1803 ( .A0(n2310), .A1(n1309), .B0(n1301), .B1(n2048), .Y(n1355)
);
ADDFHX4TS U1804 ( .A(n1354), .B(n1355), .CI(n1356), .CO(n1331), .S(n2345) );
XNOR2X4TS U1805 ( .A(n617), .B(n399), .Y(n1104) );
OAI22X4TS U1806 ( .A0(n767), .A1(n1304), .B0(n1893), .B1(n2034), .Y(n1882)
);
XNOR2X4TS U1807 ( .A(n617), .B(n762), .Y(n1713) );
ADDFHX4TS U1808 ( .A(n672), .B(n2158), .CI(n2157), .CO(n2179), .S(n2183) );
ADDFHX4TS U1809 ( .A(n2046), .B(n2047), .CI(n2045), .CO(n2062), .S(n2102) );
XNOR2X4TS U1810 ( .A(n617), .B(n671), .Y(n1161) );
OAI22X4TS U1811 ( .A0(n678), .A1(n1778), .B0(mult_x_19_n1556), .B1(n2322),
.Y(n1834) );
ADDFHX4TS U1812 ( .A(n1286), .B(n1285), .CI(n1287), .CO(n1872), .S(n1297) );
NOR2X4TS U1813 ( .A(mult_x_19_n423), .B(mult_x_19_n439), .Y(mult_x_19_n421)
);
XNOR2X2TS U1814 ( .A(n617), .B(n2221), .Y(n1107) );
BUFX3TS U1815 ( .A(n771), .Y(n3285) );
BUFX3TS U1816 ( .A(n3278), .Y(n3154) );
INVX2TS U1817 ( .A(n734), .Y(n735) );
AND2X8TS U1818 ( .A(n3274), .B(n3356), .Y(n2785) );
INVX2TS U1819 ( .A(n715), .Y(n833) );
BUFX8TS U1820 ( .A(mult_x_19_n52), .Y(n2471) );
INVX12TS U1821 ( .A(n2470), .Y(n763) );
CLKINVX12TS U1822 ( .A(n962), .Y(n2006) );
BUFX12TS U1823 ( .A(n734), .Y(n757) );
INVX6TS U1824 ( .A(n970), .Y(n972) );
BUFX3TS U1825 ( .A(n2575), .Y(n3075) );
CLKBUFX2TS U1826 ( .A(n3277), .Y(n3162) );
CLKBUFX3TS U1827 ( .A(n3360), .Y(n3080) );
CLKBUFX2TS U1828 ( .A(n3276), .Y(n3156) );
CLKBUFX3TS U1829 ( .A(n778), .Y(n3165) );
BUFX3TS U1830 ( .A(n3279), .Y(n3164) );
CLKINVX3TS U1831 ( .A(n770), .Y(n773) );
CLKINVX3TS U1832 ( .A(n770), .Y(n772) );
BUFX3TS U1833 ( .A(n3153), .Y(n3283) );
BUFX3TS U1834 ( .A(n3284), .Y(n3279) );
BUFX3TS U1835 ( .A(n3153), .Y(n778) );
XOR2X4TS U1836 ( .A(n1002), .B(n712), .Y(n2551) );
XNOR2X4TS U1837 ( .A(n713), .B(n647), .Y(n712) );
AOI2BB2X4TS U1838 ( .B0(n2474), .B1(n687), .A0N(n695), .A1N(n884), .Y(n713)
);
OAI22X4TS U1839 ( .A0(n1807), .A1(n2793), .B0(n551), .B1(n638), .Y(n837) );
OAI22X4TS U1840 ( .A0(n1807), .A1(n2794), .B0(n715), .B1(n736), .Y(n1868) );
OAI22X4TS U1841 ( .A0(n1807), .A1(n2221), .B0(n715), .B1(n399), .Y(n1795) );
OAI22X4TS U1842 ( .A0(n1807), .A1(n2796), .B0(n715), .B1(n870), .Y(n1294) );
OAI2BB1X4TS U1843 ( .A0N(n2410), .A1N(n2411), .B0(n717), .Y(n2347) );
OAI21X4TS U1844 ( .A0(n2411), .A1(n2410), .B0(n2409), .Y(n717) );
XNOR2X4TS U1845 ( .A(n718), .B(n2411), .Y(n2428) );
XNOR2X4TS U1846 ( .A(n2410), .B(n2409), .Y(n718) );
XNOR2X4TS U1847 ( .A(n722), .B(n2145), .Y(n2172) );
XOR2X4TS U1848 ( .A(n2146), .B(n723), .Y(n722) );
NOR2X8TS U1849 ( .A(n725), .B(n724), .Y(n723) );
INVX2TS U1850 ( .A(n727), .Y(n728) );
BUFX20TS U1851 ( .A(n1026), .Y(n1014) );
OAI22X2TS U1852 ( .A0(n743), .A1(n780), .B0(n842), .B1(n2889), .Y(n1002) );
OAI21X2TS U1853 ( .A0(n1653), .A1(n2112), .B0(n1652), .Y(n1656) );
OAI22X2TS U1854 ( .A0(n556), .A1(n1019), .B0(n1027), .B1(n785), .Y(n1025) );
INVX2TS U1855 ( .A(n732), .Y(n733) );
ADDFHX2TS U1856 ( .A(n2550), .B(n2549), .CI(n2548), .CO(n2494), .S(n2558) );
BUFX20TS U1857 ( .A(n2794), .Y(n828) );
ADDFHX4TS U1858 ( .A(n1742), .B(n1741), .CI(n1740), .CO(n2246), .S(n1763) );
NAND2BX2TS U1859 ( .AN(n2904), .B(n2013), .Y(n1093) );
XNOR2X4TS U1860 ( .A(n1667), .B(n1666), .Y(n1668) );
OAI22X4TS U1861 ( .A0(n841), .A1(n1321), .B0(n1320), .B1(n2327), .Y(n2340)
);
OAI22X4TS U1862 ( .A0(n678), .A1(mult_x_19_n1556), .B0(n1816), .B1(n2322),
.Y(n2143) );
XNOR2X4TS U1863 ( .A(n753), .B(n1869), .Y(n1816) );
ADDFHX4TS U1864 ( .A(n1328), .B(n1327), .CI(n1326), .CO(n1298), .S(n1349) );
ADDFHX4TS U1865 ( .A(n1707), .B(n1708), .CI(n1706), .CO(n1719), .S(n1905) );
OAI22X2TS U1866 ( .A0(n1796), .A1(n1696), .B0(n1695), .B1(n756), .Y(n1706)
);
ADDFHX4TS U1867 ( .A(n2343), .B(n2342), .CI(n2341), .CO(n2346), .S(n2514) );
NAND2X6TS U1868 ( .A(n910), .B(n909), .Y(n892) );
XOR2X4TS U1869 ( .A(n741), .B(n1862), .Y(n1896) );
XOR2X4TS U1870 ( .A(n1863), .B(n1861), .Y(n741) );
NAND2X8TS U1871 ( .A(mult_x_19_n1800), .B(n1817), .Y(n742) );
NAND2X8TS U1872 ( .A(n745), .B(n746), .Y(n1690) );
OAI22X4TS U1873 ( .A0(n768), .A1(n1548), .B0(n1545), .B1(n842), .Y(n1563) );
XOR2X4TS U1874 ( .A(n922), .B(n747), .Y(n2170) );
XOR2X4TS U1875 ( .A(n2177), .B(n2178), .Y(n747) );
BUFX20TS U1876 ( .A(n2906), .Y(n824) );
NOR2X4TS U1877 ( .A(n2763), .B(n2693), .Y(n2769) );
ADDFHX4TS U1878 ( .A(n2337), .B(n2338), .CI(n2339), .CO(n2516), .S(n2421) );
BUFX20TS U1879 ( .A(n2907), .Y(n879) );
ADDFHX4TS U1880 ( .A(n1315), .B(n1314), .CI(n1313), .CO(n1310), .S(n2518) );
CLKINVX12TS U1881 ( .A(n1280), .Y(n2470) );
OAI22X4TS U1882 ( .A0(n760), .A1(n1303), .B0(mult_x_19_n1585), .B1(n1674),
.Y(n1890) );
ADDFHX4TS U1883 ( .A(n1689), .B(n1688), .CI(n1687), .CO(n1697), .S(n1906) );
ADDFHX4TS U1884 ( .A(n624), .B(n1795), .CI(n1794), .CO(n1792), .S(n2021) );
OAI22X4TS U1885 ( .A0(n407), .A1(n1743), .B0(n2228), .B1(n2227), .Y(n2216)
);
OAI22X4TS U1886 ( .A0(n802), .A1(n1081), .B0(n1104), .B1(n1014), .Y(n1132)
);
OAI22X2TS U1887 ( .A0(n551), .A1(n650), .B0(n1807), .B1(n879), .Y(n1516) );
INVX12TS U1888 ( .A(n1931), .Y(n2112) );
ADDFHX4TS U1889 ( .A(n1606), .B(n1605), .CI(n1604), .CO(n1609), .S(n2530) );
ADDFHX2TS U1890 ( .A(n3066), .B(n1603), .CI(n1602), .CO(n1610), .S(n1605) );
CLKINVX12TS U1891 ( .A(n2901), .Y(n2052) );
OAI22X2TS U1892 ( .A0(n2318), .A1(n1695), .B0(n1680), .B1(n734), .Y(n1699)
);
INVX12TS U1893 ( .A(n897), .Y(n785) );
ADDFHX4TS U1894 ( .A(n1679), .B(n1678), .CI(n1677), .CO(n1765), .S(n1731) );
OAI22X4TS U1895 ( .A0(n764), .A1(n1682), .B0(n1681), .B1(n2227), .Y(n1701)
);
ADDFHX4TS U1896 ( .A(n1722), .B(n1721), .CI(n1720), .CO(n1912), .S(n1908) );
OAI22X4TS U1897 ( .A0(n790), .A1(n1163), .B0(n1714), .B1(n1813), .Y(n1722)
);
INVX16TS U1898 ( .A(n2670), .Y(n765) );
INVX16TS U1899 ( .A(n2670), .Y(n766) );
INVX16TS U1900 ( .A(n1820), .Y(n2486) );
INVX16TS U1901 ( .A(n2486), .Y(n769) );
ADDFHX2TS U1902 ( .A(n1614), .B(n1613), .CI(n1612), .CO(n2128), .S(n1608) );
OAI22X4TS U1903 ( .A0(n1308), .A1(n553), .B0(n785), .B1(mult_x_19_n1749),
.Y(n1335) );
ADDFHX4TS U1904 ( .A(n1332), .B(n1333), .CI(n1334), .CO(n1863), .S(n1330) );
OAI22X2TS U1905 ( .A0(n764), .A1(mult_x_19_n1587), .B0(n1303), .B1(n1674),
.Y(n1333) );
OAI22X2TS U1906 ( .A0(n767), .A1(mult_x_19_n1610), .B0(n1304), .B1(n842),
.Y(n1332) );
XOR2X4TS U1907 ( .A(n2241), .B(n3095), .Y(n1887) );
BUFX8TS U1908 ( .A(n2799), .Y(n3273) );
OAI22X2TS U1909 ( .A0(n2325), .A1(n760), .B0(n1674), .B1(n992), .Y(n2334) );
INVX8TS U1910 ( .A(n779), .Y(n780) );
INVX16TS U1911 ( .A(n2482), .Y(n782) );
INVX16TS U1912 ( .A(n782), .Y(n783) );
INVX2TS U1913 ( .A(n770), .Y(n788) );
INVX12TS U1914 ( .A(n1281), .Y(n791) );
XNOR2X2TS U1915 ( .A(n791), .B(n755), .Y(n1502) );
AO22X2TS U1916 ( .A0(n2857), .A1(n2854), .B0(final_result_ieee[22]), .B1(
n2855), .Y(n178) );
NAND2X2TS U1917 ( .A(n2854), .B(n310), .Y(n2694) );
XNOR2X2TS U1918 ( .A(n617), .B(n2319), .Y(n1106) );
NOR4X2TS U1919 ( .A(Op_MX[13]), .B(Op_MX[15]), .C(Op_MX[1]), .D(Op_MX[3]),
.Y(n2820) );
MXI2X4TS U1920 ( .A(n1739), .B(n3106), .S0(n2785), .Y(n226) );
NOR2X2TS U1921 ( .A(n3121), .B(n3106), .Y(n1475) );
AO22X2TS U1922 ( .A0(n2853), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n2852), .Y(n198) );
AO22X2TS U1923 ( .A0(n2853), .A1(n640), .B0(final_result_ieee[4]), .B1(n2852), .Y(n196) );
AO22X2TS U1924 ( .A0(n2853), .A1(n2851), .B0(final_result_ieee[5]), .B1(
n2852), .Y(n195) );
AO22X2TS U1925 ( .A0(n2853), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n2852), .Y(n197) );
CLKBUFX2TS U1926 ( .A(n2576), .Y(n3084) );
BUFX3TS U1927 ( .A(n3278), .Y(n3155) );
CLKBUFX3TS U1928 ( .A(n3278), .Y(n3153) );
BUFX3TS U1929 ( .A(n3153), .Y(n3079) );
BUFX3TS U1930 ( .A(n772), .Y(n3078) );
NAND2X2TS U1931 ( .A(n796), .B(n2630), .Y(n3297) );
NAND2X2TS U1932 ( .A(n796), .B(n2638), .Y(n3286) );
OAI22X2TS U1933 ( .A0(n1823), .A1(n2051), .B0(n1822), .B1(n499), .Y(n2148)
);
XNOR2X4TS U1934 ( .A(n500), .B(n787), .Y(n1514) );
OAI22X4TS U1935 ( .A0(n715), .A1(n762), .B0(n3098), .B1(n2908), .Y(n2158) );
OAI22X2TS U1936 ( .A0(n969), .A1(n505), .B0(n970), .B1(n1281), .Y(n2131) );
ADDFHX4TS U1937 ( .A(n2319), .B(n2221), .CI(n2156), .CO(n2184), .S(n2147) );
BUFX20TS U1938 ( .A(n855), .Y(n801) );
OAI22X4TS U1939 ( .A0(n784), .A1(n1883), .B0(n2040), .B1(n2479), .Y(n2094)
);
BUFX20TS U1940 ( .A(n855), .Y(n2479) );
INVX16TS U1941 ( .A(n989), .Y(n802) );
OAI22X4TS U1942 ( .A0(n802), .A1(n1056), .B0(n1055), .B1(n2311), .Y(n1064)
);
OAI22X4TS U1943 ( .A0(n802), .A1(n1055), .B0(n1081), .B1(n2311), .Y(n1088)
);
OAI22X2TS U1944 ( .A0(n803), .A1(n2320), .B0(n590), .B1(n2315), .Y(n2339) );
AND2X8TS U1945 ( .A(n1485), .B(n1486), .Y(n2783) );
CLKINVX6TS U1946 ( .A(n2783), .Y(n805) );
AOI2BB2X2TS U1947 ( .B0(n2784), .B1(n2674), .A0N(n806), .A1N(n3126), .Y(
n3307) );
AOI2BB2X2TS U1948 ( .B0(n2784), .B1(n2682), .A0N(n807), .A1N(n3128), .Y(
n3315) );
AOI2BB2X2TS U1949 ( .B0(n2700), .B1(n2683), .A0N(n807), .A1N(n3132), .Y(
n3331) );
AOI2BB2X2TS U1950 ( .B0(n1483), .B1(n2673), .A0N(n806), .A1N(n3144), .Y(
n3347) );
AOI2BB2X2TS U1951 ( .B0(n2784), .B1(n2684), .A0N(n806), .A1N(n3131), .Y(
n3327) );
AOI2BB2X2TS U1952 ( .B0(n2784), .B1(n2685), .A0N(n807), .A1N(n3130), .Y(
n3323) );
AOI2BB2X2TS U1953 ( .B0(n2784), .B1(n2676), .A0N(n806), .A1N(n3142), .Y(
n3343) );
AOI22X2TS U1954 ( .A0(n2827), .A1(Add_result[13]), .B0(n2843), .B1(n2799),
.Y(n3328) );
CLKBUFX2TS U1955 ( .A(Add_result[21]), .Y(n811) );
AOI22X2TS U1956 ( .A0(n2792), .A1(Add_result[12]), .B0(n2845), .B1(n2799),
.Y(n3332) );
AOI22X2TS U1957 ( .A0(n2792), .A1(Add_result[15]), .B0(n2842), .B1(n2799),
.Y(n3320) );
CLKBUFX2TS U1958 ( .A(Add_result[2]), .Y(n813) );
NOR3X1TS U1959 ( .A(Op_MX[4]), .B(Op_MX[23]), .C(Op_MX[24]), .Y(n2818) );
MX2X4TS U1960 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n2791), .Y(
mult_x_19_n1777) );
NOR3X1TS U1961 ( .A(Op_MY[17]), .B(Op_MY[23]), .C(Op_MY[24]), .Y(n2805) );
INVX2TS U1962 ( .A(n2868), .Y(n1444) );
MXI2X4TS U1963 ( .A(n1432), .B(n1431), .S0(n427), .Y(n2602) );
MXI2X4TS U1964 ( .A(n1441), .B(n1440), .S0(n427), .Y(n2603) );
NAND2X4TS U1965 ( .A(n1408), .B(n427), .Y(n1409) );
MXI2X4TS U1966 ( .A(n1276), .B(n1275), .S0(n427), .Y(n1278) );
INVX4TS U1967 ( .A(n2778), .Y(n1040) );
AOI2BB2X4TS U1968 ( .B0(n819), .B1(n972), .A0N(n2152), .A1N(n667), .Y(n818)
);
ADDFHX4TS U1969 ( .A(n1337), .B(n1336), .CI(n1335), .CO(n1348), .S(n1311) );
NOR2BX2TS U1970 ( .AN(n789), .B(n744), .Y(n2305) );
BUFX4TS U1971 ( .A(n1026), .Y(n2311) );
ADDFHX4TS U1972 ( .A(n1758), .B(n1756), .CI(n1757), .CO(n2233), .S(n1764) );
AOI21X4TS U1973 ( .A0(n2252), .A1(n565), .B0(n2921), .Y(n820) );
OAI2BB1X4TS U1974 ( .A0N(n1906), .A1N(n739), .B0(n821), .Y(n1729) );
OAI21X4TS U1975 ( .A0(n739), .A1(n1906), .B0(n1905), .Y(n821) );
AOI21X4TS U1976 ( .A0(n860), .A1(n2208), .B0(n859), .Y(n2260) );
AOI2BB2X4TS U1977 ( .B0(n2628), .B1(n2700), .A0N(n805), .A1N(n3123), .Y(
n1492) );
OAI22X2TS U1978 ( .A0(n742), .A1(n1818), .B0(n1584), .B1(n842), .Y(n2145) );
ADDFHX4TS U1979 ( .A(n1882), .B(n1881), .CI(n1880), .CO(n2455), .S(n1877) );
NAND2X8TS U1980 ( .A(n695), .B(n689), .Y(n1500) );
XOR2X4TS U1981 ( .A(n825), .B(n2444), .Y(n2459) );
XOR2X4TS U1982 ( .A(n2445), .B(n2446), .Y(n825) );
NAND2X4TS U1983 ( .A(n2445), .B(n2446), .Y(n826) );
OAI21X4TS U1984 ( .A0(n2445), .A1(n2446), .B0(n2444), .Y(n827) );
XOR2X4TS U1985 ( .A(n2297), .B(n829), .Y(mult_x_19_n786) );
CLKXOR2X2TS U1986 ( .A(n836), .B(n837), .Y(n2448) );
OAI2BB1X4TS U1987 ( .A0N(n736), .A1N(n649), .B0(n837), .Y(n832) );
AO22X4TS U1988 ( .A0(n435), .A1(n639), .B0(n833), .B1(n649), .Y(n2077) );
XOR2X4TS U1989 ( .A(n834), .B(n1791), .Y(n2022) );
XOR2X4TS U1990 ( .A(n1792), .B(n1793), .Y(n834) );
XNOR2X2TS U1991 ( .A(n792), .B(n1869), .Y(n1556) );
XOR2X4TS U1992 ( .A(n932), .B(n835), .Y(n1768) );
INVX2TS U1993 ( .A(n1765), .Y(n835) );
AOI21X4TS U1994 ( .A0(n1455), .A1(n1454), .B0(n1453), .Y(n1460) );
OAI22X4TS U1995 ( .A0(n1676), .A1(n2312), .B0(n990), .B1(n1026), .Y(n1742)
);
OAI22X4TS U1996 ( .A0(n677), .A1(n1772), .B0(n1778), .B1(n2322), .Y(n891) );
ADDFHX4TS U1997 ( .A(n2365), .B(n2364), .CI(n2363), .CO(n2422), .S(n2414) );
OAI22X2TS U1998 ( .A0(n1762), .A1(n1083), .B0(n1105), .B1(n757), .Y(n1130)
);
BUFX20TS U1999 ( .A(n2908), .Y(n867) );
XOR2X4TS U2000 ( .A(n840), .B(n1905), .Y(n1963) );
XOR2X4TS U2001 ( .A(n1906), .B(n739), .Y(n840) );
OAI22X2TS U2002 ( .A0(n2331), .A1(n555), .B0(mult_x_19_n1753), .B1(n785),
.Y(n2371) );
OAI22X2TS U2003 ( .A0(n838), .A1(n1867), .B0(n2075), .B1(n590), .Y(n2452) );
NAND2X8TS U2004 ( .A(n734), .B(mult_x_19_n1805), .Y(n1293) );
CMPR22X2TS U2005 ( .A(n2369), .B(n2370), .CO(n2415), .S(n2420) );
XNOR2X4TS U2006 ( .A(n797), .B(n870), .Y(n1317) );
XNOR2X4TS U2007 ( .A(n843), .B(n2443), .Y(n2460) );
XNOR2X4TS U2008 ( .A(n2442), .B(n2441), .Y(n843) );
XOR2X4TS U2009 ( .A(n2185), .B(n845), .Y(n2165) );
XOR2X4TS U2010 ( .A(n2186), .B(n2187), .Y(n845) );
NAND2X2TS U2011 ( .A(n2186), .B(n2187), .Y(n846) );
OAI22X4TS U2012 ( .A0(n803), .A1(n1692), .B0(n1675), .B1(n2314), .Y(n1678)
);
OAI22X4TS U2013 ( .A0(n2318), .A1(n1323), .B0(n1322), .B1(n734), .Y(n1339)
);
OAI22X4TS U2014 ( .A0(n2151), .A1(n1894), .B0(n1289), .B1(n667), .Y(n1888)
);
NAND2X8TS U2015 ( .A(n1817), .B(mult_x_19_n1800), .Y(n1820) );
OAI22X4TS U2016 ( .A0(n743), .A1(mult_x_19_n1617), .B0(n895), .B1(n2034),
.Y(n1754) );
XNOR2X4TS U2017 ( .A(n2241), .B(n786), .Y(n990) );
BUFX12TS U2018 ( .A(n2914), .Y(n847) );
OAI22X2TS U2019 ( .A0(n678), .A1(n2220), .B0(n2324), .B1(n2322), .Y(n2384)
);
OAI22X4TS U2020 ( .A0(n768), .A1(n1694), .B0(n1703), .B1(n2034), .Y(n1707)
);
NAND2X1TS U2021 ( .A(n1792), .B(n1793), .Y(n849) );
AND2X8TS U2022 ( .A(n1964), .B(n1965), .Y(mult_x_19_n453) );
OAI22X2TS U2023 ( .A0(n802), .A1(n1106), .B0(n1161), .B1(n1014), .Y(n1167)
);
XNOR2X1TS U2024 ( .A(n856), .B(n2348), .Y(mult_x_19_n943) );
XNOR2X1TS U2025 ( .A(n2347), .B(n2349), .Y(n856) );
XOR2X1TS U2026 ( .A(n858), .B(n857), .Y(mult_x_19_n921) );
ADDFHX4TS U2027 ( .A(n2458), .B(n2457), .CI(n2456), .CO(n2299), .S(n2463) );
OAI22X4TS U2028 ( .A0(n677), .A1(n1284), .B0(n1885), .B1(n2471), .Y(n1891)
);
OAI22X4TS U2029 ( .A0(n1693), .A1(n804), .B0(n1692), .B1(n2223), .Y(n1708)
);
XNOR2X2TS U2030 ( .A(n792), .B(n668), .Y(n1607) );
OAI22X2TS U2031 ( .A0(n790), .A1(n1783), .B0(n2068), .B1(n2898), .Y(n1790)
);
NAND2X6TS U2032 ( .A(n1279), .B(n2468), .Y(n1280) );
ADDFHX4TS U2033 ( .A(n2061), .B(n2060), .CI(n2059), .CO(n2064), .S(n2099) );
INVX16TS U2034 ( .A(n3102), .Y(n1026) );
XNOR2X4TS U2035 ( .A(n628), .B(n1869), .Y(n994) );
OAI22X4TS U2036 ( .A0(n2330), .A1(mult_x_19_n1687), .B0(n1702), .B1(n1813),
.Y(n1711) );
ADDFHX2TS U2037 ( .A(n1790), .B(n1789), .CI(n1788), .CO(n1825), .S(n2023) );
OAI2BB1X4TS U2038 ( .A0N(n2362), .A1N(n2361), .B0(n864), .Y(mult_x_19_n994)
);
OAI21X2TS U2039 ( .A0(n2362), .A1(n2361), .B0(n620), .Y(n864) );
XOR2X4TS U2040 ( .A(n865), .B(n620), .Y(mult_x_19_n995) );
XOR2X4TS U2041 ( .A(n2362), .B(n2361), .Y(n865) );
XNOR2X4TS U2042 ( .A(n866), .B(n914), .Y(n1873) );
XOR2X4TS U2043 ( .A(n1892), .B(n1891), .Y(n866) );
BUFX6TS U2044 ( .A(n755), .Y(n868) );
OAI2BB1X4TS U2045 ( .A0N(n2441), .A1N(n2442), .B0(n869), .Y(n2456) );
OAI21X4TS U2046 ( .A0(n2441), .A1(n2442), .B0(n2443), .Y(n869) );
XOR2X4TS U2047 ( .A(n871), .B(n2340), .Y(n2515) );
OAI22X2TS U2048 ( .A0(n2312), .A1(n2054), .B0(n2053), .B1(n1026), .Y(n2084)
);
OAI22X2TS U2049 ( .A0(n838), .A1(n2075), .B0(n2074), .B1(n2314), .Y(n2449)
);
OAI22X2TS U2050 ( .A0(n2330), .A1(n1299), .B0(mult_x_19_n1678), .B1(n2068),
.Y(n1341) );
OAI2BB1X4TS U2051 ( .A0N(n1728), .A1N(n1727), .B0(n872), .Y(n1910) );
XOR2X4TS U2052 ( .A(n873), .B(n1727), .Y(n1915) );
XOR2X4TS U2053 ( .A(n1726), .B(n1728), .Y(n873) );
XOR2X4TS U2054 ( .A(n779), .B(n2793), .Y(n895) );
OAI2BB1X4TS U2055 ( .A0N(n2295), .A1N(n2296), .B0(n874), .Y(n2297) );
ADDFHX4TS U2056 ( .A(n2390), .B(n2389), .CI(n2388), .CO(n2410), .S(n2406) );
OAI2BB1X4TS U2057 ( .A0N(n2290), .A1N(n2289), .B0(n876), .Y(n2355) );
OAI21X4TS U2058 ( .A0(n2289), .A1(n2290), .B0(n2288), .Y(n876) );
XOR2X4TS U2059 ( .A(n2288), .B(n877), .Y(mult_x_19_n923) );
ADDFHX4TS U2060 ( .A(n2058), .B(n2057), .CI(n2056), .CO(n2020), .S(n2100) );
OAI22X4TS U2061 ( .A0(n1307), .A1(n970), .B0(n505), .B1(n511), .Y(n1357) );
ADDFHX4TS U2062 ( .A(n1343), .B(n1342), .CI(n1341), .CO(n1878), .S(n1346) );
XNOR2X4TS U2063 ( .A(n2890), .B(n732), .Y(n1548) );
XOR2X4TS U2064 ( .A(n882), .B(n2350), .Y(n2360) );
XOR2X4TS U2065 ( .A(n2351), .B(n2352), .Y(n882) );
BUFX6TS U2066 ( .A(n618), .Y(n883) );
OAI22X4TS U2067 ( .A0(n2055), .A1(n628), .B0(n1014), .B1(n2899), .Y(n1794)
);
OAI22X4TS U2068 ( .A0(n769), .A1(n1703), .B0(mult_x_19_n1617), .B1(n2034),
.Y(n1710) );
OAI2BB1X4TS U2069 ( .A0N(n2236), .A1N(n844), .B0(n885), .Y(n2382) );
XOR2X4TS U2070 ( .A(n886), .B(n2236), .Y(n2232) );
OAI22X4TS U2071 ( .A0(n888), .A1(n800), .B0(n1542), .B1(n784), .Y(n1568) );
OAI22X4TS U2072 ( .A0(n2041), .A1(n888), .B0(n2481), .B1(n801), .Y(n2544) );
XNOR2X4TS U2073 ( .A(n497), .B(n650), .Y(n888) );
XNOR2X4TS U2074 ( .A(n2902), .B(n755), .Y(n1323) );
XNOR2X4TS U2075 ( .A(n2902), .B(n879), .Y(n2316) );
XOR2X4TS U2076 ( .A(n890), .B(n1781), .Y(n1810) );
OAI22X4TS U2077 ( .A0(n790), .A1(mult_x_19_n1674), .B0(n1783), .B1(n2068),
.Y(n2018) );
OAI22X4TS U2078 ( .A0(n841), .A1(n1101), .B0(n1119), .B1(n2327), .Y(n1128)
);
OAI22X2TS U2079 ( .A0(n2069), .A1(n2068), .B0(n2330), .B1(mult_x_19_n1676),
.Y(n2083) );
XOR2X4TS U2080 ( .A(n892), .B(n1899), .Y(n911) );
XNOR2X4TS U2081 ( .A(n1869), .B(n2895), .Y(n1344) );
OAI2BB1X4TS U2082 ( .A0N(n1863), .A1N(n682), .B0(n893), .Y(n1899) );
OAI22X4TS U2083 ( .A0(n768), .A1(n894), .B0(n2485), .B1(mult_x_19_n1610),
.Y(n1340) );
OAI22X4TS U2084 ( .A0(n2222), .A1(n2485), .B0(n768), .B1(n895), .Y(n2217) );
XOR2X4TS U2085 ( .A(n1864), .B(n949), .Y(n1861) );
XOR2X4TS U2086 ( .A(n904), .B(n1868), .Y(n1864) );
OAI22X4TS U2087 ( .A0(n2318), .A1(n2317), .B0(n756), .B1(n2316), .Y(n2338)
);
XOR2X4TS U2088 ( .A(n599), .B(n727), .Y(n898) );
OAI22X4TS U2089 ( .A0(n1762), .A1(n1680), .B0(n757), .B1(n899), .Y(n1756) );
XNOR2X4TS U2090 ( .A(n1764), .B(n1763), .Y(n932) );
OR2X8TS U2091 ( .A(n1098), .B(n1097), .Y(n1966) );
XOR2X4TS U2092 ( .A(n1865), .B(n1866), .Y(n949) );
OAI22X4TS U2093 ( .A0(n804), .A1(n1344), .B0(n1867), .B1(n2223), .Y(n1866)
);
OAI22X4TS U2094 ( .A0(n2310), .A1(n1345), .B0(n2048), .B1(n1870), .Y(n1865)
);
XNOR2X4TS U2095 ( .A(n464), .B(n884), .Y(n1870) );
OAI22X4TS U2096 ( .A0(n406), .A1(n1029), .B0(n1034), .B1(n555), .Y(n902) );
XOR2X4TS U2097 ( .A(n905), .B(n870), .Y(n904) );
OAI22X4TS U2098 ( .A0(n975), .A1(n801), .B0(n784), .B1(mult_x_19_n1542), .Y(
n1336) );
OAI22X4TS U2099 ( .A0(n801), .A1(n1542), .B0(n1544), .B1(n783), .Y(n1555) );
OAI22X4TS U2100 ( .A0(n1352), .A1(n784), .B0(n855), .B1(mult_x_19_n1542),
.Y(n2342) );
OAI22X4TS U2101 ( .A0(n1316), .A1(n783), .B0(n1352), .B1(n801), .Y(n2335) );
OAI22X4TS U2102 ( .A0(n801), .A1(n2155), .B0(n1815), .B1(n783), .Y(n2144) );
OAI22X4TS U2103 ( .A0(n2154), .A1(n2041), .B0(n800), .B1(n1544), .Y(n1589)
);
OAI22X4TS U2104 ( .A0(n2154), .A1(n801), .B0(n2155), .B1(n2482), .Y(n2177)
);
OAI22X4TS U2105 ( .A0(n1317), .A1(n2482), .B0(n800), .B1(n1316), .Y(n2370)
);
OAI22X4TS U2106 ( .A0(n556), .A1(mult_x_19_n1753), .B0(n1760), .B1(n548),
.Y(n2236) );
INVX16TS U2107 ( .A(n906), .Y(n1300) );
AND2X8TS U2108 ( .A(n2914), .B(mult_x_19_n1801), .Y(n906) );
OAI22X4TS U2109 ( .A0(n2310), .A1(n2049), .B0(n499), .B1(n1806), .Y(n2047)
);
OAI22X4TS U2110 ( .A0(n2051), .A1(n1822), .B0(n499), .B1(n1583), .Y(n2146)
);
OAI22X4TS U2111 ( .A0(n2310), .A1(mult_x_19_n1635), .B0(n499), .B1(n1309),
.Y(n1315) );
OAI2BB1X4TS U2112 ( .A0N(n1593), .A1N(n1592), .B0(n907), .Y(n1577) );
OAI21X4TS U2113 ( .A0(n1593), .A1(n1592), .B0(n1591), .Y(n907) );
XOR2X4TS U2114 ( .A(n908), .B(n1593), .Y(n2275) );
XOR2X4TS U2115 ( .A(n1591), .B(n1592), .Y(n908) );
INVX16TS U2116 ( .A(n2885), .Y(n1814) );
NAND2X4TS U2117 ( .A(n611), .B(n1874), .Y(n909) );
OAI21X4TS U2118 ( .A0(n1876), .A1(n1874), .B0(n1875), .Y(n910) );
XOR2X4TS U2119 ( .A(n911), .B(n1898), .Y(n1900) );
XOR2X4TS U2120 ( .A(n2885), .B(n881), .Y(n1542) );
XNOR2X4TS U2121 ( .A(n732), .B(n878), .Y(n1784) );
XOR2X4TS U2122 ( .A(n702), .B(n646), .Y(n917) );
OAI22X4TS U2123 ( .A0(n406), .A1(n2331), .B0(n555), .B1(mult_x_19_n1751),
.Y(n2389) );
OAI22X4TS U2124 ( .A0(n406), .A1(n1034), .B0(n555), .B1(n1033), .Y(n1045) );
OAI22X4TS U2125 ( .A0(n1774), .A1(n744), .B0(n1797), .B1(n918), .Y(n1801) );
XOR2X4TS U2126 ( .A(n920), .B(n2188), .Y(mult_x_19_n692) );
OAI2BB1X4TS U2127 ( .A0N(n2178), .A1N(n922), .B0(n921), .Y(n2271) );
OAI22X4TS U2128 ( .A0(n2151), .A1(n1282), .B0(n1305), .B1(n667), .Y(n1327)
);
OAI22X1TS U2129 ( .A0(n1607), .A1(n667), .B0(n970), .B1(n969), .Y(n1614) );
OAI21X4TS U2130 ( .A0(n927), .A1(n424), .B0(n926), .Y(n244) );
XOR2X4TS U2131 ( .A(n2610), .B(n928), .Y(n927) );
OAI21X4TS U2132 ( .A0(n2606), .A1(n2605), .B0(n2604), .Y(n928) );
OAI22X4TS U2133 ( .A0(n1030), .A1(n785), .B0(n556), .B1(n1029), .Y(n2870) );
OAI21X4TS U2134 ( .A0(n2423), .A1(n2422), .B0(n2421), .Y(n930) );
XOR2X4TS U2135 ( .A(n931), .B(n2421), .Y(n2520) );
OAI22X4TS U2136 ( .A0(n1685), .A1(n553), .B0(n1686), .B1(n785), .Y(n1687) );
NAND2X8TS U2137 ( .A(n1982), .B(n937), .Y(n936) );
NOR2X8TS U2138 ( .A(n1978), .B(n2266), .Y(n937) );
NOR2X8TS U2139 ( .A(n1980), .B(n1979), .Y(n2266) );
OAI21X4TS U2140 ( .A0(n1291), .A1(n941), .B0(n1290), .Y(n940) );
XNOR2X4TS U2141 ( .A(n839), .B(n1090), .Y(n942) );
OAI22X4TS U2142 ( .A0(n959), .A1(n2468), .B0(n1812), .B1(n764), .Y(n2161) );
OAI2BB1X4TS U2143 ( .A0N(n2379), .A1N(n2378), .B0(n943), .Y(n2395) );
OAI22X4TS U2144 ( .A0(n2310), .A1(n944), .B0(n2307), .B1(n2309), .Y(n2376)
);
OAI22X4TS U2145 ( .A0(n2310), .A1(n945), .B0(n2307), .B1(n944), .Y(n2215) );
OAI22X4TS U2146 ( .A0(n1704), .A1(n437), .B0(n2307), .B1(n945), .Y(n1741) );
XOR2X4TS U2147 ( .A(n598), .B(n597), .Y(mult_x_19_n764) );
XOR2X4TS U2148 ( .A(n2106), .B(n2107), .Y(n950) );
OAI22X4TS U2149 ( .A0(n1773), .A1(n763), .B0(n951), .B1(n2227), .Y(n1777) );
OAI22X4TS U2150 ( .A0(n1812), .A1(n2227), .B0(n760), .B1(n951), .Y(n1836) );
OAI2BB1X4TS U2151 ( .A0N(n1764), .A1N(n1765), .B0(n952), .Y(n2229) );
OAI22X4TS U2152 ( .A0(n1031), .A1(n555), .B0(n785), .B1(n2903), .Y(n2869) );
OAI2BB2X4TS U2153 ( .B0(n956), .B1(n955), .A0N(n2183), .A1N(n2184), .Y(n2269) );
NAND2BX4TS U2154 ( .AN(n2183), .B(n958), .Y(n957) );
OAI22X4TS U2155 ( .A0(n2150), .A1(n2227), .B0(n764), .B1(n959), .Y(n2178) );
XOR2X4TS U2156 ( .A(n433), .B(n651), .Y(n959) );
ADDFHX4TS U2157 ( .A(n2293), .B(n2292), .CI(n2291), .CO(n2107), .S(
mult_x_19_n788) );
OAI22X2TS U2158 ( .A0(n2055), .A1(n1292), .B0(n1887), .B1(n1026), .Y(n1889)
);
XNOR2X4TS U2159 ( .A(n961), .B(n656), .Y(n960) );
XOR2X4TS U2160 ( .A(n1874), .B(n611), .Y(n961) );
XOR2X4TS U2161 ( .A(n786), .B(n3013), .Y(n2315) );
XOR2X4TS U2162 ( .A(n3013), .B(n2313), .Y(n2320) );
NAND2X1TS U2163 ( .A(n963), .B(n2197), .Y(n2199) );
OA21X4TS U2164 ( .A0(n3037), .A1(n3036), .B0(n3038), .Y(n962) );
NAND2X8TS U2165 ( .A(n631), .B(n3099), .Y(mult_x_19_n423) );
OAI22X4TS U2166 ( .A0(n2315), .A1(n803), .B0(n590), .B1(n968), .Y(n2343) );
XOR2X4TS U2167 ( .A(n3013), .B(n2476), .Y(n968) );
OAI2BB1X4TS U2168 ( .A0N(n1361), .A1N(n982), .B0(n983), .Y(mult_x_19_n874)
);
OAI22X4TS U2169 ( .A0(n802), .A1(n981), .B0(n2311), .B1(n976), .Y(n2374) );
XNOR2X4TS U2170 ( .A(n628), .B(n650), .Y(n1325) );
XNOR2X4TS U2171 ( .A(n2241), .B(n881), .Y(n1319) );
OAI21X4TS U2172 ( .A0(n982), .A1(n1361), .B0(n1360), .Y(n983) );
XOR2X4TS U2173 ( .A(n984), .B(n1360), .Y(mult_x_19_n875) );
OAI22X4TS U2174 ( .A0(n676), .A1(n985), .B0(n2471), .B1(n1284), .Y(n1290) );
XNOR2X4TS U2175 ( .A(n691), .B(n1884), .Y(n985) );
OAI22X4TS U2176 ( .A0(n1798), .A1(n742), .B0(n986), .B1(n2034), .Y(n1804) );
XOR2X4TS U2177 ( .A(n2238), .B(n693), .Y(n986) );
OAI2BB1X4TS U2178 ( .A0N(n708), .A1N(n2340), .B0(n987), .Y(n1351) );
XNOR2X4TS U2179 ( .A(n791), .B(n2476), .Y(n991) );
XNOR2X4TS U2180 ( .A(n2948), .B(n881), .Y(n1760) );
XOR2X4TS U2181 ( .A(n2221), .B(n605), .Y(n992) );
OAI22X4TS U2182 ( .A0(n993), .A1(n764), .B0(n1674), .B1(mult_x_19_n1587),
.Y(n1328) );
XOR2X4TS U2183 ( .A(n2319), .B(n605), .Y(n993) );
OAI22X2TS U2184 ( .A0(n1319), .A1(n2311), .B0(n2055), .B1(n994), .Y(n2417)
);
OAI2BB1X4TS U2185 ( .A0N(n2351), .A1N(n2352), .B0(n995), .Y(n1895) );
OAI21X4TS U2186 ( .A0(n2351), .A1(n2352), .B0(n2350), .Y(n995) );
OAI22X4TS U2187 ( .A0(n2055), .A1(n1324), .B0(n1292), .B1(n1014), .Y(n1343)
);
XOR2X4TS U2188 ( .A(n627), .B(n755), .Y(n1292) );
XOR2X4TS U2189 ( .A(n2947), .B(n2950), .Y(n1111) );
NAND2X2TS U2190 ( .A(n699), .B(n1247), .Y(n1248) );
OAI21X2TS U2191 ( .A0(n1642), .A1(n1991), .B0(n1643), .Y(n1180) );
INVX8TS U2192 ( .A(n1386), .Y(n1469) );
INVX6TS U2193 ( .A(n1260), .Y(n1237) );
AOI21X2TS U2194 ( .A0(n2667), .A1(n1531), .B0(n1530), .Y(n1532) );
ADDFHX2TS U2195 ( .A(n2449), .B(n2448), .CI(n2447), .CO(n2457), .S(n2507) );
AO22X4TS U2196 ( .A0(n2946), .A1(n651), .B0(n2474), .B1(n2238), .Y(n1503) );
NAND2X4TS U2197 ( .A(n2262), .B(n3101), .Y(mult_x_19_n110) );
AOI2BB2X2TS U2198 ( .B0(n2700), .B1(n2677), .A0N(n806), .A1N(n1625), .Y(
n3335) );
AOI21X4TS U2199 ( .A0(n1455), .A1(n1379), .B0(n1378), .Y(n1384) );
XNOR2X4TS U2200 ( .A(n492), .B(n398), .Y(n1704) );
XNOR2X4TS U2201 ( .A(n604), .B(n399), .Y(n2325) );
AOI21X4TS U2202 ( .A0(n2635), .A1(n2634), .B0(n2633), .Y(n2692) );
ADDFHX4TS U2203 ( .A(n1112), .B(n1113), .CI(n1114), .CO(n1160), .S(n1133) );
ADDFHX2TS U2204 ( .A(n1124), .B(n1123), .CI(n1122), .CO(n1158), .S(n1138) );
OAI21X4TS U2205 ( .A0(n1210), .A1(n1215), .B0(n1214), .Y(n1216) );
ADDFHX4TS U2206 ( .A(n1043), .B(n1042), .CI(n1041), .CO(n1048), .S(n1047) );
NAND2X8TS U2207 ( .A(n1904), .B(n1903), .Y(n2537) );
XNOR2X4TS U2208 ( .A(n1761), .B(n786), .Y(n1695) );
XNOR2X4TS U2209 ( .A(n1761), .B(n2476), .Y(n1680) );
ADDFHX4TS U2210 ( .A(n1835), .B(n1836), .CI(n1837), .CO(n2162), .S(n1839) );
ADDFHX4TS U2211 ( .A(n1775), .B(n1777), .CI(n1776), .CO(n1840), .S(n1809) );
OAI22X2TS U2212 ( .A0(n1762), .A1(n1035), .B0(n1028), .B1(n756), .Y(n1041)
);
OAI22X2TS U2213 ( .A0(n1762), .A1(n1057), .B0(n1058), .B1(n734), .Y(n1063)
);
OAI22X4TS U2214 ( .A0(n1796), .A1(n2900), .B0(n756), .B1(n1037), .Y(n1038)
);
OAI22X2TS U2215 ( .A0(n1762), .A1(n1022), .B0(n1057), .B1(n734), .Y(n1066)
);
OAI22X2TS U2216 ( .A0(n676), .A1(n2070), .B0(n2016), .B1(n799), .Y(n2042) );
OAI22X4TS U2217 ( .A0(n676), .A1(n2071), .B0(n2070), .B1(n2471), .Y(n2082)
);
ADDFHX4TS U2218 ( .A(n1811), .B(n1809), .CI(n1810), .CO(n2011), .S(n2025) );
OAI22X4TS U2219 ( .A0(n2041), .A1(n1771), .B0(n1780), .B1(n800), .Y(n1781)
);
ADDFHX4TS U2220 ( .A(n1803), .B(n1804), .CI(n1805), .CO(n2024), .S(n2063) );
OAI22X2TS U2221 ( .A0(n551), .A1(n601), .B0(n695), .B1(n646), .Y(n1551) );
XNOR2X4TS U2222 ( .A(n628), .B(n2313), .Y(n1676) );
XNOR2X4TS U2223 ( .A(n753), .B(n2313), .Y(n2016) );
INVX8TS U2224 ( .A(n2538), .Y(n2257) );
NOR2X8TS U2225 ( .A(n1904), .B(n1903), .Y(n2538) );
OAI21X4TS U2226 ( .A0(n1437), .A1(n1422), .B0(n1421), .Y(n1427) );
INVX6TS U2227 ( .A(n2692), .Y(n2735) );
XNOR2X4TS U2228 ( .A(n792), .B(n762), .Y(n1779) );
ADDFHX4TS U2229 ( .A(n1157), .B(n1156), .CI(n1155), .CO(n1726), .S(n1159) );
ADDFHX2TS U2230 ( .A(n2555), .B(n2554), .CI(n2553), .CO(mult_x_19_n639), .S(
n2556) );
ADDFHX4TS U2231 ( .A(n2101), .B(n2100), .CI(n2099), .CO(n2292), .S(n2295) );
OAI21X4TS U2232 ( .A0(n765), .A1(n1488), .B0(n1487), .Y(n1489) );
OAI22X4TS U2233 ( .A0(n1796), .A1(n1164), .B0(n1696), .B1(n734), .Y(n1721)
);
NAND2BX2TS U2234 ( .AN(n2904), .B(n2947), .Y(n1031) );
AOI21X4TS U2235 ( .A0(n2667), .A1(n1950), .B0(n1949), .Y(n1951) );
NOR2X4TS U2236 ( .A(n1940), .B(n1947), .Y(n1950) );
ADDFHX4TS U2237 ( .A(n1154), .B(n1153), .CI(n1152), .CO(n1727), .S(n1165) );
NAND2X2TS U2238 ( .A(n796), .B(n2675), .Y(n3305) );
AOI2BB2X2TS U2239 ( .B0(n1483), .B1(n2675), .A0N(n807), .A1N(n3127), .Y(
n3311) );
INVX8TS U2240 ( .A(n1483), .Y(n1669) );
ADDFHX4TS U2241 ( .A(n1167), .B(n1166), .CI(n1165), .CO(n1907), .S(n1170) );
INVX8TS U2242 ( .A(n1375), .Y(n1455) );
XNOR2X4TS U2243 ( .A(n365), .B(n366), .Y(n2924) );
XNOR2X4TS U2244 ( .A(n1884), .B(n2319), .Y(n1284) );
NAND2X4TS U2245 ( .A(n1404), .B(n1403), .Y(n1407) );
INVX4TS U2246 ( .A(n1387), .Y(n1404) );
OAI22X2TS U2247 ( .A0(n769), .A1(n2035), .B0(n1798), .B1(n2034), .Y(n2056)
);
BUFX20TS U2248 ( .A(n1817), .Y(n2034) );
NAND2X4TS U2249 ( .A(n2994), .B(n1009), .Y(n1177) );
ADDFHX4TS U2250 ( .A(n1135), .B(n1134), .CI(n1133), .CO(n1169), .S(n1136) );
XOR2X4TS U2251 ( .A(n1527), .B(n1526), .Y(Sgf_operation_Result[8]) );
AOI21X2TS U2252 ( .A0(n2251), .A1(n2252), .B0(n2250), .Y(n2253) );
NOR2X4TS U2253 ( .A(n1433), .B(n1423), .Y(n1262) );
MX2X6TS U2254 ( .A(n1657), .B(n3246), .S0(n586), .Y(n266) );
ADDFHX2TS U2255 ( .A(n2544), .B(n2543), .CI(n2542), .CO(n2554), .S(n2400) );
AO21X4TS U2256 ( .A0(n1796), .A1(n756), .B0(n2900), .Y(n2058) );
OAI22X4TS U2257 ( .A0(n838), .A1(n1109), .B0(n1108), .B1(n590), .Y(n1113) );
ADDFHX4TS U2258 ( .A(n1878), .B(n1877), .CI(n1879), .CO(n2510), .S(n1874) );
AOI21X4TS U2259 ( .A0(n2252), .A1(n1369), .B0(n1368), .Y(n1370) );
XNOR2X4TS U2260 ( .A(n2052), .B(n399), .Y(n1058) );
NOR2X4TS U2261 ( .A(n569), .B(n2979), .Y(n1638) );
XNOR2X4TS U2262 ( .A(n433), .B(n787), .Y(n2469) );
OAI22X2TS U2263 ( .A0(n802), .A1(n1107), .B0(n1106), .B1(n2311), .Y(n1114)
);
NAND2X4TS U2264 ( .A(n1246), .B(n1267), .Y(n1451) );
NAND2X4TS U2265 ( .A(n1268), .B(n1267), .Y(n1464) );
CMPR22X2TS U2266 ( .A(n2226), .B(n2225), .CO(n2367), .S(n2242) );
OAI22X2TS U2267 ( .A0(n677), .A1(n1745), .B0(n2220), .B1(n2322), .Y(n2226)
);
ADDFHX2TS U2268 ( .A(n2098), .B(n2097), .CI(n2096), .CO(n2104), .S(n2444) );
OAI22X4TS U2269 ( .A0(n2053), .A1(n2055), .B0(n1026), .B1(n2241), .Y(n2060)
);
OAI22X4TS U2270 ( .A0(n802), .A1(n1104), .B0(n1107), .B1(n1026), .Y(n1140)
);
AO21X4TS U2271 ( .A0(n2312), .A1(n1014), .B0(n2899), .Y(n1775) );
OAI22X2TS U2272 ( .A0(n802), .A1(n1017), .B0(n1056), .B1(n2311), .Y(n1076)
);
XOR2X4TS U2273 ( .A(n2865), .B(n2866), .Y(n2867) );
NAND2X2TS U2274 ( .A(n2864), .B(n2863), .Y(n2866) );
ADDFHX4TS U2275 ( .A(n2501), .B(n2500), .CI(n2499), .CO(n2534), .S(
mult_x_19_n604) );
ADDFHX4TS U2276 ( .A(n1522), .B(n1521), .CI(n1520), .CO(n2526), .S(n2500) );
ADDFHX4TS U2277 ( .A(n2492), .B(n2491), .CI(n2490), .CO(n2499), .S(n2497) );
NAND2X4TS U2278 ( .A(n2437), .B(n2436), .Y(mult_x_19_n112) );
CMPR22X2TS U2279 ( .A(n1120), .B(n1121), .CO(n1166), .S(n1122) );
NAND2X6TS U2280 ( .A(n1264), .B(n1263), .Y(n1403) );
NOR2X4TS U2281 ( .A(n1242), .B(n1264), .Y(n1376) );
NAND3X6TS U2282 ( .A(n3206), .B(n3205), .C(n3204), .Y(n2845) );
XNOR2X4TS U2283 ( .A(n2947), .B(n2476), .Y(n1686) );
ADDFHX2TS U2284 ( .A(n2467), .B(n2466), .CI(n2465), .CO(n2492), .S(n2495) );
ADDFHX2TS U2285 ( .A(n2217), .B(n2216), .CI(n2215), .CO(n2393), .S(n2245) );
NOR2X8TS U2286 ( .A(n1009), .B(n2984), .Y(n1179) );
ADDFHX4TS U2287 ( .A(n2161), .B(n2160), .CI(n2159), .CO(n2182), .S(n2141) );
NAND2X4TS U2288 ( .A(n2599), .B(n2604), .Y(n2600) );
NAND2X4TS U2289 ( .A(n2261), .B(n998), .Y(n375) );
NAND2X4TS U2290 ( .A(n1242), .B(n1264), .Y(n1377) );
NAND2X4TS U2291 ( .A(n2582), .B(n2581), .Y(n3354) );
NOR2X4TS U2292 ( .A(n1243), .B(n1265), .Y(n1245) );
ADDFHX4TS U2293 ( .A(n2426), .B(n2424), .CI(n2425), .CO(n2431), .S(n2394) );
ADDFHX4TS U2294 ( .A(n2408), .B(n2407), .CI(n2406), .CO(n2429), .S(n2425) );
NOR2X8TS U2295 ( .A(FSM_selector_B_1_), .B(n1228), .Y(n1223) );
XNOR2X4TS U2296 ( .A(n1474), .B(n1475), .Y(n1479) );
NOR2X4TS U2297 ( .A(n1474), .B(n1475), .Y(n1276) );
MXI2X4TS U2298 ( .A(n1419), .B(n1418), .S0(n427), .Y(n2786) );
XNOR2X4TS U2299 ( .A(n2947), .B(n601), .Y(n1110) );
ADDFHX4TS U2300 ( .A(n2382), .B(n2381), .CI(n2380), .CO(n2426), .S(n2378) );
BUFX3TS U2301 ( .A(n772), .Y(n3284) );
XNOR2X4TS U2302 ( .A(n1430), .B(n1429), .Y(n1431) );
OAI21X4TS U2303 ( .A0(n1439), .A1(n1433), .B0(n1434), .Y(n1430) );
ADDFHX4TS U2304 ( .A(n1025), .B(n1023), .CI(n1024), .CO(n1050), .S(n1049) );
OAI21X4TS U2305 ( .A0(n2249), .A1(n2967), .B0(n2968), .Y(n1367) );
AOI21X4TS U2306 ( .A0(n570), .A1(n571), .B0(n2983), .Y(n2249) );
OAI22X2TS U2307 ( .A0(n407), .A1(n2150), .B0(n1547), .B1(n2468), .Y(n1588)
);
OAI22X4TS U2308 ( .A0(n407), .A1(n1547), .B0(n1546), .B1(n2468), .Y(n1562)
);
OAI22X2TS U2309 ( .A0(n407), .A1(n1546), .B0(n1540), .B1(n2468), .Y(n1569)
);
OAI22X4TS U2310 ( .A0(n764), .A1(n1802), .B0(n1773), .B1(n2227), .Y(n1800)
);
OAI22X2TS U2311 ( .A0(n760), .A1(n2073), .B0(n2072), .B1(n2227), .Y(n2081)
);
OAI22X2TS U2312 ( .A0(n407), .A1(n604), .B0(n2468), .B1(n2888), .Y(n2477) );
OAI22X4TS U2313 ( .A0(n764), .A1(n1681), .B0(n1743), .B1(n2227), .Y(n1758)
);
OAI22X4TS U2314 ( .A0(n2072), .A1(n763), .B0(n1802), .B1(n2227), .Y(n2061)
);
OAI22X4TS U2315 ( .A0(n407), .A1(n2228), .B0(n2326), .B1(n2227), .Y(n2372)
);
ADDFHX2TS U2316 ( .A(n2385), .B(n2384), .CI(n2383), .CO(n2408), .S(n2392) );
ADDFHX4TS U2317 ( .A(n1826), .B(n1825), .CI(n1824), .CO(n2137), .S(n2030) );
ADDFHX2TS U2318 ( .A(n655), .B(n2478), .CI(n2477), .CO(n1510), .S(n2488) );
ADDFHX2TS U2319 ( .A(n1569), .B(n1568), .CI(n1567), .CO(n2401), .S(n1573) );
NOR2X2TS U2320 ( .A(n664), .B(Sgf_normalized_result[0]), .Y(n2591) );
XNOR2X4TS U2321 ( .A(n2052), .B(n828), .Y(n1028) );
XNOR2X4TS U2322 ( .A(n791), .B(n2794), .Y(n1282) );
ADDFHX4TS U2323 ( .A(n2141), .B(n2140), .CI(n2139), .CO(n2187), .S(n2138) );
XNOR2X4TS U2324 ( .A(n797), .B(n786), .Y(n1815) );
XNOR2X4TS U2325 ( .A(n797), .B(n2476), .Y(n2155) );
ADDFHX4TS U2326 ( .A(n2346), .B(n2345), .CI(n2344), .CO(n2350), .S(n2353) );
NOR2X8TS U2327 ( .A(n1443), .B(n1442), .Y(n1414) );
INVX6TS U2328 ( .A(n1254), .Y(n1443) );
XNOR2X4TS U2329 ( .A(n2013), .B(n398), .Y(n1693) );
XNOR2X4TS U2330 ( .A(n999), .B(n1630), .Y(n1631) );
XNOR2X4TS U2331 ( .A(n2241), .B(n2796), .Y(n1017) );
XNOR2X4TS U2332 ( .A(n1536), .B(n1535), .Y(n1537) );
ADDFHX4TS U2333 ( .A(n1147), .B(n1146), .CI(n1145), .CO(n1137), .S(n1972) );
NAND3X4TS U2334 ( .A(n3223), .B(n3222), .C(n3221), .Y(n2856) );
ADDFHX2TS U2335 ( .A(n2547), .B(n2546), .CI(n2545), .CO(n2487), .S(n2553) );
AOI21X4TS U2336 ( .A0(n1213), .A1(n1849), .B0(n1212), .Y(n1214) );
ADDFHX4TS U2337 ( .A(n2271), .B(n2270), .CI(n2269), .CO(n2280), .S(n2272) );
AOI2BB2X4TS U2338 ( .B0(n2700), .B1(n265), .A0N(n806), .A1N(n3146), .Y(n2626) );
OAI21X4TS U2339 ( .A0(n2198), .A1(n2976), .B0(n2007), .Y(n2008) );
ADDFHX4TS U2340 ( .A(n2461), .B(n2460), .CI(n2459), .CO(n2462), .S(
mult_x_19_n832) );
ADDFHX4TS U2341 ( .A(n2357), .B(n2356), .CI(n2355), .CO(n1361), .S(n2358) );
ADDFHX4TS U2342 ( .A(n1331), .B(n1330), .CI(n1329), .CO(n1897), .S(n2356) );
ADDFHX2TS U2343 ( .A(n1575), .B(n1574), .CI(n1573), .CO(n2403), .S(n2399) );
ADDFHX4TS U2344 ( .A(n2519), .B(n2518), .CI(n2517), .CO(n2289), .S(n2524) );
XNOR2X4TS U2345 ( .A(n2218), .B(n2313), .Y(n2219) );
OR2X8TS U2346 ( .A(n1616), .B(n1615), .Y(n2287) );
ADDFHX4TS U2347 ( .A(n1610), .B(n1608), .CI(n1609), .CO(n1616), .S(n1903) );
NOR2X6TS U2348 ( .A(n1939), .B(n1941), .Y(n1944) );
ADDFHX2TS U2349 ( .A(n398), .B(n798), .CI(n1787), .CO(n1828), .S(n1793) );
XNOR2X4TS U2350 ( .A(n2052), .B(n2793), .Y(n1057) );
OAI22X2TS U2351 ( .A0(n768), .A1(n2222), .B0(n2333), .B1(n2485), .Y(n2383)
);
OAI22X2TS U2352 ( .A0(n769), .A1(n2889), .B0(n1151), .B1(n842), .Y(n1715) );
OAI22X2TS U2353 ( .A0(n767), .A1(n2333), .B0(n2332), .B1(n2485), .Y(n2388)
);
XNOR2X4TS U2354 ( .A(n878), .B(n867), .Y(n2321) );
NOR2X8TS U2355 ( .A(n1149), .B(n1148), .Y(n2433) );
ADDFHX4TS U2356 ( .A(n1711), .B(n1710), .CI(n1709), .CO(n1751), .S(n1718) );
ADDFHX4TS U2357 ( .A(n2021), .B(n2020), .CI(n2019), .CO(n2027), .S(n2087) );
NOR2X8TS U2358 ( .A(n1204), .B(n2660), .Y(n2651) );
NAND2X6TS U2359 ( .A(n2671), .B(n2659), .Y(n1204) );
NAND2X4TS U2360 ( .A(n2843), .B(n2850), .Y(n2716) );
NOR2X8TS U2361 ( .A(n1005), .B(n2977), .Y(n2122) );
ADDFHX4TS U2362 ( .A(n2455), .B(n2454), .CI(n2453), .CO(n2505), .S(n2509) );
XNOR2X4TS U2363 ( .A(n792), .B(n786), .Y(n2152) );
OAI22X2TS U2364 ( .A0(n1885), .A1(n676), .B0(n2071), .B1(n799), .Y(n2093) );
XNOR2X4TS U2365 ( .A(n1884), .B(n762), .Y(n2071) );
NAND2BX2TS U2366 ( .AN(n789), .B(n969), .Y(n1307) );
ADDFHX2TS U2367 ( .A(n663), .B(n2243), .CI(n2242), .CO(n2380), .S(n2244) );
NOR2X4TS U2368 ( .A(n1452), .B(n1249), .Y(n1251) );
NOR2X4TS U2369 ( .A(n699), .B(n1247), .Y(n1249) );
OAI21X2TS U2370 ( .A0(n1942), .A1(n1941), .B0(n583), .Y(n1943) );
ADDFHX4TS U2371 ( .A(n1909), .B(n1908), .CI(n1907), .CO(n1962), .S(n1913) );
ADDFHX2TS U2372 ( .A(n1581), .B(n1580), .CI(n1579), .CO(n1576), .S(n2277) );
NAND2X4TS U2373 ( .A(n2435), .B(n2434), .Y(mult_x_19_n113) );
XNOR2X4TS U2374 ( .A(n2218), .B(n881), .Y(n1299) );
ADDFHX4TS U2375 ( .A(n2173), .B(n2172), .CI(n2171), .CO(n2274), .S(n2186) );
AOI21X2TS U2376 ( .A0(n1929), .A1(n1928), .B0(n1927), .Y(n1930) );
NOR2X4TS U2377 ( .A(n1922), .B(n1925), .Y(n1928) );
ADDFHX4TS U2378 ( .A(n1731), .B(n1730), .CI(n1729), .CO(n1767), .S(n1958) );
OAI22X4TS U2379 ( .A0(n1796), .A1(n1302), .B0(n1886), .B1(n756), .Y(n1881)
);
XNOR2X4TS U2380 ( .A(n791), .B(n638), .Y(n1289) );
XNOR2X4TS U2381 ( .A(n705), .B(n638), .Y(n1108) );
XNOR2X4TS U2382 ( .A(n2218), .B(n1869), .Y(n1320) );
XNOR2X4TS U2383 ( .A(n2947), .B(n879), .Y(n2331) );
XNOR2X4TS U2384 ( .A(n604), .B(n762), .Y(n1303) );
AOI21X2TS U2385 ( .A0(n1929), .A1(n1660), .B0(n1659), .Y(n1661) );
ADDFHX4TS U2386 ( .A(n2175), .B(n2174), .CI(n2176), .CO(n2276), .S(n2273) );
ADDFHX4TS U2387 ( .A(n2024), .B(n2023), .CI(n2022), .CO(n2029), .S(n2066) );
ADDFHX2TS U2388 ( .A(n2373), .B(n2372), .CI(n2371), .CO(n2419), .S(n2366) );
OAI21X4TS U2389 ( .A0(n1855), .A1(n567), .B0(n1856), .Y(n2115) );
NAND2X4TS U2390 ( .A(n573), .B(n3061), .Y(n1856) );
ADDFHX4TS U2391 ( .A(n1718), .B(n1719), .CI(n1717), .CO(n1747), .S(n1960) );
ADDFHX4TS U2392 ( .A(n2164), .B(n2163), .CI(n2162), .CO(n2168), .S(n2134) );
ADDFHX4TS U2393 ( .A(n1834), .B(n1833), .CI(n1832), .CO(n2163), .S(n1838) );
XNOR2X4TS U2394 ( .A(n1814), .B(n2313), .Y(n1780) );
OAI21X4TS U2395 ( .A0(n2865), .A1(n2862), .B0(n2863), .Y(n2598) );
AOI21X4TS U2396 ( .A0(n2780), .A1(n2779), .B0(n1040), .Y(n2865) );
XNOR2X4TS U2397 ( .A(n787), .B(n690), .Y(n1783) );
XNOR2X4TS U2398 ( .A(n753), .B(n2476), .Y(n1778) );
ADDFHX4TS U2399 ( .A(n2504), .B(n2503), .CI(n2502), .CO(n2513), .S(n1898) );
XNOR2X4TS U2400 ( .A(n2948), .B(n668), .Y(n1308) );
XOR2X4TS U2401 ( .A(n2255), .B(n2918), .Y(n2256) );
ADDFHX4TS U2402 ( .A(n2089), .B(n2088), .CI(n2087), .CO(n2067), .S(n2298) );
AND2X8TS U2403 ( .A(n2586), .B(n2585), .Y(n2835) );
OAI22X2TS U2404 ( .A0(n437), .A1(n1115), .B0(n1162), .B1(n2048), .Y(n1155)
);
OAI22X2TS U2405 ( .A0(n1300), .A1(n1099), .B0(n1115), .B1(n2048), .Y(n1121)
);
INVX6TS U2406 ( .A(n2635), .Y(n2858) );
OAI21X4TS U2407 ( .A0(n2591), .A1(n3138), .B0(n2590), .Y(n2635) );
XNOR2X4TS U2408 ( .A(n2902), .B(n650), .Y(n2317) );
AO21X4TS U2409 ( .A0(n841), .A1(n1813), .B0(n2896), .Y(n2159) );
OAI22X2TS U2410 ( .A0(n2330), .A1(n2069), .B0(mult_x_19_n1674), .B1(n2068),
.Y(n2059) );
OAI22X2TS U2411 ( .A0(n790), .A1(n1702), .B0(n1744), .B1(n1813), .Y(n1740)
);
OAI22X2TS U2412 ( .A0(n841), .A1(n1119), .B0(n1118), .B1(n1813), .Y(n1123)
);
OAI22X2TS U2413 ( .A0(n790), .A1(n1082), .B0(n1101), .B1(n2327), .Y(n1131)
);
OAI22X2TS U2414 ( .A0(n790), .A1(n2329), .B0(n2328), .B1(n2327), .Y(n2390)
);
OAI22X2TS U2415 ( .A0(n790), .A1(mult_x_19_n1677), .B0(mult_x_19_n1676),
.B1(n2068), .Y(n2095) );
XNOR2X4TS U2416 ( .A(n2218), .B(n646), .Y(n2329) );
XNOR2X4TS U2417 ( .A(n1761), .B(n2796), .Y(n1035) );
ADDFHX4TS U2418 ( .A(n2528), .B(n2526), .CI(n2527), .CO(n2536), .S(n2533) );
XOR2X4TS U2419 ( .A(n619), .B(n824), .Y(n2473) );
XOR2X4TS U2420 ( .A(n2952), .B(n824), .Y(n1823) );
XNOR2X4TS U2421 ( .A(n500), .B(n824), .Y(n1505) );
XOR2X4TS U2422 ( .A(n2951), .B(n824), .Y(n1322) );
ADDFHX4TS U2423 ( .A(n2064), .B(n2062), .CI(n2063), .CO(n2026), .S(n2291) );
ADDFHX4TS U2424 ( .A(n1351), .B(n1349), .CI(n1350), .CO(n2351), .S(n2288) );
XNOR2X4TS U2425 ( .A(n2239), .B(n639), .Y(n1022) );
XNOR2X4TS U2426 ( .A(n1884), .B(n638), .Y(n2323) );
ADDFHX4TS U2427 ( .A(n2234), .B(n2233), .CI(n2232), .CO(n2379), .S(n2230) );
AO21X4TS U2428 ( .A0(n2310), .A1(n2307), .B0(n2891), .Y(n1564) );
ADDFHX4TS U2429 ( .A(n1977), .B(n1976), .CI(n1975), .CO(n1979), .S(n1098) );
ADDFHX2TS U2430 ( .A(n2417), .B(n2416), .CI(n2415), .CO(n2517), .S(n2522) );
ADDFHX2TS U2431 ( .A(n671), .B(n762), .CI(n1549), .CO(n1561), .S(n2180) );
XNOR2X4TS U2432 ( .A(n1884), .B(n671), .Y(n1885) );
XNOR2X4TS U2433 ( .A(n693), .B(n2313), .Y(n1304) );
OAI22X2TS U2434 ( .A0(n2055), .A1(n1018), .B0(n1017), .B1(n2311), .Y(n1020)
);
XNOR2X4TS U2435 ( .A(n693), .B(n2796), .Y(n1694) );
ADDFHX4TS U2436 ( .A(n2170), .B(n2169), .CI(n2168), .CO(n2189), .S(n2185) );
INVX4TS U2437 ( .A(n2433), .Y(n2435) );
OAI21X4TS U2438 ( .A0(n2433), .A1(n2282), .B0(n2434), .Y(mult_x_19_n466) );
XNOR2X4TS U2439 ( .A(n1623), .B(n1622), .Y(n1624) );
MX2X6TS U2440 ( .A(n1668), .B(n3245), .S0(n586), .Y(n265) );
ADDFHX2TS U2441 ( .A(n737), .B(n2077), .CI(n2076), .CO(n2447), .S(n2450) );
ADDFHX2TS U2442 ( .A(n2080), .B(n2078), .CI(n2079), .CO(n2443), .S(n2438) );
ADDFHX4TS U2443 ( .A(n1572), .B(n1571), .CI(n1570), .CO(mult_x_19_n647), .S(
mult_x_19_n648) );
XNOR2X4TS U2444 ( .A(n2948), .B(n828), .Y(n1034) );
XNOR2X4TS U2445 ( .A(n2218), .B(n828), .Y(n1082) );
XOR2X4TS U2446 ( .A(n690), .B(n659), .Y(n1059) );
OAI22X2TS U2447 ( .A0(n2330), .A1(n2898), .B0(n2068), .B1(n2896), .Y(n1830)
);
NAND2BX2TS U2448 ( .AN(n2904), .B(n2898), .Y(n1062) );
XNOR2X4TS U2449 ( .A(n2898), .B(n638), .Y(n1101) );
ADDFHX4TS U2450 ( .A(n1563), .B(n1562), .CI(n1561), .CO(n1575), .S(n1592) );
ADDFHX2TS U2451 ( .A(n1519), .B(n1518), .CI(n1517), .CO(n1599), .S(n1520) );
ADDFHX4TS U2452 ( .A(n2030), .B(n2029), .CI(n2028), .CO(n1842), .S(n2031) );
ADDFHX4TS U2453 ( .A(n2027), .B(n2026), .CI(n2025), .CO(n2028), .S(n2065) );
OAI21X2TS U2454 ( .A0(n1199), .A1(n2645), .B0(n1198), .Y(n1200) );
NAND2X4TS U2455 ( .A(n579), .B(n2997), .Y(n2645) );
XNOR2X4TS U2456 ( .A(n1761), .B(n2313), .Y(n1696) );
INVX16TS U2457 ( .A(n2901), .Y(n1761) );
XNOR2X4TS U2458 ( .A(n511), .B(n672), .Y(n1774) );
NOR2X6TS U2459 ( .A(n1236), .B(n1257), .Y(n1422) );
NAND2X4TS U2460 ( .A(n1236), .B(n1257), .Y(n1421) );
ADDFHX4TS U2461 ( .A(n2280), .B(n2279), .CI(n2278), .CO(mult_x_19_n675), .S(
mult_x_19_n676) );
ADDFHX4TS U2462 ( .A(n2277), .B(n2276), .CI(n2275), .CO(n2397), .S(n2278) );
XNOR2X4TS U2463 ( .A(n1814), .B(n1869), .Y(n1544) );
XNOR2X4TS U2464 ( .A(n693), .B(n786), .Y(n1893) );
ADDFHX4TS U2465 ( .A(n1298), .B(n1297), .CI(n1296), .CO(n1876), .S(n2357) );
ADDFHX4TS U2466 ( .A(n1872), .B(n1873), .CI(n1871), .CO(n2502), .S(n1875) );
ADDFHX2TS U2467 ( .A(n692), .B(n1831), .CI(n1830), .CO(n2164), .S(n1827) );
XNOR2X4TS U2468 ( .A(n792), .B(n601), .Y(n2153) );
XOR2X4TS U2469 ( .A(n1437), .B(n1436), .Y(n1441) );
OR2X8TS U2470 ( .A(n1172), .B(n1171), .Y(n2437) );
ADDFHX4TS U2471 ( .A(n1915), .B(n1914), .CI(n1913), .CO(n1965), .S(n1172) );
XNOR2X4TS U2472 ( .A(n2892), .B(n639), .Y(n1684) );
XNOR2X4TS U2473 ( .A(n2902), .B(n668), .Y(n1886) );
ADDFHX4TS U2474 ( .A(n1752), .B(n1751), .CI(n1750), .CO(n2231), .S(n1748) );
ADDFHX4TS U2475 ( .A(n2396), .B(n2395), .CI(n2394), .CO(mult_x_19_n976), .S(
mult_x_19_n977) );
ADDFHX4TS U2476 ( .A(n2414), .B(n2413), .CI(n2412), .CO(n2427), .S(n2396) );
XNOR2X4TS U2477 ( .A(n464), .B(n828), .Y(n1162) );
XNOR2X4TS U2478 ( .A(n2948), .B(n884), .Y(n1685) );
XNOR2X4TS U2479 ( .A(n693), .B(n884), .Y(n2035) );
XNOR2X4TS U2480 ( .A(n497), .B(n884), .Y(n2154) );
XNOR2X4TS U2481 ( .A(n644), .B(n884), .Y(n1773) );
OAI22X2TS U2482 ( .A0(n767), .A1(n1584), .B0(n1548), .B1(n842), .Y(n2181) );
OAI21X4TS U2483 ( .A0(n2664), .A1(n1204), .B0(n1203), .Y(n2650) );
OAI2BB2X2TS U2484 ( .B0(n3098), .B1(n671), .A0N(n2474), .A1N(n674), .Y(n1831) );
ADDFHX4TS U2485 ( .A(n1897), .B(n1896), .CI(n1895), .CO(n1901), .S(n1360) );
ADDFHX4TS U2486 ( .A(n2498), .B(n2497), .CI(n2496), .CO(mult_x_19_n613), .S(
mult_x_19_n614) );
XNOR2X4TS U2487 ( .A(n2218), .B(n884), .Y(n1321) );
OAI22X2TS U2488 ( .A0(n790), .A1(n1061), .B0(n1060), .B1(n2327), .Y(n1070)
);
XNOR2X4TS U2489 ( .A(n2898), .B(n2221), .Y(n1163) );
XNOR2X4TS U2490 ( .A(n792), .B(n2319), .Y(n1797) );
XNOR2X4TS U2491 ( .A(n969), .B(n798), .Y(n1894) );
XNOR2X4TS U2492 ( .A(n791), .B(n429), .Y(n2038) );
XNOR2X4TS U2493 ( .A(n645), .B(n761), .Y(n2015) );
XNOR2X4TS U2494 ( .A(n693), .B(n1869), .Y(n1798) );
ADDFHX4TS U2495 ( .A(n3056), .B(n3055), .CI(n3057), .CO(n1007), .S(n1005) );
XNOR2X4TS U2496 ( .A(n2898), .B(n398), .Y(n1118) );
ADDFHX4TS U2497 ( .A(n2138), .B(n2137), .CI(n2136), .CO(n2166), .S(n1841) );
ADDFHX2TS U2498 ( .A(n868), .B(n1611), .CI(n879), .CO(n2130), .S(n1612) );
XNOR2X4TS U2499 ( .A(n433), .B(n879), .Y(n2150) );
XNOR2X4TS U2500 ( .A(n500), .B(n879), .Y(n2481) );
XNOR2X4TS U2501 ( .A(n2013), .B(n879), .Y(n2074) );
NAND2X8TS U2502 ( .A(n1235), .B(n1227), .Y(n1256) );
INVX16TS U2503 ( .A(n1223), .Y(n1235) );
XNOR2X4TS U2504 ( .A(n792), .B(n2221), .Y(n2037) );
NOR2X4TS U2505 ( .A(n1047), .B(n1046), .Y(n2862) );
XNOR2X4TS U2506 ( .A(n645), .B(n2221), .Y(n1883) );
XNOR2X4TS U2507 ( .A(n2218), .B(n736), .Y(n1060) );
ADDFHX4TS U2508 ( .A(n1348), .B(n1346), .CI(n1347), .CO(n1862), .S(n2352) );
NOR2X8TS U2509 ( .A(n2728), .B(n2688), .Y(n2734) );
XNOR2X4TS U2510 ( .A(n791), .B(n2796), .Y(n1305) );
ADDFHX4TS U2511 ( .A(n2393), .B(n2392), .CI(n2391), .CO(n2424), .S(n2362) );
XNOR2X4TS U2512 ( .A(n433), .B(n868), .Y(n1547) );
ADDFHX4TS U2513 ( .A(n1076), .B(n1075), .CI(n1074), .CO(n1077), .S(n1051) );
ADDFHX4TS U2514 ( .A(n2360), .B(n2359), .CI(n2358), .CO(mult_x_19_n896), .S(
mult_x_19_n897) );
XNOR2X4TS U2515 ( .A(n1090), .B(n2221), .Y(n1054) );
XNOR2X4TS U2516 ( .A(n2237), .B(n761), .Y(n2308) );
ADDFHX4TS U2517 ( .A(n3030), .B(n3031), .CI(n3032), .CO(n1187), .S(n1186) );
XNOR2X4TS U2518 ( .A(n2218), .B(n686), .Y(n2328) );
INVX16TS U2519 ( .A(n2897), .Y(n2218) );
ADDFHX4TS U2520 ( .A(n2274), .B(n2273), .CI(n2272), .CO(n2279), .S(n2188) );
OAI22X2TS U2521 ( .A0(n784), .A1(n2884), .B0(n800), .B1(n1318), .Y(n2369) );
NAND2X8TS U2522 ( .A(mult_x_19_n1797), .B(mult_x_19_n58), .Y(n2482) );
NAND2X4TS U2523 ( .A(n2870), .B(n2869), .Y(n2871) );
XNOR2X4TS U2524 ( .A(n1090), .B(n399), .Y(n1019) );
ADDFHX2TS U2525 ( .A(n863), .B(n824), .CI(n2562), .CO(n2569), .S(n2560) );
XNOR2X4TS U2526 ( .A(n883), .B(n863), .Y(n2472) );
XNOR2X4TS U2527 ( .A(n433), .B(n863), .Y(n1540) );
XNOR2X4TS U2528 ( .A(n500), .B(n732), .Y(n1501) );
XNOR2X4TS U2529 ( .A(n2902), .B(n732), .Y(n1302) );
XNOR2X4TS U2530 ( .A(mult_x_19_n1697), .B(n863), .Y(n2054) );
XNOR2X4TS U2531 ( .A(n1814), .B(n2794), .Y(n1352) );
XOR2X4TS U2532 ( .A(n2890), .B(n3066), .Y(n1819) );
XNOR2X4TS U2533 ( .A(n2890), .B(n398), .Y(n2222) );
XNOR2X4TS U2534 ( .A(n780), .B(n691), .Y(n2333) );
XNOR2X4TS U2535 ( .A(n780), .B(n839), .Y(n2332) );
XNOR2X4TS U2536 ( .A(n755), .B(n2890), .Y(n1818) );
XOR2X4TS U2537 ( .A(n2890), .B(n669), .Y(n1545) );
XNOR2X4TS U2538 ( .A(n2890), .B(n2906), .Y(n1584) );
ADDFHX4TS U2539 ( .A(n2531), .B(n2530), .CI(n2529), .CO(n1904), .S(n2535) );
XNOR2X4TS U2540 ( .A(n644), .B(n2796), .Y(n1681) );
ADDFHX4TS U2541 ( .A(n2399), .B(n2398), .CI(n2397), .CO(mult_x_19_n661), .S(
mult_x_19_n662) );
ADDFHX4TS U2542 ( .A(n1960), .B(n1959), .CI(n1958), .CO(n1956), .S(n1971) );
OAI21X4TS U2543 ( .A0(n1179), .A1(n1178), .B0(n1177), .Y(n1988) );
NAND2X4TS U2544 ( .A(n1149), .B(n1148), .Y(n2434) );
ADDFHX4TS U2545 ( .A(n1170), .B(n1169), .CI(n1168), .CO(n1171), .S(n1149) );
XNOR2X4TS U2546 ( .A(n2947), .B(n2796), .Y(n1029) );
BUFX20TS U2547 ( .A(n736), .Y(n2796) );
ADDFHX4TS U2548 ( .A(n3020), .B(n3021), .CI(n3022), .CO(n1009), .S(n1008) );
XNOR2X4TS U2549 ( .A(n1761), .B(n762), .Y(n1116) );
BUFX20TS U2550 ( .A(n1293), .Y(n1796) );
XNOR2X4TS U2551 ( .A(n705), .B(n2319), .Y(n1675) );
ADDFHX4TS U2552 ( .A(n1073), .B(n1072), .CI(n1071), .CO(n1079), .S(n1078) );
OR2X8TS U2553 ( .A(n1486), .B(n998), .Y(n2611) );
ADDFHX4TS U2554 ( .A(n1974), .B(n1973), .CI(n1972), .CO(n2190), .S(n1980) );
ADDFHX2TS U2555 ( .A(n601), .B(n867), .CI(n1557), .CO(n2552), .S(n1560) );
XNOR2X4TS U2556 ( .A(n2218), .B(n2908), .Y(n1744) );
XNOR2X4TS U2557 ( .A(mult_x_19_n1697), .B(n867), .Y(n1712) );
XNOR2X4TS U2558 ( .A(n753), .B(n867), .Y(n2070) );
XNOR2X4TS U2559 ( .A(n878), .B(n668), .Y(n1821) );
ADDFHX4TS U2560 ( .A(n2432), .B(n2431), .CI(n2430), .CO(mult_x_19_n958), .S(
mult_x_19_n959) );
XNOR2X4TS U2561 ( .A(n878), .B(n2796), .Y(n1103) );
XNOR2X4TS U2562 ( .A(n1884), .B(n2793), .Y(n1359) );
INVX16TS U2563 ( .A(n2887), .Y(n1884) );
XNOR2X4TS U2564 ( .A(n1814), .B(n736), .Y(n1316) );
ADDFHX4TS U2565 ( .A(n1962), .B(n1963), .CI(n1961), .CO(n1970), .S(n1964) );
XNOR2X4TS U2566 ( .A(n433), .B(n824), .Y(n1546) );
CMPR22X2TS U2567 ( .A(n1126), .B(n1125), .CO(n1147), .S(n1142) );
XNOR2X4TS U2568 ( .A(n464), .B(n2313), .Y(n1309) );
XNOR2X4TS U2569 ( .A(n2239), .B(n2238), .Y(n2306) );
MXI2X4TS U2570 ( .A(n3136), .B(n3103), .S0(FSM_selector_A), .Y(n1442) );
MXI2X4TS U2571 ( .A(n3117), .B(n3104), .S0(FSM_selector_A), .Y(n1257) );
MXI2X4TS U2572 ( .A(n3115), .B(n3105), .S0(n434), .Y(n1265) );
INVX2TS U2573 ( .A(n1398), .Y(n1395) );
ADDFHX4TS U2574 ( .A(n1138), .B(n1137), .CI(n1136), .CO(n1148), .S(n2191) );
OAI2BB2X2TS U2575 ( .B0(n714), .B1(n868), .A0N(n2946), .A1N(n3095), .Y(n1603) );
ADDFHX4TS U2576 ( .A(n2067), .B(n2066), .CI(n2065), .CO(n2032), .S(n2106) );
XNOR2X4TS U2577 ( .A(n1427), .B(n1426), .Y(n1432) );
XNOR2X4TS U2578 ( .A(n878), .B(n2794), .Y(n1109) );
BUFX20TS U2579 ( .A(n648), .Y(n2794) );
XNOR2X4TS U2580 ( .A(n2898), .B(n2793), .Y(n1119) );
CMPR22X2TS U2581 ( .A(n1715), .B(n1716), .CO(n1723), .S(n1728) );
OAI22X2TS U2582 ( .A0(n767), .A1(n1150), .B0(n1694), .B1(n2034), .Y(n1716)
);
ADDFHX4TS U2583 ( .A(n3009), .B(n3010), .CI(n3011), .CO(n1185), .S(n1184) );
OR2X8TS U2584 ( .A(n1211), .B(n2974), .Y(n1848) );
AND2X4TS U2585 ( .A(n1928), .B(n426), .Y(n1000) );
XOR2X1TS U2586 ( .A(mult_x_19_n7), .B(n348), .Y(n1001) );
BUFX3TS U2587 ( .A(n817), .Y(n2575) );
INVX2TS U2588 ( .A(n2631), .Y(n2615) );
NAND2X4TS U2589 ( .A(n1406), .B(n2788), .Y(n1410) );
INVX2TS U2590 ( .A(n2266), .Y(n2268) );
XOR2X2TS U2591 ( .A(n2737), .B(n2736), .Y(n2738) );
INVX2TS U2592 ( .A(n2566), .Y(mult_x_19_n135) );
INVX2TS U2593 ( .A(mult_x_19_n43), .Y(n2926) );
NAND2X4TS U2594 ( .A(n1374), .B(n2687), .Y(n235) );
NOR2X8TS U2595 ( .A(n3217), .B(n3216), .Y(n1938) );
NOR2X8TS U2596 ( .A(n2584), .B(FS_Module_state_reg[1]), .Y(n2213) );
MX2X4TS U2597 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n2263), .Y(n348) );
AOI21X4TS U2604 ( .A0(n3058), .A1(n3059), .B0(n3060), .Y(n2197) );
CLKBUFX2TS U2605 ( .A(n1178), .Y(n2109) );
CLKINVX1TS U2606 ( .A(n1179), .Y(n1010) );
NAND2X1TS U2607 ( .A(n1010), .B(n1177), .Y(n1011) );
XNOR2X4TS U2608 ( .A(n1012), .B(n1011), .Y(n1013) );
XOR2X4TS U2609 ( .A(n617), .B(n670), .Y(n1015) );
NOR2BX1TS U2610 ( .AN(n789), .B(n1014), .Y(n1043) );
XNOR2X1TS U2611 ( .A(n2948), .B(n870), .Y(n1030) );
OAI21X4TS U2612 ( .A0(n2773), .A1(n2871), .B0(n2774), .Y(n2780) );
NAND2BX1TS U2613 ( .AN(n2904), .B(n2052), .Y(n1037) );
ADDFHX4TS U2614 ( .A(n1096), .B(n1095), .CI(n1094), .CO(n1097), .S(n1080) );
OAI21X4TS U2615 ( .A0(n1978), .A1(n603), .B0(n1981), .Y(mult_x_19_n480) );
BUFX8TS U2616 ( .A(n1817), .Y(n2485) );
ADDFHX4TS U2617 ( .A(n1142), .B(n1143), .CI(n1144), .CO(n1973), .S(n1975) );
BUFX20TS U2618 ( .A(n2915), .Y(n1817) );
INVX2TS U2619 ( .A(n2436), .Y(n1173) );
AOI21X4TS U2620 ( .A0(mult_x_19_n466), .A1(n2437), .B0(n1173), .Y(
mult_x_19_n459) );
NOR2X8TS U2621 ( .A(n2258), .B(n2697), .Y(n1195) );
ADDFHX4TS U2622 ( .A(n3006), .B(n3007), .CI(n3008), .CO(n1183), .S(n1182) );
NAND2X1TS U2623 ( .A(n2641), .B(n2646), .Y(n1192) );
INVX2TS U2624 ( .A(n2645), .Y(n1190) );
AOI21X1TS U2625 ( .A0(n2642), .A1(n2646), .B0(n1190), .Y(n1191) );
INVX2TS U2626 ( .A(n1199), .Y(n1193) );
NAND2X4TS U2627 ( .A(n2641), .B(n1201), .Y(n1619) );
ADDFHX4TS U2628 ( .A(n3000), .B(n3001), .CI(n3002), .CO(n1206), .S(n1205) );
ADDFHX4TS U2629 ( .A(n3018), .B(n3017), .CI(n3016), .CO(n1211), .S(n1207) );
OR2X8TS U2630 ( .A(n1219), .B(n1619), .Y(n1917) );
NAND2X4TS U2631 ( .A(n570), .B(n584), .Y(n2247) );
NOR2X2TS U2632 ( .A(n2247), .B(n3025), .Y(n1365) );
AOI21X4TS U2633 ( .A0(n2642), .A1(n1201), .B0(n1200), .Y(n1620) );
AOI21X4TS U2634 ( .A0(n2252), .A1(n1365), .B0(n1367), .Y(n1220) );
MXI2X4TS U2635 ( .A(n2638), .B(Add_result[23]), .S0(n793), .Y(n1222) );
INVX2TS U2636 ( .A(n1268), .Y(n1246) );
NAND2X2TS U2637 ( .A(n1448), .B(n1251), .Y(n1253) );
MXI2X4TS U2638 ( .A(n997), .B(n3114), .S0(FSM_selector_A), .Y(n1255) );
OAI21X2TS U2639 ( .A0(Op_MY[23]), .A1(FSM_selector_B_1_), .B0(n1228), .Y(
n1229) );
NAND2X2TS U2640 ( .A(n1230), .B(n1255), .Y(n1231) );
OAI21X4TS U2641 ( .A0(n1232), .A1(n1414), .B0(n1231), .Y(n1420) );
NAND2X8TS U2642 ( .A(n1235), .B(n1233), .Y(n1258) );
AOI21X4TS U2643 ( .A0(n1420), .A1(n1241), .B0(n1240), .Y(n1375) );
AOI21X4TS U2644 ( .A0(n1251), .A1(n1450), .B0(n1250), .Y(n1252) );
OAI21X4TS U2645 ( .A0(n1253), .A1(n1375), .B0(n1252), .Y(n1474) );
NOR2X8TS U2646 ( .A(n1380), .B(n1387), .Y(n1461) );
NOR2X2TS U2647 ( .A(n1465), .B(n1456), .Y(n1271) );
NAND2X2TS U2648 ( .A(n1461), .B(n1271), .Y(n1273) );
OAI21X4TS U2649 ( .A0(n1411), .A1(n1416), .B0(n1412), .Y(n1428) );
OAI21X4TS U2650 ( .A0(n1423), .A1(n1434), .B0(n1424), .Y(n1261) );
AOI21X4TS U2651 ( .A0(n1262), .A1(n1428), .B0(n1261), .Y(n1386) );
OAI21X4TS U2652 ( .A0(n1380), .A1(n1403), .B0(n1381), .Y(n1463) );
OAI21X1TS U2653 ( .A0(n1456), .A1(n1464), .B0(n1457), .Y(n1270) );
AOI21X2TS U2654 ( .A0(n1271), .A1(n1463), .B0(n1270), .Y(n1272) );
OAI21X4TS U2655 ( .A0(n1273), .A1(n1386), .B0(n1272), .Y(n1477) );
OAI21X4TS U2656 ( .A0(n1278), .A1(n2873), .B0(n1277), .Y(n225) );
ADDFHX4TS U2657 ( .A(n1312), .B(n1311), .CI(n1310), .CO(n1329), .S(n2290) );
ADDFHX2TS U2658 ( .A(n1340), .B(n1339), .CI(n1338), .CO(n1347), .S(n1350) );
NOR2X2TS U2659 ( .A(n2584), .B(n3139), .Y(n1363) );
NAND2X4TS U2660 ( .A(n1365), .B(n581), .Y(n1366) );
OAI21X4TS U2661 ( .A0(n766), .A1(n1371), .B0(n1370), .Y(n1372) );
XOR2X4TS U2662 ( .A(n1384), .B(n1383), .Y(n1385) );
NAND2X6TS U2663 ( .A(n1385), .B(n2788), .Y(n1393) );
AOI21X4TS U2664 ( .A0(n1469), .A1(n1404), .B0(n1388), .Y(n1390) );
XOR2X4TS U2665 ( .A(n1390), .B(n1389), .Y(n1391) );
AOI21X4TS U2666 ( .A0(n1455), .A1(n1448), .B0(n1450), .Y(n1396) );
XOR2X4TS U2667 ( .A(n1396), .B(n1395), .Y(n1397) );
XOR2X4TS U2668 ( .A(n1399), .B(n1398), .Y(n1400) );
INVX2TS U2669 ( .A(n1407), .Y(n1405) );
XNOR2X4TS U2670 ( .A(n1455), .B(n1405), .Y(n1406) );
NAND2X4TS U2671 ( .A(n1413), .B(n1412), .Y(n1417) );
XOR2X1TS U2672 ( .A(n1417), .B(n1416), .Y(n1418) );
NAND2X4TS U2673 ( .A(n1425), .B(n1424), .Y(n1429) );
OR2X4TS U2674 ( .A(n2786), .B(n2602), .Y(n1446) );
XOR2X1TS U2675 ( .A(n1443), .B(n1442), .Y(n2868) );
NOR2X4TS U2676 ( .A(n1446), .B(n1445), .Y(n1447) );
XOR2X4TS U2677 ( .A(n1460), .B(n1459), .Y(n1473) );
XOR2X4TS U2678 ( .A(n1471), .B(n1470), .Y(n1472) );
MXI2X4TS U2679 ( .A(n1473), .B(n1472), .S0(n427), .Y(n1986) );
XNOR2X4TS U2680 ( .A(n1477), .B(n1476), .Y(n1478) );
AOI22X1TS U2681 ( .A0(n2792), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n3273), .Y(n1493) );
XNOR2X4TS U2682 ( .A(n1489), .B(n2916), .Y(n1490) );
OAI2BB1X4TS U2683 ( .A0N(n587), .A1N(n1490), .B0(n3269), .Y(n2639) );
INVX4TS U2684 ( .A(n2651), .Y(n1940) );
OAI22X1TS U2685 ( .A0(n677), .A1(n2472), .B0(n1506), .B1(n799), .Y(n2465) );
OAI22X1TS U2686 ( .A0(n715), .A1(n879), .B0(n695), .B1(n868), .Y(n1598) );
AOI21X4TS U2687 ( .A0(n615), .A1(n2284), .B0(n1523), .Y(n1527) );
INVX2TS U2688 ( .A(n1941), .Y(n1534) );
OAI2BB1X4TS U2689 ( .A0N(n587), .A1N(n1537), .B0(n3262), .Y(n2675) );
CLKINVX1TS U2690 ( .A(n769), .Y(n1539) );
OAI2BB2X2TS U2691 ( .B0(n842), .B1(n780), .A0N(n1539), .A1N(n1538), .Y(n1567) );
OAI22X1TS U2692 ( .A0(n677), .A1(n1541), .B0(n2473), .B1(n799), .Y(n2542) );
ADDFHX4TS U2693 ( .A(n1578), .B(n1577), .CI(n1576), .CO(n1571), .S(n2398) );
CMPR32X2TS U2694 ( .A(n1595), .B(n1596), .C(n1594), .CO(n2531), .S(n2528) );
CMPR32X2TS U2695 ( .A(n650), .B(n881), .C(n1598), .CO(n1604), .S(n1601) );
AO21X4TS U2696 ( .A0(n1618), .A1(n2287), .B0(n1617), .Y(n3094) );
OAI2BB1X4TS U2697 ( .A0N(n1621), .A1N(n2661), .B0(n1620), .Y(n1623) );
NAND2X2TS U2698 ( .A(n1627), .B(n2664), .Y(n1622) );
OAI2BB1X4TS U2699 ( .A0N(n3256), .A1N(n1624), .B0(n3255), .Y(n2677) );
INVX2TS U2700 ( .A(Add_result[10]), .Y(n1625) );
INVX2TS U2701 ( .A(n2664), .Y(n1626) );
OAI2BB1X4TS U2702 ( .A0N(n585), .A1N(n1631), .B0(n3272), .Y(n2683) );
OAI21X4TS U2703 ( .A0(n2112), .A1(n1651), .B0(n1633), .Y(n1636) );
NAND2X1TS U2704 ( .A(n1660), .B(n1658), .Y(n1635) );
XNOR2X4TS U2705 ( .A(n1636), .B(n1635), .Y(n1637) );
NAND2X1TS U2706 ( .A(n1987), .B(n1992), .Y(n1641) );
INVX2TS U2707 ( .A(n1991), .Y(n1639) );
NAND2X1TS U2708 ( .A(n521), .B(n1643), .Y(n1644) );
XNOR2X4TS U2709 ( .A(n1645), .B(n1644), .Y(n1646) );
AOI22X1TS U2710 ( .A0(n2792), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n777), .Y(n1650) );
AOI2BB2X2TS U2711 ( .B0(n2700), .B1(n264), .A0N(n805), .A1N(n3147), .Y(n1649) );
NAND2X2TS U2712 ( .A(n2681), .B(n263), .Y(n1648) );
NAND3X2TS U2713 ( .A(n1650), .B(n1649), .C(n1648), .Y(n204) );
NAND2X1TS U2714 ( .A(n426), .B(n1921), .Y(n1653) );
XNOR2X4TS U2715 ( .A(n1656), .B(n1655), .Y(n1657) );
NAND2X1TS U2716 ( .A(n426), .B(n1660), .Y(n1662) );
NAND2X1TS U2717 ( .A(n1665), .B(n1664), .Y(n1666) );
AOI22X1TS U2718 ( .A0(n2828), .A1(Add_result[5]), .B0(n640), .B1(n777), .Y(
n1673) );
INVX2TS U2719 ( .A(Add_result[4]), .Y(n1670) );
AOI2BB2X4TS U2720 ( .B0(n2784), .B1(n266), .A0N(n807), .A1N(n1670), .Y(n1672) );
NAND2BX1TS U2721 ( .AN(n612), .B(n604), .Y(n1683) );
ADDFHX4TS U2722 ( .A(n1699), .B(n1698), .CI(n1697), .CO(n1749), .S(n1730) );
INVX2TS U2723 ( .A(n430), .Y(n1735) );
NAND2X1TS U2724 ( .A(n1735), .B(n1734), .Y(n1736) );
XNOR2X4TS U2725 ( .A(n1737), .B(n1736), .Y(n1738) );
OAI2BB1X4TS U2726 ( .A0N(n3260), .A1N(n1738), .B0(n3259), .Y(n2673) );
XNOR2X1TS U2727 ( .A(n753), .B(n626), .Y(n1745) );
NAND2BX1TS U2728 ( .AN(n612), .B(n1884), .Y(n1746) );
ADDFHX4TS U2729 ( .A(n1749), .B(n1748), .CI(n1747), .CO(n1984), .S(n1766) );
ADDFHX4TS U2730 ( .A(n1768), .B(n1767), .CI(n1766), .CO(n1769), .S(n1957) );
AOI21X4TS U2731 ( .A0(n632), .A1(n634), .B0(n660), .Y(mult_x_19_n424) );
ADDFHX4TS U2732 ( .A(n1843), .B(n1842), .CI(n1841), .CO(mult_x_19_n725), .S(
mult_x_19_n726) );
NAND2X1TS U2733 ( .A(n2661), .B(n1845), .Y(n1847) );
NAND2BX2TS U2734 ( .AN(n1939), .B(n1942), .Y(n1850) );
XNOR2X4TS U2735 ( .A(n1851), .B(n1850), .Y(n1852) );
OAI2BB1X4TS U2736 ( .A0N(n587), .A1N(n1852), .B0(n3263), .Y(n2682) );
NAND2X1TS U2737 ( .A(n1857), .B(n1856), .Y(n1858) );
ADDFHX4TS U2738 ( .A(n1912), .B(n1911), .CI(n1910), .CO(n1959), .S(n1961) );
OAI21X4TS U2739 ( .A0(n765), .A1(n1917), .B0(n1916), .Y(n1919) );
XNOR2X4TS U2740 ( .A(n1919), .B(n1918), .Y(n1920) );
OAI2BB1X4TS U2741 ( .A0N(n587), .A1N(n1920), .B0(n3270), .Y(n2630) );
AOI2BB2X2TS U2742 ( .B0(n2784), .B1(n2630), .A0N(n806), .A1N(n3125), .Y(
n3303) );
MXI2X4TS U2743 ( .A(n423), .B(n2588), .S0(n2785), .Y(n230) );
OAI21X2TS U2744 ( .A0(n1926), .A1(n1925), .B0(n1924), .Y(n1927) );
INVX2TS U2745 ( .A(n1932), .Y(n1934) );
NAND2X1TS U2746 ( .A(n1934), .B(n1933), .Y(n1935) );
XNOR2X4TS U2747 ( .A(n1936), .B(n1935), .Y(n1937) );
MX2X6TS U2748 ( .A(n1937), .B(n3244), .S0(n589), .Y(n267) );
NAND2X1TS U2749 ( .A(n2661), .B(n1950), .Y(n1952) );
NAND2X1TS U2750 ( .A(n3043), .B(n3044), .Y(n1953) );
XNOR2X4TS U2751 ( .A(n1954), .B(n1953), .Y(n1955) );
OAI2BB1X4TS U2752 ( .A0N(n587), .A1N(n1955), .B0(n3261), .Y(n2674) );
XOR2X4TS U2753 ( .A(n603), .B(n1967), .Y(Sgf_operation_Result[9]) );
MXI2X4TS U2754 ( .A(n1969), .B(n3107), .S0(n2785), .Y(n228) );
ADDFHX4TS U2755 ( .A(n1985), .B(n1984), .CI(n1983), .CO(mult_x_19_n1010),
.S(n1770) );
MXI2X4TS U2756 ( .A(n1986), .B(n3108), .S0(n2785), .Y(n227) );
OAI21X4TS U2757 ( .A0(n2112), .A1(n1990), .B0(n1989), .Y(n1994) );
NAND2X1TS U2758 ( .A(n1992), .B(n1991), .Y(n1993) );
AOI22X1TS U2759 ( .A0(n2828), .A1(Add_result[2]), .B0(n664), .B1(n777), .Y(
n1998) );
NAND2X1TS U2760 ( .A(n2701), .B(n262), .Y(n1996) );
XOR2X1TS U2761 ( .A(n2001), .B(n2000), .Y(n2002) );
NAND2X1TS U2762 ( .A(n2003), .B(n3039), .Y(n2004) );
XNOR2X1TS U2763 ( .A(n2121), .B(n2004), .Y(n2005) );
AOI21X1TS U2764 ( .A0(n3093), .A1(n2980), .B0(n2981), .Y(n2007) );
XNOR2X1TS U2765 ( .A(n2008), .B(n2956), .Y(n2009) );
AOI2BB2X2TS U2766 ( .B0(n2700), .B1(n2678), .A0N(n807), .A1N(n3129), .Y(
n3319) );
ADDFHX4TS U2767 ( .A(n2033), .B(n2032), .CI(n2031), .CO(mult_x_19_n743), .S(
mult_x_19_n744) );
OAI22X1TS U2768 ( .A0(n2041), .A1(n2040), .B0(n2039), .B1(n2479), .Y(n2096)
);
XOR2X4TS U2769 ( .A(n2112), .B(n2111), .Y(n2113) );
NOR2X1TS U2770 ( .A(n428), .B(n2117), .Y(n2120) );
NAND2X1TS U2771 ( .A(n2124), .B(n2123), .Y(n2125) );
XOR2X4TS U2772 ( .A(n2126), .B(n2125), .Y(n2127) );
NOR2X1TS U2773 ( .A(n551), .B(n787), .Y(n2562) );
CMPR32X2TS U2774 ( .A(n3095), .B(n2132), .C(n2131), .CO(n2559), .S(n2129) );
MXI2X4TS U2775 ( .A(n2193), .B(n3105), .S0(n2785), .Y(n229) );
XOR2X1TS U2776 ( .A(n2198), .B(n2954), .Y(n2194) );
XNOR2X2TS U2777 ( .A(n2199), .B(n2930), .Y(n2200) );
AOI21X1TS U2778 ( .A0(n582), .A1(n3014), .B0(n3015), .Y(n2201) );
XOR2X1TS U2779 ( .A(n2201), .B(n2959), .Y(n2202) );
CLKMX2X2TS U2780 ( .A(n2204), .B(n3231), .S0(n588), .Y(n250) );
CLKMX2X2TS U2781 ( .A(n2205), .B(n3229), .S0(n588), .Y(n249) );
CLKMX2X2TS U2782 ( .A(n3225), .B(n3224), .S0(n588), .Y(n247) );
XNOR2X1TS U2783 ( .A(n3072), .B(n3073), .Y(n2206) );
CLKMX2X2TS U2784 ( .A(n2206), .B(n3226), .S0(n588), .Y(n248) );
NOR4X4TS U2785 ( .A(n257), .B(n258), .C(n256), .D(n255), .Y(n2208) );
NOR4X1TS U2786 ( .A(n250), .B(n249), .C(n247), .D(n248), .Y(n2207) );
NAND2X1TS U2787 ( .A(n2210), .B(n2209), .Y(n2211) );
XNOR2X1TS U2788 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n2830) );
NOR2X4TS U2789 ( .A(n3139), .B(FS_Module_state_reg[2]), .Y(n2586) );
AOI22X1TS U2790 ( .A0(n2213), .A1(n2578), .B0(n2586), .B1(n2584), .Y(n2214)
);
ADDFHX4TS U2791 ( .A(n2231), .B(n2229), .CI(n2230), .CO(n2361), .S(n1983) );
INVX2TS U2792 ( .A(n2247), .Y(n2251) );
INVX2TS U2793 ( .A(n2249), .Y(n2250) );
OAI2BB1X4TS U2794 ( .A0N(n585), .A1N(n2256), .B0(n3251), .Y(n2629) );
AOI2BB2X2TS U2795 ( .B0(n2784), .B1(n2629), .A0N(n806), .A1N(n3134), .Y(
n3294) );
MX2X4TS U2796 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n2263), .Y(n354) );
XNOR2X1TS U2797 ( .A(n353), .B(n354), .Y(n2927) );
XNOR2X1TS U2798 ( .A(n355), .B(n356), .Y(n2934) );
MX2X6TS U2799 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n2791), .Y(n345) );
XNOR2X1TS U2800 ( .A(n345), .B(n346), .Y(n2935) );
XNOR2X1TS U2801 ( .A(n349), .B(n350), .Y(n2933) );
INVX2TS U2802 ( .A(n357), .Y(n2939) );
XNOR2X1TS U2803 ( .A(n357), .B(mult_x_19_n689), .Y(n3067) );
XOR2X1TS U2804 ( .A(n2931), .B(mult_x_19_n579), .Y(n2945) );
XNOR2X1TS U2805 ( .A(n357), .B(n358), .Y(n2938) );
MX2X4TS U2806 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n2791), .Y(
mult_x_19_n1775) );
XNOR2X1TS U2807 ( .A(n345), .B(mult_x_19_n1775), .Y(n3049) );
XNOR2X1TS U2808 ( .A(n345), .B(mult_x_19_n1773), .Y(n2957) );
XNOR2X1TS U2809 ( .A(n345), .B(mult_x_19_n1777), .Y(n3012) );
MX2X4TS U2810 ( .A(Data_MX[20]), .B(n410), .S0(n2568), .Y(n364) );
XNOR2X1TS U2811 ( .A(n363), .B(n364), .Y(n2953) );
MX2X6TS U2812 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n2263), .Y(mult_x_19_n19)
);
XOR2X1TS U2813 ( .A(n363), .B(n362), .Y(n2960) );
XNOR2X1TS U2814 ( .A(mult_x_19_n19), .B(mult_x_19_n723), .Y(n3053) );
XNOR2X1TS U2815 ( .A(mult_x_19_n19), .B(mult_x_19_n1777), .Y(n3052) );
MX2X6TS U2816 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n2568), .Y(mult_x_19_n43) );
XNOR2X1TS U2817 ( .A(mult_x_19_n43), .B(mult_x_19_n723), .Y(n3054) );
BUFX3TS U2818 ( .A(n3158), .Y(n2576) );
CLKBUFX3TS U2819 ( .A(n3080), .Y(n3159) );
OAI22X1TS U2820 ( .A0(n760), .A1(n2469), .B0(n2468), .B1(n604), .Y(n2550) );
CMPR32X2TS U2821 ( .A(n2558), .B(n2557), .C(n2556), .CO(mult_x_19_n637), .S(
mult_x_19_n638) );
CMPR32X2TS U2822 ( .A(n2561), .B(n2560), .C(n2559), .CO(n2564), .S(n2539) );
XNOR2X1TS U2823 ( .A(n357), .B(n2565), .Y(n3069) );
XNOR2X1TS U2824 ( .A(n355), .B(mult_x_19_n689), .Y(n3045) );
XNOR2X1TS U2825 ( .A(n363), .B(mult_x_19_n1791), .Y(n3070) );
INVX2TS U2826 ( .A(mult_x_19_n1777), .Y(n2567) );
XNOR2X1TS U2827 ( .A(n353), .B(mult_x_19_n633), .Y(n3063) );
XNOR2X1TS U2828 ( .A(mult_x_19_n19), .B(mult_x_19_n1775), .Y(n2942) );
XNOR2X1TS U2829 ( .A(mult_x_19_n19), .B(mult_x_19_n593), .Y(n3047) );
XNOR2X1TS U2830 ( .A(mult_x_19_n19), .B(mult_x_19_n1773), .Y(n3064) );
MX2X6TS U2831 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n2568), .Y(mult_x_19_n49) );
XNOR2X1TS U2832 ( .A(mult_x_19_n49), .B(n362), .Y(n2961) );
MX2X4TS U2833 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n2568), .Y(n360) );
XNOR2X1TS U2834 ( .A(mult_x_19_n43), .B(n360), .Y(n2966) );
XNOR2X1TS U2835 ( .A(mult_x_19_n43), .B(mult_x_19_n689), .Y(n2944) );
XNOR2X1TS U2836 ( .A(mult_x_19_n49), .B(mult_x_19_n633), .Y(n3071) );
XNOR2X1TS U2837 ( .A(mult_x_19_n49), .B(mult_x_19_n593), .Y(n2928) );
CMPR32X2TS U2838 ( .A(n669), .B(n435), .C(n2569), .CO(n2572), .S(n2563) );
AND2X2TS U2839 ( .A(n551), .B(n3098), .Y(n2570) );
XNOR2X2TS U2840 ( .A(n2570), .B(n787), .Y(n2571) );
NAND2X1TS U2841 ( .A(n2572), .B(n2571), .Y(n2573) );
INVX2TS U2842 ( .A(n366), .Y(n3062) );
AOI22X1TS U2843 ( .A0(n1364), .A1(n3139), .B0(n2586), .B1(n1938), .Y(n2580)
);
NAND2X1TS U2844 ( .A(n2582), .B(n2580), .Y(n377) );
XNOR2X1TS U2845 ( .A(n664), .B(Sgf_normalized_result[0]), .Y(n2583) );
MXI2X4TS U2846 ( .A(n3177), .B(n3176), .S0(n564), .Y(underflow_flag) );
INVX12TS U2847 ( .A(n2835), .Y(n2855) );
BUFX8TS U2848 ( .A(n2839), .Y(n2857) );
AOI2BB2X1TS U2849 ( .B0(n2857), .B1(n2588), .A0N(n2834), .A1N(
final_result_ieee[27]), .Y(n173) );
XNOR2X1TS U2850 ( .A(n2593), .B(Sgf_normalized_result[2]), .Y(n2589) );
CLKMX2X2TS U2851 ( .A(n2589), .B(n813), .S0(n2723), .Y(n307) );
XOR2X1TS U2852 ( .A(n2858), .B(n640), .Y(n2592) );
CLKMX2X2TS U2853 ( .A(n2592), .B(Add_result[4]), .S0(n2723), .Y(n305) );
XOR2X1TS U2854 ( .A(n2594), .B(n3138), .Y(n2595) );
CLKMX2X2TS U2855 ( .A(n2595), .B(Add_result[3]), .S0(n2771), .Y(n306) );
INVX2TS U2856 ( .A(n2851), .Y(n2859) );
XNOR2X1TS U2857 ( .A(n2596), .B(n3148), .Y(n2597) );
XOR2X4TS U2858 ( .A(n2606), .B(n2600), .Y(n2601) );
MXI2X1TS U2859 ( .A(n2602), .B(n3113), .S0(n2785), .Y(n231) );
MXI2X1TS U2860 ( .A(n2603), .B(n3104), .S0(n2785), .Y(n232) );
AOI22X1TS U2861 ( .A0(n2827), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n777), .Y(n2614) );
INVX2TS U2862 ( .A(Add_result[0]), .Y(n2787) );
NAND2X4TS U2863 ( .A(n2679), .B(n261), .Y(n2612) );
NAND2X1TS U2864 ( .A(n2851), .B(Sgf_normalized_result[6]), .Y(n2617) );
NAND2X1TS U2865 ( .A(n2615), .B(Sgf_normalized_result[6]), .Y(n2616) );
INVX2TS U2866 ( .A(n2837), .Y(n2618) );
XNOR2X1TS U2867 ( .A(n2619), .B(n2618), .Y(n2620) );
OAI2BB1X4TS U2868 ( .A0N(n3248), .A1N(n2624), .B0(n3247), .Y(n2699) );
AOI22X1TS U2869 ( .A0(n2827), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n777), .Y(n2627) );
NAND2X1TS U2870 ( .A(n2681), .B(n264), .Y(n2625) );
INVX2TS U2871 ( .A(n2838), .Y(n2636) );
XNOR2X1TS U2872 ( .A(n2735), .B(n2636), .Y(n2637) );
CLKMX2X2TS U2873 ( .A(n2637), .B(Add_result[8]), .S0(n2757), .Y(n301) );
OAI21X4TS U2874 ( .A0(n765), .A1(n2644), .B0(n2643), .Y(n2648) );
XNOR2X4TS U2875 ( .A(n2648), .B(n2647), .Y(n2649) );
OAI2BB1X4TS U2876 ( .A0N(n3266), .A1N(n2649), .B0(n3265), .Y(n2676) );
NAND2X1TS U2877 ( .A(n2651), .B(n2661), .Y(n2653) );
AOI21X1TS U2878 ( .A0(n2667), .A1(n2651), .B0(n2650), .Y(n2652) );
NAND2X2TS U2879 ( .A(n2655), .B(n2654), .Y(n2656) );
XNOR2X4TS U2880 ( .A(n2657), .B(n2656), .Y(n2658) );
NOR2X1TS U2881 ( .A(n2660), .B(n2663), .Y(n2666) );
NAND2X1TS U2882 ( .A(n2661), .B(n2666), .Y(n2669) );
NAND2X2TS U2883 ( .A(n2671), .B(n2940), .Y(n2672) );
NAND2X1TS U2884 ( .A(n796), .B(n2682), .Y(n3309) );
NAND2X1TS U2885 ( .A(n2701), .B(n2682), .Y(n3310) );
NOR2X8TS U2886 ( .A(n2692), .B(n2691), .Y(n2768) );
NAND2X4TS U2887 ( .A(n2847), .B(n2846), .Y(n2763) );
NAND2X1TS U2888 ( .A(n2841), .B(n2844), .Y(n2693) );
NAND2X1TS U2889 ( .A(n2768), .B(n2696), .Y(n2698) );
MXI2X1TS U2890 ( .A(n2698), .B(n2697), .S0(n2723), .Y(n285) );
AOI22X1TS U2891 ( .A0(n2827), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n777), .Y(n2704) );
NAND2X1TS U2892 ( .A(n2735), .B(n2705), .Y(n2707) );
INVX2TS U2893 ( .A(n2842), .Y(n2706) );
NAND2X1TS U2894 ( .A(n2735), .B(n2838), .Y(n2710) );
INVX2TS U2895 ( .A(n2848), .Y(n2709) );
CLKMX2X2TS U2896 ( .A(n2711), .B(n809), .S0(n2757), .Y(n300) );
NAND2X1TS U2897 ( .A(n2735), .B(n2712), .Y(n2714) );
INVX2TS U2898 ( .A(n2850), .Y(n2713) );
NAND2X1TS U2899 ( .A(n2717), .B(n2842), .Y(n2718) );
NAND2X1TS U2900 ( .A(n2735), .B(n2720), .Y(n2722) );
INVX2TS U2901 ( .A(n2840), .Y(n2721) );
BUFX8TS U2902 ( .A(n2723), .Y(n2771) );
INVX2TS U2903 ( .A(n2728), .Y(n2725) );
XOR2X1TS U2904 ( .A(n2726), .B(n2729), .Y(n2727) );
CLKMX2X2TS U2905 ( .A(n2727), .B(Add_result[10]), .S0(n2757), .Y(n299) );
NAND2X1TS U2906 ( .A(n2735), .B(n2730), .Y(n2732) );
INVX2TS U2907 ( .A(n2845), .Y(n2731) );
NAND2X1TS U2908 ( .A(n2735), .B(n2734), .Y(n2737) );
INVX2TS U2909 ( .A(n2847), .Y(n2739) );
XNOR2X1TS U2910 ( .A(n2768), .B(n2739), .Y(n2740) );
NAND2X1TS U2911 ( .A(n2768), .B(n2742), .Y(n2744) );
INVX2TS U2912 ( .A(n2856), .Y(n2743) );
NAND2X1TS U2913 ( .A(n2847), .B(n2768), .Y(n2747) );
INVX2TS U2914 ( .A(n2846), .Y(n2746) );
NAND2X1TS U2915 ( .A(n2768), .B(n2749), .Y(n2751) );
INVX2TS U2916 ( .A(n2844), .Y(n2750) );
XOR2X1TS U2917 ( .A(n2751), .B(n2750), .Y(n2752) );
NOR2X4TS U2918 ( .A(n2759), .B(n2760), .Y(n2754) );
INVX2TS U2919 ( .A(n310), .Y(n2755) );
NAND2X1TS U2920 ( .A(n2768), .B(n748), .Y(n2761) );
INVX2TS U2921 ( .A(n2763), .Y(n2764) );
NAND2X1TS U2922 ( .A(n2768), .B(n2764), .Y(n2766) );
XOR2X1TS U2923 ( .A(n2766), .B(n2765), .Y(n2767) );
NAND2X1TS U2924 ( .A(n2769), .B(n2768), .Y(n2770) );
NAND2X1TS U2925 ( .A(n2775), .B(n2774), .Y(n2776) );
XOR2X1TS U2926 ( .A(n2776), .B(n2871), .Y(n2777) );
CLKMX2X2TS U2927 ( .A(n2777), .B(P_Sgf[2]), .S0(n424), .Y(n240) );
NAND2X1TS U2928 ( .A(n2778), .B(n2779), .Y(n2781) );
XNOR2X1TS U2929 ( .A(n2781), .B(n2780), .Y(n2782) );
MXI2X1TS U2930 ( .A(n2786), .B(n3114), .S0(n2785), .Y(n233) );
NAND2X1TS U2931 ( .A(n3356), .B(n3121), .Y(n376) );
MXI2X1TS U2932 ( .A(Sgf_normalized_result[0]), .B(n2787), .S0(n2723), .Y(
n309) );
NAND2X1TS U2933 ( .A(n2788), .B(zero_flag), .Y(n2789) );
NAND3X1TS U2934 ( .A(n2790), .B(n777), .C(n2789), .Y(n380) );
BUFX8TS U2935 ( .A(n2797), .Y(n2800) );
CLKMX2X3TS U2936 ( .A(Data_MY[22]), .B(n787), .S0(n2791), .Y(n334) );
AOI22X1TS U2937 ( .A0(n2792), .A1(Add_result[6]), .B0(n2851), .B1(n777), .Y(
n3351) );
AOI22X1TS U2938 ( .A0(n2792), .A1(n809), .B0(n2838), .B1(n2799), .Y(n3344)
);
AOI22X1TS U2939 ( .A0(n2792), .A1(n808), .B0(n2846), .B1(n3273), .Y(n3308)
);
AOI22X1TS U2940 ( .A0(n2828), .A1(Add_result[8]), .B0(n2837), .B1(n777), .Y(
n3348) );
NOR2BX1TS U2941 ( .AN(n789), .B(n556), .Y(n2803) );
NOR4X1TS U2942 ( .A(Op_MY[26]), .B(Op_MY[25]), .C(Op_MY[28]), .D(Op_MY[27]),
.Y(n2808) );
NAND4BBX1TS U2943 ( .AN(Op_MY[10]), .BN(Op_MY[8]), .C(n624), .D(n647), .Y(
n2804) );
NOR4X1TS U2944 ( .A(Op_MY[29]), .B(n668), .C(Op_MY[0]), .D(Op_MY[30]), .Y(
n2806) );
NAND4X1TS U2945 ( .A(n2808), .B(n2807), .C(n2806), .D(n2805), .Y(n2825) );
AND4X2TS U2946 ( .A(n649), .B(n737), .C(n3109), .D(n2809), .Y(n2813) );
AND4X2TS U2947 ( .A(n3110), .B(n687), .C(n3149), .D(n622), .Y(n2812) );
NOR4X1TS U2948 ( .A(n600), .B(Op_MY[19]), .C(n673), .D(Op_MY[5]), .Y(n2811)
);
AND4X2TS U2949 ( .A(n3111), .B(n692), .C(n2801), .D(n3150), .Y(n2810) );
NAND4X1TS U2950 ( .A(n2813), .B(n2812), .C(n2811), .D(n2810), .Y(n2824) );
NOR4X1TS U2951 ( .A(Op_MX[20]), .B(Op_MX[8]), .C(Op_MX[10]), .D(Op_MX[16]),
.Y(n2817) );
NOR4X1TS U2952 ( .A(Op_MX[18]), .B(Op_MX[14]), .C(Op_MX[2]), .D(Op_MX[6]),
.Y(n2816) );
NOR4X1TS U2953 ( .A(Op_MX[11]), .B(Op_MX[19]), .C(Op_MX[7]), .D(Op_MX[17]),
.Y(n2815) );
NOR4X1TS U2954 ( .A(Op_MX[22]), .B(Op_MX[12]), .C(Op_MX[0]), .D(Op_MX[5]),
.Y(n2814) );
NAND4X1TS U2955 ( .A(n2817), .B(n2816), .C(n2815), .D(n2814), .Y(n2823) );
NOR4X1TS U2956 ( .A(Op_MX[26]), .B(Op_MX[25]), .C(Op_MX[28]), .D(Op_MX[27]),
.Y(n2821) );
NOR4X1TS U2957 ( .A(Op_MX[29]), .B(Op_MX[9]), .C(Op_MX[21]), .D(Op_MX[30]),
.Y(n2819) );
NAND4X1TS U2958 ( .A(n2821), .B(n2820), .C(n2819), .D(n2818), .Y(n2822) );
OAI22X1TS U2959 ( .A0(n2825), .A1(n2824), .B0(n2823), .B1(n2822), .Y(n2826)
);
AOI22X1TS U2960 ( .A0(n2827), .A1(n812), .B0(n2841), .B1(n3273), .Y(n3304)
);
AOI22X1TS U2961 ( .A0(n2827), .A1(Add_result[10]), .B0(n2848), .B1(n3273),
.Y(n3340) );
AOI22X1TS U2962 ( .A0(n2827), .A1(Add_result[22]), .B0(n2856), .B1(n3273),
.Y(n3295) );
AOI22X1TS U2963 ( .A0(n2827), .A1(Add_result[16]), .B0(n2840), .B1(n3273),
.Y(n3316) );
AOI22X1TS U2964 ( .A0(n2828), .A1(Add_result[14]), .B0(n2850), .B1(n3273),
.Y(n3324) );
AOI22X1TS U2965 ( .A0(n2828), .A1(n810), .B0(n2844), .B1(n3273), .Y(n3300)
);
AOI22X1TS U2966 ( .A0(n2828), .A1(Add_result[17]), .B0(n2847), .B1(n2799),
.Y(n3312) );
AOI22X1TS U2967 ( .A0(n2828), .A1(Add_result[11]), .B0(n2836), .B1(n777),
.Y(n3336) );
AOI22X1TS U2968 ( .A0(n2828), .A1(Add_result[23]), .B0(n2854), .B1(n3273),
.Y(n3291) );
NAND2X1TS U2969 ( .A(n2830), .B(n3358), .Y(n2832) );
NAND2X1TS U2970 ( .A(n2832), .B(n2831), .Y(n2833) );
MXI2X1TS U2971 ( .A(n2833), .B(n3152), .S0(n2855), .Y(n168) );
AOI2BB2X1TS U2972 ( .B0(n2857), .B1(n3105), .A0N(n2834), .A1N(
final_result_ieee[28]), .Y(n172) );
AOI2BB2X1TS U2973 ( .B0(n2857), .B1(n3114), .A0N(n2834), .A1N(
final_result_ieee[24]), .Y(n176) );
AOI2BB2X1TS U2974 ( .B0(n2857), .B1(n3108), .A0N(n2834), .A1N(
final_result_ieee[30]), .Y(n170) );
AOI2BB2X1TS U2975 ( .B0(n2857), .B1(n3113), .A0N(n2834), .A1N(
final_result_ieee[26]), .Y(n174) );
AOI2BB2X1TS U2976 ( .B0(n2857), .B1(n3107), .A0N(n2834), .A1N(
final_result_ieee[29]), .Y(n171) );
AOI2BB2X1TS U2977 ( .B0(n2857), .B1(n3104), .A0N(n2834), .A1N(
final_result_ieee[25]), .Y(n175) );
AOI2BB2X1TS U2978 ( .B0(n2857), .B1(n3103), .A0N(n2834), .A1N(
final_result_ieee[23]), .Y(n177) );
AO22X2TS U2979 ( .A0(n2857), .A1(n2856), .B0(final_result_ieee[21]), .B1(
n2855), .Y(n179) );
NAND2X1TS U2980 ( .A(n2858), .B(n641), .Y(n2860) );
XNOR2X1TS U2981 ( .A(n2860), .B(n2859), .Y(n2861) );
CLKMX2X2TS U2982 ( .A(n2861), .B(Add_result[5]), .S0(n2723), .Y(n304) );
MXI2X1TS U2983 ( .A(n2868), .B(n3103), .S0(n2785), .Y(n234) );
OR2X2TS U2984 ( .A(n2870), .B(n2869), .Y(n2872) );
AND2X2TS U2985 ( .A(n2872), .B(n2871), .Y(n2874) );
CLKMX2X2TS U2986 ( .A(n2874), .B(P_Sgf[1]), .S0(n2873), .Y(n3140) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk1.tcl_DW_1STAGE_syn.sdf");
endmodule
|
module scalable_proc #
(
parameter NUM_PROCESSING_UNITS = 2, // Number of processing units
parameter UART_PRESCALER = 868 // UART prescaler
)
(
// Closk & reset
input wire CLK,
input wire RST,
// UART
input wire UART_RX,
output wire UART_TX
);
// ============================================================================
// ROM
wire rom_i_stb;
reg [31:0] rom_i_adr; // Fixed to 32-bit. The ROM size must be a power of 2 less than 32
wire rom_o_stb;
wire [31:0] rom_o_dat;
rom rom
(
.CLK (CLK),
.RST (RST),
.I_STB (rom_i_stb),
.I_ADR (rom_i_adr),
.O_STB (rom_o_stb),
.O_DAT (rom_o_dat)
);
// UART transmitt interval
localparam UART_TX_INTERVAL = UART_PRESCALER * 11; // Wait for 10-bits + 1 extra
// ============================================================================
// Input shift register
localparam SREG_BITS = 32 * NUM_PROCESSING_UNITS;
reg [SREG_BITS-1:0] inp_sreg;
wire inp_sreg_i_stb = rom_o_stb;
wire [31:0] inp_sreg_i_dat = rom_o_dat;
reg inp_sreg_o_stb;
always @(posedge CLK)
if (inp_sreg_i_stb) inp_sreg <= {inp_sreg[SREG_BITS-32-1:0], inp_sreg_i_dat};
else inp_sreg <= inp_sreg;
always @(posedge CLK or posedge RST)
if (RST) inp_sreg_o_stb <= 1'd0;
else inp_sreg_o_stb <= inp_sreg_i_stb;
// ============================================================================
// Processing units
reg proc_i_stb;
wire [NUM_PROCESSING_UNITS-1:0] proc_o_stb;
wire [SREG_BITS-1:0] proc_o_dat;
genvar i;
generate for(i=0; i<NUM_PROCESSING_UNITS; i=i+1) begin
processing_unit unit
(
.CLK (CLK),
.RST (RST),
.I_STB (proc_i_stb),
.I_DAT (inp_sreg[(i+1)*32-1 : i*32]),
.O_STB (proc_o_stb[i]),
.O_DAT (proc_o_dat[(i+1)*32-1 : i*32])
);
end endgenerate
// ============================================================================
// Output shift register
reg [SREG_BITS-1:0] out_sreg;
wire out_sreg_i_ld = proc_o_stb[0];
wire [SREG_BITS-1:0] out_sreg_i_dat = proc_o_dat;
wire out_sreg_i_sh;
reg out_sreg_o_stb;
wire [3:0] out_sreg_o_dat;
always @(posedge CLK)
if (out_sreg_i_ld) out_sreg <= out_sreg_i_dat;
else if (out_sreg_i_sh) out_sreg <= out_sreg << 4;
else out_sreg <= out_sreg;
assign out_sreg_o_dat = out_sreg[SREG_BITS-1:SREG_BITS-4];
// DEBUG
always @(posedge CLK)
if (proc_o_stb) $display("%X", {4'dx, proc_o_dat});
// ============================================================================
// Control FSM
localparam STATE_INIT = 0;
localparam STATE_LOAD_START = 10;
localparam STATE_LOAD_SHIFT = 11;
localparam STATE_PROC_START = 20;
localparam STATE_PROC_WAIT = 21;
localparam STATE_SEND_START = 30;
localparam STATE_SEND_WAIT = 31;
localparam STATE_SEND_DELIM = 32;
integer fsm;
reg [32:0] fsm_cnt;
wire fsm_pulse;
reg [32:0] fsm_pulse_cnt;
// fsm
always @(posedge CLK or posedge RST)
if (RST) fsm <= STATE_INIT;
else case(fsm)
STATE_INIT: fsm <= STATE_LOAD_START;
STATE_LOAD_START: fsm <= STATE_LOAD_SHIFT;
STATE_LOAD_SHIFT: fsm <= (fsm_cnt[32]) ? STATE_PROC_START : fsm;
STATE_PROC_START: fsm <= STATE_PROC_WAIT;
STATE_PROC_WAIT: fsm <= (proc_o_stb[0]) ? STATE_SEND_START : fsm;
STATE_SEND_START: fsm <= STATE_SEND_WAIT;
STATE_SEND_WAIT: if (fsm_pulse) fsm <= (fsm_cnt[32]) ? STATE_SEND_DELIM : fsm;
STATE_SEND_DELIM: if (fsm_pulse) fsm <= STATE_INIT;
endcase
// fsm_cnt
always @(posedge CLK)
case (fsm)
STATE_LOAD_START: fsm_cnt <= NUM_PROCESSING_UNITS - 2; // 32-bits per shift
STATE_SEND_START: fsm_cnt <= NUM_PROCESSING_UNITS * (32 / 4) - 2; // 4-bits per shift
STATE_SEND_WAIT: if (fsm_pulse) fsm_cnt <= (fsm_cnt[32]) ? fsm_cnt : (fsm_cnt - 1);
default: fsm_cnt <= (fsm_cnt[32]) ? fsm_cnt : (fsm_cnt - 1);
endcase
// fsm_pulse_cnt
always @(posedge CLK or posedge RST)
if (RST) fsm_pulse_cnt <= UART_TX_INTERVAL - 2;
else fsm_pulse_cnt <= (fsm_pulse_cnt[31]) ? UART_TX_INTERVAL - 2 : fsm_pulse_cnt - 1;
assign fsm_pulse = fsm_pulse_cnt[31];
// ============================================================================
// Control signals
wire uart_i_stb;
wire [4:0] uart_i_dat;
assign rom_i_stb = (fsm == STATE_LOAD_SHIFT);
always @(posedge CLK or posedge RST)
if (RST) rom_i_adr <= 0;
else case(fsm)
STATE_LOAD_SHIFT: rom_i_adr <= rom_i_adr + 1;
default: rom_i_adr <= rom_i_adr;
endcase
always @(posedge CLK or posedge RST)
if (RST) proc_i_stb <= 0;
else proc_i_stb <= (fsm == STATE_PROC_START);
assign out_sreg_i_sh = (fsm == STATE_SEND_WAIT) && fsm_pulse;
assign uart_i_stb = fsm_pulse && ((fsm == STATE_SEND_WAIT) ||
(fsm == STATE_SEND_DELIM));
assign uart_i_dat = (fsm == STATE_SEND_WAIT) ? {1'd0, out_sreg_o_dat} :
(fsm == STATE_SEND_DELIM) ? {1'd1, 4'd0} :
{1'd1, 4'd0};
// ============================================================================
// UART string generator
reg uart_x_stb;
reg [7:0] uart_x_dat;
always @(posedge CLK)
case (uart_i_dat)
5'h00: uart_x_dat <= "0";
5'h01: uart_x_dat <= "1";
5'h02: uart_x_dat <= "2";
5'h03: uart_x_dat <= "3";
5'h04: uart_x_dat <= "4";
5'h05: uart_x_dat <= "5";
5'h06: uart_x_dat <= "6";
5'h07: uart_x_dat <= "7";
5'h08: uart_x_dat <= "8";
5'h09: uart_x_dat <= "9";
5'h0A: uart_x_dat <= "A";
5'h0B: uart_x_dat <= "B";
5'h0C: uart_x_dat <= "C";
5'h0D: uart_x_dat <= "D";
5'h0E: uart_x_dat <= "E";
5'h0F: uart_x_dat <= "F";
5'h10: uart_x_dat <= "\n";
default: uart_x_dat <= " ";
endcase
always @(posedge CLK or posedge RST)
if (RST) uart_x_stb <= 1'd0;
else uart_x_stb <= uart_i_stb;
// ============================================================================
// UART
// Baudrate prescaler initializer
reg [7:0] reg_div_we_sr;
wire reg_div_we;
always @(posedge CLK or posedge RST)
if (RST) reg_div_we_sr <= 8'h01;
else reg_div_we_sr <= {reg_div_we_sr[6:0], 1'd0};
assign reg_div_we = reg_div_we_sr[7];
// The UART
simpleuart uart
(
.clk (CLK),
.resetn (!RST),
.ser_rx (UART_RX),
.ser_tx (UART_TX),
.reg_div_we ({reg_div_we, reg_div_we, reg_div_we, reg_div_we}),
.reg_div_di (UART_PRESCALER),
.reg_div_do (),
.reg_dat_we (uart_x_stb),
.reg_dat_re (1'd0),
.reg_dat_di ({24'd0, uart_x_dat}),
.reg_dat_do (),
.reg_dat_wait ()
);
// Debug
always @(posedge CLK)
if (uart_x_stb)
$display("%c", uart_x_dat);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUF_TB_V
`define SKY130_FD_SC_HDLL__BUF_TB_V
/**
* buf: Buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__buf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hdll__buf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUF_TB_V
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_bram_block_dp #(
parameter DATA = 32,
parameter ADDR = 7
) (
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
reg [DATA-1:0] mem [(2**ADDR)-1:0];
always @(posedge a_clk) begin
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end else
a_dout <= mem[a_addr];
end
always @(posedge b_clk) begin
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end else
b_dout <= mem[b_addr];
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_ln_double_s5 (
enable, resetn,
clock,
dataa,
result);
input enable, resetn;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
fp_ln_double_s5 inst ( .clk(clock),
.areset(1'b0),
.en(enable),
.a(dataa),
.q(sub_wire0));
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module wdt(clk, ena, cnt, out);
input clk, ena, cnt;
output out;
reg [6:0] timer;
wire timer_top = (timer == 7'd127);
reg internal_enable;
wire out = internal_enable && timer_top;
always @(posedge clk) begin
if(ena) begin
internal_enable <= 1;
timer <= 0;
end else if(cnt && !timer_top) timer <= timer + 7'd1;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_testbench.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - [email protected] (Tadej Markovic) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_defines.v"
`include "uart_testbench_defines.v"
`include "wb_model_defines.v"
`include "timescale.v"
module testbench;
parameter max_wait_cnt = 20000;
// INTERNAL signals
//#################
// WB slave signals
//#################
// UART Wishbone Slave signals
wire wb_int_o;
wire [`UART_ADDR_WIDTH-1:0] wbs_adr_i;
wire [`UART_DATA_WIDTH-1:0] wbs_dat_i;
wire [`UART_DATA_WIDTH-1:0] wbs_dat_o;
wire [3:0] wbs_sel_i;
wire wbs_cyc_i;
wire wbs_stb_i;
wire [2:0] wbs_cti_i;
wire [1:0] wbs_bte_i;
wire wbs_we_i;
wire wbs_ack_o;
wire wbs_rty_o = 1'b0;
wire wbs_err_o = 1'b0;
// UART signals
//#############
// UART Serial Data I/O signals
wire stx_pad_o;
wire srx_pad_i;
// UART Modem I/O signals
wire rts_pad_o;
wire cts_pad_i;
wire dtr_pad_o;
wire dsr_pad_i;
wire ri_pad_i;
wire dcd_pad_i;
`ifdef UART_HAS_BAUDRATE_OUTPUT
wire baud_o;
`endif
// System signals
//###############
// WB clock signal
reg wb_clk; // divided device clock with period T_wb_clk_period
// WB clock enable signal
reg wb_clk_en = 1'b1;
// WB clock period variable
real T_wb_clk_period = 20;
// WB reset signal
reg wb_reset;
event reset_aserted;
event reset_released;
event int_aserted;
event int_released;
// Error detection event
event error_detected;
// UART register monitor
//#########################
// Line Status Register
// Reading LSR register
reg lsr_reg_read;
// Bit 0 - Data Ready
reg lsr_reg_bit0_change_allowed;
// Bit 1 - Overrun Error
reg lsr_reg_bit1_change_allowed;
// Bit 2 - Parity Error
reg lsr_reg_bit2_change_allowed;
reg [4:0] rx_fifo_par_rd_pointer;
integer i2;
// Bit 3 - Framing Error
reg lsr_reg_bit3_change_allowed;
reg [4:0] rx_fifo_frm_rd_pointer;
integer i3;
// Bit 4 - Break Interrupt
reg lsr_reg_bit4_change_allowed;
reg [4:0] rx_fifo_brk_rd_pointer;
integer i4;
// Bit 5 - Transmitter Holding Register Empty
reg lsr_reg_bit5_change_allowed;
// Bit 6 - Transmitter Empty
reg lsr_reg_bit6_change_allowed;
// Bit 7 - Error in RX FIFO
reg lsr_reg_bit7_change_allowed;
// UART transmitter monitor
//#########################
// TX FIFO signals
reg [7:0] tx_shift_reg;
reg tx_shift_reg_empty;
reg tx_start_bit_edge;
reg [7:0] tx_fifo [0:31];
reg [4:0] tx_fifo_wr_pointer;
reg [4:0] tx_fifo_rd_pointer;
reg [4:0] tx_fifo_status;
// UART receiver monitor
//######################
// RX FIFO signals
reg [7:0] rx_shift_reg;
reg rx_shift_reg_full;
reg rx_parity_err;
reg rx_framing_err;
reg rx_framing_glitch;
reg rx_break_int;
reg rx_overrun_err_occured;
reg [7:0] rx_fifo_data [0:31];
reg [31:0] rx_fifo_par;
reg [31:0] rx_fifo_frm;
reg [31:0] rx_fifo_brk;
reg [4:0] rx_fifo_wr_pointer;
reg [4:0] rx_fifo_rd_pointer;
reg [4:0] rx_fifo_status;
reg rx_fifo_read;
// UART register tracker
//######################
// Registers
wire [7:0] ier_reg;
wire [7:0] iir_reg;
wire [7:0] fcr_reg;
wire [7:0] lcr_reg;
wire [7:0] mcr_reg;
wire [7:0] lsr_reg;
wire [7:0] msr_reg;
wire [7:0] dll_reg;
wire [7:0] dlm_reg;
// Events
event ier_reg_changed;
event iir_reg_changed;
event fcr_reg_changed;
event lcr_reg_changed;
event mcr_reg_changed;
event lsr_reg_changed;
event msr_reg_changed;
event dll_reg_changed;
event dlm_reg_changed;
// Register access
reg [`UART_ADDR_WIDTH-1:0] reg_adr;
reg [`UART_DATA_WIDTH-1:0] reg_dat;
reg reg_dlab;
event reg_written;
event tx_reg_written;
event reg_read;
event rx_reg_read;
uart_top #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH) i_uart_top
(
.wb_clk_i (wb_clk),
.wb_rst_i (wb_reset),
.int_o (wb_int_o),
// WB slave signals - 2 address locations for two registers!
.wb_cyc_i (wbs_cyc_i),
.wb_stb_i (wbs_stb_i),
.wb_we_i (wbs_we_i),
.wb_sel_i (wbs_sel_i),
.wb_adr_i (wbs_adr_i),
.wb_dat_i (wbs_dat_i),
.wb_dat_o (wbs_dat_o),
.wb_ack_o (wbs_ack_o),
// UART signals
.stx_pad_o (stx_pad_o),
.srx_pad_i (srx_pad_i),
// Modem signals
.rts_pad_o (rts_pad_o),
.cts_pad_i (cts_pad_i),
.dtr_pad_o (dtr_pad_o),
.dsr_pad_i (dsr_pad_i),
.ri_pad_i (ri_pad_i),
.dcd_pad_i (dcd_pad_i)
`ifdef UART_HAS_BAUDRATE_OUTPUT
,
.baud_o (baud_o)
`endif
);
uart_device i_uart_device
(
// UART signals
.stx_i (stx_pad_o),
.srx_o (srx_pad_i),
// Modem signals
.rts_i (rts_pad_o),
.cts_o (cts_pad_i),
.dtr_i (dtr_pad_o),
.dsr_o (dsr_pad_i),
.ri_o (ri_pad_i),
.dcd_o (dcd_pad_i)
);
wb_master_model #(`UART_DATA_WIDTH, `UART_ADDR_WIDTH, 4) i_wb_master_model
(
.wb_rst_i (wb_reset),
.wb_clk_i (wb_clk),
.wbm_cyc_o (wbs_cyc_i),
.wbm_cti_o (),
.wbm_bte_o (),
.wbm_stb_o (wbs_stb_i),
.wbm_we_o (wbs_we_i),
.wbm_adr_o (wbs_adr_i),
.wbm_sel_o (wbs_sel_i),
.wbm_dat_o (wbs_dat_i),
.wbm_dat_i (wbs_dat_o),
.wbm_ack_i (wbs_ack_o),
.wbm_err_i (wbs_err_o), // inactive (1'b0)
.wbm_rty_i (wbs_rty_o) // inactive (1'b0)
);
initial
begin:system
// Initial system values
wb_reset = 1'b1;
wb_clk = 1'b0;
end
// WB clock generation (DEVICE clock is generated in uart_device.v)
//#################################################################
// DEVICE's clock generation:
// ----------------
// // rx_clk rising edge
// always@(posedge rx_clk)
// if (rx_clk_en)
// #(T_clk_period / 2) rx_clk = 1'b0;
// // rx_clk falling edge
// always@(negedge rx_clk)
// if (rx_clk_en)
// #(T_clk_period / 2) rx_clk = 1'b1;
// ----------------
// DEVICE's transmit clocks generation:
// ----------------
// // tx_clk rising edge
// always@(posedge tx_clk)
// if (tx_clk_en)
// #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b0;
// // tx_clk falling edge
// always@(negedge tx_clk)
// if (tx_clk_en)
// #((T_clk_period / 2) * 16 * T_divisor) tx_clk = 1'b1;
// ----------------
// WB clock
always@(posedge wb_clk)
if (wb_clk_en)
#(T_wb_clk_period / 2) wb_clk = 1'b0;
always@(negedge wb_clk)
if (wb_clk_en)
#(T_wb_clk_period / 2) wb_clk = 1'b1;
// SYSTEM signals tracker
//#######################
// Reset
always@(posedge wb_reset)
-> reset_aserted;
always@(negedge wb_reset)
-> reset_released;
// Interrupt
always@(posedge wb_int_o)
-> int_aserted;
always@(negedge wb_int_o)
-> int_released;
// UART register tracker
//######################
// UART registers:
// ----------------
// RBR (R/ | ADR 0 | DLAB 0)
// [7:0] -RX---- "rxdata" Receiver Buffer Register
// ----------------
// THR ( /W | ADR 0 | DLAB 0)
// [7:0] ----TX- "txdata" Transmitter Holding Register
// ----------------
// IER (R/W | ADR 1 | DLAB 0)
// [0] -RX---- "1" Received Data Available & Receive Fifo Timeout
// [1] ----TX- "1" Transmitter Holding Register Empty
// [2] -RX---- "1" Receiver Line Status
// [3] -MODEM- "1" Modem Status
// ----------------
// IIR (R/ | ADR 2)
// [0] ------- "0" Interrupt is Pending (decreasing priority level in following 3 bits)
// [3:1] -RX---- "011" Receiver Line Status - Overrun, Parity, Framing error or Break int. ---> READ LSR
// [3:1] -RX---- "010" Received Data Available - Fifo Trigger Level Reached ------------------> READ RBR (Fifo lower than trig.)
// [3:1] -RX---- "110" Timeout Indication - Fifo not empty & no Fifo action for 4 char times -> READ RBR
// [3:1] ----TX- "001" Transmitter Holding Register Empty - THR Empty ------------------------> READ IIR | WRITE THR
// [3:1] -MODEM- "000" Modem Status - CTS, DSR, DCD changed or RI changed from '0' to '1' ----> READ MSR
// ----------------
// FCR ( /W | ADR 2)
// [1] -RX---- "1" Clear only Receiver Fifo (not shift register)
// [2] ----TX- "1" Clear only Transmitter Fifo (not shift register)
// [7:6] -RX---- "00" 1 BYTE Receiver Fifo Interrupt trigger level
// [7:6] -RX---- "01" 4 BYTEs Receiver Fifo Interrupt trigger level
// [7:6] -RX---- "10" 8 BYTEs Receiver Fifo Interrupt trigger level
// [7:6] -RX---- "11" 14 BYTEs Receiver Fifo Interrupt trigger level
// ----------------
// LCR (R/W | ADR 3)
// [1:0] -RX-TX- "00" 5 bits in each character
// [1:0] -RX-TX- "01" 6 bits in each character
// [1:0] -RX-TX- "10" 7 bits in each character
// [1:0] -RX-TX- "11" 8 bits in each character
// [2] -RX-TX- "0" 1 stop bit
// [2] -RX-TX- "1" 1.5 stop bits (when 5 bits of char.) or 2 stop bits (when 6, 7 or 8 bits of char.)
// [3] -RX-TX- "1" Parity bit enabled
// [5:4] -RX-TX- "00" NO Stick Parity & ODD Parity bit - ODD num. of '1's is transmitted
// [5:4] -RX-TX- "01" NO Stick Parity & EVEN Parity bit - EVEN num. of '1's is transmitted
// [5:4] -RX-TX- "10" Stick Parity bit - Stick '1' as Parity bit
// [5:4] -RX-TX- "11" Stick Parity bit - Stick '0' as Parity bit
// [6] ----TX- "1" Break Control - Output is forced to '0'
// [7] ------- "1" DLAB - for access to DLL and DLM
// ----------------
// MCR ( /W | ADR 4)
// [0] -MODEM- "1" Force DTR to '0' - in LoopBack connected to DSR input
// [1] -MODEM- "1" Force RTS to '0' - in LoopBack connected to CTS input
// [2] -MODEM- "1" Force N.C.1 to '0' - in LoopBack connected to RI input
// [3] -MODEM- "1" Force N.C.2 to '0' - in LoopBack connected to DCD input
// [4] -MODEM- "1" LoopBack mode
// ----------------
// LSR (R/ | ADR 5)
// [0] -RX---- "1" Data Ready - At least 1 char. received and is in Fifo----------> READ RBR (Fifo empty)
// [1] -RX---- "1" Overrun Error - Fifo full & 1 char. received in shift reg. ----> READ LSR
// [2] -RX---- "1" Parity Error - top Fifo char. has invalid parity bit ----------> READ LSR
// [3] -RX---- "1" Framing Error - top Fifo char. has invalid stop bit -----------> READ LSR
// [4] -RX---- "1" Break Int. - top Fifo char. bits are '0' and it's ctrl. bits --> READ LSR
// [5] ----TX- "1" Transmitter Holding Register Empty - transmitter Fifo empty ---> WRITE THR
// [6] ----TX- "1" Transmitter EMpTy - transmitter Fifo empty & shift reg. empty -> WRITE THR
// [7] -RX---- "1" At least 1 Parity Error, Framing Error or Break Int. in Fifo --> READ LSR & No More Errors in Fifo
// ----------------
// MSR (R/ | ADR 6)
// [0] -MODEM- "1" Delta CTS indicator - CTS has changed it's state --------------> READ MSR
// [1] -MODEM- "1" Delta DSR indicator - DSR has changed it's state --------------> READ MSR
// [2] -MODEM- "1" Trailing Edge of RI - RI has changed from '0' to '1' ----------> READ MSR
// [3] -MODEM- "1" Delta DCD indicator - DCD has changed it's state --------------> READ MSR
// [4] -MODEM- "x" Complement of CTS input | in LoopBack equal to RTS = MCR[1]
// [5] -MODEM- "x" Complement of DSR input | in LoopBack equal to DTR = MCR[0]
// [6] -MODEM- "x" Complement of RI input | in LoopBack equal to N.C.1 = MCR[2]
// [7] -MODEM- "x" Complement of DCD input | in LoopBack equal to N.C.2 = MCR[3]
// ----------------
// DLL (R/W | ADR 0 | DLAB 1)
// [7:0] ------- "dl[ 7:0]" LSB of DL Reg. written 2. - dl == '0' disables outputs / dl = 1/(T_wb_clk_period*16*BaudRate)
// ----------------
// DLM (R/W | ADR 1 | DLAB 1)
// [7:0] ------- "dl[15:8]" MSB of DL Reg. written 1. - dl == '0' disables outputs / dl = 1/(T_wb_clk_period*16*BaudRate)
// ----------------
// Transparent UART registers
assign ier_reg[7:0] = {4'h0, testbench.i_uart_top.regs.ier };
assign iir_reg[7:0] = {4'hC, testbench.i_uart_top.regs.iir };
assign fcr_reg[7:0] = { testbench.i_uart_top.regs.fcr, 6'h0};
assign lcr_reg[7:0] = { testbench.i_uart_top.regs.lcr }; // lcr_reg[7] == DLAB !!!
assign mcr_reg[7:0] = {3'h0, testbench.i_uart_top.regs.mcr };
assign lsr_reg[7:0] = { testbench.i_uart_top.regs.lsr };
assign msr_reg[7:0] = { testbench.i_uart_top.regs.msr };
assign dll_reg[7:0] = { testbench.i_uart_top.regs.dl[ 7:0] };
assign dlm_reg[7:0] = { testbench.i_uart_top.regs.dl[15:8] };
// Tracking changes of registers
always@(ier_reg)
begin
-> ier_reg_changed;
end
always@(iir_reg)
begin
-> iir_reg_changed;
end
always@(fcr_reg)
begin
-> fcr_reg_changed;
end
always@(lcr_reg)
begin
-> lcr_reg_changed;
end
always@(mcr_reg)
begin
-> mcr_reg_changed;
end
always@(lsr_reg)
begin
-> lsr_reg_changed;
end
always@(msr_reg)
begin
-> msr_reg_changed;
end
always@(dll_reg)
begin
-> dll_reg_changed;
end
always@(dlm_reg)
begin
-> dlm_reg_changed;
end
// Tracking read/write access to registers
always@(wbs_cyc_i or wbs_stb_i or wbs_we_i or wbs_sel_i or wbs_adr_i or
wbs_dat_i /*or wbs_ack_o*/ /*or posedge wb_clk*/)
begin
if (wbs_cyc_i && wbs_stb_i)
begin
if (wbs_we_i /*&& wbs_ack_o*/) // WRITE
begin
// LOG's example of detecting of register write:
// ----------------
// case (wbs_adr_i)
// `UART_REG_TR: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
// -> dll_reg_written;
// else
// -> thr_reg_written;
// `UART_REG_IE: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
// -> dlm_reg_written;
// else
// -> ier_reg_written;
// `UART_REG_FC: -> fcr_reg_written;
// `UART_REG_LC: -> lcr_reg_written;
// `UART_REG_MC: -> mcr_reg_written;
// default: -> erroneous_write_location;
// endcase
// ----------------
reg_adr = wbs_adr_i;
reg_dat = wbs_dat_i;
reg_dlab = lcr_reg[7];
-> reg_written;
if (~reg_dlab && (reg_adr == `UART_REG_TR)) // write to FIFO
-> tx_reg_written;
end
end
end
always@(wbs_cyc_i or wbs_stb_i or wbs_we_i or wbs_sel_i or wbs_adr_i or
wbs_dat_o or wbs_ack_o /*or posedge wb_clk*/)
begin
if (wbs_cyc_i && wbs_stb_i)
begin
if (~wbs_we_i && wbs_ack_o) // READ
begin
// LOG's example of detecting of register read:
// ----------------
// case (wbs_adr_i)
// `UART_REG_RB: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
// -> dll_reg_read;
// else
// -> rbr_reg_read;
// `UART_REG_IE: if (lcr_reg[7]) // lcr_reg[7] == DLAB !!!
// -> dlm_reg_read;
// else
// -> ier_reg_read;
// `UART_REG_II: -> iir_reg_read;
// `UART_REG_LC: -> lcr_reg_read;
// `UART_REG_LS: -> lsr_reg_read;
// `UART_REG_MS: -> msr_reg_read;
// default: -> erroneous_read_location;
// endcase
// ----------------
reg_adr = wbs_adr_i;
reg_dat = wbs_dat_o;
reg_dlab = lcr_reg[7];
-> reg_read;
if (~reg_dlab && (reg_adr == `UART_REG_RB))
-> rx_reg_read;
end
end
end
// UART register monitor
//#######################
// Line Status Register
// Reading LSR register
initial
begin
lsr_reg_read = 0;
forever
begin
@(reg_read);
if (reg_adr == `UART_REG_LS)
begin
lsr_reg_read = 1'b1;
repeat (1) @(posedge wb_clk);
lsr_reg_read = 0;
end
end
end
// Bit 0 - Data Ready
initial
begin
lsr_reg_bit0_change_allowed = 0;
@(reset_released);
#10;
fork
begin: rx_fifo_status_changing
forever
begin
if (rx_fifo_status == 0)
begin
wait (rx_fifo_status > 0);
lsr_reg_bit0_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit0_change_allowed = 0;
if (~lsr_reg[0])
begin
`BENCH_ERROR("Bit 0 of LSR register not '1'!");
-> error_detected;
end
end
else
begin
wait (rx_fifo_status == 0);
lsr_reg_bit0_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit0_change_allowed = 0;
if (lsr_reg[0])
begin
`BENCH_ERROR("Bit 0 of LSR register not '0'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit0_changing
forever
begin
wait (~lsr_reg_bit0_change_allowed);
begin
@(lsr_reg[0] or lsr_reg_bit0_change_allowed);
if (~lsr_reg_bit0_change_allowed)
begin
`BENCH_ERROR("Bit 0 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// Bit 1 - Overrun Error
initial
begin
lsr_reg_bit1_change_allowed = 0;
@(reset_released);
#10;
fork
begin: rx_overrun_err_occured_changing
forever
begin
if (~rx_overrun_err_occured)
begin
wait (rx_overrun_err_occured);
lsr_reg_bit1_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit1_change_allowed = 0;
if (~lsr_reg[1])
begin
`BENCH_ERROR("Bit 1 of LSR register not '1'!");
-> error_detected;
end
end
else
begin
wait (lsr_reg_read);
lsr_reg_bit1_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit1_change_allowed = 0;
rx_overrun_err_occured = 0;
if (lsr_reg[1])
begin
`BENCH_ERROR("Bit 1 of LSR register not '0'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit1_changing
forever
begin
wait (~lsr_reg_bit1_change_allowed);
begin
@(lsr_reg[1] or lsr_reg_bit1_change_allowed);
if (~lsr_reg_bit1_change_allowed)
begin
`BENCH_ERROR("Bit 1 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// Bit 2 - Parity Error
initial
begin
lsr_reg_bit2_change_allowed = 0;
rx_fifo_par_rd_pointer = 0;
@(reset_released);
#10;
fork
begin: rx_parity_err_changing
forever
begin
if (~rx_fifo_par[rx_fifo_par_rd_pointer])
begin
wait (rx_fifo_read);
lsr_reg_bit2_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit2_change_allowed = 0;
rx_fifo_par_rd_pointer = rx_fifo_par_rd_pointer + 1'b1;
// check bit
if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer])
begin
`BENCH_ERROR("Bit 2 of LSR register not '1'!");
-> error_detected;
end
else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer])
begin
`BENCH_ERROR("Bit 2 of LSR register not '0'!");
-> error_detected;
end
end
else
begin
wait (lsr_reg_read);
lsr_reg_bit2_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit2_change_allowed = 0;
if (rx_fifo_par_rd_pointer < rx_fifo_rd_pointer)
begin
for (i2 = rx_fifo_par_rd_pointer; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1)
rx_fifo_par[i2] = 0;
rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
end
else if (rx_fifo_par_rd_pointer > rx_fifo_rd_pointer)
begin
for (i2 = rx_fifo_par_rd_pointer; i2 <= 31; i2 = i2 + 1)
rx_fifo_par[i2] = 0;
for (i2 = 0; i2 <= rx_fifo_rd_pointer; i2 = i2 + 1)
rx_fifo_par[i2] = 0;
rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
end
else
begin
rx_fifo_par = 0;
rx_fifo_par_rd_pointer = rx_fifo_rd_pointer;
end
// check bit
if (~lsr_reg[2] && rx_fifo_par[rx_fifo_par_rd_pointer])
begin
`BENCH_ERROR("Bit 2 of LSR register not '1'!");
-> error_detected;
end
else if (lsr_reg[2] && ~rx_fifo_par[rx_fifo_par_rd_pointer])
begin
`BENCH_ERROR("Bit 2 of LSR register not '0'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit2_changing
forever
begin
wait (~lsr_reg_bit2_change_allowed);
begin
@(lsr_reg[2] or lsr_reg_bit2_change_allowed);
if (~lsr_reg_bit2_change_allowed)
begin
`BENCH_ERROR("Bit 2 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// Bit 3 - Framing Error
initial
begin
lsr_reg_bit3_change_allowed = 0;
rx_fifo_frm_rd_pointer = 0;
@(reset_released);
#10;
fork
begin: rx_framing_err_changing
forever
begin
if (~rx_fifo_frm[rx_fifo_frm_rd_pointer])
begin
wait (rx_fifo_read);
lsr_reg_bit3_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit3_change_allowed = 0;
rx_fifo_frm_rd_pointer = rx_fifo_frm_rd_pointer + 1'b1;
// check bit
if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer])
begin
`BENCH_ERROR("Bit 3 of LSR register not '1'!");
-> error_detected;
end
else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer])
begin
`BENCH_ERROR("Bit 3 of LSR register not '0'!");
-> error_detected;
end
end
else
begin
wait (lsr_reg_read);
lsr_reg_bit3_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit3_change_allowed = 0;
if (rx_fifo_frm_rd_pointer < rx_fifo_rd_pointer)
begin
for (i3 = rx_fifo_frm_rd_pointer; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1)
rx_fifo_frm[i3] = 0;
rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
end
else if (rx_fifo_frm_rd_pointer > rx_fifo_rd_pointer)
begin
for (i3 = rx_fifo_frm_rd_pointer; i3 <= 31; i3 = i3 + 1)
rx_fifo_frm[i3] = 0;
for (i3 = 0; i3 <= rx_fifo_rd_pointer; i3 = i3 + 1)
rx_fifo_frm[i3] = 0;
rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
end
else
begin
rx_fifo_frm = 0;
rx_fifo_frm_rd_pointer = rx_fifo_rd_pointer;
end
// check bit
if (~lsr_reg[3] && rx_fifo_frm[rx_fifo_frm_rd_pointer])
begin
`BENCH_ERROR("Bit 3 of LSR register not '1'!");
-> error_detected;
end
else if (lsr_reg[3] && ~rx_fifo_frm[rx_fifo_frm_rd_pointer])
begin
`BENCH_ERROR("Bit 3 of LSR register not '0'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit3_changing
forever
begin
wait (~lsr_reg_bit3_change_allowed);
begin
@(lsr_reg[3] or lsr_reg_bit3_change_allowed);
if (~lsr_reg_bit3_change_allowed)
begin
`BENCH_ERROR("Bit 3 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// Bit 4 - Break Interrupt
initial
begin
lsr_reg_bit4_change_allowed = 0;
rx_fifo_brk_rd_pointer = 0;
@(reset_released);
#10;
fork
begin: rx_break_int_changing
forever
begin
if (~rx_fifo_brk[rx_fifo_brk_rd_pointer])
begin
wait (rx_fifo_read);
lsr_reg_bit4_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit4_change_allowed = 0;
rx_fifo_brk_rd_pointer = rx_fifo_brk_rd_pointer + 1'b1;
// check bit
if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer])
begin
`BENCH_ERROR("Bit 4 of LSR register not '1'!");
-> error_detected;
end
else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer])
begin
`BENCH_ERROR("Bit 4 of LSR register not '0'!");
-> error_detected;
end
end
else
begin
wait (lsr_reg_read);
lsr_reg_bit4_change_allowed = 1'b1;
repeat (1) @(posedge wb_clk);
#2;
lsr_reg_bit4_change_allowed = 0;
if (rx_fifo_brk_rd_pointer < rx_fifo_rd_pointer)
begin
for (i4 = rx_fifo_brk_rd_pointer; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1)
rx_fifo_brk[i4] = 0;
rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
end
else if (rx_fifo_brk_rd_pointer > rx_fifo_rd_pointer)
begin
for (i4 = rx_fifo_brk_rd_pointer; i4 <= 31; i4 = i4 + 1)
rx_fifo_brk[i4] = 0;
for (i4 = 0; i4 <= rx_fifo_rd_pointer; i4 = i4 + 1)
rx_fifo_brk[i4] = 0;
rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
end
else
begin
rx_fifo_brk = 0;
rx_fifo_brk_rd_pointer = rx_fifo_rd_pointer;
end
// check bit
if (~lsr_reg[4] && rx_fifo_brk[rx_fifo_brk_rd_pointer])
begin
`BENCH_ERROR("Bit 4 of LSR register not '1'!");
-> error_detected;
end
else if (lsr_reg[4] && ~rx_fifo_brk[rx_fifo_brk_rd_pointer])
begin
`BENCH_ERROR("Bit 4 of LSR register not '0'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit4_changing
forever
begin
wait (~lsr_reg_bit4_change_allowed);
begin
@(lsr_reg[4] or lsr_reg_bit4_change_allowed);
if (~lsr_reg_bit4_change_allowed)
begin
`BENCH_ERROR("Bit 4 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// Bit 5 - Transmitter Holding Register Empty
initial
begin
lsr_reg_bit5_change_allowed = 0;
@(reset_released);
#10;
fork
begin: tx_fifo_status_changing
forever
begin
if (tx_fifo_status == 0)
begin
// @(tx_reg_written);
wait (tx_fifo_status > 0);
lsr_reg_bit5_change_allowed = 1'b1;
repeat (3) @(posedge wb_clk);
#2;
lsr_reg_bit5_change_allowed = 0;
if (lsr_reg[5])
begin
`BENCH_ERROR("Bit 5 of LSR register not '0'!");
-> error_detected;
end
end
else
begin
wait (tx_fifo_status == 0);
lsr_reg_bit5_change_allowed = 1'b1;
repeat (3) @(posedge wb_clk);
#2;
lsr_reg_bit5_change_allowed = 0;
if (~lsr_reg[5])
begin
`BENCH_ERROR("Bit 5 of LSR register not '1'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit5_changing
forever
begin
wait (~lsr_reg_bit5_change_allowed);
begin
@(lsr_reg[5] or lsr_reg_bit5_change_allowed);
if (~lsr_reg_bit5_change_allowed)
begin
`BENCH_ERROR("Bit 5 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// Bit 6 - Transmitter Empty
initial
begin
lsr_reg_bit6_change_allowed = 0;
@(reset_released);
#10;
fork
begin: tx_fifo_status_and_shift_reg_changing
forever
begin
if ((tx_fifo_status == 0) && tx_shift_reg_empty)
begin
// @(tx_reg_written);
wait (tx_fifo_status > 0);
lsr_reg_bit6_change_allowed = 1'b1;
repeat (3) @(posedge wb_clk);
#2;
lsr_reg_bit6_change_allowed = 0;
if (lsr_reg[6])
begin
`BENCH_ERROR("Bit 6 of LSR register not '0'!");
-> error_detected;
end
end
else
begin
wait ((tx_fifo_status == 0) && tx_shift_reg_empty);
lsr_reg_bit6_change_allowed = 1'b1;
repeat (3) @(posedge wb_clk);
#2;
lsr_reg_bit6_change_allowed = 0;
if (~lsr_reg[6])
begin
`BENCH_ERROR("Bit 6 of LSR register not '1'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit6_changing
forever
begin
wait (~lsr_reg_bit6_change_allowed);
begin
@(lsr_reg[6] or lsr_reg_bit6_change_allowed);
if (~lsr_reg_bit6_change_allowed)
begin
`BENCH_ERROR("Bit 6 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// Bit 7 - Error in RX FIFO
initial
begin
lsr_reg_bit7_change_allowed = 0;
@(reset_released);
#10;
fork
begin: error_changing
forever
begin
if ((rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0))
begin
wait (rx_parity_err || rx_framing_err || rx_framing_glitch || rx_break_int);
lsr_reg_bit7_change_allowed = 1'b1;
repeat (3) @(posedge wb_clk);
#2;
lsr_reg_bit7_change_allowed = 0;
// check bit
if (~lsr_reg[7])
begin
`BENCH_ERROR("Bit 7 of LSR register not '1'!");
-> error_detected;
end
end
else
begin
wait (lsr_reg_read && (rx_fifo_par == 0) && (rx_fifo_frm == 0) && (rx_fifo_brk == 0));
lsr_reg_bit7_change_allowed = 1'b1;
repeat (2) @(posedge wb_clk);
#2;
lsr_reg_bit7_change_allowed = 0;
// check bit
if (lsr_reg[7])
begin
`BENCH_ERROR("Bit 7 of LSR register not '0'!");
-> error_detected;
end
end
end
end
begin: lsr_reg_bit7_changing
forever
begin
wait (~lsr_reg_bit7_change_allowed);
begin
@(lsr_reg[7] or lsr_reg_bit7_change_allowed);
if (~lsr_reg_bit7_change_allowed)
begin
`BENCH_ERROR("Bit 7 of LSR register should not change!");
-> error_detected;
end
end
end
end
join
end
// UART transmitter monitor
//#########################
// TX FIFO status
always@(tx_fifo_wr_pointer or tx_fifo_rd_pointer)
begin
if (tx_fifo_wr_pointer >= tx_fifo_rd_pointer)
tx_fifo_status = tx_fifo_wr_pointer - tx_fifo_rd_pointer;
else
tx_fifo_status = (5'h1F - tx_fifo_rd_pointer) + tx_fifo_wr_pointer;
end
// TX FIFO and TX data
initial
begin
tx_fifo_wr_pointer = 0;
tx_fifo_rd_pointer = 0;
tx_shift_reg_empty = 1;
tx_fifo_status = 0;
tx_start_bit_edge = 1;
fork
begin:write_tx_shift_reg_read_tx_fifo
forever
begin
wait ((tx_fifo_status !== 0) && tx_shift_reg_empty && tx_start_bit_edge && ~stx_pad_o);
tx_start_bit_edge = 0;
tx_shift_reg = tx_fifo[tx_fifo_rd_pointer];
tx_shift_reg_empty = 0;
@(testbench.i_uart_device.device_received_last_bit);
repeat (16393) @(posedge wb_clk);
tx_fifo_rd_pointer = tx_fifo_rd_pointer + 1'b1;
@(posedge wb_clk);
if (tx_fifo_status == 0)
begin
`BENCH_MSG("TX FIFO is empty!");
end
end
end
begin:write_tx_fifo
forever
begin
@(tx_reg_written); // write to FIFO
repeat (1) @(posedge wb_clk); // delay when writing into registers
if (tx_fifo_status <= 5'h0F)
begin
tx_fifo[tx_fifo_wr_pointer] = reg_dat;
tx_fifo_wr_pointer = tx_fifo_wr_pointer + 1'b1;
end
else // FIFO overflow
begin
`BENCH_WARNING("TX FIFO overflow!");
end
end
end
begin:empty_tx_fifo
forever
begin
wait (fcr_reg[2]);
tx_fifo_wr_pointer = 0;
tx_fifo_rd_pointer = 0;
@(posedge wb_clk);
if (tx_fifo_status == 0)
begin
`BENCH_MSG("TX FIFO is empty!");
end
end
end
begin:read_tx_shift_reg
forever
begin
@(testbench.i_uart_device.device_received_packet);
// Check data
if (tx_shift_reg != testbench.i_uart_device.rx_data)
begin
`BENCH_ERROR("TX data has ERROR!");
-> error_detected;
end
else
`BENCH_MSG("TX data correct!");
if (testbench.i_uart_device.rx_parity_error)
begin
`BENCH_ERROR("TX data has parity ERROR!");
-> error_detected;
end
else
`BENCH_MSG("TX data parity correct!");
if (testbench.i_uart_device.rx_framing_error)
begin
`BENCH_ERROR("TX data has framing ERROR!");
-> error_detected;
end
else
`BENCH_MSG("TX data framing correct!");
// Set TX FIFO read pointer
tx_start_bit_edge = 1;
repeat (7) @(wb_clk);
if (tx_shift_reg_empty == 0)
begin
tx_shift_reg_empty = 1'b1;
end
else
begin
`BENCH_ERROR("TX shift register empty while transmiting data!");
-> error_detected;
end
end
end
join
end
// UART receiver monitor
//######################
// RX FIFO status
always@(rx_fifo_wr_pointer or rx_fifo_rd_pointer)
begin
if (rx_fifo_wr_pointer >= rx_fifo_rd_pointer)
rx_fifo_status = rx_fifo_wr_pointer - rx_fifo_rd_pointer;
else
rx_fifo_status = (5'h1F - rx_fifo_rd_pointer) + rx_fifo_wr_pointer;
end
// RX FIFO and RX data
initial
begin
rx_parity_err = 0;
rx_framing_err = 0;
rx_framing_glitch = 0;
rx_break_int = 0;
rx_overrun_err_occured = 0;
rx_fifo_par = 0;
rx_fifo_frm = 0;
rx_fifo_brk = 0;
rx_shift_reg_full = 0;
rx_fifo_wr_pointer = 0;
rx_fifo_rd_pointer = 0;
rx_fifo_status = 0;
fork
begin:write_rx_shift_reg
forever
begin
@(testbench.i_uart_device.device_sent_packet);
repeat (1) @(posedge wb_clk);
rx_shift_reg = testbench.i_uart_device.sent_data;
rx_parity_err = testbench.i_uart_device.tx_parity_enabled &&
(testbench.i_uart_device.tx_parity_wrong ||
( // sample point is BIT_NUM * 2 - 1 => 3, 5, 7...
((testbench.i_uart_device.tx_glitch_num == (3 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (5 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (7 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (9 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (11 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (13 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (15 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (17 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (19 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (21 * 8 * testbench.i_uart_device.T_divisor)) ||
(testbench.i_uart_device.tx_glitch_num == (23 * 8 * testbench.i_uart_device.T_divisor))) &&
(testbench.i_uart_device.tx_glitch_num[23:0] < ((testbench.i_uart_device.tx_length + 2'h1) *
16 * testbench.i_uart_device.T_divisor))
));
rx_framing_err = testbench.i_uart_device.tx_framing_wrong;
rx_framing_glitch = (testbench.i_uart_device.tx_glitch_num == ((((testbench.i_uart_device.tx_length + 2'h2 +
testbench.i_uart_device.tx_parity_enabled) *
2) - 1'b1) * 8 * testbench.i_uart_device.T_divisor));
rx_break_int = testbench.i_uart_device.tx_break_enable &&
(testbench.i_uart_device.tx_break_num[15:0] >= ((testbench.i_uart_device.tx_length + 2'h2 +
testbench.i_uart_device.tx_parity_enabled) *
16 * testbench.i_uart_device.T_divisor));
-> testbench.i_uart_device.sent_packet_received;
if (rx_fifo_status > 5'h0F)
rx_overrun_err_occured = 1'b1;
rx_shift_reg_full = 1'b1;
end
end
begin:write_rx_fifo_read_rx_shift_reg
forever
begin
wait (rx_shift_reg_full);
if (rx_fifo_status <= 5'h0F)
begin
rx_fifo_data[rx_fifo_wr_pointer] = testbench.i_uart_device.sent_data;
rx_fifo_par[rx_fifo_wr_pointer] = rx_parity_err;
rx_fifo_frm[rx_fifo_wr_pointer] = rx_framing_err || rx_framing_glitch;
rx_fifo_brk[rx_fifo_wr_pointer] = rx_break_int;
rx_fifo_wr_pointer = rx_fifo_wr_pointer + 1'b1;
end
else // FIFO overflow
begin
`BENCH_WARNING("RX FIFO overflow!");
end
repeat (1) @(posedge wb_clk);
rx_shift_reg_full = 0;
end
end
begin:empty_rx_fifo
forever
begin
wait (fcr_reg[1]);
rx_fifo_wr_pointer = 0;
rx_fifo_rd_pointer = 0;
// rx_fifo_par = 0;
// rx_fifo_frm = 0;
// rx_fifo_brk = 0;
@(posedge wb_clk);
if (rx_fifo_status == 0)
begin
`BENCH_MSG("RX FIFO is empty!");
end
end
end
begin:read_rx_fifo
rx_fifo_read = 0;
forever
begin
@(rx_reg_read);
if (rx_fifo_status > 0)
begin
rx_fifo_read = 1'b1;
// Check data
if (rx_fifo_data[rx_fifo_rd_pointer] != reg_dat)
begin
`BENCH_ERROR("RX data has ERROR!");
-> error_detected;
end
else
begin
`BENCH_MSG("RX data correct!");
end
// Set RX FIFO read pointer
repeat (1) @(posedge wb_clk);
rx_fifo_read = 0;
rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1;
end
else
begin
`BENCH_WARNING("Reading RX FIFO while RX FIFO is empty!");
end
if ((~rx_fifo_frm[rx_fifo_rd_pointer] && lsr_reg[3]) ||
(rx_fifo_frm[rx_fifo_rd_pointer] && ~lsr_reg[3]))
begin
`BENCH_ERROR("RX data has wrong framing ERROR!");
-> error_detected;
end
else
`BENCH_MSG("RX data has correct framing error!");
// Set RX FIFO read pointer
repeat (1) @(posedge wb_clk);
rx_fifo_read = 0;
if (rx_fifo_status > 0)
begin
// rx_fifo_par[rx_fifo_rd_pointer] = 1'b0;
// rx_fifo_frm[rx_fifo_rd_pointer] = 1'b0;
// rx_fifo_brk[rx_fifo_rd_pointer] = 1'b0;
rx_fifo_rd_pointer = rx_fifo_rd_pointer + 1'b1;
end
end
end
join
end
// UART interrupt monitor
//#######################
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2015 12:30:30
// Design Name:
// Module Name: testcase_basic
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "packet_type.vh"
`include "system.vh"
module testcase_basic();
localparam X_LOCAL = 2;
localparam Y_LOCAL = 2;
localparam xpos_packets = 10;
localparam ypos_packets = 10;
localparam xneg_packets = 32;
localparam yneg_packets = 14;
localparam pe_packets = 21;
// --------------------------------------------------------------- >>>>>
//
// Area de modulos
//
// --------------------------------------------------------------- >>>>>
reg xpos = 1'b0;
reg ypos = 1'b0;
reg xneg = 1'b0;
reg yneg = 1'b0;
reg pe = 1'b0;
harness harness();
// -- x+
always
harness.xpos_in_channel.receive_credit();
// -- y+
always
harness.ypos_in_channel.receive_credit();
// -- x-
always
harness.xneg_in_channel.receive_credit();
// -- y-
always
harness.yneg_in_channel.receive_credit();
// -- pe
always
harness.pe_in_channel.receive_credit();
packet_generator
#(
.port(`X_POS),
.pe_percent(8),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
xpos_gen();
initial
begin: xpos_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < xpos_packets; index = index + 1)
begin
xpos_gen.random_packet(index);
harness.xpos_in_channel.send_packet(xpos_gen.packet);
end
xpos = 1'b1;
end
packet_generator
#(
.port(`X_NEG),
.pe_percent(1),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
xneg_gen();
initial
begin: xneg_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < xneg_packets; index = index + 1)
begin
xneg_gen.random_packet(index);
harness.xneg_in_channel.send_packet(xneg_gen.packet);
end
xneg = 1'b1;
end
packet_generator
#(
.port(`Y_POS),
.pe_percent(1),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
ypos_gen();
initial
begin: ypos_injector
integer index;
@(negedge harness.reset);
for (index = 0; index < ypos_packets; index = index + 1)
begin
ypos_gen.random_packet(index);
harness.ypos_in_channel.send_packet(ypos_gen.packet);
end
ypos = 1'b1;
end
packet_generator
#(
.port(`Y_NEG),
.pe_percent(1),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
yneg_gen();
initial
begin: yneg_injector
integer index;
@(negedge harness.reset);
//harness.yneg_in_channel.send_packet({"DAT4", "DAT3", "DAT2", "DAT1", {2'b10, 3'd2, 3'd4, "Y--"}});
for (index = 0; index < yneg_packets; index = index + 1)
begin
yneg_gen.random_packet(index);
harness.yneg_in_channel.send_packet(yneg_gen.packet);
end
yneg = 1'b1;
end
packet_generator
#(
.port(`PE),
.pe_percent(0),
.x_local(X_LOCAL),
.y_local(Y_LOCAL)
)
pe_gen();
initial
begin: pe_injector
integer index;
@(negedge harness.reset);
//harness.yneg_in_channel.send_packet({"DAT4", "DAT3", "DAT2", "DAT1", {2'b10, 3'd2, 3'd4, "Y--"}});
for (index = 0; index < pe_packets; index = index + 1)
begin
pe_gen.random_packet(index);
harness.pe_in_channel.send_packet(pe_gen.packet);
end
pe = 1'b1;
end
initial
begin : ciclo_principal
integer total_envio;
integer total_recepcion;
harness.sync_reset();
//repeat(120)
// @(negedge harness.clk);
@(xpos & ypos & xneg & yneg & pe)
repeat(20)
@(negedge harness.clk);
total_envio = harness.xpos_in_channel.packet_count +
harness.xneg_in_channel.packet_count +
harness.ypos_in_channel.packet_count +
harness.yneg_in_channel.packet_count +
harness.pe_in_channel.packet_count;
total_recepcion = harness.xpos_out_channel.packet_count +
harness.xneg_out_channel.packet_count +
harness.ypos_out_channel.packet_count +
harness.yneg_out_channel.packet_count +
harness.pe_out_channel.packet_count;
$display("",);
$display("",);
$display("",);
$display("|| -- PAQUETES ENVIADOS ---------------- >>>>>",);
$display("",);
$display("Paquetes enviados por x+: ", harness.xpos_in_channel.packet_count);
$display("Paquetes enviados por x-: ", harness.xneg_in_channel.packet_count);
$display("Paquetes enviados por y+: ", harness.ypos_in_channel.packet_count);
$display("Paquetes enviados por y-: ", harness.yneg_in_channel.packet_count);
$display("Paquetes enviados por pe: ", harness.pe_in_channel.packet_count);
$display("",);
$display("Total de paquetes enviados'testcase': ", total_envio);
$display("",);
$display("|| -- PAQUETES RECIBIDOS --------------- >>>>>",);
$display("",);
$display("Paquetes recibidos por x+: ", harness.xpos_out_channel.packet_count);
$display("Paquetes recibidos por x-: ", harness.xneg_out_channel.packet_count);
$display("Paquetes recibidos por y+: ", harness.ypos_out_channel.packet_count);
$display("Paquetes recibidos por y-: ", harness.yneg_out_channel.packet_count);
$display("Paquetes recibidos por pe: ", harness.pe_out_channel.packet_count);
$display("",);
$display("Total de paquetes recibidos'testcase': ", total_recepcion);
$display("",);
$display("|| -- TOTALES -------------------------- >>>>>",);
$display("",);
$display("",);
if(total_envio == total_recepcion)
$display("prueba satisfactoria",);
else
$display("prueba no satisfactoria",);
$display("",);
$display("",);
$display("",);
$finish;
end
endmodule // testcase_basic |
/********************************************/
/* audio_top.v */
/* */
/* 2012, [email protected] */
/********************************************/
module audio_top (
input wire clk,
input wire rst_n,
// config
input wire mix,
// audio shifter
input wire [ 15-1:0] rdata,
input wire [ 15-1:0] ldata,
input wire exchan,
output wire aud_bclk,
output wire aud_daclrck,
output wire aud_dacdat,
output wire aud_xck,
// I2C audio config
output wire i2c_sclk,
inout i2c_sdat
);
////////////////////////////////////////
// modules //
////////////////////////////////////////
// don't include these two modules for sim, as they have some probems in simulation
`ifndef SOC_SIM
// audio shifter
audio_shifter audio_shifter (
.clk (clk ),
.nreset (rst_n ),
.mix (mix ),
.rdata (rdata ),
.ldata (ldata ),
.exchan (exchan ),
.aud_bclk (aud_bclk ),
.aud_daclrck (aud_daclrck ),
.aud_dacdat (aud_dacdat ),
.aud_xck (aud_xck )
);
// I2C audio config
I2C_AV_Config audio_config (
// host side
.iCLK (clk ),
.iRST_N (rst_n ),
// i2c side
.oI2C_SCLK (i2c_sclk ),
.oI2C_SDAT (i2c_sdat )
);
`endif // SOC_SIM
endmodule
|
(** Extraction : tests of optimizations of pattern matching *)
Require Coq.extraction.Extraction.
(** First, a few basic tests *)
Definition test1 b :=
match b with
| true => true
| false => false
end.
Extraction test1. (** should be seen as the identity *)
Definition test2 b :=
match b with
| true => false
| false => false
end.
Extraction test2. (** should be seen a the always-false constant function *)
Inductive hole (A:Set) : Set := Hole | Hole2.
Definition wrong_id (A B : Set) (x:hole A) : hole B :=
match x with
| Hole _ => @Hole _
| Hole2 _ => @Hole2 _
end.
Extraction wrong_id. (** should _not_ be optimized as an identity *)
Definition test3 (A:Type)(o : option A) :=
match o with
| Some x => Some x
| None => None
end.
Extraction test3. (** Even with type parameters, should be seen as identity *)
Inductive indu : Type := A : nat -> indu | B | C.
Definition test4 n :=
match n with
| A m => A (S m)
| B => B
| C => C
end.
Extraction test4. (** should merge branchs B C into a x->x *)
Definition test5 n :=
match n with
| A m => A (S m)
| B => B
| C => B
end.
Extraction test5. (** should merge branches B C into _->B *)
Inductive indu' : Type := A' : nat -> indu' | B' | C' | D' | E' | F'.
Definition test6 n :=
match n with
| A' m => A' (S m)
| B' => C'
| C' => C'
| D' => C'
| E' => B'
| F' => B'
end.
Extraction test6. (** should merge some branches into a _->C' *)
(** NB : In Coq, "| a => a" corresponds to n, hence some "| _ -> n" are
extracted *)
Definition test7 n :=
match n with
| A m => Some m
| B => None
| C => None
end.
Extraction test7. (** should merge branches B,C into a _->None *)
(** Script from bug #2413 *)
Set Implicit Arguments.
Section S.
Definition message := nat.
Definition word := nat.
Definition mode := nat.
Definition opcode := nat.
Variable condition : word -> option opcode.
Section decoder_result.
Variable inst : Type.
Inductive decoder_result : Type :=
| DecUndefined : decoder_result
| DecUnpredictable : decoder_result
| DecInst : inst -> decoder_result
| DecError : message -> decoder_result.
End decoder_result.
Definition decode_cond_mode (mode : Type) (f : word -> decoder_result mode)
(w : word) (inst : Type) (g : mode -> opcode -> inst) :
decoder_result inst :=
match condition w with
| Some oc =>
match f w with
| DecInst i => DecInst (g i oc)
| DecError _ m => @DecError inst m
| DecUndefined _ => @DecUndefined inst
| DecUnpredictable _ => @DecUnpredictable inst
end
| None => @DecUndefined inst
end.
End S.
Extraction decode_cond_mode.
(** inner match should not be factorized with a partial x->x (different type) *)
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_test_bench (
// inputs:
A_cmp_result,
A_ctrl_ld_non_bypass,
A_en,
A_exc_active_no_break_no_crst,
A_exc_allowed,
A_exc_any_active,
A_exc_hbreak_pri1,
A_exc_highest_pri_exc_id,
A_exc_inst_fetch,
A_exc_norm_intr_pri5,
A_st_data,
A_valid,
A_wr_data_unfiltered,
A_wr_dst_reg,
E_add_br_to_taken_history_unfiltered,
M_bht_ptr_unfiltered,
M_bht_wr_data_unfiltered,
M_bht_wr_en_unfiltered,
M_mem_baddr,
M_target_pcb,
M_valid,
W_badaddr_reg,
W_bstatus_reg,
W_dst_regnum,
W_estatus_reg,
W_exception_reg,
W_iw,
W_iw_op,
W_iw_opx,
W_pcb,
W_status_reg,
W_valid,
W_vinst,
W_wr_dst_reg,
clk,
d_address,
d_byteenable,
d_read,
d_readdatavalid,
d_write,
i_address,
i_read,
i_readdatavalid,
reset_n,
// outputs:
A_wr_data_filtered,
E_add_br_to_taken_history_filtered,
M_bht_ptr_filtered,
M_bht_wr_data_filtered,
M_bht_wr_en_filtered,
test_has_ended
)
;
output [ 31: 0] A_wr_data_filtered;
output E_add_br_to_taken_history_filtered;
output [ 7: 0] M_bht_ptr_filtered;
output [ 1: 0] M_bht_wr_data_filtered;
output M_bht_wr_en_filtered;
output test_has_ended;
input A_cmp_result;
input A_ctrl_ld_non_bypass;
input A_en;
input A_exc_active_no_break_no_crst;
input A_exc_allowed;
input A_exc_any_active;
input A_exc_hbreak_pri1;
input [ 31: 0] A_exc_highest_pri_exc_id;
input A_exc_inst_fetch;
input A_exc_norm_intr_pri5;
input [ 31: 0] A_st_data;
input A_valid;
input [ 31: 0] A_wr_data_unfiltered;
input A_wr_dst_reg;
input E_add_br_to_taken_history_unfiltered;
input [ 7: 0] M_bht_ptr_unfiltered;
input [ 1: 0] M_bht_wr_data_unfiltered;
input M_bht_wr_en_unfiltered;
input [ 26: 0] M_mem_baddr;
input [ 26: 0] M_target_pcb;
input M_valid;
input [ 31: 0] W_badaddr_reg;
input [ 31: 0] W_bstatus_reg;
input [ 4: 0] W_dst_regnum;
input [ 31: 0] W_estatus_reg;
input [ 31: 0] W_exception_reg;
input [ 31: 0] W_iw;
input [ 5: 0] W_iw_op;
input [ 5: 0] W_iw_opx;
input [ 26: 0] W_pcb;
input [ 31: 0] W_status_reg;
input W_valid;
input [ 71: 0] W_vinst;
input W_wr_dst_reg;
input clk;
input [ 26: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_readdatavalid;
input d_write;
input [ 26: 0] i_address;
input i_read;
input i_readdatavalid;
input reset_n;
wire A_iw_invalid;
reg [ 26: 0] A_mem_baddr;
reg [ 26: 0] A_target_pcb;
wire [ 31: 0] A_wr_data_filtered;
wire A_wr_data_unfiltered_0_is_x;
wire A_wr_data_unfiltered_10_is_x;
wire A_wr_data_unfiltered_11_is_x;
wire A_wr_data_unfiltered_12_is_x;
wire A_wr_data_unfiltered_13_is_x;
wire A_wr_data_unfiltered_14_is_x;
wire A_wr_data_unfiltered_15_is_x;
wire A_wr_data_unfiltered_16_is_x;
wire A_wr_data_unfiltered_17_is_x;
wire A_wr_data_unfiltered_18_is_x;
wire A_wr_data_unfiltered_19_is_x;
wire A_wr_data_unfiltered_1_is_x;
wire A_wr_data_unfiltered_20_is_x;
wire A_wr_data_unfiltered_21_is_x;
wire A_wr_data_unfiltered_22_is_x;
wire A_wr_data_unfiltered_23_is_x;
wire A_wr_data_unfiltered_24_is_x;
wire A_wr_data_unfiltered_25_is_x;
wire A_wr_data_unfiltered_26_is_x;
wire A_wr_data_unfiltered_27_is_x;
wire A_wr_data_unfiltered_28_is_x;
wire A_wr_data_unfiltered_29_is_x;
wire A_wr_data_unfiltered_2_is_x;
wire A_wr_data_unfiltered_30_is_x;
wire A_wr_data_unfiltered_31_is_x;
wire A_wr_data_unfiltered_3_is_x;
wire A_wr_data_unfiltered_4_is_x;
wire A_wr_data_unfiltered_5_is_x;
wire A_wr_data_unfiltered_6_is_x;
wire A_wr_data_unfiltered_7_is_x;
wire A_wr_data_unfiltered_8_is_x;
wire A_wr_data_unfiltered_9_is_x;
wire E_add_br_to_taken_history_filtered;
wire E_add_br_to_taken_history_unfiltered_is_x;
wire [ 7: 0] M_bht_ptr_filtered;
wire M_bht_ptr_unfiltered_0_is_x;
wire M_bht_ptr_unfiltered_1_is_x;
wire M_bht_ptr_unfiltered_2_is_x;
wire M_bht_ptr_unfiltered_3_is_x;
wire M_bht_ptr_unfiltered_4_is_x;
wire M_bht_ptr_unfiltered_5_is_x;
wire M_bht_ptr_unfiltered_6_is_x;
wire M_bht_ptr_unfiltered_7_is_x;
wire [ 1: 0] M_bht_wr_data_filtered;
wire M_bht_wr_data_unfiltered_0_is_x;
wire M_bht_wr_data_unfiltered_1_is_x;
wire M_bht_wr_en_filtered;
wire M_bht_wr_en_unfiltered_is_x;
reg W_cmp_result;
reg W_exc_any_active;
reg [ 31: 0] W_exc_highest_pri_exc_id;
wire W_is_opx_inst;
reg W_iw_invalid;
wire W_op_add;
wire W_op_addi;
wire W_op_and;
wire W_op_andhi;
wire W_op_andi;
wire W_op_beq;
wire W_op_bge;
wire W_op_bgeu;
wire W_op_blt;
wire W_op_bltu;
wire W_op_bne;
wire W_op_br;
wire W_op_break;
wire W_op_bret;
wire W_op_call;
wire W_op_callr;
wire W_op_cmpeq;
wire W_op_cmpeqi;
wire W_op_cmpge;
wire W_op_cmpgei;
wire W_op_cmpgeu;
wire W_op_cmpgeui;
wire W_op_cmplt;
wire W_op_cmplti;
wire W_op_cmpltu;
wire W_op_cmpltui;
wire W_op_cmpne;
wire W_op_cmpnei;
wire W_op_crst;
wire W_op_custom;
wire W_op_div;
wire W_op_divu;
wire W_op_eret;
wire W_op_flushd;
wire W_op_flushda;
wire W_op_flushi;
wire W_op_flushp;
wire W_op_hbreak;
wire W_op_initd;
wire W_op_initda;
wire W_op_initi;
wire W_op_intr;
wire W_op_jmp;
wire W_op_jmpi;
wire W_op_ldb;
wire W_op_ldbio;
wire W_op_ldbu;
wire W_op_ldbuio;
wire W_op_ldh;
wire W_op_ldhio;
wire W_op_ldhu;
wire W_op_ldhuio;
wire W_op_ldl;
wire W_op_ldw;
wire W_op_ldwio;
wire W_op_mul;
wire W_op_muli;
wire W_op_mulxss;
wire W_op_mulxsu;
wire W_op_mulxuu;
wire W_op_nextpc;
wire W_op_nor;
wire W_op_op_rsv02;
wire W_op_op_rsv09;
wire W_op_op_rsv10;
wire W_op_op_rsv17;
wire W_op_op_rsv18;
wire W_op_op_rsv25;
wire W_op_op_rsv26;
wire W_op_op_rsv33;
wire W_op_op_rsv34;
wire W_op_op_rsv41;
wire W_op_op_rsv42;
wire W_op_op_rsv49;
wire W_op_op_rsv57;
wire W_op_op_rsv61;
wire W_op_op_rsv62;
wire W_op_op_rsv63;
wire W_op_opx_rsv00;
wire W_op_opx_rsv10;
wire W_op_opx_rsv15;
wire W_op_opx_rsv17;
wire W_op_opx_rsv21;
wire W_op_opx_rsv25;
wire W_op_opx_rsv33;
wire W_op_opx_rsv34;
wire W_op_opx_rsv35;
wire W_op_opx_rsv42;
wire W_op_opx_rsv43;
wire W_op_opx_rsv44;
wire W_op_opx_rsv47;
wire W_op_opx_rsv50;
wire W_op_opx_rsv51;
wire W_op_opx_rsv55;
wire W_op_opx_rsv56;
wire W_op_opx_rsv60;
wire W_op_opx_rsv63;
wire W_op_or;
wire W_op_orhi;
wire W_op_ori;
wire W_op_rdctl;
wire W_op_rdprs;
wire W_op_ret;
wire W_op_rol;
wire W_op_roli;
wire W_op_ror;
wire W_op_sll;
wire W_op_slli;
wire W_op_sra;
wire W_op_srai;
wire W_op_srl;
wire W_op_srli;
wire W_op_stb;
wire W_op_stbio;
wire W_op_stc;
wire W_op_sth;
wire W_op_sthio;
wire W_op_stw;
wire W_op_stwio;
wire W_op_sub;
wire W_op_sync;
wire W_op_trap;
wire W_op_wrctl;
wire W_op_wrprs;
wire W_op_xor;
wire W_op_xorhi;
wire W_op_xori;
reg [ 31: 0] W_st_data;
reg [ 26: 0] W_target_pcb;
reg W_valid_crst;
reg W_valid_hbreak;
reg W_valid_intr;
reg [ 31: 0] W_wr_data_filtered;
wire test_has_ended;
assign W_op_call = W_iw_op == 0;
assign W_op_jmpi = W_iw_op == 1;
assign W_op_op_rsv02 = W_iw_op == 2;
assign W_op_ldbu = W_iw_op == 3;
assign W_op_addi = W_iw_op == 4;
assign W_op_stb = W_iw_op == 5;
assign W_op_br = W_iw_op == 6;
assign W_op_ldb = W_iw_op == 7;
assign W_op_cmpgei = W_iw_op == 8;
assign W_op_op_rsv09 = W_iw_op == 9;
assign W_op_op_rsv10 = W_iw_op == 10;
assign W_op_ldhu = W_iw_op == 11;
assign W_op_andi = W_iw_op == 12;
assign W_op_sth = W_iw_op == 13;
assign W_op_bge = W_iw_op == 14;
assign W_op_ldh = W_iw_op == 15;
assign W_op_cmplti = W_iw_op == 16;
assign W_op_op_rsv17 = W_iw_op == 17;
assign W_op_op_rsv18 = W_iw_op == 18;
assign W_op_initda = W_iw_op == 19;
assign W_op_ori = W_iw_op == 20;
assign W_op_stw = W_iw_op == 21;
assign W_op_blt = W_iw_op == 22;
assign W_op_ldw = W_iw_op == 23;
assign W_op_cmpnei = W_iw_op == 24;
assign W_op_op_rsv25 = W_iw_op == 25;
assign W_op_op_rsv26 = W_iw_op == 26;
assign W_op_flushda = W_iw_op == 27;
assign W_op_xori = W_iw_op == 28;
assign W_op_stc = W_iw_op == 29;
assign W_op_bne = W_iw_op == 30;
assign W_op_ldl = W_iw_op == 31;
assign W_op_cmpeqi = W_iw_op == 32;
assign W_op_op_rsv33 = W_iw_op == 33;
assign W_op_op_rsv34 = W_iw_op == 34;
assign W_op_ldbuio = W_iw_op == 35;
assign W_op_muli = W_iw_op == 36;
assign W_op_stbio = W_iw_op == 37;
assign W_op_beq = W_iw_op == 38;
assign W_op_ldbio = W_iw_op == 39;
assign W_op_cmpgeui = W_iw_op == 40;
assign W_op_op_rsv41 = W_iw_op == 41;
assign W_op_op_rsv42 = W_iw_op == 42;
assign W_op_ldhuio = W_iw_op == 43;
assign W_op_andhi = W_iw_op == 44;
assign W_op_sthio = W_iw_op == 45;
assign W_op_bgeu = W_iw_op == 46;
assign W_op_ldhio = W_iw_op == 47;
assign W_op_cmpltui = W_iw_op == 48;
assign W_op_op_rsv49 = W_iw_op == 49;
assign W_op_custom = W_iw_op == 50;
assign W_op_initd = W_iw_op == 51;
assign W_op_orhi = W_iw_op == 52;
assign W_op_stwio = W_iw_op == 53;
assign W_op_bltu = W_iw_op == 54;
assign W_op_ldwio = W_iw_op == 55;
assign W_op_rdprs = W_iw_op == 56;
assign W_op_op_rsv57 = W_iw_op == 57;
assign W_op_flushd = W_iw_op == 59;
assign W_op_xorhi = W_iw_op == 60;
assign W_op_op_rsv61 = W_iw_op == 61;
assign W_op_op_rsv62 = W_iw_op == 62;
assign W_op_op_rsv63 = W_iw_op == 63;
assign W_op_opx_rsv00 = (W_iw_opx == 0) & W_is_opx_inst;
assign W_op_eret = (W_iw_opx == 1) & W_is_opx_inst;
assign W_op_roli = (W_iw_opx == 2) & W_is_opx_inst;
assign W_op_rol = (W_iw_opx == 3) & W_is_opx_inst;
assign W_op_flushp = (W_iw_opx == 4) & W_is_opx_inst;
assign W_op_ret = (W_iw_opx == 5) & W_is_opx_inst;
assign W_op_nor = (W_iw_opx == 6) & W_is_opx_inst;
assign W_op_mulxuu = (W_iw_opx == 7) & W_is_opx_inst;
assign W_op_cmpge = (W_iw_opx == 8) & W_is_opx_inst;
assign W_op_bret = (W_iw_opx == 9) & W_is_opx_inst;
assign W_op_opx_rsv10 = (W_iw_opx == 10) & W_is_opx_inst;
assign W_op_ror = (W_iw_opx == 11) & W_is_opx_inst;
assign W_op_flushi = (W_iw_opx == 12) & W_is_opx_inst;
assign W_op_jmp = (W_iw_opx == 13) & W_is_opx_inst;
assign W_op_and = (W_iw_opx == 14) & W_is_opx_inst;
assign W_op_opx_rsv15 = (W_iw_opx == 15) & W_is_opx_inst;
assign W_op_cmplt = (W_iw_opx == 16) & W_is_opx_inst;
assign W_op_opx_rsv17 = (W_iw_opx == 17) & W_is_opx_inst;
assign W_op_slli = (W_iw_opx == 18) & W_is_opx_inst;
assign W_op_sll = (W_iw_opx == 19) & W_is_opx_inst;
assign W_op_wrprs = (W_iw_opx == 20) & W_is_opx_inst;
assign W_op_opx_rsv21 = (W_iw_opx == 21) & W_is_opx_inst;
assign W_op_or = (W_iw_opx == 22) & W_is_opx_inst;
assign W_op_mulxsu = (W_iw_opx == 23) & W_is_opx_inst;
assign W_op_cmpne = (W_iw_opx == 24) & W_is_opx_inst;
assign W_op_opx_rsv25 = (W_iw_opx == 25) & W_is_opx_inst;
assign W_op_srli = (W_iw_opx == 26) & W_is_opx_inst;
assign W_op_srl = (W_iw_opx == 27) & W_is_opx_inst;
assign W_op_nextpc = (W_iw_opx == 28) & W_is_opx_inst;
assign W_op_callr = (W_iw_opx == 29) & W_is_opx_inst;
assign W_op_xor = (W_iw_opx == 30) & W_is_opx_inst;
assign W_op_mulxss = (W_iw_opx == 31) & W_is_opx_inst;
assign W_op_cmpeq = (W_iw_opx == 32) & W_is_opx_inst;
assign W_op_opx_rsv33 = (W_iw_opx == 33) & W_is_opx_inst;
assign W_op_opx_rsv34 = (W_iw_opx == 34) & W_is_opx_inst;
assign W_op_opx_rsv35 = (W_iw_opx == 35) & W_is_opx_inst;
assign W_op_divu = (W_iw_opx == 36) & W_is_opx_inst;
assign W_op_div = (W_iw_opx == 37) & W_is_opx_inst;
assign W_op_rdctl = (W_iw_opx == 38) & W_is_opx_inst;
assign W_op_mul = (W_iw_opx == 39) & W_is_opx_inst;
assign W_op_cmpgeu = (W_iw_opx == 40) & W_is_opx_inst;
assign W_op_initi = (W_iw_opx == 41) & W_is_opx_inst;
assign W_op_opx_rsv42 = (W_iw_opx == 42) & W_is_opx_inst;
assign W_op_opx_rsv43 = (W_iw_opx == 43) & W_is_opx_inst;
assign W_op_opx_rsv44 = (W_iw_opx == 44) & W_is_opx_inst;
assign W_op_trap = (W_iw_opx == 45) & W_is_opx_inst;
assign W_op_wrctl = (W_iw_opx == 46) & W_is_opx_inst;
assign W_op_opx_rsv47 = (W_iw_opx == 47) & W_is_opx_inst;
assign W_op_cmpltu = (W_iw_opx == 48) & W_is_opx_inst;
assign W_op_add = (W_iw_opx == 49) & W_is_opx_inst;
assign W_op_opx_rsv50 = (W_iw_opx == 50) & W_is_opx_inst;
assign W_op_opx_rsv51 = (W_iw_opx == 51) & W_is_opx_inst;
assign W_op_break = (W_iw_opx == 52) & W_is_opx_inst;
assign W_op_hbreak = (W_iw_opx == 53) & W_is_opx_inst;
assign W_op_sync = (W_iw_opx == 54) & W_is_opx_inst;
assign W_op_opx_rsv55 = (W_iw_opx == 55) & W_is_opx_inst;
assign W_op_opx_rsv56 = (W_iw_opx == 56) & W_is_opx_inst;
assign W_op_sub = (W_iw_opx == 57) & W_is_opx_inst;
assign W_op_srai = (W_iw_opx == 58) & W_is_opx_inst;
assign W_op_sra = (W_iw_opx == 59) & W_is_opx_inst;
assign W_op_opx_rsv60 = (W_iw_opx == 60) & W_is_opx_inst;
assign W_op_intr = (W_iw_opx == 61) & W_is_opx_inst;
assign W_op_crst = (W_iw_opx == 62) & W_is_opx_inst;
assign W_op_opx_rsv63 = (W_iw_opx == 63) & W_is_opx_inst;
assign W_is_opx_inst = W_iw_op == 58;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_target_pcb <= 0;
else if (A_en)
A_target_pcb <= M_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
A_mem_baddr <= 0;
else if (A_en)
A_mem_baddr <= M_mem_baddr;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_wr_data_filtered <= 0;
else
W_wr_data_filtered <= A_wr_data_filtered;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_st_data <= 0;
else
W_st_data <= A_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= A_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_target_pcb <= 0;
else
W_target_pcb <= A_target_pcb;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_hbreak <= 0;
else
W_valid_hbreak <= A_exc_allowed & A_exc_hbreak_pri1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_crst <= 0;
else
W_valid_crst <= A_exc_allowed & 0;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid_intr <= 0;
else
W_valid_intr <= A_exc_allowed & A_exc_norm_intr_pri5;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_any_active <= 0;
else
W_exc_any_active <= A_exc_any_active;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_exc_highest_pri_exc_id <= 0;
else
W_exc_highest_pri_exc_id <= A_exc_highest_pri_exc_id;
end
assign A_iw_invalid = A_exc_inst_fetch & A_exc_active_no_break_no_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_iw_invalid <= 0;
else
W_iw_invalid <= A_iw_invalid;
end
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign A_wr_data_unfiltered_0_is_x = ^(A_wr_data_unfiltered[0]) === 1'bx;
assign A_wr_data_filtered[0] = (A_wr_data_unfiltered_0_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[0];
assign A_wr_data_unfiltered_1_is_x = ^(A_wr_data_unfiltered[1]) === 1'bx;
assign A_wr_data_filtered[1] = (A_wr_data_unfiltered_1_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[1];
assign A_wr_data_unfiltered_2_is_x = ^(A_wr_data_unfiltered[2]) === 1'bx;
assign A_wr_data_filtered[2] = (A_wr_data_unfiltered_2_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[2];
assign A_wr_data_unfiltered_3_is_x = ^(A_wr_data_unfiltered[3]) === 1'bx;
assign A_wr_data_filtered[3] = (A_wr_data_unfiltered_3_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[3];
assign A_wr_data_unfiltered_4_is_x = ^(A_wr_data_unfiltered[4]) === 1'bx;
assign A_wr_data_filtered[4] = (A_wr_data_unfiltered_4_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[4];
assign A_wr_data_unfiltered_5_is_x = ^(A_wr_data_unfiltered[5]) === 1'bx;
assign A_wr_data_filtered[5] = (A_wr_data_unfiltered_5_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[5];
assign A_wr_data_unfiltered_6_is_x = ^(A_wr_data_unfiltered[6]) === 1'bx;
assign A_wr_data_filtered[6] = (A_wr_data_unfiltered_6_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[6];
assign A_wr_data_unfiltered_7_is_x = ^(A_wr_data_unfiltered[7]) === 1'bx;
assign A_wr_data_filtered[7] = (A_wr_data_unfiltered_7_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[7];
assign A_wr_data_unfiltered_8_is_x = ^(A_wr_data_unfiltered[8]) === 1'bx;
assign A_wr_data_filtered[8] = (A_wr_data_unfiltered_8_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[8];
assign A_wr_data_unfiltered_9_is_x = ^(A_wr_data_unfiltered[9]) === 1'bx;
assign A_wr_data_filtered[9] = (A_wr_data_unfiltered_9_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[9];
assign A_wr_data_unfiltered_10_is_x = ^(A_wr_data_unfiltered[10]) === 1'bx;
assign A_wr_data_filtered[10] = (A_wr_data_unfiltered_10_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[10];
assign A_wr_data_unfiltered_11_is_x = ^(A_wr_data_unfiltered[11]) === 1'bx;
assign A_wr_data_filtered[11] = (A_wr_data_unfiltered_11_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[11];
assign A_wr_data_unfiltered_12_is_x = ^(A_wr_data_unfiltered[12]) === 1'bx;
assign A_wr_data_filtered[12] = (A_wr_data_unfiltered_12_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[12];
assign A_wr_data_unfiltered_13_is_x = ^(A_wr_data_unfiltered[13]) === 1'bx;
assign A_wr_data_filtered[13] = (A_wr_data_unfiltered_13_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[13];
assign A_wr_data_unfiltered_14_is_x = ^(A_wr_data_unfiltered[14]) === 1'bx;
assign A_wr_data_filtered[14] = (A_wr_data_unfiltered_14_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[14];
assign A_wr_data_unfiltered_15_is_x = ^(A_wr_data_unfiltered[15]) === 1'bx;
assign A_wr_data_filtered[15] = (A_wr_data_unfiltered_15_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[15];
assign A_wr_data_unfiltered_16_is_x = ^(A_wr_data_unfiltered[16]) === 1'bx;
assign A_wr_data_filtered[16] = (A_wr_data_unfiltered_16_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[16];
assign A_wr_data_unfiltered_17_is_x = ^(A_wr_data_unfiltered[17]) === 1'bx;
assign A_wr_data_filtered[17] = (A_wr_data_unfiltered_17_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[17];
assign A_wr_data_unfiltered_18_is_x = ^(A_wr_data_unfiltered[18]) === 1'bx;
assign A_wr_data_filtered[18] = (A_wr_data_unfiltered_18_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[18];
assign A_wr_data_unfiltered_19_is_x = ^(A_wr_data_unfiltered[19]) === 1'bx;
assign A_wr_data_filtered[19] = (A_wr_data_unfiltered_19_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[19];
assign A_wr_data_unfiltered_20_is_x = ^(A_wr_data_unfiltered[20]) === 1'bx;
assign A_wr_data_filtered[20] = (A_wr_data_unfiltered_20_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[20];
assign A_wr_data_unfiltered_21_is_x = ^(A_wr_data_unfiltered[21]) === 1'bx;
assign A_wr_data_filtered[21] = (A_wr_data_unfiltered_21_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[21];
assign A_wr_data_unfiltered_22_is_x = ^(A_wr_data_unfiltered[22]) === 1'bx;
assign A_wr_data_filtered[22] = (A_wr_data_unfiltered_22_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[22];
assign A_wr_data_unfiltered_23_is_x = ^(A_wr_data_unfiltered[23]) === 1'bx;
assign A_wr_data_filtered[23] = (A_wr_data_unfiltered_23_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[23];
assign A_wr_data_unfiltered_24_is_x = ^(A_wr_data_unfiltered[24]) === 1'bx;
assign A_wr_data_filtered[24] = (A_wr_data_unfiltered_24_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[24];
assign A_wr_data_unfiltered_25_is_x = ^(A_wr_data_unfiltered[25]) === 1'bx;
assign A_wr_data_filtered[25] = (A_wr_data_unfiltered_25_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[25];
assign A_wr_data_unfiltered_26_is_x = ^(A_wr_data_unfiltered[26]) === 1'bx;
assign A_wr_data_filtered[26] = (A_wr_data_unfiltered_26_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[26];
assign A_wr_data_unfiltered_27_is_x = ^(A_wr_data_unfiltered[27]) === 1'bx;
assign A_wr_data_filtered[27] = (A_wr_data_unfiltered_27_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[27];
assign A_wr_data_unfiltered_28_is_x = ^(A_wr_data_unfiltered[28]) === 1'bx;
assign A_wr_data_filtered[28] = (A_wr_data_unfiltered_28_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[28];
assign A_wr_data_unfiltered_29_is_x = ^(A_wr_data_unfiltered[29]) === 1'bx;
assign A_wr_data_filtered[29] = (A_wr_data_unfiltered_29_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[29];
assign A_wr_data_unfiltered_30_is_x = ^(A_wr_data_unfiltered[30]) === 1'bx;
assign A_wr_data_filtered[30] = (A_wr_data_unfiltered_30_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[30];
assign A_wr_data_unfiltered_31_is_x = ^(A_wr_data_unfiltered[31]) === 1'bx;
assign A_wr_data_filtered[31] = (A_wr_data_unfiltered_31_is_x & (A_ctrl_ld_non_bypass)) ? 1'b0 : A_wr_data_unfiltered[31];
//Clearing 'X' data bits
assign E_add_br_to_taken_history_unfiltered_is_x = ^(E_add_br_to_taken_history_unfiltered) === 1'bx;
assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered_is_x ? 1'b0 : E_add_br_to_taken_history_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_en_unfiltered_is_x = ^(M_bht_wr_en_unfiltered) === 1'bx;
assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered_is_x ? 1'b0 : M_bht_wr_en_unfiltered;
//Clearing 'X' data bits
assign M_bht_wr_data_unfiltered_0_is_x = ^(M_bht_wr_data_unfiltered[0]) === 1'bx;
assign M_bht_wr_data_filtered[0] = M_bht_wr_data_unfiltered_0_is_x ? 1'b0 : M_bht_wr_data_unfiltered[0];
assign M_bht_wr_data_unfiltered_1_is_x = ^(M_bht_wr_data_unfiltered[1]) === 1'bx;
assign M_bht_wr_data_filtered[1] = M_bht_wr_data_unfiltered_1_is_x ? 1'b0 : M_bht_wr_data_unfiltered[1];
//Clearing 'X' data bits
assign M_bht_ptr_unfiltered_0_is_x = ^(M_bht_ptr_unfiltered[0]) === 1'bx;
assign M_bht_ptr_filtered[0] = M_bht_ptr_unfiltered_0_is_x ? 1'b0 : M_bht_ptr_unfiltered[0];
assign M_bht_ptr_unfiltered_1_is_x = ^(M_bht_ptr_unfiltered[1]) === 1'bx;
assign M_bht_ptr_filtered[1] = M_bht_ptr_unfiltered_1_is_x ? 1'b0 : M_bht_ptr_unfiltered[1];
assign M_bht_ptr_unfiltered_2_is_x = ^(M_bht_ptr_unfiltered[2]) === 1'bx;
assign M_bht_ptr_filtered[2] = M_bht_ptr_unfiltered_2_is_x ? 1'b0 : M_bht_ptr_unfiltered[2];
assign M_bht_ptr_unfiltered_3_is_x = ^(M_bht_ptr_unfiltered[3]) === 1'bx;
assign M_bht_ptr_filtered[3] = M_bht_ptr_unfiltered_3_is_x ? 1'b0 : M_bht_ptr_unfiltered[3];
assign M_bht_ptr_unfiltered_4_is_x = ^(M_bht_ptr_unfiltered[4]) === 1'bx;
assign M_bht_ptr_filtered[4] = M_bht_ptr_unfiltered_4_is_x ? 1'b0 : M_bht_ptr_unfiltered[4];
assign M_bht_ptr_unfiltered_5_is_x = ^(M_bht_ptr_unfiltered[5]) === 1'bx;
assign M_bht_ptr_filtered[5] = M_bht_ptr_unfiltered_5_is_x ? 1'b0 : M_bht_ptr_unfiltered[5];
assign M_bht_ptr_unfiltered_6_is_x = ^(M_bht_ptr_unfiltered[6]) === 1'bx;
assign M_bht_ptr_filtered[6] = M_bht_ptr_unfiltered_6_is_x ? 1'b0 : M_bht_ptr_unfiltered[6];
assign M_bht_ptr_unfiltered_7_is_x = ^(M_bht_ptr_unfiltered[7]) === 1'bx;
assign M_bht_ptr_filtered[7] = M_bht_ptr_unfiltered_7_is_x ? 1'b0 : M_bht_ptr_unfiltered[7];
always @(posedge clk)
begin
if (reset_n)
if (^(W_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_wr_dst_reg)
if (^(W_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_pcb) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_pcb is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(W_iw) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_iw is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_en) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/A_en is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(M_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/M_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_valid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/A_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (A_valid & A_en & A_wr_dst_reg)
if (^(A_wr_data_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: soc_design_niosII_core_cpu_test_bench/A_wr_data_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_status_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_status_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_estatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_estatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_bstatus_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_bstatus_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_exception_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_exception_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_badaddr_reg) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/W_badaddr_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(A_exc_any_active) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/A_exc_any_active is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/i_readdatavalid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_readdatavalid) === 1'bx)
begin
$write("%0d ns: ERROR: soc_design_niosII_core_cpu_test_bench/d_readdatavalid is 'x'\n", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign A_wr_data_filtered = A_wr_data_unfiltered;
//
//
// assign E_add_br_to_taken_history_filtered = E_add_br_to_taken_history_unfiltered;
//
//
// assign M_bht_wr_en_filtered = M_bht_wr_en_unfiltered;
//
//
// assign M_bht_wr_data_filtered = M_bht_wr_data_unfiltered;
//
//
// assign M_bht_ptr_filtered = M_bht_ptr_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
// Copyright (c) 2002 Michael Ruff (mruff at chiaro.com)
// Michael Runyan (mrunyan at chiaro.com)
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
module test;
reg [5:0] addr;
reg [75:0] m_poke[4:0];
reg [75:0] m_peek[4:0];
task f_copy_for_buggy_eda_vendor;
integer i;
reg [75:0] tmp;
begin
for (i = 0; i < 5; i = i + 1) begin
tmp = m_poke[i];
m_peek[i] = tmp;
end
end
endtask
task f_copy;
integer i;
begin
for (i = 0; i < 5; i = i + 1) begin
m_peek[i] = m_poke[i];
end
end
endtask
task f_dump;
integer i;
begin
for (i = 0; i < 5; i = i + 1) begin
$display ("%0d: m_poke <=> m_peek, 0x%x <=> 0x%x%s",
i, m_poke[i], m_peek[i],
m_poke[i] !== m_peek[i] ? " - ERROR" : "");
end
end
endtask
initial begin
#0;
$mempoke;
#10;
f_copy;
//f_copy_buggy_eda_vendor;
#10;
$mempeek;
#10;
f_dump;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 100G MAC Block
// /___/ /\ Filename : CMAC.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module CMAC #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CTL_PTP_TRANSPCLK_MODE = "FALSE",
parameter CTL_RX_CHECK_ACK = "TRUE",
parameter CTL_RX_CHECK_PREAMBLE = "FALSE",
parameter CTL_RX_CHECK_SFD = "FALSE",
parameter CTL_RX_DELETE_FCS = "TRUE",
parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808,
parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808,
parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808,
parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808,
parameter CTL_RX_FORWARD_CONTROL = "FALSE",
parameter CTL_RX_IGNORE_FCS = "FALSE",
parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580,
parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40,
parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001,
parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF,
parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF,
parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000,
parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000,
parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001,
parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001,
parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000,
parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000,
parameter CTL_RX_PROCESS_LFI = "FALSE",
parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF,
parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00,
parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100,
parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600,
parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00,
parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00,
parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200,
parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500,
parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200,
parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300,
parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800,
parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500,
parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00,
parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700,
parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400,
parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600,
parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00,
parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900,
parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900,
parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900,
parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400,
parameter CTL_TEST_MODE_PIN_CHAR = "FALSE",
parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001,
parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001,
parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808,
parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808,
parameter CTL_TX_FCS_INS_ENABLE = "TRUE",
parameter CTL_TX_IGNORE_FCS = "FALSE",
parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001,
parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001,
parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE",
parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1,
parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000,
parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000,
parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF,
parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00,
parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100,
parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600,
parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00,
parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00,
parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200,
parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500,
parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200,
parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300,
parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800,
parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500,
parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00,
parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700,
parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400,
parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600,
parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00,
parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900,
parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900,
parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900,
parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400,
parameter TEST_MODE_PIN_CHAR = "FALSE"
)(
output [15:0] DRP_DO,
output DRP_RDY,
output [127:0] RX_DATAOUT0,
output [127:0] RX_DATAOUT1,
output [127:0] RX_DATAOUT2,
output [127:0] RX_DATAOUT3,
output RX_ENAOUT0,
output RX_ENAOUT1,
output RX_ENAOUT2,
output RX_ENAOUT3,
output RX_EOPOUT0,
output RX_EOPOUT1,
output RX_EOPOUT2,
output RX_EOPOUT3,
output RX_ERROUT0,
output RX_ERROUT1,
output RX_ERROUT2,
output RX_ERROUT3,
output [6:0] RX_LANE_ALIGNER_FILL_0,
output [6:0] RX_LANE_ALIGNER_FILL_1,
output [6:0] RX_LANE_ALIGNER_FILL_10,
output [6:0] RX_LANE_ALIGNER_FILL_11,
output [6:0] RX_LANE_ALIGNER_FILL_12,
output [6:0] RX_LANE_ALIGNER_FILL_13,
output [6:0] RX_LANE_ALIGNER_FILL_14,
output [6:0] RX_LANE_ALIGNER_FILL_15,
output [6:0] RX_LANE_ALIGNER_FILL_16,
output [6:0] RX_LANE_ALIGNER_FILL_17,
output [6:0] RX_LANE_ALIGNER_FILL_18,
output [6:0] RX_LANE_ALIGNER_FILL_19,
output [6:0] RX_LANE_ALIGNER_FILL_2,
output [6:0] RX_LANE_ALIGNER_FILL_3,
output [6:0] RX_LANE_ALIGNER_FILL_4,
output [6:0] RX_LANE_ALIGNER_FILL_5,
output [6:0] RX_LANE_ALIGNER_FILL_6,
output [6:0] RX_LANE_ALIGNER_FILL_7,
output [6:0] RX_LANE_ALIGNER_FILL_8,
output [6:0] RX_LANE_ALIGNER_FILL_9,
output [3:0] RX_MTYOUT0,
output [3:0] RX_MTYOUT1,
output [3:0] RX_MTYOUT2,
output [3:0] RX_MTYOUT3,
output [4:0] RX_PTP_PCSLANE_OUT,
output [79:0] RX_PTP_TSTAMP_OUT,
output RX_SOPOUT0,
output RX_SOPOUT1,
output RX_SOPOUT2,
output RX_SOPOUT3,
output STAT_RX_ALIGNED,
output STAT_RX_ALIGNED_ERR,
output [6:0] STAT_RX_BAD_CODE,
output [3:0] STAT_RX_BAD_FCS,
output STAT_RX_BAD_PREAMBLE,
output STAT_RX_BAD_SFD,
output STAT_RX_BIP_ERR_0,
output STAT_RX_BIP_ERR_1,
output STAT_RX_BIP_ERR_10,
output STAT_RX_BIP_ERR_11,
output STAT_RX_BIP_ERR_12,
output STAT_RX_BIP_ERR_13,
output STAT_RX_BIP_ERR_14,
output STAT_RX_BIP_ERR_15,
output STAT_RX_BIP_ERR_16,
output STAT_RX_BIP_ERR_17,
output STAT_RX_BIP_ERR_18,
output STAT_RX_BIP_ERR_19,
output STAT_RX_BIP_ERR_2,
output STAT_RX_BIP_ERR_3,
output STAT_RX_BIP_ERR_4,
output STAT_RX_BIP_ERR_5,
output STAT_RX_BIP_ERR_6,
output STAT_RX_BIP_ERR_7,
output STAT_RX_BIP_ERR_8,
output STAT_RX_BIP_ERR_9,
output [19:0] STAT_RX_BLOCK_LOCK,
output STAT_RX_BROADCAST,
output [3:0] STAT_RX_FRAGMENT,
output [3:0] STAT_RX_FRAMING_ERR_0,
output [3:0] STAT_RX_FRAMING_ERR_1,
output [3:0] STAT_RX_FRAMING_ERR_10,
output [3:0] STAT_RX_FRAMING_ERR_11,
output [3:0] STAT_RX_FRAMING_ERR_12,
output [3:0] STAT_RX_FRAMING_ERR_13,
output [3:0] STAT_RX_FRAMING_ERR_14,
output [3:0] STAT_RX_FRAMING_ERR_15,
output [3:0] STAT_RX_FRAMING_ERR_16,
output [3:0] STAT_RX_FRAMING_ERR_17,
output [3:0] STAT_RX_FRAMING_ERR_18,
output [3:0] STAT_RX_FRAMING_ERR_19,
output [3:0] STAT_RX_FRAMING_ERR_2,
output [3:0] STAT_RX_FRAMING_ERR_3,
output [3:0] STAT_RX_FRAMING_ERR_4,
output [3:0] STAT_RX_FRAMING_ERR_5,
output [3:0] STAT_RX_FRAMING_ERR_6,
output [3:0] STAT_RX_FRAMING_ERR_7,
output [3:0] STAT_RX_FRAMING_ERR_8,
output [3:0] STAT_RX_FRAMING_ERR_9,
output STAT_RX_FRAMING_ERR_VALID_0,
output STAT_RX_FRAMING_ERR_VALID_1,
output STAT_RX_FRAMING_ERR_VALID_10,
output STAT_RX_FRAMING_ERR_VALID_11,
output STAT_RX_FRAMING_ERR_VALID_12,
output STAT_RX_FRAMING_ERR_VALID_13,
output STAT_RX_FRAMING_ERR_VALID_14,
output STAT_RX_FRAMING_ERR_VALID_15,
output STAT_RX_FRAMING_ERR_VALID_16,
output STAT_RX_FRAMING_ERR_VALID_17,
output STAT_RX_FRAMING_ERR_VALID_18,
output STAT_RX_FRAMING_ERR_VALID_19,
output STAT_RX_FRAMING_ERR_VALID_2,
output STAT_RX_FRAMING_ERR_VALID_3,
output STAT_RX_FRAMING_ERR_VALID_4,
output STAT_RX_FRAMING_ERR_VALID_5,
output STAT_RX_FRAMING_ERR_VALID_6,
output STAT_RX_FRAMING_ERR_VALID_7,
output STAT_RX_FRAMING_ERR_VALID_8,
output STAT_RX_FRAMING_ERR_VALID_9,
output STAT_RX_GOT_SIGNAL_OS,
output STAT_RX_HI_BER,
output STAT_RX_INRANGEERR,
output STAT_RX_INTERNAL_LOCAL_FAULT,
output STAT_RX_JABBER,
output [7:0] STAT_RX_LANE0_VLM_BIP7,
output STAT_RX_LANE0_VLM_BIP7_VALID,
output STAT_RX_LOCAL_FAULT,
output [19:0] STAT_RX_MF_ERR,
output [19:0] STAT_RX_MF_LEN_ERR,
output [19:0] STAT_RX_MF_REPEAT_ERR,
output STAT_RX_MISALIGNED,
output STAT_RX_MULTICAST,
output STAT_RX_OVERSIZE,
output STAT_RX_PACKET_1024_1518_BYTES,
output STAT_RX_PACKET_128_255_BYTES,
output STAT_RX_PACKET_1519_1522_BYTES,
output STAT_RX_PACKET_1523_1548_BYTES,
output STAT_RX_PACKET_1549_2047_BYTES,
output STAT_RX_PACKET_2048_4095_BYTES,
output STAT_RX_PACKET_256_511_BYTES,
output STAT_RX_PACKET_4096_8191_BYTES,
output STAT_RX_PACKET_512_1023_BYTES,
output STAT_RX_PACKET_64_BYTES,
output STAT_RX_PACKET_65_127_BYTES,
output STAT_RX_PACKET_8192_9215_BYTES,
output STAT_RX_PACKET_BAD_FCS,
output STAT_RX_PACKET_LARGE,
output [3:0] STAT_RX_PACKET_SMALL,
output STAT_RX_PAUSE,
output [15:0] STAT_RX_PAUSE_QUANTA0,
output [15:0] STAT_RX_PAUSE_QUANTA1,
output [15:0] STAT_RX_PAUSE_QUANTA2,
output [15:0] STAT_RX_PAUSE_QUANTA3,
output [15:0] STAT_RX_PAUSE_QUANTA4,
output [15:0] STAT_RX_PAUSE_QUANTA5,
output [15:0] STAT_RX_PAUSE_QUANTA6,
output [15:0] STAT_RX_PAUSE_QUANTA7,
output [15:0] STAT_RX_PAUSE_QUANTA8,
output [8:0] STAT_RX_PAUSE_REQ,
output [8:0] STAT_RX_PAUSE_VALID,
output STAT_RX_RECEIVED_LOCAL_FAULT,
output STAT_RX_REMOTE_FAULT,
output STAT_RX_STATUS,
output [3:0] STAT_RX_STOMPED_FCS,
output [19:0] STAT_RX_SYNCED,
output [19:0] STAT_RX_SYNCED_ERR,
output [2:0] STAT_RX_TEST_PATTERN_MISMATCH,
output STAT_RX_TOOLONG,
output [7:0] STAT_RX_TOTAL_BYTES,
output [13:0] STAT_RX_TOTAL_GOOD_BYTES,
output STAT_RX_TOTAL_GOOD_PACKETS,
output [3:0] STAT_RX_TOTAL_PACKETS,
output STAT_RX_TRUNCATED,
output [3:0] STAT_RX_UNDERSIZE,
output STAT_RX_UNICAST,
output STAT_RX_USER_PAUSE,
output STAT_RX_VLAN,
output [19:0] STAT_RX_VL_DEMUXED,
output [4:0] STAT_RX_VL_NUMBER_0,
output [4:0] STAT_RX_VL_NUMBER_1,
output [4:0] STAT_RX_VL_NUMBER_10,
output [4:0] STAT_RX_VL_NUMBER_11,
output [4:0] STAT_RX_VL_NUMBER_12,
output [4:0] STAT_RX_VL_NUMBER_13,
output [4:0] STAT_RX_VL_NUMBER_14,
output [4:0] STAT_RX_VL_NUMBER_15,
output [4:0] STAT_RX_VL_NUMBER_16,
output [4:0] STAT_RX_VL_NUMBER_17,
output [4:0] STAT_RX_VL_NUMBER_18,
output [4:0] STAT_RX_VL_NUMBER_19,
output [4:0] STAT_RX_VL_NUMBER_2,
output [4:0] STAT_RX_VL_NUMBER_3,
output [4:0] STAT_RX_VL_NUMBER_4,
output [4:0] STAT_RX_VL_NUMBER_5,
output [4:0] STAT_RX_VL_NUMBER_6,
output [4:0] STAT_RX_VL_NUMBER_7,
output [4:0] STAT_RX_VL_NUMBER_8,
output [4:0] STAT_RX_VL_NUMBER_9,
output STAT_TX_BAD_FCS,
output STAT_TX_BROADCAST,
output STAT_TX_FRAME_ERROR,
output STAT_TX_LOCAL_FAULT,
output STAT_TX_MULTICAST,
output STAT_TX_PACKET_1024_1518_BYTES,
output STAT_TX_PACKET_128_255_BYTES,
output STAT_TX_PACKET_1519_1522_BYTES,
output STAT_TX_PACKET_1523_1548_BYTES,
output STAT_TX_PACKET_1549_2047_BYTES,
output STAT_TX_PACKET_2048_4095_BYTES,
output STAT_TX_PACKET_256_511_BYTES,
output STAT_TX_PACKET_4096_8191_BYTES,
output STAT_TX_PACKET_512_1023_BYTES,
output STAT_TX_PACKET_64_BYTES,
output STAT_TX_PACKET_65_127_BYTES,
output STAT_TX_PACKET_8192_9215_BYTES,
output STAT_TX_PACKET_LARGE,
output STAT_TX_PACKET_SMALL,
output STAT_TX_PAUSE,
output [8:0] STAT_TX_PAUSE_VALID,
output STAT_TX_PTP_FIFO_READ_ERROR,
output STAT_TX_PTP_FIFO_WRITE_ERROR,
output [6:0] STAT_TX_TOTAL_BYTES,
output [13:0] STAT_TX_TOTAL_GOOD_BYTES,
output STAT_TX_TOTAL_GOOD_PACKETS,
output STAT_TX_TOTAL_PACKETS,
output STAT_TX_UNICAST,
output STAT_TX_USER_PAUSE,
output STAT_TX_VLAN,
output TX_OVFOUT,
output [4:0] TX_PTP_PCSLANE_OUT,
output [79:0] TX_PTP_TSTAMP_OUT,
output [15:0] TX_PTP_TSTAMP_TAG_OUT,
output TX_PTP_TSTAMP_VALID_OUT,
output TX_RDYOUT,
output [15:0] TX_SERDES_ALT_DATA0,
output [15:0] TX_SERDES_ALT_DATA1,
output [15:0] TX_SERDES_ALT_DATA2,
output [15:0] TX_SERDES_ALT_DATA3,
output [63:0] TX_SERDES_DATA0,
output [63:0] TX_SERDES_DATA1,
output [63:0] TX_SERDES_DATA2,
output [63:0] TX_SERDES_DATA3,
output [31:0] TX_SERDES_DATA4,
output [31:0] TX_SERDES_DATA5,
output [31:0] TX_SERDES_DATA6,
output [31:0] TX_SERDES_DATA7,
output [31:0] TX_SERDES_DATA8,
output [31:0] TX_SERDES_DATA9,
output TX_UNFOUT,
input CTL_CAUI4_MODE,
input CTL_RX_CHECK_ETYPE_GCP,
input CTL_RX_CHECK_ETYPE_GPP,
input CTL_RX_CHECK_ETYPE_PCP,
input CTL_RX_CHECK_ETYPE_PPP,
input CTL_RX_CHECK_MCAST_GCP,
input CTL_RX_CHECK_MCAST_GPP,
input CTL_RX_CHECK_MCAST_PCP,
input CTL_RX_CHECK_MCAST_PPP,
input CTL_RX_CHECK_OPCODE_GCP,
input CTL_RX_CHECK_OPCODE_GPP,
input CTL_RX_CHECK_OPCODE_PCP,
input CTL_RX_CHECK_OPCODE_PPP,
input CTL_RX_CHECK_SA_GCP,
input CTL_RX_CHECK_SA_GPP,
input CTL_RX_CHECK_SA_PCP,
input CTL_RX_CHECK_SA_PPP,
input CTL_RX_CHECK_UCAST_GCP,
input CTL_RX_CHECK_UCAST_GPP,
input CTL_RX_CHECK_UCAST_PCP,
input CTL_RX_CHECK_UCAST_PPP,
input CTL_RX_ENABLE,
input CTL_RX_ENABLE_GCP,
input CTL_RX_ENABLE_GPP,
input CTL_RX_ENABLE_PCP,
input CTL_RX_ENABLE_PPP,
input CTL_RX_FORCE_RESYNC,
input [8:0] CTL_RX_PAUSE_ACK,
input [8:0] CTL_RX_PAUSE_ENABLE,
input [79:0] CTL_RX_SYSTEMTIMERIN,
input CTL_RX_TEST_PATTERN,
input CTL_TX_ENABLE,
input CTL_TX_LANE0_VLM_BIP7_OVERRIDE,
input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE,
input [8:0] CTL_TX_PAUSE_ENABLE,
input [15:0] CTL_TX_PAUSE_QUANTA0,
input [15:0] CTL_TX_PAUSE_QUANTA1,
input [15:0] CTL_TX_PAUSE_QUANTA2,
input [15:0] CTL_TX_PAUSE_QUANTA3,
input [15:0] CTL_TX_PAUSE_QUANTA4,
input [15:0] CTL_TX_PAUSE_QUANTA5,
input [15:0] CTL_TX_PAUSE_QUANTA6,
input [15:0] CTL_TX_PAUSE_QUANTA7,
input [15:0] CTL_TX_PAUSE_QUANTA8,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7,
input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8,
input [8:0] CTL_TX_PAUSE_REQ,
input CTL_TX_PTP_VLANE_ADJUST_MODE,
input CTL_TX_RESEND_PAUSE,
input CTL_TX_SEND_IDLE,
input CTL_TX_SEND_RFI,
input [79:0] CTL_TX_SYSTEMTIMERIN,
input CTL_TX_TEST_PATTERN,
input [9:0] DRP_ADDR,
input DRP_CLK,
input [15:0] DRP_DI,
input DRP_EN,
input DRP_WE,
input RX_CLK,
input RX_RESET,
input [15:0] RX_SERDES_ALT_DATA0,
input [15:0] RX_SERDES_ALT_DATA1,
input [15:0] RX_SERDES_ALT_DATA2,
input [15:0] RX_SERDES_ALT_DATA3,
input [9:0] RX_SERDES_CLK,
input [63:0] RX_SERDES_DATA0,
input [63:0] RX_SERDES_DATA1,
input [63:0] RX_SERDES_DATA2,
input [63:0] RX_SERDES_DATA3,
input [31:0] RX_SERDES_DATA4,
input [31:0] RX_SERDES_DATA5,
input [31:0] RX_SERDES_DATA6,
input [31:0] RX_SERDES_DATA7,
input [31:0] RX_SERDES_DATA8,
input [31:0] RX_SERDES_DATA9,
input [9:0] RX_SERDES_RESET,
input TX_CLK,
input [127:0] TX_DATAIN0,
input [127:0] TX_DATAIN1,
input [127:0] TX_DATAIN2,
input [127:0] TX_DATAIN3,
input TX_ENAIN0,
input TX_ENAIN1,
input TX_ENAIN2,
input TX_ENAIN3,
input TX_EOPIN0,
input TX_EOPIN1,
input TX_EOPIN2,
input TX_EOPIN3,
input TX_ERRIN0,
input TX_ERRIN1,
input TX_ERRIN2,
input TX_ERRIN3,
input [3:0] TX_MTYIN0,
input [3:0] TX_MTYIN1,
input [3:0] TX_MTYIN2,
input [3:0] TX_MTYIN3,
input [1:0] TX_PTP_1588OP_IN,
input [15:0] TX_PTP_CHKSUM_OFFSET_IN,
input [63:0] TX_PTP_RXTSTAMP_IN,
input [15:0] TX_PTP_TAG_FIELD_IN,
input [15:0] TX_PTP_TSTAMP_OFFSET_IN,
input TX_PTP_UPD_CHKSUM_IN,
input TX_RESET,
input TX_SOPIN0,
input TX_SOPIN1,
input TX_SOPIN2,
input TX_SOPIN3
);
// define constants
localparam MODULE_NAME = "CMAC";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "CMAC_dr.v"
`else
localparam [40:1] CTL_PTP_TRANSPCLK_MODE_REG = CTL_PTP_TRANSPCLK_MODE;
localparam [40:1] CTL_RX_CHECK_ACK_REG = CTL_RX_CHECK_ACK;
localparam [40:1] CTL_RX_CHECK_PREAMBLE_REG = CTL_RX_CHECK_PREAMBLE;
localparam [40:1] CTL_RX_CHECK_SFD_REG = CTL_RX_CHECK_SFD;
localparam [40:1] CTL_RX_DELETE_FCS_REG = CTL_RX_DELETE_FCS;
localparam [15:0] CTL_RX_ETYPE_GCP_REG = CTL_RX_ETYPE_GCP;
localparam [15:0] CTL_RX_ETYPE_GPP_REG = CTL_RX_ETYPE_GPP;
localparam [15:0] CTL_RX_ETYPE_PCP_REG = CTL_RX_ETYPE_PCP;
localparam [15:0] CTL_RX_ETYPE_PPP_REG = CTL_RX_ETYPE_PPP;
localparam [40:1] CTL_RX_FORWARD_CONTROL_REG = CTL_RX_FORWARD_CONTROL;
localparam [40:1] CTL_RX_IGNORE_FCS_REG = CTL_RX_IGNORE_FCS;
localparam [14:0] CTL_RX_MAX_PACKET_LEN_REG = CTL_RX_MAX_PACKET_LEN;
localparam [7:0] CTL_RX_MIN_PACKET_LEN_REG = CTL_RX_MIN_PACKET_LEN;
localparam [15:0] CTL_RX_OPCODE_GPP_REG = CTL_RX_OPCODE_GPP;
localparam [15:0] CTL_RX_OPCODE_MAX_GCP_REG = CTL_RX_OPCODE_MAX_GCP;
localparam [15:0] CTL_RX_OPCODE_MAX_PCP_REG = CTL_RX_OPCODE_MAX_PCP;
localparam [15:0] CTL_RX_OPCODE_MIN_GCP_REG = CTL_RX_OPCODE_MIN_GCP;
localparam [15:0] CTL_RX_OPCODE_MIN_PCP_REG = CTL_RX_OPCODE_MIN_PCP;
localparam [15:0] CTL_RX_OPCODE_PPP_REG = CTL_RX_OPCODE_PPP;
localparam [47:0] CTL_RX_PAUSE_DA_MCAST_REG = CTL_RX_PAUSE_DA_MCAST;
localparam [47:0] CTL_RX_PAUSE_DA_UCAST_REG = CTL_RX_PAUSE_DA_UCAST;
localparam [47:0] CTL_RX_PAUSE_SA_REG = CTL_RX_PAUSE_SA;
localparam [40:1] CTL_RX_PROCESS_LFI_REG = CTL_RX_PROCESS_LFI;
localparam [15:0] CTL_RX_VL_LENGTH_MINUS1_REG = CTL_RX_VL_LENGTH_MINUS1;
localparam [63:0] CTL_RX_VL_MARKER_ID0_REG = CTL_RX_VL_MARKER_ID0;
localparam [63:0] CTL_RX_VL_MARKER_ID1_REG = CTL_RX_VL_MARKER_ID1;
localparam [63:0] CTL_RX_VL_MARKER_ID10_REG = CTL_RX_VL_MARKER_ID10;
localparam [63:0] CTL_RX_VL_MARKER_ID11_REG = CTL_RX_VL_MARKER_ID11;
localparam [63:0] CTL_RX_VL_MARKER_ID12_REG = CTL_RX_VL_MARKER_ID12;
localparam [63:0] CTL_RX_VL_MARKER_ID13_REG = CTL_RX_VL_MARKER_ID13;
localparam [63:0] CTL_RX_VL_MARKER_ID14_REG = CTL_RX_VL_MARKER_ID14;
localparam [63:0] CTL_RX_VL_MARKER_ID15_REG = CTL_RX_VL_MARKER_ID15;
localparam [63:0] CTL_RX_VL_MARKER_ID16_REG = CTL_RX_VL_MARKER_ID16;
localparam [63:0] CTL_RX_VL_MARKER_ID17_REG = CTL_RX_VL_MARKER_ID17;
localparam [63:0] CTL_RX_VL_MARKER_ID18_REG = CTL_RX_VL_MARKER_ID18;
localparam [63:0] CTL_RX_VL_MARKER_ID19_REG = CTL_RX_VL_MARKER_ID19;
localparam [63:0] CTL_RX_VL_MARKER_ID2_REG = CTL_RX_VL_MARKER_ID2;
localparam [63:0] CTL_RX_VL_MARKER_ID3_REG = CTL_RX_VL_MARKER_ID3;
localparam [63:0] CTL_RX_VL_MARKER_ID4_REG = CTL_RX_VL_MARKER_ID4;
localparam [63:0] CTL_RX_VL_MARKER_ID5_REG = CTL_RX_VL_MARKER_ID5;
localparam [63:0] CTL_RX_VL_MARKER_ID6_REG = CTL_RX_VL_MARKER_ID6;
localparam [63:0] CTL_RX_VL_MARKER_ID7_REG = CTL_RX_VL_MARKER_ID7;
localparam [63:0] CTL_RX_VL_MARKER_ID8_REG = CTL_RX_VL_MARKER_ID8;
localparam [63:0] CTL_RX_VL_MARKER_ID9_REG = CTL_RX_VL_MARKER_ID9;
localparam [40:1] CTL_TEST_MODE_PIN_CHAR_REG = CTL_TEST_MODE_PIN_CHAR;
localparam [47:0] CTL_TX_DA_GPP_REG = CTL_TX_DA_GPP;
localparam [47:0] CTL_TX_DA_PPP_REG = CTL_TX_DA_PPP;
localparam [15:0] CTL_TX_ETHERTYPE_GPP_REG = CTL_TX_ETHERTYPE_GPP;
localparam [15:0] CTL_TX_ETHERTYPE_PPP_REG = CTL_TX_ETHERTYPE_PPP;
localparam [40:1] CTL_TX_FCS_INS_ENABLE_REG = CTL_TX_FCS_INS_ENABLE;
localparam [40:1] CTL_TX_IGNORE_FCS_REG = CTL_TX_IGNORE_FCS;
localparam [15:0] CTL_TX_OPCODE_GPP_REG = CTL_TX_OPCODE_GPP;
localparam [15:0] CTL_TX_OPCODE_PPP_REG = CTL_TX_OPCODE_PPP;
localparam [40:1] CTL_TX_PTP_1STEP_ENABLE_REG = CTL_TX_PTP_1STEP_ENABLE;
localparam [10:0] CTL_TX_PTP_LATENCY_ADJUST_REG = CTL_TX_PTP_LATENCY_ADJUST;
localparam [47:0] CTL_TX_SA_GPP_REG = CTL_TX_SA_GPP;
localparam [47:0] CTL_TX_SA_PPP_REG = CTL_TX_SA_PPP;
localparam [15:0] CTL_TX_VL_LENGTH_MINUS1_REG = CTL_TX_VL_LENGTH_MINUS1;
localparam [63:0] CTL_TX_VL_MARKER_ID0_REG = CTL_TX_VL_MARKER_ID0;
localparam [63:0] CTL_TX_VL_MARKER_ID1_REG = CTL_TX_VL_MARKER_ID1;
localparam [63:0] CTL_TX_VL_MARKER_ID10_REG = CTL_TX_VL_MARKER_ID10;
localparam [63:0] CTL_TX_VL_MARKER_ID11_REG = CTL_TX_VL_MARKER_ID11;
localparam [63:0] CTL_TX_VL_MARKER_ID12_REG = CTL_TX_VL_MARKER_ID12;
localparam [63:0] CTL_TX_VL_MARKER_ID13_REG = CTL_TX_VL_MARKER_ID13;
localparam [63:0] CTL_TX_VL_MARKER_ID14_REG = CTL_TX_VL_MARKER_ID14;
localparam [63:0] CTL_TX_VL_MARKER_ID15_REG = CTL_TX_VL_MARKER_ID15;
localparam [63:0] CTL_TX_VL_MARKER_ID16_REG = CTL_TX_VL_MARKER_ID16;
localparam [63:0] CTL_TX_VL_MARKER_ID17_REG = CTL_TX_VL_MARKER_ID17;
localparam [63:0] CTL_TX_VL_MARKER_ID18_REG = CTL_TX_VL_MARKER_ID18;
localparam [63:0] CTL_TX_VL_MARKER_ID19_REG = CTL_TX_VL_MARKER_ID19;
localparam [63:0] CTL_TX_VL_MARKER_ID2_REG = CTL_TX_VL_MARKER_ID2;
localparam [63:0] CTL_TX_VL_MARKER_ID3_REG = CTL_TX_VL_MARKER_ID3;
localparam [63:0] CTL_TX_VL_MARKER_ID4_REG = CTL_TX_VL_MARKER_ID4;
localparam [63:0] CTL_TX_VL_MARKER_ID5_REG = CTL_TX_VL_MARKER_ID5;
localparam [63:0] CTL_TX_VL_MARKER_ID6_REG = CTL_TX_VL_MARKER_ID6;
localparam [63:0] CTL_TX_VL_MARKER_ID7_REG = CTL_TX_VL_MARKER_ID7;
localparam [63:0] CTL_TX_VL_MARKER_ID8_REG = CTL_TX_VL_MARKER_ID8;
localparam [63:0] CTL_TX_VL_MARKER_ID9_REG = CTL_TX_VL_MARKER_ID9;
localparam [40:1] TEST_MODE_PIN_CHAR_REG = TEST_MODE_PIN_CHAR;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire DRP_RDY_out;
wire RX_ENAOUT0_out;
wire RX_ENAOUT1_out;
wire RX_ENAOUT2_out;
wire RX_ENAOUT3_out;
wire RX_EOPOUT0_out;
wire RX_EOPOUT1_out;
wire RX_EOPOUT2_out;
wire RX_EOPOUT3_out;
wire RX_ERROUT0_out;
wire RX_ERROUT1_out;
wire RX_ERROUT2_out;
wire RX_ERROUT3_out;
wire RX_SOPOUT0_out;
wire RX_SOPOUT1_out;
wire RX_SOPOUT2_out;
wire RX_SOPOUT3_out;
wire STAT_RX_ALIGNED_ERR_out;
wire STAT_RX_ALIGNED_out;
wire STAT_RX_BAD_PREAMBLE_out;
wire STAT_RX_BAD_SFD_out;
wire STAT_RX_BIP_ERR_0_out;
wire STAT_RX_BIP_ERR_10_out;
wire STAT_RX_BIP_ERR_11_out;
wire STAT_RX_BIP_ERR_12_out;
wire STAT_RX_BIP_ERR_13_out;
wire STAT_RX_BIP_ERR_14_out;
wire STAT_RX_BIP_ERR_15_out;
wire STAT_RX_BIP_ERR_16_out;
wire STAT_RX_BIP_ERR_17_out;
wire STAT_RX_BIP_ERR_18_out;
wire STAT_RX_BIP_ERR_19_out;
wire STAT_RX_BIP_ERR_1_out;
wire STAT_RX_BIP_ERR_2_out;
wire STAT_RX_BIP_ERR_3_out;
wire STAT_RX_BIP_ERR_4_out;
wire STAT_RX_BIP_ERR_5_out;
wire STAT_RX_BIP_ERR_6_out;
wire STAT_RX_BIP_ERR_7_out;
wire STAT_RX_BIP_ERR_8_out;
wire STAT_RX_BIP_ERR_9_out;
wire STAT_RX_BROADCAST_out;
wire STAT_RX_FRAMING_ERR_VALID_0_out;
wire STAT_RX_FRAMING_ERR_VALID_10_out;
wire STAT_RX_FRAMING_ERR_VALID_11_out;
wire STAT_RX_FRAMING_ERR_VALID_12_out;
wire STAT_RX_FRAMING_ERR_VALID_13_out;
wire STAT_RX_FRAMING_ERR_VALID_14_out;
wire STAT_RX_FRAMING_ERR_VALID_15_out;
wire STAT_RX_FRAMING_ERR_VALID_16_out;
wire STAT_RX_FRAMING_ERR_VALID_17_out;
wire STAT_RX_FRAMING_ERR_VALID_18_out;
wire STAT_RX_FRAMING_ERR_VALID_19_out;
wire STAT_RX_FRAMING_ERR_VALID_1_out;
wire STAT_RX_FRAMING_ERR_VALID_2_out;
wire STAT_RX_FRAMING_ERR_VALID_3_out;
wire STAT_RX_FRAMING_ERR_VALID_4_out;
wire STAT_RX_FRAMING_ERR_VALID_5_out;
wire STAT_RX_FRAMING_ERR_VALID_6_out;
wire STAT_RX_FRAMING_ERR_VALID_7_out;
wire STAT_RX_FRAMING_ERR_VALID_8_out;
wire STAT_RX_FRAMING_ERR_VALID_9_out;
wire STAT_RX_GOT_SIGNAL_OS_out;
wire STAT_RX_HI_BER_out;
wire STAT_RX_INRANGEERR_out;
wire STAT_RX_INTERNAL_LOCAL_FAULT_out;
wire STAT_RX_JABBER_out;
wire STAT_RX_LANE0_VLM_BIP7_VALID_out;
wire STAT_RX_LOCAL_FAULT_out;
wire STAT_RX_MISALIGNED_out;
wire STAT_RX_MULTICAST_out;
wire STAT_RX_OVERSIZE_out;
wire STAT_RX_PACKET_1024_1518_BYTES_out;
wire STAT_RX_PACKET_128_255_BYTES_out;
wire STAT_RX_PACKET_1519_1522_BYTES_out;
wire STAT_RX_PACKET_1523_1548_BYTES_out;
wire STAT_RX_PACKET_1549_2047_BYTES_out;
wire STAT_RX_PACKET_2048_4095_BYTES_out;
wire STAT_RX_PACKET_256_511_BYTES_out;
wire STAT_RX_PACKET_4096_8191_BYTES_out;
wire STAT_RX_PACKET_512_1023_BYTES_out;
wire STAT_RX_PACKET_64_BYTES_out;
wire STAT_RX_PACKET_65_127_BYTES_out;
wire STAT_RX_PACKET_8192_9215_BYTES_out;
wire STAT_RX_PACKET_BAD_FCS_out;
wire STAT_RX_PACKET_LARGE_out;
wire STAT_RX_PAUSE_out;
wire STAT_RX_RECEIVED_LOCAL_FAULT_out;
wire STAT_RX_REMOTE_FAULT_out;
wire STAT_RX_STATUS_out;
wire STAT_RX_TOOLONG_out;
wire STAT_RX_TOTAL_GOOD_PACKETS_out;
wire STAT_RX_TRUNCATED_out;
wire STAT_RX_UNICAST_out;
wire STAT_RX_USER_PAUSE_out;
wire STAT_RX_VLAN_out;
wire STAT_TX_BAD_FCS_out;
wire STAT_TX_BROADCAST_out;
wire STAT_TX_FRAME_ERROR_out;
wire STAT_TX_LOCAL_FAULT_out;
wire STAT_TX_MULTICAST_out;
wire STAT_TX_PACKET_1024_1518_BYTES_out;
wire STAT_TX_PACKET_128_255_BYTES_out;
wire STAT_TX_PACKET_1519_1522_BYTES_out;
wire STAT_TX_PACKET_1523_1548_BYTES_out;
wire STAT_TX_PACKET_1549_2047_BYTES_out;
wire STAT_TX_PACKET_2048_4095_BYTES_out;
wire STAT_TX_PACKET_256_511_BYTES_out;
wire STAT_TX_PACKET_4096_8191_BYTES_out;
wire STAT_TX_PACKET_512_1023_BYTES_out;
wire STAT_TX_PACKET_64_BYTES_out;
wire STAT_TX_PACKET_65_127_BYTES_out;
wire STAT_TX_PACKET_8192_9215_BYTES_out;
wire STAT_TX_PACKET_LARGE_out;
wire STAT_TX_PACKET_SMALL_out;
wire STAT_TX_PAUSE_out;
wire STAT_TX_PTP_FIFO_READ_ERROR_out;
wire STAT_TX_PTP_FIFO_WRITE_ERROR_out;
wire STAT_TX_TOTAL_GOOD_PACKETS_out;
wire STAT_TX_TOTAL_PACKETS_out;
wire STAT_TX_UNICAST_out;
wire STAT_TX_USER_PAUSE_out;
wire STAT_TX_VLAN_out;
wire TX_OVFOUT_out;
wire TX_PTP_TSTAMP_VALID_OUT_out;
wire TX_RDYOUT_out;
wire TX_UNFOUT_out;
wire [127:0] RX_DATAOUT0_out;
wire [127:0] RX_DATAOUT1_out;
wire [127:0] RX_DATAOUT2_out;
wire [127:0] RX_DATAOUT3_out;
wire [12:0] SCAN_OUT_DRPCTRL_out;
wire [13:0] STAT_RX_TOTAL_GOOD_BYTES_out;
wire [13:0] STAT_TX_TOTAL_GOOD_BYTES_out;
wire [15:0] DRP_DO_out;
wire [15:0] STAT_RX_PAUSE_QUANTA0_out;
wire [15:0] STAT_RX_PAUSE_QUANTA1_out;
wire [15:0] STAT_RX_PAUSE_QUANTA2_out;
wire [15:0] STAT_RX_PAUSE_QUANTA3_out;
wire [15:0] STAT_RX_PAUSE_QUANTA4_out;
wire [15:0] STAT_RX_PAUSE_QUANTA5_out;
wire [15:0] STAT_RX_PAUSE_QUANTA6_out;
wire [15:0] STAT_RX_PAUSE_QUANTA7_out;
wire [15:0] STAT_RX_PAUSE_QUANTA8_out;
wire [15:0] TX_PTP_TSTAMP_TAG_OUT_out;
wire [15:0] TX_SERDES_ALT_DATA0_out;
wire [15:0] TX_SERDES_ALT_DATA1_out;
wire [15:0] TX_SERDES_ALT_DATA2_out;
wire [15:0] TX_SERDES_ALT_DATA3_out;
wire [181:0] SCAN_OUT_CMAC_out;
wire [19:0] STAT_RX_BLOCK_LOCK_out;
wire [19:0] STAT_RX_MF_ERR_out;
wire [19:0] STAT_RX_MF_LEN_ERR_out;
wire [19:0] STAT_RX_MF_REPEAT_ERR_out;
wire [19:0] STAT_RX_SYNCED_ERR_out;
wire [19:0] STAT_RX_SYNCED_out;
wire [19:0] STAT_RX_VL_DEMUXED_out;
wire [2:0] STAT_RX_TEST_PATTERN_MISMATCH_out;
wire [31:0] TX_SERDES_DATA4_out;
wire [31:0] TX_SERDES_DATA5_out;
wire [31:0] TX_SERDES_DATA6_out;
wire [31:0] TX_SERDES_DATA7_out;
wire [31:0] TX_SERDES_DATA8_out;
wire [31:0] TX_SERDES_DATA9_out;
wire [3:0] RX_MTYOUT0_out;
wire [3:0] RX_MTYOUT1_out;
wire [3:0] RX_MTYOUT2_out;
wire [3:0] RX_MTYOUT3_out;
wire [3:0] STAT_RX_BAD_FCS_out;
wire [3:0] STAT_RX_FRAGMENT_out;
wire [3:0] STAT_RX_FRAMING_ERR_0_out;
wire [3:0] STAT_RX_FRAMING_ERR_10_out;
wire [3:0] STAT_RX_FRAMING_ERR_11_out;
wire [3:0] STAT_RX_FRAMING_ERR_12_out;
wire [3:0] STAT_RX_FRAMING_ERR_13_out;
wire [3:0] STAT_RX_FRAMING_ERR_14_out;
wire [3:0] STAT_RX_FRAMING_ERR_15_out;
wire [3:0] STAT_RX_FRAMING_ERR_16_out;
wire [3:0] STAT_RX_FRAMING_ERR_17_out;
wire [3:0] STAT_RX_FRAMING_ERR_18_out;
wire [3:0] STAT_RX_FRAMING_ERR_19_out;
wire [3:0] STAT_RX_FRAMING_ERR_1_out;
wire [3:0] STAT_RX_FRAMING_ERR_2_out;
wire [3:0] STAT_RX_FRAMING_ERR_3_out;
wire [3:0] STAT_RX_FRAMING_ERR_4_out;
wire [3:0] STAT_RX_FRAMING_ERR_5_out;
wire [3:0] STAT_RX_FRAMING_ERR_6_out;
wire [3:0] STAT_RX_FRAMING_ERR_7_out;
wire [3:0] STAT_RX_FRAMING_ERR_8_out;
wire [3:0] STAT_RX_FRAMING_ERR_9_out;
wire [3:0] STAT_RX_PACKET_SMALL_out;
wire [3:0] STAT_RX_STOMPED_FCS_out;
wire [3:0] STAT_RX_TOTAL_PACKETS_out;
wire [3:0] STAT_RX_UNDERSIZE_out;
wire [4:0] RX_PTP_PCSLANE_OUT_out;
wire [4:0] STAT_RX_VL_NUMBER_0_out;
wire [4:0] STAT_RX_VL_NUMBER_10_out;
wire [4:0] STAT_RX_VL_NUMBER_11_out;
wire [4:0] STAT_RX_VL_NUMBER_12_out;
wire [4:0] STAT_RX_VL_NUMBER_13_out;
wire [4:0] STAT_RX_VL_NUMBER_14_out;
wire [4:0] STAT_RX_VL_NUMBER_15_out;
wire [4:0] STAT_RX_VL_NUMBER_16_out;
wire [4:0] STAT_RX_VL_NUMBER_17_out;
wire [4:0] STAT_RX_VL_NUMBER_18_out;
wire [4:0] STAT_RX_VL_NUMBER_19_out;
wire [4:0] STAT_RX_VL_NUMBER_1_out;
wire [4:0] STAT_RX_VL_NUMBER_2_out;
wire [4:0] STAT_RX_VL_NUMBER_3_out;
wire [4:0] STAT_RX_VL_NUMBER_4_out;
wire [4:0] STAT_RX_VL_NUMBER_5_out;
wire [4:0] STAT_RX_VL_NUMBER_6_out;
wire [4:0] STAT_RX_VL_NUMBER_7_out;
wire [4:0] STAT_RX_VL_NUMBER_8_out;
wire [4:0] STAT_RX_VL_NUMBER_9_out;
wire [4:0] TX_PTP_PCSLANE_OUT_out;
wire [63:0] TX_SERDES_DATA0_out;
wire [63:0] TX_SERDES_DATA1_out;
wire [63:0] TX_SERDES_DATA2_out;
wire [63:0] TX_SERDES_DATA3_out;
wire [6:0] RX_LANE_ALIGNER_FILL_0_out;
wire [6:0] RX_LANE_ALIGNER_FILL_10_out;
wire [6:0] RX_LANE_ALIGNER_FILL_11_out;
wire [6:0] RX_LANE_ALIGNER_FILL_12_out;
wire [6:0] RX_LANE_ALIGNER_FILL_13_out;
wire [6:0] RX_LANE_ALIGNER_FILL_14_out;
wire [6:0] RX_LANE_ALIGNER_FILL_15_out;
wire [6:0] RX_LANE_ALIGNER_FILL_16_out;
wire [6:0] RX_LANE_ALIGNER_FILL_17_out;
wire [6:0] RX_LANE_ALIGNER_FILL_18_out;
wire [6:0] RX_LANE_ALIGNER_FILL_19_out;
wire [6:0] RX_LANE_ALIGNER_FILL_1_out;
wire [6:0] RX_LANE_ALIGNER_FILL_2_out;
wire [6:0] RX_LANE_ALIGNER_FILL_3_out;
wire [6:0] RX_LANE_ALIGNER_FILL_4_out;
wire [6:0] RX_LANE_ALIGNER_FILL_5_out;
wire [6:0] RX_LANE_ALIGNER_FILL_6_out;
wire [6:0] RX_LANE_ALIGNER_FILL_7_out;
wire [6:0] RX_LANE_ALIGNER_FILL_8_out;
wire [6:0] RX_LANE_ALIGNER_FILL_9_out;
wire [6:0] STAT_RX_BAD_CODE_out;
wire [6:0] STAT_TX_TOTAL_BYTES_out;
wire [79:0] RX_PTP_TSTAMP_OUT_out;
wire [79:0] TX_PTP_TSTAMP_OUT_out;
wire [7:0] STAT_RX_LANE0_VLM_BIP7_out;
wire [7:0] STAT_RX_TOTAL_BYTES_out;
wire [8:0] STAT_RX_PAUSE_REQ_out;
wire [8:0] STAT_RX_PAUSE_VALID_out;
wire [8:0] STAT_TX_PAUSE_VALID_out;
wire DRP_RDY_delay;
wire RX_ENAOUT0_delay;
wire RX_ENAOUT1_delay;
wire RX_ENAOUT2_delay;
wire RX_ENAOUT3_delay;
wire RX_EOPOUT0_delay;
wire RX_EOPOUT1_delay;
wire RX_EOPOUT2_delay;
wire RX_EOPOUT3_delay;
wire RX_ERROUT0_delay;
wire RX_ERROUT1_delay;
wire RX_ERROUT2_delay;
wire RX_ERROUT3_delay;
wire RX_SOPOUT0_delay;
wire RX_SOPOUT1_delay;
wire RX_SOPOUT2_delay;
wire RX_SOPOUT3_delay;
wire STAT_RX_ALIGNED_ERR_delay;
wire STAT_RX_ALIGNED_delay;
wire STAT_RX_BAD_PREAMBLE_delay;
wire STAT_RX_BAD_SFD_delay;
wire STAT_RX_BIP_ERR_0_delay;
wire STAT_RX_BIP_ERR_10_delay;
wire STAT_RX_BIP_ERR_11_delay;
wire STAT_RX_BIP_ERR_12_delay;
wire STAT_RX_BIP_ERR_13_delay;
wire STAT_RX_BIP_ERR_14_delay;
wire STAT_RX_BIP_ERR_15_delay;
wire STAT_RX_BIP_ERR_16_delay;
wire STAT_RX_BIP_ERR_17_delay;
wire STAT_RX_BIP_ERR_18_delay;
wire STAT_RX_BIP_ERR_19_delay;
wire STAT_RX_BIP_ERR_1_delay;
wire STAT_RX_BIP_ERR_2_delay;
wire STAT_RX_BIP_ERR_3_delay;
wire STAT_RX_BIP_ERR_4_delay;
wire STAT_RX_BIP_ERR_5_delay;
wire STAT_RX_BIP_ERR_6_delay;
wire STAT_RX_BIP_ERR_7_delay;
wire STAT_RX_BIP_ERR_8_delay;
wire STAT_RX_BIP_ERR_9_delay;
wire STAT_RX_BROADCAST_delay;
wire STAT_RX_FRAMING_ERR_VALID_0_delay;
wire STAT_RX_FRAMING_ERR_VALID_10_delay;
wire STAT_RX_FRAMING_ERR_VALID_11_delay;
wire STAT_RX_FRAMING_ERR_VALID_12_delay;
wire STAT_RX_FRAMING_ERR_VALID_13_delay;
wire STAT_RX_FRAMING_ERR_VALID_14_delay;
wire STAT_RX_FRAMING_ERR_VALID_15_delay;
wire STAT_RX_FRAMING_ERR_VALID_16_delay;
wire STAT_RX_FRAMING_ERR_VALID_17_delay;
wire STAT_RX_FRAMING_ERR_VALID_18_delay;
wire STAT_RX_FRAMING_ERR_VALID_19_delay;
wire STAT_RX_FRAMING_ERR_VALID_1_delay;
wire STAT_RX_FRAMING_ERR_VALID_2_delay;
wire STAT_RX_FRAMING_ERR_VALID_3_delay;
wire STAT_RX_FRAMING_ERR_VALID_4_delay;
wire STAT_RX_FRAMING_ERR_VALID_5_delay;
wire STAT_RX_FRAMING_ERR_VALID_6_delay;
wire STAT_RX_FRAMING_ERR_VALID_7_delay;
wire STAT_RX_FRAMING_ERR_VALID_8_delay;
wire STAT_RX_FRAMING_ERR_VALID_9_delay;
wire STAT_RX_GOT_SIGNAL_OS_delay;
wire STAT_RX_HI_BER_delay;
wire STAT_RX_INRANGEERR_delay;
wire STAT_RX_INTERNAL_LOCAL_FAULT_delay;
wire STAT_RX_JABBER_delay;
wire STAT_RX_LANE0_VLM_BIP7_VALID_delay;
wire STAT_RX_LOCAL_FAULT_delay;
wire STAT_RX_MISALIGNED_delay;
wire STAT_RX_MULTICAST_delay;
wire STAT_RX_OVERSIZE_delay;
wire STAT_RX_PACKET_1024_1518_BYTES_delay;
wire STAT_RX_PACKET_128_255_BYTES_delay;
wire STAT_RX_PACKET_1519_1522_BYTES_delay;
wire STAT_RX_PACKET_1523_1548_BYTES_delay;
wire STAT_RX_PACKET_1549_2047_BYTES_delay;
wire STAT_RX_PACKET_2048_4095_BYTES_delay;
wire STAT_RX_PACKET_256_511_BYTES_delay;
wire STAT_RX_PACKET_4096_8191_BYTES_delay;
wire STAT_RX_PACKET_512_1023_BYTES_delay;
wire STAT_RX_PACKET_64_BYTES_delay;
wire STAT_RX_PACKET_65_127_BYTES_delay;
wire STAT_RX_PACKET_8192_9215_BYTES_delay;
wire STAT_RX_PACKET_BAD_FCS_delay;
wire STAT_RX_PACKET_LARGE_delay;
wire STAT_RX_PAUSE_delay;
wire STAT_RX_RECEIVED_LOCAL_FAULT_delay;
wire STAT_RX_REMOTE_FAULT_delay;
wire STAT_RX_STATUS_delay;
wire STAT_RX_TOOLONG_delay;
wire STAT_RX_TOTAL_GOOD_PACKETS_delay;
wire STAT_RX_TRUNCATED_delay;
wire STAT_RX_UNICAST_delay;
wire STAT_RX_USER_PAUSE_delay;
wire STAT_RX_VLAN_delay;
wire STAT_TX_BAD_FCS_delay;
wire STAT_TX_BROADCAST_delay;
wire STAT_TX_FRAME_ERROR_delay;
wire STAT_TX_LOCAL_FAULT_delay;
wire STAT_TX_MULTICAST_delay;
wire STAT_TX_PACKET_1024_1518_BYTES_delay;
wire STAT_TX_PACKET_128_255_BYTES_delay;
wire STAT_TX_PACKET_1519_1522_BYTES_delay;
wire STAT_TX_PACKET_1523_1548_BYTES_delay;
wire STAT_TX_PACKET_1549_2047_BYTES_delay;
wire STAT_TX_PACKET_2048_4095_BYTES_delay;
wire STAT_TX_PACKET_256_511_BYTES_delay;
wire STAT_TX_PACKET_4096_8191_BYTES_delay;
wire STAT_TX_PACKET_512_1023_BYTES_delay;
wire STAT_TX_PACKET_64_BYTES_delay;
wire STAT_TX_PACKET_65_127_BYTES_delay;
wire STAT_TX_PACKET_8192_9215_BYTES_delay;
wire STAT_TX_PACKET_LARGE_delay;
wire STAT_TX_PACKET_SMALL_delay;
wire STAT_TX_PAUSE_delay;
wire STAT_TX_PTP_FIFO_READ_ERROR_delay;
wire STAT_TX_PTP_FIFO_WRITE_ERROR_delay;
wire STAT_TX_TOTAL_GOOD_PACKETS_delay;
wire STAT_TX_TOTAL_PACKETS_delay;
wire STAT_TX_UNICAST_delay;
wire STAT_TX_USER_PAUSE_delay;
wire STAT_TX_VLAN_delay;
wire TX_OVFOUT_delay;
wire TX_PTP_TSTAMP_VALID_OUT_delay;
wire TX_RDYOUT_delay;
wire TX_UNFOUT_delay;
wire [127:0] RX_DATAOUT0_delay;
wire [127:0] RX_DATAOUT1_delay;
wire [127:0] RX_DATAOUT2_delay;
wire [127:0] RX_DATAOUT3_delay;
wire [13:0] STAT_RX_TOTAL_GOOD_BYTES_delay;
wire [13:0] STAT_TX_TOTAL_GOOD_BYTES_delay;
wire [15:0] DRP_DO_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA0_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA1_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA2_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA3_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA4_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA5_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA6_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA7_delay;
wire [15:0] STAT_RX_PAUSE_QUANTA8_delay;
wire [15:0] TX_PTP_TSTAMP_TAG_OUT_delay;
wire [15:0] TX_SERDES_ALT_DATA0_delay;
wire [15:0] TX_SERDES_ALT_DATA1_delay;
wire [15:0] TX_SERDES_ALT_DATA2_delay;
wire [15:0] TX_SERDES_ALT_DATA3_delay;
wire [19:0] STAT_RX_BLOCK_LOCK_delay;
wire [19:0] STAT_RX_MF_ERR_delay;
wire [19:0] STAT_RX_MF_LEN_ERR_delay;
wire [19:0] STAT_RX_MF_REPEAT_ERR_delay;
wire [19:0] STAT_RX_SYNCED_ERR_delay;
wire [19:0] STAT_RX_SYNCED_delay;
wire [19:0] STAT_RX_VL_DEMUXED_delay;
wire [2:0] STAT_RX_TEST_PATTERN_MISMATCH_delay;
wire [31:0] TX_SERDES_DATA4_delay;
wire [31:0] TX_SERDES_DATA5_delay;
wire [31:0] TX_SERDES_DATA6_delay;
wire [31:0] TX_SERDES_DATA7_delay;
wire [31:0] TX_SERDES_DATA8_delay;
wire [31:0] TX_SERDES_DATA9_delay;
wire [3:0] RX_MTYOUT0_delay;
wire [3:0] RX_MTYOUT1_delay;
wire [3:0] RX_MTYOUT2_delay;
wire [3:0] RX_MTYOUT3_delay;
wire [3:0] STAT_RX_BAD_FCS_delay;
wire [3:0] STAT_RX_FRAGMENT_delay;
wire [3:0] STAT_RX_FRAMING_ERR_0_delay;
wire [3:0] STAT_RX_FRAMING_ERR_10_delay;
wire [3:0] STAT_RX_FRAMING_ERR_11_delay;
wire [3:0] STAT_RX_FRAMING_ERR_12_delay;
wire [3:0] STAT_RX_FRAMING_ERR_13_delay;
wire [3:0] STAT_RX_FRAMING_ERR_14_delay;
wire [3:0] STAT_RX_FRAMING_ERR_15_delay;
wire [3:0] STAT_RX_FRAMING_ERR_16_delay;
wire [3:0] STAT_RX_FRAMING_ERR_17_delay;
wire [3:0] STAT_RX_FRAMING_ERR_18_delay;
wire [3:0] STAT_RX_FRAMING_ERR_19_delay;
wire [3:0] STAT_RX_FRAMING_ERR_1_delay;
wire [3:0] STAT_RX_FRAMING_ERR_2_delay;
wire [3:0] STAT_RX_FRAMING_ERR_3_delay;
wire [3:0] STAT_RX_FRAMING_ERR_4_delay;
wire [3:0] STAT_RX_FRAMING_ERR_5_delay;
wire [3:0] STAT_RX_FRAMING_ERR_6_delay;
wire [3:0] STAT_RX_FRAMING_ERR_7_delay;
wire [3:0] STAT_RX_FRAMING_ERR_8_delay;
wire [3:0] STAT_RX_FRAMING_ERR_9_delay;
wire [3:0] STAT_RX_PACKET_SMALL_delay;
wire [3:0] STAT_RX_STOMPED_FCS_delay;
wire [3:0] STAT_RX_TOTAL_PACKETS_delay;
wire [3:0] STAT_RX_UNDERSIZE_delay;
wire [4:0] RX_PTP_PCSLANE_OUT_delay;
wire [4:0] STAT_RX_VL_NUMBER_0_delay;
wire [4:0] STAT_RX_VL_NUMBER_10_delay;
wire [4:0] STAT_RX_VL_NUMBER_11_delay;
wire [4:0] STAT_RX_VL_NUMBER_12_delay;
wire [4:0] STAT_RX_VL_NUMBER_13_delay;
wire [4:0] STAT_RX_VL_NUMBER_14_delay;
wire [4:0] STAT_RX_VL_NUMBER_15_delay;
wire [4:0] STAT_RX_VL_NUMBER_16_delay;
wire [4:0] STAT_RX_VL_NUMBER_17_delay;
wire [4:0] STAT_RX_VL_NUMBER_18_delay;
wire [4:0] STAT_RX_VL_NUMBER_19_delay;
wire [4:0] STAT_RX_VL_NUMBER_1_delay;
wire [4:0] STAT_RX_VL_NUMBER_2_delay;
wire [4:0] STAT_RX_VL_NUMBER_3_delay;
wire [4:0] STAT_RX_VL_NUMBER_4_delay;
wire [4:0] STAT_RX_VL_NUMBER_5_delay;
wire [4:0] STAT_RX_VL_NUMBER_6_delay;
wire [4:0] STAT_RX_VL_NUMBER_7_delay;
wire [4:0] STAT_RX_VL_NUMBER_8_delay;
wire [4:0] STAT_RX_VL_NUMBER_9_delay;
wire [4:0] TX_PTP_PCSLANE_OUT_delay;
wire [63:0] TX_SERDES_DATA0_delay;
wire [63:0] TX_SERDES_DATA1_delay;
wire [63:0] TX_SERDES_DATA2_delay;
wire [63:0] TX_SERDES_DATA3_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_0_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_10_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_11_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_12_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_13_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_14_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_15_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_16_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_17_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_18_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_19_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_1_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_2_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_3_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_4_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_5_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_6_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_7_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_8_delay;
wire [6:0] RX_LANE_ALIGNER_FILL_9_delay;
wire [6:0] STAT_RX_BAD_CODE_delay;
wire [6:0] STAT_TX_TOTAL_BYTES_delay;
wire [79:0] RX_PTP_TSTAMP_OUT_delay;
wire [79:0] TX_PTP_TSTAMP_OUT_delay;
wire [7:0] STAT_RX_LANE0_VLM_BIP7_delay;
wire [7:0] STAT_RX_TOTAL_BYTES_delay;
wire [8:0] STAT_RX_PAUSE_REQ_delay;
wire [8:0] STAT_RX_PAUSE_VALID_delay;
wire [8:0] STAT_TX_PAUSE_VALID_delay;
wire CTL_CAUI4_MODE_in;
wire CTL_RX_CHECK_ETYPE_GCP_in;
wire CTL_RX_CHECK_ETYPE_GPP_in;
wire CTL_RX_CHECK_ETYPE_PCP_in;
wire CTL_RX_CHECK_ETYPE_PPP_in;
wire CTL_RX_CHECK_MCAST_GCP_in;
wire CTL_RX_CHECK_MCAST_GPP_in;
wire CTL_RX_CHECK_MCAST_PCP_in;
wire CTL_RX_CHECK_MCAST_PPP_in;
wire CTL_RX_CHECK_OPCODE_GCP_in;
wire CTL_RX_CHECK_OPCODE_GPP_in;
wire CTL_RX_CHECK_OPCODE_PCP_in;
wire CTL_RX_CHECK_OPCODE_PPP_in;
wire CTL_RX_CHECK_SA_GCP_in;
wire CTL_RX_CHECK_SA_GPP_in;
wire CTL_RX_CHECK_SA_PCP_in;
wire CTL_RX_CHECK_SA_PPP_in;
wire CTL_RX_CHECK_UCAST_GCP_in;
wire CTL_RX_CHECK_UCAST_GPP_in;
wire CTL_RX_CHECK_UCAST_PCP_in;
wire CTL_RX_CHECK_UCAST_PPP_in;
wire CTL_RX_ENABLE_GCP_in;
wire CTL_RX_ENABLE_GPP_in;
wire CTL_RX_ENABLE_PCP_in;
wire CTL_RX_ENABLE_PPP_in;
wire CTL_RX_ENABLE_in;
wire CTL_RX_FORCE_RESYNC_in;
wire CTL_RX_TEST_PATTERN_in;
wire CTL_TX_ENABLE_in;
wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in;
wire CTL_TX_PTP_VLANE_ADJUST_MODE_in;
wire CTL_TX_RESEND_PAUSE_in;
wire CTL_TX_SEND_IDLE_in;
wire CTL_TX_SEND_RFI_in;
wire CTL_TX_TEST_PATTERN_in;
wire DRP_CLK_in;
wire DRP_EN_in;
wire DRP_WE_in;
wire RX_CLK_in;
wire RX_RESET_in;
wire SCAN_EN_in;
wire TEST_MODE_in;
wire TEST_RESET_in;
wire TX_CLK_in;
wire TX_ENAIN0_in;
wire TX_ENAIN1_in;
wire TX_ENAIN2_in;
wire TX_ENAIN3_in;
wire TX_EOPIN0_in;
wire TX_EOPIN1_in;
wire TX_EOPIN2_in;
wire TX_EOPIN3_in;
wire TX_ERRIN0_in;
wire TX_ERRIN1_in;
wire TX_ERRIN2_in;
wire TX_ERRIN3_in;
wire TX_PTP_UPD_CHKSUM_IN_in;
wire TX_RESET_in;
wire TX_SOPIN0_in;
wire TX_SOPIN1_in;
wire TX_SOPIN2_in;
wire TX_SOPIN3_in;
wire [127:0] TX_DATAIN0_in;
wire [127:0] TX_DATAIN1_in;
wire [127:0] TX_DATAIN2_in;
wire [127:0] TX_DATAIN3_in;
wire [12:0] SCAN_IN_DRPCTRL_in;
wire [15:0] CTL_TX_PAUSE_QUANTA0_in;
wire [15:0] CTL_TX_PAUSE_QUANTA1_in;
wire [15:0] CTL_TX_PAUSE_QUANTA2_in;
wire [15:0] CTL_TX_PAUSE_QUANTA3_in;
wire [15:0] CTL_TX_PAUSE_QUANTA4_in;
wire [15:0] CTL_TX_PAUSE_QUANTA5_in;
wire [15:0] CTL_TX_PAUSE_QUANTA6_in;
wire [15:0] CTL_TX_PAUSE_QUANTA7_in;
wire [15:0] CTL_TX_PAUSE_QUANTA8_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_in;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_in;
wire [15:0] DRP_DI_in;
wire [15:0] RX_SERDES_ALT_DATA0_in;
wire [15:0] RX_SERDES_ALT_DATA1_in;
wire [15:0] RX_SERDES_ALT_DATA2_in;
wire [15:0] RX_SERDES_ALT_DATA3_in;
wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_in;
wire [15:0] TX_PTP_TAG_FIELD_IN_in;
wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_in;
wire [181:0] SCAN_IN_CMAC_in;
wire [1:0] TX_PTP_1588OP_IN_in;
wire [31:0] RX_SERDES_DATA4_in;
wire [31:0] RX_SERDES_DATA5_in;
wire [31:0] RX_SERDES_DATA6_in;
wire [31:0] RX_SERDES_DATA7_in;
wire [31:0] RX_SERDES_DATA8_in;
wire [31:0] RX_SERDES_DATA9_in;
wire [3:0] TX_MTYIN0_in;
wire [3:0] TX_MTYIN1_in;
wire [3:0] TX_MTYIN2_in;
wire [3:0] TX_MTYIN3_in;
wire [63:0] RX_SERDES_DATA0_in;
wire [63:0] RX_SERDES_DATA1_in;
wire [63:0] RX_SERDES_DATA2_in;
wire [63:0] RX_SERDES_DATA3_in;
wire [63:0] TX_PTP_RXTSTAMP_IN_in;
wire [79:0] CTL_RX_SYSTEMTIMERIN_in;
wire [79:0] CTL_TX_SYSTEMTIMERIN_in;
wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in;
wire [8:0] CTL_RX_PAUSE_ACK_in;
wire [8:0] CTL_RX_PAUSE_ENABLE_in;
wire [8:0] CTL_TX_PAUSE_ENABLE_in;
wire [8:0] CTL_TX_PAUSE_REQ_in;
wire [9:0] DRP_ADDR_in;
wire [9:0] RX_SERDES_CLK_in;
wire [9:0] RX_SERDES_RESET_in;
wire CTL_CAUI4_MODE_delay;
wire CTL_RX_CHECK_ETYPE_GCP_delay;
wire CTL_RX_CHECK_ETYPE_GPP_delay;
wire CTL_RX_CHECK_ETYPE_PCP_delay;
wire CTL_RX_CHECK_ETYPE_PPP_delay;
wire CTL_RX_CHECK_MCAST_GCP_delay;
wire CTL_RX_CHECK_MCAST_GPP_delay;
wire CTL_RX_CHECK_MCAST_PCP_delay;
wire CTL_RX_CHECK_MCAST_PPP_delay;
wire CTL_RX_CHECK_OPCODE_GCP_delay;
wire CTL_RX_CHECK_OPCODE_GPP_delay;
wire CTL_RX_CHECK_OPCODE_PCP_delay;
wire CTL_RX_CHECK_OPCODE_PPP_delay;
wire CTL_RX_CHECK_SA_GCP_delay;
wire CTL_RX_CHECK_SA_GPP_delay;
wire CTL_RX_CHECK_SA_PCP_delay;
wire CTL_RX_CHECK_SA_PPP_delay;
wire CTL_RX_CHECK_UCAST_GCP_delay;
wire CTL_RX_CHECK_UCAST_GPP_delay;
wire CTL_RX_CHECK_UCAST_PCP_delay;
wire CTL_RX_CHECK_UCAST_PPP_delay;
wire CTL_RX_ENABLE_GCP_delay;
wire CTL_RX_ENABLE_GPP_delay;
wire CTL_RX_ENABLE_PCP_delay;
wire CTL_RX_ENABLE_PPP_delay;
wire CTL_RX_ENABLE_delay;
wire CTL_RX_FORCE_RESYNC_delay;
wire CTL_RX_TEST_PATTERN_delay;
wire CTL_TX_ENABLE_delay;
wire CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay;
wire CTL_TX_PTP_VLANE_ADJUST_MODE_delay;
wire CTL_TX_RESEND_PAUSE_delay;
wire CTL_TX_SEND_IDLE_delay;
wire CTL_TX_SEND_RFI_delay;
wire CTL_TX_TEST_PATTERN_delay;
wire DRP_CLK_delay;
wire DRP_EN_delay;
wire DRP_WE_delay;
wire RX_CLK_delay;
wire RX_RESET_delay;
wire TX_CLK_delay;
wire TX_ENAIN0_delay;
wire TX_ENAIN1_delay;
wire TX_ENAIN2_delay;
wire TX_ENAIN3_delay;
wire TX_EOPIN0_delay;
wire TX_EOPIN1_delay;
wire TX_EOPIN2_delay;
wire TX_EOPIN3_delay;
wire TX_ERRIN0_delay;
wire TX_ERRIN1_delay;
wire TX_ERRIN2_delay;
wire TX_ERRIN3_delay;
wire TX_PTP_UPD_CHKSUM_IN_delay;
wire TX_RESET_delay;
wire TX_SOPIN0_delay;
wire TX_SOPIN1_delay;
wire TX_SOPIN2_delay;
wire TX_SOPIN3_delay;
wire [127:0] TX_DATAIN0_delay;
wire [127:0] TX_DATAIN1_delay;
wire [127:0] TX_DATAIN2_delay;
wire [127:0] TX_DATAIN3_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA0_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA1_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA2_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA3_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA4_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA5_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA6_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA7_delay;
wire [15:0] CTL_TX_PAUSE_QUANTA8_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER0_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER1_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER2_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER3_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER4_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER5_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER6_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER7_delay;
wire [15:0] CTL_TX_PAUSE_REFRESH_TIMER8_delay;
wire [15:0] DRP_DI_delay;
wire [15:0] RX_SERDES_ALT_DATA0_delay;
wire [15:0] RX_SERDES_ALT_DATA1_delay;
wire [15:0] RX_SERDES_ALT_DATA2_delay;
wire [15:0] RX_SERDES_ALT_DATA3_delay;
wire [15:0] TX_PTP_CHKSUM_OFFSET_IN_delay;
wire [15:0] TX_PTP_TAG_FIELD_IN_delay;
wire [15:0] TX_PTP_TSTAMP_OFFSET_IN_delay;
wire [1:0] TX_PTP_1588OP_IN_delay;
wire [31:0] RX_SERDES_DATA4_delay;
wire [31:0] RX_SERDES_DATA5_delay;
wire [31:0] RX_SERDES_DATA6_delay;
wire [31:0] RX_SERDES_DATA7_delay;
wire [31:0] RX_SERDES_DATA8_delay;
wire [31:0] RX_SERDES_DATA9_delay;
wire [3:0] TX_MTYIN0_delay;
wire [3:0] TX_MTYIN1_delay;
wire [3:0] TX_MTYIN2_delay;
wire [3:0] TX_MTYIN3_delay;
wire [63:0] RX_SERDES_DATA0_delay;
wire [63:0] RX_SERDES_DATA1_delay;
wire [63:0] RX_SERDES_DATA2_delay;
wire [63:0] RX_SERDES_DATA3_delay;
wire [63:0] TX_PTP_RXTSTAMP_IN_delay;
wire [79:0] CTL_RX_SYSTEMTIMERIN_delay;
wire [79:0] CTL_TX_SYSTEMTIMERIN_delay;
wire [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay;
wire [8:0] CTL_RX_PAUSE_ACK_delay;
wire [8:0] CTL_RX_PAUSE_ENABLE_delay;
wire [8:0] CTL_TX_PAUSE_ENABLE_delay;
wire [8:0] CTL_TX_PAUSE_REQ_delay;
wire [9:0] DRP_ADDR_delay;
wire [9:0] RX_SERDES_CLK_delay;
wire [9:0] RX_SERDES_RESET_delay;
assign #(out_delay) DRP_DO = DRP_DO_delay;
assign #(out_delay) DRP_RDY = DRP_RDY_delay;
assign #(out_delay) RX_DATAOUT0 = RX_DATAOUT0_delay;
assign #(out_delay) RX_DATAOUT1 = RX_DATAOUT1_delay;
assign #(out_delay) RX_DATAOUT2 = RX_DATAOUT2_delay;
assign #(out_delay) RX_DATAOUT3 = RX_DATAOUT3_delay;
assign #(out_delay) RX_ENAOUT0 = RX_ENAOUT0_delay;
assign #(out_delay) RX_ENAOUT1 = RX_ENAOUT1_delay;
assign #(out_delay) RX_ENAOUT2 = RX_ENAOUT2_delay;
assign #(out_delay) RX_ENAOUT3 = RX_ENAOUT3_delay;
assign #(out_delay) RX_EOPOUT0 = RX_EOPOUT0_delay;
assign #(out_delay) RX_EOPOUT1 = RX_EOPOUT1_delay;
assign #(out_delay) RX_EOPOUT2 = RX_EOPOUT2_delay;
assign #(out_delay) RX_EOPOUT3 = RX_EOPOUT3_delay;
assign #(out_delay) RX_ERROUT0 = RX_ERROUT0_delay;
assign #(out_delay) RX_ERROUT1 = RX_ERROUT1_delay;
assign #(out_delay) RX_ERROUT2 = RX_ERROUT2_delay;
assign #(out_delay) RX_ERROUT3 = RX_ERROUT3_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_0 = RX_LANE_ALIGNER_FILL_0_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_1 = RX_LANE_ALIGNER_FILL_1_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_10 = RX_LANE_ALIGNER_FILL_10_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_11 = RX_LANE_ALIGNER_FILL_11_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_12 = RX_LANE_ALIGNER_FILL_12_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_13 = RX_LANE_ALIGNER_FILL_13_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_14 = RX_LANE_ALIGNER_FILL_14_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_15 = RX_LANE_ALIGNER_FILL_15_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_16 = RX_LANE_ALIGNER_FILL_16_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_17 = RX_LANE_ALIGNER_FILL_17_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_18 = RX_LANE_ALIGNER_FILL_18_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_19 = RX_LANE_ALIGNER_FILL_19_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_2 = RX_LANE_ALIGNER_FILL_2_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_3 = RX_LANE_ALIGNER_FILL_3_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_4 = RX_LANE_ALIGNER_FILL_4_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_5 = RX_LANE_ALIGNER_FILL_5_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_6 = RX_LANE_ALIGNER_FILL_6_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_7 = RX_LANE_ALIGNER_FILL_7_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_8 = RX_LANE_ALIGNER_FILL_8_delay;
assign #(out_delay) RX_LANE_ALIGNER_FILL_9 = RX_LANE_ALIGNER_FILL_9_delay;
assign #(out_delay) RX_MTYOUT0 = RX_MTYOUT0_delay;
assign #(out_delay) RX_MTYOUT1 = RX_MTYOUT1_delay;
assign #(out_delay) RX_MTYOUT2 = RX_MTYOUT2_delay;
assign #(out_delay) RX_MTYOUT3 = RX_MTYOUT3_delay;
assign #(out_delay) RX_PTP_PCSLANE_OUT = RX_PTP_PCSLANE_OUT_delay;
assign #(out_delay) RX_PTP_TSTAMP_OUT = RX_PTP_TSTAMP_OUT_delay;
assign #(out_delay) RX_SOPOUT0 = RX_SOPOUT0_delay;
assign #(out_delay) RX_SOPOUT1 = RX_SOPOUT1_delay;
assign #(out_delay) RX_SOPOUT2 = RX_SOPOUT2_delay;
assign #(out_delay) RX_SOPOUT3 = RX_SOPOUT3_delay;
assign #(out_delay) STAT_RX_ALIGNED = STAT_RX_ALIGNED_delay;
assign #(out_delay) STAT_RX_ALIGNED_ERR = STAT_RX_ALIGNED_ERR_delay;
assign #(out_delay) STAT_RX_BAD_CODE = STAT_RX_BAD_CODE_delay;
assign #(out_delay) STAT_RX_BAD_FCS = STAT_RX_BAD_FCS_delay;
assign #(out_delay) STAT_RX_BAD_PREAMBLE = STAT_RX_BAD_PREAMBLE_delay;
assign #(out_delay) STAT_RX_BAD_SFD = STAT_RX_BAD_SFD_delay;
assign #(out_delay) STAT_RX_BIP_ERR_0 = STAT_RX_BIP_ERR_0_delay;
assign #(out_delay) STAT_RX_BIP_ERR_1 = STAT_RX_BIP_ERR_1_delay;
assign #(out_delay) STAT_RX_BIP_ERR_10 = STAT_RX_BIP_ERR_10_delay;
assign #(out_delay) STAT_RX_BIP_ERR_11 = STAT_RX_BIP_ERR_11_delay;
assign #(out_delay) STAT_RX_BIP_ERR_12 = STAT_RX_BIP_ERR_12_delay;
assign #(out_delay) STAT_RX_BIP_ERR_13 = STAT_RX_BIP_ERR_13_delay;
assign #(out_delay) STAT_RX_BIP_ERR_14 = STAT_RX_BIP_ERR_14_delay;
assign #(out_delay) STAT_RX_BIP_ERR_15 = STAT_RX_BIP_ERR_15_delay;
assign #(out_delay) STAT_RX_BIP_ERR_16 = STAT_RX_BIP_ERR_16_delay;
assign #(out_delay) STAT_RX_BIP_ERR_17 = STAT_RX_BIP_ERR_17_delay;
assign #(out_delay) STAT_RX_BIP_ERR_18 = STAT_RX_BIP_ERR_18_delay;
assign #(out_delay) STAT_RX_BIP_ERR_19 = STAT_RX_BIP_ERR_19_delay;
assign #(out_delay) STAT_RX_BIP_ERR_2 = STAT_RX_BIP_ERR_2_delay;
assign #(out_delay) STAT_RX_BIP_ERR_3 = STAT_RX_BIP_ERR_3_delay;
assign #(out_delay) STAT_RX_BIP_ERR_4 = STAT_RX_BIP_ERR_4_delay;
assign #(out_delay) STAT_RX_BIP_ERR_5 = STAT_RX_BIP_ERR_5_delay;
assign #(out_delay) STAT_RX_BIP_ERR_6 = STAT_RX_BIP_ERR_6_delay;
assign #(out_delay) STAT_RX_BIP_ERR_7 = STAT_RX_BIP_ERR_7_delay;
assign #(out_delay) STAT_RX_BIP_ERR_8 = STAT_RX_BIP_ERR_8_delay;
assign #(out_delay) STAT_RX_BIP_ERR_9 = STAT_RX_BIP_ERR_9_delay;
assign #(out_delay) STAT_RX_BLOCK_LOCK = STAT_RX_BLOCK_LOCK_delay;
assign #(out_delay) STAT_RX_BROADCAST = STAT_RX_BROADCAST_delay;
assign #(out_delay) STAT_RX_FRAGMENT = STAT_RX_FRAGMENT_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_0 = STAT_RX_FRAMING_ERR_0_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_1 = STAT_RX_FRAMING_ERR_1_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_10 = STAT_RX_FRAMING_ERR_10_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_11 = STAT_RX_FRAMING_ERR_11_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_12 = STAT_RX_FRAMING_ERR_12_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_13 = STAT_RX_FRAMING_ERR_13_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_14 = STAT_RX_FRAMING_ERR_14_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_15 = STAT_RX_FRAMING_ERR_15_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_16 = STAT_RX_FRAMING_ERR_16_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_17 = STAT_RX_FRAMING_ERR_17_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_18 = STAT_RX_FRAMING_ERR_18_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_19 = STAT_RX_FRAMING_ERR_19_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_2 = STAT_RX_FRAMING_ERR_2_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_3 = STAT_RX_FRAMING_ERR_3_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_4 = STAT_RX_FRAMING_ERR_4_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_5 = STAT_RX_FRAMING_ERR_5_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_6 = STAT_RX_FRAMING_ERR_6_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_7 = STAT_RX_FRAMING_ERR_7_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_8 = STAT_RX_FRAMING_ERR_8_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_9 = STAT_RX_FRAMING_ERR_9_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_0 = STAT_RX_FRAMING_ERR_VALID_0_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_1 = STAT_RX_FRAMING_ERR_VALID_1_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_10 = STAT_RX_FRAMING_ERR_VALID_10_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_11 = STAT_RX_FRAMING_ERR_VALID_11_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_12 = STAT_RX_FRAMING_ERR_VALID_12_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_13 = STAT_RX_FRAMING_ERR_VALID_13_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_14 = STAT_RX_FRAMING_ERR_VALID_14_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_15 = STAT_RX_FRAMING_ERR_VALID_15_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_16 = STAT_RX_FRAMING_ERR_VALID_16_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_17 = STAT_RX_FRAMING_ERR_VALID_17_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_18 = STAT_RX_FRAMING_ERR_VALID_18_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_19 = STAT_RX_FRAMING_ERR_VALID_19_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_2 = STAT_RX_FRAMING_ERR_VALID_2_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_3 = STAT_RX_FRAMING_ERR_VALID_3_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_4 = STAT_RX_FRAMING_ERR_VALID_4_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_5 = STAT_RX_FRAMING_ERR_VALID_5_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_6 = STAT_RX_FRAMING_ERR_VALID_6_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_7 = STAT_RX_FRAMING_ERR_VALID_7_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_8 = STAT_RX_FRAMING_ERR_VALID_8_delay;
assign #(out_delay) STAT_RX_FRAMING_ERR_VALID_9 = STAT_RX_FRAMING_ERR_VALID_9_delay;
assign #(out_delay) STAT_RX_GOT_SIGNAL_OS = STAT_RX_GOT_SIGNAL_OS_delay;
assign #(out_delay) STAT_RX_HI_BER = STAT_RX_HI_BER_delay;
assign #(out_delay) STAT_RX_INRANGEERR = STAT_RX_INRANGEERR_delay;
assign #(out_delay) STAT_RX_INTERNAL_LOCAL_FAULT = STAT_RX_INTERNAL_LOCAL_FAULT_delay;
assign #(out_delay) STAT_RX_JABBER = STAT_RX_JABBER_delay;
assign #(out_delay) STAT_RX_LANE0_VLM_BIP7 = STAT_RX_LANE0_VLM_BIP7_delay;
assign #(out_delay) STAT_RX_LANE0_VLM_BIP7_VALID = STAT_RX_LANE0_VLM_BIP7_VALID_delay;
assign #(out_delay) STAT_RX_LOCAL_FAULT = STAT_RX_LOCAL_FAULT_delay;
assign #(out_delay) STAT_RX_MF_ERR = STAT_RX_MF_ERR_delay;
assign #(out_delay) STAT_RX_MF_LEN_ERR = STAT_RX_MF_LEN_ERR_delay;
assign #(out_delay) STAT_RX_MF_REPEAT_ERR = STAT_RX_MF_REPEAT_ERR_delay;
assign #(out_delay) STAT_RX_MISALIGNED = STAT_RX_MISALIGNED_delay;
assign #(out_delay) STAT_RX_MULTICAST = STAT_RX_MULTICAST_delay;
assign #(out_delay) STAT_RX_OVERSIZE = STAT_RX_OVERSIZE_delay;
assign #(out_delay) STAT_RX_PACKET_1024_1518_BYTES = STAT_RX_PACKET_1024_1518_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_128_255_BYTES = STAT_RX_PACKET_128_255_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_1519_1522_BYTES = STAT_RX_PACKET_1519_1522_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_1523_1548_BYTES = STAT_RX_PACKET_1523_1548_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_1549_2047_BYTES = STAT_RX_PACKET_1549_2047_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_2048_4095_BYTES = STAT_RX_PACKET_2048_4095_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_256_511_BYTES = STAT_RX_PACKET_256_511_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_4096_8191_BYTES = STAT_RX_PACKET_4096_8191_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_512_1023_BYTES = STAT_RX_PACKET_512_1023_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_64_BYTES = STAT_RX_PACKET_64_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_65_127_BYTES = STAT_RX_PACKET_65_127_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_8192_9215_BYTES = STAT_RX_PACKET_8192_9215_BYTES_delay;
assign #(out_delay) STAT_RX_PACKET_BAD_FCS = STAT_RX_PACKET_BAD_FCS_delay;
assign #(out_delay) STAT_RX_PACKET_LARGE = STAT_RX_PACKET_LARGE_delay;
assign #(out_delay) STAT_RX_PACKET_SMALL = STAT_RX_PACKET_SMALL_delay;
assign #(out_delay) STAT_RX_PAUSE = STAT_RX_PAUSE_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA0 = STAT_RX_PAUSE_QUANTA0_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA1 = STAT_RX_PAUSE_QUANTA1_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA2 = STAT_RX_PAUSE_QUANTA2_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA3 = STAT_RX_PAUSE_QUANTA3_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA4 = STAT_RX_PAUSE_QUANTA4_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA5 = STAT_RX_PAUSE_QUANTA5_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA6 = STAT_RX_PAUSE_QUANTA6_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA7 = STAT_RX_PAUSE_QUANTA7_delay;
assign #(out_delay) STAT_RX_PAUSE_QUANTA8 = STAT_RX_PAUSE_QUANTA8_delay;
assign #(out_delay) STAT_RX_PAUSE_REQ = STAT_RX_PAUSE_REQ_delay;
assign #(out_delay) STAT_RX_PAUSE_VALID = STAT_RX_PAUSE_VALID_delay;
assign #(out_delay) STAT_RX_RECEIVED_LOCAL_FAULT = STAT_RX_RECEIVED_LOCAL_FAULT_delay;
assign #(out_delay) STAT_RX_REMOTE_FAULT = STAT_RX_REMOTE_FAULT_delay;
assign #(out_delay) STAT_RX_STATUS = STAT_RX_STATUS_delay;
assign #(out_delay) STAT_RX_STOMPED_FCS = STAT_RX_STOMPED_FCS_delay;
assign #(out_delay) STAT_RX_SYNCED = STAT_RX_SYNCED_delay;
assign #(out_delay) STAT_RX_SYNCED_ERR = STAT_RX_SYNCED_ERR_delay;
assign #(out_delay) STAT_RX_TEST_PATTERN_MISMATCH = STAT_RX_TEST_PATTERN_MISMATCH_delay;
assign #(out_delay) STAT_RX_TOOLONG = STAT_RX_TOOLONG_delay;
assign #(out_delay) STAT_RX_TOTAL_BYTES = STAT_RX_TOTAL_BYTES_delay;
assign #(out_delay) STAT_RX_TOTAL_GOOD_BYTES = STAT_RX_TOTAL_GOOD_BYTES_delay;
assign #(out_delay) STAT_RX_TOTAL_GOOD_PACKETS = STAT_RX_TOTAL_GOOD_PACKETS_delay;
assign #(out_delay) STAT_RX_TOTAL_PACKETS = STAT_RX_TOTAL_PACKETS_delay;
assign #(out_delay) STAT_RX_TRUNCATED = STAT_RX_TRUNCATED_delay;
assign #(out_delay) STAT_RX_UNDERSIZE = STAT_RX_UNDERSIZE_delay;
assign #(out_delay) STAT_RX_UNICAST = STAT_RX_UNICAST_delay;
assign #(out_delay) STAT_RX_USER_PAUSE = STAT_RX_USER_PAUSE_delay;
assign #(out_delay) STAT_RX_VLAN = STAT_RX_VLAN_delay;
assign #(out_delay) STAT_RX_VL_DEMUXED = STAT_RX_VL_DEMUXED_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_0 = STAT_RX_VL_NUMBER_0_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_1 = STAT_RX_VL_NUMBER_1_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_10 = STAT_RX_VL_NUMBER_10_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_11 = STAT_RX_VL_NUMBER_11_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_12 = STAT_RX_VL_NUMBER_12_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_13 = STAT_RX_VL_NUMBER_13_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_14 = STAT_RX_VL_NUMBER_14_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_15 = STAT_RX_VL_NUMBER_15_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_16 = STAT_RX_VL_NUMBER_16_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_17 = STAT_RX_VL_NUMBER_17_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_18 = STAT_RX_VL_NUMBER_18_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_19 = STAT_RX_VL_NUMBER_19_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_2 = STAT_RX_VL_NUMBER_2_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_3 = STAT_RX_VL_NUMBER_3_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_4 = STAT_RX_VL_NUMBER_4_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_5 = STAT_RX_VL_NUMBER_5_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_6 = STAT_RX_VL_NUMBER_6_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_7 = STAT_RX_VL_NUMBER_7_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_8 = STAT_RX_VL_NUMBER_8_delay;
assign #(out_delay) STAT_RX_VL_NUMBER_9 = STAT_RX_VL_NUMBER_9_delay;
assign #(out_delay) STAT_TX_BAD_FCS = STAT_TX_BAD_FCS_delay;
assign #(out_delay) STAT_TX_BROADCAST = STAT_TX_BROADCAST_delay;
assign #(out_delay) STAT_TX_FRAME_ERROR = STAT_TX_FRAME_ERROR_delay;
assign #(out_delay) STAT_TX_LOCAL_FAULT = STAT_TX_LOCAL_FAULT_delay;
assign #(out_delay) STAT_TX_MULTICAST = STAT_TX_MULTICAST_delay;
assign #(out_delay) STAT_TX_PACKET_1024_1518_BYTES = STAT_TX_PACKET_1024_1518_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_128_255_BYTES = STAT_TX_PACKET_128_255_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_1519_1522_BYTES = STAT_TX_PACKET_1519_1522_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_1523_1548_BYTES = STAT_TX_PACKET_1523_1548_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_1549_2047_BYTES = STAT_TX_PACKET_1549_2047_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_2048_4095_BYTES = STAT_TX_PACKET_2048_4095_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_256_511_BYTES = STAT_TX_PACKET_256_511_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_4096_8191_BYTES = STAT_TX_PACKET_4096_8191_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_512_1023_BYTES = STAT_TX_PACKET_512_1023_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_64_BYTES = STAT_TX_PACKET_64_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_65_127_BYTES = STAT_TX_PACKET_65_127_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_8192_9215_BYTES = STAT_TX_PACKET_8192_9215_BYTES_delay;
assign #(out_delay) STAT_TX_PACKET_LARGE = STAT_TX_PACKET_LARGE_delay;
assign #(out_delay) STAT_TX_PACKET_SMALL = STAT_TX_PACKET_SMALL_delay;
assign #(out_delay) STAT_TX_PAUSE = STAT_TX_PAUSE_delay;
assign #(out_delay) STAT_TX_PAUSE_VALID = STAT_TX_PAUSE_VALID_delay;
assign #(out_delay) STAT_TX_PTP_FIFO_READ_ERROR = STAT_TX_PTP_FIFO_READ_ERROR_delay;
assign #(out_delay) STAT_TX_PTP_FIFO_WRITE_ERROR = STAT_TX_PTP_FIFO_WRITE_ERROR_delay;
assign #(out_delay) STAT_TX_TOTAL_BYTES = STAT_TX_TOTAL_BYTES_delay;
assign #(out_delay) STAT_TX_TOTAL_GOOD_BYTES = STAT_TX_TOTAL_GOOD_BYTES_delay;
assign #(out_delay) STAT_TX_TOTAL_GOOD_PACKETS = STAT_TX_TOTAL_GOOD_PACKETS_delay;
assign #(out_delay) STAT_TX_TOTAL_PACKETS = STAT_TX_TOTAL_PACKETS_delay;
assign #(out_delay) STAT_TX_UNICAST = STAT_TX_UNICAST_delay;
assign #(out_delay) STAT_TX_USER_PAUSE = STAT_TX_USER_PAUSE_delay;
assign #(out_delay) STAT_TX_VLAN = STAT_TX_VLAN_delay;
assign #(out_delay) TX_OVFOUT = TX_OVFOUT_delay;
assign #(out_delay) TX_PTP_PCSLANE_OUT = TX_PTP_PCSLANE_OUT_delay;
assign #(out_delay) TX_PTP_TSTAMP_OUT = TX_PTP_TSTAMP_OUT_delay;
assign #(out_delay) TX_PTP_TSTAMP_TAG_OUT = TX_PTP_TSTAMP_TAG_OUT_delay;
assign #(out_delay) TX_PTP_TSTAMP_VALID_OUT = TX_PTP_TSTAMP_VALID_OUT_delay;
assign #(out_delay) TX_RDYOUT = TX_RDYOUT_delay;
assign #(out_delay) TX_SERDES_ALT_DATA0 = TX_SERDES_ALT_DATA0_delay;
assign #(out_delay) TX_SERDES_ALT_DATA1 = TX_SERDES_ALT_DATA1_delay;
assign #(out_delay) TX_SERDES_ALT_DATA2 = TX_SERDES_ALT_DATA2_delay;
assign #(out_delay) TX_SERDES_ALT_DATA3 = TX_SERDES_ALT_DATA3_delay;
assign #(out_delay) TX_SERDES_DATA0 = TX_SERDES_DATA0_delay;
assign #(out_delay) TX_SERDES_DATA1 = TX_SERDES_DATA1_delay;
assign #(out_delay) TX_SERDES_DATA2 = TX_SERDES_DATA2_delay;
assign #(out_delay) TX_SERDES_DATA3 = TX_SERDES_DATA3_delay;
assign #(out_delay) TX_SERDES_DATA4 = TX_SERDES_DATA4_delay;
assign #(out_delay) TX_SERDES_DATA5 = TX_SERDES_DATA5_delay;
assign #(out_delay) TX_SERDES_DATA6 = TX_SERDES_DATA6_delay;
assign #(out_delay) TX_SERDES_DATA7 = TX_SERDES_DATA7_delay;
assign #(out_delay) TX_SERDES_DATA8 = TX_SERDES_DATA8_delay;
assign #(out_delay) TX_SERDES_DATA9 = TX_SERDES_DATA9_delay;
assign #(out_delay) TX_UNFOUT = TX_UNFOUT_delay;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRP_CLK_delay = DRP_CLK;
assign #(inclk_delay) RX_CLK_delay = RX_CLK;
assign #(inclk_delay) TX_CLK_delay = TX_CLK;
assign #(in_delay) CTL_CAUI4_MODE_delay = CTL_CAUI4_MODE;
assign #(in_delay) CTL_RX_CHECK_ETYPE_GCP_delay = CTL_RX_CHECK_ETYPE_GCP;
assign #(in_delay) CTL_RX_CHECK_ETYPE_GPP_delay = CTL_RX_CHECK_ETYPE_GPP;
assign #(in_delay) CTL_RX_CHECK_ETYPE_PCP_delay = CTL_RX_CHECK_ETYPE_PCP;
assign #(in_delay) CTL_RX_CHECK_ETYPE_PPP_delay = CTL_RX_CHECK_ETYPE_PPP;
assign #(in_delay) CTL_RX_CHECK_MCAST_GCP_delay = CTL_RX_CHECK_MCAST_GCP;
assign #(in_delay) CTL_RX_CHECK_MCAST_GPP_delay = CTL_RX_CHECK_MCAST_GPP;
assign #(in_delay) CTL_RX_CHECK_MCAST_PCP_delay = CTL_RX_CHECK_MCAST_PCP;
assign #(in_delay) CTL_RX_CHECK_MCAST_PPP_delay = CTL_RX_CHECK_MCAST_PPP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_GCP_delay = CTL_RX_CHECK_OPCODE_GCP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_GPP_delay = CTL_RX_CHECK_OPCODE_GPP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_PCP_delay = CTL_RX_CHECK_OPCODE_PCP;
assign #(in_delay) CTL_RX_CHECK_OPCODE_PPP_delay = CTL_RX_CHECK_OPCODE_PPP;
assign #(in_delay) CTL_RX_CHECK_SA_GCP_delay = CTL_RX_CHECK_SA_GCP;
assign #(in_delay) CTL_RX_CHECK_SA_GPP_delay = CTL_RX_CHECK_SA_GPP;
assign #(in_delay) CTL_RX_CHECK_SA_PCP_delay = CTL_RX_CHECK_SA_PCP;
assign #(in_delay) CTL_RX_CHECK_SA_PPP_delay = CTL_RX_CHECK_SA_PPP;
assign #(in_delay) CTL_RX_CHECK_UCAST_GCP_delay = CTL_RX_CHECK_UCAST_GCP;
assign #(in_delay) CTL_RX_CHECK_UCAST_GPP_delay = CTL_RX_CHECK_UCAST_GPP;
assign #(in_delay) CTL_RX_CHECK_UCAST_PCP_delay = CTL_RX_CHECK_UCAST_PCP;
assign #(in_delay) CTL_RX_CHECK_UCAST_PPP_delay = CTL_RX_CHECK_UCAST_PPP;
assign #(in_delay) CTL_RX_ENABLE_GCP_delay = CTL_RX_ENABLE_GCP;
assign #(in_delay) CTL_RX_ENABLE_GPP_delay = CTL_RX_ENABLE_GPP;
assign #(in_delay) CTL_RX_ENABLE_PCP_delay = CTL_RX_ENABLE_PCP;
assign #(in_delay) CTL_RX_ENABLE_PPP_delay = CTL_RX_ENABLE_PPP;
assign #(in_delay) CTL_RX_ENABLE_delay = CTL_RX_ENABLE;
assign #(in_delay) CTL_RX_FORCE_RESYNC_delay = CTL_RX_FORCE_RESYNC;
assign #(in_delay) CTL_RX_PAUSE_ACK_delay = CTL_RX_PAUSE_ACK;
assign #(in_delay) CTL_RX_PAUSE_ENABLE_delay = CTL_RX_PAUSE_ENABLE;
assign #(in_delay) CTL_RX_SYSTEMTIMERIN_delay = CTL_RX_SYSTEMTIMERIN;
assign #(in_delay) CTL_RX_TEST_PATTERN_delay = CTL_RX_TEST_PATTERN;
assign #(in_delay) CTL_TX_ENABLE_delay = CTL_TX_ENABLE;
assign #(in_delay) CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE;
assign #(in_delay) CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay = CTL_TX_LANE0_VLM_BIP7_OVERRIDE;
assign #(in_delay) CTL_TX_PAUSE_ENABLE_delay = CTL_TX_PAUSE_ENABLE;
assign #(in_delay) CTL_TX_PAUSE_QUANTA0_delay = CTL_TX_PAUSE_QUANTA0;
assign #(in_delay) CTL_TX_PAUSE_QUANTA1_delay = CTL_TX_PAUSE_QUANTA1;
assign #(in_delay) CTL_TX_PAUSE_QUANTA2_delay = CTL_TX_PAUSE_QUANTA2;
assign #(in_delay) CTL_TX_PAUSE_QUANTA3_delay = CTL_TX_PAUSE_QUANTA3;
assign #(in_delay) CTL_TX_PAUSE_QUANTA4_delay = CTL_TX_PAUSE_QUANTA4;
assign #(in_delay) CTL_TX_PAUSE_QUANTA5_delay = CTL_TX_PAUSE_QUANTA5;
assign #(in_delay) CTL_TX_PAUSE_QUANTA6_delay = CTL_TX_PAUSE_QUANTA6;
assign #(in_delay) CTL_TX_PAUSE_QUANTA7_delay = CTL_TX_PAUSE_QUANTA7;
assign #(in_delay) CTL_TX_PAUSE_QUANTA8_delay = CTL_TX_PAUSE_QUANTA8;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER0_delay = CTL_TX_PAUSE_REFRESH_TIMER0;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER1_delay = CTL_TX_PAUSE_REFRESH_TIMER1;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER2_delay = CTL_TX_PAUSE_REFRESH_TIMER2;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER3_delay = CTL_TX_PAUSE_REFRESH_TIMER3;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER4_delay = CTL_TX_PAUSE_REFRESH_TIMER4;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER5_delay = CTL_TX_PAUSE_REFRESH_TIMER5;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER6_delay = CTL_TX_PAUSE_REFRESH_TIMER6;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER7_delay = CTL_TX_PAUSE_REFRESH_TIMER7;
assign #(in_delay) CTL_TX_PAUSE_REFRESH_TIMER8_delay = CTL_TX_PAUSE_REFRESH_TIMER8;
assign #(in_delay) CTL_TX_PAUSE_REQ_delay = CTL_TX_PAUSE_REQ;
assign #(in_delay) CTL_TX_PTP_VLANE_ADJUST_MODE_delay = CTL_TX_PTP_VLANE_ADJUST_MODE;
assign #(in_delay) CTL_TX_RESEND_PAUSE_delay = CTL_TX_RESEND_PAUSE;
assign #(in_delay) CTL_TX_SEND_IDLE_delay = CTL_TX_SEND_IDLE;
assign #(in_delay) CTL_TX_SEND_RFI_delay = CTL_TX_SEND_RFI;
assign #(in_delay) CTL_TX_SYSTEMTIMERIN_delay = CTL_TX_SYSTEMTIMERIN;
assign #(in_delay) CTL_TX_TEST_PATTERN_delay = CTL_TX_TEST_PATTERN;
assign #(in_delay) DRP_ADDR_delay = DRP_ADDR;
assign #(in_delay) DRP_DI_delay = DRP_DI;
assign #(in_delay) DRP_EN_delay = DRP_EN;
assign #(in_delay) DRP_WE_delay = DRP_WE;
assign #(in_delay) RX_RESET_delay = RX_RESET;
assign #(in_delay) RX_SERDES_ALT_DATA0_delay = RX_SERDES_ALT_DATA0;
assign #(in_delay) RX_SERDES_ALT_DATA1_delay = RX_SERDES_ALT_DATA1;
assign #(in_delay) RX_SERDES_ALT_DATA2_delay = RX_SERDES_ALT_DATA2;
assign #(in_delay) RX_SERDES_ALT_DATA3_delay = RX_SERDES_ALT_DATA3;
assign #(in_delay) RX_SERDES_DATA0_delay = RX_SERDES_DATA0;
assign #(in_delay) RX_SERDES_DATA1_delay = RX_SERDES_DATA1;
assign #(in_delay) RX_SERDES_DATA2_delay = RX_SERDES_DATA2;
assign #(in_delay) RX_SERDES_DATA3_delay = RX_SERDES_DATA3;
assign #(in_delay) RX_SERDES_DATA4_delay = RX_SERDES_DATA4;
assign #(in_delay) RX_SERDES_DATA5_delay = RX_SERDES_DATA5;
assign #(in_delay) RX_SERDES_DATA6_delay = RX_SERDES_DATA6;
assign #(in_delay) RX_SERDES_DATA7_delay = RX_SERDES_DATA7;
assign #(in_delay) RX_SERDES_DATA8_delay = RX_SERDES_DATA8;
assign #(in_delay) RX_SERDES_DATA9_delay = RX_SERDES_DATA9;
assign #(in_delay) RX_SERDES_RESET_delay = RX_SERDES_RESET;
assign #(in_delay) TX_DATAIN0_delay = TX_DATAIN0;
assign #(in_delay) TX_DATAIN1_delay = TX_DATAIN1;
assign #(in_delay) TX_DATAIN2_delay = TX_DATAIN2;
assign #(in_delay) TX_DATAIN3_delay = TX_DATAIN3;
assign #(in_delay) TX_ENAIN0_delay = TX_ENAIN0;
assign #(in_delay) TX_ENAIN1_delay = TX_ENAIN1;
assign #(in_delay) TX_ENAIN2_delay = TX_ENAIN2;
assign #(in_delay) TX_ENAIN3_delay = TX_ENAIN3;
assign #(in_delay) TX_EOPIN0_delay = TX_EOPIN0;
assign #(in_delay) TX_EOPIN1_delay = TX_EOPIN1;
assign #(in_delay) TX_EOPIN2_delay = TX_EOPIN2;
assign #(in_delay) TX_EOPIN3_delay = TX_EOPIN3;
assign #(in_delay) TX_ERRIN0_delay = TX_ERRIN0;
assign #(in_delay) TX_ERRIN1_delay = TX_ERRIN1;
assign #(in_delay) TX_ERRIN2_delay = TX_ERRIN2;
assign #(in_delay) TX_ERRIN3_delay = TX_ERRIN3;
assign #(in_delay) TX_MTYIN0_delay = TX_MTYIN0;
assign #(in_delay) TX_MTYIN1_delay = TX_MTYIN1;
assign #(in_delay) TX_MTYIN2_delay = TX_MTYIN2;
assign #(in_delay) TX_MTYIN3_delay = TX_MTYIN3;
assign #(in_delay) TX_PTP_1588OP_IN_delay = TX_PTP_1588OP_IN;
assign #(in_delay) TX_PTP_CHKSUM_OFFSET_IN_delay = TX_PTP_CHKSUM_OFFSET_IN;
assign #(in_delay) TX_PTP_RXTSTAMP_IN_delay = TX_PTP_RXTSTAMP_IN;
assign #(in_delay) TX_PTP_TAG_FIELD_IN_delay = TX_PTP_TAG_FIELD_IN;
assign #(in_delay) TX_PTP_TSTAMP_OFFSET_IN_delay = TX_PTP_TSTAMP_OFFSET_IN;
assign #(in_delay) TX_PTP_UPD_CHKSUM_IN_delay = TX_PTP_UPD_CHKSUM_IN;
assign #(in_delay) TX_RESET_delay = TX_RESET;
assign #(in_delay) TX_SOPIN0_delay = TX_SOPIN0;
assign #(in_delay) TX_SOPIN1_delay = TX_SOPIN1;
assign #(in_delay) TX_SOPIN2_delay = TX_SOPIN2;
assign #(in_delay) TX_SOPIN3_delay = TX_SOPIN3;
`endif
// inputs with no timing checks
assign #(inclk_delay) RX_SERDES_CLK_delay = RX_SERDES_CLK;
assign DRP_DO_delay = DRP_DO_out;
assign DRP_RDY_delay = DRP_RDY_out;
assign RX_DATAOUT0_delay = RX_DATAOUT0_out;
assign RX_DATAOUT1_delay = RX_DATAOUT1_out;
assign RX_DATAOUT2_delay = RX_DATAOUT2_out;
assign RX_DATAOUT3_delay = RX_DATAOUT3_out;
assign RX_ENAOUT0_delay = RX_ENAOUT0_out;
assign RX_ENAOUT1_delay = RX_ENAOUT1_out;
assign RX_ENAOUT2_delay = RX_ENAOUT2_out;
assign RX_ENAOUT3_delay = RX_ENAOUT3_out;
assign RX_EOPOUT0_delay = RX_EOPOUT0_out;
assign RX_EOPOUT1_delay = RX_EOPOUT1_out;
assign RX_EOPOUT2_delay = RX_EOPOUT2_out;
assign RX_EOPOUT3_delay = RX_EOPOUT3_out;
assign RX_ERROUT0_delay = RX_ERROUT0_out;
assign RX_ERROUT1_delay = RX_ERROUT1_out;
assign RX_ERROUT2_delay = RX_ERROUT2_out;
assign RX_ERROUT3_delay = RX_ERROUT3_out;
assign RX_LANE_ALIGNER_FILL_0_delay = RX_LANE_ALIGNER_FILL_0_out;
assign RX_LANE_ALIGNER_FILL_10_delay = RX_LANE_ALIGNER_FILL_10_out;
assign RX_LANE_ALIGNER_FILL_11_delay = RX_LANE_ALIGNER_FILL_11_out;
assign RX_LANE_ALIGNER_FILL_12_delay = RX_LANE_ALIGNER_FILL_12_out;
assign RX_LANE_ALIGNER_FILL_13_delay = RX_LANE_ALIGNER_FILL_13_out;
assign RX_LANE_ALIGNER_FILL_14_delay = RX_LANE_ALIGNER_FILL_14_out;
assign RX_LANE_ALIGNER_FILL_15_delay = RX_LANE_ALIGNER_FILL_15_out;
assign RX_LANE_ALIGNER_FILL_16_delay = RX_LANE_ALIGNER_FILL_16_out;
assign RX_LANE_ALIGNER_FILL_17_delay = RX_LANE_ALIGNER_FILL_17_out;
assign RX_LANE_ALIGNER_FILL_18_delay = RX_LANE_ALIGNER_FILL_18_out;
assign RX_LANE_ALIGNER_FILL_19_delay = RX_LANE_ALIGNER_FILL_19_out;
assign RX_LANE_ALIGNER_FILL_1_delay = RX_LANE_ALIGNER_FILL_1_out;
assign RX_LANE_ALIGNER_FILL_2_delay = RX_LANE_ALIGNER_FILL_2_out;
assign RX_LANE_ALIGNER_FILL_3_delay = RX_LANE_ALIGNER_FILL_3_out;
assign RX_LANE_ALIGNER_FILL_4_delay = RX_LANE_ALIGNER_FILL_4_out;
assign RX_LANE_ALIGNER_FILL_5_delay = RX_LANE_ALIGNER_FILL_5_out;
assign RX_LANE_ALIGNER_FILL_6_delay = RX_LANE_ALIGNER_FILL_6_out;
assign RX_LANE_ALIGNER_FILL_7_delay = RX_LANE_ALIGNER_FILL_7_out;
assign RX_LANE_ALIGNER_FILL_8_delay = RX_LANE_ALIGNER_FILL_8_out;
assign RX_LANE_ALIGNER_FILL_9_delay = RX_LANE_ALIGNER_FILL_9_out;
assign RX_MTYOUT0_delay = RX_MTYOUT0_out;
assign RX_MTYOUT1_delay = RX_MTYOUT1_out;
assign RX_MTYOUT2_delay = RX_MTYOUT2_out;
assign RX_MTYOUT3_delay = RX_MTYOUT3_out;
assign RX_PTP_PCSLANE_OUT_delay = RX_PTP_PCSLANE_OUT_out;
assign RX_PTP_TSTAMP_OUT_delay = RX_PTP_TSTAMP_OUT_out;
assign RX_SOPOUT0_delay = RX_SOPOUT0_out;
assign RX_SOPOUT1_delay = RX_SOPOUT1_out;
assign RX_SOPOUT2_delay = RX_SOPOUT2_out;
assign RX_SOPOUT3_delay = RX_SOPOUT3_out;
assign STAT_RX_ALIGNED_ERR_delay = STAT_RX_ALIGNED_ERR_out;
assign STAT_RX_ALIGNED_delay = STAT_RX_ALIGNED_out;
assign STAT_RX_BAD_CODE_delay = STAT_RX_BAD_CODE_out;
assign STAT_RX_BAD_FCS_delay = STAT_RX_BAD_FCS_out;
assign STAT_RX_BAD_PREAMBLE_delay = STAT_RX_BAD_PREAMBLE_out;
assign STAT_RX_BAD_SFD_delay = STAT_RX_BAD_SFD_out;
assign STAT_RX_BIP_ERR_0_delay = STAT_RX_BIP_ERR_0_out;
assign STAT_RX_BIP_ERR_10_delay = STAT_RX_BIP_ERR_10_out;
assign STAT_RX_BIP_ERR_11_delay = STAT_RX_BIP_ERR_11_out;
assign STAT_RX_BIP_ERR_12_delay = STAT_RX_BIP_ERR_12_out;
assign STAT_RX_BIP_ERR_13_delay = STAT_RX_BIP_ERR_13_out;
assign STAT_RX_BIP_ERR_14_delay = STAT_RX_BIP_ERR_14_out;
assign STAT_RX_BIP_ERR_15_delay = STAT_RX_BIP_ERR_15_out;
assign STAT_RX_BIP_ERR_16_delay = STAT_RX_BIP_ERR_16_out;
assign STAT_RX_BIP_ERR_17_delay = STAT_RX_BIP_ERR_17_out;
assign STAT_RX_BIP_ERR_18_delay = STAT_RX_BIP_ERR_18_out;
assign STAT_RX_BIP_ERR_19_delay = STAT_RX_BIP_ERR_19_out;
assign STAT_RX_BIP_ERR_1_delay = STAT_RX_BIP_ERR_1_out;
assign STAT_RX_BIP_ERR_2_delay = STAT_RX_BIP_ERR_2_out;
assign STAT_RX_BIP_ERR_3_delay = STAT_RX_BIP_ERR_3_out;
assign STAT_RX_BIP_ERR_4_delay = STAT_RX_BIP_ERR_4_out;
assign STAT_RX_BIP_ERR_5_delay = STAT_RX_BIP_ERR_5_out;
assign STAT_RX_BIP_ERR_6_delay = STAT_RX_BIP_ERR_6_out;
assign STAT_RX_BIP_ERR_7_delay = STAT_RX_BIP_ERR_7_out;
assign STAT_RX_BIP_ERR_8_delay = STAT_RX_BIP_ERR_8_out;
assign STAT_RX_BIP_ERR_9_delay = STAT_RX_BIP_ERR_9_out;
assign STAT_RX_BLOCK_LOCK_delay = STAT_RX_BLOCK_LOCK_out;
assign STAT_RX_BROADCAST_delay = STAT_RX_BROADCAST_out;
assign STAT_RX_FRAGMENT_delay = STAT_RX_FRAGMENT_out;
assign STAT_RX_FRAMING_ERR_0_delay = STAT_RX_FRAMING_ERR_0_out;
assign STAT_RX_FRAMING_ERR_10_delay = STAT_RX_FRAMING_ERR_10_out;
assign STAT_RX_FRAMING_ERR_11_delay = STAT_RX_FRAMING_ERR_11_out;
assign STAT_RX_FRAMING_ERR_12_delay = STAT_RX_FRAMING_ERR_12_out;
assign STAT_RX_FRAMING_ERR_13_delay = STAT_RX_FRAMING_ERR_13_out;
assign STAT_RX_FRAMING_ERR_14_delay = STAT_RX_FRAMING_ERR_14_out;
assign STAT_RX_FRAMING_ERR_15_delay = STAT_RX_FRAMING_ERR_15_out;
assign STAT_RX_FRAMING_ERR_16_delay = STAT_RX_FRAMING_ERR_16_out;
assign STAT_RX_FRAMING_ERR_17_delay = STAT_RX_FRAMING_ERR_17_out;
assign STAT_RX_FRAMING_ERR_18_delay = STAT_RX_FRAMING_ERR_18_out;
assign STAT_RX_FRAMING_ERR_19_delay = STAT_RX_FRAMING_ERR_19_out;
assign STAT_RX_FRAMING_ERR_1_delay = STAT_RX_FRAMING_ERR_1_out;
assign STAT_RX_FRAMING_ERR_2_delay = STAT_RX_FRAMING_ERR_2_out;
assign STAT_RX_FRAMING_ERR_3_delay = STAT_RX_FRAMING_ERR_3_out;
assign STAT_RX_FRAMING_ERR_4_delay = STAT_RX_FRAMING_ERR_4_out;
assign STAT_RX_FRAMING_ERR_5_delay = STAT_RX_FRAMING_ERR_5_out;
assign STAT_RX_FRAMING_ERR_6_delay = STAT_RX_FRAMING_ERR_6_out;
assign STAT_RX_FRAMING_ERR_7_delay = STAT_RX_FRAMING_ERR_7_out;
assign STAT_RX_FRAMING_ERR_8_delay = STAT_RX_FRAMING_ERR_8_out;
assign STAT_RX_FRAMING_ERR_9_delay = STAT_RX_FRAMING_ERR_9_out;
assign STAT_RX_FRAMING_ERR_VALID_0_delay = STAT_RX_FRAMING_ERR_VALID_0_out;
assign STAT_RX_FRAMING_ERR_VALID_10_delay = STAT_RX_FRAMING_ERR_VALID_10_out;
assign STAT_RX_FRAMING_ERR_VALID_11_delay = STAT_RX_FRAMING_ERR_VALID_11_out;
assign STAT_RX_FRAMING_ERR_VALID_12_delay = STAT_RX_FRAMING_ERR_VALID_12_out;
assign STAT_RX_FRAMING_ERR_VALID_13_delay = STAT_RX_FRAMING_ERR_VALID_13_out;
assign STAT_RX_FRAMING_ERR_VALID_14_delay = STAT_RX_FRAMING_ERR_VALID_14_out;
assign STAT_RX_FRAMING_ERR_VALID_15_delay = STAT_RX_FRAMING_ERR_VALID_15_out;
assign STAT_RX_FRAMING_ERR_VALID_16_delay = STAT_RX_FRAMING_ERR_VALID_16_out;
assign STAT_RX_FRAMING_ERR_VALID_17_delay = STAT_RX_FRAMING_ERR_VALID_17_out;
assign STAT_RX_FRAMING_ERR_VALID_18_delay = STAT_RX_FRAMING_ERR_VALID_18_out;
assign STAT_RX_FRAMING_ERR_VALID_19_delay = STAT_RX_FRAMING_ERR_VALID_19_out;
assign STAT_RX_FRAMING_ERR_VALID_1_delay = STAT_RX_FRAMING_ERR_VALID_1_out;
assign STAT_RX_FRAMING_ERR_VALID_2_delay = STAT_RX_FRAMING_ERR_VALID_2_out;
assign STAT_RX_FRAMING_ERR_VALID_3_delay = STAT_RX_FRAMING_ERR_VALID_3_out;
assign STAT_RX_FRAMING_ERR_VALID_4_delay = STAT_RX_FRAMING_ERR_VALID_4_out;
assign STAT_RX_FRAMING_ERR_VALID_5_delay = STAT_RX_FRAMING_ERR_VALID_5_out;
assign STAT_RX_FRAMING_ERR_VALID_6_delay = STAT_RX_FRAMING_ERR_VALID_6_out;
assign STAT_RX_FRAMING_ERR_VALID_7_delay = STAT_RX_FRAMING_ERR_VALID_7_out;
assign STAT_RX_FRAMING_ERR_VALID_8_delay = STAT_RX_FRAMING_ERR_VALID_8_out;
assign STAT_RX_FRAMING_ERR_VALID_9_delay = STAT_RX_FRAMING_ERR_VALID_9_out;
assign STAT_RX_GOT_SIGNAL_OS_delay = STAT_RX_GOT_SIGNAL_OS_out;
assign STAT_RX_HI_BER_delay = STAT_RX_HI_BER_out;
assign STAT_RX_INRANGEERR_delay = STAT_RX_INRANGEERR_out;
assign STAT_RX_INTERNAL_LOCAL_FAULT_delay = STAT_RX_INTERNAL_LOCAL_FAULT_out;
assign STAT_RX_JABBER_delay = STAT_RX_JABBER_out;
assign STAT_RX_LANE0_VLM_BIP7_VALID_delay = STAT_RX_LANE0_VLM_BIP7_VALID_out;
assign STAT_RX_LANE0_VLM_BIP7_delay = STAT_RX_LANE0_VLM_BIP7_out;
assign STAT_RX_LOCAL_FAULT_delay = STAT_RX_LOCAL_FAULT_out;
assign STAT_RX_MF_ERR_delay = STAT_RX_MF_ERR_out;
assign STAT_RX_MF_LEN_ERR_delay = STAT_RX_MF_LEN_ERR_out;
assign STAT_RX_MF_REPEAT_ERR_delay = STAT_RX_MF_REPEAT_ERR_out;
assign STAT_RX_MISALIGNED_delay = STAT_RX_MISALIGNED_out;
assign STAT_RX_MULTICAST_delay = STAT_RX_MULTICAST_out;
assign STAT_RX_OVERSIZE_delay = STAT_RX_OVERSIZE_out;
assign STAT_RX_PACKET_1024_1518_BYTES_delay = STAT_RX_PACKET_1024_1518_BYTES_out;
assign STAT_RX_PACKET_128_255_BYTES_delay = STAT_RX_PACKET_128_255_BYTES_out;
assign STAT_RX_PACKET_1519_1522_BYTES_delay = STAT_RX_PACKET_1519_1522_BYTES_out;
assign STAT_RX_PACKET_1523_1548_BYTES_delay = STAT_RX_PACKET_1523_1548_BYTES_out;
assign STAT_RX_PACKET_1549_2047_BYTES_delay = STAT_RX_PACKET_1549_2047_BYTES_out;
assign STAT_RX_PACKET_2048_4095_BYTES_delay = STAT_RX_PACKET_2048_4095_BYTES_out;
assign STAT_RX_PACKET_256_511_BYTES_delay = STAT_RX_PACKET_256_511_BYTES_out;
assign STAT_RX_PACKET_4096_8191_BYTES_delay = STAT_RX_PACKET_4096_8191_BYTES_out;
assign STAT_RX_PACKET_512_1023_BYTES_delay = STAT_RX_PACKET_512_1023_BYTES_out;
assign STAT_RX_PACKET_64_BYTES_delay = STAT_RX_PACKET_64_BYTES_out;
assign STAT_RX_PACKET_65_127_BYTES_delay = STAT_RX_PACKET_65_127_BYTES_out;
assign STAT_RX_PACKET_8192_9215_BYTES_delay = STAT_RX_PACKET_8192_9215_BYTES_out;
assign STAT_RX_PACKET_BAD_FCS_delay = STAT_RX_PACKET_BAD_FCS_out;
assign STAT_RX_PACKET_LARGE_delay = STAT_RX_PACKET_LARGE_out;
assign STAT_RX_PACKET_SMALL_delay = STAT_RX_PACKET_SMALL_out;
assign STAT_RX_PAUSE_QUANTA0_delay = STAT_RX_PAUSE_QUANTA0_out;
assign STAT_RX_PAUSE_QUANTA1_delay = STAT_RX_PAUSE_QUANTA1_out;
assign STAT_RX_PAUSE_QUANTA2_delay = STAT_RX_PAUSE_QUANTA2_out;
assign STAT_RX_PAUSE_QUANTA3_delay = STAT_RX_PAUSE_QUANTA3_out;
assign STAT_RX_PAUSE_QUANTA4_delay = STAT_RX_PAUSE_QUANTA4_out;
assign STAT_RX_PAUSE_QUANTA5_delay = STAT_RX_PAUSE_QUANTA5_out;
assign STAT_RX_PAUSE_QUANTA6_delay = STAT_RX_PAUSE_QUANTA6_out;
assign STAT_RX_PAUSE_QUANTA7_delay = STAT_RX_PAUSE_QUANTA7_out;
assign STAT_RX_PAUSE_QUANTA8_delay = STAT_RX_PAUSE_QUANTA8_out;
assign STAT_RX_PAUSE_REQ_delay = STAT_RX_PAUSE_REQ_out;
assign STAT_RX_PAUSE_VALID_delay = STAT_RX_PAUSE_VALID_out;
assign STAT_RX_PAUSE_delay = STAT_RX_PAUSE_out;
assign STAT_RX_RECEIVED_LOCAL_FAULT_delay = STAT_RX_RECEIVED_LOCAL_FAULT_out;
assign STAT_RX_REMOTE_FAULT_delay = STAT_RX_REMOTE_FAULT_out;
assign STAT_RX_STATUS_delay = STAT_RX_STATUS_out;
assign STAT_RX_STOMPED_FCS_delay = STAT_RX_STOMPED_FCS_out;
assign STAT_RX_SYNCED_ERR_delay = STAT_RX_SYNCED_ERR_out;
assign STAT_RX_SYNCED_delay = STAT_RX_SYNCED_out;
assign STAT_RX_TEST_PATTERN_MISMATCH_delay = STAT_RX_TEST_PATTERN_MISMATCH_out;
assign STAT_RX_TOOLONG_delay = STAT_RX_TOOLONG_out;
assign STAT_RX_TOTAL_BYTES_delay = STAT_RX_TOTAL_BYTES_out;
assign STAT_RX_TOTAL_GOOD_BYTES_delay = STAT_RX_TOTAL_GOOD_BYTES_out;
assign STAT_RX_TOTAL_GOOD_PACKETS_delay = STAT_RX_TOTAL_GOOD_PACKETS_out;
assign STAT_RX_TOTAL_PACKETS_delay = STAT_RX_TOTAL_PACKETS_out;
assign STAT_RX_TRUNCATED_delay = STAT_RX_TRUNCATED_out;
assign STAT_RX_UNDERSIZE_delay = STAT_RX_UNDERSIZE_out;
assign STAT_RX_UNICAST_delay = STAT_RX_UNICAST_out;
assign STAT_RX_USER_PAUSE_delay = STAT_RX_USER_PAUSE_out;
assign STAT_RX_VLAN_delay = STAT_RX_VLAN_out;
assign STAT_RX_VL_DEMUXED_delay = STAT_RX_VL_DEMUXED_out;
assign STAT_RX_VL_NUMBER_0_delay = STAT_RX_VL_NUMBER_0_out;
assign STAT_RX_VL_NUMBER_10_delay = STAT_RX_VL_NUMBER_10_out;
assign STAT_RX_VL_NUMBER_11_delay = STAT_RX_VL_NUMBER_11_out;
assign STAT_RX_VL_NUMBER_12_delay = STAT_RX_VL_NUMBER_12_out;
assign STAT_RX_VL_NUMBER_13_delay = STAT_RX_VL_NUMBER_13_out;
assign STAT_RX_VL_NUMBER_14_delay = STAT_RX_VL_NUMBER_14_out;
assign STAT_RX_VL_NUMBER_15_delay = STAT_RX_VL_NUMBER_15_out;
assign STAT_RX_VL_NUMBER_16_delay = STAT_RX_VL_NUMBER_16_out;
assign STAT_RX_VL_NUMBER_17_delay = STAT_RX_VL_NUMBER_17_out;
assign STAT_RX_VL_NUMBER_18_delay = STAT_RX_VL_NUMBER_18_out;
assign STAT_RX_VL_NUMBER_19_delay = STAT_RX_VL_NUMBER_19_out;
assign STAT_RX_VL_NUMBER_1_delay = STAT_RX_VL_NUMBER_1_out;
assign STAT_RX_VL_NUMBER_2_delay = STAT_RX_VL_NUMBER_2_out;
assign STAT_RX_VL_NUMBER_3_delay = STAT_RX_VL_NUMBER_3_out;
assign STAT_RX_VL_NUMBER_4_delay = STAT_RX_VL_NUMBER_4_out;
assign STAT_RX_VL_NUMBER_5_delay = STAT_RX_VL_NUMBER_5_out;
assign STAT_RX_VL_NUMBER_6_delay = STAT_RX_VL_NUMBER_6_out;
assign STAT_RX_VL_NUMBER_7_delay = STAT_RX_VL_NUMBER_7_out;
assign STAT_RX_VL_NUMBER_8_delay = STAT_RX_VL_NUMBER_8_out;
assign STAT_RX_VL_NUMBER_9_delay = STAT_RX_VL_NUMBER_9_out;
assign STAT_TX_BAD_FCS_delay = STAT_TX_BAD_FCS_out;
assign STAT_TX_BROADCAST_delay = STAT_TX_BROADCAST_out;
assign STAT_TX_FRAME_ERROR_delay = STAT_TX_FRAME_ERROR_out;
assign STAT_TX_LOCAL_FAULT_delay = STAT_TX_LOCAL_FAULT_out;
assign STAT_TX_MULTICAST_delay = STAT_TX_MULTICAST_out;
assign STAT_TX_PACKET_1024_1518_BYTES_delay = STAT_TX_PACKET_1024_1518_BYTES_out;
assign STAT_TX_PACKET_128_255_BYTES_delay = STAT_TX_PACKET_128_255_BYTES_out;
assign STAT_TX_PACKET_1519_1522_BYTES_delay = STAT_TX_PACKET_1519_1522_BYTES_out;
assign STAT_TX_PACKET_1523_1548_BYTES_delay = STAT_TX_PACKET_1523_1548_BYTES_out;
assign STAT_TX_PACKET_1549_2047_BYTES_delay = STAT_TX_PACKET_1549_2047_BYTES_out;
assign STAT_TX_PACKET_2048_4095_BYTES_delay = STAT_TX_PACKET_2048_4095_BYTES_out;
assign STAT_TX_PACKET_256_511_BYTES_delay = STAT_TX_PACKET_256_511_BYTES_out;
assign STAT_TX_PACKET_4096_8191_BYTES_delay = STAT_TX_PACKET_4096_8191_BYTES_out;
assign STAT_TX_PACKET_512_1023_BYTES_delay = STAT_TX_PACKET_512_1023_BYTES_out;
assign STAT_TX_PACKET_64_BYTES_delay = STAT_TX_PACKET_64_BYTES_out;
assign STAT_TX_PACKET_65_127_BYTES_delay = STAT_TX_PACKET_65_127_BYTES_out;
assign STAT_TX_PACKET_8192_9215_BYTES_delay = STAT_TX_PACKET_8192_9215_BYTES_out;
assign STAT_TX_PACKET_LARGE_delay = STAT_TX_PACKET_LARGE_out;
assign STAT_TX_PACKET_SMALL_delay = STAT_TX_PACKET_SMALL_out;
assign STAT_TX_PAUSE_VALID_delay = STAT_TX_PAUSE_VALID_out;
assign STAT_TX_PAUSE_delay = STAT_TX_PAUSE_out;
assign STAT_TX_PTP_FIFO_READ_ERROR_delay = STAT_TX_PTP_FIFO_READ_ERROR_out;
assign STAT_TX_PTP_FIFO_WRITE_ERROR_delay = STAT_TX_PTP_FIFO_WRITE_ERROR_out;
assign STAT_TX_TOTAL_BYTES_delay = STAT_TX_TOTAL_BYTES_out;
assign STAT_TX_TOTAL_GOOD_BYTES_delay = STAT_TX_TOTAL_GOOD_BYTES_out;
assign STAT_TX_TOTAL_GOOD_PACKETS_delay = STAT_TX_TOTAL_GOOD_PACKETS_out;
assign STAT_TX_TOTAL_PACKETS_delay = STAT_TX_TOTAL_PACKETS_out;
assign STAT_TX_UNICAST_delay = STAT_TX_UNICAST_out;
assign STAT_TX_USER_PAUSE_delay = STAT_TX_USER_PAUSE_out;
assign STAT_TX_VLAN_delay = STAT_TX_VLAN_out;
assign TX_OVFOUT_delay = TX_OVFOUT_out;
assign TX_PTP_PCSLANE_OUT_delay = TX_PTP_PCSLANE_OUT_out;
assign TX_PTP_TSTAMP_OUT_delay = TX_PTP_TSTAMP_OUT_out;
assign TX_PTP_TSTAMP_TAG_OUT_delay = TX_PTP_TSTAMP_TAG_OUT_out;
assign TX_PTP_TSTAMP_VALID_OUT_delay = TX_PTP_TSTAMP_VALID_OUT_out;
assign TX_RDYOUT_delay = TX_RDYOUT_out;
assign TX_SERDES_ALT_DATA0_delay = TX_SERDES_ALT_DATA0_out;
assign TX_SERDES_ALT_DATA1_delay = TX_SERDES_ALT_DATA1_out;
assign TX_SERDES_ALT_DATA2_delay = TX_SERDES_ALT_DATA2_out;
assign TX_SERDES_ALT_DATA3_delay = TX_SERDES_ALT_DATA3_out;
assign TX_SERDES_DATA0_delay = TX_SERDES_DATA0_out;
assign TX_SERDES_DATA1_delay = TX_SERDES_DATA1_out;
assign TX_SERDES_DATA2_delay = TX_SERDES_DATA2_out;
assign TX_SERDES_DATA3_delay = TX_SERDES_DATA3_out;
assign TX_SERDES_DATA4_delay = TX_SERDES_DATA4_out;
assign TX_SERDES_DATA5_delay = TX_SERDES_DATA5_out;
assign TX_SERDES_DATA6_delay = TX_SERDES_DATA6_out;
assign TX_SERDES_DATA7_delay = TX_SERDES_DATA7_out;
assign TX_SERDES_DATA8_delay = TX_SERDES_DATA8_out;
assign TX_SERDES_DATA9_delay = TX_SERDES_DATA9_out;
assign TX_UNFOUT_delay = TX_UNFOUT_out;
assign CTL_CAUI4_MODE_in = CTL_CAUI4_MODE_delay;
assign CTL_RX_CHECK_ETYPE_GCP_in = CTL_RX_CHECK_ETYPE_GCP_delay;
assign CTL_RX_CHECK_ETYPE_GPP_in = CTL_RX_CHECK_ETYPE_GPP_delay;
assign CTL_RX_CHECK_ETYPE_PCP_in = CTL_RX_CHECK_ETYPE_PCP_delay;
assign CTL_RX_CHECK_ETYPE_PPP_in = CTL_RX_CHECK_ETYPE_PPP_delay;
assign CTL_RX_CHECK_MCAST_GCP_in = CTL_RX_CHECK_MCAST_GCP_delay;
assign CTL_RX_CHECK_MCAST_GPP_in = CTL_RX_CHECK_MCAST_GPP_delay;
assign CTL_RX_CHECK_MCAST_PCP_in = CTL_RX_CHECK_MCAST_PCP_delay;
assign CTL_RX_CHECK_MCAST_PPP_in = CTL_RX_CHECK_MCAST_PPP_delay;
assign CTL_RX_CHECK_OPCODE_GCP_in = CTL_RX_CHECK_OPCODE_GCP_delay;
assign CTL_RX_CHECK_OPCODE_GPP_in = CTL_RX_CHECK_OPCODE_GPP_delay;
assign CTL_RX_CHECK_OPCODE_PCP_in = CTL_RX_CHECK_OPCODE_PCP_delay;
assign CTL_RX_CHECK_OPCODE_PPP_in = CTL_RX_CHECK_OPCODE_PPP_delay;
assign CTL_RX_CHECK_SA_GCP_in = CTL_RX_CHECK_SA_GCP_delay;
assign CTL_RX_CHECK_SA_GPP_in = CTL_RX_CHECK_SA_GPP_delay;
assign CTL_RX_CHECK_SA_PCP_in = CTL_RX_CHECK_SA_PCP_delay;
assign CTL_RX_CHECK_SA_PPP_in = CTL_RX_CHECK_SA_PPP_delay;
assign CTL_RX_CHECK_UCAST_GCP_in = CTL_RX_CHECK_UCAST_GCP_delay;
assign CTL_RX_CHECK_UCAST_GPP_in = CTL_RX_CHECK_UCAST_GPP_delay;
assign CTL_RX_CHECK_UCAST_PCP_in = CTL_RX_CHECK_UCAST_PCP_delay;
assign CTL_RX_CHECK_UCAST_PPP_in = CTL_RX_CHECK_UCAST_PPP_delay;
assign CTL_RX_ENABLE_GCP_in = CTL_RX_ENABLE_GCP_delay;
assign CTL_RX_ENABLE_GPP_in = CTL_RX_ENABLE_GPP_delay;
assign CTL_RX_ENABLE_PCP_in = CTL_RX_ENABLE_PCP_delay;
assign CTL_RX_ENABLE_PPP_in = CTL_RX_ENABLE_PPP_delay;
assign CTL_RX_ENABLE_in = CTL_RX_ENABLE_delay;
assign CTL_RX_FORCE_RESYNC_in = CTL_RX_FORCE_RESYNC_delay;
assign CTL_RX_PAUSE_ACK_in = CTL_RX_PAUSE_ACK_delay;
assign CTL_RX_PAUSE_ENABLE_in = CTL_RX_PAUSE_ENABLE_delay;
assign CTL_RX_SYSTEMTIMERIN_in = CTL_RX_SYSTEMTIMERIN_delay;
assign CTL_RX_TEST_PATTERN_in = CTL_RX_TEST_PATTERN_delay;
assign CTL_TX_ENABLE_in = CTL_TX_ENABLE_delay;
assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay;
assign CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in = CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay;
assign CTL_TX_PAUSE_ENABLE_in = CTL_TX_PAUSE_ENABLE_delay;
assign CTL_TX_PAUSE_QUANTA0_in = CTL_TX_PAUSE_QUANTA0_delay;
assign CTL_TX_PAUSE_QUANTA1_in = CTL_TX_PAUSE_QUANTA1_delay;
assign CTL_TX_PAUSE_QUANTA2_in = CTL_TX_PAUSE_QUANTA2_delay;
assign CTL_TX_PAUSE_QUANTA3_in = CTL_TX_PAUSE_QUANTA3_delay;
assign CTL_TX_PAUSE_QUANTA4_in = CTL_TX_PAUSE_QUANTA4_delay;
assign CTL_TX_PAUSE_QUANTA5_in = CTL_TX_PAUSE_QUANTA5_delay;
assign CTL_TX_PAUSE_QUANTA6_in = CTL_TX_PAUSE_QUANTA6_delay;
assign CTL_TX_PAUSE_QUANTA7_in = CTL_TX_PAUSE_QUANTA7_delay;
assign CTL_TX_PAUSE_QUANTA8_in = CTL_TX_PAUSE_QUANTA8_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER0_in = CTL_TX_PAUSE_REFRESH_TIMER0_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER1_in = CTL_TX_PAUSE_REFRESH_TIMER1_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER2_in = CTL_TX_PAUSE_REFRESH_TIMER2_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER3_in = CTL_TX_PAUSE_REFRESH_TIMER3_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER4_in = CTL_TX_PAUSE_REFRESH_TIMER4_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER5_in = CTL_TX_PAUSE_REFRESH_TIMER5_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER6_in = CTL_TX_PAUSE_REFRESH_TIMER6_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER7_in = CTL_TX_PAUSE_REFRESH_TIMER7_delay;
assign CTL_TX_PAUSE_REFRESH_TIMER8_in = CTL_TX_PAUSE_REFRESH_TIMER8_delay;
assign CTL_TX_PAUSE_REQ_in = CTL_TX_PAUSE_REQ_delay;
assign CTL_TX_PTP_VLANE_ADJUST_MODE_in = CTL_TX_PTP_VLANE_ADJUST_MODE_delay;
assign CTL_TX_RESEND_PAUSE_in = CTL_TX_RESEND_PAUSE_delay;
assign CTL_TX_SEND_IDLE_in = CTL_TX_SEND_IDLE_delay;
assign CTL_TX_SEND_RFI_in = CTL_TX_SEND_RFI_delay;
assign CTL_TX_SYSTEMTIMERIN_in = CTL_TX_SYSTEMTIMERIN_delay;
assign CTL_TX_TEST_PATTERN_in = CTL_TX_TEST_PATTERN_delay;
assign DRP_ADDR_in = DRP_ADDR_delay;
assign DRP_CLK_in = DRP_CLK_delay;
assign DRP_DI_in = DRP_DI_delay;
assign DRP_EN_in = DRP_EN_delay;
assign DRP_WE_in = DRP_WE_delay;
assign RX_CLK_in = RX_CLK_delay;
assign RX_RESET_in = RX_RESET_delay;
assign RX_SERDES_ALT_DATA0_in = RX_SERDES_ALT_DATA0_delay;
assign RX_SERDES_ALT_DATA1_in = RX_SERDES_ALT_DATA1_delay;
assign RX_SERDES_ALT_DATA2_in = RX_SERDES_ALT_DATA2_delay;
assign RX_SERDES_ALT_DATA3_in = RX_SERDES_ALT_DATA3_delay;
assign RX_SERDES_CLK_in = RX_SERDES_CLK_delay;
assign RX_SERDES_DATA0_in = RX_SERDES_DATA0_delay;
assign RX_SERDES_DATA1_in = RX_SERDES_DATA1_delay;
assign RX_SERDES_DATA2_in = RX_SERDES_DATA2_delay;
assign RX_SERDES_DATA3_in = RX_SERDES_DATA3_delay;
assign RX_SERDES_DATA4_in = RX_SERDES_DATA4_delay;
assign RX_SERDES_DATA5_in = RX_SERDES_DATA5_delay;
assign RX_SERDES_DATA6_in = RX_SERDES_DATA6_delay;
assign RX_SERDES_DATA7_in = RX_SERDES_DATA7_delay;
assign RX_SERDES_DATA8_in = RX_SERDES_DATA8_delay;
assign RX_SERDES_DATA9_in = RX_SERDES_DATA9_delay;
assign RX_SERDES_RESET_in = RX_SERDES_RESET_delay;
assign TX_CLK_in = TX_CLK_delay;
assign TX_DATAIN0_in = TX_DATAIN0_delay;
assign TX_DATAIN1_in = TX_DATAIN1_delay;
assign TX_DATAIN2_in = TX_DATAIN2_delay;
assign TX_DATAIN3_in = TX_DATAIN3_delay;
assign TX_ENAIN0_in = TX_ENAIN0_delay;
assign TX_ENAIN1_in = TX_ENAIN1_delay;
assign TX_ENAIN2_in = TX_ENAIN2_delay;
assign TX_ENAIN3_in = TX_ENAIN3_delay;
assign TX_EOPIN0_in = TX_EOPIN0_delay;
assign TX_EOPIN1_in = TX_EOPIN1_delay;
assign TX_EOPIN2_in = TX_EOPIN2_delay;
assign TX_EOPIN3_in = TX_EOPIN3_delay;
assign TX_ERRIN0_in = TX_ERRIN0_delay;
assign TX_ERRIN1_in = TX_ERRIN1_delay;
assign TX_ERRIN2_in = TX_ERRIN2_delay;
assign TX_ERRIN3_in = TX_ERRIN3_delay;
assign TX_MTYIN0_in = TX_MTYIN0_delay;
assign TX_MTYIN1_in = TX_MTYIN1_delay;
assign TX_MTYIN2_in = TX_MTYIN2_delay;
assign TX_MTYIN3_in = TX_MTYIN3_delay;
assign TX_PTP_1588OP_IN_in = TX_PTP_1588OP_IN_delay;
assign TX_PTP_CHKSUM_OFFSET_IN_in = TX_PTP_CHKSUM_OFFSET_IN_delay;
assign TX_PTP_RXTSTAMP_IN_in = TX_PTP_RXTSTAMP_IN_delay;
assign TX_PTP_TAG_FIELD_IN_in = TX_PTP_TAG_FIELD_IN_delay;
assign TX_PTP_TSTAMP_OFFSET_IN_in = TX_PTP_TSTAMP_OFFSET_IN_delay;
assign TX_PTP_UPD_CHKSUM_IN_in = TX_PTP_UPD_CHKSUM_IN_delay;
assign TX_RESET_in = TX_RESET_delay;
assign TX_SOPIN0_in = TX_SOPIN0_delay;
assign TX_SOPIN1_in = TX_SOPIN1_delay;
assign TX_SOPIN2_in = TX_SOPIN2_delay;
assign TX_SOPIN3_in = TX_SOPIN3_delay;
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CTL_PTP_TRANSPCLK_MODE_REG != "FALSE") &&
(CTL_PTP_TRANSPCLK_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-101] CTL_PTP_TRANSPCLK_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_PTP_TRANSPCLK_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_CHECK_ACK_REG != "TRUE") &&
(CTL_RX_CHECK_ACK_REG != "FALSE"))) begin
$display("Error: [Unisim %s-102] CTL_RX_CHECK_ACK attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_ACK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_CHECK_PREAMBLE_REG != "FALSE") &&
(CTL_RX_CHECK_PREAMBLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-103] CTL_RX_CHECK_PREAMBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_PREAMBLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_CHECK_SFD_REG != "FALSE") &&
(CTL_RX_CHECK_SFD_REG != "TRUE"))) begin
$display("Error: [Unisim %s-104] CTL_RX_CHECK_SFD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_CHECK_SFD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_DELETE_FCS_REG != "TRUE") &&
(CTL_RX_DELETE_FCS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-105] CTL_RX_DELETE_FCS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_RX_DELETE_FCS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_ETYPE_GCP_REG < 16'h0000) || (CTL_RX_ETYPE_GCP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-106] CTL_RX_ETYPE_GCP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_GCP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_ETYPE_GPP_REG < 16'h0000) || (CTL_RX_ETYPE_GPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-107] CTL_RX_ETYPE_GPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_GPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_ETYPE_PCP_REG < 16'h0000) || (CTL_RX_ETYPE_PCP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-108] CTL_RX_ETYPE_PCP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_PCP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_ETYPE_PPP_REG < 16'h0000) || (CTL_RX_ETYPE_PPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-109] CTL_RX_ETYPE_PPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_ETYPE_PPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_FORWARD_CONTROL_REG != "FALSE") &&
(CTL_RX_FORWARD_CONTROL_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] CTL_RX_FORWARD_CONTROL attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_FORWARD_CONTROL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_IGNORE_FCS_REG != "FALSE") &&
(CTL_RX_IGNORE_FCS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] CTL_RX_IGNORE_FCS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_IGNORE_FCS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_MAX_PACKET_LEN_REG < 15'h0000) || (CTL_RX_MAX_PACKET_LEN_REG > 15'h3FFF))) begin
$display("Error: [Unisim %s-112] CTL_RX_MAX_PACKET_LEN attribute is set to %h. Legal values for this attribute are 15'h0000 to 15'h3FFF. Instance: %m", MODULE_NAME, CTL_RX_MAX_PACKET_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_MIN_PACKET_LEN_REG < 8'h00) || (CTL_RX_MIN_PACKET_LEN_REG > 8'hFF))) begin
$display("Error: [Unisim %s-113] CTL_RX_MIN_PACKET_LEN attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, CTL_RX_MIN_PACKET_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_OPCODE_GPP_REG < 16'h0000) || (CTL_RX_OPCODE_GPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-114] CTL_RX_OPCODE_GPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_OPCODE_GPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_OPCODE_MAX_GCP_REG < 16'h0000) || (CTL_RX_OPCODE_MAX_GCP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-115] CTL_RX_OPCODE_MAX_GCP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_OPCODE_MAX_GCP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_OPCODE_MAX_PCP_REG < 16'h0000) || (CTL_RX_OPCODE_MAX_PCP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-116] CTL_RX_OPCODE_MAX_PCP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_OPCODE_MAX_PCP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_OPCODE_MIN_GCP_REG < 16'h0000) || (CTL_RX_OPCODE_MIN_GCP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-117] CTL_RX_OPCODE_MIN_GCP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_OPCODE_MIN_GCP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_OPCODE_MIN_PCP_REG < 16'h0000) || (CTL_RX_OPCODE_MIN_PCP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-118] CTL_RX_OPCODE_MIN_PCP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_OPCODE_MIN_PCP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_OPCODE_PPP_REG < 16'h0000) || (CTL_RX_OPCODE_PPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-119] CTL_RX_OPCODE_PPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_OPCODE_PPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_PAUSE_DA_MCAST_REG < 48'h000000000000) || (CTL_RX_PAUSE_DA_MCAST_REG > 48'hFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-120] CTL_RX_PAUSE_DA_MCAST attribute is set to %h. Legal values for this attribute are 48'h000000000000 to 48'hFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_PAUSE_DA_MCAST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_PAUSE_DA_UCAST_REG < 48'h000000000000) || (CTL_RX_PAUSE_DA_UCAST_REG > 48'hFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-121] CTL_RX_PAUSE_DA_UCAST attribute is set to %h. Legal values for this attribute are 48'h000000000000 to 48'hFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_PAUSE_DA_UCAST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_PAUSE_SA_REG < 48'h000000000000) || (CTL_RX_PAUSE_SA_REG > 48'hFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-122] CTL_RX_PAUSE_SA attribute is set to %h. Legal values for this attribute are 48'h000000000000 to 48'hFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_PAUSE_SA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_PROCESS_LFI_REG != "FALSE") &&
(CTL_RX_PROCESS_LFI_REG != "TRUE"))) begin
$display("Error: [Unisim %s-123] CTL_RX_PROCESS_LFI attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_RX_PROCESS_LFI_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_LENGTH_MINUS1_REG < 16'h0000) || (CTL_RX_VL_LENGTH_MINUS1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-124] CTL_RX_VL_LENGTH_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_LENGTH_MINUS1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID0_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID0_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-125] CTL_RX_VL_MARKER_ID0 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID10_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID10_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-127] CTL_RX_VL_MARKER_ID10 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID11_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID11_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-128] CTL_RX_VL_MARKER_ID11 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID12_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID12_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-129] CTL_RX_VL_MARKER_ID12 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID13_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID13_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-130] CTL_RX_VL_MARKER_ID13 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID14_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID14_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-131] CTL_RX_VL_MARKER_ID14 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID15_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID15_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-132] CTL_RX_VL_MARKER_ID15 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID16_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID16_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-133] CTL_RX_VL_MARKER_ID16 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID16_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID17_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID17_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-134] CTL_RX_VL_MARKER_ID17 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID17_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID18_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID18_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-135] CTL_RX_VL_MARKER_ID18 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID18_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID19_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID19_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-136] CTL_RX_VL_MARKER_ID19 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID19_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID1_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID1_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-126] CTL_RX_VL_MARKER_ID1 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID2_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID2_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-137] CTL_RX_VL_MARKER_ID2 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID3_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID3_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-138] CTL_RX_VL_MARKER_ID3 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID4_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID4_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-139] CTL_RX_VL_MARKER_ID4 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID5_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID5_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-140] CTL_RX_VL_MARKER_ID5 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID6_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID6_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-141] CTL_RX_VL_MARKER_ID6 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID7_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID7_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-142] CTL_RX_VL_MARKER_ID7 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID7_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID8_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID8_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-143] CTL_RX_VL_MARKER_ID8 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID8_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_RX_VL_MARKER_ID9_REG < 64'h0000000000000000) || (CTL_RX_VL_MARKER_ID9_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-144] CTL_RX_VL_MARKER_ID9 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_RX_VL_MARKER_ID9_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TEST_MODE_PIN_CHAR_REG != "FALSE") &&
(CTL_TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin
$display("Error: [Unisim %s-145] CTL_TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TEST_MODE_PIN_CHAR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_DA_GPP_REG < 48'h000000000000) || (CTL_TX_DA_GPP_REG > 48'hFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-146] CTL_TX_DA_GPP attribute is set to %h. Legal values for this attribute are 48'h000000000000 to 48'hFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_DA_GPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_DA_PPP_REG < 48'h000000000000) || (CTL_TX_DA_PPP_REG > 48'hFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-147] CTL_TX_DA_PPP attribute is set to %h. Legal values for this attribute are 48'h000000000000 to 48'hFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_DA_PPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_ETHERTYPE_GPP_REG < 16'h0000) || (CTL_TX_ETHERTYPE_GPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-148] CTL_TX_ETHERTYPE_GPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_ETHERTYPE_GPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_ETHERTYPE_PPP_REG < 16'h0000) || (CTL_TX_ETHERTYPE_PPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-149] CTL_TX_ETHERTYPE_PPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_ETHERTYPE_PPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_FCS_INS_ENABLE_REG != "TRUE") &&
(CTL_TX_FCS_INS_ENABLE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-150] CTL_TX_FCS_INS_ENABLE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CTL_TX_FCS_INS_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_IGNORE_FCS_REG != "FALSE") &&
(CTL_TX_IGNORE_FCS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-151] CTL_TX_IGNORE_FCS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_IGNORE_FCS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_OPCODE_GPP_REG < 16'h0000) || (CTL_TX_OPCODE_GPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-152] CTL_TX_OPCODE_GPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_OPCODE_GPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_OPCODE_PPP_REG < 16'h0000) || (CTL_TX_OPCODE_PPP_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-153] CTL_TX_OPCODE_PPP attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_OPCODE_PPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_PTP_1STEP_ENABLE_REG != "FALSE") &&
(CTL_TX_PTP_1STEP_ENABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-154] CTL_TX_PTP_1STEP_ENABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CTL_TX_PTP_1STEP_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_PTP_LATENCY_ADJUST_REG < 11'h000) || (CTL_TX_PTP_LATENCY_ADJUST_REG > 11'h7FF))) begin
$display("Error: [Unisim %s-155] CTL_TX_PTP_LATENCY_ADJUST attribute is set to %h. Legal values for this attribute are 11'h000 to 11'h7FF. Instance: %m", MODULE_NAME, CTL_TX_PTP_LATENCY_ADJUST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_SA_GPP_REG < 48'h000000000000) || (CTL_TX_SA_GPP_REG > 48'hFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-156] CTL_TX_SA_GPP attribute is set to %h. Legal values for this attribute are 48'h000000000000 to 48'hFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_SA_GPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_SA_PPP_REG < 48'h000000000000) || (CTL_TX_SA_PPP_REG > 48'hFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-157] CTL_TX_SA_PPP attribute is set to %h. Legal values for this attribute are 48'h000000000000 to 48'hFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_SA_PPP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_LENGTH_MINUS1_REG < 16'h0000) || (CTL_TX_VL_LENGTH_MINUS1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-158] CTL_TX_VL_LENGTH_MINUS1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_LENGTH_MINUS1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID0_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID0_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-159] CTL_TX_VL_MARKER_ID0 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID10_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID10_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-161] CTL_TX_VL_MARKER_ID10 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID10_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID11_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID11_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-162] CTL_TX_VL_MARKER_ID11 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID11_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID12_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID12_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-163] CTL_TX_VL_MARKER_ID12 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID13_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID13_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-164] CTL_TX_VL_MARKER_ID13 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID13_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID14_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID14_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-165] CTL_TX_VL_MARKER_ID14 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID14_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID15_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID15_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-166] CTL_TX_VL_MARKER_ID15 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID15_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID16_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID16_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-167] CTL_TX_VL_MARKER_ID16 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID16_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID17_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID17_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-168] CTL_TX_VL_MARKER_ID17 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID17_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID18_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID18_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-169] CTL_TX_VL_MARKER_ID18 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID18_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID19_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID19_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-170] CTL_TX_VL_MARKER_ID19 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID19_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID1_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID1_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-160] CTL_TX_VL_MARKER_ID1 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID2_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID2_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-171] CTL_TX_VL_MARKER_ID2 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID3_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID3_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-172] CTL_TX_VL_MARKER_ID3 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID4_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID4_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-173] CTL_TX_VL_MARKER_ID4 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID5_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID5_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-174] CTL_TX_VL_MARKER_ID5 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID6_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID6_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-175] CTL_TX_VL_MARKER_ID6 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID7_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID7_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-176] CTL_TX_VL_MARKER_ID7 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID7_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID8_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID8_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-177] CTL_TX_VL_MARKER_ID8 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID8_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTL_TX_VL_MARKER_ID9_REG < 64'h0000000000000000) || (CTL_TX_VL_MARKER_ID9_REG > 64'hFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-178] CTL_TX_VL_MARKER_ID9 attribute is set to %h. Legal values for this attribute are 64'h0000000000000000 to 64'hFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, CTL_TX_VL_MARKER_ID9_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TEST_MODE_PIN_CHAR_REG != "FALSE") &&
(TEST_MODE_PIN_CHAR_REG != "TRUE"))) begin
$display("Error: [Unisim %s-179] TEST_MODE_PIN_CHAR attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TEST_MODE_PIN_CHAR_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign SCAN_EN_in = 1'b0; //manual tie off
assign SCAN_IN_CMAC_in = 182'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
assign SCAN_IN_DRPCTRL_in = 13'b1111111111111; // tie off
assign TEST_MODE_in = 1'b0; //manual tie off
assign TEST_RESET_in = 1'b1; // tie off
SIP_CMAC SIP_CMAC_INST (
.CTL_PTP_TRANSPCLK_MODE (CTL_PTP_TRANSPCLK_MODE_REG),
.CTL_RX_CHECK_ACK (CTL_RX_CHECK_ACK_REG),
.CTL_RX_CHECK_PREAMBLE (CTL_RX_CHECK_PREAMBLE_REG),
.CTL_RX_CHECK_SFD (CTL_RX_CHECK_SFD_REG),
.CTL_RX_DELETE_FCS (CTL_RX_DELETE_FCS_REG),
.CTL_RX_ETYPE_GCP (CTL_RX_ETYPE_GCP_REG),
.CTL_RX_ETYPE_GPP (CTL_RX_ETYPE_GPP_REG),
.CTL_RX_ETYPE_PCP (CTL_RX_ETYPE_PCP_REG),
.CTL_RX_ETYPE_PPP (CTL_RX_ETYPE_PPP_REG),
.CTL_RX_FORWARD_CONTROL (CTL_RX_FORWARD_CONTROL_REG),
.CTL_RX_IGNORE_FCS (CTL_RX_IGNORE_FCS_REG),
.CTL_RX_MAX_PACKET_LEN (CTL_RX_MAX_PACKET_LEN_REG),
.CTL_RX_MIN_PACKET_LEN (CTL_RX_MIN_PACKET_LEN_REG),
.CTL_RX_OPCODE_GPP (CTL_RX_OPCODE_GPP_REG),
.CTL_RX_OPCODE_MAX_GCP (CTL_RX_OPCODE_MAX_GCP_REG),
.CTL_RX_OPCODE_MAX_PCP (CTL_RX_OPCODE_MAX_PCP_REG),
.CTL_RX_OPCODE_MIN_GCP (CTL_RX_OPCODE_MIN_GCP_REG),
.CTL_RX_OPCODE_MIN_PCP (CTL_RX_OPCODE_MIN_PCP_REG),
.CTL_RX_OPCODE_PPP (CTL_RX_OPCODE_PPP_REG),
.CTL_RX_PAUSE_DA_MCAST (CTL_RX_PAUSE_DA_MCAST_REG),
.CTL_RX_PAUSE_DA_UCAST (CTL_RX_PAUSE_DA_UCAST_REG),
.CTL_RX_PAUSE_SA (CTL_RX_PAUSE_SA_REG),
.CTL_RX_PROCESS_LFI (CTL_RX_PROCESS_LFI_REG),
.CTL_RX_VL_LENGTH_MINUS1 (CTL_RX_VL_LENGTH_MINUS1_REG),
.CTL_RX_VL_MARKER_ID0 (CTL_RX_VL_MARKER_ID0_REG),
.CTL_RX_VL_MARKER_ID1 (CTL_RX_VL_MARKER_ID1_REG),
.CTL_RX_VL_MARKER_ID10 (CTL_RX_VL_MARKER_ID10_REG),
.CTL_RX_VL_MARKER_ID11 (CTL_RX_VL_MARKER_ID11_REG),
.CTL_RX_VL_MARKER_ID12 (CTL_RX_VL_MARKER_ID12_REG),
.CTL_RX_VL_MARKER_ID13 (CTL_RX_VL_MARKER_ID13_REG),
.CTL_RX_VL_MARKER_ID14 (CTL_RX_VL_MARKER_ID14_REG),
.CTL_RX_VL_MARKER_ID15 (CTL_RX_VL_MARKER_ID15_REG),
.CTL_RX_VL_MARKER_ID16 (CTL_RX_VL_MARKER_ID16_REG),
.CTL_RX_VL_MARKER_ID17 (CTL_RX_VL_MARKER_ID17_REG),
.CTL_RX_VL_MARKER_ID18 (CTL_RX_VL_MARKER_ID18_REG),
.CTL_RX_VL_MARKER_ID19 (CTL_RX_VL_MARKER_ID19_REG),
.CTL_RX_VL_MARKER_ID2 (CTL_RX_VL_MARKER_ID2_REG),
.CTL_RX_VL_MARKER_ID3 (CTL_RX_VL_MARKER_ID3_REG),
.CTL_RX_VL_MARKER_ID4 (CTL_RX_VL_MARKER_ID4_REG),
.CTL_RX_VL_MARKER_ID5 (CTL_RX_VL_MARKER_ID5_REG),
.CTL_RX_VL_MARKER_ID6 (CTL_RX_VL_MARKER_ID6_REG),
.CTL_RX_VL_MARKER_ID7 (CTL_RX_VL_MARKER_ID7_REG),
.CTL_RX_VL_MARKER_ID8 (CTL_RX_VL_MARKER_ID8_REG),
.CTL_RX_VL_MARKER_ID9 (CTL_RX_VL_MARKER_ID9_REG),
.CTL_TEST_MODE_PIN_CHAR (CTL_TEST_MODE_PIN_CHAR_REG),
.CTL_TX_DA_GPP (CTL_TX_DA_GPP_REG),
.CTL_TX_DA_PPP (CTL_TX_DA_PPP_REG),
.CTL_TX_ETHERTYPE_GPP (CTL_TX_ETHERTYPE_GPP_REG),
.CTL_TX_ETHERTYPE_PPP (CTL_TX_ETHERTYPE_PPP_REG),
.CTL_TX_FCS_INS_ENABLE (CTL_TX_FCS_INS_ENABLE_REG),
.CTL_TX_IGNORE_FCS (CTL_TX_IGNORE_FCS_REG),
.CTL_TX_OPCODE_GPP (CTL_TX_OPCODE_GPP_REG),
.CTL_TX_OPCODE_PPP (CTL_TX_OPCODE_PPP_REG),
.CTL_TX_PTP_1STEP_ENABLE (CTL_TX_PTP_1STEP_ENABLE_REG),
.CTL_TX_PTP_LATENCY_ADJUST (CTL_TX_PTP_LATENCY_ADJUST_REG),
.CTL_TX_SA_GPP (CTL_TX_SA_GPP_REG),
.CTL_TX_SA_PPP (CTL_TX_SA_PPP_REG),
.CTL_TX_VL_LENGTH_MINUS1 (CTL_TX_VL_LENGTH_MINUS1_REG),
.CTL_TX_VL_MARKER_ID0 (CTL_TX_VL_MARKER_ID0_REG),
.CTL_TX_VL_MARKER_ID1 (CTL_TX_VL_MARKER_ID1_REG),
.CTL_TX_VL_MARKER_ID10 (CTL_TX_VL_MARKER_ID10_REG),
.CTL_TX_VL_MARKER_ID11 (CTL_TX_VL_MARKER_ID11_REG),
.CTL_TX_VL_MARKER_ID12 (CTL_TX_VL_MARKER_ID12_REG),
.CTL_TX_VL_MARKER_ID13 (CTL_TX_VL_MARKER_ID13_REG),
.CTL_TX_VL_MARKER_ID14 (CTL_TX_VL_MARKER_ID14_REG),
.CTL_TX_VL_MARKER_ID15 (CTL_TX_VL_MARKER_ID15_REG),
.CTL_TX_VL_MARKER_ID16 (CTL_TX_VL_MARKER_ID16_REG),
.CTL_TX_VL_MARKER_ID17 (CTL_TX_VL_MARKER_ID17_REG),
.CTL_TX_VL_MARKER_ID18 (CTL_TX_VL_MARKER_ID18_REG),
.CTL_TX_VL_MARKER_ID19 (CTL_TX_VL_MARKER_ID19_REG),
.CTL_TX_VL_MARKER_ID2 (CTL_TX_VL_MARKER_ID2_REG),
.CTL_TX_VL_MARKER_ID3 (CTL_TX_VL_MARKER_ID3_REG),
.CTL_TX_VL_MARKER_ID4 (CTL_TX_VL_MARKER_ID4_REG),
.CTL_TX_VL_MARKER_ID5 (CTL_TX_VL_MARKER_ID5_REG),
.CTL_TX_VL_MARKER_ID6 (CTL_TX_VL_MARKER_ID6_REG),
.CTL_TX_VL_MARKER_ID7 (CTL_TX_VL_MARKER_ID7_REG),
.CTL_TX_VL_MARKER_ID8 (CTL_TX_VL_MARKER_ID8_REG),
.CTL_TX_VL_MARKER_ID9 (CTL_TX_VL_MARKER_ID9_REG),
.TEST_MODE_PIN_CHAR (TEST_MODE_PIN_CHAR_REG),
.DRP_DO (DRP_DO_out),
.DRP_RDY (DRP_RDY_out),
.RX_DATAOUT0 (RX_DATAOUT0_out),
.RX_DATAOUT1 (RX_DATAOUT1_out),
.RX_DATAOUT2 (RX_DATAOUT2_out),
.RX_DATAOUT3 (RX_DATAOUT3_out),
.RX_ENAOUT0 (RX_ENAOUT0_out),
.RX_ENAOUT1 (RX_ENAOUT1_out),
.RX_ENAOUT2 (RX_ENAOUT2_out),
.RX_ENAOUT3 (RX_ENAOUT3_out),
.RX_EOPOUT0 (RX_EOPOUT0_out),
.RX_EOPOUT1 (RX_EOPOUT1_out),
.RX_EOPOUT2 (RX_EOPOUT2_out),
.RX_EOPOUT3 (RX_EOPOUT3_out),
.RX_ERROUT0 (RX_ERROUT0_out),
.RX_ERROUT1 (RX_ERROUT1_out),
.RX_ERROUT2 (RX_ERROUT2_out),
.RX_ERROUT3 (RX_ERROUT3_out),
.RX_LANE_ALIGNER_FILL_0 (RX_LANE_ALIGNER_FILL_0_out),
.RX_LANE_ALIGNER_FILL_1 (RX_LANE_ALIGNER_FILL_1_out),
.RX_LANE_ALIGNER_FILL_10 (RX_LANE_ALIGNER_FILL_10_out),
.RX_LANE_ALIGNER_FILL_11 (RX_LANE_ALIGNER_FILL_11_out),
.RX_LANE_ALIGNER_FILL_12 (RX_LANE_ALIGNER_FILL_12_out),
.RX_LANE_ALIGNER_FILL_13 (RX_LANE_ALIGNER_FILL_13_out),
.RX_LANE_ALIGNER_FILL_14 (RX_LANE_ALIGNER_FILL_14_out),
.RX_LANE_ALIGNER_FILL_15 (RX_LANE_ALIGNER_FILL_15_out),
.RX_LANE_ALIGNER_FILL_16 (RX_LANE_ALIGNER_FILL_16_out),
.RX_LANE_ALIGNER_FILL_17 (RX_LANE_ALIGNER_FILL_17_out),
.RX_LANE_ALIGNER_FILL_18 (RX_LANE_ALIGNER_FILL_18_out),
.RX_LANE_ALIGNER_FILL_19 (RX_LANE_ALIGNER_FILL_19_out),
.RX_LANE_ALIGNER_FILL_2 (RX_LANE_ALIGNER_FILL_2_out),
.RX_LANE_ALIGNER_FILL_3 (RX_LANE_ALIGNER_FILL_3_out),
.RX_LANE_ALIGNER_FILL_4 (RX_LANE_ALIGNER_FILL_4_out),
.RX_LANE_ALIGNER_FILL_5 (RX_LANE_ALIGNER_FILL_5_out),
.RX_LANE_ALIGNER_FILL_6 (RX_LANE_ALIGNER_FILL_6_out),
.RX_LANE_ALIGNER_FILL_7 (RX_LANE_ALIGNER_FILL_7_out),
.RX_LANE_ALIGNER_FILL_8 (RX_LANE_ALIGNER_FILL_8_out),
.RX_LANE_ALIGNER_FILL_9 (RX_LANE_ALIGNER_FILL_9_out),
.RX_MTYOUT0 (RX_MTYOUT0_out),
.RX_MTYOUT1 (RX_MTYOUT1_out),
.RX_MTYOUT2 (RX_MTYOUT2_out),
.RX_MTYOUT3 (RX_MTYOUT3_out),
.RX_PTP_PCSLANE_OUT (RX_PTP_PCSLANE_OUT_out),
.RX_PTP_TSTAMP_OUT (RX_PTP_TSTAMP_OUT_out),
.RX_SOPOUT0 (RX_SOPOUT0_out),
.RX_SOPOUT1 (RX_SOPOUT1_out),
.RX_SOPOUT2 (RX_SOPOUT2_out),
.RX_SOPOUT3 (RX_SOPOUT3_out),
.SCAN_OUT_CMAC (SCAN_OUT_CMAC_out),
.SCAN_OUT_DRPCTRL (SCAN_OUT_DRPCTRL_out),
.STAT_RX_ALIGNED (STAT_RX_ALIGNED_out),
.STAT_RX_ALIGNED_ERR (STAT_RX_ALIGNED_ERR_out),
.STAT_RX_BAD_CODE (STAT_RX_BAD_CODE_out),
.STAT_RX_BAD_FCS (STAT_RX_BAD_FCS_out),
.STAT_RX_BAD_PREAMBLE (STAT_RX_BAD_PREAMBLE_out),
.STAT_RX_BAD_SFD (STAT_RX_BAD_SFD_out),
.STAT_RX_BIP_ERR_0 (STAT_RX_BIP_ERR_0_out),
.STAT_RX_BIP_ERR_1 (STAT_RX_BIP_ERR_1_out),
.STAT_RX_BIP_ERR_10 (STAT_RX_BIP_ERR_10_out),
.STAT_RX_BIP_ERR_11 (STAT_RX_BIP_ERR_11_out),
.STAT_RX_BIP_ERR_12 (STAT_RX_BIP_ERR_12_out),
.STAT_RX_BIP_ERR_13 (STAT_RX_BIP_ERR_13_out),
.STAT_RX_BIP_ERR_14 (STAT_RX_BIP_ERR_14_out),
.STAT_RX_BIP_ERR_15 (STAT_RX_BIP_ERR_15_out),
.STAT_RX_BIP_ERR_16 (STAT_RX_BIP_ERR_16_out),
.STAT_RX_BIP_ERR_17 (STAT_RX_BIP_ERR_17_out),
.STAT_RX_BIP_ERR_18 (STAT_RX_BIP_ERR_18_out),
.STAT_RX_BIP_ERR_19 (STAT_RX_BIP_ERR_19_out),
.STAT_RX_BIP_ERR_2 (STAT_RX_BIP_ERR_2_out),
.STAT_RX_BIP_ERR_3 (STAT_RX_BIP_ERR_3_out),
.STAT_RX_BIP_ERR_4 (STAT_RX_BIP_ERR_4_out),
.STAT_RX_BIP_ERR_5 (STAT_RX_BIP_ERR_5_out),
.STAT_RX_BIP_ERR_6 (STAT_RX_BIP_ERR_6_out),
.STAT_RX_BIP_ERR_7 (STAT_RX_BIP_ERR_7_out),
.STAT_RX_BIP_ERR_8 (STAT_RX_BIP_ERR_8_out),
.STAT_RX_BIP_ERR_9 (STAT_RX_BIP_ERR_9_out),
.STAT_RX_BLOCK_LOCK (STAT_RX_BLOCK_LOCK_out),
.STAT_RX_BROADCAST (STAT_RX_BROADCAST_out),
.STAT_RX_FRAGMENT (STAT_RX_FRAGMENT_out),
.STAT_RX_FRAMING_ERR_0 (STAT_RX_FRAMING_ERR_0_out),
.STAT_RX_FRAMING_ERR_1 (STAT_RX_FRAMING_ERR_1_out),
.STAT_RX_FRAMING_ERR_10 (STAT_RX_FRAMING_ERR_10_out),
.STAT_RX_FRAMING_ERR_11 (STAT_RX_FRAMING_ERR_11_out),
.STAT_RX_FRAMING_ERR_12 (STAT_RX_FRAMING_ERR_12_out),
.STAT_RX_FRAMING_ERR_13 (STAT_RX_FRAMING_ERR_13_out),
.STAT_RX_FRAMING_ERR_14 (STAT_RX_FRAMING_ERR_14_out),
.STAT_RX_FRAMING_ERR_15 (STAT_RX_FRAMING_ERR_15_out),
.STAT_RX_FRAMING_ERR_16 (STAT_RX_FRAMING_ERR_16_out),
.STAT_RX_FRAMING_ERR_17 (STAT_RX_FRAMING_ERR_17_out),
.STAT_RX_FRAMING_ERR_18 (STAT_RX_FRAMING_ERR_18_out),
.STAT_RX_FRAMING_ERR_19 (STAT_RX_FRAMING_ERR_19_out),
.STAT_RX_FRAMING_ERR_2 (STAT_RX_FRAMING_ERR_2_out),
.STAT_RX_FRAMING_ERR_3 (STAT_RX_FRAMING_ERR_3_out),
.STAT_RX_FRAMING_ERR_4 (STAT_RX_FRAMING_ERR_4_out),
.STAT_RX_FRAMING_ERR_5 (STAT_RX_FRAMING_ERR_5_out),
.STAT_RX_FRAMING_ERR_6 (STAT_RX_FRAMING_ERR_6_out),
.STAT_RX_FRAMING_ERR_7 (STAT_RX_FRAMING_ERR_7_out),
.STAT_RX_FRAMING_ERR_8 (STAT_RX_FRAMING_ERR_8_out),
.STAT_RX_FRAMING_ERR_9 (STAT_RX_FRAMING_ERR_9_out),
.STAT_RX_FRAMING_ERR_VALID_0 (STAT_RX_FRAMING_ERR_VALID_0_out),
.STAT_RX_FRAMING_ERR_VALID_1 (STAT_RX_FRAMING_ERR_VALID_1_out),
.STAT_RX_FRAMING_ERR_VALID_10 (STAT_RX_FRAMING_ERR_VALID_10_out),
.STAT_RX_FRAMING_ERR_VALID_11 (STAT_RX_FRAMING_ERR_VALID_11_out),
.STAT_RX_FRAMING_ERR_VALID_12 (STAT_RX_FRAMING_ERR_VALID_12_out),
.STAT_RX_FRAMING_ERR_VALID_13 (STAT_RX_FRAMING_ERR_VALID_13_out),
.STAT_RX_FRAMING_ERR_VALID_14 (STAT_RX_FRAMING_ERR_VALID_14_out),
.STAT_RX_FRAMING_ERR_VALID_15 (STAT_RX_FRAMING_ERR_VALID_15_out),
.STAT_RX_FRAMING_ERR_VALID_16 (STAT_RX_FRAMING_ERR_VALID_16_out),
.STAT_RX_FRAMING_ERR_VALID_17 (STAT_RX_FRAMING_ERR_VALID_17_out),
.STAT_RX_FRAMING_ERR_VALID_18 (STAT_RX_FRAMING_ERR_VALID_18_out),
.STAT_RX_FRAMING_ERR_VALID_19 (STAT_RX_FRAMING_ERR_VALID_19_out),
.STAT_RX_FRAMING_ERR_VALID_2 (STAT_RX_FRAMING_ERR_VALID_2_out),
.STAT_RX_FRAMING_ERR_VALID_3 (STAT_RX_FRAMING_ERR_VALID_3_out),
.STAT_RX_FRAMING_ERR_VALID_4 (STAT_RX_FRAMING_ERR_VALID_4_out),
.STAT_RX_FRAMING_ERR_VALID_5 (STAT_RX_FRAMING_ERR_VALID_5_out),
.STAT_RX_FRAMING_ERR_VALID_6 (STAT_RX_FRAMING_ERR_VALID_6_out),
.STAT_RX_FRAMING_ERR_VALID_7 (STAT_RX_FRAMING_ERR_VALID_7_out),
.STAT_RX_FRAMING_ERR_VALID_8 (STAT_RX_FRAMING_ERR_VALID_8_out),
.STAT_RX_FRAMING_ERR_VALID_9 (STAT_RX_FRAMING_ERR_VALID_9_out),
.STAT_RX_GOT_SIGNAL_OS (STAT_RX_GOT_SIGNAL_OS_out),
.STAT_RX_HI_BER (STAT_RX_HI_BER_out),
.STAT_RX_INRANGEERR (STAT_RX_INRANGEERR_out),
.STAT_RX_INTERNAL_LOCAL_FAULT (STAT_RX_INTERNAL_LOCAL_FAULT_out),
.STAT_RX_JABBER (STAT_RX_JABBER_out),
.STAT_RX_LANE0_VLM_BIP7 (STAT_RX_LANE0_VLM_BIP7_out),
.STAT_RX_LANE0_VLM_BIP7_VALID (STAT_RX_LANE0_VLM_BIP7_VALID_out),
.STAT_RX_LOCAL_FAULT (STAT_RX_LOCAL_FAULT_out),
.STAT_RX_MF_ERR (STAT_RX_MF_ERR_out),
.STAT_RX_MF_LEN_ERR (STAT_RX_MF_LEN_ERR_out),
.STAT_RX_MF_REPEAT_ERR (STAT_RX_MF_REPEAT_ERR_out),
.STAT_RX_MISALIGNED (STAT_RX_MISALIGNED_out),
.STAT_RX_MULTICAST (STAT_RX_MULTICAST_out),
.STAT_RX_OVERSIZE (STAT_RX_OVERSIZE_out),
.STAT_RX_PACKET_1024_1518_BYTES (STAT_RX_PACKET_1024_1518_BYTES_out),
.STAT_RX_PACKET_128_255_BYTES (STAT_RX_PACKET_128_255_BYTES_out),
.STAT_RX_PACKET_1519_1522_BYTES (STAT_RX_PACKET_1519_1522_BYTES_out),
.STAT_RX_PACKET_1523_1548_BYTES (STAT_RX_PACKET_1523_1548_BYTES_out),
.STAT_RX_PACKET_1549_2047_BYTES (STAT_RX_PACKET_1549_2047_BYTES_out),
.STAT_RX_PACKET_2048_4095_BYTES (STAT_RX_PACKET_2048_4095_BYTES_out),
.STAT_RX_PACKET_256_511_BYTES (STAT_RX_PACKET_256_511_BYTES_out),
.STAT_RX_PACKET_4096_8191_BYTES (STAT_RX_PACKET_4096_8191_BYTES_out),
.STAT_RX_PACKET_512_1023_BYTES (STAT_RX_PACKET_512_1023_BYTES_out),
.STAT_RX_PACKET_64_BYTES (STAT_RX_PACKET_64_BYTES_out),
.STAT_RX_PACKET_65_127_BYTES (STAT_RX_PACKET_65_127_BYTES_out),
.STAT_RX_PACKET_8192_9215_BYTES (STAT_RX_PACKET_8192_9215_BYTES_out),
.STAT_RX_PACKET_BAD_FCS (STAT_RX_PACKET_BAD_FCS_out),
.STAT_RX_PACKET_LARGE (STAT_RX_PACKET_LARGE_out),
.STAT_RX_PACKET_SMALL (STAT_RX_PACKET_SMALL_out),
.STAT_RX_PAUSE (STAT_RX_PAUSE_out),
.STAT_RX_PAUSE_QUANTA0 (STAT_RX_PAUSE_QUANTA0_out),
.STAT_RX_PAUSE_QUANTA1 (STAT_RX_PAUSE_QUANTA1_out),
.STAT_RX_PAUSE_QUANTA2 (STAT_RX_PAUSE_QUANTA2_out),
.STAT_RX_PAUSE_QUANTA3 (STAT_RX_PAUSE_QUANTA3_out),
.STAT_RX_PAUSE_QUANTA4 (STAT_RX_PAUSE_QUANTA4_out),
.STAT_RX_PAUSE_QUANTA5 (STAT_RX_PAUSE_QUANTA5_out),
.STAT_RX_PAUSE_QUANTA6 (STAT_RX_PAUSE_QUANTA6_out),
.STAT_RX_PAUSE_QUANTA7 (STAT_RX_PAUSE_QUANTA7_out),
.STAT_RX_PAUSE_QUANTA8 (STAT_RX_PAUSE_QUANTA8_out),
.STAT_RX_PAUSE_REQ (STAT_RX_PAUSE_REQ_out),
.STAT_RX_PAUSE_VALID (STAT_RX_PAUSE_VALID_out),
.STAT_RX_RECEIVED_LOCAL_FAULT (STAT_RX_RECEIVED_LOCAL_FAULT_out),
.STAT_RX_REMOTE_FAULT (STAT_RX_REMOTE_FAULT_out),
.STAT_RX_STATUS (STAT_RX_STATUS_out),
.STAT_RX_STOMPED_FCS (STAT_RX_STOMPED_FCS_out),
.STAT_RX_SYNCED (STAT_RX_SYNCED_out),
.STAT_RX_SYNCED_ERR (STAT_RX_SYNCED_ERR_out),
.STAT_RX_TEST_PATTERN_MISMATCH (STAT_RX_TEST_PATTERN_MISMATCH_out),
.STAT_RX_TOOLONG (STAT_RX_TOOLONG_out),
.STAT_RX_TOTAL_BYTES (STAT_RX_TOTAL_BYTES_out),
.STAT_RX_TOTAL_GOOD_BYTES (STAT_RX_TOTAL_GOOD_BYTES_out),
.STAT_RX_TOTAL_GOOD_PACKETS (STAT_RX_TOTAL_GOOD_PACKETS_out),
.STAT_RX_TOTAL_PACKETS (STAT_RX_TOTAL_PACKETS_out),
.STAT_RX_TRUNCATED (STAT_RX_TRUNCATED_out),
.STAT_RX_UNDERSIZE (STAT_RX_UNDERSIZE_out),
.STAT_RX_UNICAST (STAT_RX_UNICAST_out),
.STAT_RX_USER_PAUSE (STAT_RX_USER_PAUSE_out),
.STAT_RX_VLAN (STAT_RX_VLAN_out),
.STAT_RX_VL_DEMUXED (STAT_RX_VL_DEMUXED_out),
.STAT_RX_VL_NUMBER_0 (STAT_RX_VL_NUMBER_0_out),
.STAT_RX_VL_NUMBER_1 (STAT_RX_VL_NUMBER_1_out),
.STAT_RX_VL_NUMBER_10 (STAT_RX_VL_NUMBER_10_out),
.STAT_RX_VL_NUMBER_11 (STAT_RX_VL_NUMBER_11_out),
.STAT_RX_VL_NUMBER_12 (STAT_RX_VL_NUMBER_12_out),
.STAT_RX_VL_NUMBER_13 (STAT_RX_VL_NUMBER_13_out),
.STAT_RX_VL_NUMBER_14 (STAT_RX_VL_NUMBER_14_out),
.STAT_RX_VL_NUMBER_15 (STAT_RX_VL_NUMBER_15_out),
.STAT_RX_VL_NUMBER_16 (STAT_RX_VL_NUMBER_16_out),
.STAT_RX_VL_NUMBER_17 (STAT_RX_VL_NUMBER_17_out),
.STAT_RX_VL_NUMBER_18 (STAT_RX_VL_NUMBER_18_out),
.STAT_RX_VL_NUMBER_19 (STAT_RX_VL_NUMBER_19_out),
.STAT_RX_VL_NUMBER_2 (STAT_RX_VL_NUMBER_2_out),
.STAT_RX_VL_NUMBER_3 (STAT_RX_VL_NUMBER_3_out),
.STAT_RX_VL_NUMBER_4 (STAT_RX_VL_NUMBER_4_out),
.STAT_RX_VL_NUMBER_5 (STAT_RX_VL_NUMBER_5_out),
.STAT_RX_VL_NUMBER_6 (STAT_RX_VL_NUMBER_6_out),
.STAT_RX_VL_NUMBER_7 (STAT_RX_VL_NUMBER_7_out),
.STAT_RX_VL_NUMBER_8 (STAT_RX_VL_NUMBER_8_out),
.STAT_RX_VL_NUMBER_9 (STAT_RX_VL_NUMBER_9_out),
.STAT_TX_BAD_FCS (STAT_TX_BAD_FCS_out),
.STAT_TX_BROADCAST (STAT_TX_BROADCAST_out),
.STAT_TX_FRAME_ERROR (STAT_TX_FRAME_ERROR_out),
.STAT_TX_LOCAL_FAULT (STAT_TX_LOCAL_FAULT_out),
.STAT_TX_MULTICAST (STAT_TX_MULTICAST_out),
.STAT_TX_PACKET_1024_1518_BYTES (STAT_TX_PACKET_1024_1518_BYTES_out),
.STAT_TX_PACKET_128_255_BYTES (STAT_TX_PACKET_128_255_BYTES_out),
.STAT_TX_PACKET_1519_1522_BYTES (STAT_TX_PACKET_1519_1522_BYTES_out),
.STAT_TX_PACKET_1523_1548_BYTES (STAT_TX_PACKET_1523_1548_BYTES_out),
.STAT_TX_PACKET_1549_2047_BYTES (STAT_TX_PACKET_1549_2047_BYTES_out),
.STAT_TX_PACKET_2048_4095_BYTES (STAT_TX_PACKET_2048_4095_BYTES_out),
.STAT_TX_PACKET_256_511_BYTES (STAT_TX_PACKET_256_511_BYTES_out),
.STAT_TX_PACKET_4096_8191_BYTES (STAT_TX_PACKET_4096_8191_BYTES_out),
.STAT_TX_PACKET_512_1023_BYTES (STAT_TX_PACKET_512_1023_BYTES_out),
.STAT_TX_PACKET_64_BYTES (STAT_TX_PACKET_64_BYTES_out),
.STAT_TX_PACKET_65_127_BYTES (STAT_TX_PACKET_65_127_BYTES_out),
.STAT_TX_PACKET_8192_9215_BYTES (STAT_TX_PACKET_8192_9215_BYTES_out),
.STAT_TX_PACKET_LARGE (STAT_TX_PACKET_LARGE_out),
.STAT_TX_PACKET_SMALL (STAT_TX_PACKET_SMALL_out),
.STAT_TX_PAUSE (STAT_TX_PAUSE_out),
.STAT_TX_PAUSE_VALID (STAT_TX_PAUSE_VALID_out),
.STAT_TX_PTP_FIFO_READ_ERROR (STAT_TX_PTP_FIFO_READ_ERROR_out),
.STAT_TX_PTP_FIFO_WRITE_ERROR (STAT_TX_PTP_FIFO_WRITE_ERROR_out),
.STAT_TX_TOTAL_BYTES (STAT_TX_TOTAL_BYTES_out),
.STAT_TX_TOTAL_GOOD_BYTES (STAT_TX_TOTAL_GOOD_BYTES_out),
.STAT_TX_TOTAL_GOOD_PACKETS (STAT_TX_TOTAL_GOOD_PACKETS_out),
.STAT_TX_TOTAL_PACKETS (STAT_TX_TOTAL_PACKETS_out),
.STAT_TX_UNICAST (STAT_TX_UNICAST_out),
.STAT_TX_USER_PAUSE (STAT_TX_USER_PAUSE_out),
.STAT_TX_VLAN (STAT_TX_VLAN_out),
.TX_OVFOUT (TX_OVFOUT_out),
.TX_PTP_PCSLANE_OUT (TX_PTP_PCSLANE_OUT_out),
.TX_PTP_TSTAMP_OUT (TX_PTP_TSTAMP_OUT_out),
.TX_PTP_TSTAMP_TAG_OUT (TX_PTP_TSTAMP_TAG_OUT_out),
.TX_PTP_TSTAMP_VALID_OUT (TX_PTP_TSTAMP_VALID_OUT_out),
.TX_RDYOUT (TX_RDYOUT_out),
.TX_SERDES_ALT_DATA0 (TX_SERDES_ALT_DATA0_out),
.TX_SERDES_ALT_DATA1 (TX_SERDES_ALT_DATA1_out),
.TX_SERDES_ALT_DATA2 (TX_SERDES_ALT_DATA2_out),
.TX_SERDES_ALT_DATA3 (TX_SERDES_ALT_DATA3_out),
.TX_SERDES_DATA0 (TX_SERDES_DATA0_out),
.TX_SERDES_DATA1 (TX_SERDES_DATA1_out),
.TX_SERDES_DATA2 (TX_SERDES_DATA2_out),
.TX_SERDES_DATA3 (TX_SERDES_DATA3_out),
.TX_SERDES_DATA4 (TX_SERDES_DATA4_out),
.TX_SERDES_DATA5 (TX_SERDES_DATA5_out),
.TX_SERDES_DATA6 (TX_SERDES_DATA6_out),
.TX_SERDES_DATA7 (TX_SERDES_DATA7_out),
.TX_SERDES_DATA8 (TX_SERDES_DATA8_out),
.TX_SERDES_DATA9 (TX_SERDES_DATA9_out),
.TX_UNFOUT (TX_UNFOUT_out),
.CTL_CAUI4_MODE (CTL_CAUI4_MODE_in),
.CTL_RX_CHECK_ETYPE_GCP (CTL_RX_CHECK_ETYPE_GCP_in),
.CTL_RX_CHECK_ETYPE_GPP (CTL_RX_CHECK_ETYPE_GPP_in),
.CTL_RX_CHECK_ETYPE_PCP (CTL_RX_CHECK_ETYPE_PCP_in),
.CTL_RX_CHECK_ETYPE_PPP (CTL_RX_CHECK_ETYPE_PPP_in),
.CTL_RX_CHECK_MCAST_GCP (CTL_RX_CHECK_MCAST_GCP_in),
.CTL_RX_CHECK_MCAST_GPP (CTL_RX_CHECK_MCAST_GPP_in),
.CTL_RX_CHECK_MCAST_PCP (CTL_RX_CHECK_MCAST_PCP_in),
.CTL_RX_CHECK_MCAST_PPP (CTL_RX_CHECK_MCAST_PPP_in),
.CTL_RX_CHECK_OPCODE_GCP (CTL_RX_CHECK_OPCODE_GCP_in),
.CTL_RX_CHECK_OPCODE_GPP (CTL_RX_CHECK_OPCODE_GPP_in),
.CTL_RX_CHECK_OPCODE_PCP (CTL_RX_CHECK_OPCODE_PCP_in),
.CTL_RX_CHECK_OPCODE_PPP (CTL_RX_CHECK_OPCODE_PPP_in),
.CTL_RX_CHECK_SA_GCP (CTL_RX_CHECK_SA_GCP_in),
.CTL_RX_CHECK_SA_GPP (CTL_RX_CHECK_SA_GPP_in),
.CTL_RX_CHECK_SA_PCP (CTL_RX_CHECK_SA_PCP_in),
.CTL_RX_CHECK_SA_PPP (CTL_RX_CHECK_SA_PPP_in),
.CTL_RX_CHECK_UCAST_GCP (CTL_RX_CHECK_UCAST_GCP_in),
.CTL_RX_CHECK_UCAST_GPP (CTL_RX_CHECK_UCAST_GPP_in),
.CTL_RX_CHECK_UCAST_PCP (CTL_RX_CHECK_UCAST_PCP_in),
.CTL_RX_CHECK_UCAST_PPP (CTL_RX_CHECK_UCAST_PPP_in),
.CTL_RX_ENABLE (CTL_RX_ENABLE_in),
.CTL_RX_ENABLE_GCP (CTL_RX_ENABLE_GCP_in),
.CTL_RX_ENABLE_GPP (CTL_RX_ENABLE_GPP_in),
.CTL_RX_ENABLE_PCP (CTL_RX_ENABLE_PCP_in),
.CTL_RX_ENABLE_PPP (CTL_RX_ENABLE_PPP_in),
.CTL_RX_FORCE_RESYNC (CTL_RX_FORCE_RESYNC_in),
.CTL_RX_PAUSE_ACK (CTL_RX_PAUSE_ACK_in),
.CTL_RX_PAUSE_ENABLE (CTL_RX_PAUSE_ENABLE_in),
.CTL_RX_SYSTEMTIMERIN (CTL_RX_SYSTEMTIMERIN_in),
.CTL_RX_TEST_PATTERN (CTL_RX_TEST_PATTERN_in),
.CTL_TX_ENABLE (CTL_TX_ENABLE_in),
.CTL_TX_LANE0_VLM_BIP7_OVERRIDE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_in),
.CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE (CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_in),
.CTL_TX_PAUSE_ENABLE (CTL_TX_PAUSE_ENABLE_in),
.CTL_TX_PAUSE_QUANTA0 (CTL_TX_PAUSE_QUANTA0_in),
.CTL_TX_PAUSE_QUANTA1 (CTL_TX_PAUSE_QUANTA1_in),
.CTL_TX_PAUSE_QUANTA2 (CTL_TX_PAUSE_QUANTA2_in),
.CTL_TX_PAUSE_QUANTA3 (CTL_TX_PAUSE_QUANTA3_in),
.CTL_TX_PAUSE_QUANTA4 (CTL_TX_PAUSE_QUANTA4_in),
.CTL_TX_PAUSE_QUANTA5 (CTL_TX_PAUSE_QUANTA5_in),
.CTL_TX_PAUSE_QUANTA6 (CTL_TX_PAUSE_QUANTA6_in),
.CTL_TX_PAUSE_QUANTA7 (CTL_TX_PAUSE_QUANTA7_in),
.CTL_TX_PAUSE_QUANTA8 (CTL_TX_PAUSE_QUANTA8_in),
.CTL_TX_PAUSE_REFRESH_TIMER0 (CTL_TX_PAUSE_REFRESH_TIMER0_in),
.CTL_TX_PAUSE_REFRESH_TIMER1 (CTL_TX_PAUSE_REFRESH_TIMER1_in),
.CTL_TX_PAUSE_REFRESH_TIMER2 (CTL_TX_PAUSE_REFRESH_TIMER2_in),
.CTL_TX_PAUSE_REFRESH_TIMER3 (CTL_TX_PAUSE_REFRESH_TIMER3_in),
.CTL_TX_PAUSE_REFRESH_TIMER4 (CTL_TX_PAUSE_REFRESH_TIMER4_in),
.CTL_TX_PAUSE_REFRESH_TIMER5 (CTL_TX_PAUSE_REFRESH_TIMER5_in),
.CTL_TX_PAUSE_REFRESH_TIMER6 (CTL_TX_PAUSE_REFRESH_TIMER6_in),
.CTL_TX_PAUSE_REFRESH_TIMER7 (CTL_TX_PAUSE_REFRESH_TIMER7_in),
.CTL_TX_PAUSE_REFRESH_TIMER8 (CTL_TX_PAUSE_REFRESH_TIMER8_in),
.CTL_TX_PAUSE_REQ (CTL_TX_PAUSE_REQ_in),
.CTL_TX_PTP_VLANE_ADJUST_MODE (CTL_TX_PTP_VLANE_ADJUST_MODE_in),
.CTL_TX_RESEND_PAUSE (CTL_TX_RESEND_PAUSE_in),
.CTL_TX_SEND_IDLE (CTL_TX_SEND_IDLE_in),
.CTL_TX_SEND_RFI (CTL_TX_SEND_RFI_in),
.CTL_TX_SYSTEMTIMERIN (CTL_TX_SYSTEMTIMERIN_in),
.CTL_TX_TEST_PATTERN (CTL_TX_TEST_PATTERN_in),
.DRP_ADDR (DRP_ADDR_in),
.DRP_CLK (DRP_CLK_in),
.DRP_DI (DRP_DI_in),
.DRP_EN (DRP_EN_in),
.DRP_WE (DRP_WE_in),
.RX_CLK (RX_CLK_in),
.RX_RESET (RX_RESET_in),
.RX_SERDES_ALT_DATA0 (RX_SERDES_ALT_DATA0_in),
.RX_SERDES_ALT_DATA1 (RX_SERDES_ALT_DATA1_in),
.RX_SERDES_ALT_DATA2 (RX_SERDES_ALT_DATA2_in),
.RX_SERDES_ALT_DATA3 (RX_SERDES_ALT_DATA3_in),
.RX_SERDES_CLK (RX_SERDES_CLK_in),
.RX_SERDES_DATA0 (RX_SERDES_DATA0_in),
.RX_SERDES_DATA1 (RX_SERDES_DATA1_in),
.RX_SERDES_DATA2 (RX_SERDES_DATA2_in),
.RX_SERDES_DATA3 (RX_SERDES_DATA3_in),
.RX_SERDES_DATA4 (RX_SERDES_DATA4_in),
.RX_SERDES_DATA5 (RX_SERDES_DATA5_in),
.RX_SERDES_DATA6 (RX_SERDES_DATA6_in),
.RX_SERDES_DATA7 (RX_SERDES_DATA7_in),
.RX_SERDES_DATA8 (RX_SERDES_DATA8_in),
.RX_SERDES_DATA9 (RX_SERDES_DATA9_in),
.RX_SERDES_RESET (RX_SERDES_RESET_in),
.SCAN_EN (SCAN_EN_in),
.SCAN_IN_CMAC (SCAN_IN_CMAC_in),
.SCAN_IN_DRPCTRL (SCAN_IN_DRPCTRL_in),
.TEST_MODE (TEST_MODE_in),
.TEST_RESET (TEST_RESET_in),
.TX_CLK (TX_CLK_in),
.TX_DATAIN0 (TX_DATAIN0_in),
.TX_DATAIN1 (TX_DATAIN1_in),
.TX_DATAIN2 (TX_DATAIN2_in),
.TX_DATAIN3 (TX_DATAIN3_in),
.TX_ENAIN0 (TX_ENAIN0_in),
.TX_ENAIN1 (TX_ENAIN1_in),
.TX_ENAIN2 (TX_ENAIN2_in),
.TX_ENAIN3 (TX_ENAIN3_in),
.TX_EOPIN0 (TX_EOPIN0_in),
.TX_EOPIN1 (TX_EOPIN1_in),
.TX_EOPIN2 (TX_EOPIN2_in),
.TX_EOPIN3 (TX_EOPIN3_in),
.TX_ERRIN0 (TX_ERRIN0_in),
.TX_ERRIN1 (TX_ERRIN1_in),
.TX_ERRIN2 (TX_ERRIN2_in),
.TX_ERRIN3 (TX_ERRIN3_in),
.TX_MTYIN0 (TX_MTYIN0_in),
.TX_MTYIN1 (TX_MTYIN1_in),
.TX_MTYIN2 (TX_MTYIN2_in),
.TX_MTYIN3 (TX_MTYIN3_in),
.TX_PTP_1588OP_IN (TX_PTP_1588OP_IN_in),
.TX_PTP_CHKSUM_OFFSET_IN (TX_PTP_CHKSUM_OFFSET_IN_in),
.TX_PTP_RXTSTAMP_IN (TX_PTP_RXTSTAMP_IN_in),
.TX_PTP_TAG_FIELD_IN (TX_PTP_TAG_FIELD_IN_in),
.TX_PTP_TSTAMP_OFFSET_IN (TX_PTP_TSTAMP_OFFSET_IN_in),
.TX_PTP_UPD_CHKSUM_IN (TX_PTP_UPD_CHKSUM_IN_in),
.TX_RESET (TX_RESET_in),
.TX_SOPIN0 (TX_SOPIN0_in),
.TX_SOPIN1 (TX_SOPIN1_in),
.TX_SOPIN2 (TX_SOPIN2_in),
.TX_SOPIN3 (TX_SOPIN3_in),
.GSR (glblGSR)
);
specify
(DRP_CLK => DRP_DO[0]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[10]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[11]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[12]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[13]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[14]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[15]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[1]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[2]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[3]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[4]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[5]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[6]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[7]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[8]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_DO[9]) = (0:0:0, 0:0:0);
(DRP_CLK => DRP_RDY) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[100]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[101]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[102]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[103]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[104]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[105]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[106]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[107]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[108]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[109]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[10]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[110]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[111]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[112]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[113]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[114]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[115]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[116]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[117]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[118]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[119]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[11]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[120]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[121]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[122]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[123]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[124]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[125]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[126]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[127]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[12]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[13]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[14]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[15]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[16]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[17]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[18]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[19]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[20]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[21]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[22]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[23]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[24]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[25]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[26]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[27]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[28]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[29]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[30]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[31]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[32]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[33]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[34]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[35]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[36]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[37]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[38]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[39]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[40]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[41]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[42]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[43]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[44]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[45]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[46]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[47]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[48]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[49]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[50]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[51]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[52]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[53]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[54]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[55]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[56]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[57]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[58]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[59]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[60]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[61]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[62]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[63]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[64]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[65]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[66]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[67]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[68]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[69]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[70]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[71]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[72]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[73]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[74]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[75]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[76]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[77]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[78]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[79]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[7]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[80]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[81]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[82]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[83]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[84]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[85]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[86]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[87]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[88]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[89]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[8]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[90]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[91]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[92]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[93]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[94]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[95]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[96]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[97]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[98]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[99]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT0[9]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[100]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[101]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[102]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[103]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[104]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[105]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[106]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[107]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[108]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[109]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[10]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[110]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[111]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[112]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[113]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[114]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[115]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[116]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[117]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[118]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[119]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[11]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[120]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[121]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[122]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[123]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[124]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[125]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[126]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[127]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[12]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[13]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[14]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[15]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[16]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[17]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[18]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[19]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[20]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[21]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[22]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[23]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[24]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[25]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[26]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[27]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[28]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[29]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[30]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[31]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[32]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[33]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[34]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[35]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[36]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[37]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[38]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[39]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[40]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[41]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[42]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[43]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[44]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[45]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[46]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[47]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[48]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[49]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[50]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[51]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[52]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[53]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[54]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[55]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[56]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[57]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[58]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[59]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[60]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[61]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[62]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[63]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[64]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[65]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[66]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[67]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[68]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[69]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[70]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[71]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[72]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[73]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[74]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[75]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[76]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[77]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[78]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[79]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[7]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[80]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[81]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[82]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[83]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[84]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[85]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[86]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[87]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[88]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[89]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[8]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[90]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[91]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[92]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[93]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[94]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[95]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[96]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[97]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[98]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[99]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT1[9]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[100]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[101]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[102]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[103]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[104]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[105]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[106]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[107]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[108]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[109]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[10]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[110]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[111]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[112]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[113]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[114]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[115]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[116]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[117]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[118]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[119]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[11]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[120]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[121]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[122]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[123]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[124]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[125]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[126]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[127]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[12]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[13]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[14]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[15]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[16]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[17]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[18]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[19]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[20]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[21]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[22]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[23]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[24]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[25]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[26]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[27]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[28]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[29]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[30]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[31]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[32]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[33]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[34]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[35]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[36]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[37]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[38]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[39]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[40]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[41]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[42]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[43]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[44]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[45]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[46]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[47]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[48]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[49]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[50]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[51]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[52]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[53]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[54]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[55]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[56]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[57]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[58]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[59]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[60]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[61]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[62]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[63]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[64]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[65]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[66]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[67]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[68]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[69]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[70]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[71]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[72]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[73]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[74]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[75]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[76]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[77]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[78]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[79]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[7]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[80]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[81]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[82]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[83]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[84]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[85]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[86]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[87]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[88]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[89]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[8]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[90]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[91]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[92]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[93]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[94]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[95]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[96]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[97]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[98]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[99]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT2[9]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[100]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[101]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[102]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[103]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[104]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[105]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[106]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[107]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[108]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[109]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[10]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[110]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[111]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[112]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[113]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[114]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[115]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[116]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[117]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[118]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[119]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[11]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[120]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[121]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[122]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[123]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[124]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[125]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[126]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[127]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[12]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[13]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[14]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[15]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[16]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[17]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[18]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[19]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[20]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[21]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[22]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[23]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[24]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[25]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[26]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[27]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[28]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[29]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[30]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[31]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[32]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[33]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[34]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[35]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[36]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[37]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[38]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[39]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[40]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[41]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[42]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[43]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[44]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[45]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[46]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[47]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[48]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[49]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[50]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[51]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[52]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[53]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[54]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[55]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[56]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[57]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[58]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[59]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[60]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[61]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[62]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[63]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[64]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[65]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[66]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[67]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[68]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[69]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[70]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[71]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[72]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[73]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[74]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[75]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[76]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[77]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[78]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[79]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[7]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[80]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[81]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[82]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[83]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[84]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[85]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[86]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[87]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[88]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[89]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[8]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[90]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[91]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[92]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[93]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[94]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[95]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[96]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[97]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[98]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[99]) = (0:0:0, 0:0:0);
(RX_CLK => RX_DATAOUT3[9]) = (0:0:0, 0:0:0);
(RX_CLK => RX_ENAOUT0) = (0:0:0, 0:0:0);
(RX_CLK => RX_ENAOUT1) = (0:0:0, 0:0:0);
(RX_CLK => RX_ENAOUT2) = (0:0:0, 0:0:0);
(RX_CLK => RX_ENAOUT3) = (0:0:0, 0:0:0);
(RX_CLK => RX_EOPOUT0) = (0:0:0, 0:0:0);
(RX_CLK => RX_EOPOUT1) = (0:0:0, 0:0:0);
(RX_CLK => RX_EOPOUT2) = (0:0:0, 0:0:0);
(RX_CLK => RX_EOPOUT3) = (0:0:0, 0:0:0);
(RX_CLK => RX_ERROUT0) = (0:0:0, 0:0:0);
(RX_CLK => RX_ERROUT1) = (0:0:0, 0:0:0);
(RX_CLK => RX_ERROUT2) = (0:0:0, 0:0:0);
(RX_CLK => RX_ERROUT3) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_0[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_0[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_0[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_0[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_0[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_0[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_0[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_10[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_10[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_10[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_10[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_10[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_10[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_10[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_11[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_11[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_11[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_11[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_11[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_11[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_11[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_12[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_12[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_12[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_12[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_12[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_12[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_12[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_13[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_13[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_13[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_13[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_13[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_13[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_13[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_14[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_14[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_14[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_14[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_14[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_14[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_14[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_15[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_15[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_15[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_15[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_15[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_15[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_15[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_16[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_16[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_16[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_16[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_16[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_16[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_16[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_17[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_17[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_17[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_17[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_17[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_17[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_17[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_18[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_18[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_18[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_18[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_18[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_18[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_18[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_19[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_19[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_19[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_19[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_19[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_19[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_19[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_1[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_1[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_1[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_1[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_1[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_1[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_1[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_2[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_2[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_2[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_2[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_2[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_2[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_2[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_3[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_3[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_3[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_3[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_3[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_3[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_3[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_4[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_4[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_4[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_4[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_4[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_4[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_4[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_5[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_5[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_5[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_5[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_5[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_5[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_5[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_6[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_6[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_6[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_6[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_6[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_6[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_6[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_7[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_7[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_7[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_7[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_7[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_7[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_7[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_8[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_8[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_8[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_8[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_8[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_8[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_8[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_9[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_9[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_9[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_9[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_9[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_9[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_LANE_ALIGNER_FILL_9[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT0[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT0[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT0[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT0[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT1[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT1[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT1[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT1[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT2[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT2[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT2[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT2[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT3[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT3[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT3[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_MTYOUT3[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_PCSLANE_OUT[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_PCSLANE_OUT[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_PCSLANE_OUT[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_PCSLANE_OUT[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_PCSLANE_OUT[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[0]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[10]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[11]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[12]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[13]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[14]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[15]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[16]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[17]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[18]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[19]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[1]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[20]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[21]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[22]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[23]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[24]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[25]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[26]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[27]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[28]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[29]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[2]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[30]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[31]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[32]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[33]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[34]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[35]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[36]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[37]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[38]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[39]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[3]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[40]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[41]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[42]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[43]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[44]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[45]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[46]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[47]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[48]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[49]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[4]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[50]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[51]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[52]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[53]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[54]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[55]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[56]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[57]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[58]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[59]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[5]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[60]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[61]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[62]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[63]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[64]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[65]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[66]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[67]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[68]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[69]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[6]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[70]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[71]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[72]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[73]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[74]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[75]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[76]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[77]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[78]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[79]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[7]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[8]) = (0:0:0, 0:0:0);
(RX_CLK => RX_PTP_TSTAMP_OUT[9]) = (0:0:0, 0:0:0);
(RX_CLK => RX_SOPOUT0) = (0:0:0, 0:0:0);
(RX_CLK => RX_SOPOUT1) = (0:0:0, 0:0:0);
(RX_CLK => RX_SOPOUT2) = (0:0:0, 0:0:0);
(RX_CLK => RX_SOPOUT3) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_ALIGNED) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_ALIGNED_ERR) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_CODE[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_CODE[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_CODE[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_FCS[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_FCS[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_FCS[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_FCS[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_PREAMBLE) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BAD_SFD) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_0) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_1) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_10) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_11) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_12) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_13) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_14) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_15) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_16) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_17) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_18) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_19) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_2) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_3) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_4) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_5) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_6) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_7) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_8) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BIP_ERR_9) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[16]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[17]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[18]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[19]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BLOCK_LOCK[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_BROADCAST) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAGMENT[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAGMENT[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAGMENT[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAGMENT[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_0[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_0[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_0[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_0[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_10[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_10[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_10[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_10[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_11[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_11[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_11[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_11[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_12[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_12[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_12[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_12[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_13[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_13[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_13[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_13[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_14[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_14[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_14[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_14[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_15[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_15[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_15[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_15[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_16[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_16[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_16[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_16[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_17[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_17[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_17[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_17[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_18[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_18[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_18[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_18[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_19[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_19[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_19[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_19[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_1[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_1[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_1[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_1[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_2[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_2[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_2[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_2[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_3[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_3[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_3[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_3[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_4[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_4[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_4[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_4[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_5[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_5[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_5[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_5[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_6[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_6[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_6[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_6[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_7[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_7[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_7[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_7[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_8[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_8[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_8[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_8[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_9[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_9[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_9[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_9[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_0) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_1) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_10) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_11) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_12) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_13) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_14) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_15) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_16) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_17) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_18) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_19) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_2) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_3) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_4) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_5) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_6) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_7) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_8) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_FRAMING_ERR_VALID_9) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_GOT_SIGNAL_OS) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_HI_BER) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_INRANGEERR) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_INTERNAL_LOCAL_FAULT) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_JABBER) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LANE0_VLM_BIP7_VALID) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_LOCAL_FAULT) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[16]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[17]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[18]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[19]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_ERR[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[16]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[17]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[18]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[19]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_LEN_ERR[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[16]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[17]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[18]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[19]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MF_REPEAT_ERR[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MISALIGNED) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_MULTICAST) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_OVERSIZE) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_1024_1518_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_128_255_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_1519_1522_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_1523_1548_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_1549_2047_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_2048_4095_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_256_511_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_4096_8191_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_512_1023_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_64_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_65_127_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_8192_9215_BYTES) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_BAD_FCS) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_LARGE) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_SMALL[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_SMALL[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_SMALL[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PACKET_SMALL[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA0[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA1[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA2[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA3[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA4[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA5[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA6[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA7[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_QUANTA8[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_REQ[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_PAUSE_VALID[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_RECEIVED_LOCAL_FAULT) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_REMOTE_FAULT) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_STATUS) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_STOMPED_FCS[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_STOMPED_FCS[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_STOMPED_FCS[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_STOMPED_FCS[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[16]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[17]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[18]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[19]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[16]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[17]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[18]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[19]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_SYNCED_ERR[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TEST_PATTERN_MISMATCH[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOOLONG) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_BYTES[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_BYTES[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_GOOD_PACKETS) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_PACKETS[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_PACKETS[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_PACKETS[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TOTAL_PACKETS[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_TRUNCATED) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_UNDERSIZE[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_UNDERSIZE[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_UNDERSIZE[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_UNDERSIZE[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_UNICAST) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_USER_PAUSE) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VLAN) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[10]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[11]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[12]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[13]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[14]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[15]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[16]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[17]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[18]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[19]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[5]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[6]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[7]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[8]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_DEMUXED[9]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_0[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_0[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_0[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_0[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_0[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_10[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_10[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_10[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_10[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_10[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_11[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_11[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_11[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_11[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_11[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_12[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_12[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_12[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_12[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_12[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_13[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_13[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_13[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_13[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_13[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_14[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_14[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_14[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_14[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_14[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_15[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_15[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_15[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_15[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_15[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_16[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_16[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_16[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_16[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_16[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_17[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_17[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_17[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_17[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_17[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_18[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_18[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_18[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_18[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_18[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_19[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_19[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_19[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_19[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_19[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_1[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_1[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_1[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_1[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_1[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_2[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_2[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_2[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_2[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_2[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_3[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_3[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_3[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_3[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_3[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_4[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_4[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_4[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_4[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_4[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_5[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_5[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_5[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_5[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_5[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_6[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_6[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_6[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_6[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_6[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_7[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_7[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_7[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_7[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_7[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_8[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_8[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_8[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_8[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_8[4]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_9[0]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_9[1]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_9[2]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_9[3]) = (0:0:0, 0:0:0);
(RX_CLK => STAT_RX_VL_NUMBER_9[4]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_BAD_FCS) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_BROADCAST) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_FRAME_ERROR) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_LOCAL_FAULT) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_MULTICAST) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_1024_1518_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_128_255_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_1519_1522_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_1523_1548_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_1549_2047_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_2048_4095_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_256_511_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_4096_8191_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_512_1023_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_64_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_65_127_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_8192_9215_BYTES) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_LARGE) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PACKET_SMALL) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[0]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[1]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[2]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[3]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[4]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[5]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[6]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[7]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PAUSE_VALID[8]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PTP_FIFO_READ_ERROR) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_PTP_FIFO_WRITE_ERROR) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_BYTES[0]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_BYTES[1]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_BYTES[2]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_BYTES[3]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_BYTES[4]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_BYTES[5]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_BYTES[6]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[0]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[10]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[11]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[12]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[13]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[1]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[2]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[3]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[4]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[5]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[6]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[7]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[8]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_BYTES[9]) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_GOOD_PACKETS) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_TOTAL_PACKETS) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_UNICAST) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_USER_PAUSE) = (0:0:0, 0:0:0);
(TX_CLK => STAT_TX_VLAN) = (0:0:0, 0:0:0);
(TX_CLK => TX_OVFOUT) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_PCSLANE_OUT[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_PCSLANE_OUT[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_PCSLANE_OUT[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_PCSLANE_OUT[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_PCSLANE_OUT[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[32]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[33]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[34]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[35]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[36]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[37]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[38]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[39]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[40]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[41]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[42]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[43]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[44]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[45]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[46]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[47]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[48]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[49]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[50]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[51]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[52]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[53]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[54]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[55]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[56]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[57]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[58]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[59]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[60]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[61]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[62]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[63]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[64]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[65]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[66]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[67]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[68]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[69]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[70]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[71]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[72]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[73]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[74]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[75]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[76]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[77]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[78]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[79]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_OUT[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_TAG_OUT[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_PTP_TSTAMP_VALID_OUT) = (0:0:0, 0:0:0);
(TX_CLK => TX_RDYOUT) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA0[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA1[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA2[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_ALT_DATA3[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[32]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[33]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[34]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[35]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[36]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[37]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[38]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[39]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[40]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[41]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[42]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[43]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[44]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[45]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[46]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[47]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[48]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[49]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[50]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[51]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[52]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[53]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[54]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[55]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[56]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[57]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[58]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[59]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[60]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[61]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[62]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[63]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA0[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[32]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[33]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[34]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[35]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[36]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[37]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[38]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[39]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[40]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[41]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[42]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[43]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[44]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[45]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[46]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[47]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[48]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[49]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[50]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[51]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[52]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[53]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[54]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[55]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[56]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[57]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[58]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[59]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[60]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[61]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[62]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[63]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA1[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[32]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[33]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[34]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[35]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[36]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[37]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[38]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[39]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[40]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[41]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[42]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[43]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[44]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[45]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[46]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[47]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[48]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[49]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[50]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[51]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[52]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[53]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[54]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[55]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[56]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[57]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[58]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[59]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[60]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[61]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[62]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[63]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA2[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[32]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[33]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[34]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[35]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[36]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[37]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[38]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[39]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[40]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[41]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[42]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[43]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[44]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[45]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[46]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[47]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[48]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[49]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[50]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[51]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[52]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[53]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[54]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[55]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[56]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[57]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[58]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[59]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[60]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[61]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[62]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[63]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA3[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA4[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA5[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA6[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA7[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA8[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[0]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[10]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[11]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[12]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[13]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[14]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[15]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[16]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[17]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[18]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[19]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[1]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[20]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[21]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[22]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[23]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[24]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[25]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[26]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[27]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[28]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[29]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[2]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[30]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[31]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[3]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[4]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[5]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[6]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[7]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[8]) = (0:0:0, 0:0:0);
(TX_CLK => TX_SERDES_DATA9[9]) = (0:0:0, 0:0:0);
(TX_CLK => TX_UNFOUT) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge DRP_CLK, 0:0:0, notifier);
$period (negedge RX_CLK, 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[0], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[1], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[2], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[3], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[4], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[5], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[6], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[7], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[8], 0:0:0, notifier);
$period (negedge RX_SERDES_CLK[9], 0:0:0, notifier);
$period (negedge TX_CLK, 0:0:0, notifier);
$period (posedge DRP_CLK, 0:0:0, notifier);
$period (posedge RX_CLK, 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[0], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[1], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[2], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[3], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[4], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[5], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[6], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[7], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[8], 0:0:0, notifier);
$period (posedge RX_SERDES_CLK[9], 0:0:0, notifier);
$period (posedge TX_CLK, 0:0:0, notifier);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[0]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[1]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[2]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[3]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[4]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[5]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[6]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[7]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[8]);
$recrem ( negedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[9]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]);
$recrem ( negedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]);
$recrem ( negedge RX_RESET, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_RESET_delay, RX_CLK_delay);
$recrem ( negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]);
$recrem ( negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[1]);
$recrem ( negedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[2]);
$recrem ( negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[0]);
$recrem ( negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]);
$recrem ( negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[2]);
$recrem ( negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[3]);
$recrem ( negedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[4]);
$recrem ( negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[0]);
$recrem ( negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[1]);
$recrem ( negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]);
$recrem ( negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[5]);
$recrem ( negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[6]);
$recrem ( negedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[7]);
$recrem ( negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[1]);
$recrem ( negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]);
$recrem ( negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[7]);
$recrem ( negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[8]);
$recrem ( negedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[9]);
$recrem ( negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[1]);
$recrem ( negedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]);
$recrem ( negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[2]);
$recrem ( negedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]);
$recrem ( negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[2]);
$recrem ( negedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]);
$recrem ( negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[2]);
$recrem ( negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[3]);
$recrem ( negedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]);
$recrem ( negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[3]);
$recrem ( negedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]);
$recrem ( negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[3]);
$recrem ( negedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]);
$recrem ( negedge TX_RESET, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_RESET_delay, TX_CLK_delay);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[0]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[1]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[2]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[3]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[4]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[5]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[6]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[7]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[8]);
$recrem ( posedge CTL_CAUI4_MODE, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, CTL_CAUI4_MODE_delay, RX_SERDES_CLK_delay[9]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[0]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[1]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[2]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[3]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[4]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[5]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[6]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[7]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[8]);
$recrem ( posedge CTL_RX_FORCE_RESYNC, posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, CTL_RX_FORCE_RESYNC_delay, RX_SERDES_CLK_delay[9]);
$recrem ( posedge RX_RESET, posedge RX_CLK, 0:0:0, 0:0:0, notifier,,, RX_RESET_delay, RX_CLK_delay);
$recrem ( posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[0]);
$recrem ( posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[1]);
$recrem ( posedge RX_SERDES_RESET[0], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[0], RX_SERDES_CLK_delay[2]);
$recrem ( posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[0]);
$recrem ( posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[1]);
$recrem ( posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[2]);
$recrem ( posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[3]);
$recrem ( posedge RX_SERDES_RESET[1], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[1], RX_SERDES_CLK_delay[4]);
$recrem ( posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[0]);
$recrem ( posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[1]);
$recrem ( posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[2]);
$recrem ( posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[5]);
$recrem ( posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[6]);
$recrem ( posedge RX_SERDES_RESET[2], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[2], RX_SERDES_CLK_delay[7]);
$recrem ( posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[1]);
$recrem ( posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[3]);
$recrem ( posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[7]);
$recrem ( posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[8]);
$recrem ( posedge RX_SERDES_RESET[3], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[3], RX_SERDES_CLK_delay[9]);
$recrem ( posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[1]);
$recrem ( posedge RX_SERDES_RESET[4], posedge RX_SERDES_CLK[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[4], RX_SERDES_CLK_delay[4]);
$recrem ( posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[2]);
$recrem ( posedge RX_SERDES_RESET[5], posedge RX_SERDES_CLK[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[5], RX_SERDES_CLK_delay[5]);
$recrem ( posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[2]);
$recrem ( posedge RX_SERDES_RESET[6], posedge RX_SERDES_CLK[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[6], RX_SERDES_CLK_delay[6]);
$recrem ( posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[2]);
$recrem ( posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[3]);
$recrem ( posedge RX_SERDES_RESET[7], posedge RX_SERDES_CLK[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[7], RX_SERDES_CLK_delay[7]);
$recrem ( posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[3]);
$recrem ( posedge RX_SERDES_RESET[8], posedge RX_SERDES_CLK[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[8], RX_SERDES_CLK_delay[8]);
$recrem ( posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[3]);
$recrem ( posedge RX_SERDES_RESET[9], posedge RX_SERDES_CLK[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_RESET_delay[9], RX_SERDES_CLK_delay[9]);
$recrem ( posedge TX_RESET, posedge TX_CLK, 0:0:0, 0:0:0, notifier,,, TX_RESET_delay, TX_CLK_delay);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[0]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[1]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[2]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[3]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[4]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[5]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[6]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[7]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[8]);
$setuphold (posedge DRP_CLK, negedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[9]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[0], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[0]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[10], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[10]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[11], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[11]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[12], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[12]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[13], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[13]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[14], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[14]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[15], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[15]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[1], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[1]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[2], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[2]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[3], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[3]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[4], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[4]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[5], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[5]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[6], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[6]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[7], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[7]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[8], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[8]);
$setuphold (posedge DRP_CLK, negedge DRP_DI[9], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[9]);
$setuphold (posedge DRP_CLK, negedge DRP_EN, 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_EN_delay);
$setuphold (posedge DRP_CLK, negedge DRP_WE, 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_WE_delay);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[0], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[0]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[1], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[1]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[2], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[2]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[3], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[3]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[4], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[4]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[5], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[5]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[6], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[6]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[7], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[7]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[8], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[8]);
$setuphold (posedge DRP_CLK, posedge DRP_ADDR[9], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_ADDR_delay[9]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[0], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[0]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[10], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[10]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[11], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[11]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[12], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[12]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[13], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[13]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[14], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[14]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[15], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[15]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[1], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[1]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[2], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[2]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[3], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[3]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[4], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[4]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[5], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[5]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[6], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[6]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[7], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[7]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[8], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[8]);
$setuphold (posedge DRP_CLK, posedge DRP_DI[9], 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_DI_delay[9]);
$setuphold (posedge DRP_CLK, posedge DRP_EN, 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_EN_delay);
$setuphold (posedge DRP_CLK, posedge DRP_WE, 0:0:0, 0:0:0, notifier,,, DRP_CLK_delay, DRP_WE_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_GCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_GPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_PCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_ETYPE_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_PPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_GCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_GPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_PCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_MCAST_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_PPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_GCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_GPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_PCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_OPCODE_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_PPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_GCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_GPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_PCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_SA_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_PPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_GCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_GPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_PCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_CHECK_UCAST_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_PPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_GCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_GPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_PCP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_ENABLE_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_PPP_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_FORCE_RESYNC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_FORCE_RESYNC_delay);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[0]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[1]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[2]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[3]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[4]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[5]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[6]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[7]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ACK[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[8]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[0]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[1]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[2]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[3]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[4]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[5]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[6]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[7]);
$setuphold (posedge RX_CLK, negedge CTL_RX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[8]);
$setuphold (posedge RX_CLK, negedge CTL_RX_TEST_PATTERN, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_TEST_PATTERN_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_GCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_GPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_PCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_ETYPE_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_ETYPE_PPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_GCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_GPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_PCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_MCAST_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_MCAST_PPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_GCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_GPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_PCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_OPCODE_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_OPCODE_PPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_GCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_GPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_PCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_SA_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_SA_PPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_GCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_GPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_PCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_CHECK_UCAST_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_CHECK_UCAST_PPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_GCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_GCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_GPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_GPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_PCP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_PCP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_ENABLE_PPP, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_ENABLE_PPP_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_FORCE_RESYNC, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_FORCE_RESYNC_delay);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[0]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[1]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[2]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[3]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[4]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[5]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[6]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[7]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ACK[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ACK_delay[8]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[0]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[1]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[2]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[3]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[4]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[5]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[6]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[7]);
$setuphold (posedge RX_CLK, posedge CTL_RX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_PAUSE_ENABLE_delay[8]);
$setuphold (posedge RX_CLK, posedge CTL_RX_TEST_PATTERN, 0:0:0, 0:0:0, notifier,,, RX_CLK_delay, CTL_RX_TEST_PATTERN_delay);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[0]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[10]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[11]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[12]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[13]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[14]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[15]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[16]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[17]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[18]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[19]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[1]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[20]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[21]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[22]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[23]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[24]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[25]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[26]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[27]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[28]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[29]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[2]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[30]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[31]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[32]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[33]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[34]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[35]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[36]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[37]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[38]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[39]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[3]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[40]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[41]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[42]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[43]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[44]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[45]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[46]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[47]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[48]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[49]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[4]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[50]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[51]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[52]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[53]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[54]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[55]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[56]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[57]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[58]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[59]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[5]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[60]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[61]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[62]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[63]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[64]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[65]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[66]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[67]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[68]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[69]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[6]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[70]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[71]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[72]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[73]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[74]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[75]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[76]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[77]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[78]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[79]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[7]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[8]);
$setuphold (posedge RX_SERDES_CLK[0], negedge CTL_RX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[9]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[0]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[10]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[11]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[12]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[13]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[14]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[15]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[1]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[2]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[3]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[4]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[5]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[6]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[7]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[8]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_ALT_DATA0[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[9]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[0]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[10]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[11]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[12]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[13]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[14]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[15]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[16]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[17]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[18]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[19]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[1]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[20]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[21]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[22]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[23]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[24]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[25]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[26]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[27]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[28]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[29]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[2]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[30]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[31]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[32]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[33]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[34]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[35]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[36]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[37]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[38]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[39]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[3]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[40]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[41]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[42]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[43]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[44]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[45]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[46]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[47]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[48]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[49]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[4]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[50]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[51]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[52]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[53]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[54]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[55]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[56]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[57]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[58]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[59]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[5]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[60]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[61]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[62]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[63]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[6]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[7]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[8]);
$setuphold (posedge RX_SERDES_CLK[0], negedge RX_SERDES_DATA0[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[9]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[0]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[10]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[11]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[12]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[13]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[14]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[15]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[16]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[17]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[18]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[19]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[1]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[20]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[21]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[22]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[23]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[24]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[25]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[26]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[27]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[28]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[29]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[2]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[30]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[31]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[32]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[33]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[34]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[35]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[36]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[37]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[38]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[39]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[3]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[40]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[41]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[42]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[43]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[44]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[45]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[46]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[47]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[48]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[49]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[4]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[50]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[51]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[52]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[53]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[54]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[55]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[56]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[57]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[58]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[59]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[5]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[60]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[61]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[62]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[63]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[64]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[65]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[66]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[67]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[68]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[69]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[6]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[70]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[71]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[72]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[73]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[74]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[75]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[76]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[77]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[78]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[79]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[7]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[8]);
$setuphold (posedge RX_SERDES_CLK[0], posedge CTL_RX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], CTL_RX_SYSTEMTIMERIN_delay[9]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[0]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[10]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[11]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[12]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[13]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[14]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[15]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[1]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[2]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[3]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[4]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[5]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[6]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[7]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[8]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_ALT_DATA0[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_ALT_DATA0_delay[9]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[0]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[10]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[11]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[12]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[13]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[14]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[15]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[16]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[17]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[18]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[19]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[1]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[20]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[21]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[22]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[23]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[24]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[25]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[26]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[27]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[28]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[29]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[2]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[30]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[31]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[32]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[33]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[34]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[35]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[36]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[37]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[38]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[39]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[3]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[40]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[41]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[42]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[43]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[44]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[45]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[46]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[47]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[48]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[49]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[4]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[50]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[51]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[52]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[53]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[54]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[55]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[56]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[57]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[58]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[59]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[5]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[60]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[61]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[62]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[63]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[6]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[7]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[8]);
$setuphold (posedge RX_SERDES_CLK[0], posedge RX_SERDES_DATA0[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[0], RX_SERDES_DATA0_delay[9]);
$setuphold (posedge RX_SERDES_CLK[1], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[0]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[10]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[11]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[12]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[13]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[14]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[15]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[1]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[2]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[3]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[4]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[5]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[6]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[7]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[8]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_ALT_DATA1[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[9]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[0]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[10]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[11]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[12]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[13]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[14]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[15]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[16]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[17]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[18]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[19]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[1]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[20]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[21]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[22]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[23]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[24]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[25]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[26]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[27]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[28]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[29]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[2]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[30]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[31]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[32]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[33]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[34]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[35]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[36]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[37]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[38]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[39]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[3]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[40]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[41]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[42]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[43]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[44]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[45]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[46]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[47]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[48]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[49]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[4]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[50]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[51]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[52]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[53]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[54]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[55]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[56]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[57]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[58]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[59]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[5]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[60]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[61]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[62]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[63]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[6]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[7]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[8]);
$setuphold (posedge RX_SERDES_CLK[1], negedge RX_SERDES_DATA1[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[9]);
$setuphold (posedge RX_SERDES_CLK[1], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[0]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[10]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[11]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[12]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[13]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[14]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[15]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[1]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[2]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[3]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[4]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[5]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[6]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[7]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[8]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_ALT_DATA1[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_ALT_DATA1_delay[9]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[0]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[10]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[11]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[12]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[13]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[14]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[15]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[16]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[17]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[18]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[19]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[1]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[20]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[21]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[22]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[23]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[24]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[25]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[26]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[27]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[28]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[29]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[2]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[30]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[31]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[32]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[33]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[34]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[35]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[36]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[37]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[38]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[39]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[3]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[40]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[41]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[42]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[43]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[44]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[45]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[46]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[47]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[48]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[49]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[4]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[50]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[51]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[52]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[53]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[54]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[55]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[56]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[57]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[58]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[59]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[5]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[60]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[61]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[62]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[63]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[6]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[7]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[8]);
$setuphold (posedge RX_SERDES_CLK[1], posedge RX_SERDES_DATA1[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[1], RX_SERDES_DATA1_delay[9]);
$setuphold (posedge RX_SERDES_CLK[2], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[0]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[10]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[11]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[12]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[13]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[14]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[15]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[1]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[2]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[3]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[4]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[5]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[6]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[7]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[8]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_ALT_DATA2[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[9]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[0]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[10]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[11]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[12]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[13]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[14]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[15]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[16]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[17]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[18]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[19]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[1]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[20]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[21]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[22]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[23]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[24]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[25]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[26]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[27]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[28]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[29]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[2]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[30]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[31]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[32]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[33]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[34]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[35]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[36]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[37]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[38]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[39]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[3]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[40]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[41]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[42]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[43]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[44]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[45]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[46]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[47]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[48]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[49]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[4]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[50]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[51]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[52]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[53]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[54]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[55]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[56]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[57]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[58]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[59]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[5]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[60]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[61]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[62]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[63]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[6]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[7]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[8]);
$setuphold (posedge RX_SERDES_CLK[2], negedge RX_SERDES_DATA2[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[9]);
$setuphold (posedge RX_SERDES_CLK[2], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[0]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[10]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[11]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[12]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[13]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[14]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[15]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[1]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[2]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[3]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[4]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[5]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[6]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[7]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[8]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_ALT_DATA2[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_ALT_DATA2_delay[9]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[0]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[10]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[11]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[12]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[13]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[14]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[15]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[16]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[17]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[18]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[19]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[1]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[20]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[21]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[22]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[23]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[24]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[25]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[26]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[27]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[28]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[29]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[2]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[30]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[31]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[32]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[33]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[34]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[35]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[36]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[37]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[38]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[39]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[3]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[40]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[41]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[42]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[43]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[44]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[45]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[46]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[47]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[48]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[49]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[4]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[50]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[51]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[52]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[53]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[54]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[55]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[56]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[57]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[58]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[59]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[5]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[60]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[61]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[62]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[63]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[6]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[7]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[8]);
$setuphold (posedge RX_SERDES_CLK[2], posedge RX_SERDES_DATA2[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[2], RX_SERDES_DATA2_delay[9]);
$setuphold (posedge RX_SERDES_CLK[3], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[0]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[10]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[11]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[12]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[13]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[14]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[15]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[1]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[2]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[3]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[4]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[5]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[6]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[7]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[8]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_ALT_DATA3[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[9]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[0]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[10]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[11]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[12]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[13]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[14]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[15]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[16]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[17]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[18]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[19]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[1]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[20]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[21]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[22]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[23]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[24]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[25]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[26]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[27]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[28]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[29]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[2]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[30]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[31]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[32]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[33]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[34]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[35]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[36]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[37]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[38]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[39]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[3]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[40]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[41]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[42]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[43]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[44]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[45]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[46]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[47]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[48]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[49]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[4]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[50]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[51]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[52]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[53]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[54]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[55]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[56]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[57]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[58]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[59]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[5]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[60]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[61]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[62]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[63]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[6]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[7]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[8]);
$setuphold (posedge RX_SERDES_CLK[3], negedge RX_SERDES_DATA3[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[9]);
$setuphold (posedge RX_SERDES_CLK[3], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[0]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[10]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[11]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[12]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[13]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[14]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[15]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[1]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[2]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[3]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[4]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[5]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[6]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[7]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[8]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_ALT_DATA3[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_ALT_DATA3_delay[9]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[0]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[10]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[11]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[12]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[13]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[14]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[15]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[16]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[17]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[18]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[19]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[1]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[20]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[21]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[22]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[23]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[24]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[25]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[26]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[27]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[28]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[29]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[2]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[30]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[31]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[32], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[32]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[33], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[33]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[34], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[34]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[35], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[35]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[36], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[36]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[37], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[37]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[38], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[38]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[39], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[39]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[3]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[40], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[40]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[41], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[41]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[42], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[42]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[43], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[43]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[44], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[44]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[45], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[45]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[46], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[46]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[47], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[47]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[48], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[48]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[49], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[49]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[4]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[50], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[50]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[51], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[51]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[52], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[52]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[53], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[53]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[54], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[54]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[55], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[55]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[56], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[56]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[57], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[57]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[58], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[58]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[59], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[59]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[5]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[60], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[60]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[61], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[61]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[62], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[62]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[63], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[63]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[6]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[7]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[8]);
$setuphold (posedge RX_SERDES_CLK[3], posedge RX_SERDES_DATA3[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[3], RX_SERDES_DATA3_delay[9]);
$setuphold (posedge RX_SERDES_CLK[4], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[0]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[10]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[11]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[12]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[13]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[14]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[15]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[16]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[17]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[18]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[19]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[1]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[20]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[21]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[22]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[23]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[24]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[25]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[26]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[27]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[28]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[29]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[2]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[30]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[31]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[3]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[4]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[5]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[6]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[7]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[8]);
$setuphold (posedge RX_SERDES_CLK[4], negedge RX_SERDES_DATA4[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[9]);
$setuphold (posedge RX_SERDES_CLK[4], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[0]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[10]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[11]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[12]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[13]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[14]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[15]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[16]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[17]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[18]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[19]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[1]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[20]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[21]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[22]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[23]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[24]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[25]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[26]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[27]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[28]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[29]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[2]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[30]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[31]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[3]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[4]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[5]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[6]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[7]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[8]);
$setuphold (posedge RX_SERDES_CLK[4], posedge RX_SERDES_DATA4[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[4], RX_SERDES_DATA4_delay[9]);
$setuphold (posedge RX_SERDES_CLK[5], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[0]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[10]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[11]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[12]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[13]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[14]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[15]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[16]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[17]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[18]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[19]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[1]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[20]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[21]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[22]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[23]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[24]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[25]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[26]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[27]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[28]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[29]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[2]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[30]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[31]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[3]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[4]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[5]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[6]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[7]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[8]);
$setuphold (posedge RX_SERDES_CLK[5], negedge RX_SERDES_DATA5[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[9]);
$setuphold (posedge RX_SERDES_CLK[5], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[0]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[10]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[11]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[12]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[13]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[14]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[15]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[16]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[17]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[18]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[19]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[1]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[20]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[21]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[22]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[23]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[24]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[25]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[26]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[27]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[28]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[29]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[2]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[30]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[31]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[3]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[4]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[5]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[6]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[7]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[8]);
$setuphold (posedge RX_SERDES_CLK[5], posedge RX_SERDES_DATA5[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[5], RX_SERDES_DATA5_delay[9]);
$setuphold (posedge RX_SERDES_CLK[6], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[0]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[10]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[11]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[12]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[13]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[14]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[15]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[16]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[17]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[18]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[19]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[1]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[20]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[21]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[22]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[23]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[24]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[25]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[26]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[27]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[28]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[29]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[2]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[30]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[31]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[3]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[4]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[5]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[6]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[7]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[8]);
$setuphold (posedge RX_SERDES_CLK[6], negedge RX_SERDES_DATA6[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[9]);
$setuphold (posedge RX_SERDES_CLK[6], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[0]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[10]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[11]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[12]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[13]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[14]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[15]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[16]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[17]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[18]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[19]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[1]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[20]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[21]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[22]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[23]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[24]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[25]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[26]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[27]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[28]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[29]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[2]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[30]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[31]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[3]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[4]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[5]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[6]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[7]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[8]);
$setuphold (posedge RX_SERDES_CLK[6], posedge RX_SERDES_DATA6[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[6], RX_SERDES_DATA6_delay[9]);
$setuphold (posedge RX_SERDES_CLK[7], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[0]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[10]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[11]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[12]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[13]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[14]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[15]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[16]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[17]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[18]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[19]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[1]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[20]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[21]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[22]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[23]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[24]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[25]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[26]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[27]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[28]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[29]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[2]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[30]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[31]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[3]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[4]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[5]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[6]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[7]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[8]);
$setuphold (posedge RX_SERDES_CLK[7], negedge RX_SERDES_DATA7[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[9]);
$setuphold (posedge RX_SERDES_CLK[7], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[0]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[10]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[11]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[12]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[13]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[14]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[15]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[16]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[17]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[18]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[19]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[1]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[20]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[21]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[22]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[23]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[24]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[25]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[26]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[27]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[28]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[29]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[2]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[30]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[31]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[3]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[4]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[5]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[6]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[7]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[8]);
$setuphold (posedge RX_SERDES_CLK[7], posedge RX_SERDES_DATA7[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[7], RX_SERDES_DATA7_delay[9]);
$setuphold (posedge RX_SERDES_CLK[8], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[0]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[10]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[11]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[12]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[13]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[14]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[15]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[16]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[17]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[18]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[19]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[1]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[20]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[21]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[22]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[23]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[24]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[25]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[26]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[27]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[28]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[29]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[2]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[30]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[31]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[3]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[4]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[5]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[6]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[7]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[8]);
$setuphold (posedge RX_SERDES_CLK[8], negedge RX_SERDES_DATA8[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[9]);
$setuphold (posedge RX_SERDES_CLK[8], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[0]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[10]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[11]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[12]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[13]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[14]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[15]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[16]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[17]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[18]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[19]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[1]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[20]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[21]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[22]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[23]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[24]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[25]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[26]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[27]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[28]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[29]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[2]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[30]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[31]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[3]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[4]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[5]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[6]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[7]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[8]);
$setuphold (posedge RX_SERDES_CLK[8], posedge RX_SERDES_DATA8[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[8], RX_SERDES_DATA8_delay[9]);
$setuphold (posedge RX_SERDES_CLK[9], negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[0]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[10]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[11]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[12]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[13]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[14]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[15]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[16]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[17]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[18]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[19]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[1]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[20]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[21]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[22]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[23]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[24]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[25]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[26]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[27]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[28]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[29]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[2]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[30]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[31]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[3]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[4]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[5]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[6]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[7]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[8]);
$setuphold (posedge RX_SERDES_CLK[9], negedge RX_SERDES_DATA9[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[9]);
$setuphold (posedge RX_SERDES_CLK[9], posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], CTL_CAUI4_MODE_delay);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[0], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[0]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[10], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[10]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[11], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[11]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[12], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[12]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[13], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[13]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[14], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[14]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[15], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[15]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[16], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[16]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[17], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[17]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[18], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[18]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[19], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[19]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[1], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[1]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[20], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[20]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[21], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[21]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[22], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[22]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[23], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[23]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[24], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[24]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[25], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[25]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[26], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[26]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[27], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[27]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[28], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[28]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[29], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[29]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[2], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[2]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[30], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[30]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[31], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[31]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[3], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[3]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[4], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[4]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[5], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[5]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[6], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[6]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[7], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[7]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[8], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[8]);
$setuphold (posedge RX_SERDES_CLK[9], posedge RX_SERDES_DATA9[9], 0:0:0, 0:0:0, notifier,,, RX_SERDES_CLK_delay[9], RX_SERDES_DATA9_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_CAUI4_MODE_delay);
$setuphold (posedge TX_CLK, negedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_ENABLE_delay);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA0[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA1[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA2[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA3[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA4[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA5[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA6[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA7[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_QUANTA8[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER0[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER1[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER2[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER3[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER4[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER5[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER6[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER7[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REFRESH_TIMER8[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PAUSE_REQ[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_PTP_VLANE_ADJUST_MODE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PTP_VLANE_ADJUST_MODE_delay);
$setuphold (posedge TX_CLK, negedge CTL_TX_RESEND_PAUSE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_RESEND_PAUSE_delay);
$setuphold (posedge TX_CLK, negedge CTL_TX_SEND_IDLE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SEND_IDLE_delay);
$setuphold (posedge TX_CLK, negedge CTL_TX_SEND_RFI, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SEND_RFI_delay);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[0]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[10]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[11]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[12]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[13]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[14]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[15]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[16]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[17]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[18]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[19]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[1]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[20]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[21]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[22]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[23]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[24]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[25]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[26]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[27]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[28]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[29]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[2]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[30]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[31]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[32]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[33]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[34]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[35]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[36]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[37]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[38]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[39]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[3]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[40]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[41]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[42]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[43]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[44]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[45]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[46]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[47]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[48]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[49]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[4]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[50]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[51]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[52]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[53]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[54]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[55]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[56]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[57]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[58]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[59]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[5]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[60]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[61]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[62]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[63]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[64]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[65]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[66]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[67]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[68]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[69]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[6]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[70]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[71]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[72]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[73]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[74]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[75]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[76]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[77]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[78]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[79]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[7]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[8]);
$setuphold (posedge TX_CLK, negedge CTL_TX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[9]);
$setuphold (posedge TX_CLK, negedge CTL_TX_TEST_PATTERN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_TEST_PATTERN_delay);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[100]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[101]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[102]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[103]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[104]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[105]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[106]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[107]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[108]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[109]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[110]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[111]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[112]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[113]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[114]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[115]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[116]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[117]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[118]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[119]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[120]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[121]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[122]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[123]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[124]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[125]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[126]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[127]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[16]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[17]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[18]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[19]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[20]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[21]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[22]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[23]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[24]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[25]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[26]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[27]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[28]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[29]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[30]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[31]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[32]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[33]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[34]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[35]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[36]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[37]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[38]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[39]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[40]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[41]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[42]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[43]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[44]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[45]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[46]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[47]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[48]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[49]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[50]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[51]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[52]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[53]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[54]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[55]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[56]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[57]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[58]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[59]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[60]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[61]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[62]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[63]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[64]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[65]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[66]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[67]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[68]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[69]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[70]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[71]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[72]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[73]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[74]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[75]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[76]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[77]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[78]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[79]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[80]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[81]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[82]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[83]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[84]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[85]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[86]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[87]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[88]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[89]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[90]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[91]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[92]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[93]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[94]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[95]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[96]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[97]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[98]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[99]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[100]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[101]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[102]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[103]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[104]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[105]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[106]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[107]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[108]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[109]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[110]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[111]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[112]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[113]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[114]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[115]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[116]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[117]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[118]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[119]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[120]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[121]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[122]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[123]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[124]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[125]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[126]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[127]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[16]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[17]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[18]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[19]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[20]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[21]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[22]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[23]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[24]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[25]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[26]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[27]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[28]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[29]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[30]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[31]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[32]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[33]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[34]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[35]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[36]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[37]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[38]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[39]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[40]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[41]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[42]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[43]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[44]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[45]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[46]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[47]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[48]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[49]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[50]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[51]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[52]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[53]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[54]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[55]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[56]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[57]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[58]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[59]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[60]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[61]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[62]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[63]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[64]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[65]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[66]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[67]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[68]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[69]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[70]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[71]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[72]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[73]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[74]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[75]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[76]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[77]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[78]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[79]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[80]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[81]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[82]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[83]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[84]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[85]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[86]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[87]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[88]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[89]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[90]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[91]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[92]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[93]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[94]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[95]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[96]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[97]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[98]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[99]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[100]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[101]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[102]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[103]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[104]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[105]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[106]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[107]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[108]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[109]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[110]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[111]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[112]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[113]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[114]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[115]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[116]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[117]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[118]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[119]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[120]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[121]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[122]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[123]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[124]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[125]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[126]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[127]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[16]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[17]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[18]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[19]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[20]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[21]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[22]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[23]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[24]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[25]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[26]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[27]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[28]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[29]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[30]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[31]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[32]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[33]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[34]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[35]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[36]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[37]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[38]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[39]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[40]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[41]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[42]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[43]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[44]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[45]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[46]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[47]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[48]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[49]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[50]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[51]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[52]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[53]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[54]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[55]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[56]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[57]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[58]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[59]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[60]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[61]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[62]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[63]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[64]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[65]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[66]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[67]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[68]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[69]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[70]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[71]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[72]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[73]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[74]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[75]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[76]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[77]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[78]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[79]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[80]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[81]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[82]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[83]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[84]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[85]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[86]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[87]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[88]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[89]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[90]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[91]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[92]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[93]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[94]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[95]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[96]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[97]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[98]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[99]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[100]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[101]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[102]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[103]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[104]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[105]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[106]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[107]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[108]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[109]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[110]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[111]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[112]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[113]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[114]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[115]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[116]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[117]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[118]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[119]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[120]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[121]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[122]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[123]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[124]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[125]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[126]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[127]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[16]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[17]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[18]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[19]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[20]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[21]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[22]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[23]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[24]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[25]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[26]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[27]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[28]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[29]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[30]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[31]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[32]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[33]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[34]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[35]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[36]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[37]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[38]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[39]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[40]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[41]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[42]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[43]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[44]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[45]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[46]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[47]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[48]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[49]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[50]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[51]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[52]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[53]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[54]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[55]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[56]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[57]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[58]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[59]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[60]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[61]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[62]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[63]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[64]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[65]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[66]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[67]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[68]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[69]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[70]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[71]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[72]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[73]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[74]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[75]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[76]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[77]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[78]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[79]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[80]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[81]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[82]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[83]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[84]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[85]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[86]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[87]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[88]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[89]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[90]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[91]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[92]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[93]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[94]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[95]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[96]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[97]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[98]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[99]);
$setuphold (posedge TX_CLK, negedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_ENAIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN0_delay);
$setuphold (posedge TX_CLK, negedge TX_ENAIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN1_delay);
$setuphold (posedge TX_CLK, negedge TX_ENAIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN2_delay);
$setuphold (posedge TX_CLK, negedge TX_ENAIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN3_delay);
$setuphold (posedge TX_CLK, negedge TX_EOPIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN0_delay);
$setuphold (posedge TX_CLK, negedge TX_EOPIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN1_delay);
$setuphold (posedge TX_CLK, negedge TX_EOPIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN2_delay);
$setuphold (posedge TX_CLK, negedge TX_EOPIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN3_delay);
$setuphold (posedge TX_CLK, negedge TX_ERRIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN0_delay);
$setuphold (posedge TX_CLK, negedge TX_ERRIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN1_delay);
$setuphold (posedge TX_CLK, negedge TX_ERRIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN2_delay);
$setuphold (posedge TX_CLK, negedge TX_ERRIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN3_delay);
$setuphold (posedge TX_CLK, negedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_PTP_1588OP_IN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_1588OP_IN_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_PTP_1588OP_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_1588OP_IN_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_PTP_CHKSUM_OFFSET_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[16]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[17]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[18]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[19]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[20]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[21]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[22]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[23]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[24]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[25]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[26]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[27]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[28]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[29]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[30]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[31]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[32]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[33]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[34]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[35]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[36]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[37]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[38]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[39]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[40]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[41]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[42]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[43]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[44]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[45]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[46]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[47]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[48]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[49]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[50]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[51]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[52]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[53]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[54]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[55]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[56]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[57]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[58]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[59]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[60]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[61]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[62]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_PTP_RXTSTAMP_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[0]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TAG_FIELD_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[10]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[11]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[12]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[13]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[14]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[15]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[1]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[2]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[3]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[4]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[5]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[6]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[7]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[8]);
$setuphold (posedge TX_CLK, negedge TX_PTP_TSTAMP_OFFSET_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[9]);
$setuphold (posedge TX_CLK, negedge TX_PTP_UPD_CHKSUM_IN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_UPD_CHKSUM_IN_delay);
$setuphold (posedge TX_CLK, negedge TX_SOPIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN0_delay);
$setuphold (posedge TX_CLK, negedge TX_SOPIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN1_delay);
$setuphold (posedge TX_CLK, negedge TX_SOPIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN2_delay);
$setuphold (posedge TX_CLK, negedge TX_SOPIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN3_delay);
$setuphold (posedge TX_CLK, posedge CTL_CAUI4_MODE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_CAUI4_MODE_delay);
$setuphold (posedge TX_CLK, posedge CTL_TX_ENABLE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_ENABLE_delay);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_delay);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_ENABLE[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_ENABLE_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA0[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA0_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA1[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA1_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA2[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA2_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA3[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA3_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA4[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA4_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA5[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA5_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA6[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA6_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA7[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA7_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_QUANTA8[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_QUANTA8_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER0[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER0_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER1[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER1_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER2[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER2_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER3[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER3_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER4[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER4_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER5[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER5_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER6[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER6_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER7[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER7_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REFRESH_TIMER8[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REFRESH_TIMER8_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PAUSE_REQ[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PAUSE_REQ_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_PTP_VLANE_ADJUST_MODE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_PTP_VLANE_ADJUST_MODE_delay);
$setuphold (posedge TX_CLK, posedge CTL_TX_RESEND_PAUSE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_RESEND_PAUSE_delay);
$setuphold (posedge TX_CLK, posedge CTL_TX_SEND_IDLE, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SEND_IDLE_delay);
$setuphold (posedge TX_CLK, posedge CTL_TX_SEND_RFI, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SEND_RFI_delay);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[0]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[10]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[11]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[12]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[13]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[14]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[15]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[16]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[17]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[18]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[19]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[1]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[20]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[21]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[22]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[23]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[24]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[25]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[26]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[27]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[28]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[29]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[2]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[30]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[31]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[32]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[33]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[34]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[35]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[36]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[37]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[38]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[39]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[3]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[40]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[41]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[42]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[43]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[44]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[45]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[46]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[47]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[48]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[49]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[4]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[50]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[51]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[52]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[53]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[54]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[55]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[56]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[57]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[58]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[59]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[5]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[60]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[61]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[62]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[63]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[64]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[65]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[66]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[67]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[68]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[69]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[6]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[70]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[71]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[72]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[73]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[74]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[75]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[76]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[77]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[78]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[79]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[7]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[8]);
$setuphold (posedge TX_CLK, posedge CTL_TX_SYSTEMTIMERIN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_SYSTEMTIMERIN_delay[9]);
$setuphold (posedge TX_CLK, posedge CTL_TX_TEST_PATTERN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, CTL_TX_TEST_PATTERN_delay);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[100]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[101]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[102]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[103]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[104]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[105]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[106]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[107]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[108]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[109]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[110]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[111]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[112]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[113]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[114]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[115]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[116]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[117]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[118]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[119]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[120]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[121]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[122]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[123]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[124]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[125]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[126]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[127]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[16]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[17]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[18]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[19]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[20]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[21]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[22]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[23]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[24]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[25]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[26]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[27]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[28]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[29]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[30]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[31]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[32]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[33]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[34]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[35]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[36]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[37]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[38]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[39]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[40]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[41]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[42]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[43]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[44]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[45]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[46]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[47]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[48]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[49]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[50]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[51]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[52]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[53]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[54]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[55]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[56]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[57]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[58]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[59]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[60]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[61]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[62]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[63]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[64]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[65]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[66]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[67]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[68]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[69]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[70]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[71]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[72]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[73]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[74]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[75]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[76]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[77]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[78]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[79]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[80]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[81]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[82]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[83]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[84]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[85]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[86]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[87]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[88]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[89]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[90]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[91]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[92]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[93]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[94]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[95]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[96]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[97]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[98]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[99]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN0[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN0_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[100]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[101]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[102]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[103]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[104]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[105]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[106]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[107]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[108]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[109]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[110]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[111]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[112]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[113]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[114]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[115]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[116]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[117]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[118]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[119]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[120]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[121]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[122]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[123]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[124]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[125]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[126]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[127]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[16]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[17]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[18]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[19]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[20]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[21]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[22]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[23]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[24]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[25]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[26]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[27]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[28]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[29]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[30]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[31]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[32]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[33]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[34]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[35]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[36]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[37]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[38]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[39]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[40]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[41]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[42]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[43]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[44]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[45]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[46]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[47]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[48]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[49]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[50]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[51]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[52]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[53]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[54]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[55]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[56]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[57]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[58]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[59]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[60]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[61]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[62]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[63]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[64]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[65]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[66]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[67]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[68]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[69]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[70]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[71]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[72]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[73]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[74]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[75]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[76]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[77]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[78]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[79]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[80]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[81]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[82]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[83]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[84]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[85]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[86]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[87]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[88]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[89]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[90]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[91]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[92]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[93]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[94]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[95]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[96]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[97]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[98]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[99]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN1[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN1_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[100]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[101]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[102]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[103]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[104]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[105]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[106]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[107]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[108]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[109]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[110]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[111]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[112]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[113]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[114]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[115]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[116]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[117]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[118]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[119]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[120]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[121]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[122]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[123]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[124]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[125]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[126]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[127]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[16]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[17]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[18]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[19]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[20]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[21]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[22]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[23]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[24]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[25]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[26]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[27]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[28]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[29]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[30]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[31]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[32]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[33]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[34]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[35]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[36]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[37]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[38]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[39]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[40]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[41]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[42]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[43]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[44]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[45]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[46]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[47]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[48]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[49]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[50]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[51]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[52]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[53]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[54]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[55]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[56]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[57]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[58]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[59]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[60]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[61]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[62]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[63]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[64]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[65]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[66]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[67]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[68]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[69]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[70]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[71]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[72]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[73]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[74]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[75]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[76]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[77]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[78]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[79]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[80]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[81]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[82]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[83]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[84]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[85]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[86]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[87]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[88]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[89]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[90]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[91]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[92]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[93]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[94]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[95]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[96]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[97]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[98]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[99]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN2[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN2_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[100], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[100]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[101], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[101]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[102], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[102]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[103], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[103]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[104], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[104]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[105], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[105]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[106], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[106]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[107], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[107]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[108], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[108]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[109], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[109]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[110], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[110]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[111], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[111]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[112], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[112]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[113], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[113]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[114], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[114]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[115], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[115]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[116], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[116]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[117], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[117]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[118], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[118]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[119], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[119]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[120], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[120]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[121], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[121]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[122], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[122]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[123], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[123]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[124], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[124]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[125], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[125]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[126], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[126]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[127], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[127]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[16]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[17]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[18]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[19]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[20]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[21]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[22]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[23]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[24]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[25]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[26]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[27]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[28]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[29]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[30]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[31]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[32]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[33]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[34]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[35]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[36]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[37]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[38]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[39]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[40]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[41]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[42]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[43]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[44]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[45]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[46]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[47]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[48]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[49]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[50]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[51]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[52]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[53]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[54]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[55]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[56]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[57]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[58]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[59]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[60]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[61]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[62]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[63], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[63]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[64], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[64]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[65], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[65]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[66], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[66]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[67], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[67]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[68], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[68]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[69], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[69]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[70], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[70]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[71], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[71]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[72], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[72]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[73], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[73]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[74], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[74]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[75], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[75]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[76], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[76]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[77], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[77]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[78], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[78]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[79], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[79]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[80], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[80]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[81], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[81]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[82], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[82]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[83], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[83]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[84], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[84]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[85], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[85]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[86], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[86]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[87], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[87]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[88], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[88]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[89], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[89]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[90], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[90]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[91], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[91]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[92], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[92]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[93], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[93]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[94], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[94]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[95], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[95]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[96], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[96]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[97], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[97]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[98], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[98]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[99], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[99]);
$setuphold (posedge TX_CLK, posedge TX_DATAIN3[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_DATAIN3_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_ENAIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN0_delay);
$setuphold (posedge TX_CLK, posedge TX_ENAIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN1_delay);
$setuphold (posedge TX_CLK, posedge TX_ENAIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN2_delay);
$setuphold (posedge TX_CLK, posedge TX_ENAIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ENAIN3_delay);
$setuphold (posedge TX_CLK, posedge TX_EOPIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN0_delay);
$setuphold (posedge TX_CLK, posedge TX_EOPIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN1_delay);
$setuphold (posedge TX_CLK, posedge TX_EOPIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN2_delay);
$setuphold (posedge TX_CLK, posedge TX_EOPIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_EOPIN3_delay);
$setuphold (posedge TX_CLK, posedge TX_ERRIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN0_delay);
$setuphold (posedge TX_CLK, posedge TX_ERRIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN1_delay);
$setuphold (posedge TX_CLK, posedge TX_ERRIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN2_delay);
$setuphold (posedge TX_CLK, posedge TX_ERRIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_ERRIN3_delay);
$setuphold (posedge TX_CLK, posedge TX_MTYIN0[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN0[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN0[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN0[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN0_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN1[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN1[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN1[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN1[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN1_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN2[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN2[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN2[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN2[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN2_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN3[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN3[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN3[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_MTYIN3[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_MTYIN3_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_PTP_1588OP_IN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_1588OP_IN_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_PTP_1588OP_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_1588OP_IN_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_PTP_CHKSUM_OFFSET_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_CHKSUM_OFFSET_IN_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[16], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[16]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[17], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[17]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[18], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[18]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[19], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[19]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[20], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[20]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[21], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[21]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[22], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[22]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[23], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[23]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[24], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[24]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[25], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[25]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[26], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[26]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[27], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[27]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[28], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[28]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[29], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[29]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[30], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[30]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[31], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[31]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[32], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[32]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[33], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[33]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[34], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[34]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[35], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[35]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[36], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[36]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[37], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[37]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[38], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[38]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[39], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[39]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[40], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[40]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[41], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[41]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[42], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[42]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[43], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[43]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[44], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[44]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[45], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[45]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[46], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[46]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[47], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[47]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[48], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[48]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[49], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[49]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[50], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[50]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[51], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[51]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[52], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[52]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[53], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[53]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[54], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[54]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[55], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[55]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[56], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[56]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[57], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[57]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[58], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[58]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[59], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[59]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[60], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[60]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[61], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[61]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[62], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[62]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_PTP_RXTSTAMP_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_RXTSTAMP_IN_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[0], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[0]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TAG_FIELD_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TAG_FIELD_IN_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[10], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[10]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[11], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[11]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[12], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[12]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[13], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[13]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[14], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[14]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[15], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[15]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[1], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[1]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[2], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[2]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[3], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[3]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[4], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[4]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[5], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[5]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[6], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[6]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[7], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[7]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[8], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[8]);
$setuphold (posedge TX_CLK, posedge TX_PTP_TSTAMP_OFFSET_IN[9], 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_TSTAMP_OFFSET_IN_delay[9]);
$setuphold (posedge TX_CLK, posedge TX_PTP_UPD_CHKSUM_IN, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_PTP_UPD_CHKSUM_IN_delay);
$setuphold (posedge TX_CLK, posedge TX_SOPIN0, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN0_delay);
$setuphold (posedge TX_CLK, posedge TX_SOPIN1, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN1_delay);
$setuphold (posedge TX_CLK, posedge TX_SOPIN2, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN2_delay);
$setuphold (posedge TX_CLK, posedge TX_SOPIN3, 0:0:0, 0:0:0, notifier,,, TX_CLK_delay, TX_SOPIN3_delay);
$width (negedge DRP_CLK, 0:0:0, 0, notifier);
$width (negedge RX_CLK, 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[0], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[1], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[2], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[3], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[4], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[5], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[6], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[7], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[8], 0:0:0, 0, notifier);
$width (negedge RX_SERDES_CLK[9], 0:0:0, 0, notifier);
$width (negedge TX_CLK, 0:0:0, 0, notifier);
$width (posedge DRP_CLK, 0:0:0, 0, notifier);
$width (posedge RX_CLK, 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[0], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[1], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[2], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[3], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[4], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[5], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[6], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[7], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[8], 0:0:0, 0, notifier);
$width (posedge RX_SERDES_CLK[9], 0:0:0, 0, notifier);
$width (posedge TX_CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_fifo # (
parameter P_FIFO_DATA_WIDTH = 19,
parameter P_FIFO_DEPTH_WIDTH = 7
)
(
input wr_clk,
input wr_rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_clk,
input rd_rst_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0;
localparam S_SYNC_STAGE0 = 3'b001;
localparam S_SYNC_STAGE1 = 3'b010;
localparam S_SYNC_STAGE2 = 3'b100;
reg [2:0] cur_wr_state;
reg [2:0] next_wr_state;
reg [2:0] cur_rd_state;
reg [2:0] next_rd_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_rear_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_front_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync;
(* KEEP = "TRUE", EQUIVALENT_REGISTER_REMOVAL = "NO" *) reg r_front_sync_en;
reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_front_sync_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_rear_sync_en_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DEPTH_WIDTH
:P_FIFO_ALLOC_WIDTH] r_rear_sync_addr;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_sync_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_sync_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
always @(posedge wr_clk or negedge wr_rst_n)
begin
if (wr_rst_n == 0) begin
r_rear_addr <= 0;
end
else begin
if (wr_en == 1)
r_rear_addr <= r_rear_addr + 1;
end
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_sync_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge rd_clk or negedge rd_rst_n)
begin
if (rd_rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
/////////////////////////////////////////////////////////////////////////////////////////////
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
cur_wr_state <= S_SYNC_STAGE0;
else
cur_wr_state <= next_wr_state;
end
always @(posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0)
r_rear_sync_en <= 0;
else
r_rear_sync_en <= r_rear_sync;
end
always @(posedge wr_clk)
begin
r_front_sync_en_d1 <= r_front_sync_en;
r_front_sync_en_d2 <= r_front_sync_en_d1;
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
if(r_front_sync_en_d2 == 1)
next_wr_state <= S_SYNC_STAGE1;
else
next_wr_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_wr_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_front_sync_en_d2 == 0)
next_wr_state <= S_SYNC_STAGE0;
else
next_wr_state <= S_SYNC_STAGE2;
end
default: begin
next_wr_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge wr_clk or negedge wr_rst_n)
begin
if(wr_rst_n == 0) begin
r_rear_sync_data <= 0;
r_front_sync_addr <= 0;
end
else begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_rear_sync_data <= r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_front_sync_addr <= r_front_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_wr_state)
S_SYNC_STAGE0: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE1: begin
r_rear_sync <= 0;
end
S_SYNC_STAGE2: begin
r_rear_sync <= 1;
end
default: begin
r_rear_sync <= 0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
cur_rd_state <= S_SYNC_STAGE0;
else
cur_rd_state <= next_rd_state;
end
always @(posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0)
r_front_sync_en <= 0;
else
r_front_sync_en <= r_front_sync;
end
always @(posedge rd_clk)
begin
r_rear_sync_en_d1 <= r_rear_sync_en;
r_rear_sync_en_d2 <= r_rear_sync_en_d1;
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
if(r_rear_sync_en_d2 == 1)
next_rd_state <= S_SYNC_STAGE1;
else
next_rd_state <= S_SYNC_STAGE0;
end
S_SYNC_STAGE1: begin
next_rd_state <= S_SYNC_STAGE2;
end
S_SYNC_STAGE2: begin
if(r_rear_sync_en_d2 == 0)
next_rd_state <= S_SYNC_STAGE0;
else
next_rd_state <= S_SYNC_STAGE2;
end
default: begin
next_rd_state <= S_SYNC_STAGE0;
end
endcase
end
always @ (posedge rd_clk or negedge rd_rst_n)
begin
if(rd_rst_n == 0) begin
r_front_sync_data <= 0;
r_rear_sync_addr <= 0;
end
else begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
end
S_SYNC_STAGE1: begin
r_front_sync_data <= r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH];
r_rear_sync_addr <= r_rear_sync_data;
end
S_SYNC_STAGE2: begin
end
default: begin
end
endcase
end
end
always @ (*)
begin
case(cur_rd_state)
S_SYNC_STAGE0: begin
r_front_sync <= 1;
end
S_SYNC_STAGE1: begin
r_front_sync <= 1;
end
S_SYNC_STAGE2: begin
r_front_sync <= 0;
end
default: begin
r_front_sync <= 0;
end
endcase
end
/////////////////////////////////////////////////////////////////////////////////////////////
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "WRITE_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding, r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (rd_clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (wr_clk),
.WREN (wr_en)
);
endmodule
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Register map:
//addr register type
//0 read data r
//1 write data w
//2 status r/w
//3 control r/w
//6 end-of-packet-value r/w
//INPUT_CLOCK: 116000000
//ISMASTER: 0
//DATABITS: 8
//TARGETCLOCK: 128000
//NUMSLAVES: 1
//CPOL: 0
//CPHA: 0
//LSBFIRST: 0
//EXTRADELAY: 0
//TARGETSSDELAY: 0
module wasca_spi_stm32 (
// inputs:
MOSI,
SCLK,
SS_n,
clk,
data_from_cpu,
mem_addr,
read_n,
reset_n,
spi_select,
write_n,
// outputs:
MISO,
data_to_cpu,
dataavailable,
endofpacket,
irq,
readyfordata
)
;
output MISO;
output [ 15: 0] data_to_cpu;
output dataavailable;
output endofpacket;
output irq;
output readyfordata;
input MOSI;
input SCLK;
input SS_n;
input clk;
input [ 15: 0] data_from_cpu;
input [ 2: 0] mem_addr;
input read_n;
input reset_n;
input spi_select;
input write_n;
wire E;
reg EOP;
wire MISO;
reg MOSI_reg;
reg ROE;
reg RRDY;
wire TMT;
reg TOE;
reg TRDY;
wire control_wr_strobe;
reg d1_tx_holding_emptied;
reg data_rd_strobe;
reg [ 15: 0] data_to_cpu;
reg data_wr_strobe;
wire dataavailable;
wire ds1_SCLK;
wire ds1_SS_n;
reg ds2_SCLK;
reg ds2_SS_n;
reg ds3_SS_n;
wire ds_MOSI;
wire endofpacket;
reg [ 15: 0] endofpacketvalue_reg;
wire endofpacketvalue_wr_strobe;
wire forced_shift;
reg iEOP_reg;
reg iE_reg;
reg iROE_reg;
reg iRRDY_reg;
reg iTMT_reg;
reg iTOE_reg;
reg iTRDY_reg;
wire irq;
reg irq_reg;
wire p1_data_rd_strobe;
wire [ 15: 0] p1_data_to_cpu;
wire p1_data_wr_strobe;
wire p1_rd_strobe;
wire p1_wr_strobe;
reg rd_strobe;
wire readyfordata;
wire resetShiftSample;
reg [ 7: 0] rx_holding_reg;
wire sample_clock;
reg shiftStateZero;
wire shift_clock;
reg [ 7: 0] shift_reg;
wire [ 10: 0] spi_control;
wire [ 10: 0] spi_status;
reg [ 3: 0] state;
wire status_wr_strobe;
reg transactionEnded;
reg tx_holding_emptied;
reg [ 7: 0] tx_holding_reg;
reg wr_strobe;
//spi_control_port, which is an e_avalon_slave
assign p1_rd_strobe = ~rd_strobe & spi_select & ~read_n;
// Read is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_strobe <= 0;
else
rd_strobe <= p1_rd_strobe;
end
assign p1_data_rd_strobe = p1_rd_strobe & (mem_addr == 0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_rd_strobe <= 0;
else
data_rd_strobe <= p1_data_rd_strobe;
end
assign p1_wr_strobe = ~wr_strobe & spi_select & ~write_n;
// Write is a two-cycle event.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wr_strobe <= 0;
else
wr_strobe <= p1_wr_strobe;
end
assign p1_data_wr_strobe = p1_wr_strobe & (mem_addr == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_wr_strobe <= 0;
else
data_wr_strobe <= p1_data_wr_strobe;
end
assign control_wr_strobe = wr_strobe & (mem_addr == 3);
assign status_wr_strobe = wr_strobe & (mem_addr == 2);
assign endofpacketvalue_wr_strobe = wr_strobe & (mem_addr == 6);
assign TMT = SS_n & TRDY;
assign E = ROE | TOE;
assign spi_status = {EOP, E, RRDY, TRDY, TMT, TOE, ROE, 3'b0};
// Streaming data ready for pickup.
assign dataavailable = RRDY;
// Ready to accept streaming data.
assign readyfordata = TRDY;
// Endofpacket condition detected.
assign endofpacket = EOP;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
iEOP_reg <= 0;
iE_reg <= 0;
iRRDY_reg <= 0;
iTRDY_reg <= 0;
iTMT_reg <= 0;
iTOE_reg <= 0;
iROE_reg <= 0;
end
else if (control_wr_strobe)
begin
iEOP_reg <= data_from_cpu[9];
iE_reg <= data_from_cpu[8];
iRRDY_reg <= data_from_cpu[7];
iTRDY_reg <= data_from_cpu[6];
iTMT_reg <= data_from_cpu[5];
iTOE_reg <= data_from_cpu[4];
iROE_reg <= data_from_cpu[3];
end
end
assign spi_control = {iEOP_reg, iE_reg, iRRDY_reg, iTRDY_reg, 1'b0, iTOE_reg, iROE_reg, 3'b0};
// IRQ output.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_reg <= 0;
else
irq_reg <= (EOP & iEOP_reg) | ((TOE | ROE) & iE_reg) | (RRDY & iRRDY_reg) | (TRDY & iTRDY_reg) | (TOE & iTOE_reg) | (ROE & iROE_reg);
end
assign irq = irq_reg;
// End-of-packet value register.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
endofpacketvalue_reg <= 0;
else if (endofpacketvalue_wr_strobe)
endofpacketvalue_reg <= data_from_cpu;
end
assign p1_data_to_cpu = ((mem_addr == 2))? spi_status :
((mem_addr == 3))? spi_control :
((mem_addr == 6))? endofpacketvalue_reg :
rx_holding_reg;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_to_cpu <= 0;
else
// Data to cpu.
data_to_cpu <= p1_data_to_cpu;
end
assign forced_shift = ds2_SS_n & ~ds3_SS_n;
assign ds1_SS_n = SS_n;
// System clock domain events.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
ds2_SS_n <= 1;
ds3_SS_n <= 1;
transactionEnded <= 0;
EOP <= 0;
RRDY <= 0;
TRDY <= 1;
TOE <= 0;
ROE <= 0;
tx_holding_reg <= 0;
rx_holding_reg <= 0;
d1_tx_holding_emptied <= 0;
end
else
begin
ds2_SS_n <= ds1_SS_n;
ds3_SS_n <= ds2_SS_n;
transactionEnded <= forced_shift;
d1_tx_holding_emptied <= tx_holding_emptied;
if (tx_holding_emptied & ~d1_tx_holding_emptied)
TRDY <= 1;
// EOP must be updated by the last (2nd) cycle of access.
if ((p1_data_rd_strobe && (rx_holding_reg == endofpacketvalue_reg)) || (p1_data_wr_strobe && (data_from_cpu[7 : 0] == endofpacketvalue_reg)))
EOP <= 1;
if (forced_shift)
begin
if (RRDY)
ROE <= 1;
else
rx_holding_reg <= shift_reg;
RRDY <= 1;
end
// On data read, clear the RRDY bit.
if (data_rd_strobe)
RRDY <= 0;
// On status write, clear all status bits (ignore the data).
if (status_wr_strobe)
begin
EOP <= 0;
RRDY <= 0;
ROE <= 0;
TOE <= 0;
end
// On data write, load the transmit holding register and prepare to execute.
//Safety feature: if tx_holding_reg is already occupied, ignore this write, and generate
//the write-overrun error.
if (data_wr_strobe)
begin
if (TRDY)
tx_holding_reg <= data_from_cpu;
if (~TRDY)
TOE <= 1;
TRDY <= 0;
end
end
end
assign resetShiftSample = ~reset_n | transactionEnded;
assign MISO = ~SS_n & shift_reg[7];
assign ds1_SCLK = SCLK;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
ds2_SCLK <= 0;
else
ds2_SCLK <= ds1_SCLK;
end
assign shift_clock = ((~ds1_SS_n & ~ds1_SCLK)) & ~((~ds2_SS_n & ~ds2_SCLK));
assign sample_clock = (~(~ds1_SS_n & ~ds1_SCLK)) & ~(~(~ds2_SS_n & ~ds2_SCLK));
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
state <= 0;
else
state <= resetShiftSample ? 0 : (sample_clock & (state != 8)) ? (state + 1) : state;
end
assign ds_MOSI = MOSI;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
MOSI_reg <= 0;
else
MOSI_reg <= resetShiftSample ? 0 : sample_clock ? ds_MOSI : MOSI_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
shift_reg <= 0;
else
shift_reg <= resetShiftSample ? 0 : shift_clock ? (shiftStateZero ? tx_holding_reg : {shift_reg[6 : 0], MOSI_reg}) : shift_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
shiftStateZero <= 1;
else
shiftStateZero <= resetShiftSample ? 1 : shift_clock? 0 : shiftStateZero;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
tx_holding_emptied <= 0;
else
tx_holding_emptied <= resetShiftSample ? 0 : shift_clock ? (shiftStateZero ? 1 : 0) : tx_holding_emptied;
end
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: dangling_port.v,v 1.1 2001/07/08 03:22:08 sib4 Exp $
// $Log: dangling_port.v,v $
// Revision 1.1 2001/07/08 03:22:08 sib4
// Test for PR#209
//
//
// Test for PR#209, VVP wrong nodangle of dangling port.
module main;
reg retval;
reg a, b;
function f;
input dangle;
begin
f = retval;
end
endfunction
initial
begin
#1 retval <= 1;
#1 a <= f(0);
#1 b <= f(1);
#1 $display("PASSED");
$finish;
end
endmodule
|
module unpipeline #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 1,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = slave_read & ~master_waitrequest;
assign slave_readdata = master_readdata;
endmodule
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Tue May 13 23:58:38 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub
// /home/keith/Documents/VHDL-lib/top/lab_5/part_3/ip/clk_base/clk_base_stub.v
// Design : clk_base
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_base(clk_raw, clk_250MHz, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_raw,clk_250MHz,locked" */;
input clk_raw;
output clk_250MHz;
output locked;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_FUNCTIONAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_1_data_stream_1_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_1_data_stream_1_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "auto";
parameter DATA_WIDTH = 32'd8;
parameter ADDR_WIDTH = 32'd1;
parameter DEPTH = 32'd2;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_1_data_stream_1_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_1_data_stream_1_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="pointer_basic,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=2,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=211,HLS_SYN_LUT=228,HLS_VERSION=2018_2}" *)
module pointer_basic (
ap_clk,
ap_rst_n,
s_axi_pointer_basic_io_AWVALID,
s_axi_pointer_basic_io_AWREADY,
s_axi_pointer_basic_io_AWADDR,
s_axi_pointer_basic_io_WVALID,
s_axi_pointer_basic_io_WREADY,
s_axi_pointer_basic_io_WDATA,
s_axi_pointer_basic_io_WSTRB,
s_axi_pointer_basic_io_ARVALID,
s_axi_pointer_basic_io_ARREADY,
s_axi_pointer_basic_io_ARADDR,
s_axi_pointer_basic_io_RVALID,
s_axi_pointer_basic_io_RREADY,
s_axi_pointer_basic_io_RDATA,
s_axi_pointer_basic_io_RRESP,
s_axi_pointer_basic_io_BVALID,
s_axi_pointer_basic_io_BREADY,
s_axi_pointer_basic_io_BRESP,
interrupt
);
parameter ap_ST_fsm_state1 = 3'd1;
parameter ap_ST_fsm_state2 = 3'd2;
parameter ap_ST_fsm_state3 = 3'd4;
parameter C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH = 32;
parameter C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH = 5;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input ap_clk;
input ap_rst_n;
input s_axi_pointer_basic_io_AWVALID;
output s_axi_pointer_basic_io_AWREADY;
input [C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH - 1:0] s_axi_pointer_basic_io_AWADDR;
input s_axi_pointer_basic_io_WVALID;
output s_axi_pointer_basic_io_WREADY;
input [C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH - 1:0] s_axi_pointer_basic_io_WDATA;
input [C_S_AXI_POINTER_BASIC_IO_WSTRB_WIDTH - 1:0] s_axi_pointer_basic_io_WSTRB;
input s_axi_pointer_basic_io_ARVALID;
output s_axi_pointer_basic_io_ARREADY;
input [C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH - 1:0] s_axi_pointer_basic_io_ARADDR;
output s_axi_pointer_basic_io_RVALID;
input s_axi_pointer_basic_io_RREADY;
output [C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH - 1:0] s_axi_pointer_basic_io_RDATA;
output [1:0] s_axi_pointer_basic_io_RRESP;
output s_axi_pointer_basic_io_BVALID;
input s_axi_pointer_basic_io_BREADY;
output [1:0] s_axi_pointer_basic_io_BRESP;
output interrupt;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [2:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_ready;
wire [31:0] d_i;
reg d_o_ap_vld;
reg [31:0] acc;
reg [31:0] d_read_reg_52;
wire [31:0] acc_assign_fu_41_p2;
reg [31:0] acc_assign_reg_57;
wire ap_CS_fsm_state2;
wire ap_CS_fsm_state3;
reg [2:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 3'd1;
#0 acc = 32'd0;
end
pointer_basic_pointer_basic_io_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_POINTER_BASIC_IO_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_POINTER_BASIC_IO_DATA_WIDTH ))
pointer_basic_pointer_basic_io_s_axi_U(
.AWVALID(s_axi_pointer_basic_io_AWVALID),
.AWREADY(s_axi_pointer_basic_io_AWREADY),
.AWADDR(s_axi_pointer_basic_io_AWADDR),
.WVALID(s_axi_pointer_basic_io_WVALID),
.WREADY(s_axi_pointer_basic_io_WREADY),
.WDATA(s_axi_pointer_basic_io_WDATA),
.WSTRB(s_axi_pointer_basic_io_WSTRB),
.ARVALID(s_axi_pointer_basic_io_ARVALID),
.ARREADY(s_axi_pointer_basic_io_ARREADY),
.ARADDR(s_axi_pointer_basic_io_ARADDR),
.RVALID(s_axi_pointer_basic_io_RVALID),
.RREADY(s_axi_pointer_basic_io_RREADY),
.RDATA(s_axi_pointer_basic_io_RDATA),
.RRESP(s_axi_pointer_basic_io_RRESP),
.BVALID(s_axi_pointer_basic_io_BVALID),
.BREADY(s_axi_pointer_basic_io_BREADY),
.BRESP(s_axi_pointer_basic_io_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle),
.d_o(acc_assign_reg_57),
.d_o_ap_vld(d_o_ap_vld),
.d_i(d_i)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
acc <= acc_assign_fu_41_p2;
acc_assign_reg_57 <= acc_assign_fu_41_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
d_read_reg_52 <= d_i;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
d_o_ap_vld = 1'b1;
end else begin
d_o_ap_vld = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign acc_assign_fu_41_p2 = (acc + d_read_reg_52);
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
endmodule //pointer_basic
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: gsu_umult.v
// /___/ /\ Timestamp: Fri Oct 02 08:35:52 2020
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// Device : 3s400pq208-4
// Input file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.ngc
// Output file : D:/prj/sd2snes/verilog/sd2snes_gsu/ipcore_dir/tmp/_cg/gsu_umult.v
// # of Modules : 1
// Design Name : gsu_umult
// Xilinx : D:\Xilinx\14.7\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module gsu_umult (
p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
output [15 : 0] p;
input [7 : 0] a;
input [7 : 0] b;
// synthesis translate_off
wire \blk00000001/sig00000011 ;
wire \NLW_blk00000001/blk00000003_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ;
MULT18X18 \blk00000001/blk00000003 (
.A({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , a[7], a[6],
a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 ,
\blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , \blk00000001/sig00000011 , b[7], b[6],
b[5], b[4], b[3], b[2], b[1], b[0]}),
.P({\NLW_blk00000001/blk00000003_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000003_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000003_P<16>_UNCONNECTED ,
p[15], p[14], p[13], p[12], p[11], p[10], p[9], p[8], p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0]})
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000011 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
`timescale 1 ns / 1 ps
module draw_fifo_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 3
)
(
// Users to add ports here
output reg [15:0] x1,
output reg [15:0] y1,
output reg [15:0] x2,
output reg [15:0] y2,
output reg [15:0] x3,
output reg [15:0] c1,
output reg [15:0] c2,
output reg [15:0] c3,
output wire ap_rstn,
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 + 2: 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the // privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 + 2: 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 + 2 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 + 2: 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 0;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 2
reg slv_rstn = 'b0;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
wire fifo_empty;
wire fifo_full;
wire ren;
reg fifo_ren2 = 'b0;
reg [2:0] state = 3'h0;
wire [31:0] fifo_dout;
reg [31:0] x1y1PreLoad = 32'h0;
reg [31:0] x2y2PreLoad = 32'h0;
reg [31:0] x3c1PreLoad = 32'h0;
reg [31:0] c2c3PreLoad = 32'h0;
reg fifo_next;
reg fifo_start = 'b0;
reg fifo_busy = 'b0;
reg fifo_prefetch = 'b0;
assign ap_start = fifo_start && (~ap_ready || (state == 3'd4));
always @(posedge S_AXI_ACLK) begin
if (ap_start)
fifo_busy <= 'b1;
else if (ap_ready)
fifo_busy <= 'b0;
end
// control FIFO
assign ren = (state < 3'd4);
always @(posedge S_AXI_ACLK) begin
fifo_ren2 <= ren & ~fifo_empty;
fifo_next <= ap_idle && fifo_empty && (state == 4'd0) && ~fifo_start;
end
// load register until state == 3'h4
// preStart means shift register is 'full'
always @(posedge S_AXI_ACLK) begin
if (~slv_rstn) begin
x1 <= x1;
y1 <= y1;
x2 <= x2;
y2 <= y2;
x3 <= x3;
c1 <= c1;
c2 <= c2;
c3 <= c3;
x1y1PreLoad <= x1y1PreLoad;
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= c2c3PreLoad;
state <= 3'h0;
fifo_start <= 'b0;
fifo_prefetch <= 'b0;
end
else if (state == 3'h4) begin
if (~fifo_start || ap_ready) begin
// draw parameter loaded and the engine is ready
x1 <= x1y1PreLoad[15:0];
y1 <= x1y1PreLoad[31:16];
x2 <= x2y2PreLoad[15:0];
y2 <= x2y2PreLoad[31:16];
x3 <= x3c1PreLoad[15:0];
c1 <= x3c1PreLoad[31:16];
c2 <= c2c3PreLoad[15:0];
c3 <= c2c3PreLoad[31:16];
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= c2c3PreLoad;
fifo_prefetch <= fifo_prefetch;
// start the engine
fifo_start <= 'b1;
if (fifo_prefetch) begin
// next data prefetched
x1y1PreLoad <= fifo_dout;
state <= 3'h1;
end
else begin
// next not ready
x1y1PreLoad <= x1y1PreLoad;
state <= 3'h0;
end
end
else begin
// wait for the engine done
x1 <= x1;
y1 <= y1;
x2 <= x2;
y2 <= y2;
x3 <= x3;
c1 <= c1;
c2 <= c2;
c3 <= c3;
x1y1PreLoad <= x1y1PreLoad;
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= c2c3PreLoad;
fifo_prefetch <= fifo_prefetch;
fifo_start <= fifo_start;
state <= state;
end
end
else begin
x1 <= x1;
y1 <= y1;
x2 <= x2;
y2 <= y2;
x3 <= x3;
c1 <= c1;
c2 <= c2;
c3 <= c3;
fifo_start <= ap_ready ? 'b0 : fifo_start;
if (fifo_ren2) begin
// fifo can be read; load a word
// shift registers
case (state)
3'd0:
begin
x1y1PreLoad <= fifo_dout;
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= c2c3PreLoad;
fifo_prefetch <= 'b0;
end
3'd1:
begin
x1y1PreLoad <= x1y1PreLoad;
x2y2PreLoad <= fifo_dout;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= c2c3PreLoad;
fifo_prefetch <= 'b0;
end
3'd2:
begin
x1y1PreLoad <= x1y1PreLoad;
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= fifo_dout;
c2c3PreLoad <= c2c3PreLoad;
fifo_prefetch <= 'b0;
end
3'd3:
begin
x1y1PreLoad <= x1y1PreLoad;
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= fifo_dout;
fifo_prefetch <= ~fifo_empty;
end
default:
begin
x1y1PreLoad <= x1y1PreLoad;
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= c2c3PreLoad;
fifo_prefetch <= fifo_prefetch;
end
endcase
// update the regsiter count
state <= state + 3'h1;
end
else begin
// wait for next data
x1y1PreLoad <= x1y1PreLoad;
x2y2PreLoad <= x2y2PreLoad;
x3c1PreLoad <= x3c1PreLoad;
c2c3PreLoad <= c2c3PreLoad;
fifo_start <= ap_ready ? 'b0 : fifo_start;
fifo_prefetch <= fifo_prefetch;
state <= state;
end
end
end
// I/O Connections assignments
assign ap_rstn = slv_rstn;
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
wire fifo_wen = slv_reg_wren && (axi_awaddr[2] == 1'h0);
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_rstn <= 'b0;
end
else
if (slv_reg_wren
&& (axi_awaddr[2] == 1'h1)
&& (S_AXI_WSTRB[3] == 'b1)
) begin
slv_rstn <= S_AXI_WDATA[31];
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[4:2] )
3'h0 : reg_data_out <= {30'h0, fifo_full, fifo_next};
3'h1 : reg_data_out <= {slv_rstn, ap_start, fifo_busy, 25'h0, ap_idle, state};
3'h2 : reg_data_out <= {y1, x1};
3'h3 : reg_data_out <= x1y1PreLoad;
3'h4 : reg_data_out <= {y2, x2};
3'h5 : reg_data_out <= x2y2PreLoad;
3'h6 : reg_data_out <= {c1, x3};
3'h7 : reg_data_out <= x3c1PreLoad;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
draw_fifo draw_fifo (
.srst (~slv_rstn),
.clk (S_AXI_ACLK),
.din (S_AXI_WDATA),
.wr_en (fifo_wen),
.rd_en (ren),
.dout (fifo_dout),
.full (fifo_full),
.empty (fifo_empty)
);
// User logic ends
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
rst_sync_l, rst_both_l, rst_async_l, d, clk
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input clk; // To sub1 of sub1.v, ...
input d; // To sub1 of sub1.v, ...
input rst_async_l; // To sub2 of sub2.v
input rst_both_l; // To sub1 of sub1.v, ...
input rst_sync_l; // To sub1 of sub1.v
// End of automatics
sub1 sub1 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_sync_l (rst_sync_l),
.d (d));
sub2 sub2 (/*AUTOINST*/
// Inputs
.clk (clk),
.rst_both_l (rst_both_l),
.rst_async_l (rst_async_l),
.d (d));
endmodule
module sub1 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_sync_l, d
);
input clk;
input rst_both_l;
input rst_sync_l;
//input rst_async_l;
input d;
reg q1;
reg q2;
always @(posedge clk) begin
if (~rst_sync_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2) ;
end
endmodule
module sub2 (/*AUTOARG*/
// Inputs
clk, rst_both_l, rst_async_l, d
);
input clk;
input rst_both_l;
//input rst_sync_l;
input rst_async_l;
input d;
reg q1;
reg q2;
reg q3;
always @(posedge clk or negedge rst_async_l) begin
if (~rst_async_l) begin
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
q1 <= 1'h0;
// End of automatics
end else begin
q1 <= d;
end
end
always @(posedge clk or negedge rst_both_l) begin
q2 <= (~rst_both_l) ? 1'b0 : d;
end
// Make there be more async uses than sync uses
always @(posedge clk or negedge rst_both_l) begin
q3 <= (~rst_both_l) ? 1'b0 : d;
if (0 && q1 && q2 && q3) ;
end
endmodule
|
module MUX2x1(
out,
sel,
in0,
in1
);
parameter width = 8;
output wire [width - 1 : 0] out;
input wire sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
assign out = (sel == 2'h0) ? in0 : in1;
endmodule
module MUX4x1(
out,
sel,
in0,
in1,
in2,
in3
);
parameter width = 8;
output wire [width - 1 : 0] out;
input wire [1:0] sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
input wire [width - 1 : 0] in2;
input wire [width - 1 : 0] in3;
assign out = (sel == 2'h0) ? in0 :
(sel == 2'h1) ? in1 :
(sel == 2'h2) ? in2 : in3;
endmodule
module MUX8x1(
out,
sel,
in0,
in1,
in2,
in3,
in4,
in5,
in6,
in7
);
parameter width = 8;
output wire [width - 1 : 0] out;
input wire [2:0] sel;
input wire [width - 1 : 0] in0;
input wire [width - 1 : 0] in1;
input wire [width - 1 : 0] in2;
input wire [width - 1 : 0] in3;
input wire [width - 1 : 0] in4;
input wire [width - 1 : 0] in5;
input wire [width - 1 : 0] in6;
input wire [width - 1 : 0] in7;
assign out = (sel == 3'h0) ? in0 :
(sel == 3'h1) ? in1 :
(sel == 3'h2) ? in2 :
(sel == 3'h3) ? in3 :
(sel == 3'h4) ? in4 :
(sel == 3'h5) ? in5 :
(sel == 3'h6) ? in6 : in7;
endmodule |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:10:16 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_selector_A, FSM_selector_C, exp_oper_result_8_,
Exp_module_Overflow_flag_A, Sgf_operation_EVEN1_left_N9,
Sgf_operation_EVEN1_left_N8, Sgf_operation_EVEN1_left_N7,
Sgf_operation_EVEN1_left_N6, Sgf_operation_EVEN1_left_N5,
Sgf_operation_EVEN1_left_N4, Sgf_operation_EVEN1_left_N3,
Sgf_operation_EVEN1_left_N2, Sgf_operation_EVEN1_left_N1,
Sgf_operation_EVEN1_left_N0, Sgf_operation_EVEN1_middle_N9,
Sgf_operation_EVEN1_middle_N8, Sgf_operation_EVEN1_middle_N7,
Sgf_operation_EVEN1_middle_N6, Sgf_operation_EVEN1_middle_N5,
Sgf_operation_EVEN1_middle_N4, Sgf_operation_EVEN1_middle_N3,
Sgf_operation_EVEN1_middle_N2, Sgf_operation_EVEN1_middle_N1,
Sgf_operation_EVEN1_middle_N0, Sgf_operation_EVEN1_right_N10,
Sgf_operation_EVEN1_right_N9, Sgf_operation_EVEN1_right_N8,
Sgf_operation_EVEN1_right_N7, Sgf_operation_EVEN1_right_N6,
Sgf_operation_EVEN1_right_N5, Sgf_operation_EVEN1_right_N4,
Sgf_operation_EVEN1_right_N3, Sgf_operation_EVEN1_right_N2,
Sgf_operation_EVEN1_right_N1, Sgf_operation_EVEN1_right_N0, n167,
n169, n170, n171, n172, n173, n174, n175, n176, n177, n178, n179,
n180, n181, n182, n183, n184, n185, n186, n187, n188, n189, n190,
n191, n192, n193, n194, n195, n196, n197, n198, n199, n200, n201,
n202, n203, n204, n205, n206, n207, n208, n209, n210, n211, n212,
n213, n214, n215, n216, n217, n218, n219, n220, n221, n222, n223,
n224, n225, n226, n227, n228, n229, n230, n231, n232, n233, n234,
n235, n236, n237, n238, n239, n240, n241, n242, n243, n244, n245,
n246, n247, n248, n249, n250, n251, n252, n253, n254, n255, n256,
n257, n258, n259, n260, n261, n262, n263, n264, n265, n266, n267,
n268, n269, n270, n271, n272, n273, n274, n275, n276, n277, n278,
n279, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n319, n320, n321, n322, n323, n324, n326,
n327, n328, n331, n333, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n346, n348, n350, n354, n356, n358, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, DP_OP_111J16_123_4462_n891, DP_OP_111J16_123_4462_n880,
DP_OP_111J16_123_4462_n831, DP_OP_111J16_123_4462_n827,
DP_OP_111J16_123_4462_n821, DP_OP_111J16_123_4462_n820,
DP_OP_111J16_123_4462_n792, DP_OP_111J16_123_4462_n785,
DP_OP_111J16_123_4462_n783, DP_OP_111J16_123_4462_n774,
DP_OP_111J16_123_4462_n773, DP_OP_111J16_123_4462_n767,
DP_OP_111J16_123_4462_n766, DP_OP_111J16_123_4462_n758,
DP_OP_111J16_123_4462_n757, DP_OP_111J16_123_4462_n754,
DP_OP_111J16_123_4462_n753, DP_OP_111J16_123_4462_n752,
DP_OP_111J16_123_4462_n751, DP_OP_111J16_123_4462_n749,
DP_OP_111J16_123_4462_n744, DP_OP_111J16_123_4462_n728,
DP_OP_111J16_123_4462_n720, DP_OP_111J16_123_4462_n713,
DP_OP_111J16_123_4462_n707, DP_OP_111J16_123_4462_n699,
DP_OP_111J16_123_4462_n698, DP_OP_111J16_123_4462_n697,
DP_OP_111J16_123_4462_n695, DP_OP_111J16_123_4462_n694,
DP_OP_111J16_123_4462_n685, DP_OP_111J16_123_4462_n684,
DP_OP_111J16_123_4462_n683, DP_OP_111J16_123_4462_n682,
DP_OP_111J16_123_4462_n680, DP_OP_111J16_123_4462_n625,
DP_OP_111J16_123_4462_n620, DP_OP_111J16_123_4462_n619,
DP_OP_111J16_123_4462_n617, DP_OP_111J16_123_4462_n616,
DP_OP_111J16_123_4462_n607, DP_OP_111J16_123_4462_n606,
DP_OP_111J16_123_4462_n605, DP_OP_111J16_123_4462_n224,
DP_OP_111J16_123_4462_n220, DP_OP_111J16_123_4462_n219,
DP_OP_111J16_123_4462_n168, DP_OP_111J16_123_4462_n161,
DP_OP_111J16_123_4462_n160, DP_OP_111J16_123_4462_n159,
DP_OP_111J16_123_4462_n158, DP_OP_111J16_123_4462_n150,
DP_OP_111J16_123_4462_n149, DP_OP_111J16_123_4462_n140,
DP_OP_111J16_123_4462_n130, DP_OP_111J16_123_4462_n128,
DP_OP_111J16_123_4462_n123, DP_OP_111J16_123_4462_n117,
DP_OP_111J16_123_4462_n116, DP_OP_111J16_123_4462_n106,
DP_OP_111J16_123_4462_n103, DP_OP_111J16_123_4462_n97,
DP_OP_111J16_123_4462_n96, DP_OP_111J16_123_4462_n94,
DP_OP_111J16_123_4462_n89, DP_OP_111J16_123_4462_n83,
DP_OP_111J16_123_4462_n82, DP_OP_111J16_123_4462_n72,
DP_OP_111J16_123_4462_n71, DP_OP_111J16_123_4462_n59,
DP_OP_111J16_123_4462_n58, DP_OP_111J16_123_4462_n48,
DP_OP_111J16_123_4462_n46, DP_OP_111J16_123_4462_n45,
DP_OP_111J16_123_4462_n39, DP_OP_111J16_123_4462_n36,
DP_OP_111J16_123_4462_n21, DP_OP_111J16_123_4462_n20,
DP_OP_111J16_123_4462_n19, DP_OP_111J16_123_4462_n18,
DP_OP_111J16_123_4462_n17, DP_OP_111J16_123_4462_n16,
DP_OP_111J16_123_4462_n15, DP_OP_111J16_123_4462_n14,
DP_OP_111J16_123_4462_n12, DP_OP_111J16_123_4462_n11,
DP_OP_111J16_123_4462_n10, DP_OP_111J16_123_4462_n9,
DP_OP_111J16_123_4462_n8, DP_OP_111J16_123_4462_n7,
DP_OP_111J16_123_4462_n6, add_x_19_n308, add_x_19_n272, add_x_19_n271,
add_x_19_n243, add_x_19_n232, add_x_19_n221, add_x_19_n216,
add_x_19_n215, add_x_19_n213, add_x_19_n205, add_x_19_n204,
add_x_19_n202, add_x_19_n201, add_x_19_n197, add_x_19_n194,
add_x_19_n186, add_x_19_n185, add_x_19_n179, add_x_19_n178,
add_x_19_n176, add_x_19_n168, add_x_19_n161, add_x_19_n160,
add_x_19_n152, add_x_19_n142, add_x_19_n141, add_x_19_n132,
add_x_19_n130, add_x_19_n125, add_x_19_n124, add_x_19_n122,
add_x_19_n104, add_x_19_n94, add_x_19_n85, add_x_19_n67, add_x_19_n57,
add_x_19_n51, add_x_19_n47, add_x_19_n39, add_x_19_n24, add_x_19_n19,
add_x_19_n18, add_x_19_n17, add_x_19_n16, add_x_19_n15, add_x_19_n14,
add_x_19_n13, add_x_19_n12, add_x_19_n11, add_x_19_n10, add_x_19_n9,
add_x_19_n8, add_x_19_n7, mult_x_23_a_0_, mult_x_23_n554,
mult_x_23_n553, mult_x_23_n552, mult_x_23_n551, mult_x_23_n550,
mult_x_23_n549, mult_x_23_n546, mult_x_23_n545, mult_x_23_n541,
mult_x_23_n540, mult_x_23_n533, mult_x_23_n530, mult_x_23_n525,
mult_x_23_n524, mult_x_23_n523, mult_x_23_n521, mult_x_23_n520,
mult_x_23_n518, mult_x_23_n517, mult_x_23_n516, mult_x_23_n492,
mult_x_23_n480, mult_x_23_n472, mult_x_23_n470, mult_x_23_n461,
mult_x_23_n459, mult_x_23_n194, mult_x_23_n190, mult_x_23_n141,
mult_x_23_n140, mult_x_23_n127, mult_x_23_n121, mult_x_23_n120,
mult_x_23_n114, mult_x_23_n113, mult_x_23_n109, mult_x_23_n101,
mult_x_23_n100, mult_x_23_n99, mult_x_23_n97, mult_x_23_n94,
mult_x_23_n88, mult_x_23_n87, mult_x_23_n81, mult_x_23_n78,
mult_x_23_n71, mult_x_23_n65, mult_x_23_n50, mult_x_23_n49,
mult_x_23_n47, mult_x_23_n39, mult_x_23_n38, mult_x_23_n36,
mult_x_23_n21, mult_x_23_n20, mult_x_23_n19, mult_x_23_n18,
mult_x_23_n17, mult_x_23_n16, mult_x_23_n15, mult_x_23_n14,
mult_x_23_n13, mult_x_23_n12, mult_x_23_n11, mult_x_23_n10,
mult_x_23_n9, mult_x_23_n8, mult_x_23_n7, mult_x_23_n6,
mult_x_55_a_8_, mult_x_55_a_0_, mult_x_55_n583, mult_x_55_n570,
mult_x_55_n569, mult_x_55_n568, mult_x_55_n567, mult_x_55_n566,
mult_x_55_n565, mult_x_55_n562, mult_x_55_n559, mult_x_55_n557,
mult_x_55_n556, mult_x_55_n555, mult_x_55_n554, mult_x_55_n544,
mult_x_55_n543, mult_x_55_n538, mult_x_55_n537, mult_x_55_n536,
mult_x_55_n535, mult_x_55_n533, mult_x_55_n532, mult_x_55_n531,
mult_x_55_n530, mult_x_55_n529, mult_x_55_n506, mult_x_55_n505,
mult_x_55_n504, mult_x_55_n494, mult_x_55_n490, mult_x_55_n480,
mult_x_55_n479, mult_x_55_n449, mult_x_55_n448, mult_x_55_n446,
mult_x_55_n445, mult_x_55_n444, mult_x_55_n270, mult_x_55_n188,
mult_x_55_n130, mult_x_55_n121, mult_x_55_n116, mult_x_55_n115,
mult_x_55_n95, mult_x_55_n94, mult_x_55_n88, mult_x_55_n87,
mult_x_55_n78, mult_x_55_n72, mult_x_55_n71, mult_x_55_n69,
mult_x_55_n59, mult_x_55_n58, mult_x_55_n56, mult_x_55_n48,
mult_x_55_n47, mult_x_55_n45, mult_x_55_n32, mult_x_55_n18,
mult_x_55_n17, mult_x_55_n16, mult_x_55_n15, mult_x_55_n14,
mult_x_55_n13, mult_x_55_n12, mult_x_55_n11, mult_x_55_n10,
mult_x_55_n9, mult_x_55_n8, mult_x_55_n7, mult_x_55_n6, mult_x_55_n4,
mult_x_55_n3, DP_OP_111J16_123_4462_n778, add_x_19_n310, n390, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n419, n420, n421, n424, n425, n426, n427, n428, n429, n430, n431,
n432, n433, n434, n435, n436, n437, n438, n439, n440, n441, n442,
n443, n444, n445, n446, n447, n448, n449, n450, n451, n452, n453,
n454, n455, n456, n457, n458, n459, n460, n461, n462, n463, n464,
n465, n466, n467, n468, n469, n470, n471, n472, n473, n474, n475,
n476, n477, n478, n479, n480, n481, n482, n483, n484, n485, n486,
n487, n488, n489, n490, n491, n492, n493, n494, n495, n496, n497,
n498, n499, n500, n501, n502, n503, n504, n505, n506, n507, n508,
n509, n510, n511, n512, n513, n514, n515, n516, n517, n518, n519,
n520, n521, n522, n523, n524, n526, n527, n528, n529, n530, n531,
n532, n533, n534, n535, n536, n537, n538, n539, n540, n541, n542,
n543, n544, n545, n546, n547, n548, n549, n550, n551, n552, n553,
n554, n555, n556, n557, n558, n559, n560, n561, n562, n563, n564,
n565, n566, n567, n568, n569, n570, n571, n572, n573, n574, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708,
n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719,
n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906,
n907, n908, n909, n910, n911, n912, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1105, n1106,
n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116,
n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126,
n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136,
n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061,
n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071,
n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081,
n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091,
n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101,
n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111,
n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181,
n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191,
n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201,
n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211,
n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221,
n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231,
n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241,
n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251,
n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261,
n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271,
n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281,
n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291,
n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301,
n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311,
n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321,
n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331,
n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341,
n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411,
n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421,
n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431,
n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441,
n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451,
n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461,
n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471,
n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481,
n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491,
n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501,
n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511,
n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521,
n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531,
n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541,
n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551,
n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561,
n3562, n3563, n3565, n3566, n3567, n3568, n3569, n3570, n3572, n3573,
n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583,
n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593,
n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603,
n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613,
n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623,
n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633,
n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643,
n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653,
n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663,
n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673,
n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683,
n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693,
n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703,
n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713,
n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723,
n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733,
n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743,
n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753,
n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763,
n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773,
n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783,
n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793,
n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803,
n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813,
n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823,
n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833,
n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843,
n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853,
n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863,
n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873,
n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883,
n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893,
n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903,
n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913,
n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923,
n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933,
n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943,
n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953,
n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963,
n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973,
n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983,
n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993,
n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003,
n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013,
n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023,
n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033,
n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043,
n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053,
n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063,
n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4072, n4073;
wire [19:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [23:1] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [24:0] Sgf_operation_Result;
wire [9:0] Sgf_operation_EVEN1_Q_middle;
wire [9:0] Sgf_operation_EVEN1_Q_left;
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_left_N1), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[1]) );
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_right_N4), .CK(clk), .Q(Sgf_operation_Result[4])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_right_N5), .CK(clk), .Q(Sgf_operation_Result[5])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_right_N7), .CK(clk), .Q(Sgf_operation_Result[7])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_right_N8), .CK(clk), .Q(Sgf_operation_Result[8])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_right_N9), .CK(clk), .Q(Sgf_operation_Result[9])
);
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_10_ ( .D(
Sgf_operation_EVEN1_right_N10), .CK(clk), .Q(Sgf_operation_Result[10])
);
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(clk), .RN(
n4060), .Q(Op_MY[31]) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[1]), .QN(n3930) );
DFFRX4TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[2]), .QN(n3906) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n379), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[3]), .QN(n3928) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(n378), .CK(clk), .RN(n3973), .Q(
FS_Module_state_reg[0]) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n4063), .Q(FSM_selector_A),
.QN(n3900) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n3648), .Q(Op_MX[26]), .QN(n3905) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n3972), .Q(Op_MX[25]), .QN(n3908) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n873), .Q(Op_MX[24]), .QN(n3981) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(clk), .RN(n4060),
.Q(Add_result[7]), .QN(n3955) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(clk), .RN(n4060),
.Q(Add_result[6]), .QN(n3956) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(clk), .RN(n4060),
.Q(Add_result[5]), .QN(n3954) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(clk), .RN(n4060),
.Q(Add_result[3]), .QN(n3957) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(clk), .RN(n4060),
.Q(Add_result[2]), .QN(n3958) );
DFFRX4TS R_31 ( .D(n324), .CK(clk), .RN(n412), .Q(Op_MY[12]), .QN(n867) );
DFFRX4TS R_1194 ( .D(n323), .CK(clk), .RN(n414), .Q(Op_MY[11]), .QN(n1451)
);
DFFRX2TS R_1075 ( .D(n319), .CK(clk), .RN(n413), .Q(Op_MY[7]) );
DFFRX4TS R_32 ( .D(n312), .CK(clk), .RN(n4062), .Q(Op_MY[0]), .QN(n1461) );
DFFRX4TS Sel_B_Q_reg_0_ ( .D(n309), .CK(clk), .RN(n4062), .Q(
FSM_selector_B[0]), .QN(n3909) );
DFFRX4TS Sel_B_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n4062), .Q(
FSM_selector_B[1]), .QN(n707) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(clk), .RN(n4062),
.QN(n3896) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n274), .CK(clk), .RN(n873),
.QN(n3903) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n234), .CK(clk), .RN(
n3973), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n233), .CK(clk), .RN(
n3977), .Q(P_Sgf[18]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n232), .CK(clk), .RN(
n4057), .Q(P_Sgf[17]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(clk), .RN(
n4057), .Q(P_Sgf[16]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(clk), .RN(
n3974), .Q(P_Sgf[15]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(clk), .RN(
n3976), .Q(P_Sgf[14]) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n227), .CK(clk), .RN(
n3976), .Q(P_Sgf[12]), .QN(n1448) );
DFFRX2TS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n226), .CK(clk), .RN(
n3976), .Q(P_Sgf[11]), .QN(n1449) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(clk), .RN(
n4056), .Q(P_Sgf[0]), .QN(n3940) );
DFFRX2TS R_772 ( .D(n2865), .CK(clk), .RN(n872), .Q(n4049) );
DFFRX2TS R_1064 ( .D(n4039), .CK(clk), .RN(n4067), .Q(n4040) );
DFFRX4TS R_151 ( .D(n326), .CK(clk), .RN(n411), .Q(mult_x_23_n524), .QN(
n4029) );
DFFRXLTS R_1137 ( .D(n358), .CK(clk), .RN(n409), .Q(n4046) );
DFFRX4TS R_120 ( .D(n315), .CK(clk), .RN(n411), .Q(mult_x_55_n536), .QN(
n4026) );
DFFRXLTS R_1038 ( .D(n314), .CK(clk), .RN(n414), .Q(n4035) );
DFFRXLTS R_243 ( .D(n380), .CK(clk), .RN(n3973), .Q(n4022) );
DFFRXLTS R_249 ( .D(n257), .CK(clk), .RN(n3975), .Q(n4020) );
DFFRXLTS R_252 ( .D(n258), .CK(clk), .RN(n3975), .Q(n4019) );
DFFRXLTS R_255 ( .D(n259), .CK(clk), .RN(n876), .Q(n4018) );
DFFRXLTS R_258 ( .D(n261), .CK(clk), .RN(n4072), .Q(n4017) );
DFFRXLTS R_261 ( .D(n252), .CK(clk), .RN(n876), .Q(n4016) );
DFFRXLTS R_264 ( .D(n253), .CK(clk), .RN(n876), .Q(n4015) );
DFFRXLTS R_267 ( .D(n254), .CK(clk), .RN(n3975), .Q(n4014) );
DFFRXLTS R_270 ( .D(n255), .CK(clk), .RN(n3975), .Q(n4013) );
DFFRXLTS R_273 ( .D(n256), .CK(clk), .RN(n3975), .Q(n4012) );
DFFRXLTS R_335 ( .D(n251), .CK(clk), .RN(n3975), .Q(n4011) );
DFFRX4TS R_89 ( .D(n356), .CK(clk), .RN(n908), .Q(mult_x_23_a_0_), .QN(n4008) );
DFFRXLTS R_364 ( .D(n249), .CK(clk), .RN(n4056), .Q(n4007) );
DFFRXLTS R_370 ( .D(n250), .CK(clk), .RN(n3975), .Q(n4005) );
DFFRXLTS R_665 ( .D(mult_x_55_n567), .CK(clk), .RN(n3649), .Q(n4047) );
DFFRXLTS R_858 ( .D(n333), .CK(clk), .RN(n4061), .Q(n4045) );
DFFRXLTS R_1156 ( .D(DP_OP_111J16_123_4462_n891), .CK(clk), .RN(n3979), .Q(
n4024) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(clk), .RN(n4059),
.Q(Add_result[10]), .QN(n3923) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(clk), .RN(n4059),
.Q(Add_result[12]), .QN(n3921) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(clk), .RN(n4065), .Q(final_result_ieee[31]), .QN(n3971) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(clk), .RN(n4058), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(clk), .RN(n4073), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(clk), .RN(n3734), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(clk), .RN(n3878), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(clk), .RN(n874), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(clk), .RN(n3647), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(clk), .RN(n873), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(clk), .RN(n4073), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(clk), .RN(n4073), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(clk), .RN(n4073), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(clk), .RN(n409), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(clk), .RN(n908), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(clk), .RN(n4066), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(clk), .RN(n409), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(clk), .RN(n908), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(clk), .RN(n4066), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(clk), .RN(n4066), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(clk), .RN(n408), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(clk), .RN(n908), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(clk), .RN(n4066), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(clk), .RN(n4067), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(clk), .RN(n4065), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(clk), .RN(n4065), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(clk), .RN(n4065), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(clk), .RN(n4065), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(clk), .RN(n4065), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(clk), .RN(n4065), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(clk), .RN(n4065), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(clk), .RN(n4065), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(clk), .RN(n4065), .Q(final_result_ieee[0]) );
DFFRX1TS R_668 ( .D(mult_x_55_n565), .CK(clk), .RN(n878), .Q(Op_MX[11]),
.QN(n3960) );
DFFRX1TS R_121 ( .D(mult_x_55_n533), .CK(clk), .RN(n4062), .QN(n4038) );
DFFRX1TS R_145 ( .D(n314), .CK(clk), .RN(n3880), .QN(n4033) );
DFFRX1TS R_139 ( .D(DP_OP_111J16_123_4462_n891), .CK(clk), .RN(n3877), .QN(
n4037) );
DFFRX1TS R_750 ( .D(mult_x_23_n552), .CK(clk), .RN(n4062), .Q(Op_MX[17]),
.QN(n3993) );
DFFRX1TS R_65 ( .D(mult_x_55_n567), .CK(clk), .RN(n4073), .QN(n4031) );
DFFRXLTS R_1110 ( .D(mult_x_55_a_0_), .CK(clk), .RN(n908), .Q(Op_MX[0]),
.QN(n3951) );
DFFRXLTS R_149 ( .D(DP_OP_111J16_123_4462_n880), .CK(clk), .RN(n3979), .QN(
n4027) );
DFFRX1TS R_675 ( .D(n354), .CK(clk), .RN(n871), .Q(n4051), .QN(n4010) );
DFFRXLTS R_999 ( .D(mult_x_23_n518), .CK(clk), .RN(n412), .Q(Op_MY[20]),
.QN(n4028) );
DFFRX1TS R_682 ( .D(mult_x_23_n554), .CK(clk), .RN(n4073), .Q(Op_MX[13]),
.QN(n4043) );
DFFRX1TS R_671 ( .D(mult_x_55_n566), .CK(clk), .RN(n878), .Q(Op_MX[9]), .QN(
n4032) );
DFFRXLTS R_337 ( .D(mult_x_55_n570), .CK(clk), .RN(n4058), .Q(Op_MX[1]),
.QN(n3959) );
DFFRXLTS R_874 ( .D(n327), .CK(clk), .RN(n414), .Q(n4054), .QN(n4023) );
DFFRX1TS R_279 ( .D(mult_x_55_n568), .CK(clk), .RN(n4073), .QN(n3997) );
DFFRX1TS R_663 ( .D(mult_x_23_n550), .CK(clk), .RN(n4073), .Q(n4052), .QN(
n3996) );
DFFRX2TS R_752 ( .D(mult_x_23_n553), .CK(clk), .RN(n871), .QN(n733) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(clk), .RN(
n4056), .Q(P_Sgf[5]), .QN(n3967) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(clk), .RN(
n4056), .Q(P_Sgf[1]), .QN(n3963) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(clk), .RN(
n4056), .Q(P_Sgf[6]), .QN(n3968) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(clk), .RN(
n906), .Q(P_Sgf[2]), .QN(n3964) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(clk), .RN(
n3974), .Q(P_Sgf[9]), .QN(n3961) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(clk), .RN(
n906), .Q(P_Sgf[7]), .QN(n3969) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(clk), .RN(
n906), .Q(P_Sgf[3]), .QN(n3965) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(clk), .RN(
n4056), .Q(P_Sgf[8]), .QN(n3970) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(clk), .RN(
n4056), .Q(P_Sgf[4]), .QN(n3966) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(clk), .RN(n872), .Q(
Exp_module_Overflow_flag_A), .QN(n3962) );
DFFRX2TS R_870 ( .D(mult_x_55_a_8_), .CK(clk), .RN(n874), .Q(Op_MX[8]) );
DFFRX2TS R_679 ( .D(n348), .CK(clk), .RN(n4061), .Q(Op_MX[4]), .QN(n737) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n272), .CK(clk), .RN(n4066),
.Q(underflow_flag), .QN(n3935) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(clk),
.RN(n874), .Q(Sgf_normalized_result[3]), .QN(n3929) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n204), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[13]), .QN(n3944) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(clk),
.RN(n4067), .Q(Sgf_normalized_result[7]), .QN(n3939) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[12]), .QN(n3932) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n205), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[14]), .QN(n3941) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n207), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[16]), .QN(n3938) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(clk),
.RN(n4063), .Q(Sgf_normalized_result[2]), .QN(n437) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(clk),
.RN(n874), .Q(Sgf_normalized_result[6]), .QN(n3936) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(clk),
.RN(n3876), .Q(Sgf_normalized_result[0]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_middle_N4), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[4]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_middle_N6), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[6]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_middle_N7), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[7]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_middle_N8), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[8]) );
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_right_N1), .CK(clk), .Q(Sgf_operation_Result[1])
);
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_middle_N0), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[0]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_2_ ( .D(
Sgf_operation_EVEN1_middle_N2), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[2]) );
DFFHQX4TS Sgf_operation_EVEN1_middle_DatO_reg_3_ ( .D(
Sgf_operation_EVEN1_middle_N3), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[3]) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_left_N6), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[6]) );
DFFRX1TS R_841 ( .D(n236), .CK(clk), .RN(n447), .Q(n3989) );
DFFRX1TS R_844 ( .D(n237), .CK(clk), .RN(n447), .Q(n3987) );
DFFRX1TS R_850 ( .D(n239), .CK(clk), .RN(n4056), .Q(n3983) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_left_N0), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[0]) );
DFFHQX4TS DP_OP_111J16_123_4462_R_1081 ( .D(DP_OP_111J16_123_4462_n150),
.CK(clk), .Q(n3871) );
DFFHQX4TS DP_OP_111J16_123_4462_R_987 ( .D(n833), .CK(clk), .Q(n3856) );
DFFHQX4TS DP_OP_111J16_123_4462_R_947 ( .D(DP_OP_111J16_123_4462_n83), .CK(
clk), .Q(n3854) );
DFFHQX4TS DP_OP_111J16_123_4462_R_224 ( .D(DP_OP_111J16_123_4462_n9), .CK(
clk), .Q(n3811) );
DFFHQX2TS DP_OP_111J16_123_4462_R_218 ( .D(DP_OP_111J16_123_4462_n10), .CK(
clk), .Q(n3808) );
DFFHQX4TS DP_OP_111J16_123_4462_R_436 ( .D(DP_OP_111J16_123_4462_n140), .CK(
clk), .Q(n3822) );
DFFHQX4TS DP_OP_111J16_123_4462_R_352 ( .D(DP_OP_111J16_123_4462_n106), .CK(
clk), .Q(n3820) );
DFFHQX2TS DP_OP_111J16_123_4462_R_238 ( .D(DP_OP_111J16_123_4462_n17), .CK(
clk), .Q(n3815) );
DFFQX1TS DP_OP_111J16_123_4462_R_1061 ( .D(DP_OP_111J16_123_4462_n158), .CK(
clk), .Q(n3868) );
DFFQX1TS DP_OP_111J16_123_4462_R_1062 ( .D(DP_OP_111J16_123_4462_n159), .CK(
clk), .Q(n3869) );
DFFHQX2TS DP_OP_111J16_123_4462_R_456 ( .D(DP_OP_111J16_123_4462_n59), .CK(
clk), .Q(n3824) );
DFFQX1TS DP_OP_111J16_123_4462_R_450 ( .D(DP_OP_111J16_123_4462_n72), .CK(
clk), .Q(n3823) );
DFFQX1TS DP_OP_111J16_123_4462_R_926 ( .D(DP_OP_111J16_123_4462_n94), .CK(
clk), .Q(n3853) );
DFFHQX4TS DP_OP_111J16_123_4462_R_1164 ( .D(DP_OP_111J16_123_4462_n219),
.CK(clk), .Q(n3875) );
DFFQX1TS DP_OP_111J16_123_4462_R_658 ( .D(n3883), .CK(clk), .Q(n3834) );
DFFRX4TS DP_OP_111J16_123_4462_R_1103 ( .D(n3838), .CK(clk), .RN(n3876), .Q(
DP_OP_111J16_123_4462_n751) );
DFFSX4TS DP_OP_111J16_123_4462_R_1104 ( .D(n3874), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n753) );
DFFRX4TS DP_OP_111J16_123_4462_R_1085 ( .D(n3873), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n606), .QN(n3894) );
DFFSX2TS DP_OP_111J16_123_4462_R_1084 ( .D(n3872), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n616) );
DFFRX4TS DP_OP_111J16_123_4462_R_1071 ( .D(n3881), .CK(clk), .RN(n3877), .Q(
DP_OP_111J16_123_4462_n831) );
DFFSX4TS DP_OP_111J16_123_4462_R_1044 ( .D(n3852), .CK(clk), .SN(n871), .Q(
DP_OP_111J16_123_4462_n749) );
DFFRX4TS DP_OP_111J16_123_4462_R_1043 ( .D(n3863), .CK(clk), .RN(n3978), .Q(
DP_OP_111J16_123_4462_n821) );
DFFRX4TS DP_OP_111J16_123_4462_R_1025 ( .D(n3866), .CK(clk), .RN(n3880), .Q(
DP_OP_111J16_123_4462_n698), .QN(n3888) );
DFFRX4TS DP_OP_111J16_123_4462_R_1019 ( .D(n3865), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n607), .QN(n3887) );
DFFSX4TS DP_OP_111J16_123_4462_R_1015 ( .D(n3841), .CK(clk), .SN(n3978), .Q(
DP_OP_111J16_123_4462_n744) );
DFFRX4TS DP_OP_111J16_123_4462_R_1011 ( .D(n3861), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n605), .QN(n3889) );
DFFSX4TS DP_OP_111J16_123_4462_R_1010 ( .D(n3860), .CK(clk), .SN(n409), .Q(
DP_OP_111J16_123_4462_n680), .QN(n3893) );
DFFSX4TS DP_OP_111J16_123_4462_R_1009 ( .D(n730), .CK(clk), .SN(n409), .Q(
DP_OP_111J16_123_4462_n713), .QN(n740) );
DFFRX4TS DP_OP_111J16_123_4462_R_1007 ( .D(n3859), .CK(clk), .RN(n408), .Q(
DP_OP_111J16_123_4462_n699), .QN(n3886) );
DFFSX4TS DP_OP_111J16_123_4462_R_1003 ( .D(n3857), .CK(clk), .SN(n3735), .Q(
DP_OP_111J16_123_4462_n625) );
DFFSX4TS DP_OP_111J16_123_4462_R_993 ( .D(n649), .CK(clk), .SN(n3978), .Q(
DP_OP_111J16_123_4462_n754) );
DFFRX4TS DP_OP_111J16_123_4462_R_968 ( .D(n3855), .CK(clk), .RN(n3735), .Q(
DP_OP_111J16_123_4462_n697), .QN(n3890) );
DFFSX4TS DP_OP_111J16_123_4462_R_907 ( .D(n3849), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n684), .QN(n898) );
DFFSX4TS DP_OP_111J16_123_4462_R_905 ( .D(n3848), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n685), .QN(n896) );
DFFRX4TS DP_OP_111J16_123_4462_R_903 ( .D(n3847), .CK(clk), .RN(n3879), .Q(
DP_OP_111J16_123_4462_n695), .QN(n3892) );
DFFSX4TS DP_OP_111J16_123_4462_R_830 ( .D(n3800), .CK(clk), .SN(n3877), .Q(
n727) );
DFFSX4TS DP_OP_111J16_123_4462_R_831 ( .D(n3844), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n728) );
DFFRX4TS DP_OP_111J16_123_4462_R_822 ( .D(n3882), .CK(clk), .RN(n3879), .Q(
n3837), .QN(n1445) );
DFFSX4TS DP_OP_111J16_123_4462_R_819 ( .D(n3843), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n683), .QN(n734) );
DFFSX4TS DP_OP_111J16_123_4462_R_742 ( .D(n3799), .CK(clk), .SN(n872), .Q(
DP_OP_111J16_123_4462_n757) );
DFFSX4TS DP_OP_111J16_123_4462_R_744 ( .D(n3839), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n766) );
DFFRX4TS DP_OP_111J16_123_4462_R_820 ( .D(n3882), .CK(clk), .RN(n3879), .Q(
DP_OP_111J16_123_4462_n707), .QN(n880) );
DFFSX4TS DP_OP_111J16_123_4462_R_685 ( .D(n3836), .CK(clk), .SN(n3879), .Q(
DP_OP_111J16_123_4462_n694), .QN(n3891) );
DFFSX4TS DP_OP_111J16_123_4462_R_618 ( .D(n3801), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n767), .QN(n3885) );
DFFSX4TS DP_OP_111J16_123_4462_R_620 ( .D(n3831), .CK(clk), .SN(n872), .Q(
DP_OP_111J16_123_4462_n758) );
DFFSX4TS DP_OP_111J16_123_4462_R_427 ( .D(n3803), .CK(clk), .SN(n3876), .QN(
n1446) );
DFFSX4TS DP_OP_111J16_123_4462_R_289 ( .D(n3797), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n773) );
DFFSX4TS DP_OP_111J16_123_4462_R_278 ( .D(n3817), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n774) );
DFFSX4TS DP_OP_111J16_123_4462_R_277 ( .D(n3816), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n783) );
DFFSX4TS DP_OP_111J16_123_4462_R_1018 ( .D(n3796), .CK(clk), .SN(n3876), .Q(
DP_OP_111J16_123_4462_n820) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[9]), .QN(n3945) );
DFFSX1TS add_x_19_R_1142 ( .D(add_x_19_n216), .CK(clk), .SN(n875), .Q(n3784)
);
DFFSX1TS add_x_19_R_1125 ( .D(add_x_19_n232), .CK(clk), .SN(n875), .Q(n3776)
);
DFFSX2TS add_x_19_R_1078 ( .D(add_x_19_n160), .CK(clk), .SN(n876), .Q(n3773),
.QN(n1462) );
DFFSX2TS add_x_19_R_1133 ( .D(add_x_19_n124), .CK(clk), .SN(n3793), .Q(n3780) );
DFFSX2TS add_x_19_R_1035 ( .D(add_x_19_n178), .CK(clk), .SN(n3792), .Q(n3771) );
DFFSX2TS add_x_19_R_1130 ( .D(add_x_19_n272), .CK(clk), .SN(n3790), .Q(n3778) );
DFFSX2TS add_x_19_R_1134 ( .D(add_x_19_n132), .CK(clk), .SN(n3793), .Q(n3781) );
DFFSX2TS add_x_19_R_1082 ( .D(add_x_19_n310), .CK(clk), .SN(n3790), .QN(
n1447) );
DFFSX2TS add_x_19_R_1141 ( .D(add_x_19_n215), .CK(clk), .SN(n3976), .Q(n3783) );
DFFSX2TS add_x_19_R_1140 ( .D(add_x_19_n243), .CK(clk), .SN(n3976), .Q(n3782) );
DFFSX1TS add_x_19_R_1099 ( .D(add_x_19_n213), .CK(clk), .SN(n875), .Q(n3775)
);
DFFSX1TS add_x_19_R_1126 ( .D(add_x_19_n19), .CK(clk), .SN(n875), .Q(n3777)
);
DFFRXLTS add_x_19_R_1094 ( .D(add_x_19_n24), .CK(clk), .RN(n3793), .Q(n3774)
);
DFFSX1TS add_x_19_R_985 ( .D(add_x_19_n221), .CK(clk), .SN(n876), .Q(n3769)
);
DFFSX1TS add_x_19_R_1145 ( .D(n2984), .CK(clk), .SN(n3792), .Q(n3785) );
DFFRX2TS add_x_19_R_1147_RW_0 ( .D(add_x_19_n160), .CK(clk), .RN(n3792), .Q(
n3787) );
DFFRX2TS add_x_19_R_1146 ( .D(add_x_19_n185), .CK(clk), .RN(n447), .Q(n3786)
);
DFFRX4TS add_x_19_R_1131 ( .D(add_x_19_n204), .CK(clk), .RN(n3977), .Q(n3779) );
DFFSX4TS add_x_19_R_986 ( .D(add_x_19_n18), .CK(clk), .SN(n4057), .Q(n3770)
);
DFFSX1TS add_x_19_R_967 ( .D(add_x_19_n186), .CK(clk), .SN(n4057), .Q(n3768)
);
DFFSX1TS add_x_19_R_966 ( .D(add_x_19_n185), .CK(clk), .SN(n3976), .Q(n3767)
);
DFFSX2TS add_x_19_R_940 ( .D(add_x_19_n17), .CK(clk), .SN(n3977), .Q(n3766)
);
DFFSX1TS add_x_19_R_777 ( .D(add_x_19_n194), .CK(clk), .SN(n3792), .Q(n3765)
);
DFFRXLTS add_x_19_R_764 ( .D(add_x_19_n202), .CK(clk), .RN(n3977), .Q(n3764)
);
DFFSX1TS add_x_19_R_730 ( .D(add_x_19_n168), .CK(clk), .SN(n4057), .Q(n3763)
);
DFFSX1TS add_x_19_R_644 ( .D(add_x_19_n14), .CK(clk), .SN(n875), .Q(n3762)
);
DFFSX1TS add_x_19_R_642 ( .D(add_x_19_n12), .CK(clk), .SN(n3974), .Q(n3761)
);
DFFSX1TS add_x_19_R_637 ( .D(add_x_19_n13), .CK(clk), .SN(n3974), .Q(n3760)
);
DFFSX1TS add_x_19_R_635 ( .D(add_x_19_n15), .CK(clk), .SN(n3977), .Q(n3759)
);
DFFSX1TS add_x_19_R_631 ( .D(add_x_19_n11), .CK(clk), .SN(n3977), .Q(n3758)
);
DFFSX1TS add_x_19_R_629 ( .D(add_x_19_n10), .CK(clk), .SN(n3974), .Q(n3757)
);
DFFSX1TS add_x_19_R_608 ( .D(add_x_19_n9), .CK(clk), .SN(n420), .Q(n3756) );
DFFSX1TS add_x_19_R_576 ( .D(add_x_19_n130), .CK(clk), .SN(n3790), .Q(n3754)
);
DFFSX1TS add_x_19_R_458 ( .D(add_x_19_n8), .CK(clk), .SN(n421), .Q(n3753) );
DFFSX1TS add_x_19_R_421 ( .D(n1798), .CK(clk), .SN(n420), .Q(n3752) );
DFFSX1TS add_x_19_R_419 ( .D(n706), .CK(clk), .SN(n421), .Q(n3751) );
DFFSX1TS add_x_19_R_415 ( .D(n1859), .CK(clk), .SN(n3790), .Q(n3749) );
DFFSX1TS add_x_19_R_409 ( .D(n1875), .CK(clk), .SN(n3790), .Q(n3747) );
DFFSX1TS add_x_19_R_407 ( .D(n1878), .CK(clk), .SN(n3790), .Q(n3746) );
DFFSX1TS add_x_19_R_405 ( .D(n1467), .CK(clk), .SN(n421), .Q(n3745) );
DFFSX1TS add_x_19_R_403 ( .D(n1460), .CK(clk), .SN(n3793), .QN(n742) );
DFFHQX4TS mult_x_23_R_1128 ( .D(mult_x_23_n194), .CK(clk), .Q(n3727) );
DFFHQX4TS mult_x_23_R_1127 ( .D(mult_x_23_n140), .CK(clk), .Q(n3726) );
DFFHQX4TS mult_x_23_R_1129 ( .D(n1257), .CK(clk), .Q(n3728) );
DFFHQX4TS mult_x_23_R_490 ( .D(mult_x_23_n88), .CK(clk), .Q(n3689) );
DFFHQX4TS mult_x_23_R_970 ( .D(mult_x_23_n120), .CK(clk), .Q(n3707) );
DFFHQX4TS mult_x_23_R_972 ( .D(mult_x_23_n121), .CK(clk), .Q(n3709) );
DFFHQX4TS mult_x_23_R_971 ( .D(mult_x_23_n140), .CK(clk), .Q(n3708) );
DFFHQX4TS mult_x_23_R_1117 ( .D(mult_x_23_n140), .CK(clk), .Q(n3723) );
DFFHQX2TS mult_x_23_R_431 ( .D(mult_x_23_n19), .CK(clk), .Q(n3682) );
DFFHQX2TS mult_x_23_R_426 ( .D(mult_x_23_n18), .CK(clk), .Q(n3681) );
DFFHQX2TS mult_x_23_R_312 ( .D(mult_x_23_n16), .CK(clk), .Q(n3679) );
DFFHQX2TS mult_x_23_R_307 ( .D(mult_x_23_n15), .CK(clk), .Q(n3678) );
DFFHQX2TS mult_x_23_R_204 ( .D(mult_x_23_n14), .CK(clk), .Q(n3676) );
DFFHQX4TS mult_x_23_R_58 ( .D(mult_x_23_n12), .CK(clk), .Q(n3673) );
DFFHQX2TS mult_x_23_R_56 ( .D(mult_x_23_n11), .CK(clk), .Q(n3672) );
DFFHQX4TS mult_x_23_R_52 ( .D(mult_x_23_n9), .CK(clk), .Q(n3670) );
DFFHQX4TS mult_x_23_R_50 ( .D(mult_x_23_n8), .CK(clk), .Q(n3669) );
DFFHQX4TS mult_x_23_R_453 ( .D(mult_x_23_n109), .CK(clk), .Q(n3686) );
DFFHQX1TS mult_x_23_R_305 ( .D(mult_x_23_n81), .CK(clk), .Q(n3677) );
DFFHQX1TS mult_x_23_R_977 ( .D(mult_x_23_n7), .CK(clk), .Q(n3712) );
DFFHQX4TS mult_x_23_R_990 ( .D(mult_x_23_n140), .CK(clk), .Q(n3713) );
DFFHQX4TS mult_x_23_R_885 ( .D(mult_x_23_n50), .CK(clk), .Q(n3704) );
DFFHQX4TS mult_x_23_R_854 ( .D(mult_x_23_n39), .CK(clk), .Q(n3700) );
DFFHQX4TS mult_x_23_R_825 ( .D(mult_x_23_n65), .CK(clk), .Q(n3698) );
DFFHQX4TS mult_x_23_R_884 ( .D(mult_x_23_n49), .CK(clk), .Q(n3703) );
DFFHQX4TS mult_x_23_R_853 ( .D(mult_x_23_n38), .CK(clk), .Q(n3699) );
DFFRX4TS mult_x_23_R_1150 ( .D(mult_x_23_n520), .CK(clk), .RN(n3979), .Q(
n3666), .QN(n3739) );
DFFSX4TS mult_x_23_R_1144 ( .D(n3729), .CK(clk), .SN(n3880), .QN(n3738) );
DFFRX4TS mult_x_23_R_1138 ( .D(n3561), .CK(clk), .RN(n878), .Q(n3692), .QN(
n705) );
DFFSX4TS mult_x_23_R_1112 ( .D(n3694), .CK(clk), .SN(n3735), .Q(
mult_x_23_n546) );
DFFSX4TS mult_x_23_R_1114 ( .D(n2943), .CK(clk), .SN(n3734), .Q(n3675), .QN(
n840) );
DFFSX1TS mult_x_23_R_1113 ( .D(n3722), .CK(clk), .SN(n3880), .Q(
mult_x_23_n470) );
DFFRX4TS mult_x_23_R_1106 ( .D(n3721), .CK(clk), .RN(n3734), .Q(
mult_x_23_n533), .QN(n3737) );
DFFRX4TS mult_x_23_R_1097 ( .D(mult_x_23_n516), .CK(clk), .RN(n3978), .Q(
n3664), .QN(n3741) );
DFFSX1TS mult_x_23_R_1091 ( .D(n3720), .CK(clk), .SN(n3735), .Q(
mult_x_23_n461) );
DFFRX4TS mult_x_23_R_1092 ( .D(mult_x_23_n525), .CK(clk), .RN(n3979), .Q(
n3667), .QN(n3743) );
DFFSX1TS mult_x_23_R_1069 ( .D(n3719), .CK(clk), .SN(n3735), .Q(
mult_x_23_n459) );
DFFSX4TS mult_x_23_R_1065 ( .D(n3718), .CK(clk), .SN(n3734), .Q(
mult_x_23_n541), .QN(n888) );
DFFSX4TS mult_x_23_R_1105 ( .D(n3693), .CK(clk), .SN(n3734), .Q(n3668), .QN(
n3742) );
DFFSX4TS mult_x_23_R_1136 ( .D(n3716), .CK(clk), .SN(n869), .Q(
mult_x_23_n549) );
DFFSX1TS mult_x_23_R_1000 ( .D(n3715), .CK(clk), .SN(n3880), .Q(
mult_x_23_n480) );
DFFRX4TS mult_x_23_R_1001 ( .D(mult_x_23_n518), .CK(clk), .RN(n3972), .Q(
n3665), .QN(n3740) );
DFFRX4TS mult_x_23_R_976 ( .D(n3711), .CK(clk), .RN(n3735), .Q(n3696), .QN(
n729) );
DFFSX4TS mult_x_23_R_955 ( .D(n3716), .CK(clk), .SN(n870), .Q(n3691) );
DFFSX4TS mult_x_23_R_890 ( .D(n3705), .CK(clk), .SN(n3735), .Q(
mult_x_23_n540), .QN(n864) );
DFFSX1TS mult_x_23_R_875 ( .D(n3702), .CK(clk), .SN(n3734), .Q(
mult_x_23_n472) );
DFFSX1TS mult_x_23_R_859 ( .D(n3701), .CK(clk), .SN(n3734), .Q(
mult_x_23_n492) );
DFFRX2TS mult_x_23_R_975 ( .D(mult_x_23_n553), .CK(clk), .RN(n3972), .Q(
n3695) );
DFFRX4TS mult_x_23_R_861 ( .D(n333), .CK(clk), .RN(n3648), .Q(mult_x_23_n517), .QN(n3706) );
DFFRX4TS R_1206 ( .D(mult_x_23_n553), .CK(clk), .RN(n3649), .Q(n3663), .QN(
n1452) );
DFFRX4TS mult_x_23_R_1063 ( .D(mult_x_23_n552), .CK(clk), .RN(n3876), .Q(
n3662), .QN(n1450) );
DFFRX4TS mult_x_23_R_1143 ( .D(mult_x_23_n551), .CK(clk), .RN(n3972), .Q(
n3661) );
DFFHQX4TS mult_x_23_R_592 ( .D(mult_x_23_n100), .CK(clk), .Q(n3690) );
DFFHQX4TS mult_x_55_R_983 ( .D(mult_x_55_n115), .CK(clk), .Q(n3626) );
DFFHQX4TS mult_x_55_R_649 ( .D(mult_x_55_n87), .CK(clk), .Q(n3608) );
DFFHQX1TS mult_x_55_R_646 ( .D(mult_x_55_n188), .CK(clk), .Q(n3606) );
DFFHQX2TS mult_x_55_R_549 ( .D(mult_x_55_n16), .CK(clk), .Q(n3595) );
DFFHQX4TS mult_x_55_R_984 ( .D(mult_x_55_n116), .CK(clk), .Q(n3627) );
DFFHQX4TS mult_x_55_R_480 ( .D(mult_x_55_n69), .CK(clk), .Q(n3591) );
DFFHQX4TS mult_x_55_R_477 ( .D(mult_x_55_n56), .CK(clk), .Q(n3590) );
DFFHQX4TS mult_x_55_R_385 ( .D(mult_x_55_n11), .CK(clk), .Q(n3589) );
DFFHQX2TS mult_x_55_R_383 ( .D(mult_x_55_n13), .CK(clk), .Q(n3588) );
DFFHQX2TS mult_x_55_R_381 ( .D(mult_x_55_n12), .CK(clk), .Q(n3587) );
DFFHQX2TS mult_x_55_R_373 ( .D(mult_x_55_n10), .CK(clk), .Q(n3586) );
DFFHQX2TS mult_x_55_R_346 ( .D(mult_x_55_n9), .CK(clk), .Q(n3585) );
DFFHQX4TS mult_x_55_R_344 ( .D(mult_x_55_n7), .CK(clk), .Q(n3584) );
DFFHQX4TS mult_x_55_R_342 ( .D(mult_x_55_n6), .CK(clk), .Q(n3583) );
DFFHQX4TS mult_x_55_R_340 ( .D(mult_x_55_n8), .CK(clk), .Q(n3582) );
DFFHQX2TS mult_x_55_R_656 ( .D(mult_x_55_n14), .CK(clk), .Q(n3610) );
DFFHQX4TS mult_x_55_R_647 ( .D(n1011), .CK(clk), .Q(n3607) );
DFFQX1TS mult_x_55_R_748 ( .D(n3651), .CK(clk), .Q(n3619) );
DFFQX1TS mult_x_55_R_724 ( .D(mult_x_55_n47), .CK(clk), .Q(n3617) );
DFFHQX4TS mult_x_55_R_486 ( .D(mult_x_55_n32), .CK(clk), .Q(n3593) );
DFFHQX4TS mult_x_55_R_483 ( .D(mult_x_55_n45), .CK(clk), .Q(n3592) );
DFFHQX2TS mult_x_55_R_725 ( .D(mult_x_55_n48), .CK(clk), .Q(n3618) );
DFFQX1TS mult_x_55_R_616 ( .D(mult_x_55_n72), .CK(clk), .Q(n3603) );
DFFSX4TS mult_x_55_R_1167 ( .D(n3629), .CK(clk), .SN(n3978), .Q(
mult_x_55_n446) );
DFFSX1TS mult_x_55_R_298 ( .D(n3578), .CK(clk), .SN(n3880), .Q(
mult_x_55_n504), .QN(n3645) );
DFFSX1TS mult_x_55_R_1076 ( .D(n3634), .CK(clk), .SN(n3735), .Q(
mult_x_55_n506), .QN(n3643) );
DFFSX4TS mult_x_55_R_1163 ( .D(n3642), .CK(clk), .SN(n409), .Q(
mult_x_55_n557), .QN(n3658) );
DFFSX4TS mult_x_55_R_1160 ( .D(n3641), .CK(clk), .SN(n3647), .Q(
mult_x_55_n449) );
DFFRX1TS mult_x_55_R_1161 ( .D(n313), .CK(clk), .RN(n4063), .Q(
mult_x_55_n538) );
DFFSX4TS mult_x_55_R_1157 ( .D(n3639), .CK(clk), .SN(n3979), .Q(
mult_x_55_n445) );
DFFRX4TS mult_x_55_R_1121 ( .D(n320), .CK(clk), .RN(n3649), .Q(
mult_x_55_n531), .QN(n3655) );
DFFSX1TS mult_x_55_R_1122 ( .D(n3638), .CK(clk), .SN(n3648), .Q(
mult_x_55_n479) );
DFFSX4TS mult_x_55_R_1111 ( .D(n3637), .CK(clk), .SN(n908), .Q(
mult_x_55_n583), .QN(n3659) );
DFFRX4TS mult_x_55_R_1108 ( .D(n319), .CK(clk), .RN(n3649), .Q(
mult_x_55_n532), .QN(n3652) );
DFFSX1TS mult_x_55_R_1109 ( .D(n3636), .CK(clk), .SN(n3648), .Q(
mult_x_55_n480) );
DFFRX4TS mult_x_55_R_1073 ( .D(n3633), .CK(clk), .RN(n3647), .Q(n3613), .QN(
n700) );
DFFRX2TS mult_x_55_R_1041 ( .D(n314), .CK(clk), .RN(n4063), .Q(
mult_x_55_n537) );
DFFSX4TS mult_x_55_R_1040 ( .D(n3631), .CK(clk), .SN(n3647), .Q(
mult_x_55_n448), .QN(n3654) );
DFFSX4TS mult_x_55_R_1158 ( .D(n3630), .CK(clk), .SN(n3648), .Q(
mult_x_55_n559), .QN(n849) );
DFFRX4TS mult_x_55_R_1072 ( .D(mult_x_55_n566), .CK(clk), .RN(n4063), .Q(
n3612), .QN(n854) );
DFFSX4TS mult_x_55_R_882 ( .D(n3623), .CK(clk), .SN(n3648), .Q(
mult_x_55_n554), .QN(n715) );
DFFSX4TS mult_x_55_R_881 ( .D(n3622), .CK(clk), .SN(n3647), .Q(n3611) );
DFFSX1TS mult_x_55_R_815 ( .D(n3621), .CK(clk), .SN(n3647), .Q(
mult_x_55_n494) );
DFFSX4TS mult_x_55_R_1166 ( .D(n1174), .CK(clk), .SN(n3648), .Q(
mult_x_55_n562), .QN(n832) );
DFFSX4TS mult_x_55_R_814 ( .D(n3616), .CK(clk), .SN(n3979), .Q(
mult_x_55_n444) );
DFFSX4TS mult_x_55_R_680 ( .D(n3615), .CK(clk), .SN(n872), .Q(mult_x_55_n556), .QN(n862) );
DFFRX4TS R_1217 ( .D(mult_x_55_n567), .CK(clk), .RN(n408), .Q(n3573), .QN(
n3657) );
DFFRX4TS mult_x_55_R_284 ( .D(n322), .CK(clk), .RN(n3647), .Q(mult_x_55_n529), .QN(n3581) );
DFFRX4TS mult_x_55_R_299 ( .D(n321), .CK(clk), .RN(n3649), .Q(mult_x_55_n530), .QN(n3580) );
DFFSX4TS mult_x_55_R_318 ( .D(n3579), .CK(clk), .SN(n3648), .Q(
mult_x_55_n555), .QN(n892) );
DFFSX1TS mult_x_55_R_283 ( .D(n3576), .CK(clk), .SN(n3647), .Q(
mult_x_55_n490) );
DFFRX4TS mult_x_55_R_1101 ( .D(mult_x_55_n568), .CK(clk), .RN(n3648), .Q(
n3574) );
DFFRX4TS mult_x_55_R_1029 ( .D(mult_x_55_n565), .CK(clk), .RN(n3647), .Q(
n3572) );
DFFRX4TS DP_OP_111J16_123_4462_R_832 ( .D(n3845), .CK(clk), .RN(n3876), .Q(
DP_OP_111J16_123_4462_n827) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n4061), .Q(Op_MY[27]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n4061), .Q(Op_MY[25]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n208), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[17]), .QN(n3943) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n4061), .Q(Op_MY[28]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n871), .Q(Op_MY[29]) );
DFFRX4TS mult_x_55_R_1059 ( .D(n3632), .CK(clk), .RN(n3649), .Q(
mult_x_55_n544) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[11]), .QN(n3948) );
DFFSHQX4TS R_755_IP ( .D(n3629), .CK(clk), .SN(n878), .Q(n4036) );
DFFRHQX1TS R_40 ( .D(n313), .CK(clk), .RN(n869), .Q(n3570) );
DFFSHQX8TS R_809_IP ( .D(n3568), .CK(clk), .SN(n869), .Q(n3569) );
DFFSHQX8TS R_90_IP ( .D(n3567), .CK(clk), .SN(n870), .Q(n4034) );
DFFRHQX1TS R_701 ( .D(mult_x_23_n551), .CK(clk), .RN(n870), .Q(Op_MX[19]) );
DFFRX1TS R_847 ( .D(n238), .CK(clk), .RN(n3973), .Q(n3985) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(clk), .RN(n4060),
.QN(n4069) );
DFFRHQX2TS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(clk), .RN(
n4072), .Q(P_Sgf[13]) );
DFFSHQX8TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n3565), .CK(clk), .SN(n869),
.Q(n3901) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(clk), .RN(n878),
.QN(n3902) );
DFFSRHQX8TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(clk),
.SN(1'b1), .RN(n870), .Q(Sgf_normalized_result[10]) );
DFFSHQX8TS R_1090_IP ( .D(n3562), .CK(clk), .SN(n870), .Q(n3563) );
DFFRHQX2TS Sel_C_Q_reg_0_ ( .D(n214), .CK(clk), .RN(n869), .Q(FSM_selector_C) );
DFFSHQX4TS mult_x_55_R_1039_IP ( .D(n1442), .CK(clk), .SN(n878), .Q(n3660)
);
DFFRHQX8TS mult_x_55_R_756_IP ( .D(n425), .CK(clk), .RN(n870), .Q(n3644) );
DFFRHQX4TS DP_OP_111J16_123_4462_R_1045_IP ( .D(n738), .CK(clk), .RN(n870),
.Q(n3895) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n276), .CK(clk), .RN(n878),
.QN(n3897) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(clk), .RN(
n4057), .Q(P_Sgf[10]), .QN(n4068) );
DFFRX1TS R_317 ( .D(n350), .CK(clk), .RN(n4067), .Q(Op_MX[6]) );
DFFSX2TS DP_OP_111J16_123_4462_R_167 ( .D(n3804), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n792) );
DFFRXLTS R_498 ( .D(n245), .CK(clk), .RN(n3794), .Q(n4000) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n3978), .Q(Op_MY[30]), .QN(n3927) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_left_N5), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[5]) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_2_ ( .D(
Sgf_operation_EVEN1_left_N2), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[2]) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(clk),
.RN(n4063), .Q(Sgf_normalized_result[8]), .QN(n3937) );
DFFRX2TS mult_x_55_R_1023 ( .D(n316), .CK(clk), .RN(n3649), .Q(
mult_x_55_n535) );
DFFSHQX8TS DP_OP_111J16_123_4462_R_770 ( .D(n3840), .CK(clk), .SN(n870), .Q(
DP_OP_111J16_123_4462_n682) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n4061), .Q(Op_MY[24]) );
DFFHQX4TS mult_x_23_R_1151 ( .D(mult_x_23_n113), .CK(clk), .Q(n3730) );
DFFHQX4TS DP_OP_111J16_123_4462_R_473 ( .D(DP_OP_111J16_123_4462_n46), .CK(
clk), .Q(n3825) );
DFFHQX4TS mult_x_55_R_550 ( .D(mult_x_55_n130), .CK(clk), .Q(n3596) );
DFFSX4TS mult_x_23_R_1067 ( .D(n3710), .CK(clk), .SN(n3880), .Q(
mult_x_23_n545) );
DFFHQX8TS mult_x_23_R_452 ( .D(mult_x_23_n190), .CK(clk), .Q(n3685) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n212), .CK(clk),
.RN(n871), .Q(Sgf_normalized_result[21]), .QN(n3942) );
DFFHQX4TS mult_x_23_R_1118 ( .D(mult_x_23_n127), .CK(clk), .Q(n3724) );
DFFHQX4TS mult_x_55_R_980 ( .D(mult_x_55_n18), .CK(clk), .Q(n3625) );
DFFRX2TS mult_x_55_R_1159 ( .D(n3640), .CK(clk), .RN(n871), .Q(
mult_x_55_n270), .QN(n3656) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_3_ ( .D(
Sgf_operation_EVEN1_left_N3), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[3]) );
DFFRX4TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(clk), .RN(n4062),
.QN(n3899) );
DFFHQX4TS DP_OP_111J16_123_4462_R_234 ( .D(DP_OP_111J16_123_4462_n15), .CK(
clk), .Q(n3813) );
DFFSX2TS mult_x_55_R_996 ( .D(n3628), .CK(clk), .SN(n3734), .Q(
mult_x_55_n505) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n4061), .Q(Op_MY[23]) );
DFFHQX1TS mult_x_55_R_594 ( .D(mult_x_55_n58), .CK(clk), .Q(n3600) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_8_ ( .D(
Sgf_operation_EVEN1_left_N8), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[8]) );
DFFRX4TS DP_OP_111J16_123_4462_R_1012 ( .D(n3821), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n785) );
DFFHQX4TS DP_OP_111J16_123_4462_R_333 ( .D(DP_OP_111J16_123_4462_n16), .CK(
clk), .Q(n3818) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_left_N9), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[9]) );
DFFHQX4TS DP_OP_111J16_123_4462_R_214 ( .D(DP_OP_111J16_123_4462_n12), .CK(
clk), .Q(n3807) );
DFFHQX4TS mult_x_23_R_1153 ( .D(mult_x_23_n114), .CK(clk), .Q(n3732) );
DFFQX4TS mult_x_55_R_595 ( .D(mult_x_55_n59), .CK(clk), .Q(n3601) );
DFFHQX8TS mult_x_55_R_749 ( .D(n3650), .CK(clk), .Q(n3620) );
DFFHQX8TS Sgf_operation_EVEN1_right_DatO_reg_0_ ( .D(
Sgf_operation_EVEN1_right_N0), .CK(clk), .Q(Sgf_operation_Result[0])
);
DFFRX4TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(clk), .RN(n4062),
.QN(n3898) );
DFFHQX4TS DP_OP_111J16_123_4462_R_633 ( .D(DP_OP_111J16_123_4462_n19), .CK(
clk), .Q(n3832) );
DFFHQX1TS mult_x_55_R_639 ( .D(mult_x_55_n94), .CK(clk), .Q(n3604) );
DFFQX4TS mult_x_55_R_615 ( .D(n1097), .CK(clk), .Q(n3602) );
DFFHQX8TS Sgf_operation_EVEN1_left_DatO_reg_7_ ( .D(
Sgf_operation_EVEN1_left_N7), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[7]) );
DFFRX2TS mult_x_55_R_1102 ( .D(n3635), .CK(clk), .RN(n3647), .Q(
mult_x_55_n543) );
DFFHQX8TS DP_OP_111J16_123_4462_R_236 ( .D(DP_OP_111J16_123_4462_n14), .CK(
clk), .Q(n3814) );
DFFRX4TS DP_OP_111J16_123_4462_R_1004 ( .D(n3858), .CK(clk), .RN(n3880), .Q(
DP_OP_111J16_123_4462_n617) );
DFFSX1TS R_849 ( .D(Sgf_operation_Result[24]), .CK(clk), .SN(n906), .Q(n3984) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(clk), .RN(n4059),
.Q(Add_result[8]), .QN(n3953) );
DFFSX1TS R_846 ( .D(Sgf_operation_Result[23]), .CK(clk), .SN(n447), .Q(n3986) );
DFFSX2TS R_843 ( .D(Sgf_operation_Result[22]), .CK(clk), .SN(n447), .Q(n3988) );
DFFSX2TS R_840 ( .D(Sgf_operation_Result[21]), .CK(clk), .SN(n447), .Q(n3990) );
DFFRX4TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n4062), .Q(zero_flag), .QN(n3952) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n408), .Q(Op_MX[31]) );
DFFRX4TS R_1149 ( .D(mult_x_23_n520), .CK(clk), .RN(n3979), .Q(Op_MY[18]) );
DFFRX4TS R_73 ( .D(n358), .CK(clk), .RN(n4067), .QN(n4042) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(clk), .RN(n4058),
.Q(Add_result[22]), .QN(n3911) );
DFFRX4TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(clk), .RN(n4058),
.Q(Add_result[18]), .QN(n3915) );
DFFRX4TS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(clk), .RN(n878), .Q(final_result_ieee[21]) );
DFFRHQX4TS mult_x_23_R_1068_IP ( .D(n327), .CK(clk), .RN(n869), .Q(n3717) );
DFFSX2TS add_x_19_R_1036 ( .D(add_x_19_n179), .CK(clk), .SN(n875), .Q(n3772)
);
DFFHQX8TS mult_x_55_R_897 ( .D(mult_x_55_n3), .CK(clk), .Q(n3624) );
DFFQX1TS DP_OP_111J16_123_4462_R_588 ( .D(DP_OP_111J16_123_4462_n128), .CK(
clk), .Q(n3826) );
DFFHQX4TS DP_OP_111J16_123_4462_R_599 ( .D(DP_OP_111J16_123_4462_n168), .CK(
clk), .Q(n3827) );
DFFHQX8TS Sgf_operation_EVEN1_middle_DatO_reg_1_ ( .D(
Sgf_operation_EVEN1_middle_N1), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[1]) );
DFFHQX4TS mult_x_55_R_553 ( .D(mult_x_55_n15), .CK(clk), .Q(n3598) );
DFFRHQX2TS mult_x_23_R_891 ( .D(n1475), .CK(clk), .RN(n3735), .Q(n817) );
DFFHQX8TS mult_x_23_R_991 ( .D(mult_x_23_n21), .CK(clk), .Q(n3714) );
DFFRHQX8TS mult_x_23_R_1089 ( .D(mult_x_23_n550), .CK(clk), .RN(n3877), .Q(
n811) );
DFFHQX8TS mult_x_55_R_581 ( .D(mult_x_55_n78), .CK(clk), .Q(n3599) );
DFFHQX8TS Sgf_operation_EVEN1_middle_DatO_reg_9_ ( .D(
Sgf_operation_EVEN1_middle_N9), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[9]) );
DFFHQX4TS Sgf_operation_EVEN1_left_DatO_reg_4_ ( .D(
Sgf_operation_EVEN1_left_N4), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_left[4]) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(clk), .RN(n4059),
.Q(Add_result[13]), .QN(n3920) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(clk), .RN(n4059),
.Q(Add_result[14]), .QN(n3919) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(clk), .RN(n4059),
.Q(Add_result[11]), .QN(n3922) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(clk), .RN(n4059),
.Q(Add_result[9]), .QN(n3924) );
DFFRX4TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n213), .CK(clk),
.RN(n872), .Q(Sgf_normalized_result[22]), .QN(n3933) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n307), .CK(clk),
.RN(n873), .Q(Sgf_normalized_result[23]), .QN(n3949) );
DFFRX2TS R_1096 ( .D(mult_x_23_n516), .CK(clk), .RN(n4061), .Q(Op_MY[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n211), .CK(clk),
.RN(n874), .Q(Sgf_normalized_result[20]), .QN(n3931) );
DFFSHQX8TS DP_OP_111J16_123_4462_R_816 ( .D(n3842), .CK(clk), .SN(n908), .Q(
n695) );
DFFHQX4TS mult_x_55_R_551 ( .D(mult_x_55_n17), .CK(clk), .Q(n3597) );
DFFRHQX8TS DP_OP_111J16_123_4462_R_913 ( .D(n3851), .CK(clk), .RN(n3734),
.Q(n686) );
DFFRXLTS R_708 ( .D(n241), .CK(clk), .RN(n447), .Q(n3994) );
DFFRXLTS R_827 ( .D(n240), .CK(clk), .RN(n447), .Q(n3991) );
DFFRXLTS R_1116 ( .D(DP_OP_111J16_123_4462_n880), .CK(clk), .RN(n4063), .QN(
n3925) );
DFFRXLTS R_652 ( .D(n242), .CK(clk), .RN(n906), .Q(n3999) );
DFFRXLTS R_467 ( .D(n243), .CK(clk), .RN(n875), .Q(n4003) );
DFFRXLTS R_393 ( .D(n247), .CK(clk), .RN(n875), .Q(n4004) );
DFFRXLTS R_367 ( .D(n248), .CK(clk), .RN(n906), .Q(n4006) );
DFFRXLTS R_495 ( .D(n246), .CK(clk), .RN(n906), .Q(n4001) );
DFFRXLTS R_492 ( .D(n244), .CK(clk), .RN(n447), .Q(n4002) );
DFFRXLTS R_1162 ( .D(n313), .CK(clk), .RN(n4063), .Q(n4030) );
DFFRXLTS R_686 ( .D(mult_x_55_n533), .CK(clk), .RN(n413), .Q(n4025) );
DFFHQX4TS mult_x_23_R_1119 ( .D(n1258), .CK(clk), .Q(n3725) );
DFFHQX4TS DP_OP_111J16_123_4462_R_1080 ( .D(DP_OP_111J16_123_4462_n149),
.CK(clk), .Q(n3870) );
DFFHQX4TS mult_x_23_R_1152 ( .D(mult_x_23_n141), .CK(clk), .Q(n3731) );
DFFHQX8TS DP_OP_111J16_123_4462_R_600 ( .D(DP_OP_111J16_123_4462_n21), .CK(
clk), .Q(n3828) );
DFFRHQX2TS DP_OP_111J16_123_4462_R_1014 ( .D(n3862), .CK(clk), .RN(n3878),
.Q(n674) );
DFFHQX8TS Sgf_operation_EVEN1_middle_DatO_reg_5_ ( .D(
Sgf_operation_EVEN1_middle_N5), .CK(clk), .Q(
Sgf_operation_EVEN1_Q_middle[5]) );
DFFSX2TS R_1182 ( .D(add_x_19_n142), .CK(clk), .SN(n421), .Q(n663) );
DFFRX2TS R_1183 ( .D(n3003), .CK(clk), .RN(n420), .Q(n662) );
DFFSX2TS R_1184 ( .D(n1917), .CK(clk), .SN(n421), .Q(n661) );
DFFHQX8TS R_1186 ( .D(n660), .CK(clk), .Q(n1811) );
DFFHQX8TS R_1187 ( .D(n659), .CK(clk), .Q(n1805) );
DFFSX2TS R_1188 ( .D(n3440), .CK(clk), .SN(n415), .Q(n658) );
DFFSX2TS R_1190 ( .D(n843), .CK(clk), .SN(n415), .Q(n656) );
DFFQX1TS R_1193 ( .D(n463), .CK(clk), .Q(n654) );
DFFSX2TS R_1196 ( .D(n653), .CK(clk), .SN(n412), .Q(n1494) );
DFFRX4TS R_1195 ( .D(n3577), .CK(clk), .RN(n3649), .Q(n3575), .QN(n3653) );
DFFQX1TS R_1197 ( .D(n497), .CK(clk), .Q(n652) );
DFFQX1TS R_1198 ( .D(n3088), .CK(clk), .Q(n651) );
DFFRX4TS DP_OP_111J16_123_4462_R_856 ( .D(n3846), .CK(clk), .RN(n3878), .Q(
DP_OP_111J16_123_4462_n720), .QN(n823) );
DFFHQX4TS R_1204 ( .D(DP_OP_111J16_123_4462_n128), .CK(clk), .Q(n647) );
DFFHQX4TS R_1203 ( .D(n3083), .CK(clk), .Q(n648) );
DFFRX2TS R_1207 ( .D(n645), .CK(clk), .RN(n878), .Q(n961) );
DFFSX4TS DP_OP_111J16_123_4462_R_1013 ( .D(n3805), .CK(clk), .SN(n3877), .Q(
DP_OP_111J16_123_4462_n778), .QN(n3884) );
DFFHQX4TS DP_OP_111J16_123_4462_R_602 ( .D(DP_OP_111J16_123_4462_n20), .CK(
clk), .Q(n3829) );
DFFSX2TS R_1214 ( .D(n2233), .CK(clk), .SN(n3977), .Q(n641) );
DFFSX4TS R_1213 ( .D(n2234), .CK(clk), .SN(n3977), .Q(n642) );
DFFSX4TS R_1212 ( .D(n3008), .CK(clk), .SN(n3977), .Q(n643) );
DFFRX2TS R_1215 ( .D(n2987), .CK(clk), .RN(n3790), .Q(n640) );
DFFRX2TS R_1216 ( .D(add_x_19_n124), .CK(clk), .RN(n3790), .Q(n639) );
DFFRX2TS R_1218 ( .D(n638), .CK(clk), .RN(n408), .Q(n1478) );
DFFRX4TS add_x_19_R_1170 ( .D(add_x_19_n142), .CK(clk), .RN(n3792), .Q(n3789) );
DFFSX2TS R_1227 ( .D(n441), .CK(clk), .SN(n906), .Q(n633) );
DFFHQX4TS R_1229 ( .D(mult_x_23_n6), .CK(clk), .Q(n631) );
DFFHQX8TS R_1234 ( .D(DP_OP_111J16_123_4462_n130), .CK(clk), .Q(n626) );
DFFSX2TS R_1235 ( .D(add_x_19_n85), .CK(clk), .SN(n3793), .Q(n625) );
DFFRX2TS R_1236 ( .D(add_x_19_n94), .CK(clk), .RN(n3792), .Q(n624) );
DFFRX2TS R_1237 ( .D(add_x_19_n104), .CK(clk), .RN(n3792), .Q(n623) );
DFFRX2TS R_1238 ( .D(add_x_19_n57), .CK(clk), .RN(n3794), .Q(n622) );
DFFRX2TS R_1239 ( .D(add_x_19_n39), .CK(clk), .RN(n3794), .Q(n621) );
DFFRX2TS R_1240 ( .D(add_x_19_n67), .CK(clk), .RN(n3794), .Q(n620) );
DFFSX2TS R_1241 ( .D(n4055), .CK(clk), .SN(n447), .Q(n619), .QN(n618) );
DFFRX2TS R_1242 ( .D(add_x_19_n47), .CK(clk), .RN(n3794), .Q(n617) );
DFFSX2TS R_1243 ( .D(add_x_19_n161), .CK(clk), .SN(n421), .Q(n616), .QN(n615) );
DFFSX2TS R_1247 ( .D(n3004), .CK(clk), .SN(n876), .Q(n611) );
DFFHQX8TS R_1248 ( .D(DP_OP_111J16_123_4462_n224), .CK(clk), .Q(n610) );
DFFSX2TS R_1249 ( .D(add_x_19_n308), .CK(clk), .SN(n421), .Q(n609) );
DFFHQX4TS R_1250 ( .D(mult_x_23_n78), .CK(clk), .Q(n608) );
DFFSX2TS R_1251 ( .D(add_x_19_n271), .CK(clk), .SN(n3793), .Q(n607), .QN(
n606) );
DFFQX1TS R_1252 ( .D(DP_OP_111J16_123_4462_n36), .CK(clk), .Q(n605) );
DFFRX2TS R_1253 ( .D(add_x_19_n125), .CK(clk), .RN(n420), .Q(n604) );
DFFHQX4TS R_1259 ( .D(DP_OP_111J16_123_4462_n116), .CK(clk), .Q(n598) );
DFFQX4TS R_1256 ( .D(DP_OP_111J16_123_4462_n123), .CK(clk), .Q(n601) );
DFFHQX8TS R_1261 ( .D(DP_OP_111J16_123_4462_n82), .CK(clk), .Q(n596) );
DFFHQX8TS R_1264 ( .D(mult_x_23_n71), .CK(clk), .Q(n593) );
DFFHQX8TS R_1265 ( .D(mult_x_23_n36), .CK(clk), .Q(n592) );
DFFHQX8TS R_1266 ( .D(mult_x_23_n47), .CK(clk), .Q(n591) );
DFFRX2TS R_1267 ( .D(n1859), .CK(clk), .RN(n3792), .Q(n590) );
DFFSX2TS R_1268 ( .D(add_x_19_n152), .CK(clk), .SN(n421), .Q(n589) );
DFFRX2TS R_1269 ( .D(n1467), .CK(clk), .RN(n3794), .Q(n588) );
DFFQX1TS R_1270 ( .D(DP_OP_111J16_123_4462_n58), .CK(clk), .Q(n587) );
DFFQX1TS R_1271 ( .D(DP_OP_111J16_123_4462_n45), .CK(clk), .Q(n586) );
DFFSX2TS R_1273 ( .D(add_x_19_n176), .CK(clk), .SN(n876), .Q(n582), .QN(n581) );
DFFHQX8TS R_1274 ( .D(DP_OP_111J16_123_4462_n161), .CK(clk), .Q(n580) );
DFFRX2TS mult_x_23_R_773 ( .D(n3697), .CK(clk), .RN(n3972), .Q(
mult_x_23_n530) );
DFFHQX8TS mult_x_55_R_650 ( .D(mult_x_55_n88), .CK(clk), .Q(n3609) );
DFFHQX2TS mult_x_23_R_397 ( .D(mult_x_23_n97), .CK(clk), .Q(n3680) );
DFFHQX4TS R_1254 ( .D(n833), .CK(clk), .Q(n603) );
DFFHQX4TS mult_x_55_R_548 ( .D(mult_x_55_n121), .CK(clk), .Q(n3594) );
DFFRX4TS DP_OP_111J16_123_4462_R_911 ( .D(n3850), .CK(clk), .RN(n4058), .Q(
DP_OP_111J16_123_4462_n620) );
DFFRX2TS DP_OP_111J16_123_4462_R_1031 ( .D(n3867), .CK(clk), .RN(n3880), .Q(
DP_OP_111J16_123_4462_n619) );
DFFHQX8TS DP_OP_111J16_123_4462_R_351 ( .D(DP_OP_111J16_123_4462_n220), .CK(
clk), .Q(n3819) );
DFFHQX4TS DP_OP_111J16_123_4462_R_220 ( .D(DP_OP_111J16_123_4462_n11), .CK(
clk), .Q(n3809) );
DFFRXLTS R_806 ( .D(n235), .CK(clk), .RN(n3973), .Q(n3992) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n210), .CK(clk),
.RN(n871), .Q(Sgf_normalized_result[19]), .QN(n3946) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n206), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[15]), .QN(n3947) );
DFFSX4TS R_1225 ( .D(n441), .CK(clk), .SN(n3974), .Q(n636) );
DFFSX4TS R_1226 ( .D(n441), .CK(clk), .SN(n876), .Q(n635), .QN(n634) );
DFFRX4TS R_297 ( .D(n321), .CK(clk), .RN(n4058), .Q(Op_MY[9]) );
DFFRX4TS R_995 ( .D(n320), .CK(clk), .RN(n4058), .Q(Op_MY[8]) );
DFFRX1TS R_1189 ( .D(n287), .CK(clk), .RN(n4058), .Q(n657) );
DFFSHQX8TS DP_OP_111J16_123_4462_R_912 ( .D(n3798), .CK(clk), .SN(n3880),
.Q(n403) );
DFFHQX8TS R_1263 ( .D(n401), .CK(clk), .Q(n594) );
DFFHQX4TS R_1272 ( .D(mult_x_23_n87), .CK(clk), .Q(n585) );
DFFRHQX8TS R_45 ( .D(n331), .CK(clk), .RN(n413), .Q(n571) );
DFFSX4TS R_1231 ( .D(add_x_19_n197), .CK(clk), .SN(n876), .Q(n630), .QN(n629) );
DFFRX4TS add_x_19_R_1169 ( .D(n637), .CK(clk), .RN(n3792), .Q(n3788) );
DFFHQX4TS R_1228 ( .D(mult_x_55_n4), .CK(clk), .Q(n632) );
DFFHQX4TS Sgf_operation_EVEN1_right_DatO_reg_6_ ( .D(
Sgf_operation_EVEN1_right_N6), .CK(clk), .Q(Sgf_operation_Result[6])
);
DFFHQX4TS mult_x_23_R_1154 ( .D(mult_x_23_n101), .CK(clk), .Q(n3733) );
DFFHQX4TS R_1255 ( .D(mult_x_23_n99), .CK(clk), .Q(n602) );
DFFHQX4TS R_1246 ( .D(mult_x_23_n94), .CK(clk), .Q(n612) );
DFFHQX2TS mult_x_23_R_488 ( .D(mult_x_23_n100), .CK(clk), .Q(n3688) );
DFFHQX1TS mult_x_23_R_433 ( .D(mult_x_23_n20), .CK(clk), .Q(n3683) );
DFFHQX2TS R_1205 ( .D(n3082), .CK(clk), .Q(n646) );
DFFRHQX4TS mult_x_55_R_929 ( .D(mult_x_55_n570), .CK(clk), .RN(n908), .Q(
n671) );
DFFHQX1TS mult_x_23_R_470 ( .D(mult_x_23_n17), .CK(clk), .Q(n3687) );
DFFHQX2TS mult_x_23_R_441 ( .D(mult_x_23_n100), .CK(clk), .Q(n3684) );
DFFHQX1TS mult_x_55_R_640 ( .D(mult_x_55_n95), .CK(clk), .Q(n3605) );
DFFHQX2TS R_1262 ( .D(DP_OP_111J16_123_4462_n89), .CK(clk), .Q(n595) );
DFFHQX4TS R_1257 ( .D(DP_OP_111J16_123_4462_n97), .CK(clk), .Q(n600) );
DFFHQX1TS mult_x_23_R_114 ( .D(mult_x_23_n13), .CK(clk), .Q(n3674) );
DFFHQX4TS R_1232 ( .D(DP_OP_111J16_123_4462_n96), .CK(clk), .Q(n628) );
DFFRHQX2TS DP_OP_111J16_123_4462_R_712 ( .D(n3802), .CK(clk), .RN(n3877),
.Q(n816) );
DFFHQX4TS R_1245 ( .D(n3736), .CK(clk), .Q(n613) );
DFFQX2TS R_1258 ( .D(DP_OP_111J16_123_4462_n103), .CK(clk), .Q(n599) );
DFFRHQX4TS DP_OP_111J16_123_4462_R_1017 ( .D(n3864), .CK(clk), .RN(n3878),
.Q(n836) );
DFFRX4TS mult_x_55_R_676 ( .D(n3614), .CK(clk), .RN(n872), .QN(n390) );
DFFQX1TS mult_x_23_R_54 ( .D(mult_x_23_n10), .CK(clk), .Q(n3671) );
DFFHQX4TS R_1244 ( .D(DP_OP_111J16_123_4462_n71), .CK(clk), .Q(n614) );
DFFRX2TS DP_OP_111J16_123_4462_R_1042 ( .D(n3830), .CK(clk), .RN(n4061), .Q(
DP_OP_111J16_123_4462_n752) );
DFFRX2TS mult_x_23_R_1115 ( .D(DP_OP_111J16_123_4462_n880), .CK(clk), .RN(
n3972), .Q(mult_x_23_n521) );
DFFRHQX4TS R_100 ( .D(n328), .CK(clk), .RN(n869), .Q(Op_MY[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n4067), .Q(Op_MY[26]), .QN(n721) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n3878), .Q(Op_MX[27]), .QN(n3907) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n873), .Q(Op_MX[23]), .QN(n3982) );
DFFRX2TS DP_OP_111J16_123_4462_R_901 ( .D(n323), .CK(clk), .RN(n3878), .Q(
n430) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n3972), .Q(Op_MX[28]), .QN(n3904) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n3972), .Q(Op_MX[29]), .QN(n3995) );
DFFRX2TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n275), .CK(clk), .RN(n874),
.Q(n743), .QN(n4070) );
DFFRX1TS mult_x_55_R_1168 ( .D(n3646), .CK(clk), .RN(n3648), .QN(n697) );
DFFQX1TS DP_OP_111J16_123_4462_R_222 ( .D(DP_OP_111J16_123_4462_n8), .CK(clk), .Q(n3810) );
DFFQX1TS DP_OP_111J16_123_4462_R_210 ( .D(DP_OP_111J16_123_4462_n7), .CK(clk), .Q(n3806) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(clk),
.RN(n4067), .Q(Sgf_normalized_result[4]), .QN(n3950) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n3972), .Q(Op_MX[30]), .QN(n4044) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(clk),
.RN(n4066), .Q(Sgf_normalized_result[5]), .QN(n3926) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(clk),
.RN(n4073), .Q(Sgf_normalized_result[1]), .QN(n436) );
DFFRX2TS mult_x_23_R_877 ( .D(n327), .CK(clk), .RN(n3734), .Q(mult_x_23_n523) );
DFFHQX2TS DP_OP_111J16_123_4462_R_659 ( .D(DP_OP_111J16_123_4462_n39), .CK(
clk), .Q(n3835) );
DFFHQX1TS DP_OP_111J16_123_4462_R_657 ( .D(DP_OP_111J16_123_4462_n48), .CK(
clk), .Q(n3833) );
DFFRX2TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(clk), .RN(
n4060), .QN(n1443) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(clk),
.RN(n4064), .Q(Sgf_normalized_result[18]), .QN(n3934) );
DFFRX1TS R_930 ( .D(n346), .CK(clk), .RN(n908), .Q(Op_MX[2]) );
DFFSX1TS add_x_19_R_417 ( .D(n1856), .CK(clk), .SN(n3790), .Q(n3750) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n281), .CK(clk), .RN(n4062),
.Q(exp_oper_result_8_), .QN(n3910) );
DFFRXLTS R_294 ( .D(mult_x_55_n569), .CK(clk), .RN(n3978), .Q(n4048), .QN(
n3998) );
DFFQX1TS DP_OP_111J16_123_4462_R_226 ( .D(DP_OP_111J16_123_4462_n6), .CK(clk), .Q(n3812) );
DFFSX1TS add_x_19_R_411 ( .D(n1900), .CK(clk), .SN(n4072), .Q(n3748) );
DFFSX1TS add_x_19_R_763 ( .D(add_x_19_n201), .CK(clk), .SN(n4057), .QN(n574)
);
DFFRX2TS R_246 ( .D(n260), .CK(clk), .RN(n4072), .Q(n4021) );
DFFSX1TS R_889_IP ( .D(n3566), .CK(clk), .SN(n869), .Q(n4041), .QN(n4050) );
DFFRXLTS add_x_19_R_604 ( .D(add_x_19_n16), .CK(clk), .RN(n4072), .Q(n3755)
);
DFFRXLTS R_689 ( .D(n366), .CK(clk), .RN(n3978), .Q(n4053), .QN(n4009) );
DFFSX1TS add_x_19_R_401 ( .D(add_x_19_n51), .CK(clk), .SN(n4072), .Q(n3744)
);
DFFRHQX2TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(clk), .RN(n870),
.Q(Add_result[4]) );
DFFSRHQX2TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(clk), .SN(1'b1),
.RN(n869), .Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(clk), .RN(n4059),
.Q(Add_result[15]), .QN(n3918) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(clk), .RN(n4059),
.Q(Add_result[16]), .QN(n3917) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(clk), .RN(n4060),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(clk), .RN(n4059),
.Q(Add_result[17]), .QN(n3916) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(clk), .RN(n415),
.Q(Add_result[20]), .QN(n3913) );
DFFRX2TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(clk), .RN(n4058),
.Q(Add_result[21]), .QN(n3912) );
INVX2TS U405 ( .A(mult_x_23_n7), .Y(mult_x_23_n71) );
INVX2TS U406 ( .A(n419), .Y(n421) );
CLKINVX1TS U407 ( .A(n410), .Y(n414) );
CLKINVX1TS U408 ( .A(n410), .Y(n412) );
CLKINVX2TS U409 ( .A(n407), .Y(n408) );
CLKINVX2TS U410 ( .A(n407), .Y(n409) );
NAND2X1TS U411 ( .A(n2783), .B(mult_x_55_n72), .Y(mult_x_55_n10) );
BUFX3TS U412 ( .A(n3735), .Y(n4058) );
CLKINVX2TS U413 ( .A(n419), .Y(n420) );
NAND2X6TS U414 ( .A(add_x_19_n310), .B(add_x_19_n152), .Y(add_x_19_n10) );
CLKINVX1TS U415 ( .A(n410), .Y(n413) );
AOI2BB2X1TS U416 ( .B0(n3379), .B1(n243), .A0N(n900), .A1N(n3249), .Y(n3251)
);
INVX4TS U417 ( .A(n3005), .Y(n1393) );
INVX6TS U418 ( .A(n498), .Y(DP_OP_111J16_123_4462_n220) );
OR2X6TS U419 ( .A(mult_x_55_n58), .B(n2807), .Y(n3651) );
NOR2X4TS U420 ( .A(n2905), .B(n2904), .Y(mult_x_23_n99) );
INVX4TS U421 ( .A(mult_x_23_n94), .Y(n2442) );
INVX4TS U422 ( .A(n3012), .Y(n3004) );
NAND2X1TS U423 ( .A(n2847), .B(n2846), .Y(n2848) );
NAND2X6TS U424 ( .A(n1695), .B(n1694), .Y(n2895) );
INVX2TS U425 ( .A(n3525), .Y(n3526) );
INVX6TS U426 ( .A(add_x_19_n201), .Y(n1395) );
NAND2X1TS U427 ( .A(n2784), .B(n2821), .Y(n2785) );
NAND2X1TS U428 ( .A(n3028), .B(n3027), .Y(n3029) );
BUFX4TS U429 ( .A(n3525), .Y(n3523) );
NOR2X1TS U430 ( .A(n4067), .B(beg_FSM), .Y(n732) );
AOI2BB2X1TS U431 ( .B0(n3379), .B1(n239), .A0N(n900), .A1N(n4069), .Y(n3351)
);
NAND2X1TS U432 ( .A(n4055), .B(P_Sgf[19]), .Y(n554) );
NAND2XLTS U433 ( .A(n842), .B(Add_result[23]), .Y(n471) );
CLKINVX2TS U434 ( .A(n3071), .Y(n3081) );
INVX1TS U435 ( .A(n3049), .Y(n3014) );
BUFX3TS U436 ( .A(n3978), .Y(n3735) );
NAND2XLTS U437 ( .A(n3559), .B(n743), .Y(n1359) );
NAND2XLTS U438 ( .A(n842), .B(Add_result[6]), .Y(n1220) );
INVX1TS U439 ( .A(n2099), .Y(n3100) );
NAND2X2TS U440 ( .A(n2991), .B(n1101), .Y(n3006) );
NAND2XLTS U441 ( .A(n443), .B(Add_result[20]), .Y(n922) );
NAND2XLTS U442 ( .A(n443), .B(Add_result[21]), .Y(n1014) );
NAND2X1TS U443 ( .A(n3106), .B(n1457), .Y(n3107) );
NAND2X2TS U444 ( .A(n2936), .B(n919), .Y(n2937) );
NAND2X1TS U445 ( .A(n3852), .B(n1468), .Y(n1469) );
NAND2X2TS U446 ( .A(n2909), .B(n2908), .Y(n2910) );
NAND2X2TS U447 ( .A(n2998), .B(n512), .Y(n3009) );
NAND2X6TS U448 ( .A(n547), .B(n2819), .Y(n1380) );
CLKINVX2TS U449 ( .A(n1317), .Y(n2919) );
INVX2TS U450 ( .A(n3980), .Y(n410) );
CLKINVX1TS U451 ( .A(n2778), .Y(n2734) );
INVX2TS U452 ( .A(n907), .Y(n407) );
INVX2TS U453 ( .A(n3791), .Y(n419) );
NAND2X1TS U454 ( .A(n3052), .B(n3050), .Y(n3019) );
BUFX8TS U455 ( .A(n3086), .Y(n1073) );
NAND2X2TS U456 ( .A(n3335), .B(n254), .Y(n3237) );
INVX2TS U457 ( .A(n3262), .Y(n3384) );
NAND2X4TS U458 ( .A(n1755), .B(n1754), .Y(n2903) );
INVX4TS U459 ( .A(n964), .Y(n3094) );
CLKMX2X2TS U460 ( .A(n2582), .B(n3991), .S0(n633), .Y(n240) );
CLKINVX6TS U461 ( .A(n3257), .Y(n2588) );
NOR2X6TS U462 ( .A(n1625), .B(n1624), .Y(n2912) );
NAND2X6TS U463 ( .A(n2096), .B(n2095), .Y(n1110) );
NOR2X6TS U464 ( .A(n2370), .B(n2369), .Y(n498) );
NAND2X4TS U465 ( .A(n985), .B(n548), .Y(n547) );
INVX4TS U466 ( .A(n2907), .Y(n2909) );
CLKINVX6TS U467 ( .A(n3257), .Y(n3392) );
INVX2TS U468 ( .A(n950), .Y(n3098) );
NAND2X4TS U469 ( .A(n2229), .B(n515), .Y(n3044) );
NAND2X1TS U470 ( .A(n354), .B(n366), .Y(n3167) );
NAND2X1TS U471 ( .A(n3425), .B(n3448), .Y(n3426) );
OAI2BB1X2TS U472 ( .A0N(mult_x_55_n570), .A1N(n1203), .B0(n3123), .Y(n3157)
);
INVX4TS U473 ( .A(n841), .Y(n443) );
BUFX3TS U474 ( .A(n3353), .Y(n3361) );
CLKBUFX2TS U475 ( .A(n3975), .Y(n3791) );
CLKBUFX2TS U476 ( .A(n908), .Y(n907) );
CLKBUFX2TS U477 ( .A(n3649), .Y(n3980) );
INVX8TS U478 ( .A(n2825), .Y(n2835) );
MX2X4TS U479 ( .A(n3364), .B(n4011), .S0(n635), .Y(n251) );
XOR2X2TS U480 ( .A(n350), .B(n4039), .Y(n3183) );
OR2X1TS U481 ( .A(n3177), .B(n1071), .Y(n741) );
AOI22X2TS U482 ( .A0(n1350), .A1(Add_result[16]), .B0(n3388), .B1(
Sgf_normalized_result[15]), .Y(n1352) );
NAND2X2TS U483 ( .A(n2794), .B(n2793), .Y(n2802) );
AO21XLTS U484 ( .A0(n853), .A1(n2842), .B0(n850), .Y(n2843) );
INVX2TS U485 ( .A(n2781), .Y(n773) );
NOR2X1TS U486 ( .A(n850), .B(n1451), .Y(n2844) );
AND4X1TS U487 ( .A(n455), .B(n3538), .C(n4033), .D(n4034), .Y(n3543) );
INVX2TS U488 ( .A(n2138), .Y(n1030) );
INVX2TS U489 ( .A(n3403), .Y(n3483) );
BUFX4TS U490 ( .A(n3390), .Y(n902) );
AO21X1TS U491 ( .A0(n861), .A1(n895), .B0(n3891), .Y(n3176) );
OR2X4TS U492 ( .A(n2794), .B(n2793), .Y(n2804) );
INVX2TS U493 ( .A(n2136), .Y(n1301) );
NAND2X6TS U494 ( .A(n1007), .B(n1740), .Y(n2913) );
NAND2X1TS U495 ( .A(n346), .B(n358), .Y(n3123) );
NAND2X2TS U496 ( .A(n1768), .B(n1769), .Y(n2772) );
NAND2X4TS U497 ( .A(n2364), .B(n2365), .Y(n2776) );
BUFX3TS U498 ( .A(n3309), .Y(n3388) );
CLKINVX1TS U499 ( .A(n829), .Y(n1193) );
NOR2X1TS U500 ( .A(n977), .B(n2585), .Y(n976) );
NAND2X2TS U501 ( .A(n2227), .B(Sgf_operation_EVEN1_Q_left[0]), .Y(n3050) );
INVX2TS U502 ( .A(n2818), .Y(n548) );
CLKINVX2TS U503 ( .A(n2916), .Y(n1315) );
NAND2X2TS U504 ( .A(n328), .B(n316), .Y(n3800) );
CLKBUFX2TS U505 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n1101) );
INVX2TS U506 ( .A(n3073), .Y(n1151) );
NAND2X4TS U507 ( .A(n561), .B(n562), .Y(n3465) );
NAND2X2TS U508 ( .A(n4055), .B(n3557), .Y(n1473) );
CLKBUFX2TS U509 ( .A(Sgf_operation_EVEN1_Q_left[9]), .Y(n807) );
NOR2X2TS U510 ( .A(n3142), .B(n3125), .Y(n1338) );
NOR4X1TS U511 ( .A(Op_MX[8]), .B(Op_MX[2]), .C(Op_MX[6]), .D(Op_MX[4]), .Y(
n3545) );
INVX6TS U512 ( .A(n3389), .Y(n3261) );
BUFX4TS U513 ( .A(n1741), .Y(n1007) );
CLKINVX6TS U514 ( .A(mult_x_55_n71), .Y(n2783) );
NAND2X4TS U515 ( .A(n2526), .B(n2525), .Y(n2916) );
NAND2X1TS U516 ( .A(Sgf_normalized_result[20]), .B(Sgf_normalized_result[21]), .Y(n3475) );
NAND2X1TS U517 ( .A(n2325), .B(n2348), .Y(n2331) );
NAND2X6TS U518 ( .A(n2756), .B(n2755), .Y(DP_OP_111J16_123_4462_n72) );
INVX2TS U519 ( .A(n3569), .Y(n3539) );
NOR2X6TS U520 ( .A(n2758), .B(n2759), .Y(n2780) );
INVX6TS U521 ( .A(n1213), .Y(n950) );
NAND2BX1TS U522 ( .AN(n3516), .B(round_mode[1]), .Y(n1288) );
NAND2X2TS U523 ( .A(n2758), .B(n2759), .Y(n2781) );
CLKMX2X4TS U524 ( .A(Data_MY[19]), .B(n571), .S0(n3129), .Y(n331) );
NOR2X4TS U525 ( .A(n314), .B(n326), .Y(n3142) );
INVX2TS U526 ( .A(n1100), .Y(n3177) );
INVX4TS U527 ( .A(n2858), .Y(n4039) );
NOR2X4TS U528 ( .A(n2526), .B(n2525), .Y(n2915) );
CLKBUFX2TS U529 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n515) );
NAND2XLTS U530 ( .A(n661), .B(n604), .Y(add_x_19_n7) );
AO21X2TS U531 ( .A0(n576), .A1(n577), .B0(n578), .Y(n3253) );
NAND2X1TS U532 ( .A(n348), .B(n2865), .Y(n3150) );
NOR2X4TS U533 ( .A(n2098), .B(n3099), .Y(n1300) );
INVX1TS U534 ( .A(n3309), .Y(n972) );
NOR2X6TS U535 ( .A(n3031), .B(n3032), .Y(n3036) );
NOR2X6TS U536 ( .A(n3024), .B(n3026), .Y(n3007) );
CLKAND2X2TS U537 ( .A(n2996), .B(n2995), .Y(n664) );
NAND2X4TS U538 ( .A(n324), .B(n312), .Y(n3796) );
NOR2X4TS U539 ( .A(n701), .B(n1224), .Y(n1433) );
INVX2TS U540 ( .A(Data_MY[11]), .Y(n784) );
NOR2X4TS U541 ( .A(n2818), .B(n2811), .Y(n763) );
NOR2X6TS U542 ( .A(n2811), .B(n2819), .Y(n761) );
ADDFHX2TS U543 ( .A(n2433), .B(n2432), .CI(n2431), .CO(n2437), .S(n2709) );
NAND2X2TS U544 ( .A(n3512), .B(n2775), .Y(n3557) );
NAND2X2TS U545 ( .A(n3101), .B(n3102), .Y(n951) );
CLKBUFX2TS U546 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n1165) );
AND2X4TS U547 ( .A(n1918), .B(n701), .Y(n535) );
NAND2X4TS U548 ( .A(n981), .B(n3102), .Y(n948) );
INVX3TS U549 ( .A(n2812), .Y(n760) );
NOR3X1TS U550 ( .A(n236), .B(n237), .C(P_Sgf[0]), .Y(n3219) );
INVX3TS U551 ( .A(n3052), .Y(n3018) );
NAND2X4TS U552 ( .A(n1918), .B(n2366), .Y(n499) );
NAND2X1TS U553 ( .A(n2982), .B(n2981), .Y(n2983) );
NAND2X4TS U554 ( .A(n565), .B(n2163), .Y(n3027) );
NAND2X1TS U555 ( .A(n712), .B(n2977), .Y(n2978) );
BUFX2TS U556 ( .A(n2541), .Y(n838) );
AND2X6TS U557 ( .A(n1144), .B(n1885), .Y(n579) );
NAND2X4TS U558 ( .A(n2867), .B(n2866), .Y(n2868) );
AND2X6TS U559 ( .A(n1223), .B(n506), .Y(n428) );
NAND2X4TS U560 ( .A(n2701), .B(n2700), .Y(n2819) );
BUFX3TS U561 ( .A(n2549), .Y(n667) );
INVX2TS U562 ( .A(n2994), .Y(n2996) );
INVX2TS U563 ( .A(n2350), .Y(n2325) );
NAND2X6TS U564 ( .A(n2022), .B(n2021), .Y(n3102) );
NOR2X6TS U565 ( .A(n2022), .B(n2021), .Y(n3101) );
NAND2X6TS U566 ( .A(n1757), .B(n1756), .Y(mult_x_55_n72) );
INVX2TS U567 ( .A(Data_MX[5]), .Y(n1175) );
INVX12TS U568 ( .A(n2801), .Y(n1011) );
NOR2X4TS U569 ( .A(n3930), .B(n3193), .Y(n3512) );
BUFX3TS U570 ( .A(n2345), .Y(n1096) );
NOR2X6TS U571 ( .A(n565), .B(n2163), .Y(n3026) );
INVX6TS U572 ( .A(n1417), .Y(n503) );
CLKAND2X2TS U573 ( .A(n3314), .B(n882), .Y(n456) );
CLKINVX1TS U574 ( .A(n2225), .Y(n2971) );
AO21XLTS U575 ( .A0(n1601), .A1(n729), .B0(n459), .Y(n2374) );
NAND2X1TS U576 ( .A(n735), .B(n1063), .Y(n1062) );
NOR2X2TS U577 ( .A(n3900), .B(n3910), .Y(n3454) );
NAND2X2TS U578 ( .A(n2435), .B(n2436), .Y(n1249) );
INVX2TS U579 ( .A(round_mode[0]), .Y(n1287) );
ADDFHX2TS U580 ( .A(n2548), .B(n2547), .CI(n1463), .CO(n2597), .S(n2553) );
NAND2X4TS U581 ( .A(n1438), .B(n815), .Y(n1083) );
ADDFHX2TS U582 ( .A(n1592), .B(n1590), .CI(n1591), .CO(n1599), .S(n1639) );
ADDFHX2TS U583 ( .A(n1612), .B(n1611), .CI(n1610), .CO(n2439), .S(n2431) );
NAND2X1TS U584 ( .A(n1455), .B(n2225), .Y(n2226) );
NOR2X2TS U585 ( .A(n2318), .B(n2333), .Y(n2323) );
CLKINVX1TS U586 ( .A(n3340), .Y(n3299) );
NAND2X2TS U587 ( .A(n1311), .B(n1304), .Y(n1303) );
ADDFHX2TS U588 ( .A(n1617), .B(n1616), .CI(n1615), .CO(n2380), .S(n1623) );
NOR2X1TS U589 ( .A(n3340), .B(n588), .Y(n3313) );
NOR2X1TS U590 ( .A(n3340), .B(n622), .Y(n3319) );
NOR2X2TS U591 ( .A(n850), .B(n3580), .Y(n2791) );
INVX2TS U592 ( .A(n1308), .Y(n1304) );
NAND2X4TS U593 ( .A(n999), .B(n998), .Y(n1641) );
NAND2X2TS U594 ( .A(n2505), .B(n2504), .Y(n2922) );
INVX2TS U595 ( .A(n2353), .Y(n2327) );
OAI22X2TS U596 ( .A0(n853), .A1(n1773), .B0(n2842), .B1(n2789), .Y(n2790) );
OAI22X2TS U597 ( .A0(n1252), .A1(n1606), .B0(n865), .B1(n1603), .Y(n1612) );
AND2X6TS U598 ( .A(n2823), .B(n2821), .Y(n724) );
NAND2X4TS U599 ( .A(n2214), .B(n2213), .Y(n3448) );
INVX8TS U600 ( .A(n882), .Y(n444) );
INVX6TS U601 ( .A(n2368), .Y(n506) );
NOR2X2TS U602 ( .A(n1462), .B(n1447), .Y(n3278) );
OAI2BB1X2TS U603 ( .A0N(n736), .A1N(n1358), .B0(n3202), .Y(n3468) );
INVX8TS U604 ( .A(n1223), .Y(n2367) );
CLKINVX2TS U605 ( .A(n3456), .Y(n442) );
INVX2TS U606 ( .A(FSM_selector_C), .Y(n3226) );
INVX2TS U607 ( .A(Data_MY[0]), .Y(n758) );
NAND2X6TS U608 ( .A(n1137), .B(n2854), .Y(n1136) );
NAND2X2TS U609 ( .A(n986), .B(n2081), .Y(n923) );
NOR2BX1TS U610 ( .AN(Sgf_normalized_result[18]), .B(n3946), .Y(n1332) );
NOR2X4TS U611 ( .A(n1440), .B(n1843), .Y(n2223) );
NOR2X4TS U612 ( .A(n3339), .B(n620), .Y(n3322) );
NAND2X4TS U613 ( .A(n746), .B(n894), .Y(n757) );
CLKBUFX2TS U614 ( .A(n2955), .Y(n1074) );
XNOR2X1TS U615 ( .A(n2237), .B(n2254), .Y(n1472) );
NAND2X2TS U616 ( .A(n815), .B(n826), .Y(n1404) );
NAND2X2TS U617 ( .A(n2551), .B(n2550), .Y(n912) );
ADDFHX2TS U618 ( .A(n2430), .B(n2429), .CI(n2428), .CO(n2710), .S(n2434) );
OAI22X2TS U619 ( .A0(n1647), .A1(n858), .B0(n1633), .B1(n890), .Y(n1648) );
OAI21X2TS U620 ( .A0(n2350), .A1(n2349), .B0(n2348), .Y(n2351) );
NAND2X4TS U621 ( .A(n2678), .B(n2677), .Y(n2784) );
INVX6TS U622 ( .A(n2345), .Y(n2324) );
AND2X6TS U623 ( .A(n1428), .B(n2982), .Y(n717) );
OAI21X2TS U624 ( .A0(n943), .A1(n2389), .B0(n2388), .Y(n944) );
INVX4TS U625 ( .A(n1080), .Y(n2551) );
OAI2BB1X2TS U626 ( .A0N(n990), .A1N(n989), .B0(n2053), .Y(n988) );
CMPR32X2TS U627 ( .A(n2423), .B(n2422), .C(n2421), .CO(n2751), .S(n2417) );
OAI21X2TS U628 ( .A0(n2509), .A1(n2508), .B0(n1240), .Y(n1238) );
AO21X2TS U629 ( .A0(n2483), .A1(n2481), .B0(mult_x_23_n546), .Y(n2871) );
XNOR2X2TS U630 ( .A(n1570), .B(n686), .Y(n1579) );
OAI21X2TS U631 ( .A0(n2152), .A1(n2151), .B0(n692), .Y(n2157) );
OAI2BB1X2TS U632 ( .A0N(n1487), .A1N(n1023), .B0(n1021), .Y(n1760) );
INVX3TS U633 ( .A(n1414), .Y(n1412) );
XNOR2X2TS U634 ( .A(n1099), .B(n1077), .Y(n2122) );
XNOR2X2TS U635 ( .A(n2103), .B(n886), .Y(n2117) );
NAND2X4TS U636 ( .A(n1313), .B(n1312), .Y(n1311) );
NAND2X1TS U637 ( .A(n720), .B(n2158), .Y(n2159) );
NOR2X4TS U638 ( .A(n2211), .B(n2210), .Y(n3403) );
NAND2X4TS U639 ( .A(n1181), .B(n2859), .Y(n1182) );
INVX4TS U640 ( .A(n2939), .Y(n1137) );
INVX2TS U641 ( .A(n2012), .Y(n1173) );
NOR2X6TS U642 ( .A(n2212), .B(n1148), .Y(n3484) );
INVX2TS U643 ( .A(Data_MX[4]), .Y(n1177) );
OAI21X2TS U644 ( .A0(n2479), .A1(n1158), .B0(n960), .Y(n1675) );
NAND2XLTS U645 ( .A(n2146), .B(n2145), .Y(n2147) );
AOI21X2TS U646 ( .A0(n882), .A1(n2564), .B0(n2563), .Y(n979) );
NAND2X1TS U647 ( .A(n2336), .B(n2335), .Y(n2337) );
XNOR2X2TS U648 ( .A(n811), .B(Op_MY[16]), .Y(n1668) );
NOR2X6TS U649 ( .A(n567), .B(n2281), .Y(n2347) );
XNOR2X2TS U650 ( .A(n2409), .B(DP_OP_111J16_123_4462_n698), .Y(n1653) );
NAND2X2TS U651 ( .A(n2277), .B(n2349), .Y(n2282) );
NOR2X6TS U652 ( .A(n3339), .B(n588), .Y(n3314) );
CLKBUFX3TS U653 ( .A(n2071), .Y(n397) );
ADDFHX2TS U654 ( .A(n1985), .B(n1984), .CI(n1983), .CO(n2395), .S(n1989) );
OAI22X2TS U655 ( .A0(n2109), .A1(n856), .B0(n2110), .B1(n1302), .Y(n2120) );
NAND2BX2TS U656 ( .AN(n1368), .B(n2295), .Y(n2301) );
NAND2X2TS U657 ( .A(n2250), .B(n2280), .Y(n2266) );
BUFX3TS U658 ( .A(n2222), .Y(n815) );
NAND2X2TS U659 ( .A(n746), .B(n4049), .Y(n1178) );
NAND2X2TS U660 ( .A(n2336), .B(n2332), .Y(n2348) );
ADDFHX2TS U661 ( .A(n1767), .B(n1766), .CI(n1765), .CO(n1770), .S(n1758) );
NAND2XLTS U662 ( .A(n2142), .B(n2141), .Y(n2143) );
INVX6TS U663 ( .A(n2032), .Y(n2046) );
NAND2X1TS U664 ( .A(n2054), .B(n991), .Y(n987) );
NOR2X2TS U665 ( .A(n3214), .B(n3213), .Y(n3215) );
NAND2X1TS U666 ( .A(n1645), .B(n1002), .Y(n998) );
OAI22X2TS U667 ( .A0(n1581), .A1(n858), .B0(n1986), .B1(n890), .Y(n1990) );
NAND2X1TS U668 ( .A(n1158), .B(n3692), .Y(n960) );
BUFX6TS U669 ( .A(n1971), .Y(n402) );
CLKBUFX2TS U670 ( .A(n1056), .Y(n834) );
INVX2TS U671 ( .A(n1570), .Y(n2754) );
NAND2BX2TS U672 ( .AN(n2083), .B(n740), .Y(n1312) );
NOR2X4TS U673 ( .A(n2247), .B(n2263), .Y(n2270) );
CLKAND2X2TS U674 ( .A(mult_x_23_a_0_), .B(n2463), .Y(n1690) );
INVX2TS U675 ( .A(n828), .Y(n2145) );
INVX2TS U676 ( .A(n2332), .Y(n2335) );
AO21X1TS U677 ( .A0(n770), .A1(n893), .B0(n518), .Y(n1766) );
CLKINVX6TS U678 ( .A(n2317), .Y(n2320) );
NOR2X2TS U679 ( .A(n621), .B(n3340), .Y(n2563) );
NAND2XLTS U680 ( .A(n1452), .B(n3692), .Y(n1183) );
CLKINVX2TS U681 ( .A(n2422), .Y(n2415) );
OAI21X2TS U682 ( .A0(n1487), .A1(n1023), .B0(n1026), .Y(n1021) );
NOR2X6TS U683 ( .A(n2583), .B(n1089), .Y(n3394) );
CLKBUFX2TS U684 ( .A(n2140), .Y(n509) );
INVX4TS U685 ( .A(n2980), .Y(n2982) );
NAND2X2TS U686 ( .A(n2084), .B(n3893), .Y(n1313) );
ADDFHX2TS U687 ( .A(n1969), .B(n1968), .CI(n1967), .CO(n2724), .S(n2727) );
OAI22X2TS U688 ( .A0(n1986), .A1(n858), .B0(n2397), .B1(n890), .Y(n2404) );
OAI22X1TS U689 ( .A0(n1156), .A1(n1712), .B0(n1711), .B1(n835), .Y(n1716) );
NAND2X2TS U690 ( .A(n2285), .B(n2298), .Y(n2288) );
INVX1TS U691 ( .A(n1799), .Y(n1148) );
NOR2X6TS U692 ( .A(n2994), .B(n2992), .Y(n507) );
CLKXOR2X2TS U693 ( .A(n1565), .B(n1076), .Y(n1580) );
INVX4TS U694 ( .A(n2412), .Y(n2420) );
INVX2TS U695 ( .A(n2496), .Y(n1230) );
INVX2TS U696 ( .A(n1924), .Y(n837) );
NAND2X4TS U697 ( .A(n1887), .B(n1886), .Y(n2992) );
NOR2BX2TS U698 ( .AN(n848), .B(DP_OP_111J16_123_4462_n682), .Y(n2089) );
NAND2X4TS U699 ( .A(n3227), .B(n625), .Y(n3340) );
INVX4TS U700 ( .A(n993), .Y(n895) );
NOR2BX2TS U701 ( .AN(n1066), .B(n2110), .Y(n2029) );
INVX4TS U702 ( .A(n734), .Y(n890) );
BUFX3TS U703 ( .A(n1423), .Y(n1072) );
OAI2BB1X2TS U704 ( .A0N(DP_OP_111J16_123_4462_n680), .A1N(
DP_OP_111J16_123_4462_n713), .B0(DP_OP_111J16_123_4462_n699), .Y(n1644) );
NOR2X4TS U705 ( .A(n1887), .B(n1886), .Y(n2993) );
INVX4TS U706 ( .A(n2269), .Y(n2272) );
NAND2XLTS U707 ( .A(n831), .B(n2183), .Y(n2184) );
CLKINVX6TS U708 ( .A(n1596), .Y(n1645) );
OAI22X2TS U709 ( .A0(n2068), .A1(n2411), .B0(n857), .B1(n2085), .Y(n2088) );
NAND2X2TS U710 ( .A(n2007), .B(n2006), .Y(n3170) );
NAND2X4TS U711 ( .A(n1185), .B(n1184), .Y(n2054) );
NAND2X2TS U712 ( .A(n528), .B(n527), .Y(n2401) );
XOR2X2TS U713 ( .A(n1100), .B(n825), .Y(n1582) );
NAND2X1TS U714 ( .A(Sgf_normalized_result[10]), .B(Sgf_normalized_result[11]), .Y(n3397) );
NAND2XLTS U715 ( .A(n2173), .B(n800), .Y(n2174) );
XNOR2X2TS U716 ( .A(n3662), .B(n571), .Y(n1685) );
CLKINVX6TS U717 ( .A(n709), .Y(n858) );
CLKXOR2X2TS U718 ( .A(n1099), .B(n1076), .Y(n1988) );
XNOR2X2TS U719 ( .A(n4029), .B(mult_x_23_n545), .Y(n1708) );
CLKBUFX2TS U720 ( .A(n2408), .Y(n396) );
NAND2X6TS U721 ( .A(n2264), .B(n2263), .Y(n2313) );
NOR2X6TS U722 ( .A(n2317), .B(n2319), .Y(n2346) );
NOR2X2TS U723 ( .A(n850), .B(n468), .Y(n1762) );
NOR2X2TS U724 ( .A(n2292), .B(n2244), .Y(n2246) );
NAND2BX2TS U725 ( .AN(n932), .B(n813), .Y(n930) );
XNOR2X2TS U726 ( .A(n2103), .B(n1077), .Y(n2017) );
ADDFHX2TS U727 ( .A(n1530), .B(n1529), .CI(n1528), .CO(n1547), .S(n1531) );
ADDFHX2TS U728 ( .A(n2689), .B(n2690), .CI(n2688), .CO(n2695), .S(n2697) );
NAND2X2TS U729 ( .A(n2196), .B(n513), .Y(n2197) );
OAI22X2TS U730 ( .A0(n1517), .A1(n1020), .B0(n891), .B1(n1186), .Y(n1969) );
NAND2X4TS U731 ( .A(n1889), .B(n1888), .Y(n2995) );
OAI21X2TS U732 ( .A0(n1079), .A1(n2198), .B0(n513), .Y(n2203) );
XOR2X2TS U733 ( .A(n2412), .B(n1076), .Y(n2396) );
NOR2X2TS U734 ( .A(n1034), .B(n501), .Y(n1904) );
NAND2X4TS U735 ( .A(n2637), .B(n2636), .Y(n2836) );
AOI2BB1X2TS U736 ( .A0N(n1913), .A1N(n1891), .B0(n1890), .Y(n1892) );
XOR2X2TS U737 ( .A(n1565), .B(n1077), .Y(n426) );
AND2X6TS U738 ( .A(n2247), .B(n568), .Y(n567) );
XNOR2X2TS U739 ( .A(n1147), .B(n3664), .Y(n2387) );
INVX2TS U740 ( .A(n2186), .Y(n1347) );
BUFX3TS U741 ( .A(n1166), .Y(n1079) );
INVX2TS U742 ( .A(n570), .Y(n1938) );
INVX6TS U743 ( .A(n1085), .Y(n2181) );
OR2X1TS U744 ( .A(n1823), .B(n1824), .Y(n831) );
INVX2TS U745 ( .A(n1565), .Y(n2398) );
OR2X2TS U746 ( .A(n3887), .B(DP_OP_111J16_123_4462_n707), .Y(n1184) );
OR2X2TS U747 ( .A(n3889), .B(DP_OP_111J16_123_4462_n707), .Y(n1003) );
NOR2X1TS U748 ( .A(n2177), .B(n2178), .Y(n2180) );
INVX6TS U749 ( .A(n2977), .Y(n2964) );
NAND2X4TS U750 ( .A(n973), .B(n3787), .Y(n2562) );
INVX4TS U751 ( .A(Op_MY[16]), .Y(n1617) );
NOR2BX2TS U752 ( .AN(n848), .B(DP_OP_111J16_123_4462_n707), .Y(n2059) );
CLKINVX6TS U753 ( .A(n2247), .Y(n2264) );
XNOR2X2TS U754 ( .A(n1090), .B(n1077), .Y(n2030) );
NOR2BX1TS U755 ( .AN(n868), .B(n729), .Y(n2467) );
BUFX16TS U756 ( .A(mult_x_23_n533), .Y(n883) );
XNOR2X2TS U757 ( .A(n1168), .B(n894), .Y(n1928) );
INVX2TS U758 ( .A(n2198), .Y(n2196) );
NAND2X4TS U759 ( .A(n1454), .B(n1345), .Y(n2269) );
INVX2TS U760 ( .A(n2165), .Y(n2168) );
INVX2TS U761 ( .A(n3837), .Y(n1071) );
INVX12TS U762 ( .A(n2837), .Y(n541) );
NAND2X1TS U763 ( .A(n1035), .B(n3824), .Y(n1034) );
AND4X6TS U764 ( .A(n712), .B(n1191), .C(n1459), .D(n1428), .Y(n718) );
NOR2X2TS U765 ( .A(n850), .B(mult_x_55_n444), .Y(n1763) );
NOR2X6TS U766 ( .A(n2259), .B(n2258), .Y(n2299) );
BUFX6TS U767 ( .A(n1566), .Y(n859) );
OAI22X1TS U768 ( .A0(n1476), .A1(n3660), .B0(n863), .B1(n2651), .Y(n2668) );
OR2X4TS U769 ( .A(n2242), .B(n553), .Y(n1369) );
ADDFHX2TS U770 ( .A(n1521), .B(n1520), .CI(n1519), .CO(n1968), .S(n1921) );
OAI22X2TS U771 ( .A0(n847), .A1(n519), .B0(mult_x_55_n554), .B1(n1540), .Y(
n1550) );
NAND2X2TS U772 ( .A(n1295), .B(n1293), .Y(n1292) );
INVX8TS U773 ( .A(n400), .Y(n2014) );
CMPR22X2TS U774 ( .A(n2456), .B(n2455), .CO(n2457), .S(n2451) );
XNOR2X1TS U775 ( .A(n516), .B(n868), .Y(n2461) );
INVX6TS U776 ( .A(n851), .Y(n853) );
MX2X2TS U777 ( .A(n3907), .B(n3897), .S0(n569), .Y(n568) );
CLKINVX12TS U778 ( .A(n2408), .Y(n1076) );
INVX3TS U779 ( .A(n1948), .Y(n1195) );
INVX6TS U780 ( .A(n709), .Y(n857) );
INVX8TS U781 ( .A(n886), .Y(n470) );
INVX6TS U782 ( .A(n715), .Y(n891) );
NOR2BX2TS U783 ( .AN(n894), .B(n850), .Y(n1521) );
INVX2TS U784 ( .A(n1453), .Y(n1910) );
INVX6TS U785 ( .A(n864), .Y(n865) );
INVX2TS U786 ( .A(n1903), .Y(n1426) );
NOR2X2TS U787 ( .A(mult_x_55_n559), .B(mult_x_55_n446), .Y(n1482) );
INVX12TS U788 ( .A(n2753), .Y(n861) );
CLKINVX2TS U789 ( .A(n2636), .Y(n539) );
NAND2X4TS U790 ( .A(n1882), .B(n1883), .Y(n2965) );
BUFX16TS U791 ( .A(n1244), .Y(n1020) );
INVX2TS U792 ( .A(DP_OP_111J16_123_4462_n682), .Y(n993) );
NOR2BX2TS U793 ( .AN(n868), .B(mult_x_23_n540), .Y(n2512) );
INVX6TS U794 ( .A(n2259), .Y(n2241) );
NOR2BX2TS U795 ( .AN(n868), .B(n889), .Y(n2495) );
XOR2X2TS U796 ( .A(n2463), .B(n3706), .Y(n1712) );
OR3X1TS U797 ( .A(n1913), .B(n587), .C(n1908), .Y(n484) );
NAND2X4TS U798 ( .A(n1465), .B(n3076), .Y(n3188) );
NOR2X4TS U799 ( .A(n3788), .B(n3789), .Y(n973) );
NOR2X6TS U800 ( .A(n458), .B(n457), .Y(n1098) );
XNOR2X2TS U801 ( .A(n3573), .B(mult_x_55_n529), .Y(n1483) );
NAND2X6TS U802 ( .A(n1899), .B(n790), .Y(n792) );
CLKINVX6TS U803 ( .A(Op_MY[11]), .Y(n782) );
NOR2X2TS U804 ( .A(mult_x_55_n559), .B(mult_x_55_n448), .Y(n1507) );
INVX4TS U805 ( .A(n1413), .Y(n1864) );
XNOR2X2TS U806 ( .A(n3574), .B(mult_x_55_n530), .Y(n1496) );
OR2X4TS U807 ( .A(n1066), .B(n3890), .Y(n704) );
NAND2BX2TS U808 ( .AN(FSM_selector_B[1]), .B(Op_MY[28]), .Y(n1345) );
ADDHX2TS U809 ( .A(n2608), .B(n2607), .CO(n2675), .S(n2609) );
XNOR2X2TS U810 ( .A(n1450), .B(n2459), .Y(n2484) );
NOR2BX1TS U811 ( .AN(n868), .B(n705), .Y(n2446) );
NAND3X2TS U812 ( .A(n1033), .B(n2981), .C(n2980), .Y(n1191) );
XOR2X2TS U813 ( .A(n1901), .B(n2961), .Y(n479) );
XOR2X2TS U814 ( .A(n2474), .B(mult_x_23_n524), .Y(n2460) );
NAND2X2TS U815 ( .A(n1901), .B(n1900), .Y(n1086) );
AND2X6TS U816 ( .A(DP_OP_111J16_123_4462_n616), .B(
DP_OP_111J16_123_4462_n682), .Y(n2753) );
OR2X6TS U817 ( .A(n1867), .B(n1868), .Y(n1428) );
NAND2X4TS U818 ( .A(n1033), .B(n2981), .Y(n1192) );
CLKINVX6TS U819 ( .A(n686), .Y(n1093) );
NAND2X6TS U820 ( .A(n1454), .B(n2235), .Y(n2259) );
INVX2TS U821 ( .A(n3895), .Y(n1171) );
BUFX4TS U822 ( .A(n811), .Y(n1147) );
NOR2X6TS U823 ( .A(n1883), .B(n1882), .Y(n1396) );
INVX4TS U824 ( .A(n3613), .Y(n2842) );
INVX4TS U825 ( .A(n888), .Y(n889) );
INVX12TS U826 ( .A(n526), .Y(n2108) );
BUFX3TS U827 ( .A(n1995), .Y(n905) );
INVX4TS U828 ( .A(n851), .Y(n852) );
NOR2BX2TS U829 ( .AN(n894), .B(mult_x_55_n555), .Y(n2667) );
NAND2XLTS U830 ( .A(n1453), .B(n489), .Y(n488) );
BUFX3TS U831 ( .A(n3652), .Y(n468) );
INVX2TS U832 ( .A(n1294), .Y(n1293) );
INVX12TS U833 ( .A(DP_OP_111J16_123_4462_n695), .Y(n1006) );
XOR2X2TS U834 ( .A(n455), .B(n2463), .Y(n2450) );
NAND2BX2TS U835 ( .AN(Op_MY[12]), .B(n3695), .Y(n2448) );
XOR2X2TS U836 ( .A(n2474), .B(n3667), .Y(n2452) );
NAND2X4TS U837 ( .A(n3837), .B(DP_OP_111J16_123_4462_n607), .Y(n495) );
NOR2X2TS U838 ( .A(n893), .B(mult_x_55_n480), .Y(n457) );
INVX8TS U839 ( .A(n1495), .Y(n1511) );
NAND2BX2TS U840 ( .AN(n848), .B(DP_OP_111J16_123_4462_n699), .Y(n1994) );
NOR2X1TS U841 ( .A(n863), .B(n1461), .Y(n2633) );
INVX6TS U842 ( .A(n892), .Y(n893) );
NAND2X6TS U843 ( .A(n1865), .B(n1866), .Y(n2981) );
NOR2X1TS U844 ( .A(n1908), .B(n614), .Y(n491) );
INVX2TS U845 ( .A(n3717), .Y(n2459) );
NAND2X4TS U846 ( .A(n808), .B(n1863), .Y(n2972) );
NAND2X2TS U847 ( .A(n2445), .B(n867), .Y(n1140) );
CLKINVX1TS U848 ( .A(n614), .Y(n489) );
CLKINVX6TS U849 ( .A(n1900), .Y(n1088) );
BUFX12TS U850 ( .A(n1450), .Y(n459) );
CLKXOR2X4TS U851 ( .A(n817), .B(n811), .Y(n1253) );
CLKINVX3TS U852 ( .A(n1901), .Y(n1087) );
NAND2BX2TS U853 ( .AN(n2008), .B(n1309), .Y(n1296) );
CLKXOR2X2TS U854 ( .A(n1077), .B(n848), .Y(n1993) );
NAND2X2TS U855 ( .A(DP_OP_111J16_123_4462_n821), .B(
DP_OP_111J16_123_4462_n749), .Y(n1575) );
INVX6TS U856 ( .A(n679), .Y(n1875) );
CLKINVX6TS U857 ( .A(n1493), .Y(n2645) );
INVX4TS U858 ( .A(n2960), .Y(n1878) );
CLKINVX3TS U859 ( .A(n1156), .Y(n2445) );
INVX2TS U860 ( .A(n2215), .Y(n1879) );
INVX6TS U861 ( .A(n862), .Y(n863) );
INVX4TS U862 ( .A(n3885), .Y(n983) );
INVX6TS U863 ( .A(n1309), .Y(n866) );
OA22X2TS U864 ( .A0(n1161), .A1(n2627), .B0(n2628), .B1(n2659), .Y(n2629) );
BUFX8TS U865 ( .A(n3662), .Y(n516) );
NAND2X6TS U866 ( .A(n2761), .B(n2762), .Y(n1376) );
INVX12TS U867 ( .A(n1298), .Y(n884) );
NOR2BX2TS U868 ( .AN(n1896), .B(n1243), .Y(n1242) );
ADDFHX2TS U869 ( .A(n1799), .B(n1798), .CI(n1797), .CO(n806) );
OA21X1TS U870 ( .A0(n1913), .A1(n1219), .B0(n1218), .Y(n722) );
INVX8TS U871 ( .A(mult_x_23_n549), .Y(n2463) );
CLKINVX12TS U872 ( .A(n3696), .Y(n2485) );
NOR2X2TS U873 ( .A(n1160), .B(n592), .Y(n1243) );
CLKINVX2TS U874 ( .A(n1908), .Y(n1419) );
INVX2TS U875 ( .A(n695), .Y(n1309) );
NAND2X4TS U876 ( .A(n1038), .B(n1037), .Y(n1453) );
INVX12TS U877 ( .A(n918), .Y(n885) );
INVX3TS U878 ( .A(n2106), .Y(n1298) );
NOR2X2TS U879 ( .A(n691), .B(n675), .Y(n483) );
NAND2X4TS U880 ( .A(n1407), .B(n1109), .Y(n1107) );
AND2X6TS U881 ( .A(n485), .B(n1278), .Y(n486) );
INVX2TS U882 ( .A(n3854), .Y(n1037) );
INVX6TS U883 ( .A(n1291), .Y(n2106) );
NAND2X6TS U884 ( .A(n596), .B(n628), .Y(n1908) );
INVX2TS U885 ( .A(n816), .Y(n564) );
AND2X4TS U886 ( .A(n3712), .B(n613), .Y(n1109) );
INVX1TS U887 ( .A(n1850), .Y(n1114) );
INVX2TS U888 ( .A(n2206), .Y(n1857) );
CLKXOR2X4TS U889 ( .A(n1133), .B(n3588), .Y(n1852) );
XNOR2X2TS U890 ( .A(n1053), .B(n3598), .Y(n2204) );
XNOR2X2TS U891 ( .A(n672), .B(n894), .Y(n2619) );
NOR2X1TS U892 ( .A(n1895), .B(n591), .Y(n1784) );
NOR2X1TS U893 ( .A(n1895), .B(n608), .Y(n1871) );
INVX2TS U894 ( .A(n3587), .Y(n1043) );
AOI21X2TS U895 ( .A0(n1853), .A1(n626), .B0(n603), .Y(n1854) );
BUFX8TS U896 ( .A(mult_x_55_n583), .Y(n2659) );
NOR2BX2TS U897 ( .AN(n628), .B(n595), .Y(n1278) );
XOR2X2TS U898 ( .A(n2653), .B(mult_x_55_n537), .Y(n2627) );
BUFX8TS U899 ( .A(n2661), .Y(n462) );
OR2X6TS U900 ( .A(n1842), .B(n1841), .Y(n720) );
INVX6TS U901 ( .A(n671), .Y(n2653) );
INVX4TS U902 ( .A(n671), .Y(n672) );
AOI21X2TS U903 ( .A0(n631), .A1(n3703), .B0(n3704), .Y(n1783) );
CLKXOR2X2TS U904 ( .A(n1053), .B(n3598), .Y(n820) );
NAND2X6TS U905 ( .A(n754), .B(n537), .Y(n466) );
NOR2X4TS U906 ( .A(DP_OP_111J16_123_4462_n117), .B(n424), .Y(n492) );
INVX2TS U907 ( .A(n1919), .Y(n1841) );
NOR2X4TS U908 ( .A(n1059), .B(n2989), .Y(n1336) );
INVX12TS U909 ( .A(n1070), .Y(n1160) );
INVX6TS U910 ( .A(n1895), .Y(n1408) );
NAND2X2TS U911 ( .A(n1456), .B(n644), .Y(n1119) );
NOR2X6TS U912 ( .A(n677), .B(n1848), .Y(n777) );
INVX2TS U913 ( .A(n3689), .Y(n584) );
CLKINVX6TS U914 ( .A(n612), .Y(n453) );
INVX4TS U915 ( .A(n2194), .Y(n1848) );
NAND2X6TS U916 ( .A(n2989), .B(n1059), .Y(n1335) );
NOR2X6TS U917 ( .A(n1817), .B(n1818), .Y(n2165) );
NAND2X6TS U918 ( .A(n1822), .B(n1821), .Y(n800) );
INVX12TS U919 ( .A(n1846), .Y(n1059) );
NAND2X6TS U920 ( .A(n1806), .B(n1807), .Y(n747) );
INVX4TS U921 ( .A(n2141), .Y(n1836) );
NAND2X2TS U922 ( .A(n694), .B(n1402), .Y(n1122) );
CLKINVX6TS U923 ( .A(n1835), .Y(n749) );
NOR2X4TS U924 ( .A(n1832), .B(n1833), .Y(n2140) );
NAND2X6TS U925 ( .A(n1834), .B(n827), .Y(n2141) );
OR2X4TS U926 ( .A(n1803), .B(Sgf_operation_EVEN1_Q_middle[1]), .Y(n1806) );
INVX6TS U927 ( .A(Sgf_operation_EVEN1_Q_left[0]), .Y(n2192) );
INVX8TS U928 ( .A(Sgf_operation_EVEN1_Q_left[9]), .Y(n1828) );
INVX8TS U929 ( .A(Sgf_operation_Result[6]), .Y(n1816) );
INVX8TS U930 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n1826) );
NAND2X6TS U931 ( .A(n762), .B(n759), .Y(n1008) );
ADDFHX2TS U932 ( .A(n2666), .B(n2667), .CI(n2665), .CO(n2672), .S(n2674) );
INVX16TS U933 ( .A(n1067), .Y(n848) );
OAI21X4TS U934 ( .A0(n986), .A1(n2081), .B0(n2080), .Y(n924) );
OAI22X4TS U935 ( .A0(n744), .A1(n518), .B0(n893), .B1(n2657), .Y(n2664) );
INVX12TS U936 ( .A(n764), .Y(n770) );
OAI22X4TS U937 ( .A0(n853), .A1(n1541), .B0(n2842), .B1(n1477), .Y(n1485) );
ADDFHX4TS U938 ( .A(n1486), .B(n1485), .CI(n1484), .CO(n1562), .S(n1551) );
XOR2X4TS U939 ( .A(n2925), .B(n2924), .Y(Sgf_operation_EVEN1_left_N7) );
XOR2X4TS U940 ( .A(mult_x_23_n554), .B(n358), .Y(n3561) );
NAND2X4TS U941 ( .A(n1373), .B(n2903), .Y(mult_x_23_n121) );
INVX4TS U942 ( .A(n2615), .Y(n2631) );
AND2X8TS U943 ( .A(n2923), .B(n2936), .Y(n726) );
NAND3X4TS U944 ( .A(n1029), .B(n3078), .C(n1028), .Y(
DP_OP_111J16_123_4462_n161) );
XNOR2X4TS U945 ( .A(n3255), .B(n3762), .Y(n3256) );
OAI21X4TS U946 ( .A0(n3378), .A1(n3765), .B0(n629), .Y(n3255) );
NOR2X8TS U947 ( .A(n3499), .B(n1443), .Y(n2584) );
NOR2X4TS U948 ( .A(n1152), .B(n2906), .Y(mult_x_23_n120) );
XOR2X4TS U949 ( .A(n3151), .B(n1259), .Y(n3849) );
NAND2X2TS U950 ( .A(mult_x_23_n7), .B(mult_x_23_n49), .Y(mult_x_23_n47) );
NAND2X2TS U951 ( .A(mult_x_23_n7), .B(mult_x_23_n38), .Y(mult_x_23_n36) );
XNOR2X4TS U952 ( .A(n2937), .B(n1234), .Y(Sgf_operation_EVEN1_left_N6) );
NAND2X4TS U953 ( .A(n3006), .B(n1393), .Y(add_x_19_n15) );
OAI21X2TS U954 ( .A0(n3372), .A1(n3344), .B0(n3343), .Y(n3345) );
AOI21X4TS U955 ( .A0(n3376), .A1(n3342), .B0(n3341), .Y(n3343) );
XNOR2X2TS U956 ( .A(n3183), .B(n3149), .Y(n3151) );
OAI21X4TS U957 ( .A0(n3372), .A1(n3371), .B0(n3370), .Y(n3373) );
INVX6TS U958 ( .A(n3369), .Y(n3370) );
NOR2X4TS U959 ( .A(n3340), .B(n617), .Y(n3341) );
INVX4TS U960 ( .A(n3101), .Y(n3103) );
NOR2X6TS U961 ( .A(n2320), .B(n2319), .Y(n2333) );
NAND2X8TS U962 ( .A(n2894), .B(n2893), .Y(n2929) );
ADDFHX2TS U963 ( .A(n2376), .B(n2375), .CI(n2374), .CO(n2384), .S(n2373) );
AOI21X4TS U964 ( .A0(n3396), .A1(n3395), .B0(n732), .Y(n378) );
NAND3X2TS U965 ( .A(n3252), .B(n3251), .C(n3250), .Y(n195) );
NAND2X4TS U966 ( .A(n1073), .B(n3071), .Y(DP_OP_111J16_123_4462_n9) );
NAND2BX2TS U967 ( .AN(n2443), .B(mult_x_23_a_0_), .Y(n1141) );
NAND2X4TS U968 ( .A(n2241), .B(n2258), .Y(n2291) );
NOR2X2TS U969 ( .A(mult_x_23_n94), .B(n2912), .Y(mult_x_23_n87) );
NAND2X4TS U970 ( .A(n3015), .B(n2232), .Y(n3008) );
XNOR2X4TS U971 ( .A(n3294), .B(n3758), .Y(n3295) );
NAND2X4TS U972 ( .A(n2777), .B(n2776), .Y(mult_x_55_n12) );
INVX4TS U973 ( .A(n2030), .Y(n2031) );
OAI22X2TS U974 ( .A0(n2017), .A1(DP_OP_111J16_123_4462_n680), .B0(n2030),
.B1(n846), .Y(n1464) );
NOR2X8TS U975 ( .A(n2914), .B(n2934), .Y(mult_x_23_n38) );
NAND2X8TS U976 ( .A(n3736), .B(n2932), .Y(n2914) );
NAND2X6TS U977 ( .A(n1317), .B(n1233), .Y(n1157) );
XNOR2X4TS U978 ( .A(n3281), .B(n3756), .Y(n3282) );
CLKINVX3TS U979 ( .A(n3339), .Y(n3300) );
NOR2X8TS U980 ( .A(n3339), .B(n617), .Y(n3342) );
NAND2X8TS U981 ( .A(n1031), .B(n1030), .Y(n3079) );
AOI21X2TS U982 ( .A0(n882), .A1(n3233), .B0(n3232), .Y(n3234) );
INVX16TS U983 ( .A(n1206), .Y(n882) );
NOR2X4TS U984 ( .A(n2507), .B(n2915), .Y(n1316) );
MXI2X4TS U985 ( .A(n4044), .B(n3902), .S0(n569), .Y(n2336) );
MXI2X4TS U986 ( .A(n3995), .B(n3903), .S0(n569), .Y(n2319) );
NAND2X4TS U987 ( .A(n2900), .B(n2899), .Y(mult_x_23_n16) );
OAI22X1TS U988 ( .A0(mult_x_23_n533), .A1(n3665), .B0(n3668), .B1(
mult_x_23_n517), .Y(n2869) );
OAI21X4TS U989 ( .A0(n2327), .A1(n2346), .B0(n2349), .Y(n2328) );
XNOR2X4TS U990 ( .A(n2463), .B(mult_x_23_n521), .Y(n2489) );
INVX6TS U991 ( .A(n3021), .Y(n3045) );
NOR2X8TS U992 ( .A(n3022), .B(n3021), .Y(add_x_19_n215) );
BUFX8TS U993 ( .A(n3663), .Y(n1158) );
NAND2X4TS U994 ( .A(n2898), .B(n2897), .Y(mult_x_23_n18) );
ADDFHX4TS U995 ( .A(n2892), .B(n2891), .CI(n2890), .CO(n2876), .S(n2893) );
BUFX20TS U996 ( .A(FSM_selector_A), .Y(n569) );
OAI21X4TS U997 ( .A0(n3163), .A1(n3796), .B0(n3164), .Y(n3127) );
OR2X4TS U998 ( .A(n2706), .B(n2707), .Y(n689) );
NOR2X8TS U999 ( .A(n2991), .B(n1101), .Y(n3005) );
NOR2X4TS U1000 ( .A(n2346), .B(n2350), .Y(n2352) );
INVX12TS U1001 ( .A(n2468), .Y(n2854) );
NOR2X4TS U1002 ( .A(n1510), .B(n744), .Y(n458) );
INVX8TS U1003 ( .A(DP_OP_111J16_123_4462_n71), .Y(n3087) );
ADDFHX4TS U1004 ( .A(n2381), .B(n2380), .CI(n2379), .CO(n2382), .S(n2372) );
AOI21X4TS U1005 ( .A0(n882), .A1(n609), .B0(n3754), .Y(n3377) );
CLKINVX12TS U1006 ( .A(DP_OP_111J16_123_4462_n72), .Y(n439) );
AOI21X2TS U1007 ( .A0(n3016), .A1(n2232), .B0(n2231), .Y(n2233) );
INVX4TS U1008 ( .A(n3016), .Y(n3023) );
NOR2X8TS U1009 ( .A(n1979), .B(n404), .Y(mult_x_55_n115) );
XNOR2X4TS U1010 ( .A(n3307), .B(n3752), .Y(n3308) );
OAI21X4TS U1011 ( .A0(n3372), .A1(n3306), .B0(n3305), .Y(n3307) );
INVX4TS U1012 ( .A(mult_x_23_n99), .Y(mult_x_23_n101) );
NAND3X4TS U1013 ( .A(n983), .B(n431), .C(n522), .Y(n521) );
CLKINVX6TS U1014 ( .A(n983), .Y(n524) );
OAI22X2TS U1015 ( .A0(n1988), .A1(n860), .B0(n2396), .B1(n895), .Y(n2402) );
OAI22X2TS U1016 ( .A0(n1988), .A1(n895), .B0(n1580), .B1(n861), .Y(n1991) );
XOR2X4TS U1017 ( .A(n346), .B(n358), .Y(n3152) );
OAI22X2TS U1018 ( .A0(n1601), .A1(n1709), .B0(n729), .B1(n1685), .Y(n1714)
);
OAI22X2TS U1019 ( .A0(n1601), .A1(n516), .B0(n729), .B1(n459), .Y(n1615) );
NOR2X8TS U1020 ( .A(add_x_19_n201), .B(n3005), .Y(n2984) );
NAND2X6TS U1021 ( .A(n1162), .B(n1258), .Y(n1373) );
AOI2BB2X2TS U1022 ( .B0(n252), .B1(n3384), .A0N(n900), .A1N(n3920), .Y(n3386) );
NAND2X8TS U1023 ( .A(n2783), .B(n2773), .Y(mult_x_55_n58) );
NOR2X8TS U1024 ( .A(n3339), .B(n622), .Y(n3320) );
NAND2X4TS U1025 ( .A(mult_x_23_n190), .B(n2895), .Y(mult_x_23_n17) );
ADDFHX4TS U1026 ( .A(n1923), .B(n1922), .CI(n1921), .CO(n1973), .S(n1978) );
OAI22X4TS U1027 ( .A0(n2490), .A1(n1711), .B0(n835), .B1(n2453), .Y(n1715)
);
NAND2X4TS U1028 ( .A(DP_OP_111J16_123_4462_n220), .B(n497), .Y(
DP_OP_111J16_123_4462_n14) );
INVX12TS U1029 ( .A(n2815), .Y(n2817) );
XNOR2X4TS U1030 ( .A(n3345), .B(n3748), .Y(n3346) );
XOR2X4TS U1031 ( .A(n3488), .B(n3487), .Y(n3489) );
XOR2X4TS U1032 ( .A(n2835), .B(n2834), .Y(Sgf_operation_EVEN1_right_N5) );
BUFX20TS U1033 ( .A(n2483), .Y(n942) );
XNOR2X2TS U1034 ( .A(n3661), .B(Op_MY[12]), .Y(n2482) );
ADDFHX4TS U1035 ( .A(n1600), .B(n1599), .CI(n1598), .CO(n1981), .S(n1658) );
ADDFHX4TS U1036 ( .A(n1629), .B(n1628), .CI(n1627), .CO(n1598), .S(n1663) );
NOR2X2TS U1037 ( .A(n850), .B(mult_x_55_n445), .Y(n1481) );
OAI22X4TS U1038 ( .A0(n1701), .A1(n1252), .B0(n865), .B1(mult_x_23_n461),
.Y(n1721) );
XOR2X4TS U1039 ( .A(n3450), .B(n3426), .Y(n3427) );
OAI22X2TS U1040 ( .A0(n2483), .A1(n1702), .B0(n889), .B1(mult_x_23_n470),
.Y(n1698) );
ADDFHX4TS U1041 ( .A(n1609), .B(n1608), .CI(n1607), .CO(n1622), .S(n2432) );
XOR2X4TS U1042 ( .A(n1511), .B(mult_x_55_n270), .Y(n799) );
OAI21X2TS U1043 ( .A0(n3017), .A1(add_x_19_n271), .B0(n1403), .Y(
add_x_19_n221) );
OAI22X2TS U1044 ( .A0(n1577), .A1(n860), .B0(n1580), .B1(n895), .Y(n1589) );
ADDFHX4TS U1045 ( .A(n1690), .B(n1689), .CI(n1688), .CO(n1693), .S(n1748) );
OAI22X4TS U1046 ( .A0(n2483), .A1(mult_x_23_n470), .B0(n2481), .B1(n1666),
.Y(n1689) );
NOR2X8TS U1047 ( .A(n3339), .B(n621), .Y(n2564) );
NAND2X8TS U1048 ( .A(n1128), .B(n1126), .Y(n1125) );
INVX4TS U1049 ( .A(n2904), .Y(n2900) );
INVX4TS U1050 ( .A(n1585), .Y(n1591) );
ADDFHX2TS U1051 ( .A(n3666), .B(n571), .CI(n2869), .CO(n2892), .S(n2872) );
OAI22X2TS U1052 ( .A0(n883), .A1(n3666), .B0(n3668), .B1(n571), .Y(n2378) );
XNOR2X4TS U1053 ( .A(n2453), .B(n3666), .Y(n2488) );
ADDFHX4TS U1054 ( .A(n2889), .B(n2888), .CI(n2887), .CO(n2894), .S(n2391) );
ADDFHX4TS U1055 ( .A(n2872), .B(n2871), .CI(n2870), .CO(n2890), .S(n2888) );
NAND3X6TS U1056 ( .A(n3079), .B(n1027), .C(n3095), .Y(n1029) );
XNOR2X4TS U1057 ( .A(n571), .B(n1158), .Y(n1719) );
XNOR2X4TS U1058 ( .A(n2785), .B(n927), .Y(Sgf_operation_EVEN1_right_N7) );
OAI22X2TS U1059 ( .A0(n2479), .A1(n2476), .B0(n2477), .B1(n1723), .Y(n2510)
);
XNOR2X4TS U1060 ( .A(n2474), .B(n3675), .Y(n2476) );
XNOR2X4TS U1061 ( .A(n3286), .B(n3757), .Y(n3287) );
OAI21X2TS U1062 ( .A0(n3378), .A1(n3285), .B0(n3284), .Y(n3286) );
ADDFHX4TS U1063 ( .A(n1586), .B(n1584), .CI(n1585), .CO(n1983), .S(n1588) );
NAND2X2TS U1064 ( .A(n2779), .B(n2778), .Y(mult_x_55_n18) );
INVX4TS U1065 ( .A(n3046), .Y(n3048) );
INVX4TS U1066 ( .A(n3013), .Y(add_x_19_n186) );
OAI21X2TS U1067 ( .A0(n3010), .A1(n3013), .B0(n3009), .Y(add_x_19_n179) );
ADDFHX2TS U1068 ( .A(n1744), .B(n1743), .CI(n1742), .CO(n1691), .S(n2747) );
OAI22X4TS U1069 ( .A0(n1666), .A1(n2483), .B0(n889), .B1(n1019), .Y(n1673)
);
XNOR2X4TS U1070 ( .A(n3661), .B(n3665), .Y(n1605) );
INVX16TS U1071 ( .A(n392), .Y(n916) );
INVX3TS U1072 ( .A(n463), .Y(DP_OP_111J16_123_4462_n140) );
NAND2X8TS U1073 ( .A(n666), .B(n1103), .Y(DP_OP_111J16_123_4462_n48) );
NAND2X8TS U1074 ( .A(n439), .B(n665), .Y(n666) );
ADDFHX4TS U1075 ( .A(n1991), .B(n1990), .CI(n1989), .CO(n2393), .S(n1980) );
INVX8TS U1076 ( .A(n2757), .Y(n665) );
INVX4TS U1077 ( .A(add_x_19_n124), .Y(n1917) );
AOI21X2TS U1078 ( .A0(add_x_19_n243), .A1(n3052), .B0(n3051), .Y(n1040) );
AOI21X2TS U1079 ( .A0(n3015), .A1(add_x_19_n243), .B0(n3016), .Y(n1403) );
INVX4TS U1080 ( .A(n2227), .Y(n1042) );
INVX8TS U1081 ( .A(n771), .Y(n756) );
NAND2X4TS U1082 ( .A(n2833), .B(n2832), .Y(n2834) );
ADDFHX2TS U1083 ( .A(n2386), .B(n3739), .CI(n2385), .CO(n2889), .S(n2388) );
NAND2X6TS U1084 ( .A(n2424), .B(n2425), .Y(n3071) );
NAND2X4TS U1085 ( .A(n2149), .B(n2148), .Y(n3033) );
NOR2X8TS U1086 ( .A(n2148), .B(n2149), .Y(n3032) );
NAND2X4TS U1087 ( .A(n538), .B(n3003), .Y(add_x_19_n9) );
OAI22X2TS U1088 ( .A0(n1654), .A1(n859), .B0(n1636), .B1(n897), .Y(n2570) );
OAI22X2TS U1089 ( .A0(n2490), .A1(n1734), .B0(n1712), .B1(n835), .Y(n1720)
);
XNOR2X4TS U1090 ( .A(n2453), .B(n3665), .Y(n1734) );
BUFX20TS U1091 ( .A(n2409), .Y(n1100) );
NOR2X2TS U1092 ( .A(DP_OP_111J16_123_4462_n158), .B(n3097), .Y(
DP_OP_111J16_123_4462_n149) );
NAND2X2TS U1093 ( .A(n1067), .B(n887), .Y(n1068) );
OAI22X4TS U1094 ( .A0(n1708), .A1(n865), .B0(mult_x_23_n461), .B1(n1252),
.Y(n1718) );
XNOR2X4TS U1095 ( .A(n2856), .B(n2855), .Y(Sgf_operation_EVEN1_left_N5) );
NAND2X8TS U1096 ( .A(mult_x_23_n530), .B(n2485), .Y(n1601) );
INVX6TS U1097 ( .A(n1009), .Y(mult_x_55_n4) );
XNOR2X2TS U1098 ( .A(n3574), .B(Op_MY[0]), .Y(n2606) );
XOR2X4TS U1099 ( .A(n1195), .B(n782), .Y(n1194) );
OAI22X4TS U1100 ( .A0(n2108), .A1(n2026), .B0(n2043), .B1(n2110), .Y(n2041)
);
NAND2X4TS U1101 ( .A(n2099), .B(n950), .Y(n1105) );
NAND2X2TS U1102 ( .A(add_x_19_n132), .B(add_x_19_n308), .Y(add_x_19_n8) );
NAND2X6TS U1103 ( .A(n395), .B(n912), .Y(n2092) );
BUFX16TS U1104 ( .A(n1169), .Y(n392) );
BUFX6TS U1105 ( .A(DP_OP_111J16_123_4462_n607), .Y(n393) );
BUFX6TS U1106 ( .A(n3659), .Y(n394) );
XNOR2X4TS U1107 ( .A(n672), .B(n3580), .Y(n1943) );
OAI22X4TS U1108 ( .A0(n1161), .A1(n2654), .B0(n1943), .B1(n2659), .Y(n1960)
);
OAI2BB1X4TS U1109 ( .A0N(n1080), .A1N(n914), .B0(n2549), .Y(n395) );
INVX16TS U1110 ( .A(Sgf_operation_Result[0]), .Y(n1802) );
NAND2X8TS U1111 ( .A(n550), .B(n549), .Y(n985) );
NAND3X8TS U1112 ( .A(n398), .B(n1432), .C(n1431), .Y(n2990) );
NAND2X8TS U1113 ( .A(n536), .B(n535), .Y(n398) );
OA21X4TS U1114 ( .A0(n1151), .A1(n3071), .B0(n3072), .Y(n1103) );
NAND3X6TS U1115 ( .A(DP_OP_111J16_123_4462_n821), .B(
DP_OP_111J16_123_4462_n751), .C(DP_OP_111J16_123_4462_n720), .Y(n1172)
);
XOR2X4TS U1116 ( .A(mult_x_55_n445), .B(n2653), .Y(n2601) );
XOR2X4TS U1117 ( .A(n1380), .B(n405), .Y(Sgf_operation_EVEN1_right_N10) );
OAI22X4TS U1118 ( .A0(n1497), .A1(n2842), .B0(n853), .B1(n1513), .Y(n1515)
);
XOR2X4TS U1119 ( .A(n3573), .B(mult_x_55_n445), .Y(n1135) );
XOR2X4TS U1120 ( .A(n2053), .B(n785), .Y(n399) );
OA22X4TS U1121 ( .A0(n1566), .A1(n2009), .B0(n2015), .B1(
DP_OP_111J16_123_4462_n685), .Y(n400) );
NAND2X2TS U1122 ( .A(n2215), .B(n2216), .Y(n3452) );
NAND2X4TS U1123 ( .A(n1808), .B(n1809), .Y(n2200) );
NOR2X4TS U1124 ( .A(n1809), .B(n1808), .Y(n2199) );
NOR2X6TS U1125 ( .A(n1809), .B(n1808), .Y(n690) );
NAND2X8TS U1126 ( .A(n762), .B(n759), .Y(n401) );
OAI22X4TS U1127 ( .A0(n1483), .A1(n744), .B0(n893), .B1(n1479), .Y(n1480) );
CLKBUFX2TS U1128 ( .A(n690), .Y(n1150) );
BUFX3TS U1129 ( .A(n2164), .Y(n1085) );
NOR2X6TS U1130 ( .A(n2704), .B(n2705), .Y(n2733) );
NAND2X6TS U1131 ( .A(n2705), .B(n2704), .Y(n2778) );
XOR2X4TS U1132 ( .A(n2453), .B(n3741), .Y(n1711) );
AO21X1TS U1133 ( .A0(n857), .A1(n2411), .B0(n3892), .Y(n2423) );
OAI22X2TS U1134 ( .A0(n1068), .A1(n2411), .B0(n3892), .B1(n857), .Y(n2111)
);
OAI22X4TS U1135 ( .A0(n895), .A1(n1594), .B0(n1005), .B1(n860), .Y(n1630) );
XNOR2X1TS U1136 ( .A(n985), .B(n1248), .Y(Sgf_operation_EVEN1_right_N9) );
NAND2X6TS U1137 ( .A(n3037), .B(n3007), .Y(n1039) );
NAND2X2TS U1138 ( .A(n3037), .B(n3041), .Y(n1127) );
ADDFHX4TS U1139 ( .A(n1642), .B(n1641), .CI(n1640), .CO(n1637), .S(n2569) );
INVX4TS U1140 ( .A(n2817), .Y(n404) );
NAND2X6TS U1141 ( .A(n3884), .B(DP_OP_111J16_123_4462_n783), .Y(n1567) );
AND2X4TS U1142 ( .A(n2813), .B(n2812), .Y(n405) );
CLKBUFX3TS U1143 ( .A(n2172), .Y(n1102) );
OR2X6TS U1144 ( .A(n1420), .B(n1193), .Y(add_x_19_n152) );
CLKBUFX2TS U1145 ( .A(n810), .Y(n755) );
CLKBUFX3TS U1146 ( .A(n754), .Y(n681) );
INVX2TS U1147 ( .A(n410), .Y(n411) );
CLKINVX1TS U1148 ( .A(n877), .Y(n415) );
INVX16TS U1149 ( .A(n4073), .Y(n877) );
INVX2TS U1150 ( .A(Sgf_operation_EVEN1_right_N2), .Y(n659) );
NAND2BX1TS U1151 ( .AN(n477), .B(Sgf_normalized_result[16]), .Y(n478) );
NAND2X2TS U1152 ( .A(Sgf_normalized_result[17]), .B(
Sgf_normalized_result[16]), .Y(n3445) );
MX2X6TS U1153 ( .A(n3325), .B(n4018), .S0(n635), .Y(n259) );
MX2X6TS U1154 ( .A(n3231), .B(n4013), .S0(n635), .Y(n255) );
MX2X6TS U1155 ( .A(n3302), .B(n4020), .S0(n635), .Y(n257) );
MX2X6TS U1156 ( .A(n3374), .B(n4015), .S0(n635), .Y(n253) );
MX2X4TS U1157 ( .A(n3308), .B(n4012), .S0(n635), .Y(n256) );
MX2X6TS U1158 ( .A(n2581), .B(n3994), .S0(n636), .Y(n241) );
MX2X6TS U1159 ( .A(n3248), .B(n3999), .S0(n636), .Y(n242) );
CLKMX2X4TS U1160 ( .A(n3282), .B(n4005), .S0(n636), .Y(n250) );
MX2X6TS U1161 ( .A(n3254), .B(n4001), .S0(n636), .Y(n246) );
MX2X6TS U1162 ( .A(n3245), .B(n4003), .S0(n636), .Y(n243) );
MX2X6TS U1163 ( .A(n3268), .B(n4004), .S0(n636), .Y(n247) );
CLKINVX6TS U1164 ( .A(n3871), .Y(n1094) );
INVX2TS U1165 ( .A(n1847), .Y(n1048) );
INVX2TS U1166 ( .A(n484), .Y(n501) );
OR2X6TS U1167 ( .A(n804), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2187) );
AND2X2TS U1168 ( .A(n2621), .B(n394), .Y(n803) );
OAI21X2TS U1169 ( .A0(n2339), .A1(n2338), .B0(n2337), .Y(n2340) );
NOR2BX2TS U1170 ( .AN(n894), .B(mult_x_55_n554), .Y(n2644) );
INVX2TS U1171 ( .A(n3933), .Y(n475) );
OAI22X2TS U1172 ( .A0(n698), .A1(mult_x_23_n545), .B0(n865), .B1(n1704), .Y(
n1731) );
AO21X2TS U1173 ( .A0(n1566), .A1(DP_OP_111J16_123_4462_n685), .B0(n3890),
.Y(n1586) );
NAND2BX2TS U1174 ( .AN(n1998), .B(n740), .Y(n1188) );
NAND2BX2TS U1175 ( .AN(n437), .B(Sgf_normalized_result[3]), .Y(n476) );
OAI22X2TS U1176 ( .A0(n2612), .A1(n2626), .B0(n2604), .B1(n844), .Y(n2611)
);
OAI21X2TS U1177 ( .A0(n2435), .A1(n2436), .B0(n2434), .Y(n1250) );
NOR2XLTS U1178 ( .A(n3407), .B(n3406), .Y(n3408) );
INVX2TS U1179 ( .A(n1763), .Y(n1487) );
NAND2X1TS U1180 ( .A(n2965), .B(n1459), .Y(n2966) );
INVX4TS U1181 ( .A(n2938), .Y(n440) );
CLKBUFX2TS U1182 ( .A(Sgf_operation_EVEN1_Q_left[7]), .Y(n512) );
OAI22X2TS U1183 ( .A0(n2420), .A1(n1071), .B0(n2754), .B1(n881), .Y(n1444)
);
INVX6TS U1184 ( .A(n3262), .Y(n3391) );
INVX4TS U1185 ( .A(n3093), .Y(n3091) );
AOI2BB2X2TS U1186 ( .B0(n3391), .B1(n261), .A0N(n901), .A1N(n3911), .Y(n3348) );
NAND2X1TS U1187 ( .A(n3041), .B(n3040), .Y(n3042) );
INVX4TS U1188 ( .A(Sgf_operation_Result[10]), .Y(n694) );
AND2X2TS U1189 ( .A(mult_x_55_a_0_), .B(n356), .Y(n3135) );
NAND2X4TS U1190 ( .A(n3090), .B(n3089), .Y(n3092) );
INVX2TS U1191 ( .A(Data_MY[17]), .Y(n2942) );
INVX4TS U1192 ( .A(n3525), .Y(n3527) );
NAND2X1TS U1193 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n3497) );
NOR2X2TS U1194 ( .A(n3088), .B(n498), .Y(DP_OP_111J16_123_4462_n96) );
AND2X8TS U1195 ( .A(n3856), .B(n598), .Y(n424) );
XOR2X1TS U1196 ( .A(n3577), .B(n316), .Y(n425) );
AND2X8TS U1197 ( .A(n1906), .B(n1907), .Y(n427) );
AND2X8TS U1198 ( .A(n2973), .B(n1455), .Y(n429) );
AND2X8TS U1199 ( .A(n1574), .B(DP_OP_111J16_123_4462_n758), .Y(n431) );
OR2X8TS U1200 ( .A(n1032), .B(n710), .Y(n432) );
AO21X4TS U1201 ( .A0(n786), .A1(n695), .B0(n3888), .Y(n433) );
CLKINVX12TS U1202 ( .A(Op_MY[0]), .Y(n2656) );
AND2X6TS U1203 ( .A(n2923), .B(n2921), .Y(n434) );
AND2X6TS U1204 ( .A(n941), .B(n1454), .Y(n2247) );
AO21X4TS U1205 ( .A0(n3468), .A1(n2209), .B0(n2208), .Y(n435) );
XOR2X4TS U1206 ( .A(n2975), .B(n2974), .Y(n438) );
NAND2X8TS U1207 ( .A(n1818), .B(n1817), .Y(n810) );
INVX2TS U1208 ( .A(n2957), .Y(n2959) );
MX2X2TS U1209 ( .A(n3427), .B(P_Sgf[18]), .S0(n441), .Y(n233) );
MX2X2TS U1210 ( .A(n3473), .B(P_Sgf[15]), .S0(n441), .Y(n230) );
INVX2TS U1211 ( .A(n3451), .Y(n557) );
INVX4TS U1212 ( .A(DP_OP_111J16_123_4462_n158), .Y(n2558) );
MX2X2TS U1213 ( .A(n3495), .B(P_Sgf[14]), .S0(n441), .Y(n229) );
NAND2X2TS U1214 ( .A(n3467), .B(n1473), .Y(n1360) );
MXI2X2TS U1215 ( .A(n3462), .B(n3897), .S0(n3559), .Y(n276) );
NAND3X2TS U1216 ( .A(n3328), .B(n3327), .C(n3326), .Y(n212) );
NAND2X2TS U1217 ( .A(n2801), .B(mult_x_55_n188), .Y(mult_x_55_n14) );
NAND3X2TS U1218 ( .A(n3239), .B(n3238), .C(n3237), .Y(n207) );
NAND3X4TS U1219 ( .A(n3461), .B(n1363), .C(n563), .Y(n560) );
MXI2X2TS U1220 ( .A(n3415), .B(n3898), .S0(n3559), .Y(n278) );
NAND2X2TS U1221 ( .A(n3531), .B(FSM_selector_B[0]), .Y(n975) );
INVX2TS U1222 ( .A(Sgf_operation_EVEN1_right_N3), .Y(n660) );
NAND2X2TS U1223 ( .A(n3798), .B(n3115), .Y(n3113) );
XNOR2X1TS U1224 ( .A(n3798), .B(n3115), .Y(n3851) );
AOI2BB2X2TS U1225 ( .B0(n3391), .B1(n244), .A0N(n902), .A1N(n3954), .Y(n3275) );
NAND2X2TS U1226 ( .A(n3144), .B(n3143), .Y(n3145) );
NAND2X4TS U1227 ( .A(n1355), .B(n1353), .Y(n254) );
NOR2X2TS U1228 ( .A(n3161), .B(n3160), .Y(n3162) );
NAND2X2TS U1229 ( .A(n440), .B(n2939), .Y(n2941) );
INVX2TS U1230 ( .A(n819), .Y(n3134) );
OAI21X1TS U1231 ( .A0(n1221), .A1(n842), .B0(n1220), .Y(n300) );
NAND2X2TS U1232 ( .A(n3845), .B(n3800), .Y(n3844) );
INVX4TS U1233 ( .A(n2637), .Y(n540) );
MX2X2TS U1234 ( .A(n3441), .B(Add_result[17]), .S0(n443), .Y(n289) );
NAND2X2TS U1235 ( .A(n3178), .B(n741), .Y(n3179) );
INVX8TS U1236 ( .A(n3261), .Y(n3383) );
BUFX6TS U1237 ( .A(n3390), .Y(n901) );
NOR2X4TS U1238 ( .A(n3839), .B(n3799), .Y(n3838) );
MX2X2TS U1239 ( .A(n3218), .B(Add_result[8]), .S0(n842), .Y(n298) );
NOR2X2TS U1240 ( .A(n3630), .B(n3641), .Y(n3640) );
INVX3TS U1241 ( .A(n2947), .Y(n1139) );
XOR2X1TS U1242 ( .A(n1914), .B(n3812), .Y(n1915) );
BUFX12TS U1243 ( .A(mult_x_55_n569), .Y(n3577) );
NAND2X2TS U1244 ( .A(n3500), .B(n1282), .Y(n1281) );
NOR2X4TS U1245 ( .A(DP_OP_111J16_123_4462_n891), .B(
DP_OP_111J16_123_4462_n880), .Y(n3803) );
MX2X2TS U1246 ( .A(n3212), .B(Add_result[7]), .S0(n842), .Y(n299) );
INVX8TS U1247 ( .A(mult_x_55_n568), .Y(n1174) );
OAI22X2TS U1248 ( .A0(n2410), .A1(n860), .B0(n2419), .B1(n895), .Y(n2418) );
NAND2X2TS U1249 ( .A(n1347), .B(n2187), .Y(n2189) );
BUFX6TS U1250 ( .A(n878), .Y(n4067) );
BUFX16TS U1251 ( .A(n3459), .Y(n4055) );
MX2X6TS U1252 ( .A(Data_MX[3]), .B(n4048), .S0(n745), .Y(mult_x_55_n569) );
NOR2X4TS U1253 ( .A(n2458), .B(n2457), .Y(n2938) );
INVX3TS U1254 ( .A(n2342), .Y(n2321) );
MX2X6TS U1255 ( .A(Data_MY[15]), .B(n4054), .S0(n746), .Y(n327) );
INVX6TS U1256 ( .A(n2161), .Y(n1901) );
NAND3X1TS U1257 ( .A(n3413), .B(n3557), .C(FSM_selector_B[1]), .Y(n3532) );
INVX16TS U1258 ( .A(n2850), .Y(n746) );
INVX8TS U1259 ( .A(n3412), .Y(n3433) );
INVX2TS U1260 ( .A(n2274), .Y(n2248) );
BUFX12TS U1261 ( .A(n3309), .Y(n3353) );
AND2X2TS U1262 ( .A(n3375), .B(n609), .Y(n696) );
BUFX8TS U1263 ( .A(n3062), .Y(n879) );
INVX2TS U1264 ( .A(n1852), .Y(n2210) );
INVX3TS U1265 ( .A(n3378), .Y(n576) );
INVX2TS U1266 ( .A(n2346), .Y(n2277) );
NAND2X1TS U1267 ( .A(n1159), .B(n3502), .Y(n1209) );
INVX2TS U1268 ( .A(n2583), .Y(n971) );
INVX4TS U1269 ( .A(n3437), .Y(n3477) );
NAND2X4TS U1270 ( .A(n1332), .B(n446), .Y(n3437) );
NAND2X8TS U1271 ( .A(n3502), .B(n3193), .Y(n2583) );
BUFX12TS U1272 ( .A(n3244), .Y(n3378) );
NAND2X6TS U1273 ( .A(n1377), .B(n1454), .Y(n2255) );
CLKINVX2TS U1274 ( .A(n3517), .Y(overflow_flag) );
NOR2X1TS U1275 ( .A(n3193), .B(FS_Module_state_reg[2]), .Y(n3194) );
AND2X2TS U1276 ( .A(n3220), .B(n3221), .Y(n1063) );
NAND2X4TS U1277 ( .A(n3935), .B(n3517), .Y(n3514) );
NAND2XLTS U1278 ( .A(n3516), .B(n3935), .Y(n3518) );
INVX4TS U1279 ( .A(n3733), .Y(n454) );
CLKMX2X2TS U1280 ( .A(n3988), .B(n3987), .S0(n633), .Y(n237) );
INVX2TS U1281 ( .A(n3563), .Y(n3533) );
INVX16TS U1282 ( .A(FS_Module_state_reg[0]), .Y(n3193) );
INVX12TS U1283 ( .A(n867), .Y(n868) );
NAND2X8TS U1284 ( .A(DP_OP_111J16_123_4462_n685), .B(
DP_OP_111J16_123_4462_n619), .Y(n1566) );
INVX8TS U1285 ( .A(n3692), .Y(n2477) );
INVX12TS U1286 ( .A(n880), .Y(n881) );
INVX2TS U1287 ( .A(n3627), .Y(n1054) );
CLKINVX1TS U1288 ( .A(n571), .Y(n572) );
NAND2X1TS U1289 ( .A(n1287), .B(n1285), .Y(n1284) );
INVX2TS U1290 ( .A(Data_MX[16]), .Y(n1180) );
INVX4TS U1291 ( .A(round_mode[1]), .Y(n1285) );
INVX4TS U1292 ( .A(n3000), .Y(n3002) );
NOR2X4TS U1293 ( .A(n3014), .B(n3008), .Y(add_x_19_n204) );
NAND2X2TS U1294 ( .A(n2959), .B(n2958), .Y(add_x_19_n19) );
NAND2X4TS U1295 ( .A(add_x_19_n272), .B(n1383), .Y(n1382) );
INVX4TS U1296 ( .A(mult_x_23_n140), .Y(mult_x_23_n141) );
NAND2X4TS U1297 ( .A(n723), .B(n435), .Y(n1130) );
NAND2X2TS U1298 ( .A(n1383), .B(n3030), .Y(add_x_19_n24) );
NAND2X2TS U1299 ( .A(n557), .B(n3452), .Y(n556) );
INVX4TS U1300 ( .A(n3024), .Y(n3041) );
NAND2X2TS U1301 ( .A(n1360), .B(n1359), .Y(n275) );
NAND2X2TS U1302 ( .A(n2969), .B(n2992), .Y(n2970) );
XOR2X1TS U1303 ( .A(n2941), .B(n2940), .Y(Sgf_operation_EVEN1_left_N4) );
NAND2X2TS U1304 ( .A(n975), .B(n974), .Y(n309) );
NAND2X2TS U1305 ( .A(n542), .B(n2836), .Y(n2838) );
NOR2X6TS U1306 ( .A(n3436), .B(n560), .Y(n559) );
NAND2X2TS U1307 ( .A(n3103), .B(n3102), .Y(n3104) );
NAND2X4TS U1308 ( .A(n1305), .B(n1303), .Y(n2593) );
INVX3TS U1309 ( .A(mult_x_55_n94), .Y(n2797) );
INVX4TS U1310 ( .A(n2995), .Y(n508) );
INVX2TS U1311 ( .A(n2780), .Y(n2782) );
NAND2X2TS U1312 ( .A(n2923), .B(n2922), .Y(n2924) );
NAND2X2TS U1313 ( .A(n3883), .B(n3080), .Y(DP_OP_111J16_123_4462_n7) );
NAND3X4TS U1314 ( .A(n1349), .B(n1351), .C(n1352), .Y(n1348) );
MXI2X2TS U1315 ( .A(n3436), .B(n3899), .S0(n3559), .Y(n277) );
XOR2X1TS U1316 ( .A(n1176), .B(n3155), .Y(n3867) );
NAND2X2TS U1317 ( .A(n3532), .B(n3531), .Y(n308) );
NAND2X4TS U1318 ( .A(n380), .B(n976), .Y(n3531) );
NOR2X4TS U1319 ( .A(n380), .B(n1209), .Y(n1208) );
MXI2X4TS U1320 ( .A(n2303), .B(n1362), .S0(n442), .Y(n3436) );
INVX6TS U1321 ( .A(n2905), .Y(mult_x_23_n190) );
XOR2X1TS U1322 ( .A(n3124), .B(n1202), .Y(n3848) );
OR2X4TS U1323 ( .A(n3075), .B(n3074), .Y(n3883) );
NOR2X2TS U1324 ( .A(n3156), .B(n3805), .Y(n3862) );
NAND2X4TS U1325 ( .A(n1088), .B(n1087), .Y(n790) );
INVX4TS U1326 ( .A(n2504), .Y(n1266) );
NAND2X2TS U1327 ( .A(n3112), .B(n3111), .Y(n3115) );
MXI2X2TS U1328 ( .A(n2312), .B(n3901), .S0(n3559), .Y(n1474) );
NOR2X2TS U1329 ( .A(n3184), .B(n3183), .Y(n3857) );
INVX4TS U1330 ( .A(n2774), .Y(n2805) );
MX2X2TS U1331 ( .A(n3447), .B(Add_result[18]), .S0(n843), .Y(n288) );
NAND2X2TS U1332 ( .A(n3180), .B(n3179), .Y(DP_OP_111J16_123_4462_n6) );
NAND2X2TS U1333 ( .A(n2886), .B(n2933), .Y(mult_x_23_n9) );
NAND2X2TS U1334 ( .A(n2765), .B(n2764), .Y(n2767) );
XNOR2X1TS U1335 ( .A(n323), .B(n3577), .Y(n653) );
NAND2X4TS U1336 ( .A(n2566), .B(n618), .Y(n1212) );
NAND2X4TS U1337 ( .A(n1625), .B(n1624), .Y(n2911) );
XOR2X1TS U1338 ( .A(n358), .B(mult_x_23_n553), .Y(n645) );
INVX2TS U1339 ( .A(n1915), .Y(n460) );
MX2X2TS U1340 ( .A(n3414), .B(Add_result[16]), .S0(n443), .Y(n290) );
MX2X2TS U1341 ( .A(n3435), .B(Add_result[15]), .S0(n443), .Y(n291) );
MX2X2TS U1342 ( .A(n3358), .B(Add_result[9]), .S0(n843), .Y(n297) );
MX2X2TS U1343 ( .A(n3410), .B(Add_result[11]), .S0(n443), .Y(n295) );
MX2X2TS U1344 ( .A(n3419), .B(Add_result[14]), .S0(n443), .Y(n292) );
MX2X2TS U1345 ( .A(n3422), .B(Add_result[13]), .S0(n843), .Y(n293) );
OR2X4TS U1346 ( .A(n477), .B(n3442), .Y(n3443) );
NAND2X2TS U1347 ( .A(n1281), .B(n3226), .Y(n214) );
NAND2X2TS U1348 ( .A(n2849), .B(n2848), .Y(mult_x_55_n6) );
NAND2X4TS U1349 ( .A(n1778), .B(n1777), .Y(n2774) );
NOR2X4TS U1350 ( .A(n3182), .B(n3803), .Y(n3821) );
MX2X2TS U1351 ( .A(n3402), .B(n903), .S0(n842), .Y(n296) );
MX2X2TS U1352 ( .A(n3399), .B(n904), .S0(n842), .Y(n294) );
INVX6TS U1353 ( .A(n2961), .Y(n1900) );
CLKMX2X3TS U1354 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n3511), .Y(n342) );
NOR2X4TS U1355 ( .A(n2885), .B(n2884), .Y(n2934) );
XOR2X4TS U1356 ( .A(n1782), .B(n3811), .Y(n1889) );
INVX2TS U1357 ( .A(n333), .Y(n3567) );
NAND2X2TS U1358 ( .A(n3693), .B(n2944), .Y(n3721) );
NAND2X2TS U1359 ( .A(n3479), .B(n3438), .Y(n3439) );
NAND2BX2TS U1360 ( .AN(mult_x_55_n570), .B(n3716), .Y(n819) );
NAND2X4TS U1361 ( .A(n333), .B(n321), .Y(n3831) );
INVX12TS U1362 ( .A(n2864), .Y(mult_x_23_n553) );
NAND2X2TS U1363 ( .A(n1205), .B(n1204), .Y(n1203) );
NOR2X4TS U1364 ( .A(n333), .B(n321), .Y(n3799) );
NAND2X2TS U1365 ( .A(n3479), .B(n475), .Y(n474) );
NOR2X4TS U1366 ( .A(mult_x_23_n520), .B(mult_x_55_n533), .Y(n3805) );
INVX8TS U1367 ( .A(n841), .Y(n843) );
INVX2TS U1368 ( .A(n348), .Y(n1262) );
INVX12TS U1369 ( .A(n841), .Y(n842) );
INVX6TS U1370 ( .A(n2497), .Y(n1232) );
INVX6TS U1371 ( .A(n2630), .Y(n546) );
INVX2TS U1372 ( .A(mult_x_23_n525), .Y(n3562) );
NAND3X6TS U1373 ( .A(n1398), .B(n1397), .C(n1790), .Y(n1069) );
INVX2TS U1374 ( .A(n350), .Y(n3110) );
NAND3X6TS U1375 ( .A(n972), .B(n3360), .C(n3226), .Y(n3257) );
INVX2TS U1376 ( .A(n2121), .Y(n2084) );
NOR2X4TS U1377 ( .A(n3353), .B(n3226), .Y(n2587) );
INVX12TS U1378 ( .A(n477), .Y(n3479) );
NAND2X2TS U1379 ( .A(n2954), .B(n2953), .Y(mult_x_23_n8) );
MX2X4TS U1380 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n746), .Y(n319) );
XOR2X1TS U1381 ( .A(mult_x_55_n567), .B(n350), .Y(n638) );
INVX2TS U1382 ( .A(n706), .Y(n3060) );
INVX12TS U1383 ( .A(n3413), .Y(n841) );
NAND2X4TS U1384 ( .A(n1141), .B(n1140), .Y(n2878) );
MX2X4TS U1385 ( .A(Data_MY[6]), .B(n4025), .S0(n2945), .Y(mult_x_55_n533) );
INVX8TS U1386 ( .A(n480), .Y(n940) );
CLKMX2X2TS U1387 ( .A(n3199), .B(Add_result[2]), .S0(n3413), .Y(n304) );
BUFX8TS U1388 ( .A(n3459), .Y(n441) );
INVX3TS U1389 ( .A(n1150), .Y(n2201) );
MX2X1TS U1390 ( .A(n3509), .B(Add_result[1]), .S0(n3413), .Y(n305) );
MX2X4TS U1391 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n2945), .Y(
mult_x_23_n520) );
AND2X2TS U1392 ( .A(n3477), .B(n3476), .Y(n3478) );
NOR2X8TS U1393 ( .A(n3529), .B(n3514), .Y(n3524) );
INVX8TS U1394 ( .A(n877), .Y(n878) );
MX2X6TS U1395 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n3129), .Y(
mult_x_55_n565) );
NOR2BX2TS U1396 ( .AN(n1018), .B(n3437), .Y(n1017) );
INVX2TS U1397 ( .A(n2281), .Y(n2250) );
BUFX16TS U1398 ( .A(n3508), .Y(n2945) );
INVX4TS U1399 ( .A(n3217), .Y(n3210) );
NAND2BX1TS U1400 ( .AN(n3935), .B(n3557), .Y(n450) );
NAND2X8TS U1401 ( .A(n1159), .B(n3513), .Y(n3413) );
INVX6TS U1402 ( .A(n2304), .Y(n1385) );
BUFX3TS U1403 ( .A(n2390), .Y(n943) );
AND2X2TS U1404 ( .A(n3225), .B(n3930), .Y(n1282) );
INVX6TS U1405 ( .A(n2255), .Y(n2237) );
BUFX16TS U1406 ( .A(n3508), .Y(n3129) );
INVX8TS U1407 ( .A(n567), .Y(n2314) );
BUFX16TS U1408 ( .A(n2479), .Y(n445) );
NAND3X1TS U1409 ( .A(n1288), .B(n1286), .C(n1284), .Y(n1283) );
INVX3TS U1410 ( .A(n2628), .Y(n2614) );
OAI22X2TS U1411 ( .A0(n1156), .A1(n2450), .B0(n2454), .B1(n4008), .Y(n1143)
);
BUFX8TS U1412 ( .A(n3501), .Y(n1159) );
INVX1TS U1413 ( .A(n3499), .Y(n3225) );
INVX1TS U1414 ( .A(n3513), .Y(n3197) );
NOR2X1TS U1415 ( .A(n3475), .B(n3474), .Y(n3476) );
INVX2TS U1416 ( .A(n3213), .Y(n3207) );
INVX4TS U1417 ( .A(n2260), .Y(n553) );
INVX8TS U1418 ( .A(n2585), .Y(n3502) );
NAND2BX1TS U1419 ( .AN(n1287), .B(n3516), .Y(n1286) );
INVX8TS U1420 ( .A(n845), .Y(n846) );
NAND2X4TS U1421 ( .A(n1564), .B(DP_OP_111J16_123_4462_n774), .Y(n481) );
INVX4TS U1422 ( .A(n1291), .Y(n786) );
BUFX16TS U1423 ( .A(n2490), .Y(n1156) );
NOR2X4TS U1424 ( .A(n850), .B(n3655), .Y(n2792) );
INVX6TS U1425 ( .A(n2653), .Y(n2621) );
AND2X4TS U1426 ( .A(n3618), .B(n1325), .Y(n1324) );
INVX2TS U1427 ( .A(n287), .Y(n3914) );
NAND2X4TS U1428 ( .A(n454), .B(n453), .Y(n452) );
BUFX12TS U1429 ( .A(FS_Module_state_reg[1]), .Y(n1089) );
INVX2TS U1430 ( .A(n3644), .Y(n2603) );
INVX2TS U1431 ( .A(n4036), .Y(n1470) );
INVX8TS U1432 ( .A(DP_OP_111J16_123_4462_n698), .Y(n918) );
OAI21X2TS U1433 ( .A0(n643), .A1(n642), .B0(n641), .Y(add_x_19_n205) );
NAND2X4TS U1434 ( .A(n596), .B(n600), .Y(n1038) );
INVX2TS U1435 ( .A(n3582), .Y(n793) );
INVX2TS U1436 ( .A(n3584), .Y(n1322) );
INVX2TS U1437 ( .A(n3673), .Y(n1319) );
INVX2TS U1438 ( .A(n628), .Y(n487) );
INVX2TS U1439 ( .A(n674), .Y(n675) );
NOR2X4TS U1440 ( .A(exp_oper_result_8_), .B(Exp_module_Overflow_flag_A), .Y(
n3517) );
INVX2TS U1441 ( .A(Sgf_normalized_result[10]), .Y(n3406) );
INVX2TS U1442 ( .A(n3684), .Y(n627) );
INVX2TS U1443 ( .A(n3832), .Y(n1196) );
NAND2X4TS U1444 ( .A(n3724), .B(n3723), .Y(n1045) );
OR2X4TS U1445 ( .A(n3894), .B(n1445), .Y(n1004) );
INVX2TS U1446 ( .A(Add_result[4]), .Y(n3249) );
XOR2X1TS U1447 ( .A(n3774), .B(n606), .Y(n1280) );
NOR2BX1TS U1448 ( .AN(n4014), .B(n634), .Y(n1354) );
CLKAND2X2TS U1449 ( .A(n3785), .B(n3786), .Y(n577) );
NOR2X8TS U1450 ( .A(FS_Module_state_reg[2]), .B(n3928), .Y(n3513) );
CLKMX2X2TS U1451 ( .A(n3990), .B(n3989), .S0(n619), .Y(n236) );
NOR2BX2TS U1452 ( .AN(Op_MY[12]), .B(n3668), .Y(n1707) );
INVX8TS U1453 ( .A(mult_x_23_a_0_), .Y(n835) );
NAND2X2TS U1454 ( .A(n3002), .B(n3001), .Y(add_x_19_n11) );
INVX3TS U1455 ( .A(n2984), .Y(add_x_19_n194) );
NAND2X2TS U1456 ( .A(add_x_19_n215), .B(n3049), .Y(add_x_19_n213) );
NAND2X2TS U1457 ( .A(n3048), .B(n3047), .Y(add_x_19_n17) );
NAND2X6TS U1458 ( .A(n534), .B(n1429), .Y(n1431) );
NAND2X4TS U1459 ( .A(n1422), .B(n1421), .Y(n534) );
NAND2X4TS U1460 ( .A(n1382), .B(n3030), .Y(n1381) );
INVX2TS U1461 ( .A(add_x_19_n243), .Y(n2234) );
INVX8TS U1462 ( .A(add_x_19_n272), .Y(add_x_19_n271) );
INVX6TS U1463 ( .A(DP_OP_111J16_123_4462_n48), .Y(DP_OP_111J16_123_4462_n46)
);
MX2X2TS U1464 ( .A(n3489), .B(P_Sgf[17]), .S0(n4055), .Y(n232) );
MX2X2TS U1465 ( .A(n3405), .B(P_Sgf[16]), .S0(n441), .Y(n231) );
INVX4TS U1466 ( .A(n2546), .Y(DP_OP_111J16_123_4462_n224) );
NOR2X6TS U1467 ( .A(n1316), .B(n1315), .Y(n1314) );
INVX2TS U1468 ( .A(n3040), .Y(n3025) );
INVX2TS U1469 ( .A(n3032), .Y(n3034) );
INVX4TS U1470 ( .A(n3085), .Y(DP_OP_111J16_123_4462_n45) );
INVX8TS U1471 ( .A(n1149), .Y(n1440) );
INVX2TS U1472 ( .A(n3050), .Y(n3051) );
INVX3TS U1473 ( .A(n3484), .Y(n3486) );
NAND2X2TS U1474 ( .A(n3483), .B(n3481), .Y(n3404) );
NAND2X6TS U1475 ( .A(n1425), .B(n1424), .Y(n1906) );
NAND3X4TS U1476 ( .A(n939), .B(n3463), .C(n3464), .Y(n2359) );
NAND2X6TS U1477 ( .A(n2735), .B(n2798), .Y(mult_x_55_n47) );
NAND2X2TS U1478 ( .A(n2810), .B(n2809), .Y(mult_x_55_n15) );
NAND2X6TS U1479 ( .A(n3095), .B(n964), .Y(n963) );
NOR2X4TS U1480 ( .A(n2956), .B(n1074), .Y(n3031) );
NAND2X2TS U1481 ( .A(n3079), .B(n3078), .Y(DP_OP_111J16_123_4462_n21) );
NAND3X6TS U1482 ( .A(n559), .B(n3467), .C(n3465), .Y(n939) );
NAND2X2TS U1483 ( .A(n2782), .B(n2781), .Y(mult_x_55_n11) );
NAND2X4TS U1484 ( .A(n2442), .B(mult_x_23_n97), .Y(mult_x_23_n15) );
NAND2X2TS U1485 ( .A(mult_x_23_n194), .B(n2868), .Y(mult_x_23_n21) );
INVX2TS U1486 ( .A(n3461), .Y(n3462) );
INVX4TS U1487 ( .A(n2965), .Y(n1884) );
NAND2X4TS U1488 ( .A(n1367), .B(n3394), .Y(n561) );
INVX4TS U1489 ( .A(n2800), .Y(mult_x_55_n188) );
INVX8TS U1490 ( .A(n2868), .Y(n1257) );
INVX4TS U1491 ( .A(n1182), .Y(n2940) );
NAND2X1TS U1492 ( .A(n3055), .B(n2961), .Y(add_x_19_n39) );
MX2X2TS U1493 ( .A(n3362), .B(Sgf_normalized_result[23]), .S0(n3361), .Y(
n307) );
NAND2X1TS U1494 ( .A(n3056), .B(n679), .Y(add_x_19_n57) );
INVX6TS U1495 ( .A(n2137), .Y(n532) );
NAND2X4TS U1496 ( .A(n1366), .B(n3456), .Y(n562) );
NAND2X2TS U1497 ( .A(n2928), .B(n2927), .Y(mult_x_23_n12) );
INVX6TS U1498 ( .A(n2733), .Y(n2779) );
MX2X2TS U1499 ( .A(n3444), .B(Add_result[22]), .S0(n3413), .Y(n284) );
NAND2X6TS U1500 ( .A(n1267), .B(n1266), .Y(n2923) );
INVX4TS U1501 ( .A(n2914), .Y(mult_x_23_n49) );
NAND2X4TS U1502 ( .A(n1626), .B(n2911), .Y(mult_x_23_n14) );
NAND2X2TS U1503 ( .A(n1263), .B(n1262), .Y(n1261) );
NAND2X6TS U1504 ( .A(n2441), .B(n2440), .Y(mult_x_23_n97) );
NAND2X4TS U1505 ( .A(n254), .B(n3391), .Y(n1349) );
NAND2X2TS U1506 ( .A(n3075), .B(n3074), .Y(n3080) );
OAI21X2TS U1507 ( .A0(n472), .A1(n842), .B0(n471), .Y(n283) );
NAND2X4TS U1508 ( .A(n2861), .B(n2860), .Y(n1181) );
INVX6TS U1509 ( .A(n2929), .Y(mult_x_23_n65) );
AND2X4TS U1510 ( .A(n3181), .B(mult_x_55_n565), .Y(n3882) );
NAND2X2TS U1511 ( .A(n3157), .B(n3158), .Y(n1202) );
INVX6TS U1512 ( .A(n2912), .Y(n1626) );
XOR2X2TS U1513 ( .A(n921), .B(n3931), .Y(n920) );
ADDFHX2TS U1514 ( .A(n2752), .B(n1444), .CI(n2751), .CO(n3075), .S(n2426) );
NAND2X6TS U1515 ( .A(n1212), .B(n1210), .Y(n380) );
INVX2TS U1516 ( .A(n2045), .Y(n566) );
NAND2X6TS U1517 ( .A(n1179), .B(n1178), .Y(n2865) );
NAND2X2TS U1518 ( .A(n2930), .B(n2932), .Y(mult_x_23_n10) );
MXI2X4TS U1519 ( .A(n1328), .B(n1326), .S0(n634), .Y(n252) );
NAND2X2TS U1520 ( .A(n2195), .B(n2194), .Y(n3202) );
NAND2X6TS U1521 ( .A(n1250), .B(n1249), .Y(n2708) );
NAND2X2TS U1522 ( .A(n3168), .B(n3167), .Y(n3181) );
INVX3TS U1523 ( .A(n2082), .Y(n1310) );
AND2X2TS U1524 ( .A(n2947), .B(n2879), .Y(Sgf_operation_EVEN1_left_N1) );
INVX12TS U1525 ( .A(n1473), .Y(n3559) );
INVX2TS U1526 ( .A(n1467), .Y(n682) );
NOR2X4TS U1527 ( .A(n3442), .B(n474), .Y(n473) );
INVX2TS U1528 ( .A(n2123), .Y(n2132) );
XNOR2X2TS U1529 ( .A(n1016), .B(n3942), .Y(n1015) );
OAI21X1TS U1530 ( .A0(n3797), .A1(n3816), .B0(n3817), .Y(n3130) );
NAND2X2TS U1531 ( .A(n2804), .B(n2802), .Y(mult_x_55_n7) );
CLKMX2X3TS U1532 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n3511), .Y(n369) );
INVX3TS U1533 ( .A(n2284), .Y(n2293) );
CLKMX2X3TS U1534 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n3511), .Y(n368) );
XOR2X2TS U1535 ( .A(n3421), .B(n3944), .Y(n3422) );
XOR2X2TS U1536 ( .A(n3418), .B(n3941), .Y(n3419) );
CLKMX2X3TS U1537 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n3511), .Y(n339) );
CLKMX2X3TS U1538 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n3511), .Y(n370) );
XOR2X2TS U1539 ( .A(n3401), .B(n3406), .Y(n3402) );
CLKMX2X3TS U1540 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n3511), .Y(n367) );
XOR2X2TS U1541 ( .A(n3398), .B(n3932), .Y(n3399) );
AO22X2TS U1542 ( .A0(n3530), .A1(Sgf_normalized_result[21]), .B0(
final_result_ieee[21]), .B1(n3529), .Y(n169) );
AO22X2TS U1543 ( .A0(n3515), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[18]), .B1(n3529), .Y(n172) );
NAND2X2TS U1544 ( .A(n3119), .B(n3118), .Y(n3147) );
AO22X2TS U1545 ( .A0(n3528), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n3526), .Y(n189) );
INVX2TS U1546 ( .A(n3182), .Y(n3845) );
NAND2X2TS U1547 ( .A(n331), .B(n319), .Y(n3817) );
AO22X2TS U1548 ( .A0(n3528), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n3526), .Y(n188) );
CLKMX2X3TS U1549 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n3511), .Y(n338) );
NAND2X2TS U1550 ( .A(n3479), .B(n1017), .Y(n1016) );
AO22X2TS U1551 ( .A0(n3528), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n3526), .Y(n187) );
AO22X2TS U1552 ( .A0(n3528), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[5]), .B1(n3526), .Y(n185) );
AO22X2TS U1553 ( .A0(n3528), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n3527), .Y(n180) );
XOR2X2TS U1554 ( .A(n478), .B(n3943), .Y(n3441) );
AO22X2TS U1555 ( .A0(n3528), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n3527), .Y(n184) );
AO22X2TS U1556 ( .A0(n3528), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n3527), .Y(n181) );
AO22X2TS U1557 ( .A0(n3528), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n3527), .Y(n182) );
AO22X2TS U1558 ( .A0(n3528), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n3527), .Y(n183) );
AO22X2TS U1559 ( .A0(n3515), .A1(n1018), .B0(final_result_ieee[20]), .B1(
n3529), .Y(n170) );
CLKMX2X4TS U1560 ( .A(n3273), .B(n4002), .S0(n636), .Y(n244) );
CLKMX2X3TS U1561 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n3511), .Y(n341) );
CLKMX2X3TS U1562 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n3511), .Y(n340) );
INVX3TS U1563 ( .A(n314), .Y(n3631) );
NAND2X2TS U1564 ( .A(n327), .B(n315), .Y(n1457) );
XNOR2X2TS U1565 ( .A(n3363), .B(n3753), .Y(n3364) );
XOR2X2TS U1566 ( .A(n3357), .B(n3945), .Y(n3358) );
CLKMX2X3TS U1567 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n3511), .Y(n337) );
XOR2X2TS U1568 ( .A(n3434), .B(n3947), .Y(n3435) );
XOR2X2TS U1569 ( .A(n3409), .B(n3948), .Y(n3410) );
AO22X2TS U1570 ( .A0(n3530), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[22]), .B1(n3529), .Y(n167) );
INVX2TS U1571 ( .A(n3505), .Y(n1358) );
INVX6TS U1572 ( .A(n2505), .Y(n1267) );
INVX8TS U1573 ( .A(n2356), .Y(n2330) );
NAND2X4TS U1574 ( .A(n801), .B(n800), .Y(n2179) );
NAND2X6TS U1575 ( .A(n546), .B(n2629), .Y(n2765) );
INVX6TS U1576 ( .A(n1335), .Y(n778) );
INVX4TS U1577 ( .A(mult_x_23_n554), .Y(n3716) );
NAND2X6TS U1578 ( .A(n2877), .B(n2878), .Y(n2947) );
NOR2X4TS U1579 ( .A(n328), .B(n316), .Y(n3182) );
NAND2X2TS U1580 ( .A(mult_x_23_n520), .B(mult_x_55_n533), .Y(n3816) );
INVX3TS U1581 ( .A(mult_x_23_n550), .Y(n3710) );
MX2X4TS U1582 ( .A(n2863), .B(n733), .S0(n745), .Y(n2864) );
ADDFHX2TS U1583 ( .A(n2882), .B(n2881), .CI(n2880), .CO(n2885), .S(n2875) );
MX2X4TS U1584 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n745), .Y(mult_x_23_n518) );
NAND2X2TS U1585 ( .A(mult_x_23_n525), .B(n313), .Y(n3164) );
INVX2TS U1586 ( .A(n2282), .Y(n2278) );
BUFX8TS U1587 ( .A(n3524), .Y(n3530) );
AO22X2TS U1588 ( .A0(n3524), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[17]), .B1(n3527), .Y(n173) );
AO22X2TS U1589 ( .A0(n3524), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[14]), .B1(n3527), .Y(n176) );
CLKMX2X4TS U1590 ( .A(n3256), .B(n4000), .S0(n636), .Y(n245) );
AO22X2TS U1591 ( .A0(n3524), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[13]), .B1(n3527), .Y(n177) );
AO22X2TS U1592 ( .A0(n3524), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n3527), .Y(n179) );
CLKMX2X3TS U1593 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n879), .Y(n310) );
INVX3TS U1594 ( .A(n2287), .Y(n2300) );
NOR2X1TS U1595 ( .A(mult_x_23_n552), .B(mult_x_55_n568), .Y(n3149) );
BUFX8TS U1596 ( .A(n3524), .Y(n3528) );
MX2X4TS U1597 ( .A(Data_MY[5]), .B(n4024), .S0(n745), .Y(
DP_OP_111J16_123_4462_n891) );
INVX3TS U1598 ( .A(mult_x_55_n533), .Y(n3616) );
CLKMX2X3TS U1599 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n879), .Y(n374) );
XNOR2X1TS U1600 ( .A(n3205), .B(n3926), .Y(n3206) );
CLKMX2X3TS U1601 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n879), .Y(n373) );
OR2X4TS U1602 ( .A(n745), .B(n1180), .Y(n1179) );
CLKINVX3TS U1603 ( .A(n1295), .Y(n1290) );
CLKMX2X3TS U1604 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n879), .Y(n372) );
CLKMX2X3TS U1605 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n879), .Y(n343) );
OAI2BB1X2TS U1606 ( .A0N(n1391), .A1N(n696), .B0(n3377), .Y(n1327) );
CLKMX2X3TS U1607 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n879), .Y(n371) );
NAND2X2TS U1608 ( .A(n745), .B(Op_MY[11]), .Y(n783) );
OAI21X2TS U1609 ( .A0(n2565), .A1(n3372), .B0(n979), .Y(n978) );
INVX3TS U1610 ( .A(n2309), .Y(n2307) );
AND3X4TS U1611 ( .A(n3823), .B(n490), .C(n488), .Y(n1782) );
BUFX20TS U1612 ( .A(n745), .Y(n3511) );
XNOR2X2TS U1613 ( .A(n1222), .B(n3936), .Y(n1221) );
OAI21X1TS U1614 ( .A0(n3210), .A1(n3209), .B0(n3208), .Y(n3211) );
NAND2X2TS U1615 ( .A(ready), .B(n3192), .Y(n3198) );
INVX2TS U1616 ( .A(n755), .Y(n2167) );
OR2X2TS U1617 ( .A(n3076), .B(n1465), .Y(n3077) );
MX2X4TS U1618 ( .A(Data_MX[12]), .B(mult_x_23_a_0_), .S0(n3129), .Y(n356) );
OR2X2TS U1619 ( .A(n2952), .B(n2951), .Y(n2954) );
MX2X4TS U1620 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n3062), .Y(n324) );
INVX2TS U1621 ( .A(n2989), .Y(n1430) );
INVX2TS U1622 ( .A(n2294), .Y(n2295) );
NOR2BX2TS U1623 ( .AN(n3219), .B(n1061), .Y(n1060) );
INVX2TS U1624 ( .A(n2313), .Y(n2265) );
INVX16TS U1625 ( .A(n2850), .Y(n745) );
NAND2X2TS U1626 ( .A(n3320), .B(n1329), .Y(n3321) );
MX2X4TS U1627 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n2945), .Y(
mult_x_23_n554) );
NAND2X6TS U1628 ( .A(n2305), .B(n1385), .Y(n2309) );
MX2X4TS U1629 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n2945), .Y(mult_x_55_n570)
);
ADDFHX2TS U1630 ( .A(n1732), .B(n1731), .CI(n1730), .CO(n1724), .S(n2509) );
NAND2X6TS U1631 ( .A(n1297), .B(n1296), .Y(n1295) );
MXI2X4TS U1632 ( .A(n1177), .B(n737), .S0(n3062), .Y(n348) );
MX2X4TS U1633 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n3129), .Y(n321) );
MX2X4TS U1634 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n3062), .Y(n320) );
ADDFHX2TS U1635 ( .A(n2687), .B(n2686), .CI(n2685), .CO(n1964), .S(n2696) );
NAND2X2TS U1636 ( .A(n3314), .B(n3375), .Y(n3315) );
INVX2TS U1637 ( .A(n1159), .Y(n977) );
INVX12TS U1638 ( .A(n1330), .Y(n3375) );
OR2X2TS U1639 ( .A(n1908), .B(n605), .Y(n1912) );
NOR2X1TS U1640 ( .A(n3520), .B(Sgf_normalized_result[2]), .Y(n3521) );
INVX4TS U1641 ( .A(n2148), .Y(n1787) );
NAND2X1TS U1642 ( .A(n683), .B(n2169), .Y(n2170) );
NAND2X6TS U1643 ( .A(n2586), .B(n1089), .Y(n3309) );
OR2X4TS U1644 ( .A(n2447), .B(n2446), .Y(n739) );
OR2X6TS U1645 ( .A(n2445), .B(n1142), .Y(n2877) );
OAI21X2TS U1646 ( .A0(n3378), .A1(n3280), .B0(n3279), .Y(n3281) );
AOI21X4TS U1647 ( .A0(n3217), .A1(n3216), .B0(n3215), .Y(n3412) );
INVX12TS U1648 ( .A(n1160), .Y(n1407) );
NAND2BX2TS U1649 ( .AN(n3411), .B(n1270), .Y(n1269) );
INVX12TS U1650 ( .A(n3525), .Y(n3529) );
NOR2X1TS U1651 ( .A(n3431), .B(n3932), .Y(n3420) );
NOR2X1TS U1652 ( .A(n3431), .B(n3428), .Y(n3417) );
NAND2X6TS U1653 ( .A(n2775), .B(n3190), .Y(n4073) );
INVX12TS U1654 ( .A(n2655), .Y(n2661) );
NOR2X1TS U1655 ( .A(FS_Module_state_reg[0]), .B(n731), .Y(n3496) );
OAI21X2TS U1656 ( .A0(mult_x_23_n523), .A1(n883), .B0(n1268), .Y(n1679) );
NAND2X6TS U1657 ( .A(n1118), .B(n1122), .Y(n1121) );
INVX8TS U1658 ( .A(n568), .Y(n2263) );
INVX2TS U1659 ( .A(n2845), .Y(n2841) );
NAND2X4TS U1660 ( .A(n3499), .B(n2585), .Y(n2586) );
INVX4TS U1661 ( .A(n677), .Y(n1916) );
INVX2TS U1662 ( .A(n2792), .Y(n1776) );
NAND2X2TS U1663 ( .A(n1453), .B(n1036), .Y(n1035) );
INVX4TS U1664 ( .A(n848), .Y(n655) );
NAND2X4TS U1665 ( .A(n3742), .B(n1617), .Y(n1268) );
INVX2TS U1666 ( .A(n1354), .Y(n1353) );
INVX4TS U1667 ( .A(add_x_19_n122), .Y(n3795) );
INVX2TS U1668 ( .A(n2463), .Y(n1671) );
NAND2X6TS U1669 ( .A(n1004), .B(n1003), .Y(n1002) );
INVX2TS U1670 ( .A(n1093), .Y(n527) );
OAI21X1TS U1671 ( .A0(n607), .A1(n3775), .B0(n3246), .Y(n3247) );
NAND2X6TS U1672 ( .A(n511), .B(n1094), .Y(n510) );
INVX6TS U1673 ( .A(n3503), .Y(n1846) );
NOR2X2TS U1674 ( .A(n1461), .B(n467), .Y(n2617) );
INVX4TS U1675 ( .A(n1093), .Y(n929) );
INVX2TS U1676 ( .A(n1211), .Y(n1210) );
CLKAND2X2TS U1677 ( .A(n3224), .B(n3223), .Y(n735) );
OAI21X2TS U1678 ( .A0(n1280), .A1(n633), .B0(n1279), .Y(n235) );
NOR2X1TS U1679 ( .A(n3445), .B(n3934), .Y(n3438) );
INVX2TS U1680 ( .A(n1482), .Y(n1536) );
INVX2TS U1681 ( .A(n3570), .Y(n3538) );
BUFX16TS U1682 ( .A(DP_OP_111J16_123_4462_n684), .Y(n2110) );
CLKINVX1TS U1683 ( .A(Op_MX[19]), .Y(n3548) );
OR2X8TS U1684 ( .A(n3906), .B(FS_Module_state_reg[3]), .Y(n2585) );
INVX8TS U1685 ( .A(n898), .Y(n899) );
INVX2TS U1686 ( .A(n3820), .Y(n1218) );
INVX4TS U1687 ( .A(DP_OP_111J16_123_4462_n713), .Y(n845) );
CLKMX2X4TS U1688 ( .A(n658), .B(n657), .S0(n656), .Y(n287) );
NAND2X2TS U1689 ( .A(n3875), .B(n599), .Y(n1796) );
BUFX12TS U1690 ( .A(n4029), .Y(n455) );
NAND2X2TS U1691 ( .A(n610), .B(n654), .Y(DP_OP_111J16_123_4462_n18) );
INVX2TS U1692 ( .A(n3607), .Y(n1134) );
INVX2TS U1693 ( .A(Add_result[1]), .Y(n3240) );
INVX12TS U1694 ( .A(Sgf_operation_Result[9]), .Y(n1829) );
INVX4TS U1695 ( .A(n3445), .Y(n446) );
INVX6TS U1696 ( .A(n3659), .Y(n552) );
BUFX16TS U1697 ( .A(mult_x_23_n541), .Y(n2481) );
CLKMX2X4TS U1698 ( .A(n3984), .B(n3983), .S0(n633), .Y(n239) );
INVX6TS U1699 ( .A(Sgf_operation_EVEN1_Q_middle[0]), .Y(n1081) );
INVX6TS U1700 ( .A(n3732), .Y(n1273) );
BUFX3TS U1701 ( .A(n4056), .Y(n447) );
CLKBUFX2TS U1702 ( .A(n2080), .Y(n448) );
INVX8TS U1703 ( .A(n1099), .Y(n1154) );
OAI22X4TS U1704 ( .A0(n1578), .A1(n890), .B0(n1593), .B1(n858), .Y(n1628) );
OAI21X4TS U1705 ( .A0(n1246), .A1(n2778), .B0(n2795), .Y(n1245) );
XOR2X4TS U1706 ( .A(n2053), .B(n785), .Y(n911) );
XOR2X4TS U1707 ( .A(n449), .B(n813), .Y(n1950) );
XOR2X4TS U1708 ( .A(n1929), .B(n933), .Y(n449) );
NOR2X8TS U1709 ( .A(n1012), .B(DP_OP_111J16_123_4462_n766), .Y(n688) );
OAI21X4TS U1710 ( .A0(n2359), .A1(n3557), .B0(n450), .Y(n272) );
NOR2X8TS U1711 ( .A(n2257), .B(n2256), .Y(n2304) );
NAND2X8TS U1712 ( .A(n2236), .B(n1454), .Y(n2257) );
AND2X4TS U1713 ( .A(n2224), .B(n1466), .Y(n719) );
XOR2X2TS U1714 ( .A(n2267), .B(n2266), .Y(n2268) );
BUFX8TS U1715 ( .A(n1110), .Y(n463) );
AND2X8TS U1716 ( .A(n1423), .B(n537), .Y(n673) );
NOR2X8TS U1717 ( .A(n1416), .B(n451), .Y(n1415) );
NOR2X4TS U1718 ( .A(n1276), .B(n452), .Y(n451) );
INVX6TS U1719 ( .A(n1065), .Y(n805) );
NOR2X8TS U1720 ( .A(n640), .B(n639), .Y(add_x_19_n122) );
AOI21X4TS U1721 ( .A0(n1190), .A1(n1455), .B0(n2971), .Y(n2975) );
NAND2X2TS U1722 ( .A(n2588), .B(n258), .Y(n3329) );
OR3X4TS U1723 ( .A(n3313), .B(n456), .C(n1390), .Y(n1389) );
INVX12TS U1724 ( .A(Sgf_operation_Result[4]), .Y(n1813) );
NAND3X8TS U1725 ( .A(n1190), .B(n429), .C(n717), .Y(n1410) );
NAND2BX4TS U1726 ( .AN(n1830), .B(n2985), .Y(n3011) );
OAI21X4TS U1727 ( .A0(n798), .A1(n1098), .B0(n797), .Y(n1498) );
NOR2X8TS U1728 ( .A(n434), .B(n2506), .Y(n2507) );
OAI22X2TS U1729 ( .A0(n1601), .A1(n2486), .B0(n729), .B1(n2484), .Y(n2513)
);
XOR2X4TS U1730 ( .A(n1451), .B(n2653), .Y(n1518) );
NOR2X8TS U1731 ( .A(n2749), .B(n2748), .Y(n2896) );
NAND2X8TS U1732 ( .A(n1217), .B(n1215), .Y(add_x_19_n185) );
AO21X4TS U1733 ( .A0(add_x_19_n272), .A1(n3049), .B0(add_x_19_n243), .Y(
n3020) );
XOR2X4TS U1734 ( .A(n2152), .B(n2147), .Y(n2956) );
NAND2X4TS U1735 ( .A(n3004), .B(n3011), .Y(add_x_19_n12) );
OAI21X4TS U1736 ( .A0(n3469), .A1(n3491), .B0(n3470), .Y(n2208) );
NAND2BX4TS U1737 ( .AN(DP_OP_111J16_123_4462_n123), .B(
DP_OP_111J16_123_4462_n128), .Y(DP_OP_111J16_123_4462_n16) );
AO22X2TS U1738 ( .A0(n3737), .A1(n3675), .B0(n3742), .B1(n3739), .Y(n1616)
);
OAI22X4TS U1739 ( .A0(n1005), .A1(DP_OP_111J16_123_4462_n682), .B0(n984),
.B1(n860), .Y(n1649) );
NAND2X2TS U1740 ( .A(n2876), .B(n2875), .Y(n2930) );
OAI22X4TS U1741 ( .A0(n942), .A1(n1602), .B0(n2481), .B1(n1614), .Y(n1620)
);
XOR2X4TS U1742 ( .A(n461), .B(n460), .Y(n533) );
NAND3X6TS U1743 ( .A(n504), .B(n502), .C(n505), .Y(n461) );
INVX8TS U1744 ( .A(n1027), .Y(n962) );
INVX6TS U1745 ( .A(n1838), .Y(n465) );
CLKINVX6TS U1746 ( .A(add_x_19_n308), .Y(n2987) );
NAND4X8TS U1747 ( .A(n1434), .B(n1431), .C(n1432), .D(n1430), .Y(
add_x_19_n308) );
INVX16TS U1748 ( .A(n940), .Y(n2090) );
AO22X4TS U1749 ( .A0(n426), .A1(n845), .B0(n3893), .B1(n2045), .Y(n2124) );
INVX12TS U1750 ( .A(n469), .Y(n1570) );
XNOR2X4TS U1751 ( .A(n448), .B(n464), .Y(n2594) );
XNOR2X4TS U1752 ( .A(n986), .B(n2081), .Y(n464) );
NAND2X8TS U1753 ( .A(n466), .B(n465), .Y(n1056) );
NAND2X6TS U1754 ( .A(n2172), .B(n1825), .Y(n1132) );
NAND2X8TS U1755 ( .A(n768), .B(n1008), .Y(n767) );
NAND3X6TS U1756 ( .A(n953), .B(n1414), .C(n1864), .Y(n1164) );
NAND2X8TS U1757 ( .A(n1411), .B(n1410), .Y(n2979) );
AOI21X4TS U1758 ( .A0(n1898), .A1(n3685), .B0(n3686), .Y(n1384) );
OAI21X4TS U1759 ( .A0(n2298), .A1(n2294), .B0(n1369), .Y(n2261) );
BUFX6TS U1760 ( .A(mult_x_55_n557), .Y(n467) );
ADDFHX4TS U1761 ( .A(n1857), .B(n1856), .CI(n1855), .CO(n808), .S(n676) );
OAI22X4TS U1762 ( .A0(n2626), .A1(n1494), .B0(n2647), .B1(n3653), .Y(n1506)
);
NAND2BX4TS U1763 ( .AN(n3083), .B(n3082), .Y(DP_OP_111J16_123_4462_n15) );
NAND2X4TS U1764 ( .A(n2580), .B(n2579), .Y(n3082) );
NOR2X8TS U1765 ( .A(n2580), .B(n2579), .Y(n3083) );
XOR2X4TS U1766 ( .A(n1570), .B(n470), .Y(n1636) );
XNOR2X4TS U1767 ( .A(n1569), .B(n430), .Y(n469) );
XOR2X4TS U1768 ( .A(n473), .B(n3949), .Y(n472) );
NOR2X8TS U1769 ( .A(n2800), .B(n771), .Y(mult_x_55_n94) );
NOR2X8TS U1770 ( .A(n2362), .B(n2363), .Y(n771) );
NOR2X8TS U1771 ( .A(n2360), .B(n2361), .Y(n2800) );
OAI21X4TS U1772 ( .A0(n2225), .A1(n1409), .B0(n2972), .Y(n1413) );
NOR2X8TS U1773 ( .A(n1863), .B(n1862), .Y(n1409) );
NAND2X8TS U1774 ( .A(n676), .B(n1860), .Y(n2225) );
OAI21X4TS U1775 ( .A0(n3929), .A1(n3200), .B0(n476), .Y(n3217) );
NOR2BX4TS U1776 ( .AN(n436), .B(Sgf_normalized_result[0]), .Y(n3200) );
OR2X8TS U1777 ( .A(n1269), .B(n3412), .Y(n477) );
XNOR2X4TS U1778 ( .A(n1899), .B(n479), .Y(n1888) );
NAND2X8TS U1779 ( .A(n2369), .B(n2370), .Y(n497) );
NOR2X4TS U1780 ( .A(n1563), .B(n483), .Y(n482) );
XOR2X4TS U1781 ( .A(n940), .B(n887), .Y(n1633) );
XOR2X4TS U1782 ( .A(n482), .B(n481), .Y(n480) );
NOR2X6TS U1783 ( .A(n2994), .B(n2993), .Y(n1418) );
NOR2X8TS U1784 ( .A(n1888), .B(n1889), .Y(n2994) );
AOI2BB1X4TS U1785 ( .A0N(n1913), .A1N(n487), .B0(n839), .Y(n1872) );
INVX12TS U1786 ( .A(n485), .Y(n1913) );
NAND2X8TS U1787 ( .A(n493), .B(n492), .Y(n485) );
NAND2XLTS U1788 ( .A(n485), .B(n491), .Y(n490) );
AOI21X4TS U1789 ( .A0(n485), .A1(n1419), .B0(n1453), .Y(n1785) );
NOR2X4TS U1790 ( .A(n1277), .B(n486), .Y(n1792) );
XOR2X4TS U1791 ( .A(n1913), .B(n3814), .Y(n1797) );
NAND2BX4TS U1792 ( .AN(n1781), .B(n510), .Y(n493) );
OAI21X4TS U1793 ( .A0(n1065), .A1(n1110), .B0(n3084), .Y(n833) );
NAND2X8TS U1794 ( .A(n494), .B(n1417), .Y(n500) );
NOR2X8TS U1795 ( .A(n508), .B(n507), .Y(n1417) );
NAND2X8TS U1796 ( .A(n2968), .B(n1418), .Y(n494) );
INVX12TS U1797 ( .A(n500), .Y(n678) );
NAND2X8TS U1798 ( .A(n678), .B(n1433), .Y(n1432) );
NAND2X8TS U1799 ( .A(n496), .B(n495), .Y(n1596) );
OR2X8TS U1800 ( .A(n3894), .B(DP_OP_111J16_123_4462_n707), .Y(n496) );
NOR2X8TS U1801 ( .A(n1920), .B(n1919), .Y(add_x_19_n142) );
XNOR2X4TS U1802 ( .A(n500), .B(n499), .Y(n1920) );
INVX12TS U1803 ( .A(n2367), .Y(n1918) );
NAND4X4TS U1804 ( .A(n2968), .B(n1418), .C(n1223), .D(n506), .Y(n504) );
NAND2X8TS U1805 ( .A(n503), .B(n428), .Y(n502) );
INVX12TS U1806 ( .A(n1224), .Y(n2366) );
AOI21X4TS U1807 ( .A0(n1224), .A1(n506), .B0(n427), .Y(n505) );
AND2X8TS U1808 ( .A(n2218), .B(n3424), .Y(n723) );
NAND2X8TS U1809 ( .A(n1121), .B(n1120), .Y(n779) );
OAI21X4TS U1810 ( .A0(n3011), .A1(n3000), .B0(n3001), .Y(add_x_19_n161) );
XOR2X2TS U1811 ( .A(n1792), .B(n3809), .Y(n1874) );
NAND2X8TS U1812 ( .A(n580), .B(n3870), .Y(n511) );
XNOR2X4TS U1813 ( .A(n1121), .B(n1117), .Y(n1842) );
INVX8TS U1814 ( .A(n580), .Y(DP_OP_111J16_123_4462_n160) );
XNOR2X4TS U1815 ( .A(n580), .B(n3829), .Y(n644) );
NOR2X8TS U1816 ( .A(n1437), .B(n1435), .Y(n1801) );
NAND2X6TS U1817 ( .A(n3870), .B(n580), .Y(n1095) );
NOR2X8TS U1818 ( .A(n1807), .B(n1806), .Y(n2198) );
BUFX3TS U1819 ( .A(n747), .Y(n513) );
NOR2X8TS U1820 ( .A(n1113), .B(n514), .Y(n2164) );
NOR3X8TS U1821 ( .A(n1166), .B(n690), .C(n2198), .Y(n514) );
NAND2X8TS U1822 ( .A(n724), .B(n1091), .Y(n550) );
NAND2X8TS U1823 ( .A(n1371), .B(n1370), .Y(n1091) );
NAND2X8TS U1824 ( .A(n1405), .B(n429), .Y(n953) );
OAI22X4TS U1825 ( .A0(n1601), .A1(n1685), .B0(n2485), .B1(mult_x_23_n480),
.Y(n1669) );
NAND2X4TS U1826 ( .A(mult_x_23_n127), .B(n2902), .Y(mult_x_23_n113) );
XOR2X4TS U1827 ( .A(n517), .B(n829), .Y(n1052) );
XOR2X4TS U1828 ( .A(n1839), .B(Sgf_operation_Result[10]), .Y(n517) );
BUFX6TS U1829 ( .A(n2658), .Y(n518) );
AND2X8TS U1830 ( .A(n1010), .B(n2814), .Y(n812) );
OAI22X4TS U1831 ( .A0(n1156), .A1(n2488), .B0(n1736), .B1(n835), .Y(n2471)
);
OAI22X4TS U1832 ( .A0(n1020), .A1(n1505), .B0(n891), .B1(n519), .Y(n1530) );
XNOR2X4TS U1833 ( .A(n468), .B(n854), .Y(n519) );
XOR2X4TS U1834 ( .A(n1099), .B(n825), .Y(n1635) );
NAND3X8TS U1835 ( .A(n523), .B(n521), .C(n520), .Y(n1099) );
OR2X8TS U1836 ( .A(n522), .B(n431), .Y(n520) );
NAND2X8TS U1837 ( .A(n1573), .B(DP_OP_111J16_123_4462_n720), .Y(n522) );
NAND2BX4TS U1838 ( .AN(n431), .B(n524), .Y(n523) );
NOR2X8TS U1839 ( .A(n390), .B(n3613), .Y(n851) );
NAND2X6TS U1840 ( .A(n767), .B(n765), .Y(mult_x_55_n3) );
OAI22X4TS U1841 ( .A0(n2626), .A1(n2604), .B0(n2647), .B1(n2603), .Y(n2665)
);
OAI22X2TS U1842 ( .A0(n1476), .A1(n697), .B0(n863), .B1(n1959), .Y(n2693) );
NAND2X4TS U1843 ( .A(n2736), .B(n2737), .Y(n3084) );
NAND2BX4TS U1844 ( .AN(n3097), .B(n3096), .Y(DP_OP_111J16_123_4462_n19) );
NAND2X4TS U1845 ( .A(n2598), .B(n2599), .Y(n3096) );
NOR2X8TS U1846 ( .A(n2599), .B(n2598), .Y(n3097) );
NAND2X2TS U1847 ( .A(n2108), .B(n2110), .Y(n528) );
AND2X8TS U1848 ( .A(n1571), .B(n2110), .Y(n526) );
OAI2BB1X4TS U1849 ( .A0N(n2063), .A1N(n2062), .B0(n529), .Y(n2541) );
OAI21X4TS U1850 ( .A0(n2062), .A1(n2063), .B0(n531), .Y(n529) );
XOR2X4TS U1851 ( .A(n530), .B(n2062), .Y(n2093) );
XOR2X4TS U1852 ( .A(n2063), .B(n531), .Y(n530) );
OAI22X4TS U1853 ( .A0(n2064), .A1(n859), .B0(n2061), .B1(n897), .Y(n531) );
XOR2X4TS U1854 ( .A(n940), .B(n886), .Y(n2064) );
NAND2X4TS U1855 ( .A(n2137), .B(n2136), .Y(n964) );
NAND2X8TS U1856 ( .A(n532), .B(n1301), .Y(n3095) );
NAND2X4TS U1857 ( .A(n1919), .B(n1920), .Y(n3003) );
NAND2X2TS U1858 ( .A(n533), .B(n1916), .Y(add_x_19_n125) );
NOR2X8TS U1859 ( .A(n533), .B(n1916), .Y(add_x_19_n124) );
NAND2X8TS U1860 ( .A(n536), .B(n535), .Y(n1434) );
INVX8TS U1861 ( .A(n678), .Y(n536) );
NOR2X8TS U1862 ( .A(n2151), .B(n2153), .Y(n537) );
INVX12TS U1863 ( .A(add_x_19_n142), .Y(n538) );
XNOR2X4TS U1864 ( .A(n4026), .B(n3653), .Y(n2604) );
NAND2X8TS U1865 ( .A(n540), .B(n539), .Y(n542) );
NOR2X8TS U1866 ( .A(n2641), .B(n2640), .Y(n2826) );
NAND2X8TS U1867 ( .A(n2825), .B(n543), .Y(n1371) );
NOR2X6TS U1868 ( .A(n2826), .B(n2831), .Y(n543) );
NOR2X4TS U1869 ( .A(n2639), .B(n2638), .Y(n2831) );
NAND2X8TS U1870 ( .A(n544), .B(n2836), .Y(n2825) );
NAND2X8TS U1871 ( .A(n542), .B(n541), .Y(n544) );
AND2X8TS U1872 ( .A(n545), .B(n2764), .Y(n2837) );
NAND2X4TS U1873 ( .A(n2766), .B(n2765), .Y(n545) );
OAI21X4TS U1874 ( .A0(n2768), .A1(n1376), .B0(n2769), .Y(n2766) );
NOR2X8TS U1875 ( .A(n2701), .B(n2700), .Y(n2818) );
AOI21X4TS U1876 ( .A0(n2823), .A1(n2820), .B0(n2681), .Y(n549) );
NAND2X8TS U1877 ( .A(n552), .B(n551), .Y(n2655) );
XNOR2X4TS U1878 ( .A(mult_x_55_n583), .B(n671), .Y(n551) );
NAND2X6TS U1879 ( .A(n2639), .B(n2638), .Y(n2832) );
AND2X8TS U1880 ( .A(n2242), .B(n553), .Y(n2294) );
OR2X8TS U1881 ( .A(n728), .B(FSM_selector_B[1]), .Y(n2242) );
OAI21X4TS U1882 ( .A0(n555), .A1(n4055), .B0(n554), .Y(n234) );
XOR2X4TS U1883 ( .A(n558), .B(n556), .Y(n555) );
OAI21X4TS U1884 ( .A0(n3450), .A1(n3449), .B0(n3448), .Y(n558) );
AOI21X4TS U1885 ( .A0(n435), .A1(n3424), .B0(n3423), .Y(n3450) );
NAND2X4TS U1886 ( .A(n2706), .B(n2707), .Y(n2795) );
NOR2X8TS U1887 ( .A(n2707), .B(n2706), .Y(n1246) );
INVX2TS U1888 ( .A(n563), .Y(n3415) );
MX2X6TS U1889 ( .A(n2289), .B(n2290), .S0(n442), .Y(n563) );
OAI21X4TS U1890 ( .A0(DP_OP_111J16_123_4462_n778), .A1(n564), .B0(
DP_OP_111J16_123_4462_n783), .Y(n1563) );
XOR2X4TS U1891 ( .A(n2160), .B(n2159), .Y(n565) );
AOI2BB2X4TS U1892 ( .B0(n2031), .B1(n3893), .A0N(n846), .A1N(n566), .Y(n2032) );
XOR2X4TS U1893 ( .A(n2090), .B(n1077), .Y(n2045) );
AOI21X4TS U1894 ( .A0(n1027), .A1(n3095), .B0(n3094), .Y(
DP_OP_111J16_123_4462_n168) );
NAND2X8TS U1895 ( .A(n966), .B(n965), .Y(n1027) );
OA22X4TS U1896 ( .A0(n2652), .A1(n1931), .B0(n2650), .B1(n1512), .Y(n570) );
XOR2X4TS U1897 ( .A(n573), .B(n1567), .Y(n1064) );
AO21X4TS U1898 ( .A0(n836), .A1(DP_OP_111J16_123_4462_n785), .B0(n816), .Y(
n573) );
OAI2BB1X4TS U1899 ( .A0N(n576), .A1N(n574), .B0(n3764), .Y(n3272) );
NOR2X8TS U1900 ( .A(n3731), .B(n3730), .Y(n1274) );
XNOR2X4TS U1901 ( .A(n3324), .B(n3747), .Y(n3325) );
OAI22X4TS U1902 ( .A0(n984), .A1(DP_OP_111J16_123_4462_n682), .B0(n861),
.B1(n1651), .Y(n1643) );
ADDHX4TS U1903 ( .A(n2066), .B(n2067), .CO(n2063), .S(n2077) );
ADDFHX4TS U1904 ( .A(n2415), .B(n2414), .CI(n2413), .CO(n2416), .S(n2406) );
ADDFHX4TS U1905 ( .A(n2401), .B(n2400), .CI(n2399), .CO(n2413), .S(n2403) );
NOR2X8TS U1906 ( .A(n3012), .B(n3000), .Y(add_x_19_n160) );
NAND2X8TS U1907 ( .A(n1868), .B(n1867), .Y(n1033) );
XNOR2X4TS U1908 ( .A(n1570), .B(n887), .Y(n1986) );
NOR2X2TS U1909 ( .A(n2546), .B(n1065), .Y(DP_OP_111J16_123_4462_n130) );
AO21X1TS U1910 ( .A0(n630), .A1(n3767), .B0(n3768), .Y(n578) );
INVX8TS U1911 ( .A(n1408), .Y(n583) );
NAND2X4TS U1912 ( .A(n602), .B(n585), .Y(n1895) );
OAI2BB1X4TS U1913 ( .A0N(n3688), .A1N(n585), .B0(n584), .Y(n1070) );
OR2X2TS U1914 ( .A(n1908), .B(n586), .Y(n1891) );
OAI21X1TS U1915 ( .A0(n1910), .A1(n586), .B0(n3825), .Y(n1890) );
OAI21X1TS U1916 ( .A0(n615), .A1(n1447), .B0(n589), .Y(n3277) );
NOR2X1TS U1917 ( .A(n3368), .B(n590), .Y(n3232) );
OR2X4TS U1918 ( .A(n1160), .B(n593), .Y(n1397) );
OAI21X2TS U1919 ( .A0(n595), .A1(n1791), .B0(n3853), .Y(n1277) );
OAI21X4TS U1920 ( .A0(n601), .A1(n597), .B0(n3826), .Y(n1437) );
INVX2TS U1921 ( .A(n603), .Y(n597) );
INVX2TS U1922 ( .A(n601), .Y(n1163) );
NAND2X2TS U1923 ( .A(n626), .B(n598), .Y(n1781) );
OA21X4TS U1924 ( .A0(n608), .A1(n1160), .B0(n3677), .Y(n1321) );
AOI21X1TS U1925 ( .A0(n1853), .A1(n610), .B0(n3822), .Y(n1849) );
NAND2X1TS U1926 ( .A(n581), .B(n611), .Y(n3293) );
AOI21X4TS U1927 ( .A0(n973), .A1(n616), .B0(add_x_19_n141), .Y(n2561) );
AOI2BB1X2TS U1928 ( .A0N(n3283), .A1N(n1462), .B0(n616), .Y(n3284) );
NOR2X1TS U1929 ( .A(n3368), .B(n623), .Y(n3228) );
NOR2X4TS U1930 ( .A(n3795), .B(n623), .Y(n3229) );
NOR2X1TS U1931 ( .A(n3368), .B(n624), .Y(n3303) );
CLKINVX1TS U1932 ( .A(n626), .Y(n1800) );
OAI21X4TS U1933 ( .A0(n1275), .A1(n1276), .B0(n627), .Y(n1272) );
XNOR2X4TS U1934 ( .A(n3713), .B(n3714), .Y(n829) );
XOR2X4TS U1935 ( .A(n3713), .B(n3714), .Y(n1402) );
XOR2X4TS U1936 ( .A(n3713), .B(n3714), .Y(n693) );
AOI21X4TS U1937 ( .A0(n3726), .A1(n3727), .B0(n3728), .Y(n1840) );
AOI21X2TS U1938 ( .A0(n631), .A1(n613), .B0(n3698), .Y(n1106) );
NAND2X1TS U1939 ( .A(n633), .B(n3992), .Y(n1279) );
CLKMX2X2TS U1940 ( .A(n3986), .B(n3985), .S0(n633), .Y(n238) );
CLKMX2X3TS U1941 ( .A(n3287), .B(n4007), .S0(n636), .Y(n249) );
CLKMX2X2TS U1942 ( .A(n3295), .B(n4006), .S0(n636), .Y(n248) );
INVX8TS U1943 ( .A(n637), .Y(add_x_19_n310) );
AND2X8TS U1944 ( .A(n1420), .B(n1193), .Y(n637) );
NAND2X4TS U1945 ( .A(n432), .B(n1458), .Y(n2221) );
OAI21X2TS U1946 ( .A0(n3868), .A1(DP_OP_111J16_123_4462_n160), .B0(n3869),
.Y(n1197) );
XOR2X4TS U1947 ( .A(n1452), .B(n3665), .Y(n1703) );
OAI21X4TS U1948 ( .A0(n648), .A1(n647), .B0(n646), .Y(
DP_OP_111J16_123_4462_n117) );
INVX2TS U1949 ( .A(n3830), .Y(n649) );
OAI21X2TS U1950 ( .A0(DP_OP_111J16_123_4462_n754), .A1(
DP_OP_111J16_123_4462_n744), .B0(DP_OP_111J16_123_4462_n749), .Y(n1568) );
INVX2TS U1951 ( .A(n3841), .Y(n3863) );
NOR2X2TS U1952 ( .A(mult_x_23_n516), .B(n322), .Y(n3841) );
NOR2X2TS U1953 ( .A(DP_OP_111J16_123_4462_n753), .B(
DP_OP_111J16_123_4462_n744), .Y(n650) );
AOI21X4TS U1954 ( .A0(n650), .A1(DP_OP_111J16_123_4462_n720), .B0(n1568),
.Y(n1569) );
OAI21X2TS U1955 ( .A0(n652), .A1(n651), .B0(n599), .Y(n839) );
AO21X1TS U1956 ( .A0(n2626), .A1(n2647), .B0(n3653), .Y(n1537) );
OAI22X2TS U1957 ( .A0(n2626), .A1(n3653), .B0(n844), .B1(n2623), .Y(n2635)
);
XNOR2X1TS U1958 ( .A(n3575), .B(n894), .Y(n2625) );
NAND2X1TS U1959 ( .A(n2656), .B(n3575), .Y(n2623) );
INVX8TS U1960 ( .A(n1067), .Y(n1066) );
NAND2X8TS U1961 ( .A(DP_OP_111J16_123_4462_n820), .B(
DP_OP_111J16_123_4462_n831), .Y(n1067) );
MXI2X1TS U1962 ( .A(n1805), .B(n3964), .S0(n4055), .Y(n217) );
MXI2X1TS U1963 ( .A(n1811), .B(n3965), .S0(n3510), .Y(n218) );
XNOR2X4TS U1964 ( .A(n2997), .B(n664), .Y(n1420) );
INVX12TS U1965 ( .A(n764), .Y(n744) );
NAND2X2TS U1966 ( .A(n2817), .B(n2816), .Y(mult_x_55_n16) );
OAI2BB1X4TS U1967 ( .A0N(n2817), .A1N(n1245), .B0(n2816), .Y(mult_x_55_n116)
);
ADDFHX4TS U1968 ( .A(n2135), .B(n2134), .CI(n2133), .S(n668) );
ADDFHX2TS U1969 ( .A(n2135), .B(n2134), .CI(n2133), .CO(n2136), .S(n2050) );
OAI22X4TS U1970 ( .A0(n2037), .A1(n884), .B0(n2107), .B1(n866), .Y(n2135) );
INVX4TS U1971 ( .A(n2662), .Y(n2663) );
NOR2X8TS U1972 ( .A(n2214), .B(n2213), .Y(n3449) );
INVX4TS U1973 ( .A(n2799), .Y(mult_x_55_n78) );
OAI22X2TS U1974 ( .A0(n2626), .A1(n2646), .B0(n2647), .B1(n1963), .Y(n2642)
);
XNOR2X4TS U1975 ( .A(n916), .B(n918), .Y(n2023) );
NAND2BX2TS U1976 ( .AN(n2098), .B(n2097), .Y(n2051) );
OAI2BB2X4TS U1977 ( .B0(n861), .B1(n3891), .A0N(n993), .A1N(n669), .Y(n2067)
);
NOR2X4TS U1978 ( .A(n1066), .B(n3891), .Y(n669) );
NAND2X8TS U1979 ( .A(n756), .B(n1011), .Y(n670) );
NAND2X4TS U1980 ( .A(n756), .B(n1011), .Y(n1010) );
OAI21X4TS U1981 ( .A0(n2816), .A1(n2808), .B0(n2809), .Y(n766) );
NOR2X8TS U1982 ( .A(n809), .B(n1047), .Y(n1046) );
ADDFHX4TS U1983 ( .A(n2643), .B(n2644), .CI(n2642), .CO(n2691), .S(n2699) );
NAND2X6TS U1984 ( .A(n2036), .B(n2035), .Y(n3099) );
XNOR2X2TS U1985 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n697), .Y(n2044) );
CLKINVX12TS U1986 ( .A(DP_OP_111J16_123_4462_n697), .Y(n917) );
XNOR2X4TS U1987 ( .A(n2766), .B(n2767), .Y(Sgf_operation_EVEN1_right_N3) );
NAND2BX1TS U1988 ( .AN(n3657), .B(n2656), .Y(n2657) );
NOR2X6TS U1989 ( .A(Sgf_operation_EVEN1_Q_left[8]), .B(n2985), .Y(n3012) );
OR2X2TS U1990 ( .A(n1820), .B(n1819), .Y(n683) );
ADDFHX4TS U1991 ( .A(n2129), .B(n2128), .CI(n2127), .CO(n2554), .S(n2130) );
ADDFHX4TS U1992 ( .A(n2102), .B(n2101), .CI(n2100), .CO(n2552), .S(n2555) );
OAI22X2TS U1993 ( .A0(n2105), .A1(n884), .B0(n2091), .B1(n866), .Y(n2100) );
OAI22X4TS U1994 ( .A0(n2107), .A1(n884), .B0(n2105), .B1(n866), .Y(n2128) );
NOR2X8TS U1995 ( .A(n3018), .B(n2957), .Y(n3015) );
NOR2X8TS U1996 ( .A(n2228), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2957) );
INVX8TS U1997 ( .A(n954), .Y(n1166) );
XNOR2X4TS U1998 ( .A(n1844), .B(n3681), .Y(n677) );
ADDFHX4TS U1999 ( .A(n2089), .B(n2087), .CI(n2088), .CO(n2076), .S(n2101) );
NAND2X4TS U2000 ( .A(n924), .B(n923), .Y(n2532) );
XNOR2X2TS U2001 ( .A(n2220), .B(n2221), .Y(n2227) );
CLKBUFX2TS U2002 ( .A(n673), .Y(n818) );
NOR2X8TS U2003 ( .A(n2164), .B(n1112), .Y(n1423) );
NAND2X4TS U2004 ( .A(add_x_19_n202), .B(n1395), .Y(add_x_19_n16) );
NAND2X4TS U2005 ( .A(n438), .B(n802), .Y(add_x_19_n202) );
NOR2X8TS U2006 ( .A(n438), .B(n802), .Y(add_x_19_n201) );
XOR2X2TS U2007 ( .A(n2188), .B(n2189), .Y(n2195) );
NAND2X2TS U2008 ( .A(n1460), .B(n1903), .Y(n1424) );
NAND2X6TS U2009 ( .A(n1902), .B(n791), .Y(n1425) );
NAND2X4TS U2010 ( .A(n1427), .B(n1426), .Y(n791) );
INVX4TS U2011 ( .A(DP_OP_111J16_123_4462_n767), .Y(n1012) );
OAI22X2TS U2012 ( .A0(n4008), .A1(n2489), .B0(n2464), .B1(n1156), .Y(n2491)
);
OAI22X2TS U2013 ( .A0(n2044), .A1(n897), .B0(n2024), .B1(n1566), .Y(n2040)
);
INVX4TS U2014 ( .A(n2097), .Y(n1299) );
NAND2BX1TS U2015 ( .AN(n1062), .B(n3222), .Y(n1061) );
NAND2X6TS U2016 ( .A(n1428), .B(n1192), .Y(n1414) );
NAND2X4TS U2017 ( .A(n2176), .B(n1825), .Y(n1112) );
ADDFHX2TS U2018 ( .A(n2115), .B(n2114), .CI(n2113), .CO(n2118), .S(n2125) );
INVX8TS U2019 ( .A(n1396), .Y(n1459) );
OAI22X2TS U2020 ( .A0(n445), .A1(n2449), .B0(n705), .B1(n2452), .Y(n2455) );
MXI2X4TS U2021 ( .A(n3982), .B(n3901), .S0(n569), .Y(n2254) );
INVX2TS U2022 ( .A(n631), .Y(n1790) );
INVX4TS U2023 ( .A(n701), .Y(n1422) );
OAI22X2TS U2024 ( .A0(n2487), .A1(n2461), .B0(n729), .B1(n2473), .Y(n2500)
);
INVX2TS U2025 ( .A(n947), .Y(n946) );
INVX2TS U2026 ( .A(n1318), .Y(n830) );
INVX12TS U2027 ( .A(Sgf_operation_EVEN1_Q_left[6]), .Y(n1215) );
INVX2TS U2028 ( .A(n1996), .Y(n1187) );
NAND2X6TS U2029 ( .A(n3513), .B(n3193), .Y(n3499) );
NOR2X4TS U2030 ( .A(n1283), .B(n1060), .Y(n3500) );
CLKINVX6TS U2031 ( .A(DP_OP_111J16_123_4462_n766), .Y(n1573) );
INVX2TS U2032 ( .A(n3819), .Y(n1219) );
INVX2TS U2033 ( .A(n2550), .Y(n914) );
INVX6TS U2034 ( .A(Sgf_operation_EVEN1_Q_left[3]), .Y(n1810) );
NAND2X1TS U2035 ( .A(n707), .B(Op_MY[27]), .Y(n941) );
NAND2X2TS U2036 ( .A(n1461), .B(n3572), .Y(n1926) );
NOR2X2TS U2037 ( .A(n700), .B(n1461), .Y(n1946) );
NAND2X2TS U2038 ( .A(n707), .B(Op_MY[25]), .Y(n2235) );
AOI2BB2X2TS U2039 ( .B0(n3742), .B1(n2459), .A0N(n883), .A1N(mult_x_23_n524),
.Y(n1665) );
OAI22X2TS U2040 ( .A0(n2487), .A1(n1677), .B0(n2485), .B1(n516), .Y(n1608)
);
INVX2TS U2041 ( .A(n1311), .Y(n1306) );
INVX2TS U2042 ( .A(n2347), .Y(n2326) );
NAND2X2TS U2043 ( .A(n707), .B(Op_MY[29]), .Y(n2276) );
NAND2X4TS U2044 ( .A(n2257), .B(n2256), .Y(n2305) );
NAND2X4TS U2045 ( .A(n3601), .B(n795), .Y(n794) );
NAND2X6TS U2046 ( .A(n774), .B(n772), .Y(n1024) );
INVX2TS U2047 ( .A(n1479), .Y(n774) );
INVX2TS U2048 ( .A(n1739), .Y(n1075) );
INVX2TS U2049 ( .A(n346), .Y(n1204) );
INVX4TS U2050 ( .A(n2013), .Y(n952) );
NAND3X6TS U2051 ( .A(n1092), .B(n1109), .C(n1408), .Y(n1108) );
NAND4X6TS U2052 ( .A(n950), .B(n949), .C(n951), .D(n948), .Y(n965) );
INVX6TS U2053 ( .A(n2139), .Y(n1031) );
INVX2TS U2054 ( .A(n3674), .Y(n687) );
INVX2TS U2055 ( .A(n3672), .Y(n680) );
NAND2X4TS U2056 ( .A(n2162), .B(n2161), .Y(n3040) );
NAND2X4TS U2057 ( .A(n701), .B(n2366), .Y(n1429) );
NAND2X4TS U2058 ( .A(n2367), .B(n2366), .Y(n1421) );
INVX2TS U2059 ( .A(n3175), .Y(n2752) );
INVX2TS U2060 ( .A(n2502), .Y(n1264) );
INVX4TS U2061 ( .A(n2503), .Y(n1265) );
NAND3X6TS U2062 ( .A(n440), .B(n1182), .C(n2854), .Y(n1138) );
INVX2TS U2063 ( .A(n3067), .Y(n2001) );
NOR2X4TS U2064 ( .A(n2007), .B(n2006), .Y(n3169) );
INVX12TS U2065 ( .A(Sgf_operation_Result[5]), .Y(n1815) );
INVX2TS U2066 ( .A(n3931), .Y(n1018) );
NOR2X4TS U2067 ( .A(FS_Module_state_reg[0]), .B(n1089), .Y(n3190) );
NAND2X4TS U2068 ( .A(n2253), .B(n3394), .Y(n1361) );
INVX2TS U2069 ( .A(n2444), .Y(n1142) );
INVX2TS U2070 ( .A(n602), .Y(n1275) );
NAND2X4TS U2071 ( .A(n2984), .B(add_x_19_n178), .Y(add_x_19_n176) );
INVX2TS U2072 ( .A(n3154), .Y(n1260) );
XOR2X1TS U2073 ( .A(n3153), .B(n3158), .Y(n3850) );
NOR2X2TS U2074 ( .A(n3711), .B(n3128), .Y(n1176) );
AOI2BB2X2TS U2075 ( .B0(n3391), .B1(n245), .A0N(n901), .A1N(n3956), .Y(n3355) );
NAND3X2TS U2076 ( .A(n2591), .B(n2590), .C(n2589), .Y(n193) );
NOR2BX1TS U2077 ( .AN(n4022), .B(n618), .Y(n1211) );
INVX2TS U2078 ( .A(n1460), .Y(n1427) );
INVX2TS U2079 ( .A(n836), .Y(n691) );
NAND2X6TS U2080 ( .A(n775), .B(n1124), .Y(n1858) );
INVX2TS U2081 ( .A(n587), .Y(n1036) );
INVX2TS U2082 ( .A(n600), .Y(n1791) );
INVX2TS U2083 ( .A(n1002), .Y(n1000) );
AND2X6TS U2084 ( .A(DP_OP_111J16_123_4462_n620), .B(n695), .Y(n1291) );
NAND2X2TS U2085 ( .A(n1461), .B(n1195), .Y(n1947) );
INVX6TS U2086 ( .A(n2190), .Y(n956) );
NAND2X2TS U2087 ( .A(n1511), .B(n3656), .Y(n797) );
OAI22X2TS U2088 ( .A0(n698), .A1(n1603), .B0(n865), .B1(n1613), .Y(n1619) );
INVX6TS U2089 ( .A(n2140), .Y(n2146) );
INVX6TS U2090 ( .A(n1834), .Y(n748) );
INVX2TS U2091 ( .A(n1078), .Y(n2155) );
OAI22X2TS U2092 ( .A0(n995), .A1(n881), .B0(n916), .B1(n1445), .Y(n1592) );
INVX2TS U2093 ( .A(n2054), .Y(n989) );
INVX2TS U2094 ( .A(n991), .Y(n990) );
INVX6TS U2095 ( .A(n2257), .Y(n2238) );
INVX2TS U2096 ( .A(n2176), .Y(n2177) );
NAND2X2TS U2097 ( .A(n2656), .B(n3574), .Y(n2600) );
INVX4TS U2098 ( .A(n933), .Y(n932) );
INVX2TS U2099 ( .A(n1369), .Y(n1368) );
INVX2TS U2100 ( .A(n2301), .Y(n2296) );
OAI22X2TS U2101 ( .A0(n1601), .A1(n1678), .B0(n2485), .B1(n1677), .Y(n2430)
);
INVX6TS U2102 ( .A(n1409), .Y(n2973) );
INVX8TS U2103 ( .A(Sgf_operation_EVEN1_Q_left[4]), .Y(n1812) );
NOR2X4TS U2104 ( .A(n1160), .B(n591), .Y(n1228) );
INVX2TS U2105 ( .A(n2993), .Y(n2969) );
NOR2X2TS U2106 ( .A(n2326), .B(n2346), .Y(n2329) );
INVX2TS U2107 ( .A(n632), .Y(n1869) );
NAND2X4TS U2108 ( .A(add_x_19_n272), .B(n1129), .Y(n1128) );
INVX2TS U2109 ( .A(n3428), .Y(n3429) );
NAND2X4TS U2110 ( .A(n2458), .B(n2457), .Y(n2939) );
NAND2X6TS U2111 ( .A(n2361), .B(n2360), .Y(n2801) );
INVX4TS U2112 ( .A(n1768), .Y(n1200) );
INVX4TS U2113 ( .A(n1769), .Y(n1199) );
INVX3TS U2114 ( .A(n327), .Y(n2857) );
NOR2X6TS U2115 ( .A(n1695), .B(n1694), .Y(n2905) );
NOR2X6TS U2116 ( .A(n2392), .B(n2391), .Y(n2926) );
CLKINVX6TS U2117 ( .A(n2908), .Y(n1236) );
OAI21X2TS U2118 ( .A0(n1738), .A1(n1739), .B0(n1737), .Y(n1254) );
INVX2TS U2119 ( .A(n3690), .Y(n1795) );
NAND2X1TS U2120 ( .A(n2973), .B(n2972), .Y(n2974) );
INVX4TS U2121 ( .A(n1812), .Y(n802) );
INVX2TS U2122 ( .A(add_x_19_n51), .Y(n1780) );
NOR2X6TS U2123 ( .A(n2216), .B(n2215), .Y(n3451) );
INVX2TS U2124 ( .A(n358), .Y(n1205) );
OAI22X2TS U2125 ( .A0(n2754), .A1(n1071), .B0(n3177), .B1(n881), .Y(n3174)
);
INVX4TS U2126 ( .A(n3468), .Y(n3494) );
NOR2X1TS U2127 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n1207) );
INVX4TS U2128 ( .A(n2822), .Y(n2681) );
BUFX8TS U2129 ( .A(n1091), .Y(n927) );
INVX2TS U2130 ( .A(n3190), .Y(n3191) );
NAND2X1TS U2131 ( .A(n952), .B(n1173), .Y(n3064) );
INVX2TS U2132 ( .A(n3133), .Y(n3864) );
INVX2TS U2133 ( .A(n1340), .Y(n1339) );
NOR2BX1TS U2134 ( .AN(n4021), .B(n634), .Y(n1340) );
OAI21X2TS U2135 ( .A0(n920), .A1(n843), .B0(n922), .Y(n286) );
NOR2X2TS U2136 ( .A(n477), .B(n3437), .Y(n921) );
OAI21X2TS U2137 ( .A0(n1015), .A1(n443), .B0(n1014), .Y(n285) );
MXI2X2TS U2138 ( .A(n3463), .B(n3910), .S0(n3559), .Y(n281) );
INVX2TS U2139 ( .A(n2852), .Y(Sgf_operation_EVEN1_right_N0) );
INVX6TS U2140 ( .A(n1779), .Y(mult_x_55_n59) );
CLKMX2X2TS U2141 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n879), .Y(n335) );
XOR2X1TS U2142 ( .A(mult_x_55_n565), .B(n354), .Y(n3614) );
XOR2X1TS U2143 ( .A(n1174), .B(n3629), .Y(n3646) );
CLKMX2X2TS U2144 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n879), .Y(n336) );
XOR2X1TS U2145 ( .A(n3121), .B(n3120), .Y(n3840) );
NAND2X1TS U2146 ( .A(n3148), .B(n3147), .Y(n3120) );
AOI2BB2X2TS U2147 ( .B0(n3391), .B1(n247), .A0N(n901), .A1N(n3953), .Y(n3270) );
XOR2X1TS U2148 ( .A(n2948), .B(n2947), .Y(Sgf_operation_EVEN1_left_N2) );
MXI2X2TS U2149 ( .A(n3464), .B(n3902), .S0(n3559), .Y(n273) );
NAND2X4TS U2150 ( .A(n3094), .B(n3079), .Y(n1028) );
INVX3TS U2151 ( .A(mult_x_55_a_8_), .Y(n3622) );
XOR2X1TS U2152 ( .A(mult_x_55_n567), .B(n3622), .Y(n3623) );
INVX3TS U2153 ( .A(mult_x_55_n565), .Y(n3630) );
XOR2X1TS U2154 ( .A(n354), .B(mult_x_55_n566), .Y(n3633) );
INVX3TS U2155 ( .A(n313), .Y(n3641) );
INVX4TS U2156 ( .A(n316), .Y(n3629) );
INVX4TS U2157 ( .A(n2728), .Y(n1979) );
INVX3TS U2158 ( .A(n877), .Y(n870) );
INVX3TS U2159 ( .A(n877), .Y(n869) );
NAND2X2TS U2160 ( .A(n2920), .B(mult_x_23_n81), .Y(mult_x_23_n13) );
NAND2X2TS U2161 ( .A(n3013), .B(add_x_19_n185), .Y(add_x_19_n14) );
INVX2TS U2162 ( .A(n3011), .Y(add_x_19_n168) );
CLKBUFX3TS U2163 ( .A(n3975), .Y(n3790) );
INVX8TS U2164 ( .A(add_x_19_n185), .Y(n2988) );
CLKBUFX2TS U2165 ( .A(n3973), .Y(n3793) );
OAI21X2TS U2166 ( .A0(add_x_19_n271), .A1(n1041), .B0(n1040), .Y(
add_x_19_n232) );
NAND2X2TS U2167 ( .A(n3049), .B(n3052), .Y(n1041) );
OAI2BB1X2TS U2168 ( .A0N(n3131), .A1N(n1337), .B0(n3132), .Y(n3846) );
NOR2X2TS U2169 ( .A(n3133), .B(n3156), .Y(n1337) );
BUFX3TS U2170 ( .A(n874), .Y(n3978) );
XOR2X1TS U2171 ( .A(n3146), .B(n3145), .Y(n3873) );
INVX2TS U2172 ( .A(n3142), .Y(n3144) );
INVX2TS U2173 ( .A(n3838), .Y(n3874) );
INVX2TS U2174 ( .A(n3080), .Y(DP_OP_111J16_123_4462_n39) );
INVX2TS U2175 ( .A(n3088), .Y(DP_OP_111J16_123_4462_n219) );
NAND2X4TS U2176 ( .A(n3087), .B(n1073), .Y(DP_OP_111J16_123_4462_n58) );
INVX6TS U2177 ( .A(n497), .Y(DP_OP_111J16_123_4462_n106) );
NAND2X2TS U2178 ( .A(n3087), .B(DP_OP_111J16_123_4462_n72), .Y(
DP_OP_111J16_123_4462_n10) );
XOR2X1TS U2179 ( .A(n3189), .B(n3188), .Y(Sgf_operation_EVEN1_middle_N2) );
AND2X4TS U2180 ( .A(n2763), .B(n1376), .Y(Sgf_operation_EVEN1_right_N1) );
XOR2X1TS U2181 ( .A(n3173), .B(n3172), .Y(Sgf_operation_EVEN1_middle_N4) );
BUFX3TS U2182 ( .A(n873), .Y(n4064) );
INVX2TS U2183 ( .A(Data_MX[15]), .Y(n2863) );
INVX2TS U2184 ( .A(n877), .Y(n871) );
BUFX3TS U2185 ( .A(n4061), .Y(n4065) );
BUFX3TS U2186 ( .A(n3972), .Y(n4059) );
BUFX3TS U2187 ( .A(n4060), .Y(n4061) );
BUFX3TS U2188 ( .A(n3978), .Y(n3649) );
INVX2TS U2189 ( .A(rst), .Y(n875) );
NOR2X4TS U2190 ( .A(n970), .B(n969), .Y(n968) );
NAND2X2TS U2191 ( .A(n3342), .B(n3375), .Y(n3344) );
INVX2TS U2192 ( .A(rst), .Y(n4072) );
INVX2TS U2193 ( .A(n1387), .Y(n1386) );
NOR2BX1TS U2194 ( .AN(n4019), .B(n634), .Y(n1387) );
INVX2TS U2195 ( .A(rst), .Y(n876) );
MX2X4TS U2196 ( .A(Data_MY[3]), .B(mult_x_55_n536), .S0(n746), .Y(n315) );
INVX2TS U2197 ( .A(n877), .Y(n872) );
CLKBUFX3TS U2198 ( .A(n4072), .Y(n4056) );
INVX2TS U2199 ( .A(n3449), .Y(n3425) );
AND2X2TS U2200 ( .A(n3413), .B(n3557), .Y(n974) );
AOI21X2TS U2201 ( .A0(n3217), .A1(Sgf_normalized_result[5]), .B0(n3207), .Y(
n1222) );
BUFX3TS U2202 ( .A(n3979), .Y(n3878) );
CLKBUFX3TS U2203 ( .A(n3879), .Y(n4063) );
OR2X2TS U2204 ( .A(n3930), .B(FS_Module_state_reg[2]), .Y(n731) );
XOR2X2TS U2205 ( .A(n2838), .B(n2837), .Y(Sgf_operation_EVEN1_right_N4) );
NAND2X2TS U2206 ( .A(n689), .B(n2795), .Y(mult_x_55_n17) );
XOR2X2TS U2207 ( .A(n1066), .B(n1093), .Y(n2026) );
AO22X4TS U2208 ( .A0(n2103), .A1(n3837), .B0(n1090), .B1(n880), .Y(n1584) );
XOR2X4TS U2209 ( .A(n1069), .B(n680), .Y(n679) );
INVX6TS U2210 ( .A(n3053), .Y(n1467) );
NOR2X8TS U2211 ( .A(n2205), .B(n2204), .Y(n3490) );
NAND2X4TS U2212 ( .A(n2205), .B(n2204), .Y(n3491) );
XOR2X4TS U2213 ( .A(n1873), .B(n684), .Y(n1867) );
XNOR2X4TS U2214 ( .A(n3053), .B(n925), .Y(n684) );
ADDFHX4TS U2215 ( .A(n2404), .B(n2403), .CI(n2402), .CO(n2405), .S(n2394) );
NAND2X4TS U2216 ( .A(n2049), .B(n2050), .Y(n2097) );
INVX6TS U2217 ( .A(n2098), .Y(n949) );
NOR2X4TS U2218 ( .A(n2336), .B(n2335), .Y(n2339) );
ADDHX4TS U2219 ( .A(n2005), .B(n2004), .CO(n2006), .S(n2000) );
OAI22X4TS U2220 ( .A0(n2106), .A1(n3888), .B0(n695), .B1(n1372), .Y(n2005)
);
ADDFHX4TS U2221 ( .A(n2120), .B(n2119), .CI(n2118), .CO(n2547), .S(n2127) );
OAI21X2TS U2222 ( .A0(n1750), .A1(n1749), .B0(n1748), .Y(n1378) );
INVX8TS U2223 ( .A(n2906), .Y(n1162) );
NOR2X6TS U2224 ( .A(n2906), .B(n2896), .Y(n2902) );
ADDFHX4TS U2225 ( .A(n1700), .B(n1699), .CI(n1698), .CO(n1749), .S(n1753) );
INVX6TS U2226 ( .A(n1215), .Y(n685) );
NAND2X4TS U2227 ( .A(n2363), .B(n2362), .Y(n2814) );
XOR2X4TS U2228 ( .A(n1272), .B(n3678), .Y(n706) );
CLKINVX1TS U2229 ( .A(n809), .Y(n1466) );
INVX8TS U2230 ( .A(n3057), .Y(n1859) );
INVX12TS U2231 ( .A(n2963), .Y(n1798) );
XNOR2X2TS U2232 ( .A(n2621), .B(mult_x_55_n531), .Y(n2654) );
XNOR2X4TS U2233 ( .A(n1793), .B(n687), .Y(n3053) );
CMPR22X2TS U2234 ( .A(n1935), .B(n1934), .CO(n1922), .S(n1939) );
OAI21X2TS U2235 ( .A0(n2355), .A1(n2356), .B0(n2354), .Y(n3455) );
NAND2X6TS U2236 ( .A(n2730), .B(n2729), .Y(n2816) );
XOR2X4TS U2237 ( .A(n688), .B(n823), .Y(n822) );
INVX6TS U2238 ( .A(n2955), .Y(n1876) );
AOI21X4TS U2239 ( .A0(n3624), .A1(n3591), .B0(n1788), .Y(n1789) );
AOI21X1TS U2240 ( .A0(n2142), .A1(n828), .B0(n1836), .Y(n692) );
AND2X6TS U2241 ( .A(n1833), .B(n1832), .Y(n828) );
OAI22X2TS U2242 ( .A0(n942), .A1(n1605), .B0(n2481), .B1(n1602), .Y(n1609)
);
INVX8TS U2243 ( .A(n929), .Y(n825) );
NAND2X2TS U2244 ( .A(n677), .B(n1848), .Y(n1124) );
ADDFHX2TS U2245 ( .A(n1620), .B(n1619), .CI(n1618), .CO(n2379), .S(n1621) );
XNOR2X4TS U2246 ( .A(n3661), .B(n3666), .Y(n1666) );
ADDFHX4TS U2247 ( .A(n1501), .B(n1503), .CI(n1502), .CO(n1533), .S(n1523) );
ADDFHX4TS U2248 ( .A(n1707), .B(n1706), .CI(n1705), .CO(n1747), .S(n1725) );
OAI22X4TS U2249 ( .A0(n942), .A1(mult_x_23_n472), .B0(n2481), .B1(n1702),
.Y(n1706) );
OAI2BB2X2TS U2250 ( .B0(n1161), .B1(n1943), .A0N(n837), .A1N(n2851), .Y(
n1956) );
XNOR2X4TS U2251 ( .A(n2463), .B(n3717), .Y(n2454) );
AO21X2TS U2252 ( .A0(n2659), .A1(n2655), .B0(n672), .Y(n1516) );
CLKXOR2X2TS U2253 ( .A(n672), .B(mult_x_55_n449), .Y(n2618) );
NAND2X6TS U2254 ( .A(n1697), .B(n1696), .Y(DP_OP_111J16_123_4462_n94) );
OAI22X4TS U2255 ( .A0(n2652), .A1(n1959), .B0(n863), .B1(mult_x_55_n494),
.Y(n1958) );
ADDFHX4TS U2256 ( .A(n1958), .B(n1957), .CI(n1956), .CO(n1951), .S(n2684) );
ADDFHX4TS U2257 ( .A(n1632), .B(n1631), .CI(n1630), .CO(n1638), .S(n1657) );
INVX2TS U2258 ( .A(n3893), .Y(n967) );
NAND2X8TS U2259 ( .A(n1253), .B(mult_x_23_n540), .Y(n698) );
XNOR2X4TS U2260 ( .A(n1948), .B(n3580), .Y(n699) );
OR2X8TS U2261 ( .A(n2368), .B(n427), .Y(n701) );
XNOR2X2TS U2262 ( .A(n1948), .B(mult_x_55_n449), .Y(n702) );
OR2X8TS U2263 ( .A(n1741), .B(n1740), .Y(n703) );
NOR2X4TS U2264 ( .A(n2035), .B(n2036), .Y(n1213) );
BUFX12TS U2265 ( .A(n3244), .Y(n3372) );
INVX4TS U2266 ( .A(n3372), .Y(n1391) );
CLKINVX6TS U2267 ( .A(n1330), .Y(n1329) );
OAI22X4TS U2268 ( .A0(n2490), .A1(n2489), .B0(n2488), .B1(n835), .Y(n2498)
);
XNOR2X2TS U2269 ( .A(n2453), .B(Op_MY[16]), .Y(n2464) );
NOR2X1TS U2270 ( .A(mult_x_55_n566), .B(mult_x_23_n550), .Y(n708) );
AND2X8TS U2271 ( .A(DP_OP_111J16_123_4462_n617), .B(
DP_OP_111J16_123_4462_n683), .Y(n709) );
XNOR2X4TS U2272 ( .A(n1197), .B(n1196), .Y(n710) );
OA21X4TS U2273 ( .A0(n3026), .A1(n3040), .B0(n3027), .Y(n711) );
OR2X8TS U2274 ( .A(n1881), .B(n1880), .Y(n712) );
XNOR2X4TS U2275 ( .A(n2653), .B(n3652), .Y(n713) );
OA22X4TS U2276 ( .A0(n444), .A1(n3339), .B0(n3372), .B1(n1331), .Y(n714) );
INVX8TS U2277 ( .A(n3508), .Y(n2850) );
OA21X4TS U2278 ( .A0(n2182), .A1(n800), .B0(n2183), .Y(n716) );
INVX2TS U2279 ( .A(n925), .Y(n2213) );
INVX4TS U2280 ( .A(n1152), .Y(mult_x_23_n127) );
NAND2X4TS U2281 ( .A(mult_x_23_n194), .B(n703), .Y(n1152) );
XNOR2X2TS U2282 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n699), .Y(n2003) );
NAND2X4TS U2283 ( .A(n1841), .B(n1842), .Y(n2158) );
INVX2TS U2284 ( .A(n2178), .Y(n2173) );
AND2X8TS U2285 ( .A(mult_x_23_n65), .B(n2932), .Y(n725) );
NOR2X4TS U2286 ( .A(n2867), .B(n2866), .Y(n2901) );
INVX6TS U2287 ( .A(n2901), .Y(mult_x_23_n194) );
AND2X8TS U2288 ( .A(n1146), .B(n721), .Y(n728) );
NAND2X2TS U2289 ( .A(n2470), .B(n2469), .Y(n2853) );
XNOR2X1TS U2290 ( .A(mult_x_55_a_0_), .B(n356), .Y(n730) );
OR2X4TS U2291 ( .A(n2195), .B(n2194), .Y(n736) );
AO21X2TS U2292 ( .A0(n3830), .A1(n3863), .B0(n1469), .Y(n738) );
INVX4TS U2293 ( .A(n2865), .Y(n1263) );
INVX2TS U2294 ( .A(n3031), .Y(n1383) );
INVX2TS U2295 ( .A(n3821), .Y(n3156) );
INVX2TS U2296 ( .A(n1472), .Y(n2312) );
XNOR2X2TS U2297 ( .A(n1853), .B(DP_OP_111J16_123_4462_n18), .Y(n1847) );
INVX2TS U2298 ( .A(n877), .Y(n874) );
INVX2TS U2299 ( .A(n877), .Y(n873) );
BUFX3TS U2300 ( .A(n4067), .Y(n4060) );
BUFX3TS U2301 ( .A(n4067), .Y(n4062) );
BUFX3TS U2302 ( .A(n3979), .Y(n3877) );
BUFX3TS U2303 ( .A(n3979), .Y(n3876) );
BUFX3TS U2304 ( .A(n4064), .Y(n908) );
CLKBUFX2TS U2305 ( .A(n3973), .Y(n3794) );
CLKBUFX3TS U2306 ( .A(n3975), .Y(n3792) );
CLKINVX12TS U2307 ( .A(Sgf_operation_EVEN1_Q_left[2]), .Y(n1804) );
OAI21X4TS U2308 ( .A0(n2199), .A1(n747), .B0(n2200), .Y(n1113) );
NAND2X8TS U2309 ( .A(n749), .B(n748), .Y(n2142) );
OAI22X4TS U2310 ( .A0(n1542), .A1(n700), .B0(n853), .B1(n750), .Y(n1538) );
OAI22X4TS U2311 ( .A0(n1497), .A1(n853), .B0(n700), .B1(n750), .Y(n1501) );
XNOR2X4TS U2312 ( .A(n1168), .B(mult_x_55_n535), .Y(n750) );
INVX8TS U2313 ( .A(Sgf_operation_Result[8]), .Y(n1831) );
INVX6TS U2314 ( .A(n3065), .Y(n751) );
NAND2X8TS U2315 ( .A(n753), .B(n752), .Y(n981) );
NAND2X8TS U2316 ( .A(n751), .B(n3063), .Y(n752) );
OAI21X4TS U2317 ( .A0(n3172), .A1(n3169), .B0(n3170), .Y(n3065) );
NAND3X6TS U2318 ( .A(n952), .B(n1173), .C(n3063), .Y(n753) );
NAND2X6TS U2319 ( .A(n2013), .B(n2012), .Y(n3063) );
XNOR2X4TS U2320 ( .A(n886), .B(n1066), .Y(n2009) );
NOR2X8TS U2321 ( .A(n1072), .B(n681), .Y(n2152) );
NAND2X8TS U2322 ( .A(n1132), .B(n716), .Y(n754) );
OAI21X4TS U2323 ( .A0(n796), .A1(n810), .B0(n2169), .Y(n2172) );
NAND2XLTS U2324 ( .A(n756), .B(n2814), .Y(mult_x_55_n13) );
NOR2X1TS U2325 ( .A(n672), .B(n894), .Y(n2620) );
OAI21X4TS U2326 ( .A0(n745), .A1(n758), .B0(n757), .Y(n312) );
NOR2X8TS U2327 ( .A(n761), .B(n760), .Y(n759) );
NAND2X8TS U2328 ( .A(n985), .B(n763), .Y(n762) );
AND2X8TS U2329 ( .A(n1478), .B(mult_x_55_n555), .Y(n764) );
AOI21X4TS U2330 ( .A0(n1245), .A1(n769), .B0(n766), .Y(n765) );
AND2X8TS U2331 ( .A(n2728), .B(n769), .Y(n768) );
NOR2X6TS U2332 ( .A(n2733), .B(n1246), .Y(n2728) );
NOR2X6TS U2333 ( .A(n2815), .B(n2808), .Y(n769) );
NOR2X8TS U2334 ( .A(n2730), .B(n2729), .Y(n2815) );
NOR2X8TS U2335 ( .A(n2732), .B(n2731), .Y(n2808) );
NOR2X8TS U2336 ( .A(n2703), .B(n2702), .Y(n2811) );
INVX4TS U2337 ( .A(n744), .Y(n772) );
AOI2BB1X4TS U2338 ( .A0N(n2780), .A1N(n2776), .B0(n773), .Y(n780) );
XNOR2X4TS U2339 ( .A(n3573), .B(Op_MY[11]), .Y(n1479) );
OAI21X4TS U2340 ( .A0(n1845), .A1(n1336), .B0(n776), .Y(n775) );
NOR2X6TS U2341 ( .A(n778), .B(n777), .Y(n776) );
NAND2X8TS U2342 ( .A(n779), .B(n1119), .Y(n1845) );
NAND2X8TS U2343 ( .A(n781), .B(n780), .Y(n1009) );
NAND2X8TS U2344 ( .A(mult_x_55_n95), .B(n2760), .Y(n781) );
NOR2X8TS U2345 ( .A(n2796), .B(n2780), .Y(n2760) );
NOR2X8TS U2346 ( .A(n2364), .B(n2365), .Y(n2796) );
NAND2X8TS U2347 ( .A(n670), .B(n2814), .Y(mult_x_55_n95) );
XNOR2X4TS U2348 ( .A(Op_MY[11]), .B(n3574), .Y(n1504) );
NOR3X1TS U2349 ( .A(Op_MY[23]), .B(Op_MY[24]), .C(Op_MY[11]), .Y(n3534) );
XOR2X4TS U2350 ( .A(n1168), .B(n782), .Y(n2789) );
OAI21X4TS U2351 ( .A0(n746), .A1(n784), .B0(n783), .Y(n323) );
OAI21X4TS U2352 ( .A0(n2542), .A1(n399), .B0(n2541), .Y(n909) );
XOR2X4TS U2353 ( .A(n991), .B(n2054), .Y(n785) );
OAI2BB1X4TS U2354 ( .A0N(n433), .A1N(n1596), .B0(n787), .Y(n1585) );
OAI21X4TS U2355 ( .A0(n433), .A1(n1596), .B0(n788), .Y(n787) );
XOR2X4TS U2356 ( .A(n788), .B(n789), .Y(n1632) );
OAI22X4TS U2357 ( .A0(n916), .A1(n881), .B0(n3889), .B1(n1445), .Y(n788) );
XOR2X4TS U2358 ( .A(n433), .B(n1596), .Y(n789) );
NAND2X8TS U2359 ( .A(n792), .B(n1086), .Y(n1902) );
NAND2BX4TS U2360 ( .AN(DP_OP_111J16_123_4462_n89), .B(
DP_OP_111J16_123_4462_n94), .Y(DP_OP_111J16_123_4462_n12) );
NOR2X8TS U2361 ( .A(n1697), .B(n1696), .Y(DP_OP_111J16_123_4462_n89) );
INVX3TS U2362 ( .A(add_x_19_n132), .Y(add_x_19_n130) );
NAND2X8TS U2363 ( .A(n2990), .B(n2989), .Y(add_x_19_n132) );
XOR2X4TS U2364 ( .A(n794), .B(n793), .Y(n2148) );
AOI2BB2X4TS U2365 ( .B0(n3590), .B1(n3624), .A0N(n3600), .A1N(n632), .Y(n795) );
NOR2X8TS U2366 ( .A(n2165), .B(n796), .Y(n2176) );
NOR2X8TS U2367 ( .A(n1820), .B(n1819), .Y(n796) );
NOR2X4TS U2368 ( .A(n1511), .B(n3656), .Y(n798) );
XOR2X4TS U2369 ( .A(n1098), .B(n799), .Y(n1967) );
NAND2X4TS U2370 ( .A(n1102), .B(n2173), .Y(n801) );
AO21X4TS U2371 ( .A0(n2661), .A1(n1518), .B0(n803), .Y(n1936) );
XOR2X4TS U2372 ( .A(n1803), .B(Sgf_operation_EVEN1_Q_middle[1]), .Y(n804) );
MXI2X4TS U2373 ( .A(n3981), .B(n3896), .S0(FSM_selector_A), .Y(n2256) );
BUFX12TS U2374 ( .A(mult_x_55_n557), .Y(n2647) );
NAND2XLTS U2375 ( .A(n2191), .B(n2190), .Y(n2193) );
NAND2X4TS U2376 ( .A(n1105), .B(n3099), .Y(n2052) );
INVX12TS U2377 ( .A(n1276), .Y(n1898) );
ADDFHX4TS U2378 ( .A(n1676), .B(n1675), .CI(n1674), .CO(n2433), .S(n2435) );
OAI22X2TS U2379 ( .A0(n1597), .A1(n856), .B0(n1579), .B1(n899), .Y(n1627) );
XOR2X4TS U2380 ( .A(n2412), .B(n825), .Y(n1597) );
NOR2X2TS U2381 ( .A(n3140), .B(n3139), .Y(n3141) );
XOR2X2TS U2382 ( .A(mult_x_55_a_8_), .B(n1475), .Y(n3139) );
BUFX12TS U2383 ( .A(n3661), .Y(n1153) );
INVX8TS U2384 ( .A(n1116), .Y(n1456) );
XNOR2X4TS U2385 ( .A(n1948), .B(mult_x_55_n444), .Y(n1505) );
BUFX20TS U2386 ( .A(n1898), .Y(n1092) );
OAI21X4TS U2387 ( .A0(n2244), .A1(n2291), .B0(n2243), .Y(n2245) );
NOR2X4TS U2388 ( .A(n2242), .B(n2260), .Y(n2244) );
XOR2X2TS U2389 ( .A(n1872), .B(n3807), .Y(n1877) );
XOR2X4TS U2390 ( .A(n1854), .B(n3818), .Y(n1855) );
INVX8TS U2391 ( .A(n2962), .Y(n1856) );
OAI22X4TS U2392 ( .A0(n698), .A1(n1708), .B0(mult_x_23_n540), .B1(
mult_x_23_n459), .Y(n1699) );
AND2X8TS U2393 ( .A(n1123), .B(n1114), .Y(n809) );
OAI22X4TS U2394 ( .A0(n1636), .A1(n859), .B0(n1595), .B1(n897), .Y(n1642) );
OAI22X2TS U2395 ( .A0(n2626), .A1(n1963), .B0(n2647), .B1(mult_x_55_n506),
.Y(n2687) );
MXI2X4TS U2396 ( .A(n3460), .B(n3962), .S0(n3510), .Y(n271) );
ADDHX4TS U2397 ( .A(n2635), .B(n2634), .CO(n2636), .S(n2630) );
AOI21X2TS U2398 ( .A0(n435), .A1(n3483), .B0(n3482), .Y(n3488) );
ADDFHX2TS U2399 ( .A(n2512), .B(n2511), .CI(n2510), .CO(n1737), .S(n2521) );
BUFX20TS U2400 ( .A(DP_OP_111J16_123_4462_n699), .Y(n1077) );
NOR2X6TS U2401 ( .A(n3360), .B(n3226), .Y(n3389) );
OR2X6TS U2402 ( .A(n3360), .B(FSM_selector_C), .Y(n3262) );
BUFX12TS U2403 ( .A(n3389), .Y(n1350) );
ADDFHX2TS U2404 ( .A(n1776), .B(n1775), .CI(n1774), .CO(n2786), .S(n1771) );
CLKINVX12TS U2405 ( .A(n3612), .Y(n1948) );
BUFX12TS U2406 ( .A(n1930), .Y(n813) );
NAND2X2TS U2407 ( .A(n1859), .B(n820), .Y(n1400) );
OAI22X4TS U2408 ( .A0(n852), .A1(n1927), .B0(n700), .B1(n1513), .Y(n1937) );
OAI22X4TS U2409 ( .A0(n2069), .A1(n884), .B0(n1653), .B1(n866), .Y(n2530) );
ADDFHX2TS U2410 ( .A(Sgf_operation_EVEN1_Q_middle[5]), .B(n1814), .CI(n1815),
.S(n814) );
OAI21X4TS U2411 ( .A0(n812), .A1(n2796), .B0(n2776), .Y(mult_x_55_n88) );
NAND2X4TS U2412 ( .A(n1051), .B(n1847), .Y(n2222) );
ADDFHX2TS U2413 ( .A(n3743), .B(n1681), .CI(n1680), .CO(n2428), .S(n1682) );
ADDFHX2TS U2414 ( .A(mult_x_23_n524), .B(n3743), .CI(n1679), .CO(n1610), .S(
n2429) );
NAND2X4TS U2415 ( .A(n1823), .B(n1824), .Y(n2183) );
AOI21X2TS U2416 ( .A0(n1779), .A1(n2798), .B0(n2805), .Y(mult_x_55_n48) );
ADDHX4TS U2417 ( .A(n2111), .B(n2112), .CO(n2102), .S(n2119) );
OAI22X4TS U2418 ( .A0(n2086), .A1(n857), .B0(n2085), .B1(n2411), .Y(n2112)
);
XNOR2X2TS U2419 ( .A(n887), .B(n1066), .Y(n2086) );
NAND2X4TS U2420 ( .A(n2731), .B(n2732), .Y(n2809) );
NOR2X4TS U2421 ( .A(n3093), .B(DP_OP_111J16_123_4462_n89), .Y(
DP_OP_111J16_123_4462_n82) );
INVX4TS U2422 ( .A(n2826), .Y(n2828) );
AO22X2TS U2423 ( .A0(n462), .A1(n2601), .B0(n2660), .B1(n394), .Y(n2676) );
NAND2X4TS U2424 ( .A(n814), .B(n1819), .Y(n2169) );
XOR2X4TS U2425 ( .A(n962), .B(n963), .Y(Sgf_operation_EVEN1_middle_N9) );
AND2X4TS U2426 ( .A(n1864), .B(n953), .Y(n821) );
INVX12TS U2427 ( .A(n822), .Y(n1565) );
XOR2X2TS U2428 ( .A(n3828), .B(n3827), .Y(n824) );
ADDFHX4TS U2429 ( .A(n2536), .B(n2537), .CI(n2535), .CO(n2575), .S(n2533) );
OAI22X2TS U2430 ( .A0(n2079), .A1(DP_OP_111J16_123_4462_n680), .B0(n3886),
.B1(DP_OP_111J16_123_4462_n713), .Y(n2537) );
CLKINVX6TS U2431 ( .A(n1047), .Y(n826) );
ADDFHX4TS U2432 ( .A(Sgf_operation_EVEN1_Q_middle[9]), .B(n1829), .CI(n1828),
.S(n827) );
OAI22X2TS U2433 ( .A0(n1578), .A1(n858), .B0(n1581), .B1(n890), .Y(n1600) );
OAI21X2TS U2434 ( .A0(n2293), .A1(n2292), .B0(n2291), .Y(n2297) );
OAI22X2TS U2435 ( .A0(n2484), .A1(n2487), .B0(n2485), .B1(n1733), .Y(n2518)
);
OAI2BB1X4TS U2436 ( .A0N(n2917), .A1N(n830), .B0(n1314), .Y(n1170) );
OAI22X4TS U2437 ( .A0(DP_OP_111J16_123_4462_n680), .A1(n3886), .B0(n1994),
.B1(DP_OP_111J16_123_4462_n713), .Y(n1465) );
BUFX4TS U2438 ( .A(n1392), .Y(n1149) );
ADDFHX4TS U2439 ( .A(mult_x_55_n270), .B(n1544), .CI(n1543), .CO(n1548), .S(
n1528) );
XNOR2X4TS U2440 ( .A(mult_x_55_n531), .B(n832), .Y(n1512) );
CLKBUFX2TS U2441 ( .A(n2153), .Y(n1078) );
NAND2X8TS U2442 ( .A(n1082), .B(n1081), .Y(n2191) );
ADDFHX4TS U2443 ( .A(n1713), .B(n1715), .CI(n1714), .CO(n1750), .S(n1745) );
NAND2X2TS U2444 ( .A(n2168), .B(n755), .Y(n2166) );
ADDFHX4TS U2445 ( .A(n1944), .B(n1946), .CI(n1945), .CO(n1952), .S(n1965) );
ADDFHX2TS U2446 ( .A(n2515), .B(n2514), .CI(n2513), .CO(n2520), .S(n2522) );
BUFX8TS U2447 ( .A(n2655), .Y(n1161) );
ADDFHX2TS U2448 ( .A(n1536), .B(n1535), .CI(n1534), .CO(n1552), .S(n1556) );
CMPR22X2TS U2449 ( .A(n1961), .B(n1960), .CO(n1966), .S(n2692) );
OAI2BB1X1TS U2450 ( .A0N(n1092), .A1N(n1897), .B0(n1242), .Y(n1241) );
NOR2X4TS U2451 ( .A(n583), .B(n592), .Y(n1897) );
OAI22X4TS U2452 ( .A0(n1594), .A1(n861), .B0(n1577), .B1(n895), .Y(n1629) );
INVX6TS U2453 ( .A(n1217), .Y(n1216) );
OAI22X4TS U2454 ( .A0(n445), .A1(n2478), .B0(n2477), .B1(n2476), .Y(n2515)
);
XOR2X2TS U2455 ( .A(n2474), .B(Op_MY[16]), .Y(n2478) );
ADDHX4TS U2456 ( .A(n2042), .B(n2041), .CO(n2126), .S(n2039) );
XNOR2X4TS U2457 ( .A(n686), .B(DP_OP_111J16_123_4462_n607), .Y(n2043) );
NAND2X4TS U2458 ( .A(n2702), .B(n2703), .Y(n2812) );
INVX8TS U2459 ( .A(n2659), .Y(n2851) );
NAND2X6TS U2460 ( .A(n2739), .B(n2738), .Y(DP_OP_111J16_123_4462_n128) );
OAI22X2TS U2461 ( .A0(n2072), .A1(n858), .B0(n1647), .B1(n2411), .Y(n2538)
);
ADDFHX4TS U2462 ( .A(n1936), .B(n1937), .CI(n1938), .CO(n1975), .S(n1970) );
NAND2X8TS U2463 ( .A(n3086), .B(n3073), .Y(n2757) );
ADDFHX4TS U2464 ( .A(n2669), .B(n2670), .CI(n2668), .CO(n2698), .S(n2671) );
OR2X8TS U2465 ( .A(mult_x_23_a_0_), .B(mult_x_23_n549), .Y(n2490) );
NOR2X6TS U2466 ( .A(n2237), .B(n2254), .Y(n2306) );
NAND2X4TS U2467 ( .A(n1032), .B(n710), .Y(n1458) );
OAI22X2TS U2468 ( .A0(n445), .A1(mult_x_23_n492), .B0(n2477), .B1(n1667),
.Y(n1744) );
ADDFHX2TS U2469 ( .A(n1673), .B(n1672), .CI(n1671), .CO(n2436), .S(n1692) );
ADDFHX4TS U2470 ( .A(n2029), .B(n2028), .CI(n2027), .CO(n2038), .S(n2033) );
OAI22X4TS U2471 ( .A0(n2023), .A1(n866), .B0(n2016), .B1(n884), .Y(n2027) );
OAI22X2TS U2472 ( .A0(n2037), .A1(n866), .B0(n2023), .B1(n884), .Y(n2048) );
XOR2X4TS U2473 ( .A(n1169), .B(n3892), .Y(n2071) );
BUFX20TS U2474 ( .A(n1493), .Y(n2626) );
ADDFHX2TS U2475 ( .A(n1507), .B(n3656), .CI(n1506), .CO(n1529), .S(n1499) );
ADDFHX4TS U2476 ( .A(n2020), .B(n2019), .CI(n2018), .CO(n2021), .S(n2013) );
OAI22X4TS U2477 ( .A0(n2483), .A1(n2480), .B0(n2481), .B1(n1722), .Y(n2511)
);
OAI22X4TS U2478 ( .A0(n942), .A1(mult_x_23_n546), .B0(n2481), .B1(n1735),
.Y(n2472) );
INVX8TS U2479 ( .A(n1439), .Y(n1047) );
CLKINVX12TS U2480 ( .A(Sgf_operation_EVEN1_Q_left[8]), .Y(n1830) );
NAND2X4TS U2481 ( .A(n2527), .B(n2528), .Y(n2908) );
INVX8TS U2482 ( .A(n1394), .Y(n2989) );
XNOR2X4TS U2483 ( .A(n393), .B(n887), .Y(n2085) );
XNOR2X4TS U2484 ( .A(DP_OP_111J16_123_4462_n606), .B(n887), .Y(n2068) );
ADDFHX4TS U2485 ( .A(n1649), .B(n1650), .CI(n1648), .CO(n1656), .S(n2577) );
INVX12TS U2486 ( .A(n995), .Y(n2103) );
ADDFHX4TS U2487 ( .A(n1940), .B(n1941), .CI(n1939), .CO(n1971), .S(n1955) );
XOR2X4TS U2488 ( .A(n1801), .B(n3813), .Y(n1851) );
XNOR2X4TS U2489 ( .A(n3574), .B(mult_x_55_n532), .Y(n1931) );
ADDFHX4TS U2490 ( .A(n1747), .B(n1745), .CI(n1746), .CO(n2746), .S(n1751) );
NAND2X4TS U2491 ( .A(n3592), .B(n3624), .Y(n1325) );
ADDFHX4TS U2492 ( .A(n2540), .B(n2539), .CI(n2538), .CO(n2578), .S(n2574) );
NOR2X4TS U2493 ( .A(DP_OP_111J16_123_4462_n123), .B(n3083), .Y(
DP_OP_111J16_123_4462_n116) );
OAI22X4TS U2494 ( .A0(n2652), .A1(n1504), .B0(n2650), .B1(mult_x_55_n562),
.Y(n1535) );
AO22X4TS U2495 ( .A0(n462), .A1(n2621), .B0(n2620), .B1(n2851), .Y(n2761) );
AO22X4TS U2496 ( .A0(n462), .A1(n2619), .B0(n2618), .B1(n2851), .Y(n2762) );
INVX12TS U2497 ( .A(n1090), .Y(n1583) );
MXI2X4TS U2498 ( .A(n261), .B(Add_result[23]), .S0(FSM_selector_C), .Y(n3359) );
NAND2X2TS U2499 ( .A(n3360), .B(n3359), .Y(n3362) );
MX2X6TS U2500 ( .A(n3346), .B(n4017), .S0(n633), .Y(n261) );
NAND2X4TS U2501 ( .A(n988), .B(n987), .Y(n2531) );
ADDFHX2TS U2502 ( .A(n3667), .B(mult_x_23_n523), .CI(n1604), .CO(n1618), .S(
n1611) );
OAI2BB2X2TS U2503 ( .B0(n3668), .B1(n840), .A0N(n3737), .A1N(n1617), .Y(
n1604) );
ADDFHX2TS U2504 ( .A(n2530), .B(n2529), .CI(n2531), .CO(n2576), .S(n2721) );
INVX12TS U2505 ( .A(n1013), .Y(n2412) );
BUFX20TS U2506 ( .A(n2647), .Y(n844) );
OAI2BB2X2TS U2507 ( .B0(n2647), .B1(mult_x_55_n505), .A0N(n2645), .A1N(n3643), .Y(n1944) );
BUFX20TS U2508 ( .A(n1244), .Y(n847) );
OAI22X4TS U2509 ( .A0(n1020), .A1(n854), .B0(mult_x_55_n554), .B1(n1947),
.Y(n2686) );
OAI22X2TS U2510 ( .A0(n854), .A1(n891), .B0(n1194), .B1(n1020), .Y(n1775) );
INVX12TS U2511 ( .A(n849), .Y(n850) );
NOR2X2TS U2512 ( .A(mult_x_55_n559), .B(n4026), .Y(n1544) );
OAI22X4TS U2513 ( .A0(n2487), .A1(n2473), .B0(n729), .B1(n2486), .Y(n2494)
);
OAI22X2TS U2514 ( .A0(n445), .A1(n2474), .B0(n705), .B1(n2448), .Y(n2456) );
OAI22X2TS U2515 ( .A0(n445), .A1(n2460), .B0(n705), .B1(n2475), .Y(n2501) );
XOR2X4TS U2516 ( .A(n854), .B(mult_x_55_n535), .Y(n1517) );
XNOR2X4TS U2517 ( .A(n1948), .B(n3581), .Y(n1492) );
INVX16TS U2518 ( .A(n2108), .Y(n855) );
INVX16TS U2519 ( .A(n855), .Y(n856) );
OAI22X2TS U2520 ( .A0(n1582), .A1(n2108), .B0(n2110), .B1(n1093), .Y(n1985)
);
OAI22X2TS U2521 ( .A0(n2117), .A1(n859), .B0(n2116), .B1(n897), .Y(n2548) );
OAI22X4TS U2522 ( .A0(n2055), .A1(n897), .B0(n2061), .B1(n859), .Y(n2542) );
OAI22X4TS U2523 ( .A0(n1595), .A1(n1566), .B0(DP_OP_111J16_123_4462_n685),
.B1(n3890), .Y(n1590) );
INVX4TS U2524 ( .A(n2753), .Y(n860) );
NAND2X8TS U2525 ( .A(mult_x_55_n543), .B(n2650), .Y(n1476) );
OAI22X2TS U2526 ( .A0(n2652), .A1(mult_x_55_n562), .B0(n863), .B1(n2600),
.Y(n2608) );
OAI22X4TS U2527 ( .A0(n2652), .A1(mult_x_55_n494), .B0(n2650), .B1(n1931),
.Y(n1941) );
OAI22X2TS U2528 ( .A0(n2652), .A1(n2651), .B0(n863), .B1(n697), .Y(n2690) );
OAI22X2TS U2529 ( .A0(n2070), .A1(n884), .B0(n2069), .B1(n866), .Y(n2534) );
OAI22X2TS U2530 ( .A0(n1653), .A1(n2106), .B0(n695), .B1(n3888), .Y(n1650)
);
BUFX3TS U2531 ( .A(n870), .Y(n3879) );
NOR2X4TS U2532 ( .A(n3214), .B(n3926), .Y(n3216) );
NAND2X6TS U2533 ( .A(n2000), .B(n1999), .Y(n3067) );
OAI22X2TS U2534 ( .A0(n2003), .A1(n846), .B0(n1998), .B1(
DP_OP_111J16_123_4462_n680), .Y(n1999) );
XNOR2X4TS U2535 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n3516) );
BUFX3TS U2536 ( .A(n872), .Y(n3734) );
BUFX3TS U2537 ( .A(n871), .Y(n3880) );
BUFX3TS U2538 ( .A(n873), .Y(n3647) );
BUFX3TS U2539 ( .A(n3879), .Y(n3648) );
NAND2X4TS U2540 ( .A(n3322), .B(n1329), .Y(n3323) );
AOI21X2TS U2541 ( .A0(n3320), .A1(n882), .B0(n1344), .Y(n1343) );
AOI2BB2X4TS U2542 ( .B0(n3376), .B1(n3322), .A0N(n620), .A1N(n3340), .Y(
n1346) );
INVX4TS U2543 ( .A(n1206), .Y(n3376) );
NOR2X2TS U2544 ( .A(n883), .B(n3664), .Y(n2883) );
OAI22X2TS U2545 ( .A0(n883), .A1(n868), .B0(n3668), .B1(n3667), .Y(n1686) );
OAI2BB2X2TS U2546 ( .B0(n883), .B1(n3667), .A0N(n3742), .A1N(n455), .Y(n1670) );
XNOR2X4TS U2547 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n698), .Y(n2016) );
XNOR2X4TS U2548 ( .A(n885), .B(n1066), .Y(n1997) );
NAND2X2TS U2549 ( .A(n655), .B(n885), .Y(n1372) );
INVX16TS U2550 ( .A(n917), .Y(n886) );
INVX16TS U2551 ( .A(n1006), .Y(n887) );
OAI22X2TS U2552 ( .A0(n2483), .A1(n2482), .B0(n889), .B1(n2480), .Y(n2514)
);
OAI22X2TS U2553 ( .A0(n2483), .A1(n1722), .B0(n2481), .B1(mult_x_23_n472),
.Y(n1732) );
OAI22X2TS U2554 ( .A0(n852), .A1(n1542), .B0(n700), .B1(n1541), .Y(n1549) );
OAI22X4TS U2555 ( .A0(n853), .A1(n1928), .B0(n2842), .B1(n1927), .Y(n1929)
);
OAI22X4TS U2556 ( .A0(n2065), .A1(n2411), .B0(n2068), .B1(n858), .Y(n2078)
);
NOR2BX4TS U2557 ( .AN(n1066), .B(n2411), .Y(n2115) );
BUFX8TS U2558 ( .A(DP_OP_111J16_123_4462_n683), .Y(n2411) );
OAI22X2TS U2559 ( .A0(n2487), .A1(mult_x_23_n480), .B0(n2485), .B1(n1678),
.Y(n1680) );
OAI22X2TS U2560 ( .A0(n2487), .A1(n459), .B0(n729), .B1(n2462), .Y(n2492) );
OAI22X4TS U2561 ( .A0(n847), .A1(n1540), .B0(n891), .B1(n699), .Y(n1486) );
OAI22X2TS U2562 ( .A0(n744), .A1(mult_x_55_n480), .B0(n893), .B1(
mult_x_55_n479), .Y(n1502) );
INVX16TS U2563 ( .A(n2656), .Y(n894) );
OAI22X4TS U2564 ( .A0(n861), .A1(n2057), .B0(n2056), .B1(
DP_OP_111J16_123_4462_n682), .Y(n2066) );
INVX12TS U2565 ( .A(n896), .Y(n897) );
OAI22X4TS U2566 ( .A0(n2024), .A1(n897), .B0(n1566), .B1(n2015), .Y(n2028)
);
OAI22X4TS U2567 ( .A0(n856), .A1(n825), .B0(n2110), .B1(n2025), .Y(n2042) );
BUFX6TS U2568 ( .A(n3390), .Y(n900) );
AOI2BB2X2TS U2569 ( .B0(n3379), .B1(n248), .A0N(n901), .A1N(n3924), .Y(n3337) );
AOI2BB2X2TS U2570 ( .B0(n3379), .B1(n251), .A0N(n901), .A1N(n3921), .Y(n3366) );
AOI2BB2X2TS U2571 ( .B0(n3379), .B1(n255), .A0N(n902), .A1N(n3917), .Y(n3238) );
AOI2BB2X2TS U2572 ( .B0(n3379), .B1(n253), .A0N(n901), .A1N(n3919), .Y(n3381) );
AOI2BB2X2TS U2573 ( .B0(n3384), .B1(n256), .A0N(n902), .A1N(n3916), .Y(n3333) );
AOI2BB2X2TS U2574 ( .B0(n3379), .B1(n250), .A0N(n902), .A1N(n3922), .Y(n3289) );
OR2X4TS U2575 ( .A(n902), .B(n3918), .Y(n1351) );
AOI2BB2X2TS U2576 ( .B0(n3391), .B1(n258), .A0N(n902), .A1N(n3914), .Y(n3317) );
AOI2BB2X2TS U2577 ( .B0(n3379), .B1(n246), .A0N(n902), .A1N(n3955), .Y(n3259) );
AOI2BB2X2TS U2578 ( .B0(n3391), .B1(n260), .A0N(n900), .A1N(n3912), .Y(n3327) );
AOI2BB2X2TS U2579 ( .B0(n3384), .B1(n240), .A0N(n901), .A1N(n3240), .Y(n3242) );
NAND2X4TS U2580 ( .A(n3360), .B(n2587), .Y(n3390) );
AOI21X1TS U2581 ( .A0(n3802), .A1(n3131), .B0(n3130), .Y(n3132) );
CLKBUFX2TS U2582 ( .A(Add_result[10]), .Y(n903) );
CLKBUFX2TS U2583 ( .A(Add_result[12]), .Y(n904) );
OAI22X2TS U2584 ( .A0(n698), .A1(n2377), .B0(n865), .B1(n2387), .Y(n2390) );
CLKXOR2X2TS U2585 ( .A(n1904), .B(n3810), .Y(n1905) );
XOR2X4TS U2586 ( .A(n2453), .B(n3743), .Y(n2443) );
INVX2TS U2587 ( .A(n4016), .Y(n1328) );
NAND2X4TS U2588 ( .A(n3504), .B(n3503), .Y(n3505) );
XNOR2X2TS U2589 ( .A(n2193), .B(n2192), .Y(n3504) );
NAND2X2TS U2590 ( .A(Sgf_normalized_result[4]), .B(Sgf_normalized_result[5]),
.Y(n3213) );
AO22X2TS U2591 ( .A0(n3528), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[4]), .B1(n3526), .Y(n186) );
XNOR2X4TS U2592 ( .A(mult_x_55_n570), .B(mult_x_23_n554), .Y(n3136) );
OAI21X4TS U2593 ( .A0(n3799), .A1(n3801), .B0(n3831), .Y(n3830) );
XNOR2X2TS U2594 ( .A(mult_x_55_n566), .B(mult_x_23_n550), .Y(n3148) );
NAND3X2TS U2595 ( .A(n3331), .B(n3330), .C(n3329), .Y(n211) );
INVX2TS U2596 ( .A(rst), .Y(n906) );
OAI2BB1X4TS U2597 ( .A0N(n2542), .A1N(n399), .B0(n909), .Y(n2573) );
XOR2X4TS U2598 ( .A(n838), .B(n910), .Y(n2545) );
XOR2X4TS U2599 ( .A(n911), .B(n2542), .Y(n910) );
XOR2X4TS U2600 ( .A(n667), .B(n915), .Y(n2596) );
XOR2X4TS U2601 ( .A(n2551), .B(n2550), .Y(n915) );
XOR2X4TS U2602 ( .A(n1169), .B(n470), .Y(n2104) );
XOR2X4TS U2603 ( .A(n392), .B(n3886), .Y(n2011) );
INVX2TS U2604 ( .A(n2921), .Y(n919) );
AND2X8TS U2605 ( .A(n2503), .B(n2502), .Y(n2921) );
NAND2X4TS U2606 ( .A(n2559), .B(n2560), .Y(DP_OP_111J16_123_4462_n103) );
XNOR2X4TS U2607 ( .A(n926), .B(n3589), .Y(n925) );
AOI21X4TS U2608 ( .A0(n3624), .A1(n3608), .B0(n3609), .Y(n926) );
NOR2X8TS U2609 ( .A(n1865), .B(n1866), .Y(n2980) );
XOR2X4TS U2610 ( .A(n2824), .B(n928), .Y(Sgf_operation_EVEN1_right_N8) );
AOI21X4TS U2611 ( .A0(n927), .A1(n2821), .B0(n2820), .Y(n928) );
INVX12TS U2612 ( .A(n1064), .Y(n1090) );
OAI22X4TS U2613 ( .A0(n2075), .A1(n856), .B0(n899), .B1(n2074), .Y(n2081) );
XOR2X4TS U2614 ( .A(n1583), .B(n929), .Y(n2074) );
OAI2BB1X4TS U2615 ( .A0N(n931), .A1N(n1929), .B0(n930), .Y(n1972) );
NAND2BX4TS U2616 ( .AN(n813), .B(n932), .Y(n931) );
OAI22X4TS U2617 ( .A0(n1926), .A1(n2842), .B0(n852), .B1(n850), .Y(n933) );
NOR2X8TS U2618 ( .A(n668), .B(n2049), .Y(n2098) );
MXI2X8TS U2619 ( .A(n936), .B(n934), .S0(n3456), .Y(n3464) );
XNOR2X4TS U2620 ( .A(n935), .B(n2331), .Y(n934) );
AO21X4TS U2621 ( .A0(n2330), .A1(n2329), .B0(n2328), .Y(n935) );
XOR2X4TS U2622 ( .A(n937), .B(n2331), .Y(n936) );
AO21X4TS U2623 ( .A0(n2324), .A1(n2323), .B0(n2322), .Y(n937) );
MXI2X8TS U2624 ( .A(n938), .B(n2358), .S0(n3456), .Y(n3463) );
XNOR2X4TS U2625 ( .A(n3453), .B(n3454), .Y(n938) );
OAI2BB1X4TS U2626 ( .A0N(n3456), .A1N(n2268), .B0(n1361), .Y(n3467) );
OAI22X4TS U2627 ( .A0(n2074), .A1(n2108), .B0(n899), .B1(n2073), .Y(n2535)
);
XNOR2X4TS U2628 ( .A(n2090), .B(n686), .Y(n2073) );
NAND2X4TS U2629 ( .A(n2247), .B(n2263), .Y(n2274) );
OR2X8TS U2630 ( .A(n3909), .B(FSM_selector_B[1]), .Y(n1454) );
OAI21X4TS U2631 ( .A0(n497), .A1(n3088), .B0(DP_OP_111J16_123_4462_n103),
.Y(DP_OP_111J16_123_4462_n97) );
NAND2X8TS U2632 ( .A(n3738), .B(mult_x_23_n541), .Y(n2483) );
OAI2BB1X4TS U2633 ( .A0N(n943), .A1N(n2389), .B0(n944), .Y(n2887) );
XOR2X4TS U2634 ( .A(n945), .B(n2388), .Y(n2383) );
XOR2X4TS U2635 ( .A(n2390), .B(n2389), .Y(n945) );
NOR2BX4TS U2636 ( .AN(n2014), .B(n946), .Y(n2034) );
XOR2X4TS U2637 ( .A(n2014), .B(n947), .Y(n2019) );
OAI22X4TS U2638 ( .A0(n704), .A1(DP_OP_111J16_123_4462_n685), .B0(n1566),
.B1(n3890), .Y(n947) );
OAI21X4TS U2639 ( .A0(n981), .A1(n3101), .B0(n3102), .Y(n2099) );
OAI21X4TS U2640 ( .A0(n2186), .A1(n2188), .B0(n2187), .Y(n954) );
AND2X8TS U2641 ( .A(n955), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2186) );
XOR2X4TS U2642 ( .A(n1803), .B(Sgf_operation_EVEN1_Q_middle[1]), .Y(n955) );
AOI21X4TS U2643 ( .A0(n2191), .A1(n2192), .B0(n956), .Y(n2188) );
NAND3X8TS U2644 ( .A(n958), .B(n957), .C(n2158), .Y(n2220) );
NAND2X8TS U2645 ( .A(n673), .B(n720), .Y(n957) );
NAND2X8TS U2646 ( .A(n1056), .B(n720), .Y(n958) );
XNOR2X4TS U2647 ( .A(n1902), .B(n959), .Y(n1225) );
XNOR2X4TS U2648 ( .A(n1460), .B(n1903), .Y(n959) );
XOR2X4TS U2649 ( .A(n1241), .B(n3669), .Y(n1460) );
NAND2X8TS U2650 ( .A(n961), .B(n2477), .Y(n2479) );
XOR2X4TS U2651 ( .A(DP_OP_111J16_123_4462_n606), .B(n1093), .Y(n2109) );
XNOR2X4TS U2652 ( .A(n3889), .B(n1093), .Y(n1302) );
NAND2X2TS U2653 ( .A(n655), .B(n686), .Y(n2025) );
XOR2X2TS U2654 ( .A(n1565), .B(n825), .Y(n1646) );
XNOR2X4TS U2655 ( .A(n459), .B(n3675), .Y(n1710) );
NOR2X8TS U2656 ( .A(n1300), .B(n1299), .Y(n966) );
XNOR2X4TS U2657 ( .A(mult_x_23_n545), .B(n3675), .Y(n1664) );
OAI21X4TS U2658 ( .A0(n1992), .A1(n967), .B0(n1188), .Y(n1996) );
XOR2X4TS U2659 ( .A(n968), .B(n3751), .Y(n3231) );
NOR2BX4TS U2660 ( .AN(n1391), .B(n3230), .Y(n969) );
AO21X4TS U2661 ( .A0(n3229), .A1(n882), .B0(n3228), .Y(n970) );
OAI21X4TS U2662 ( .A0(n2584), .A1(n971), .B0(n1089), .Y(n3360) );
XOR2X4TS U2663 ( .A(n1100), .B(n1076), .Y(n2419) );
XOR2X4TS U2664 ( .A(n1090), .B(n1076), .Y(n1594) );
XNOR2X4TS U2665 ( .A(n2090), .B(n396), .Y(n1577) );
XNOR2X4TS U2666 ( .A(n1570), .B(n396), .Y(n2410) );
XOR2X4TS U2667 ( .A(n978), .B(n742), .Y(n2566) );
INVX12TS U2668 ( .A(n980), .Y(n1169) );
XOR2X4TS U2669 ( .A(DP_OP_111J16_123_4462_n728), .B(n836), .Y(n980) );
XOR2X4TS U2670 ( .A(n1970), .B(n1971), .Y(n1375) );
XOR2X1TS U2671 ( .A(n3104), .B(n981), .Y(Sgf_operation_EVEN1_middle_N6) );
XOR2X4TS U2672 ( .A(n982), .B(n2010), .Y(n2007) );
OAI22X4TS U2673 ( .A0(n2011), .A1(n846), .B0(n967), .B1(n2003), .Y(n2010) );
XOR2X4TS U2674 ( .A(n1295), .B(n1293), .Y(n982) );
XOR2X4TS U2675 ( .A(n1169), .B(n1076), .Y(n984) );
OAI22X4TS U2676 ( .A0(n2083), .A1(DP_OP_111J16_123_4462_n680), .B0(n2079),
.B1(n846), .Y(n986) );
XNOR2X4TS U2677 ( .A(n1570), .B(n1077), .Y(n2083) );
NAND2X8TS U2678 ( .A(n994), .B(n992), .Y(n991) );
NAND2BX4TS U2679 ( .AN(n1651), .B(n993), .Y(n992) );
NAND2BX4TS U2680 ( .AN(n1652), .B(n2753), .Y(n994) );
NAND2X4TS U2681 ( .A(DP_OP_111J16_123_4462_n792), .B(n1446), .Y(n996) );
XOR2X4TS U2682 ( .A(n996), .B(n997), .Y(n995) );
OAI2BB1X4TS U2683 ( .A0N(DP_OP_111J16_123_4462_n827), .A1N(n836), .B0(n727),
.Y(n997) );
OAI2BB1X4TS U2684 ( .A0N(n1000), .A1N(n1596), .B0(n1634), .Y(n999) );
XOR2X4TS U2685 ( .A(n1634), .B(n1001), .Y(n2572) );
XOR2X4TS U2686 ( .A(n1645), .B(n1002), .Y(n1001) );
XOR2X4TS U2687 ( .A(n2103), .B(n1076), .Y(n1005) );
OAI22X4TS U2688 ( .A0(n2072), .A1(n890), .B0(n858), .B1(n397), .Y(n2536) );
XOR2X4TS U2689 ( .A(n2103), .B(n1006), .Y(n2072) );
NAND2X8TS U2690 ( .A(n703), .B(n1257), .Y(n1256) );
OAI22X2TS U2691 ( .A0(n1601), .A1(n1710), .B0(n729), .B1(n1709), .Y(n1717)
);
OAI22X2TS U2692 ( .A0(n2487), .A1(n1733), .B0(n729), .B1(n1710), .Y(n1730)
);
NAND2X8TS U2693 ( .A(mult_x_55_n94), .B(n2760), .Y(n2799) );
NAND3X2TS U2694 ( .A(n3312), .B(n3311), .C(n3310), .Y(n209) );
XNOR2X4TS U2695 ( .A(n3043), .B(n3042), .Y(Sgf_operation_Result[22]) );
AOI21X4TS U2696 ( .A0(n3423), .A1(n2218), .B0(n2217), .Y(n2219) );
AOI21X2TS U2697 ( .A0(n882), .A1(n3304), .B0(n3303), .Y(n3305) );
AOI21X4TS U2698 ( .A0(n401), .A1(n2728), .B0(n1245), .Y(mult_x_55_n121) );
AOI21X4TS U2699 ( .A0(n401), .A1(n2779), .B0(n2734), .Y(mult_x_55_n130) );
NAND2X8TS U2700 ( .A(mult_x_55_n557), .B(mult_x_55_n544), .Y(n1493) );
NOR2X8TS U2701 ( .A(n2739), .B(n2738), .Y(DP_OP_111J16_123_4462_n123) );
XNOR2X4TS U2702 ( .A(n1576), .B(n1575), .Y(n1013) );
OAI22X4TS U2703 ( .A0(n1605), .A1(n2481), .B0(n942), .B1(n1019), .Y(n1676)
);
XNOR2X4TS U2704 ( .A(n3661), .B(n571), .Y(n1019) );
NOR2X8TS U2705 ( .A(n2715), .B(n2714), .Y(n2904) );
XOR2X4TS U2706 ( .A(n1022), .B(n1487), .Y(n1488) );
XOR2X4TS U2707 ( .A(n1026), .B(n1023), .Y(n1022) );
NAND2X8TS U2708 ( .A(n1025), .B(n1024), .Y(n1023) );
OR2X4TS U2709 ( .A(n518), .B(n893), .Y(n1025) );
OAI22X4TS U2710 ( .A0(n1492), .A1(n891), .B0(n699), .B1(n847), .Y(n1026) );
NAND2X8TS U2711 ( .A(n1214), .B(mult_x_55_n554), .Y(n1244) );
NOR2X8TS U2712 ( .A(n2560), .B(n2559), .Y(n3088) );
XOR2X4TS U2713 ( .A(n1845), .B(n1441), .Y(n1032) );
NAND2X1TS U2714 ( .A(n1033), .B(n1428), .Y(n2976) );
NAND2X8TS U2715 ( .A(n1039), .B(n711), .Y(add_x_19_n243) );
NAND2X8TS U2716 ( .A(n1042), .B(n2192), .Y(n3052) );
AND2X8TS U2717 ( .A(n3036), .B(n3007), .Y(n3049) );
XOR2X4TS U2718 ( .A(n1794), .B(n1043), .Y(n1799) );
XOR2X4TS U2719 ( .A(n1044), .B(n3682), .Y(n1394) );
NAND2BX4TS U2720 ( .AN(n3725), .B(n1045), .Y(n1044) );
OAI21X4TS U2721 ( .A0(n589), .A1(n663), .B0(n662), .Y(add_x_19_n141) );
NAND2BX4TS U2722 ( .AN(n1051), .B(n1048), .Y(n1439) );
XNOR2X4TS U2723 ( .A(n1058), .B(n1057), .Y(n1051) );
NAND2X8TS U2724 ( .A(n1049), .B(n1046), .Y(n1055) );
NAND2X8TS U2725 ( .A(n1392), .B(n1050), .Y(n1049) );
AND2X8TS U2726 ( .A(n2222), .B(n432), .Y(n1050) );
INVX12TS U2727 ( .A(n432), .Y(n1843) );
NAND2X8TS U2728 ( .A(n2220), .B(n1458), .Y(n1392) );
NAND2X4TS U2729 ( .A(n1837), .B(n1052), .Y(n2154) );
NOR2X8TS U2730 ( .A(n1052), .B(n1837), .Y(n2153) );
OAI2BB1X4TS U2731 ( .A0N(n3626), .A1N(n594), .B0(n1054), .Y(n1053) );
NAND2X8TS U2732 ( .A(n1055), .B(n2224), .Y(n1405) );
NAND2BX4TS U2733 ( .AN(n1123), .B(n1850), .Y(n2224) );
NOR2X4TS U2734 ( .A(n818), .B(n834), .Y(n2160) );
XOR2X4TS U2735 ( .A(n677), .B(n1848), .Y(n1057) );
AOI21X4TS U2736 ( .A0(n1845), .A1(n1335), .B0(n1336), .Y(n1058) );
OAI21X4TS U2737 ( .A0(n693), .A1(n694), .B0(n824), .Y(n1118) );
XOR2X4TS U2738 ( .A(n3827), .B(n3828), .Y(n1839) );
NOR2X8TS U2739 ( .A(n2178), .B(n2182), .Y(n1825) );
NOR2X8TS U2740 ( .A(n1824), .B(n1823), .Y(n2182) );
NOR2X8TS U2741 ( .A(n1822), .B(n1821), .Y(n2178) );
OAI21X4TS U2742 ( .A0(n3500), .A1(n3499), .B0(n3498), .Y(n377) );
NAND2X4TS U2743 ( .A(n2139), .B(n2138), .Y(n3078) );
NOR2X8TS U2744 ( .A(n2737), .B(n2736), .Y(n1065) );
OAI22X4TS U2745 ( .A0(n2056), .A1(n861), .B0(n1652), .B1(
DP_OP_111J16_123_4462_n682), .Y(n2060) );
OR2X8TS U2746 ( .A(n1999), .B(n2000), .Y(n3068) );
OAI22X2TS U2747 ( .A0(n884), .A1(n1997), .B0(n2002), .B1(n866), .Y(n2004) );
XNOR2X4TS U2748 ( .A(n1100), .B(n886), .Y(n1595) );
ADDFHX2TS U2749 ( .A(n868), .B(n1669), .CI(n1670), .CO(n1683), .S(n1742) );
NAND2X2TS U2750 ( .A(n2427), .B(n2426), .Y(n3072) );
XNOR2X2TS U2751 ( .A(n2453), .B(n571), .Y(n1736) );
OAI22X2TS U2752 ( .A0(n2490), .A1(n1736), .B0(n1734), .B1(n835), .Y(n2517)
);
XOR2X4TS U2753 ( .A(n1737), .B(n1075), .Y(n1255) );
XNOR2X4TS U2754 ( .A(n1858), .B(n1401), .Y(n1123) );
NAND2X2TS U2755 ( .A(n2917), .B(n2916), .Y(n2918) );
OAI22X4TS U2756 ( .A0(n1020), .A1(n1186), .B0(mult_x_55_n554), .B1(n1505),
.Y(n1503) );
OAI22X2TS U2757 ( .A0(n2117), .A1(n897), .B0(n2104), .B1(n859), .Y(n2129) );
XNOR2X2TS U2758 ( .A(n2474), .B(n2459), .Y(n2475) );
OAI22X2TS U2759 ( .A0(n2082), .A1(n884), .B0(n2070), .B1(n866), .Y(n2094) );
OAI22X2TS U2760 ( .A0(n1483), .A1(n893), .B0(n744), .B1(n1508), .Y(n1534) );
ADDFHX4TS U2761 ( .A(n2059), .B(n2060), .CI(n2058), .CO(n2053), .S(n2062) );
BUFX20TS U2762 ( .A(mult_x_55_n556), .Y(n2650) );
OAI22X4TS U2763 ( .A0(n2109), .A1(n2110), .B0(n2108), .B1(n2043), .Y(n2114)
);
OA22X2TS U2764 ( .A0(n2075), .A1(n2110), .B0(n1111), .B1(n2108), .Y(n1080)
);
NAND2X2TS U2765 ( .A(n2622), .B(n2617), .Y(n2769) );
AOI2BB2X4TS U2766 ( .B0(n462), .B1(n2618), .A0N(n2627), .A1N(n2659), .Y(
n2616) );
AO22X2TS U2767 ( .A0(n2661), .A1(n2602), .B0(n2601), .B1(n2851), .Y(n2607)
);
OAI22X4TS U2768 ( .A0(n2073), .A1(n856), .B0(n1646), .B1(n899), .Y(n2539) );
OAI22X4TS U2769 ( .A0(n847), .A1(n1932), .B0(n891), .B1(n1517), .Y(n1923) );
INVX12TS U2770 ( .A(n1802), .Y(n1082) );
ADDFHX4TS U2771 ( .A(n2693), .B(n2692), .CI(n2691), .CO(n2683), .S(n2694) );
XOR2X4TS U2772 ( .A(n1083), .B(n719), .Y(n2229) );
OAI21X4TS U2773 ( .A0(n3046), .A1(n3044), .B0(n3047), .Y(n2231) );
XOR2X4TS U2774 ( .A(n1084), .B(n2976), .Y(n1217) );
OAI21X4TS U2775 ( .A0(n821), .A1(n2980), .B0(n2981), .Y(n1084) );
CLKINVX12TS U2776 ( .A(mult_x_55_n72), .Y(n1201) );
NOR2X4TS U2777 ( .A(n3490), .B(n3469), .Y(n2209) );
XOR2X2TS U2778 ( .A(n2658), .B(n894), .Y(n2649) );
OAI22X2TS U2779 ( .A0(n1161), .A1(n713), .B0(n2654), .B1(n2659), .Y(n2689)
);
ADDFHX4TS U2780 ( .A(n2126), .B(n2124), .CI(n2125), .CO(n2131), .S(n2133) );
OAI2BB2X4TS U2781 ( .B0(n1924), .B1(n2655), .A0N(n1518), .A1N(n2851), .Y(
n1934) );
OAI22X2TS U2782 ( .A0(n2652), .A1(mult_x_55_n490), .B0(n2650), .B1(n1504),
.Y(n1539) );
OAI22X4TS U2783 ( .A0(n770), .A1(n2648), .B0(n1962), .B1(mult_x_55_n555),
.Y(n2643) );
XOR2X4TS U2784 ( .A(n2658), .B(mult_x_55_n538), .Y(n2648) );
OAI22X4TS U2785 ( .A0(n770), .A1(n1962), .B0(n1942), .B1(n893), .Y(n1961) );
ADDFHX4TS U2786 ( .A(n2495), .B(n2494), .CI(n2493), .CO(n2523), .S(n2496) );
ADDFHX4TS U2787 ( .A(n1857), .B(n1856), .CI(n1855), .CO(n1862), .S(n1861) );
XOR2X4TS U2788 ( .A(n2103), .B(n825), .Y(n2075) );
NAND2X8TS U2789 ( .A(n1095), .B(n1094), .Y(n1853) );
XOR2X4TS U2790 ( .A(n1849), .B(n3815), .Y(n1850) );
NOR2X4TS U2791 ( .A(n2470), .B(n2469), .Y(n2468) );
XNOR2X4TS U2792 ( .A(n2658), .B(mult_x_55_n446), .Y(n1925) );
BUFX6TS U2793 ( .A(mult_x_55_n71), .Y(n1097) );
XOR2X4TS U2794 ( .A(n2324), .B(n2315), .Y(n1365) );
NOR2X6TS U2795 ( .A(n2241), .B(n2258), .Y(n2292) );
CLKXOR2X2TS U2796 ( .A(n1892), .B(n3806), .Y(n1907) );
BUFX20TS U2797 ( .A(n1476), .Y(n2652) );
XNOR2X2TS U2798 ( .A(n848), .B(n2408), .Y(n2057) );
AO22X4TS U2799 ( .A0(n2645), .A1(n3645), .B0(n3658), .B1(n1509), .Y(n1520)
);
NAND2X4TS U2800 ( .A(n2558), .B(DP_OP_111J16_123_4462_n159), .Y(
DP_OP_111J16_123_4462_n20) );
OAI22X2TS U2801 ( .A0(n1493), .A1(mult_x_55_n505), .B0(n467), .B1(
mult_x_55_n504), .Y(n1935) );
OAI22X4TS U2802 ( .A0(n1633), .A1(n858), .B0(n1593), .B1(n890), .Y(n1631) );
AOI2BB2X2TS U2803 ( .B0(n3391), .B1(n257), .A0N(n902), .A1N(n3915), .Y(n3311) );
XNOR2X2TS U2804 ( .A(n2412), .B(n885), .Y(n2070) );
XNOR2X4TS U2805 ( .A(n3301), .B(n3745), .Y(n3302) );
XNOR2X2TS U2806 ( .A(n2103), .B(n885), .Y(n2037) );
NAND2X4TS U2807 ( .A(Sgf_normalized_result[12]), .B(
Sgf_normalized_result[13]), .Y(n3428) );
NOR2X1TS U2808 ( .A(n3431), .B(n3430), .Y(n3432) );
OAI22X4TS U2809 ( .A0(n2071), .A1(n2411), .B0(n2065), .B1(n857), .Y(n2058)
);
NAND2X4TS U2810 ( .A(n3085), .B(n3883), .Y(DP_OP_111J16_123_4462_n36) );
BUFX20TS U2811 ( .A(n3572), .Y(n1168) );
NAND3X8TS U2812 ( .A(n1108), .B(n1107), .C(n1106), .Y(n1406) );
OAI22X4TS U2813 ( .A0(n1111), .A1(n2110), .B0(n2108), .B1(n1302), .Y(n2087)
);
XOR2X4TS U2814 ( .A(n1169), .B(n1093), .Y(n1111) );
XNOR2X4TS U2815 ( .A(n644), .B(n1456), .Y(n1117) );
XNOR2X4TS U2816 ( .A(n594), .B(n3625), .Y(n1116) );
XNOR2X4TS U2817 ( .A(n3829), .B(DP_OP_111J16_123_4462_n160), .Y(n1115) );
NAND2BX4TS U2818 ( .AN(n1456), .B(n1115), .Y(n1120) );
CLKINVX12TS U2819 ( .A(Sgf_operation_EVEN1_Q_left[5]), .Y(n1814) );
AOI21X4TS U2820 ( .A0(n2181), .A1(n2176), .B0(n1102), .Y(n2175) );
NOR2X8TS U2821 ( .A(n3484), .B(n3403), .Y(n3424) );
XOR2X4TS U2822 ( .A(n2171), .B(n2170), .Y(n2212) );
NOR2X8TS U2823 ( .A(n3451), .B(n3449), .Y(n2218) );
XOR2X4TS U2824 ( .A(n2185), .B(n2184), .Y(n2216) );
XNOR2X4TS U2825 ( .A(n1125), .B(n3029), .Y(Sgf_operation_Result[23]) );
NOR2BX4TS U2826 ( .AN(n1127), .B(n3025), .Y(n1126) );
OAI21X4TS U2827 ( .A0(n3032), .A1(n3030), .B0(n3033), .Y(n3037) );
NOR2BX4TS U2828 ( .AN(n3036), .B(n3024), .Y(n1129) );
NAND2X8TS U2829 ( .A(n2219), .B(n1130), .Y(add_x_19_n272) );
NAND2X8TS U2830 ( .A(n1131), .B(n1400), .Y(n1860) );
OAI2BB1X4TS U2831 ( .A0N(n3057), .A1N(n2204), .B0(n1858), .Y(n1131) );
OAI2BB1X4TS U2832 ( .A0N(n3624), .A1N(n3606), .B0(n1134), .Y(n1133) );
NOR2X8TS U2833 ( .A(n2162), .B(n2161), .Y(n3024) );
OAI22X4TS U2834 ( .A0(n893), .A1(n1135), .B0(n744), .B1(n1925), .Y(n1930) );
OAI22X4TS U2835 ( .A0(n1510), .A1(n893), .B0(n744), .B1(n1135), .Y(n1519) );
XOR2X4TS U2836 ( .A(mult_x_55_n536), .B(mult_x_55_n562), .Y(n2651) );
NAND3X8TS U2837 ( .A(n1138), .B(n2853), .C(n1136), .Y(n1234) );
OAI2BB1X4TS U2838 ( .A0N(n1139), .A1N(n739), .B0(n2946), .Y(n2861) );
OAI22X4TS U2839 ( .A0(n1156), .A1(n2443), .B0(n4008), .B1(n2450), .Y(n2447)
);
OAI22X2TS U2840 ( .A0(n2017), .A1(n846), .B0(n2011), .B1(
DP_OP_111J16_123_4462_n680), .Y(n2012) );
OAI22X2TS U2841 ( .A0(n1020), .A1(n1949), .B0(n891), .B1(n702), .Y(n2685) );
ADDFHX4TS U2842 ( .A(n1516), .B(n1515), .CI(n1514), .CO(n1524), .S(n1974) );
INVX12TS U2843 ( .A(n3691), .Y(n2453) );
NAND2X8TS U2844 ( .A(n1144), .B(n1885), .Y(n2968) );
NAND2X8TS U2845 ( .A(n1164), .B(n718), .Y(n1144) );
OAI22X2TS U2846 ( .A0(n2479), .A1(n1703), .B0(n705), .B1(mult_x_23_n492),
.Y(n1700) );
NAND2X4TS U2847 ( .A(n2451), .B(n1143), .Y(n2859) );
OAI22X2TS U2848 ( .A0(n445), .A1(n1719), .B0(n705), .B1(n1703), .Y(n1705) );
OAI22X2TS U2849 ( .A0(n2055), .A1(n1566), .B0(n1654), .B1(n897), .Y(n2529)
);
ADDFHX4TS U2850 ( .A(n1645), .B(n1644), .CI(n1643), .CO(n1634), .S(n2540) );
BUFX6TS U2851 ( .A(n3909), .Y(n1146) );
OAI22X4TS U2852 ( .A0(n770), .A1(mult_x_55_n479), .B0(mult_x_55_n555), .B1(
n1508), .Y(n1543) );
OR2X6TS U2853 ( .A(n2427), .B(n2426), .Y(n3073) );
OAI21X4TS U2854 ( .A0(DP_OP_111J16_123_4462_n159), .A1(n3097), .B0(n3096),
.Y(DP_OP_111J16_123_4462_n150) );
OAI22X2TS U2855 ( .A0(n1154), .A1(n881), .B0(n2398), .B1(n1071), .Y(n2414)
);
XNOR2X2TS U2856 ( .A(n1565), .B(n885), .Y(n2091) );
NOR2X8TS U2857 ( .A(n2757), .B(DP_OP_111J16_123_4462_n71), .Y(n3085) );
OAI22X4TS U2858 ( .A0(n1583), .A1(n1071), .B0(n1987), .B1(n881), .Y(n2399)
);
XNOR2X2TS U2859 ( .A(mult_x_23_n553), .B(mult_x_55_n569), .Y(n3158) );
ADDFHX2TS U2860 ( .A(n2611), .B(n2610), .CI(n2609), .CO(n2640), .S(n2639) );
INVX2TS U2861 ( .A(n3037), .Y(n3038) );
OAI21X4TS U2862 ( .A0(add_x_19_n271), .A1(n3039), .B0(n3038), .Y(n3043) );
OAI22X2TS U2863 ( .A0(n1154), .A1(n1445), .B0(n2420), .B1(n881), .Y(n2421)
);
NAND2X2TS U2864 ( .A(n2798), .B(n2804), .Y(n2807) );
XNOR2X2TS U2865 ( .A(n2090), .B(n885), .Y(n2105) );
XNOR2X4TS U2866 ( .A(n1170), .B(n2910), .Y(Sgf_operation_EVEN1_left_N9) );
ADDFHX4TS U2867 ( .A(n1622), .B(n1623), .CI(n1621), .CO(n2371), .S(n2438) );
ADDFHX2TS U2868 ( .A(n3740), .B(n2874), .CI(n2873), .CO(n2880), .S(n2891) );
OAI21X4TS U2869 ( .A0(n2935), .A1(n2934), .B0(n2933), .Y(mult_x_23_n39) );
NOR2X8TS U2870 ( .A(n2931), .B(n725), .Y(n2935) );
ADDFHX2TS U2871 ( .A(n2517), .B(n2518), .CI(n2516), .CO(n2508), .S(n2519) );
AO22X2TS U2872 ( .A0(n3515), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n3527), .Y(n178) );
INVX2TS U2873 ( .A(n2613), .Y(n2602) );
NAND2X2TS U2874 ( .A(n2392), .B(n2391), .Y(n2927) );
NAND2X8TS U2875 ( .A(n1157), .B(n1235), .Y(mult_x_23_n140) );
OAI21X4TS U2876 ( .A0(n3023), .A1(n3021), .B0(n3044), .Y(add_x_19_n216) );
NAND2X2TS U2877 ( .A(n3479), .B(n3478), .Y(n3480) );
OAI22X2TS U2878 ( .A0(n1635), .A1(n899), .B0(n1646), .B1(n2108), .Y(n2571)
);
ADDFHX4TS U2879 ( .A(n2571), .B(n2572), .CI(n2570), .CO(n1655), .S(n2718) );
OAI22X2TS U2880 ( .A0(n445), .A1(n2452), .B0(n705), .B1(n2460), .Y(n2466) );
MX2X6TS U2881 ( .A(Data_MX[14]), .B(n4046), .S0(n2945), .Y(n358) );
NOR2X1TS U2882 ( .A(n3561), .B(n3152), .Y(n3153) );
OAI22X2TS U2883 ( .A0(n2104), .A1(DP_OP_111J16_123_4462_n685), .B0(n2044),
.B1(n1566), .Y(n2113) );
MX2X6TS U2884 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n3062), .Y(n350) );
AOI21X4TS U2885 ( .A0(n1408), .A1(n1898), .B0(n1407), .Y(n1793) );
OAI21X2TS U2886 ( .A0(n3372), .A1(n3235), .B0(n3234), .Y(n3236) );
XNOR2X4TS U2887 ( .A(n3455), .B(n2357), .Y(n2358) );
OAI21X2TS U2888 ( .A0(n3378), .A1(n3293), .B0(n3292), .Y(n3294) );
OAI21X2TS U2889 ( .A0(n632), .A1(n3619), .B0(n3620), .Y(n1893) );
NAND2X4TS U2890 ( .A(n2913), .B(n703), .Y(mult_x_23_n20) );
OAI22X4TS U2891 ( .A0(n445), .A1(n1723), .B0(n705), .B1(n1719), .Y(n1739) );
OAI21X4TS U2892 ( .A0(mult_x_23_n81), .A1(n2926), .B0(n2927), .Y(
mult_x_23_n6) );
AOI21X4TS U2893 ( .A0(n439), .A1(n1073), .B0(n3081), .Y(
DP_OP_111J16_123_4462_n59) );
INVX2TS U2894 ( .A(n2399), .Y(n1984) );
AOI21X4TS U2895 ( .A0(n2324), .A1(n2334), .B0(n2342), .Y(n2279) );
NAND2X2TS U2896 ( .A(n2238), .B(n2256), .Y(n2239) );
INVX4TS U2897 ( .A(n2922), .Y(n2506) );
NOR2X8TS U2898 ( .A(n1756), .B(n1757), .Y(mult_x_55_n71) );
INVX6TS U2899 ( .A(mult_x_55_n58), .Y(n2735) );
AND2X8TS U2900 ( .A(n1436), .B(n1163), .Y(n1435) );
XNOR2X2TS U2901 ( .A(n1090), .B(n885), .Y(n2107) );
OAI22X2TS U2902 ( .A0(n698), .A1(n1664), .B0(mult_x_23_n540), .B1(n1606),
.Y(n1674) );
NAND2X4TS U2903 ( .A(n3091), .B(n3092), .Y(DP_OP_111J16_123_4462_n11) );
XNOR2X2TS U2904 ( .A(n2412), .B(n887), .Y(n1581) );
AOI21X2TS U2905 ( .A0(n2342), .A1(n2341), .B0(n2340), .Y(n2343) );
NAND2X4TS U2906 ( .A(n2207), .B(n2206), .Y(n3470) );
XOR2X4TS U2907 ( .A(n1167), .B(n2496), .Y(n2503) );
XNOR2X4TS U2908 ( .A(n1232), .B(n2498), .Y(n1167) );
OAI22X2TS U2909 ( .A0(n2475), .A1(n445), .B0(n2478), .B1(n705), .Y(n2493) );
OAI21X2TS U2910 ( .A0(mult_x_55_a_8_), .A1(n1475), .B0(mult_x_55_n567), .Y(
n3119) );
INVX2TS U2911 ( .A(n2288), .Y(n2286) );
INVX2TS U2912 ( .A(n2299), .Y(n2285) );
NAND2X4TS U2913 ( .A(n1162), .B(n2903), .Y(mult_x_23_n19) );
CMPR22X2TS U2914 ( .A(n1721), .B(n1720), .CO(n1726), .S(n1738) );
XNOR2X4TS U2915 ( .A(n3373), .B(n3749), .Y(n3374) );
OAI2BB1X4TS U2916 ( .A0N(n882), .A1N(add_x_19_n122), .B0(n3368), .Y(n3369)
);
AO21X2TS U2917 ( .A0(n445), .A1(n705), .B0(n1452), .Y(n1607) );
NAND3X2TS U2918 ( .A(n3338), .B(n3337), .C(n3336), .Y(n200) );
INVX4TS U2919 ( .A(n3257), .Y(n3335) );
OAI21X4TS U2920 ( .A0(n3146), .A1(n3142), .B0(n3143), .Y(n3108) );
ADDFHX4TS U2921 ( .A(n2040), .B(n2039), .CI(n2038), .CO(n2134), .S(n2047) );
NAND2X8TS U2922 ( .A(n1172), .B(n1171), .Y(n2409) );
XNOR2X4TS U2923 ( .A(n3612), .B(n3611), .Y(n1214) );
NAND2X2TS U2924 ( .A(n2347), .B(n2352), .Y(n2355) );
XOR2X4TS U2925 ( .A(mult_x_23_n552), .B(n1174), .Y(n3155) );
MXI2X8TS U2926 ( .A(n1175), .B(n3997), .S0(n3062), .Y(mult_x_55_n568) );
XOR2X4TS U2927 ( .A(n348), .B(n2865), .Y(n3128) );
XNOR2X4TS U2928 ( .A(mult_x_23_n553), .B(n1263), .Y(n3711) );
OR2X4TS U2929 ( .A(n2451), .B(n1143), .Y(n2860) );
XOR2X4TS U2930 ( .A(n2474), .B(n3666), .Y(n1723) );
CLKINVX12TS U2931 ( .A(n3663), .Y(n2474) );
AOI2BB2X4TS U2932 ( .B0(n2661), .B1(n2660), .A0N(n713), .A1N(n2659), .Y(
n2662) );
XNOR2X4TS U2933 ( .A(n2621), .B(mult_x_55_n444), .Y(n2660) );
XNOR2X4TS U2934 ( .A(n2436), .B(n2435), .Y(n1251) );
OAI21X2TS U2935 ( .A0(n2479), .A1(n1667), .B0(n1183), .Y(n1672) );
NAND2BX4TS U2936 ( .AN(n1445), .B(n848), .Y(n1185) );
XNOR2X4TS U2937 ( .A(n854), .B(mult_x_55_n445), .Y(n1186) );
OAI21X4TS U2938 ( .A0(n3185), .A1(n3188), .B0(n3186), .Y(n3069) );
NAND2BX4TS U2939 ( .AN(n1187), .B(n905), .Y(n3186) );
OAI2BB1X4TS U2940 ( .A0N(n3893), .A1N(n1993), .B0(n1189), .Y(n3076) );
NAND2BX4TS U2941 ( .AN(n1992), .B(n740), .Y(n1189) );
BUFX6TS U2942 ( .A(n1405), .Y(n1190) );
OAI22X2TS U2943 ( .A0(n1492), .A1(n847), .B0(mult_x_55_n554), .B1(n1194),
.Y(n1761) );
NAND2X8TS U2944 ( .A(n1198), .B(n2772), .Y(n1779) );
NAND2X8TS U2945 ( .A(n1201), .B(n2773), .Y(n1198) );
NAND2X8TS U2946 ( .A(n1200), .B(n1199), .Y(n2773) );
OA21X4TS U2947 ( .A0(n2562), .A1(n3266), .B0(n2561), .Y(n1206) );
NOR2X4TS U2948 ( .A(n1208), .B(n1207), .Y(n3395) );
NAND2X8TS U2949 ( .A(n1216), .B(n685), .Y(n3013) );
XOR2X4TS U2950 ( .A(n722), .B(n1796), .Y(n1868) );
AND2X8TS U2951 ( .A(n1225), .B(n1905), .Y(n1224) );
OR2X8TS U2952 ( .A(n1225), .B(n1905), .Y(n1223) );
XNOR2X4TS U2953 ( .A(n1226), .B(n3670), .Y(n2961) );
OAI2BB1X4TS U2954 ( .A0N(n1898), .A1N(n1784), .B0(n1227), .Y(n1226) );
NOR2BX4TS U2955 ( .AN(n1783), .B(n1228), .Y(n1227) );
OAI21X4TS U2956 ( .A0(n1231), .A1(n1230), .B0(n1229), .Y(n2504) );
NAND2BX4TS U2957 ( .AN(n1232), .B(n2498), .Y(n1229) );
NOR2BX4TS U2958 ( .AN(n1232), .B(n2498), .Y(n1231) );
NOR2X8TS U2959 ( .A(n2907), .B(n2915), .Y(n1233) );
NAND2X8TS U2960 ( .A(n1318), .B(n2507), .Y(n1317) );
NAND2X8TS U2961 ( .A(n1234), .B(n726), .Y(n1318) );
NOR2X8TS U2962 ( .A(n1237), .B(n1236), .Y(n1235) );
NOR2X8TS U2963 ( .A(n2916), .B(n2907), .Y(n1237) );
NOR2X8TS U2964 ( .A(n2528), .B(n2527), .Y(n2907) );
OAI2BB1X4TS U2965 ( .A0N(n2509), .A1N(n2508), .B0(n1238), .Y(n2866) );
XOR2X4TS U2966 ( .A(n1239), .B(n1240), .Y(n2528) );
XOR2X4TS U2967 ( .A(n2509), .B(n2508), .Y(n1239) );
XNOR2X4TS U2968 ( .A(n1255), .B(n1738), .Y(n1240) );
OAI22X4TS U2969 ( .A0(n1932), .A1(n891), .B0(n1933), .B1(n1244), .Y(n1940)
);
XOR2X4TS U2970 ( .A(n3100), .B(n1247), .Y(Sgf_operation_EVEN1_middle_N7) );
NAND2BX4TS U2971 ( .AN(n3098), .B(n3099), .Y(n1247) );
XOR2X4TS U2972 ( .A(mult_x_55_n444), .B(n3575), .Y(n1963) );
NAND2BX4TS U2973 ( .AN(n2818), .B(n2819), .Y(n1248) );
OAI21X4TS U2974 ( .A0(n2895), .A1(n2904), .B0(n2899), .Y(mult_x_23_n100) );
XNOR2X4TS U2975 ( .A(n1251), .B(n2434), .Y(n2711) );
BUFX16TS U2976 ( .A(n698), .Y(n1252) );
OAI2BB1X4TS U2977 ( .A0N(n1739), .A1N(n1738), .B0(n1254), .Y(n1728) );
AOI21X4TS U2978 ( .A0(n2902), .A1(n1258), .B0(n2750), .Y(mult_x_23_n114) );
NAND2X8TS U2979 ( .A(n1256), .B(n2913), .Y(n1258) );
NOR2X8TS U2980 ( .A(mult_x_23_n78), .B(n2926), .Y(mult_x_23_n7) );
NOR2X8TS U2981 ( .A(n2741), .B(n2740), .Y(mult_x_23_n78) );
NAND2BX4TS U2982 ( .AN(n1260), .B(n3155), .Y(n1259) );
OAI2BB1X4TS U2983 ( .A0N(mult_x_55_n569), .A1N(n1261), .B0(n3150), .Y(n3154)
);
OAI21X1TS U2984 ( .A0(n2940), .A1(n2938), .B0(n2939), .Y(n2856) );
NAND2X8TS U2985 ( .A(n1265), .B(n1264), .Y(n2936) );
NAND2BX4TS U2986 ( .AN(n3475), .B(n3477), .Y(n3442) );
NOR2BX4TS U2987 ( .AN(n3416), .B(n3428), .Y(n1270) );
OAI2BB1X4TS U2988 ( .A0N(n925), .A1N(n1467), .B0(n1271), .Y(n1880) );
OAI21X4TS U2989 ( .A0(n925), .A1(n1467), .B0(n806), .Y(n1271) );
NOR2X8TS U2990 ( .A(n1274), .B(n1273), .Y(n1276) );
NAND2X4TS U2991 ( .A(n1289), .B(n1292), .Y(n2018) );
OAI2BB1X4TS U2992 ( .A0N(n1294), .A1N(n1290), .B0(n2010), .Y(n1289) );
NAND2X2TS U2993 ( .A(n896), .B(n848), .Y(n1294) );
NAND2BX4TS U2994 ( .AN(n2002), .B(n1298), .Y(n1297) );
OAI2BB1X4TS U2995 ( .A0N(n1306), .A1N(n1308), .B0(n2552), .Y(n1305) );
XNOR2X4TS U2996 ( .A(n1307), .B(n2552), .Y(n2595) );
XOR2X4TS U2997 ( .A(n1311), .B(n1308), .Y(n1307) );
AOI2BB2X4TS U2998 ( .B0(n1310), .B1(n1309), .A0N(n2091), .A1N(n884), .Y(
n1308) );
XOR2X4TS U2999 ( .A(n1154), .B(n885), .Y(n2082) );
XNOR2X4TS U3000 ( .A(n1168), .B(mult_x_55_n532), .Y(n1477) );
XOR2X4TS U3001 ( .A(n3572), .B(mult_x_55_n444), .Y(n1541) );
XOR2X4TS U3002 ( .A(n1320), .B(n1319), .Y(n2960) );
OAI2BB1X4TS U3003 ( .A0N(n1092), .A1N(n1871), .B0(n1321), .Y(n1320) );
XOR2X4TS U3004 ( .A(n1323), .B(n1322), .Y(n2161) );
OAI21X4TS U3005 ( .A0(n3617), .A1(n632), .B0(n1324), .Y(n1323) );
XOR2X4TS U3006 ( .A(n1327), .B(add_x_19_n7), .Y(n1326) );
NAND2BX4TS U3007 ( .AN(n3299), .B(n714), .Y(n3301) );
NAND2X4TS U3008 ( .A(n3300), .B(n1329), .Y(n1331) );
OR2X8TS U3009 ( .A(n2562), .B(n582), .Y(n1330) );
ADDFHX4TS U3010 ( .A(n1726), .B(n1725), .CI(n1724), .CO(n1752), .S(n1727) );
INVX2TS U3011 ( .A(n3416), .Y(n3431) );
INVX2TS U3012 ( .A(n2930), .Y(n2931) );
INVX2TS U3013 ( .A(n2935), .Y(mult_x_23_n50) );
OAI21X2TS U3014 ( .A0(n3378), .A1(n1330), .B0(n444), .Y(n3363) );
AOI21X4TS U3015 ( .A0(n3707), .A1(n3708), .B0(n3709), .Y(n1844) );
NAND2X4TS U3016 ( .A(n805), .B(n3084), .Y(DP_OP_111J16_123_4462_n17) );
XOR2X4TS U3017 ( .A(n2919), .B(n2918), .Y(Sgf_operation_EVEN1_left_N8) );
MXI2X4TS U3018 ( .A(Data_MX[18]), .B(n4040), .S0(n745), .Y(n2858) );
OAI21X2TS U3019 ( .A0(n632), .A1(n3602), .B0(n3603), .Y(n1788) );
ADDFX2TS U3020 ( .A(n2841), .B(n2840), .CI(n2839), .CO(n2847), .S(n2793) );
INVX2TS U3021 ( .A(n2802), .Y(n2803) );
INVX2TS U3022 ( .A(n1665), .Y(n1681) );
OA21X4TS U3023 ( .A0(mult_x_55_n59), .A1(n2807), .B0(n2806), .Y(n3650) );
OAI22X4TS U3024 ( .A0(n1987), .A1(n1445), .B0(n2398), .B1(n881), .Y(n2400)
);
NAND2X4TS U3025 ( .A(n2314), .B(n2313), .Y(n2316) );
OAI22X4TS U3026 ( .A0(n2397), .A1(n857), .B0(n2411), .B1(n3892), .Y(n2422)
);
XNOR2X4TS U3027 ( .A(n1565), .B(n886), .Y(n2061) );
ADDFHX4TS U3028 ( .A(n1952), .B(n1951), .CI(n1950), .CO(n1977), .S(n1953) );
XNOR2X4TS U3029 ( .A(mult_x_55_n562), .B(mult_x_55_n445), .Y(n1959) );
NAND3X2TS U3030 ( .A(n3318), .B(n3317), .C(n3316), .Y(n210) );
BUFX20TS U3031 ( .A(n1601), .Y(n2487) );
OAI21X4TS U3032 ( .A0(n2344), .A1(n1096), .B0(n2343), .Y(n3453) );
NOR2X4TS U3033 ( .A(n2333), .B(n2339), .Y(n2341) );
NAND2X8TS U3034 ( .A(n2775), .B(n3501), .Y(n3508) );
NOR2X8TS U3035 ( .A(n3193), .B(FS_Module_state_reg[1]), .Y(n3501) );
AOI21X4TS U3036 ( .A0(n3127), .A1(n1338), .B0(n3126), .Y(n3133) );
OAI21X4TS U3037 ( .A0(n1341), .A1(n635), .B0(n1339), .Y(n260) );
XOR2X4TS U3038 ( .A(n1342), .B(n3744), .Y(n1341) );
NAND2BX4TS U3039 ( .AN(n3319), .B(n1343), .Y(n1342) );
NOR2BX4TS U3040 ( .AN(n1391), .B(n3321), .Y(n1344) );
OAI21X4TS U3041 ( .A0(n3323), .A1(n3372), .B0(n1346), .Y(n3324) );
NAND2BX2TS U3042 ( .AN(n1348), .B(n3393), .Y(n206) );
NAND2BX4TS U3043 ( .AN(n635), .B(n1356), .Y(n1355) );
XNOR2X4TS U3044 ( .A(n3236), .B(n3750), .Y(n1356) );
XOR2X4TS U3045 ( .A(n3472), .B(n1357), .Y(n3473) );
OA21X4TS U3046 ( .A0(n3490), .A1(n3494), .B0(n3491), .Y(n1357) );
AOI2BB2X4TS U3047 ( .B0(n2614), .B1(n462), .A0N(n2613), .A1N(n2659), .Y(
n2615) );
XNOR2X4TS U3048 ( .A(n2296), .B(n2297), .Y(n1362) );
NOR2BX4TS U3049 ( .AN(n1472), .B(n3560), .Y(n1363) );
OAI22X4TS U3050 ( .A0(n1365), .A1(n3456), .B0(n1364), .B1(n442), .Y(n3461)
);
XOR2X4TS U3051 ( .A(n2330), .B(n2316), .Y(n1364) );
XOR2X4TS U3052 ( .A(n2283), .B(n2282), .Y(n1366) );
XOR2X4TS U3053 ( .A(n2279), .B(n2278), .Y(n1367) );
OA21X4TS U3054 ( .A0(n2826), .A1(n2832), .B0(n2827), .Y(n1370) );
OAI21X4TS U3055 ( .A0(n2304), .A1(n2308), .B0(n2305), .Y(n2287) );
NAND2BX4TS U3056 ( .AN(n2629), .B(n2630), .Y(n2764) );
OAI2BB1X4TS U3057 ( .A0N(n1972), .A1N(n402), .B0(n1374), .Y(n2726) );
OAI21X4TS U3058 ( .A0(n1972), .A1(n402), .B0(n1970), .Y(n1374) );
XOR2X4TS U3059 ( .A(n1375), .B(n1972), .Y(n1976) );
XNOR2X4TS U3060 ( .A(n4029), .B(mult_x_23_n546), .Y(n1722) );
XOR2X1TS U3061 ( .A(n2771), .B(n1376), .Y(Sgf_operation_EVEN1_right_N2) );
OAI21X4TS U3062 ( .A0(Op_MY[23]), .A1(FSM_selector_B[1]), .B0(n1146), .Y(
n1377) );
OAI2BB1X4TS U3063 ( .A0N(n1749), .A1N(n1750), .B0(n1378), .Y(n2743) );
XOR2X4TS U3064 ( .A(n1379), .B(n1750), .Y(n2745) );
XOR2X4TS U3065 ( .A(n1749), .B(n1748), .Y(n1379) );
NOR2X8TS U3066 ( .A(n1755), .B(n1754), .Y(n2906) );
XNOR2X4TS U3067 ( .A(n3035), .B(n1381), .Y(Sgf_operation_Result[21]) );
XOR2X4TS U3068 ( .A(n1384), .B(n3679), .Y(n2962) );
OAI21X4TS U3069 ( .A0(n1388), .A1(n635), .B0(n1386), .Y(n258) );
XOR2X4TS U3070 ( .A(n1389), .B(n3746), .Y(n1388) );
NOR2BX4TS U3071 ( .AN(n1391), .B(n3315), .Y(n1390) );
XOR2X4TS U3072 ( .A(n821), .B(n2983), .Y(n2991) );
XOR2X4TS U3073 ( .A(n2989), .B(n1846), .Y(n1441) );
NAND2X8TS U3074 ( .A(n1092), .B(n1399), .Y(n1398) );
NOR2X8TS U3075 ( .A(n583), .B(n593), .Y(n1399) );
XOR2X4TS U3076 ( .A(n1859), .B(n820), .Y(n1401) );
XOR2X4TS U3077 ( .A(n2223), .B(n1404), .Y(n2228) );
XOR2X4TS U3078 ( .A(n1406), .B(n3671), .Y(add_x_19_n51) );
AOI21X4TS U3079 ( .A0(n717), .A1(n1413), .B0(n1412), .Y(n1411) );
XOR2X4TS U3080 ( .A(n1415), .B(n3676), .Y(n2963) );
OAI21X4TS U3081 ( .A0(n612), .A1(n1795), .B0(n3680), .Y(n1416) );
NOR2BX4TS U3082 ( .AN(n1853), .B(n1800), .Y(n1436) );
OAI21X4TS U3083 ( .A0(n1440), .A1(n1843), .B0(n826), .Y(n1438) );
OAI21X4TS U3084 ( .A0(n2957), .A1(n3050), .B0(n2958), .Y(n3016) );
NAND2X4TS U3085 ( .A(n2228), .B(Sgf_operation_EVEN1_Q_left[1]), .Y(n2958) );
XNOR2X4TS U3086 ( .A(n3020), .B(n3019), .Y(Sgf_operation_Result[24]) );
INVX8TS U3087 ( .A(n3015), .Y(n3022) );
OAI22X4TS U3088 ( .A0(n2116), .A1(n859), .B0(n2064), .B1(n897), .Y(n2550) );
XNOR2X4TS U3089 ( .A(n1090), .B(n886), .Y(n2116) );
OAI21X4TS U3090 ( .A0(n3005), .A1(add_x_19_n202), .B0(n3006), .Y(
add_x_19_n197) );
NAND2X2TS U3091 ( .A(n2447), .B(n2446), .Y(n2946) );
NOR2X4TS U3092 ( .A(n2799), .B(n1097), .Y(mult_x_55_n69) );
NOR2X4TS U3093 ( .A(n2799), .B(mult_x_55_n58), .Y(mult_x_55_n56) );
NOR2X8TS U3094 ( .A(n2988), .B(n3010), .Y(add_x_19_n178) );
ADDFHX2TS U3095 ( .A(n1589), .B(n1588), .CI(n1587), .CO(n1982), .S(n1660) );
AOI21X2TS U3096 ( .A0(n2353), .A1(n2352), .B0(n2351), .Y(n2354) );
XNOR2X4TS U3097 ( .A(DP_OP_111J16_123_4462_n606), .B(
DP_OP_111J16_123_4462_n699), .Y(n1998) );
MX2X6TS U3098 ( .A(Data_MX[20]), .B(n4050), .S0(n2945), .Y(n1475) );
AOI2BB2X2TS U3099 ( .B0(n426), .B1(n3893), .A0N(n2122), .A1N(n846), .Y(n2123) );
NAND2X4TS U3100 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n3214) );
OAI22X4TS U3101 ( .A0(n2419), .A1(n860), .B0(n895), .B1(n3891), .Y(n3175) );
OAI21X4TS U3102 ( .A0(n2321), .A1(n2333), .B0(n2338), .Y(n2322) );
MXI2X2TS U3103 ( .A(n3480), .B(n1443), .S0(n443), .Y(n282) );
XNOR2X4TS U3104 ( .A(n2412), .B(n886), .Y(n1654) );
XNOR2X4TS U3105 ( .A(n2412), .B(n1077), .Y(n2121) );
INVX2TS U3106 ( .A(n3036), .Y(n3039) );
NAND2X2TS U3107 ( .A(n2320), .B(n2319), .Y(n2338) );
XOR2X2TS U3108 ( .A(n2293), .B(n2286), .Y(n2290) );
OAI21X2TS U3109 ( .A0(n3143), .A1(n3125), .B0(n1457), .Y(n3126) );
NAND2X4TS U3110 ( .A(n326), .B(n314), .Y(n3143) );
XNOR2X4TS U3111 ( .A(n1099), .B(n886), .Y(n2055) );
XNOR2X4TS U3112 ( .A(n2409), .B(DP_OP_111J16_123_4462_n699), .Y(n2079) );
AOI2BB2X4TS U3113 ( .B0(n2645), .B1(n1509), .A0N(n2647), .A1N(n1494), .Y(
n1495) );
OAI21X4TS U3114 ( .A0(n2896), .A1(n2903), .B0(n2897), .Y(n2750) );
NOR2X4TS U3115 ( .A(n327), .B(n315), .Y(n3125) );
OR2X8TS U3116 ( .A(n2680), .B(n2679), .Y(n2823) );
ADDFHX4TS U3117 ( .A(n1556), .B(n1555), .CI(n1554), .CO(n1557), .S(n1545) );
XNOR2X4TS U3118 ( .A(n393), .B(n1077), .Y(n1992) );
ADDFHX4TS U3119 ( .A(n1490), .B(n1489), .CI(n1488), .CO(n1759), .S(n1561) );
NAND2X6TS U3120 ( .A(n2741), .B(n2740), .Y(mult_x_23_n81) );
OAI22X4TS U3121 ( .A0(n2626), .A1(n2624), .B0(n844), .B1(n2612), .Y(n2632)
);
XNOR2X4TS U3122 ( .A(n3653), .B(mult_x_55_n448), .Y(n2612) );
XNOR2X4TS U3123 ( .A(n3653), .B(mult_x_55_n449), .Y(n2624) );
XNOR2X2TS U3124 ( .A(n2302), .B(n2301), .Y(n2303) );
OAI21X2TS U3125 ( .A0(n2300), .A1(n2299), .B0(n2298), .Y(n2302) );
XNOR2X4TS U3126 ( .A(DP_OP_111J16_123_4462_n605), .B(n2408), .Y(n1651) );
NAND2X4TS U3127 ( .A(n2212), .B(n1148), .Y(n3485) );
NAND2X4TS U3128 ( .A(n2715), .B(n2714), .Y(n2899) );
NOR2X4TS U3129 ( .A(n2336), .B(n2332), .Y(n2350) );
INVX6TS U3130 ( .A(n3266), .Y(n3291) );
AOI21X4TS U3131 ( .A0(n630), .A1(n3771), .B0(n3772), .Y(n3266) );
NAND2X4TS U3132 ( .A(n2211), .B(n2210), .Y(n3481) );
NOR2X6TS U3133 ( .A(n2095), .B(n2096), .Y(n2546) );
OAI22X2TS U3134 ( .A0(n2652), .A1(n2605), .B0(n2650), .B1(n3660), .Y(n2666)
);
XNOR2X4TS U3135 ( .A(mult_x_55_n562), .B(mult_x_55_n449), .Y(n2605) );
OR2X2TS U3136 ( .A(n2878), .B(n2877), .Y(n2879) );
MXI2X2TS U3137 ( .A(n3466), .B(n3903), .S0(n3559), .Y(n274) );
INVX4TS U3138 ( .A(n3465), .Y(n3466) );
XNOR2X4TS U3139 ( .A(n1948), .B(n3655), .Y(n1540) );
ADDFHX4TS U3140 ( .A(n1533), .B(n1532), .CI(n1531), .CO(n1546), .S(n1525) );
NAND2X4TS U3141 ( .A(n2748), .B(n2749), .Y(n2897) );
XNOR2X2TS U3142 ( .A(n1147), .B(n868), .Y(n1701) );
NAND2BX2TS U3143 ( .AN(Op_MY[12]), .B(n811), .Y(n1704) );
XNOR2X4TS U3144 ( .A(n1147), .B(mult_x_23_n517), .Y(n2377) );
XNOR2X4TS U3145 ( .A(n811), .B(n3666), .Y(n1606) );
XNOR2X4TS U3146 ( .A(n1147), .B(n571), .Y(n1603) );
XNOR2X4TS U3147 ( .A(n1147), .B(n3665), .Y(n1613) );
NAND2BX2TS U3148 ( .AN(Op_MY[12]), .B(n516), .Y(n2462) );
XNOR2X4TS U3149 ( .A(n516), .B(Op_MY[16]), .Y(n1733) );
XNOR2X4TS U3150 ( .A(n516), .B(n3666), .Y(n1709) );
XNOR2X4TS U3151 ( .A(n516), .B(n3667), .Y(n2473) );
XNOR2X4TS U3152 ( .A(n516), .B(mult_x_23_n517), .Y(n1678) );
XNOR2X4TS U3153 ( .A(n516), .B(n3664), .Y(n1677) );
NOR2X6TS U3154 ( .A(n2998), .B(n512), .Y(n3010) );
NAND2X4TS U3155 ( .A(n2999), .B(n3009), .Y(add_x_19_n13) );
INVX4TS U3156 ( .A(n3010), .Y(n2999) );
XNOR2X4TS U3157 ( .A(n3573), .B(mult_x_55_n530), .Y(n1508) );
ADDFHX2TS U3158 ( .A(n1718), .B(n1717), .CI(n1716), .CO(n1746), .S(n1729) );
MXI2X4TS U3159 ( .A(n2311), .B(n2310), .S0(n3456), .Y(n3560) );
ADDFHX4TS U3160 ( .A(n1524), .B(n1523), .CI(n1522), .CO(n1526), .S(n2722) );
ADDFHX2TS U3161 ( .A(n1500), .B(n1499), .CI(n1498), .CO(n1527), .S(n1522) );
XOR2X4TS U3162 ( .A(n1870), .B(n3586), .Y(n2215) );
AOI21X4TS U3163 ( .A0(n3624), .A1(n3599), .B0(n1869), .Y(n1870) );
NOR2X8TS U3164 ( .A(n3021), .B(n3046), .Y(n2232) );
NOR2X8TS U3165 ( .A(n2229), .B(n515), .Y(n3021) );
ADDFHX4TS U3166 ( .A(n2078), .B(n2077), .CI(n2076), .CO(n2080), .S(n2549) );
ADDFHX4TS U3167 ( .A(n1657), .B(n1656), .CI(n1655), .CO(n1662), .S(n2567) );
ADDFHX2TS U3168 ( .A(n1539), .B(n1538), .CI(n1537), .CO(n1555), .S(n1532) );
ADDFHX4TS U3169 ( .A(n2524), .B(n2523), .CI(n2522), .CO(n2525), .S(n2505) );
OR2X8TS U3170 ( .A(n2876), .B(n2875), .Y(n2932) );
NAND2BX2TS U3171 ( .AN(Op_MY[12]), .B(n1153), .Y(n1735) );
XNOR2X4TS U3172 ( .A(n3661), .B(n3664), .Y(n1614) );
XNOR2X4TS U3173 ( .A(n3661), .B(mult_x_23_n517), .Y(n1602) );
XNOR2X4TS U3174 ( .A(n3661), .B(n3667), .Y(n2480) );
XNOR2X4TS U3175 ( .A(n1153), .B(Op_MY[16]), .Y(n1702) );
INVX4TS U3176 ( .A(n2796), .Y(n2777) );
NOR2X4TS U3177 ( .A(n2797), .B(n2796), .Y(mult_x_55_n87) );
OAI21X2TS U3178 ( .A0(n3800), .A1(n3803), .B0(n3804), .Y(n3802) );
ADDFHX4TS U3179 ( .A(n1639), .B(n1638), .CI(n1637), .CO(n1659), .S(n1661) );
ADDFHX4TS U3180 ( .A(n1553), .B(n1552), .CI(n1551), .CO(n1560), .S(n1558) );
XNOR2X4TS U3181 ( .A(n2658), .B(mult_x_55_n444), .Y(n1510) );
AOI21X4TS U3182 ( .A0(DP_OP_111J16_123_4462_n720), .A1(
DP_OP_111J16_123_4462_n751), .B0(DP_OP_111J16_123_4462_n752), .Y(n1576) );
XNOR2X4TS U3183 ( .A(n1090), .B(n887), .Y(n1647) );
NAND2X2TS U3184 ( .A(n707), .B(Op_MY[24]), .Y(n2236) );
XOR2X4TS U3185 ( .A(n3575), .B(mult_x_55_n529), .Y(n1509) );
NOR2X4TS U3186 ( .A(mult_x_23_n525), .B(n313), .Y(n3163) );
MX2X6TS U3187 ( .A(Data_MY[1]), .B(n4030), .S0(n2945), .Y(n313) );
NAND2X4TS U3188 ( .A(n2230), .B(n1165), .Y(n3047) );
XNOR2X4TS U3189 ( .A(DP_OP_111J16_123_4462_n606), .B(
DP_OP_111J16_123_4462_n698), .Y(n2008) );
ADDFHX4TS U3190 ( .A(n2788), .B(n2787), .CI(n2786), .CO(n2794), .S(n1777) );
NOR2X2TS U3191 ( .A(n3805), .B(n3797), .Y(n3131) );
NOR2X4TS U3192 ( .A(n331), .B(n319), .Y(n3797) );
AOI21X4TS U3193 ( .A0(n3778), .A1(n3779), .B0(add_x_19_n205), .Y(n3244) );
NOR2X4TS U3194 ( .A(n624), .B(n3795), .Y(n3304) );
NOR2X4TS U3195 ( .A(n3795), .B(n590), .Y(n3233) );
INVX6TS U3196 ( .A(n2616), .Y(n2622) );
XOR2X4TS U3197 ( .A(n2175), .B(n2174), .Y(n2214) );
XNOR2X4TS U3198 ( .A(DP_OP_111J16_123_4462_n605), .B(
DP_OP_111J16_123_4462_n695), .Y(n2065) );
XNOR2X4TS U3199 ( .A(n393), .B(DP_OP_111J16_123_4462_n698), .Y(n2002) );
ADDFHX4TS U3200 ( .A(n2744), .B(n2743), .CI(n2742), .CO(n1694), .S(n2749) );
XNOR2X4TS U3201 ( .A(n2653), .B(n4026), .Y(n2628) );
ADDFHX2TS U3202 ( .A(n1549), .B(n1548), .CI(n1550), .CO(n1559), .S(n1554) );
OAI21X4TS U3203 ( .A0(n3484), .A1(n3481), .B0(n3485), .Y(n3423) );
XNOR2X4TS U3204 ( .A(n2409), .B(DP_OP_111J16_123_4462_n695), .Y(n2397) );
ADDFHX2TS U3205 ( .A(n1482), .B(n1481), .CI(n1480), .CO(n1489), .S(n1553) );
NOR2X4TS U3206 ( .A(n2799), .B(mult_x_55_n47), .Y(mult_x_55_n45) );
ADDFHX4TS U3207 ( .A(n1978), .B(n1977), .CI(n1976), .CO(n2729), .S(n2707) );
NAND2X4TS U3208 ( .A(n2640), .B(n2641), .Y(n2827) );
XNOR2X4TS U3209 ( .A(n1570), .B(n885), .Y(n2069) );
XOR2X4TS U3210 ( .A(n2252), .B(n2251), .Y(n2253) );
INVX2TS U3211 ( .A(n2266), .Y(n2251) );
NAND2X4TS U3212 ( .A(n2679), .B(n2680), .Y(n2822) );
NAND2X4TS U3213 ( .A(n2259), .B(n2258), .Y(n2298) );
NAND2X2TS U3214 ( .A(n3045), .B(n3044), .Y(add_x_19_n18) );
NOR2X4TS U3215 ( .A(n1996), .B(n905), .Y(n3185) );
XNOR2X4TS U3216 ( .A(DP_OP_111J16_123_4462_n606), .B(n2408), .Y(n1652) );
NOR2X8TS U3217 ( .A(n2557), .B(n2556), .Y(DP_OP_111J16_123_4462_n158) );
INVX6TS U3218 ( .A(n3227), .Y(n3368) );
XNOR2X4TS U3219 ( .A(DP_OP_111J16_123_4462_n606), .B(n886), .Y(n2024) );
XNOR2X4TS U3220 ( .A(n1168), .B(mult_x_55_n531), .Y(n1491) );
XNOR2X4TS U3221 ( .A(n1168), .B(mult_x_55_n530), .Y(n1764) );
XOR2X4TS U3222 ( .A(n1168), .B(mult_x_55_n449), .Y(n1927) );
XOR2X4TS U3223 ( .A(n1168), .B(n4026), .Y(n1497) );
XOR2X4TS U3224 ( .A(n1168), .B(mult_x_55_n448), .Y(n1513) );
XNOR2X4TS U3225 ( .A(n1168), .B(mult_x_55_n529), .Y(n1773) );
XOR2X4TS U3226 ( .A(n3572), .B(mult_x_55_n445), .Y(n1542) );
ADDFHX2TS U3227 ( .A(n2633), .B(n2632), .CI(n2631), .CO(n2638), .S(n2637) );
OAI21X4TS U3228 ( .A0(n2912), .A1(mult_x_23_n97), .B0(n2911), .Y(
mult_x_23_n88) );
OAI22X2TS U3229 ( .A0(n770), .A1(n1942), .B0(n1925), .B1(mult_x_55_n555),
.Y(n1945) );
XOR2X4TS U3230 ( .A(n2658), .B(mult_x_55_n536), .Y(n1942) );
XOR2X4TS U3231 ( .A(n2967), .B(n2966), .Y(n2985) );
ADDFHX4TS U3232 ( .A(n2384), .B(n2382), .CI(n2383), .CO(n2392), .S(n2740) );
NOR2X4TS U3233 ( .A(n850), .B(n3581), .Y(n2845) );
NOR2X4TS U3234 ( .A(n3407), .B(n3397), .Y(n3416) );
NAND2X2TS U3235 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n3407) );
NAND2X4TS U3236 ( .A(n2317), .B(n2319), .Y(n2349) );
NAND2X4TS U3237 ( .A(n2986), .B(n807), .Y(n3001) );
XOR2X4TS U3238 ( .A(n579), .B(n2970), .Y(n2986) );
NAND2X4TS U3239 ( .A(n2255), .B(n2254), .Y(n2308) );
OR2X8TS U3240 ( .A(n2678), .B(n2677), .Y(n2821) );
ADDFHX4TS U3241 ( .A(n2673), .B(n2672), .CI(n2671), .CO(n2679), .S(n2678) );
XNOR2X4TS U3242 ( .A(n393), .B(DP_OP_111J16_123_4462_n697), .Y(n2015) );
NOR2X8TS U3243 ( .A(n2207), .B(n2206), .Y(n3469) );
OAI21X4TS U3244 ( .A0(n2240), .A1(n2306), .B0(n2239), .Y(n2284) );
XOR2X4TS U3245 ( .A(n1948), .B(n3654), .Y(n1933) );
AND2X8TS U3246 ( .A(n3513), .B(n3512), .Y(n3525) );
MXI2X4TS U3247 ( .A(n3105), .B(n455), .S0(n3129), .Y(n326) );
MXI2X4TS U3248 ( .A(n3458), .B(n3457), .S0(n3456), .Y(n3460) );
NOR2X2TS U3249 ( .A(n3453), .B(n3454), .Y(n3458) );
ADDFHX4TS U3250 ( .A(n2675), .B(n2676), .CI(n2674), .CO(n2677), .S(n2641) );
ADDFHX4TS U3251 ( .A(n2699), .B(n2698), .CI(n2697), .CO(n2700), .S(n2680) );
ADDFHX4TS U3252 ( .A(n2713), .B(n2712), .CI(n2711), .CO(n2714), .S(n1695) );
ADDFHX4TS U3253 ( .A(n2034), .B(n2033), .CI(n1464), .CO(n2035), .S(n2022) );
ADDFHX4TS U3254 ( .A(n1753), .B(n1752), .CI(n1751), .CO(n1754), .S(n1741) );
NOR2X4TS U3255 ( .A(n2622), .B(n2617), .Y(n2768) );
CMPR22X2TS U3256 ( .A(n2492), .B(n2491), .CO(n2497), .S(n2499) );
OAI22X2TS U3257 ( .A0(n2649), .A1(n744), .B0(n2648), .B1(mult_x_55_n555),
.Y(n2669) );
ADDFHX4TS U3258 ( .A(n1982), .B(n1981), .CI(n1980), .CO(n3090), .S(n1697) );
ADDFHX2TS U3259 ( .A(n1763), .B(n1762), .CI(n1761), .CO(n1772), .S(n1765) );
INVX8TS U3260 ( .A(n2090), .Y(n1987) );
XOR2X4TS U3261 ( .A(n3695), .B(n3741), .Y(n1667) );
XOR2X4TS U3262 ( .A(DP_OP_111J16_123_4462_n625), .B(n403), .Y(n1571) );
INVX12TS U3263 ( .A(n3394), .Y(n3456) );
XNOR2X4TS U3264 ( .A(n1565), .B(n887), .Y(n1593) );
XOR2X4TS U3265 ( .A(n1450), .B(mult_x_23_n524), .Y(n2486) );
NOR2X4TS U3266 ( .A(n2238), .B(n2256), .Y(n2240) );
CMPR22X2TS U3267 ( .A(n2472), .B(n2471), .CO(n2516), .S(n2524) );
NAND2X4TS U3268 ( .A(n2956), .B(n1074), .Y(n3030) );
NOR2X4TS U3269 ( .A(n2799), .B(n3651), .Y(mult_x_55_n32) );
XOR2X4TS U3270 ( .A(n1894), .B(n3583), .Y(n2163) );
AOI21X2TS U3271 ( .A0(n3624), .A1(n3593), .B0(n1893), .Y(n1894) );
OAI21X4TS U3272 ( .A0(n3451), .A1(n3448), .B0(n3452), .Y(n2217) );
NOR2X8TS U3273 ( .A(n2441), .B(n2440), .Y(mult_x_23_n94) );
ADDFHX4TS U3274 ( .A(n2439), .B(n2437), .CI(n2438), .CO(n1625), .S(n2440) );
INVX6TS U3275 ( .A(n2784), .Y(n2820) );
XOR2X4TS U3276 ( .A(n3594), .B(n3595), .Y(n2194) );
XOR2X4TS U3277 ( .A(n2658), .B(mult_x_55_n537), .Y(n1962) );
OR2X8TS U3278 ( .A(n2894), .B(n2893), .Y(n3736) );
NOR2X8TS U3279 ( .A(n2230), .B(n1165), .Y(n3046) );
NAND2X2TS U3280 ( .A(n3049), .B(n3015), .Y(n3017) );
ADDFHX4TS U3281 ( .A(n2724), .B(n2723), .CI(n2722), .CO(n2360), .S(n2732) );
ADDFHX4TS U3282 ( .A(n2132), .B(n2131), .CI(n2130), .CO(n2138), .S(n2137) );
ADDFHX4TS U3283 ( .A(n2373), .B(n2372), .CI(n2371), .CO(n2741), .S(n1624) );
ADDFHX4TS U3284 ( .A(n2710), .B(n2708), .CI(n2709), .CO(n2441), .S(n2715) );
ADDFHX4TS U3285 ( .A(n2597), .B(n2596), .CI(n2595), .CO(n2598), .S(n2557) );
NOR2X8TS U3286 ( .A(n2755), .B(n2756), .Y(DP_OP_111J16_123_4462_n71) );
ADDFHX4TS U3287 ( .A(n1760), .B(n1759), .CI(n1758), .CO(n1769), .S(n1757) );
NAND2X4TS U3288 ( .A(n2557), .B(n2556), .Y(DP_OP_111J16_123_4462_n159) );
MXI2X4TS U3289 ( .A(n3904), .B(n4070), .S0(n569), .Y(n2271) );
OAI2BB2X2TS U3290 ( .B0(n2647), .B1(n2646), .A0N(n2645), .A1N(n3644), .Y(
n2670) );
XOR2X4TS U3291 ( .A(n3575), .B(mult_x_55_n445), .Y(n2646) );
CMPR22X2TS U3292 ( .A(n1687), .B(n1686), .CO(n1688), .S(n1713) );
OAI21X2TS U3293 ( .A0(n3668), .A1(Op_MY[12]), .B0(n883), .Y(n1687) );
ADDFHX4TS U3294 ( .A(n2521), .B(n2520), .CI(n2519), .CO(n2527), .S(n2526) );
XNOR2X4TS U3295 ( .A(n3624), .B(n3610), .Y(n2206) );
ADDFHX4TS U3296 ( .A(n2555), .B(n2554), .CI(n2553), .CO(n2556), .S(n2139) );
XOR2X4TS U3297 ( .A(n1948), .B(mult_x_55_n536), .Y(n1932) );
ADDFHX2TS U3298 ( .A(n2501), .B(n2500), .CI(n2499), .CO(n2502), .S(n2470) );
XNOR2X4TS U3299 ( .A(DP_OP_111J16_123_4462_n607), .B(n2408), .Y(n2056) );
BUFX20TS U3300 ( .A(DP_OP_111J16_123_4462_n694), .Y(n2408) );
NOR3X4TS U3301 ( .A(n3927), .B(FSM_selector_B[1]), .C(FSM_selector_B[0]),
.Y(n2332) );
ADDFHX4TS U3302 ( .A(n2418), .B(n2416), .CI(n2417), .CO(n2427), .S(n2424) );
ADDFHX4TS U3303 ( .A(n2718), .B(n2717), .CI(n2716), .CO(n2579), .S(n2739) );
ADDFHX2TS U3304 ( .A(n2467), .B(n2466), .CI(n2465), .CO(n2469), .S(n2458) );
CMPR22X2TS U3305 ( .A(n2663), .B(n2664), .CO(n2688), .S(n2673) );
AOI21X4TS U3306 ( .A0(n3069), .A1(n3068), .B0(n2001), .Y(n3172) );
OAI21X4TS U3307 ( .A0(n3780), .A1(n3781), .B0(n604), .Y(n3227) );
ADDFHX4TS U3308 ( .A(n1660), .B(n1659), .CI(n1658), .CO(n1696), .S(n2560) );
ADDFHX4TS U3309 ( .A(n1562), .B(n1560), .CI(n1561), .CO(n1756), .S(n2758) );
AOI21X4TS U3310 ( .A0(n2246), .A1(n2284), .B0(n2245), .Y(n2345) );
NAND2X4TS U3311 ( .A(n1454), .B(n2276), .Y(n2317) );
ADDFHX4TS U3312 ( .A(n2594), .B(n2593), .CI(n2592), .CO(n2095), .S(n2599) );
NAND2X8TS U3313 ( .A(n625), .B(add_x_19_n122), .Y(n3339) );
OR2X8TS U3314 ( .A(n1778), .B(n1777), .Y(n2798) );
ADDFHX4TS U3315 ( .A(n1772), .B(n1771), .CI(n1770), .CO(n1778), .S(n1768) );
BUFX20TS U3316 ( .A(n3657), .Y(n2658) );
ADDFHX4TS U3317 ( .A(n1955), .B(n1954), .CI(n1953), .CO(n2706), .S(n2705) );
OR2X8TS U3318 ( .A(n2425), .B(n2424), .Y(n3086) );
ADDFHX4TS U3319 ( .A(n2048), .B(n2046), .CI(n2047), .CO(n2049), .S(n2036) );
ADDFHX4TS U3320 ( .A(n1527), .B(n1526), .CI(n1525), .CO(n2363), .S(n2361) );
ADDFHX4TS U3321 ( .A(n2395), .B(n2394), .CI(n2393), .CO(n2756), .S(n3089) );
ADDFHX4TS U3322 ( .A(n2747), .B(n2746), .CI(n2745), .CO(n2748), .S(n1755) );
ADDFHX4TS U3323 ( .A(n2696), .B(n2695), .CI(n2694), .CO(n2702), .S(n2701) );
ADDFHX4TS U3324 ( .A(n2683), .B(n2684), .CI(n2682), .CO(n2704), .S(n2703) );
AOI21X4TS U3325 ( .A0(n2262), .A1(n2287), .B0(n2261), .Y(n2356) );
NOR2X4TS U3326 ( .A(n2272), .B(n2271), .Y(n2275) );
NAND2X2TS U3327 ( .A(n2269), .B(n2271), .Y(n2280) );
NOR2X4TS U3328 ( .A(n2269), .B(n2271), .Y(n2281) );
OAI21X4TS U3329 ( .A0(DP_OP_111J16_123_4462_n94), .A1(n3093), .B0(n3092),
.Y(DP_OP_111J16_123_4462_n83) );
NOR2X8TS U3330 ( .A(n3090), .B(n3089), .Y(n3093) );
ADDFHX4TS U3331 ( .A(n2569), .B(n2568), .CI(n2567), .CO(n2369), .S(n2580) );
NOR2X8TS U3332 ( .A(n2986), .B(n807), .Y(n3000) );
MXI2X4TS U3333 ( .A(n3908), .B(n3898), .S0(FSM_selector_A), .Y(n2258) );
AOI21X4TS U3334 ( .A0(n3624), .A1(n3604), .B0(n3605), .Y(n1794) );
ADDFHX4TS U3335 ( .A(n1663), .B(n1662), .CI(n1661), .CO(n2559), .S(n2370) );
XOR2X4TS U3336 ( .A(n3596), .B(n3597), .Y(n3503) );
OAI22X2TS U3337 ( .A0(n2625), .A1(n2626), .B0(n844), .B1(n2624), .Y(n2634)
);
MXI2X4TS U3338 ( .A(n3905), .B(n3899), .S0(FSM_selector_A), .Y(n2260) );
ADDFHX4TS U3339 ( .A(n1729), .B(n1728), .CI(n1727), .CO(n1740), .S(n2867) );
ADDFHX4TS U3340 ( .A(n1559), .B(n1558), .CI(n1557), .CO(n2759), .S(n2364) );
ADDFHX4TS U3341 ( .A(n1547), .B(n1546), .CI(n1545), .CO(n2365), .S(n2362) );
XOR2X4TS U3342 ( .A(n1789), .B(n3585), .Y(n2955) );
XNOR2X1TS U3343 ( .A(n1174), .B(n3631), .Y(n1442) );
INVX2TS U3344 ( .A(DP_OP_111J16_123_4462_n880), .Y(n2943) );
OR2X8TS U3345 ( .A(n1861), .B(n1860), .Y(n1455) );
OAI22X1TS U3346 ( .A0(n2122), .A1(DP_OP_111J16_123_4462_n680), .B0(n2121),
.B1(n846), .Y(n1463) );
CLKBUFX3TS U3347 ( .A(n4057), .Y(n3977) );
BUFX3TS U3348 ( .A(n3649), .Y(n3979) );
INVX2TS U3349 ( .A(n2316), .Y(n2315) );
INVX2TS U3350 ( .A(n2334), .Y(n2318) );
NAND2X2TS U3351 ( .A(n2200), .B(n2201), .Y(n2202) );
NAND2X1TS U3352 ( .A(n2154), .B(n2155), .Y(n2156) );
INVX2TS U3353 ( .A(n3291), .Y(n3283) );
INVX8TS U3354 ( .A(n3262), .Y(n3379) );
INVX2TS U3355 ( .A(n2811), .Y(n2813) );
INVX2TS U3356 ( .A(n2831), .Y(n2833) );
INVX2TS U3357 ( .A(n2808), .Y(n2810) );
INVX2TS U3358 ( .A(mult_x_23_n78), .Y(n2920) );
OAI21X2TS U3359 ( .A0(n2835), .A1(n2831), .B0(n2832), .Y(n2830) );
INVX2TS U3360 ( .A(DP_OP_111J16_123_4462_n891), .Y(n3639) );
INVX2TS U3361 ( .A(n3055), .Y(add_x_19_n47) );
XOR2X1TS U3362 ( .A(n3114), .B(n3113), .Y(n3843) );
XOR2X1TS U3363 ( .A(n3162), .B(mult_x_55_n565), .Y(n3872) );
NOR2X8TS U3364 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n2775) );
MX2X6TS U3365 ( .A(Data_MY[21]), .B(n4045), .S0(n879), .Y(n333) );
BUFX20TS U3366 ( .A(n3508), .Y(n3062) );
NAND2X2TS U3367 ( .A(mult_x_23_n518), .B(n320), .Y(n3801) );
MX2X4TS U3368 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n879), .Y(mult_x_23_n516) );
MX2X4TS U3369 ( .A(Data_MY[10]), .B(n3539), .S0(n746), .Y(n322) );
NAND2X2TS U3370 ( .A(mult_x_23_n516), .B(n322), .Y(n3852) );
INVX2TS U3371 ( .A(n323), .Y(n1468) );
MX2X6TS U3372 ( .A(Data_MY[4]), .B(n1470), .S0(n3129), .Y(n316) );
MX2X6TS U3373 ( .A(Data_MY[2]), .B(n4035), .S0(n745), .Y(n314) );
MX2X6TS U3374 ( .A(Data_MY[13]), .B(n3533), .S0(n2945), .Y(mult_x_23_n525)
);
NAND2X4TS U3376 ( .A(n2584), .B(n1089), .Y(n1471) );
AND2X8TS U3377 ( .A(n1471), .B(n2583), .Y(n3459) );
INVX2TS U3378 ( .A(n1474), .Y(n3565) );
INVX2TS U3379 ( .A(n1475), .Y(n3566) );
INVX2TS U3380 ( .A(n322), .Y(n3568) );
AO21X1TS U3382 ( .A0(n1476), .A1(n863), .B0(mult_x_55_n562), .Y(n1484) );
OAI22X1TS U3383 ( .A0(n852), .A1(n1477), .B0(n2842), .B1(n1491), .Y(n1490)
);
OAI22X1TS U3384 ( .A0(n852), .A1(n1491), .B0(n700), .B1(n1764), .Y(n1767) );
OAI22X1TS U3385 ( .A0(n2652), .A1(n1496), .B0(n863), .B1(mult_x_55_n490),
.Y(n1500) );
OAI22X1TS U3386 ( .A0(n1476), .A1(n1512), .B0(n863), .B1(n1496), .Y(n1514)
);
XNOR2X4TS U3387 ( .A(n672), .B(n3581), .Y(n1924) );
CLKINVX6TS U3388 ( .A(DP_OP_111J16_123_4462_n773), .Y(n1564) );
OAI22X1TS U3389 ( .A0(n1579), .A1(n856), .B0(n1582), .B1(n899), .Y(n1587) );
CLKINVX6TS U3390 ( .A(DP_OP_111J16_123_4462_n757), .Y(n1574) );
XNOR2X4TS U3391 ( .A(n1099), .B(n887), .Y(n1578) );
OAI22X1TS U3392 ( .A0(n1635), .A1(n856), .B0(n1597), .B1(n899), .Y(n1640) );
OAI22X1TS U3393 ( .A0(n698), .A1(n1613), .B0(n865), .B1(n2377), .Y(n2376) );
OAI22X1TS U3394 ( .A0(n2483), .A1(n1614), .B0(n889), .B1(n1153), .Y(n2375)
);
OAI22X1TS U3395 ( .A0(n698), .A1(n1668), .B0(n865), .B1(n1664), .Y(n1684) );
OAI22X1TS U3396 ( .A0(n698), .A1(mult_x_23_n459), .B0(mult_x_23_n540), .B1(
n1668), .Y(n1743) );
CMPR32X2TS U3397 ( .A(n1683), .B(n1684), .C(n1682), .CO(n2713), .S(n2744) );
ADDFHX4TS U3398 ( .A(n1693), .B(n1692), .CI(n1691), .CO(n2712), .S(n2742) );
OAI22X1TS U3399 ( .A0(n852), .A1(n1764), .B0(n2842), .B1(n1773), .Y(n1774)
);
AO21X1TS U3400 ( .A0(n1020), .A1(n891), .B0(n854), .Y(n2788) );
XOR2X1TS U3401 ( .A(n1785), .B(n3808), .Y(n1786) );
ADDFHX4TS U3402 ( .A(n1787), .B(add_x_19_n51), .CI(n1786), .CO(n1899), .S(
n1887) );
ADDFHX4TS U3403 ( .A(n1799), .B(n1798), .CI(n1797), .CO(n1873), .S(n1866) );
INVX12TS U3404 ( .A(Sgf_operation_Result[1]), .Y(n1803) );
NAND2X8TS U3405 ( .A(n1802), .B(Sgf_operation_EVEN1_Q_middle[0]), .Y(n2190)
);
ADDFHX4TS U3406 ( .A(Sgf_operation_EVEN1_Q_middle[2]), .B(n1805), .CI(n1804),
.CO(n1808), .S(n1807) );
ADDFHX4TS U3407 ( .A(Sgf_operation_EVEN1_Q_middle[3]), .B(n1811), .CI(n1810),
.CO(n1817), .S(n1809) );
ADDFHX4TS U3408 ( .A(Sgf_operation_EVEN1_Q_middle[4]), .B(n1813), .CI(n1812),
.CO(n1819), .S(n1818) );
ADDFHX4TS U3409 ( .A(Sgf_operation_EVEN1_Q_middle[5]), .B(n1815), .CI(n1814),
.CO(n1821), .S(n1820) );
INVX12TS U3410 ( .A(Sgf_operation_Result[7]), .Y(n1827) );
ADDFHX4TS U3411 ( .A(Sgf_operation_EVEN1_Q_middle[6]), .B(n1816), .CI(n1215),
.CO(n1823), .S(n1822) );
ADDFHX4TS U3412 ( .A(Sgf_operation_EVEN1_Q_middle[7]), .B(n1827), .CI(n1826),
.CO(n1832), .S(n1824) );
ADDFHX4TS U3413 ( .A(Sgf_operation_EVEN1_Q_middle[9]), .B(n1829), .CI(n1828),
.CO(n1837), .S(n1835) );
ADDFHX4TS U3414 ( .A(Sgf_operation_EVEN1_Q_middle[8]), .B(n1831), .CI(n1830),
.CO(n1834), .S(n1833) );
NAND2X8TS U3415 ( .A(n2146), .B(n2142), .Y(n2151) );
AOI21X4TS U3416 ( .A0(n2142), .A1(n828), .B0(n1836), .Y(n2150) );
OAI21X4TS U3417 ( .A0(n2153), .A1(n2150), .B0(n2154), .Y(n1838) );
CLKXOR2X4TS U3418 ( .A(n1840), .B(n3683), .Y(n1919) );
XNOR2X4TS U3419 ( .A(n1898), .B(n3687), .Y(n3057) );
ADDFHX4TS U3420 ( .A(n1852), .B(n706), .CI(n1851), .CO(n1865), .S(n1863) );
ADDFHX4TS U3421 ( .A(n1876), .B(n1875), .CI(n1874), .CO(n1886), .S(n1883) );
ADDFHX4TS U3422 ( .A(n1879), .B(n1878), .CI(n1877), .CO(n1882), .S(n1881) );
NAND2X8TS U3423 ( .A(n1880), .B(n1881), .Y(n2977) );
AOI21X4TS U3424 ( .A0(n1459), .A1(n2964), .B0(n1884), .Y(n1885) );
INVX12TS U3425 ( .A(n2163), .Y(n1903) );
AOI21X1TS U3426 ( .A0(n631), .A1(n3699), .B0(n3700), .Y(n1896) );
NOR2X8TS U3427 ( .A(n1907), .B(n1906), .Y(n2368) );
AOI21X1TS U3428 ( .A0(n3833), .A1(n3834), .B0(n3835), .Y(n1909) );
OAI21X1TS U3429 ( .A0(n1910), .A1(n605), .B0(n1909), .Y(n1911) );
AOI2BB1X1TS U3430 ( .A0N(n1913), .A1N(n1912), .B0(n1911), .Y(n1914) );
OAI22X4TS U3431 ( .A0(n847), .A1(n702), .B0(n891), .B1(n1933), .Y(n1957) );
XOR2X1TS U3432 ( .A(n1948), .B(n894), .Y(n1949) );
ADDFHX4TS U3433 ( .A(n1966), .B(n1965), .CI(n1964), .CO(n1954), .S(n2682) );
ADDFHX4TS U3434 ( .A(n1975), .B(n1974), .CI(n1973), .CO(n2723), .S(n2725) );
NOR2BX1TS U3435 ( .AN(n848), .B(n695), .Y(n1995) );
OAI22X1TS U3436 ( .A0(n2016), .A1(n695), .B0(n2008), .B1(n2106), .Y(n2020)
);
XNOR2X4TS U3437 ( .A(n2052), .B(n2051), .Y(Sgf_operation_EVEN1_middle_N8) );
ADDFHX4TS U3438 ( .A(n2094), .B(n2093), .CI(n2092), .CO(n2544), .S(n2592) );
OAI21X4TS U3439 ( .A0(n2152), .A1(n509), .B0(n2145), .Y(n2144) );
XNOR2X4TS U3440 ( .A(n2144), .B(n2143), .Y(n2149) );
XNOR2X4TS U3441 ( .A(n2157), .B(n2156), .Y(n2162) );
XNOR2X4TS U3442 ( .A(n2181), .B(n2166), .Y(n2211) );
AOI21X4TS U3443 ( .A0(n2181), .A1(n2168), .B0(n2167), .Y(n2171) );
AOI21X4TS U3444 ( .A0(n2181), .A1(n2180), .B0(n2179), .Y(n2185) );
CLKXOR2X4TS U3445 ( .A(n2197), .B(n1079), .Y(n2205) );
XNOR2X4TS U3446 ( .A(n2203), .B(n2202), .Y(n2207) );
XNOR2X4TS U3447 ( .A(n1190), .B(n2226), .Y(n2230) );
NAND2X1TS U3448 ( .A(n2242), .B(n2260), .Y(n2243) );
INVX2TS U3449 ( .A(n2270), .Y(n2249) );
AOI21X4TS U3450 ( .A0(n2324), .A1(n2249), .B0(n2248), .Y(n2252) );
NOR2X2TS U3451 ( .A(n2299), .B(n2294), .Y(n2262) );
AOI21X4TS U3452 ( .A0(n2330), .A1(n2314), .B0(n2265), .Y(n2267) );
NOR2X8TS U3453 ( .A(n2270), .B(n2275), .Y(n2334) );
NAND2X1TS U3454 ( .A(n2272), .B(n2271), .Y(n2273) );
OAI21X4TS U3455 ( .A0(n2275), .A1(n2274), .B0(n2273), .Y(n2342) );
OAI21X4TS U3456 ( .A0(n2281), .A1(n2313), .B0(n2280), .Y(n2353) );
AOI21X2TS U3457 ( .A0(n2330), .A1(n2347), .B0(n2353), .Y(n2283) );
XOR2X1TS U3458 ( .A(n2300), .B(n2288), .Y(n2289) );
XOR2X1TS U3459 ( .A(n2307), .B(n2306), .Y(n2311) );
XOR2X1TS U3460 ( .A(n2309), .B(n2308), .Y(n2310) );
NAND2X1TS U3461 ( .A(n2334), .B(n2341), .Y(n2344) );
INVX2TS U3462 ( .A(n3454), .Y(n2357) );
CMPR32X2TS U3463 ( .A(Op_MY[16]), .B(mult_x_23_n521), .C(n2378), .CO(n2389),
.S(n2381) );
OAI22X1TS U3464 ( .A0(n883), .A1(n571), .B0(n3668), .B1(n3665), .Y(n2386) );
OAI22X1TS U3465 ( .A0(n2483), .A1(n1153), .B0(n2481), .B1(mult_x_23_n546),
.Y(n2385) );
OAI22X1TS U3466 ( .A0(n698), .A1(n2387), .B0(n865), .B1(n1147), .Y(n2870) );
OAI22X1TS U3467 ( .A0(n2396), .A1(n861), .B0(n2410), .B1(n895), .Y(n2407) );
ADDFHX4TS U3468 ( .A(n2407), .B(n2406), .CI(n2405), .CO(n2425), .S(n2755) );
NAND2BX1TS U3469 ( .AN(n868), .B(n2463), .Y(n2444) );
XNOR2X1TS U3470 ( .A(n3695), .B(Op_MY[12]), .Y(n2449) );
OAI22X1TS U3471 ( .A0(n1156), .A1(n2454), .B0(n2464), .B1(n835), .Y(n2465)
);
ADDFHX4TS U3472 ( .A(n2534), .B(n2533), .CI(n2532), .CO(n2720), .S(n2543) );
ADDFHX4TS U3473 ( .A(n2545), .B(n2544), .CI(n2543), .CO(n2736), .S(n2096) );
NAND2X1TS U3474 ( .A(n2564), .B(n1329), .Y(n2565) );
ADDFHX4TS U3475 ( .A(n2575), .B(n2574), .CI(n2573), .CO(n2717), .S(n2719) );
ADDFHX4TS U3476 ( .A(n2578), .B(n2577), .CI(n2576), .CO(n2568), .S(n2716) );
XNOR2X1TS U3477 ( .A(n3769), .B(n3770), .Y(n2581) );
XNOR2X1TS U3478 ( .A(n3776), .B(n3777), .Y(n2582) );
AOI22X1TS U3479 ( .A0(n1350), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n3353), .Y(n2591) );
AOI2BB2X1TS U3480 ( .B0(n3379), .B1(n241), .A0N(n900), .A1N(n3958), .Y(n2590) );
NAND2X1TS U3481 ( .A(n3335), .B(n240), .Y(n2589) );
XNOR2X4TS U3482 ( .A(n2653), .B(mult_x_55_n446), .Y(n2613) );
OAI22X1TS U3483 ( .A0(n2652), .A1(n2606), .B0(n2605), .B1(n2650), .Y(n2610)
);
ADDFHX4TS U3484 ( .A(n2721), .B(n2720), .CI(n2719), .CO(n2738), .S(n2737) );
ADDFHX4TS U3485 ( .A(n2727), .B(n2726), .CI(n2725), .CO(n2731), .S(n2730) );
MX2X6TS U3486 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n3129), .Y(n346) );
XOR2X1TS U3487 ( .A(n3577), .B(n346), .Y(n3632) );
XNOR2X1TS U3488 ( .A(mult_x_55_n570), .B(n346), .Y(n3642) );
OR2X2TS U3489 ( .A(n2762), .B(n2761), .Y(n2763) );
XOR2X1TS U3490 ( .A(mult_x_55_n568), .B(n348), .Y(n3635) );
MX2X6TS U3491 ( .A(Data_MX[7]), .B(n4047), .S0(n3129), .Y(mult_x_55_n567) );
XNOR2X1TS U3492 ( .A(mult_x_55_n567), .B(n319), .Y(n3636) );
XNOR2X1TS U3493 ( .A(mult_x_55_n567), .B(n320), .Y(n3638) );
INVX2TS U3494 ( .A(n2768), .Y(n2770) );
NAND2X1TS U3495 ( .A(n2770), .B(n2769), .Y(n2771) );
NAND2X2TS U3496 ( .A(n2773), .B(n2772), .Y(mult_x_55_n9) );
NAND2X2TS U3497 ( .A(n2798), .B(n2774), .Y(mult_x_55_n8) );
OAI22X1TS U3498 ( .A0(n852), .A1(n2789), .B0(n700), .B1(mult_x_55_n559), .Y(
n2840) );
CMPR32X2TS U3499 ( .A(n2792), .B(n2791), .C(n2790), .CO(n2839), .S(n2787) );
MX2X4TS U3500 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n3062), .Y(mult_x_55_a_0_)
);
INVX2TS U3501 ( .A(mult_x_55_a_0_), .Y(n3637) );
AOI21X1TS U3502 ( .A0(n2805), .A1(n2804), .B0(n2803), .Y(n2806) );
NAND2X1TS U3503 ( .A(n2823), .B(n2822), .Y(n2824) );
NAND2X1TS U3504 ( .A(n2828), .B(n2827), .Y(n2829) );
XNOR2X1TS U3505 ( .A(n2830), .B(n2829), .Y(Sgf_operation_EVEN1_right_N6) );
XOR3X2TS U3506 ( .A(n2845), .B(n2844), .C(n2843), .Y(n2846) );
OR2X2TS U3507 ( .A(n2847), .B(n2846), .Y(n2849) );
MX2X6TS U3508 ( .A(Data_MX[10]), .B(n4051), .S0(n746), .Y(n354) );
XNOR2X1TS U3509 ( .A(n1174), .B(n3616), .Y(n3621) );
XNOR2X1TS U3510 ( .A(mult_x_55_n568), .B(n350), .Y(n3579) );
MX2X4TS U3511 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n2945), .Y(mult_x_55_a_8_)
);
XNOR2X1TS U3512 ( .A(mult_x_55_n568), .B(n322), .Y(n3576) );
MX2X4TS U3513 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n3129), .Y(mult_x_55_n566)
);
XNOR2X1TS U3514 ( .A(n3577), .B(n320), .Y(n3628) );
XNOR2X1TS U3515 ( .A(n3577), .B(n348), .Y(n3615) );
XNOR2X1TS U3516 ( .A(n3577), .B(n319), .Y(n3634) );
XNOR2X1TS U3517 ( .A(n3577), .B(n321), .Y(n3578) );
NAND2BX1TS U3518 ( .AN(n1461), .B(n2851), .Y(n2852) );
NAND2X1TS U3519 ( .A(n2854), .B(n2853), .Y(n2855) );
MX2X6TS U3520 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n2945), .Y(
mult_x_23_n551) );
INVX4TS U3521 ( .A(mult_x_23_n551), .Y(n3694) );
XNOR2X1TS U3522 ( .A(n3694), .B(n2857), .Y(n3702) );
MX2X6TS U3523 ( .A(Data_MX[21]), .B(n4052), .S0(n3062), .Y(mult_x_23_n550)
);
XNOR2X1TS U3524 ( .A(n3710), .B(n2857), .Y(n3719) );
XNOR2X1TS U3525 ( .A(mult_x_23_n550), .B(mult_x_23_n525), .Y(n3720) );
XNOR2X1TS U3526 ( .A(mult_x_23_n551), .B(n4039), .Y(n3729) );
NAND2X1TS U3527 ( .A(n2860), .B(n2859), .Y(n2862) );
XNOR2X1TS U3528 ( .A(n2862), .B(n2861), .Y(Sgf_operation_EVEN1_left_N3) );
XNOR2X1TS U3529 ( .A(mult_x_23_n553), .B(n333), .Y(n3701) );
NOR2BX1TS U3530 ( .AN(n868), .B(n835), .Y(Sgf_operation_EVEN1_left_N0) );
OAI22X1TS U3531 ( .A0(n883), .A1(mult_x_23_n517), .B0(n3668), .B1(n3664),
.Y(n2874) );
OAI22X1TS U3532 ( .A0(n1252), .A1(n1147), .B0(mult_x_23_n540), .B1(
mult_x_23_n545), .Y(n2873) );
AO21X1TS U3533 ( .A0(n1252), .A1(n865), .B0(mult_x_23_n545), .Y(n2882) );
MX2X6TS U3534 ( .A(Data_MX[22]), .B(n4053), .S0(n3129), .Y(n366) );
CMPR32X2TS U3535 ( .A(n3665), .B(mult_x_23_n517), .C(n2883), .CO(n2949), .S(
n2881) );
INVX2TS U3536 ( .A(n2934), .Y(n2886) );
NAND2X2TS U3537 ( .A(n2885), .B(n2884), .Y(n2933) );
NAND2X1TS U3538 ( .A(n3736), .B(n2929), .Y(mult_x_23_n11) );
CLKINVX1TS U3539 ( .A(n2895), .Y(mult_x_23_n109) );
INVX4TS U3540 ( .A(n2896), .Y(n2898) );
INVX4TS U3541 ( .A(n2915), .Y(n2917) );
AOI21X4TS U3542 ( .A0(n1234), .A1(n2936), .B0(n2921), .Y(n2925) );
INVX2TS U3543 ( .A(n2926), .Y(n2928) );
MXI2X4TS U3544 ( .A(n2942), .B(n3925), .S0(n746), .Y(
DP_OP_111J16_123_4462_n880) );
XNOR2X1TS U3545 ( .A(n3694), .B(n2943), .Y(n3722) );
XNOR2X2TS U3546 ( .A(mult_x_23_n550), .B(n366), .Y(n3693) );
INVX2TS U3547 ( .A(n366), .Y(n2944) );
MX2X6TS U3548 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n3062), .Y(
mult_x_23_n552) );
XOR2X1TS U3549 ( .A(mult_x_23_n552), .B(n2865), .Y(n3697) );
XNOR2X1TS U3550 ( .A(mult_x_23_n551), .B(n1475), .Y(n3705) );
XNOR2X1TS U3551 ( .A(mult_x_23_n552), .B(n4039), .Y(n3718) );
XNOR2X1TS U3552 ( .A(mult_x_23_n552), .B(mult_x_23_n518), .Y(n3715) );
NAND2X1TS U3553 ( .A(n739), .B(n2946), .Y(n2948) );
CMPR32X2TS U3554 ( .A(n3741), .B(n3742), .C(n2949), .CO(n2952), .S(n2884) );
AND2X2TS U3555 ( .A(n883), .B(n3668), .Y(n2950) );
XNOR2X1TS U3556 ( .A(n2950), .B(n3664), .Y(n2951) );
NAND2X1TS U3557 ( .A(n2952), .B(n2951), .Y(n2953) );
CLKBUFX3TS U3558 ( .A(n875), .Y(n4057) );
BUFX3TS U3559 ( .A(n4057), .Y(n3975) );
AOI21X4TS U3560 ( .A0(n2979), .A1(n712), .B0(n2964), .Y(n2967) );
XNOR2X4TS U3561 ( .A(n2979), .B(n2978), .Y(n2998) );
OAI21X4TS U3562 ( .A0(n579), .A1(n2993), .B0(n2992), .Y(n2997) );
INVX2TS U3563 ( .A(n3026), .Y(n3028) );
NAND2X1TS U3564 ( .A(n3034), .B(n3033), .Y(n3035) );
NAND2X2TS U3565 ( .A(n682), .B(n2960), .Y(add_x_19_n67) );
NAND2X1TS U3566 ( .A(n679), .B(n1780), .Y(n3054) );
NOR2X2TS U3567 ( .A(add_x_19_n67), .B(n3054), .Y(n3055) );
INVX2TS U3568 ( .A(add_x_19_n67), .Y(n3056) );
NAND2X2TS U3569 ( .A(n2962), .B(n3057), .Y(add_x_19_n104) );
INVX2TS U3570 ( .A(add_x_19_n104), .Y(n3058) );
NAND2X1TS U3571 ( .A(n3058), .B(n3060), .Y(add_x_19_n94) );
INVX2TS U3572 ( .A(n1798), .Y(n3059) );
NAND2X1TS U3573 ( .A(n3060), .B(n3059), .Y(n3061) );
NOR2X1TS U3574 ( .A(add_x_19_n104), .B(n3061), .Y(add_x_19_n85) );
BUFX3TS U3575 ( .A(n4072), .Y(n3973) );
XNOR2X1TS U3576 ( .A(n3136), .B(n3135), .Y(n3859) );
NOR2BX1TS U3577 ( .AN(n848), .B(n846), .Y(Sgf_operation_EVEN1_middle_N0) );
NAND2X1TS U3578 ( .A(n3064), .B(n3063), .Y(n3066) );
XNOR2X1TS U3579 ( .A(n3066), .B(n3065), .Y(Sgf_operation_EVEN1_middle_N5) );
NAND2X2TS U3580 ( .A(n3068), .B(n3067), .Y(n3070) );
XNOR2X1TS U3581 ( .A(n3070), .B(n3069), .Y(Sgf_operation_EVEN1_middle_N3) );
NAND2X1TS U3582 ( .A(n3073), .B(n3072), .Y(DP_OP_111J16_123_4462_n8) );
AND2X2TS U3583 ( .A(n3077), .B(n3188), .Y(Sgf_operation_EVEN1_middle_N1) );
INVX2TS U3584 ( .A(Data_MY[14]), .Y(n3105) );
INVX2TS U3585 ( .A(n3127), .Y(n3146) );
INVX2TS U3586 ( .A(n3125), .Y(n3106) );
XNOR2X1TS U3587 ( .A(n3108), .B(n3107), .Y(n3861) );
XNOR2X4TS U3588 ( .A(mult_x_23_n551), .B(mult_x_55_n567), .Y(n3798) );
NOR2X1TS U3589 ( .A(mult_x_23_n551), .B(mult_x_55_n567), .Y(n3109) );
XNOR2X1TS U3590 ( .A(n3139), .B(n3109), .Y(n3114) );
NAND2X1TS U3591 ( .A(n350), .B(n4039), .Y(n3112) );
OAI2BB1X1TS U3592 ( .A0N(n3110), .A1N(n2858), .B0(mult_x_55_n568), .Y(n3111)
);
INVX2TS U3593 ( .A(n356), .Y(n3116) );
XOR2X1TS U3594 ( .A(n3116), .B(n3136), .Y(n3117) );
NAND2X1TS U3595 ( .A(n3117), .B(n730), .Y(n3860) );
XOR2X2TS U3596 ( .A(n354), .B(n366), .Y(n3160) );
XNOR2X1TS U3597 ( .A(n3160), .B(n708), .Y(n3121) );
NAND2X1TS U3598 ( .A(mult_x_55_a_8_), .B(n1475), .Y(n3118) );
NOR2X1TS U3599 ( .A(mult_x_23_n553), .B(mult_x_55_n569), .Y(n3122) );
XNOR2X1TS U3600 ( .A(n3128), .B(n3122), .Y(n3124) );
MX2X4TS U3601 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n3062), .Y(n328) );
NAND2X2TS U3602 ( .A(DP_OP_111J16_123_4462_n880), .B(
DP_OP_111J16_123_4462_n891), .Y(n3804) );
XNOR2X1TS U3603 ( .A(n3152), .B(n3134), .Y(n3138) );
NAND2X1TS U3604 ( .A(n3136), .B(n3135), .Y(n3137) );
XOR2X1TS U3605 ( .A(n3138), .B(n3137), .Y(n3842) );
XOR2X1TS U3606 ( .A(mult_x_23_n551), .B(n1475), .Y(n3140) );
XOR2X1TS U3607 ( .A(n3141), .B(n3148), .Y(n3858) );
XNOR2X1TS U3608 ( .A(n3148), .B(n3147), .Y(n3847) );
XNOR2X1TS U3609 ( .A(n3155), .B(n3154), .Y(n3855) );
XNOR2X1TS U3610 ( .A(n3158), .B(n3157), .Y(n3866) );
INVX2TS U3611 ( .A(n354), .Y(n3159) );
XNOR2X1TS U3612 ( .A(mult_x_23_n550), .B(n3159), .Y(n3161) );
INVX2TS U3613 ( .A(n3163), .Y(n3165) );
NAND2X1TS U3614 ( .A(n3165), .B(n3164), .Y(n3166) );
XOR2X1TS U3615 ( .A(n3166), .B(n3796), .Y(n3865) );
OAI21X1TS U3616 ( .A0(n354), .A1(n366), .B0(mult_x_55_n566), .Y(n3168) );
INVX2TS U3617 ( .A(n3169), .Y(n3171) );
NAND2X1TS U3618 ( .A(n3171), .B(n3170), .Y(n3173) );
CMPR32X2TS U3619 ( .A(n3176), .B(n3175), .C(n3174), .CO(n3178), .S(n3074) );
OR2X2TS U3620 ( .A(n3178), .B(n741), .Y(n3180) );
XNOR2X1TS U3621 ( .A(n3181), .B(mult_x_55_n565), .Y(n3836) );
NOR2X2TS U3622 ( .A(mult_x_23_n518), .B(n320), .Y(n3839) );
XOR2X1TS U3623 ( .A(mult_x_23_n552), .B(n4039), .Y(n3184) );
OR2X2TS U3624 ( .A(n324), .B(n312), .Y(n3881) );
INVX2TS U3625 ( .A(n3185), .Y(n3187) );
NAND2X1TS U3626 ( .A(n3187), .B(n3186), .Y(n3189) );
CLKBUFX2TS U3627 ( .A(n4057), .Y(n3976) );
CLKBUFX2TS U3628 ( .A(n4063), .Y(n4066) );
BUFX3TS U3629 ( .A(n869), .Y(n3972) );
NOR2X2TS U3630 ( .A(n3191), .B(n3497), .Y(ready) );
INVX2TS U3631 ( .A(ack_FSM), .Y(n3192) );
MXI2X1TS U3632 ( .A(n3502), .B(n3194), .S0(n1089), .Y(n3195) );
NAND2X1TS U3633 ( .A(n3198), .B(n3195), .Y(n376) );
NAND2X1TS U3634 ( .A(n3394), .B(zero_flag), .Y(n3196) );
NAND4X1TS U3635 ( .A(n3198), .B(n3197), .C(n3353), .D(n3196), .Y(n379) );
INVX2TS U3636 ( .A(n3200), .Y(n3520) );
XNOR2X1TS U3637 ( .A(n3520), .B(Sgf_normalized_result[2]), .Y(n3199) );
XOR2X1TS U3638 ( .A(n3210), .B(Sgf_normalized_result[4]), .Y(n3201) );
CLKMX2X2TS U3639 ( .A(n3201), .B(Add_result[4]), .S0(n843), .Y(n302) );
NAND2X1TS U3640 ( .A(n736), .B(n3202), .Y(n3203) );
XOR2X1TS U3641 ( .A(n3203), .B(n3505), .Y(n3204) );
CLKMX2X2TS U3642 ( .A(n3204), .B(P_Sgf[13]), .S0(n4055), .Y(n228) );
NAND2X1TS U3643 ( .A(n3210), .B(n3950), .Y(n3205) );
CLKMX2X2TS U3644 ( .A(n3206), .B(Add_result[5]), .S0(n3413), .Y(n301) );
NAND2X1TS U3645 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[6]),
.Y(n3209) );
NAND2X1TS U3646 ( .A(n3207), .B(Sgf_normalized_result[6]), .Y(n3208) );
XNOR2X1TS U3647 ( .A(n3211), .B(n3939), .Y(n3212) );
XNOR2X1TS U3648 ( .A(n3433), .B(n3937), .Y(n3218) );
NOR4X1TS U3649 ( .A(n235), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[17]), .Y(
n3222) );
NOR4X1TS U3650 ( .A(P_Sgf[16]), .B(P_Sgf[14]), .C(P_Sgf[15]), .D(P_Sgf[13]),
.Y(n3221) );
NOR4X1TS U3651 ( .A(P_Sgf[12]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n3220) );
NOR4X1TS U3652 ( .A(P_Sgf[5]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[8]), .Y(
n3224) );
NOR4X1TS U3653 ( .A(P_Sgf[1]), .B(P_Sgf[2]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n3223) );
NAND2X1TS U3654 ( .A(n3375), .B(n3229), .Y(n3230) );
NAND2X1TS U3655 ( .A(n3375), .B(n3233), .Y(n3235) );
AOI22X1TS U3656 ( .A0(n3383), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n3388), .Y(n3239) );
AOI22X1TS U3657 ( .A0(n3383), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n3353), .Y(n3243) );
NAND2X1TS U3658 ( .A(n3392), .B(n239), .Y(n3241) );
NAND3X1TS U3659 ( .A(n3243), .B(n3242), .C(n3241), .Y(n192) );
XOR2X1TS U3660 ( .A(n3378), .B(n3755), .Y(n3245) );
AOI21X1TS U3661 ( .A0(n3782), .A1(n3783), .B0(n3784), .Y(n3246) );
XNOR2X1TS U3662 ( .A(n3247), .B(n3766), .Y(n3248) );
AOI22X1TS U3663 ( .A0(n3383), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n3353), .Y(n3252) );
NAND2X1TS U3664 ( .A(n3392), .B(n242), .Y(n3250) );
XNOR2X1TS U3665 ( .A(n3253), .B(n3760), .Y(n3254) );
AOI22X1TS U3666 ( .A0(n3383), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n3353), .Y(n3260) );
NAND2X1TS U3667 ( .A(n2588), .B(n245), .Y(n3258) );
NAND3X1TS U3668 ( .A(n3260), .B(n3259), .C(n3258), .Y(n198) );
AOI22X1TS U3669 ( .A0(n1350), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n3353), .Y(n3265) );
AOI2BB2X1TS U3670 ( .B0(n3391), .B1(n242), .A0N(n900), .A1N(n3957), .Y(n3264) );
NAND2X1TS U3671 ( .A(n2588), .B(n241), .Y(n3263) );
NAND3X1TS U3672 ( .A(n3265), .B(n3264), .C(n3263), .Y(n194) );
OAI21X1TS U3673 ( .A0(n3378), .A1(n582), .B0(n3283), .Y(n3267) );
XNOR2X1TS U3674 ( .A(n3267), .B(n3761), .Y(n3268) );
AOI22X1TS U3675 ( .A0(n3383), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n3388), .Y(n3271) );
NAND2X1TS U3676 ( .A(n2588), .B(n246), .Y(n3269) );
NAND3X1TS U3677 ( .A(n3271), .B(n3270), .C(n3269), .Y(n199) );
XNOR2X1TS U3678 ( .A(n3272), .B(n3759), .Y(n3273) );
AOI22X1TS U3679 ( .A0(n1350), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n3353), .Y(n3276) );
NAND2X1TS U3680 ( .A(n3335), .B(n243), .Y(n3274) );
NAND3X1TS U3681 ( .A(n3276), .B(n3275), .C(n3274), .Y(n196) );
NAND2X1TS U3682 ( .A(n3278), .B(n581), .Y(n3280) );
AOI21X1TS U3683 ( .A0(n3291), .A1(n3278), .B0(n3277), .Y(n3279) );
NAND2X1TS U3684 ( .A(n581), .B(n3773), .Y(n3285) );
AOI22X1TS U3685 ( .A0(n1350), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n3388), .Y(n3290) );
NAND2X1TS U3686 ( .A(n3392), .B(n249), .Y(n3288) );
NAND3X1TS U3687 ( .A(n3290), .B(n3289), .C(n3288), .Y(n202) );
AOI21X1TS U3688 ( .A0(n3291), .A1(n611), .B0(n3763), .Y(n3292) );
AOI22X1TS U3689 ( .A0(n3389), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n3388), .Y(n3298) );
AOI2BB2X1TS U3690 ( .B0(n3384), .B1(n249), .A0N(n900), .A1N(n3923), .Y(n3297) );
NAND2X1TS U3691 ( .A(n3392), .B(n248), .Y(n3296) );
NAND3X1TS U3692 ( .A(n3298), .B(n3297), .C(n3296), .Y(n201) );
NAND2X1TS U3693 ( .A(n1329), .B(n3304), .Y(n3306) );
AOI22X1TS U3694 ( .A0(n1350), .A1(n287), .B0(Sgf_normalized_result[18]),
.B1(n3361), .Y(n3312) );
NAND2X1TS U3695 ( .A(n2588), .B(n256), .Y(n3310) );
AOI22X1TS U3696 ( .A0(n3383), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n3361), .Y(n3318) );
NAND2X1TS U3697 ( .A(n3392), .B(n257), .Y(n3316) );
AOI22X1TS U3698 ( .A0(n1350), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n3361), .Y(n3328) );
NAND2X1TS U3699 ( .A(n2588), .B(n259), .Y(n3326) );
AOI22X1TS U3700 ( .A0(n3389), .A1(Add_result[21]), .B0(n1018), .B1(n3361),
.Y(n3331) );
AOI2BB2X1TS U3701 ( .B0(n3379), .B1(n259), .A0N(n901), .A1N(n3913), .Y(n3330) );
AOI22X1TS U3702 ( .A0(n3389), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n3361), .Y(n3334) );
NAND2X1TS U3703 ( .A(n3392), .B(n255), .Y(n3332) );
NAND3X1TS U3704 ( .A(n3334), .B(n3333), .C(n3332), .Y(n208) );
AOI22X1TS U3705 ( .A0(n1350), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n3388), .Y(n3338) );
NAND2X1TS U3706 ( .A(n3335), .B(n247), .Y(n3336) );
AOI22X1TS U3707 ( .A0(n3383), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n3361), .Y(n3349) );
NAND2X1TS U3708 ( .A(n3392), .B(n260), .Y(n3347) );
NAND3X1TS U3709 ( .A(n3349), .B(n3348), .C(n3347), .Y(n213) );
AOI22X1TS U3710 ( .A0(n1350), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n3388), .Y(n3352) );
NAND2X1TS U3711 ( .A(n3392), .B(n238), .Y(n3350) );
NAND3X1TS U3712 ( .A(n3352), .B(n3351), .C(n3350), .Y(n191) );
AOI22X1TS U3713 ( .A0(n3389), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n3353), .Y(n3356) );
NAND2X1TS U3714 ( .A(n3392), .B(n244), .Y(n3354) );
NAND3X1TS U3715 ( .A(n3356), .B(n3355), .C(n3354), .Y(n197) );
NAND2X1TS U3716 ( .A(n3433), .B(Sgf_normalized_result[8]), .Y(n3357) );
AOI22X1TS U3717 ( .A0(n1350), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n3388), .Y(n3367) );
NAND2X1TS U3718 ( .A(n2588), .B(n250), .Y(n3365) );
NAND3X1TS U3719 ( .A(n3367), .B(n3366), .C(n3365), .Y(n203) );
NAND2X1TS U3720 ( .A(n3375), .B(add_x_19_n122), .Y(n3371) );
AOI22X1TS U3721 ( .A0(n3389), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n3388), .Y(n3382) );
NAND2X1TS U3722 ( .A(n3335), .B(n252), .Y(n3380) );
NAND3X1TS U3723 ( .A(n3382), .B(n3381), .C(n3380), .Y(n205) );
AOI22X1TS U3724 ( .A0(n3383), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n3388), .Y(n3387) );
NAND2X1TS U3725 ( .A(n2588), .B(n251), .Y(n3385) );
NAND3X1TS U3726 ( .A(n3387), .B(n3386), .C(n3385), .Y(n204) );
NAND2X1TS U3727 ( .A(n3392), .B(n253), .Y(n3393) );
NAND2X1TS U3728 ( .A(n3394), .B(n3952), .Y(n3396) );
NAND2X1TS U3729 ( .A(n3433), .B(n3416), .Y(n3398) );
INVX2TS U3730 ( .A(n3407), .Y(n3400) );
NAND2X1TS U3731 ( .A(n3433), .B(n3400), .Y(n3401) );
XNOR2X1TS U3732 ( .A(n435), .B(n3404), .Y(n3405) );
NAND2X1TS U3733 ( .A(n3433), .B(n3408), .Y(n3409) );
NAND2X1TS U3734 ( .A(Sgf_normalized_result[14]), .B(
Sgf_normalized_result[15]), .Y(n3411) );
XNOR2X1TS U3735 ( .A(n3479), .B(n3938), .Y(n3414) );
NAND2X1TS U3736 ( .A(n3433), .B(n3417), .Y(n3418) );
NAND2X1TS U3737 ( .A(n3433), .B(n3420), .Y(n3421) );
NAND2X1TS U3738 ( .A(n3429), .B(Sgf_normalized_result[14]), .Y(n3430) );
NAND2X1TS U3739 ( .A(n3433), .B(n3432), .Y(n3434) );
XOR2X1TS U3740 ( .A(n3439), .B(n3946), .Y(n3440) );
XOR2X1TS U3741 ( .A(n3443), .B(n3933), .Y(n3444) );
NAND2X1TS U3742 ( .A(n3479), .B(n446), .Y(n3446) );
XOR2X1TS U3743 ( .A(n3446), .B(n3934), .Y(n3447) );
AND2X2TS U3744 ( .A(n3455), .B(n3454), .Y(n3457) );
BUFX16TS U3745 ( .A(n3459), .Y(n3510) );
INVX2TS U3746 ( .A(n3469), .Y(n3471) );
NAND2X1TS U3747 ( .A(n3471), .B(n3470), .Y(n3472) );
NAND2X1TS U3748 ( .A(Sgf_normalized_result[22]), .B(
Sgf_normalized_result[23]), .Y(n3474) );
INVX2TS U3749 ( .A(n3481), .Y(n3482) );
NAND2X1TS U3750 ( .A(n3486), .B(n3485), .Y(n3487) );
INVX2TS U3751 ( .A(n3490), .Y(n3492) );
NAND2X1TS U3752 ( .A(n3492), .B(n3491), .Y(n3493) );
XOR2X1TS U3753 ( .A(n3494), .B(n3493), .Y(n3495) );
AOI21X1TS U3754 ( .A0(n1159), .A1(n3497), .B0(n3496), .Y(n3498) );
MXI2X1TS U3755 ( .A(n1456), .B(n1449), .S0(n3510), .Y(n226) );
OR2X2TS U3756 ( .A(n3504), .B(n3503), .Y(n3506) );
NAND2X1TS U3757 ( .A(n3506), .B(n3505), .Y(n3507) );
MXI2X1TS U3758 ( .A(n3507), .B(n1448), .S0(n3510), .Y(n227) );
CLKBUFX2TS U3759 ( .A(n3977), .Y(n3974) );
NAND2X1TS U3760 ( .A(n3557), .B(n3900), .Y(n375) );
MXI2X1TS U3761 ( .A(n1802), .B(n3940), .S0(n4055), .Y(n215) );
MXI2X1TS U3762 ( .A(n694), .B(n4068), .S0(n3510), .Y(n225) );
MXI2X1TS U3763 ( .A(Sgf_normalized_result[0]), .B(n4069), .S0(n3413), .Y(
n306) );
XNOR2X1TS U3764 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n3509) );
MXI2X1TS U3765 ( .A(n1827), .B(n3969), .S0(n4055), .Y(n222) );
MXI2X1TS U3766 ( .A(n1829), .B(n3961), .S0(n4055), .Y(n224) );
MXI2X1TS U3767 ( .A(n1816), .B(n3968), .S0(n3510), .Y(n221) );
MXI2X1TS U3768 ( .A(n1813), .B(n3966), .S0(n3510), .Y(n219) );
MXI2X1TS U3769 ( .A(n1803), .B(n3963), .S0(n3510), .Y(n216) );
MXI2X1TS U3770 ( .A(n1815), .B(n3967), .S0(n3510), .Y(n220) );
MXI2X1TS U3771 ( .A(n1831), .B(n3970), .S0(n3510), .Y(n223) );
BUFX8TS U3772 ( .A(n3524), .Y(n3515) );
AO22X2TS U3773 ( .A0(n3515), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n3529), .Y(n190) );
NAND2X1TS U3774 ( .A(n3518), .B(n3517), .Y(n3519) );
MXI2X1TS U3775 ( .A(n3519), .B(n3971), .S0(n3529), .Y(n262) );
XOR2X1TS U3776 ( .A(n3521), .B(n3929), .Y(n3522) );
CLKMX2X2TS U3777 ( .A(n3522), .B(Add_result[3]), .S0(n3413), .Y(n303) );
AOI2BB2X1TS U3778 ( .B0(n3530), .B1(n3898), .A0N(n3523), .A1N(
final_result_ieee[25]), .Y(n268) );
AOI2BB2X1TS U3779 ( .B0(n3530), .B1(n3897), .A0N(n3523), .A1N(
final_result_ieee[27]), .Y(n266) );
AOI2BB2X1TS U3780 ( .B0(n4070), .B1(n3530), .A0N(n3523), .A1N(
final_result_ieee[28]), .Y(n265) );
AOI2BB2X1TS U3781 ( .B0(n3530), .B1(n3896), .A0N(n3523), .A1N(
final_result_ieee[24]), .Y(n269) );
AOI2BB2X1TS U3782 ( .B0(n3530), .B1(n3899), .A0N(n3523), .A1N(
final_result_ieee[26]), .Y(n267) );
AOI2BB2X1TS U3783 ( .B0(n3530), .B1(n3901), .A0N(n3523), .A1N(
final_result_ieee[23]), .Y(n270) );
AOI2BB2X1TS U3784 ( .B0(n3530), .B1(n3903), .A0N(n3523), .A1N(
final_result_ieee[29]), .Y(n264) );
AOI2BB2X1TS U3785 ( .B0(n3530), .B1(n3902), .A0N(n3523), .A1N(
final_result_ieee[30]), .Y(n263) );
AO22X1TS U3786 ( .A0(n3515), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[16]), .B1(n3529), .Y(n174) );
AO22X2TS U3787 ( .A0(n3515), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[15]), .B1(n3529), .Y(n175) );
AO22X2TS U3788 ( .A0(n3515), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[19]), .B1(n3529), .Y(n171) );
NOR4X1TS U3789 ( .A(Op_MY[26]), .B(Op_MY[25]), .C(Op_MY[28]), .D(Op_MY[27]),
.Y(n3537) );
NOR4X1TS U3790 ( .A(n3533), .B(Op_MY[22]), .C(Op_MY[16]), .D(Op_MY[18]), .Y(
n3536) );
NOR4X1TS U3791 ( .A(Op_MY[29]), .B(Op_MY[12]), .C(Op_MY[0]), .D(Op_MY[30]),
.Y(n3535) );
NAND4X1TS U3792 ( .A(n3537), .B(n3536), .C(n3535), .D(n3534), .Y(n3556) );
AND4X2TS U3793 ( .A(n4026), .B(n4036), .C(n4037), .D(n4038), .Y(n3542) );
NOR4X1TS U3794 ( .A(Op_MY[7]), .B(Op_MY[8]), .C(Op_MY[9]), .D(n3539), .Y(
n3541) );
AND4X2TS U3795 ( .A(n4023), .B(n4027), .C(n572), .D(n4028), .Y(n3540) );
NAND4X1TS U3796 ( .A(n3543), .B(n3542), .C(n3541), .D(n3540), .Y(n3555) );
AND4X2TS U3797 ( .A(n4031), .B(n3997), .C(n4032), .D(n3998), .Y(n3547) );
NOR4BBX1TS U3798 ( .AN(n4041), .BN(n4042), .C(n4040), .D(n4049), .Y(n3546)
);
AND4X1TS U3799 ( .A(n835), .B(n4009), .C(n4010), .D(n3959), .Y(n3544) );
NAND4X1TS U3800 ( .A(n3547), .B(n3546), .C(n3545), .D(n3544), .Y(n3554) );
NOR4X1TS U3801 ( .A(Op_MX[26]), .B(Op_MX[25]), .C(Op_MX[28]), .D(Op_MX[27]),
.Y(n3552) );
AND4X2TS U3802 ( .A(n3548), .B(n3993), .C(n733), .D(n3960), .Y(n3551) );
AND4X2TS U3803 ( .A(n3995), .B(n3996), .C(n4043), .D(n4044), .Y(n3550) );
AND3X2TS U3804 ( .A(n3951), .B(n3981), .C(n3982), .Y(n3549) );
NAND4X1TS U3805 ( .A(n3552), .B(n3551), .C(n3550), .D(n3549), .Y(n3553) );
OAI22X1TS U3806 ( .A0(n3556), .A1(n3555), .B0(n3554), .B1(n3553), .Y(n3558)
);
CLKMX2X2TS U3807 ( .A(n3558), .B(zero_flag), .S0(n3557), .Y(n311) );
MXI2X1TS U3808 ( .A(n3560), .B(n3896), .S0(n3559), .Y(n279) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk1.tcl_KOA_2STAGE_syn.sdf");
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
data_out,
// Inputs
wr, wa, rst_l, rd, ra, data_in, clk
);
input clk;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [31:0] data_in; // To sub of reg_1r1w.v
input [7:0] ra; // To sub of reg_1r1w.v
input rd; // To sub of reg_1r1w.v
input rst_l; // To sub of reg_1r1w.v
input [7:0] wa; // To sub of reg_1r1w.v
input wr; // To sub of reg_1r1w.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] data_out; // From sub of reg_1r1w.v
// End of automatics
reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8))
sub
(/*AUTOINST*/
// Outputs
.data_out (data_out[31:0]),
// Inputs
.data_in (data_in[31:0]),
.ra (ra[7:0]),
.wa (wa[7:0]),
.wr (wr),
.rd (rd),
.clk (clk),
.rst_l (rst_l));
endmodule
module reg_1r1w
#(
parameter WIDTH=32,
parameter ADRWID=10,
parameter DEPTH=1024,
parameter RST=0
)
(/*AUTOARG*/
// Outputs
data_out,
// Inputs
data_in, ra, wa, wr, rd, clk, rst_l
);
input [WIDTH-1:0] data_in;
input [ADRWID-1:0] ra;
input [ADRWID-1:0] wa;
input wr;
input rd;
input clk;
input rst_l;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] array [DEPTH-1:0];
reg [ADRWID-1:0] ra_r, wa_r;
reg [WIDTH-1:0] data_in_r;
reg wr_r;
reg rd_r;
integer x;
// Message 679
always @(posedge clk) begin
int tmp = x + 1;
if (tmp !== x + 1) $stop;
end
always @(posedge clk or negedge rst_l) begin
if (!rst_l) begin
for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE
if (RST == 1) begin
array[x] <= 0;
end
end
ra_r <= 0;
wa_r <= 0;
wr_r <= 0;
rd_r <= 0;
data_in_r <= 0;
end
else begin
ra_r <= ra;
wa_r <= wa;
wr_r <= wr;
rd_r <= rd;
data_in_r <= data_in;
if (wr_r) array[wa_r] <= data_in_r;
end
end
endmodule
// Local Variables:
// verilog-auto-inst-param-value: t
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o2bb2a (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2BB2A_PP_SYMBOL_V
|
module BigSDRAM(clock0,clock180,clock270,reset,leds,ddr_clock0,ddr_clock90,ddr_clock270,ddr_cke,ddr_csn,ddr_rasn,ddr_casn,ddr_wen,ddr_ba,ddr_addr,ddr_dm,ddr_dq,ddr_dqs);
input wire clock0;
input wire clock180;
input wire clock270;
input wire reset;
output wire [7:0] leds;
input wire ddr_clock0;
input wire ddr_clock90;
input wire ddr_clock270;
output wire ddr_cke;
output wire ddr_csn;
output wire ddr_rasn;
output wire ddr_casn;
output wire ddr_wen;
output wire [1:0] ddr_ba;
output wire [12:0] ddr_addr;
output wire [1:0] ddr_dm;
inout wire [15:0] ddr_dq;
inout wire [1:0] ddr_dqs;
wire [7:0] seq_next;
wire [11:0] seq_oreg;
wire [7:0] seq_oreg_wen;
wire [19:0] coderom_data_o;
wire [4095:0] coderomtext_data_o;
wire [31:0] ddrctl_page;
wire ddrctl_ready;
wire swc_ready;
Seq
seq (.clock(clock0),
.reset(reset),
.inst(coderom_data_o),
.inst_text(coderomtext_data_o),
.inst_en(1),
.ireg_0(ddrctl_page[7:0]),
.ireg_1({7'h00,ddrctl_ready}),
.ireg_2({7'h00,swc_ready}),
.ireg_3(8'h00),
.next(seq_next),
.oreg(seq_oreg),
.oreg_wen(seq_oreg_wen));
BigSDRAMRom
coderom (.addr(seq_next),
.data_o(coderom_data_o));
`ifdef SIM
BigSDRAMRomText
coderomtext (.addr(seq_next),
.data_o(coderomtext_data_o));
`endif
DdrCtl1
ddrctl (.clock0(clock180),
.clock90(clock270),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[0]),
.page(ddrctl_page),
.ready(ddrctl_ready),
.ddr_clock0(ddr_clock0),
.ddr_clock90(ddr_clock90),
.ddr_clock270(ddr_clock270),
.ddr_cke(ddr_cke),
.ddr_csn(ddr_csn),
.ddr_rasn(ddr_rasn),
.ddr_casn(ddr_casn),
.ddr_wen(ddr_wen),
.ddr_ba(ddr_ba),
.ddr_addr(ddr_addr),
.ddr_dm(ddr_dm),
.ddr_dq(ddr_dq),
.ddr_dqs(ddr_dqs));
LedBank
ledbank (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[1]),
.leds(leds));
Swc
swc (.clock(clock180),
.reset(reset),
.inst(seq_oreg),
.inst_en(seq_oreg_wen[2]),
.ready(swc_ready));
endmodule // BigSDRAM
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : V5-Block Plus for PCI Express
// File : PIO_EP_MEM_ACCESS.v
//--
//-- Description: Endpoint Memory Access Unit. This module provides access functions
//-- to the Endpoint memory aperture.
//--
//-- Read Access: Module returns data for the specifed address and
//-- byte enables selected.
//--
//-- Write Access: Module accepts data, byte enables and updates
//-- data when write enable is asserted. Modules signals write busy
//-- when data write is in progress.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
`define TCQ 1
`define PIO_MEM_ACCESS_WR_RST 3'b000
`define PIO_MEM_ACCESS_WR_WAIT 3'b001
`define PIO_MEM_ACCESS_WR_READ 3'b010
`define PIO_MEM_ACCESS_WR_WRITE 3'b100
module PIO_EP_MEM_ACCESS (
clk,
rst_n,
// Read Access
rd_addr_i, // I [10:0]
rd_be_i, // I [3:0]
rd_data_o, // O [31:0]
// Write Access
wr_addr_i, // I [10:0]
wr_be_i, // I [7:0]
wr_data_i, // I [31:0]
wr_en_i, // I
wr_busy_o // O
);
input clk;
input rst_n;
/*
* Read Port
*/
input [10:0] rd_addr_i;
input [3:0] rd_be_i;
output [31:0] rd_data_o;
/*
* Write Port
*/
input [10:0] wr_addr_i;
input [7:0] wr_be_i;
input [31:0] wr_data_i;
input wr_en_i;
output wr_busy_o;
wire [31:0] rd_data_o;
reg [31:0] rd_data_raw_o;
wire [31:0] rd_data0_o, rd_data1_o, rd_data2_o, rd_data3_o;
wire wr_busy_o;
reg write_en;
reg [31:0] post_wr_data;
reg [31:0] w_pre_wr_data;
reg [2:0] wr_mem_state;
reg [31:0] pre_wr_data;
wire [31:0] w_pre_wr_data0;
wire [31:0] w_pre_wr_data1;
wire [31:0] w_pre_wr_data2;
wire [31:0] w_pre_wr_data3;
reg [31:0] pre_wr_data0_q, pre_wr_data1_q, pre_wr_data2_q, pre_wr_data3_q;
reg [31:0] DW0, DW1, DW2;
/**
** Memory Write Process
**/
/*
* Extract current data bytes. These need to be swizzled
* BRAM storage format :
* data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
*/
wire [7:0] w_pre_wr_data_b3 = pre_wr_data[31:24];
wire [7:0] w_pre_wr_data_b2 = pre_wr_data[23:16];
wire [7:0] w_pre_wr_data_b1 = pre_wr_data[15:08];
wire [7:0] w_pre_wr_data_b0 = pre_wr_data[07:00];
/*
* Extract new data bytes from payload
* TLP Payload format :
* data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
*/
wire [7:0] w_wr_data_b3 = wr_data_i[07:00];
wire [7:0] w_wr_data_b2 = wr_data_i[15:08];
wire [7:0] w_wr_data_b1 = wr_data_i[23:16];
wire [7:0] w_wr_data_b0 = wr_data_i[31:24];
always @(posedge clk or negedge rst_n) begin
if ( !rst_n ) begin
pre_wr_data <= 32'b0;
post_wr_data <= 32'b0;
pre_wr_data <= 32'b0;
write_en <= 1'b0;
pre_wr_data0_q <= 32'b0;
pre_wr_data1_q <= 32'b0;
pre_wr_data2_q <= 32'b0;
pre_wr_data3_q <= 32'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end else begin
case ( wr_mem_state )
`PIO_MEM_ACCESS_WR_RST : begin
if (wr_en_i) begin // read state
wr_mem_state <= `PIO_MEM_ACCESS_WR_WAIT; //Pipelining happens in RAM's internal output reg.
end else begin
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end
end
`PIO_MEM_ACCESS_WR_WAIT : begin
/*
* Pipeline B port data before processing. Virtex 5 Block RAMs have internal
output register enabled.
*/
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_READ ;
end
`PIO_MEM_ACCESS_WR_READ : begin
/*
* Now save the selected BRAM B port data out
*/
pre_wr_data <= w_pre_wr_data;
write_en <= 1'b0;
wr_mem_state <= `PIO_MEM_ACCESS_WR_WRITE;
end
`PIO_MEM_ACCESS_WR_WRITE : begin
/*
* Merge new enabled data and write target BlockRAM location
*/
post_wr_data <= {{wr_be_i[3] ? w_wr_data_b3 : w_pre_wr_data_b3},
{wr_be_i[2] ? w_wr_data_b2 : w_pre_wr_data_b2},
{wr_be_i[1] ? w_wr_data_b1 : w_pre_wr_data_b1},
{wr_be_i[0] ? w_wr_data_b0 : w_pre_wr_data_b0}};
write_en <= 1'b1;
wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
end
endcase
end
end
/*
* Write controller busy
*/
assign wr_busy_o = wr_en_i | (wr_mem_state != `PIO_MEM_ACCESS_WR_RST);
/*
* Select BlockRAM output based on higher 2 address bits
*/
always @* // (wr_addr_i or pre_wr_data0_q or pre_wr_data1_q or pre_wr_data2_q or pre_wr_data3_q) begin
begin
case ({wr_addr_i[10:9]}) /* synthesis full_case */ /* synthesis parallel_case */
2'b00 : w_pre_wr_data = w_pre_wr_data0;
2'b01 : w_pre_wr_data = w_pre_wr_data1;
2'b10 : w_pre_wr_data = w_pre_wr_data2;
2'b11 : w_pre_wr_data = w_pre_wr_data3;
endcase
end
/*
* Memory Read Controller
*/
wire rd_data0_en = {rd_addr_i[10:9] == 2'b00};
wire rd_data1_en = {rd_addr_i[10:9] == 2'b01};
wire rd_data2_en = {rd_addr_i[10:9] == 2'b10};
wire rd_data3_en = {rd_addr_i[10:9] == 2'b11};
always @(rd_addr_i or rd_data0_o or rd_data1_o or rd_data2_o or rd_data3_o)
begin
case ({rd_addr_i[10:9]}) /* synthesis full_case */ /* synthesis parallel_case */
2'b00 : rd_data_raw_o = rd_data0_o;
2'b01 : rd_data_raw_o = rd_data1_o;
2'b10 : rd_data_raw_o = rd_data2_o;
2'b11 : rd_data_raw_o = rd_data3_o;
endcase
end
/* Handle Read byte enables */
assign rd_data_o = {{rd_be_i[0] ? rd_data_raw_o[07:00] : 8'h0},
{rd_be_i[1] ? rd_data_raw_o[15:08] : 8'h0},
{rd_be_i[2] ? rd_data_raw_o[23:16] : 8'h0},
{rd_be_i[3] ? rd_data_raw_o[31:24] : 8'h0}};
EP_MEM EP_MEM (
.clk_i(clk),
.a_rd_a_i_0(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_0(rd_data0_en), // I [1:0]
.a_rd_d_o_0(rd_data0_o), // O [31:0]
.b_wr_a_i_0(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_0(post_wr_data), // I [31:0]
.b_wr_en_i_0({write_en & (wr_addr_i[10:9] == 2'b00)}), // I
.b_rd_d_o_0(w_pre_wr_data0[31:0]), // O [31:0]
.b_rd_en_i_0({wr_addr_i[10:9] == 2'b00}), // I
.a_rd_a_i_1(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_1(rd_data1_en), // I [1:0]
.a_rd_d_o_1(rd_data1_o), // O [31:0]
.b_wr_a_i_1(wr_addr_i[8:0]), // [8:0]
.b_wr_d_i_1(post_wr_data), // [31:0]
.b_wr_en_i_1({write_en & (wr_addr_i[10:9] == 2'b01)}), // I
.b_rd_d_o_1(w_pre_wr_data1[31:0]), // [31:0]
.b_rd_en_i_1({wr_addr_i[10:9] == 2'b01}), // I
.a_rd_a_i_2(rd_addr_i[8:0]), // I [8:0]
.a_rd_en_i_2(rd_data2_en), // I [1:0]
.a_rd_d_o_2(rd_data2_o), // O [31:0]
.b_wr_a_i_2(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_2(post_wr_data), // I [31:0]
.b_wr_en_i_2({write_en & (wr_addr_i[10:9] == 2'b10)}), // I
.b_rd_d_o_2(w_pre_wr_data2[31:0]), // I [31:0]
.b_rd_en_i_2({wr_addr_i[10:9] == 2'b10}), // I
.a_rd_a_i_3(rd_addr_i[8:0]), // [8:0]
.a_rd_en_i_3(rd_data3_en), // [1:0]
.a_rd_d_o_3(rd_data3_o), // O [31:0]
.b_wr_a_i_3(wr_addr_i[8:0]), // I [8:0]
.b_wr_d_i_3(post_wr_data), // I [31:0]
.b_wr_en_i_3({write_en & (wr_addr_i[10:9] == 2'b11)}), // I
.b_rd_d_o_3(w_pre_wr_data3[31:0]), // I [31:0]
.b_rd_en_i_3({wr_addr_i[10:9] == 2'b11}) // I
);
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(wr_mem_state)
begin
if (wr_mem_state==`PIO_MEM_ACCESS_WR_RST) state_ascii <= #`TCQ "PIO_MEM_WR_RST";
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_WAIT) state_ascii <= #`TCQ "PIO_MEM_WR_WAIT";
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_READ) state_ascii <= #`TCQ "PIO_MEM_WR_READ";
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_WRITE) state_ascii <= #`TCQ "PIO_MEM_WR_WRITE";
else state_ascii <= #`TCQ "PIO MEM STATE ERR";
end
// synthesis translate_on
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_4_V
`define SKY130_FD_SC_HS__OR2B_4_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_4 (
X ,
A ,
B_N ,
VPWR,
VGND
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_4 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_4_V
|
module forward_mem_stage(mem_wb_op,mem_wb_regA,mem_wb_regC,ex_mem_op,ex_mem_regA,F3,mem_wb_CCR_write,ex_mem_CCR_write);
parameter ADD = 6'b000000;
parameter NDU = 6'b001000;
parameter ADC = 6'b000010;
parameter ADZ = 6'b000001;
parameter ADI = 4'b0001;
parameter NDC = 6'b001010;
parameter NDZ = 6'b001001;
parameter LHI = 4'b0011;
parameter LW = 4'b0100;
parameter SW = 4'b0101;
parameter LM = 4'b0110;
parameter SM = 4'b0111;
parameter BEQ = 4'b1100;
parameter JAL = 4'b1000;
parameter JLR = 4'b1001;
input [2:0] mem_wb_regA,mem_wb_regC,ex_mem_regA;
input [5:0]mem_wb_op,ex_mem_op;
input mem_wb_CCR_write,ex_mem_CCR_write;
output reg [1:0]F3;
always @(*)
begin
if(ex_mem_op[5:2]==SW)
begin
if((ex_mem_regA == mem_wb_regC)&&(mem_wb_op==ADD||mem_wb_op==NDU||mem_wb_op==ADC||mem_wb_op==ADZ
||mem_wb_op==NDC||mem_wb_op==NDZ)&&(mem_wb_CCR_write==1'b0))
F3 = 2'd2;//b
else if((ex_mem_regA==mem_wb_regA)&&(mem_wb_op[5:2]==LW))
F3 = 2'd3;//c
else
F3 = 2'b0;
end
else
F3 = 2'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND2_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__AND2_PP_BLACKBOX_V
/**
* and2: 2-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__and2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND2_PP_BLACKBOX_V
|
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=5000 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=Display_PLL" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" self_reset_on_loss_lock="OFF" width_clock=5 areset clk inclk locked CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 15.1 cbx_altclkbuf 2015:10:14:18:59:15:SJ cbx_altiobuf_bidir 2015:10:14:18:59:15:SJ cbx_altiobuf_in 2015:10:14:18:59:15:SJ cbx_altiobuf_out 2015:10:14:18:59:15:SJ cbx_altpll 2015:10:14:18:59:15:SJ cbx_cycloneii 2015:10:14:18:59:15:SJ cbx_lpm_add_sub 2015:10:14:18:59:15:SJ cbx_lpm_compare 2015:10:14:18:59:15:SJ cbx_lpm_counter 2015:10:14:18:59:15:SJ cbx_lpm_decode 2015:10:14:18:59:15:SJ cbx_lpm_mux 2015:10:14:18:59:15:SJ cbx_mgl 2015:10:21:19:02:34:SJ cbx_nadder 2015:10:14:18:59:15:SJ cbx_stratix 2015:10:14:18:59:15:SJ cbx_stratixii 2015:10:14:18:59:15:SJ cbx_stratixiii 2015:10:14:18:59:15:SJ cbx_stratixv 2015:10:14:18:59:15:SJ cbx_util_mgl 2015:10:14:18:59:15:SJ VERSION_END
//CBXI_INSTANCE_NAME="UART_Display_PLL_display0_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1 reg 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module Display_PLL_altpll
(
areset,
clk,
inclk,
locked) /* synthesis synthesis_clearbox=1 */;
input areset;
output [4:0] clk;
input [1:0] inclk;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg pll_lock_sync;
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
wire wire_pll1_locked;
// synopsys translate_off
initial
pll_lock_sync = 0;
// synopsys translate_on
always @ ( posedge wire_pll1_locked or posedge areset)
if (areset == 1'b1) pll_lock_sync <= 1'b0;
else pll_lock_sync <= 1'b1;
cycloneive_pll pll1
(
.activeclock(),
.areset(areset),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(wire_pll1_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 5000,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.self_reset_on_loss_lock = "off",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]},
locked = (wire_pll1_locked & pll_lock_sync);
endmodule //Display_PLL_altpll
//VALID FILE
|
// $Id: c_and_nto1.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// n-input bitwise AND
module c_and_nto1
(data_in, data_out);
// number of inputs
parameter num_ports = 2;
// width of each input
parameter width = 1;
// vector of inputs
input [0:width*num_ports-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar i;
for(i = 0; i < width; i = i + 1)
begin:bit_positions
wire [0:num_ports-1] data;
genvar j;
for(j = 0; j < num_ports; j = j + 1)
begin:input_ports
assign data[j] = data_in[j*width+i];
end
assign data_out[i] = &data;
end
endgenerate
endmodule
|
// **************************************************************************
// $Header: /var/lib/cvs/dncvs/FPGA/dini/misc/reset_resync.v,v 1.3 2014/09/12 05:26:45 neal Exp $
// **************************************************************************
// Description:
// Transfers a reset signal from one clock domain into another.
// **************************************************************************
// $Log: reset_resync.v,v $
// Revision 1.3 2014/09/12 05:26:45 neal
// Added an option to control the output polarity of the reset signal.
//
// Revision 1.2 2014/08/28 20:07:13 neal
// Added a property to help the vivado tools.
//
// Revision 1.1 2014/07/02 12:55:11 neal
// Added a resync module specifically for reset resynchronization to make timing constraint exclusions simpler.
//
// **************************************************************************
`ifdef INCL_RESET_RESYNC
`else
`define INCL_RESET_RESYNC
module reset_resync #(
parameter VALUE_DURING_RESET = 1
) (
input rst_in,
input clk_in,
input clk_out,
(* ASYNC_REG = "TRUE" *) (* keep="true" *) output reg rst_out
);
// **********************************************************************
// WRITE CLOCK DOMAIN
// **********************************************************************
(* keep="true" *) reg rst_in_dly;
always @(posedge clk_in or posedge rst_in) begin
if (rst_in) begin
rst_in_dly <= 1'b1;
end else begin
rst_in_dly <= 1'b0;
end
end
// **********************************************************************
// READ CLOCK DOMAIN DATA TRANSFER
// **********************************************************************
initial begin
rst_out = VALUE_DURING_RESET;
end
always @(posedge clk_out or posedge rst_in_dly) begin
if (rst_in_dly) begin
rst_out <= VALUE_DURING_RESET;
end else begin
rst_out <= ~VALUE_DURING_RESET;
end
end
endmodule
`endif // INCL_RESET_RESYNC
|
//Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
//Date : Mon Aug 08 14:08:37 2016
//Host : WK116 running 64-bit major release (build 9200)
//Command : generate_target PmodSD.bd
//Design : PmodSD
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "PmodSD,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=PmodSD,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=3,numReposBlks=3,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=Global}" *) (* HW_HANDOFF = "PmodSD.hwdef" *)
module PmodSD
(AXI_LITE_SDCS_araddr,
AXI_LITE_SDCS_arready,
AXI_LITE_SDCS_arvalid,
AXI_LITE_SDCS_awaddr,
AXI_LITE_SDCS_awready,
AXI_LITE_SDCS_awvalid,
AXI_LITE_SDCS_bready,
AXI_LITE_SDCS_bresp,
AXI_LITE_SDCS_bvalid,
AXI_LITE_SDCS_rdata,
AXI_LITE_SDCS_rready,
AXI_LITE_SDCS_rresp,
AXI_LITE_SDCS_rvalid,
AXI_LITE_SDCS_wdata,
AXI_LITE_SDCS_wready,
AXI_LITE_SDCS_wstrb,
AXI_LITE_SDCS_wvalid,
AXI_LITE_SPI_araddr,
AXI_LITE_SPI_arready,
AXI_LITE_SPI_arvalid,
AXI_LITE_SPI_awaddr,
AXI_LITE_SPI_awready,
AXI_LITE_SPI_awvalid,
AXI_LITE_SPI_bready,
AXI_LITE_SPI_bresp,
AXI_LITE_SPI_bvalid,
AXI_LITE_SPI_rdata,
AXI_LITE_SPI_rready,
AXI_LITE_SPI_rresp,
AXI_LITE_SPI_rvalid,
AXI_LITE_SPI_wdata,
AXI_LITE_SPI_wready,
AXI_LITE_SPI_wstrb,
AXI_LITE_SPI_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
s_axi_aclk,
s_axi_aresetn);
input [8:0]AXI_LITE_SDCS_araddr;
output AXI_LITE_SDCS_arready;
input AXI_LITE_SDCS_arvalid;
input [8:0]AXI_LITE_SDCS_awaddr;
output AXI_LITE_SDCS_awready;
input AXI_LITE_SDCS_awvalid;
input AXI_LITE_SDCS_bready;
output [1:0]AXI_LITE_SDCS_bresp;
output AXI_LITE_SDCS_bvalid;
output [31:0]AXI_LITE_SDCS_rdata;
input AXI_LITE_SDCS_rready;
output [1:0]AXI_LITE_SDCS_rresp;
output AXI_LITE_SDCS_rvalid;
input [31:0]AXI_LITE_SDCS_wdata;
output AXI_LITE_SDCS_wready;
input [3:0]AXI_LITE_SDCS_wstrb;
input AXI_LITE_SDCS_wvalid;
input [6:0]AXI_LITE_SPI_araddr;
output AXI_LITE_SPI_arready;
input AXI_LITE_SPI_arvalid;
input [6:0]AXI_LITE_SPI_awaddr;
output AXI_LITE_SPI_awready;
input AXI_LITE_SPI_awvalid;
input AXI_LITE_SPI_bready;
output [1:0]AXI_LITE_SPI_bresp;
output AXI_LITE_SPI_bvalid;
output [31:0]AXI_LITE_SPI_rdata;
input AXI_LITE_SPI_rready;
output [1:0]AXI_LITE_SPI_rresp;
output AXI_LITE_SPI_rvalid;
input [31:0]AXI_LITE_SPI_wdata;
output AXI_LITE_SPI_wready;
input [3:0]AXI_LITE_SPI_wstrb;
input AXI_LITE_SPI_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
input s_axi_aclk;
input s_axi_aresetn;
wire [6:0]AXI_LITE_1_ARADDR;
wire AXI_LITE_1_ARREADY;
wire AXI_LITE_1_ARVALID;
wire [6:0]AXI_LITE_1_AWADDR;
wire AXI_LITE_1_AWREADY;
wire AXI_LITE_1_AWVALID;
wire AXI_LITE_1_BREADY;
wire [1:0]AXI_LITE_1_BRESP;
wire AXI_LITE_1_BVALID;
wire [31:0]AXI_LITE_1_RDATA;
wire AXI_LITE_1_RREADY;
wire [1:0]AXI_LITE_1_RRESP;
wire AXI_LITE_1_RVALID;
wire [31:0]AXI_LITE_1_WDATA;
wire AXI_LITE_1_WREADY;
wire [3:0]AXI_LITE_1_WSTRB;
wire AXI_LITE_1_WVALID;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire [0:0]axi_gpio_sdcs_gpio_io_o;
wire [0:0]axi_gpio_sdcs_gpio_io_t;
wire axi_quad_spi_sd_SPI_0_IO0_I;
wire axi_quad_spi_sd_SPI_0_IO0_O;
wire axi_quad_spi_sd_SPI_0_IO0_T;
wire axi_quad_spi_sd_SPI_0_IO1_I;
wire axi_quad_spi_sd_SPI_0_IO1_O;
wire axi_quad_spi_sd_SPI_0_IO1_T;
wire axi_quad_spi_sd_SPI_0_SCK_I;
wire axi_quad_spi_sd_SPI_0_SCK_O;
wire axi_quad_spi_sd_SPI_0_SCK_T;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire pmod_bridge_0_in0_I;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
assign AXI_LITE_1_ARADDR = AXI_LITE_SPI_araddr[6:0];
assign AXI_LITE_1_ARVALID = AXI_LITE_SPI_arvalid;
assign AXI_LITE_1_AWADDR = AXI_LITE_SPI_awaddr[6:0];
assign AXI_LITE_1_AWVALID = AXI_LITE_SPI_awvalid;
assign AXI_LITE_1_BREADY = AXI_LITE_SPI_bready;
assign AXI_LITE_1_RREADY = AXI_LITE_SPI_rready;
assign AXI_LITE_1_WDATA = AXI_LITE_SPI_wdata[31:0];
assign AXI_LITE_1_WSTRB = AXI_LITE_SPI_wstrb[3:0];
assign AXI_LITE_1_WVALID = AXI_LITE_SPI_wvalid;
assign AXI_LITE_SDCS_arready = S_AXI_1_ARREADY;
assign AXI_LITE_SDCS_awready = S_AXI_1_AWREADY;
assign AXI_LITE_SDCS_bresp[1:0] = S_AXI_1_BRESP;
assign AXI_LITE_SDCS_bvalid = S_AXI_1_BVALID;
assign AXI_LITE_SDCS_rdata[31:0] = S_AXI_1_RDATA;
assign AXI_LITE_SDCS_rresp[1:0] = S_AXI_1_RRESP;
assign AXI_LITE_SDCS_rvalid = S_AXI_1_RVALID;
assign AXI_LITE_SDCS_wready = S_AXI_1_WREADY;
assign AXI_LITE_SPI_arready = AXI_LITE_1_ARREADY;
assign AXI_LITE_SPI_awready = AXI_LITE_1_AWREADY;
assign AXI_LITE_SPI_bresp[1:0] = AXI_LITE_1_BRESP;
assign AXI_LITE_SPI_bvalid = AXI_LITE_1_BVALID;
assign AXI_LITE_SPI_rdata[31:0] = AXI_LITE_1_RDATA;
assign AXI_LITE_SPI_rresp[1:0] = AXI_LITE_1_RRESP;
assign AXI_LITE_SPI_rvalid = AXI_LITE_1_RVALID;
assign AXI_LITE_SPI_wready = AXI_LITE_1_WREADY;
assign Pmod_out_pin10_o = 0;
assign Pmod_out_pin10_t = 0;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_ARADDR = AXI_LITE_SDCS_araddr[8:0];
assign S_AXI_1_ARVALID = AXI_LITE_SDCS_arvalid;
assign S_AXI_1_AWADDR = AXI_LITE_SDCS_awaddr[8:0];
assign S_AXI_1_AWVALID = AXI_LITE_SDCS_awvalid;
assign S_AXI_1_BREADY = AXI_LITE_SDCS_bready;
assign S_AXI_1_RREADY = AXI_LITE_SDCS_rready;
assign S_AXI_1_WDATA = AXI_LITE_SDCS_wdata[31:0];
assign S_AXI_1_WSTRB = AXI_LITE_SDCS_wstrb[3:0];
assign S_AXI_1_WVALID = AXI_LITE_SDCS_wvalid;
assign pmod_bridge_0_Pmod_out_PIN10_I = 0;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodSD_axi_gpio_0_0 axi_gpio_sdcs
(.gpio_io_i(pmod_bridge_0_in0_I),
.gpio_io_o(axi_gpio_sdcs_gpio_io_o),
.gpio_io_t(axi_gpio_sdcs_gpio_io_t),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID));
PmodSD_axi_quad_spi_0_0 axi_quad_spi_sd
(.ext_spi_clk(s_axi_aclk_1),
.io0_i(axi_quad_spi_sd_SPI_0_IO0_I),
.io0_o(axi_quad_spi_sd_SPI_0_IO0_O),
.io0_t(axi_quad_spi_sd_SPI_0_IO0_T),
.io1_i(axi_quad_spi_sd_SPI_0_IO1_I),
.io1_o(axi_quad_spi_sd_SPI_0_IO1_O),
.io1_t(axi_quad_spi_sd_SPI_0_IO1_T),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(AXI_LITE_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(AXI_LITE_1_ARREADY),
.s_axi_arvalid(AXI_LITE_1_ARVALID),
.s_axi_awaddr(AXI_LITE_1_AWADDR),
.s_axi_awready(AXI_LITE_1_AWREADY),
.s_axi_awvalid(AXI_LITE_1_AWVALID),
.s_axi_bready(AXI_LITE_1_BREADY),
.s_axi_bresp(AXI_LITE_1_BRESP),
.s_axi_bvalid(AXI_LITE_1_BVALID),
.s_axi_rdata(AXI_LITE_1_RDATA),
.s_axi_rready(AXI_LITE_1_RREADY),
.s_axi_rresp(AXI_LITE_1_RRESP),
.s_axi_rvalid(AXI_LITE_1_RVALID),
.s_axi_wdata(AXI_LITE_1_WDATA),
.s_axi_wready(AXI_LITE_1_WREADY),
.s_axi_wstrb(AXI_LITE_1_WSTRB),
.s_axi_wvalid(AXI_LITE_1_WVALID),
.sck_i(axi_quad_spi_sd_SPI_0_SCK_I),
.sck_o(axi_quad_spi_sd_SPI_0_SCK_O),
.sck_t(axi_quad_spi_sd_SPI_0_SCK_T),
.ss_i(1'b0));
PmodSD_pmod_bridge_0_0 pmod_bridge_0
(.in0_I(pmod_bridge_0_in0_I),
.in0_O(axi_gpio_sdcs_gpio_io_o),
.in0_T(axi_gpio_sdcs_gpio_io_t),
.in1_I(axi_quad_spi_sd_SPI_0_IO0_I),
.in1_O(axi_quad_spi_sd_SPI_0_IO0_O),
.in1_T(axi_quad_spi_sd_SPI_0_IO0_T),
.in2_I(axi_quad_spi_sd_SPI_0_IO1_I),
.in2_O(axi_quad_spi_sd_SPI_0_IO1_O),
.in2_T(axi_quad_spi_sd_SPI_0_IO1_T),
.in3_I(axi_quad_spi_sd_SPI_0_SCK_I),
.in3_O(axi_quad_spi_sd_SPI_0_SCK_O),
.in3_T(axi_quad_spi_sd_SPI_0_SCK_T),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
//
//
//===----------------------------------------------------------------------===//
module acl_stall_monitor #(NODES=32) (
input clock,
input resetn,
input [NODES-1:0] valid,
input [NODES-1:0] stall_in,
input [NODES-1:0] stall_out,
output [32*NODES-1:0] stall_count
);
reg [31:0] stall_count_mem[NODES-1:0];
generate
genvar i;
for (i=0; i<NODES; i=i+1)
begin : node_gen
always @(posedge clock or negedge resetn)
begin
if (~(resetn))
begin
stall_count_mem[i] <= 32'h0;
end
else
begin
if ( valid[i] && stall_out[i] && !stall_in[i])
stall_count_mem[i] <= stall_count_mem[i] + 2'h01;
end
end
assign stall_count[i] = stall_count_mem[i];
end
endgenerate
endmodule
|
// file: clk_166M_83M_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_166M_83M_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [3:1] COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_166M_83M_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: ps2_cache.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ps2_cache (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [21:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [21:0] q;
output rdempty;
output wrfull;
wire sub_wire0;
wire [21:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [21:0] q = sub_wire1[21:0];
wire rdempty = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.aclr (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone III",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 22,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "22"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "22"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "22"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 22 0 INPUT NODEFVAL "data[21..0]"
// Retrieval info: USED_PORT: q 0 0 22 0 OUTPUT NODEFVAL "q[21..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 22 0 data 0 0 22 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 22 0 @q 0 0 22 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ps2_cache_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file ram_13x28_15x7.v when simulating
// the core, ram_13x28_15x7. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module ram_13x28_15x7(
clka,
dina,
addra,
wea,
douta,
clkb,
dinb,
addrb,
web,
doutb);
input clka;
input [27 : 0] dina;
input [12 : 0] addra;
input [0 : 0] wea;
output [27 : 0] douta;
input clkb;
input [6 : 0] dinb;
input [14 : 0] addrb;
input [0 : 0] web;
output [6 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V2_8 #(
.C_ADDRA_WIDTH(13),
.C_ADDRB_WIDTH(15),
.C_ALGORITHM(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex5"),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_SSRA(0),
.C_HAS_SSRB(0),
.C_INIT_FILE_NAME("ram_13x28_15x7.mif"),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(8192),
.C_READ_DEPTH_B(32768),
.C_READ_WIDTH_A(28),
.C_READ_WIDTH_B(7),
.C_SIM_COLLISION_CHECK("ALL"),
.C_SINITA_VAL("0"),
.C_SINITB_VAL("0"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_RAMB16BWER_RST_BHV(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(8192),
.C_WRITE_DEPTH_B(32768),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(28),
.C_WRITE_WIDTH_B(7),
.C_XDEVICEFAMILY("virtex5"))
inst (
.CLKA(clka),
.DINA(dina),
.ADDRA(addra),
.WEA(wea),
.DOUTA(douta),
.CLKB(clkb),
.DINB(dinb),
.ADDRB(addrb),
.WEB(web),
.DOUTB(doutb),
.ENA(),
.REGCEA(),
.SSRA(),
.ENB(),
.REGCEB(),
.SSRB(),
.DBITERR(),
.SBITERR());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram_13x28_15x7 is "black_box"
endmodule
|
/**
file : sm_rtl.v
abs. :
vers. : 3 - сброс счетчика происходит по началу пакета и по концу
это важно, т.к. сброс по началу прочему-то не всегда происходит
feat. :
1. clk_ena - Ok!
2. ширина окна TIME+1 т.к. предполагаем, что один такт на загрузку
warrn. : При реализации при ошибках обратить внимание на операция загрузки
с предыдущей стадии(см. vers. )
power :
все работает в рамках окна
*/
module sm_control_v3(
clk, rst,
clk_ena,
// control
first, // разрешение загрузки в выходной регистр первого блока
// master
windows, // окно для работы блока
//count,
last // разрешение загрузки в свой выходной регистр
);
parameter WIDTH = 8;
parameter MOD_COUNT = 14;
/// Main ///
input clk, rst;
// out.
output windows;
output last;
//output [(WIDTH-1):0] count;
/// Enabling ///
input clk_ena;
input first;
wire carry; // перенос счетчика
wire oor_ena = first | carry;
wire co_ena = windows & clk_ena;
wire dff_ena = oor_ena & clk_ena;
wire count_load = first | carry;
/// local
wire [WIDTH-1:0] dfload = 0;
wire adf_in; // вход разрешающего триггера
wire adf_out;
// отсчетчик
counter_load
//counter_load_dbus
#(
.MOD_COUNT(MOD_COUNT),
.WIDTH(WIDTH))
label_cnt_load(
.clk(clk), .rst(rst),
.clk_ena(co_ena),
// control
.load(
count_load),
//first), // загрузить данные
// out
.carry(carry), // перенесо счетчика
//.count(count),
// datastream
.dfload(dfload)); // data for load
// триггер разрешения работы
a_dff #(
.WIDTH(WIDTH))
label_aff(
.clk(clk), .aclr(rst),
.ena(dff_ena),
.data(adf_in),
.q(adf_out));
// comb. logic
assign adf_in = ~carry | first;
// out
assign last = carry;
assign windows = first | adf_out;
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 14767 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w64,
w65,
w16384,
w16319,
w1040,
w15279,
w512,
w14767;
assign w1 = i_data0;
assign w1040 = w65 << 4;
assign w14767 = w15279 - w512;
assign w15279 = w16319 - w1040;
assign w16319 = w16384 - w65;
assign w16384 = w1 << 14;
assign w512 = w1 << 9;
assign w64 = w1 << 6;
assign w65 = w1 + w64;
assign o_data0 = w14767;
//multiplier_block area estimate = 6935.54390735736;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_BEHAVIORAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_gt_rx_valid_filter_7x.v
// Version : 3.0
//-- Description: GTX module for 7-series Integrated PCIe Block
//--
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns / 1ns
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_gt_rx_valid_filter_7x #(
parameter CLK_COR_MIN_LAT = 28,
parameter TCQ = 1
)
(
output [1:0] USER_RXCHARISK,
output [15:0] USER_RXDATA,
output USER_RXVALID,
output USER_RXELECIDLE,
output [ 2:0] USER_RX_STATUS,
output USER_RX_PHY_STATUS,
input [1:0] GT_RXCHARISK,
input [15:0] GT_RXDATA,
input GT_RXVALID,
input GT_RXELECIDLE,
input [ 2:0] GT_RX_STATUS,
input GT_RX_PHY_STATUS,
input PLM_IN_L0,
input PLM_IN_RS,
input USER_CLK,
input RESET
);
localparam EIOS_DET_IDL = 5'b00001;
localparam EIOS_DET_NO_STR0 = 5'b00010;
localparam EIOS_DET_STR0 = 5'b00100;
localparam EIOS_DET_STR1 = 5'b01000;
localparam EIOS_DET_DONE = 5'b10000;
localparam EIOS_COM = 8'hBC;
localparam EIOS_IDL = 8'h7C;
localparam FTSOS_COM = 8'hBC;
localparam FTSOS_FTS = 8'h3C;
reg [4:0] reg_state_eios_det;
wire [4:0] state_eios_det;
reg reg_eios_detected;
wire eios_detected;
reg reg_symbol_after_eios;
wire symbol_after_eios;
localparam USER_RXVLD_IDL = 4'b0001;
localparam USER_RXVLD_EI = 4'b0010;
localparam USER_RXVLD_EI_DB0 = 4'b0100;
localparam USER_RXVLD_EI_DB1 = 4'b1000;
reg [1:0] gt_rxcharisk_q;
reg [15:0] gt_rxdata_q;
reg gt_rxvalid_q;
reg gt_rxelecidle_q;
reg [ 2:0] gt_rx_status_q;
reg gt_rx_phy_status_q;
reg gt_rx_is_skp0_q;
reg gt_rx_is_skp1_q;
// EIOS detector
always @(posedge USER_CLK) begin
if (RESET) begin
reg_eios_detected <= #TCQ 1'b0;
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ 2'b00;
gt_rxdata_q <= #TCQ 16'h0;
gt_rxvalid_q <= #TCQ 1'b0;
gt_rxelecidle_q <= #TCQ 1'b0;
gt_rx_status_q <= #TCQ 3'b000;
gt_rx_phy_status_q <= #TCQ 1'b0;
gt_rx_is_skp0_q <= #TCQ 1'b0;
gt_rx_is_skp1_q <= #TCQ 1'b0;
end else begin
reg_eios_detected <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b0;
gt_rxcharisk_q <= #TCQ GT_RXCHARISK;
gt_rxelecidle_q <= #TCQ GT_RXELECIDLE;
gt_rxdata_q <= #TCQ GT_RXDATA;
gt_rx_phy_status_q <= #TCQ GT_RX_PHY_STATUS;
//De-assert rx_valid signal when EIOS is detected on RXDATA
if(((reg_state_eios_det == 5'b10000)) && (PLM_IN_L0)
) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (GT_RXELECIDLE && !gt_rxvalid_q) begin
gt_rxvalid_q <= #TCQ 1'b0;
end
else begin
gt_rxvalid_q <= GT_RXVALID;
end
if (gt_rxvalid_q) begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
else if (!gt_rxvalid_q && PLM_IN_L0) begin
gt_rx_status_q <= #TCQ 3'b0;
end
else begin
gt_rx_status_q <= #TCQ GT_RX_STATUS;
end
if (GT_RXCHARISK[0] && GT_RXDATA[7:0] == FTSOS_FTS)
gt_rx_is_skp0_q <= #TCQ 1'b1;
else
gt_rx_is_skp0_q <= #TCQ 1'b0;
if (GT_RXCHARISK[1] && GT_RXDATA[15:8] == FTSOS_FTS)
gt_rx_is_skp1_q <= #TCQ 1'b1;
else
gt_rx_is_skp1_q <= #TCQ 1'b0;
case ( state_eios_det )
EIOS_DET_IDL : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_COM) &&
(gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_NO_STR0;
reg_eios_detected <= #TCQ 1'b1;
// gt_rxvalid_q <= #TCQ 1'b0;
end else if ((gt_rxcharisk_q[1]) && (gt_rxdata_q[15:8] == EIOS_COM))
reg_state_eios_det <= #TCQ EIOS_DET_STR0;
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_NO_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL)))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else if (gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR0 : begin
if ((gt_rxcharisk_q[0] && (gt_rxdata_q[7:0] == EIOS_IDL)) &&
(gt_rxcharisk_q[1] && (gt_rxdata_q[15:8] == EIOS_IDL))) begin
reg_state_eios_det <= #TCQ EIOS_DET_STR1;
reg_eios_detected <= #TCQ 1'b1;
gt_rxvalid_q <= #TCQ 1'b0;
reg_symbol_after_eios <= #TCQ 1'b1;
end else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_STR1 : begin
if ((gt_rxcharisk_q[0]) && (gt_rxdata_q[7:0] == EIOS_IDL))
begin
reg_state_eios_det <= #TCQ EIOS_DET_DONE;
gt_rxvalid_q <= #TCQ 1'b0;
end
else
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
EIOS_DET_DONE : begin
reg_state_eios_det <= #TCQ EIOS_DET_IDL;
end
endcase
end
end
assign state_eios_det = reg_state_eios_det;
assign eios_detected = reg_eios_detected;
assign symbol_after_eios = reg_symbol_after_eios;
/*SRL16E #(.INIT(0)) rx_elec_idle_delay (.Q(USER_RXELECIDLE),
.D(gt_rxelecidle_q),
.CLK(USER_CLK),
.CE(1'b1), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
*/
wire rst_l = ~RESET;
assign USER_RXVALID = gt_rxvalid_q;
assign USER_RXCHARISK[0] = gt_rxvalid_q ? gt_rxcharisk_q[0] : 1'b0;
assign USER_RXCHARISK[1] = (gt_rxvalid_q && !symbol_after_eios) ? gt_rxcharisk_q[1] : 1'b0;
assign USER_RXDATA[7:0] = gt_rxdata_q[7:0];
assign USER_RXDATA[15:8] = gt_rxdata_q[15:8];
assign USER_RX_STATUS = gt_rx_status_q;
assign USER_RX_PHY_STATUS = gt_rx_phy_status_q;
assign USER_RXELECIDLE = gt_rxelecidle_q;
endmodule
|
// Check the various variable array selects (small to large).
module top;
reg passed;
wire [1:0] a [1:4];
wire [0:0] s0 = 0;
wire [1:0] s1 = 0;
wire [2:0] s2 = 0;
reg [1:0] ar [1:4];
wire [1:0] c [-3:0];
wire [0:0] s3 = 0;
wire [1:0] s4 = 0;
reg [1:0] cr [-3:0];
wire [1:0] res_a0 = a[s0];
wire [1:0] res_a1 = a[s1];
wire [1:0] res_a2 = a[s2];
wire [1:0] res_c3 = c[s3];
wire [1:0] res_c4 = c[s4];
reg res_a [1:4];
reg res_c [-3:0];
assign a[1] = 2'd0;
assign a[2] = 2'b1;
assign a[3] = 2'd2;
assign a[4] = 2'd3;
assign c[-3] = 2'd0;
assign c[-2] = 2'b1;
assign c[-1] = 2'd2;
assign c[0] = 2'd3;
initial begin
#1;
passed = 1'b1;
ar[1] = 2'd0;
ar[2] = 2'b1;
ar[3] = 2'd2;
ar[4] = 2'd3;
cr[-3] = 2'd0;
cr[-2] = 2'b1;
cr[-1] = 2'd2;
cr[0] = 2'd3;
// Check procedural R-value variable bit selects of a net.
$display("a[s0]: %b", a[s0]);
if (a[s0] !== 2'bxx) begin
$display("Failed a[s0], expected 2'bxx, got %b", a[s0]);
passed = 1'b0;
end
$display("a[s1]: %b", a[s1]);
if (a[s1] !== 2'bxx) begin
$display("Failed a[s1], expected 2'bxx, got %b", a[s1]);
passed = 1'b0;
end
$display("a[s2]: %b", a[s2]);
if (a[s2] !== 2'bxx) begin
$display("Failed a[s2], expected 2'bxx, got %b", a[s2]);
passed = 1'b0;
end
$display("c[s3]: %b", c[s3]);
if (c[s3] !== 2'b11) begin
$display("Failed c[s3], expected 2'b11, got %b", c[s3]);
passed = 1'b0;
end
$display("c[s4]: %b", c[s4]);
if (c[s4] !== 2'b11) begin
$display("Failed c[s4], expected 2'b11, got %b", c[s4]);
passed = 1'b0;
end
// Check procedural R-value variable bit selects of a reg.
$display("ar[s0]: %b", ar[s0]);
if (ar[s0] !== 2'bxx) begin
$display("Failed ar[s0], expected 2'bxx, got %b", ar[s0]);
passed = 1'b0;
end
$display("ar[s1]: %b", ar[s1]);
if (ar[s1] !== 2'bxx) begin
$display("Failed ar[s1], expected 2'bxx, got %b", ar[s1]);
passed = 1'b0;
end
$display("ar[s2]: %b", ar[s2]);
if (ar[s2] !== 2'bxx) begin
$display("Failed ar[s2], expected 2'bxx, got %b", ar[s2]);
passed = 1'b0;
end
$display("cr[s3]: %b", cr[s3]);
if (cr[s3] !== 2'b11) begin
$display("Failed cr[s3], expected 2'b11, got %b", cr[s3]);
passed = 1'b0;
end
$display("cr[s4]: %b", cr[s4]);
if (cr[s4] !== 2'b11) begin
$display("Failed cr[s4], expected 2'b11, got %b", cr[s4]);
passed = 1'b0;
end
// Check continuous assignment R-value variable bit selects.
if (res_a0 !== 2'bxx) begin
$display("Failed res_a0, expected 2'bxx, got %b", res_a0);
passed = 1'b0;
end
if (res_a1 !== 2'bxx) begin
$display("Failed res_a1, expected 2'bxx, got %b", res_a1);
passed = 1'b0;
end
if (res_a2 !== 2'bxx) begin
$display("Failed res_a2, expected 2'bxx, got %b", res_a2);
passed = 1'b0;
end
if (res_c3 !== 2'b11) begin
$display("Failed res_c3, expected 2'b11, got %b", res_c3);
passed = 1'b0;
end
if (res_c4 !== 2'b11) begin
$display("Failed res_c4, expected 2'b11, got %b", res_c4);
passed = 1'b0;
end
// Check procedural L-value variable bit selects.
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s0] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s0], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s1] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s1], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_a[1] = 1'bx;
res_a[2] = 1'bx;
res_a[3] = 1'bx;
res_a[4] = 1'bx;
res_a[s2] = 1'b0;
if (res_a[1] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [1], got %b", res_a[1]);
passed = 1'b0;
end
if (res_a[2] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [2], got %b", res_a[2]);
passed = 1'b0;
end
if (res_a[3] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [3], got %b", res_a[3]);
passed = 1'b0;
end
if (res_a[4] !== 1'bx) begin
$display("Failed res_a[s2], expected 1'bx for [4], got %b", res_a[4]);
passed = 1'b0;
end
res_c[-3] = 1'bx;
res_c[-2] = 1'bx;
res_c[-1] = 1'bx;
res_c[0] = 1'bx;
res_c[s3] = 1'b0;
if (res_c[-3] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-3], got %b", res_c[-3]);
passed = 1'b0;
end
if (res_c[-2] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-2], got %b", res_c[-2]);
passed = 1'b0;
end
if (res_c[-1] !== 1'bx) begin
$display("Failed res_c[s3], expected 1'bx for [-1], got %b", res_c[-1]);
passed = 1'b0;
end
if (res_c[0] !== 1'b0) begin
$display("Failed res_c[s3], expected 1'b0 for [0], got %b", res_c[0]);
passed = 1'b0;
end
res_c[-3] = 1'bx;
res_c[-2] = 1'bx;
res_c[-1] = 1'bx;
res_c[0] = 1'bx;
res_c[s4] = 1'b0;
if (res_c[-3] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-3], got %b", res_c[-3]);
passed = 1'b0;
end
if (res_c[-2] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-2], got %b", res_c[-2]);
passed = 1'b0;
end
if (res_c[-1] !== 1'bx) begin
$display("Failed res_c[s4], expected 1'bx for [-1], got %b", res_c[-1]);
passed = 1'b0;
end
if (res_c[0] !== 1'b0) begin
$display("Failed res_c[s4], expected 1'b0 for [0], got %b", res_c[0]);
passed = 1'b0;
end
if (passed) $display("Compare tests passed");
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXR Engine takes unformatted completions, formats
// these packets into "TLP's" or Transaction Layer Packets. These packets must
// meet max-request, max-payload, and payload termination requirements (see Read
// Completion Boundary). The TXR Engine does not check these requirements during
// operation, but may do so during simulation. This Engine is capable of
// operating at "line rate". This file also contains the txr_formatter module,
// which formats request headers.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txr_engine_classic
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA")
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN, // Addition for RIFFA_RST
output DONE_TXR_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR Classic
input TXR_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TXR_TLP,
output TXR_TLP_VALID,
output TXR_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_START_OFFSET,
output TXR_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_TLP_END_OFFSET,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY
);
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
(C_VENDOR == "XILINX") ? 0 :
0;
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign DONE_TXR_RST = ~RST_IN;
txr_formatter_classic
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
.C_VENDOR (C_VENDOR))
txr_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txr_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXR_DATA_READY),
.TX_PKT (TXR_TLP[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TXR_TLP_START_FLAG),
.TX_PKT_START_OFFSET (TXR_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TXR_TLP_END_FLAG),
.TX_PKT_END_OFFSET (TXR_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TXR_TLP_VALID),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXR_DATA_VALID),
.TX_DATA (TXR_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (TXR_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txr_formatter_classic
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
parameter C_MAX_ALIGN_WIDTH = 32,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXR
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
wire wWrReq;
wire [`TLP_FMT_W-1:0] wHdrLoFmt;
wire [63:0] wHdrLo;
wire [63:0] _wTxHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddr[1:0];
wire [(`TLP_REQADDR_W/2)-1:0] wTxHdrAddrDW0;
wire wTxHdr4DW;
wire wTxHdrAlignmentNeeded;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
assign wHdrLoFmt = {1'b0, TXR_META_TYPE[`TRLS_TYPE_PAY_I],1'bx};
// Reserved Fields
assign wHdrLo[`TLP_RSVD0_R] = `TLP_RSVD0_V;
assign wHdrLo[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
assign wHdrLo[`TLP_TH_R] = `TLP_TH_W'b0;
assign wHdrLo[`TLP_RSVD1_R] = `TLP_RSVD1_V;
assign wHdrLo[`TLP_RSVD2_R] = `TLP_RSVD2_V;
// Generic Header Fields
assign wHdrLo[`TLP_LEN_R] = TXR_META_LENGTH;
assign wHdrLo[`TLP_EP_R] = TXR_META_EP;
assign wHdrLo[`TLP_TD_R] = `TLP_NODIGEST_V;
assign wHdrLo[`TLP_ATTR0_R] = TXR_META_ATTR[1:0];
assign wHdrLo[`TLP_ATTR1_R] = TXR_META_ATTR[2];
assign wHdrLo[`TLP_TYPE_R] = TXR_META_TYPE; // WORKAROUND
assign wHdrLo[`TLP_TC_R] = TXR_META_TC;
assign wHdrLo[`TLP_FMT_R] = wHdrLoFmt;
// Request Specific Fields
assign wHdrLo[`TLP_REQFBE_R] = TXR_META_FDWBE;
assign wHdrLo[`TLP_REQLBE_R] = TXR_META_LDWBE;
assign wHdrLo[`TLP_REQTAG_R] = TXR_META_TAG;
assign wHdrLo[`TLP_REQREQID_R] = CONFIG_COMPLETER_ID;
// Second header formatting stage
assign wTxHdr4DW = wTxHdrAddr[1] != 32'b0;
assign {wTxHdr[`TLP_FMT_R],wTxHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(_wTxHdr[`TLP_TYPE_I +: `SIG_TYPE_W],wTxHdr4DW);
assign wTxHdr[`TLP_TYPE_I-1:0] = _wTxHdr[`TLP_TYPE_I-1:0];
assign wTxHdr[63:32] = _wTxHdr[63:32];
assign wTxHdr[127:64] = {wTxHdrAddr[~wTxHdr4DW],wTxHdrAddr[wTxHdr4DW]};
// Metadata, to the aligner
assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
assign wTxHdrAddrDW0 = wTxHdrAddr[0];
assign wTxHdrAlignmentNeeded = (wTxHdrAddrDW0[2] == wTxHdr4DW);
assign wTxHdrNonpayLen = {1'b0,{wTxHdr4DW,~wTxHdr4DW,~wTxHdr4DW}} + ((C_VENDOR == "ALTERA") ? {3'b0,(wTxHdrAlignmentNeeded & ~wTxHdrNopayload)}:0);
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXR_META_READY),
.RD_DATA ({wTxHdrAddr[1],wTxHdrAddr[0],_wTxHdr[63:0]}),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA ({TXR_META_ADDR, wHdrLo}),
.WR_DATA_VALID (TXR_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency simulation mode. In this
// case just pass everything through to the ARM, which can bit-bang this
// (because it is so slow).
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd200);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine_ultrascale.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TX Engine takes unformatted request and completions,
// formats these packets into AXI packets for the Xilinx Core. These packets
// must meet max-request, max-payload, and payload termination requirements (see
// Read Completion Boundary). The TX Engine does not check these requirements
// during operation, but may do so during simulation.
//
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "ultrascale.vh"
module tx_engine_ultrascale
#(parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_TXC_RST,
output DONE_TXR_RST,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: CC
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
output TXC_SENT,
// Interface: RQ
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
// Interface: TXR Engine
input TXR_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
input TXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
input TXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
output TXR_DATA_READY,
input TXR_META_VALID,
input [`SIG_FBE_W-1:0] TXR_META_FDWBE,
input [`SIG_LBE_W-1:0] TXR_META_LDWBE,
input [`SIG_ADDR_W-1:0] TXR_META_ADDR,
input [`SIG_LEN_W-1:0] TXR_META_LENGTH,
input [`SIG_TAG_W-1:0] TXR_META_TAG,
input [`SIG_TC_W-1:0] TXR_META_TC,
input [`SIG_ATTR_W-1:0] TXR_META_ATTR,
input [`SIG_TYPE_W-1:0] TXR_META_TYPE,
input TXR_META_EP,
output TXR_META_READY,
output TXR_SENT
);
localparam C_DEPTH_PACKETS = 10;
/*AUTOWIRE*/
/*AUTOINPUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
reg rTxcSent;
reg rTxrSent;
assign TXC_SENT = rTxcSent;
assign TXR_SENT = rTxrSent;
always @(posedge CLK) begin
rTxcSent <= S_AXIS_CC_TLAST & S_AXIS_CC_TVALID & S_AXIS_CC_TREADY;
rTxrSent <= S_AXIS_RQ_TLAST & S_AXIS_RQ_TVALID & S_AXIS_RQ_TREADY;
end
txr_engine_ultrascale
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txr_engine_inst
(/*AUTOINST*/
// Outputs
.DONE_TXR_RST (DONE_TXR_RST),
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY),
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP));
txc_engine_ultrascale
#(
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS))
txc_engine_inst
(/*AUTOINST*/
// Outputs
.DONE_TXC_RST (DONE_TXC_RST),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_BUS (RST_BUS),
.RST_LOGIC (RST_LOGIC),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Apr 14 18:32:23 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top bd_proc_sys_reset_0_0 -prefix
// bd_proc_sys_reset_0_0_ bd_proc_sys_reset_0_0_stub.v
// Design : bd_proc_sys_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module bd_proc_sys_reset_0_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: wr_data_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose:
//Reference:
//Revision History: 5/2/2012 Fixed data_wr_end_r logic which didn't hold its state when data_rdy_i was deasserted and
// data_valid was asserted.
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_wr_data_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_TYPE = "DDR3",
parameter MODE = "WR", //"WR", "RD"
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter COLUMN_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i, //
input [4:0] rst_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input [3:0] data_mode_i, // "00" = bram;
input mem_init_done_i,
input wr_data_mask_gen_i,
output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
// And then it should reasserted when
// it is generating the last_word.
input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
input cmd_validB_i,
input cmd_validC_i,
output last_word_o,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
// input [ADDR_WIDTH-1:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
input memc_cmd_full_i,
input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen
// connect from mcb_rd_empty when used as rd_data_gen
// When both data_rdy and data_valid is asserted, the ouput data is valid.
output data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
// pattern is available.
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o, // generated data pattern
output data_wr_end_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o
);
//
reg [DWIDTH-1:0] data;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF;
reg burst_count_reached2;
reg data_valid;
reg [BL_WIDTH:0]user_burst_cnt;
reg [2:0] walk_cnt;
wire fifo_not_full;
integer i,j;
reg [31:0] w3data;
reg data_wr_end_r;
wire data_wr_end;
wire bram_rd_valid_o;
function integer logb2;
input [31:0] number;
integer i;
begin
i = number;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
assign fifo_not_full = data_rdy_i;
// data_wr_end_r is used in nCK_PER_CLK == 2; when nCK_PER_CLK = 4, data_wr_end_o == data_valid_o;
always @(posedge clk_i)
begin
if (~user_burst_cnt[0] && data_valid && data_rdy_i && MEM_BURST_LEN == 8)
data_wr_end_r <= #TCQ 1'b1;
else if (data_rdy_i) // keep the data_wr_end_r asserted if data_rdy_i is deasserted because of mc's write
// data fifo full.
data_wr_end_r <= #TCQ 1'b0;
end
//assign data_wr_end_o = data_wr_end_r && fifo_not_full; */
assign data_wr_end_o = (nCK_PER_CLK == 4 || nCK_PER_CLK == 2 && MEM_BURST_LEN == 4) ? data_valid_o :data_wr_end_r ;//(MEM_BURST_LEN == 8) ? user_burst_cnt[0] & data_valid_o :
assign data_valid_o = data_valid ;//& ~memc_cmd_full_i;// (nCK_PER_CLK == 4)?data_valid_r: data_valid ;//& fifo_not_full;
//assign data_wr_end_o = data_wr_end_r;
always @ (posedge clk_i)
begin
cmd_start <= #TCQ cmd_validC_i & cmd_rdyC ;
cmd_startB <= #TCQ cmd_valid_i & cmd_rdyB;
cmd_startC <= #TCQ cmd_validB_i & cmd_rdyC;
cmd_startD <= #TCQ cmd_validB_i & cmd_rdyD;
cmd_startE <= #TCQ cmd_validB_i & cmd_rdyE;
cmd_startF <= #TCQ cmd_validB_i & cmd_rdyF;
end
// counter to count user burst length
always @( posedge clk_i)
begin
if ( rst_i[0] )
user_burst_cnt <= #TCQ 'd0;
else if(cmd_start)
// if (FAMILY == "SPARTAN6") begin
// SPATAN6 has maximum of burst length of 64.
if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000)
// user_burst_cnt <= #TCQ 7'b1000000;
begin
user_burst_cnt[6:0] <= #TCQ 7'd64;
user_burst_cnt[BL_WIDTH:7] <= 'b0;
end
else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}})
user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}};
else
user_burst_cnt <= #TCQ {1'b0,bl_i};
// else
// user_burst_cnt <= #TCQ bl_i;
// else if(fifo_not_full && data_valid && ~memc_cmd_full_i)
else if(fifo_not_full && data_valid )
if (user_burst_cnt != 6'd0)
user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
else
user_burst_cnt <=#TCQ 'd0;
end
reg u_bcount_2;
wire last_word_t;
always @ (posedge clk_i)
begin
if ((user_burst_cnt == 2 && fifo_not_full )|| (cmd_startC && bl_i == 1))
u_bcount_2 <= #TCQ 1'b1;
else if (last_word_o)
u_bcount_2 <= #TCQ 1'b0;
end
assign last_word_o = u_bcount_2 & fifo_not_full;
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
assign cmd_rdy_o = cmd_rdy & fifo_not_full;
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdy <= #TCQ 1'b1; // the state should be '0' for bram_interface during reset.
else if (bram_rd_valid_o) // need work here.
cmd_rdy <= #TCQ 1'b1;
else if (cmd_start)
if (bl_i == 1)
cmd_rdy <= #TCQ 1'b1;
else
cmd_rdy <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdy <= #TCQ bram_rd_valid_o;//1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i [0])
cmd_rdyB <= #TCQ 1'b1;
else if (cmd_startB)
if (bl_i == 1)
cmd_rdyB <= #TCQ 1'b1;
else
cmd_rdyB <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyB <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyC <= #TCQ 1'b1;
else if (cmd_startC)
if (bl_i == 1)
cmd_rdyC <= #TCQ 1'b1;
else
cmd_rdyC <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyC <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyD <= #TCQ 1'b1;
else if (cmd_startD)
if (bl_i == 1)
cmd_rdyD <= #TCQ 1'b1;
else
cmd_rdyD <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyD <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyE <= #TCQ 1'b1;
else if (cmd_startE)
if (bl_i == 1)
cmd_rdyE <= #TCQ 1'b1;
else
cmd_rdyE <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyE <= #TCQ 1'b1;
end
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdyF <= #TCQ 1'b1;
else if (cmd_startF)
if (bl_i == 1)
cmd_rdyF <= #TCQ 1'b1;
else
cmd_rdyF <= #TCQ 1'b0;
else if ((user_burst_cnt == 6'd2 && fifo_not_full ) )
cmd_rdyF <= #TCQ 1'b1;
end
reg dvalid;
always @ (posedge clk_i)
begin
if (rst_i[1])
data_valid <= #TCQ 'd0;
else if(cmd_start)
data_valid <= #TCQ 1'b1;
else if (fifo_not_full && user_burst_cnt <= 6'd1)
data_valid <= #TCQ 1'b0;
// data_valid <= dvalid ;
end
mig_7series_v1_9_s7ven_data_gen #
(
.TCQ (TCQ),
.ADDR_WIDTH (32 ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.DWIDTH (DWIDTH),
.MEM_BURST_LEN (MEM_BURST_LEN),
.nCK_PER_CLK (nCK_PER_CLK),
.START_ADDR (START_ADDR),
.DATA_PATTERN (DATA_PATTERN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.COLUMN_WIDTH (COLUMN_WIDTH),
.EYE_TEST (EYE_TEST)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.prbs_fseed_i (prbs_fseed_i),
.mem_init_done_i (mem_init_done_i),
.mode_load_i (mode_load_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_startB ),
.cmd_startC (cmd_startC ),
.cmd_startD (cmd_startD ),
.cmd_startE (cmd_startE ),
.m_addr_i (addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (fifo_not_full ),
.data_o (data_o ),
.data_mask_o (data_mask_o),
.bram_rd_valid_o (bram_rd_valid_o),
.tg_st_addr_o ()
);
endmodule
|
`include "../defined.vh"
module Mult
(
clk,
rst,
a,
b,
mult_func,
c_mult
);
input clk;
input rst;
input [31:0] a;
input [31:0] b;
input [3:0] mult_func;
output reg [31:0] c_mult;
reg[31:0] Hi,Lo;
reg write_Lo,write_Hi;
reg[2:0] comm;
wire signed[31:0] a_s,b_s;
assign a_s=a;
assign b_s=b;
always@(*)
begin
c_mult<=0;
write_Lo<=0;
write_Hi<=0;
comm<=0;
case(mult_func)
`MULT_NOTHING:
c_mult<=0;
`MULT_READ_LO:
c_mult<=Lo;
`MULT_READ_HI:
c_mult<=Hi;
`MULT_WRITE_LO:
write_Lo<=1;
`MULT_WRITE_HI:
write_Hi<=1;
`MULT_MULT:
comm<=1;
`MULT_SIGNED_MULT:
comm<=2;
`MULT_DIVIDE:
comm<=3;
`MULT_SIGNED_DIVIDE:
comm<=4;
endcase
end
always@(posedge clk or posedge rst)
begin
if(rst)
begin
Hi<=0;
Lo<=0;
end
else if(comm==0)
begin
if(write_Lo)
Lo<=a;
if(write_Hi)
Hi<=a;
end
else if(comm==1)//mult
{Hi,Lo}<=a*b;
else if(comm==2)//mult_signed
{Hi,Lo}<=a_s*b_s;
else if(comm==3)//div
begin
if(b!=32'b0)
begin
Lo<=32'b0;//FIXME: DIV is removed a/b;
Hi<=32'b0;//FIXME: DIV is removed a%b;
end
end
else if(comm==4)//div_signed
begin
if(b_s!=32'b0)
begin
Lo<=32'b0;//FIXME: DIV is removed a_s/b_s;
Hi<=32'b0;//FIXME: DIV is removed a_s%b_s;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLCLKP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLCLKP_PP_SYMBOL_V
/**
* dlclkp: Clock gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlclkp (
//# {{clocks|Clocking}}
input CLK ,
input GATE,
output GCLK,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLCLKP_PP_SYMBOL_V
|
`timescale 1ns / 1ps
module mixer_t;
// ins
reg clk;
reg rst;
reg [7:0] ack_i;
reg [(8*24-1):0] data_i;
reg [1:0] pop_i;
mixer uut(
.clk(clk), .rst(rst), .rst_ch(0),
.ack_i(ack_i), .data_i(data_i),
.vol_i({32'h01_000000, 32'h02_000000, 32'h03_000000, 32'h04_000000,
32'h05_000000, 32'h06_000000, 32'h07_000000, 32'h08_000000}),
.pop_i(pop_i));
parameter TCLK = 10;
always #(TCLK/2) clk = ~clk;
initial begin
$dumpfile("mixer_t.lxt");
$dumpvars(0, uut);
clk = 0;
ack_i = 0;
data_i = 0;
pop_i = 0;
rst = 0;
#(TCLK);
rst = 1;
#(TCLK);
rst = 0;
#(TCLK * 1000);
$finish(2);
end
always begin
#(TCLK*32);
pop_i = 2'b11;
#(TCLK);
pop_i = 2'b00;
end
genvar ig;
generate
for(ig = 0; ig < 8; ig = ig + 1) begin:g
wire [7:0] ch = ig;
reg [15:0] counter_ff;
initial begin
counter_ff <= 0;
end
always @(posedge clk) begin
if (uut.pop_o[ig]) begin
#(TCLK);
data_i[(ig*24) +: 24] = {ch, counter_ff};
counter_ff = counter_ff + 1;
ack_i[ig] = 1;
#(TCLK);
ack_i[ig] = 0;
end
end
end
endgenerate
genvar iga;
generate
for(iga = 0; iga < 2; iga = iga + 1) begin:ga
always @(posedge clk) begin
if (uut.ack_o[iga])
$display("ch: %d. out: %h", iga, uut.data_o);
end
end
endgenerate
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus master and slave (combined) interface - zero cycle read delay.
*
*/
module rcn_master_slave_fast
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
input cs,
input [1:0] seq,
output busy,
input wr,
input [3:0] mask,
input [23:0] addr,
input [31:0] wdata,
output rdone,
output wdone,
output [1:0] rsp_seq,
output [3:0] rsp_mask,
output [23:0] rsp_addr,
output [31:0] rsp_data,
output slave_cs,
output slave_wr,
output [3:0] slave_mask,
output [23:0] slave_addr,
output [31:0] slave_wdata,
input [31:0] slave_rdata
);
parameter MASTER_ID = 0;
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [5:0] my_id = MASTER_ID;
wire [23:0] my_mask = ADDR_MASK;
wire [23:0] my_base = ADDR_BASE;
wire my_resp = rin[68] && !rin[67] && (rin[65:60] == my_id);
wire my_req = rin[68] && rin[67] && ((rin[55:34] & my_mask[23:2]) == my_base[23:2]);
wire [68:0] resp;
wire req_valid;
wire [68:0] req;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 69'd0;
rout <= 69'd0;
end
else
begin
rin <= rcn_in;
rout <= (my_req) ? resp : (req_valid) ? req : (my_resp) ? 69'd0 : rin;
end
assign busy = rin[68] && !my_resp;
assign req_valid = cs && !(rin[68] && !my_resp);
assign req = {1'b1, 1'b1, wr, my_id, mask, addr[23:2], seq, wdata};
assign rdone = my_resp && !rin[66];
assign wdone = my_resp && rin[66];
assign rsp_seq = rin[33:32];
assign rsp_mask = rin[59:56];
assign rsp_addr = {rin[55:34], 2'd0};
assign rsp_data = rin[31:0];
assign slave_cs = my_req;
assign slave_wr = rin[66];
assign slave_mask = rin[59:56];
assign slave_addr = {rin[55:34], 2'd0};
assign slave_wdata = rin[31:0];
assign resp = {1'b1, 1'b0, rin[66:32], slave_rdata};
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:55:16 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R2_P2 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24;
CLKAND2X2TS U18 ( .A(in1[0]), .B(in2[0]), .Y(n20) );
XOR2XLTS U19 ( .A(in1[3]), .B(in2[3]), .Y(n17) );
XOR2XLTS U20 ( .A(in1[5]), .B(in2[5]), .Y(n15) );
OAI211XLTS U21 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[4]), .C0(in1[4]), .Y(n22)
);
OAI211XLTS U22 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[2]), .C0(in1[2]), .Y(n14)
);
AOI2BB1XLTS U23 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n20), .Y(res[0]) );
OAI2BB1X1TS U24 ( .A0N(in1[3]), .A1N(in2[3]), .B0(n14), .Y(n19) );
XOR2XLTS U25 ( .A(n16), .B(n15), .Y(res[5]) );
XOR2XLTS U26 ( .A(n18), .B(n17), .Y(res[3]) );
CMPR32X2TS U27 ( .A(in2[4]), .B(in1[4]), .C(n19), .CO(n16), .S(res[4]) );
CMPR32X2TS U28 ( .A(in1[1]), .B(in2[1]), .C(n20), .CO(n21), .S(res[1]) );
CMPR32X2TS U29 ( .A(in1[2]), .B(in2[2]), .C(n21), .CO(n18), .S(res[2]) );
OAI2BB1X1TS U30 ( .A0N(in1[5]), .A1N(in2[5]), .B0(n22), .Y(n23) );
CMPR32X2TS U31 ( .A(in1[6]), .B(in2[6]), .C(n23), .CO(n24), .S(res[6]) );
CMPR32X2TS U32 ( .A(in1[7]), .B(in2[7]), .C(n24), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("GeAr_N8_R2_P2_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_PP_SYMBOL_V
`define SKY130_FD_SC_HS__A41OI_PP_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a41oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_PP_SYMBOL_V
|
`timescale 1ns/10ps
module VGA2InterfaceSim;
reg clock;
reg reset;
reg color_r;
reg color_g;
reg color_b;
wire [10:0] fb_addr_h;
wire [10:0] fb_addr_v;
wire vga_hsync;
wire vga_vsync;
wire vga_r;
wire vga_g;
wire vga_b;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#1000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0 color_r = 0;
color_g = 0;
color_b = 0;
#40 color_r = 1;
color_g = 0;
color_b = 0;
#40 color_r = 1;
color_g = 1;
color_b = 0;
#40 color_r = 0;
color_g = 1;
color_b = 0;
#40 color_r = 0;
color_g = 0;
color_b = 0;
#40 color_r = 0;
color_g = 0;
color_b = 1;
end // initial begin
VGA2Interface #(.HAddrSize(11),
.HVisibleArea(4),
.HFrontPorch(2),
.HSyncPulse(3),
.HBackPorch(2),
.VAddrSize(11),
.VVisibleArea(5),
.VFrontPorch(2),
.VSyncPulse(3),
.VBackPorch(2))
vgaint (.clock(clock),
.reset(reset),
.color_r(color_r),
.color_g(color_g),
.color_b(color_b),
.fb_addr_h(fb_addr_h),
.fb_addr_v(fb_addr_v),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // VGA2InterfaceSim
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog wrapper for lpflow_lsbuf_lh_isowell with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
.X(X),
.A(A),
.LOWLVPWR(LOWLVPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
wire LOWLVPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Tecnológico de Costa Rica
// Engineer: Juan José Rojas Salazar
//
// Create Date: 30.07.2016 10:22:05
// Design Name:
// Module Name: Barrel_shifter
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module Barrel_Shifter#(parameter SWR=26, parameter EWR=5)(
//Implicit bit + Significand Width (23 bits for simple format, 52 bits for Double format)
//+ guard Bit + round bit
//INPUTS
input wire clk,
input wire rst,
input wire load_i,
input wire [EWR-1:0] Shift_Value_i,
input wire [SWR-1:0] Shift_Data_i,
input wire Left_Right_i,
input wire Bit_Shift_i,
//OUTPUTS
output wire [SWR-1:0] N_mant_o
);
wire [SWR-1:0] Data_Reg;
Mux_Array #(.SWR(SWR),.EWR(EWR)) Mux_Array(
.clk(clk),
.rst(rst),
.load_i(load_i),
.Data_i(Shift_Data_i),
.FSM_left_right_i(Left_Right_i),
.Shift_Value_i(Shift_Value_i),
.bit_shift_i(Bit_Shift_i),
.Data_o(Data_Reg)
);
RegisterAdd #(.W(SWR)) Output_Reg(
.clk(clk),
.rst(rst),
.load(load_i),
.D(Data_Reg),
.Q(N_mant_o)
);
endmodule
|
//
// Copyright (c) 2003 Launchbird Design Systems, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
// Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
// IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//
// Overview:
//
// Performs finite impulse response (FIR) filtering.
// The filter's sum of products is pipelined with a register after
// every multiplier and adder. The adder network is a balanced binary
// tree to minimize latency. The sum of products has no numeric loss because the
// multipliers keep all resulting bits and each adder extends the precision by 1.
//
// Interface:
//
// Synchronization:
// clock_c : Clock input.
// reset_i : Filter delay bank synchronous reset. Does not reset sum of products pipeline registers.
//
// Inputs:
// data_i : Input data.
// k0_i : Coefficient 0 multiplied by in_i(0).
// k1_i : Coefficient 1 multiplied by in_i(k-1).
// k2_i : Coefficient 2 multiplied by in_i(k-2).
// ...
// k<order>_i : Coefficient <order> multiplied by in_i(k-<order>).
//
// Outputs:
// data_o : Output data.
//
// Built In Parameters:
//
// Filter Order = 3
// Input Precision = 8
// Coefficient Precision = 8
// Sum of Products Latency = 3
//
//
//
//
// Generated by Confluence 0.6.3 -- Launchbird Design Systems, Inc. -- www.launchbird.com
//
// Build Date : Fri Aug 22 09:45:46 CDT 2003
//
// Interface
//
// Build Name : cf_fir_3_8_8
// Clock Domains : clock_c
// Vector Input : reset_i(1)
// Vector Input : data_i(8)
// Vector Input : k0_i(8)
// Vector Input : k1_i(8)
// Vector Input : k2_i(8)
// Vector Input : k3_i(8)
// Vector Output : data_o(18)
//
//
//
module cf_fir_3_8_8 (clock_c, reset_i, data_i, k0_i, k1_i, k2_i, k3_i, data_o);
input clock_c;
input reset_i;
input [7:0] data_i;
input [7:0] k0_i;
input [7:0] k1_i;
input [7:0] k2_i;
input [7:0] k3_i;
output [17:0] data_o;
wire [17:0] n1;
cf_fir_3_8_8_1 s1 (clock_c, reset_i, k0_i, k1_i, k2_i, k3_i, data_i, n1);
assign data_o = n1;
endmodule
module cf_fir_3_8_8_1 (clock_c, i1, i2, i3, i4, i5, i6, o1);
input clock_c;
input i1;
input [7:0] i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
output [17:0] o1;
wire n1;
wire n2;
wire [17:0] s3_1;
assign n1 = 1'b1;
assign n2 = 1'b0;
cf_fir_3_8_8_2 s3 (clock_c, n1, n2, i1, i2, i3, i4, i5, i6, s3_1);
assign o1 = s3_1;
endmodule
module cf_fir_3_8_8_2 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, o1);
input clock_c;
input i1;
input i2;
input i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [7:0] i8;
output [17:0] o1;
reg [7:0] n1;
reg [7:0] n2;
reg [7:0] n3;
reg [7:0] n4;
wire n5;
wire [17:0] n6;
wire n7;
wire [17:0] n8;
wire [17:0] n9;
reg [17:0] n10;
wire [16:0] s11_1;
wire [16:0] s11_2;
wire [15:0] s12_1;
wire [15:0] s12_2;
wire [15:0] s12_3;
wire [15:0] s12_4;
always @ (posedge clock_c)
begin
if (i3 == 1'b1)
n1 <= 8'b00000000;
else if (i1 == 1'b1)
n1 <= i8;
if (i3 == 1'b1)
n2 <= 8'b00000000;
else if (i1 == 1'b1)
n2 <= n1;
if (i3 == 1'b1)
n3 <= 8'b00000000;
else if (i1 == 1'b1)
n3 <= n2;
if (i3 == 1'b1)
n4 <= 8'b00000000;
else if (i1 == 1'b1)
n4 <= n3;
if (i2 == 1'b1)
n10 <= 18'b000000000000000000;
else if (i1 == 1'b1)
n10 <= n9;
end
assign n5 = s11_1[16];
assign n6 = {n5, s11_1};
assign n7 = s11_2[16];
assign n8 = {n7, s11_2};
assign n9 = n6 + n8;
cf_fir_3_8_8_4 s11 (clock_c, i1, i2, s12_1, s12_2, s12_3, s12_4, s11_1, s11_2);
cf_fir_3_8_8_3 s12 (clock_c, i1, i2, i4, i5, i6, i7, n1, n2, n3, n4, s12_1, s12_2, s12_3, s12_4);
assign o1 = n10;
endmodule
module cf_fir_3_8_8_3 (clock_c, i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, o1, o2, o3, o4);
input clock_c;
input i1;
input i2;
input [7:0] i3;
input [7:0] i4;
input [7:0] i5;
input [7:0] i6;
input [7:0] i7;
input [7:0] i8;
input [7:0] i9;
input [7:0] i10;
output [15:0] o1;
output [15:0] o2;
output [15:0] o3;
output [15:0] o4;
wire [15:0] n1;
reg [15:0] n2;
wire [15:0] n3;
reg [15:0] n4;
wire [15:0] n5;
reg [15:0] n6;
wire [15:0] n7;
reg [15:0] n8;
assign n1 = {8'b00000000, i3} * {8'b00000000, i7};
always @ (posedge clock_c)
begin
if (i2 == 1'b1)
n2 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n2 <= n1;
if (i2 == 1'b1)
n4 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n4 <= n3;
if (i2 == 1'b1)
n6 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n6 <= n5;
if (i2 == 1'b1)
n8 <= 16'b0000000000000000;
else if (i1 == 1'b1)
n8 <= n7;
end
assign n3 = {8'b00000000, i4} * {8'b00000000, i8};
assign n5 = {8'b00000000, i5} * {8'b00000000, i9};
assign n7 = {8'b00000000, i6} * {8'b00000000, i10};
assign o4 = n8;
assign o3 = n6;
assign o2 = n4;
assign o1 = n2;
endmodule
module cf_fir_3_8_8_4 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2);
input clock_c;
input i1;
input i2;
input [15:0] i3;
input [15:0] i4;
input [15:0] i5;
input [15:0] i6;
output [16:0] o1;
output [16:0] o2;
wire n1;
wire [16:0] n2;
wire n3;
wire [16:0] n4;
wire [16:0] n5;
reg [16:0] n6;
wire n7;
wire [16:0] n8;
wire n9;
wire [16:0] n10;
wire [16:0] n11;
reg [16:0] n12;
assign n1 = i3[15];
assign n2 = {n1, i3};
assign n3 = i4[15];
assign n4 = {n3, i4};
assign n5 = n2 + n4;
always @ (posedge clock_c)
begin
if (i2 == 1'b1)
n6 <= 17'b00000000000000000;
else if (i1 == 1'b1)
n6 <= n5;
if (i2 == 1'b1)
n12 <= 17'b00000000000000000;
else if (i1 == 1'b1)
n12 <= n11;
end
assign n7 = i5[15];
assign n8 = {n7, i5};
assign n9 = i6[15];
assign n10 = {n9, i6};
assign n11 = n8 + n10;
assign o2 = n12;
assign o1 = n6;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.91
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : Virtex-6
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands and
// requests to change the IO configuration. These requests come
// the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCNFG2WR = 2
)
(/*AUTOARG*/
// Outputs
grant_row_r, sent_row, sending_row, grant_config_r,
io_config_strobe, force_io_config_rd_r1, io_config_valid_r,
grant_col_r, sending_col, sent_col, grant_col_wr, send_cmd0_col,
send_cmd1_row, cs_en0, cs_en1, insert_maint_r1,
// Inputs
clk, rst, rts_row, insert_maint_r, rts_col, rtc,
force_io_config_rd_r, col_rdy_wr
);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg io_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire io_config_kill_rts_col = (nCNFG2WR == 1) ? 1'b0 : io_config_strobe_r;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T") begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(io_config_kill_rts_col || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~io_config_kill_rts_col}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// IO config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_io_config_last_master;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_io_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
input force_io_config_rd_r;
wire io_config_strobe_ns =
~io_config_strobe_r && (|rtc || force_io_config_rd_r) && ~granted_col_ns;
always @(posedge clk) io_config_strobe_r <= #TCQ io_config_strobe_ns;
output wire io_config_strobe;
assign io_config_strobe = io_config_strobe_r;
reg force_io_config_rd_r1_lcl;
always @(posedge clk) force_io_config_rd_r1_lcl <=
#TCQ force_io_config_rd_r;
output wire force_io_config_rd_r1;
assign force_io_config_rd_r1 = force_io_config_rd_r1_lcl;
assign upd_io_config_last_master =
io_config_strobe_r && ~force_io_config_rd_r1_lcl;
// Generate io_config_valid.
reg io_config_valid_r_lcl;
wire io_config_valid_ns;
assign io_config_valid_ns =
~rst && (io_config_valid_r_lcl || io_config_strobe_ns);
always @(posedge clk) io_config_valid_r_lcl <= #TCQ io_config_valid_ns;
output wire io_config_valid_r;
assign io_config_valid_r = io_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
output wire sent_col;
assign sent_col = sent_col_lcl;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
generate
case ({(nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
2'b00 : begin : one_one_not2T
end
2'b01 : begin : one_one_2T
end
2'b10 : begin : two_one_not2T
always @(/*AS*/sent_row_or_maint) cs_en0 = sent_row_or_maint;
always @(/*AS*/sent_col_lcl) cs_en1 = sent_col_lcl;
end
2'b11 : begin : two_one_2T
always @(/*AS*/sent_col_lcl or sent_row_or_maint) cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(/*AS*/sent_col_lcl) send_cmd0_col = sent_col_lcl;
always @(/*AS*/sent_row_or_maint) send_cmd1_row = sent_row_or_maint;
end
endcase
endgenerate
endmodule
|
// Signed 40-bit streaming accumulator with 16-bit inputs
// File: HDL_Coding_Techniques/multipliers/multipliers4.v
//
// Source:
// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
//
module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
input clk, ce, sload,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0;
reg sload_reg = 0;
reg signed [2*SIZEIN-1:0] mult_reg = 0;
reg signed [SIZEOUT-1:0] adder_out = 0, old_result;
always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
if (sload_reg)
old_result <= 0;
else
// 'sload' is now active (=low) and opens the accumulation loop.
// The accumulator takes the next multiplier output in
// the same cycle.
old_result <= adder_out;
end
always @(posedge clk)
if (ce)
begin
a_reg <= a;
b_reg <= b;
mult_reg <= a_reg * b_reg;
sload_reg <= sload;
// Store accumulation result into a register
adder_out <= old_result + mult_reg;
end
// Output accumulation result
assign accum_out = adder_out;
endmodule
// Adapted variant of above
module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
input clk,
input ce,
input rst,
input signed [SIZEIN-1:0] a, b,
output signed [SIZEOUT-1:0] accum_out,
output overflow
);
// Declare registers for intermediate values
reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0;
reg signed [2*SIZEIN-1:0] mult_reg = 0;
reg signed [SIZEOUT:0] adder_out = 0;
reg overflow_reg = 0;
always @(posedge clk) begin
//if (ce)
begin
a_reg <= a;
b_reg <= b;
a_reg2 <= a_reg;
b_reg2 <= b_reg;
mult_reg <= a_reg2 * b_reg2;
// Store accumulation result into a register
adder_out <= adder_out + mult_reg;
overflow_reg <= overflow;
end
if (rst) begin
a_reg <= 0;
a_reg2 <= 0;
b_reg <= 0;
b_reg2 <= 0;
mult_reg <= 0;
adder_out <= 0;
overflow_reg <= 1'b0;
end
end
assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;
// Output accumulation result
assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_TB_V
`define SKY130_FD_SC_HVL__DFXTP_TB_V
/**
* dfxtp: Delay flop, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__dfxtp.v"
module top();
// Inputs are registered
reg D;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__dfxtp dut (.D(D), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_TB_V
|
//////////////////////////////////////////////////////////////////////////////////
// d_KES_CS_buffer.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH decoder (page decoder) ELP buffer
// Module Name: d_KES_CS_buffer
// File Name: d_KES_CS_buffer.v
//
// Version: v1.0.0
//
// Description: Error location polynomial's coefficient buffer between KES and CS
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module d_KES_CS_buffer
#(
parameter Multi = 2,
parameter GaloisFieldDegree = 12,
parameter MaxErrorCountBits = 9,
parameter ELPCoefficients = 15
)
(
i_clk ,
i_RESET ,
i_stop_dec ,
i_exe_buf ,
i_kes_fail ,
i_buf_sequence_end ,
i_chunk_number ,
i_error_count ,
i_v_000 ,
i_v_001 ,
i_v_002 ,
i_v_003 ,
i_v_004 ,
i_v_005 ,
i_v_006 ,
i_v_007 ,
i_v_008 ,
i_v_009 ,
i_v_010 ,
i_v_011 ,
i_v_012 ,
i_v_013 ,
i_v_014 ,
i_cs_available ,
o_buf_available ,
o_exe_cs ,
o_kes_sequence_end ,
o_kes_fail ,
o_error_count ,
o_ELP_coef
);
input i_clk ;
input i_RESET ;
input i_stop_dec ;
input i_exe_buf ;
input i_kes_fail ;
input i_buf_sequence_end ;
input i_chunk_number ;
input [3:0] i_error_count ;
input [GaloisFieldDegree - 1:0] i_v_000 ;
input [GaloisFieldDegree - 1:0] i_v_001 ;
input [GaloisFieldDegree - 1:0] i_v_002 ;
input [GaloisFieldDegree - 1:0] i_v_003 ;
input [GaloisFieldDegree - 1:0] i_v_004 ;
input [GaloisFieldDegree - 1:0] i_v_005 ;
input [GaloisFieldDegree - 1:0] i_v_006 ;
input [GaloisFieldDegree - 1:0] i_v_007 ;
input [GaloisFieldDegree - 1:0] i_v_008 ;
input [GaloisFieldDegree - 1:0] i_v_009 ;
input [GaloisFieldDegree - 1:0] i_v_010 ;
input [GaloisFieldDegree - 1:0] i_v_011 ;
input [GaloisFieldDegree - 1:0] i_v_012 ;
input [GaloisFieldDegree - 1:0] i_v_013 ;
input [GaloisFieldDegree - 1:0] i_v_014 ;
input i_cs_available ;
output o_buf_available ;
output reg o_exe_cs ;
output reg [Multi - 1:0] o_kes_sequence_end ;
output reg [Multi - 1:0] o_kes_fail ;
output reg [Multi*MaxErrorCountBits - 1:0] o_error_count ;
output reg [Multi*GaloisFieldDegree*ELPCoefficients - 1:0] o_ELP_coef ;
reg r_buf_sequence_end;
reg [3:0] r_cur_state;
reg [3:0] r_nxt_state;
reg [Multi - 1:0] r_cs_enable;
reg [Multi - 1:0] r_kes_fail;
reg [Multi*MaxErrorCountBits - 1:0] r_error_count;
reg [Multi*GaloisFieldDegree - 1:0] r_v_000;
reg [Multi*GaloisFieldDegree - 1:0] r_v_001;
reg [Multi*GaloisFieldDegree - 1:0] r_v_002;
reg [Multi*GaloisFieldDegree - 1:0] r_v_003;
reg [Multi*GaloisFieldDegree - 1:0] r_v_004;
reg [Multi*GaloisFieldDegree - 1:0] r_v_005;
reg [Multi*GaloisFieldDegree - 1:0] r_v_006;
reg [Multi*GaloisFieldDegree - 1:0] r_v_007;
reg [Multi*GaloisFieldDegree - 1:0] r_v_008;
reg [Multi*GaloisFieldDegree - 1:0] r_v_009;
reg [Multi*GaloisFieldDegree - 1:0] r_v_010;
reg [Multi*GaloisFieldDegree - 1:0] r_v_011;
reg [Multi*GaloisFieldDegree - 1:0] r_v_012;
reg [Multi*GaloisFieldDegree - 1:0] r_v_013;
reg [Multi*GaloisFieldDegree - 1:0] r_v_014;
localparam State_Idle = 4'b0000;
localparam State_Input = 4'b0001;
localparam State_Standby = 4'b0010;
localparam State_Out_Ready = 4'b0100;
localparam State_Output = 4'b1000;
assign o_buf_available = !((r_cur_state == State_Out_Ready) || (r_cur_state == State_Output));
always @ (posedge i_clk) begin
if (i_RESET || i_stop_dec)
r_cur_state <= State_Idle;
else
r_cur_state <= r_nxt_state;
end
always @ (*) begin
if(i_RESET || i_stop_dec)
r_nxt_state <= State_Idle;
else begin
case (r_cur_state)
State_Idle:
r_nxt_state <= (i_exe_buf) ? State_Input : State_Idle;
State_Input:
r_nxt_state <= State_Standby;
State_Standby:
r_nxt_state <= (i_exe_buf) ? State_Input : ( (r_buf_sequence_end) ? State_Out_Ready : State_Standby );
State_Out_Ready:
r_nxt_state <= (i_cs_available) ? State_Output : State_Out_Ready;
State_Output:
r_nxt_state <= State_Idle;
default:
r_nxt_state <= State_Idle;
endcase
end
end
always @ (posedge i_clk) begin
if (i_RESET || i_stop_dec)
r_buf_sequence_end <= 0;
else
case (r_nxt_state)
State_Idle:
r_buf_sequence_end <= 0;
State_Input:
r_buf_sequence_end <= i_buf_sequence_end;
default:
r_buf_sequence_end <= r_buf_sequence_end;
endcase
end
always @ (posedge i_clk) begin
if (i_RESET || i_stop_dec)
begin
o_exe_cs <= 0;
o_kes_sequence_end <= 0;
o_kes_fail <= 0;
o_error_count <= 0;
o_ELP_coef <= 0;
end
else begin
case (r_nxt_state)
State_Output: begin
o_exe_cs <= 1'b1;
o_kes_sequence_end <= r_cs_enable;
o_kes_fail <= r_kes_fail;
o_error_count <= r_error_count;
o_ELP_coef <= { r_v_000,
r_v_001,
r_v_002,
r_v_003,
r_v_004,
r_v_005,
r_v_006,
r_v_007,
r_v_008,
r_v_009,
r_v_010,
r_v_011,
r_v_012,
r_v_013,
r_v_014 };
end
default: begin
o_exe_cs <= 0;
o_kes_sequence_end <= 0;
o_kes_fail <= 0;
o_error_count <= 0;
o_ELP_coef <= 0;
end
endcase
end
end
always @ (posedge i_clk) begin
if (i_RESET || i_stop_dec)
begin
r_cs_enable <= 0;
r_kes_fail <= 0;
r_error_count <= 0;
r_v_000 <= 0;
r_v_001 <= 0;
r_v_002 <= 0;
r_v_003 <= 0;
r_v_004 <= 0;
r_v_005 <= 0;
r_v_006 <= 0;
r_v_007 <= 0;
r_v_008 <= 0;
r_v_009 <= 0;
r_v_010 <= 0;
r_v_011 <= 0;
r_v_012 <= 0;
r_v_013 <= 0;
r_v_014 <= 0;
end
else begin
case (r_nxt_state)
State_Idle: begin
r_cs_enable <= 0;
r_kes_fail <= 0;
r_error_count <= 0;
r_v_000 <= 0;
r_v_001 <= 0;
r_v_002 <= 0;
r_v_003 <= 0;
r_v_004 <= 0;
r_v_005 <= 0;
r_v_006 <= 0;
r_v_007 <= 0;
r_v_008 <= 0;
r_v_009 <= 0;
r_v_010 <= 0;
r_v_011 <= 0;
r_v_012 <= 0;
r_v_013 <= 0;
r_v_014 <= 0;
end
State_Input: begin
if (i_kes_fail) begin
case (i_chunk_number)
1'b0: begin
r_kes_fail[0] <= 1'b1;
r_cs_enable[0] <= 1'b1;
end
1'b1: begin
r_kes_fail[1] <= 1'b1;
r_cs_enable[0] <= 1'b1;
end
endcase
r_error_count <= r_error_count;
r_v_000 <= r_v_000;
r_v_001 <= r_v_001;
r_v_002 <= r_v_002;
r_v_003 <= r_v_003;
r_v_004 <= r_v_004;
r_v_005 <= r_v_005;
r_v_006 <= r_v_006;
r_v_007 <= r_v_007;
r_v_008 <= r_v_008;
r_v_009 <= r_v_009;
r_v_010 <= r_v_010;
r_v_011 <= r_v_011;
r_v_012 <= r_v_012;
r_v_013 <= r_v_013;
r_v_014 <= r_v_014;
end
else begin
r_kes_fail <= r_kes_fail;
case (i_chunk_number)
1'b0: begin
r_cs_enable[0] <= (|i_error_count) ? 1'b1 : 1'b0;
r_error_count[MaxErrorCountBits*1 - 1:MaxErrorCountBits*(1 - 1)] <= i_error_count;
r_v_000[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_000;
r_v_001[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_001;
r_v_002[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_002;
r_v_003[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_003;
r_v_004[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_004;
r_v_005[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_005;
r_v_006[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_006;
r_v_007[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_007;
r_v_008[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_008;
r_v_009[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_009;
r_v_010[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_010;
r_v_011[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_011;
r_v_012[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_012;
r_v_013[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_013;
r_v_014[GaloisFieldDegree*1 - 1:GaloisFieldDegree*(1 - 1)] <= i_v_014;
end
1'b1: begin
r_cs_enable[1] <= (|i_error_count) ? 1'b1 : 1'b0;
r_error_count[MaxErrorCountBits*2 - 1:MaxErrorCountBits*(2 - 1)] <= i_error_count;
r_v_000[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_000;
r_v_001[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_001;
r_v_002[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_002;
r_v_003[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_003;
r_v_004[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_004;
r_v_005[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_005;
r_v_006[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_006;
r_v_007[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_007;
r_v_008[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_008;
r_v_009[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_009;
r_v_010[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_010;
r_v_011[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_011;
r_v_012[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_012;
r_v_013[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_013;
r_v_014[GaloisFieldDegree*2 - 1:GaloisFieldDegree*(2 - 1)] <= i_v_014;
end
default: begin
r_cs_enable <= r_cs_enable;
r_error_count <= r_error_count;
r_v_000 <= r_v_000;
r_v_001 <= r_v_001;
r_v_002 <= r_v_002;
r_v_003 <= r_v_003;
r_v_004 <= r_v_004;
r_v_005 <= r_v_005;
r_v_006 <= r_v_006;
r_v_007 <= r_v_007;
r_v_008 <= r_v_008;
r_v_009 <= r_v_009;
r_v_010 <= r_v_010;
r_v_011 <= r_v_011;
r_v_012 <= r_v_012;
r_v_013 <= r_v_013;
r_v_014 <= r_v_014;
end
endcase
end
end
default: begin
r_kes_fail <= r_kes_fail;
r_cs_enable <= r_cs_enable;
r_error_count <= r_error_count;
r_v_000 <= r_v_000;
r_v_001 <= r_v_001;
r_v_002 <= r_v_002;
r_v_003 <= r_v_003;
r_v_004 <= r_v_004;
r_v_005 <= r_v_005;
r_v_006 <= r_v_006;
r_v_007 <= r_v_007;
r_v_008 <= r_v_008;
r_v_009 <= r_v_009;
r_v_010 <= r_v_010;
r_v_011 <= r_v_011;
r_v_012 <= r_v_012;
r_v_013 <= r_v_013;
r_v_014 <= r_v_014;
end
endcase
end
end
endmodule
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol (backslash, in ascii) in a function abstraction
[\x:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t1] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
(** Finally, having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(* ###################################################################### *)
(** *** Free Variables and Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)] yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11.t12) = \x:T11. t12
[x:=s](\y:T11.t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
(* FILL IN HERE *)
.
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
(* FILL IN HERE *) Admitted.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t : T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->B. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x : T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End STLC.
(* $Date: 2013-07-18 09:59:22 -0400 (Thu, 18 Jul 2013) $ *)
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora Module Generator version 2.8
//
// Date: $Date: 2007/09/28 12:50:34 $
// Tag: $Name: i+HEAD+134158 $
// File: $RCSfile: aurora_lane_gtp.ejava,v $
// Rev: $Revision: 1.2 $
//
// Company: Xilinx
//
// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
// APPLICATION OR STANDARD, XILINX IS MAKING NO
// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// AURORA_LANE
//
//
// Description: The AURORA_LANE module provides a full duplex 2-byte aurora
// lane connection using a single GTP. The module handles lane
// initialization, symbol generation and decoding as well as
// error detection. It also decodes some of the channel bonding
// indicator signals needed by the Global logic.
//
// * Supports GTP
//
`timescale 1 ns / 10 ps
module aurora_201_AURORA_LANE
(
// GTP Interface
RX_DATA,
RX_NOT_IN_TABLE,
RX_DISP_ERR,
RX_CHAR_IS_K,
RX_CHAR_IS_COMMA,
RX_STATUS,
RX_BUF_ERR,
TX_BUF_ERR,
RX_REALIGN,
RX_POLARITY,
RX_RESET,
TX_CHAR_IS_K,
TX_DATA,
TX_RESET,
// Comma Detect Phase Align Interface
ENA_COMMA_ALIGN,
// TX_LL Interface
GEN_SCP,
GEN_ECP,
GEN_PAD,
TX_PE_DATA,
TX_PE_DATA_V,
GEN_CC,
// RX_LL Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// Global Logic Interface
GEN_A,
GEN_K,
GEN_R,
GEN_V,
LANE_UP,
SOFT_ERROR,
HARD_ERROR,
CHANNEL_BOND_LOAD,
GOT_A,
GOT_V,
//System Interface
USER_CLK,
RESET
);
//***********************************Port Declarations*******************************
// GTP Interface
input [15:0] RX_DATA; // 2-byte data bus from the GTP.
input [1:0] RX_NOT_IN_TABLE; // Invalid 10-bit code was recieved.
input [1:0] RX_DISP_ERR; // Disparity error detected on RX interface.
input [1:0] RX_CHAR_IS_K; // Indicates which bytes of RX_DATA are control.
input [1:0] RX_CHAR_IS_COMMA; // Comma received on given byte.
input [5:0] RX_STATUS; // Part of GTP status and error bus.
input RX_BUF_ERR; // Overflow/Underflow of RX buffer detected.
input TX_BUF_ERR; // Overflow/Underflow of TX buffer detected.
input RX_REALIGN; // SERDES was realigned because of a new comma.
output RX_POLARITY; // Controls interpreted polarity of serial data inputs.
output RX_RESET; // Reset RX side of GTP logic.
output [1:0] TX_CHAR_IS_K; // TX_DATA byte is a control character.
output [15:0] TX_DATA; // 2-byte data bus to the GTP.
output TX_RESET; // Reset TX side of GTP logic.
// Comma Detect Phase Align Interface
output ENA_COMMA_ALIGN; // Request comma alignment.
// TX_LL Interface
input GEN_SCP; // SCP generation request from TX_LL.
input GEN_ECP; // ECP generation request from TX_LL.
input GEN_PAD; // PAD generation request from TX_LL.
input [0:15] TX_PE_DATA; // Data from TX_LL to send over lane.
input TX_PE_DATA_V; // Indicates TX_PE_DATA is Valid.
input GEN_CC; // CC generation request from TX_LL.
// RX_LL Interface
output RX_PAD; // Indicates lane received PAD.
output [0:15] RX_PE_DATA; // RX data from lane to RX_LL.
output RX_PE_DATA_V; // RX_PE_DATA is data, not control symbol.
output RX_SCP; // Indicates lane received SCP.
output RX_ECP; // Indicates lane received ECP.
// Global Logic Interface
input GEN_A; // 'A character' generation request from Global Logic.
input [0:1] GEN_K; // 'K character' generation request from Global Logic.
input [0:1] GEN_R; // 'R character' generation request from Global Logic.
input [0:1] GEN_V; // Verification data generation request.
output LANE_UP; // Lane is ready for bonding and verification.
output SOFT_ERROR; // Soft error detected.
output HARD_ERROR; // Hard error detected.
output CHANNEL_BOND_LOAD; // Channel Bonding done code recieved.
output [0:1] GOT_A; // Indicates lane recieved 'A character' bytes.
output GOT_V; // Verification symbols received.
// System Interface
input USER_CLK; // System clock for all non-GTP Aurora Logic.
input RESET; // Reset the lane.
//*********************************Wire Declarations**********************************
wire gen_k_i;
wire [0:1] gen_sp_data_i;
wire [0:1] gen_spa_data_i;
wire rx_sp_i;
wire rx_spa_i;
wire rx_neg_i;
wire enable_error_detect_i;
wire do_word_align_i;
wire hard_error_reset_i;
//*********************************Main Body of Code**********************************
// Lane Initialization state machine
aurora_201_LANE_INIT_SM lane_init_sm_i
(
// GTP Interface
.RX_NOT_IN_TABLE(RX_NOT_IN_TABLE),
.RX_DISP_ERR(RX_DISP_ERR),
.RX_CHAR_IS_COMMA(RX_CHAR_IS_COMMA),
.RX_REALIGN(RX_REALIGN),
.RX_RESET(RX_RESET),
.TX_RESET(TX_RESET),
.RX_POLARITY(RX_POLARITY),
// Comma Detect Phase Alignment Interface
.ENA_COMMA_ALIGN(ENA_COMMA_ALIGN),
// Symbol Generator Interface
.GEN_K(gen_k_i),
.GEN_SP_DATA(gen_sp_data_i),
.GEN_SPA_DATA(gen_spa_data_i),
// Symbol Decoder Interface
.RX_SP(rx_sp_i),
.RX_SPA(rx_spa_i),
.RX_NEG(rx_neg_i),
.DO_WORD_ALIGN(do_word_align_i),
// Error Detection Logic Interface
.HARD_ERROR_RESET(hard_error_reset_i),
.ENABLE_ERROR_DETECT(enable_error_detect_i),
// Global Logic Interface
.LANE_UP(LANE_UP),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
// Channel Bonding Count Decode module
aurora_201_CHBOND_COUNT_DEC chbond_count_dec_i
(
.RX_STATUS(RX_STATUS),
.CHANNEL_BOND_LOAD(CHANNEL_BOND_LOAD),
.USER_CLK(USER_CLK)
);
// Symbol Generation module
aurora_201_SYM_GEN sym_gen_i
(
// TX_LL Interface
.GEN_SCP(GEN_SCP),
.GEN_ECP(GEN_ECP),
.GEN_PAD(GEN_PAD),
.TX_PE_DATA(TX_PE_DATA),
.TX_PE_DATA_V(TX_PE_DATA_V),
.GEN_CC(GEN_CC),
// Global Logic Interface
.GEN_A(GEN_A),
.GEN_K(GEN_K),
.GEN_R(GEN_R),
.GEN_V(GEN_V),
// Lane Init SM Interface
.GEN_K_FSM(gen_k_i),
.GEN_SP_DATA(gen_sp_data_i),
.GEN_SPA_DATA(gen_spa_data_i),
// GTP Interface
.TX_CHAR_IS_K({TX_CHAR_IS_K[0],TX_CHAR_IS_K[1]}),
.TX_DATA({TX_DATA[7:0],TX_DATA[15:8]}),
// System Interface
.USER_CLK(USER_CLK)
);
// Symbol Decode module
aurora_201_SYM_DEC sym_dec_i
(
// RX_LL Interface
.RX_PAD(RX_PAD),
.RX_PE_DATA(RX_PE_DATA),
.RX_PE_DATA_V(RX_PE_DATA_V),
.RX_SCP(RX_SCP),
.RX_ECP(RX_ECP),
// Lane Init SM Interface
.DO_WORD_ALIGN(do_word_align_i),
.RX_SP(rx_sp_i),
.RX_SPA(rx_spa_i),
.RX_NEG(rx_neg_i),
// Global Logic Interface
.GOT_A(GOT_A),
.GOT_V(GOT_V),
// GTP Interface
.RX_DATA({RX_DATA[7:0],RX_DATA[15:8]}),
.RX_CHAR_IS_K({RX_CHAR_IS_K[0],RX_CHAR_IS_K[1]}),
.RX_CHAR_IS_COMMA({RX_CHAR_IS_COMMA[0],RX_CHAR_IS_COMMA[1]}),
// System Interface
.USER_CLK(USER_CLK),
.RESET(RESET)
);
// Error Detection module
aurora_201_ERROR_DETECT error_detect_i
(
// Lane Init SM Interface
.ENABLE_ERROR_DETECT(enable_error_detect_i),
.HARD_ERROR_RESET(hard_error_reset_i),
// Global Logic Interface
.SOFT_ERROR(SOFT_ERROR),
.HARD_ERROR(HARD_ERROR),
// GTP Interface
.RX_BUF_ERR(RX_BUF_ERR),
.RX_DISP_ERR({RX_DISP_ERR[0],RX_DISP_ERR[1]}),
.RX_NOT_IN_TABLE({RX_NOT_IN_TABLE[0],RX_NOT_IN_TABLE[1]}),
.TX_BUF_ERR(TX_BUF_ERR),
.RX_REALIGN(RX_REALIGN),
// System Interface
.USER_CLK(USER_CLK)
);
endmodule
|
/***********************************************
Module Name: CORDIC
Feature: CORDIC algorithm
An example for the GEM Projects
Coder: Garfield
Organization: xxxx Group, Department of Architecture
------------------------------------------------------
Input ports: clk: System clock
Reset_n: System reset
opernd: input number to be calculated
Output Ports: results: results of operation
------------------------------------------------------
History:
06-21-2016: First Version by Garfield
06-21-2016: Verified by CORDIC_Test
***********************************************/
`define ORDER 12
// CORDIC order by simulation
`define WIDTH 15
//CORDIC ports bit width by simulatation
`define K 14'h26DD
module CORDIC
#(parameter MODE = 1)
//CORDIC Mode
(
CLK,
RESET_n,
operand,
results
);
localparam PORT_WIDTH = (MODE == 3) ? (7 + `WIDTH) : ( (MODE == 2) ? (2 + `WIDTH) :(`WIDTH));
localparam IN_WIDTH = 2 * PORT_WIDTH;
localparam OUT_WIDTH = 2 * PORT_WIDTH;
localparam ONE = 15'd16384;
input CLK;
input RESET_n;
input signed[(IN_WIDTH - 1) : 0] operand;
output signed[(OUT_WIDTH - 1) : 0] results;
wire[(PORT_WIDTH-1):0] x[(`ORDER+1):0];
wire[(PORT_WIDTH-1):0] y[(`ORDER+1):0];
wire[(PORT_WIDTH-1):0] z[(`ORDER+1):0];
//middle signals
generate
begin
case(MODE)
1:
begin
assign x[0] = `K;
assign y[0] = 14'h0;
assign z[0] = operand[PORT_WIDTH -1 : 0];
end
2:
begin
assign x[0] = ONE;
assign y[0] = operand[PORT_WIDTH -1 : 0];
assign z[0] = 14'h0;
end
3:
begin
assign x[0] = operand[PORT_WIDTH -1 : 0];
assign y[0] = operand[2*PORT_WIDTH -1 : PORT_WIDTH];
assign z[0] = 14'h0;
end
default:
begin
assign x[0] = `K;
assign y[0] = 14'h0;
assign z[0] = operand[PORT_WIDTH -1 : 0];
end
endcase
end
endgenerate
generate
begin
case(MODE)
1:
begin
assign results = {x[13], y[13]};
end
2:
begin
assign results = {{(PORT_WIDTH){1'b0}}, z[13]};
end
3:
begin
assign results = {{(PORT_WIDTH){1'b0}}, x[13]};
end
default:
begin
assign results = {x[13], y[13]};
end
endcase
end
endgenerate
//CORDIC pipeline
//Connection to the modules
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h3243), .ORDER(0), .MODE(MODE) )
CE0 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[0]), .y_k(y[0]), .z_k(z[0]),
.x_k1(x[1]), .y_k1(y[1]), .z_k1(z[1]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h1DAC), .ORDER(1), .MODE(MODE) )
CE1 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[1]), .y_k(y[1]), .z_k(z[1]),
.x_k1(x[2]), .y_k1(y[2]), .z_k1(z[2]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0FAD), .ORDER(2), .MODE(MODE) )
CE2 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[2]), .y_k(y[2]), .z_k(z[2]),
.x_k1(x[3]), .y_k1(y[3]), .z_k1(z[3]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h07F5), .ORDER(3) , .MODE(MODE) )
CE3 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[3]), .y_k(y[3]), .z_k(z[3]),
.x_k1(x[4]), .y_k1(y[4]), .z_k1(z[4]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h03FE), .ORDER(4) , .MODE(MODE) )
CE4 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[4]), .y_k(y[4]), .z_k(z[4]),
.x_k1(x[5]), .y_k1(y[5]), .z_k1(z[5]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h01FF), .ORDER(5) , .MODE(MODE) )
CE5 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[5]), .y_k(y[5]), .z_k(z[5]),
.x_k1(x[6]), .y_k1(y[6]), .z_k1(z[6]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h00FF), .ORDER(6) , .MODE(MODE) )
CE6 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[6]), .y_k(y[6]), .z_k(z[6]),
.x_k1(x[7]), .y_k1(y[7]), .z_k1(z[7]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h007F), .ORDER(7) , .MODE(MODE) )
CE7 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[7]), .y_k(y[7]), .z_k(z[7]),
.x_k1(x[8]), .y_k1(y[8]), .z_k1(z[8]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h003F), .ORDER(8) , .MODE(MODE) )
CE8 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[8]), .y_k(y[8]), .z_k(z[8]),
.x_k1(x[9]), .y_k1(y[9]), .z_k1(z[9]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h001F), .ORDER(9) , .MODE(MODE) )
CE9 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[9]), .y_k(y[9]), .z_k(z[9]),
.x_k1(x[10]), .y_k1(y[10]), .z_k1(z[10]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h000F), .ORDER(10) , .MODE(MODE) )
CE10 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[10]), .y_k(y[10]), .z_k(z[10]),
.x_k1(x[11]), .y_k1(y[11]), .z_k1(z[11]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0007), .ORDER(11) , .MODE(MODE) )
CE11 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[11]), .y_k(y[11]), .z_k(z[11]),
.x_k1(x[12]), .y_k1(y[12]), .z_k1(z[12]) );
CORDIC_elemet #(.ADDRESS_WIDTH(PORT_WIDTH-1), .VALUE_WIDTH(PORT_WIDTH-1), .e_k(14'h0003), .ORDER(12) , .MODE(MODE) )
CE12 ( .CLK(CLK), .RESET_n(RESET_n),
.x_k(x[12]), .y_k(y[12]), .z_k(z[12]),
.x_k1(x[13]), .y_k1(y[13]), .z_k1(z[13]) );
endmodule |
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : arb_row_col.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block receives request to send row and column commands and
// requests to change the IO configuration. These requests come
// the individual bank machines. The arbitration winner is selected
// and driven back to the bank machines.
//
// The CS enables are generated. For 2:1 mode, row commands are sent
// in the "0" phase, and column commands are sent in the "1" phase.
//
// In 2T mode, a further arbitration is performed between the row
// and column commands. The winner of this arbitration inhibits
// arbitration by the loser. The winner is allowed to arbitrate, the loser is
// blocked until the next state. The winning address command
// is repeated on both the "0" and the "1" phases and the CS
// is asserted for just the "1" phase.
`timescale 1 ps / 1 ps
module arb_row_col #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter CWL = 5,
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nCNFG2WR = 2,
parameter nRAS = 37500, // ACT->PRE cmd period (CKs)
parameter nRCD = 12500, // ACT->R/W delay (CKs)
parameter nWR = 6 // Write recovery (CKs)
)
(/*AUTOARG*/
// Outputs
grant_row_r, grant_pre_r, sent_row, sending_row, sending_pre, grant_config_r,
io_config_strobe, force_io_config_rd_r1, io_config_valid_r,
grant_col_r, sending_col, sent_col, grant_col_wr, send_cmd0_col,
send_cmd1_row, send_cmd1_col, send_cmd1_pre, send_cmd2_col, send_cmd2_pre,
send_cmd3_col, col_channel_offset, send_cmd3_pre, cs_en0, cs_en1, cs_en2,
cs_en3, insert_maint_r1,
// Inputs
clk, rst, rts_row, rts_pre, insert_maint_r, rts_col, rtc,
force_io_config_rd_r, col_rdy_wr
);
input clk;
input rst;
input [nBANK_MACHS-1:0] rts_row;
input insert_maint_r;
input [nBANK_MACHS-1:0] rts_col;
reg io_config_strobe_r;
wire block_grant_row;
wire block_grant_col;
wire io_config_kill_rts_col = (nCNFG2WR <= 1) ? 1'b0 : io_config_strobe_r;
wire [nBANK_MACHS-1:0] col_request;
wire granted_col_ns = |col_request;
wire [nBANK_MACHS-1:0] row_request =
rts_row & {nBANK_MACHS{~insert_maint_r}};
wire granted_row_ns = |row_request;
generate
if (ADDR_CMD_MODE == "2T") begin : row_col_2T_arb
assign col_request =
rts_col & {nBANK_MACHS{~(io_config_kill_rts_col || insert_maint_r)}};
// Give column command priority whenever previous state has no row request.
wire [1:0] row_col_grant;
wire [1:0] current_master = ~granted_row_ns ? 2'b10 : row_col_grant;
wire upd_last_master = ~granted_row_ns || |row_col_grant;
round_robin_arb #
(.WIDTH (2))
row_col_arb0
(.grant_ns (),
.grant_r (row_col_grant),
.upd_last_master (upd_last_master),
.current_master (current_master),
.clk (clk),
.rst (rst),
.req ({granted_row_ns, granted_col_ns}),
.disable_grant (1'b0));
assign {block_grant_col, block_grant_row} = row_col_grant;
end
else begin : row_col_1T_arb
assign col_request = rts_col & {nBANK_MACHS{~io_config_kill_rts_col}};
assign block_grant_row = 1'b0;
assign block_grant_col = 1'b0;
end
endgenerate
// Row address/command arbitration.
wire[nBANK_MACHS-1:0] grant_row_r_lcl;
output wire[nBANK_MACHS-1:0] grant_row_r;
assign grant_row_r = grant_row_r_lcl;
reg granted_row_r;
always @(posedge clk) granted_row_r <= #TCQ granted_row_ns;
wire sent_row_lcl = granted_row_r && ~block_grant_row;
output wire sent_row;
assign sent_row = sent_row_lcl;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
row_arb0
(.grant_ns (),
.grant_r (grant_row_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_row_lcl),
.current_master (grant_row_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (row_request),
.disable_grant (1'b0));
output wire [nBANK_MACHS-1:0] sending_row;
assign sending_row = grant_row_r_lcl & {nBANK_MACHS{~block_grant_row}};
// Precharge arbitration for 4:1 mode
input [nBANK_MACHS-1:0] rts_pre;
output wire[nBANK_MACHS-1:0] grant_pre_r;
output wire [nBANK_MACHS-1:0] sending_pre;
wire sent_pre_lcl;
generate
if((nCK_PER_CLK == 4) && (ADDR_CMD_MODE != "2T")) begin : pre_4_1_1T_arb
reg granted_pre_r;
wire[nBANK_MACHS-1:0] grant_pre_r_lcl;
wire granted_pre_ns = |rts_pre;
assign grant_pre_r = grant_pre_r_lcl;
always @(posedge clk) granted_pre_r <= #TCQ granted_pre_ns;
assign sent_pre_lcl = granted_pre_r;
assign sending_pre = grant_pre_r_lcl;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
pre_arb0
(.grant_ns (),
.grant_r (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_pre_lcl),
.current_master (grant_pre_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rts_pre),
.disable_grant (1'b0));
end
endgenerate
`ifdef MC_SVA
all_bank_machines_row_arb:
cover property (@(posedge clk) (~rst && &rts_row));
`endif
// IO config arbitration.
input [nBANK_MACHS-1:0] rtc;
wire [nBANK_MACHS-1:0] grant_config_r_lcl;
output wire [nBANK_MACHS-1:0] grant_config_r;
assign grant_config_r = grant_config_r_lcl;
wire upd_io_config_last_master;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
config_arb0
(.grant_ns (),
.grant_r (grant_config_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (upd_io_config_last_master),
.current_master (grant_config_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (rtc[nBANK_MACHS-1:0]),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_config_arb: cover property (@(posedge clk) (~rst && &rtc));
`endif
input force_io_config_rd_r;
wire io_config_strobe_ns =
~io_config_strobe_r && (|rtc || force_io_config_rd_r) && ~granted_col_ns;
always @(posedge clk) io_config_strobe_r <= #TCQ io_config_strobe_ns;
output wire io_config_strobe;
assign io_config_strobe = io_config_strobe_r;
reg force_io_config_rd_r1_lcl;
always @(posedge clk) force_io_config_rd_r1_lcl <=
#TCQ force_io_config_rd_r;
output wire force_io_config_rd_r1;
assign force_io_config_rd_r1 = force_io_config_rd_r1_lcl;
assign upd_io_config_last_master =
io_config_strobe_r && ~force_io_config_rd_r1_lcl;
// Generate io_config_valid.
reg io_config_valid_r_lcl;
wire io_config_valid_ns;
assign io_config_valid_ns =
~rst && (io_config_valid_r_lcl || io_config_strobe_ns);
always @(posedge clk) io_config_valid_r_lcl <= #TCQ io_config_valid_ns;
output wire io_config_valid_r;
assign io_config_valid_r = io_config_valid_r_lcl;
// Column address/command arbitration.
wire [nBANK_MACHS-1:0] grant_col_r_lcl;
output wire [nBANK_MACHS-1:0] grant_col_r;
assign grant_col_r = grant_col_r_lcl;
reg granted_col_r;
always @(posedge clk) granted_col_r <= #TCQ granted_col_ns;
wire sent_col_lcl;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (),
.grant_r (grant_col_r_lcl[nBANK_MACHS-1:0]),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_request),
.disable_grant (1'b0));
`ifdef MC_SVA
all_bank_machines_col_arb:
cover property (@(posedge clk) (~rst && &rts_col));
`endif
output wire [nBANK_MACHS-1:0] sending_col;
assign sending_col = grant_col_r_lcl & {nBANK_MACHS{~block_grant_col}};
assign sent_col_lcl = granted_col_r && ~block_grant_col;
output wire sent_col;
assign sent_col = sent_col_lcl;
// If we need early wr_data_addr because ECC is on, arbitrate
// to see which bank machine might sent the next wr_data_addr;
input [nBANK_MACHS-1:0] col_rdy_wr;
output wire [nBANK_MACHS-1:0] grant_col_wr;
generate
if (EARLY_WR_DATA_ADDR == "OFF") begin : early_wr_addr_arb_off
assign grant_col_wr = {nBANK_MACHS{1'b0}};
end
else begin : early_wr_addr_arb_on
wire [nBANK_MACHS-1:0] grant_col_wr_raw;
round_robin_arb #
(.WIDTH (nBANK_MACHS))
col_arb0
(.grant_ns (grant_col_wr_raw),
.grant_r (),
.upd_last_master (sent_col_lcl),
.current_master (grant_col_r_lcl[nBANK_MACHS-1:0]),
.clk (clk),
.rst (rst),
.req (col_rdy_wr),
.disable_grant (1'b0));
reg [nBANK_MACHS-1:0] grant_col_wr_r;
wire [nBANK_MACHS-1:0] grant_col_wr_ns = granted_col_ns
? grant_col_wr_raw
: grant_col_wr_r;
always @(posedge clk) grant_col_wr_r <= #TCQ grant_col_wr_ns;
assign grant_col_wr = grant_col_wr_ns;
end // block: early_wr_addr_arb_on
endgenerate
output reg send_cmd0_col = 1'b0;
output reg send_cmd1_row = 1'b0;
output reg send_cmd1_col = 1'b0;
output reg send_cmd1_pre = 1'b0;
output reg send_cmd2_col = 1'b0;
output reg send_cmd2_pre = 1'b0;
output reg send_cmd3_col = 1'b0;
output reg send_cmd3_pre = 1'b0;
output reg cs_en0 = 1'b0;
output reg cs_en1 = 1'b0;
output reg cs_en2 = 1'b0;
output reg cs_en3 = 1'b0;
output wire [5:0] col_channel_offset;
reg insert_maint_r1_lcl;
always @(posedge clk) insert_maint_r1_lcl <= #TCQ insert_maint_r;
output wire insert_maint_r1;
assign insert_maint_r1 = insert_maint_r1_lcl;
wire sent_row_or_maint = sent_row_lcl || insert_maint_r1_lcl;
generate
case ({(nCK_PER_CLK == 4), (nCK_PER_CLK == 2), (ADDR_CMD_MODE == "2T")})
3'b000 : begin : one_one_not2T
end
3'b001 : begin : one_one_2T
end
3'b010 : begin : two_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) cs_en0 = sent_row_or_maint;
always @(sent_col_lcl) cs_en1 = sent_col_lcl;
assign col_channel_offset = 1;
end
end
3'b011 : begin : two_one_2T
always @(sent_col_lcl or sent_row_or_maint)
cs_en1 = sent_row_or_maint || sent_col_lcl;
always @(sent_row_or_maint) send_cmd1_row = sent_row_or_maint;
always @(sent_col_lcl) send_cmd0_col = sent_col_lcl;
assign col_channel_offset = 1;
end
3'b100 : begin : four_one_not2T
if(!(CWL % 2)) begin // Place column commands on slot 0 for even CWL
always @(sent_col_lcl) begin
cs_en0 = sent_col_lcl;
send_cmd0_col = sent_col_lcl;
end
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
assign col_channel_offset = 0;
end
else begin // Place column commands on slot 1 for odd CWL
always @(sent_row_or_maint) cs_en0 = sent_row_or_maint;
always @(sent_col_lcl) cs_en1 = sent_col_lcl;
assign col_channel_offset = 1;
end
always @(sent_pre_lcl) cs_en2 = sent_pre_lcl;
end
3'b101 : begin : four_one_2T
always @(sent_row_or_maint) begin
cs_en1 = sent_row_or_maint;
send_cmd1_row = sent_row_or_maint;
end
always @(sent_col_lcl) begin
cs_en3 = sent_col_lcl;
send_cmd2_col = sent_col_lcl;
send_cmd3_col = sent_col_lcl;
end
assign col_channel_offset = 3;
end
endcase
endgenerate
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
input sgmii_refclk_p,
input sgmii_refclk_n,
input [3:0] sgmii_rxn,
input [3:0] sgmii_rxp,
output [3:0] sgmii_txn,
output [3:0] sgmii_txp,
output mdio_mdc,
inout mdio_mdio,
output [1:0] pl_led,
output [1:0] pl_pmod,
input pl_btn
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
wire bd_aresetn ;
//wire sgmii_refclk_se;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod[0] = cnt_3[23];
assign pl_pmod[1] = bd_aresetn;
// sgmii ref clk
/*
IBUFDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IBUF_LOW_PWR("TRUE"), // Low power="TRUE", Highest performance="FALSE"
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFDS_i_sgmii_refclk (
.O (sgmii_refclk_se), // Buffer output
.I (sgmii_refclk_p), // Diff_p buffer input (connect directly to top-level port)
.IB (sgmii_refclk_n) // Diff_n buffer input (connect directly to top-level port)
);
*/
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.mdio_mdc (mdio_mdc ),
.mdio_mdio_io (mdio_mdio ),
.ref_clk_125_n (sgmii_refclk_n ),
.ref_clk_125_p (sgmii_refclk_p ),
.sgmii_0_rxn (sgmii_rxn[0] ),
.sgmii_0_rxp (sgmii_rxp[0] ),
.sgmii_0_txn (sgmii_txn[0] ),
.sgmii_0_txp (sgmii_txp[0] ),
.sgmii_1_rxn (sgmii_rxn[1] ),
.sgmii_1_rxp (sgmii_rxp[1] ),
.sgmii_1_txn (sgmii_txn[1] ),
.sgmii_1_txp (sgmii_txp[1] ),
.sgmii_2_rxn (sgmii_rxn[2] ),
.sgmii_2_rxp (sgmii_rxp[2] ),
.sgmii_2_txn (sgmii_txn[2] ),
.sgmii_2_txp (sgmii_txp[2] ),
.sgmii_3_rxn (sgmii_rxn[3] ),
.sgmii_3_rxp (sgmii_rxp[3] ),
.sgmii_3_txn (sgmii_txn[3] ),
.sgmii_3_txp (sgmii_txp[3] ),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m ),
.bd_aresetn ( bd_aresetn ),
.ext_rst ( pl_btn )
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Allowed import return types:
// void, byte, shortint, int, longint, real, shortreal, chandle, and string
// Scalar bit and logic
//
// Allowed argument types:
// Same as above plus packed arrays
import "DPI-C" pure function bit dpii_f_bit (input bit i);
import "DPI-C" pure function bit [8-1:0] dpii_f_bit8 (input bit [8-1:0] i);
import "DPI-C" pure function bit [9-1:0] dpii_f_bit9 (input bit [9-1:0] i);
import "DPI-C" pure function bit [16-1:0] dpii_f_bit16 (input bit [16-1:0] i);
import "DPI-C" pure function bit [17-1:0] dpii_f_bit17 (input bit [17-1:0] i);
import "DPI-C" pure function bit [32-1:0] dpii_f_bit32 (input bit [32-1:0] i);
// Illegal to return > 32 bits, so we use longint
import "DPI-C" pure function longint dpii_f_bit33 (input bit [33-1:0] i);
import "DPI-C" pure function longint dpii_f_bit64 (input bit [64-1:0] i);
import "DPI-C" pure function int dpii_f_int (input int i);
import "DPI-C" pure function byte dpii_f_byte (input byte i);
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
import "DPI-C" pure function void dpii_v_byte (input byte i, output byte o);
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
import "DPI-C" pure function void dpii_v_uint (input int unsigned i, output int unsigned o);
import "DPI-C" pure function void dpii_v_ushort (input shortint unsigned i, output shortint unsigned o);
import "DPI-C" pure function void dpii_v_ulong (input longint unsigned i, output longint unsigned o);
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" pure function void dpii_v_bit64 (input bit [64-1:0] i, output bit [64-1:0] o);
import "DPI-C" pure function void dpii_v_bit95 (input bit [95-1:0] i, output bit [95-1:0] o);
import "DPI-C" pure function void dpii_v_bit96 (input bit [96-1:0] i, output bit [96-1:0] o);
import "DPI-C" pure function int dpii_f_strlen (input string i);
import "DPI-C" function void dpii_f_void ();
// Try a task
import "DPI-C" task dpii_t_void ();
import "DPI-C" context task dpii_t_void_context ();
import "DPI-C" task dpii_t_int (input int i, output int o);
// Try non-pure, aliasing with name
import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i);
import "DPI-C" dpii_fa_bit = function int oth_f_int2(input int i);
bit i_b, o_b;
bit [7:0] i_b8;
bit [8:0] i_b9;
bit [15:0] i_b16;
bit [16:0] i_b17;
bit [31:0] i_b32;
bit [32:0] i_b33, o_b33;
bit [63:0] i_b64, o_b64;
bit [94:0] i_b95, o_b95;
bit [95:0] i_b96, o_b96;
int i_i, o_i;
byte i_y, o_y;
shortint i_s, o_s;
longint i_l, o_l;
int unsigned i_iu, o_iu;
shortint unsigned i_su, o_su;
longint unsigned i_lu, o_lu;
// verilator lint_off UNDRIVEN
chandle i_c, o_c;
string i_n, o_n;
// verilator lint_on UNDRIVEN
real i_d, o_d;
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [94:0] wide;
bit [6*8:1] string6;
initial begin
wide = 95'h15caff7a73c48afee4ffcb57;
i_b = 1'b1;
i_b8 = {1'b1,wide[8-2:0]};
i_b9 = {1'b1,wide[9-2:0]};
i_b16 = {1'b1,wide[16-2:0]};
i_b17 = {1'b1,wide[17-2:0]};
i_b32 = {1'b1,wide[32-2:0]};
i_b33 = {1'b1,wide[33-2:0]};
i_b64 = {1'b1,wide[64-2:0]};
i_b95 = {1'b1,wide[95-2:0]};
i_b96 = {1'b1,wide[96-2:0]};
i_i = {1'b1,wide[32-2:0]};
i_iu= {1'b1,wide[32-2:0]};
i_y = {1'b1,wide[8-2:0]};
i_s = {1'b1,wide[16-2:0]};
i_su= {1'b1,wide[16-2:0]};
i_l = {1'b1,wide[64-2:0]};
i_lu= {1'b1,wide[64-2:0]};
i_d = 32.1;
`ifndef NO_SHORTREAL
i_f = 30.2;
`endif
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_bit8 (i_b8) !== ~i_b8) $stop;
if (dpii_f_bit9 (i_b9) !== ~i_b9) $stop;
if (dpii_f_bit16 (i_b16) !== ~i_b16) $stop;
if (dpii_f_bit17 (i_b17) !== ~i_b17) $stop;
if (dpii_f_bit32 (i_b32) !== ~i_b32) $stop;
// These return different sizes, so we need to truncate
// verilator lint_off WIDTH
o_b33 = dpii_f_bit33 (i_b33);
o_b64 = dpii_f_bit64 (i_b64);
// verilator lint_on WIDTH
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_d) != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_uint (i_iu,o_iu); if (o_iu !== ~i_iu) $stop;
dpii_v_ushort (i_su,o_su); if (o_su !== ~i_su) $stop;
dpii_v_ulong (i_lu,o_lu); if (o_lu !== ~i_lu) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
dpii_v_real (i_d,o_d); if (o_d != i_d+1.5) $stop;
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_v_bit64 (i_b64,o_b64); if (o_b64 !== ~i_b64) $stop;
dpii_v_bit95 (i_b95,o_b95); if (o_b95 !== ~i_b95) $stop;
dpii_v_bit96 (i_b96,o_b96); if (o_b96 !== ~i_b96) $stop;
if (dpii_f_strlen ("")!=0) $stop;
if (dpii_f_strlen ("s")!=1) $stop;
if (dpii_f_strlen ("st")!=2) $stop;
if (dpii_f_strlen ("str")!=3) $stop;
if (dpii_f_strlen ("stri")!=4) $stop;
if (dpii_f_strlen ("string_l")!=8) $stop;
if (dpii_f_strlen ("string_len")!=10) $stop;
string6 = "hello6";
`ifdef VERILATOR
string6 = $c48(string6); // Don't optimize away - want to see the constant conversion function
`endif
if (dpii_f_strlen (string6) != 6) $stop;
dpii_f_void();
dpii_t_void();
dpii_t_void_context();
i_i = 32'h456789ab;
dpii_t_int (i_i,o_i); if (o_b !== ~i_b) $stop;
// Check alias
if (oth_f_int1(32'd123) !== ~32'd123) $stop;
if (oth_f_int2(32'd124) !== ~32'd124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
i_b <= ~i_b;
// This once mis-threw a BLKSEQ warning
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFBBN_SYMBOL_V
`define SKY130_FD_SC_HD__SDFBBN_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFBBN_SYMBOL_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_sdiv(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataouta, o_dataouta_valid, i_dataouta_stall,
o_dataoutb, o_dataoutb_valid, i_dataoutb_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 32;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataouta, o_dataoutb;
output o_dataouta_valid, o_dataoutb_valid;
input i_dataouta_stall, i_dataoutb_stall;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_fifo_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_a_valid & is_fifo_b_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & (i_dataouta_stall | i_dataoutb_stall));
assign is_fifo_stalled = (shift_reg_valid[0] & (i_dataouta_stall | i_dataoutb_stall)) | !(is_fifo_a_valid & is_fifo_b_valid);
acl_int_div32s sdiv_unit(
.enable(~is_stalled), .clock(clock), .denom(datab), .numer(dataa),
.quotient(o_dataouta), .remain(o_dataoutb));
assign o_dataouta_valid = shift_reg_valid[0];
assign o_dataoutb_valid = shift_reg_valid[0];
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXC Engine (Classic) takes a single stream of TLP
// packets and provides the completion packets on the RXC Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "tlp.vh"
module rxc_engine_classic
#(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH = 10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXC_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXC Engine
output [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
output RXC_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
output RXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
output RXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
output [`SIG_LBE_W-1:0] RXC_META_LDWBE,
output [`SIG_FBE_W-1:0] RXC_META_FDWBE,
output [`SIG_TAG_W-1:0] RXC_META_TAG,
output [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
output [`SIG_TYPE_W-1:0] RXC_META_TYPE,
output [`SIG_LEN_W-1:0] RXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
output [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
output RXC_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID);
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_RX_DATA_STAGES = C_RX_COMPUTATION_STAGES;
localparam C_RX_META_STAGES = C_RX_DATA_STAGES - 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// Cycle index in the SOP register when enable is raised
// Computation can begin when the last DW of the header is recieved.
localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH);
// The computation cycle must be at least one cycle before the address is enabled
localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
localparam C_RX_METADW0_CYCLE = (`TLP_CPLMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`TLP_CPLMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW2_CYCLE = (`TLP_CPLMETADW2_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW2_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_CPLMETADW2_I%C_PCI_DATA_WIDTH);
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_MAX_ABLANK_WIDTH = 32;
localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
wire [`TLP_CPLADDR_W-1:0] wAddr;
wire [`TLP_CPLHDR_W-1:0] wMetadata;
wire [`TLP_TYPE_W-1:0] wType;
wire [`TLP_LEN_W-1:0] wLength;
wire [2:0] wHdrLength;
wire [2:0] wHdrLengthM1;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire wEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire wStartFlag;
wire _wStartFlag;
wire [2:0] wStartOffset;
wire [3:0] wStartFlags;
wire wInsertBlank;
wire [C_PCI_DATA_WIDTH-1:0] wRxcData;
wire [95:0] wRxcMetadata;
wire wRxcDataValid;
wire wRxcDataEndFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataEndOffset;
wire wRxcDataStartFlag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataStartOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxcDataWordEnable;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
reg rValid,_rValid;
reg rRST;
assign DONE_RXC_RST = ~rRST;
// Calculate the header length (start offset), and header length minus 1 (end offset)
assign wHdrLength = 3'b011;
assign wHdrLengthM1 = 3'b010;
// Determine if the TLP has an inserted blank before the payload
assign wInsertBlank = ~wAddr[2] & (C_VENDOR == "ALTERA");
assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength; //RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
// Outputs
assign RXC_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXC_DATA_VALID = wRxcDataValid;
assign RXC_DATA_END_FLAG = wRxcDataEndFlag;
assign RXC_DATA_END_OFFSET = wRxcDataEndOffset;
assign RXC_DATA_START_FLAG = wRxcDataStartFlag;
assign RXC_DATA_START_OFFSET = wRxcDataStartOffset;
assign RXC_META_LENGTH = wRxcMetadata[`TLP_LEN_R];
//assign RXC_META_TC = wRxcMetadata[`TLP_TC_R];
//assign RXC_META_ATTR = {wRxcMetadata[`TLP_ATTR1_R], wRxcMetadata[`TLP_ATTR0_R]};
assign RXC_META_TYPE = tlp_to_trellis_type({wRxcMetadata[`TLP_FMT_R],wRxcMetadata[`TLP_TYPE_R]});
assign RXC_META_ADDR = wRxcMetadata[`TLP_CPLADDR_R];
assign RXC_META_COMPLETER_ID = wRxcMetadata[`TLP_CPLCPLID_R];
assign RXC_META_BYTES_REMAINING = wRxcMetadata[`TLP_CPLBYTECNT_R];
assign RXC_META_TAG = wRxcMetadata[`TLP_CPLTAG_R];
assign RXC_META_EP = wRxcMetadata[`TLP_EP_R];
assign RXC_META_FDWBE = 0;// TODO: Remove (use addr)
assign RXC_META_LDWBE = 0;// TODO: Remove (use addr)
assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_METADW2_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I] & rValid; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_METADW2_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
end else begin // 256
assign wStartFlags[3] = 0;
assign wStartFlags[2] = 0;
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (RX_SR_EOP[C_RX_INPUT_STAGES+1]) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(rRST) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
register
#(// Parameters
.C_WIDTH (32))
metadata_DW0_register
(// Outputs
.RD_DATA (wMetadata[31:0]),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32))
meta_DW1_register
(// Outputs
.RD_DATA (wMetadata[63:32]),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32))
meta_DW2_register
(// Outputs
.RD_DATA (wMetadata[95:64]),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[C_RX_METADW2_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW2_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_TYPE_W))
metadata_type_register
(// Outputs
.RD_DATA (wType),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[(`TLP_TYPE_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_TYPE_W]),
.WR_EN (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_LEN_W))
metadata_length_register
(// Outputs
.RD_DATA (wLength),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[((`TLP_LEN_I%C_PCI_DATA_WIDTH) + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
.WR_EN (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_CPLADDR_W))
metadata_address_register
(// Outputs
.RD_DATA (wAddr),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[((`TLP_CPLADDR_I%C_PCI_DATA_WIDTH) + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_CPLADDR_W]),
.WR_EN (wRxSrSop[`TLP_CPLADDR_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (1'b0)
/*AUTOINSTPARAM*/)
start_flag_register
(// Outputs
.RD_DATA (wStartFlag),
// Inputs
.RST_IN (0),
.WR_DATA (_wStartFlag),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset)
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXC_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
end else begin
register
#(// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxcDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXC_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxcDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
end
endgenerate
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`TLP_CPLHDR_W + 2*(clog2s(C_PCI_DATA_WIDTH/32) + 1)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxcMetadata,wRxcDataStartFlag,wRxcDataStartOffset,wRxcDataEndFlag,wRxcDataEndOffset}),
.RD_DATA_VALID (wRxcDataValid),
// Inputs
.WR_DATA ({wMetadata, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
.WR_DATA_VALID (rValid & RX_SR_VALID[C_TOTAL_STAGES - C_RX_OUTPUT_STAGES]),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (RX_TLP_START_FLAG & RX_TLP_VALID &
(RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_CPL)),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__TAP_FUNCTIONAL_V
/**
* tap: Tap cell with no tap connections (no contacts on metal1).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tap ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAP_FUNCTIONAL_V |
//////////////////////////////////////////////////////////////////////////////////
// NPM_Toggle_DO_tADL_DDR100 for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPM_Toggle_DO_tADL_DDR100
// Module Name: NPM_Toggle_DO_tADL_DDR100
// File Name: NPM_Toggle_DO_tADL_DDR100.v
//
// Version: v1.0.0
//
// Description: NFC PM data out FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPM_Toggle_DO_tADL_DDR100
#
(
// support "serial execution"
// Data Packet Width (DQ): 8 bit
// iOption: set SDR/DDR mode
// 0-SDR(WE#), 1-DDR(DQS)
// NumOfData: 0 means 1
// -> unit: word (32 bit = 4 B)
// _tADL.v
// (original design: tCDQSS = 110 ns, tWPRE = 30 ns)
//
// tCDQSS = 250 ns => 25 cycles
// tWPRE = 50 ns => 5 cycles
// future -> add data buffer?
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
oReady ,
oLastStep ,
iStart ,
iOption ,
iTargetWay ,
iWriteData ,
iWriteLast ,
iWriteValid ,
oWriteReady ,
oPO_DQStrobe ,
oPO_DQ ,
oPO_ChipEnable ,
oPO_WriteEnable ,
oPO_AddressLatchEnable ,
oPO_CommandLatchEnable ,
oDQSOutEnable ,
oDQOutEnable
);
input iSystemClock ;
input iReset ;
output oReady ;
output oLastStep ;
input iStart ;
input iOption ;
input [NumberOfWays - 1:0] iTargetWay ;
input [31:0] iWriteData ;
input iWriteLast ;
input iWriteValid ;
output oWriteReady ;
output [7:0] oPO_DQStrobe ;
output [31:0] oPO_DQ ;
output [2*NumberOfWays - 1:0] oPO_ChipEnable ;
output [3:0] oPO_WriteEnable ;
output [3:0] oPO_AddressLatchEnable ;
output [3:0] oPO_CommandLatchEnable ;
output oDQSOutEnable ;
output oDQOutEnable ;
// FSM Parameters/Wires/Regs
localparam DTO_FSM_BIT = 9; // DaTa Out
localparam DTO_RESET = 9'b000_000_001;
localparam DTO_READY = 9'b000_000_010;
localparam DTO_DQS01 = 9'b000_000_100; // info. capture, wait state for tCDQSS
localparam DTO_DQS02 = 9'b000_001_000; // wait state for tCDQSS
localparam DTO_WPRAM = 9'b000_010_000; // wait state for tWRPE
localparam DTO_DQOUT = 9'b000_100_000; // DQ out: loop
localparam DTO_PAUSE = 9'b001_000_000; // pause DQ out
localparam DTO_DQLST = 9'b010_000_000; // DQ out: last
localparam DTO_WPSAM = 9'b100_000_000; // wait state for tWPST
localparam DTO_WPSA2 = 9'b110_000_000; // temp. state: will be removed
reg [DTO_FSM_BIT-1:0] rDTO_cur_state ;
reg [DTO_FSM_BIT-1:0] rDTO_nxt_state ;
// Internal Wires/Regs
reg rReady ;
reg rLastStep ;
reg rOption ;
reg [4:0] rDTOSubCounter ;
wire [2*NumberOfWays - 1:0] wPO_ChipEnable ;
wire wtCDQSSDone ;
wire wtWPREDone ;
wire wLoopDone ;
wire wtWPSTDone ;
reg [7:0] rPO_DQStrobe ;
reg [31:0] rPO_DQ ;
reg [2*NumberOfWays - 1:0] rPO_ChipEnable ;
reg [3:0] rPO_WriteEnable ;
reg [3:0] rPO_AddressLatchEnable ;
reg [3:0] rPO_CommandLatchEnable ;
reg rDQSOutEnable ;
reg rDQOutEnable ;
reg rStageFlag ;
// Control Signals
// Target Way Decoder
assign wPO_ChipEnable = { iTargetWay[NumberOfWays - 1:0], iTargetWay[NumberOfWays - 1:0] };
// Flow Control
assign wtCDQSSDone = (rDTOSubCounter[4:0] == 5'd25); // 25 => 250 ns
assign wtWPREDone = (rDTOSubCounter[4:0] == 5'd30); // 30 - 25 = 5 => 50 ns
assign wLoopDone = iWriteLast & iWriteValid;
assign wtWPSTDone = (rDTOSubCounter[4:0] == 5'd3); // 3 - 0 = 3 => 30 ns, tWPST = 6.5 ns
// FSM: DaTa Out (DTO)
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rDTO_cur_state <= DTO_RESET;
end else begin
rDTO_cur_state <= rDTO_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (rDTO_cur_state)
DTO_RESET: begin
rDTO_nxt_state <= DTO_READY;
end
DTO_READY: begin
rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY;
end
DTO_DQS01: begin
rDTO_nxt_state <= DTO_DQS02;
end
DTO_DQS02: begin
rDTO_nxt_state <= (wtCDQSSDone)? DTO_WPRAM:DTO_DQS02;
end
DTO_WPRAM: begin
rDTO_nxt_state <= (wtWPREDone)? ((iWriteValid)? DTO_DQOUT:DTO_PAUSE):DTO_WPRAM;
end
DTO_DQOUT: begin
rDTO_nxt_state <= (rStageFlag)? (DTO_DQOUT):((wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE));
end
DTO_PAUSE: begin
rDTO_nxt_state <= (wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE);
end
DTO_DQLST: begin
rDTO_nxt_state <= (rStageFlag)? DTO_DQLST:DTO_WPSAM;
end
DTO_WPSAM: begin
rDTO_nxt_state <= (wtWPSTDone)? DTO_WPSA2:DTO_WPSAM;
end
DTO_WPSA2: begin
rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY;
end
default:
rDTO_nxt_state <= DTO_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rReady <= 0;
rLastStep <= 0;
rOption <= 0;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQSOutEnable <= 0;
rDQOutEnable <= 0;
rStageFlag <= 0;
end else begin
case (rDTO_nxt_state)
DTO_RESET: begin
rReady <= 0;
rLastStep <= 0;
rOption <= 0;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQSOutEnable <= 0;
rDQOutEnable <= 0;
rStageFlag <= 0;
end
DTO_READY: begin
rReady <= 1;
rLastStep <= 0;
rOption <= 0;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQSOutEnable <= 0;
rDQOutEnable <= 0;
rStageFlag <= 0;
end
DTO_DQS01: begin
rReady <= 0;
rLastStep <= 0;
rOption <= iOption;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= wPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b1111;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (iOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 0;
end
DTO_DQS02: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b1111;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 0;
end
DTO_WPRAM: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1;
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 1'b0;
end
DTO_DQOUT: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0];
rPO_DQStrobe[7:0] <= 8'b0011_0011;
rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0];
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1001;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0;
end
DTO_PAUSE: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0];
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= { 4{rPO_DQ[31:24]} };
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 1'b0;
end
DTO_DQLST: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b0011_0011; // 8'b0110_0110;
rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0];
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b0001;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0;
end
DTO_WPSAM: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1;
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b0;
rStageFlag <= 1'b0;
end
DTO_WPSA2: begin
rReady <= 1;
rLastStep <= 1;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0];
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b0;
rStageFlag <= 1'b0;
end
endcase
end
end
// Output
assign oReady = rReady ;
assign oLastStep = rLastStep ;
assign oWriteReady = wtWPREDone & (~rStageFlag);
assign oPO_DQStrobe = rPO_DQStrobe ;
assign oPO_DQ = rPO_DQ ;
assign oPO_ChipEnable = rPO_ChipEnable ;
assign oPO_WriteEnable = rPO_WriteEnable ;
assign oPO_AddressLatchEnable = rPO_AddressLatchEnable;
assign oPO_CommandLatchEnable = rPO_CommandLatchEnable;
assign oDQSOutEnable = rDQSOutEnable ;
assign oDQOutEnable = rDQOutEnable ;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:41:33 10/30/2014
// Design Name:
// Module Name: UART_loop
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_loop(
input UartRx,
output UartTx,
input clk100,
output [7:0]LED
);
wire [7:0]Rx_D;
reg [7:0]Tx_D;
reg WR = 1'b0;
reg RD = 1'b0;
reg RST = 1'b0;
wire RXNE;
wire TXE;
// Instantiate the module
UART_Rx # (
.CLOCK(100_000_000),
.BAUD_RATE(115200)
)rx_module (
.CLK(clk100),
.D(Rx_D),
.RD(RD),
.RST(RST),
.RX(UartRx),
.RXNE(RXNE)
);
// Instantiate the module
UART_Tx # (
.CLOCK(100_000_000),
.BAUD_RATE(115200)
) tx_module (
.CLK(clk100),
.D(Tx_D),
.WR(WR),
.RST(RST),
.TX(UartTx),
.TXE(TXE)
);
assign LED = Rx_D;
reg tog = 1'b0;
reg prevRXNE = 1'b0;
always @(posedge clk100) begin
if (prevRXNE == 1'b0 && RXNE == 1'b1) begin
RD <= 1'b1;
Tx_D <= Rx_D;
WR <= 1'b1;
tog <= !tog;
end else begin
RD <= 1'b0;
WR <= 1'b0;
end
prevRXNE <= RXNE;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
Test #(16,2) test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'hf9b3a5000165ed38
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [31:0] out;
parameter N = 0;
parameter PASSDOWN = 1;
add #(PASSDOWN) add (.in (in[(2*N)-1:(0*N)]),
.out (out));
endmodule
module add (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
parameter PASSDOWN = 9999;
input [31:0] in;
output [31:0] out;
wire out = in + PASSDOWN;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
/*
Filename: scsdp.v
Version: 1.0
Verilog Standard: Verilog-2001
Description: A simple, single clock, simple dual port (SCSDP) ram
Notes: Any modifications to this file should meet the conditions set
forth in the "Trellis Style Guide"
Author: Dustin Richmond (@darichmond)
Co-Authors:
*/
`timescale 1ns/1ns
`include "functions.vh"
module scsdpram
#(
parameter C_WIDTH = 32,
parameter C_DEPTH = 1024
)
(
input CLK,
input RD1_EN,
input [clog2s(C_DEPTH)-1:0] RD1_ADDR,
output [C_WIDTH-1:0] RD1_DATA,
input WR1_EN,
input [clog2s(C_DEPTH)-1:0] WR1_ADDR,
input [C_WIDTH-1:0] WR1_DATA
);
reg [C_WIDTH-1:0] rMemory [C_DEPTH-1:0];
reg [C_WIDTH-1:0] rDataOut;
assign RD1_DATA = rDataOut;
always @(posedge CLK) begin
if (WR1_EN) begin
rMemory[WR1_ADDR] <= #1 WR1_DATA;
end
if(RD1_EN) begin
rDataOut <= #1 rMemory[RD1_ADDR];
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:51:45 05/17/2016
// Design Name:
// Module Name: ROM_16x32
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ROM_16x32(
input wire clk,
input wire [11:0] addr,
output reg [15:0] data
);
reg [11:0] addr_reg;
always @(posedge clk)
addr_reg <= addr;
always @*
case (addr_reg)
//code x00 y x01
12'h000: data = 16'b0000000000000000; //
12'h001: data = 16'b0000000000000000; //
12'h002: data = 16'b0000000000000000; //
12'h003: data = 16'b0000000000000000; //
12'h004: data = 16'b0000000000000000; //
12'h005: data = 16'b0000000000000000; //
12'h006: data = 16'b0000000000000000; //
12'h007: data = 16'b0000000000000000; //
12'h008: data = 16'b0000000000000000; //
12'h009: data = 16'b0000000000000000; //
12'h00a: data = 16'b0000000000000000; //
12'h00b: data = 16'b0000000000000000; //
12'h00c: data = 16'b0000000000000000; //
12'h00d: data = 16'b0000000000000000; //
12'h00e: data = 16'b0000000000000000; //
12'h00f: data = 16'b0000000000000000; //
12'h010: data = 16'b0000000000000000; //
12'h011: data = 16'b0000000000000000; //
12'h012: data = 16'b0000000000000000; //
12'h013: data = 16'b0000000000000000; //
12'h014: data = 16'b0000000000000000; //
12'h015: data = 16'b0000000000000000; //
12'h016: data = 16'b0000000000000000; //
12'h017: data = 16'b0000000000000000; //
12'h018: data = 16'b0000000000000000; //
12'h019: data = 16'b0000000000000000; //
12'h01a: data = 16'b0000000000000000; //
12'h01b: data = 16'b0000000000000000; //
12'h01c: data = 16'b0000000000000000; //
12'h01d: data = 16'b0000000000000000; //
12'h01e: data = 16'b0000000000000000; //
12'h01f: data = 16'b0000000000000000; //
//code x5E0 y x5F0 "/"
12'h5e0: data = 16'b0000000000000000; //
12'h5e1: data = 16'b0000000000000000; //
12'h5e2: data = 16'b0000000000000000; //
12'h5e3: data = 16'b0000000000000000; //
12'h5e4: data = 16'b0000000000000000; //
12'h5e5: data = 16'b0000000000000000; //
12'h5e6: data = 16'b0000000000000000; //
12'h5e7: data = 16'b0000000000000000; //
12'h5e8: data = 16'b0000000000000110; // ++
12'h5e9: data = 16'b0000000000000111; // +++
12'h5ea: data = 16'b0000000000001110; // +++
12'h5eb: data = 16'b0000000000011100; // +++
12'h5ec: data = 16'b0000000000111000; // +++
12'h5ed: data = 16'b0000000001110000; // +++
12'h5ee: data = 16'b0000000011100000; // +++
12'h5ef: data = 16'b0000000111000000; // +++
12'h5f0: data = 16'b0000001110000000; // +++
12'h5f1: data = 16'b0000011100000000; // +++
12'h5f2: data = 16'b0000111000000000; // +++
12'h5f3: data = 16'b0001110000000000; // +++
12'h5f4: data = 16'b0011100000000000; // +++
12'h5f5: data = 16'b0111000000000000; // +++
12'h5f6: data = 16'b1110000000000000; //+++
12'h5f7: data = 16'b1100000000000000; //++
12'h5f8: data = 16'b0000000000000000; //
12'h5f9: data = 16'b0000000000000000; //
12'h5fa: data = 16'b0000000000000000; //
12'h5fb: data = 16'b0000000000000000; //
12'h5fc: data = 16'b0000000000000000; //
12'h5fd: data = 16'b0000000000000000; //
12'h5fe: data = 16'b0000000000000000; //
12'h5ff: data = 16'b0000000000000000; //
//code x60 y x61 NUMERO 0
12'h600: data = 16'b0000000000000000; //
12'h601: data = 16'b0000000000000000; //
12'h602: data = 16'b0000000000000000; //
12'h603: data = 16'b0000000000000000; //
12'h604: data = 16'b0000000000000000; //
12'h605: data = 16'b0001111111100000; // ********
12'h606: data = 16'b0011111111110000; // **********
12'h607: data = 16'b0111100001111000; // **** ****
12'h608: data = 16'b1111000000111100; // **** ****
12'h609: data = 16'b1111000000111100; // **** ****
12'h60a: data = 16'b1111000000111100; // **** ****
12'h60b: data = 16'b1111000001111100; // **** *****
12'h60c: data = 16'b1111000011111100; // **** ******
12'h60d: data = 16'b1111000111111100; // **** *******
12'h60e: data = 16'b1111001111111100; // **** ********
12'h60f: data = 16'b1111011111111100; // **** *********
12'h610: data = 16'b1111111110111100; // ********* ****
12'h611: data = 16'b1111111100111100; // ******** ****
12'h612: data = 16'b1111111000111100; // ******* ****
12'h613: data = 16'b1111110000111100; // ****** ****
12'h614: data = 16'b1111100000111100; // ***** ****
12'h615: data = 16'b1111000000111100; // **** ****
12'h616: data = 16'b1111000000111100; // **** ****
12'h617: data = 16'b1111000000111100; // **** ****
12'h618: data = 16'b0111100001111000; // **** ****
12'h619: data = 16'b0011111111110000; // **********
12'h61a: data = 16'b0001111111100000; // ********
12'h61b: data = 16'b0000000000000000; //
12'h61c: data = 16'b0000000000000000; //
12'h61d: data = 16'b0000000000000000; //
12'h61e: data = 16'b0000000000000000; //
12'h61f: data = 16'b0000000000000000; //
//code x62 y x63 NUMERO 1
12'h620: data = 16'b0000000000000000; //
12'h621: data = 16'b0000000000000000; //
12'h622: data = 16'b0000000000000000; //
12'h623: data = 16'b0000000000000000; //
12'h624: data = 16'b0000000000000000; //
12'h625: data = 16'b0000000001000000; // *
12'h626: data = 16'b0000000011000000; // **
12'h627: data = 16'b0000000111000000; // ***
12'h628: data = 16'b0000001111000000; // ****
12'h629: data = 16'b0000011111000000; // *****
12'h62a: data = 16'b0000111111000000; // ******
12'h62b: data = 16'b0001111111000000; // *******
12'h62c: data = 16'b0011111111000000; // ********
12'h62d: data = 16'b0000001111000000; // ****
12'h62e: data = 16'b0000001111000000; // ****
12'h62f: data = 16'b0000001111000000; // ****
12'h630: data = 16'b0000001111000000; // ****
12'h631: data = 16'b0000001111000000; // ****
12'h632: data = 16'b0000001111000000; // ****
12'h633: data = 16'b0000001111000000; // ****
12'h634: data = 16'b0000001111000000; // ****
12'h635: data = 16'b0000001111000000; // ****
12'h636: data = 16'b0000001111000000; // ****
12'h637: data = 16'b0000001111000000; // ****
12'h638: data = 16'b0000001111000000; // ****
12'h639: data = 16'b0011111111111100; // ************
12'h63a: data = 16'b0011111111111100; // ************
12'h63b: data = 16'b0000000000000000; //
12'h63c: data = 16'b0000000000000000; //
12'h63d: data = 16'b0000000000000000; //
12'h63e: data = 16'b0000000000000000; //
12'h63f: data = 16'b0000000000000000; //
//code x64 y x65 NUMERO 2
12'h640: data = 16'b0000000000000000; //
12'h641: data = 16'b0000000000000000; //
12'h642: data = 16'b0000000000000000; //
12'h643: data = 16'b0000000000000000; //
12'h644: data = 16'b0000000000000000; //
12'h645: data = 16'b0000111111110000; // ********
12'h646: data = 16'b0001111111111000; // **********
12'h647: data = 16'b0011110001111100; // **** *****
12'h648: data = 16'b0111100000111100; // **** ****
12'h649: data = 16'b1111000000111100; // **** ****
12'h64a: data = 16'b1111000000111100; // **** ****
12'h64b: data = 16'b0000000000111100; // ****
12'h64c: data = 16'b0000000000111100; // ****
12'h64d: data = 16'b0000000001111000; // ****
12'h64e: data = 16'b0000000011110000; // ****
12'h64f: data = 16'b0000000111100000; // ****
12'h650: data = 16'b0000001111000000; // ****
12'h651: data = 16'b0000011110000000; // ****
12'h652: data = 16'b0000111100000000; // ****
12'h653: data = 16'b0001111000000000; // ****
12'h654: data = 16'b0011110000000000; // ****
12'h655: data = 16'b0111100000000000; // ****
12'h656: data = 16'b1111000000000000; // ****
12'h657: data = 16'b1111000000111100; // **** ****
12'h658: data = 16'b1111000000111100; // **** ****
12'h659: data = 16'b1111111111111100; // **************
12'h65a: data = 16'b1111111111111100; // **************
12'h65b: data = 16'b0000000000000000; //
12'h65c: data = 16'b0000000000000000; //
12'h65d: data = 16'b0000000000000000; //
12'h65e: data = 16'b0000000000000000; //
12'h65f: data = 16'b0000000000000000; //
//code x66 y x67 NUMERO 3
12'h660: data = 16'b0000000000000000; //
12'h661: data = 16'b0000000000000000; //
12'h662: data = 16'b0000000000000000; //
12'h663: data = 16'b0000000000000000; //
12'h664: data = 16'b0000000000000000; //
12'h665: data = 16'b0001111111100000; // ********
12'h666: data = 16'b0011111111110000; // **********
12'h667: data = 16'b0111100001111000; // **** ****
12'h668: data = 16'b1111000000111100; // **** ****
12'h669: data = 16'b0000000000111100; // ****
12'h66a: data = 16'b0000000000111100; // ****
12'h66b: data = 16'b0000000000111100; // ****
12'h66c: data = 16'b0000000000111100; // ****
12'h66d: data = 16'b0000000001111000; // ****
12'h66e: data = 16'b0000011111110000; // *******
12'h66f: data = 16'b0000011111100000; // ******
12'h670: data = 16'b0000011111110000; // *******
12'h671: data = 16'b0000000001111000; // ****
12'h672: data = 16'b0000000000111100; // ****
12'h673: data = 16'b0000000000111100; // ****
12'h674: data = 16'b0000000000111100; // ****
12'h675: data = 16'b0000000000111100; // ****
12'h676: data = 16'b0000000000111100; // ****
12'h677: data = 16'b1111000000111100; // **** ****
12'h678: data = 16'b0111100001111000; // **** ****
12'h679: data = 16'b0011111111110000; // **********
12'h67a: data = 16'b0001111111100000; // ********
12'h67b: data = 16'b0000000000000000; //
12'h67c: data = 16'b0000000000000000; //
12'h67d: data = 16'b0000000000000000; //
12'h67e: data = 16'b0000000000000000; //
12'h67f: data = 16'b0000000000000000; //
//code x68 y x69 NUMERO 4
12'h680: data = 16'b0000000000000000; //
12'h681: data = 16'b0000000000000000; //
12'h682: data = 16'b0000000000000000; //
12'h683: data = 16'b0000000000000000; //
12'h684: data = 16'b0000000000000000; //
12'h685: data = 16'b0000000000010000; // *
12'h686: data = 16'b0000000000110000; // **
12'h687: data = 16'b0000000001110000; // ***
12'h688: data = 16'b0000000011110000; // ****
12'h689: data = 16'b0000000111110000; // *****
12'h68a: data = 16'b0000001111110000; // ******
12'h68b: data = 16'b0000011111110000; // *******
12'h68c: data = 16'b0000111011110000; // *** ****
12'h68d: data = 16'b0001110011110000; // *** ****
12'h68e: data = 16'b0011100011110000; // *** ****
12'h68f: data = 16'b0111000011110000; // *** ****
12'h690: data = 16'b1111111111111100; // **************
12'h691: data = 16'b1111111111111100; // **************
12'h692: data = 16'b0000000011110000; // ****
12'h693: data = 16'b0000000011110000; // ****
12'h694: data = 16'b0000000011110000; // ****
12'h695: data = 16'b0000000011110000; // ****
12'h696: data = 16'b0000000011110000; // ****
12'h697: data = 16'b0000000011110000; // ****
12'h698: data = 16'b0000000011110000; // ****
12'h699: data = 16'b0000000011110000; // ****
12'h69a: data = 16'b0000000111111000; // ******
12'h69b: data = 16'b0000000000000000; //
12'h69c: data = 16'b0000000000000000; //
12'h69d: data = 16'b0000000000000000; //
12'h69e: data = 16'b0000000000000000; //
12'h69f: data = 16'b0000000000000000; //
//code x6a y x6b NUMERO 5
12'h6a0: data = 16'b0000000000000000; //
12'h6a1: data = 16'b0000000000000000; //
12'h6a2: data = 16'b0000000000000000; //
12'h6a3: data = 16'b0000000000000000; //
12'h6a4: data = 16'b0000000000000000; //
12'h6a5: data = 16'b1111111111111100; // **************
12'h6a6: data = 16'b1111111111111100; // **************
12'h6a7: data = 16'b1111000000000000; // ****
12'h6a8: data = 16'b1111000000000000; // ****
12'h6a9: data = 16'b1111000000000000; // ****
12'h6aa: data = 16'b1111000000000000; // ****
12'h6ab: data = 16'b1111000000000000; // ****
12'h6ac: data = 16'b1111000000000000; // ****
12'h6ad: data = 16'b1111111111100000; // **********
12'h6ae: data = 16'b1111111111110000; // ************
12'h6af: data = 16'b0000000001111000; // ****
12'h6b0: data = 16'b0000000000111100; // ****
12'h6b1: data = 16'b0000000000111100; // ****
12'h6b2: data = 16'b0000000000111100; // ****
12'h6b3: data = 16'b0000000000111100; // ****
12'h6b4: data = 16'b0000000000111100; // ****
12'h6b5: data = 16'b0000000000111100; // ****
12'h6b6: data = 16'b0000000000111100; // ****
12'h6b7: data = 16'b1111000000111100; // **** ****
12'h6b8: data = 16'b0111100001111000; // **** ****
12'h6b9: data = 16'b0011111111110000; // **********
12'h6ba: data = 16'b0001111111100000; // ********
12'h6bb: data = 16'b0000000000000000; //
12'h6bc: data = 16'b0000000000000000; //
12'h6bd: data = 16'b0000000000000000; //
12'h6be: data = 16'b0000000000000000; //
12'h6bf: data = 16'b0000000000000000; //
//code x6c y x6d NUMERO 6
12'h6c0: data = 16'b0000000000000000; //
12'h6c1: data = 16'b0000000000000000; //
12'h6c2: data = 16'b0000000000000000; //
12'h6c3: data = 16'b0000000000000000; //
12'h6c4: data = 16'b0000000000000000; //
12'h6c5: data = 16'b0000011110000000; // *****
12'h6c6: data = 16'b0000111100000000; // ****
12'h6c7: data = 16'b0001111000000000; // ****
12'h6c8: data = 16'b0011110000000000; // ****
12'h6c9: data = 16'b0111100000000000; // ****
12'h6ca: data = 16'b1111000000000000; // ****
12'h6cb: data = 16'b1111000000000000; // ****
12'h6cc: data = 16'b1111000000000000; // ****
12'h6cd: data = 16'b1111000000000000; // ****
12'h6ce: data = 16'b1111111111110000; // ************
12'h6cf: data = 16'b1111111111111000; // *************
12'h6d0: data = 16'b1111100001111100; // ***** *****
12'h6d1: data = 16'b1111000000111100; // **** ****
12'h6d2: data = 16'b1111000000111100; // **** ****
12'h6d3: data = 16'b1111000000111100; // **** ****
12'h6d4: data = 16'b1111000000111100; // **** ****
12'h6d5: data = 16'b1111000000111100; // **** ****
12'h6d6: data = 16'b1111000000111100; // **** ****
12'h6d7: data = 16'b1111000000111100; // **** ****
12'h6d8: data = 16'b0111100001111000; // **** ****
12'h6d9: data = 16'b0011111111110000; // **********
12'h6da: data = 16'b0001111111100000; // ********
12'h6db: data = 16'b0000000000000000; //
12'h6dc: data = 16'b0000000000000000; //
12'h6dd: data = 16'b0000000000000000; //
12'h6de: data = 16'b0000000000000000; //
12'h6df: data = 16'b0000000000000000; //
//code x6e y x6f NUMERO 7
12'h6e0: data = 16'b0000000000000000; //
12'h6e1: data = 16'b0000000000000000; //
12'h6e2: data = 16'b0000000000000000; //
12'h6e3: data = 16'b0000000000000000; //
12'h6e4: data = 16'b0000000000000000; //
12'h6e5: data = 16'b1111111111111100; // **************
12'h6e6: data = 16'b1111111111111100; // **************
12'h6e7: data = 16'b1111000000111100; // **** ****
12'h6e8: data = 16'b0000000000111100; // ****
12'h6e9: data = 16'b0000000000111100; // ****
12'h6ea: data = 16'b0000000000111100; // ****
12'h6eb: data = 16'b0000000000111100; // ****
12'h6ec: data = 16'b0000000000111100; // ****
12'h6ed: data = 16'b0000000001111000; // ****
12'h6ee: data = 16'b0000000011110000; // ****
12'h6ef: data = 16'b0000000111100000; // ****
12'h6f0: data = 16'b0000001111000000; // ****
12'h6f1: data = 16'b0000011110000000; // ****
12'h6f2: data = 16'b0000011110000000; // ****
12'h6f3: data = 16'b0000011110000000; // ****
12'h6f4: data = 16'b0000011110000000; // ****
12'h6f5: data = 16'b0000011110000000; // ****
12'h6f6: data = 16'b0000011110000000; // ****
12'h6f7: data = 16'b0000011110000000; // ****
12'h6f8: data = 16'b0000011110000000; // ****
12'h6f9: data = 16'b0000011110000000; // ****
12'h6fa: data = 16'b0000011110000000; // ****
12'h6fb: data = 16'b0000000000000000; //
12'h6fc: data = 16'b0000000000000000; //
12'h6fd: data = 16'b0000000000000000; //
12'h6fe: data = 16'b0000000000000000; //
12'h6ff: data = 16'b0000000000000000; //
//code x70 y x71 NUMERO 8
12'h700: data = 16'b0000000000000000; //
12'h701: data = 16'b0000000000000000; //
12'h702: data = 16'b0000000000000000; //
12'h703: data = 16'b0000000000000000; //
12'h704: data = 16'b0000000000000000; //
12'h705: data = 16'b0001111111100000; // ********
12'h706: data = 16'b0011111111110000; // **********
12'h707: data = 16'b0111100001111000; // **** ****
12'h708: data = 16'b1111000000111100; // **** ****
12'h709: data = 16'b1111000000111100; // **** ****
12'h70a: data = 16'b1111000000111100; // **** ****
12'h70b: data = 16'b1111000000111100; // **** ****
12'h70c: data = 16'b1111000000111100; // **** ****
12'h70d: data = 16'b1111000000111100; // **** ****
12'h70e: data = 16'b0111100001111000; // **** ****
12'h70f: data = 16'b0011111111110000; // **********
12'h710: data = 16'b0011111111110000; // **********
12'h711: data = 16'b0111100000111100; // **** ****
12'h712: data = 16'b1111000000111100; // **** ****
12'h713: data = 16'b1111000000111100; // **** ****
12'h714: data = 16'b1111000000111100; // **** ****
12'h715: data = 16'b1111000000111100; // **** ****
12'h716: data = 16'b1111000000111100; // **** ****
12'h717: data = 16'b1111000000111100; // **** ****
12'h718: data = 16'b0111100001111000; // **** ****
12'h719: data = 16'b0011111111110000; // **********
12'h71a: data = 16'b0001111111100000; // ********
12'h71b: data = 16'b0000000000000000; //
12'h71c: data = 16'b0000000000000000; //
12'h71d: data = 16'b0000000000000000; //
12'h71e: data = 16'b0000000000000000; //
12'h71f: data = 16'b0000000000000000; //
//code x72 y x73 NUMERO 9
12'h720: data = 16'b0000000000000000; //
12'h721: data = 16'b0000000000000000; //
12'h722: data = 16'b0000000000000000; //
12'h723: data = 16'b0000000000000000; //
12'h724: data = 16'b0000000000000000; //
12'h725: data = 16'b0001111111100000; // ********
12'h726: data = 16'b0011111111110000; // **********
12'h727: data = 16'b0111100001111000; // **** ****
12'h728: data = 16'b1111000000111100; // **** ****
12'h729: data = 16'b1111000000111100; // **** ****
12'h72a: data = 16'b1111000000111100; // **** ****
12'h72b: data = 16'b1111000000111100; // **** ****
12'h72c: data = 16'b1111000000111100; // **** ****
12'h72d: data = 16'b1111000000111100; // **** ****
12'h72e: data = 16'b0111100000111100; // **** ****
12'h72f: data = 16'b0011111111111100; // ************
12'h730: data = 16'b0001111111111100; // ***********
12'h731: data = 16'b0000000000111100; // ****
12'h732: data = 16'b0000000000111100; // ****
12'h733: data = 16'b0000000000111100; // ****
12'h734: data = 16'b0000000000111100; // ****
12'h735: data = 16'b0000000000111100; // ****
12'h736: data = 16'b0000000000111100; // ****
12'h737: data = 16'b0000000000111100; // ****
12'h738: data = 16'b0111100001111000; // **** ****
12'h739: data = 16'b0011111111110000; // **********
12'h73a: data = 16'b0001111111100000; // ********
12'h73b: data = 16'b0000000000000000; //
12'h73c: data = 16'b0000000000000000; //
12'h73d: data = 16'b0000000000000000; //
12'h73e: data = 16'b0000000000000000; //
12'h73f: data = 16'b0000000000000000; //
//code x74 y x75
12'h740: data = 16'b0000000000000000; //
12'h741: data = 16'b0000000000000000; //
12'h742: data = 16'b0000000000000000; //
12'h743: data = 16'b0000000000000000; //
12'h744: data = 16'b0000000000000000; //
12'h745: data = 16'b0000000000000000; //
12'h746: data = 16'b0000000000000000; //
12'h747: data = 16'b0000000000000000; //
12'h748: data = 16'b0000001110000000; // ***
12'h749: data = 16'b0000011111000000; // *****
12'h74a: data = 16'b0000011111000000; // *****
12'h74b: data = 16'b0000011111000000; // *****
12'h74c: data = 16'b0000001110000000; // ***
12'h74d: data = 16'b0000000000000000; //
12'h74e: data = 16'b0000000000000000; //
12'h74f: data = 16'b0000000000000000; //
12'h750: data = 16'b0000000000000000; //
12'h751: data = 16'b0000000000000000; //
12'h752: data = 16'b0000000000000000; //
12'h753: data = 16'b0000001110000000; // ***
12'h754: data = 16'b0000011111000000; // *****
12'h755: data = 16'b0000011111000000; // *****
12'h756: data = 16'b0000011111000000; // *****
12'h757: data = 16'b0000001110000000; // ***
12'h758: data = 16'b0000000000000000; //
12'h759: data = 16'b0000000000000000; //
12'h75a: data = 16'b0000000000000000; //
12'h75b: data = 16'b0000000000000000; //
12'h75c: data = 16'b0000000000000000; //
12'h75d: data = 16'b0000000000000000; //
12'h75e: data = 16'b0000000000000000; //
12'h75f: data = 16'b0000000000000000; //
//code xc2 y xc3 a
12'hc20: data = 16'b0000000000000000; //
12'hc21: data = 16'b0000000000000000; //
12'hc22: data = 16'b0000000000000000; //
12'hc23: data = 16'b0000000000000000; //
12'hc24: data = 16'b0000000000000000; //
12'hc25: data = 16'b0000000000000000; //
12'hc26: data = 16'b0000000000000000; //
12'hc27: data = 16'b0000000000000000; //
12'hc28: data = 16'b0000000000000000; //
12'hc29: data = 16'b0000000000000000; //
12'hc2a: data = 16'b0111111111000000; // *********
12'hc2b: data = 16'b0111111111100000; // **********
12'hc2c: data = 16'b0000000011110000; // ****
12'hc2d: data = 16'b0000000011110000; // ****
12'hc2e: data = 16'b0011111111110000; // **********
12'hc2f: data = 16'b0111111111110000; // ***********
12'hc30: data = 16'b1111100111110000; // ***** *****
12'hc31: data = 16'b1111000011110000; // **** ****
12'hc32: data = 16'b1111000011110000; // **** ****
12'hc33: data = 16'b1111000011110000; // **** ****
12'hc34: data = 16'b1111000011110000; // **** ****
12'hc35: data = 16'b1111100111110000; // ***** *****
12'hc36: data = 16'b0111111110111000; // ******** ***
12'hc37: data = 16'b0011111100011100; // ****** ***
12'hc38: data = 16'b0000000000000000; //
12'hc39: data = 16'b0000000000000000; //
12'hc3a: data = 16'b0000000000000000; //
12'hc3b: data = 16'b0000000000000000; //
12'hc3c: data = 16'b0000000000000000; //
12'hc3d: data = 16'b0000000000000000; //
12'hc3e: data = 16'b0000000000000000; //
12'hc3f: data = 16'b0000000000000000; //
//code xc6 y xc7 m
12'hc60: data = 16'b0000000000000000; //
12'hc61: data = 16'b0000000000000000; //
12'hc62: data = 16'b0000000000000000; //
12'hc63: data = 16'b0000000000000000; //
12'hc64: data = 16'b0000000000000000; //
12'hc65: data = 16'b0000000000000000; //
12'hc66: data = 16'b0000000000000000; //
12'hc67: data = 16'b0000000000000000; //
12'hc68: data = 16'b0000000000000000; //
12'hc69: data = 16'b0000000000000000; //
12'hc6a: data = 16'b0000000000000000; //
12'hc6b: data = 16'b0011110000111100; // **** ****
12'hc6c: data = 16'b0111111001111110; // ****** ******
12'hc6d: data = 16'b0111111111111111; // ***************
12'hc6e: data = 16'b0111101111101111; // **** ***** ****
12'hc6f: data = 16'b0111000111000111; // *** *** ***
12'hc70: data = 16'b0111000111000111; // *** *** ***
12'hc71: data = 16'b0111000111000111; // *** *** ***
12'hc72: data = 16'b0111000111000111; // *** *** ***
12'hc73: data = 16'b0111000111000111; // *** *** ***
12'hc74: data = 16'b0111000111000111; // *** *** ***
12'hc75: data = 16'b0111000111000111; // *** *** ***
12'hc76: data = 16'b0111000111000111; // *** *** ***
12'hc77: data = 16'b0111000111000111; // *** *** ***
12'hc78: data = 16'b0000000000000000; //
12'hc79: data = 16'b0000000000000000; //
12'hc7a: data = 16'b0000000000000000; //
12'hc7b: data = 16'b0000000000000000; //
12'hc7c: data = 16'b0000000000000000; //
12'hc7d: data = 16'b0000000000000000; //
12'hc7e: data = 16'b0000000000000000; //
12'hc7f: data = 16'b0000000000000000; //
//code xc8 y xc9 p
12'hc80: data = 16'b0000000000000000; //
12'hc81: data = 16'b0000000000000000; //
12'hc82: data = 16'b0000000000000000; //
12'hc83: data = 16'b0000000000000000; //
12'hc84: data = 16'b0000000000000000; //
12'hc85: data = 16'b0000000000000000; //
12'hc86: data = 16'b0000000000000000; //
12'hc87: data = 16'b0000000000000000; //
12'hc88: data = 16'b0000000000000000; //
12'hc89: data = 16'b0000000000000000; //
12'hc8a: data = 16'b1110001111110000; // *** ******
12'hc8b: data = 16'b0111011111111000; // *** ********
12'hc8c: data = 16'b0011111001111100; // ***** *****
12'hc8d: data = 16'b0011110000111100; // **** ****
12'hc8e: data = 16'b0011110000111100; // **** ****
12'hc8f: data = 16'b0011110000111100; // **** ****
12'hc90: data = 16'b0011110000111100; // **** ****
12'hc91: data = 16'b0011110000111100; // **** ****
12'hc92: data = 16'b0011110000111100; // **** ****
12'hc93: data = 16'b0011110000111100; // **** ****
12'hc94: data = 16'b0011110000111100; // **** ****
12'hc95: data = 16'b0011111001111100; // ***** *****
12'hc96: data = 16'b0011111111111000; // ***********
12'hc97: data = 16'b0011111111110000; // **********
12'hc98: data = 16'b0011110000000000; // ****
12'hc99: data = 16'b0011110000000000; // ****
12'hc9a: data = 16'b0011110000000000; // ****
12'hc9b: data = 16'b0011110000000000; // ****
12'hc9c: data = 16'b0011110000000000; // ****
12'hc9d: data = 16'b1111111100000000; // ********
12'hc9e: data = 16'b0000000000000000; //
12'hc9f: data = 16'b0000000000000000; //
default: data = 16'b0000000000000000;
endcase
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: ENCLab:ip:Tiger4NSC:1.2.3
// IP Revision: 1
(* X_CORE_INFO = "FMCTop,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "OpenSSD2_Tiger4NSC_1_0,FMCTop,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_Tiger4NSC_1_0 (
iClock,
iReset,
C_AWVALID,
C_AWREADY,
C_AWADDR,
C_AWPROT,
C_WVALID,
C_WREADY,
C_WDATA,
C_WSTRB,
C_BVALID,
C_BREADY,
C_BRESP,
C_ARVALID,
C_ARREADY,
C_ARADDR,
C_ARPROT,
C_RVALID,
C_RREADY,
C_RDATA,
C_RRESP,
D_AWADDR,
D_AWLEN,
D_AWSIZE,
D_AWBURST,
D_AWCACHE,
D_AWPROT,
D_AWVALID,
D_AWREADY,
D_WDATA,
D_WSTRB,
D_WLAST,
D_WVALID,
D_WREADY,
D_BRESP,
D_BVALID,
D_BREADY,
D_ARADDR,
D_ARLEN,
D_ARSIZE,
D_ARBURST,
D_ARCACHE,
D_ARPROT,
D_ARVALID,
D_ARREADY,
D_RDATA,
D_RRESP,
D_RLAST,
D_RVALID,
D_RREADY,
oOpcode,
oTargetID,
oSourceID,
oAddress,
oLength,
oCMDValid,
iCMDReady,
oWriteData,
oWriteLast,
oWriteValid,
iWriteReady,
iReadData,
iReadLast,
iReadValid,
oReadReady,
iReadyBusy,
oROMClock,
oROMReset,
oROMAddr,
oROMRW,
oROMEnable,
oROMWData,
iROMRData,
iSharedKESReady,
oErrorDetectionEnd,
oDecodeNeeded,
oSyndromes,
iIntraSharedKESEnd,
iErroredChunk,
iCorrectionFail,
iErrorCount,
iELPCoefficients,
oCSAvailable,
O_DEBUG
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire iClock;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 signal_reset RST" *)
input wire iReset;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWVALID" *)
input wire C_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWREADY" *)
output wire C_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWADDR" *)
input wire [31 : 0] C_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWPROT" *)
input wire [2 : 0] C_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WVALID" *)
input wire C_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WREADY" *)
output wire C_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WDATA" *)
input wire [31 : 0] C_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WSTRB" *)
input wire [3 : 0] C_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI BVALID" *)
output wire C_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI BREADY" *)
input wire C_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI BRESP" *)
output wire [1 : 0] C_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARVALID" *)
input wire C_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARREADY" *)
output wire C_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARADDR" *)
input wire [31 : 0] C_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARPROT" *)
input wire [2 : 0] C_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RVALID" *)
output wire C_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RREADY" *)
input wire C_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RDATA" *)
output wire [31 : 0] C_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RRESP" *)
output wire [1 : 0] C_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWADDR" *)
output wire [31 : 0] D_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWLEN" *)
output wire [7 : 0] D_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWSIZE" *)
output wire [2 : 0] D_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWBURST" *)
output wire [1 : 0] D_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWCACHE" *)
output wire [3 : 0] D_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWPROT" *)
output wire [2 : 0] D_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWVALID" *)
output wire D_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWREADY" *)
input wire D_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WDATA" *)
output wire [31 : 0] D_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WSTRB" *)
output wire [3 : 0] D_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WLAST" *)
output wire D_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WVALID" *)
output wire D_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WREADY" *)
input wire D_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI BRESP" *)
input wire [1 : 0] D_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI BVALID" *)
input wire D_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI BREADY" *)
output wire D_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARADDR" *)
output wire [31 : 0] D_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARLEN" *)
output wire [7 : 0] D_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARSIZE" *)
output wire [2 : 0] D_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARBURST" *)
output wire [1 : 0] D_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARCACHE" *)
output wire [3 : 0] D_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARPROT" *)
output wire [2 : 0] D_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARVALID" *)
output wire D_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARREADY" *)
input wire D_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RDATA" *)
input wire [31 : 0] D_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RRESP" *)
input wire [1 : 0] D_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RLAST" *)
input wire D_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RVALID" *)
input wire D_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RREADY" *)
output wire D_RREADY;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface Opcode" *)
output wire [5 : 0] oOpcode;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface TargetID" *)
output wire [4 : 0] oTargetID;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface SourceID" *)
output wire [4 : 0] oSourceID;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface Address" *)
output wire [31 : 0] oAddress;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface Length" *)
output wire [15 : 0] oLength;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface CMDValid" *)
output wire oCMDValid;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface CMDReady" *)
input wire iCMDReady;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteData" *)
output wire [31 : 0] oWriteData;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteLast" *)
output wire oWriteLast;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteValid" *)
output wire oWriteValid;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteReady" *)
input wire iWriteReady;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadData" *)
input wire [31 : 0] iReadData;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadLast" *)
input wire iReadLast;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadValid" *)
input wire iReadValid;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadReady" *)
output wire oReadReady;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadyBusy" *)
input wire [7 : 0] iReadyBusy;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface CLK" *)
output wire oROMClock;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface RST" *)
output wire oROMReset;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface ADDR" *)
output wire [255 : 0] oROMAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface WE" *)
output wire oROMRW;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface EN" *)
output wire oROMEnable;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface DIN" *)
output wire [63 : 0] oROMWData;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface DOUT" *)
input wire [63 : 0] iROMRData;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface SharedKESReady" *)
input wire iSharedKESReady;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ErrorDetectionEnd" *)
output wire [1 : 0] oErrorDetectionEnd;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface DecodeNeeded" *)
output wire [1 : 0] oDecodeNeeded;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface Syndromes" *)
output wire [647 : 0] oSyndromes;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface IntraSharedKESEnd" *)
input wire iIntraSharedKESEnd;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ErroredChunk" *)
input wire [1 : 0] iErroredChunk;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface CorrectionFail" *)
input wire [1 : 0] iCorrectionFail;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ErrorCount" *)
input wire [17 : 0] iErrorCount;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ELPCoefficients" *)
input wire [359 : 0] iELPCoefficients;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface CSAvailable" *)
output wire oCSAvailable;
output wire [31 : 0] O_DEBUG;
FMCTop #(
.NumberOfWays(8),
.ProgWordWidth(64),
.UProgSize(256),
.BCHDecMulti(2),
.GaloisFieldDegree(12),
.MaxErrorCountBits(9),
.Syndromes(27),
.ELPCoefficients(15)
) inst (
.iClock(iClock),
.iReset(iReset),
.C_AWVALID(C_AWVALID),
.C_AWREADY(C_AWREADY),
.C_AWADDR(C_AWADDR),
.C_AWPROT(C_AWPROT),
.C_WVALID(C_WVALID),
.C_WREADY(C_WREADY),
.C_WDATA(C_WDATA),
.C_WSTRB(C_WSTRB),
.C_BVALID(C_BVALID),
.C_BREADY(C_BREADY),
.C_BRESP(C_BRESP),
.C_ARVALID(C_ARVALID),
.C_ARREADY(C_ARREADY),
.C_ARADDR(C_ARADDR),
.C_ARPROT(C_ARPROT),
.C_RVALID(C_RVALID),
.C_RREADY(C_RREADY),
.C_RDATA(C_RDATA),
.C_RRESP(C_RRESP),
.D_AWADDR(D_AWADDR),
.D_AWLEN(D_AWLEN),
.D_AWSIZE(D_AWSIZE),
.D_AWBURST(D_AWBURST),
.D_AWCACHE(D_AWCACHE),
.D_AWPROT(D_AWPROT),
.D_AWVALID(D_AWVALID),
.D_AWREADY(D_AWREADY),
.D_WDATA(D_WDATA),
.D_WSTRB(D_WSTRB),
.D_WLAST(D_WLAST),
.D_WVALID(D_WVALID),
.D_WREADY(D_WREADY),
.D_BRESP(D_BRESP),
.D_BVALID(D_BVALID),
.D_BREADY(D_BREADY),
.D_ARADDR(D_ARADDR),
.D_ARLEN(D_ARLEN),
.D_ARSIZE(D_ARSIZE),
.D_ARBURST(D_ARBURST),
.D_ARCACHE(D_ARCACHE),
.D_ARPROT(D_ARPROT),
.D_ARVALID(D_ARVALID),
.D_ARREADY(D_ARREADY),
.D_RDATA(D_RDATA),
.D_RRESP(D_RRESP),
.D_RLAST(D_RLAST),
.D_RVALID(D_RVALID),
.D_RREADY(D_RREADY),
.oOpcode(oOpcode),
.oTargetID(oTargetID),
.oSourceID(oSourceID),
.oAddress(oAddress),
.oLength(oLength),
.oCMDValid(oCMDValid),
.iCMDReady(iCMDReady),
.oWriteData(oWriteData),
.oWriteLast(oWriteLast),
.oWriteValid(oWriteValid),
.iWriteReady(iWriteReady),
.iReadData(iReadData),
.iReadLast(iReadLast),
.iReadValid(iReadValid),
.oReadReady(oReadReady),
.iReadyBusy(iReadyBusy),
.oROMClock(oROMClock),
.oROMReset(oROMReset),
.oROMAddr(oROMAddr),
.oROMRW(oROMRW),
.oROMEnable(oROMEnable),
.oROMWData(oROMWData),
.iROMRData(iROMRData),
.iSharedKESReady(iSharedKESReady),
.oErrorDetectionEnd(oErrorDetectionEnd),
.oDecodeNeeded(oDecodeNeeded),
.oSyndromes(oSyndromes),
.iIntraSharedKESEnd(iIntraSharedKESEnd),
.iErroredChunk(iErroredChunk),
.iCorrectionFail(iCorrectionFail),
.iErrorCount(iErrorCount),
.iELPCoefficients(iELPCoefficients),
.oCSAvailable(oCSAvailable),
.O_DEBUG(O_DEBUG)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_PP_SYMBOL_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer
// Mirror data for simple accesses.
// Merge data for burst.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_w_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_fix,
input wire cmd_modified,
input wire cmd_complete_wrap,
input wire cmd_packed_wrap,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_S_AXI_BYTES_LOG:0] cmd_step,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for SI-side word lanes on MI-side.
genvar word_cnt;
// Generate variable for intra SI-word byte control (on MI-side) for always pack.
genvar byte_cnt;
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
wire sel_first_word;
wire first_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] current_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire [C_RATIO-1:0] current_word_idx;
wire last_beat;
wire last_word;
wire last_word_extra_carry;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;
// Sub-word handling for the next cycle.
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
wire first_mi_word;
wire [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Handle wrap buffering.
wire store_in_wrap_buffer_enabled;
wire store_in_wrap_buffer;
wire ARESET_or_store_in_wrap_buffer;
wire use_wrap_buffer;
reg wrap_buffer_available;
// Detect start of MI word.
wire first_si_in_mi;
// Throttling help signals.
wire word_complete_next_wrap;
wire word_complete_next_wrap_qual;
wire word_complete_next_wrap_valid;
wire word_complete_next_wrap_pop;
wire word_complete_next_wrap_last;
wire word_complete_next_wrap_stall;
wire word_complete_last_word;
wire word_complete_rest;
wire word_complete_rest_qual;
wire word_complete_rest_valid;
wire word_complete_rest_pop;
wire word_complete_rest_last;
wire word_complete_rest_stall;
wire word_completed;
wire word_completed_qualified;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal packed write data.
wire use_expander_data;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wdata_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wrap_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_i; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_i; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_last_word_mux;
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_last_word_mux;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer;
// Internal signals for MI-side.
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Data on the MI-side is available when data a complete word has been
// assembled from the data on SI-side (and potentially from any remainder in
// the wrap buffer).
// No data is produced on the MI-side when a unaligned packed wrap is
// encountered, instead it stored in the wrap buffer to be used when the
// last SI-side data beat is received.
//
// The command is popped from the command queue once the last beat on the
// SI-side has been ackowledged.
//
// The packing process is stalled when a new MI-side is completed but not
// yet acknowledged (by ready).
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING
assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};
end else begin : NO_LARGE_UPSIZING
assign cmd_step_i = cmd_step;
end
endgenerate
generate
if ( C_FAMILY == "rtl" ||
( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED
// Detect when MI-side word is completely assembled.
assign word_completed = ( cmd_fix ) |
( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( ~cmd_fix & last_word ) |
( ~cmd_modified ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_completed_qualified = word_completed & cmd_valid & ~store_in_wrap_buffer_enabled;
// RTL equivalent of optimized partial extressions (address wrap for next word).
assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap &
next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_complete_next_wrap_qual = word_complete_next_wrap & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_next_wrap_valid = word_complete_next_wrap_qual & S_AXI_WVALID;
assign word_complete_next_wrap_pop = word_complete_next_wrap_valid & M_AXI_WREADY_I;
assign word_complete_next_wrap_last = word_complete_next_wrap_pop & M_AXI_WLAST_I;
assign word_complete_next_wrap_stall = word_complete_next_wrap_valid & ~M_AXI_WREADY_I;
// RTL equivalent of optimized partial extressions (last word and the remaining).
assign word_complete_last_word = last_word & ~cmd_fix;
assign word_complete_rest = word_complete_last_word | cmd_fix | ~cmd_modified;
assign word_complete_rest_qual = word_complete_rest & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_rest_valid = word_complete_rest_qual & S_AXI_WVALID;
assign word_complete_rest_pop = word_complete_rest_valid & M_AXI_WREADY_I;
assign word_complete_rest_last = word_complete_rest_pop & M_AXI_WLAST_I;
assign word_complete_rest_stall = word_complete_rest_valid & ~M_AXI_WREADY_I;
end else begin : USE_FPGA_WORD_COMPLETED
wire next_word_wrap;
wire sel_word_complete_next_wrap;
wire sel_word_complete_next_wrap_qual;
wire sel_word_complete_next_wrap_stall;
wire sel_last_word;
wire sel_word_complete_rest;
wire sel_word_complete_rest_qual;
wire sel_word_complete_rest_stall;
// Optimize next word address wrap branch of expression.
//
generic_baseblocks_v2_1_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) next_word_wrap_inst
(
.CIN(1'b1),
.S(sel_first_word),
.A(pre_next_word_1),
.B(cmd_next_word),
.COUT(next_word_wrap)
);
assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_inst
(
.CIN(next_word_wrap),
.S(sel_word_complete_next_wrap),
.COUT(word_complete_next_wrap)
);
assign sel_word_complete_next_wrap_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_valid_inst
(
.CIN(word_complete_next_wrap),
.S(sel_word_complete_next_wrap_qual),
.COUT(word_complete_next_wrap_qual)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_qual_inst
(
.CIN(word_complete_next_wrap_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_next_wrap_valid)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_pop_inst
(
.CIN(word_complete_next_wrap_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_next_wrap_pop)
);
assign sel_word_complete_next_wrap_stall = ~M_AXI_WREADY_I;
generic_baseblocks_v2_1_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(word_complete_next_wrap_valid),
.I(sel_word_complete_next_wrap_stall),
.O(word_complete_next_wrap_stall)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_last_inst
(
.CIN(word_complete_next_wrap_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_next_wrap_last)
);
// Optimize last word and "rest" branch of expression.
//
assign sel_last_word = ~cmd_fix;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst_2
(
.CIN(last_word_extra_carry),
.S(sel_last_word),
.COUT(word_complete_last_word)
);
assign sel_word_complete_rest = cmd_fix | ~cmd_modified;
generic_baseblocks_v2_1_carry_or #
(
.C_FAMILY(C_FAMILY)
) pop_si_data_inst
(
.CIN(word_complete_last_word),
.S(sel_word_complete_rest),
.COUT(word_complete_rest)
);
assign sel_word_complete_rest_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_valid_inst
(
.CIN(word_complete_rest),
.S(sel_word_complete_rest_qual),
.COUT(word_complete_rest_qual)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_qual_inst
(
.CIN(word_complete_rest_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_rest_valid)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_pop_inst
(
.CIN(word_complete_rest_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_rest_pop)
);
assign sel_word_complete_rest_stall = ~M_AXI_WREADY_I;
generic_baseblocks_v2_1_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_stall_inst
(
.CIN(word_complete_rest_valid),
.I(sel_word_complete_rest_stall),
.O(word_complete_rest_stall)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_last_inst
(
.CIN(word_complete_rest_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_rest_last)
);
// Combine the two branches to generate the full signal.
assign word_completed = word_complete_next_wrap | word_complete_rest;
assign word_completed_qualified = word_complete_next_wrap_qual | word_complete_rest_qual;
end
endgenerate
// Pop word from SI-side.
assign S_AXI_WREADY_I = ~mi_stalling & cmd_valid;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_M_WVALID
assign M_AXI_WVALID_I = S_AXI_WVALID & word_completed_qualified;
end else begin : USE_FPGA_M_WVALID
assign M_AXI_WVALID_I = ( word_complete_next_wrap_valid | word_complete_rest_valid);
end
endgenerate
// Get SI-side data.
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER_SI_POP
assign pop_si_data = S_AXI_WVALID & ~mi_stalling & cmd_valid;
end else begin : NO_REGISTER_SI_POP
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_SI
assign pop_si_data = S_AXI_WVALID & S_AXI_WREADY_I;
end else begin : USE_FPGA_POP_SI
assign pop_si_data = ~( word_complete_next_wrap_stall | word_complete_rest_stall ) &
cmd_valid & S_AXI_WVALID;
end
end
endgenerate
// Signal that the command is done (so that it can be poped from command queue).
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_CMD_READY
assign cmd_ready_i = cmd_valid & M_AXI_WLAST_I & pop_mi_data_i;
end else begin : USE_FPGA_CMD_READY
assign cmd_ready_i = ( word_complete_next_wrap_last | word_complete_rest_last);
end
endgenerate
assign cmd_ready = cmd_ready_i;
// Set last upsized word.
assign M_AXI_WLAST_I = S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Write transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offest points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be packed, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first SI-side data beat.
//
// First MI is set while the entire first MI-side word is processed.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each generated MI word it is decreased
// until Last beat is reached.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple SI words per MI word
assign sel_first_word = first_word | cmd_fix;
assign current_word = sel_first_word ? cmd_first_word :
current_word_1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD
// Calculate next word.
assign pre_next_word_i = ( next_word_i + cmd_step_i );
// Calculate next word.
assign next_word_i = sel_first_word ? cmd_next_word :
pre_next_word_1;
end else begin : USE_FPGA_NEXT_WORD
wire [C_M_AXI_BYTES_LOG-1:0] next_sel;
wire [C_M_AXI_BYTES_LOG:0] next_carry_local;
// Assign input to local vectors.
assign next_carry_local[0] = 1'b0;
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
LUT6_2 # (
.INIT(64'h5A5A_5A66_F0F0_F0CC)
) LUT6_2_inst (
.O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)
.I3(first_word), // LUT input (1-bit)
.I4(cmd_fix), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY next_carry_inst
(
.O (next_carry_local[bit_cnt+1]),
.CI (next_carry_local[bit_cnt]),
.DI (cmd_step_i[bit_cnt]),
.S (next_sel[bit_cnt])
);
XORCY next_xorcy_inst
(
.O(pre_next_word_i[bit_cnt]),
.CI(next_carry_local[bit_cnt]),
.LI(next_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Calculate next word.
assign next_word = next_word_i & cmd_mask;
assign pre_next_word = pre_next_word_i & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = sel_first_word ? ( cmd_first_word | cmd_offset ) :
( current_word_1 | cmd_offset );
// Prepare next word address.
generate
if ( C_FAMILY == "rtl" || C_M_AXI_REGISTER ) begin : USE_RTL_CURR_WORD
reg [C_M_AXI_BYTES_LOG-1:0] current_word_q;
reg first_word_q;
reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_q;
always @ (posedge ACLK) begin
if (ARESET) begin
first_word_q <= 1'b1;
current_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
pre_next_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
end else begin
if ( pop_si_data ) begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_q <= 1'b1;
end else begin
first_word_q <= 1'b0;
end
current_word_q <= next_word;
pre_next_word_q <= pre_next_word;
end
end
end
assign first_word = first_word_q;
assign current_word_1 = current_word_q;
assign pre_next_word_1 = pre_next_word_q;
end else begin : USE_FPGA_CURR_WORD
reg first_word_cmb;
wire first_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] local_pre_next_word_i;
always @ *
begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_cmb = 1'b1;
end else begin
first_word_cmb = 1'b0;
end
end
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_current_inst (
.O(current_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(next_word[bit_cnt]), // LUT input (1-bit)
.I1(current_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_current_inst (
.Q(current_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(current_word_i[bit_cnt]) // Data input
);
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_next_inst (
.O(local_pre_next_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(pre_next_word[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_next_inst (
.Q(pre_next_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(local_pre_next_word_i[bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_first_inst (
.O(first_word_i), // 6-LUT output (1-bit)
.I0(first_word_cmb), // LUT input (1-bit)
.I1(first_word), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_first_inst (
.Q(first_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_word_i) // Data input
);
end
endgenerate
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH
reg [8-1:0] length_counter_q;
reg first_mi_word_q;
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word_q <= 1'b1;
length_counter_q <= 8'b0;
end else begin
if ( pop_mi_data_i ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word_q <= 1'b1;
end else begin
first_mi_word_q <= 1'b0;
end
length_counter_q <= next_length_counter;
end
end
end
assign first_mi_word = first_mi_word_q;
assign length_counter_1 = length_counter_q;
end else begin : USE_FPGA_LENGTH
wire [8-1:0] length_counter_i;
wire [8-1:0] length_counter_ii;
wire [8-1:0] length_sel;
wire [8-1:0] length_di;
wire [8:0] length_local_carry;
// Assign input to local vectors.
assign length_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6_2 # (
.INIT(64'h333C_555A_FFF0_FFF0)
) LUT6_length_inst (
.O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(length_di[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(cmd_length[bit_cnt]), // LUT input (1-bit)
.I2(1'b1), // LUT input (1-bit)
.I3(1'b1), // LUT input (1-bit)
.I4(first_mi_word), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY carry_inst
(
.O (length_local_carry[bit_cnt+1]),
.CI (length_local_carry[bit_cnt]),
.DI (length_di[bit_cnt]),
.S (length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(length_counter_ii[bit_cnt]),
.CI(length_local_carry[bit_cnt]),
.LI(length_sel[bit_cnt])
);
LUT4 # (
.INIT(16'hCCCA)
) LUT4_inst (
.O(length_counter_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(length_counter_ii[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_length_inst (
.Q(length_counter_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(length_counter_i[bit_cnt]) // Data input
);
end // end for bit_cnt
wire first_mi_word_i;
LUT6 # (
.INIT(64'hAAAC_AAAC_AAAC_AAAC)
) LUT6_first_mi_inst (
.O(first_mi_word_i), // 6-LUT output (1-bit)
.I0(M_AXI_WLAST_I), // LUT input (1-bit)
.I1(first_mi_word), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop), // LUT input (1-bit)
.I4(1'b1), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_inst (
.Q(first_mi_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_mi_word_i) // Data input
);
end
endgenerate
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LAST_WORD
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be assembled into this MI-side word.
assign last_word = ( cmd_modified & last_beat & ( current_word == cmd_last_word ) );
end else begin : USE_FPGA_LAST_WORD
wire last_beat_curr_word;
generic_baseblocks_v2_1_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE(8'b0),
.C_DATA_WIDTH(8)
) last_beat_inst
(
.CIN(1'b1),
.S(first_mi_word),
.A(length_counter_1),
.B(cmd_length),
.COUT(last_beat)
);
generic_baseblocks_v2_1_comparator_sel #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) last_beat_curr_word_inst
(
.CIN(last_beat),
.S(sel_first_word),
.A(current_word_1),
.B(cmd_first_word),
.V(cmd_last_word),
.COUT(last_beat_curr_word)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst
(
.CIN(last_beat_curr_word),
.S(cmd_modified),
.COUT(last_word)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle wrap buffer:
//
// The wrap buffer is used to move data around in an unaligned WRAP
// transaction. SI-side data word(s) for an unaligned accesses are delay
// to be packed with with the tail of the transaction to make it a WRAP
// transaction that is aligned to native MI-side data with.
// For example: an 32bit to 64bit write upsizing @ 0x4 will delay the first
// word until the 0x0 data arrives in the last data beat. This will make the
// Upsized transaction be WRAP at 0x8 on the MI-side
// (was WRAP @ 0x4 on SI-side).
//
/////////////////////////////////////////////////////////////////////////////
// The unaligned SI-side words are pushed into the wrap buffer.
assign store_in_wrap_buffer_enabled = cmd_packed_wrap & ~wrap_buffer_available & cmd_valid;
assign store_in_wrap_buffer = store_in_wrap_buffer_enabled & S_AXI_WVALID;
assign ARESET_or_store_in_wrap_buffer = store_in_wrap_buffer | ARESET;
// The wrap buffer is used to complete last word.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_USE_WRAP
assign use_wrap_buffer = wrap_buffer_available & last_word;
end else begin : USE_FPGA_USE_WRAP
wire last_word_carry;
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst2
(
.CIN(last_word),
.S(1'b1),
.COUT(last_word_carry)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst3
(
.CIN(last_word_carry),
.S(1'b1),
.COUT(last_word_extra_carry)
);
carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(last_word_carry),
.I(wrap_buffer_available),
.O(use_wrap_buffer)
);
end
endgenerate
// Wrap buffer becomes available when the unaligned wrap words has been taken care of.
always @ (posedge ACLK) begin
if (ARESET) begin
wrap_buffer_available <= 1'b0;
end else begin
if ( store_in_wrap_buffer & word_completed ) begin
wrap_buffer_available <= 1'b1;
end else if ( cmd_ready_i ) begin
wrap_buffer_available <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pack multiple data SI-side words into fewer MI-side data word.
// Data is only packed when modify is set. Granularity is SI-side word for
// the combinatorial data mux.
//
// Expander:
// WDATA is expanded to all SI-word lane on the MI-side.
// WSTRB is activted to the correct SI-word lane on the MI-side.
//
// Packer:
// The WDATA and WSTRB registers are always cleared before a new word is
// assembled.
// WDATA is (SI-side word granularity)
// * Combinatorial WDATA is used for current word line or when expanding.
// * All other is taken from registers.
// WSTRB is
// * Combinatorial for single data to matching word lane
// * Zero for single data to mismatched word lane
// * Register data when multiple data
//
// To support sub-sized packing during Always Pack is the combinatorial
// information packed with "or" instead of multiplexing.
//
/////////////////////////////////////////////////////////////////////////////
// Determine if expander data should be used.
assign use_expander_data = ~cmd_modified & cmd_valid;
// Registers and combinatorial data word mux.
generate
for (word_cnt = 0; word_cnt < C_RATIO ; word_cnt = word_cnt + 1) begin : WORD_LANE
// Generate select signal per SI-side word.
if ( C_RATIO == 1 ) begin : SINGLE_WORD
assign current_word_idx[word_cnt] = 1'b1;
end else begin : MULTIPLE_WORD
assign current_word_idx[word_cnt] = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG] == word_cnt;
end
if ( ( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_EXPANDER
// Expander only functionality.
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = {C_S_AXI_DATA_WIDTH{1'b0}};
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end else begin
if ( pop_si_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end
end
end else begin : NO_REGISTER
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end // end if C_M_AXI_REGISTER
end else begin : USE_ALWAYS_PACKER
// Packer functionality
for (byte_cnt = 0; byte_cnt < C_S_AXI_DATA_WIDTH / 8 ; byte_cnt = byte_cnt + 1) begin : BYTE_LANE
if ( C_FAMILY == "rtl" ) begin : USE_RTL_DATA
// Generate extended write data and strobe in wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
end else if ( pop_mi_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
end
if ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b1;
end else if ( pop_mi_data ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end
end
end
end else begin : NO_REGISTER
// Generate extended write data and strobe.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( pop_mi_data | store_in_wrap_buffer_enabled ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & pop_si_data & S_AXI_WSTRB[byte_cnt] ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
end // end if C_M_AXI_REGISTER
end else begin : USE_FPGA_DATA
always @ *
begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];
end else begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_data_inst (
.O(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_strb_inst (
.O(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(S_AXI_WSTRB[byte_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end else begin : NO_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & cmd_valid & S_AXI_WSTRB[byte_cnt];
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] &
S_AXI_WSTRB[byte_cnt] &
cmd_valid & S_AXI_WVALID;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_data_inst (
.O(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'h0000_0000_0000_AAAE)
) LUT6_strb_inst (
.O(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(word_complete_rest_pop), // LUT input (1-bit)
.I5(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET_or_store_in_wrap_buffer), // Synchronous reset input
.D(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]}} ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt] |
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] );
end
end // end if C_M_AXI_REGISTER
end // end if C_FAMILY
end // end for byte_cnt
end // end if USE_ALWAYS_PACKER
end // end for word_cnt
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
reg M_AXI_WLAST_q;
reg M_AXI_WVALID_q;
// Register MI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WLAST_q <= 1'b0;
M_AXI_WVALID_q <= 1'b0;
end else begin
if ( M_AXI_WREADY_I ) begin
M_AXI_WLAST_q <= M_AXI_WLAST_I;
M_AXI_WVALID_q <= M_AXI_WVALID_I;
end
end
end
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_q;
assign M_AXI_WVALID = M_AXI_WVALID_q;
assign M_AXI_WREADY_I = ( M_AXI_WVALID_q & M_AXI_WREADY) | ~M_AXI_WVALID_q;
// Get MI-side data.
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
assign pop_mi_data = M_AXI_WVALID_q & M_AXI_WREADY_I;
// Detect when MI-side is stalling.
assign mi_stalling = ( M_AXI_WVALID_q & ~M_AXI_WREADY_I ) & ~store_in_wrap_buffer_enabled;
end else begin : NO_REGISTER
// Combinatorial MI-side Data.
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
// Get MI-side data.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_MI
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
end else begin : USE_FPGA_POP_MI
assign pop_mi_data_i = ( word_complete_next_wrap_pop | word_complete_rest_pop);
end
assign pop_mi_data = pop_mi_data_i;
// Detect when MI-side is stalling.
assign mi_stalling = word_completed_qualified & ~M_AXI_WREADY_I;
end
endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : axi_basic_top.v
// Version : 2.4
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for constant arrays access
module constant_array_test();
reg [7:0] out_word;
reg [2:0] index;
constant_array dut(index, out_word);
initial begin
index = 2;
#1; // wait for signal assignments
if(out_word !== 16)
begin
$display("FAILED 1");
$finish();
end
index = 4;
#1;
if(out_word !== 64)
begin
$display("FAILED 2");
$finish();
end
if(dut.test_a !== 32)
begin
$display("FAILED 3");
$finish();
end
if(dut.test_b !== 4)
begin
$display("FAILED 4");
$finish();
end
if(dut.test_c !== 3'b100)
begin
$display("FAILED 5");
$finish();
end
if(dut.test_d !== 1'b1)
begin
$display("FAILED 6");
$finish();
end
$display("PASSED");
end
endmodule
|
`default_nettype none
module simple_ddr3(
input wire clk, // clk491520
input wire rst,
input wire [27:0] addr_i,
input wire [31:0] data_i,
input wire we_i,
input wire pop_i,
output wire [31:0] data_o,
output wire ack_o,
output wire busy_o,
// MIG interface
output wire mig_cmd_clk,
output wire mig_cmd_en,
output wire [2:0] mig_cmd_instr,
output wire [5:0] mig_cmd_bl,
output wire [29:0] mig_cmd_byte_addr,
input wire mig_cmd_empty,
input wire mig_cmd_full,
output wire mig_wr_clk,
output wire mig_wr_en,
output wire [3:0] mig_wr_mask,
output wire [31:0] mig_wr_data,
input wire mig_wr_full,
input wire mig_wr_empty,
input wire [6:0] mig_wr_count,
input wire mig_wr_underrun,
input wire mig_wr_error,
output wire mig_rd_clk,
output wire mig_rd_en,
input wire [31:0] mig_rd_data,
input wire mig_rd_full,
input wire mig_rd_empty,
input wire [6:0] mig_rd_count,
input wire mig_rd_overflow,
input wire mig_rd_error);
reg [27:0] addr_ff;
reg [31:0] wdata_ff;
reg [31:0] rdata_ff;
reg ack_ff;
reg [5:0] state_ff;
localparam ST_INIT = 1;
localparam ST_FILL_WRBUF = 2;
localparam ST_EMIT_WR_CMD = 3;
localparam ST_EMIT_RD_CMD = 4;
localparam ST_WAIT_RD_DATA = 5;
always @(posedge clk) begin
if (rst) begin
addr_ff <= 28'b0;
wdata_ff <= 32'b0;
rdata_ff <= 32'b0;
state_ff <= ST_INIT;
ack_ff <= 1'b0;
end else begin
case (state_ff)
ST_INIT: begin
addr_ff <= addr_i;
wdata_ff <= data_i;
ack_ff <= 1'b0;
if (we_i) begin
state_ff <= ST_FILL_WRBUF;
end else if (pop_i) begin
state_ff <= ST_EMIT_RD_CMD;
end else begin
state_ff <= ST_INIT;
end
end
ST_FILL_WRBUF: begin
state_ff <= ST_EMIT_WR_CMD;
ack_ff <= 1'b0;
end
ST_EMIT_WR_CMD: begin
state_ff <= ST_INIT;
ack_ff <= 1'b0;
end
ST_EMIT_RD_CMD: begin
state_ff <= ST_WAIT_RD_DATA;
ack_ff <= 1'b0;
end
ST_WAIT_RD_DATA: begin
if (mig_rd_count == 6'h00) begin // FIXME: mig_rd_empty?
state_ff <= ST_WAIT_RD_DATA;
ack_ff <= 1'b0;
end else begin
rdata_ff <= mig_rd_data;
state_ff <= ST_INIT;
ack_ff <= 1'b1;
end
end
endcase
end
end
assign mig_cmd_clk = clk;
assign mig_cmd_en = (state_ff == ST_EMIT_RD_CMD || state_ff == ST_EMIT_WR_CMD) ? 1'b1 : 1'b0;
assign mig_cmd_instr = (state_ff == ST_EMIT_RD_CMD) ? 3'b001 : 3'b010;
assign mig_cmd_bl = 6'b0;
assign mig_cmd_byte_addr[29:0] = {addr_ff, 2'b00};
// FIXME: wait until mig_cmd_empty or !mig_cmd_full?
assign mig_wr_clk = clk;
assign mig_wr_en = (state_ff == ST_FILL_WRBUF) ? 1'b1 : 1'b0;
assign mig_wr_mask = 4'b0000;
assign mig_wr_data = wdata_ff;
// mig_wr_full, mig_wr_empty, mig_wr_count, mig_wr_underrun, mig_wr_error
assign mig_rd_clk = clk;
assign mig_rd_en = (state_ff == ST_WAIT_RD_DATA) ? 1'b1 : 1'b0;
// mig_rd_full, mig_rd_empty, mig_rd_overflow, mig_rd_error
assign data_o = rdata_ff;
assign ack_o = ack_ff;
assign busy_o = (state_ff != ST_INIT) ? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
// Josh Sackos
//
// Create Date: 07/26/2012
// Module Name: slaveSelect
// Project Name: PmodACL_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: A simple module involving the switching of the slave select line
// during transmission and idle states.
//
// Inputs:
// rst User input Reset
// transmit signal from SPImaster causing ss line to go low
// ( enable )
// done signal from SPIinterface causing ss line to go
// high ( disable )
//
// Outputs:
// ss ss output to ACL
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added comments and modified code (Josh Sackos)
////////////////////////////////////////////////////////////////////////////////////
// ===================================================================================
// Define Module, Inputs and Outputs
// ===================================================================================
module slaveSelect(
rst,
clk,
transmit,
done,
ss
);
// ====================================================================================
// Port Declarations
// ====================================================================================
input rst;
input clk;
input transmit;
input done;
output ss;
reg ss = 1'b1;
// ===================================================================================
// Implementation
// ===================================================================================
//-----------------------------------------------
// Generates Slave Select Signal
//-----------------------------------------------
always @(posedge clk)
begin: ssprocess
begin
//reset state, ss goes high ( disabled )
if (rst == 1'b1)
ss <= 1'b1;
//if transmitting, then ss goes low ( enabled )
else if (transmit == 1'b1)
ss <= 1'b0;
//if done, then ss goes high ( disabled )
else if (done == 1'b1)
ss <= 1'b1;
end
end
endmodule
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/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_ocm_mem.v
*
* Date : 2012-11
*
* Description : Mimics OCM model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_ocm_mem();
`include "processing_system7_bfm_v2_0_5_local_params.v"
parameter mem_size = 32'h4_0000; /// 256 KB
parameter mem_addr_width = clogb2(mem_size/mem_width);
reg [data_width-1:0] ocm_memory [0:(mem_size/mem_width)-1]; /// 256 KB memory
/* preload memory from file */
task automatic pre_load_mem_from_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
$readmemh(file_name,ocm_memory,start_addr>>shft_addr_bits);
endtask
/* preload memory with some random data */
task automatic pre_load_mem;
input [1:0] data_type;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
begin
addr = start_addr >> shft_addr_bits;
for (i = 0; i < no_of_bytes; i = i + mem_width) begin
case(data_type)
ALL_RANDOM : ocm_memory[addr] = $random;
ALL_ZEROS : ocm_memory[addr] = 32'h0000_0000;
ALL_ONES : ocm_memory[addr] = 32'hFFFF_FFFF;
default : ocm_memory[addr] = $random;
endcase
addr = addr+1;
end
end
endtask
/* Write memory */
task write_mem;
input [max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
reg [mem_addr_width-1:0] addr;
reg [max_burst_bits-1 :0] wr_temp_data;
reg [data_width-1:0] pre_pad_data,post_pad_data,temp_data;
integer bytes_left;
integer pre_pad_bytes;
integer post_pad_bytes;
begin
addr = start_addr >> shft_addr_bits;
wr_temp_data = data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Writing OCM Memory starting address (0x%0h) with %0d bytes.\n Data (0x%0h)",$time, DISP_INT_INFO, start_addr, no_of_bytes, data);
`endif
temp_data = wr_temp_data[data_width-1:0];
bytes_left = no_of_bytes;
/* when the no. of bytes to be updated is less than mem_width */
if(bytes_left < mem_width) begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
end
bytes_left = bytes_left + pre_pad_bytes;
end
/* This is needed for post padding the data ...*/
post_pad_bytes = mem_width - bytes_left;
post_pad_data = ocm_memory[addr];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end else begin
/* first data word in the burst , if unaligned address, the adjust the wr_data accordingly for first write*/
if(start_addr[shft_addr_bits-1:0] > 0) begin
temp_data = ocm_memory[addr];
pre_pad_bytes = mem_width - start_addr[shft_addr_bits-1:0];
repeat(pre_pad_bytes) temp_data = temp_data << 8;
repeat(pre_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = wr_temp_data[7:0];
wr_temp_data = wr_temp_data >> 8;
bytes_left = bytes_left -1;
end
end else begin
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
/* first data word end */
ocm_memory[addr] = temp_data;
addr = addr + 1;
while(bytes_left > (mem_width-1) ) begin /// for unaliged address necessary to check for mem_wd-1 , accordingly we have to pad post bytes.
ocm_memory[addr] = wr_temp_data[data_width-1:0];
addr = addr+1;
wr_temp_data = wr_temp_data >> data_width;
bytes_left = bytes_left - mem_width;
end
post_pad_data = ocm_memory[addr];
post_pad_bytes = mem_width - bytes_left;
/* This is needed for last transfer in unaliged burst */
if(bytes_left > 0) begin
temp_data = wr_temp_data[data_width-1:0];
repeat(post_pad_bytes) temp_data = temp_data << 8;
repeat(bytes_left) post_pad_data = post_pad_data >> 8;
repeat(post_pad_bytes) begin
temp_data = temp_data >> 8;
temp_data[data_width-1:data_width-8] = post_pad_data[7:0];
post_pad_data = post_pad_data >> 8;
end
ocm_memory[addr] = temp_data;
end
end
`ifdef XLNX_INT_DBG $display("[%0d] : %0s : DONE -> Writing OCM Memory starting address (0x%0h)",$time, DISP_INT_INFO, start_addr );
`endif
end
endtask
/* read_memory */
task read_mem;
output[max_burst_bits-1 :0] data;
input [addr_width-1:0] start_addr;
input [max_burst_bytes_width:0] no_of_bytes;
integer i;
reg [mem_addr_width-1:0] addr;
reg [data_width-1:0] temp_rd_data;
reg [max_burst_bits-1:0] temp_data;
integer pre_bytes;
integer bytes_left;
begin
addr = start_addr >> shft_addr_bits;
pre_bytes = start_addr[shft_addr_bits-1:0];
bytes_left = no_of_bytes;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : Reading OCM Memory starting address (0x%0h) -> %0d bytes",$time, DISP_INT_INFO, start_addr,no_of_bytes );
`endif
/* Get first data ... if unaligned address */
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
if(no_of_bytes < mem_width ) begin
temp_data = temp_data >> (pre_bytes * 8);
repeat(max_burst_bytes - mem_width)
temp_data = temp_data >> 8;
end else begin
bytes_left = bytes_left - (mem_width - pre_bytes);
addr = addr+1;
/* Got first data */
while (bytes_left > (mem_width-1) ) begin
temp_data = temp_data >> data_width;
temp_data[max_burst_bits-1 : max_burst_bits-data_width] = ocm_memory[addr];
addr = addr+1;
bytes_left = bytes_left - mem_width;
end
/* Get last valid data in the burst*/
temp_rd_data = ocm_memory[addr];
while(bytes_left > 0) begin
temp_data = temp_data >> 8;
temp_data[max_burst_bits-1 : max_burst_bits-8] = temp_rd_data[7:0];
temp_rd_data = temp_rd_data >> 8;
bytes_left = bytes_left - 1;
end
/* align to the brst_byte length */
repeat(max_burst_bytes - no_of_bytes)
temp_data = temp_data >> 8;
end
data = temp_data;
`ifdef XLNX_INT_DBG
$display("[%0d] : %0s : DONE -> Reading OCM Memory starting address (0x%0h), Data returned(0x%0h)",$time, DISP_INT_INFO, start_addr, data );
`endif
end
endtask
/* backdoor read to memory */
task peek_mem_to_file;
input [(max_chars*8)-1:0] file_name;
input [addr_width-1:0] start_addr;
input [int_width-1:0] no_of_bytes;
integer rd_fd;
integer bytes;
reg [addr_width-1:0] addr;
reg [data_width-1:0] rd_data;
begin
rd_fd = $fopen(file_name,"w");
bytes = no_of_bytes;
addr = start_addr >> shft_addr_bits;
while (bytes > 0) begin
rd_data = ocm_memory[addr];
$fdisplayh(rd_fd,rd_data);
bytes = bytes - 4;
addr = addr + 1;
end
end
endtask
endmodule
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