text
stringlengths 992
1.04M
|
|---|
/*
VGA Demo 800x600 at 72Hz
http://www-mtl.mit.edu/Courses/6.111/labkit/vga.shtml
800x600, 72Hz 50.000 800 56 120 64 600 37 6 23
Pixel Clock (MHz): 50.000
Horizontal (in Pixels)
Active Video: 800 (16us)
Front Porch: 56 (1.12us)
Sync Pulse: 120 (2.4us)
Back Porch: 64 (1.28us)
Total pixel clock ticks: 1040 (20.8us)
Vertical (in Lines, so x20.8us)
Active Video: 600 (12480us)
Front Porch: 37 (769.6us)
Sync Pulse: 6 (124.8us)
Back Porch: 23 (478.4us)
Total pixel clock ticks: 666 (13.32us)
Total pixel clock ticks: 692,640
50,000,000 / 692,640 = 72.187572188 = 72Hz
1 pixel clock = 1/50Mhz = 20ns = 0.02us
*/
module vga_demo
(
CLOCK_50,
RESET,
VGA_RED,
VGA_GREEN,
VGA_BLUE,
VGA_HS,
VGA_VS
);
input CLOCK_50;
input RESET;
output VGA_RED;
output VGA_GREEN;
output VGA_BLUE;
output VGA_HS;
output VGA_VS;
/* Internal registers for horizontal signal timing */
reg [10:0] hor_reg; // to count 1040 different values up to 1039
reg hor_sync;
wire hor_max = (hor_reg == 1039); // to tell when a line is full
/* Internal registers for vertical signal timing */
reg [9:0] ver_reg; // to count 666 different values up to 665
reg ver_sync;
reg red, green, blue;
wire ver_max = (ver_reg == 665); // to tell when a line is full
// Code
/* Running through line */
always @ (posedge CLOCK_50 or posedge RESET) begin
if (RESET) begin
hor_reg <= 0;
ver_reg <= 0;
end
else if (hor_max) begin
hor_reg <= 0;
/* Running through frame */
if (ver_max)
ver_reg <= 0;
else
ver_reg <= ver_reg + 1;
end else
hor_reg <= hor_reg + 1;
end
always @ (posedge CLOCK_50 or posedge RESET) begin
if (RESET) begin
hor_sync <= 0;
ver_sync <= 0;
end
else begin
/* Generating the horizontal sync signal */
if (hor_reg == 856) // video (800) + front porch (56)
hor_sync <= 1; // turn on horizontal sync pulse
else if (hor_reg == 976) // video (800) + front porch (56) + Sync Pulse (120)
hor_sync <= 0; // turn off horizontal sync pulse
/* Generating the vertical sync signal */
if (ver_reg == 637) // LINES: video (600) + front porch (37)
ver_sync <= 1; // turn on vertical sync pulse
else if (ver_reg == 643) // LINES: video (600) + front porch (37) + Sync Pulse (6)
ver_sync <= 0; // turn off vertical sync pulse
// Draw a single square.
if (hor_reg >= 100 && hor_reg <= 200 && ver_reg >= 100 && ver_reg <= 200) begin
red <= 1;
green <= 0;
blue <= 0;
end
else begin
red <= 1;
green <= 1;
blue <= 1;
end
end
end
// Send the sync signals to the output, inverted as the sync pulse is low.
// Maybe wrong as this doc says pulse id positive http://tinyvga.com/vga-timing/800x600@72Hz
assign VGA_HS = ~hor_sync;
assign VGA_VS = ~ver_sync;
// Send a pattern of colours (based on the registry bits) but do not output anything during the synchronization periods
//assign VGA_RED = (!hor_reg[0] && !ver_reg[0] && ver_reg < 600 && hor_reg < 800);
//assign VGA_GREEN = (!hor_reg[1] && !ver_reg[1] && ver_reg < 600 && hor_reg < 800);
//assign VGA_BLUE = (!hor_reg[2] && !ver_reg[2] && ver_reg < 600 && hor_reg < 800);
assign VGA_RED = red && ver_reg < 600 && hor_reg < 800;
assign VGA_GREEN = green && ver_reg < 600 && hor_reg < 800;
assign VGA_BLUE = blue && ver_reg < 600 && hor_reg < 800;
// http://gerfficient.com/2013/02/11/fpga-to-vga-using-de0-nano/
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module cmd_seq_core
#(
parameter ABUSWIDTH = 16,
parameter OUTPUTS = 1,
parameter CMD_MEM_SIZE = 2048
) (
input wire BUS_CLK,
input wire BUS_RST,
input wire [ABUSWIDTH-1:0] BUS_ADD,
input wire [7:0] BUS_DATA_IN,
input wire BUS_RD,
input wire BUS_WR,
output reg [7:0] BUS_DATA_OUT,
output wire [OUTPUTS-1:0] CMD_CLK_OUT,
input wire CMD_CLK_IN,
input wire CMD_EXT_START_FLAG,
output wire CMD_EXT_START_ENABLE,
output wire [OUTPUTS-1:0] CMD_DATA,
output reg CMD_READY,
output reg CMD_START_FLAG
);
localparam VERSION = 1;
wire SOFT_RST; //0
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
// reset sync
// when write to addr = 0 then reset
reg RST_FF, RST_FF2, BUS_RST_FF, BUS_RST_FF2;
always @(posedge BUS_CLK) begin
RST_FF <= SOFT_RST;
RST_FF2 <= RST_FF;
BUS_RST_FF <= BUS_RST;
BUS_RST_FF2 <= BUS_RST_FF;
end
wire SOFT_RST_FLAG;
assign SOFT_RST_FLAG = ~RST_FF2 & RST_FF;
wire BUS_RST_FLAG;
assign BUS_RST_FLAG = BUS_RST_FF2 & ~BUS_RST_FF; // trailing edge
wire RST;
assign RST = BUS_RST_FLAG | SOFT_RST_FLAG;
wire RST_CMD_CLK;
flag_domain_crossing cmd_rst_flag_domain_crossing (
.CLK_A(BUS_CLK),
.CLK_B(CMD_CLK_IN),
.FLAG_IN_CLK_A(RST),
.FLAG_OUT_CLK_B(RST_CMD_CLK)
);
wire START; // 1
assign START = (BUS_ADD==1 && BUS_WR);
// start sync
// when write to addr = 1 then send command
reg START_FF, START_FF2;
always @(posedge BUS_CLK) begin
START_FF <= START;
START_FF2 <= START_FF;
end
wire START_FLAG;
assign START_FLAG = ~START_FF2 & START_FF;
wire start_sync;
flag_domain_crossing cmd_start_flag_domain_crossing (
.CLK_A(BUS_CLK),
.CLK_B(CMD_CLK_IN),
.FLAG_IN_CLK_A(START_FLAG),
.FLAG_OUT_CLK_B(start_sync)
);
reg [0:0] CONF_FINISH; // 1
wire CONF_EN_EXT_START, CONF_DIS_CLOCK_GATE, CONF_DIS_CMD_PULSE; // 2
wire [1:0] CONF_OUTPUT_MODE; // 2 Mode == 0: posedge, 1: negedge, 2: Manchester Code according to IEEE 802.3, 3: Manchester Code according to G.E. Thomas aka Biphase-L or Manchester-II
wire [15:0] CONF_CMD_SIZE; // 3 - 4
wire [31:0] CONF_REPEAT_COUNT; // 5 - 8
wire [15:0] CONF_START_REPEAT; // 9 - 10
wire [15:0] CONF_STOP_REPEAT; // 11 - 12
wire [7:0] CONF_OUTPUT_ENABLE; //13
// ATTENTION:
// -(CONF_CMD_SIZE - CONF_START_REPEAT - CONF_STOP_REPEAT) must be greater than or equal to 2
// - CONF_START_REPEAT must be greater than or equal to 2
// - CONF_STOP_REPEAT must be greater than or equal to 2
reg [7:0] status_regs [15:0];
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 8'b0000_0000;
status_regs[3] <= 0;
status_regs[4] <= 0;
status_regs[5] <= 8'd1; // CONF_REPEAT_COUNT, repeat once by default
status_regs[6] <= 0;
status_regs[7] <= 0;
status_regs[8] <= 0;
status_regs[9] <= 0; // CONF_START_REPEAT
status_regs[10] <= 0;
status_regs[11] <= 0;// CONF_STOP_REPEAT
status_regs[12] <= 0;
status_regs[13] <= 8'hff; //OUTPUT_EN
status_regs[14] <= 0;
status_regs[15] <= 0;
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
assign CONF_CMD_SIZE = {status_regs[4], status_regs[3]};
assign CONF_REPEAT_COUNT = {status_regs[8], status_regs[7], status_regs[6], status_regs[5]};
assign CONF_START_REPEAT = {status_regs[10], status_regs[9]};
assign CONF_STOP_REPEAT = {status_regs[12], status_regs[11]};
assign CONF_OUTPUT_ENABLE = status_regs[13];
assign CONF_DIS_CMD_PULSE = status_regs[2][4];
assign CONF_DIS_CLOCK_GATE = status_regs[2][3]; // no clock domain crossing needed
assign CONF_OUTPUT_MODE = status_regs[2][2:1]; // no clock domain crossing needed
assign CONF_EN_EXT_START = status_regs[2][0];
wire CONF_DIS_CMD_PULSE_CMD_CLK;
three_stage_synchronizer conf_dis_cmd_pulse_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_DIS_CMD_PULSE),
.OUT(CONF_DIS_CMD_PULSE_CMD_CLK)
);
three_stage_synchronizer conf_en_ext_start_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_EN_EXT_START),
.OUT(CMD_EXT_START_ENABLE)
);
wire [15:0] CONF_CMD_SIZE_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) cmd_size_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_CMD_SIZE),
.OUT(CONF_CMD_SIZE_CMD_CLK)
);
wire [31:0] CONF_REPEAT_COUNT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(32)
) repeat_cnt_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_REPEAT_COUNT),
.OUT(CONF_REPEAT_COUNT_CMD_CLK)
);
wire [15:0] CONF_START_REPEAT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) start_repeat_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_START_REPEAT),
.OUT(CONF_START_REPEAT_CMD_CLK)
);
wire [15:0] CONF_STOP_REPEAT_CMD_CLK;
three_stage_synchronizer #(
.WIDTH(16)
) stop_repeat_sync (
.CLK(CMD_CLK_IN),
.IN(CONF_STOP_REPEAT),
.OUT(CONF_STOP_REPEAT_CMD_CLK)
);
(* RAM_STYLE="{BLOCK}" *)
reg [7:0] cmd_mem [CMD_MEM_SIZE-1:0];
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
if(BUS_ADD == 0)
BUS_DATA_OUT <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT <= {7'b0, CONF_FINISH};
else if(BUS_ADD < 16)
BUS_DATA_OUT <= status_regs[BUS_ADD[3:0]];
else if(BUS_ADD < CMD_MEM_SIZE)
BUS_DATA_OUT <= cmd_mem[BUS_ADD[10:0]-16];
else
BUS_DATA_OUT <= 8'b0;
end
end
always @ (posedge BUS_CLK) begin
if (BUS_WR && BUS_ADD >= 16)
cmd_mem[BUS_ADD[10:0]-16] <= BUS_DATA_IN;
end
reg [7:0] CMD_MEM_DATA;
reg [10:0] CMD_MEM_ADD;
always @(posedge CMD_CLK_IN)
CMD_MEM_DATA <= cmd_mem[CMD_MEM_ADD];
wire ext_send_cmd;
assign ext_send_cmd = (CMD_EXT_START_FLAG & CMD_EXT_START_ENABLE);
wire send_cmd;
assign send_cmd = start_sync | ext_send_cmd;
localparam WAIT = 1, SEND = 2;
reg [15:0] cnt;
reg [31:0] repeat_cnt;
reg [2:0] state, next_state;
always @ (posedge CMD_CLK_IN)
if (RST_CMD_CLK)
state <= WAIT;
else
state <= next_state;
reg END_SEQ_REP_NEXT, END_SEQ_REP;
always @ (*) begin
if(repeat_cnt < CONF_REPEAT_COUNT_CMD_CLK && cnt == CONF_CMD_SIZE_CMD_CLK-1-CONF_STOP_REPEAT_CMD_CLK && !END_SEQ_REP)
END_SEQ_REP_NEXT = 1;
else
END_SEQ_REP_NEXT = 0;
end
always @ (posedge CMD_CLK_IN)
END_SEQ_REP <= END_SEQ_REP_NEXT;
always @ (*) begin
case(state)
WAIT : if(send_cmd)
next_state = SEND;
else
next_state = WAIT;
SEND : if(cnt == CONF_CMD_SIZE_CMD_CLK && repeat_cnt==CONF_REPEAT_COUNT_CMD_CLK)
next_state = WAIT;
else
next_state = SEND;
default : next_state = WAIT;
endcase
end
always @ (posedge CMD_CLK_IN) begin
if (RST_CMD_CLK)
cnt <= 0;
else if(state != next_state)
cnt <= 0;
else if(cnt == CONF_CMD_SIZE_CMD_CLK || END_SEQ_REP) begin
if(CONF_START_REPEAT_CMD_CLK != 0)
cnt <= CONF_START_REPEAT_CMD_CLK+1;
else
cnt <= 1;
end
else
cnt <= cnt + 1;
end
always @ (posedge CMD_CLK_IN) begin
if (send_cmd || RST_CMD_CLK)
repeat_cnt <= 1;
else if(state == SEND && (cnt == CONF_CMD_SIZE_CMD_CLK || END_SEQ_REP) && repeat_cnt != 0)
repeat_cnt <= repeat_cnt + 1;
end
always @ (*) begin
if(state != next_state && next_state == SEND)
CMD_MEM_ADD = 0;
else if(state == SEND)
if(cnt == CONF_CMD_SIZE_CMD_CLK-1 || END_SEQ_REP_NEXT) begin
if(CONF_START_REPEAT_CMD_CLK != 0)
CMD_MEM_ADD = (CONF_START_REPEAT_CMD_CLK)/8;
else
CMD_MEM_ADD = 0;
end
else begin
if(END_SEQ_REP)
CMD_MEM_ADD = (CONF_START_REPEAT_CMD_CLK+1)/8;
else
CMD_MEM_ADD = (cnt+1)/8;
end
else
CMD_MEM_ADD = 0; //no latch
end
reg [7:0] send_word;
always @ (posedge CMD_CLK_IN) begin
if(RST_CMD_CLK)
send_word <= 0;
else if(state == SEND) begin
if(next_state == WAIT)
send_word <= 0; // by default set to output to zero (this is strange -> bug of FEI4?)
else if(cnt == CONF_CMD_SIZE_CMD_CLK || END_SEQ_REP)
send_word <= CMD_MEM_DATA;
else if(cnt %8 == 0)
send_word <= CMD_MEM_DATA;
//else
// send_word[7:0] <= {send_word[6:0], 1'b0};
end
end
wire cmd_data_ser;
assign cmd_data_ser = send_word[7-((cnt-1)%8)];
reg [7:0] cmd_data_neg;
reg [7:0] cmd_data_pos;
always @ (negedge CMD_CLK_IN)
cmd_data_neg <= {8{cmd_data_ser}} & CONF_OUTPUT_ENABLE;
always @ (posedge CMD_CLK_IN)
cmd_data_pos <= {8{cmd_data_ser}} & CONF_OUTPUT_ENABLE;
genvar k;
generate
for (k = 0; k < OUTPUTS; k = k + 1) begin: gen
ODDR MANCHESTER_CODE_INST (
.Q(CMD_DATA[k]),
.C(CMD_CLK_IN),
.CE(1'b1),
.D1((CONF_OUTPUT_MODE == 2'b00) ? cmd_data_pos[k] : ((CONF_OUTPUT_MODE == 2'b01) ? cmd_data_neg[k] : ((CONF_OUTPUT_MODE == 2'b10) ? ~cmd_data_pos[k] : cmd_data_pos[k]))),
.D2((CONF_OUTPUT_MODE == 2'b00) ? cmd_data_pos[k] : ((CONF_OUTPUT_MODE == 2'b01) ? cmd_data_neg[k] : ((CONF_OUTPUT_MODE == 2'b10) ? cmd_data_pos[k] : ~cmd_data_pos[k]))),
.R(1'b0),
.S(1'b0)
);
ODDR CMD_CLK_FORWARDING_INST (
.Q(CMD_CLK_OUT[k]),
.C(CMD_CLK_IN),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R(CONF_DIS_CLOCK_GATE),
.S(1'b0)
);
end
endgenerate
// command start flag
always @ (posedge CMD_CLK_IN)
if (state == SEND && cnt == (CONF_START_REPEAT_CMD_CLK + 1) && CONF_DIS_CMD_PULSE_CMD_CLK == 1'b0)
CMD_START_FLAG <= 1'b1;
else
CMD_START_FLAG <= 1'b0;
// ready signal
always @ (posedge CMD_CLK_IN)
if (state == WAIT)
CMD_READY <= 1'b1;
else
CMD_READY <= 1'b0;
// ready readout sync
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync(.clk_in(CMD_CLK_IN), .pulse_in(CMD_READY), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_FINISH <= 1;
else if(START)
CONF_FINISH <= 0;
else if(DONE_SYNC)
CONF_FINISH <= 1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_M_V
`define SKY130_FD_SC_LP__NOR2_M_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_m (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_m (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_SYMBOL_V
`define SKY130_FD_SC_LP__ISO0N_SYMBOL_V
/**
* iso0n: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 VPWR ;
supply0 KAGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//
// --------------------------------------------------------
// Bug Description:
//
// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
// input to the flop does not propagate to the output
// signal entry_vld[0] correctly. The value that propagates
// is the new value of dvld[0] not the one just before the
// posedge of gclk_vld[0].
// --------------------------------------------------------
// Define to see the bug with test failing with gated clock 'gclk_vld'
// Comment out the define to see the test passing with ungated clock 'clk'
`define GATED_CLK_TESTCASE 1
// A side effect of the problem is this warning, disabled by default
//verilator lint_on IMPERFECTSCH
// Test Bench
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
wire [7:0] dvld = crc[7:0];
wire [7:0] ff_en_e1 = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] entry_vld; // From test of Test.v
wire [7:0] ff_en_vld; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_en_vld (ff_en_vld[7:0]),
.entry_vld (entry_vld[7:0]),
// Inputs
.clk (clk),
.dvld (dvld[7:0]),
.ff_en_e1 (ff_en_e1[7:0]));
reg err_code;
reg ffq_clk_active;
reg [7:0] prv_dvld;
initial begin
err_code = 0;
ffq_clk_active = 0;
end
always @ (posedge clk) begin
prv_dvld = test.dvld;
end
always @ (negedge test.ff_entry_dvld_0.clk) begin
ffq_clk_active = 1;
if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
$display ("----");
$stop;
end
else if (err_code) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
$display ("----");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module llq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on COMBDLY */
assign q = qr;
endmodule
module ffq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
always @(posedge clk)
qr <= d;
assign q = qr;
endmodule
// DUT module
module Test (/*AUTOARG*/
// Outputs
ff_en_vld, entry_vld,
// Inputs
clk, dvld, ff_en_e1
);
input clk;
input [7:0] dvld;
input [7:0] ff_en_e1;
output [7:0] ff_en_vld;
output wire [7:0] entry_vld;
wire [7:0] gclk_vld;
wire [7:0] ff_en_vld /*verilator clock_enable*/;
reg [7:0] flop_en_vld;
always @(posedge clk) flop_en_vld <= ff_en_e1;
// clock gating
`ifdef GATED_CLK_TESTCASE
assign gclk_vld = {8{clk}} & ff_en_vld;
`else
assign gclk_vld = {8{clk}};
`endif
// latch for avoiding glitch on the clock gating control
llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
// flops that use the gated clock signal
ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O2111AI_TB_V
`define SKY130_FD_SC_LS__O2111AI_TB_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o2111ai.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg D1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
D1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 D1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 C1 = 1'b1;
#280 D1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 C1 = 1'b0;
#460 D1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 D1 = 1'b1;
#660 C1 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 D1 = 1'bx;
#840 C1 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__o2111ai dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .D1(D1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O2111AI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_1_V
`define SKY130_FD_SC_HD__OR4BB_1_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4bb_1 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or4bb_1 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_1_V
|
`timescale 1ns/10ps
module tb_spi_mode;
reg sys_clk = 1'b0;
reg sys_rst = 1'b0;
reg sdemu_sd_clk = 1'b0;
reg flipsyfat_sdemu_cmd_t_i = 1'b1;
reg [3:0] flipsyfat_sdemu_sd_dat_i = 4'b1111;
initial forever #2 sys_clk = ~sys_clk;
reg [31:0] n;
initial begin
$dumpfile("tb_spi_mode.vcd");
$dumpvars;
#10 sys_rst = 1'b1;
#100 sys_rst = 1'b0;
#1000
for (n=0; n<10; n++)
spi_byte(8'hFF);
#1000
spi_cs(1'b0);
spi_byte(8'hff);
spi_byte(8'hff);
spi_byte(8'h40);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h95);
for (n=0; n<4; n++)
spi_byte(8'hFF);
spi_byte(8'h48);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h02);
spi_byte(8'haa);
spi_byte(8'h87);
for (n=0; n<8; n++)
spi_byte(8'hFF);
spi_byte(8'h77);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<5; n++)
spi_byte(8'hFF);
spi_byte(8'h69);
spi_byte(8'h40);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<5; n++)
spi_byte(8'hFF);
spi_byte(8'h7a);
spi_byte(8'h40);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<7; n++)
spi_byte(8'hFF);
spi_cs(1'b1);
spi_byte(8'hFF);
#1000;
for (n=0; n<10; n++)
spi_byte(8'hFF);
spi_cs(1'b0);
for (n=0; n<2; n++)
spi_byte(8'hFF);
spi_byte(8'h40);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h95);
for (n=0; n<4; n++)
spi_byte(8'hFF);
spi_byte(8'h48);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h02);
spi_byte(8'haa);
spi_byte(8'h87);
for (n=0; n<8; n++)
spi_byte(8'hFF);
spi_byte(8'h77);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<5; n++)
spi_byte(8'hFF);
spi_byte(8'h69);
spi_byte(8'h40);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<5; n++)
spi_byte(8'hFF);
spi_byte(8'h77);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<5; n++)
spi_byte(8'hFF);
spi_byte(8'h69);
spi_byte(8'h40);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<5; n++)
spi_byte(8'hFF);
spi_byte(8'h50);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h02);
spi_byte(8'h00);
for (n=0; n<3; n++)
spi_byte(8'hFF);
spi_cs(1'b1);
spi_byte(8'hFF);
#1000;
spi_cs(1'b0);
for (n=0; n<2; n++)
spi_byte(8'hFF);
spi_byte(8'h51);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
spi_byte(8'h00);
for (n=0; n<20; n++)
spi_byte(8'hFF);
#1000 $finish;
end
task spi_cs;
input state;
begin
flipsyfat_sdemu_sd_dat_i[3] = state;
end
endtask
task spi_byte;
input [7:0] mosibyte;
reg [7:0] misobyte;
reg [7:0] misobyte_next;
reg [7:0] i;
begin
misobyte_next = 0;
for (i = 0; i < 8; i++) begin
flipsyfat_sdemu_cmd_t_i = mosibyte[7-i];
#12 sdemu_sd_clk = 1;
#12 sdemu_sd_clk = 0;
misobyte_next[7-i] = flipsyfat_sdemu_sd_dat_o[0];
end
#100
misobyte = misobyte_next;
$display("SPI %x -> %x", mosibyte, misobyte);
end
endtask
wire flipsyfat_sdemu_cmd_t_o;
wire flipsyfat_sdemu_cmd_t_oe;
wire flipsyfat_sdemu_sd_cmd_t;
wire [3:0] flipsyfat_sdemu_sd_dat_o;
wire [3:0] flipsyfat_sdemu_sd_dat_t;
wire [6:0] flipsyfat_sdemu_internal_rd_port_adr;
wire [31:0] flipsyfat_sdemu_internal_rd_port_dat_r;
wire [6:0] flipsyfat_sdemu_internal_wr_port_adr;
wire [31:0] flipsyfat_sdemu_internal_wr_port_dat_r;
wire flipsyfat_sdemu_internal_wr_port_we;
wire [31:0] flipsyfat_sdemu_internal_wr_port_dat_w;
wire [3:0] flipsyfat_sdemu_card_state;
wire flipsyfat_sdemu_mode_4bit;
wire flipsyfat_sdemu_mode_spi;
wire flipsyfat_sdemu_mode_crc_disable;
wire flipsyfat_sdemu_spi_sel;
wire [47:0] flipsyfat_sdemu_cmd_in;
wire [5:0] flipsyfat_sdemu_cmd_in_last;
wire flipsyfat_sdemu_cmd_in_crc_good;
wire flipsyfat_sdemu_cmd_in_act;
wire flipsyfat_sdemu_data_in_act;
wire flipsyfat_sdemu_data_in_busy;
wire flipsyfat_sdemu_data_in_another;
wire flipsyfat_sdemu_data_in_stop;
wire flipsyfat_sdemu_data_in_done;
wire flipsyfat_sdemu_data_in_crc_good;
wire [135:0] flipsyfat_sdemu_resp_out;
wire [3:0] flipsyfat_sdemu_resp_type;
wire flipsyfat_sdemu_resp_busy;
wire flipsyfat_sdemu_resp_act;
wire flipsyfat_sdemu_resp_done;
wire [511:0] flipsyfat_sdemu_data_out_reg;
wire flipsyfat_sdemu_data_out_src;
wire [9:0] flipsyfat_sdemu_data_out_len;
wire flipsyfat_sdemu_data_out_busy;
wire flipsyfat_sdemu_data_out_act;
wire flipsyfat_sdemu_data_out_stop;
wire flipsyfat_sdemu_data_out_done;
wire [5:0] flipsyfat_sdemu_cmd_in_cmd;
wire flipsyfat_sdemu_info_card_desel;
reg flipsyfat_sdemu_err_op_out_range = 1'd0;
wire flipsyfat_sdemu_err_unhandled_cmd;
wire flipsyfat_sdemu_err_cmd_crc;
wire [10:0] flipsyfat_sdemu_phy_idc;
wire [10:0] flipsyfat_sdemu_phy_odc;
wire [6:0] flipsyfat_sdemu_phy_istate;
wire [6:0] flipsyfat_sdemu_phy_ostate;
wire [7:0] flipsyfat_sdemu_phy_spi_cnt;
wire [6:0] flipsyfat_sdemu_link_state;
wire [15:0] flipsyfat_sdemu_link_ddc;
wire [15:0] flipsyfat_sdemu_link_dc;
wire flipsyfat_sdemu_block_read_act;
wire [31:0] flipsyfat_sdemu_block_read_addr;
wire [31:0] flipsyfat_sdemu_block_read_num;
wire flipsyfat_sdemu_block_read_stop;
wire flipsyfat_sdemu_block_write_act;
wire [31:0] flipsyfat_sdemu_block_write_addr;
wire [31:0] flipsyfat_sdemu_block_write_num;
wire [22:0] flipsyfat_sdemu_block_preerase_num;
wire [31:0] flipsyfat_sdemu_block_erase_start;
wire [31:0] flipsyfat_sdemu_block_erase_end;
reg flipsyfat_sdemu_block_read_go = 1'b0;
reg flipsyfat_sdemu_block_write_done = 1'b0;
reg [31:0] rd_buffer[0:127];
reg [6:0] memadr_5;
always @(posedge sdemu_sd_clk) begin
memadr_5 <= flipsyfat_sdemu_internal_rd_port_adr;
end
assign flipsyfat_sdemu_internal_rd_port_dat_r = rd_buffer[memadr_5];
reg [31:0] wr_buffer[0:127];
reg [6:0] memadr_7;
always @(posedge sdemu_sd_clk) begin
if (flipsyfat_sdemu_internal_wr_port_we)
wr_buffer[flipsyfat_sdemu_internal_wr_port_adr] <= flipsyfat_sdemu_internal_wr_port_dat_w;
memadr_7 <= flipsyfat_sdemu_internal_wr_port_adr;
end
assign flipsyfat_sdemu_internal_wr_port_dat_r = wr_buffer[memadr_7];
sd_phy sd_phy(
.bram_rd_sd_q(flipsyfat_sdemu_internal_rd_port_dat_r),
.bram_wr_sd_q(flipsyfat_sdemu_internal_wr_port_dat_r),
.card_state(flipsyfat_sdemu_card_state),
.clk_50(sys_clk),
.data_in_act(flipsyfat_sdemu_data_in_act),
.data_in_another(flipsyfat_sdemu_data_in_another),
.data_in_stop(flipsyfat_sdemu_data_in_stop),
.data_out_act(flipsyfat_sdemu_data_out_act),
.data_out_len(flipsyfat_sdemu_data_out_len),
.data_out_reg(flipsyfat_sdemu_data_out_reg),
.data_out_src(flipsyfat_sdemu_data_out_src),
.data_out_stop(flipsyfat_sdemu_data_out_stop),
.mode_4bit(flipsyfat_sdemu_mode_4bit),
.mode_crc_disable(flipsyfat_sdemu_mode_crc_disable),
.mode_spi(flipsyfat_sdemu_mode_spi),
.reset_n((~sys_rst)),
.resp_act(flipsyfat_sdemu_resp_act),
.resp_busy(flipsyfat_sdemu_resp_busy),
.resp_out(flipsyfat_sdemu_resp_out),
.resp_type(flipsyfat_sdemu_resp_type),
.sd_clk(sdemu_sd_clk),
.sd_cmd_i(flipsyfat_sdemu_cmd_t_i),
.sd_dat_i(flipsyfat_sdemu_sd_dat_i),
.bram_rd_sd_addr(flipsyfat_sdemu_internal_rd_port_adr),
.bram_wr_sd_addr(flipsyfat_sdemu_internal_wr_port_adr),
.bram_wr_sd_data(flipsyfat_sdemu_internal_wr_port_dat_w),
.bram_wr_sd_wren(flipsyfat_sdemu_internal_wr_port_we),
.cmd_in(flipsyfat_sdemu_cmd_in),
.cmd_in_act(flipsyfat_sdemu_cmd_in_act),
.cmd_in_crc_good(flipsyfat_sdemu_cmd_in_crc_good),
.data_in_busy(flipsyfat_sdemu_data_in_busy),
.data_in_crc_good(flipsyfat_sdemu_data_in_crc_good),
.data_in_done(flipsyfat_sdemu_data_in_done),
.data_out_busy(flipsyfat_sdemu_data_out_busy),
.data_out_done(flipsyfat_sdemu_data_out_done),
.idc(flipsyfat_sdemu_phy_idc),
.istate(flipsyfat_sdemu_phy_istate),
.odc(flipsyfat_sdemu_phy_odc),
.ostate(flipsyfat_sdemu_phy_ostate),
.resp_done(flipsyfat_sdemu_resp_done),
.sd_cmd_o(flipsyfat_sdemu_cmd_t_o),
.sd_cmd_t(flipsyfat_sdemu_sd_cmd_t),
.sd_dat_o(flipsyfat_sdemu_sd_dat_o),
.sd_dat_t(flipsyfat_sdemu_sd_dat_t),
.spi_cnt(flipsyfat_sdemu_phy_spi_cnt),
.spi_sel(flipsyfat_sdemu_spi_sel)
);
sd_link sd_link(
.block_read_go(flipsyfat_sdemu_block_read_go),
.block_write_done(flipsyfat_sdemu_block_write_done),
.clk_50(sys_clk),
.opt_enable_hs(1'd1),
.phy_cmd_in(flipsyfat_sdemu_cmd_in),
.phy_cmd_in_act(flipsyfat_sdemu_cmd_in_act),
.phy_cmd_in_crc_good(flipsyfat_sdemu_cmd_in_crc_good),
.phy_data_in_busy(flipsyfat_sdemu_data_in_busy),
.phy_data_in_crc_good(flipsyfat_sdemu_data_in_crc_good),
.phy_data_in_done(flipsyfat_sdemu_data_in_done),
.phy_data_out_busy(flipsyfat_sdemu_data_out_busy),
.phy_data_out_done(flipsyfat_sdemu_data_out_done),
.phy_resp_done(flipsyfat_sdemu_resp_done),
.phy_spi_sel(flipsyfat_sdemu_spi_sel),
.reset_n((~sys_rst)),
.block_erase_end(flipsyfat_sdemu_block_erase_end),
.block_erase_start(flipsyfat_sdemu_block_erase_start),
.block_preerase_num(flipsyfat_sdemu_block_preerase_num),
.block_read_act(flipsyfat_sdemu_block_read_act),
.block_read_addr(flipsyfat_sdemu_block_read_addr),
.block_read_num(flipsyfat_sdemu_block_read_num),
.block_read_stop(flipsyfat_sdemu_block_read_stop),
.block_write_act(flipsyfat_sdemu_block_write_act),
.block_write_addr(flipsyfat_sdemu_block_write_addr),
.block_write_num(flipsyfat_sdemu_block_write_num),
.cmd_in_cmd(flipsyfat_sdemu_cmd_in_cmd),
.cmd_in_last(flipsyfat_sdemu_cmd_in_last),
.dc(flipsyfat_sdemu_link_dc),
.ddc(flipsyfat_sdemu_link_ddc),
.err_cmd_crc(flipsyfat_sdemu_err_cmd_crc),
.err_unhandled_cmd(flipsyfat_sdemu_err_unhandled_cmd),
.info_card_desel(flipsyfat_sdemu_info_card_desel),
.link_card_state(flipsyfat_sdemu_card_state),
.phy_data_in_act(flipsyfat_sdemu_data_in_act),
.phy_data_in_another(flipsyfat_sdemu_data_in_another),
.phy_data_in_stop(flipsyfat_sdemu_data_in_stop),
.phy_data_out_act(flipsyfat_sdemu_data_out_act),
.phy_data_out_len(flipsyfat_sdemu_data_out_len),
.phy_data_out_reg(flipsyfat_sdemu_data_out_reg),
.phy_data_out_src(flipsyfat_sdemu_data_out_src),
.phy_data_out_stop(flipsyfat_sdemu_data_out_stop),
.phy_mode_4bit(flipsyfat_sdemu_mode_4bit),
.phy_mode_crc_disable(flipsyfat_sdemu_mode_crc_disable),
.phy_mode_spi(flipsyfat_sdemu_mode_spi),
.phy_resp_act(flipsyfat_sdemu_resp_act),
.phy_resp_busy(flipsyfat_sdemu_resp_busy),
.phy_resp_out(flipsyfat_sdemu_resp_out),
.phy_resp_type(flipsyfat_sdemu_resp_type),
.state(flipsyfat_sdemu_link_state)
);
// Trivial sd-mgr layer
initial for (n = 0; n < 128; n++) rd_buffer[n] = 32'hABCD4567;
always @(posedge flipsyfat_sdemu_block_read_act) begin
$display("Block Read");
#2000
flipsyfat_sdemu_block_read_go = 1;
#40
flipsyfat_sdemu_block_read_go = 0;
end
always @(posedge flipsyfat_sdemu_block_write_act) begin
$display("Block Write");
#2000
flipsyfat_sdemu_block_write_done = 1;
#40
flipsyfat_sdemu_block_write_done = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FAHCON_PP_SYMBOL_V
`define SKY130_FD_SC_HD__FAHCON_PP_SYMBOL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__fahcon (
//# {{data|Data Signals}}
input A ,
input B ,
input CI ,
output COUT_N,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__FAHCON_PP_SYMBOL_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxr_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXR Engine (Classic) takes a single stream of TLP
// packets and provides the request packets on the RXR Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "tlp.vh"
module rxr_engine_classic
#(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXR_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXR
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
/*AUTOWIRE*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// Cycle index in the SOP register when enable is raised
// Computation can begin when the last DW of the header is recieved.
localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
// The computation cycle must be at least one cycle before the address is enabled
localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_RESET_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +
C_PCI_DATA_WIDTH*(C_RX_ADDRDW1_CYCLE - C_RX_METADW0_CYCLE) +
`TLP_4DWHBIT_I;
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_MAX_ABLANK_WIDTH = 32;
localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
wire [63:0] wAddrFmt;
wire [63:0] wMetadata;
wire [`TLP_TYPE_W-1:0] wType;
wire [`TLP_LEN_W-1:0] wLength;
wire wAddrDW0Bit2;
wire wAddrDW1Bit2;
wire wAddrHiReset;
wire [31:0] wAddrMux[(`TLP_REQADDR_W / 32)-1:0];
wire [63:0] wAddr;
wire w4DWH;
wire wHasPayload;
wire [2:0] wHdrLength;
wire [2:0] wHdrLengthM1;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wEndFlag;
wire wEndFlag;
wire [C_OFFSET_WIDTH-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [3:0] wStartFlags;
wire wStartFlag;
wire _wStartFlag;
wire [clog2s(C_MAX_START_OFFSET)-1:0] wStartOffset;
wire wInsertBlank;
wire wRotateAddressField;
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
wire [63:0] wRxrMetadata;
wire wRxrDataValid;
wire wRxrDataReady; // Pinned High
wire wRxrDataEndFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire wRxrDataStartFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataStartOffset;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
reg rValid,_rValid;
reg rRST;
assign DONE_RXR_RST = ~rRST;
assign wAddrHiReset = ~RX_SR_DATA[C_RX_ADDRDW1_RESET_INDEX];
// Select Addr[31:0] from one of the two possible locations in the TLP based
// on header length (1 bit)
assign wRotateAddressField = w4DWH;
assign wAddrFmt = {wAddrMux[~wRotateAddressField],wAddrMux[wRotateAddressField]};
assign wAddrMux[0] = wAddr[31:0];
assign wAddrMux[1] = wAddr[63:32];
// Calculate the header length (start offset), and header length minus 1 (end offset)
assign wHdrLength = {w4DWH,~w4DWH,~w4DWH};
assign wHdrLengthM1 = {1'b0,1'b1,w4DWH};
// Determine if the TLP has an inserted blank before the payload
assign wInsertBlank = ((w4DWH & wAddrDW1Bit2) | (~w4DWH & ~wAddrDW0Bit2)) & (C_VENDOR == "ALTERA");
assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength;//RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
// Inputs
// Technically an input, but the trellis protocol specifies it must be held high at all times
assign wRxrDataReady = 1;
// Outputs
assign RXR_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXR_DATA_VALID = wRxrDataValid;
assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
assign RXR_DATA_END_OFFSET = wRxrDataEndOffset;
assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
assign RXR_DATA_START_OFFSET = wRxrDataStartOffset;
assign RXR_META_BAR_DECODED = 0;
assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];
assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];
assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};
assign RXR_META_TYPE = tlp_to_trellis_type({wRxrMetadata[`TLP_FMT_R],wRxrMetadata[`TLP_TYPE_R]});
assign RXR_META_ADDR = wRxrMetaAddr;
assign RXR_META_REQUESTER_ID = wRxrMetadata[`TLP_REQREQID_R];
assign RXR_META_TAG = wRxrMetadata[`TLP_REQTAG_R];
assign RXR_META_FDWBE = wRxrMetadata[`TLP_REQFBE_R];
assign RXR_META_LDWBE = wRxrMetadata[`TLP_REQLBE_R];
assign RXR_META_EP = wRxrMetadata[`TLP_EP_R];
assign _wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES];
assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
end else begin // 256
assign wStartFlags[3] = 0;
assign wStartFlags[2] = 0;
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(rRST) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset[C_OFFSET_WIDTH-1:0])
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
end else begin
register
#(
// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxrDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXR_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxrDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
end
endgenerate
register
#(
// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_DW0_register
(
// Outputs
.RD_DATA (wMetadata[31:0]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW1_register
(// Outputs
.RD_DATA (wMetadata[63:32]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW0_register
(// Outputs
.RD_DATA (wAddr[31:0]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_ADDRDW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW0_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW1_register
(// Outputs
.RD_DATA (wAddr[63:32]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_ADDRDW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
.RST_IN (wAddrHiReset & wRxSrSop[C_RX_ADDRDW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_4DWH_register
(// Outputs
.RD_DATA ({wHasPayload,w4DWH}),
// Inputs
.WR_DATA (RX_SR_DATA[`TLP_FMT_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +: 2]),
.WR_EN (wRxSrSop[`TLP_4DWHBIT_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_TYPE_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_type_register
(// Outputs
.RD_DATA (wType),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_TYPE_I/* + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES*/) +: `TLP_TYPE_W]),
.WR_EN (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH/* + C_RX_INPUT_STAGES*/]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_LEN_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_length_register
(// Outputs
.RD_DATA (wLength),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_LEN_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
.WR_EN (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW0_bit_2_register
(// Outputs
.RD_DATA (wAddrDW0Bit2),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
.WR_EN (wRxSrSop[(`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW1_bit_2_register
(// Outputs
.RD_DATA (wAddrDW1Bit2),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
.WR_EN (wRxSrSop[(`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
start_flag_register
(// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`TLP_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxrMetadata,wRxrMetaAddr,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset}),
.RD_DATA_VALID (wRxrDataValid),
// Inputs
.WR_DATA ({wMetadata, wAddrFmt, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
.WR_DATA_VALID (rValid & RX_SR_VALID[C_TOTAL_STAGES-C_RX_OUTPUT_STAGES]),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_REQ)),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common")
// End:
|
/*
:Project
FPGA-Imaging-Library
:Design
FrameController
:Function
For controlling a BlockRAM from xilinx.
Give the first output after ram_read_latency cycles while the input enable.
:Module
Main module
:Version
1.0
:Modified
2015-05-12
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module FrameController(
clk,
rst_n,
in_enable,
in_data,
out_ready,
out_data,
ram_addr);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter work_mode = 0;
/*
::description
This module's WR mode.
::range
0 for Write, 1 for Read
*/
parameter wr_mode = 0;
/*
::description
Data bit width.
*/
parameter data_width = 8;
/*
::description
Width of image.
::range
1 - 4096
*/
parameter im_width = 320;
/*
::description
Height of image.
::range
1 - 4096
*/
parameter im_height = 240;
/*
::description
Address bit width of a ram for storing this image.
::range
Depend on im_width and im_height.
*/
parameter addr_width = 17;
/*
::description
RL of RAM, in xilinx 7-series device, it is 2.
::range
0 - 15, Depend on your using ram.
*/
parameter ram_read_latency = 2;
/*
::description
The first row you want to storing, used for eliminating offset.
::range
Depend on your input offset.
*/
parameter row_init = 0;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Input data enable, in pipeline mode, it works as another rst_n, in req-ack mode, only it is high will in_data can be really changes.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [data_width - 1 : 0] in_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output[data_width - 1 : 0] out_data;
/*
::description
Address for ram.
*/
output[addr_width - 1 : 0] ram_addr;
reg[addr_width - 1 : 0] reg_ram_addr;
reg[3 : 0] con_ready;
assign ram_addr = reg_ram_addr;
assign out_data = out_ready ? in_data : 0;
generate
if(wr_mode == 0) begin
if(work_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_ram_addr <= row_init * im_width;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end else begin
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
reg_ram_addr <= row_init * im_width - 1;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end
assign out_ready = ~rst_n || ~in_enable ? 0 : 1;
end else begin
if(work_mode == 0) begin
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
reg_ram_addr <= 0;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end else begin
always @(posedge in_enable or negedge rst_n) begin
if(~rst_n)
reg_ram_addr <= 0 - 1;
else if(reg_ram_addr == im_width * im_height - 1)
reg_ram_addr <= 0;
else
reg_ram_addr <= reg_ram_addr + 1;
end
end
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_ready <= 0;
else if (con_ready == ram_read_latency)
con_ready <= con_ready;
else
con_ready <= con_ready + 1;
end
assign out_ready = con_ready == ram_read_latency ? 1 : 0;
end
endgenerate
endmodule |
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_w the_niosii_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_r the_niosii_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosii_jtag_uart_0_scfifo_w the_niosii_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosii_jtag_uart_0_scfifo_r the_niosii_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosii_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosii_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_BLACKBOX_V
`define SKY130_FD_SC_LP__ISOBUFSRC_BLACKBOX_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__isobufsrc (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_lvds_in (
// data interface
rx_clk,
rx_data_in_p,
rx_data_in_n,
rx_data_p,
rx_data_n,
// delay-data interface
up_clk,
up_dld,
up_dwdata,
up_drdata,
// delay-cntrl interface
delay_clk,
delay_rst,
delay_locked);
// parameters
parameter BUFTYPE = 0;
parameter IODELAY_CTRL = 0;
parameter IODELAY_GROUP = "dev_if_delay_group";
localparam SERIES7 = 0;
localparam VIRTEX6 = 1;
// data interface
input rx_clk;
input rx_data_in_p;
input rx_data_in_n;
output rx_data_p;
output rx_data_n;
// delay-data interface
input up_clk;
input up_dld;
input [ 4:0] up_dwdata;
output [ 4:0] up_drdata;
// delay-cntrl interface
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg rx_data_n;
// internal signals
wire rx_data_n_s;
wire rx_data_ibuf_s;
wire rx_data_idelay_s;
// delay controller
generate
if (IODELAY_CTRL == 1) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYCTRL i_delay_ctrl (
.RST (delay_rst),
.REFCLK (delay_clk),
.RDY (delay_locked));
end else begin
assign delay_locked = 1'b1;
end
endgenerate
// receive data interface, ibuf -> idelay -> iddr
IBUFDS i_rx_data_ibuf (
.I (rx_data_in_p),
.IB (rx_data_in_n),
.O (rx_data_ibuf_s));
if (BUFTYPE == VIRTEX6) begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IODELAYE1 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("I"),
.HIGH_PERFORMANCE_MODE ("TRUE"),
.IDELAY_TYPE ("VAR_LOADABLE"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("FIXED"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.T (1'b1),
.CE (1'b0),
.INC (1'b0),
.CLKIN (1'b0),
.DATAIN (1'b0),
.ODATAIN (1'b0),
.CINVCTRL (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.RST (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end else begin
(* IODELAY_GROUP = IODELAY_GROUP *)
IDELAYE2 #(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("IDATAIN"),
.HIGH_PERFORMANCE_MODE ("FALSE"),
.IDELAY_TYPE ("VAR_LOAD"),
.IDELAY_VALUE (0),
.REFCLK_FREQUENCY (200.0),
.PIPE_SEL ("FALSE"),
.SIGNAL_PATTERN ("DATA"))
i_rx_data_idelay (
.CE (1'b0),
.INC (1'b0),
.DATAIN (1'b0),
.LDPIPEEN (1'b0),
.CINVCTRL (1'b0),
.REGRST (1'b0),
.C (up_clk),
.IDATAIN (rx_data_ibuf_s),
.DATAOUT (rx_data_idelay_s),
.LD (up_dld),
.CNTVALUEIN (up_dwdata),
.CNTVALUEOUT (up_drdata));
end
IDDR #(
.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("ASYNC"))
i_rx_data_iddr (
.CE (1'b1),
.R (1'b0),
.S (1'b0),
.C (rx_clk),
.D (rx_data_idelay_s),
.Q1 (rx_data_p),
.Q2 (rx_data_n_s));
always @(posedge rx_clk) begin
rx_data_n <= rx_data_n_s;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZE = 8;
integer cnt = 0;
logic [SIZE-1:0] vld_for;
logic vld_if = 1'b0;
logic vld_else = 1'b0;
genvar i;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if (cnt==SIZE) begin : if_cnt_finish
$write("*-* All Finished *-*\n");
$finish;
end : if_cnt_finish_bad
generate
for (i=0; i<SIZE; i=i+1) begin : generate_for
always @ (posedge clk)
if (cnt == i) vld_for[i] <= 1'b1;
end : generate_for_bad
endgenerate
generate
if (SIZE>0) begin : generate_if_if
always @ (posedge clk)
vld_if <= 1'b1;
end : generate_if_if_bad
else begin : generate_if_else
always @ (posedge clk)
vld_else <= 1'b1;
end : generate_if_else_bad
endgenerate
endmodule : t_bad
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 12:18:33 05/14/2010
// Design Name:
// Module Name: Clock_module_FRL
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description: generate clocks from 200MHz clock input.
// If Sora_FRL is used, only 133MHz for DDR2 module is needed
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Clock_module_FRL(
input clk200,
input rst,
output clk133,
output [4:0] locked_debug,
output unlocked_err
);
wire locked1, locked_pll;
wire clk176, clk200_pll;
assign unlocked_err = (~locked1) & (~locked_pll);
assign locked_debug = {1'b0, 1'b0, 1'b0, locked1, locked_pll};
PLL_200MI_200MO PLL_200MI_200MO_inst(
.CLKIN1_IN(clk200),
.RST_IN(rst),
.CLKOUT0_OUT(clk200_pll),
.LOCKED_OUT(locked_pll)
);
DCM_200MI_133MO_176MO DCM_200MI_133MO_176MO_inst(
.CLKIN_IN(clk200_pll),
.CLKDV_OUT(clk133),
.CLKFX_OUT(clk176),
.RST_IN(rst),
.LOCKED_OUT(locked1),
.CLK0_OUT()
);
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: BLK_MEM_GEN_v8_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_2 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_2 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_2 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_2 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_2 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_2
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_2 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_2 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_2 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_2 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_2 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_2 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_2 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_2 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_2 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_2
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_2 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_2
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_2
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_2
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (BLK_MEM_GEN_v8_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module BLK_MEM_GEN_v8_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module BLK_MEM_GEN_v8_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
BLK_MEM_GEN_v8_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
BLK_MEM_GEN_v8_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_2
#(parameter C_CORENAME = "blk_mem_gen_v8_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = ""
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (CLKA),
.RSTA (rsta_in),
.ENA (ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB),
.ENB (ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_2
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_2
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
BLK_MEM_GEN_v8_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 11/04/2007
This bursting read master is passed a word aligned address, length in bytes,
and a 'go' bit. The master will continue to post full length bursts until
the length register reaches a value less than a full burst. A single final
burst is then posted and when all the reads return the done bit will be asserted.
To use this master you must simply drive the control signals into this block,
and also read the data from the exposed read FIFO. To read from the exposed FIFO
use the 'user_read_buffer' signal to pop data from the FIFO 'user_buffer_data'.
The signal 'user_data_available' is asserted whenever data is available from the
exposed FIFO.
*/
// altera message_off 10230
module burst_read_master (
clk,
reset,
// control inputs and outputs
control_fixed_location,
control_read_base,
control_read_length,
control_go,
control_done,
control_early_done,
// user logic inputs and outputs
user_read_buffer,
user_buffer_data,
user_data_available,
// master inputs and outputs
master_address,
master_read,
master_byteenable,
master_readdata,
master_readdatavalid,
master_burstcount,
master_waitrequest
);
parameter DATAWIDTH = 32;
parameter MAXBURSTCOUNT = 4;
parameter BURSTCOUNTWIDTH = 3;
parameter BYTEENABLEWIDTH = 4;
parameter ADDRESSWIDTH = 32;
parameter FIFODEPTH = 32;
parameter FIFODEPTH_LOG2 = 5;
parameter FIFOUSEMEMORY = 1; // set to 0 to use LEs instead
input clk;
input reset;
// control inputs and outputs
input control_fixed_location;
input [ADDRESSWIDTH-1:0] control_read_base;
input [ADDRESSWIDTH-1:0] control_read_length;
input control_go;
output wire control_done;
output wire control_early_done; // don't use this unless you know what you are doing, it's going to fire when the last read is posted, not when the last data returns!
// user logic inputs and outputs
input user_read_buffer;
output wire [DATAWIDTH-1:0] user_buffer_data;
output wire user_data_available;
// master inputs and outputs
input master_waitrequest;
input master_readdatavalid;
input [DATAWIDTH-1:0] master_readdata;
output wire [ADDRESSWIDTH-1:0] master_address;
output wire master_read;
output wire [BYTEENABLEWIDTH-1:0] master_byteenable;
output wire [BURSTCOUNTWIDTH-1:0] master_burstcount;
// internal control signals
reg control_fixed_location_d1;
wire fifo_empty;
reg [ADDRESSWIDTH-1:0] address;
reg [ADDRESSWIDTH-1:0] length;
reg [FIFODEPTH_LOG2-1:0] reads_pending;
wire increment_address;
wire [BURSTCOUNTWIDTH-1:0] burst_count;
wire [BURSTCOUNTWIDTH-1:0] first_short_burst_count;
wire first_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] final_short_burst_count;
wire final_short_burst_enable;
wire [BURSTCOUNTWIDTH-1:0] burst_boundary_word_address;
reg burst_begin;
wire too_many_reads_pending;
wire [FIFODEPTH_LOG2-1:0] fifo_used;
// registering the control_fixed_location bit
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
control_fixed_location_d1 <= 0;
end
else
begin
if (control_go == 1)
begin
control_fixed_location_d1 <= control_fixed_location;
end
end
end
// master address logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
address <= 0;
end
else
begin
if(control_go == 1)
begin
address <= control_read_base;
end
else if((increment_address == 1) & (control_fixed_location_d1 == 0))
begin
address <= address + (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, increment by the burst count presented
end
end
end
// master length logic
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
length <= 0;
end
else
begin
if(control_go == 1)
begin
length <= control_read_length;
end
else if(increment_address == 1)
begin
length <= length - (burst_count * BYTEENABLEWIDTH); // always performing word size accesses, decrement by the burst count presented
end
end
end
// controlled signals going to the master/control ports
assign master_address = address;
assign master_byteenable = -1; // all ones, always performing word size accesses
assign master_burstcount = burst_count;
assign control_done = (length == 0) & (reads_pending == 0); // need to make sure that the reads have returned before firing the done bit
assign control_early_done = (length == 0); // advanced feature, you should use 'control_done' if you need all the reads to return first
assign master_read = (too_many_reads_pending == 0) & (length != 0);
assign burst_boundary_word_address = ((address / BYTEENABLEWIDTH) & (MAXBURSTCOUNT - 1));
assign first_short_burst_enable = (burst_boundary_word_address != 0);
assign final_short_burst_enable = (length < (MAXBURSTCOUNT * BYTEENABLEWIDTH));
assign first_short_burst_count = ((burst_boundary_word_address & 1'b1) == 1'b1)? 1 : // if the burst boundary isn't a multiple of 2 then must post a burst of 1 to get to a multiple of 2 for the next burst
(((MAXBURSTCOUNT - burst_boundary_word_address) < (length / BYTEENABLEWIDTH))?
(MAXBURSTCOUNT - burst_boundary_word_address) : (length / BYTEENABLEWIDTH));
assign final_short_burst_count = (length / BYTEENABLEWIDTH);
assign burst_count = (first_short_burst_enable == 1)? first_short_burst_count : // this will get the transfer back on a burst boundary,
(final_short_burst_enable == 1)? final_short_burst_count : MAXBURSTCOUNT;
assign increment_address = (too_many_reads_pending == 0) & (master_waitrequest == 0) & (length != 0);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFODEPTH - MAXBURSTCOUNT - 4); // make sure there are fewer reads posted than room in the FIFO
// tracking FIFO
always @ (posedge clk or posedge reset)
begin
if (reset == 1)
begin
reads_pending <= 0;
end
else
begin
if(increment_address == 1)
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending + burst_count;
end
else
begin
reads_pending <= reads_pending + burst_count - 1; // a burst read was posted, but a word returned
end
end
else
begin
if(master_readdatavalid == 0)
begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end
else
begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
// read data feeding user logic
assign user_data_available = !fifo_empty;
scfifo the_master_to_user_fifo (
.aclr (reset),
.clock (clk),
.data (master_readdata),
.empty (fifo_empty),
.q (user_buffer_data),
.rdreq (user_read_buffer),
.usedw (fifo_used),
.wrreq (master_readdatavalid)
);
defparam the_master_to_user_fifo.lpm_width = DATAWIDTH;
defparam the_master_to_user_fifo.lpm_numwords = FIFODEPTH;
defparam the_master_to_user_fifo.lpm_widthu = FIFODEPTH_LOG2; //Deepak
defparam the_master_to_user_fifo.lpm_showahead = "ON";
defparam the_master_to_user_fifo.use_eab = (FIFOUSEMEMORY == 1)? "ON" : "OFF";
defparam the_master_to_user_fifo.add_ram_output_register = "OFF";
defparam the_master_to_user_fifo.underflow_checking = "OFF";
defparam the_master_to_user_fifo.overflow_checking = "OFF";
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Setoid.
Require Import PeanoNat Le Gt Minus Bool Lt.
Set Implicit Arguments.
(* Set Universe Polymorphism. *)
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
Open Scope list_scope.
(** Standard notations for lists.
In a special module to avoid conflicts. *)
Module ListNotations.
Notation " [ ] " := nil (format "[ ]") : list_scope.
Notation " [ x ] " := (cons x nil) : list_scope.
Notation " [ x ; .. ; y ] " := (cons x .. (cons y nil) ..) : list_scope.
End ListNotations.
Import ListNotations.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| [] => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| [] => None
| x :: _ => Some x
end.
Definition tl (l:list A) :=
match l with
| [] => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end.
End Lists.
Section Facts.
Variable A : Type.
(** *** Genereric facts *)
(** Discrimination *)
Theorem nil_cons : forall (x:A) (l:list A), [] <> x :: l.
Proof.
intros; discriminate.
Qed.
(** Destruction *)
Theorem destruct_list : forall l : list A, {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
Lemma hd_error_tl_repr : forall l (a:A) r,
hd_error l = Some a /\ tl l = r <-> l = a :: r.
Proof. destruct l as [|x xs].
- unfold hd_error, tl; intros a r. split; firstorder discriminate.
- intros. simpl. split.
* intros (H1, H2). inversion H1. rewrite H2. reflexivity.
* inversion 1. subst. auto.
Qed.
Lemma hd_error_some_nil : forall l (a:A), hd_error l = Some a -> l <> nil.
Proof. unfold hd_error. destruct l; now discriminate. Qed.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
simpl; reflexivity.
Qed.
Theorem hd_error_cons : forall (l : list A) (x : A), hd_error (x::l) = Some x.
Proof.
intros; simpl; reflexivity.
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem not_in_cons (x a : A) (l : list A):
~ In x (a::l) <-> x<>a /\ ~ In x l.
Proof.
simpl. intuition.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
induction l; simpl; destruct 1.
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl. apply f_equal. auto.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof.
intros a b l H; inversion_clear H; auto.
Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intro H; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil : forall (x y:list A) (a:A), [] <> x ++ a :: y.
Proof.
unfold not.
destruct x as [| a l]; simpl; intros.
discriminate H.
discriminate H.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l : forall l:list A, [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r : forall l:list A, l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end : forall (l:list A), l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc : forall l m n:list A, l ++ m ++ n = (l ++ m) ++ n.
Proof.
intros l m n; induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse : forall l m n:list A, (l ++ m) ++ n = l ++ m ++ n.
Proof.
auto using app_assoc.
Qed.
Hint Resolve app_assoc_reverse.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons : forall (x y:list A) (a:A), a :: (x ++ y) = (a :: x) ++ y.
Proof.
auto.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil : forall l l':list A, l ++ l' = [] -> l = [] /\ l' = [].
Proof.
destruct l as [| x l]; destruct l' as [| y l']; simpl; auto.
intro; discriminate.
intros H; discriminate H.
Qed.
Theorem app_eq_unit :
forall (x y:list A) (a:A),
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x as [| a l]; [ destruct y as [| a l] | destruct y as [| a0 l0] ];
simpl.
intros a H; discriminate H.
left; split; auto.
right; split; auto.
generalize H.
generalize (app_nil_r l); intros E.
rewrite -> E; auto.
intros.
injection H.
intro.
assert ([] = l ++ a0 :: l0) by auto.
apply app_cons_not_nil in H1 as [].
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
induction x as [| x l IHl];
[ destruct y as [| a l] | destruct y as [| a l0] ];
simpl; auto.
- intros a b H.
injection H.
auto.
- intros a0 b H.
injection H as H1 H0.
apply app_cons_not_nil in H0 as [].
- intros a b H.
injection H as H1 H0.
assert ([] = l ++ [a]) by auto.
apply app_cons_not_nil in H as [].
- intros a0 b H.
injection H as <- H0.
destruct (IHl l0 a0 b H0) as (<-,<-).
split; auto.
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
induction l; simpl; auto.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a.
elim l; simpl; auto.
intros a0 y H H0.
now_show ((a0 = a \/ In a y) \/ In a m).
elim H0; auto.
intro H1.
now_show ((a0 = a \/ In a y) \/ In a m).
elim (H H1); auto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a.
elim l; simpl; intro H.
now_show (In a m).
elim H; auto; intro H0.
now_show (In a m).
elim H0. (* subProof completed *)
intros y H0 H1.
now_show (H = a \/ In a (y ++ m)).
elim H1; auto 4.
intro H2.
now_show (H = a \/ In a (y ++ m)).
elim H2; auto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
induction l; simpl; auto; injection 1; auto.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l l1 l2; revert l1 l2 l.
induction l1 as [ | x1 l1]; destruct l2 as [ | x2 l2];
simpl; auto; intros l H.
absurd (length (x2 :: l2 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite <- H; auto with arith.
absurd (length (x1 :: l1 ++ l) <= length l).
simpl; rewrite app_length; auto with arith.
rewrite H; auto with arith.
injection H; clear H; intros; f_equal; eauto.
Qed.
End Facts.
Hint Resolve app_assoc app_assoc_reverse: datatypes v62.
Hint Resolve app_comm_cons app_cons_not_nil: datatypes v62.
Hint Immediate app_eq_nil: datatypes v62.
Hint Resolve app_eq_unit app_inj_tail: datatypes v62.
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes v62.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l.
- right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : option A :=
match n, l with
| O, x :: _ => Some x
| S n, _ :: l => nth_error l n
| _, _ => None
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; induction n as [| n hn]; simpl.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l as [| a l hl]; simpl.
* inversion 2.
* intros d ie; right; apply hn; auto with arith.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n & Hn & Hn').
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
induction l; destruct n; simpl; intros; auto.
- inversion H.
- apply IHl; auto with arith.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
induction l.
- inversion 1.
- intros [|n] d d'; simpl; auto with arith.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
induction l.
- inversion 1.
- intros l' d [|n]; simpl; auto with arith.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
induction l; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; auto with arith.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); auto with arith.
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto with arith.
* destruct (IH H) as (n,Hn).
exists (S n); simpl; auto with arith.
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l; destruct n; simpl.
- split; auto.
- split; auto with arith.
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- split; now auto with arith.
- rewrite IHl; split; auto with arith.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; simpl in *; try easy.
- exists nil; exists l. injection H; clear H; intros; now subst.
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n; intros [|a l] H; auto; try solve [inversion H].
simpl in *. apply IHn. auto with arith.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
induction l as [|x l]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
induction l.
destruct 1; auto.
intros d _.
destruct l; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
induction l.
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
induction l.
simpl; auto.
simpl; intros.
assert (l++l' <> []).
destruct l.
simpl; auto.
simpl; discriminate.
specialize (IHl l' H).
destruct (l++l'); [elim H0; auto|f_equal; auto].
Qed.
(****************************************)
(** ** Counting occurences of a element *)
(****************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In l x : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l]; simpl.
- split; [destruct 1 | apply gt_irrefl].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition.
Qed.
Theorem count_occ_not_In l x : ~ In x l <-> count_occ l x = 0.
Proof.
rewrite count_occ_In. unfold gt. now rewrite Nat.nlt_ge, Nat.le_0_r.
Qed.
Lemma count_occ_nil x : count_occ [] x = 0.
Proof.
reflexivity.
Qed.
Theorem count_occ_inv_nil l :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_cons_eq l x y :
x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_cons_neq l x y :
x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
induction x as [| a l IHl].
destruct y as [| a l].
simpl.
auto.
simpl.
rewrite app_nil_r; auto.
intro y.
simpl.
rewrite (IHl y).
rewrite app_assoc; trivial.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros.
apply (rev_app_distr l [a]); simpl; auto.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
induction l as [| a l IHl].
simpl; auto.
simpl.
rewrite (rev_unit (rev l) a).
rewrite IHl; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
induction l.
simpl; intuition.
intros.
simpl.
intuition.
subst.
apply in_or_app; right; simpl; auto.
apply in_or_app; left; firstorder.
destruct (in_app_or _ _ _ H); firstorder.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
induction l;simpl; auto.
rewrite app_length.
rewrite IHl.
simpl.
elim (length l); simpl; auto.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
induction l.
intros; inversion H.
intros.
simpl in H.
simpl (rev (a :: l)).
simpl (length (a :: l) - S n).
inversion H.
rewrite <- minus_n_n; simpl.
rewrite <- rev_length.
rewrite app_nth2; auto.
rewrite <- minus_n_n; auto.
rewrite app_nth1; auto.
rewrite (minus_plus_simpl_l_reverse (length l) n 1).
replace (1 + length l) with (S (length l)); auto with arith.
rewrite <- minus_Sn_m; auto with arith.
apply IHl ; auto with arith.
rewrite rev_length; auto.
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Section Reverse_Induction.
Lemma rev_list_ind :
forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
induction l; auto.
Qed.
Theorem rev_ind :
forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros.
generalize (rev_involutive l).
intros E; rewrite <- E.
apply (rev_list_ind P).
auto.
simpl.
intros.
apply (H0 a (rev l0)).
auto.
Qed.
End Reverse_Induction.
(*************************)
(** ** Concatenation *)
(*************************)
Fixpoint concat (l : list (list A)) : list A :=
match l with
| nil => nil
| cons x l => x ++ concat l
end.
Lemma concat_nil : concat nil = nil.
Proof.
reflexivity.
Qed.
Lemma concat_cons : forall x l, concat (cons x l) = x ++ concat l.
Proof.
reflexivity.
Qed.
Lemma concat_app : forall l1 l2, concat (l1 ++ l2) = concat l1 ++ concat l2.
Proof.
intros l1; induction l1 as [|x l1 IH]; intros l2; simpl.
+ reflexivity.
+ rewrite IH; apply app_assoc.
Qed.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| [] => []
| a :: t => (f a) :: (map t)
end.
Lemma map_cons (x:A)(l:list A) : map (x::l) = (f x) :: (map l).
Proof.
reflexivity.
Qed.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
induction l; simpl map; destruct n; firstorder.
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
induction n; intros [ | ] ? Heq; simpl in *; inversion Heq; auto.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
induction l; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
induction l; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
destruct l; simpl; reflexivity || discriminate.
Qed.
(** [map] and count of occurrences *)
Hypothesis decA: forall x1 x2 : A, {x1 = x2} + {x1 <> x2}.
Hypothesis decB: forall y1 y2 : B, {y1 = y2} + {y1 <> y2}.
Hypothesis Hfinjective: forall x1 x2: A, (f x1) = (f x2) -> x1 = x2.
Theorem count_occ_map x l:
count_occ decA l x = count_occ decB (map l) (f x).
Proof.
revert x. induction l as [| a l' Hrec]; intro x; simpl.
- reflexivity.
- specialize (Hrec x).
destruct (decA a x) as [H1|H1], (decB (f a) (f x)) as [H2|H2].
* rewrite Hrec. reflexivity.
* contradiction H2. rewrite H1. reflexivity.
* specialize (Hfinjective H2). contradiction H1.
* assumption.
Qed.
(** [flat_map] *)
Definition flat_map (f:A -> list B) :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma in_flat_map : forall (f:A->list B)(l:list A)(y:B),
In y (flat_map f l) <-> exists x, In x l /\ In y (f x).
Proof using A B.
induction l; simpl; split; intros.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H).
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
End Map.
Lemma flat_map_concat_map : forall A B (f : A -> list B) l,
flat_map f l = concat (map f l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite IH; reflexivity.
Qed.
Lemma concat_map : forall A B (f : A -> B) l, map f (concat l) = concat (map (map f) l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
+ reflexivity.
+ rewrite map_app, IH; reflexivity.
Qed.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
induction l; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
induction l; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext_in :
forall (A B : Type)(f g:A->B) l, (forall a, In a l -> f a = g a) -> map f l = map g l.
Proof.
induction l; simpl; auto.
intros; rewrite H by intuition; rewrite IHl; auto.
Qed.
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
intros; apply map_ext_in; auto.
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables (A : Type) (B : Type).
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
induction l.
simpl; auto.
intros.
simpl.
auto.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intros A l.
enough (H : forall n, fold_left (fun x _ => S x) l n = n + length l) by exact (H 0).
induction l; simpl; auto.
intros; rewrite IHl.
simpl; auto with arith.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables (A : Type) (B : Type).
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A : Type) (f : A -> A -> A),
(forall x y z : A, f x (f y z) = f (f x y) z) ->
forall (a0 : A), (forall y : A, f a0 y = f y a0) ->
forall (l : list A), fold_left f l a0 = fold_right f a0 l.
Proof.
intros A f assoc a0 comma0 l.
induction l as [ | a1 l ]; [ simpl; reflexivity | ].
simpl. rewrite <- IHl. clear IHl. revert a1. induction l; [ auto | ].
simpl. intro. rewrite <- assoc. rewrite IHl. rewrite IHl. auto.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
induction l; simpl; intuition.
inversion H.
firstorder.
destruct (orb_prop _ _ H1); firstorder.
firstorder.
subst.
rewrite H2; auto.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
induction l.
inversion 1.
simpl; intros.
destruct (orb_false_elim _ _ H0); clear H0; auto.
destruct n ; auto.
rewrite IHl; auto with arith.
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
induction l1; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
induction l; simpl; intuition.
destruct (andb_prop _ _ H1).
congruence.
destruct (andb_prop _ _ H1); auto.
assert (forallb l = true).
apply H0; intuition.
rewrite H1; auto.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
induction l1; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
induction l; simpl.
intuition.
intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
Lemma find_some l x : find l = Some x -> In x l /\ f x = true.
Proof.
induction l as [|a l IH]; simpl; [easy| ].
case_eq (f a); intros Ha Eq.
* injection Eq as ->; auto.
* destruct (IH Eq); auto.
Qed.
Lemma find_none l : find l = None -> forall x, In x l -> f x = false.
Proof.
induction l as [|a l IH]; simpl; [easy|].
case_eq (f a); intros Ha Eq x IN; [easy|].
destruct IN as [<-|IN]; auto.
Qed.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
Theorem partition_cons1 a l l1 l2:
partition l = (l1, l2) ->
f a = true ->
partition (a::l) = (a::l1, l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_cons2 a l l1 l2:
partition l = (l1, l2) ->
f a=false ->
partition (a::l) = (l1, a::l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_length l l1 l2:
partition l = (l1, l2) ->
length l = length l1 + length l2.
Proof.
revert l1 l2. induction l as [ | a l' Hrec]; intros l1 l2.
- now intros [= <- <- ].
- simpl. destruct (f a), (partition l') as (left, right);
intros [= <- <- ]; simpl; rewrite (Hrec left right); auto.
Qed.
Theorem partition_inv_nil (l : list A):
partition l = ([], []) <-> l = [].
Proof.
split.
- destruct l as [|a l' _].
* intuition.
* simpl. destruct (f a), (partition l'); now intros [= -> ->].
- now intros ->.
Qed.
Theorem elements_in_partition l l1 l2:
partition l = (l1, l2) ->
forall x:A, In x l <-> In x l1 \/ In x l2.
Proof.
revert l1 l2. induction l as [| a l' Hrec]; simpl; intros l1 l2 Eq x.
- injection Eq as <- <-. tauto.
- destruct (partition l') as (left, right).
specialize (Hrec left right eq_refl x).
destruct (f a); injection Eq as <- <-; simpl; tauto.
Qed.
End Bool.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (a0,b) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l; destruct l'; simpl; intros; auto; try discriminate.
injection H; clear H; intros.
rewrite IHl; auto.
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2; clear H2; intros; subst; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
unfold lel; auto with arith.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
apply le_trans with (length m); auto with arith.
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
unfold lel; simpl; auto with arith.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; auto with arith.
intros a' y H H0.
now_show (nil = a' :: y).
absurd (S (length y) <= 0); auto with arith.
Qed.
End length_order.
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes v62.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
Hint Unfold incl.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
Hint Resolve incl_refl.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_tl.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appl.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
Hint Immediate incl_appr.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
unfold incl; simpl; intros a l m H H0 a0 H1.
now_show (In a0 m).
elim H1.
now_show (a = a0 -> In a0 m).
elim H1; auto; intro H2.
now_show (a = a0 -> In a0 m).
elim H2; auto. (* solves subgoal *)
now_show (In a0 l -> In a0 m).
auto.
Qed.
Hint Resolve incl_cons.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
Hint Resolve incl_app.
End SetIncl.
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app: datatypes v62.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply Peano.le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
induction n.
simpl; auto.
destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
induction n; destruct l; simpl; auto.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (firstn (S (S n)) (a::l)) with ((a::nil)++firstn (S n) l).
change (firstn (S n) (a::l)) with (a::firstn n l).
rewrite removelast_app.
rewrite IHn; auto with arith.
clear IHn; destruct l; simpl in *; try discriminate.
inversion_clear H.
inversion_clear H0.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
induction n; destruct l.
simpl; auto.
simpl; auto.
simpl; auto.
intros.
simpl in H.
change (removelast (a :: l)) with (removelast ((a::nil)++l)).
rewrite removelast_app.
simpl; f_equal; auto with arith.
intro H0; rewrite H0 in H; inversion_clear H; inversion_clear H1.
Qed.
End Cutting.
(**********************************************************************)
(** ** Predicate for List addition/removal (no need for decidability) *)
(**********************************************************************)
Section Add.
Variable A : Type.
(* [Add a l l'] means that [l'] is exactly [l], with [a] added
once somewhere *)
Inductive Add (a:A) : list A -> list A -> Prop :=
| Add_head l : Add a l (a::l)
| Add_cons x l l' : Add a l l' -> Add a (x::l) (x::l').
Lemma Add_app a l1 l2 : Add a (l1++l2) (l1++a::l2).
Proof.
induction l1; simpl; now constructor.
Qed.
Lemma Add_split a l l' :
Add a l l' -> exists l1 l2, l = l1++l2 /\ l' = l1++a::l2.
Proof.
induction 1.
- exists nil; exists l; split; trivial.
- destruct IHAdd as (l1 & l2 & Hl & Hl').
exists (x::l1); exists l2; split; simpl; f_equal; trivial.
Qed.
Lemma Add_in a l l' : Add a l l' ->
forall x, In x l' <-> In x (a::l).
Proof.
induction 1; intros; simpl in *; rewrite ?IHAdd; tauto.
Qed.
Lemma Add_length a l l' : Add a l l' -> length l' = S (length l).
Proof.
induction 1; simpl; auto with arith.
Qed.
Lemma Add_inv a l : In a l -> exists l', Add a l' l.
Proof.
intro Ha. destruct (in_split _ _ Ha) as (l1 & l2 & ->).
exists (l1 ++ l2). apply Add_app.
Qed.
Lemma incl_Add_inv a l u v :
~In a l -> incl (a::l) v -> Add a u v -> incl l u.
Proof.
intros Ha H AD y Hy.
assert (Hy' : In y (a::u)).
{ rewrite <- (Add_in AD). apply H; simpl; auto. }
destruct Hy'; [ subst; now elim Ha | trivial ].
Qed.
End Add.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_Add a l l' : Add a l l' -> (NoDup l' <-> NoDup l /\ ~In a l).
Proof.
induction 1 as [l|x l l' AD IH].
- split; [ inversion_clear 1; now split | now constructor ].
- split.
+ inversion_clear 1. rewrite IH in *. rewrite (Add_in AD) in *.
simpl in *; split; try constructor; intuition.
+ intros (N,IN). inversion_clear N. constructor.
* rewrite (Add_in AD); simpl in *; intuition.
* apply IH. split; trivial. simpl in *; intuition.
Qed.
Lemma NoDup_remove l l' a :
NoDup (l++a::l') -> NoDup (l++l') /\ ~In a (l++l').
Proof.
apply NoDup_Add. apply Add_app.
Qed.
Lemma NoDup_remove_1 l l' a : NoDup (l++a::l') -> NoDup (l++l').
Proof.
intros. now apply NoDup_remove with a.
Qed.
Lemma NoDup_remove_2 l l' a : NoDup (l++a::l') -> ~In a (l++l').
Proof.
intros. now apply NoDup_remove.
Qed.
Theorem NoDup_cons_iff a l:
NoDup (a::l) <-> ~ In a l /\ NoDup l.
Proof.
split.
+ inversion_clear 1. now split.
+ now constructor.
Qed.
(** Effective computation of a list without duplicates *)
Hypothesis decA: forall x y : A, {x = y} + {x <> y}.
Fixpoint nodup (l : list A) : list A :=
match l with
| [] => []
| x::xs => if in_dec decA x xs then nodup xs else x::(nodup xs)
end.
Lemma nodup_In l x : In x (nodup l) <-> In x l.
Proof.
induction l as [|a l' Hrec]; simpl.
- reflexivity.
- destruct (in_dec decA a l'); simpl; rewrite Hrec.
* intuition; now subst.
* reflexivity.
Qed.
Lemma NoDup_nodup l: NoDup (nodup l).
Proof.
induction l as [|a l' Hrec]; simpl.
- constructor.
- destruct (in_dec decA a l'); simpl.
* assumption.
* constructor; [ now rewrite nodup_In | assumption].
Qed.
Lemma nodup_inv k l a : nodup k = a :: l -> ~ In a l.
Proof.
intros H.
assert (H' : NoDup (a::l)).
{ rewrite <- H. apply NoDup_nodup. }
now inversion_clear H'.
Qed.
Theorem NoDup_count_occ l:
NoDup l <-> (forall x:A, count_occ decA l x <= 1).
Proof.
induction l as [| a l' Hrec].
- simpl; split; auto. constructor.
- rewrite NoDup_cons_iff, Hrec, (count_occ_not_In decA). clear Hrec. split.
+ intros (Ha, H) x. simpl. destruct (decA a x); auto.
subst; now rewrite Ha.
+ split.
* specialize (H a). rewrite count_occ_cons_eq in H; trivial.
now inversion H.
* intros x. specialize (H x). simpl in *. destruct (decA a x); auto.
now apply Nat.lt_le_incl.
Qed.
Theorem NoDup_count_occ' l:
NoDup l <-> (forall x:A, In x l -> count_occ decA l x = 1).
Proof.
rewrite NoDup_count_occ.
setoid_rewrite (count_occ_In decA). unfold gt, lt in *.
split; intros H x; specialize (H x);
set (n := count_occ decA l x) in *; clearbody n.
(* the rest would be solved by omega if we had it here... *)
- now apply Nat.le_antisymm.
- destruct (Nat.le_gt_cases 1 n); trivial.
+ rewrite H; trivial.
+ now apply Nat.lt_le_incl.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. discriminate H; auto with arith.
* apply IHl.
intros i j Hi E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi Hj E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. subst a. apply nth_In; auto with arith.
* elim Hal. subst a. apply nth_In; auto with arith.
* f_equal. apply IH; auto with arith. }
{ induction l as [|a l]; intros H; constructor.
* intro Ha. eapply In_nth in Ha. destruct Ha as (n & Hn & Hn').
specialize (H 0 (S n)). simpl in H. discriminate H; eauto with arith.
* apply IHl.
intros i j Hi Hj E. apply eq_add_S, H; simpl; auto with arith. }
Qed.
(** Having [NoDup] hypotheses bring more precise facts about [incl]. *)
Lemma NoDup_incl_length l l' :
NoDup l -> incl l l' -> length l <= length l'.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH]; simpl.
- auto with arith.
- intros l' H.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_length AD). apply le_n_S. apply IH.
now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_length_incl l l' :
NoDup l -> length l' <= length l -> incl l l' -> incl l' l.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH].
- destruct l'; easy.
- intros l' E H x Hx.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_in AD) in Hx. simpl in Hx.
destruct Hx as [Hx|Hx]; [left; trivial|right].
revert x Hx. apply (IH l''); trivial.
* apply le_S_n. now rewrite <- (Add_length AD).
* now apply incl_Add_inv with a l'.
Qed.
End ReDun.
(** NoDup and map *)
(** NB: the reciprocal result holds only for injective functions,
see FinFun.v *)
Lemma NoDup_map_inv A B (f:A->B) l : NoDup (map f l) -> NoDup l.
Proof.
induction l; simpl; inversion_clear 1; subst; constructor; auto.
intro H. now apply (in_map f) in H.
Qed.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
induction len; intros.
inversion H.
simpl seq.
destruct n; simpl.
auto with arith.
rewrite IHlen;simpl; auto with arith.
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
induction len; simpl; auto.
intros.
rewrite IHlen.
auto with arith.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). apply (Lt.lt_irrefl _ H).
Qed.
End NatSeq.
Section Exists_Forall.
(** * Existential and universal predicates over lists *)
Variable A:Type.
Section One_predicate.
Variable P:A->Prop.
Inductive Exists : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists (x::l)
| Exists_cons_tl : forall x l, Exists l -> Exists (x::l).
Hint Constructors Exists.
Lemma Exists_exists (l:list A) :
Exists l <-> (exists x, In x l /\ P x).
Proof.
split.
- induction 1; firstorder.
- induction l; firstorder; subst; auto.
Qed.
Lemma Exists_nil : Exists nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons x l:
Exists (x::l) <-> P x \/ Exists l.
Proof. split; inversion 1; auto. Qed.
Lemma Exists_dec l:
(forall x:A, {P x} + { ~ P x }) ->
{Exists l} + {~ Exists l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- right. now rewrite Exists_nil.
- destruct Hrec as [Hl'|Hl'].
* left. now apply Exists_cons_tl.
* destruct (Pdec a) as [Ha|Ha].
+ left. now apply Exists_cons_hd.
+ right. now inversion_clear 1.
Qed.
Inductive Forall : list A -> Prop :=
| Forall_nil : Forall nil
| Forall_cons : forall x l, P x -> Forall l -> Forall (x::l).
Hint Constructors Forall.
Lemma Forall_forall (l:list A):
Forall l <-> (forall x, In x l -> P x).
Proof.
split.
- induction 1; firstorder; subst; auto.
- induction l; firstorder.
Qed.
Lemma Forall_inv : forall (a:A) l, Forall (a :: l) -> P a.
Proof.
intros; inversion H; trivial.
Qed.
Lemma Forall_rect : forall (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall l -> Q l.
Proof.
intros Q H H'; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Qed.
Lemma Forall_dec :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A, {Forall l} + {~ Forall l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- left. apply Forall_nil.
- destruct Hrec as [Hl'|Hl'].
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Forall_cons.
* right. now inversion_clear 1.
+ right. now inversion_clear 1.
Qed.
End One_predicate.
Lemma Forall_Exists_neg (P:A->Prop)(l:list A) :
Forall (fun x => ~ P x) l <-> ~(Exists P l).
Proof.
rewrite Forall_forall, Exists_exists. firstorder.
Qed.
Lemma Exists_Forall_neg (P:A->Prop)(l:list A) :
(forall x, P x \/ ~P x) ->
Exists (fun x => ~ P x) l <-> ~(Forall P l).
Proof.
intro Dec.
split.
- rewrite Forall_forall, Exists_exists; firstorder.
- intros NF.
induction l as [|a l IH].
+ destruct NF. constructor.
+ destruct (Dec a) as [Ha|Ha].
* apply Exists_cons_tl, IH. contradict NF. now constructor.
* now apply Exists_cons_hd.
Qed.
Lemma Forall_Exists_dec (P:A->Prop) :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A,
{Forall P l} + {Exists (fun x => ~ P x) l}.
Proof.
intros Pdec l.
destruct (Forall_dec P Pdec l); [left|right]; trivial.
apply Exists_Forall_neg; trivial.
intro x. destruct (Pdec x); [now left|now right].
Qed.
Lemma Forall_impl : forall (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros P Q H l. rewrite !Forall_forall. firstorder.
Qed.
End Exists_Forall.
Hint Constructors Exists.
Hint Constructors Forall.
Section Forall2.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Variables A B : Type.
Variable R : A -> B -> Prop.
Inductive Forall2 : list A -> list B -> Prop :=
| Forall2_nil : Forall2 [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 l l' -> Forall2 (x::l) (y::l').
Hint Constructors Forall2.
Theorem Forall2_refl : Forall2 [] [].
Proof. intros; apply Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall l1 l2 l',
Forall2 (l1 ++ l2) l' ->
exists l1' l2', Forall2 l1 l1' /\ Forall2 l2 l2' /\ l' = l1' ++ l2'.
Proof.
induction l1; intros.
exists [], l'; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall l1' l2' l,
Forall2 l (l1' ++ l2') ->
exists l1 l2, Forall2 l1 l1' /\ Forall2 l2 l2' /\ l = l1 ++ l2.
Proof.
induction l1'; intros.
exists [], l; auto.
simpl in H; inversion H; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall l1 l2 l1' l2',
Forall2 l1 l1' -> Forall2 l2 l2' -> Forall2 (l1 ++ l2) (l1' ++ l2').
Proof.
intros. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
End Forall2.
Hint Constructors Forall2.
Section ForallPairs.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Variable A : Type.
Variable R : A -> A -> Prop.
Definition ForallPairs l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs : list A -> Prop :=
| FOP_nil : ForallOrdPairs nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs l -> ForallOrdPairs (a::l).
Hint Constructors ForallOrdPairs.
Lemma ForallOrdPairs_In : forall l,
ForallOrdPairs l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs l: ForallPairs l -> ForallOrdPairs l.
Proof.
induction l; auto. intros H.
constructor.
apply <- Forall_forall. intros; apply H; simpl; auto.
apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs :
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs l -> ForallPairs l.
Proof.
intros Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
End ForallPairs.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
Hint Resolve app_nil_end : datatypes v62.
(* end hide *)
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(* Unset Universe Polymorphism. *)
|
`timescale 1ns/1ps
primitive not_u (out, in);
output out;
input in;
table
0 : 1;
1 : 0;
endtable
endprimitive
// Any instance of this gate will use the small time scale that was
// in place when it was defined.
module gate_sdf(out, in);
output out;
input in;
wire out, in;
assign out = ~in;
specify
(in => out) = (0.5, 0.5);
endspecify
endmodule
/*
* Icarus does not currently support UDPs with a variable delay.
* It also needs to support NULL decay delays, buf/not/etc. should
* only allow two delays maximum.
*/
module top;
initial begin
$monitor("%.3f", $realtime,, sml_const.test, sml_var.test,
sml_const.out_g, sml_const.out_u,
sml_const.out_m, sml_const.out_s,
sml_var.out_g, sml_var.out_u,,
sml_const.out_f, med_const.out_f,
lrg_const.out_f,,
med_const.test, med_var.test,
med_const.out_g, med_const.out_u,
med_const.out_m, med_const.out_s,
med_var.out_g, med_var.out_u,,
lrg_const.test, lrg_var.test,
lrg_const.out_g, lrg_const.out_u,
lrg_const.out_m, lrg_const.out_s,
lrg_var.out_g, lrg_var.out_u);
#1.3 $finish(0);
end
endmodule
/*
* These should have a positive edge at 1234 time ticks.
*/
// Check that constant delays are scaled correctly.
module sml_const;
reg test, in;
wire out_g, out_u, out_m, out_s, out_f;
not #(1.134, 0) dut_g (out_g, in);
not_u #(1.134, 0) dut_u (out_u, in);
sml_inv dut_m (out_m, in);
gate_sdf dut_f (out_f, in);
sml_sdf dut_s (out_s, in);
initial begin
$sdf_annotate("ivltests/real_delay.sdf");
$sdf_annotate("ivltests/real_delay_sml.sdf");
in = 1'b1;
in <= #0.1 1'b0;
test = 1'b0;
#1.234 test = 1'b1;
end
endmodule
// Check that the specify delays are scaled correctly.
module sml_inv(out, in);
output out;
input in;
wire out, in;
assign out = ~in;
specify
(in => out) = (1.134, 0);
endspecify
endmodule
// Check that the SDF delays scale correctly.
module sml_sdf(out, in);
output out;
input in;
wire out, in;
assign out = ~in;
specify
(in => out) = (0.5, 0.5);
endspecify
endmodule
// Check that variable delays are scaled correctly.
module sml_var;
reg test, in;
real dly, dly2, dly3;
wire out_g, out_u;
not #(dly2, dly3) dut_g (out_g, in);
not_u #(dly2, dly3) dut_u (out_u, in);
initial begin
in = 1'b1;
in <= #0.1 1'b0;
dly = 1.234;
dly2 = 1.134;
dly3 = 0.0;
test = 1'b0;
#(dly) test = 1'b1;
end
endmodule
`timescale 1ns/10ps
/*
* These should have a positive edge at 1230 time ticks.
*/
// Check that constant delays are scaled correctly.
module med_const;
reg test, in;
wire out_g, out_u, out_m, out_s, out_f;
not #(1.134, 0) dut_g (out_g, in);
not_u #(1.134, 0) dut_u (out_u, in);
med_inv dut_m (out_m, in);
gate_sdf dut_f (out_f, in);
med_sdf dut_s (out_s, in);
initial begin
$sdf_annotate("ivltests/real_delay.sdf");
$sdf_annotate("ivltests/real_delay_med.sdf");
in = 1'b1;
in <= #0.1 1'b0;
test = 1'b0;
#1.234 test = 1'b1;
end
endmodule
// Check that the specify delays are scaled correctly.
module med_inv(out, in);
output out;
input in;
wire out, in;
assign out = ~in;
specify
(in => out) = (1.134, 0);
endspecify
endmodule
// Check that the SDF delays scale correctly.
module med_sdf(out, in);
output out;
input in;
wire out, in;
assign out = ~in;
specify
(in => out) = (0.5, 0.5);
endspecify
endmodule
// Check that variable delays are scaled correctly.
module med_var;
reg test, in;
real dly, dly2, dly3;
wire out_g, out_u;
not #(dly2, dly3) dut_g (out_g, in);
not_u #(dly2, dly3) dut_u (out_u, in);
initial begin
in = 1'b1;
in <= #0.1 1'b0;
dly = 1.234;
dly2 = 1.134;
dly3 = 0.0;
test = 1'b0;
#(dly) test = 1'b1;
end
endmodule
`timescale 1ns/100ps
/*
* These should have a positive edge at 1200 time ticks.
*/
// Check that constant delays are scaled correctly.
module lrg_const;
reg test, in;
wire out_g, out_u, out_m, out_s, out_f;
not #(1.134, 0) gate (out_g, in);
not_u #(1.134, 0) dut_u (out_u, in);
lrg_inv dut_m (out_m, in);
gate_sdf dut_f (out_f, in);
lrg_sdf dut_s (out_s, in);
initial begin
$sdf_annotate("ivltests/real_delay.sdf");
$sdf_annotate("ivltests/real_delay_lrg.sdf");
in = 1'b1;
in <= #0.1 1'b0;
test = 1'b0;
#1.234 test = 1'b1;
end
endmodule
// Check that the specify delays are scaled correctly.
module lrg_inv(out, in);
output out;
input in;
wire out, in;
assign out = ~in;
specify
(in => out) = (1.134, 0);
endspecify
endmodule
// Check that the SDF delays scale correctly.
module lrg_sdf(out, in);
output out;
input in;
wire out, in;
assign out = ~in;
specify
(in => out) = (0.5, 0.5);
endspecify
endmodule
// Check that variable delays are scaled correctly.
module lrg_var;
reg test, in;
real dly, dly2, dly3;
wire out_g, out_u;
not #(dly2, dly3) dut_g (out_g, in);
not_u #(dly2, dly3) dut_u (out_u, in);
initial begin
in = 1'b1;
in <= #0.1 1'b0;
dly = 1.234;
dly2 = 1.134;
dly3 = 0.0;
test = 1'b0;
#(dly) test = 1'b1;
end
endmodule
|
// This module converts a singed or an unsigned integer into a floating point number.
module acl_fp_convert_from_int(clock, resetn, dataa, result, enable, valid_in, valid_out, stall_in, stall_out);
parameter UNSIGNED = 0;
parameter HIGH_CAPACITY = 1;
parameter ROUNDING_MODE = 0;
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock, resetn;
input [31:0] dataa;
output [31:0] result;
input enable, valid_in, stall_in;
output valid_out, stall_out;
reg c1_valid;
wire c1_stall;
wire c1_enable;
reg c2_valid;
wire c2_stall;
wire c2_enable;
reg c3_valid;
wire c3_stall;
wire c3_enable;
reg c4_valid;
wire c4_stall;
wire c4_enable;
reg c5_valid;
wire c5_stall;
wire c5_enable;
// Cycle 1 - convert the number to an appropriately signed value and determine the sign of the resulting number.
reg [31:0] c1_value_to_convert;
reg c1_sign;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_sign <= 1'bx;
c1_value_to_convert <= 32'dx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if (UNSIGNED == 1)
begin
c1_sign <= 1'b0;
c1_value_to_convert <= dataa;
end
else
begin
c1_sign <= dataa[31];
// Convert the value to be positive prior to conversion
c1_value_to_convert <= (dataa ^ {32{dataa[31]}}) + {1'b0, dataa[31]};
end
end
end
// Cycle 2 - initial shifting to determine the magnitude of the number
reg [31:0] c2_value_to_convert;
reg [7:0] c2_exponent;
reg c2_sign, c2_done;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
wire top_bits_0 = ~(|c1_value_to_convert[31:16]);
wire bottom_bits_0 = ~(|c1_value_to_convert[15:0]);
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_valid <= 1'b0;
c2_value_to_convert <= 32'dx;
c2_exponent <= 8'dx;
c2_sign <= 1'bx;
c2_done <= 1'bx;
end
else if (c2_enable)
begin
c2_valid <= c1_valid;
c2_sign <= c1_sign;
c2_done <= top_bits_0 & bottom_bits_0;
if (top_bits_0 & bottom_bits_0)
begin
c2_exponent <= 8'd0;
c2_value_to_convert <= c1_value_to_convert;
end
else if (top_bits_0)
begin
c2_exponent <= 8'd142; // = 8'd158 - 8'd16;
c2_value_to_convert <= {c1_value_to_convert[15:0], 16'd0};
end
else
begin
c2_exponent <= 8'd158;
c2_value_to_convert <= c1_value_to_convert;
end
end
end
// Cycle 3 - second stage of shifting
reg [31:0] c3_value_to_convert;
reg [7:0] c3_exponent;
reg c3_sign, c3_done;
assign c3_enable = (HIGH_CAPACITY == 1) ? (~c3_valid | ~c3_stall) : enable;
assign c2_stall = c3_valid & c3_stall;
wire top_12bits_0 = ~(|c2_value_to_convert[31:20]);
wire top_8bits_0 = ~(|c2_value_to_convert[31:24]);
wire top_4bits_0 = ~(|c2_value_to_convert[31:28]);
reg [1:0] c3_exp_adjust;
always@(*)
begin
if (top_12bits_0 & ~c2_done)
c3_exp_adjust = 2'd3;
else if (top_8bits_0 & ~c2_done)
c3_exp_adjust = 2'd2;
else if (top_4bits_0 & ~c2_done)
c3_exp_adjust = 2'd1;
else
c3_exp_adjust = 2'd0;
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_valid <= 1'b0;
c3_value_to_convert <= 32'dx;
c3_exponent <= 8'dx;
c3_sign <= 1'bx;
c3_done <= 1'bx;
end
else if (c3_enable)
begin
c3_valid <= c2_valid;
c3_sign <= c2_sign;
c3_done <= c2_done;
c3_exponent <= c2_exponent - {1'b0, c3_exp_adjust, 2'd0};
case (c3_exp_adjust)
2'b11: c3_value_to_convert <= {c2_value_to_convert[19:0], 12'd0};
2'b10: c3_value_to_convert <= {c2_value_to_convert[23:0], 8'd0};
2'b01: c3_value_to_convert <= {c2_value_to_convert[27:0], 4'd0};
2'b00: c3_value_to_convert <= c2_value_to_convert;
endcase
end
end
// Cycle 4 - Last stage of shifting
reg [31:0] c4_value_to_convert;
reg [7:0] c4_exponent;
reg c4_sign;
assign c4_enable = (HIGH_CAPACITY == 1) ? (~c4_valid | ~c4_stall) : enable;
assign c3_stall = c4_valid & c4_stall;
wire top_3bits_0 = ~(|c3_value_to_convert[31:29]);
wire top_2bits_0 = ~(|c3_value_to_convert[31:30]);
wire top_1bits_0 = ~(c3_value_to_convert[31]);
reg [1:0] c4_exp_adjust;
always@(*)
begin
if (top_3bits_0 & ~c3_done)
c4_exp_adjust = 2'd3;
else if (top_2bits_0 & ~c3_done)
c4_exp_adjust = 2'd2;
else if (top_1bits_0 & ~c3_done)
c4_exp_adjust = 2'd1;
else
c4_exp_adjust = 2'd0;
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_valid <= 1'b0;
c4_value_to_convert <= 32'dx;
c4_exponent <= 8'dx;
c4_sign <= 1'bx;
end
else if (c4_enable)
begin
c4_valid <= c3_valid;
c4_sign <= c3_sign;
c4_exponent <= c3_exponent - {1'b0, c4_exp_adjust};
case (c4_exp_adjust)
2'b11: c4_value_to_convert <= {c3_value_to_convert[28:0], 3'd0};
2'b10: c4_value_to_convert <= {c3_value_to_convert[29:0], 2'd0};
2'b01: c4_value_to_convert <= {c3_value_to_convert[30:0], 1'd0};
2'b00: c4_value_to_convert <= c3_value_to_convert;
endcase
end
end
// Cycle 5 - Rounding stage
reg [22:0] c5_mantissa;
reg [7:0] c5_exponent;
reg c5_sign;
assign c5_enable = (HIGH_CAPACITY == 1) ? (~c5_valid | ~c5_stall) : enable;
assign c4_stall = c5_valid & c5_stall;
wire [3:0] c5_bottom_4 = {c4_value_to_convert[8:6], |c4_value_to_convert[5:0]};
reg [24:0] c5_temp_mantissa;
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
always@(*)
begin
case (ROUNDING_MODE)
4: // 4 - round down (towards -infinity)
begin
if (UNSIGNED == 1)
begin
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]};
end
else
begin
if (|c5_bottom_4[2:0] & c4_sign)
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]};
end
end
3: // 3 - round up (towards +infinity)
begin
if (UNSIGNED == 1)
begin
if (|c5_bottom_4[2:0])
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]};
end
else
begin
if (|c5_bottom_4[2:0] & ~c4_sign)
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]};
end
end
2: // 2 - round towards zero (truncation)
begin
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]};
end
1: // 1 - round to nearest with ties away from zero
begin
if (c5_bottom_4[2])
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]};
end
default: // 0 and default are round to nearest-even.
begin
if ((&c5_bottom_4[3:2]) || (c5_bottom_4[2] & |c5_bottom_4[1:0]))
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]} + 1'b1;
else
c5_temp_mantissa <= {1'b0, c4_value_to_convert[31:8]};
end
endcase
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_valid <= 1'b0;
c5_mantissa <= 32'dx;
c5_exponent <= 8'dx;
c5_sign <= 1'bx;
end
else if (c5_enable)
begin
c5_valid <= c4_valid;
c5_sign <= c4_sign;
c5_exponent <= c4_exponent + c5_temp_mantissa[24];
c5_mantissa <= c5_temp_mantissa[24] ? c5_temp_mantissa[23:1] : c5_temp_mantissa[22:0];
end
end
assign c5_stall = stall_in;
assign result = {c5_sign, c5_exponent, c5_mantissa};
assign valid_out = c5_valid;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211O_TB_V
`define SKY130_FD_SC_LP__A211O_TB_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_lp__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211O_TB_V
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response Down-Sizer
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_7_r_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always smaller than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512.
// S_DATA_WIDTH = M_DATA_WIDTH not allowed.
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 2,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire cmd_mirror,
input wire cmd_fix,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_M_AXI_BYTES_LOG:0] cmd_step,
input wire [3-1:0] cmd_size,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for MI-side word lanes on SI-side.
genvar word_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// .
localparam [24-1:0] C_DOUBLE_LEN = 24'b0000_0000_0000_0000_1111_1111;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
reg first_word;
reg [C_S_AXI_BYTES_LOG-1:0] current_word_1;
reg [C_S_AXI_BYTES_LOG-1:0] current_word;
wire [C_S_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire [C_RATIO_LOG-1:0] current_index;
wire last_beat;
wire last_word;
wire new_si_word;
reg [C_S_AXI_BYTES_LOG-1:0] size_mask;
// Sub-word handling for the next cycle.
wire [C_S_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Loading of new rresp data.
wire load_rresp;
reg need_to_update_rresp;
reg [2-1:0] S_AXI_RRESP_ACC;
// Detect start of MI word.
wire first_si_in_mi;
wire first_mi_in_si;
// Throttling help signals.
wire word_completed;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal SI-side control signals.
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_II;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
reg [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
//
/////////////////////////////////////////////////////////////////////////////
// Generate address bits used for SI-side transaction size.
always @ *
begin
case (cmd_size)
3'b000: size_mask = C_DOUBLE_LEN[8 +: C_S_AXI_BYTES_LOG];
3'b001: size_mask = C_DOUBLE_LEN[7 +: C_S_AXI_BYTES_LOG];
3'b010: size_mask = C_DOUBLE_LEN[6 +: C_S_AXI_BYTES_LOG];
3'b011: size_mask = C_DOUBLE_LEN[5 +: C_S_AXI_BYTES_LOG];
3'b100: size_mask = C_DOUBLE_LEN[4 +: C_S_AXI_BYTES_LOG];
3'b101: size_mask = C_DOUBLE_LEN[3 +: C_S_AXI_BYTES_LOG];
3'b110: size_mask = C_DOUBLE_LEN[2 +: C_S_AXI_BYTES_LOG];
3'b111: size_mask = C_DOUBLE_LEN[1 +: C_S_AXI_BYTES_LOG]; // Illegal setting.
endcase
end
// Detect when MI-side word is completely assembled.
assign word_completed = ( cmd_fix ) |
( cmd_mirror ) |
( ~cmd_fix & ( ( next_word & size_mask ) == {C_S_AXI_BYTES_LOG{1'b0}} ) ) |
( ~cmd_fix & last_word );
// Pop word from SI-side.
assign M_AXI_RREADY_I = cmd_valid & (S_AXI_RREADY_I | ~word_completed);
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & word_completed & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_RVALID & M_AXI_RREADY_I;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Read transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offset points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be extracted, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first MI-side data beat.
//
// First MI is set during the first MI-side data beat.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each generated MI word it is decreased
// until Last Beat is reached.
//
// Last word is determined depending as the last MI-side word generated for
// the command (generated from the AW translation).
// If burst aren't supported all MI-side words are concidered to be the last.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple MI words per SI word
always @ *
begin
if ( first_word | cmd_fix )
current_word = cmd_first_word;
else
current_word = current_word_1;
end
// Calculate next word.
assign next_word = ( current_word + cmd_step ) & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = current_word + cmd_offset;
// Get the ratio bits (MI-side words vs SI-side words).
assign current_index = current_word_adjusted[C_S_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG];
// Prepare next word address.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
current_word_1 <= 'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
// Prepare for next access.
first_word <= 1'b1;
end else begin
first_word <= 1'b0;
end
current_word_1 <= next_word;
end
end
end
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 8'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat );
// Detect new SI-side data word.
assign new_si_word = ( current_word == {C_S_AXI_BYTES_LOG{1'b0}} );
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions).
//
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_RID_I = cmd_id;
// Handle last flag, i.e. set for SI-side last word.
assign S_AXI_RLAST_I = M_AXI_RLAST & ~cmd_split;
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of RRESP.
//
// The accumulated RRESP register is updated for each MI-side response that
// is used in an SI-side word, i.e. the worst status for all included data
// so far.
//
/////////////////////////////////////////////////////////////////////////////
// Detect first SI-side word per MI-side word.
assign first_si_in_mi = cmd_mirror |
first_mi_word |
( ~cmd_mirror & ( ( current_word & size_mask ) == {C_S_AXI_BYTES_LOG{1'b0}} ) );
// Force load accumulated RRESPs to first value or continously for non split.
assign load_rresp = first_si_in_mi;
// Update if more critical.
always @ *
begin
case (S_AXI_RRESP_ACC)
C_RESP_EXOKAY: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_OKAY |
M_AXI_RRESP == C_RESP_SLVERROR |
M_AXI_RRESP == C_RESP_DECERR );
C_RESP_OKAY: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_SLVERROR |
M_AXI_RRESP == C_RESP_DECERR );
C_RESP_SLVERROR: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_DECERR );
C_RESP_DECERR: need_to_update_rresp = 1'b0;
endcase
end
// Select accumultated or direct depending on setting.
always @ *
begin
if ( load_rresp || need_to_update_rresp ) begin
S_AXI_RRESP_I = M_AXI_RRESP;
end else begin
S_AXI_RRESP_I = S_AXI_RRESP_ACC;
end
end
// Accumulate MI-side RRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_RRESP_ACC <= S_AXI_RRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Demultiplex data to form complete data word.
//
/////////////////////////////////////////////////////////////////////////////
// Registers and combinatorial data MI-word size mux.
generate
for (word_cnt = 0; word_cnt < (2 ** C_RATIO_LOG) ; word_cnt = word_cnt + 1) begin : WORD_LANE
// Generate extended write data and strobe.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else begin
if ( pop_si_data ) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else if ( current_index == word_cnt & pop_mi_data ) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= M_AXI_RDATA;
end
end
end
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_index == word_cnt ) | cmd_mirror ) begin
S_AXI_RDATA_I[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] = M_AXI_RDATA;
end else begin
S_AXI_RDATA_I[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] =
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH];
end
end
end // end for word_cnt
endgenerate
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
endmodule
|
`timescale 1ns / 1ps
module PS2_Controller #(parameter INITIALIZE_MOUSE = 0) (
// Inputs
CLOCK_50,
reset,
the_command,
send_command,
// Bidirectionals
PS2_CLK, // PS2 Clock
PS2_DAT, // PS2 Data
// Outputs
command_was_sent,
error_communication_timed_out,
received_data,
received_data_en // If 1 - new data has been received
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input CLOCK_50;
input reset;
input [7:0] the_command;
input send_command;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output command_was_sent;
output error_communication_timed_out;
output [7:0] received_data;
output received_data_en;
wire [7:0] the_command_w;
wire send_command_w, command_was_sent_w, error_communication_timed_out_w;
generate
if(INITIALIZE_MOUSE) begin
assign the_command_w = init_done ? the_command : 8'hf4;
assign send_command_w = init_done ? send_command : (!command_was_sent_w && !error_communication_timed_out_w);
assign command_was_sent = init_done ? command_was_sent_w : 0;
assign error_communication_timed_out = init_done ? error_communication_timed_out_w : 1;
reg init_done;
always @(posedge CLOCK_50)
if(reset) init_done <= 0;
else if(command_was_sent_w) init_done <= 1;
end else begin
assign the_command_w = the_command;
assign send_command_w = send_command;
assign command_was_sent = command_was_sent_w;
assign error_communication_timed_out = error_communication_timed_out_w;
end
endgenerate
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
localparam PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
wire ps2_clk_posedge;
wire ps2_clk_negedge;
wire start_receiving_data;
wire wait_for_incoming_data;
// Internal Registers
reg [7:0] idle_counter;
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
// State Machine Registers
reg [2:0] ns_ps2_transceiver;
reg [2:0] s_ps2_transceiver;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
s_ps2_transceiver <= PS2_STATE_0_IDLE;
else
s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*)
begin
// Defaults
ns_ps2_transceiver = PS2_STATE_0_IDLE;
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if ((idle_counter == 8'hFF) &&
(send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else
ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
if ((received_data_en == 1'b1)/* && (ps2_clk_posedge == 1'b1)*/)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if ((command_was_sent == 1'b1) ||
(error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if (received_data_en == 1'b1)
begin
if (send_command == 1'b0)
ns_ps2_transceiver = PS2_STATE_0_IDLE;
else
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else
begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= PS2_CLK;
ps2_data_reg <= PS2_DAT;
end
end
always @(posedge CLOCK_50)
begin
if (reset == 1'b1)
idle_counter <= 6'h00;
else if ((s_ps2_transceiver == PS2_STATE_0_IDLE) &&
(idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign ps2_clk_posedge =
((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge =
((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data =
(s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
Altera_UP_PS2_Data_In PS2_Data_In (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
// Bidirectionals
// Outputs
.received_data (received_data),
.received_data_en (received_data_en)
);
Altera_UP_PS2_Command_Out PS2_Command_Out (
// Inputs
.clk (CLOCK_50),
.reset (reset),
.the_command (the_command_w),
.send_command (send_command_w),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
// Bidirectionals
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// Outputs
.command_was_sent (command_was_sent_w),
.error_communication_timed_out (error_communication_timed_out_w)
);
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_3.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_3) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_3_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_3_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_3_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_3",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_3" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_3_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
//assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
// To Fix CR855535
assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_3_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_3_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_3_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_3
#(parameter C_CORENAME = "blk_mem_gen_v8_3_3",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_3_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_3_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
/****************************************************************************************
*
* File Name: IS42S16320.V
* Version: 1.1
* Date: Oct 8th, 2003
* Model: BUS Functional
* Simulator: Model Technology
* Modify Timing parametre and check to fit other speed
* Model: IC42S16320 -7
****************************************************************************************/
`timescale 1ns / 1ps
module IS42S16320 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);
parameter addr_bits = 13;
parameter data_bits = 16;
parameter col_bits = 10;
parameter mem_sizes = 8388608;
inout [data_bits - 1 : 0] Dq;
input [addr_bits - 1 : 0] Addr;
input [1 : 0] Ba;
input Clk;
input Cke;
input Cs_n;
input Ras_n;
input Cas_n;
input We_n;
input [1 : 0] Dqm;
reg [data_bits - 1 : 0] Bank0 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes];
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes];
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline
reg [1 : 0] Dqm_reg0, Dqm_reg1; // DQM Operation Pipeline
reg [addr_bits - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;
reg [addr_bits - 1 : 0] Mode_reg;
reg [data_bits - 1 : 0] Dq_reg, Dq_dqm;
reg [col_bits - 1 : 0] Col_temp, Burst_counter;
reg Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg Pc_b0, Pc_b1, Pc_b2, Pc_b3; // Bank Precharge
reg [1 : 0] Bank_precharge [0 : 3]; // Precharge Command
reg A10_precharge [0 : 3]; // Addr[10] = 1 (All banks)
reg Auto_precharge [0 : 3]; // RW Auto Precharge (Bank)
reg Read_precharge [0 : 3]; // R Auto Precharge
reg Write_precharge [0 : 3]; // W Auto Precharge
reg RW_interrupt_read [0 : 3]; // RW Interrupt Read with Auto Precharge
reg RW_interrupt_write [0 : 3]; // RW Interrupt Write with Auto Precharge
reg [1 : 0] RW_interrupt_bank; // RW Interrupt Bank
integer RW_interrupt_counter [0 : 3]; // RW Interrupt Counter
integer Count_precharge [0 : 3]; // RW Auto Precharge Counter
reg Data_in_enable;
reg Data_out_enable;
reg [1 : 0] Bank, Prev_bank;
reg [addr_bits - 1 : 0] Row;
reg [col_bits - 1 : 0] Col, Col_brst;
// Internal system clock
reg CkeZ, Sys_clk;
// Commands Decode
wire Active_enable = ~Cs_n & ~Ras_n & Cas_n & We_n;
wire Aref_enable = ~Cs_n & ~Ras_n & ~Cas_n & We_n;
wire Burst_term = ~Cs_n & Ras_n & Cas_n & ~We_n;
wire Mode_reg_enable = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire Prech_enable = ~Cs_n & ~Ras_n & Cas_n & ~We_n;
wire Read_enable = ~Cs_n & Ras_n & ~Cas_n & We_n;
wire Write_enable = ~Cs_n & Ras_n & ~Cas_n & ~We_n;
// Burst Length Decode
wire Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] & Mode_reg[0];
wire Burst_length_4 = ~Mode_reg[2] & Mode_reg[1] & ~Mode_reg[0];
wire Burst_length_8 = ~Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
wire Burst_length_f = Mode_reg[2] & Mode_reg[1] & Mode_reg[0];
// CAS Latency Decode
wire Cas_latency_2 = ~Mode_reg[6] & Mode_reg[5] & ~Mode_reg[4];
wire Cas_latency_3 = ~Mode_reg[6] & Mode_reg[5] & Mode_reg[4];
// Write Burst Mode
wire Write_burst_mode = Mode_reg[9];
wire Dq_chk = Sys_clk & Data_in_enable; // Check setup/hold time for DQ
assign Dq = Dq_reg; // DQ buffer
// Commands Operation
`define ACT 0
`define NOP 1
`define READ 2
`define WRITE 3
`define PRECH 4
`define A_REF 5
`define BST 6
`define LMR 7
//***********************************************************************
// Timing Parameters for -7
parameter tAC = 5.4; // CAS=3
parameter tHZ = 5.4;
parameter tOH = 2.7; //CAS=3
parameter tMRD = 2.0; // 2 Clk Cycles, 10 ns
parameter tRAS = 45.0;
parameter tRC = 70.0;
parameter tRCD = 20.0;
parameter tRP = 20.0;
parameter tRRD = 14.0;
parameter tDPL = 14.0; //
//************************************************************************
// Timing Check variable
time MRD_chk;
time DPL_chkm [0 : 3];
time RC_chk, RRD_chk;
time RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time RP_chk0, RP_chk1, RP_chk2, RP_chk3;
initial begin
Dq_reg = {data_bits{1'bz}};
Data_in_enable = 0; Data_out_enable = 0;
Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
DPL_chkm[0] = 0; DPL_chkm[1] = 0; DPL_chkm[2] = 0; DPL_chkm[3] = 0;
RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0;
RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0;
RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
MRD_chk = 0; RC_chk = 0; RRD_chk = 0;
RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
$timeformat (-9, 1, " ns", 12);
end
// System clock generator
always begin
@ (posedge Clk) begin
Sys_clk = CkeZ;
CkeZ = Cke;
end
@ (negedge Clk) begin
Sys_clk = 1'b0;
end
end
always @ (posedge Sys_clk) begin
// Internal Commamd Pipelined
Command[0] = Command[1];
Command[1] = Command[2];
Command[2] = Command[3];
Command[3] = `NOP;
Col_addr[0] = Col_addr[1];
Col_addr[1] = Col_addr[2];
Col_addr[2] = Col_addr[3];
Col_addr[3] = {col_bits{1'b0}};
Bank_addr[0] = Bank_addr[1];
Bank_addr[1] = Bank_addr[2];
Bank_addr[2] = Bank_addr[3];
Bank_addr[3] = 2'b0;
Bank_precharge[0] = Bank_precharge[1];
Bank_precharge[1] = Bank_precharge[2];
Bank_precharge[2] = Bank_precharge[3];
Bank_precharge[3] = 2'b0;
A10_precharge[0] = A10_precharge[1];
A10_precharge[1] = A10_precharge[2];
A10_precharge[2] = A10_precharge[3];
A10_precharge[3] = 1'b0;
// Dqm pipeline for Read
Dqm_reg0 = Dqm_reg1;
Dqm_reg1 = Dqm;
// Read or Write with Auto Precharge Counter
if (Auto_precharge[0] === 1'b1) begin
Count_precharge[0] = Count_precharge[0] + 1;
end
if (Auto_precharge[1] === 1'b1) begin
Count_precharge[1] = Count_precharge[1] + 1;
end
if (Auto_precharge[2] === 1'b1) begin
Count_precharge[2] = Count_precharge[2] + 1;
end
if (Auto_precharge[3] === 1'b1) begin
Count_precharge[3] = Count_precharge[3] + 1;
end
// Read or Write Interrupt Counter
if (RW_interrupt_write[0] === 1'b1) begin
RW_interrupt_counter[0] = RW_interrupt_counter[0] + 1;
end
if (RW_interrupt_write[1] === 1'b1) begin
RW_interrupt_counter[1] = RW_interrupt_counter[1] + 1;
end
if (RW_interrupt_write[2] === 1'b1) begin
RW_interrupt_counter[2] = RW_interrupt_counter[2] + 1;
end
if (RW_interrupt_write[3] === 1'b1) begin
RW_interrupt_counter[3] = RW_interrupt_counter[3] + 1;
end
// tMRD Counter
MRD_chk = MRD_chk + 1;
// Auto Refresh
if (Aref_enable === 1'b1) begin
// Auto Refresh to Auto Refresh
if ($time - RC_chk < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Auto Refresh", $time);
end
// Precharge to Auto Refresh
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Auto Refresh", $time);
end
// Precharge to Refresh
if (Pc_b0 === 1'b0 || Pc_b1 === 1'b0 || Pc_b2 === 1'b0 || Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: All banks must be Precharge before Auto Refresh", $time);
end
// Load Mode Register to Auto Refresh
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Auto Refresh", $time);
end
// Record Current tRC time
RC_chk = $time;
end
// Load Mode Register
if (Mode_reg_enable === 1'b1) begin
// Register Mode
Mode_reg = Addr;
// Precharge to Load Mode Register
if (Pc_b0 === 1'b0 && Pc_b1 === 1'b0 && Pc_b2 === 1'b0 && Pc_b3 === 1'b0) begin
$display ("%m : at time %t ERROR: all banks must be Precharge before Load Mode Register", $time);
end
// Precharge to Load Mode Register
if (($time - RP_chk0 < tRP) || ($time - RP_chk1 < tRP) ||
($time - RP_chk2 < tRP) || ($time - RP_chk3 < tRP)) begin
$display ("%m : at time %t ERROR: tRP violation during Load Mode Register", $time);
end
// Auto Refresh to Load Mode Register
if ($time - RC_chk < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Load Mode Register", $time);
end
// Load Mode Register to Load Mode Register
if (MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violation during Load Mode Register", $time);
end
// Reset MRD Counter
MRD_chk = 0;
end
// Active Block (Latch Bank Address and Row Address)
if (Active_enable === 1'b1) begin
// Activate Bank 0
if (Ba === 2'b00 && Pc_b0 === 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk0 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 0", $time);
end
// Precharge to Activate Bank 0
if ($time - RP_chk0 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 0", $time);
end
// Record variables
Act_b0 = 1'b1;
Pc_b0 = 1'b0;
B0_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk0 = $time;
RC_chk0 = $time;
RCD_chk0 = $time;
end
if (Ba == 2'b01 && Pc_b1 == 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk1 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 1", $time);
end
// Precharge to Activate Bank 1
if ($time - RP_chk1 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 1", $time);
end
// Record variables
Act_b1 = 1'b1;
Pc_b1 = 1'b0;
B1_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk1 = $time;
RC_chk1 = $time;
RCD_chk1 = $time;
end
if (Ba == 2'b10 && Pc_b2 == 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk2 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 2", $time);
end
// Precharge to Activate Bank 2
if ($time - RP_chk2 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 2", $time);
end
// Record variables
Act_b2 = 1'b1;
Pc_b2 = 1'b0;
B2_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk2 = $time;
RC_chk2 = $time;
RCD_chk2 = $time;
end
if (Ba == 2'b11 && Pc_b3 == 1'b1) begin
// ACTIVE to ACTIVE command period
if ($time - RC_chk3 < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank 3", $time);
end
// Precharge to Activate Bank 3
if ($time - RP_chk3 < tRP) begin
$display ("%m : at time %t ERROR: tRP violation during Activate bank 3", $time);
end
// Record variables
Act_b3 = 1'b1;
Pc_b3 = 1'b0;
B3_row_addr = Addr [addr_bits - 1 : 0];
RAS_chk3 = $time;
RC_chk3 = $time;
RCD_chk3 = $time;
end
// Active Bank A to Active Bank B
if ((Prev_bank != Ba) && ($time - RRD_chk < tRRD)) begin
$display ("%m : at time %t ERROR: tRRD violation during Activate bank = %d", $time, Ba);
end
// Auto Refresh to Activate
if ($time - RC_chk < tRC) begin
$display ("%m : at time %t ERROR: tRC violation during Activate bank = %d", $time, Ba);
end
// Load Mode Register to Active
if (MRD_chk < tMRD ) begin
$display ("%m : at time %t ERROR: tMRD violation during Activate bank = %d", $time, Ba);
end
// Record variables for checking violation
RRD_chk = $time;
Prev_bank = Ba;
end
// Precharge Block
if (Prech_enable == 1'b1) begin
// Load Mode Register to Precharge
if ($time - MRD_chk < tMRD) begin
$display ("%m : at time %t ERROR: tMRD violaiton during Precharge", $time);
end
// Precharge Bank 0
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b00)) && Act_b0 === 1'b1) begin
Act_b0 = 1'b0;
Pc_b0 = 1'b1;
RP_chk0 = $time;
// Activate to Precharge
if ($time - RAS_chk0 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[0] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Precharge Bank 1
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b01)) && Act_b1 === 1'b1) begin
Act_b1 = 1'b0;
Pc_b1 = 1'b1;
RP_chk1 = $time;
// Activate to Precharge
if ($time - RAS_chk1 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[1] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Precharge Bank 2
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b10)) && Act_b2 === 1'b1) begin
Act_b2 = 1'b0;
Pc_b2 = 1'b1;
RP_chk2 = $time;
// Activate to Precharge
if ($time - RAS_chk2 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[2] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Precharge Bank 3
if ((Addr[10] === 1'b1 || (Addr[10] === 1'b0 && Ba === 2'b11)) && Act_b3 === 1'b1) begin
Act_b3 = 1'b0;
Pc_b3 = 1'b1;
RP_chk3 = $time;
// Activate to Precharge
if ($time - RAS_chk3 < tRAS) begin
$display ("%m : at time %t ERROR: tRAS violation during Precharge", $time);
end
// tDPL violation check for write
if ($time - DPL_chkm[3] < tDPL) begin
$display ("%m : at time %t ERROR: tDPL violation during Precharge", $time);
end
end
// Terminate a Write Immediately (if same bank or all banks)
if (Data_in_enable === 1'b1 && (Bank === Ba || Addr[10] === 1'b1)) begin
Data_in_enable = 1'b0;
end
// Precharge Command Pipeline for Read
if (Cas_latency_3 === 1'b1) begin
Command[2] = `PRECH;
Bank_precharge[2] = Ba;
A10_precharge[2] = Addr[10];
end else if (Cas_latency_2 === 1'b1) begin
Command[1] = `PRECH;
Bank_precharge[1] = Ba;
A10_precharge[1] = Addr[10];
end
end
// Burst terminate
if (Burst_term === 1'b1) begin
// Terminate a Write Immediately
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
end
// Terminate a Read Depend on CAS Latency
if (Cas_latency_3 === 1'b1) begin
Command[2] = `BST;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `BST;
end
end
// Read, Write, Column Latch
if (Read_enable === 1'b1) begin
// Check to see if bank is open (ACT)
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Read", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// CAS Latency pipeline
if (Cas_latency_3 == 1'b1) begin
Command[2] = `READ;
Col_addr[2] = Addr;
Bank_addr[2] = Ba;
end else if (Cas_latency_2 == 1'b1) begin
Command[1] = `READ;
Col_addr[1] = Addr;
Bank_addr[1] = Ba;
end
// Read interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
RW_interrupt_counter[RW_interrupt_bank] = 0;
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Read_precharge[Ba] = 1'b1;
end
end
// Write Command
if (Write_enable == 1'b1) begin
// Activate to Write
if ((Ba == 2'b00 && Pc_b0 == 1'b1) || (Ba == 2'b01 && Pc_b1 == 1'b1) ||
(Ba == 2'b10 && Pc_b2 == 1'b1) || (Ba == 2'b11 && Pc_b3 == 1'b1)) begin
$display("%m : at time %t ERROR: Bank is not Activated for Write", $time);
end
// Activate to Read or Write
if ((Ba == 2'b00) && ($time - RCD_chk0 < tRCD) ||
(Ba == 2'b01) && ($time - RCD_chk1 < tRCD) ||
(Ba == 2'b10) && ($time - RCD_chk2 < tRCD) ||
(Ba == 2'b11) && ($time - RCD_chk3 < tRCD)) begin
$display("%m : at time %t ERROR: tRCD violation during Read", $time);
end
// Latch Write command, Bank, and Column
Command[0] = `WRITE;
Col_addr[0] = Addr;
Bank_addr[0] = Ba;
// Write interrupt Write (terminate Write immediately)
if (Data_in_enable == 1'b1) begin
Data_in_enable = 1'b0;
// Interrupting a Write with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Write_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_write[RW_interrupt_bank] = 1'b1;
end
end
// Write interrupt Read (terminate Read immediately)
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
// Interrupting a Read with Autoprecharge
if (Auto_precharge[RW_interrupt_bank] == 1'b1 && Read_precharge[RW_interrupt_bank] == 1'b1) begin
RW_interrupt_read[RW_interrupt_bank] = 1'b1;
end
end
// Write with Auto Precharge
if (Addr[10] == 1'b1) begin
Auto_precharge[Ba] = 1'b1;
Count_precharge[Ba] = 0;
RW_interrupt_bank = Ba;
Write_precharge[Ba] = 1'b1;
end
end
/*
Write with Auto Precharge Calculation
The device start internal precharge when:
1. Meet minimum tRAS requirement
and 2. tDPL cycle(s) after last valid data
or 3. Interrupt by a Read or Write (with or without Auto
Precharge)
Note: Model is starting the internal precharge 1 cycle after
they meet all the
requirement but tRP will be compensate for the time after
the 1 cycle.
*/
if ((Auto_precharge[0] == 1'b1) && (Write_precharge[0] == 1'b1))
begin
if ((($time - RAS_chk0 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [0] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [0] >= 8))) ||
(RW_interrupt_write[0] == 1'b1 && RW_interrupt_counter[0] >= 1)) begin // Case 3
Auto_precharge[0] = 1'b0;
Write_precharge[0] = 1'b0;
RW_interrupt_write[0] = 1'b0;
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time + tDPL;
end
end
if ((Auto_precharge[1] == 1'b1) && (Write_precharge[1] == 1'b1))
begin
if ((($time - RAS_chk1 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [1] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [1] >= 8))) ||
(RW_interrupt_write[1] == 1'b1 && RW_interrupt_counter[1] >= 1)) begin // Case 3
Auto_precharge[1] = 1'b0;
Write_precharge[1] = 1'b0;
RW_interrupt_write[1] = 1'b0;
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time + tDPL;
end
end
if ((Auto_precharge[2] == 1'b1) && (Write_precharge[2] == 1'b1))
begin
if ((($time - RAS_chk2 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [2] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [2] >= 8))) ||
(RW_interrupt_write[2] == 1'b1 && RW_interrupt_counter[2] >= 1)) begin // Case 3
Auto_precharge[2] = 1'b0;
Write_precharge[2] = 1'b0;
RW_interrupt_write[2] = 1'b0;
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time + tDPL;
end
// end
end
if ((Auto_precharge[3] == 1'b1) && (Write_precharge[3] == 1'b1))
begin
if ((($time - RAS_chk3 >= tRAS) &&
// Case 1
(((Burst_length_1 == 1'b1 || Write_burst_mode == 1'b1) && Count_precharge [3] >= 1) || // Case 2
(Burst_length_2 == 1'b1 && Count_precharge [3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge [3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge [3] >= 8))) ||
(RW_interrupt_write[3] == 1'b1 && RW_interrupt_counter[3] >= 1)) begin // Case 3
Auto_precharge[3] = 1'b0;
Write_precharge[3] = 1'b0;
RW_interrupt_write[3] = 1'b0;
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time + tDPL;
end
end
// Read with Auto Precharge Calculation
// The device start internal precharge:
// 1. Meet minimum tRAS requirement
// and 2. CAS Latency - 1 cycles before last burst
// or 3. Interrupt by a Read or Write (with or without AutoPrecharge)
if ((Auto_precharge[0] == 1'b1) && (Read_precharge[0] == 1'b1))
begin
if ((($time - RAS_chk0 >= tRAS) &&
// Case 1
((Burst_length_1 == 1'b1 && Count_precharge[0] >= 1) ||
// Case 2
(Burst_length_2 == 1'b1 && Count_precharge[0] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[0] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[0] >= 8))) ||
(RW_interrupt_read[0] == 1'b1)) begin
// Case 3
Pc_b0 = 1'b1;
Act_b0 = 1'b0;
RP_chk0 = $time;
Auto_precharge[0] = 1'b0;
Read_precharge[0] = 1'b0;
RW_interrupt_read[0] = 1'b0;
end
end
if ((Auto_precharge[1] == 1'b1) && (Read_precharge[1] == 1'b1))
begin
if ((($time - RAS_chk1 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[1] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[1] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[1] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[1] >= 8))) ||
(RW_interrupt_read[1] == 1'b1)) begin
Pc_b1 = 1'b1;
Act_b1 = 1'b0;
RP_chk1 = $time;
Auto_precharge[1] = 1'b0;
Read_precharge[1] = 1'b0;
RW_interrupt_read[1] = 1'b0;
end
end
if ((Auto_precharge[2] == 1'b1) && (Read_precharge[2] == 1'b1))
begin
if ((($time - RAS_chk2 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[2] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[2] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[2] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[2] >= 8))) ||
(RW_interrupt_read[2] == 1'b1)) begin
Pc_b2 = 1'b1;
Act_b2 = 1'b0;
RP_chk2 = $time;
Auto_precharge[2] = 1'b0;
Read_precharge[2] = 1'b0;
RW_interrupt_read[2] = 1'b0;
end
end
if ((Auto_precharge[3] == 1'b1) && (Read_precharge[3] == 1'b1))
begin
if ((($time - RAS_chk3 >= tRAS) &&
((Burst_length_1 == 1'b1 && Count_precharge[3] >= 1) ||
(Burst_length_2 == 1'b1 && Count_precharge[3] >= 2) ||
(Burst_length_4 == 1'b1 && Count_precharge[3] >= 4) ||
(Burst_length_8 == 1'b1 && Count_precharge[3] >= 8))) ||
(RW_interrupt_read[3] == 1'b1)) begin
Pc_b3 = 1'b1;
Act_b3 = 1'b0;
RP_chk3 = $time;
Auto_precharge[3] = 1'b0;
Read_precharge[3] = 1'b0;
RW_interrupt_read[3] = 1'b0;
end
end
// Internal Precharge or Bst
if (Command[0] == `PRECH) begin // Precharge terminate a read with same bank or all banks
if (Bank_precharge[0] == Bank || A10_precharge[0] == 1'b1) begin
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
end else if (Command[0] == `BST) begin // BST terminate a read to current bank
if (Data_out_enable == 1'b1) begin
Data_out_enable = 1'b0;
end
end
if (Data_out_enable == 1'b0) begin
Dq_reg <= #tOH {data_bits{1'bz}};
end
// Detect Read or Write command
if (Command[0] == `READ) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b0;
Data_out_enable = 1'b1;
end else if (Command[0] == `WRITE) begin
Bank = Bank_addr[0];
Col = Col_addr[0];
Col_brst = Col_addr[0];
case (Bank_addr[0])
2'b00 : Row = B0_row_addr;
2'b01 : Row = B1_row_addr;
2'b10 : Row = B2_row_addr;
2'b11 : Row = B3_row_addr;
endcase
Burst_counter = 0;
Data_in_enable = 1'b1;
Data_out_enable = 1'b0;
end
// DQ buffer (Driver/Receiver)
if (Data_in_enable == 1'b1) begin
// Writing Data to Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0 [{Row, Col}];
2'b01 : Dq_dqm = Bank1 [{Row, Col}];
2'b10 : Dq_dqm = Bank2 [{Row, Col}];
2'b11 : Dq_dqm = Bank3 [{Row, Col}];
endcase
// Dqm operation
if (Dqm[0] == 1'b0) begin
Dq_dqm [ 7 : 0] = Dq [ 7 : 0];
end
if (Dqm[1] == 1'b0) begin
Dq_dqm [15 : 8] = Dq [15 : 8];
end
// Write to memory
case (Bank)
2'b00 : Bank0 [{Row, Col}] = Dq_dqm;
2'b01 : Bank1 [{Row, Col}] = Dq_dqm;
2'b10 : Bank2 [{Row, Col}] = Dq_dqm;
2'b11 : Bank3 [{Row, Col}] = Dq_dqm;
endcase
if (Dqm !== 2'b11) begin
// Record tDPL for manual precharge
DPL_chkm [Bank] = $time;
end
// Advance burst counter subroutine
#tHZ Burst_decode;
end else if (Data_out_enable == 1'b1) begin
// Reading Data from Memory
// Array buffer
case (Bank)
2'b00 : Dq_dqm = Bank0[{Row, Col}];
2'b01 : Dq_dqm = Bank1[{Row, Col}];
2'b10 : Dq_dqm = Bank2[{Row, Col}];
2'b11 : Dq_dqm = Bank3[{Row, Col}];
endcase
// Dqm operation
if (Dqm_reg0 [0] == 1'b1) begin
Dq_dqm [ 7 : 0] = 8'bz;
end
if (Dqm_reg0 [1] == 1'b1) begin
Dq_dqm [15 : 8] = 8'bz;
end
if (Dqm_reg0 !== 2'b11) begin
Dq_reg = #tAC Dq_dqm;
end else begin
Dq_reg = #tHZ {data_bits{1'bz}};
end
// Advance burst counter subroutine
Burst_decode;
end
end
// Burst counter decode
task Burst_decode;
begin
// Advance Burst Counter
Burst_counter = Burst_counter + 1;
// Burst Type
if (Mode_reg[3] == 1'b0) begin
// Sequential Burst
Col_temp = Col + 1;
end else if (Mode_reg[3] == 1'b1) begin
// Interleaved Burst
Col_temp[2] = Burst_counter[2] ^ Col_brst[2];
Col_temp[1] = Burst_counter[1] ^ Col_brst[1];
Col_temp[0] = Burst_counter[0] ^ Col_brst[0];
end
// Burst Length
if (Burst_length_2) begin
// Burst Length = 2
Col [0] = Col_temp [0];
end else if (Burst_length_4) begin
// Burst Length = 4
Col [1 : 0] = Col_temp [1 : 0];
end else if (Burst_length_8) begin
// Burst Length = 8
Col [2 : 0] = Col_temp [2 : 0];
end else begin
// Burst Length = FULL
Col = Col_temp;
end
// Burst Read Single Write
if (Write_burst_mode == 1'b1) begin
Data_in_enable = 1'b0;
end
// Data Counter
if (Burst_length_1 == 1'b1) begin
if (Burst_counter >= 1) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_2 == 1'b1) begin
if (Burst_counter >= 2) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_4 == 1'b1) begin
if (Burst_counter >= 4) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end else if (Burst_length_8 == 1'b1) begin
if (Burst_counter >= 8) begin
Data_in_enable = 1'b0;
Data_out_enable = 1'b0;
end
end
end
endtask
// *************************************************************************************
// Timing Parameters for -7
specify
specparam
tAH = 0.8, // Addr, Ba Hold Time
tAS = 1.5, // Addr, Ba Setup Time
tCH = 2.5, // Clock High-Level Width
tCL = 2.5, // Clock Low-Level Width
tCK = 7.0, // Clock Cycle Time,cas=3
tDH = 0.8, // Data-in Hold Time
tDS = 1.5, // Data-in Setup Time
tCKH = 0.8, // CKE Hold Time
tCKS = 1.5, // CKE Setup Time
tCMH = 0.8, // CS#, RAS#, CAS#, WE#, DQM# Hold Time
tCMS = 1.5; // CS#, RAS#, CAS#, WE#, DQM# Setup Time
// ************************************************************************
$width (posedge Clk, tCH);
$width (negedge Clk, tCL);
$period (negedge Clk, tCK);
$period (posedge Clk, tCK);
$setuphold(posedge Clk, Cke, tCKS, tCKH);
$setuphold(posedge Clk, Cs_n, tCMS, tCMH);
$setuphold(posedge Clk, Cas_n, tCMS, tCMH);
$setuphold(posedge Clk, Ras_n, tCMS, tCMH);
$setuphold(posedge Clk, We_n, tCMS, tCMH);
$setuphold(posedge Clk, Addr, tAS, tAH);
$setuphold(posedge Clk, Ba, tAS, tAH);
$setuphold(posedge Clk, Dqm, tCMS, tCMH);
$setuphold(posedge Dq_chk, Dq, tDS, tDH);
endspecify
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// parameters for array sizes
localparam WA = 8; // address dimension size
localparam WB = 8; // bit dimension size
localparam NO = 10; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// msg926
logic [3:0][31:0] packedArray;
initial packedArray <= '0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) array_bg <= '0;
else if (cnt[30:2]==1) array_bg <= '0;
else if (cnt[30:2]==2) array_bg <= '0;
else if (cnt[30:2]==3) array_bg <= '0;
else if (cnt[30:2]==4) array_bg <= '0;
else if (cnt[30:2]==5) array_bg <= '0;
else if (cnt[30:2]==6) array_bg <= '0;
else if (cnt[30:2]==7) array_bg <= '0;
else if (cnt[30:2]==8) array_bg <= '0;
else if (cnt[30:2]==9) array_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (array_bg !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (array_bg !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (array_bg !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==6) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==8) begin if (array_bg !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==9) begin if (array_bg !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_bg); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) array_lt <= '0;
else if (cnt[30:2]==1) array_lt <= '0;
else if (cnt[30:2]==2) array_lt <= '0;
else if (cnt[30:2]==3) array_lt <= '0;
else if (cnt[30:2]==4) array_lt <= '0;
else if (cnt[30:2]==5) array_lt <= '0;
else if (cnt[30:2]==6) array_lt <= '0;
else if (cnt[30:2]==7) array_lt <= '0;
else if (cnt[30:2]==8) array_lt <= '0;
else if (cnt[30:2]==9) array_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (array_lt !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (array_lt !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (array_lt !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==7) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==8) begin if (array_lt !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==9) begin if (array_lt !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_lt); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/05/2016 06:16:20 PM
// Design Name:
// Module Name: FPU_Multiplication_Function_v2
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_v2
//SINGLE PRECISION PARAMETERS
/*# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
RecursiveKOA #(.SW(SW+1), .Opt_FPGA_ASIC(1)) Sgf_operation (
.clk(clk),
.rst(rst),
.load_b_i(FSM_load_second_step),
.Data_A_i({1'b1,Op_MX[SW-1:0]}),
.Data_B_i({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o(P_Sgf)
);
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
// P-D unit (instruction decoder)
module pd(
input clk_sys,
input [0:15] w, // internal W bus
input strob1, // STROB1
input strob1b, // STROB1 back
input w_ir, // W -> IR: send bus W to instruction register IR
output [0:15] ir, // IR register
input si1, // invalidate IR contents
// --- Instructions ------------------------------------------------------
output ls, // LS
output rj, // RJ
output bs, // BS
output ou, // OU
output in, // IN
output is, // IS
output ri, // RI
output pufa, // any of the wide or floating point arithmetic instructions
output rb$, // RB
output cb, // CB
output sc$, // S/C opcode group
output oc, // BRC, BLC
output ka2, // KA2 opcode group
output gr, // G/L opcode group
output hlt, // HLT
output mcl, // MCL
output sin, // SIU, SIL, SIT, CIT
output gi, // GIU, GIL
output lip, // LIP
output mb, // MB
output im, // IM
output ki, // KI
output fi, // FI
output sp, // SP
output rz, // RZ
output ib, // IB
output lpc, // LPC
output rpc, // RPC
output shc, // SHC
output rc$, // RIC, RKY
output ng$, // NGA, NGC
output zb$, // ZLB, ZRB
output uj, // UJ
output lwlwt, // LWT, LW
output lj, // LJ
output ka1, // KA1 opcode group
output exl, // EXL
output inou, // IN, OU
output sr, // SRX, SRY, SRZ, SHC (shift right)
output md, // MD
output jkrb, // JS, IRB, DRB
output lwrs, // LWS, RWS
output lrcb, // LB, CB, RB (byte-addressing ops)
output nrf, // NRF
// --- Instruction params ------------------------------------------------
output b0, // B==0 (opcode field B is 0 - no B-modification)
output c0, // C==0 (opcode field C is 0 - instruction argument is stored in the next word)
output na, // instruction with a Normal Argument
output xi, // instruction is illegal
output nef, // instruction is ineffective
input q, // Q system flag
input mc_3, // MC==3: three consecutive pre-modifications
input [0:8] r0, // upper R0 register (CPU flags)
output _0_v, // A14
input p, // P flag (branch)
output amb, // A75
output apb, // B65
output ap1, // register A plus 1 (for IRB)
output am1, // register A minus 1 (for DRB)
input wls, // A70
output bcoc$, // A89
output saryt, // SARYT: ALU operation mode (0 - logic, 1 - arythmetic)
output sd, // ALU function select
output scb, // ALU function select
output sca, // ALU function select
output sb, // ALU function select
output sab, // ALU function select
output saa, // ALU function select
output aryt, // A68
output sbar$, // B91
input at15, // A07
output ust_z, // B49
output ust_v, // A08
output ust_mc, // B80
output ust_leg, // B93
output eat0, // A13
output ust_y, // A53
output ust_x, // A47
output blr, // A87
input wpb, // A58
input wr, // A60
input pp, // A62
input ww, // B60
input wm, // A38
input wp, // A37
input wzi, // "0" indicator (Wskaźnik Zera)
// --- States ------------------------------------------------------------
input w$, // W& state
input p4, // P4 state
input we, // WE state
input wx, // WX state
input wa, // WA state
input wz, // WZ state
// --- State transitions -------------------------------------------------
output ewz, // Enter WZ
output ew$, // Enter W&
output ewe, // Enter WE
output ewa, // Enter WA
output ewp, // Enter WP
output ewr, // Enter WR
output ewm, // Enter WM
output eww, // Enter WW
output ewx, // Enter WX
output ekc_1, // EKC*1 - Enter cycle end (Koniec Cyklu)
output ekc_2, // EKC*2 - Enter cycle end (Koniec Cyklu)
output lar$, // B82
output ssp$, // B81
output p16, // A36
input lk, // LK != 0
output efp, // A11
output sar$, // A05
output srez$, // A17
output axy, // A46
output lac // B43
);
parameter INOU_USER_ILLEGAL;
wor __NC; // unconnected signals here, to suppress warnings
// IR - instruction register
wire ir_clk = strob1 & w_ir;
ir REG_IR(
.clk_sys(clk_sys),
.d(w),
.c(ir_clk),
.invalidate(si1),
.q(ir)
);
assign c0 = (ir[13:15] != 0);
wire ir13_14 = (ir[13:14] != 0);
wire ir01 = (ir[0:1] != 0);
wire b_1 = (ir[10:12] == 1);
assign b0 = (ir[10:12] == 0);
// decoder for 2-arg instructions with normal argument (opcodes 020-036 and 040-057)
// decoder for KA1 instruction group (opcodes 060-067)
wire lw, tw, rw, pw, bb, bm, bc, bn;
wire aw, ac, sw, cw, _or, om, nr, nm, er, em, xr, xm, cl, lb;
wire awt, trb, irb, drb, cwt, lwt, lws, rws, js, c, s, j, l, g, b_n;
idec1 IDEC1(
.i(ir[0:5]),
.o({lw, tw, ls, ri, rw, pw, rj, is, bb, bm, bs, bc, bn, ou, in, pufa, aw, ac, sw, cw, _or, om, nr, nm, er, em, xr, xm, cl, lb, rb$, cb, awt, trb, irb, drb, cwt, lwt, lws, rws, js, ka2, c, s, j, l, g, b_n})
);
assign sc$ = s | c;
assign oc = ka2 & ~ir[7];
assign gr = l | g;
// opcode field A register number decoder
wire [0:7] a_eq;
decoder8 DEC_A_EQ(
.i(ir[7:9]),
.ena(1'b1),
.o({a_eq})
);
// S opcode group decoder
decoder8 DEC_S(
.i(ir[7:9]),
.ena(s),
.o({hlt, mcl, sin, gi, lip, __NC, __NC, __NC})
);
// B/N opcode group decoder
decoder8 DEC_BN(
.i(ir[7:9]),
.ena(b_n),
.o({mb, im, ki, fi, sp, md, rz, ib})
);
wire ngl, srz;
decoder8 DEC_D(
.i({b_1, ir[15], ir[6]}),
.ena(c),
.o({__NC, __NC, __NC, __NC, ngl, srz, rpc, lpc})
);
assign shc = c & ir[11];
wire c_b0 = c & b0;
// C opcode group decoder
wire sx, sz, sly, slx, srxy;
decoder8 DEC_OTHER(
.i(ir[13:15]),
.ena(c_b0),
.o({rc$, zb$, sx, ng$, sz, sly, slx, srxy})
);
// --- Ineffective, illegal instr. ---------------------------------------
wire snef = (a_eq[5:7] != 0);
wire M85_11 = ir[10] | (ir[11] & ir[12]);
wire xi_1 = (INOU_USER_ILLEGAL & inou & q) | (M85_11 & c) | (q & s) | (q & ~snef & b_n);
wire xi_2 = (md & mc_3) | (c & ir13_14 & b_1) | (snef & s);
wire nef_jcs = a_eq[7] & ~r0[3];
wire nef_jys = a_eq[6] & ~r0[7];
wire nef_jxs = a_eq[5] & ~r0[8];
wire nef_jvs = a_eq[4] & ~r0[2];
wire nef_js = js & (nef_jcs | nef_jys | nef_jxs | nef_jvs);
wire nef_jg = a_eq[3] & ~r0[6];
wire nef_je = a_eq[2] & ~r0[5];
wire nef_jl = a_eq[1] & ~r0[4];
wire nef_jjs = (j | js) & (nef_jg | nef_je | nef_jl);
wire nef_jn = j & a_eq[6] & r0[5];
wire nef_jm = j & a_eq[5] & ~r0[1];
wire nef_jz = j & a_eq[4] & ~r0[0];
assign xi = ~ir01 | xi_1 | xi_2;
assign nef = xi | p | nef_js | nef_jjs | nef_jm | nef_jn | nef_jz;
// --- Instruction groups ------------------------------------------------
wire cns = ccb | ng$ | sw;
wire a = aw | ac | awt;
assign lwrs = lws | rws;
wire ans = sw | ng$ | a;
wire riirb = ri | irb;
wire krb = irb | drb;
assign jkrb = js | krb;
wire nglbb = ngl | bb;
assign bcoc$ = bc | oc;
wire wlsbs = wls | bs;
wire emnm = em | nm;
wire orxr = _or | xr;
wire lbcb = lb | cb;
assign lrcb = lbcb | rb$;
wire mis = m | is;
assign aryt = cw | cwt;
wire c$ = cw | cwt | cl;
wire ccb = c$ | cb;
assign inou = in | ou;
wire rbib = rb$ | ib;
wire bmib = bm | ib;
assign sr = srxy | srz | shc;
wire lrcbsr = lrcb | sr;
wire gmio = mcl | gi | inou;
wire hsm = hlt | sin | md;
wire sl = slx | sz | sly;
wire pcrs = rpc | lpc | rc$ | sx;
wire fimb = fi | im | mb;
// --- ALU control signals -----------------------------------------------
wire uka = ka1 & ir[6];
wire M90_8 = sl | ri | krb;
assign saryt = (we & M49_6) | (p4) | (w$ & M90_8) | ((cns ^ M90_12) & w$);
wire M90_12 = a | trb | ib;
wire M49_6 = lwrs | lj | js | krb;
assign apb = (~uka & p4) | (M90_12 & w$) | (M49_6 & we);
assign amb = (uka & p4) | (cns & w$);
wire M84_8 = riirb ^ nglbb;
wire M67_8 = bm | is | er | xr;
wire sds = (wz & (xm | em)) | (M67_8 & w$) | (w$ & M84_8) | (we & wlsbs);
wire ssb = w$ & (ngl | oc | bc);
assign sd = sds | amb;
assign sb = apb | ssb | sl | ap1;
wire M93_12 = sl | ls | orxr;
wire M50_8 = (M93_12 & w$) | (w$ & nglbb) | (wlsbs & we) | (wz & ~nm & (mis | lrcb));
wire ssab = rb$ & w$ & wpb;
wire ssaa = (rb$ & w$ & ~wpb) | (w$ & lb);
wire ssca = (M84_8 & w$) | (w$ & (bs | bn | nr)) | (wz & (emnm | lrcb)) | (we & ls);
assign sca = ssca | apb | ssaa;
assign scb = ssca | apb | ssab;
assign saa = ssaa | amb | ap1 | M50_8;
assign sab = ssab | amb | ap1 | M50_8;
assign sbar$ = lrcb | mis | (gr & ir[7]) | bm | pw | tw;
assign nrf = ir[7] & ka2 & ir[6];
wire fppn = pufa ^ nrf;
assign _0_v = js & a_eq[4] & we;
assign ap1 = riirb & w$;
assign am1 = drb & w$;
// R0 flags control signals
wire nor$ = ngl | er | nr | orxr;
assign ust_z = (nor$ & w$) | (w$ & ans) | (m & wz);
wire m = xm | om | emnm;
assign ust_v = (ans ^ (ir[6] & sl)) & w$;
assign ust_mc = ans & w$;
assign ust_leg = ccb & w$;
wire M59_8 = (ir[6] & r0[8]) | (~ir[6] & r0[7]);
assign eat0 = (srxy & M59_8) | (shc & at15); // | was ^, but there is no need for ^
assign ust_y = (w$ & sl) | (sr & ~shc & wx);
assign ust_x = wa & sx;
assign blr = w$ & oc & ~ir[6];
// execution phase control signals
wire ngrij = ng$ | ri | rj;
wire prawy = lbcb & wpb;
assign lwlwt = lwt | lw;
assign uj = j & ~a_eq[7]; // Note: jump conditions are checked during ineffective instruction tests, so everything becomes "UJ"
assign lj = j & a_eq[7];
assign ewa = (pcrs & pp) | (ngrij & pp) | (we & ~wls & ls) | (~wpb & lbcb & wr);
assign ewp = (lrcb & wx) | (wx & sr & ~lk) | (rj & wa) | (pp & (uj | lwlwt));
assign ewe = (lj & ww) | (ls & wa) | (pp & (llb | zb$ | js)) | (~wzi & krb & w$);
// execution phase control signals
// instruction cycle end signal
wire grlk = gr & lk;
wire M59_6 = rbib | (~wzi & (krb | is));
assign ekc_1 = (~lac & wr & ~grlk & ~lrcb) | (~lrcb & wp) | (~llb & we) | (~M59_6 & w$);
assign ewz = (w$ & ~wzi & is) | (wr & m) | (pp & lrcbsr);
wire M88_6 = is | rb$ | bmib | prawy;
assign ew$ = (wr & M88_6) | (we & wlsbs) | (ri & ww) | ((ng$ | lbcb) & wa) | (pp & sew$);
// control signals
assign lar$ = lb | ri | ans | trb | ls | sl | nor$ | krb;
wire M92_12 = bc | bn | bb | trb | oc;
assign ssp$ = is | bmib | M92_12 | bs;
wire sew$ = M92_12 | krb | nor$ | sl | sw | a | c$;
wire llb = bs | ls | lwrs;
assign ka1 = js | (ir[0:2] == 3'b110);
assign na = ~ka1 & ~ka2 & ~sc$ & ir01;
assign exl = ka2 & (ir[6:7] == 2'b01);
wire M63_3 = ng$ & ir[6];
wire M31_6 = ((ac | M63_3) & w$ & r0[3]) | (r0[7] & sly) | (uka & p4) | (lj & we);
assign p16 = (~M63_3 & w$ & cns) | (riirb & w$) | (ib & w$) | (slx & r0[8]) | M31_6;
// execution phase control signals
wire M60_8 = ~lk & inou;
wire M76_3 = l ^ M60_8;
assign ewr = (wp & lrcb) | (lk & wr & l) | (lws & we) | (M76_3 & wx) | M20_9 | M20_10;
wire M20_9 = M60_8 & wm;
wire M20_10 = (fimb | lac | tw) & pp;
assign ewm = gmio & pp;
assign efp = fppn & pp;
assign sar$ = l | lws | tw;
wire M75_6 = pw | rw | lj | rz | ki;
assign eww = (we & rws) | (pp & M75_6) | (ri & wa) | (lk & ww & g) | (wx & g) | (mis & wz) | (rbib & w$);
assign srez$ = rbib | mis; // it was ^ instead of |, but there is no need for ^
// execution phase control signal
// instruction cycle end signal
assign ewx = (lrcbsr & wz) | (pp & (gr ^ hsm)) | ((inou & lk) & wm) | (lk & (inou | sr) & wx);
assign axy = sr | (ir[6] & rbib);
assign ekc_2 = (wx & hsm) | (wm & ~inou) | (~grlk & ~lj & ~ri & ww) | (pcrs & wa);
assign lac = bmib | mis;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/*
* Integer multiply/divide module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_muldiv (
input [31:0] x, // 16 MSb for division
input [15:0] y,
output [31:0] o,
input [ 2:0] f,
input word_op,
output cfo,
output ofo,
input clk,
output exc
);
// Net declarations
wire as, bs, cfs, cfu;
wire [16:0] a, b;
wire [33:0] p;
wire div0, over, ovf, mint;
wire [33:0] zi;
wire [16:0] di;
wire [17:0] q;
wire [17:0] s;
// Module instantiations
zet_signmul17 signmul17 (
.clk (clk),
.a (a),
.b (b),
.p (p)
);
zet_div_su #(
.z_width(34)
) div_su (
.clk (clk),
.ena (1'b1),
.z (zi),
.d (di),
.q (q),
.s (s),
.ovf (ovf)
);
// Sign ext. for imul
assign as = f[0] & (word_op ? x[15] : x[7]);
assign bs = f[0] & (word_op ? y[15] : y[7]);
assign a = word_op ? { as, x[15:0] }
: { {9{as}}, x[7:0] };
assign b = word_op ? { bs, y } : { {9{bs}}, y[7:0] };
assign zi = f[2] ? { 26'h0, x[7:0] }
: (word_op ? (f[0] ? { {2{x[31]}}, x }
: { 2'b0, x })
: (f[0] ? { {18{x[15]}}, x[15:0] }
: { 18'b0, x[15:0] }));
assign di = word_op ? (f[0] ? { y[15], y } : { 1'b0, y })
: (f[0] ? { {9{y[7]}}, y[7:0] }
: { 9'h000, y[7:0] });
assign o = f[2] ? { 16'h0, q[7:0], s[7:0] }
: (f[1] ? ( word_op ? {s[15:0], q[15:0]}
: {16'h0, s[7:0], q[7:0]})
: p[31:0]);
assign ofo = f[1] ? 1'b0 : cfo;
assign cfo = f[1] ? 1'b0 : !(f[0] ? cfs : cfu);
assign cfu = word_op ? (o[31:16] == 16'h0)
: (o[15:8] == 8'h0);
assign cfs = word_op ? (o[31:16] == {16{o[15]}})
: (o[15:8] == {8{o[7]}});
// Exceptions
assign over = word_op ? (f[0] ? (q[17:16]!={2{q[15]}})
: (q[17:16]!=2'b0) )
: (f[0] ? (q[17:8]!={10{q[7]}})
: (q[17:8]!=10'h000));
assign mint = f[0] & (word_op ? (x==32'h80000000)
: (x==16'h8000));
assign div0 = ~|di;
assign exc = div0 | (!f[2] & (ovf | over | mint));
endmodule
|
// $Id: rtr_crossbar_mac.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// configurable crossbar module
//==============================================================================
module rtr_crossbar_mac
(ctrl_in_op_ip, data_in_ip, data_out_op);
`include "c_constants.v"
//---------------------------------------------------------------------------
// parameters
//---------------------------------------------------------------------------
// number of input/output ports
parameter num_ports = 5;
// width per port
parameter width = 32;
// select implementation variant
parameter crossbar_type = `CROSSBAR_TYPE_MUX;
//---------------------------------------------------------------------------
// interface
//---------------------------------------------------------------------------
// crosspoint control signals
input [0:num_ports*num_ports-1] ctrl_in_op_ip;
// vector of input data
input [0:num_ports*width-1] data_in_ip;
// vector of output data
output [0:num_ports*width-1] data_out_op;
wire [0:num_ports*width-1] data_out_op;
//---------------------------------------------------------------------------
// implementation
//---------------------------------------------------------------------------
wire [0:num_ports*num_ports-1] ctrl_in_ip_op;
c_interleave
#(.width(num_ports*num_ports),
.num_blocks(num_ports))
ctrl_in_ip_op_intl
(.data_in(ctrl_in_op_ip),
.data_out(ctrl_in_ip_op));
c_crossbar
#(.num_in_ports(num_ports),
.num_out_ports(num_ports),
.width(width),
.crossbar_type(crossbar_type))
xbr
(.ctrl_ip_op(ctrl_in_ip_op),
.data_in_ip(data_in_ip),
.data_out_op(data_out_op));
endmodule
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: k580wn59.v
//
// Programmable interrupt controller k580wn59 design file of Bashkiria-2M replica.
//
// Warning: Interrupt level shift not supported.
module k580wn59(
input clk, input reset, input addr, input we_n,
input[7:0] idata, output reg[7:0] odata,
output intr, input inta_n, input[7:0] irq);
reg[1:0] state;
reg[7:0] irqmask;
reg[7:0] smask;
reg[7:0] serviced;
reg[2:0] addr0;
reg[7:0] addr1;
reg init;
reg addrfmt;
reg exinta_n;
wire[7:0] r = irq & ~(irqmask | smask);
assign intr = |r;
reg[2:0] x;
always @(*)
casex (r)
8'bxxxxxxx1: x = 3'b000;
8'bxxxxxx10: x = 3'b001;
8'bxxxxx100: x = 3'b010;
8'bxxxx1000: x = 3'b011;
8'bxxx10000: x = 3'b100;
8'bxx100000: x = 3'b101;
8'bx1000000: x = 3'b110;
default: x = 3'b111;
endcase
always @(*)
casex ({inta_n,state})
3'b000: odata = 8'hCD;
3'bx01: odata = addrfmt ? {addr0,x,2'b00} : {addr0[2:1],x,3'b000};
3'bx1x: odata = addr1;
3'b100: odata = addr ? irqmask : irq;
endcase
always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 0; init <= 0; irqmask <= 8'hFF; smask <= 8'hFF; serviced <= 0; exinta_n <= 1'b1;
end else begin
exinta_n <= inta_n;
smask <= smask & (irq|serviced);
case (state)
2'b00: begin
if (~we_n) begin
init <= 0;
casex ({addr,idata[4:3]})
3'b000:
case (idata[7:5])
3'b001: serviced <= 0;
3'b011: serviced[idata[2:0]] <= 0;
endcase
3'b01x: begin init <= 1'b1; addr0 <= idata[7:5]; addrfmt <= idata[2]; end
3'b1xx: if (init) addr1 <= idata; else irqmask <= idata;
endcase
end
if (inta_n&~exinta_n) state <= 2'b01;
end
2'b01: begin
if (inta_n&~exinta_n) state <= 2'b10;
end
2'b10: begin
if (inta_n&~exinta_n) begin
state <= 2'b00;
smask[x] <= 1'b1;
serviced[x] <= 1'b1;
end
end
endcase
end
end
endmodule
|
/**
* This is written by Zhiyang Ong
* for EE577b Extra Credit Homework , Question 2
*
* Behavioral model for the Hamming encoder
*/
module ham_15_11_encoder (d,c);
// Output signals representing the 15-bit encoded vector
output reg [14:0] c;
// Input signals representing the 11-bit input
input [10:0] d;
// Declare "reg" signals...
// Parity bits for Hamming encoding
reg [3:0] p;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
always @(*)
begin
// Determine for each parity bit, what data bits is it made of
//p[0]=((d[0]^d[1])^(d[3]^d[4]))^((d[6]^d[8])^d[10]);
p[0]=d[0]^d[1]^d[3]^d[4]^d[6]^d[8]^d[10];
// assign p[0]=d[0];
//p{0}=d{0};
//p(0)=d(0);
p[1]=((d[0]^d[2])^(d[3]^d[5]))^((d[6]^d[9])^d[10]);
p[2]=((d[1]^d[2])^(d[3]^d[7]))^((d[8]^d[9])^d[10]);
p[3]=((d[4]^d[5])^(d[6]^d[7]))^((d[8]^d[9])^d[10]);
// Assign the encoded signal bits to data bits...
c[2]=d[0];
c[4]=d[1];
c[5]=d[2];
c[6]=d[3];
c[8]=d[4];
c[9]=d[5];
c[10]=d[6];
c[11]=d[7];
c[12]=d[8];
c[13]=d[9];
c[14]=d[10];
// Introduce parity bits to encode signal values
c[0]=p[0];
c[1]=p[1];
c[3]=p[2];
c[7]=p[3];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O2111A_BEHAVIORAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_BEHAVIORAL_PP_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_a_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:26:55 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_a_e.v,v 1.1 2006/04/10 15:42:10 wig Exp $
// $Date: 2006/04/10 15:42:10 $
// $Log: inst_a_e.v,v $
// Revision 1.1 2006/04/10 15:42:10 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_a_e
//
// No user `defines in this module
module inst_a_e
//
// Generated module inst_a
//
(
widesig_o,
widesig_r_0,
widesig_r_1,
widesig_r_2,
widesig_r_3,
widesig_r_4,
widesig_r_5,
widesig_r_6,
widesig_r_7,
widesig_r_8,
widesig_r_9,
widesig_r_10,
widesig_r_11,
widesig_r_12,
widesig_r_13,
widesig_r_14,
widesig_r_15,
widesig_r_16,
widesig_r_17,
widesig_r_18,
widesig_r_19,
widesig_r_20,
widesig_r_21,
widesig_r_22,
widesig_r_23,
widesig_r_24,
widesig_r_25,
widesig_r_26,
widesig_r_27,
widesig_r_28,
widesig_r_29,
widesig_r_30,
unsplice_a1_no3, // leaves 3 unconnected
unsplice_a2_all128, // full 128 bit port
unsplice_a3_up100, // connect 100 bits from 0
unsplice_a4_mid100, // connect mid 100 bits
unsplice_a5_midp100, // connect mid 100 bits
unsplice_bad_a,
unsplice_bad_b,
widemerge_a1,
p_mix_test1_go
);
// Generated Module Outputs:
output [31:0] widesig_o;
output widesig_r_0;
output widesig_r_1;
output widesig_r_2;
output widesig_r_3;
output widesig_r_4;
output widesig_r_5;
output widesig_r_6;
output widesig_r_7;
output widesig_r_8;
output widesig_r_9;
output widesig_r_10;
output widesig_r_11;
output widesig_r_12;
output widesig_r_13;
output widesig_r_14;
output widesig_r_15;
output widesig_r_16;
output widesig_r_17;
output widesig_r_18;
output widesig_r_19;
output widesig_r_20;
output widesig_r_21;
output widesig_r_22;
output widesig_r_23;
output widesig_r_24;
output widesig_r_25;
output widesig_r_26;
output widesig_r_27;
output widesig_r_28;
output widesig_r_29;
output widesig_r_30;
output [127:0] unsplice_a1_no3;
output [127:0] unsplice_a2_all128;
output [127:0] unsplice_a3_up100;
output [127:0] unsplice_a4_mid100;
output [127:0] unsplice_a5_midp100;
output [127:0] unsplice_bad_a;
output [127:0] unsplice_bad_b;
output [31:0] widemerge_a1;
output p_mix_test1_go;
// Generated Wires:
wire [31:0] widesig_o;
wire widesig_r_0;
wire widesig_r_1;
wire widesig_r_2;
wire widesig_r_3;
wire widesig_r_4;
wire widesig_r_5;
wire widesig_r_6;
wire widesig_r_7;
wire widesig_r_8;
wire widesig_r_9;
wire widesig_r_10;
wire widesig_r_11;
wire widesig_r_12;
wire widesig_r_13;
wire widesig_r_14;
wire widesig_r_15;
wire widesig_r_16;
wire widesig_r_17;
wire widesig_r_18;
wire widesig_r_19;
wire widesig_r_20;
wire widesig_r_21;
wire widesig_r_22;
wire widesig_r_23;
wire widesig_r_24;
wire widesig_r_25;
wire widesig_r_26;
wire widesig_r_27;
wire widesig_r_28;
wire widesig_r_29;
wire widesig_r_30;
wire [127:0] unsplice_a1_no3;
wire [127:0] unsplice_a2_all128;
wire [127:0] unsplice_a3_up100;
wire [127:0] unsplice_a4_mid100;
wire [127:0] unsplice_a5_midp100;
wire [127:0] unsplice_bad_a;
wire [127:0] unsplice_bad_b;
wire [31:0] widemerge_a1;
wire p_mix_test1_go;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [7:0] s_port_offset_01;
wire [7:0] s_port_offset_02;
wire [1:0] s_port_offset_02b;
wire test1; // __W_PORT_SIGNAL_MAP_REQ
wire [4:0] test2;
wire [3:0] test3;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
assign p_mix_test1_go = test1; // __I_O_BIT_PORT
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for inst_aa
ent_aa inst_aa (
.port_1(test1), // Use internally test1
.port_2(test2[0]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[0]), // Bus combining o.k.
.port_o(s_port_offset_01),
.port_o02[10:3](s_port_offset_02), // __W_PORT// __E_CANNOT_COMBINE_SPLICES
.port_o02[1:0](s_port_offset_02b) // __W_PORT// __E_CANNOT_COMBINE_SPLICES
);
// End of Generated Instance Port Map for inst_aa
// Generated Instance Port Map for inst_ab
ent_ab inst_ab (
.port_2(test2[1]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[1]), // Bus combining o.k.
.port_ab_1(test1), // Use internally test1
.port_i(s_port_offset_01),
.port_i02[10:3](s_port_offset_02), // __W_PORT// __E_CANNOT_COMBINE_SPLICES
.port_i02[2:1](s_port_offset_02b) // __W_PORT// __E_CANNOT_COMBINE_SPLICES
);
// End of Generated Instance Port Map for inst_ab
// Generated Instance Port Map for inst_ac
ent_ac inst_ac (
.port_2(test2[3]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[2]) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ac
// Generated Instance Port Map for inst_ad
ent_ad inst_ad (
.port_2(test2[4]), // Bus with hole in the middleNeeds input to be happy
.port_3(test3[3]) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ad
// Generated Instance Port Map for inst_ae
ent_ae inst_ae (
.port_2(test2), // Bus with hole in the middleNeeds input to be happy
.port_3(test3) // Bus combining o.k.
);
// End of Generated Instance Port Map for inst_ae
endmodule
//
// End of Generated Module rtl of inst_a_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
zq_req, app_zq_ack,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
app_zq_req, zq_ack
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
input app_sr_req;
output wire sr_req;
assign sr_req = app_sr_req;
input sr_active;
output wire app_sr_active;
assign app_sr_active = sr_active;
input app_ref_req;
output wire ref_req;
assign ref_req = app_ref_req;
input ref_ack;
output wire app_ref_ack;
assign app_ref_ack = ref_ack;
input app_zq_req;
output wire zq_req;
assign zq_req = app_zq_req;
input zq_ack;
output wire app_zq_ack;
assign app_zq_ack = zq_ack;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
mig_7series_v1_9_ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
mig_7series_v1_9_ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
mig_7series_v1_9_ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple[3:0]),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
//
// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24)
//
// On Tue Jun 8 18:41:53 EDT 2010
//
//
// Ports:
// Name I/O size props
// RDY_iport0_put O 1
// RDY_iport1_put O 1
// oport_get O 153
// RDY_oport_get O 1
// CLK I 1 clock
// RST_N I 1 reset
// iport0_put I 153
// iport1_put I 153
// EN_iport0_put I 1
// EN_iport1_put I 1
// EN_oport_get I 1
//
// No combinational paths from inputs to outputs
//
//
module mkPktMerge(CLK,
RST_N,
iport0_put,
EN_iport0_put,
RDY_iport0_put,
iport1_put,
EN_iport1_put,
RDY_iport1_put,
EN_oport_get,
oport_get,
RDY_oport_get);
input CLK;
input RST_N;
// action method iport0_put
input [152 : 0] iport0_put;
input EN_iport0_put;
output RDY_iport0_put;
// action method iport1_put
input [152 : 0] iport1_put;
input EN_iport1_put;
output RDY_iport1_put;
// actionvalue method oport_get
input EN_oport_get;
output [152 : 0] oport_get;
output RDY_oport_get;
// signals for module outputs
wire [152 : 0] oport_get;
wire RDY_iport0_put, RDY_iport1_put, RDY_oport_get;
// register fi0Active
reg fi0Active;
wire fi0Active__D_IN;
wire fi0Active__EN;
// register fi0HasPrio
reg fi0HasPrio;
reg fi0HasPrio__D_IN;
wire fi0HasPrio__EN;
// register fi1Active
reg fi1Active;
wire fi1Active__D_IN, fi1Active__EN;
// ports of submodule fi0
wire [152 : 0] fi0__D_IN, fi0__D_OUT;
wire fi0__CLR, fi0__DEQ, fi0__EMPTY_N, fi0__ENQ, fi0__FULL_N;
// ports of submodule fi1
wire [152 : 0] fi1__D_IN, fi1__D_OUT;
wire fi1__CLR, fi1__DEQ, fi1__EMPTY_N, fi1__ENQ, fi1__FULL_N;
// ports of submodule fo
reg [152 : 0] fo__D_IN;
wire [152 : 0] fo__D_OUT;
wire fo__CLR, fo__DEQ, fo__EMPTY_N, fo__ENQ, fo__FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_arbitrate,
CAN_FIRE_RL_fi0_advance,
CAN_FIRE_RL_fi1_advance,
CAN_FIRE_iport0_put,
CAN_FIRE_iport1_put,
CAN_FIRE_oport_get,
WILL_FIRE_RL_arbitrate,
WILL_FIRE_RL_fi0_advance,
WILL_FIRE_RL_fi1_advance,
WILL_FIRE_iport0_put,
WILL_FIRE_iport1_put,
WILL_FIRE_oport_get;
// inputs to muxes for submodule ports
wire [152 : 0] MUX_fo__enq_1__VAL_1;
wire MUX_fi0Active__write_1__SEL_1,
MUX_fi0Active__write_1__VAL_1,
MUX_fi1Active__write_1__SEL_1;
// remaining internal signals
reg [63 : 0] v__h679;
wire fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10;
// action method iport0_put
assign RDY_iport0_put = fi0__FULL_N ;
assign CAN_FIRE_iport0_put = fi0__FULL_N ;
assign WILL_FIRE_iport0_put = EN_iport0_put ;
// action method iport1_put
assign RDY_iport1_put = fi1__FULL_N ;
assign CAN_FIRE_iport1_put = fi1__FULL_N ;
assign WILL_FIRE_iport1_put = EN_iport1_put ;
// actionvalue method oport_get
assign oport_get = fo__D_OUT ;
assign RDY_oport_get = fo__EMPTY_N ;
assign CAN_FIRE_oport_get = fo__EMPTY_N ;
assign WILL_FIRE_oport_get = EN_oport_get ;
// submodule fi0
arSRLFIFO_a fi0 (.CLK(CLK),
.RST_N(RST_N),
.D_IN(fi0__D_IN),
.ENQ(fi0__ENQ),
.DEQ(fi0__DEQ),
.CLR(fi0__CLR),
.D_OUT(fi0__D_OUT),
.EMPTY_N(fi0__EMPTY_N),
.FULL_N(fi0__FULL_N));
// submodule fi1
arSRLFIFO_b fi1
(.CLK(CLK),
.RST_N(RST_N),
.D_IN(fi1__D_IN),
.ENQ(fi1__ENQ),
.DEQ(fi1__DEQ),
.CLR(fi1__CLR),
.D_OUT(fi1__D_OUT),
.EMPTY_N(fi1__EMPTY_N),
.FULL_N(fi1__FULL_N));
// submodule fo
arSRLFIFO_c fo
(.CLK(CLK),
.RST_N(RST_N),
.D_IN(fo__D_IN),
.ENQ(fo__ENQ),
.DEQ(fo__DEQ),
.CLR(fo__CLR),
.D_OUT(fo__D_OUT),
.EMPTY_N(fo__EMPTY_N),
.FULL_N(fo__FULL_N));
// rule RL_arbitrate
assign CAN_FIRE_RL_arbitrate =
fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10 &&
fi0__EMPTY_N &&
fi1__EMPTY_N &&
!fi0Active &&
!fi1Active ;
assign WILL_FIRE_RL_arbitrate = CAN_FIRE_RL_arbitrate ;
// rule RL_fi0_advance
assign CAN_FIRE_RL_fi0_advance = fi0__EMPTY_N && fo__FULL_N && !fi1Active ;
assign WILL_FIRE_RL_fi0_advance =
CAN_FIRE_RL_fi0_advance && !WILL_FIRE_RL_arbitrate ;
// rule RL_fi1_advance
assign CAN_FIRE_RL_fi1_advance = fi1__EMPTY_N && fo__FULL_N && !fi0Active ;
assign WILL_FIRE_RL_fi1_advance =
CAN_FIRE_RL_fi1_advance && !WILL_FIRE_RL_fi0_advance &&
!WILL_FIRE_RL_arbitrate ;
// inputs to muxes for submodule ports
assign MUX_fi0Active__write_1__SEL_1 = WILL_FIRE_RL_arbitrate && fi0HasPrio ;
assign MUX_fi1Active__write_1__SEL_1 =
WILL_FIRE_RL_arbitrate && !fi0HasPrio ;
assign MUX_fi0Active__write_1__VAL_1 =
fi0HasPrio ? !fi0__D_OUT[151] : !fi1__D_OUT[151] ;
assign MUX_fo__enq_1__VAL_1 = fi0HasPrio ? fi0__D_OUT : fi1__D_OUT ;
// register fi0Active
assign fi0Active__D_IN =
MUX_fi0Active__write_1__SEL_1 ?
MUX_fi0Active__write_1__VAL_1 :
!fi0__D_OUT[151] ;
assign fi0Active__EN =
WILL_FIRE_RL_arbitrate && fi0HasPrio ||
WILL_FIRE_RL_fi0_advance ;
// register fi0HasPrio
always@(WILL_FIRE_RL_arbitrate or
fi0HasPrio or WILL_FIRE_RL_fi0_advance or WILL_FIRE_RL_fi1_advance)
begin
// case (1'b1) // synopsys parallel_case
// WILL_FIRE_RL_arbitrate: fi0HasPrio__D_IN = !fi0HasPrio;
// WILL_FIRE_RL_fi0_advance: fi0HasPrio__D_IN = 1'd0;
// WILL_FIRE_RL_fi1_advance: fi0HasPrio__D_IN = 1'd1;
//case (1'b1) // synopsys parallel_case
// WILL_FIRE_RL_arbitrate: fi0HasPrio__D_IN = !fi0HasPrio;
fi0HasPrio__D_IN = !fi0HasPrio;
// WILL_FIRE_RL_fi0_advance: fi0HasPrio__D_IN = 1'd0;
// WILL_FIRE_RL_fi1_advance: fi0HasPrio__D_IN = 1'd1;
// endcase
//endcase
end
assign fi0HasPrio__EN =
WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance ||
WILL_FIRE_RL_fi1_advance ;
// register fi1Active
assign fi1Active__D_IN =
MUX_fi1Active__write_1__SEL_1 ?
MUX_fi0Active__write_1__VAL_1 :
!fi1__D_OUT[151] ;
assign fi1Active__EN =
WILL_FIRE_RL_arbitrate && !fi0HasPrio ||
WILL_FIRE_RL_fi1_advance ;
// submodule fi0
assign fi0__D_IN = iport0_put ;
assign fi0__DEQ =
WILL_FIRE_RL_arbitrate && fi0HasPrio ||
WILL_FIRE_RL_fi0_advance ;
assign fi0__ENQ = EN_iport0_put ;
assign fi0__CLR = 1'b0 ;
// submodule fi1
assign fi1__D_IN = iport1_put ;
assign fi1__DEQ =
WILL_FIRE_RL_arbitrate && !fi0HasPrio ||
WILL_FIRE_RL_fi1_advance ;
assign fi1__ENQ = EN_iport1_put ;
assign fi1__CLR = 1'b0 ;
// submodule fo
always@(WILL_FIRE_RL_arbitrate or
MUX_fo__enq_1__VAL_1 or
WILL_FIRE_RL_fi0_advance or
fi0__D_OUT or WILL_FIRE_RL_fi1_advance or fi1__D_OUT)
begin
// case (1'b1) // synopsys parallel_case
//WILL_FIRE_RL_arbitrate: fo__D_IN = MUX_fo__enq_1__VAL_1;
fo__D_IN = MUX_fo__enq_1__VAL_1;
// WILL_FIRE_RL_fi0_advance: fo__D_IN = fi0__D_OUT;
// WILL_FIRE_RL_fi1_advance: fo__D_IN = fi1__D_OUT;
// endcase
end
assign fo__DEQ = EN_oport_get ;
assign fo__ENQ =
WILL_FIRE_RL_arbitrate || WILL_FIRE_RL_fi0_advance ||
WILL_FIRE_RL_fi1_advance ;
assign fo__CLR = 1'b0 ;
// remaining internal signals
assign fo_RDY_enq_AND_IF_fi0HasPrio_THEN_fi0_RDY_firs_ETC___d10 =
fo__FULL_N && (fi0HasPrio ? fi0__EMPTY_N : fi1__EMPTY_N) ;
// handling of inlined registers
always@(posedge CLK)
begin
if (!RST_N)
begin
fi0Active <= 1'd0;
fi0HasPrio <= 1'd1;
fi1Active <= 1'd0;
end
else
begin
if (fi0Active__EN) fi0Active <= fi0Active__D_IN;
if (fi0HasPrio__EN)
fi0HasPrio <= fi0HasPrio__D_IN;
if (fi1Active__EN) fi1Active <= fi1Active__D_IN;
end
end
// handling of system tasks
endmodule // mkPktMerge
module arSRLFIFO_a (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N);
input CLK;
input RST_N;
input [152:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [152:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire fulln;
wire emptyn;
wire always_one;
wire always_zero;
assign always_one = 1'b1;
assign always_zero = 1'b0;
generic_fifo_sc_a fifo_1
(.clk(CLK),
.rst(RST_N),
.clr (CLR),
.din (D_IN),
.we (ENQ),
.dout (D_OUT),
.re (DEQ),
.full_r (FULL_N),
.empty_r(EMPTY_N),
.full_n_r (fulln),
.empty_n_r (emptyn)
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal FIFO Single Clock ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// D/L from: http://www.opencores.org/cores/generic_fifos/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __
//
// __Date: 2002-09-25 05:42:06 __
// __Revision: 1.1.1.1 __
// __Author: rudi __
// __Locker: __
// __State: Exp __
//
// Change History:
// __Log: not supported by cvs2svn __
//
//
//
//
//
//
//
//
//
//
/*
Description
===========
I/Os
----
rst low active, either sync. or async. master reset (see below how to select)
clr synchronous clear (just like reset but always synchronous), high active
re read enable, synchronous, high active
we read enable, synchronous, high active
din Data Input
dout Data Output
full Indicates the FIFO is full (combinatorial output)
full_r same as above, but registered output (see note below)
empty Indicates the FIFO is empty
empty_r same as above, but registered output (see note below)
full_n Indicates if the FIFO has space for N entries (combinatorial output)
full_n_r same as above, but registered output (see note below)
empty_n Indicates the FIFO has at least N entries (combinatorial output)
empty_n_r same as above, but registered output (see note below)
level indicates the FIFO level:
2'b00 0-25% full
2'b01 25-50% full
2'b10 50-75% full
2'b11 %75-100% full
combinatorial vs. registered status outputs
-------------------------------------------
Both the combinatorial and registered status outputs have exactly the same
synchronous timing. Meaning they are being asserted immediately at the clock
edge after the last read or write. The combinatorial outputs however, pass
through several levels of logic before they are output. The registered status
outputs are direct outputs of a flip-flop. The reason both are provided, is
that the registered outputs require quite a bit of additional logic inside
the FIFO. If you can meet timing of your device with the combinatorial
outputs, use them ! The FIFO will be smaller. If the status signals are
in the critical pass, use the registered outputs, they have a much smaller
output delay (actually only Tcq).
Parameters
----------
The FIFO takes 3 parameters:
dw Data bus width
aw Address bus width (Determines the FIFO size by evaluating 2^aw)
n N is a second status threshold constant for full_n and empty_n
If you have no need for the second status threshold, do not
connect the outputs and the logic should be removed by your
synthesis tool.
Synthesis Results
-----------------
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
at about 116 MHz (IO insertion disabled). The registered status outputs
are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
available.
Misc
----
This design assumes you will do appropriate status checking externally.
IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
empty will place the FIFO in an undefined state.
*/
// Selecting Sync. or Async Reset
// ------------------------------
// Uncomment one of the two lines below. The first line for
// synchronous reset, the second for asynchronous reset
//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset
//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset
`define dw 153
`define aw 4
`define n 32
`define max_size 30
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
module generic_fifo_sc_a(clk, rst, clr, din, we, dout, re,
full_r, empty_r,
full_n_r, empty_n_r);
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
input clk, rst, clr;
input [`dw-1:0] din;
input we;
output [`dw-1:0] dout;
input re;
output full, full_r;
output empty, empty_r;
output full_n, full_n_r;
output empty_n, empty_n_r;
output [1:0] level;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [`aw-1:0] wp;
wire [`aw-1:0] wp_pl1;
wire [`aw-1:0] wp_pl2;
reg [`aw-1:0] rp;
wire [`aw-1:0] rp_pl1;
reg full_r;
reg empty_r;
reg gb;
reg gb2;
reg [`aw:0] cnt;
wire full_n, empty_n;
reg full_n_r, empty_n_r;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
wire always_zero;
assign always_zero = 1'b0;
wire [`dw-1:0] junk_out;
wire [`dw-1:0] junk_in;
// manually assign
assign junk_in = 0;
dual_port_ram ram1(
.clk( clk ),
.addr1( rp ),
.addr2( wp ),
.we1( we ),
.we2( always_zero ),
.out1( doutz ),
.out2( junk_out ),
.data1( din ),
.data2 ( junk_in)
);
wire [`dw-1:0] doutz;
assign dout = (1'b1) ? doutz: junk_out;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk )
begin
if(!rst) wp <= {4'b0000};
else
if(clr) wp <= {4'b0000};
else
if(we) wp <= wp_pl1;
end
assign wp_pl1 = wp + { {3'b000}, 1'b1};
assign wp_pl2 = wp + { {2'b00}, 2'b10};
always @(posedge clk )
begin
if(!rst) rp <= {4'b0000};
else
if(clr) rp <= {4'b0000};
else
if(re) rp <= rp_pl1;
end
assign rp_pl1 = rp + { {3'b000}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) && !gb);
assign full = ((wp == rp) && gb);
// Guard Bit ...
always @(posedge clk )
begin
if(!rst) gb <= 1'b0;
else
if(clr) gb <= 1'b0;
else
if((wp_pl1 == rp) && we) gb <= 1'b1;
else
if(re) gb <= 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//
// Guard Bit ...
always @(posedge clk )
begin
if(!rst) gb2 <= 1'b0;
else
if(clr) gb2 <= 1'b0;
else
if((wp_pl2 == rp) && we) gb2 <= 1'b1;
else
if((wp != rp) && re) gb2 <= 1'b0;
end
always @(posedge clk )
begin
if(!rst) full_r <= 1'b0;
else
if(clr) full_r <= 1'b0;
else
if(we && ((wp_pl1 == rp) && gb2) && !re) full_r <= 1'b1;
else
if(re && ((wp_pl1 != rp) | !gb2) && !we) full_r <= 1'b0;
end
always @(posedge clk )
begin
if(!rst) empty_r <= 1'b1;
else
if(clr) empty_r <= 1'b1;
else
if(we && ((wp != rp_pl1) | gb2) && !re) empty_r <= 1'b0;
else
if(re && ((wp == rp_pl1) && !gb2) && !we) empty_r <= 1'b1;
end
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full_n && Empty_n Flags
//
assign empty_n = cnt < `n;
assign full_n = !(cnt < (`max_size-`n+1));
assign level = {{cnt[`aw]}, {cnt[`aw]}} | cnt[`aw-1:`aw-2];
// N entries status
always @(posedge clk )
begin
if(!rst) cnt <= {4'b0000};
else
if(clr) cnt <= {4'b0000};
else
if( re && !we) cnt <= cnt + { 5'b11111};
else
if(!re && we) cnt <= cnt + { {4'b0000}, 1'b1};
end
////////////////////////////////////////////////////////////////////
//
// Registered Full_n && Empty_n Flags
//
always @(posedge clk )
begin
if(!rst) empty_n_r <= 1'b1;
else
if(clr) empty_n_r <= 1'b1;
else
if(we && (cnt >= (`n-1) ) && !re) empty_n_r <= 1'b0;
else
if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1;
end
always @(posedge clk )
begin
if(!rst) full_n_r <= 1'b0;
else
if(clr) full_n_r <= 1'b0;
else
if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1;
else
if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0;
end
endmodule
module arSRLFIFO_b (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N);
input CLK;
input RST_N;
input [152:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [152:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire fulln;
wire emptyn;
wire always_one;
wire always_zero;
assign always_one = 1'b1;
assign always_zero = 1'b0;
generic_fifo_sc_b fifo_1
(.clk(CLK),
.rst(RST_N),
.clr (CLR),
.din (D_IN),
.we (ENQ),
.dout (D_OUT),
.re (DEQ),
.full_r (FULL_N),
.empty_r(EMPTY_N),
.full_n_r (fulln),
.empty_n_r (emptyn)
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal FIFO Single Clock ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// D/L from: http://www.opencores.org/cores/generic_fifos/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __
//
// __Date: 2002-09-25 05:42:06 __
// __Revision: 1.1.1.1 __
// __Author: rudi __
// __Locker: __
// __State: Exp __
//
// Change History:
// __Log: not supported by cvs2svn __
//
//
//
//
//
//
//
//
//
//
/*
Description
===========
I/Os
----
rst low active, either sync. or async. master reset (see below how to select)
clr synchronous clear (just like reset but always synchronous), high active
re read enable, synchronous, high active
we read enable, synchronous, high active
din Data Input
dout Data Output
full Indicates the FIFO is full (combinatorial output)
full_r same as above, but registered output (see note below)
empty Indicates the FIFO is empty
empty_r same as above, but registered output (see note below)
full_n Indicates if the FIFO has space for N entries (combinatorial output)
full_n_r same as above, but registered output (see note below)
empty_n Indicates the FIFO has at least N entries (combinatorial output)
empty_n_r same as above, but registered output (see note below)
level indicates the FIFO level:
2'b00 0-25% full
2'b01 25-50% full
2'b10 50-75% full
2'b11 %75-100% full
combinatorial vs. registered status outputs
-------------------------------------------
Both the combinatorial and registered status outputs have exactly the same
synchronous timing. Meaning they are being asserted immediately at the clock
edge after the last read or write. The combinatorial outputs however, pass
through several levels of logic before they are output. The registered status
outputs are direct outputs of a flip-flop. The reason both are provided, is
that the registered outputs require quite a bit of additional logic inside
the FIFO. If you can meet timing of your device with the combinatorial
outputs, use them ! The FIFO will be smaller. If the status signals are
in the critical pass, use the registered outputs, they have a much smaller
output delay (actually only Tcq).
Parameters
----------
The FIFO takes 3 parameters:
dw Data bus width
aw Address bus width (Determines the FIFO size by evaluating 2^aw)
n N is a second status threshold constant for full_n and empty_n
If you have no need for the second status threshold, do not
connect the outputs and the logic should be removed by your
synthesis tool.
Synthesis Results
-----------------
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
at about 116 MHz (IO insertion disabled). The registered status outputs
are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
available.
Misc
----
This design assumes you will do appropriate status checking externally.
IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
empty will place the FIFO in an undefined state.
*/
// Selecting Sync. or Async Reset
// ------------------------------
// Uncomment one of the two lines below. The first line for
// synchronous reset, the second for asynchronous reset
//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset
//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
module generic_fifo_sc_b(clk, rst, clr, din, we, dout, re,
full_r, empty_r,
full_n_r, empty_n_r);
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
input clk, rst, clr;
input [`dw-1:0] din;
input we;
output [`dw-1:0] dout;
input re;
output full, full_r;
output empty, empty_r;
output full_n, full_n_r;
output empty_n, empty_n_r;
output [1:0] level;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [`aw-1:0] wp;
wire [`aw-1:0] wp_pl1;
wire [`aw-1:0] wp_pl2;
reg [`aw-1:0] rp;
wire [`aw-1:0] rp_pl1;
reg full_r;
reg empty_r;
reg gb;
reg gb2;
reg [`aw:0] cnt;
wire full_n, empty_n;
reg full_n_r, empty_n_r;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
wire always_zero;
assign always_zero = 1'b0;
wire [`dw-1:0] junk_out;
wire [`dw-1:0] junk_in;
// manually assign
assign junk_in = 0;
dual_port_ram ram1(
.clk( clk ),
.addr1( rp ),
.addr2( wp ),
.we1( we ),
.we2( always_zero ),
.out1( doutz ),
.out2( junk_out ),
.data1( din ),
.data2 ( junk_in)
);
wire [`dw-1:0] doutz;
assign dout = (1'b1) ? doutz: junk_out;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk )
begin
if(!rst) wp <= {4'b0000};
else
if(clr) wp <= {4'b0000};
else
if(we) wp <= wp_pl1;
end
assign wp_pl1 = wp + { {3'b000}, 1'b1};
assign wp_pl2 = wp + { {2'b00}, 2'b10};
always @(posedge clk )
begin
if(!rst) rp <= {4'b0000};
else
if(clr) rp <= {4'b0000};
else
if(re) rp <= rp_pl1;
end
assign rp_pl1 = rp + { {3'b000}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) && !gb);
assign full = ((wp == rp) && gb);
// Guard Bit ...
always @(posedge clk )
begin
if(!rst) gb <= 1'b0;
else
if(clr) gb <= 1'b0;
else
if((wp_pl1 == rp) && we) gb <= 1'b1;
else
if(re) gb <= 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//
// Guard Bit ...
always @(posedge clk )
begin
if(!rst) gb2 <= 1'b0;
else
if(clr) gb2 <= 1'b0;
else
if((wp_pl2 == rp) && we) gb2 <= 1'b1;
else
if((wp != rp) && re) gb2 <= 1'b0;
end
always @(posedge clk )
begin
if(!rst) full_r <= 1'b0;
else
if(clr) full_r <= 1'b0;
else
if(we && ((wp_pl1 == rp) && gb2) && !re) full_r <= 1'b1;
else
if(re && ((wp_pl1 != rp) | !gb2) && !we) full_r <= 1'b0;
end
always @(posedge clk )
begin
if(!rst) empty_r <= 1'b1;
else
if(clr) empty_r <= 1'b1;
else
if(we && ((wp != rp_pl1) | gb2) && !re) empty_r <= 1'b0;
else
if(re && ((wp == rp_pl1) && !gb2) && !we) empty_r <= 1'b1;
end
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full_n && Empty_n Flags
//
assign empty_n = cnt < `n;
assign full_n = !(cnt < (`max_size-`n+1));
assign level = {{cnt[`aw]}, {cnt[`aw]}} | cnt[`aw-1:`aw-2];
// N entries status
always @(posedge clk )
begin
if(!rst) cnt <= {4'b0000};
else
if(clr) cnt <= {4'b0000};
else
if( re && !we) cnt <= cnt + { 5'b11111};
else
if(!re && we) cnt <= cnt + { {4'b0000}, 1'b1};
end
////////////////////////////////////////////////////////////////////
//
// Registered Full_n && Empty_n Flags
//
always @(posedge clk )
begin
if(!rst) empty_n_r <= 1'b1;
else
if(clr) empty_n_r <= 1'b1;
else
if(we && (cnt >= (`n-1) ) && !re) empty_n_r <= 1'b0;
else
if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1;
end
always @(posedge clk )
begin
if(!rst) full_n_r <= 1'b0;
else
if(clr) full_n_r <= 1'b0;
else
if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1;
else
if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0;
end
endmodule
module arSRLFIFO_c (CLK, RST_N, D_IN,ENQ,DEQ,CLR,D_OUT,EMPTY_N,FULL_N);
input CLK;
input RST_N;
input [152:0] D_IN;
input ENQ;
input DEQ;
input CLR;
output [152:0] D_OUT;
output EMPTY_N;
output FULL_N;
wire fulln;
wire emptyn;
wire always_one;
wire always_zero;
assign always_one = 1'b1;
assign always_zero = 1'b0;
generic_fifo_sc_c fifo_1
(.clk(CLK),
.rst(RST_N),
.clr (CLR),
.din (D_IN),
.we (ENQ),
.dout (D_OUT),
.re (DEQ),
.full_r (FULL_N),
.empty_r(EMPTY_N),
.full_n_r (fulln),
.empty_n_r (emptyn)
);
endmodule
/////////////////////////////////////////////////////////////////////
//// ////
//// Universal FIFO Single Clock ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// D/L from: http://www.opencores.org/cores/generic_fifos/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2002 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// __Id: generic_fifo_sc_a.v,v 1.1.1.1 2002-09-25 05:42:06 rudi Exp __
//
// __Date: 2002-09-25 05:42:06 __
// __Revision: 1.1.1.1 __
// __Author: rudi __
// __Locker: __
// __State: Exp __
//
// Change History:
// __Log: not supported by cvs2svn __
//
//
//
//
//
//
//
//
//
//
/*
Description
===========
I/Os
----
rst low active, either sync. or async. master reset (see below how to select)
clr synchronous clear (just like reset but always synchronous), high active
re read enable, synchronous, high active
we read enable, synchronous, high active
din Data Input
dout Data Output
full Indicates the FIFO is full (combinatorial output)
full_r same as above, but registered output (see note below)
empty Indicates the FIFO is empty
empty_r same as above, but registered output (see note below)
full_n Indicates if the FIFO has space for N entries (combinatorial output)
full_n_r same as above, but registered output (see note below)
empty_n Indicates the FIFO has at least N entries (combinatorial output)
empty_n_r same as above, but registered output (see note below)
level indicates the FIFO level:
2'b00 0-25% full
2'b01 25-50% full
2'b10 50-75% full
2'b11 %75-100% full
combinatorial vs. registered status outputs
-------------------------------------------
Both the combinatorial and registered status outputs have exactly the same
synchronous timing. Meaning they are being asserted immediately at the clock
edge after the last read or write. The combinatorial outputs however, pass
through several levels of logic before they are output. The registered status
outputs are direct outputs of a flip-flop. The reason both are provided, is
that the registered outputs require quite a bit of additional logic inside
the FIFO. If you can meet timing of your device with the combinatorial
outputs, use them ! The FIFO will be smaller. If the status signals are
in the critical pass, use the registered outputs, they have a much smaller
output delay (actually only Tcq).
Parameters
----------
The FIFO takes 3 parameters:
dw Data bus width
aw Address bus width (Determines the FIFO size by evaluating 2^aw)
n N is a second status threshold constant for full_n and empty_n
If you have no need for the second status threshold, do not
connect the outputs and the logic should be removed by your
synthesis tool.
Synthesis Results
-----------------
In a Spartan 2e a 8 bit wide, 8 entries deep FIFO, takes 85 LUTs and runs
at about 116 MHz (IO insertion disabled). The registered status outputs
are valid after 2.1NS, the combinatorial once take out to 6.5 NS to be
available.
Misc
----
This design assumes you will do appropriate status checking externally.
IMPORTANT ! writing while the FIFO is full or reading while the FIFO is
empty will place the FIFO in an undefined state.
*/
// Selecting Sync. or Async Reset
// ------------------------------
// Uncomment one of the two lines below. The first line for
// synchronous reset, the second for asynchronous reset
//`define SC_FIFO_ASYNC_RESET // Uncomment for Syncr. reset
//`define SC_FIFO_ASYNC_RESET or negedge rst // Uncomment for Async. reset
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
module generic_fifo_sc_c(clk, rst, clr, din, we, dout, re,
full_r, empty_r,
full_n_r, empty_n_r);
/*
parameter dw=8;
parameter aw=8;
parameter n=32;
parameter max_size = 1<<aw;
*/
input clk, rst, clr;
input [`dw-1:0] din;
input we;
output [`dw-1:0] dout;
input re;
output full, full_r;
output empty, empty_r;
output full_n, full_n_r;
output empty_n, empty_n_r;
output [1:0] level;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [`aw-1:0] wp;
wire [`aw-1:0] wp_pl1;
wire [`aw-1:0] wp_pl2;
reg [`aw-1:0] rp;
wire [`aw-1:0] rp_pl1;
reg full_r;
reg empty_r;
reg gb;
reg gb2;
reg [`aw:0] cnt;
wire full_n, empty_n;
reg full_n_r, empty_n_r;
////////////////////////////////////////////////////////////////////
//
// Memory Block
//
wire always_zero;
assign always_zero = 1'b0;
wire [`dw-1:0] junk_out;
wire [`dw-1:0] junk_in;
// manually assign
assign junk_in = 0;
dual_port_ram ram1(
.clk( clk ),
.addr1( rp ),
.addr2( wp ),
.we1( we ),
.we2( always_zero ),
.out1( doutz ),
.out2( junk_out ),
.data1( din ),
.data2 ( junk_in)
);
wire [`dw-1:0] doutz;
assign dout = (1'b1) ? doutz: junk_out;
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
always @(posedge clk )
begin
if(!rst) wp <= {4'b0000};
else
if(clr) wp <= {4'b0000};
else
if(we) wp <= wp_pl1;
end
assign wp_pl1 = wp + { {3'b000}, 1'b1};
assign wp_pl2 = wp + { {2'b00}, 2'b10};
always @(posedge clk )
begin
if(!rst) rp <= {4'b0000};
else
if(clr) rp <= {4'b0000};
else
if(re) rp <= rp_pl1;
end
assign rp_pl1 = rp + { {3'b000}, 1'b1};
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full & Empty Flags
//
assign empty = ((wp == rp) && !gb);
assign full = ((wp == rp) && gb);
// Guard Bit ...
always @(posedge clk )
begin
if(!rst) gb <= 1'b0;
else
if(clr) gb <= 1'b0;
else
if((wp_pl1 == rp) && we) gb <= 1'b1;
else
if(re) gb <= 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// Registered Full & Empty Flags
//
// Guard Bit ...
always @(posedge clk )
begin
if(!rst) gb2 <= 1'b0;
else
if(clr) gb2 <= 1'b0;
else
if((wp_pl2 == rp) && we) gb2 <= 1'b1;
else
if((wp != rp) && re) gb2 <= 1'b0;
end
always @(posedge clk )
begin
if(!rst) full_r <= 1'b0;
else
if(clr) full_r <= 1'b0;
else
if(we && ((wp_pl1 == rp) && gb2) && !re) full_r <= 1'b1;
else
if(re && ((wp_pl1 != rp) | !gb2) && !we) full_r <= 1'b0;
end
always @(posedge clk )
begin
if(!rst) empty_r <= 1'b1;
else
if(clr) empty_r <= 1'b1;
else
if(we && ((wp != rp_pl1) | gb2) && !re) empty_r <= 1'b0;
else
if(re && ((wp == rp_pl1) && !gb2) && !we) empty_r <= 1'b1;
end
////////////////////////////////////////////////////////////////////
//
// Combinatorial Full_n && Empty_n Flags
//
assign empty_n = cnt < `n;
assign full_n = !(cnt < (`max_size-`n+1));
assign level = {{cnt[`aw]}, {cnt[`aw]}} | cnt[`aw-1:`aw-2];
// N entries status
always @(posedge clk )
begin
if(!rst) cnt <= {4'b0000};
else
if(clr) cnt <= {4'b0000};
else
if( re && !we) cnt <= cnt + { 5'b11111};
else
if(!re && we) cnt <= cnt + { {4'b0000}, 1'b1};
end
////////////////////////////////////////////////////////////////////
//
// Registered Full_n && Empty_n Flags
//
always @(posedge clk )
begin
if(!rst) empty_n_r <= 1'b1;
else
if(clr) empty_n_r <= 1'b1;
else
if(we && (cnt >= (`n-1) ) && !re) empty_n_r <= 1'b0;
else
if(re && (cnt <= `n ) && !we) empty_n_r <= 1'b1;
end
always @(posedge clk )
begin
if(!rst) full_n_r <= 1'b0;
else
if(clr) full_n_r <= 1'b0;
else
if(we && (cnt >= (`max_size-`n) ) && !re) full_n_r <= 1'b1;
else
if(re && (cnt <= (`max_size-`n+1)) && !we) full_n_r <= 1'b0;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: rd_data_gen.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module has all the timing control for generating "compare data"
// to compare the read data from memory.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_rd_data_gen #
(
parameter TCQ = 100,
parameter FAMILY = "VIRTEX7", // "SPARTAN6", "VIRTEX6"
parameter MEM_TYPE = "DDR3",
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter COLUMN_WIDTH = 10
)
(
input clk_i, //
input [4:0] rst_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i, // "00" = bram;
input mode_load_i,
input [3:0] vio_instr_mode_value,
output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted.
// And then it should reasserted when
// it is generating the last_word.
input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid.
output reg cmd_start_o,
// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data
output user_bl_cnt_is_1_o,
input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6
// connect from mcb_rd_empty when used as rd_data_gen in sp6
// connect from rd_data_valid in v6
// When both data_rdy and data_valid is asserted, the ouput data is valid.
output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the
// pattern is available.
// output [DWIDTH-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
output [31:0] tg_st_addr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o // generated data pattern NUM_DQ_PINS*nCK_PER_CLK*2-1
);
//
wire [31:0] prbs_data;
reg cmd_start;
reg [31:0] adata;
reg [31:0] hdata;
reg [31:0] ndata;
reg [31:0] w1data;
reg [NUM_DQ_PINS*4-1:0] v6_w1data;
reg [31:0] w0data;
reg [DWIDTH-1:0] data;
reg cmd_rdy;
reg [BL_WIDTH:0]user_burst_cnt;
reg [31:0] w3data;
reg prefetch;
assign data_port_fifo_rdy = data_rdy_i;
reg user_bl_cnt_is_1;
assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
always @ (posedge clk_i)
begin
if (data_port_fifo_rdy)
if ((user_burst_cnt == 2 && FAMILY == "SPARTAN6")
|| (user_burst_cnt == 2 && FAMILY == "VIRTEX6")
)
user_bl_cnt_is_1 <= #TCQ 1'b1;
else
user_bl_cnt_is_1 <= #TCQ 1'b0;
end
//reg cmd_start_b;
always @(cmd_valid_i,data_port_fifo_rdy,cmd_rdy,user_bl_cnt_is_1,prefetch)
begin
cmd_start = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
cmd_start_o = cmd_valid_i & cmd_rdy & ( data_port_fifo_rdy | prefetch) ;
end
// counter to count user burst length
always @( posedge clk_i)
begin
if ( rst_i[0] )
user_burst_cnt <= #TCQ 'd0;
else if(cmd_valid_i && cmd_rdy && ( data_port_fifo_rdy | prefetch) ) begin
// SPATAN6 has maximum of burst length of 64.
if (FAMILY == "SPARTAN6" && bl_i[5:0] == 6'b000000)
begin
user_burst_cnt[6:0] <= #TCQ 7'd64;
user_burst_cnt[BL_WIDTH:7] <= 'b0;
end
else if (FAMILY == "VIRTEX6" && bl_i[BL_WIDTH - 1:0] == {BL_WIDTH {1'b0}})
user_burst_cnt <= #TCQ {1'b1, {BL_WIDTH{1'b0}}};
else
user_burst_cnt <= #TCQ {1'b0,bl_i };
end
else if(data_port_fifo_rdy)
if (user_burst_cnt != 6'd0)
user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
else
user_burst_cnt <= #TCQ 'd0;
end
// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
// is assert and reassert during the last data
//data_valid_o logic
always @( posedge clk_i)
begin
if ( rst_i[0] )
prefetch <= #TCQ 1'b1;
else if (data_port_fifo_rdy || cmd_start)
prefetch <= #TCQ 1'b0;
else if (user_burst_cnt == 0 && ~data_port_fifo_rdy)
prefetch <= #TCQ 1'b1;
end
assign cmd_rdy_o = cmd_rdy ;
always @( posedge clk_i)
begin
if ( rst_i[0] )
cmd_rdy <= #TCQ 1'b1;
else if (cmd_valid_i && cmd_rdy && (data_port_fifo_rdy || prefetch ))
cmd_rdy <= #TCQ 1'b0;
else if ((data_port_fifo_rdy && user_burst_cnt == 2 && vio_instr_mode_value != 7 ) ||
(data_port_fifo_rdy && user_burst_cnt == 1 && vio_instr_mode_value == 7 ))
cmd_rdy <= #TCQ 1'b1;
end
always @ (data_port_fifo_rdy)
if (FAMILY == "SPARTAN6")
data_valid_o = data_port_fifo_rdy;
else
data_valid_o = data_port_fifo_rdy;
/*
generate
if (FAMILY == "SPARTAN6")
begin : SP6_DGEN
s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.data_mask_o (),
.bram_rd_valid_o ()
);
end
endgenerate*/
//generate
//if (FAMILY == "VIRTEX6")
//begin : V_DGEN
mig_7series_v1_9_s7ven_data_gen #
(
.TCQ (TCQ),
.DMODE ("READ"),
.nCK_PER_CLK (nCK_PER_CLK),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.ADDR_WIDTH (32 ),
.BL_WIDTH (BL_WIDTH ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.DWIDTH (DWIDTH ),
.DATA_PATTERN (DATA_PATTERN ),
.NUM_DQ_PINS (NUM_DQ_PINS ),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.COLUMN_WIDTH (COLUMN_WIDTH)
)
s7ven_data_gen
(
.clk_i (clk_i ),
.rst_i (rst_i[1] ),
.data_rdy_i (data_rdy_i ),
.mem_init_done_i (1'b1),
.wr_data_mask_gen_i (1'b0),
.prbs_fseed_i (prbs_fseed_i),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_i ),
.cmd_startA (cmd_start ),
.cmd_startB (cmd_start ),
.cmd_startC (cmd_start ),
.cmd_startD (cmd_start ),
.cmd_startE (cmd_start ),
.m_addr_i (addr_i),//(m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (addr_i ),
.user_burst_cnt (user_burst_cnt),
.fifo_rdy_i (data_port_fifo_rdy ),
.data_o (data_o ),
.tg_st_addr_o (tg_st_addr_o),
.data_mask_o (),
.bram_rd_valid_o ()
);
//end
//endgenerate
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_axi_basic_rx_null_gen.v
// Version : 3.2
// //
// Description: //
// TRN to AXI RX null generator. Generates null packets for use in //
// discontinue situations. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_null_gen //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_axi_basic_rx_null_gen # (
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
input m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
input m_axis_rx_tlast, // RX data is last
input [21:0] m_axis_rx_tuser, // RX user signals
// Null Inputs
//-----------
output null_rx_tvalid, // NULL generated tvalid
output null_rx_tlast, // NULL generated tlast
output [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
output null_rdst_rdy, // NULL generated rdst_rdy
output reg [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
localparam INTERFACE_WIDTH_DWORDS = (C_DATA_WIDTH == 128) ? 11'd4 :
(C_DATA_WIDTH == 64) ? 11'd2 : 11'd1;
//----------------------------------------------------------------------------//
// NULL packet generator state machine //
// This state machine shadows the AXI RX interface, tracking each packet as //
// it's passed to the AXI user. When a multi-cycle packet is detected, the //
// state machine automatically generates a "null" packet. In the event of a //
// discontinue, the RX pipeline can switch over to this null packet as //
// necessary. //
//----------------------------------------------------------------------------//
// State machine variables and states
localparam IDLE = 0;
localparam IN_PACKET = 1;
reg cur_state;
reg next_state;
// Signals for tracking a packet on the AXI interface
reg [11:0] reg_pkt_len_counter;
reg [11:0] pkt_len_counter;
wire [11:0] pkt_len_counter_dec;
wire pkt_done;
// Calculate packet fields, which are needed to determine total packet length.
wire [11:0] new_pkt_len;
wire [9:0] payload_len;
wire [1:0] packet_fmt;
wire packet_td;
reg [3:0] packet_overhead;
// Misc.
wire [KEEP_WIDTH-1:0] eof_tkeep;
wire straddle_sof;
wire eof;
// Create signals to detect sof and eof situations. These signals vary depending
// on data width.
assign eof = m_axis_rx_tuser[21];
generate
if(C_DATA_WIDTH == 128) begin : sof_eof_128
assign straddle_sof = (m_axis_rx_tuser[14:13] == 2'b11);
end
else begin : sof_eof_64_32
assign straddle_sof = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Calculate the length of the packet being presented on the RX interface. To //
// do so, we need the relevent packet fields that impact total packet length. //
// These are: //
// - Header length: obtained from bit 1 of FMT field in 1st DWORD of header //
// - Payload length: obtained from LENGTH field in 1st DWORD of header //
// - TLP digest: obtained from TD field in 1st DWORD of header //
// - Current data: the number of bytes that have already been presented //
// on the data interface //
// //
// packet length = header + payload + tlp digest - # of DWORDS already //
// transmitted //
// //
// packet_overhead is where we calculate everything except payload. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : len_calc_128
assign packet_fmt = straddle_sof ?
m_axis_rx_tdata[94:93] : m_axis_rx_tdata[30:29];
assign packet_td = straddle_sof ?
m_axis_rx_tdata[79] : m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ?
(straddle_sof ? m_axis_rx_tdata[73:64] : m_axis_rx_tdata[9:0]) : 10'h0;
always @(*) begin
// In 128-bit mode, the amount of data currently on the interface
// depends on whether we're straddling or not. If so, 2 DWORDs have been
// seen. If not, 4 DWORDs.
case({packet_fmt[0], packet_td, straddle_sof})
// Header + TD - Data currently on interface
3'b0_0_0: packet_overhead = 4'd3 + 4'd0 - 4'd4;
3'b0_0_1: packet_overhead = 4'd3 + 4'd0 - 4'd2;
3'b0_1_0: packet_overhead = 4'd3 + 4'd1 - 4'd4;
3'b0_1_1: packet_overhead = 4'd3 + 4'd1 - 4'd2;
3'b1_0_0: packet_overhead = 4'd4 + 4'd0 - 4'd4;
3'b1_0_1: packet_overhead = 4'd4 + 4'd0 - 4'd2;
3'b1_1_0: packet_overhead = 4'd4 + 4'd1 - 4'd4;
3'b1_1_1: packet_overhead = 4'd4 + 4'd1 - 4'd2;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
else if(C_DATA_WIDTH == 64) begin : len_calc_64
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 64-bit mode: no straddling, so always 2 DWORDs
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead[1:0] = 2'b01 ;//4'd3 + 4'd0 - 4'd2; // 1
2'b0_1: packet_overhead[1:0] = 2'b10 ;//4'd3 + 4'd1 - 4'd2; // 2
2'b1_0: packet_overhead[1:0] = 2'b10 ;//4'd4 + 4'd0 - 4'd2; // 2
2'b1_1: packet_overhead[1:0] = 2'b11 ;//4'd4 + 4'd1 - 4'd2; // 3
endcase
end
assign new_pkt_len =
{{10{1'b0}}, packet_overhead[1:0]} + {2'b0, payload_len};
end
else begin : len_calc_32
assign packet_fmt = m_axis_rx_tdata[30:29];
assign packet_td = m_axis_rx_tdata[15];
assign payload_len = packet_fmt[1] ? m_axis_rx_tdata[9:0] : 10'h0;
always @(*) begin
// 32-bit mode: no straddling, so always 1 DWORD
case({packet_fmt[0], packet_td})
// Header + TD - Data currently on interface
2'b0_0: packet_overhead = 4'd3 + 4'd0 - 4'd1;
2'b0_1: packet_overhead = 4'd3 + 4'd1 - 4'd1;
2'b1_0: packet_overhead = 4'd4 + 4'd0 - 4'd1;
2'b1_1: packet_overhead = 4'd4 + 4'd1 - 4'd1;
endcase
end
assign new_pkt_len =
{{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
end
endgenerate
// Now calculate actual packet length, adding the packet overhead and the
// payload length. This is signed math, so sign-extend packet_overhead.
// NOTE: a payload length of zero means 1024 DW in the PCIe spec, but this
// behavior isn't supported in our block.
//assign new_pkt_len =
// {{9{packet_overhead[3]}}, packet_overhead[2:0]} + {2'b0, payload_len};
// Math signals needed in the state machine below. These are seperate wires to
// help ensure synthesis tools sre smart about optimizing them.
assign pkt_len_counter_dec = reg_pkt_len_counter - INTERFACE_WIDTH_DWORDS;
assign pkt_done = (reg_pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
//----------------------------------------------------------------------------//
// Null generator Mealy state machine. Determine outputs based on: //
// 1) current st //
// 2) current inp //
//----------------------------------------------------------------------------//
always @(*) begin
case (cur_state)
// IDLE state: the interface is IDLE and we're waiting for a packet to
// start. If a packet starts, move to state IN_PACKET and begin tracking
// it as long as it's NOT a single cycle packet (indicated by assertion of
// eof at packet start)
IDLE: begin
if(m_axis_rx_tvalid && m_axis_rx_tready && !eof) begin
next_state = IN_PACKET;
end
else begin
next_state = IDLE;
end
pkt_len_counter = new_pkt_len;
end
// IN_PACKET: a mutli-cycle packet is in progress and we're tracking it. We
// are in lock-step with the AXI interface decrementing our packet length
// tracking reg, and waiting for the packet to finish.
//
// * If packet finished and a new one starts, this is a straddle situation.
// Next state is IN_PACKET (128-bit only).
// * If the current packet is done, next state is IDLE.
// * Otherwise, next state is IN_PACKET.
IN_PACKET: begin
// Straddle packet
if((C_DATA_WIDTH == 128) && straddle_sof && m_axis_rx_tvalid) begin
pkt_len_counter = new_pkt_len;
next_state = IN_PACKET;
end
// Current packet finished
else if(m_axis_rx_tready && pkt_done)
begin
pkt_len_counter = new_pkt_len;
next_state = IDLE;
end
// Packet in progress
else begin
if(m_axis_rx_tready) begin
// Not throttled
pkt_len_counter = pkt_len_counter_dec;
end
else begin
// Throttled
pkt_len_counter = reg_pkt_len_counter;
end
next_state = IN_PACKET;
end
end
default: begin
pkt_len_counter = reg_pkt_len_counter;
next_state = IDLE;
end
endcase
end
// Synchronous NULL packet generator state machine logic
always @(posedge user_clk) begin
if(user_rst) begin
cur_state <= #TCQ IDLE;
reg_pkt_len_counter <= #TCQ 12'h0;
end
else begin
cur_state <= #TCQ next_state;
reg_pkt_len_counter <= #TCQ pkt_len_counter;
end
end
// Generate tkeep/is_eof for an end-of-packet situation.
generate
if(C_DATA_WIDTH == 128) begin : strb_calc_128
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
10'd3: null_is_eof = 5'b11011;
10'd4: null_is_eof = 5'b11111;
default: null_is_eof = 5'b00011;
endcase
end
// tkeep not used in 128-bit interface
assign eof_tkeep = {KEEP_WIDTH{1'b0}};
end
else if(C_DATA_WIDTH == 64) begin : strb_calc_64
always @(*) begin
// Assign null_is_eof depending on how many DWORDs are left in the
// packet.
case(pkt_len_counter)
10'd1: null_is_eof = 5'b10011;
10'd2: null_is_eof = 5'b10111;
default: null_is_eof = 5'b00011;
endcase
end
// Assign tkeep to 0xFF or 0x0F depending on how many DWORDs are left in
// the current packet.
assign eof_tkeep = { ((pkt_len_counter == 12'd2) ? 4'hF:4'h0), 4'hF };
end
else begin : strb_calc_32
always @(*) begin
// is_eof is either on or off for 32-bit
if(pkt_len_counter == 12'd1) begin
null_is_eof = 5'b10011;
end
else begin
null_is_eof = 5'b00011;
end
end
// The entire DWORD is always valid in 32-bit mode, so tkeep is always 0xF
assign eof_tkeep = 4'hF;
end
endgenerate
// Finally, use everything we've generated to calculate our NULL outputs
assign null_rx_tvalid = 1'b1;
assign null_rx_tlast = (pkt_len_counter <= INTERFACE_WIDTH_DWORDS);
assign null_rx_tkeep = null_rx_tlast ? eof_tkeep : {KEEP_WIDTH{1'b1}};
assign null_rdst_rdy = null_rx_tlast;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
//============================================================
reg bad;
initial begin
bad=0;
c96(96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0000, 96'h0_0000_0000_0000_0000, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0002, 96'h4_4444_4444_4444_4444, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h0_2000_0000_0000_0000, 96'h0_0000_0000_0000_0044, 96'h0_0888_8888_8888_8888);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8888, 96'h0_0000_0000_0000_0001, 96'h0);
c96(96'h8_8888_8888_8888_8888, 96'h8_8888_8888_8888_8889, 96'h0_0000_0000_0000_0000, 96'h8_8888_8888_8888_8888);
c96(96'h1_0000_0000_8eba_434a, 96'h0_0000_0000_0000_0001, 96'h1_0000_0000_8eba_434a, 96'h0);
c96(96'h0003, 96'h0002, 96'h0001, 96'h0001);
c96(96'h0003, 96'h0003, 96'h0001, 96'h0000);
c96(96'h0003, 96'h0004, 96'h0000, 96'h0003);
c96(96'h0000, 96'hffff, 96'h0000, 96'h0000);
c96(96'hffff, 96'h0001, 96'hffff, 96'h0000);
c96(96'hffff, 96'hffff, 96'h0001, 96'h0000);
c96(96'hffff, 96'h0003, 96'h5555, 96'h0000);
c96(96'hffff_ffff, 96'h0001, 96'hffff_ffff, 96'h0000);
c96(96'hffff_ffff, 96'hffff, 96'h0001_0001, 96'h0000);
c96(96'hfffe_ffff, 96'hffff, 96'h0000_ffff, 96'hfffe);
c96(96'h1234_5678, 96'h9abc, 96'h0000_1e1e, 96'h2c70);
c96(96'h0000_0000, 96'h0001_0000, 96'h0000, 96'h0000_0000);
c96(96'h0007_0000, 96'h0003_0000, 96'h0002, 96'h0001_0000);
c96(96'h0007_0005, 96'h0003_0000, 96'h0002, 96'h0001_0005);
c96(96'h0006_0000, 96'h0002_0000, 96'h0003, 96'h0000_0000);
c96(96'h8000_0001, 96'h4000_7000, 96'h0001, 96'h3fff_9001);
c96(96'hbcde_789a, 96'hbcde_789a, 96'h0001, 96'h0000_0000);
c96(96'hbcde_789b, 96'hbcde_789a, 96'h0001, 96'h0000_0001);
c96(96'hbcde_7899, 96'hbcde_789a, 96'h0000, 96'hbcde_7899);
c96(96'hffff_ffff, 96'hffff_ffff, 96'h0001, 96'h0000_0000);
c96(96'hffff_ffff, 96'h0001_0000, 96'hffff, 96'h0000_ffff);
c96(96'h0123_4567_89ab, 96'h0001_0000, 96'h0123_4567, 96'h0000_89ab);
c96(96'h8000_fffe_0000, 96'h8000_ffff, 96'h0000_ffff, 96'h7fff_ffff);
c96(96'h8000_0000_0003, 96'h2000_0000_0001, 96'h0003, 96'h2000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000, 96'hffff_ffff, 96'h0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_0000_0000, 96'h0001_0001, 96'h0000_0000_0000);
c96(96'hfffe_ffff_0000_0000, 96'hffff_0000_0000, 96'h0000_ffff, 96'hfffe_0000_0000);
c96(96'h1234_5678_0000_0000, 96'h9abc_0000_0000, 96'h0000_1e1e, 96'h2c70_0000_0000);
c96(96'h0000_0000_0000_0000, 96'h0001_0000_0000_0000, 96'h0000, 96'h0000_0000_0000_0000);
c96(96'h0007_0000_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0000_0000_0000);
c96(96'h0007_0005_0000_0000, 96'h0003_0000_0000_0000, 96'h0002, 96'h0001_0005_0000_0000);
c96(96'h0006_0000_0000_0000, 96'h0002_0000_0000_0000, 96'h0003, 96'h0000_0000_0000_0000);
c96(96'h8000_0001_0000_0000, 96'h4000_7000_0000_0000, 96'h0001, 96'h3fff_9001_0000_0000);
c96(96'hbcde_789a_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hbcde_789b_0000_0000, 96'hbcde_789a_0000_0000, 96'h0001, 96'h0000_0001_0000_0000);
c96(96'hbcde_7899_0000_0000, 96'hbcde_789a_0000_0000, 96'h0000, 96'hbcde_7899_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'hffff_ffff_0000_0000, 96'h0001, 96'h0000_0000_0000_0000);
c96(96'hffff_ffff_0000_0000, 96'h0001_0000_0000_0000, 96'hffff, 96'h0000_ffff_0000_0000);
c96(96'h7fff_8000_0000_0000, 96'h8000_0000_0001, 96'h0000_fffe, 96'h7fff_ffff_0002);
c96(96'h8000_0000_fffe_0000, 96'h8000_0000_ffff, 96'h0000_ffff, 96'h7fff_ffff_ffff);
c96(96'h0008_8888_8888_8888_8888, 96'h0002_0000_0000_0000, 96'h0004_4444, 96'h0000_8888_8888_8888);
if (bad) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
task c96;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
c96u( u, v, expq, expr);
c96s( u, v, expq, expr);
c96s(-u, v,-expq,-expr);
c96s( u,-v,-expq, expr);
c96s(-u,-v, expq,-expr);
endtask
task c96u;
input [95:0] u;
input [95:0] v;
input [95:0] expq;
input [95:0] expr;
reg [95:0] gotq;
reg [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /u %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
task c96s;
input signed [95:0] u;
input signed [95:0] v;
input signed [95:0] expq;
input signed [95:0] expr;
reg signed [95:0] gotq;
reg signed [95:0] gotr;
gotq = u/v;
gotr = u%v;
if (gotq != expq && v!=0) begin
bad = 1;
end
if (gotr != expr && v!=0) begin
bad = 1;
end
if (bad
`ifdef TEST_VERBOSE
|| 1
`endif
) begin
$write(" %x /s %x = got %x exp %x %% got %x exp %x", u,v,gotq,expq,gotr,expr);
// Test for v=0 to prevent Xs causing grief
if (gotq != expq && v!=0) $write(" BADQ");
if (gotr != expr && v!=0) $write(" BADR");
$write("\n");
end
endtask
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_1r1w_16x160.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
// _____________________________________________________________________________
//
// rf_16x156_scan - DFT scan wrapper around 'rf_16x156' part.
// _____________________________________________________________________________
//
// Description:
// The data out of the 'rf_16x156' part is not scannable. This wrapper adds
// a register to monitor the output of the memory array and a mux, enabled
// by 'testmux_sel' to enable this register to control the cone of logic down
// stream of the memories data out port.
// _____________________________________________________________________________
`include "sys.h"
module jbi_1r1w_16x160 (/*AUTOARG*/
// Outputs
dout,
// Inputs
wrclk, wr_en, wr_adr, din, rdclk, read_en, rd_adr, rst_l, hold,
testmux_sel, rst_tri_en
);
// Write port.
input wrclk;
input wr_en;
input [3:0] wr_adr;
input [159:0] din;
// Read port.
input rdclk;
input read_en;
input [3:0] rd_adr;
output [159:0] dout;
// Other.
input rst_l;
input hold;
input testmux_sel;
input rst_tri_en;
// Wires and Regs.
wire [159:0] dout_array;
wire [159:0] dout_scan;
wire si_r, si_w;
// Register Array.
/* bw_r_rf16x160 AUTO_TEMPLATE (
.dout (dout_array),
.so_w (),
.so_r (),
.se (1'b0),
.si (),
.sehold (hold),
.reset_l (rst_l),
.word_wen ( {4{1'b1}} ),
.byte_wen ( {20{1'b1}} ),
.wr_clk (wrclk),
.rd_clk (rdclk),
) */
bw_r_rf16x160 array (/*AUTOINST*/
// Outputs
.dout (dout_array), // Templated
.so_w (), // Templated
.so_r (), // Templated
// Inputs
.din (din[159:0]),
.rd_adr (rd_adr[3:0]),
.wr_adr (wr_adr[3:0]),
.read_en (read_en),
.wr_en (wr_en),
.rst_tri_en (rst_tri_en),
.word_wen ( {4{1'b1}} ), // Templated
.byte_wen ( {20{1'b1}} ), // Templated
.rd_clk (rdclk), // Templated
.wr_clk (wrclk), // Templated
.se (1'b0), // Templated
.si_r (si_r),
.si_w (si_w),
.reset_l (rst_l), // Templated
.sehold (hold)); // Templated
// DFT Scan port.
assign dout = (testmux_sel)? dout_scan: dout_array;
wire [159:0] next_dout_scan = dout_array;
dff_ns #(160) dout_scan_reg (.din(next_dout_scan), .q(dout_scan), .clk(rdclk));
endmodule
// Local Variables:
// verilog-library-directories:("../../../srams/rtl")
// verilog-auto-sense-defines-constant:t
// verilog-auto-inst-ordered:t
// End:
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Thu May 1 14:05:15 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/bram/bram_funcsim.v
// Design : bram
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_2,Vivado 2014.1" *) (* CHECK_LICENSE_TYPE = "bram,blk_mem_gen_v8_2,{}" *)
(* core_generation_info = "bram,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=bram.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=16,C_READ_WIDTH_A=16,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=16,C_READ_WIDTH_B=16,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=1,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 5.11005 mW}" *)
(* NotValidForBitStream *)
module bram
(clka,
wea,
addra,
dina,
clkb,
addrb,
doutb);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
input [0:0]wea;
input [10:0]addra;
input [15:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK" *) input clkb;
input [10:0]addrb;
output [15:0]doutb;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]doutb;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [15:0]NLW_U0_douta_UNCONNECTED;
wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [15:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "11" *)
(* C_ADDRB_WIDTH = "11" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 5.11005 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram.mem" *)
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "0" *)
(* C_MEM_TYPE = "1" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "2048" *)
(* C_READ_DEPTH_B = "2048" *)
(* C_READ_WIDTH_A = "16" *)
(* C_READ_WIDTH_B = "16" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "2048" *)
(* C_WRITE_DEPTH_B = "2048" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "16" *)
(* C_WRITE_WIDTH_B = "16" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
bramblk_mem_gen_v8_2__parameterized0 U0
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(NLW_U0_douta_UNCONNECTED[15:0]),
.doutb(doutb),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rstb(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[15:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bramblk_mem_gen_generic_cstr
(doutb,
wea,
clka,
clkb,
addra,
addrb,
dina);
output [15:0]doutb;
input [0:0]wea;
input clka;
input clkb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]doutb;
wire [0:0]wea;
bramblk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bramblk_mem_gen_prim_width
(doutb,
wea,
clka,
clkb,
addra,
addrb,
dina);
output [15:0]doutb;
input [0:0]wea;
input clka;
input clkb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]doutb;
wire [0:0]wea;
bramblk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module bramblk_mem_gen_prim_wrapper
(doutb,
wea,
clka,
clkb,
addra,
addrb,
dina);
output [15:0]doutb;
input [0:0]wea;
input clka;
input clkb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]doutb;
wire \n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire \n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(1),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,addrb,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clkb),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:16],doutb}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:2],\n_74_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,\n_75_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(wea),
.ENBWREN(1'b1),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({1'b1,1'b1,1'b1,1'b1}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bramblk_mem_gen_top
(doutb,
wea,
clka,
clkb,
addra,
addrb,
dina);
output [15:0]doutb;
input [0:0]wea;
input clka;
input clkb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]doutb;
wire [0:0]wea;
bramblk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *) (* C_FAMILY = "zynq" *) (* C_XDEVICEFAMILY = "zynq" *)
(* C_ELABORATION_DIR = "./" *) (* C_INTERFACE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_SLAVE_TYPE = "0" *) (* C_USE_BRAM_BLOCK = "0" *) (* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *) (* C_HAS_AXI_ID = "0" *) (* C_AXI_ID_WIDTH = "4" *)
(* C_MEM_TYPE = "1" *) (* C_BYTE_SIZE = "9" *) (* C_ALGORITHM = "1" *)
(* C_PRIM_TYPE = "1" *) (* C_LOAD_INIT_FILE = "0" *) (* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
(* C_INIT_FILE = "bram.mem" *) (* C_USE_DEFAULT_DATA = "0" *) (* C_DEFAULT_DATA = "0" *)
(* C_HAS_RSTA = "0" *) (* C_RST_PRIORITY_A = "CE" *) (* C_RSTRAM_A = "0" *)
(* C_INITA_VAL = "0" *) (* C_HAS_ENA = "0" *) (* C_HAS_REGCEA = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "16" *) (* C_READ_WIDTH_A = "16" *) (* C_WRITE_DEPTH_A = "2048" *)
(* C_READ_DEPTH_A = "2048" *) (* C_ADDRA_WIDTH = "11" *) (* C_HAS_RSTB = "0" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_RSTRAM_B = "0" *) (* C_INITB_VAL = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_REGCEB = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_WEB_WIDTH = "1" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_B = "16" *)
(* C_READ_WIDTH_B = "16" *) (* C_WRITE_DEPTH_B = "2048" *) (* C_READ_DEPTH_B = "2048" *)
(* C_ADDRB_WIDTH = "11" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *) (* C_HAS_MEM_OUTPUT_REGS_B = "1" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_ECC = "0" *) (* C_EN_ECC_PIPE = "0" *) (* C_HAS_INJECTERR = "0" *)
(* C_SIM_COLLISION_CHECK = "ALL" *) (* C_COMMON_CLK = "0" *) (* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_EN_SLEEP_PIN = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_COUNT_36K_BRAM = "1" *)
(* C_COUNT_18K_BRAM = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 5.11005 mW" *) (* downgradeipidentifiedwarnings = "yes" *)
module bramblk_mem_gen_v8_2__parameterized0
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [10:0]addra;
input [15:0]dina;
output [15:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [10:0]addrb;
input [15:0]dinb;
output [15:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [10:0]rdaddrecc;
input sleep;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [15:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [15:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [10:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]dinb;
wire [15:0]doutb;
wire eccpipece;
wire ena;
wire enb;
wire injectdbiterr;
wire injectsbiterr;
wire regcea;
wire regceb;
wire rsta;
wire rstb;
wire s_aclk;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_injectdbiterr;
wire s_axi_injectsbiterr;
wire s_axi_rready;
wire [15:0]s_axi_wdata;
wire s_axi_wlast;
wire [0:0]s_axi_wstrb;
wire s_axi_wvalid;
wire sleep;
wire [0:0]wea;
wire [0:0]web;
assign dbiterr = \<const0> ;
assign douta[15] = \<const0> ;
assign douta[14] = \<const0> ;
assign douta[13] = \<const0> ;
assign douta[12] = \<const0> ;
assign douta[11] = \<const0> ;
assign douta[10] = \<const0> ;
assign douta[9] = \<const0> ;
assign douta[8] = \<const0> ;
assign douta[7] = \<const0> ;
assign douta[6] = \<const0> ;
assign douta[5] = \<const0> ;
assign douta[4] = \<const0> ;
assign douta[3] = \<const0> ;
assign douta[2] = \<const0> ;
assign douta[1] = \<const0> ;
assign douta[0] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bramblk_mem_gen_v8_2_synth inst_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module bramblk_mem_gen_v8_2_synth
(doutb,
wea,
clka,
clkb,
addra,
addrb,
dina);
output [15:0]doutb;
input [0:0]wea;
input clka;
input clkb;
input [10:0]addra;
input [10:0]addrb;
input [15:0]dina;
wire [10:0]addra;
wire [10:0]addrb;
wire clka;
wire clkb;
wire [15:0]dina;
wire [15:0]doutb;
wire [0:0]wea;
bramblk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.addra(addra),
.addrb(addrb),
.clka(clka),
.clkb(clkb),
.dina(dina),
.doutb(doutb),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// one-way bidirectional connection:
// altera message_off 10665
module acl_ic_slave_endpoint
#(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer NUM_MASTERS = 1, // > 0
parameter integer PIPELINE_RETURN_PATHS = 1, // 0|1
parameter integer WRP_FIFO_DEPTH = 0, // >= 0 (0 disables)
parameter integer RRP_FIFO_DEPTH = 1, // > 0 (don't care if SLAVE_FIXED_LATENCY > 0)
parameter integer RRP_USE_LL_FIFO = 1, // 0|1
parameter integer SLAVE_FIXED_LATENCY = 0, // 0=not fixed latency, >0=# fixed latency cycles
// if >0 effectively RRP_FIFO_DEPTH=SLAVE_FIXED_LATENCY+1
parameter integer SEPARATE_READ_WRITE_STALLS = 0 // 0|1
)
(
input logic clock,
input logic resetn,
// Arbitrated master.
acl_arb_intf m_intf,
// Slave.
acl_arb_intf s_intf,
input logic s_readdatavalid,
input logic [DATA_W-1:0] s_readdata,
input logic s_writeack,
// Write return path.
acl_ic_wrp_intf wrp_intf,
// Read return path.
acl_ic_rrp_intf rrp_intf
);
logic wrp_stall, rrp_stall;
generate
if( SEPARATE_READ_WRITE_STALLS == 0 )
begin
// Need specific sensitivity list instead of always_comb
// otherwise Modelsim will encounter an infinite loop.
always @(s_intf.stall, m_intf.req, rrp_stall, wrp_stall)
begin
// Arbitration request.
s_intf.req = m_intf.req;
if( rrp_stall | wrp_stall )
begin
s_intf.req.read = 1'b0;
s_intf.req.write = 1'b0;
end
// Stall signals.
m_intf.stall = s_intf.stall | rrp_stall | wrp_stall;
end
end
else
begin
// Need specific sensitivity list instead of always_comb
// otherwise Modelsim will encounter an infinite loop.
always @(s_intf.stall, m_intf.req, rrp_stall, wrp_stall)
begin
// Arbitration request.
s_intf.req = m_intf.req;
if( rrp_stall )
s_intf.req.read = 1'b0;
if( wrp_stall )
s_intf.req.write = 1'b0;
// Stall signals.
m_intf.stall = s_intf.stall;
if( m_intf.req.request & m_intf.req.read & rrp_stall )
m_intf.stall = 1'b1;
if( m_intf.req.request & m_intf.req.write & wrp_stall )
m_intf.stall = 1'b1;
end
end
endgenerate
// Write return path.
acl_ic_slave_wrp #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W),
.FIFO_DEPTH(WRP_FIFO_DEPTH),
.NUM_MASTERS(NUM_MASTERS),
.PIPELINE(PIPELINE_RETURN_PATHS)
)
wrp (
.clock( clock ),
.resetn( resetn ),
.m_intf( m_intf ),
.wrp_intf( wrp_intf ),
.s_writeack( s_writeack ),
.stall( wrp_stall )
);
// Read return path.
acl_ic_slave_rrp #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W),
.FIFO_DEPTH(RRP_FIFO_DEPTH),
.USE_LL_FIFO(RRP_USE_LL_FIFO),
.SLAVE_FIXED_LATENCY(SLAVE_FIXED_LATENCY),
.NUM_MASTERS(NUM_MASTERS),
.PIPELINE(PIPELINE_RETURN_PATHS)
)
rrp (
.clock( clock ),
.resetn( resetn ),
.m_intf( m_intf ),
.s_readdatavalid( s_readdatavalid ),
.s_readdata( s_readdata ),
.rrp_intf( rrp_intf ),
.stall( rrp_stall )
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005-2007 by Wilson Snyder.
module t (/*AUTOARG*/);
reg [3:0] value;
reg [3:0] valuex;
// verilator lint_off CASEOVERLAP
// verilator lint_off CASEWITHX
// verilator lint_off CASEX
// Note for Verilator Xs must become zeros, or the Xs may match.
initial begin
value = 4'b1001;
valuex = 4'b1xxx;
case (value)
4'b1xxx: $stop;
4'b1???: $stop;
4'b1001: ;
default: $stop;
endcase
case (valuex)
4'b1???: $stop;
4'b1xxx: ;
4'b1001: ;
4'b1000: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
//
casex (value)
4'b100x: ;
default: $stop;
endcase
casex (value)
4'b100?: ;
default: $stop;
endcase
casex (valuex)
4'b100x: ;
default: $stop;
endcase
casex (valuex)
4'b100?: ;
default: $stop;
endcase
//
casez (value)
4'bxxxx: $stop;
4'b100?: ;
default: $stop;
endcase
casez (valuex)
4'b1xx?: ;
4'b100?: ; // 1xxx is mapped to this by Verilator -x-assign 0
default: $stop;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_7_streaming_top.v
// Version : v1.0
// Description: Streaming Top level module for VIVADO.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
`timescale 1ps/1ps
`include "axi_traffic_gen_v2_0_7_defines.v"
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_7_streaming_top
#(
parameter C_FAMILY = "virtex7",
parameter C_S_AXI_ID_WIDTH = 1,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_AXIS1_HAS_TKEEP = 1 ,
parameter C_AXIS1_HAS_TSTRB = 1 ,
parameter C_AXIS2_HAS_TKEEP = 1 ,
parameter C_AXIS2_HAS_TSTRB = 1 ,
parameter C_AXIS_TDATA_WIDTH = 32,
parameter C_AXIS_TUSER_WIDTH = 8,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter ZERO_INVALID = 1,
parameter C_ATG_STREAMING_MST_ONLY = 1,
parameter C_ATG_STREAMING_MST_LPBK = 0,
parameter C_ATG_STREAMING_SLV_LPBK = 0,
parameter C_ATG_STREAMING_MAX_LEN_BITS = 1,
parameter C_FIRST_AXIS = 2,
parameter C_AXIS_SPARSE_EN = 0,
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 0
) (
input Clk ,
input Rst_n ,
input core_global_start ,
input core_global_stop ,
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input awvalid_s ,
output awready_s ,
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
input [C_S_AXI_ID_WIDTH-1:0] arid_s ,
input [31:0] araddr_s ,
input arvalid_s ,
output arready_s ,
output [C_S_AXI_ID_WIDTH-1:0] rid_s ,
output rlast_s ,
output [C_S_AXI_DATA_WIDTH-1:0] rdata_s ,
output [1:0] rresp_s ,
output rvalid_s ,
input rready_s ,
//axis1_out
input axis1_out_tready ,
output axis1_out_tvalid ,
output axis1_out_tlast ,
output [C_AXIS_TDATA_WIDTH-1:0] axis1_out_tdata ,
output [(C_AXIS_TDATA_WIDTH/8)-1:0] axis1_out_tstrb ,
output [(C_AXIS_TDATA_WIDTH/8)-1:0] axis1_out_tkeep ,
output [C_AXIS_TUSER_WIDTH-1:0] axis1_out_tuser ,
output [C_AXIS_TID_WIDTH-1:0] axis1_out_tid ,
output [C_AXIS_TDEST_WIDTH-1:0] axis1_out_tdest ,
//axis1_in
output axis1_in_tready ,
input axis1_in_tvalid ,
input axis1_in_tlast ,
input [C_AXIS_TDATA_WIDTH-1:0] axis1_in_tdata ,
input [(C_AXIS_TDATA_WIDTH/8)-1:0] axis1_in_tstrb ,
input [(C_AXIS_TDATA_WIDTH/8)-1:0] axis1_in_tkeep ,
input [C_AXIS_TUSER_WIDTH-1:0] axis1_in_tuser ,
input [C_AXIS_TID_WIDTH-1:0] axis1_in_tid ,
input [C_AXIS_TDEST_WIDTH-1:0] axis1_in_tdest ,
output reg [15:0] axis1_err_counter ,
//axis2_in
output axis2_in_tready ,
input axis2_in_tvalid ,
input axis2_in_tlast ,
input [C_AXIS_TDATA_WIDTH-1:0] axis2_in_tdata ,
input [(C_AXIS_TDATA_WIDTH/8)-1:0] axis2_in_tstrb ,
input [(C_AXIS_TDATA_WIDTH/8)-1:0] axis2_in_tkeep ,
input [C_AXIS_TUSER_WIDTH-1:0] axis2_in_tuser ,
input [C_AXIS_TID_WIDTH-1:0] axis2_in_tid ,
input [C_AXIS_TDEST_WIDTH-1:0] axis2_in_tdest ,
//axis2_out
input axis2_out_tready ,
output axis2_out_tvalid ,
output axis2_out_tlast ,
output [C_AXIS_TDATA_WIDTH-1:0] axis2_out_tdata ,
output [(C_AXIS_TDATA_WIDTH/8)-1:0] axis2_out_tstrb ,
output [(C_AXIS_TDATA_WIDTH/8)-1:0] axis2_out_tkeep ,
output [C_AXIS_TUSER_WIDTH-1:0] axis2_out_tuser ,
output [C_AXIS_TID_WIDTH-1:0] axis2_out_tid ,
output [C_AXIS_TDEST_WIDTH-1:0] axis2_out_tdest
);
wire [7:0] axis_ex_rev = `AXIEX_REV ;
//
// C_ATG_STREAMING_MST_ONLY : Only AXIS1 out Master interface available
// C_ATG_STREAMING_MST_LPBK : Only AXIS1 out and AXIS1 in interface available
// C_ATG_STREAMING_SLV_LPBK : Only AXIS2 out and AXIS2 in interface available
//
// Register interface:start
//
//
reg [31:0] reg0_ctrl_ff ;
reg [31:0] reg1_config_ff ;
reg [31:0] reg2_tdata_ff = 32'h0;
wire reg1_out0_tlast = 1'b0;
wire [15:0] trand_i ;
reg [31:0] reg2_word_ff ;
reg [31:0] reg3_word_ff ;
reg [31:0] reg4_word_ff ;
reg [31:0] reg5_word_ff ;
reg [31:0] reg6_word_ff ;
reg [31:0] reg7_word_ff ;
reg [31:0] reg8_word_ff ;
wire [23:0] reg2_tran_len ;
wire [15:0] reg2_tran_cnt ;
wire random_lenth ;
wire random_delay ;
wire user_keepstrb ;
wire [C_AXIS_TDEST_WIDTH-1:0] s1_out_tdest ;
wire [15:0] delay_cnt ;
wire infinite_trans ;
wire [(C_AXIS_TDATA_WIDTH/8-1):0] user_keep_strb;
//Get configuration data from registers.
reg s1_out_run;
reg s1_out_run_ff;
//rd/wr to registers
//wr
reg [31:0] awaddrbus_ff ;
reg [C_S_AXI_ID_WIDTH-1:0] awid_ff ;
reg awvalid_s_ff ;
reg wvalid_s_ff ;
reg [31:0] wdatabus_ff ;
reg [3:0] wstrb_ff ;
reg slv_aw_valid_ff, slv_w_valid_ff;
reg slv_wbusy_ff ;
wire slv_aw_valid;
wire slv_awi_valid;
wire [31:0] awaddrbus = (slv_aw_valid_ff) ? awaddrbus_ff[31:0] : awaddr_s[31:0];
wire [C_S_AXI_ID_WIDTH-1:0] awid = (slv_awi_valid) ? awid_s[C_S_AXI_ID_WIDTH-1:0] : awid_ff[C_S_AXI_ID_WIDTH-1:0];
wire [31:0] wdatabus = (slv_w_valid_ff) ? wdatabus_ff[31:0] : wdata_s[31:0];
wire [3:0] wstrb = (slv_w_valid_ff) ? wstrb_ff[3:0] : wstrb_s[3:0];
always @(posedge Clk) begin
awid_ff[C_S_AXI_ID_WIDTH-1:0] <= (Rst_n) ? awid[C_S_AXI_ID_WIDTH-1:0] : {C_S_AXI_ID_WIDTH{1'b0}};
awaddrbus_ff[31:0] <= (Rst_n) ? awaddrbus[31:0] : 32'h0;
awvalid_s_ff <= (Rst_n) ? awvalid_s : 1'b0;
wdatabus_ff[31:0] <= (Rst_n) ? wdatabus[31:0] : 32'h0;
wvalid_s_ff <= (Rst_n) ? wvalid_s : 1'b0;
wstrb_ff[3:0] <= (Rst_n) ? wstrb[3:0] : 4'h0;
end
//rd
reg [31:0] rd_out_ff ;
reg [31:0] araddrbus_ff ;
reg [C_S_AXI_ID_WIDTH-1:0] arid_ff;
reg arvalid_s_ff ;
reg slv_rbusy_ff ;
wire [31:0] araddrbus = araddr_s[31:0];
wire [C_S_AXI_ID_WIDTH-1:0] arid = (slv_rbusy_ff) ? arid_ff[C_S_AXI_ID_WIDTH-1:0] : arid_s[C_S_AXI_ID_WIDTH-1:0];
always @(posedge Clk) begin
araddrbus_ff[31:0] <= (Rst_n) ? araddrbus[31:0] : 32'h0;
arid_ff[C_S_AXI_ID_WIDTH-1:0] <= (Rst_n) ? arid[C_S_AXI_ID_WIDTH-1:0] : {C_S_AXI_ID_WIDTH{1'b0}};
arvalid_s_ff <= (Rst_n) ? arvalid_s : 1'b0;
end
//register interface control logic.
reg slv_arready_ff, slv_awready_ff, slv_wready_ff;
reg slv_bvalid_ff, slv_rvalid_ff;
reg slv_wr_req_ff;
wire slv_rd_req = arvalid_s && slv_arready_ff;
assign slv_awi_valid = (awvalid_s && slv_awready_ff);
assign slv_aw_valid = (awvalid_s && slv_awready_ff) ||
(slv_aw_valid_ff && ~slv_wbusy_ff);
wire slv_w_valid = (wvalid_s && slv_wready_ff) ||
(slv_w_valid_ff && ~slv_wbusy_ff);
wire slv_wr_req = slv_aw_valid && slv_w_valid;
wire slv_rdone = rready_s && slv_rvalid_ff && slv_rbusy_ff;
wire slv_wdone = bready_s && slv_bvalid_ff && slv_wbusy_ff;
wire slv_rstart = ~slv_rbusy_ff && slv_rd_req;
wire slv_wstart = ~slv_wbusy_ff && slv_wr_req;
wire slv_rbusy = ~slv_rdone && (slv_rstart || slv_rbusy_ff);
wire slv_wbusy = ~slv_wdone && (slv_wstart || slv_wbusy_ff);
wire slv_arready = ~slv_rbusy;
wire slv_awready = ~slv_aw_valid;
wire slv_wready = ~slv_w_valid;
wire streaming_wr_reg_sel = ((awaddrbus_ff[11:4] == 8'h03 )|(awaddrbus_ff[11:4] == 8'h04)|(awaddrbus_ff[11:4] == 8'h05));
wire [8:0] slvr_reg_dec = (9'h1 << (araddrbus[5:2]-4'b1100));
wire [8:0] slvw_reg_dec = ({8'h0,streaming_wr_reg_sel} << (awaddrbus_ff[5:2]-4'b1100));
wire [8:0] slv_reg_wr = (slv_wr_req_ff) ? slvw_reg_dec[8:0] : 9'h0;
wire slv_bvalid = slv_wbusy ;//&& slv_wr_req;
wire slv_rvalid = slv_rbusy;
always @(posedge Clk) begin
slv_wbusy_ff <= (Rst_n) ? slv_wbusy : 1'b0;
slv_rbusy_ff <= (Rst_n) ? slv_rbusy : 1'b0;
slv_aw_valid_ff <= (Rst_n) ? slv_aw_valid : 1'b0;
slv_w_valid_ff <= (Rst_n) ? slv_w_valid : 1'b0;
slv_awready_ff <= (Rst_n) ? slv_awready : 1'b0;
slv_wready_ff <= (Rst_n) ? slv_wready : 1'b0;
slv_arready_ff <= (Rst_n) ? slv_arready : 1'b0;
slv_bvalid_ff <= (Rst_n) ? slv_bvalid : 1'b0;
slv_rvalid_ff <= (Rst_n) ? slv_rvalid : 1'b0;
slv_wr_req_ff <= (Rst_n) ? slv_wr_req : 1'b0;
end
wire p2_overflow;
wire s1_out_ctl_en;
reg s1_out_ctl_done;
reg [31:0] axis_trn_cnt;
wire wr1clr_done;
assign wr1clr_done = ((wdatabus_ff[1]| wdatabus_ff[0])®0_ctrl_ff[1])? 1'b0 : wdatabus_ff[1];
wire [31:0] reg0_ctrl = (slv_reg_wr[0]) ? {wdatabus_ff[31:2],wr1clr_done,wdatabus_ff[0]} : {reg0_ctrl_ff[31:2],s1_out_ctl_done,s1_out_ctl_en};
wire [31:0] reg1_config = (slv_reg_wr[1]) ? wdatabus_ff[31:0] : reg1_config_ff[31:0];
wire [31:0] reg2_word = (slv_reg_wr[2]) ? wdatabus_ff[31:0] : reg2_word_ff[31:0];
wire [31:0] reg3_word = axis_trn_cnt;
wire [31:0] reg4_word = (slv_reg_wr[4]) ? wdatabus_ff[31:0] : reg4_word_ff[31:0]; //axis_strb_w0;
wire [31:0] reg5_word = (slv_reg_wr[5]) ? wdatabus_ff[31:0] : reg5_word_ff[31:0]; //axis_strb_w1;
wire [31:0] reg6_word = (slv_reg_wr[6]) ? wdatabus_ff[31:0] : reg6_word_ff[31:0]; //axis_strb_w2;
wire [31:0] reg7_word = (slv_reg_wr[7]) ? wdatabus_ff[31:0] : reg7_word_ff[31:0]; //axis_strb_w3;
wire [31:0] reg8_word = (slv_reg_wr[8]) ? {24'h0,wdatabus_ff[7:0]} : reg8_word_ff[31:0]; //TLEN new reg;
wire [31:0] wr_mask = { { 8 { wstrb_ff[3] } }, { 8 { wstrb_ff[2] } },
{ 8 { wstrb_ff[1] } }, { 8 { wstrb_ff[0] } } };
assign user_keep_strb = {reg7_word_ff,reg6_word_ff,reg5_word_ff,reg4_word_ff};
always @(posedge Clk) begin
reg0_ctrl_ff[31:0] <= (Rst_n) ? reg0_ctrl[31:0] : 32'h0;
reg1_config_ff[31:0] <= (Rst_n) ? reg1_config[31:0] : 32'h1;
reg2_word_ff[31:0] <= (Rst_n) ? reg2_word[31:0] : 32'h0;
reg3_word_ff[31:0] <= (Rst_n) ? reg3_word[31:0] : 32'h0;
reg4_word_ff[31:0] <= (Rst_n) ? reg4_word[31:0] : 32'h0;
reg5_word_ff[31:0] <= (Rst_n) ? reg5_word[31:0] : 32'h0;
reg6_word_ff[31:0] <= (Rst_n) ? reg6_word[31:0] : 32'h0;
reg7_word_ff[31:0] <= (Rst_n) ? reg7_word[31:0] : 32'h0;
reg8_word_ff[31:0] <= (Rst_n) ? reg8_word[31:0] : 32'h0;
end
wire [3:0] p2_depth, p3_depth;
wire [31:0] reg0_rd_value = { axis_ex_rev[7:0],reg0_ctrl_ff[23:0]};
wire [31:0] reg_early_out =
((slvr_reg_dec[0]) ? reg0_rd_value[31:0] : 32'h0) |
((slvr_reg_dec[1]) ? reg1_config_ff[31:0] : 32'h0) |
((slvr_reg_dec[2]) ? reg2_word_ff[31:0] : 32'h0) |
((slvr_reg_dec[3]) ? reg3_word_ff[31:0] : 32'h0) |
((slvr_reg_dec[4]) ? reg4_word_ff[31:0] : 32'h0) |
((slvr_reg_dec[5]) ? reg5_word_ff[31:0] : 32'h0) |
((slvr_reg_dec[6]) ? reg6_word_ff[31:0] : 32'h0) |
((slvr_reg_dec[7]) ? reg7_word_ff[31:0] : 32'h0) |
((slvr_reg_dec[8]) ? reg8_word_ff[31:0] : 32'h0) ;
wire [31:0] rd_out = (slv_rstart) ? reg_early_out[31:0] : rd_out_ff[31:0];
always @(posedge Clk) begin
rd_out_ff[31:0] <= rd_out[31:0];
end
//register interface output assignment
assign awready_s = slv_awready_ff;
assign wready_s = slv_wready_ff;
assign bid_s[C_S_AXI_ID_WIDTH-1:0] = (slv_bvalid_ff) ? awid_ff[C_S_AXI_ID_WIDTH-1:0] : {C_S_AXI_ID_WIDTH{1'b0}};
assign bresp_s[1:0] = 2'b00;
assign bvalid_s = slv_bvalid_ff;
assign arready_s = slv_arready_ff;
assign rid_s[C_S_AXI_ID_WIDTH-1:0] = (slv_rvalid_ff) ? arid_ff[C_S_AXI_ID_WIDTH-1:0] : 16'h0;
assign rlast_s = 1'b1;
assign rdata_s[C_S_AXI_DATA_WIDTH-1:0] = (slv_rvalid_ff) ? { 2 { rd_out_ff[31:0] } } : 64'h0;
assign rresp_s[1:0] = 2'b0;
assign rvalid_s = slv_rvalid_ff;
// Register interface:end
//generate global_start/global_stop pulse
wire global_start_pulse;
wire global_stop_pulse;
reg global_start_1ff;
reg global_stop_1ff;
always @(posedge Clk) begin
global_start_1ff <= (Rst_n) ? core_global_start : 1'b0;
global_stop_1ff <= (Rst_n) ? core_global_stop : 1'b0;
end
assign global_start_pulse = ~global_start_1ff & core_global_start;
assign global_stop_pulse = ~global_stop_1ff & core_global_stop ;
//Read of registers by Core
//
//Current Value Set to Core
reg random_lenth_c;
reg random_delay_c;
reg user_keepstrb_c;
reg [C_AXIS_TDEST_WIDTH-1:0] s1_out_tdest_c;
reg [15:0] delay_cnt_c;
reg [23:0] reg2_tran_len_c;
reg [15:0] reg2_tran_cnt_c;
reg infinite_trans_c;
always @(posedge Clk) begin
if(Rst_n == 1'b0 ) begin
random_lenth_c <= 1'b0;
random_delay_c <= 1'b0;
user_keepstrb_c <= 1'b0;
s1_out_tdest_c <= {C_AXIS_TDEST_WIDTH{1'b0}};
delay_cnt_c <= 16'h0;
reg2_tran_len_c <= 24'h0;
reg2_tran_cnt_c <= 16'h0;
infinite_trans_c <= 1'b0;
end else begin
random_lenth_c <= random_lenth ;
random_delay_c <= random_delay ;
user_keepstrb_c <= user_keepstrb ;
s1_out_tdest_c <= s1_out_tdest ;
delay_cnt_c <= delay_cnt ;
reg2_tran_len_c <= reg2_tran_len ;
reg2_tran_cnt_c <= reg2_tran_cnt ;
infinite_trans_c <= infinite_trans ;
end
end
//Get the Snap-Shot of Registers when core is not running.
assign random_lenth = s1_out_run ? random_lenth_c : reg1_config_ff[0];
assign random_delay = s1_out_run ? random_delay_c : reg1_config_ff[1];
assign user_keepstrb = s1_out_run ? user_keepstrb_c: reg1_config_ff[2];
assign s1_out_tdest = s1_out_run ? s1_out_tdest_c : reg1_config_ff[8+8-1:8];
assign delay_cnt = s1_out_run ? delay_cnt_c : reg1_config_ff[31:16];
//reg2
assign reg2_tran_len = s1_out_run ? reg2_tran_len_c: {reg8_word_ff[7:0], reg2_word_ff[15:0]};
assign reg2_tran_cnt = s1_out_run ? reg2_tran_cnt_c: ((reg2_word_ff[31:16] == 16'h0) ? 16'h2 : reg2_word_ff[31:16]);
assign infinite_trans = s1_out_run ? infinite_trans_c :(reg2_word_ff[31:16] == 16'h0);
//Channel en/run status
wire s1_out_reg_en;
wire s1_in_reg_en;
reg s1_in_run;
wire s2_out_reg_en;
reg s2_out_run;
wire s2_in_reg_en;
reg s2_in_run;
wire reset_s1_out_en;
wire reset_s1_out_done;
assign s1_out_reg_en =(slv_reg_wr[0] & wdatabus_ff[0] ) | global_start_pulse;
assign reset_s1_out_en =(slv_reg_wr[0] & ~wdatabus_ff[0]) | global_stop_pulse ;
assign reset_s1_out_done = slv_reg_wr[0] & ( wdatabus_ff[1] | wdatabus_ff[0]);
assign s1_in_reg_en = slv_reg_wr[0] & wdatabus_ff[0];
assign s2_out_reg_en = slv_reg_wr[0] & wdatabus_ff[0];
assign s2_in_reg_en = slv_reg_wr[0] & wdatabus_ff[0];
wire s1_out_ctl_pulse;
reg s1_out_ctl_en_ff;
assign s1_out_ctl_en = (s1_out_reg_en) ? 1'b1 : ((s1_out_ctl_done | reset_s1_out_en) ? 1'b0 :s1_out_ctl_en_ff );
assign s1_out_ctl_pulse = s1_out_ctl_en & ~s1_out_ctl_en_ff;
always @(posedge Clk) begin
if(Rst_n == 1'b0 ) begin
s1_out_ctl_en_ff <= 1'b0;
s1_out_run_ff <= 1'b0;
end else begin
s1_out_ctl_en_ff <= s1_out_ctl_en;
s1_out_run_ff <= s1_out_run;
end
end
always @(posedge Clk) begin
if(Rst_n == 1'b0 ) begin
s1_out_ctl_done <= 1'b0;
end else if(s1_out_ctl_pulse | reset_s1_out_done) begin
s1_out_ctl_done <= 1'b0;
end else if(s1_out_run == 1'b0 & s1_out_run_ff == 1'b1) begin
s1_out_ctl_done <= 1'b1;
end
end
// C_ATG_STREAMING_MST_ONLY or C_ATG_STREAMING_MST_LPBK :start
//AXIS1-OUT
wire [15:0] beat_cnt_i;
generate if(C_ATG_STREAMING_MAX_LEN_BITS == 16 ) begin: STRM_MAXLEN1
assign beat_cnt_i = trand_i[15:0];
end
endgenerate
generate if(C_ATG_STREAMING_MAX_LEN_BITS != 16 ) begin: STRM_MAXLEN0
assign beat_cnt_i = {{(16-C_ATG_STREAMING_MAX_LEN_BITS){1'b0}},trand_i[(C_ATG_STREAMING_MAX_LEN_BITS-1):0]} ;
end
endgenerate
generate if(C_ATG_STREAMING_MST_ONLY == 1 || C_ATG_STREAMING_MST_LPBK == 1 ) begin: ATG_STREAMING_MST_ONLY_OR_LPBK_ON
reg tvalid_i;
reg tlast_i;
wire dbgcnt0_pause;
//capture register length
reg [15:0] axis1_tran_cnt;
reg [23:0] axis1_beat_cnt;
reg [23:0] axis1_beats_req;
wire axis1_trans_not0 = (axis1_tran_cnt != 16'h0);
wire axis1_trans_eql1 = (axis1_tran_cnt == 16'h1);
wire axis1_trans_eql0 = (axis1_tran_cnt == 16'h0);
wire axis1_beats_not0 = (axis1_beat_cnt != 24'h0);
wire axis1_beats_eql1 = (axis1_beat_cnt == 24'h1);
wire axis1_beats_req_eql0 = (axis1_beats_req == 24'h0);
wire axis1_out_last_sampled = axis1_out_tvalid & axis1_out_tready & axis1_out_tlast;
//Run status of each channel
always @(posedge Clk) begin
if(Rst_n == 1'b0 ) begin
s1_out_run <= 1'b0;
end else if(s1_out_run == 1'b1 & axis1_trans_eql0 == 1'b1) begin //ch running
s1_out_run <= 1'b0;
end else if(s1_out_ctl_pulse == 1'b1 & axis1_trans_not0 == 1'b1) begin //ch enabled
s1_out_run <= 1'b1;
end
end
//
//No.Of transactions to be generated
//
always @(posedge Clk) begin
if(Rst_n == 1'b0 ) begin
axis1_tran_cnt <= 16'h0;
end else if(s1_out_run == 1'b0) begin //reg-write
axis1_tran_cnt <= reg2_tran_cnt;
end else if(axis1_out_tvalid && axis1_out_tready && axis1_out_tlast) begin
if(s1_out_ctl_en_ff == 1'b0) begin //Force trnas to be generated to 0,when cen made to 0.
axis1_tran_cnt <= 16'h0;
end else begin
axis1_tran_cnt <= axis1_tran_cnt - (axis1_trans_not0 && ~infinite_trans);
end
end
end
//
//delay counters: To insert delays between transactions generated at
//AXIS1_OUT
//
reg [15:0] ld_cnt;
wire delay_not0 = (random_delay)?(trand_i[15:0] != 16'h0):(delay_cnt != 16'h0);
wire ld_cnt0 = (ld_cnt == 16'h0) ;
wire ld_cnt_not0 = (ld_cnt != 16'h0) ;
assign dbgcnt0_pause = ld_cnt_not0 ;
always @(posedge Clk) begin
if(Rst_n == 1'b0) begin
ld_cnt <= 16'h0;
end else if(axis1_out_last_sampled == 1'b1) begin
if(random_delay == 1'b1) begin
ld_cnt <= (trand_i[15:0] == 16'h0)? 16'h0: trand_i[15:0] -1'b1;
end else begin
//As delay is flopped,load a value of less by 1 for delay's > 0
ld_cnt <= (delay_cnt == 16'h0)?16'h0:delay_cnt - 1'b1;
end
end else begin
ld_cnt <= ld_cnt - ld_cnt_not0;
end
end
always @(posedge Clk) begin
if(Rst_n == 1'b0) begin
tvalid_i <= 1'b0;
end else if(axis1_out_tvalid && ~axis1_out_tready) begin
tvalid_i <= tvalid_i;
//CEN is disabled during transfers
end else if(~s1_out_ctl_en_ff & axis1_out_tvalid & axis1_out_tready & axis1_out_tlast) begin
tvalid_i <= 1'b0;
//Last beat of requested no.of transfers
end else if(axis1_trans_eql1 & axis1_out_tvalid & axis1_out_tready & axis1_out_tlast) begin
tvalid_i <= 1'b0;
//Last beat of current transfer + a delay between transfers
end else if(axis1_out_tvalid & axis1_out_tready & axis1_out_tlast & delay_not0 ) begin
tvalid_i <= 1'b0;
end else begin
//Assert tvalid if transfers are pending.
tvalid_i <= s1_out_run & axis1_trans_not0 && ~dbgcnt0_pause ;
end
end
//
//No.Of beats to be generated per transaction
//
always @(posedge Clk) begin
if(Rst_n == 1'b0 ) begin
axis1_beat_cnt <= 24'h0;
axis1_beats_req <= 24'h0;
end else if(axis1_out_last_sampled == 1'b1 | s1_out_run == 1'b0) begin
if(random_lenth == 1'b1 ) begin
axis1_beat_cnt <= (beat_cnt_i == 16'h0)? 24'h1:{8'h0, beat_cnt_i};
axis1_beats_req <= (beat_cnt_i == 16'h0)? 24'h1:{8'h0, beat_cnt_i};
end else begin
//axis1_beat_cnt <= (reg2_tran_len[15:0] == 16'h0)? 16'h1: reg2_tran_len[15:0];
axis1_beat_cnt <= reg2_tran_len[23:0];
axis1_beats_req <= reg2_tran_len[23:0];
end
end else if(axis1_out_tvalid && axis1_out_tready) begin
axis1_beat_cnt <= axis1_beat_cnt - axis1_beats_not0;
axis1_beats_req <= axis1_beats_req;
end
end
//
//Strobe-keep generation
//
wire [(C_AXIS_TDATA_WIDTH/8-1):0] keep_strb ;
wire [127:0] sparse_keep_strb_all1;
wire [127:0] sparse_keep_strb_all0;
reg [2*(C_AXIS_TDATA_WIDTH/8)-1:0] sparse_keep_strb ;
assign sparse_keep_strb_all1 = {128{1'b1}};
assign sparse_keep_strb_all0 = {128{1'b0}};
//
//Generate TKEEP and TSTRB such that
// a. TKEEP = TSTRB
// b. Valid bytes are all contigious ie 1,3,7,F are the only valid sparse
// strobe/keep signals allowed for 32-bit tdata.
//
always @(posedge Clk) begin
if(Rst_n == 1'b0) begin
sparse_keep_strb <= {sparse_keep_strb_all0[C_AXIS_TDATA_WIDTH/8-1:0],sparse_keep_strb_all1[C_AXIS_TDATA_WIDTH/8-1:0]};
end else if( user_keepstrb == 1'b1 ) begin
sparse_keep_strb <= user_keep_strb;
end else if((sparse_keep_strb[C_AXIS_TDATA_WIDTH/8-1:0] == 1) && (axis1_out_last_sampled == 1'b1) ) begin
sparse_keep_strb <= {sparse_keep_strb_all0[C_AXIS_TDATA_WIDTH/8-1:0],sparse_keep_strb_all1[C_AXIS_TDATA_WIDTH/8-1:0]};
end else if(axis1_out_last_sampled == 1'b1) begin
sparse_keep_strb <= {sparse_keep_strb[0],sparse_keep_strb[2*(C_AXIS_TDATA_WIDTH/8)-1:1]};
end
end
assign keep_strb = sparse_keep_strb[C_AXIS_TDATA_WIDTH/8-1:0];
//
// tlast generation
//
always @(posedge Clk) begin
if(Rst_n == 1'b0) begin
tlast_i <= 1'b0;
//Keep tlast set if no.of beats =1 after end of each transfer.
end else if(axis1_out_tvalid && axis1_out_tready && axis1_out_tlast) begin
tlast_i <= (axis1_beats_req_eql0)?1'b1:1'b0;
//set tlast if no.of beats requested = 1(register value =0)
end else if(s1_out_run & axis1_beats_req_eql0) begin
tlast_i <= 1'b1;
//assert for last beat (where no.of beats >1)
end else if(axis1_out_tvalid && axis1_out_tready) begin
tlast_i <= s1_out_run & axis1_beats_eql1 &(axis1_trans_not0 & ~dbgcnt0_pause);
//de-assert if core is not in run state.
end else if(s1_out_run == 1'b0) begin
tlast_i <= 1'b0;
end
end
//Data generation
wire [C_AXIS_TDATA_WIDTH-1:0] tdata_i;
//
//using randgen which generates 16-bit random generator.
//Make 1024 bit width data (maximum allowed data width)
// and assign based on current data width selected
//
wire axis1_gen_out_nxt_data;
assign axis1_gen_out_nxt_data = axis1_out_tvalid & axis1_out_tready;
axi_traffic_gen_v2_0_7_randgen
stream_data_gen (
.seed (16'hABCD ),
.randnum (trand_i ),
.generate_next(axis1_gen_out_nxt_data),
.reset (~Rst_n ),
.clk (Clk )
);
assign tdata_i = { 64{trand_i} };
// AXIS1_OUT outputs generation generation
assign axis1_out_tvalid = tvalid_i;
assign axis1_out_tlast = tlast_i;
assign axis1_out_tkeep = (tvalid_i && tlast_i) ? (C_AXIS_SPARSE_EN ? keep_strb : {C_AXIS_TDATA_WIDTH/8{1'b1}}):{C_AXIS_TDATA_WIDTH/8{1'b1}};
assign axis1_out_tstrb = (tvalid_i && tlast_i) ? (C_AXIS_SPARSE_EN ? keep_strb : {C_AXIS_TDATA_WIDTH/8{1'b1}}):{C_AXIS_TDATA_WIDTH/8{1'b1}};
//NO_SPARSE_STRB_KEEP assign axis1_out_tkeep = {C_AXIS_TDATA_WIDTH/8{1'b1}};
//NO_SPARSE_STRB_KEEP assign axis1_out_tstrb = {C_AXIS_TDATA_WIDTH/8{1'b1}};
assign axis1_out_tdata = tdata_i;
assign axis1_out_tuser = {(C_AXIS_TUSER_WIDTH){1'b0}};
assign axis1_out_tid = {(C_AXIS_TID_WIDTH){1'b0}};
assign axis1_out_tdest = s1_out_tdest;
// C_ATG_STREAMING_MST_ONLY or C_ATG_STREAMING_SLV_LPBK :end
end
endgenerate
generate if(C_ATG_STREAMING_MST_ONLY == 0 && C_ATG_STREAMING_MST_LPBK == 0 ) begin: ATG_STREAMING_MST_ONLY_OR_LPBK_OFF
// AXIS1_OUT outputs generation generation
assign axis1_out_tvalid = 1'b0;
assign axis1_out_tlast = 1'b0;
assign axis1_out_tkeep = {C_AXIS_TDATA_WIDTH/8{1'b0}};
assign axis1_out_tstrb = {C_AXIS_TDATA_WIDTH/8{1'b0}};
assign axis1_out_tdata = {C_AXIS_TDATA_WIDTH{1'b0}};
assign axis1_out_tuser = {(C_AXIS_TUSER_WIDTH){1'b0}};
assign axis1_out_tid = {(C_AXIS_TID_WIDTH){1'b0}};
assign axis1_out_tdest = {(C_AXIS_TDEST_WIDTH){1'b0}};
end
endgenerate
// C_ATG_STREAMING_SLV_LPBK:begin
wire [(C_AXIS_TDATA_WIDTH/8)-1:0] axis2_in_tstrb_i;
generate if(C_AXIS2_HAS_TSTRB == 0 && C_AXIS2_HAS_TKEEP == 1 ) begin: AXIS2_STRB0_KEEP1
assign axis2_in_tstrb_i = axis2_in_tkeep;
end else begin: AXIS2_STRB_KEEP
assign axis2_in_tstrb_i = axis2_in_tstrb;
end
endgenerate
generate if(C_ATG_STREAMING_SLV_LPBK == 1 ) begin: ATG_STREAMING_SLV_LPBK_ON
localparam AXIS_FIFO_WIDTH = C_AXIS_TDATA_WIDTH*10/8 + C_AXIS_TUSER_WIDTH + C_AXIS_TID_WIDTH + C_AXIS_TDEST_WIDTH +1;
wire p2_push = axis2_in_tvalid && axis2_in_tready;
wire p2_block_notfull = 1'b0;
wire p2_block_outvalid = 1'b0;
wire [AXIS_FIFO_WIDTH-1:0] invalid_data = {AXIS_FIFO_WIDTH{1'b0}};
axi_traffic_gen_v2_0_7_axis_fifo #(
.ZERO_INVALID(ZERO_INVALID),
.WIDTH(AXIS_FIFO_WIDTH)
) P2 (
.Clk (Clk),
.Rst_n (Rst_n),
.in_data ({ axis2_in_tlast,
axis2_in_tdata[C_AXIS_TDATA_WIDTH-1:0 ] ,
axis2_in_tkeep[C_AXIS_TDATA_WIDTH/8-1:0] ,
axis2_in_tstrb_i[C_AXIS_TDATA_WIDTH/8-1:0] ,
axis2_in_tuser[C_AXIS_TUSER_WIDTH-1:0 ] ,
axis2_in_tid [C_AXIS_TID_WIDTH-1:0 ] ,
axis2_in_tdest[C_AXIS_TDEST_WIDTH-1:0 ]
}),
.in_invalid_data (invalid_data),
.in_push (p2_push),
.in_ready (axis2_out_tready),
.in_block_notfull (p2_block_notfull),
.in_block_outvalid(p2_block_notfull),
.out_valid (axis2_out_tvalid),
.out_notfull (axis2_in_tready),
.out_overflow (p2_overflow),
.out_depth (p2_depth[3:0]),
.out_data ({axis2_out_tlast,
axis2_out_tdata[C_AXIS_TDATA_WIDTH-1:0 ] ,
axis2_out_tkeep[C_AXIS_TDATA_WIDTH/8-1:0] ,
axis2_out_tstrb[C_AXIS_TDATA_WIDTH/8-1:0] ,
axis2_out_tuser[C_AXIS_TUSER_WIDTH-1:0 ] ,
axis2_out_tid [C_AXIS_TID_WIDTH-1:0 ] ,
axis2_out_tdest[C_AXIS_TDEST_WIDTH-1:0 ]
} )
);
end
endgenerate
generate if(C_ATG_STREAMING_SLV_LPBK == 0 ) begin: ATG_STREAMING_SLV_LPBK_OFF
assign axis2_in_tready = 1'b0;
assign axis2_out_tvalid = 1'b0;
assign axis2_out_tlast = 1'b0;
assign axis2_out_tkeep = {C_AXIS_TDATA_WIDTH/8{1'b0}};
assign axis2_out_tstrb = {C_AXIS_TDATA_WIDTH/8{1'b0}};
assign axis2_out_tdata = {C_AXIS_TDATA_WIDTH{1'b0}};
assign axis2_out_tuser = {(C_AXIS_TUSER_WIDTH){1'b0}};
assign axis2_out_tid = {(C_AXIS_TID_WIDTH){1'b0}};
assign axis2_out_tdest = {(C_AXIS_TDEST_WIDTH){1'b0}};
end
endgenerate
// C_ATG_STREAMING_SLV_LPBK:end
//C_ATG_STREAMING_MST_LPBK:start
//2013.2 New features:
// a. Master loopback
// b. TID,TDEST ports addtions
wire axis1_gen_in_nxt_data;
reg axis1_gen_in_nxt_data_d1;
wire [15:0] axis1_trand_in_i;
wire [C_AXIS_TDATA_WIDTH-1:0] axis1_trand_in_i2;
wire [C_AXIS_TDATA_WIDTH-1:0] axis1_trand_in;
wire [C_AXIS_TDATA_WIDTH-1:0] axis1_comp_data;
wire [(C_AXIS_TDATA_WIDTH/8)-1:0] axis1_keep_strb_valid;
wire [C_AXIS_TDATA_WIDTH-1:0] axis1_keep_strb_ext; //From Interface
wire [C_AXIS_TDATA_WIDTH/8-1:0] axis1_keep_strb_int; //Internally generated
//valid mask for incoming data stream
// TKEEP TSTRB Description
// 1 1 Data byte
// 1 0 Position byte
// 0 0 Null byte
// 0 1 Must not be used
// **ONLY* data bytes are compared ie., TKEEP =1 and TSTRB =1
wire [(C_AXIS_TDATA_WIDTH/8)-1:0] axis1_in_tstrb_i;
generate if(C_AXIS1_HAS_TSTRB == 0 && C_AXIS1_HAS_TKEEP == 1 ) begin: AXIS1_STRB0_KEEP1
assign axis1_in_tstrb_i = axis1_in_tkeep;
end else begin: AXIS1_STRB_KEEP
assign axis1_in_tstrb_i = axis1_in_tstrb;
end
endgenerate
assign axis1_keep_strb_valid = axis1_in_tkeep & axis1_in_tstrb_i;
generate
genvar byte_num;
for (byte_num = 0; byte_num < C_AXIS_TDATA_WIDTH/8; byte_num = byte_num+1) begin : axis1_keep_strb_gen
assign axis1_keep_strb_ext[byte_num*8+7:byte_num*8] =
{8{axis1_keep_strb_valid[byte_num]}};
end
endgenerate
//
//Generate TKEEP and TSTRB such that
// a. TKEEP = TSTRB
// b. Valid bytes are all contigious ie 1,3,7,F are the only valid sparse
// strobe/keep signals allowed for 32-bit tdata.
//
wire [(C_AXIS_TDATA_WIDTH/8-1):0] keep_strb_int ;
reg [2*(C_AXIS_TDATA_WIDTH/8)-1:0] sparse_keep_strb_int ;
wire [127:0] sparse_keep_strb_int_all1;
wire [127:0] sparse_keep_strb_int_all0;
wire axis1_in_last_sampled = axis1_in_tvalid & axis1_in_tready & axis1_in_tlast;
assign sparse_keep_strb_int_all1 = {128{1'b1}};
assign sparse_keep_strb_int_all0 = {128{1'b0}};
always @(posedge Clk) begin
if(Rst_n == 1'b0) begin
sparse_keep_strb_int <= {sparse_keep_strb_int_all0[C_AXIS_TDATA_WIDTH/8-1:0],sparse_keep_strb_int_all1[C_AXIS_TDATA_WIDTH/8-1:0]};
end else if( user_keepstrb == 1'b1 ) begin
sparse_keep_strb_int <= user_keep_strb;
end else if((sparse_keep_strb_int[C_AXIS_TDATA_WIDTH/8-1:0] == 1) && (axis1_in_last_sampled == 1'b1) ) begin
sparse_keep_strb_int <= {sparse_keep_strb_int_all0[C_AXIS_TDATA_WIDTH/8-1:0],sparse_keep_strb_int_all1[C_AXIS_TDATA_WIDTH/8-1:0]};
end else if(axis1_in_last_sampled == 1'b1) begin
sparse_keep_strb_int <= {sparse_keep_strb_int[0],sparse_keep_strb_int[2*(C_AXIS_TDATA_WIDTH/8)-1:1]};
end
end
assign keep_strb_int = sparse_keep_strb_int[C_AXIS_TDATA_WIDTH/8-1:0];
assign axis1_keep_strb_int = (axis1_in_tvalid & axis1_in_tlast) ? (C_AXIS_SPARSE_EN ? keep_strb_int : {C_AXIS_TDATA_WIDTH/8{1'b1}} ) : {C_AXIS_TDATA_WIDTH/8{1'b1}};
//NO_SPARSE_STRB_KEEP assign axis1_keep_strb_int = {C_AXIS_TDATA_WIDTH/8{1'b1}};
assign axis1_trand_in_i2 = { 64{axis1_trand_in_i}};
assign axis1_comp_data = axis1_in_tdata & axis1_keep_strb_ext;
assign axis1_trand_in = axis1_trand_in_i2 & axis1_keep_strb_ext;
//
//No.Of Transactions received
//
generate if(C_ATG_STREAMING_MST_ONLY == 1 ) begin: ATG_TRN_MO
always@(posedge Clk) begin
if(!Rst_n) begin
axis_trn_cnt <= 32'h0;
end else if(axis1_out_tvalid == 1'b1 &
axis1_out_tready == 1'b1 &
axis1_out_tlast )begin
axis_trn_cnt <= axis_trn_cnt + 1'b1;
end
end
end
endgenerate
generate if(C_ATG_STREAMING_MST_LPBK == 1 ) begin: ATG_TRN_ML
always@(posedge Clk) begin
if(!Rst_n) begin
axis_trn_cnt <= 32'h0;
end else if(axis1_in_tvalid == 1'b1 &
axis1_in_tready == 1'b1 &
axis1_in_tlast )begin
axis_trn_cnt <= axis_trn_cnt + 1'b1;
end
end
end
endgenerate
generate if(C_ATG_STREAMING_SLV_LPBK == 1 ) begin: ATG_TRN_SL
always@(posedge Clk) begin
if(!Rst_n) begin
axis_trn_cnt <= 32'h0;
end else if(axis2_out_tvalid == 1'b1 &
axis2_out_tready == 1'b1 &
axis2_out_tlast )begin
axis_trn_cnt <= axis_trn_cnt + 1'b1;
end
end
end
endgenerate
//
//Error counter: Maintain internal error counter of 1-bit higher width
// to check for overlflow
// Stop incrementing once overflow happens
//
reg [16:0] axis1_err_counter_i;
//
//Stage1: Compare byte level data
//
reg [C_AXIS_TDATA_WIDTH/8-1:0] stage1_data_cmp;
generate
genvar cmp_byte_num;
for (cmp_byte_num = 0; cmp_byte_num < C_AXIS_TDATA_WIDTH/8; cmp_byte_num = cmp_byte_num+1) begin : stage_1_comp
always@(posedge Clk) begin
if(!Rst_n) begin
stage1_data_cmp[cmp_byte_num] <= 1'b0;
end else if(axis1_gen_in_nxt_data ) begin
if( (axis1_in_tkeep[cmp_byte_num] != axis1_keep_strb_int[cmp_byte_num]) || //keep error
(axis1_in_tstrb_i[cmp_byte_num] != axis1_keep_strb_int[cmp_byte_num]) || //strb error
(axis1_trand_in[cmp_byte_num*8+7:cmp_byte_num*8] != axis1_comp_data[cmp_byte_num*8+7:cmp_byte_num*8]) //data error
) begin
stage1_data_cmp[cmp_byte_num] <= 1'b1;
end else begin
stage1_data_cmp[cmp_byte_num] <= 1'b0;
end
end
end //always
end //for-loop
endgenerate
//
//Stage2: Compare stage-1 data
//
always @(posedge Clk) begin
if(!Rst_n) begin
axis1_err_counter_i <= 17'h0;
end else if(axis1_gen_in_nxt_data_d1) begin
if(( stage1_data_cmp != 0 ) & (axis1_err_counter_i[16] == 1'b0)) begin
axis1_err_counter_i <= axis1_err_counter_i + 16'h1;
end
end
end
assign axis1_gen_in_nxt_data = axis1_in_tvalid & axis1_in_tready;
always @(posedge Clk) begin
if(!Rst_n) begin
axis1_gen_in_nxt_data_d1 <= 1'b0;
end else begin
axis1_gen_in_nxt_data_d1 <= axis1_gen_in_nxt_data;
end
end
axi_traffic_gen_v2_0_7_randgen
stream_data_chk (
.seed (16'hABCD ),
.randnum (axis1_trand_in_i ),
.generate_next(axis1_gen_in_nxt_data),
.reset (~Rst_n ),
.clk (Clk )
);
//C_ATG_STREAMING_MST_LPBK:end
generate if(C_ATG_STREAMING_MST_LPBK == 1 ) begin: ATG_STREAMING_MST_LPBK_ON
assign axis1_in_tready = 1'b1; //Ready to accept all the time.
//
//Since error counter is not required immmediately, flop o/p signals
// for better timing.
//
always @(posedge Clk) begin
if(!Rst_n) begin
axis1_err_counter <= 16'h0;
end else if(axis1_err_counter_i[16]) begin
axis1_err_counter <= 16'hFFFF;
end else begin
axis1_err_counter <= axis1_err_counter_i[15:0];
end
end
end
endgenerate
generate if(C_ATG_STREAMING_MST_LPBK == 0 ) begin: ATG_STREAMING_MST_LPBK_OFF
assign axis1_in_tready = 1'b0; //Loop bakc off
always @(posedge Clk) begin
axis1_err_counter <= 16'h0;
end
end
endgenerate
endmodule
|
module halfband_interp
(input clock, input reset, input enable,
input strobe_in, input strobe_out,
input [15:0] signal_in_i, input [15:0] signal_in_q,
output reg [15:0] signal_out_i, output reg [15:0] signal_out_q,
output wire [12:0] debug);
wire [15:0] coeff_ram_out;
wire [15:0] data_ram_out_i;
wire [15:0] data_ram_out_q;
wire [3:0] data_rd_addr;
reg [3:0] data_wr_addr;
reg [2:0] coeff_rd_addr;
wire filt_done;
wire [15:0] mac_out_i;
wire [15:0] mac_out_q;
reg [15:0] delayed_middle_i, delayed_middle_q;
wire [7:0] shift = 8'd9;
reg stb_out_happened;
wire [15:0] data_ram_out_i_b;
always @(posedge clock)
if(strobe_in)
stb_out_happened <= #1 1'b0;
else if(strobe_out)
stb_out_happened <= #1 1'b1;
assign debug = {filt_done,data_rd_addr,data_wr_addr,coeff_rd_addr};
wire [15:0] signal_out_i = stb_out_happened ? mac_out_i : delayed_middle_i;
wire [15:0] signal_out_q = stb_out_happened ? mac_out_q : delayed_middle_q;
/* always @(posedge clock)
if(reset)
begin
signal_out_i <= #1 16'd0;
signal_out_q <= #1 16'd0;
end
else if(strobe_in)
begin
signal_out_i <= #1 delayed_middle_i; // Multiply by 1 for middle coeff
signal_out_q <= #1 delayed_middle_q;
end
//else if(filt_done&stb_out_happened)
else if(stb_out_happened)
begin
signal_out_i <= #1 mac_out_i;
signal_out_q <= #1 mac_out_q;
end
*/
always @(posedge clock)
if(reset)
coeff_rd_addr <= #1 3'd0;
else if(coeff_rd_addr != 3'd0)
coeff_rd_addr <= #1 coeff_rd_addr + 3'd1;
else if(strobe_in)
coeff_rd_addr <= #1 3'd1;
reg filt_done_d1;
always@(posedge clock)
filt_done_d1 <= #1 filt_done;
always @(posedge clock)
if(reset)
data_wr_addr <= #1 4'd0;
//else if(strobe_in)
else if(filt_done & ~filt_done_d1)
data_wr_addr <= #1 data_wr_addr + 4'd1;
always @(posedge clock)
if(coeff_rd_addr == 3'd7)
begin
delayed_middle_i <= #1 data_ram_out_i_b;
// delayed_middle_q <= #1 data_ram_out_q_b;
end
// always @(posedge clock)
// if(reset)
// data_rd_addr <= #1 4'd0;
// else if(strobe_in)
// data_rd_addr <= #1 data_wr_addr + 4'd1;
// else if(!filt_done)
// data_rd_addr <= #1 data_rd_addr + 4'd1;
// else
// data_rd_addr <= #1 data_wr_addr;
wire [3:0] data_rd_addr1 = data_wr_addr + {1'b0,coeff_rd_addr};
wire [3:0] data_rd_addr2 = data_wr_addr + 15 - {1'b0,coeff_rd_addr};
// always @(posedge clock)
// if(reset)
// filt_done <= #1 1'b1;
// else if(strobe_in)
// filt_done <= #1 1'b0;
// else if(coeff_rd_addr == 4'd0)
// filt_done <= #1 1'b1;
assign filt_done = (coeff_rd_addr == 3'd0);
coeff_ram coeff_ram ( .clock(clock),.rd_addr({1'b0,coeff_rd_addr}),.rd_data(coeff_ram_out) );
ram16_2sum data_ram_i ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_i),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_i_b),.sum(data_ram_out_i));
ram16_2sum data_ram_q ( .clock(clock),.write(strobe_in),.wr_addr(data_wr_addr),.wr_data(signal_in_q),
.rd_addr1(data_rd_addr1),.rd_addr2(data_rd_addr2),.rd_data(data_ram_out_q));
mac mac_i (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_i),.y(coeff_ram_out),.shift(shift),.z(mac_out_i) );
mac mac_q (.clock(clock),.reset(reset),.enable(~filt_done),.clear(strobe_in),
.x(data_ram_out_q),.y(coeff_ram_out),.shift(shift),.z(mac_out_q) );
endmodule // halfband_interp
|
// $Header: $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Differential Signaling Input Buffer
// /___/ /\ Filename : IBUFDS.v
// \ \ / \
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Add LOC paramter;
// 07/21/05 - CR 212974 -- matched unisim parameters as requested by other tools
// 07/19/06 - Add else to handle x case for o_out (CR 234718).
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 07/13/12 - 669215 - add parameter DQS_BIAS
// 08/29/12 - 675511 - add DQS_BIAS functionality
// 09/11/12 - 677753 - remove X glitch on O
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module IBUFDS (O, I, IB);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
parameter CAPACITANCE = "DONT_CARE";
parameter DIFF_TERM = "FALSE";
parameter DQS_BIAS = "FALSE";
parameter IBUF_DELAY_VALUE = "0";
parameter IBUF_LOW_PWR = "TRUE";
parameter IFD_DELAY_VALUE = "AUTO";
parameter IOSTANDARD = "DEFAULT";
localparam MODULE_NAME = "IBUFDS";
output O;
input I, IB;
wire i_in, ib_in;
reg o_out;
reg DQS_BIAS_BINARY = 1'b0;
assign O = o_out;
assign i_in = I;
assign ib_in = IB;
initial begin
case (DQS_BIAS)
"TRUE" : DQS_BIAS_BINARY <= #1 1'b1;
"FALSE" : DQS_BIAS_BINARY <= #1 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DQS_BIAS on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DQS_BIAS);
$finish;
end
endcase
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on %s instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", MODULE_NAME, CAPACITANCE);
$finish;
end
endcase
case (DIFF_TERM)
"TRUE", "FALSE" : ;
default : begin
$display("Attribute Syntax Error : The attribute DIFF_TERM on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, DIFF_TERM);
$finish;
end
endcase // case(DIFF_TERM)
case (IBUF_DELAY_VALUE)
"0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", MODULE_NAME, IBUF_DELAY_VALUE);
$finish;
end
endcase
case (IBUF_LOW_PWR)
"FALSE", "TRUE" : ;
default : begin
$display("Attribute Syntax Error : The attribute IBUF_LOW_PWR on %s instance %m is set to %s. Legal values for this attribute are TRUE or FALSE.", MODULE_NAME, IBUF_LOW_PWR);
$finish;
end
endcase
case (IFD_DELAY_VALUE)
"AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ;
default : begin
$display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on %s instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", MODULE_NAME, IFD_DELAY_VALUE);
$finish;
end
endcase
end
always @(i_in or ib_in or DQS_BIAS_BINARY) begin
if (i_in == 1'b1 && ib_in == 1'b0)
o_out <= 1'b1;
else if (i_in == 1'b0 && ib_in == 1'b1)
o_out <= 1'b0;
else if ((i_in === 1'bz || i_in == 1'b0) && (ib_in === 1'bz || ib_in == 1'b1))
if (DQS_BIAS_BINARY == 1'b1)
o_out <= 1'b0;
else
o_out <= 1'bx;
else if ((i_in === 1'bx) || (ib_in === 1'bx))
o_out <= 1'bx;
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
(IB => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_TB_V
`define SKY130_FD_SC_MS__SDFXBP_TB_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfxbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sdfxbp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O211A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O211A_PP_BLACKBOX_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O211A_PP_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_BEHAVIORAL_PP_V |
module vesa_tpg(
clock,
reset,
dout_ready,
dout_valid,
dout_data,
dout_sop,
dout_eop,
bpp // 3'b000 = 18bpp, 3'b001 = 24bpp
);
parameter MAX_BPC = 8;
input clock;
input reset;
input dout_ready;
output dout_valid;
output [MAX_BPC*3-1:0] dout_data;
output dout_sop;
output dout_eop;
wire [1:0] dout_empty;
input [2:0] bpp;
assign dout_empty = 0;
parameter WIDTH=1920;
parameter HEIGHT=1080;
localparam CTRL_PKT_NUM=3;
localparam CTRL_PKT_HEADER=24'd15;
localparam DATA_PKT_HEADER=24'd0;
///////////////////////
reg [11:0] dot_cnt;
reg [11:0] line_cnt;
///////////////////////
// Catch ready signal
reg dout_ready_reg;
always @(posedge clock or posedge reset) begin
if (reset)
dout_ready_reg <= 0;
else
dout_ready_reg <= dout_ready;
end
///////////////////////
// valid is always 1 but masked by dout_ready_reg
assign dout_valid = dout_ready_reg;
///////////////////////
// State Machine
//reg out;
reg [1:0] pkt_state;
localparam STATE_CTRL_PKT_SOP = 0;
localparam STATE_CTRL_PKT_DAT = 1;
localparam STATE_DATA_PKT_SOP = 2;
localparam STATE_DATA_PKT_DAT = 3;
wire ctrl_pkt_sop = (pkt_state == STATE_CTRL_PKT_SOP ) ? 1 : 0 ;
wire ctrl_pkt_eop = ((pkt_state == STATE_CTRL_PKT_DAT) & (dot_cnt==(CTRL_PKT_NUM-1)) ) ? 1 : 0 ;
wire data_pkt_sop = (pkt_state == STATE_DATA_PKT_SOP ) ? 1 : 0 ;
wire data_pkt_eop = ((pkt_state == STATE_DATA_PKT_DAT) & (dot_cnt==(WIDTH-1)) & (line_cnt==(HEIGHT-1)) ) ? 1 : 0 ;
always @ (posedge clock or posedge reset) begin
if (reset) pkt_state <= STATE_CTRL_PKT_SOP;
else
case (pkt_state) // state transitions
STATE_CTRL_PKT_SOP: if (dout_ready_reg) pkt_state <= STATE_CTRL_PKT_DAT;
STATE_CTRL_PKT_DAT: if (dout_ready_reg & ctrl_pkt_eop) pkt_state <= STATE_DATA_PKT_SOP;
STATE_DATA_PKT_SOP: if (dout_ready_reg) pkt_state <= STATE_DATA_PKT_DAT;
STATE_DATA_PKT_DAT: if (dout_ready_reg & data_pkt_eop) pkt_state <= STATE_CTRL_PKT_SOP;
default : pkt_state <= STATE_CTRL_PKT_DAT;
endcase
end
///////////////////////
/////////////////////////
// sop and eop signals
assign dout_sop = (ctrl_pkt_sop | data_pkt_sop) & dout_ready_reg;
assign dout_eop = (ctrl_pkt_eop | data_pkt_eop) & dout_ready_reg;
always @(posedge clock or posedge reset) begin
if (reset) begin
dot_cnt <= 0;
end
else begin
if (dout_ready_reg)
if ((pkt_state == STATE_DATA_PKT_DAT) ) begin
if ( dot_cnt < (WIDTH-1) )
dot_cnt <= dot_cnt + 1;
else
dot_cnt <= 0;
end
else if ((pkt_state == STATE_CTRL_PKT_DAT) )begin // control packet
if ( dot_cnt < (CTRL_PKT_NUM-1) )
dot_cnt <= dot_cnt + 1;
else
dot_cnt <= 0;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
line_cnt <= 0;
end
else begin
if (dout_ready_reg ) begin
if (pkt_state == STATE_DATA_PKT_DAT) begin
if ( dot_cnt == (WIDTH-1) ) begin
if ( line_cnt < (HEIGHT-1) )
line_cnt <= line_cnt+1;
else
line_cnt <= 0;
end
end
else
line_cnt <= 0;
end
end
end
reg [MAX_BPC*3-1:0] ctrl_data;
wire [MAX_BPC-1:0] r_data;
wire [MAX_BPC-1:0] g_data;
wire [MAX_BPC-1:0] b_data;
wire [MAX_BPC*3-1:0] image_data={r_data, g_data, b_data};
///////////////////////
// Making Image Data
// Generate VESA ramp 6bpc
wire r_line_active_18bpp = line_cnt[7:6] == 2'b00;
wire g_line_active_18bpp = line_cnt[7:6] == 2'b01;
wire b_line_active_18bpp = line_cnt[7:6] == 2'b10;
wire w_line_active_18bpp = line_cnt[7:6] == 2'b11;
wire [MAX_BPC-1:0] r_data_18bpp = {{6{r_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
wire [MAX_BPC-1:0] g_data_18bpp = {{6{g_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
wire [MAX_BPC-1:0] b_data_18bpp = {{6{b_line_active_18bpp}} & dot_cnt[5:0] | {6{w_line_active_18bpp}} & dot_cnt[5:0], {MAX_BPC-6{1'b0}}};
// Generate VESA ramp 8bpc
wire r_line_active_24bpp = line_cnt[7:6] == 2'b00;
wire g_line_active_24bpp = line_cnt[7:6] == 2'b01;
wire b_line_active_24bpp = line_cnt[7:6] == 2'b10;
wire w_line_active_24bpp = line_cnt[7:6] == 2'b11;
wire [MAX_BPC-1:0] r_data_24bpp = {{8{r_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
wire [MAX_BPC-1:0] g_data_24bpp = {{8{g_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
wire [MAX_BPC-1:0] b_data_24bpp = {{8{b_line_active_24bpp}} & dot_cnt[7:0] | {8{w_line_active_24bpp}} & dot_cnt[7:0], {MAX_BPC-8{1'b0}}};
// Combiner
assign r_data = 16'd0 | {16{bpp == 3'b001}} & r_data_24bpp | {16{bpp == 3'b000}} & r_data_18bpp;
assign g_data = 16'd0 | {16{bpp == 3'b001}} & g_data_24bpp | {16{bpp == 3'b000}} & g_data_18bpp;
assign b_data = 16'd0 | {16{bpp == 3'b001}} & b_data_24bpp | {16{bpp == 3'b000}} & b_data_18bpp;
///////////////////////
// Making Final Output Data
reg [MAX_BPC*3-1:0] dout_data;
always @(pkt_state or ctrl_data or image_data ) begin
case (pkt_state)
STATE_CTRL_PKT_SOP: dout_data = CTRL_PKT_HEADER;
STATE_CTRL_PKT_DAT: dout_data = ctrl_data;
STATE_DATA_PKT_SOP: dout_data = DATA_PKT_HEADER;
default: dout_data = image_data;
endcase
end
wire [15:0] w_width = WIDTH;
wire [15:0] w_height = HEIGHT;
always @(dot_cnt[3:0]) begin
case (dot_cnt[3:0])
4'd0 : ctrl_data = {{MAX_BPC-4{1'b0}}, w_width[ 7: 4], {MAX_BPC-4{1'b0}}, w_width[11: 8], {MAX_BPC-4{1'b0}}, w_width[15:12]};
4'd1 : ctrl_data = {{MAX_BPC-4{1'b0}}, w_height[11: 8], {MAX_BPC-4{1'b0}}, w_height[15:12], {MAX_BPC-4{1'b0}}, w_width[ 3: 0]};
4'd2 : ctrl_data = {{MAX_BPC-4{1'b0}}, 4'b0011, {MAX_BPC-4{1'b0}}, w_height[ 3: 0], {MAX_BPC-4{1'b0}}, w_height[ 7: 4]};
default : ctrl_data = {MAX_BPC*3{1'bx}};
endcase
end
endmodule
|
// -----------------------------------------------------------------------
//
// Copyright 2004 Tommy Thorn - All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, Inc., 53 Temple Place Ste 330,
// Bostom MA 02111-1307, USA; either version 2 of the License, or
// (at your option) any later version; incorporated herein by reference.
//
// -----------------------------------------------------------------------
/*
* Simulate a specific subset of the Altera Shift register
* (lpm_clshift).
*
* Not very ambitious, just the bare minimum.
*/
`timescale 1ns/10ps
module arithshiftbidir(distance,
data,
direction,
result);
parameter lpm_type = "LPM_CLSHIFT";
parameter lpm_shifttype = "ARITHMETIC";
parameter lpm_width = 32;
parameter lpm_widthdist = 5;
input wire [lpm_widthdist-1:0] distance;
input signed [lpm_width-1 :0] data;
input wire direction;
output wire [lpm_width-1 :0] result;
wire [lpm_width-1 :0] lsh = data << distance;
wire [lpm_width-1 :0] rsh = data >> distance;
wire [lpm_width-1 :0] rshN = ~(~data >> distance);
wire [lpm_width-1 :0] arsh = data[lpm_width-1] ? rshN : rsh;
assign result = direction ? arsh : lsh;
endmodule
`ifdef TEST_ARITHSHIFTBIDIR
module test_arithshiftbidir();
reg [31:0] data;
reg [ 4:0] dist;
reg dir;
wire [31:0] resulta, resultl;
arithshiftbidir a(dist, data, dir, resulta);
defparam a.lpm_shifttype = "ARITHMETIC";
initial begin
#0 data = 48; dir = 0; dist = 0;
$monitor("dir %d dist %2d A %8x", dir, dist, resulta);
repeat (2) begin
repeat (32)
#1 dist = dist + 1;
data = 32'h98765432;
dir = ~dir;
end
dir = 1;
data = 32'h08765432;
repeat (32)
#1 dist = dist + 1;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_16_V
`define SKY130_FD_SC_LP__CLKINVLP_16_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog wrapper for clkinvlp with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinvlp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__clkinvlp_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__clkinvlp base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BAI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O21BAI_PP_BLACKBOX_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o21bai (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BAI_PP_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [31:0] sum;
wire [15:0] out0;
wire [15:0] out1;
wire [15:0] inData = crc[15:0];
wire wr0a = crc[16];
wire wr0b = crc[17];
wire wr1a = crc[18];
wire wr1b = crc[19];
fifo fifo (
// Outputs
.out0 (out0[15:0]),
.out1 (out1[15:0]),
// Inputs
.clk (clk),
.wr0a (wr0a),
.wr0b (wr0b),
.wr1a (wr1a),
.wr1b (wr1b),
.inData (inData[15:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 32'h0;
end
else if (cyc>10 && cyc<90) begin
sum <= {sum[30:0],sum[31]} ^ {out1, out0};
end
else if (cyc==99) begin
if (sum !== 32'he8bbd130) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module fifo (/*AUTOARG*/
// Outputs
out0, out1,
// Inputs
clk, wr0a, wr0b, wr1a, wr1b, inData
);
input clk;
input wr0a;
input wr0b;
input wr1a;
input wr1b;
input [15:0] inData;
output [15:0] out0;
output [15:0] out1;
reg [15:0] mem [1:0];
reg [15:0] memtemp2 [1:0];
reg [15:0] memtemp3 [1:0];
assign out0 = {mem[0] ^ memtemp2[0]};
assign out1 = {mem[1] ^ memtemp3[1]};
always @(posedge clk) begin
// These mem assignments must be done in order after processing
if (wr0a) begin
memtemp2[0] <= inData;
mem[0] <= inData;
end
if (wr0b) begin
memtemp3[0] <= inData;
mem[0] <= ~inData;
end
if (wr1a) begin
memtemp3[1] <= inData;
mem[1] <= inData;
end
if (wr1b) begin
memtemp2[1] <= inData;
mem[1] <= ~inData;
end
end
endmodule
|
/*
* Arithmetic and logical operations for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_arlog (
input [15:0] x,
input [15:0] y,
input [ 2:0] f,
output [15:0] o,
input word_op,
input cfi,
output cfo,
output afo,
output ofo
);
// Net declarations
wire [15:0] op2;
wire [15:0] outadd;
wire [15:0] outlog;
wire ci;
wire cfoadd;
wire log;
wire xs;
wire ys;
wire os;
// Module instances
zet_fulladd16 fulladd16 ( // We instantiate only one adder
.x (x), // to have less hardware
.y (op2),
.ci (ci),
.co (cfoadd),
.z (outadd),
.s (f[0])
);
// Assignemnts
assign op2 = f[0] ? ~y /* sbb,sub,cmp */
: y; /* add, adc */
assign ci = f[2] | ~f[2] & f[1] & (!f[0] & cfi
| f[0] & ~cfi);
assign log = f[2:0]==3'd1 || f[2:0]==3'd4 || f[2:0]==3'd6;
assign afo = !log & (x[4] ^ y[4] ^ outadd[4]);
assign cfo = !log & (word_op ? cfoadd : (x[8]^y[8]^outadd[8]));
assign xs = word_op ? x[15] : x[7];
assign ys = word_op ? y[15] : y[7];
assign os = word_op ? outadd[15] : outadd[7];
assign ofo = !log &
(f[0] ? (~xs & ys & os | xs & ~ys & ~os)
: (~xs & ~ys & os | xs & ys & ~os));
assign outlog = f[2] ? (f[1] ? x^y : x&y) : x|y;
assign o = log ? outlog : outadd;
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// mix up border and pixels, add palette and blanks
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module video_palframe(
input wire clk, // 28MHz clock
input wire hpix,
input wire vpix,
input wire hblank,
input wire vblank,
input wire hsync_start,
input wire vsync,
input wire [ 3:0] pixels,
input wire [ 3:0] border,
input wire border_sync,
input wire border_sync_ena,
// ulaplus related
input wire [ 1:0] up_palsel,
input wire [ 2:0] up_paper,
input wire [ 2:0] up_ink,
input wire up_pixel,
input wire up_ena,
input wire up_palwr,
input wire [ 5:0] up_paladdr,
input wire [ 7:0] up_paldata,
input wire atm_palwr,
input wire [ 5:0] atm_paldata,
output wire [ 5:0] palcolor, // just for palette readback
output wire [ 5:0] color
);
reg [7:0] palette_read;
wire [ 3:0] zxcolor;
wire [ 5:0] up_color;
wire [ 8:0] palette_color;
reg [3:0] synced_border;
reg vsync_r;
reg [1:0] ctr_14;
reg ctr_h;
reg ctr_v;
always @(posedge clk)
if( border_sync )
synced_border <= border;
assign zxcolor = (hpix&vpix) ? pixels : (border_sync_ena ? synced_border : border);
assign up_color = (hpix&vpix) ? {up_palsel,~up_pixel,up_pixel?up_ink:up_paper} : {3'd0,border[2:0]};
assign palette_color = up_ena ? {3'b100,up_color} : {5'd0,zxcolor};
// palette
reg [7:0] palette [0:511]; // let quartus instantiate it as RAM
always @(posedge clk)
begin
if( atm_palwr || up_palwr )
begin : palette_write
reg [8:0] pal_addr;
pal_addr = atm_palwr ? { 5'd0, zxcolor } : { 3'b100, up_paladdr };
palette[pal_addr] <= atm_palwr ? {atm_paldata[3:2],1'b0,atm_paldata[5:4],1'b0,atm_paldata[1:0]} : up_paldata;
end
palette_read <= palette[palette_color];
end
assign palcolor = {palette_read[4:3],palette_read[7:6], palette_read[1:0]};
// make 3bit palette
always @(posedge clk)
vsync_r <= vsync;
//
wire vsync_start = vsync && !vsync_r;
//
initial ctr_14 = 2'b00;
always @(posedge clk)
ctr_14 <= ctr_14+2'b01;
//
initial ctr_h = 1'b0;
always @(posedge clk) if( hsync_start )
ctr_h <= ~ctr_h;
//
initial ctr_v = 1'b0;
always @(posedge clk) if( vsync_start )
ctr_v <= ~ctr_v;
wire plus1 = ctr_14[1] ^ ctr_h ^ ctr_v;
wire [1:0] red;
wire [1:0] grn;
wire [1:0] blu;
video_palframe_mk3bit red_color
(
.plus1 (plus1 ),
.color_in (palette_read[7:5]),
.color_out(red )
);
//
video_palframe_mk3bit grn_color
(
.plus1 (plus1 ),
.color_in (palette_read[4:2]),
.color_out(grn )
);
//
assign blu = palette_read[1:0];
assign color = (hblank | vblank) ? 6'd0 : {grn,red,blu};
endmodule
module video_palframe_mk3bit
(
input wire plus1,
input wire [2:0] color_in,
output reg [1:0] color_out
);
always @*
case( color_in )
3'b000: color_out <= 2'b00;
3'b001: color_out <= plus1 ? 2'b01 : 2'b00;
3'b010: color_out <= 2'b01;
3'b011: color_out <= plus1 ? 2'b10 : 2'b01;
3'b100: color_out <= 2'b10;
3'b101: color_out <= plus1 ? 2'b11 : 2'b10;
default: color_out <= 2'b11;
endcase
endmodule
|
`include "riscv_defs.v"
module tb_core;
//--------------------------------------------------------------
parameter C_IRQV_SZ = 32;
reg clk = 1'b1;
reg resetb = 1'b0;
// response
wire request;
reg ireqready;
reg irspvalid;
wire irsprerr;
reg [`RV_XLEN-1:0] irspdata;
// verification fifo
wire [`RV_XLEN-1:0] fifo_dout;
// id stage
wire ids_ack;
reg ids_ack_rand;
// hvec
wire hvec_wr;
reg [`RV_XLEN-1:0] hvec_pc;
reg hvec_rand;
// pfu
wire ireqvalid;
wire [`RV_XLEN-1:0] ireqaddr;
wire irspready;
wire ids_dav;
wire [`RV_XLEN-1:0] ids_ins;
wire [`RV_XLEN-1:0] ids_pc;
wire hvec_pc_ready;
//
//--------------------------------------------------------------
// general setup
//
initial
begin
$dumpfile("wave.lxt");
$dumpvars(0, tb_core);
#(200_000);
$finish();
end
// generate a clock
//
always
begin
#50;
clk = ~clk;
end
// generate a reset
//
always @ (posedge clk)
begin
resetb <= 1'b1;
end
// response
//
assign irsprerr = 1'b0; // TODO
assign request = ireqvalid & ireqready;
//
always @ (posedge clk or negedge resetb)
begin
if (~resetb) begin
end else begin
if (ireqvalid) begin
ireqready <= $random();
end
end
//
if (request) begin
if (ireqaddr[1:0] === 2'b0); else $error("Misaligned address."); // TODO assert
irspvalid <= 1'b1;
irspdata <= ireqaddr;
end else begin
irspvalid <= 1'b0;
end
end
// verification fifo
//
fifo
#(
.C_FIFO_WIDTH (`RV_XLEN),
.C_FIFO_DEPTH_X (4)
) i_fifo (
// global
.clk_i (clk),
.clk_en_i (1'b1),
.resetb_i (resetb),
// control and status
.flush_i (1'b0),
.empty_o (),
.full_o (),
// write port
.wr_i (request),
.din_i (ireqaddr),
// read port
.rd_i (ids_ack),
.dout_o (fifo_dout)
);
// id stage
//
assign ids_ack = (ids_dav ? ids_ack_rand : 1'b0);
//
always @ (posedge clk)
begin
if (ids_ack) begin // new ins this cycle
if (fifo_dout === ids_ins && fifo_dout === ids_pc) begin
end else begin
$error("Incorrect data returned by PFU");
$fatal();
end
end
//
ids_ack_rand <= $random();
end
// hvec
//
assign hvec_wr = hvec_rand & hvec_pc_ready;
always @ (posedge clk or negedge resetb)
begin
if (~resetb) begin
hvec_rand <= 1'b0;
end else begin
hvec_pc <= { $random(), 2'b0 };
if (hvec_pc_ready) begin
if ($random() % 10 == 0) begin
hvec_rand <= 1'b1;
end else begin
hvec_rand <= 1'b0;
end
end
end
end
// prefetch unit
//
pfu
#(
.C_BUS_SZX (5), // bus width base 2 exponent
.C_FIFO_DEPTH_X (2), // pfu fifo depth base 2 exponent
.C_RESET_VECTOR (32'h00000000)
) i_pfu (
// global
.clk_i (clk),
.clk_en_i (1'b1),
.resetb_i (resetb),
// instruction cache interface
.ireqready_i (ireqready),
.ireqvalid_o (ireqvalid),
.ireqhpl_o (),
.ireqaddr_o (ireqaddr),
.irspready_o (irspready),
.irspvalid_i (irspvalid),
.irsprerr_i (irsprerr),
.irspdata_i (irspdata),
// decoder interface
.ids_dav_o (ids_dav), // new fetch available
.ids_ack_i (ids_ack),//ids_ack), // ack this fetch
.ids_sofid_o (), // first fetch since vectoring
.ids_ins_o (ids_ins), // instruction fetched
.ids_ferr_o (), // this instruction fetch resulted in error
.ids_pc_o (ids_pc), // address of this instruction
// vectoring and exception controller interface
.hvec_pc_ready_o (hvec_pc_ready),
.hvec_pc_wr_i (hvec_wr),
.hvec_pc_din_i (hvec_pc),
// pfu stage interface
.exs_hpl_i (2'b0)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4B_2_V
`define SKY130_FD_SC_HD__NOR4B_2_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog wrapper for nor4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__nor4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__nor4b_2 (
Y ,
A ,
B ,
C ,
D_N
);
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__nor4b base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4B_2_V
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
/*
* the module of constants
*
* addr out effective
* 1 0 1
* 2 1 1
* 4 + 1
* 8 - 1
* 16 cubic 1
* other 0 0
*/
module const_ (clk, addr, out, effective);
input clk;
input [5:0] addr;
output reg [`WIDTH_D0:0] out;
output reg effective; // active high if out is effective
always @ (posedge clk)
begin
effective <= 1;
case (addr)
1: out <= 0;
2: out <= 1;
4: out <= {6'b000101, 1182'd0};
8: out <= {6'b001001, 1182'd0};
16: out <= {6'b010101, 1182'd0};
default:
begin out <= 0; effective <= 0; end
endcase
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1
)
(
input rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
(* keep = "true", max_fanout = 3 *) wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v1_9_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v1_9_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v1_9_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v1_9_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP)
,.PHY_1_IODELAY_GRP (IODELAY_GRP)
,.PHY_2_IODELAY_GRP (IODELAY_GRP)
,.BANK_TYPE (BANK_TYPE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_TB_V
`define SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_TB_V
/**
* lpflow_isobufsrckapwr: Input isolation, noninverted sleep on
* keep-alive power rail.
*
* X = (!A | SLEEP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_isobufsrckapwr.v"
module top();
// Inputs are registered
reg SLEEP;
reg A;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
SLEEP = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 KAPWR = 1'b1;
#200 SLEEP = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 KAPWR = 1'b0;
#340 SLEEP = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SLEEP = 1'b1;
#540 KAPWR = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SLEEP = 1'bx;
#680 KAPWR = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_isobufsrckapwr dut (.SLEEP(SLEEP), .A(A), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_ISOBUFSRCKAPWR_TB_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v4_0_poc_pd.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: IDDR used as phase detector. The pos_edge and neg_edge stuff
// prevents any noise that could happen when the phase shift clock is very
// nearly aligned to the fabric clock.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v4_0_poc_pd #
(parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter SIM_CAL_OPTION = "NONE",
parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
pd_out,
// Inputs
iddr_rst, clk, kclk, mmcm_ps_clk
);
input iddr_rst;
input clk;
input kclk;
input mmcm_ps_clk;
wire q1;
IDDR #
(.DDR_CLK_EDGE ("OPPOSITE_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC"))
u_phase_detector
(.Q1 (q1),
.Q2 (),
.C (mmcm_ps_clk),
.CE (1'b1),
.D (kclk),
.R (iddr_rst),
.S (1'b0));
// Path from q1 to xxx_edge_samp must be constrained to be less than 1/4 cycle. FIXME
reg pos_edge_samp;
generate if (SIM_CAL_OPTION == "NONE" || POC_USE_METASTABLE_SAMP == "TRUE") begin : no_eXes
always @(posedge clk) pos_edge_samp <= #TCQ q1;
end else begin : eXes
reg q1_delayed;
reg rising_clk_seen;
always @(posedge mmcm_ps_clk) begin
rising_clk_seen <= 1'b0;
q1_delayed <= 1'bx;
end
always @(posedge clk) begin
rising_clk_seen = 1'b1;
if (rising_clk_seen) q1_delayed <= q1;
end
always @(posedge clk) begin
pos_edge_samp <= q1_delayed;
end
end endgenerate
reg pd_out_r;
always @(posedge clk) pd_out_r <= #TCQ pos_edge_samp;
output pd_out;
assign pd_out = pd_out_r;
endmodule // mic_7series_v4_0_poc_pd
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_frontend.v
//
// *Module Description:
// openMSP430 Instruction fetch and decode unit
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 60 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-02-03 22:12:25 +0100 (Mi, 03 Feb 2010) $
//----------------------------------------------------------------------------
`include "timescale.v"
`include "openMSP430_defines.v"
module omsp_frontend (
// OUTPUTs
dbg_halt_st, // Halt/Run status from CPU
decode_noirq, // Frontend decode instruction
e_state, // Execution state
exec_done, // Execution completed
inst_ad, // Decoded Inst: destination addressing mode
inst_as, // Decoded Inst: source addressing mode
inst_alu, // ALU control signals
inst_bw, // Decoded Inst: byte width
inst_dest, // Decoded Inst: destination (one hot)
inst_dext, // Decoded Inst: destination extended instruction word
inst_irq_rst, // Decoded Inst: Reset interrupt
inst_jmp, // Decoded Inst: Conditional jump
inst_sext, // Decoded Inst: source extended instruction word
inst_so, // Decoded Inst: Single-operand arithmetic
inst_src, // Decoded Inst: source (one hot)
inst_type, // Decoded Instruction type
irq_acc, // Interrupt request accepted (one-hot signal)
mab, // Frontend Memory address bus
mb_en, // Frontend Memory bus enable
nmi_acc, // Non-Maskable interrupt request accepted
pc, // Program counter
pc_nxt, // Next PC value (for CALL & IRQ)
// INPUTs
cpuoff, // Turns off the CPU
dbg_halt_cmd, // Halt CPU command
dbg_reg_sel, // Debug selected register for rd/wr access
fe_pmem_wait, // Frontend wait for Instruction fetch
gie, // General interrupt enable
irq, // Maskable interrupts
mclk, // Main system clock
mdb_in, // Frontend Memory data bus input
nmi_evt, // Non-maskable interrupt event
pc_sw, // Program counter software value
pc_sw_wr, // Program counter software write
puc, // Main system reset
wdt_irq // Watchdog-timer interrupt
);
// OUTPUTs
//=========
output dbg_halt_st; // Halt/Run status from CPU
output decode_noirq; // Frontend decode instruction
output [3:0] e_state; // Execution state
output exec_done; // Execution completed
output [7:0] inst_ad; // Decoded Inst: destination addressing mode
output [7:0] inst_as; // Decoded Inst: source addressing mode
output [11:0] inst_alu; // ALU control signals
output inst_bw; // Decoded Inst: byte width
output [15:0] inst_dest; // Decoded Inst: destination (one hot)
output [15:0] inst_dext; // Decoded Inst: destination extended instruction word
output inst_irq_rst; // Decoded Inst: Reset interrupt
output [7:0] inst_jmp; // Decoded Inst: Conditional jump
output [15:0] inst_sext; // Decoded Inst: source extended instruction word
output [7:0] inst_so; // Decoded Inst: Single-operand arithmetic
output [15:0] inst_src; // Decoded Inst: source (one hot)
output [2:0] inst_type; // Decoded Instruction type
output [13:0] irq_acc; // Interrupt request accepted (one-hot signal)
output [15:0] mab; // Frontend Memory address bus
output mb_en; // Frontend Memory bus enable
output nmi_acc; // Non-Maskable interrupt request accepted
output [15:0] pc; // Program counter
output [15:0] pc_nxt; // Next PC value (for CALL & IRQ)
// INPUTs
//=========
input cpuoff; // Turns off the CPU
input dbg_halt_cmd; // Halt CPU command
input [3:0] dbg_reg_sel; // Debug selected register for rd/wr access
input fe_pmem_wait; // Frontend wait for Instruction fetch
input gie; // General interrupt enable
input [13:0] irq; // Maskable interrupts
input mclk; // Main system clock
input [15:0] mdb_in; // Frontend Memory data bus input
input nmi_evt; // Non-maskable interrupt event
input [15:0] pc_sw; // Program counter software value
input pc_sw_wr; // Program counter software write
input puc; // Main system reset
input wdt_irq; // Watchdog-timer interrupt
//=============================================================================
// 1) FRONTEND STATE MACHINE
//=============================================================================
// The wire "conv" is used as state bits to calculate the next response
reg [2:0] i_state;
reg [2:0] i_state_nxt;
reg [1:0] inst_sz;
wire [1:0] inst_sz_nxt;
wire irq_detect;
wire [2:0] inst_type_nxt;
wire is_const;
reg [15:0] sconst_nxt;
reg [3:0] e_state_nxt;
// State machine definitons
parameter I_IRQ_FETCH = 3'h0;
parameter I_IRQ_DONE = 3'h1;
parameter I_DEC = 3'h2; // New instruction ready for decode
parameter I_EXT1 = 3'h3; // 1st Extension word
parameter I_EXT2 = 3'h4; // 2nd Extension word
parameter I_IDLE = 3'h5; // CPU is in IDLE mode
// States Transitions
always @(i_state or inst_sz or inst_sz_nxt or pc_sw_wr or exec_done or
exec_done or irq_detect or cpuoff or dbg_halt_cmd or e_state)
case(i_state)
I_IDLE : i_state_nxt = (irq_detect & ~dbg_halt_cmd) ? I_IRQ_FETCH :
(~cpuoff & ~dbg_halt_cmd) ? I_DEC : I_IDLE;
I_IRQ_FETCH: i_state_nxt = I_IRQ_DONE;
I_IRQ_DONE : i_state_nxt = I_DEC;
I_DEC : i_state_nxt = irq_detect ? I_IRQ_FETCH :
(cpuoff | dbg_halt_cmd) & exec_done ? I_IDLE :
dbg_halt_cmd & (e_state==`E_IDLE) ? I_IDLE :
pc_sw_wr ? I_DEC :
~exec_done & ~(e_state==`E_IDLE) ? I_DEC : // Wait in decode state
(inst_sz_nxt!=2'b00) ? I_EXT1 : I_DEC; // until execution is completed
I_EXT1 : i_state_nxt = irq_detect ? I_IRQ_FETCH :
pc_sw_wr ? I_DEC :
(inst_sz!=2'b01) ? I_EXT2 : I_DEC;
I_EXT2 : i_state_nxt = irq_detect ? I_IRQ_FETCH : I_DEC;
default : i_state_nxt = I_IRQ_FETCH;
endcase
// State machine
always @(posedge mclk or posedge puc)
if (puc) i_state <= I_IRQ_FETCH;
else i_state <= i_state_nxt;
// Utility signals
wire decode_noirq = ((i_state==I_DEC) & (exec_done | (e_state==`E_IDLE)));
wire decode = decode_noirq | irq_detect;
wire fetch = ~((i_state==I_DEC) & ~(exec_done | (e_state==`E_IDLE))) & ~(e_state_nxt==`E_IDLE);
// Debug interface cpu status
reg dbg_halt_st;
always @(posedge mclk or posedge puc)
if (puc) dbg_halt_st <= 1'b0;
else dbg_halt_st <= dbg_halt_cmd & (i_state_nxt==I_IDLE);
//=============================================================================
// 2) INTERRUPT HANDLING
//=============================================================================
// Detect nmi interrupt
reg inst_nmi;
always @(posedge mclk or posedge puc)
if (puc) inst_nmi <= 1'b0;
else if (nmi_evt) inst_nmi <= 1'b1;
else if (i_state==I_IRQ_DONE) inst_nmi <= 1'b0;
// Detect reset interrupt
reg inst_irq_rst;
always @(posedge mclk or posedge puc)
if (puc) inst_irq_rst <= 1'b1;
else if (exec_done) inst_irq_rst <= 1'b0;
// Detect other interrupts
assign irq_detect = (inst_nmi | ((|irq | wdt_irq) & gie)) & ~dbg_halt_cmd & (exec_done | (i_state==I_IDLE));
// Select interrupt vector
reg [3:0] irq_num;
always @(posedge mclk or posedge puc)
if (puc) irq_num <= 4'hf;
else if (irq_detect) irq_num <= inst_nmi ? 4'he :
irq[13] ? 4'hd :
irq[12] ? 4'hc :
irq[11] ? 4'hb :
(irq[10] | wdt_irq) ? 4'ha :
irq[9] ? 4'h9 :
irq[8] ? 4'h8 :
irq[7] ? 4'h7 :
irq[6] ? 4'h6 :
irq[5] ? 4'h5 :
irq[4] ? 4'h4 :
irq[3] ? 4'h3 :
irq[2] ? 4'h2 :
irq[1] ? 4'h1 :
irq[0] ? 4'h0 : 4'hf;
wire [15:0] irq_addr = {11'h7ff, irq_num, 1'b0};
// Interrupt request accepted
wire [15:0] irq_acc_all = (16'h0001 << irq_num) & {16{(i_state==I_IRQ_FETCH)}};
wire [13:0] irq_acc = irq_acc_all[13:0];
wire nmi_acc = irq_acc_all[14];
//=============================================================================
// 3) FETCH INSTRUCTION
//=============================================================================
//
// 3.1) PROGRAM COUNTER & MEMORY INTERFACE
//-----------------------------------------
// Program counter
reg [15:0] pc;
// Compute next PC value
wire [15:0] pc_incr = pc + {14'h0000, fetch, 1'b0};
wire [15:0] pc_nxt = pc_sw_wr ? pc_sw :
(i_state==I_IRQ_FETCH) ? irq_addr :
(i_state==I_IRQ_DONE) ? mdb_in : pc_incr;
always @(posedge mclk or posedge puc)
if (puc) pc <= 16'h0000;
else pc <= pc_nxt;
// Check if ROM has been busy in order to retry ROM access
reg pmem_busy;
always @(posedge mclk or posedge puc)
if (puc) pmem_busy <= 16'h0000;
else pmem_busy <= fe_pmem_wait;
// Memory interface
wire [15:0] mab = pc_nxt;
wire mb_en = fetch | pc_sw_wr | (i_state==I_IRQ_FETCH) | pmem_busy | (dbg_halt_st & ~dbg_halt_cmd);
//
// 3.2) INSTRUCTION REGISTER
//--------------------------------
// Instruction register
wire [15:0] ir = mdb_in;
// Detect if source extension word is required
wire is_sext = (inst_as[`IDX] | inst_as[`SYMB] | inst_as[`ABS] | inst_as[`IMM]);
// Detect if destination extension word is required
wire is_dext = (inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS]);
// For the Symbolic addressing mode, add -2 to the extension word in order
// to make up for the PC address
wire [15:0] ext_incr = ((i_state==I_EXT1) & inst_as[`SYMB]) |
((i_state==I_EXT2) & inst_ad[`SYMB]) |
((i_state==I_EXT1) & ~inst_as[`SYMB] &
~(i_state_nxt==I_EXT2) & inst_ad[`SYMB]) ? 16'hfffe : 16'h0000;
wire [15:0] ext_nxt = ir + ext_incr;
// Store source extension word
reg [15:0] inst_sext;
always @(posedge mclk or posedge puc)
if (puc) inst_sext <= 16'h0000;
else if (decode & is_const) inst_sext <= sconst_nxt;
else if (decode & inst_type_nxt[`INST_JMP]) inst_sext <= {{5{ir[9]}},ir[9:0],1'b0};
else if ((i_state==I_EXT1) & is_sext) inst_sext <= ext_nxt;
// Source extension word is ready
wire inst_sext_rdy = (i_state==I_EXT1) & is_sext;
// Store destination extension word
reg [15:0] inst_dext;
always @(posedge mclk or posedge puc)
if (puc) inst_dext <= 16'h0000;
else if ((i_state==I_EXT1) & ~is_sext) inst_dext <= ext_nxt;
else if (i_state==I_EXT2) inst_dext <= ext_nxt;
// Destination extension word is ready
wire inst_dext_rdy = (((i_state==I_EXT1) & ~is_sext) | (i_state==I_EXT2));
//=============================================================================
// 4) DECODE INSTRUCTION
//=============================================================================
//
// 4.1) OPCODE: INSTRUCTION TYPE
//----------------------------------------
// Instructions type is encoded in a one hot fashion as following:
//
// 3'b001: Single-operand arithmetic
// 3'b010: Conditional jump
// 3'b100: Two-operand arithmetic
reg [2:0] inst_type;
assign inst_type_nxt = {(ir[15:14]!=2'b00),
(ir[15:13]==3'b001),
(ir[15:13]==3'b000)} & {3{~irq_detect}};
always @(posedge mclk or posedge puc)
if (puc) inst_type <= 3'b000;
else if (decode) inst_type <= inst_type_nxt;
//
// 4.2) OPCODE: SINGLE-OPERAND ARITHMETIC
//----------------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 8'b00000001: RRC
// 8'b00000010: SWPB
// 8'b00000100: RRA
// 8'b00001000: SXT
// 8'b00010000: PUSH
// 8'b00100000: CALL
// 8'b01000000: RETI
// 8'b10000000: IRQ
reg [7:0] inst_so;
wire [7:0] inst_so_nxt = irq_detect ? 8'h80 : ((8'h01<<ir[9:7]) & {8{inst_type_nxt[`INST_SO]}});
always @(posedge mclk or posedge puc)
if (puc) inst_so <= 8'h00;
else if (decode) inst_so <= inst_so_nxt;
//
// 4.3) OPCODE: CONDITIONAL JUMP
//--------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 8'b00000001: JNE/JNZ
// 8'b00000010: JEQ/JZ
// 8'b00000100: JNC/JLO
// 8'b00001000: JC/JHS
// 8'b00010000: JN
// 8'b00100000: JGE
// 8'b01000000: JL
// 8'b10000000: JMP
reg [2:0] inst_jmp_bin;
always @(posedge mclk or posedge puc)
if (puc) inst_jmp_bin <= 3'h0;
else if (decode) inst_jmp_bin <= ir[12:10];
wire [7:0] inst_jmp = (8'h01<<inst_jmp_bin) & {8{inst_type[`INST_JMP]}};
//
// 4.4) OPCODE: TWO-OPERAND ARITHMETIC
//-------------------------------------
// Instructions are encoded in a one hot fashion as following:
//
// 12'b000000000001: MOV
// 12'b000000000010: ADD
// 12'b000000000100: ADDC
// 12'b000000001000: SUBC
// 12'b000000010000: SUB
// 12'b000000100000: CMP
// 12'b000001000000: DADD
// 12'b000010000000: BIT
// 12'b000100000000: BIC
// 12'b001000000000: BIS
// 12'b010000000000: XOR
// 12'b100000000000: AND
wire [15:0] inst_to_1hot = (16'h0001<<ir[15:12]) & {16{inst_type_nxt[`INST_TO]}};
wire [11:0] inst_to_nxt = inst_to_1hot[15:4];
//
// 4.5) SOURCE AND DESTINATION REGISTERS
//---------------------------------------
// Destination register
reg [3:0] inst_dest_bin;
always @(posedge mclk or posedge puc)
if (puc) inst_dest_bin <= 4'h0;
else if (decode) inst_dest_bin <= ir[3:0];
wire [15:0] inst_dest = dbg_halt_st ? (16'h0001 << dbg_reg_sel) :
inst_type[`INST_JMP] ? 16'h0001 :
inst_so[`IRQ] |
inst_so[`PUSH] |
inst_so[`CALL] ? 16'h0002 :
(16'h0001 << inst_dest_bin);
// Source register
reg [3:0] inst_src_bin;
always @(posedge mclk or posedge puc)
if (puc) inst_src_bin <= 4'h0;
else if (decode) inst_src_bin <= ir[11:8];
wire [15:0] inst_src = inst_type[`INST_TO] ? (16'h0001 << inst_src_bin) :
inst_so[`RETI] ? 16'h0002 :
inst_so[`IRQ] ? 16'h0001 :
inst_type[`INST_SO] ? (16'h0001 << inst_dest_bin) : 16'h0000;
//
// 4.6) SOURCE ADDRESSING MODES
//--------------------------------
// Source addressing modes are encoded in a one hot fashion as following:
//
// 13'b0000000000001: Register direct.
// 13'b0000000000010: Register indexed.
// 13'b0000000000100: Register indirect.
// 13'b0000000001000: Register indirect autoincrement.
// 13'b0000000010000: Symbolic (operand is in memory at address PC+x).
// 13'b0000000100000: Immediate (operand is next word in the instruction stream).
// 13'b0000001000000: Absolute (operand is in memory at address x).
// 13'b0000010000000: Constant 4.
// 13'b0000100000000: Constant 8.
// 13'b0001000000000: Constant 0.
// 13'b0010000000000: Constant 1.
// 13'b0100000000000: Constant 2.
// 13'b1000000000000: Constant -1.
reg [12:0] inst_as_nxt;
wire [3:0] src_reg = inst_type_nxt[`INST_SO] ? ir[3:0] : ir[11:8];
always @(src_reg or ir or inst_type_nxt)
begin
if (inst_type_nxt[`INST_JMP])
inst_as_nxt = 13'b0000000000001;
else if (src_reg==4'h3) // Addressing mode using R3
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b1000000000000;
2'b10 : inst_as_nxt = 13'b0100000000000;
2'b01 : inst_as_nxt = 13'b0010000000000;
default: inst_as_nxt = 13'b0001000000000;
endcase
else if (src_reg==4'h2) // Addressing mode using R2
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b0000100000000;
2'b10 : inst_as_nxt = 13'b0000010000000;
2'b01 : inst_as_nxt = 13'b0000001000000;
default: inst_as_nxt = 13'b0000000000001;
endcase
else if (src_reg==4'h0) // Addressing mode using R0
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b0000000100000;
2'b10 : inst_as_nxt = 13'b0000000000100;
2'b01 : inst_as_nxt = 13'b0000000010000;
default: inst_as_nxt = 13'b0000000000001;
endcase
else // General Addressing mode
case (ir[5:4])
2'b11 : inst_as_nxt = 13'b0000000001000;
2'b10 : inst_as_nxt = 13'b0000000000100;
2'b01 : inst_as_nxt = 13'b0000000000010;
default: inst_as_nxt = 13'b0000000000001;
endcase
end
assign is_const = |inst_as_nxt[12:7];
reg [7:0] inst_as;
always @(posedge mclk or posedge puc)
if (puc) inst_as <= 8'h00;
else if (decode) inst_as <= {is_const, inst_as_nxt[6:0]};
// 13'b0000010000000: Constant 4.
// 13'b0000100000000: Constant 8.
// 13'b0001000000000: Constant 0.
// 13'b0010000000000: Constant 1.
// 13'b0100000000000: Constant 2.
// 13'b1000000000000: Constant -1.
always @(inst_as_nxt)
begin
if (inst_as_nxt[7]) sconst_nxt = 16'h0004;
else if (inst_as_nxt[8]) sconst_nxt = 16'h0008;
else if (inst_as_nxt[9]) sconst_nxt = 16'h0000;
else if (inst_as_nxt[10]) sconst_nxt = 16'h0001;
else if (inst_as_nxt[11]) sconst_nxt = 16'h0002;
else if (inst_as_nxt[12]) sconst_nxt = 16'hffff;
else sconst_nxt = 16'h0000;
end
//
// 4.7) DESTINATION ADDRESSING MODES
//-----------------------------------
// Destination addressing modes are encoded in a one hot fashion as following:
//
// 8'b00000001: Register direct.
// 8'b00000010: Register indexed.
// 8'b00010000: Symbolic (operand is in memory at address PC+x).
// 8'b01000000: Absolute (operand is in memory at address x).
reg [7:0] inst_ad_nxt;
wire [3:0] dest_reg = ir[3:0];
always @(dest_reg or ir or inst_type_nxt)
begin
if (~inst_type_nxt[`INST_TO])
inst_ad_nxt = 8'b00000000;
else if (dest_reg==4'h2) // Addressing mode using R2
case (ir[7])
1'b1 : inst_ad_nxt = 8'b01000000;
default: inst_ad_nxt = 8'b00000001;
endcase
else if (dest_reg==4'h0) // Addressing mode using R0
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00010000;
default: inst_ad_nxt = 8'b00000001;
endcase
else // General Addressing mode
case (ir[7])
2'b1 : inst_ad_nxt = 8'b00000010;
default: inst_ad_nxt = 8'b00000001;
endcase
end
reg [7:0] inst_ad;
always @(posedge mclk or posedge puc)
if (puc) inst_ad <= 8'h00;
else if (decode) inst_ad <= inst_ad_nxt;
//
// 4.8) REMAINING INSTRUCTION DECODING
//-------------------------------------
// Operation size
reg inst_bw;
always @(posedge mclk or posedge puc)
if (puc) inst_bw <= 1'b0;
else if (decode) inst_bw <= ir[6] & ~inst_type_nxt[`INST_JMP] & ~irq_detect & ~dbg_halt_cmd;
// Extended instruction size
assign inst_sz_nxt = {1'b0, (inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS] | inst_as_nxt[`IMM])} +
{1'b0, ((inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS]) & ~inst_type_nxt[`INST_SO])};
always @(posedge mclk or posedge puc)
if (puc) inst_sz <= 2'b00;
else if (decode) inst_sz <= inst_sz_nxt;
//=============================================================================
// 5) EXECUTION-UNIT STATE MACHINE
//=============================================================================
// State machine registers
reg [3:0] e_state;
// State machine control signals
//--------------------------------
wire src_acalc_pre = inst_as_nxt[`IDX] | inst_as_nxt[`SYMB] | inst_as_nxt[`ABS];
wire src_rd_pre = inst_as_nxt[`INDIR] | inst_as_nxt[`INDIR_I] | inst_as_nxt[`IMM] | inst_so_nxt[`RETI];
wire dst_acalc_pre = inst_ad_nxt[`IDX] | inst_ad_nxt[`SYMB] | inst_ad_nxt[`ABS];
wire dst_acalc = inst_ad[`IDX] | inst_ad[`SYMB] | inst_ad[`ABS];
wire dst_rd_pre = inst_ad_nxt[`IDX] | inst_so_nxt[`PUSH] | inst_so_nxt[`CALL] | inst_so_nxt[`RETI];
wire dst_rd = inst_ad[`IDX] | inst_so[`PUSH] | inst_so[`CALL] | inst_so[`RETI];
wire inst_branch = (inst_ad_nxt[`DIR] & (ir[3:0]==4'h0)) | inst_type_nxt[`INST_JMP] | inst_so_nxt[`RETI];
reg exec_jmp;
always @(posedge mclk or posedge puc)
if (puc) exec_jmp <= 1'b0;
else if (inst_branch & decode) exec_jmp <= 1'b1;
else if (e_state==`E_JUMP) exec_jmp <= 1'b0;
reg exec_dst_wr;
always @(posedge mclk or posedge puc)
if (puc) exec_dst_wr <= 1'b0;
else if (e_state==`E_DST_RD) exec_dst_wr <= 1'b1;
else if (e_state==`E_DST_WR) exec_dst_wr <= 1'b0;
reg exec_src_wr;
always @(posedge mclk or posedge puc)
if (puc) exec_src_wr <= 1'b0;
else if (inst_type[`INST_SO] & (e_state==`E_SRC_RD)) exec_src_wr <= 1'b1;
else if ((e_state==`E_SRC_WR) || (e_state==`E_DST_WR)) exec_src_wr <= 1'b0;
reg exec_dext_rdy;
always @(posedge mclk or posedge puc)
if (puc) exec_dext_rdy <= 1'b0;
else if (e_state==`E_DST_RD) exec_dext_rdy <= 1'b0;
else if (inst_dext_rdy) exec_dext_rdy <= 1'b1;
// Execution first state
//wire [3:0] e_first_state = dbg_halt_cmd ? `E_IDLE :
wire [3:0] e_first_state = ~dbg_halt_st & inst_so_nxt[`IRQ] ? `E_IRQ_0 :
dbg_halt_cmd | (i_state==I_IDLE) ? `E_IDLE :
cpuoff ? `E_IDLE :
src_acalc_pre ? `E_SRC_AD :
src_rd_pre ? `E_SRC_RD :
dst_acalc_pre ? `E_DST_AD :
dst_rd_pre ? `E_DST_RD : `E_EXEC;
// State machine
//--------------------------------
// States Transitions
always @(e_state or dst_acalc or dst_rd or inst_sext_rdy or
inst_dext_rdy or exec_dext_rdy or exec_jmp or exec_dst_wr or
e_first_state or exec_src_wr)
case(e_state)
`E_IDLE : e_state_nxt = e_first_state;
`E_IRQ_0 : e_state_nxt = `E_IRQ_1;
`E_IRQ_1 : e_state_nxt = `E_IRQ_2;
`E_IRQ_2 : e_state_nxt = `E_IRQ_3;
`E_IRQ_3 : e_state_nxt = `E_IRQ_4;
`E_IRQ_4 : e_state_nxt = `E_EXEC;
`E_SRC_AD : e_state_nxt = inst_sext_rdy ? `E_SRC_RD : `E_SRC_AD;
`E_SRC_RD : e_state_nxt = dst_acalc ? `E_DST_AD :
dst_rd ? `E_DST_RD : `E_EXEC;
`E_DST_AD : e_state_nxt = (inst_dext_rdy |
exec_dext_rdy) ? `E_DST_RD : `E_DST_AD;
`E_DST_RD : e_state_nxt = `E_EXEC;
`E_EXEC : e_state_nxt = exec_dst_wr ? `E_DST_WR :
exec_jmp ? `E_JUMP :
exec_src_wr ? `E_SRC_WR : e_first_state;
`E_JUMP : e_state_nxt = e_first_state;
`E_DST_WR : e_state_nxt = exec_jmp ? `E_JUMP : e_first_state;
`E_SRC_WR : e_state_nxt = e_first_state;
default : e_state_nxt = `E_IRQ_0;
endcase
// State machine
always @(posedge mclk or posedge puc)
if (puc) e_state <= `E_IRQ_1;
else e_state <= e_state_nxt;
// Frontend State machine control signals
//----------------------------------------
wire exec_done = exec_jmp ? (e_state==`E_JUMP) :
exec_dst_wr ? (e_state==`E_DST_WR) :
exec_src_wr ? (e_state==`E_SRC_WR) : (e_state==`E_EXEC);
//=============================================================================
// 6) EXECUTION-UNIT STATE CONTROL
//=============================================================================
//
// 6.1) ALU CONTROL SIGNALS
//-------------------------------------
//
// 12'b000000000001: Enable ALU source inverter
// 12'b000000000010: Enable Incrementer
// 12'b000000000100: Enable Incrementer on carry bit
// 12'b000000001000: Select Adder
// 12'b000000010000: Select AND
// 12'b000000100000: Select OR
// 12'b000001000000: Select XOR
// 12'b000010000000: Select DADD
// 12'b000100000000: Update N, Z & C (C=~Z)
// 12'b001000000000: Update all status bits
// 12'b010000000000: Update status bit for XOR instruction
// 12'b100000000000: Don't write to destination
reg [11:0] inst_alu;
wire alu_src_inv = inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_to_nxt[`BIC] ;
wire alu_inc = inst_to_nxt[`SUB] | inst_to_nxt[`CMP];
wire alu_inc_c = inst_to_nxt[`ADDC] | inst_to_nxt[`DADD] |
inst_to_nxt[`SUBC];
wire alu_add = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] |
inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_type_nxt[`INST_JMP] |
inst_so_nxt[`RETI];
wire alu_and = inst_to_nxt[`AND] | inst_to_nxt[`BIC] |
inst_to_nxt[`BIT];
wire alu_or = inst_to_nxt[`BIS];
wire alu_xor = inst_to_nxt[`XOR];
wire alu_dadd = inst_to_nxt[`DADD];
wire alu_stat_7 = inst_to_nxt[`BIT] | inst_to_nxt[`AND] |
inst_so_nxt[`SXT];
wire alu_stat_f = inst_to_nxt[`ADD] | inst_to_nxt[`ADDC] |
inst_to_nxt[`SUB] | inst_to_nxt[`SUBC] |
inst_to_nxt[`CMP] | inst_to_nxt[`DADD] |
inst_to_nxt[`BIT] | inst_to_nxt[`XOR] |
inst_to_nxt[`AND] |
inst_so_nxt[`RRC] | inst_so_nxt[`RRA] |
inst_so_nxt[`SXT];
wire alu_shift = inst_so_nxt[`RRC] | inst_so_nxt[`RRA];
wire exec_no_wr = inst_to_nxt[`CMP] | inst_to_nxt[`BIT];
always @(posedge mclk or posedge puc)
if (puc) inst_alu <= 12'h000;
else if (decode) inst_alu <= {exec_no_wr,
alu_shift,
alu_stat_f,
alu_stat_7,
alu_dadd,
alu_xor,
alu_or,
alu_and,
alu_add,
alu_inc_c,
alu_inc,
alu_src_inv};
endmodule // omsp_frontend
`include "openMSP430_undefines.v"
|
//////////////////////////////////////////////////////////////////
// //
// UART //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// This is a synchronous UART meaning it uses the system //
// clock rather than having its own clock. This means the //
// standard UART Baud rates are approximated and not exact. //
// However the UART tandard provides for a 10% margin on //
// baud rates and this module is much more accurate than that. //
// //
// The Baud rate must be set before synthesis and is not //
// programmable. This keeps the UART small. //
// //
// The UART uses 8 data bits, 1 stop bit and no parity bits. //
// //
// The UART has a 16-byte transmit and a 16-byte receive FIFO //
// These FIFOs are implemented in flipflops - FPGAs have lots //
// of flipflops! //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "system_config_defines.v"
`include "global_defines.v"
// Normally AMBER_UART_BAUD is defined in the system_config_defines.v file.
`ifndef AMBER_UART_BAUD
`define AMBER_UART_BAUD 230400
`endif
module uart #(
parameter WB_DWIDTH = 32,
parameter WB_SWIDTH = 4
)(
input i_clk,
input [31:0] i_wb_adr,
input [WB_SWIDTH-1:0] i_wb_sel,
input i_wb_we,
output [WB_DWIDTH-1:0] o_wb_dat,
input [WB_DWIDTH-1:0] i_wb_dat,
input i_wb_cyc,
input i_wb_stb,
output o_wb_ack,
output o_wb_err,
output o_uart_int,
input i_uart_cts_n, // Clear To Send
output o_uart_txd, // Transmit data
output o_uart_rts_n, // Request to Send
input i_uart_rxd // Receive data
);
`include "register_addresses.v"
localparam [3:0] TXD_IDLE = 4'd0,
TXD_START = 4'd1,
TXD_DATA0 = 4'd2,
TXD_DATA1 = 4'd3,
TXD_DATA2 = 4'd4,
TXD_DATA3 = 4'd5,
TXD_DATA4 = 4'd6,
TXD_DATA5 = 4'd7,
TXD_DATA6 = 4'd8,
TXD_DATA7 = 4'd9,
TXD_STOP1 = 4'd10,
TXD_STOP2 = 4'd11,
TXD_STOP3 = 4'd12;
localparam [3:0] RXD_IDLE = 4'd0,
RXD_START = 4'd1,
RXD_START_MID = 4'd2,
RXD_START_MID1 = 4'd3,
RXD_DATA0 = 4'd4,
RXD_DATA1 = 4'd5,
RXD_DATA2 = 4'd6,
RXD_DATA3 = 4'd7,
RXD_DATA4 = 4'd8,
RXD_DATA5 = 4'd9,
RXD_DATA6 = 4'd10,
RXD_DATA7 = 4'd11,
RXD_STOP = 4'd12;
localparam RX_INTERRUPT_COUNT = 24'h3fffff;
// -------------------------------------------------------------------------
// Baud Rate Configuration
// -------------------------------------------------------------------------
`ifndef Veritak
localparam real UART_BAUD = `AMBER_UART_BAUD; // Hz
`ifdef XILINX_VIRTEX6_FPGA
localparam real CLK_FREQ = 1200.0 / `AMBER_CLK_DIVIDER ; // MHz
`else
localparam real CLK_FREQ = 800.0 / `AMBER_CLK_DIVIDER ; // MHz
`endif
localparam real UART_BIT_PERIOD = 1000000000 / UART_BAUD; // nS
localparam real UART_WORD_PERIOD = ( UART_BIT_PERIOD * 12 ); // nS
localparam real CLK_PERIOD = 1000 / CLK_FREQ; // nS
localparam real CLKS_PER_WORD = UART_WORD_PERIOD / CLK_PERIOD;
localparam real CLKS_PER_BIT = CLKS_PER_WORD / 12;
// These are rounded to the nearest whole number
// i.e. 29.485960 -> 29
// 29.566303 -> 30
localparam [9:0] TX_BITPULSE_COUNT = CLKS_PER_BIT;
localparam [9:0] TX_CLKS_PER_WORD = CLKS_PER_WORD;
`else
localparam [9:0] TX_BITPULSE_COUNT = 30;
localparam [9:0] TX_CLKS_PER_WORD = 360;
`endif
localparam [9:0] TX_BITADJUST_COUNT = TX_CLKS_PER_WORD - 11*TX_BITPULSE_COUNT;
localparam [9:0] RX_BITPULSE_COUNT = TX_BITPULSE_COUNT-2;
localparam [9:0] RX_HALFPULSE_COUNT = TX_BITPULSE_COUNT/2 - 4;
// -------------------------------------------------------------------------
reg tx_interrupt = 'd0;
reg rx_interrupt = 'd0;
reg [23:0] rx_int_timer = 'd0;
wire fifo_enable;
reg [7:0] tx_fifo [0:15];
wire tx_fifo_full;
wire tx_fifo_empty;
wire tx_fifo_half_or_less_full;
wire tx_fifo_push;
wire tx_fifo_push_not_full;
wire tx_fifo_pop_not_empty;
reg [4:0] tx_fifo_wp = 'd0;
reg [4:0] tx_fifo_rp = 'd0;
reg [4:0] tx_fifo_count = 'd0; // number of entries in the fifo
reg tx_fifo_full_flag = 'd0;
reg [7:0] rx_fifo [0:15];
reg rx_fifo_empty = 1'd1;
reg rx_fifo_full = 1'd0;
wire rx_fifo_half_or_more; // true when half full or greater
reg [4:0] rx_fifo_count = 'd0; // number of entries in the fifo
wire rx_fifo_push;
wire rx_fifo_push_not_full;
wire rx_fifo_pop;
wire rx_fifo_pop_not_empty;
reg [4:0] rx_fifo_wp = 'd0;
reg [4:0] rx_fifo_rp = 'd0;
wire [7:0] tx_byte;
reg [3:0] txd_state = TXD_IDLE;
reg txd = 1'd1;
reg tx_bit_pulse = 'd0;
reg [9:0] tx_bit_pulse_count = 'd0;
reg [7:0] rx_byte = 'd0;
reg [3:0] rxd_state = RXD_IDLE;
wire rx_start;
reg rxen = 'd0;
reg [9:0] rx_bit_pulse_count = 'd0;
reg restart_rx_bit_count = 'd0;
reg [4:0] rxd_d = 5'h1f;
reg [3:0] uart0_cts_n_d = 4'hf;
// Wishbone registers
reg [7:0] uart_rsr_reg = 'd0; // Receive status, (Write) Error Clear
reg [7:0] uart_lcrh_reg = 'd0; // Line Control High Byte
reg [7:0] uart_lcrm_reg = 'd0; // Line Control Middle Byte
reg [7:0] uart_lcrl_reg = 'd0; // Line Control Low Byte
reg [7:0] uart_cr_reg = 'd0; // Control Register
// Wishbone interface
reg [31:0] wb_rdata32 = 'd0;
wire wb_start_write;
wire wb_start_read;
reg wb_start_read_d1 = 'd0;
wire [31:0] wb_wdata32;
integer i;
// ======================================================
// Wishbone Interface
// ======================================================
// Can't start a write while a read is completing. The ack for the read cycle
// needs to be sent first
assign wb_start_write = i_wb_stb && i_wb_we && !wb_start_read_d1;
assign wb_start_read = i_wb_stb && !i_wb_we && !o_wb_ack;
always @( posedge i_clk )
wb_start_read_d1 <= wb_start_read;
assign o_wb_err = 1'd0;
assign o_wb_ack = i_wb_stb && ( wb_start_write || wb_start_read_d1 );
generate
if (WB_DWIDTH == 128)
begin : wb128
assign wb_wdata32 = i_wb_adr[3:2] == 2'd3 ? i_wb_dat[127:96] :
i_wb_adr[3:2] == 2'd2 ? i_wb_dat[ 95:64] :
i_wb_adr[3:2] == 2'd1 ? i_wb_dat[ 63:32] :
i_wb_dat[ 31: 0] ;
assign o_wb_dat = {4{wb_rdata32}};
end
else
begin : wb32
assign wb_wdata32 = i_wb_dat;
assign o_wb_dat = wb_rdata32;
end
endgenerate
// ======================================================
// UART 0 Receive FIFO
// ======================================================
assign rx_fifo_pop = wb_start_read && i_wb_adr[15:0] == AMBER_UART_DR;
assign rx_fifo_push_not_full = rx_fifo_push && !rx_fifo_full;
assign rx_fifo_pop_not_empty = rx_fifo_pop && !rx_fifo_empty;
assign rx_fifo_half_or_more = rx_fifo_count >= 5'd8;
always @ ( posedge i_clk )
begin
if ( fifo_enable )
begin
// RX FIFO Push
if ( rx_fifo_push_not_full )
begin
rx_fifo[rx_fifo_wp[3:0]] <= rx_byte;
rx_fifo_wp <= rx_fifo_wp + 1'd1;
end
if ( rx_fifo_pop_not_empty )
begin
rx_fifo_rp <= rx_fifo_rp + 1'd1;
end
if ( rx_fifo_push_not_full && !rx_fifo_pop_not_empty )
rx_fifo_count <= rx_fifo_count + 1'd1;
else if ( rx_fifo_pop_not_empty && !rx_fifo_push_not_full )
rx_fifo_count <= rx_fifo_count - 1'd1;
rx_fifo_full <= rx_fifo_wp == {~rx_fifo_rp[4], rx_fifo_rp[3:0]};
rx_fifo_empty <= rx_fifo_wp == rx_fifo_rp;
if ( rx_fifo_empty || rx_fifo_pop )
rx_int_timer <= 'd0;
else if ( rx_int_timer != RX_INTERRUPT_COUNT )
rx_int_timer <= rx_int_timer + 1'd1;
end
else // No FIFO
begin
rx_int_timer <= 'd0;
if ( rx_fifo_push )
begin
rx_fifo[0] <= rx_byte;
rx_fifo_empty <= 1'd0;
rx_fifo_full <= 1'd1;
end
else if ( rx_fifo_pop )
begin
rx_fifo_empty <= 1'd1;
rx_fifo_full <= 1'd0;
end
end
end
// ======================================================
// Transmit Interrupts
// ======================================================
// UART 0 Transmit Interrupt
always @ ( posedge i_clk )
begin
// Clear the interrupt
if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
tx_interrupt <= 1'd0;
// Set the interrupt
else if ( fifo_enable )
// This interrupt clears automatically as bytes are pushed into the tx fifo
// cr bit 5 is Transmit Interrupt Enable
tx_interrupt <= tx_fifo_half_or_less_full && uart_cr_reg[5];
else
// This interrupt clears automatically when a byte is written to tx
// cr bit 5 is Transmit Interrupt Enable
tx_interrupt <= tx_fifo_empty && uart_cr_reg[5];
end
// ======================================================
// Receive Interrupts
// ======================================================
always @ ( posedge i_clk )
if (fifo_enable)
rx_interrupt <= rx_fifo_half_or_more || rx_int_timer == RX_INTERRUPT_COUNT;
else
rx_interrupt <= rx_fifo_full;
assign o_uart_int = ( tx_interrupt & uart_cr_reg[5] ) | // UART transmit interrupt w/ enable
( rx_interrupt & uart_cr_reg[4] ) ; // UART receive interrupt w/ enable
assign fifo_enable = uart_lcrh_reg[4];
// ========================================================
// UART Transmit
// ========================================================
assign o_uart_txd = txd;
assign tx_fifo_full = fifo_enable ? tx_fifo_count >= 5'd16 : tx_fifo_full_flag;
assign tx_fifo_empty = fifo_enable ? tx_fifo_count == 5'd00 : !tx_fifo_full_flag;
assign tx_fifo_half_or_less_full = tx_fifo_count <= 5'd8;
assign tx_byte = fifo_enable ? tx_fifo[tx_fifo_rp[3:0]] : tx_fifo[0] ;
assign tx_fifo_push = wb_start_write && i_wb_adr[15:0] == AMBER_UART_DR;
assign tx_fifo_push_not_full = tx_fifo_push && !tx_fifo_full;
assign tx_fifo_pop_not_empty = txd_state == TXD_STOP3 && tx_bit_pulse == 1'd1 && !tx_fifo_empty;
// Transmit FIFO
always @( posedge i_clk )
begin
// Use 8-entry FIFO
if ( fifo_enable )
begin
// Push
if ( tx_fifo_push_not_full )
begin
tx_fifo[tx_fifo_wp[3:0]] <= wb_wdata32[7:0];
tx_fifo_wp <= tx_fifo_wp + 1'd1;
end
// Pop
if ( tx_fifo_pop_not_empty )
tx_fifo_rp <= tx_fifo_rp + 1'd1;
// Count up
if (tx_fifo_push_not_full && !tx_fifo_pop_not_empty)
tx_fifo_count <= tx_fifo_count + 1'd1;
// Count down
else if (tx_fifo_pop_not_empty && !tx_fifo_push_not_full)
tx_fifo_count <= tx_fifo_count - 1'd1;
end
// Do not use 8-entry FIFO, single entry register instead
else
begin
// Clear FIFO values
tx_fifo_wp <= 'd0;
tx_fifo_rp <= 'd0;
tx_fifo_count <= 'd0;
// Push
if ( tx_fifo_push_not_full )
begin
tx_fifo[0] <= wb_wdata32[7:0];
tx_fifo_full_flag <= 1'd1;
end
// Pop
else if ( tx_fifo_pop_not_empty )
tx_fifo_full_flag <= 1'd0;
end
end
// ========================================================
// Register Clear to Send Input
// ========================================================
always @( posedge i_clk )
uart0_cts_n_d <= {uart0_cts_n_d[2:0], i_uart_cts_n};
// ========================================================
// Transmit Pulse generater - matches baud rate
// ========================================================
always @( posedge i_clk )
if (( tx_bit_pulse_count == (TX_BITADJUST_COUNT-1) && txd_state == TXD_STOP2 ) ||
( tx_bit_pulse_count == (TX_BITPULSE_COUNT-1) && txd_state != TXD_STOP2 ) )
begin
tx_bit_pulse_count <= 'd0;
tx_bit_pulse <= 1'd1;
end
else
begin
tx_bit_pulse_count <= tx_bit_pulse_count + 1'd1;
tx_bit_pulse <= 1'd0;
end
// ========================================================
// Byte Transmitted
// ========================================================
// Idle state, txd = 1
// start bit, txd = 0
// Data x 8, lsb first
// stop bit, txd = 1
// X = 0x58 = 01011000
always @( posedge i_clk )
if ( tx_bit_pulse )
case ( txd_state )
TXD_IDLE :
begin
txd <= 1'd1;
if ( uart0_cts_n_d[3:1] == 3'b000 && !tx_fifo_empty )
txd_state <= TXD_START;
end
TXD_START :
begin
txd <= 1'd0;
txd_state <= TXD_DATA0;
end
TXD_DATA0 :
begin
txd <= tx_byte[0];
txd_state <= TXD_DATA1;
end
TXD_DATA1 :
begin
txd <= tx_byte[1];
txd_state <= TXD_DATA2;
end
TXD_DATA2 :
begin
txd <= tx_byte[2];
txd_state <= TXD_DATA3;
end
TXD_DATA3 :
begin
txd <= tx_byte[3];
txd_state <= TXD_DATA4;
end
TXD_DATA4 :
begin
txd <= tx_byte[4];
txd_state <= TXD_DATA5;
end
TXD_DATA5 :
begin
txd <= tx_byte[5];
txd_state <= TXD_DATA6;
end
TXD_DATA6 :
begin
txd <= tx_byte[6];
txd_state <= TXD_DATA7;
end
TXD_DATA7 :
begin
txd <= tx_byte[7];
txd_state <= TXD_STOP1;
end
TXD_STOP1 :
begin
txd <= 1'd1;
txd_state <= TXD_STOP2;
end
TXD_STOP2 :
begin
txd <= 1'd1;
txd_state <= TXD_STOP3;
end
TXD_STOP3 :
begin
txd <= 1'd1;
txd_state <= TXD_IDLE;
end
default :
begin
txd <= 1'd1;
end
endcase
// ========================================================
// UART Receive
// ========================================================
assign o_uart_rts_n = ~rxen;
assign rx_fifo_push = rxd_state == RXD_STOP && rx_bit_pulse_count == 10'd0;
// ========================================================
// Receive bit pulse
// ========================================================
// Pulse generater - matches baud rate
always @( posedge i_clk )
if ( restart_rx_bit_count )
rx_bit_pulse_count <= 'd0;
else
rx_bit_pulse_count <= rx_bit_pulse_count + 1'd1;
// ========================================================
// Detect 1->0 transition. Filter out glitches and jaggedy transitions
// ========================================================
always @( posedge i_clk )
rxd_d[4:0] <= {rxd_d[3:0], i_uart_rxd};
assign rx_start = rxd_d[4:3] == 2'b11 && rxd_d[1:0] == 2'b00;
// ========================================================
// Receive state machine
// ========================================================
always @( posedge i_clk )
case ( rxd_state )
RXD_IDLE :
if ( rx_fifo_full )
rxen <= 1'd0;
else
begin
rxd_state <= RXD_START;
rxen <= 1'd1;
restart_rx_bit_count <= 1'd1;
rx_byte <= 'd0;
end
RXD_START :
// Filter out glitches and jaggedy transitions
if ( rx_start )
begin
rxd_state <= RXD_START_MID1;
restart_rx_bit_count <= 1'd1;
end
else
restart_rx_bit_count <= 1'd0;
// This state just delays the check on the
// rx_bit_pulse_count value by 1 clock cycle to
// give it time to reset
RXD_START_MID1 :
rxd_state <= RXD_START_MID;
RXD_START_MID :
if ( rx_bit_pulse_count == RX_HALFPULSE_COUNT )
begin
rxd_state <= RXD_DATA0;
restart_rx_bit_count <= 1'd1;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA0 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_DATA1;
restart_rx_bit_count <= 1'd1;
rx_byte[0] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA1 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_DATA2;
restart_rx_bit_count <= 1'd1;
rx_byte[1] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA2 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_DATA3;
restart_rx_bit_count <= 1'd1;
rx_byte[2] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA3 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_DATA4;
restart_rx_bit_count <= 1'd1;
rx_byte[3] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA4 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_DATA5;
restart_rx_bit_count <= 1'd1;
rx_byte[4] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA5 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_DATA6;
restart_rx_bit_count <= 1'd1;
rx_byte[5] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA6 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_DATA7;
restart_rx_bit_count <= 1'd1;
rx_byte[6] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_DATA7 :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT )
begin
rxd_state <= RXD_STOP;
restart_rx_bit_count <= 1'd1;
rx_byte[7] <= i_uart_rxd;
end
else
restart_rx_bit_count <= 1'd0;
RXD_STOP :
if ( rx_bit_pulse_count == RX_BITPULSE_COUNT ) // half way through stop bit
begin
rxd_state <= RXD_IDLE;
restart_rx_bit_count <= 1'd1;
end
else
restart_rx_bit_count <= 1'd0;
default :
begin
rxd_state <= RXD_IDLE;
end
endcase
// ========================================================
// Register Writes
// ========================================================
always @( posedge i_clk )
if ( wb_start_write )
case ( i_wb_adr[15:0] )
// Receive status, (Write) Error Clear
AMBER_UART_RSR: uart_rsr_reg <= wb_wdata32[7:0];
// Line Control High Byte
AMBER_UART_LCRH: uart_lcrh_reg <= wb_wdata32[7:0];
// Line Control Middle Byte
AMBER_UART_LCRM: uart_lcrm_reg <= wb_wdata32[7:0];
// Line Control Low Byte
AMBER_UART_LCRL: uart_lcrl_reg <= wb_wdata32[7:0];
// Control Register
AMBER_UART_CR: uart_cr_reg <= wb_wdata32[7:0];
endcase
// ========================================================
// Register Reads
// ========================================================
always @( posedge i_clk )
if ( wb_start_read )
case ( i_wb_adr[15:0] )
AMBER_UART_CID0: wb_rdata32 <= 32'h0d;
AMBER_UART_CID1: wb_rdata32 <= 32'hf0;
AMBER_UART_CID2: wb_rdata32 <= 32'h05;
AMBER_UART_CID3: wb_rdata32 <= 32'hb1;
AMBER_UART_PID0: wb_rdata32 <= 32'h10;
AMBER_UART_PID1: wb_rdata32 <= 32'h10;
AMBER_UART_PID2: wb_rdata32 <= 32'h04;
AMBER_UART_PID3: wb_rdata32 <= 32'h00;
AMBER_UART_DR: // Rx data
if ( fifo_enable )
wb_rdata32 <= {24'd0, rx_fifo[rx_fifo_rp[3:0]]};
else
wb_rdata32 <= {24'd0, rx_fifo[0]};
AMBER_UART_RSR: wb_rdata32 <= uart_rsr_reg; // Receive status, (Write) Error Clear
AMBER_UART_LCRH: wb_rdata32 <= uart_lcrh_reg; // Line Control High Byte
AMBER_UART_LCRM: wb_rdata32 <= uart_lcrm_reg; // Line Control Middle Byte
AMBER_UART_LCRL: wb_rdata32 <= uart_lcrl_reg; // Line Control Low Byte
AMBER_UART_CR: wb_rdata32 <= uart_cr_reg; // Control Register
// UART Tx/Rx Status
AMBER_UART_FR: wb_rdata32 <= {tx_fifo_empty, // tx fifo empty
rx_fifo_full, // rx fifo full
tx_fifo_full, // tx fifo full
rx_fifo_empty, // rx fifo empty
!tx_fifo_empty, // uart busy
1'd1, // !Data Carrier Detect
1'd1, // !Data Set Ready
!uart0_cts_n_d[3] // !Clear to Send
}; // Flag Register
// Interrupt Status
AMBER_UART_IIR: wb_rdata32 <= {5'd0,
1'd0, // RTIS - receive timeout interrupt
tx_interrupt, // TIS - transmit interrupt status
rx_interrupt, // RIS - receive interrupt status
1'd0 // Modem interrupt status
}; // (Write) Clear Int
default: wb_rdata32 <= 32'h00c0ffee;
endcase
// =======================================================================================
// =======================================================================================
// =======================================================================================
// Non-synthesizable debug code
// =======================================================================================
//synopsys translate_off
// ========================================================
// Report UART Register accesses
// ========================================================
`ifndef Veritak
// Check in case UART approximate period
// is too far off
initial
begin
if ((( TX_BITPULSE_COUNT * CLK_PERIOD ) > (UART_BIT_PERIOD * 1.03) ) ||
(( TX_BITPULSE_COUNT * CLK_PERIOD ) < (UART_BIT_PERIOD * 0.97) ) )
begin
`TB_ERROR_MESSAGE
$display("UART TX bit period, %.1f, is too big. UART will not work!", TX_BITPULSE_COUNT * CLK_PERIOD);
$display("Baud rate is %f, and baud bit period is %.1f", UART_BAUD, UART_BIT_PERIOD);
$display("Either reduce the baud rate, or increase the system clock frequency");
$display("------");
end
end
`endif
`ifdef AMBER_UART_DEBUG
wire wb_read_ack;
reg uart0_rx_int_d1 = 'd0;
assign wb_read_ack = i_wb_stb && !i_wb_we && o_wb_ack;
`ifndef Veritak
initial
begin
$display("%m UART period = %f nS, want %f nS, %d, %d",
(TX_BITPULSE_COUNT*11 + TX_BITADJUST_COUNT) * CLK_PERIOD,
UART_WORD_PERIOD,
TX_BITPULSE_COUNT, TX_BITADJUST_COUNT);
end
`endif
// Transmit Interrupts
always @ ( posedge i_clk )
if ( wb_start_write && i_wb_adr[15:0] == AMBER_UART_ICR )
;
else if ( fifo_enable )
begin
if (tx_interrupt == 1'd0 && tx_fifo_half_or_less_full && uart_cr_reg[5])
$display("%m: tx_interrupt Interrupt Set with FIFO enabled");
if (tx_interrupt == 1'd1 && !(tx_fifo_half_or_less_full && uart_cr_reg[5]))
$display("%m: tx_interrupt Interrupt Cleared with FIFO enabled");
end
else
begin
if (tx_interrupt == 1'd0 && tx_fifo_empty && uart_cr_reg[5])
$display("%m: tx_interrupt Interrupt Set with FIFO disabled");
if (tx_interrupt == 1'd1 && !(tx_fifo_empty && uart_cr_reg[5]))
$display("%m: tx_interrupt Interrupt Cleared with FIFO disabled");
end
// Receive Interrupts
always @ ( posedge i_clk )
begin
uart0_rx_int_d1 <= rx_interrupt;
if ( rx_interrupt && !uart0_rx_int_d1 )
begin
`TB_DEBUG_MESSAGE
$display("rx_interrupt Interrupt fifo_enable %d, rx_fifo_full %d",
fifo_enable, rx_fifo_full);
$display("rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
end
if ( !rx_interrupt && uart0_rx_int_d1 )
begin
`TB_DEBUG_MESSAGE
$display("rx_interrupt Interrupt Cleared fifo_enable %d, rx_fifo_full %d",
fifo_enable, rx_fifo_full);
$display(" rx_fifo_half_or_more %d, rx_int_timer 0x%08h, rx_fifo_count %d",
rx_fifo_half_or_more, rx_int_timer, rx_fifo_count);
end
end
always @( posedge i_clk )
if ( wb_read_ack || wb_start_write )
begin
`TB_DEBUG_MESSAGE
if ( wb_start_write )
$write("Write 0x%08x to ", wb_wdata32);
else
$write("Read 0x%08x from ", o_wb_dat);
case ( i_wb_adr[15:0] )
AMBER_UART_PID0: $write("UART PID0 register");
AMBER_UART_PID1: $write("UART PID1 register");
AMBER_UART_PID2: $write("UART PID2 register");
AMBER_UART_PID3: $write("UART PID3 register");
AMBER_UART_CID0: $write("UART CID0 register");
AMBER_UART_CID1: $write("UART CID1 register");
AMBER_UART_CID2: $write("UART CID2 register");
AMBER_UART_CID3: $write("UART CID3 register");
AMBER_UART_DR: $write("UART Tx/Rx char %c", wb_start_write ? wb_wdata32[7:0] : o_wb_dat[7:0] );
AMBER_UART_RSR: $write("UART (Read) Receive status, (Write) Error Clear");
AMBER_UART_LCRH: $write("UART Line Control High Byte");
AMBER_UART_LCRM: $write("UART Line Control Middle Byte");
AMBER_UART_LCRL: $write("UART Line Control Low Byte");
AMBER_UART_CR: $write("UART Control Register");
AMBER_UART_FR: $write("UART Flag Register");
AMBER_UART_IIR: $write("UART (Read) Interrupt Identification Register");
default:
begin
`TB_ERROR_MESSAGE
$write("Unknown UART Register region");
end
endcase
$write(", Address 0x%08h\n", i_wb_adr);
end
`endif
// ========================================================
// Assertions
// ========================================================
always @ ( posedge i_clk )
begin
if ( rx_fifo_pop && !rx_fifo_push && rx_fifo_empty )
begin
`TB_WARNING_MESSAGE
$write("UART rx FIFO underflow\n");
end
if ( !rx_fifo_pop && rx_fifo_push && rx_fifo_full )
begin
`TB_WARNING_MESSAGE
$write("UART rx FIFO overflow\n");
end
if ( tx_fifo_push && tx_fifo_full )
begin
`TB_WARNING_MESSAGE
$display("UART tx FIFO overflow - char = %c", wb_wdata32[7:0]);
end
end
// ========================================================
// Debug State Machines
// ========================================================
wire [(10*8)-1:0] xTXD_STATE;
wire [(14*8)-1:0] xRXD_STATE;
assign xTXD_STATE = txd_state == TXD_IDLE ? "TXD_IDLE" :
txd_state == TXD_START ? "TXD_START" :
txd_state == TXD_DATA0 ? "TXD_DATA0" :
txd_state == TXD_DATA1 ? "TXD_DATA1" :
txd_state == TXD_DATA2 ? "TXD_DATA2" :
txd_state == TXD_DATA3 ? "TXD_DATA3" :
txd_state == TXD_DATA4 ? "TXD_DATA4" :
txd_state == TXD_DATA5 ? "TXD_DATA5" :
txd_state == TXD_DATA6 ? "TXD_DATA6" :
txd_state == TXD_DATA7 ? "TXD_DATA7" :
txd_state == TXD_STOP1 ? "TXD_STOP1" :
txd_state == TXD_STOP2 ? "TXD_STOP2" :
txd_state == TXD_STOP3 ? "TXD_STOP3" :
"UNKNOWN" ;
assign xRXD_STATE = rxd_state == RXD_IDLE ? "RXD_IDLE" :
rxd_state == RXD_START ? "RXD_START" :
rxd_state == RXD_START_MID1 ? "RXD_START_MID1":
rxd_state == RXD_START_MID ? "RXD_START_MID" :
rxd_state == RXD_DATA0 ? "RXD_DATA0" :
rxd_state == RXD_DATA1 ? "RXD_DATA1" :
rxd_state == RXD_DATA2 ? "RXD_DATA2" :
rxd_state == RXD_DATA3 ? "RXD_DATA3" :
rxd_state == RXD_DATA4 ? "RXD_DATA4" :
rxd_state == RXD_DATA5 ? "RXD_DATA5" :
rxd_state == RXD_DATA6 ? "RXD_DATA6" :
rxd_state == RXD_DATA7 ? "RXD_DATA7" :
rxd_state == RXD_STOP ? "RXD_STOP" :
"UNKNOWN" ;
//synopsys translate_on
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description: Phy layer SD host controller for 1 bit SD mode
* When the i_data_en signal goes high the core will read in the
* i_write_flag.
* Writing:
* If high then it will read in the i_data_h2s data until
* it reads i_data_count bytes from the host, each i_data_stb will tell
* the above phy to present a new byte to on the i_data_h2s register.
*
* Reading:
* read the number of bytes on i_data_count. when a new byte is finished
* the new byte will be on o_data_s2h.
*
* To activate a transaction set i_en along with i_write_flag to 1 for write
* or 0 for read, the core will strobe in/out data on it's own, it's
* up to the above layer to make sure there is enough data or space
* available, the maximum space should be 2048 bytes. when a transaction is
* finished the o_finished flag will go high, the controlling core must
* de-assert i_en in order to reset the core to get ready for new
* transactions. This signal will go high for one clock cycle if the host
* de-asserts i_en before a transaction is finished.
*
* clk: sdio_clk
* rst: reset core
* i_en: Enable a data transaction
* o_finished: transaction is finished (de-assert i_en to reset)
* i_write_flag: 1 = Write, 0 = Read
* i_data_h2s: Data from host to SD card
* o_data_h2s: Data from SD card to host
* i_data_count: Number of bytes to read/write
* o_data_stb: request or strobe in a byte
* o_crc_err: CRC error occured during read
* io_sd_data: raw sdio data bits
*
* Changes:
* 2015.08.24: Initial commit
*/
module sd_sd1_phy (
input clk,
input rst,
input i_en,
output reg o_finished,
input i_write_flag,
output reg o_crc_err, //Detected a CRC error during read
output reg o_data_stb,
input [11:0] i_data_count,
input [7:0] i_data_h2s,
output reg [7:0] o_data_s2h,
inout [7:0] io_sd_data
);
//local parameters
localparam IDLE = 4'h0;
localparam WRITE_START = 4'h1;
localparam WRITE = 4'h2;
localparam WRITE_CRC = 4'h3;
localparam WRITE_FINISHED= 4'h4;
localparam READ_START = 4'h5;
localparam READ = 4'h6;
localparam READ_CRC = 4'h7;
localparam FINISHED = 4'h8;
//registes/wires
reg [3:0] state;
reg [7:0] sd_data;
wire sd_data_bit;
wire [15:0] gen_crc;
reg [15:0] crc;
reg crc_rst;
reg [3:0] bit_count; //Need 4 bits to cound the CRC value
wire sd_bit;
reg r_sd_bit;
//submodules
sd_crc_16 (
.clk (clk ),
.rst (crc_rst ),
.en (crc_en ),
//.bitval (r_sd_bit ), //Shoud this be registered?
.bitval (sd_bit ),
.crc (gen_crc )
);
//asynchronous logic
assign sd_data_bit = (state == WRITE_START) ? 1'b0 :
(state == WRITE_CRC) ? crc[15] :
(state == WRITE_FINISHED) ? 1'b1 :
sd_data[7];
assign io_sd_data = (i_write_flag) ? {7'b0, sd_data_bit}, 8'hZZ;
assign sd_bit = io_sd_data[0];
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_data_stb <= 0;
if (rst) begin
sd_data <= 0;
state <= IDLE;
crc_rst <= 1;
crc_en <= 0;
o_finished <= 0;
bit_count <= 0;
data_count <= 0;
o_crc_err <= 0;
end
else begin
case (state)
IDLE: begin
crc_en <= 0;
crc_rst <= 1;
o_finished <= 0;
bit_count <= 0;
data_count <= 0;
o_crc_err <= 0;
if (i_en) begin
crc_rst <= 0;
if(i_write_flag) begin
state <= WRITE_START;
end
else begin
state <= READ_START;
end
end
end
WRITE_START: begin
//Set the data bit low to initiate a transaction
//The assignment statement above will take care of setting data bit to 0
state <= WRITE;
crc_en <= 1;
sd_data <= i_data_h2s;
end
WRITE: begin
sd_data <= {sd_data[6:0], 0};
bit_count <= bit_count + 1;
if (bit_count >= 7) begin
if (data_count < i_data_count) begin
o_data_stb <= 1;
bit_count <= 0;
data_count <= data_count + 1;
sd_data <= i_data_h2s;
end
else begin
state <= WRITE_CRC;
crc_en <= 0;
crc <= gen_crc;
end
end
end
WRITE_CRC: begin
crc <= {crc[14:0], sd_bit};
bit_count <= bit_count + 1;
if (bit_count >= 15) begin
state <= WRITE_FINISHED;
end
end
WRITE_FINISHED: begin
//Pass through, assign statement will set the value to 1
state <= FINISHED;
end
READ_START: begin
//Wait for data bit to go low
if (!sd_bit) begin
crc_en <= 1;
state <= READ;
end
end
READ: begin
//Shift the bits in
o_data_s2h <= {o_data_sh[6:0], sd_bit};
bit_count <= bit_count + bit_count + 8'h1;
if (bit_count >= 7) begin
//Finished reading a byte
o_data_stb <= 1; //Will this give me enough time for the new data to get clocked in?
bit_count <= 0;
if (data_count < i_data_count) begin
data_count <= data_count + 1;
end
else begin
//Finished reading all bytes
state <= READ_CRC;
end
end
end
READ_CRC: begin
crc_en <= 0; //XXX: should this be in the previous state??
crc <= {crc[14:0], sd_bit};
if (bit_count >= 15) begin
state <= FINISHED;
end
end
FINISHED: begin
o_finished <= 1;
if (crc != gen_crc) begin
o_crc_err <= 1;
end
if (!i_en) begin
o_finished <= 0;
state <= IDLE;
end
end
default: begin
end
endcase
r_sd_bt <= sd_bit;
end
end
endmodule
|
`timescale 1ns/1ps
module axi_master_wr #(
parameter ID_WIDTH = 2,
parameter ADDR_WIDTH = 64,
parameter DATA_WIDTH = 512,
parameter AWUSER_WIDTH = 8,
parameter ARUSER_WIDTH = 8,
parameter WUSER_WIDTH = 1,
parameter RUSER_WIDTH = 1,
parameter BUSER_WIDTH = 1
)
(
input clk ,
input rst_n ,
input clear ,
input [031:0] i_snap_context,
//---- AXI bus ----
// AXI write address channel
output [ID_WIDTH - 1:0] m_axi_awid ,
output reg[ADDR_WIDTH - 1:0] m_axi_awaddr ,
output reg[007:0] m_axi_awlen ,
output [002:0] m_axi_awsize ,
output [001:0] m_axi_awburst ,
output [003:0] m_axi_awcache ,
output [001:0] m_axi_awlock ,
output [002:0] m_axi_awprot ,
output [003:0] m_axi_awqos ,
output [003:0] m_axi_awregion,
output [AWUSER_WIDTH - 1:0] m_axi_awuser ,
output reg m_axi_awvalid ,
input m_axi_awready ,
// AXI write data channel
output [ID_WIDTH - 1:0] m_axi_wid ,
output [DATA_WIDTH - 1:0] m_axi_wdata ,
output [(DATA_WIDTH/8) - 1:0] m_axi_wstrb ,
output reg m_axi_wlast ,
output reg m_axi_wvalid ,
input m_axi_wready ,
// AXI write response channel
output m_axi_bready ,
input [ID_WIDTH - 1:0] m_axi_bid ,
input [001:0] m_axi_bresp ,
input m_axi_bvalid ,
//---- local bus ----
output lcl_ibusy ,
input lcl_istart ,
input [ADDR_WIDTH - 1:0] lcl_iaddr ,
input [007:0] lcl_inum ,
output lcl_irdy ,
input lcl_den ,
input [DATA_WIDTH - 1:0] lcl_din ,
input lcl_idone ,
//---- status report ----
output [005:0] status ,
output [003:0] error
);
//---- declarations ----
wire fifo_wrbuf_rdrq;
wire fifo_wrbuf_olast;
wire fifo_wrbuf_ordy;
wire fifo_wrbuf_flush;
wire fifo_wrbuf_empty;
reg read_wrbuf_enable;
reg [001:0] wr_error;
wire fifo_wrbuf_overflow,fifo_wrbuf_underflow;
reg wrovfl, wrudfl;
reg ibusy;
//---- signals for AXI advanced features ----
assign m_axi_awid = 20'd0;
assign m_axi_wid = 20'd0;
assign m_axi_awsize = 3'd6; // 2^6=512
assign m_axi_awburst = 2'd1; // INCR mode for memory access
assign m_axi_awcache = 4'd3; // Normal Non-cacheable Bufferable
assign m_axi_awuser = i_snap_context[AWUSER_WIDTH - 1:0];
assign m_axi_awprot = 3'd0;
assign m_axi_awqos = 4'd0;
assign m_axi_awregion = 4'd0; //?
assign m_axi_wstrb = 64'hffff_ffff_ffff_ffff;
assign m_axi_awlock = 2'b00; // normal access
/***********************************************************************
* writing channel *
***********************************************************************/
//---- AXI writing valid, address and burst length ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_awvalid <= 1'b0;
else if(lcl_istart & ~lcl_ibusy)
m_axi_awvalid <= 1'b1;
else if(m_axi_awready)
m_axi_awvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
m_axi_awlen <= 8'b0;
m_axi_awaddr <= 64'b0;
end
else if(lcl_istart)
begin
m_axi_awlen <= lcl_inum - 8'd1;
m_axi_awaddr <= lcl_iaddr;
end
//---- writing FIFO, regular, local -> AXI master ----
fifo_axi_lcl maxi_wrbuf(
.clk (clk ),
.rst_n(rst_n ),
.clr (clear ),
.ovfl (fifo_wrbuf_overflow ),
.udfl (fifo_wrbuf_underflow),
.iend (lcl_idone ), //synced with,or after the last input data
.irdy (lcl_irdy ), //stop asserting den when irdy is 0, but with margin
.den (lcl_den ),
.din (lcl_din ),
.rdrq (fifo_wrbuf_rdrq ), //MUST be deasserted when olast is 1
.olast(fifo_wrbuf_olast ), //synced with the last output data
.ordy (fifo_wrbuf_ordy ), //stop asserting rdrq when ordy is 0, but with margin
.dout (m_axi_wdata ),
.dv (),
.empty(fifo_wrbuf_empty ),
.flush(fifo_wrbuf_flush )
);
//---- fifo writing enable window ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
read_wrbuf_enable <= 1'd0;
else if(fifo_wrbuf_olast) // deasserts at the last reading request
read_wrbuf_enable <= 1'd0;
else
read_wrbuf_enable <= fifo_wrbuf_ordy;
//---- request reading FIFO when 1) during reading progress; 2) FIFO data ready; 3) AXI slave ready or AXI master doses off ----
assign fifo_wrbuf_rdrq = read_wrbuf_enable & (m_axi_wready | (~m_axi_wready & ~m_axi_wvalid));
//---- AXI master wvalid ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_wvalid <= 1'b0;
else if(fifo_wrbuf_rdrq) // one cycle after read request
m_axi_wvalid <= 1'b1;
else if(m_axi_wready) // 1) during reading: FIFO dout not ready; 2) outside reading: the last data sending to slave
m_axi_wvalid <= 1'b0;
//---- AXI master last valid write data, must be synced with both wready and wvalid ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_wlast <= 1'd0;
else if(fifo_wrbuf_olast)
m_axi_wlast <= 1'd1;
else if(m_axi_wready)
m_axi_wlast <= 1'd0;
//---- local write request should be silent when this busy signal asserts, otherwise will be ignored ----
// to lcl_istart: should only be asserted after the last burst is read out of the fifo
always@(posedge clk or negedge rst_n)
if(~rst_n)
ibusy <= 1'b0;
else if(lcl_istart)
ibusy <= 1'b1;
else if(fifo_wrbuf_olast)
ibusy <= 1'b0;
assign lcl_ibusy = ibusy;
/***********************************************************************
* status gathering and report *
***********************************************************************/
//---- status report ----
assign status = {
fifo_wrbuf_flush, // b[5]
fifo_wrbuf_empty, // b[4]
wrovfl, // b[3]
wrudfl, // b[2]
wr_error // b[1:0]
};
assign error = {
wrovfl,
wrudfl,
wr_error};
//---- axi write response capture ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
wr_error <= 2'b0;
else if(m_axi_bvalid & m_axi_bready & (m_axi_bresp != 2'b0))
wr_error <= m_axi_bresp;
assign m_axi_bready = 1'b1;
//---- FIFO error capture ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
{wrovfl,wrudfl} <= 4'b0;
else if(clear)
{wrovfl,wrudfl} <= 4'b0;
else
case({fifo_wrbuf_overflow,fifo_wrbuf_underflow})
2'b01: {wrovfl,wrudfl} <= {wrovfl,1'b1};
2'b10: {wrovfl,wrudfl} <= {1'b1,wrudfl};
default:;
endcase
endmodule
|
// Copyright 2007 Altera Corporation. All rights reserved.
// Altera products are protected under numerous U.S. and foreign patents,
// maskwork rights, copyrights and other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed
// by the terms and conditions of the applicable Altera Reference Design
// License Agreement (either as signed by you or found at www.altera.com). By
// using this reference design file, you indicate your acceptance of such terms
// and conditions between you and Altera Corporation. In the event that you do
// not agree with such terms and conditions, you may not use the reference
// design file and please promptly destroy any copies you have made.
//
// This reference design file is being provided on an "as-is" basis and as an
// accommodation and therefore all warranties, representations or guarantees of
// any kind (whether express, implied or statutory) including, without
// limitation, warranties of merchantability, non-infringement, or fitness for
// a particular purpose, are specifically disclaimed. By making this reference
// design file available, Altera expressly does not recommend, suggest or
// require that this reference design file be used in combination with any
// other product not provided by Altera.
/////////////////////////////////////////////////////////////////////////////
// baeckler - 05-13-2005
//
// Six input three output compressor (non-carry adder)
//
// Maps to 3 Stratix II six luts. Use optimize = speed
//
module six_three_comp (data,sum);
input [5:0] data;
output [2:0] sum;
reg [2:0] sum /* synthesis keep */;
always @(data) begin
case (data)
0: sum=0;
1: sum=1;
2: sum=1;
3: sum=2;
4: sum=1;
5: sum=2;
6: sum=2;
7: sum=3;
8: sum=1;
9: sum=2;
10: sum=2;
11: sum=3;
12: sum=2;
13: sum=3;
14: sum=3;
15: sum=4;
16: sum=1;
17: sum=2;
18: sum=2;
19: sum=3;
20: sum=2;
21: sum=3;
22: sum=3;
23: sum=4;
24: sum=2;
25: sum=3;
26: sum=3;
27: sum=4;
28: sum=3;
29: sum=4;
30: sum=4;
31: sum=5;
32: sum=1;
33: sum=2;
34: sum=2;
35: sum=3;
36: sum=2;
37: sum=3;
38: sum=3;
39: sum=4;
40: sum=2;
41: sum=3;
42: sum=3;
43: sum=4;
44: sum=3;
45: sum=4;
46: sum=4;
47: sum=5;
48: sum=2;
49: sum=3;
50: sum=3;
51: sum=4;
52: sum=3;
53: sum=4;
54: sum=4;
55: sum=5;
56: sum=3;
57: sum=4;
58: sum=4;
59: sum=5;
60: sum=4;
61: sum=5;
62: sum=5;
63: sum=6;
default: sum=0;
endcase
end
endmodule
|
/* salsa_slowsixteen.v
*
* Copyright (c) 2013 kramble
* Derived from scrypt.c Copyright 2009 Colin Percival, 2011 ArtForz
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
module salsa (clk, B, Bx, Bo, X0out, Xaddr);
// Latency 16 clock cycles, approx 20nS propagation delay (SLOW!)
input clk;
// input feedback;
input [511:0]B;
input [511:0]Bx;
// output reg [511:0]Bo; // Output is registered
output [511:0]Bo; // Output is async
output [511:0]X0out; // Becomes new X0
output [9:0] Xaddr;
wire [9:0] xa1, xa2, xa3, xa4, ya1, ya2, ya3, ya4;
reg [511:0]x1d1, x1d1a;
reg [511:0]x1d2, x1d2a;
reg [511:0]x1d3, x1d3a;
reg [511:0]x1d4, x1d4a;
reg [511:0]Xod1, Xod1a;
reg [511:0]Xod2, Xod2a;
reg [511:0]Xod3, Xod3a;
reg [511:0]Xod4, X0out;
reg [511:0]xxd1, xxd1a;
reg [511:0]xxd2, xxd2a;
reg [511:0]xxd3, xxd3a;
reg [511:0]xxd4, xxd4a;
reg [511:0]yyd1, yyd1a;
reg [511:0]yyd2, yyd2a;
reg [511:0]yyd3, yyd3a;
reg [511:0]yyd4, yyd4a;
wire [511:0]xx; // Initial xor
wire [511:0]x1; // Salasa core outputs
wire [511:0]x2;
wire [511:0]x3;
wire [511:0]xr;
wire [511:0]Xo;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsax1 (clk, xx, x1, xa1);
salsa_core salsax2 (clk, x1, x2, xa2);
salsa_core salsax3 (clk, x2, x3, xa3);
salsa_core salsax4 (clk, x3, xr, xa4);
wire [511:0]yy; // Initial xor
wire [511:0]y1; // Salasa core outputs
wire [511:0]y2;
wire [511:0]y3;
wire [511:0]yr;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsay1 (clk, yy, y1, ya1);
salsa_core salsay2 (clk, y1, y2, ya2);
salsa_core salsay3 (clk, y2, y3, ya3);
salsa_core salsay4 (clk, y3, yr, ya4);
assign Xaddr = yyd4[9:0] + ya4;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
// Initial XOR. NB this adds to the propagation delay of the first salsa, may want register it.
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign Xo[`IDX(i)] = xxd4a[`IDX(i)] + xr[`IDX(i)];
assign yy[`IDX(i)] = x1d4a[`IDX(i)] ^ Xo[`IDX(i)];
assign Bo[`IDX(i)] = yyd4a[`IDX(i)] + yr[`IDX(i)]; // Async output
end
endgenerate
always @ (posedge clk)
begin
x1d1 <= Bx;
x1d1a <= x1d1;
x1d2 <= x1d1a;
x1d2a <= x1d2;
x1d3 <= x1d2a;
x1d3a <= x1d3;
x1d4 <= x1d3a;
x1d4a <= x1d4;
Xod1 <= Xo;
Xod1a <= Xod1;
Xod2 <= Xod1a;
Xod2a <= Xod2;
Xod3 <= Xod2a;
Xod3a <= Xod3;
Xod4 <= Xod3a;
X0out <= Xod4; // We output this to become new X0
xxd1 <= xx;
xxd1a <= xxd1;
xxd2 <= xxd1a;
xxd2a <= xxd2;
xxd3 <= xxd2a;
xxd3a <= xxd3;
xxd4 <= xxd3a;
xxd4a <= xxd4;
yyd1 <= yy;
yyd1a <= yyd1;
yyd2 <= yyd1a;
yyd2a <= yyd2;
yyd3 <= yyd2a;
yyd3a <= yyd3;
yyd4 <= yyd3a;
yyd4a <= yyd4;
end
endmodule
module salsa_core (clk, xx, out, Xaddr);
input clk;
input [511:0]xx;
output reg [511:0]out; // Output is registered
output [9:0] Xaddr; // Address output unregistered
// This is clunky due to my lack of verilog skills but it works so elegance can come later
wire [31:0]c00; // Column results
wire [31:0]c01;
wire [31:0]c02;
wire [31:0]c03;
wire [31:0]c04;
wire [31:0]c05;
wire [31:0]c06;
wire [31:0]c07;
wire [31:0]c08;
wire [31:0]c09;
wire [31:0]c10;
wire [31:0]c11;
wire [31:0]c12;
wire [31:0]c13;
wire [31:0]c14;
wire [31:0]c15;
wire [31:0]r00; // Row results
wire [31:0]r01;
wire [31:0]r02;
wire [31:0]r03;
wire [31:0]r04;
wire [31:0]r05;
wire [31:0]r06;
wire [31:0]r07;
wire [31:0]r08;
wire [31:0]r09;
wire [31:0]r10;
wire [31:0]r11;
wire [31:0]r12;
wire [31:0]r13;
wire [31:0]r14;
wire [31:0]r15;
wire [31:0]c00s; // Column sums
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s; // Row sums
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
reg [31:0]c00d; // Column results registered
reg [31:0]c01d;
reg [31:0]c02d;
reg [31:0]c03d;
reg [31:0]c04d;
reg [31:0]c05d;
reg [31:0]c06d;
reg [31:0]c07d;
reg [31:0]c08d;
reg [31:0]c09d;
reg [31:0]c10d;
reg [31:0]c11d;
reg [31:0]c12d;
reg [31:0]c13d;
reg [31:0]c14d;
reg [31:0]c15d;
/* From scrypt.c
#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
for (i = 0; i < 8; i += 2) {
// Operate on columns
x04 ^= R(x00+x12, 7); x09 ^= R(x05+x01, 7); x14 ^= R(x10+x06, 7); x03 ^= R(x15+x11, 7);
x08 ^= R(x04+x00, 9); x13 ^= R(x09+x05, 9); x02 ^= R(x14+x10, 9); x07 ^= R(x03+x15, 9);
x12 ^= R(x08+x04,13); x01 ^= R(x13+x09,13); x06 ^= R(x02+x14,13); x11 ^= R(x07+x03,13);
x00 ^= R(x12+x08,18); x05 ^= R(x01+x13,18); x10 ^= R(x06+x02,18); x15 ^= R(x11+x07,18);
// Operate on rows
x01 ^= R(x00+x03, 7); x06 ^= R(x05+x04, 7); x11 ^= R(x10+x09, 7); x12 ^= R(x15+x14, 7);
x02 ^= R(x01+x00, 9); x07 ^= R(x06+x05, 9); x08 ^= R(x11+x10, 9); x13 ^= R(x12+x15, 9);
x03 ^= R(x02+x01,13); x04 ^= R(x07+x06,13); x09 ^= R(x08+x11,13); x14 ^= R(x13+x12,13);
x00 ^= R(x03+x02,18); x05 ^= R(x04+x07,18); x10 ^= R(x09+x08,18); x15 ^= R(x14+x13,18);
}
*/
// cols
assign c04s = xx[`IDX(0)] + xx[`IDX(12)];
assign c04 = xx[`IDX(4)] ^ { c04s[24:0], c04s[31:25] };
assign c09s = xx[`IDX(5)] + xx[`IDX(1)];
assign c09 = xx[`IDX(9)] ^ { c09s[24:0], c09s[31:25] };
assign c14s = xx[`IDX(10)] + xx[`IDX(6)];
assign c14 = xx[`IDX(14)] ^ { c14s[24:0], c14s[31:25] };
assign c03s = xx[`IDX(15)] + xx[`IDX(11)];
assign c03 = xx[`IDX(03)] ^ { c03s[24:0], c03s[31:25] };
assign c08s = c04 + xx[`IDX(0)];
assign c08 = xx[`IDX(8)] ^ { c08s[22:0], c08s[31:23] };
assign c13s = c09 + xx[`IDX(5)];
assign c13 = xx[`IDX(13)] ^ { c13s[22:0], c13s[31:23] };
assign c02s = c14 + xx[`IDX(10)];
assign c02 = xx[`IDX(2)] ^ { c02s[22:0], c02s[31:23] };
assign c07s = c03 + xx[`IDX(15)];
assign c07 = xx[`IDX(7)] ^ { c07s[22:0], c07s[31:23] };
assign c12s = c08 + c04;
assign c12 = xx[`IDX(12)] ^ { c12s[18:0], c12s[31:19] };
assign c01s = c13 + c09;
assign c01 = xx[`IDX(1)] ^ { c01s[18:0], c01s[31:19] };
assign c06s = c02 + c14;
assign c06 = xx[`IDX(6)] ^ { c06s[18:0], c06s[31:19] };
assign c11s = c07 + c03;
assign c11 = xx[`IDX(11)] ^ { c11s[18:0], c11s[31:19] };
assign c00s = c12 + c08;
assign c00 = xx[`IDX(0)] ^ { c00s[13:0], c00s[31:14] };
assign c05s = c01 + c13;
assign c05 = xx[`IDX(5)] ^ { c05s[13:0], c05s[31:14] };
assign c10s = c06 + c02;
assign c10 = xx[`IDX(10)] ^ { c10s[13:0], c10s[31:14] };
assign c15s = c11 + c07;
assign c15 = xx[`IDX(15)] ^ { c15s[13:0], c15s[31:14] };
// rows
assign r01s = c00d + c03d;
assign r01 = c01d ^ { r01s[24:0], r01s[31:25] };
assign r06s = c05d + c04d;
assign r06 = c06d ^ { r06s[24:0], r06s[31:25] };
assign r11s = c10d + c09d;
assign r11 = c11d ^ { r11s[24:0], r11s[31:25] };
assign r12s = c15d + c14d;
assign r12 = c12d ^ { r12s[24:0], r12s[31:25] };
assign r02s = r01 + c00d;
assign r02 = c02d ^ { r02s[22:0], r02s[31:23] };
assign r07s = r06 + c05d;
assign r07 = c07d ^ { r07s[22:0], r07s[31:23] };
assign r08s = r11 + c10d;
assign r08 = c08d ^ { r08s[22:0], r08s[31:23] };
assign r13s = r12 + c15d;
assign r13 = c13d ^ { r13s[22:0], r13s[31:23] };
assign r03s = r02 + r01;
assign r03 = c03d ^ { r03s[18:0], r03s[31:19] };
assign r04s = r07 + r06;
assign r04 = c04d ^ { r04s[18:0], r04s[31:19] };
assign r09s = r08 + r11;
assign r09 = c09d ^ { r09s[18:0], r09s[31:19] };
assign r14s = r13 + r12;
assign r14 = c14d ^ { r14s[18:0], r14s[31:19] };
assign r00s = r03 + r02;
assign r00 = c00d ^ { r00s[13:0], r00s[31:14] };
assign r05s = r04 + r07;
assign r05 = c05d ^ { r05s[13:0], r05s[31:14] };
assign r10s = r09 + r08;
assign r10 = c10d ^ { r10s[13:0], r10s[31:14] };
assign r15s = r14 + r13;
assign r15 = c15d ^ { r15s[13:0], r15s[31:14] };
wire [511:0]xo; // Rename row results
assign xo = { r15, r14, r13, r12, r11, r10, r09, r08, r07, r06, r05, r04, r03, r02, r01, r00 };
assign Xaddr = xo[9:0]; // Unregistered output
always @ (posedge clk)
begin
c00d <= c00;
c01d <= c01;
c02d <= c02;
c03d <= c03;
c04d <= c04;
c05d <= c05;
c06d <= c06;
c07d <= c07;
c08d <= c08;
c09d <= c09;
c10d <= c10;
c11d <= c11;
c12d <= c12;
c13d <= c13;
c14d <= c14;
c15d <= c15;
out <= xo; // Registered output
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : rank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
//*****************************************************************************
// This block is responsible for managing various rank level timing
// parameters. For now, only Four Activate Window (FAW) and Write
// To Read delay are implemented here.
//
// Each rank machine generates its own inhbt_act_faw_r and inhbt_rd.
// These per rank machines are driven into the bank machines. Each
// bank machines selects the correct inhibits based on the rank
// of its current request.
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_9_rank_cntrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter BURST_MODE = "8", // Burst length
parameter DQRD2DQWR_DLY = 2, // RD->WR DQ Bus Delay
parameter CL = 5, // Read CAS latency
parameter CWL = 5, // Write CAS latency
parameter ID = 0, // Unique ID for each instance
parameter nBANK_MACHS = 4, // # bank machines in MC
parameter nCK_PER_CLK = 2, // DRAM clock : MC clock
parameter nFAW = 30, // four activate window (CKs)
parameter nREFRESH_BANK = 8, // # REF commands to pull-in
parameter nRRD = 4, // ACT->ACT period (CKs)
parameter nWTR = 4, // Internal write->read
// delay (CKs)
parameter PERIODIC_RD_TIMER_DIV = 20, // Maintenance prescaler divisor
// for periodic read timer
parameter RANK_BM_BV_WIDTH = 16, // Width required to broadcast a
// single bit rank signal among
// all the bank machines
parameter RANK_WIDTH = 2, // # of bits to count ranks
parameter RANKS = 4, // # of ranks of DRAM
parameter REFRESH_TIMER_DIV = 39 // Maintenance prescaler divivor
// for refresh timer
)
(
// Maintenance requests
output periodic_rd_request,
output wire refresh_request,
// Inhibit signals
output reg inhbt_act_faw_r,
output reg inhbt_rd,
output reg inhbt_wr,
// System Inputs
input clk,
input rst,
// User maintenance requests
input app_periodic_rd_req,
input app_ref_req,
// Inputs
input [RANK_BM_BV_WIDTH-1:0] act_this_rank_r,
input clear_periodic_rd_request,
input col_rd_wr,
input init_calib_complete,
input insert_maint_r1,
input maint_prescaler_tick_r,
input [RANK_WIDTH-1:0] maint_rank_r,
input maint_zq_r,
input maint_sre_r,
input maint_srx_r,
input [(RANKS*nBANK_MACHS)-1:0] rank_busy_r,
input refresh_tick,
input [nBANK_MACHS-1:0] sending_col,
input [nBANK_MACHS-1:0] sending_row,
input [RANK_BM_BV_WIDTH-1:0] rd_this_rank_r,
input [RANK_BM_BV_WIDTH-1:0] wr_this_rank_r
);
//***************************************************************************
// RRD configuration. The bank machines have a mechanism to prevent RAS to
// RAS on adjacent fabric CLK states to the same rank. When
// nCK_PER_CLK == 1, this translates to a minimum of 2 for nRRD, 4 for nRRD
// when nCK_PER_CLK == 2 and 8 for nRRD when nCK_PER_CLK == 4. Some of the
// higher clock rate DDR3 DRAMs have nRRD > 4. The additional RRD inhibit
// is worked into the inhbt_faw signal.
//***************************************************************************
localparam nADD_RRD = nRRD -
(
(nCK_PER_CLK == 1) ? 2 :
(nCK_PER_CLK == 2) ? 4 :
/*(nCK_PER_CLK == 4)*/ 8
);
// divide by nCK_PER_CLK and add a cycle if there's a remainder
localparam nRRD_CLKS =
(nCK_PER_CLK == 1) ? nADD_RRD :
(nCK_PER_CLK == 2) ? ((nADD_RRD/2)+(nADD_RRD%2)) :
/*(nCK_PER_CLK == 4)*/ ((nADD_RRD/4)+((nADD_RRD%4) ? 1 : 0));
// take binary log to obtain counter width and add a tick for the idle cycle
localparam ADD_RRD_CNTR_WIDTH = clogb2(nRRD_CLKS + /* idle state */ 1);
//***************************************************************************
// Internal signals
//***************************************************************************
reg act_this_rank;
integer i; // loop invariant
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
//***************************************************************************
// Determine if this rank has been activated. act_this_rank_r is a
// registered bit vector from individual bank machines indicating the
// corresponding bank machine is sending
// an activate. Timing is improved with this method.
//***************************************************************************
always @(/*AS*/act_this_rank_r or sending_row) begin
act_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
act_this_rank =
act_this_rank || (sending_row[i] && act_this_rank_r[(i*RANKS)+ID]);
end
reg add_rrd_inhbt = 1'b0;
generate
if (nADD_RRD > 0 && ADD_RRD_CNTR_WIDTH > 1) begin :add_rdd1
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {{ADD_RRD_CNTR_WIDTH-1{1'b0}}, 1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd1
else if (nADD_RRD > 0) begin :add_rdd0
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_ns;
reg[ADD_RRD_CNTR_WIDTH-1:0] add_rrd_r;
always @(/*AS*/act_this_rank or add_rrd_r or rst) begin
add_rrd_ns = add_rrd_r;
if (rst) add_rrd_ns = {ADD_RRD_CNTR_WIDTH{1'b0}};
else
if (act_this_rank)
add_rrd_ns = nRRD_CLKS[0+:ADD_RRD_CNTR_WIDTH];
else if (|add_rrd_r) add_rrd_ns =
add_rrd_r - {1'b1};
end
always @(posedge clk) add_rrd_r <= #TCQ add_rrd_ns;
always @(/*AS*/add_rrd_ns) add_rrd_inhbt = |add_rrd_ns;
end // add_rdd0
endgenerate
// Compute inhbt_act_faw_r. Only allow a limited number of activates
// in a window. Both the number of activates and the window are
// configurable. This depends on the RRD mechanism to prevent
// two consecutive activates to the same rank.
//
// Subtract three from the specified nFAW. Subtract three because:
// -Zero for the delay into the SRL is really one state.
// -Sending_row is used to trigger the delay. Sending_row is one
// state delayed from the arb.
// -inhbt_act_faw_r is registered to make timing work, hence the
// generation needs to be one state early.
localparam nFAW_CLKS = (nCK_PER_CLK == 1)
? nFAW
: (nCK_PER_CLK == 2) ? ((nFAW/2) + (nFAW%2)) :
((nFAW/4) + ((nFAW%4) ? 1 : 0));
generate
begin : inhbt_act_faw
wire act_delayed;
wire [4:0] shift_depth = nFAW_CLKS[4:0] - 5'd3;
SRLC32E #(.INIT(32'h00000000) ) SRLC32E0
(.Q(act_delayed), // SRL data output
.Q31(), // SRL cascade output pin
.A(shift_depth), // 5-bit shift depth select input
.CE(1'b1), // Clock enable input
.CLK(clk), // Clock input
.D(act_this_rank) // SRL data input
);
reg [2:0] faw_cnt_ns;
reg [2:0] faw_cnt_r;
reg inhbt_act_faw_ns;
always @(/*AS*/act_delayed or act_this_rank or add_rrd_inhbt
or faw_cnt_r or rst) begin
if (rst) faw_cnt_ns = 3'b0;
else begin
faw_cnt_ns = faw_cnt_r;
if (act_this_rank) faw_cnt_ns = faw_cnt_r + 3'b1;
if (act_delayed) faw_cnt_ns = faw_cnt_ns - 3'b1;
end
inhbt_act_faw_ns = (faw_cnt_ns == 3'h4) || add_rrd_inhbt;
end
always @(posedge clk) faw_cnt_r <= #TCQ faw_cnt_ns;
always @(posedge clk) inhbt_act_faw_r <= #TCQ inhbt_act_faw_ns;
end // block: inhbt_act_faw
endgenerate
// In the DRAM spec, tWTR starts from CK following the end of the data
// burst. Since we don't directly have that spec, the wtr timer is
// based on when the CAS write command is sent to the DRAM.
//
// To compute the wtr timer value, first compute the time from the write command
// to the read command. This is CWL + data_time + nWTR.
//
// Two is subtracted from the required wtr time since the timer
// starts two states after the arbitration cycle.
localparam ONE = 1;
localparam TWO = 2;
localparam CASWR2CASRD = CWL + (BURST_MODE == "4" ? 2 : 4) + nWTR;
localparam CASWR2CASRD_CLKS = (nCK_PER_CLK == 1)
? CASWR2CASRD :
(nCK_PER_CLK == 2)
? ((CASWR2CASRD / 2) + (CASWR2CASRD % 2)) :
((CASWR2CASRD / 4) + ((CASWR2CASRD % 4) ? 1 :0));
localparam WTR_CNT_WIDTH = clogb2(CASWR2CASRD_CLKS);
generate
begin : wtr_timer
reg write_this_rank;
always @(/*AS*/sending_col or wr_this_rank_r) begin
write_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
write_this_rank =
write_this_rank || (sending_col[i] && wr_this_rank_r[(i*RANKS)+ID]);
end
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_r;
reg [WTR_CNT_WIDTH-1:0] wtr_cnt_ns;
always @(/*AS*/rst or write_this_rank or wtr_cnt_r)
if (rst) wtr_cnt_ns = {WTR_CNT_WIDTH{1'b0}};
else begin
wtr_cnt_ns = wtr_cnt_r;
if (write_this_rank) wtr_cnt_ns =
CASWR2CASRD_CLKS[WTR_CNT_WIDTH-1:0] - ONE[WTR_CNT_WIDTH-1:0];
else if (|wtr_cnt_r) wtr_cnt_ns = wtr_cnt_r - ONE[WTR_CNT_WIDTH-1:0];
end
wire inhbt_rd_ns = |wtr_cnt_ns;
always @(posedge clk) wtr_cnt_r <= #TCQ wtr_cnt_ns;
always @(inhbt_rd_ns) inhbt_rd = inhbt_rd_ns;
end
endgenerate
// In the DRAM spec (with AL = 0), the read-to-write command delay is implied to
// be CL + data_time + 2 tCK - CWL. The CL + data_time - CWL terms ensure the
// read and write data do not collide on the DQ bus. The 2 tCK ensures a gap
// between them. Here, we allow the user to tune this fixed term via the
// DQRD2DQWR_DLY parameter. There's a potential for optimization by relocating
// this to the rank_common module, since this is a DQ/DQS bus-level requirement,
// not a per-rank requirement.
localparam CASRD2CASWR = CL + (BURST_MODE == "4" ? 2 : 4) + DQRD2DQWR_DLY - CWL;
localparam CASRD2CASWR_CLKS = (nCK_PER_CLK == 1)
? CASRD2CASWR :
(nCK_PER_CLK == 2)
? ((CASRD2CASWR / 2) + (CASRD2CASWR % 2)) :
((CASRD2CASWR / 4) + ((CASRD2CASWR % 4) ? 1 :0));
localparam RTW_CNT_WIDTH = clogb2(CASRD2CASWR_CLKS);
generate
begin : rtw_timer
reg read_this_rank;
always @(/*AS*/sending_col or rd_this_rank_r) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_r;
reg [RTW_CNT_WIDTH-1:0] rtw_cnt_ns;
always @(/*AS*/rst or col_rd_wr or sending_col or rtw_cnt_r)
if (rst) rtw_cnt_ns = {RTW_CNT_WIDTH{1'b0}};
else begin
rtw_cnt_ns = rtw_cnt_r;
if (col_rd_wr && |sending_col) rtw_cnt_ns =
CASRD2CASWR_CLKS[RTW_CNT_WIDTH-1:0] - ONE[RTW_CNT_WIDTH-1:0];
else if (|rtw_cnt_r) rtw_cnt_ns = rtw_cnt_r - ONE[RTW_CNT_WIDTH-1:0];
end
wire inhbt_wr_ns = |rtw_cnt_ns;
always @(posedge clk) rtw_cnt_r <= #TCQ rtw_cnt_ns;
always @(inhbt_wr_ns) inhbt_wr = inhbt_wr_ns;
end
endgenerate
// Refresh request generation. Implement a "refresh bank". Referred
// to as pullin-in refresh in the JEDEC spec.
// The refresh_rank_r counter increments when a refresh to this
// rank has been decoded. In the up direction, the count saturates
// at nREFRESH_BANK. As specified in the JEDEC spec, nREFRESH_BANK
// is normally eight. The counter decrements with each refresh_tick,
// saturating at zero. A refresh will be requests when the rank is
// not busy and refresh_rank_r != nREFRESH_BANK, or refresh_rank_r
// equals zero.
localparam REFRESH_BANK_WIDTH = clogb2(nREFRESH_BANK + 1);
generate begin : refresh_generation
reg my_rank_busy;
always @(/*AS*/rank_busy_r) begin
my_rank_busy = 1'b0;
for (i=0; i < nBANK_MACHS; i=i+1)
my_rank_busy = my_rank_busy || rank_busy_r[(i*RANKS)+ID];
end
wire my_refresh =
insert_maint_r1 && ~maint_zq_r && ~maint_sre_r && ~maint_srx_r &&
(maint_rank_r == ID[RANK_WIDTH-1:0]);
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_r;
reg [REFRESH_BANK_WIDTH-1:0] refresh_bank_ns;
always @(/*AS*/app_ref_req or init_calib_complete or my_refresh
or refresh_bank_r or refresh_tick)
if (~init_calib_complete)
if (REFRESH_TIMER_DIV == 0)
refresh_bank_ns = nREFRESH_BANK[0+:REFRESH_BANK_WIDTH];
else refresh_bank_ns = {REFRESH_BANK_WIDTH{1'b0}};
else
case ({my_refresh, refresh_tick, app_ref_req})
3'b000, 3'b110, 3'b101, 3'b111 : refresh_bank_ns = refresh_bank_r;
3'b010, 3'b001, 3'b011 : refresh_bank_ns =
(|refresh_bank_r)?
refresh_bank_r - ONE[0+:REFRESH_BANK_WIDTH]:
refresh_bank_r;
3'b100 : refresh_bank_ns =
refresh_bank_r + ONE[0+:REFRESH_BANK_WIDTH];
endcase // case ({my_refresh, refresh_tick})
always @(posedge clk) refresh_bank_r <= #TCQ refresh_bank_ns;
`ifdef MC_SVA
refresh_bank_overflow: assert property (@(posedge clk)
(rst || (refresh_bank_r <= nREFRESH_BANK)));
refresh_bank_underflow: assert property (@(posedge clk)
(rst || ~(~|refresh_bank_r && ~my_refresh && refresh_tick)));
refresh_hi_priority: cover property (@(posedge clk)
(rst && ~|refresh_bank_ns && (refresh_bank_r ==
ONE[0+:REFRESH_BANK_WIDTH])));
refresh_bank_full: cover property (@(posedge clk)
(rst && (refresh_bank_r ==
nREFRESH_BANK[0+:REFRESH_BANK_WIDTH])));
`endif
assign refresh_request = init_calib_complete &&
(~|refresh_bank_r ||
((refresh_bank_r != nREFRESH_BANK[0+:REFRESH_BANK_WIDTH]) && ~my_rank_busy));
end
endgenerate
// Periodic read request generation.
localparam PERIODIC_RD_TIMER_WIDTH = clogb2(PERIODIC_RD_TIMER_DIV + /*idle state*/ 1);
generate begin : periodic_rd_generation
if ( PERIODIC_RD_TIMER_DIV != 0 ) begin // enable periodic reads
reg read_this_rank;
always @(/*AS*/rd_this_rank_r or sending_col) begin
read_this_rank = 1'b0;
for (i = 0; i < nBANK_MACHS; i = i + 1)
read_this_rank =
read_this_rank || (sending_col[i] && rd_this_rank_r[(i*RANKS)+ID]);
end
reg read_this_rank_r;
reg read_this_rank_r1;
always @(posedge clk) read_this_rank_r <= #TCQ read_this_rank;
always @(posedge clk) read_this_rank_r1 <= #TCQ read_this_rank_r;
wire int_read_this_rank = read_this_rank &&
(((nCK_PER_CLK == 4) && read_this_rank_r) ||
((nCK_PER_CLK != 4) && read_this_rank_r1));
reg periodic_rd_cntr1_ns;
reg periodic_rd_cntr1_r;
always @(/*AS*/clear_periodic_rd_request or periodic_rd_cntr1_r) begin
periodic_rd_cntr1_ns = periodic_rd_cntr1_r;
if (clear_periodic_rd_request)
periodic_rd_cntr1_ns = periodic_rd_cntr1_r + 1'b1;
end
always @(posedge clk) begin
if (rst) periodic_rd_cntr1_r <= #TCQ 1'b0;
else periodic_rd_cntr1_r <= #TCQ periodic_rd_cntr1_ns;
end
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_r;
reg [PERIODIC_RD_TIMER_WIDTH-1:0] periodic_rd_timer_ns;
always @(/*AS*/init_calib_complete or maint_prescaler_tick_r
or periodic_rd_timer_r or int_read_this_rank) begin
periodic_rd_timer_ns = periodic_rd_timer_r;
if (~init_calib_complete)
periodic_rd_timer_ns = {PERIODIC_RD_TIMER_WIDTH{1'b0}};
else if (int_read_this_rank)
periodic_rd_timer_ns =
PERIODIC_RD_TIMER_DIV[0+:PERIODIC_RD_TIMER_WIDTH];
else if (|periodic_rd_timer_r && maint_prescaler_tick_r)
periodic_rd_timer_ns =
periodic_rd_timer_r - ONE[0+:PERIODIC_RD_TIMER_WIDTH];
end
always @(posedge clk) periodic_rd_timer_r <= #TCQ periodic_rd_timer_ns;
wire periodic_rd_timer_one = maint_prescaler_tick_r &&
(periodic_rd_timer_r == ONE[0+:PERIODIC_RD_TIMER_WIDTH]);
reg periodic_rd_request_r;
wire periodic_rd_request_ns = ~rst &&
((app_periodic_rd_req && init_calib_complete) ||
((PERIODIC_RD_TIMER_DIV != 0) && ~init_calib_complete) ||
// (~(read_this_rank || clear_periodic_rd_request) &&
(~((int_read_this_rank) || (clear_periodic_rd_request && periodic_rd_cntr1_r)) &&
(periodic_rd_request_r || periodic_rd_timer_one)));
always @(posedge clk) periodic_rd_request_r <=
#TCQ periodic_rd_request_ns;
`ifdef MC_SVA
read_clears_periodic_rd_request: cover property (@(posedge clk)
(rst && (periodic_rd_request_r && read_this_rank)));
`endif
assign periodic_rd_request = init_calib_complete && periodic_rd_request_r;
end else
assign periodic_rd_request = 1'b0; //to disable periodic reads
end
endgenerate
endmodule
|
(** * Rel: Properties of Relations *)
(* $Date: 2013-04-01 09:15:45 -0400 (Mon, 01 Apr 2013) $ *)
Require Export SfLib.
(** A (binary) _relation_ is just a parameterized proposition. As you know
from your undergraduate discrete math course, there are a lot of
ways of discussing and describing relations _in general_ -- ways
of classifying relations (are they reflexive, transitive, etc.),
theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. Let us pause here to review a few that will be useful in
what follows. *)
(** A (binary) relation _on_ a set [X] is a proposition parameterized by two
[X]s -- i.e., it is a logical assertion involving two values from
the set [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-that-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====>
Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m
*)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined in Logic.v is a
partial function. *)
(* Print next_nat.
(* ====>
Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n)
*)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed. *)
(** However, the [<=] relation on numbers is not a partial function.
This can be shown by contradiction. In short: Assume, for a
contradiction, that [<=] is a partial function. But then, since
[0 <= 0] and [0 <= 1], it follows that [0 = 1]. This is nonsense,
so our assumption was contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply Hc with (x := 0).
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in Logic.v is not a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined in Logic.v is a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
SCase "le_n". apply rt_refl.
SCase "le_S".
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** (The following [Tactic Notation] definitions are explained in
Imp.v. You can ignore them if you haven't read that chapter
yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_register(clock, resetn, i_counter_reset, i_settings, i_datain, i_datain_valid, o_datain_stall, o_dataout, o_dataout_valid, i_dataout_stall);
parameter DATA_WIDTH = 32;
input clock, resetn, i_counter_reset;
input [DATA_WIDTH-1:0] i_settings;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
vfabric_counter_fifo fifo0 (.clock(clock), .resetn(resetn), .i_counter_reset(i_counter_reset),
.i_datain_valid(i_datain_valid), .o_datain_stall(o_datain_stall),
.o_dataout_valid(o_dataout_valid), .i_dataout_stall(i_dataout_stall));
assign o_dataout = i_settings;
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
//-----------------------------------------------------------------
// USB CDC Device
// V0.1
// Ultra-Embedded.com
// Copyright 2014-2019
//
// Email: [email protected]
//
// License: LGPL
//-----------------------------------------------------------------
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Generated File
//-----------------------------------------------------------------
module usb_cdc_core
(
// Inputs
input clk_i
,input rst_i
,input enable_i
,input [ 7:0] utmi_data_in_i
,input utmi_txready_i
,input utmi_rxvalid_i
,input utmi_rxactive_i
,input utmi_rxerror_i
,input [ 1:0] utmi_linestate_i
,input inport_valid_i
,input [ 7:0] inport_data_i
,input outport_accept_i
// Outputs
,output [ 7:0] utmi_data_out_o
,output utmi_txvalid_o
,output [ 1:0] utmi_op_mode_o
,output [ 1:0] utmi_xcvrselect_o
,output utmi_termselect_o
,output utmi_dppulldown_o
,output utmi_dmpulldown_o
,output inport_accept_o
,output outport_valid_o
,output [ 7:0] outport_data_o
);
parameter USB_SPEED_HS = "False"; // True or False
//-----------------------------------------------------------------
// Defines
//-----------------------------------------------------------------
// Device class
`define DEV_CLASS_RESERVED 8'h00
`define DEV_CLASS_AUDIO 8'h01
`define DEV_CLASS_COMMS 8'h02
`define DEV_CLASS_HID 8'h03
`define DEV_CLASS_MONITOR 8'h04
`define DEV_CLASS_PHY_IF 8'h05
`define DEV_CLASS_POWER 8'h06
`define DEV_CLASS_PRINTER 8'h07
`define DEV_CLASS_STORAGE 8'h08
`define DEV_CLASS_HUB 8'h09
`define DEV_CLASS_TMC 8'hFE
`define DEV_CLASS_VENDOR_CUSTOM 8'hFF
// Standard requests (via SETUP packets)
`define REQ_GET_STATUS 8'h00
`define REQ_CLEAR_FEATURE 8'h01
`define REQ_SET_FEATURE 8'h03
`define REQ_SET_ADDRESS 8'h05
`define REQ_GET_DESCRIPTOR 8'h06
`define REQ_SET_DESCRIPTOR 8'h07
`define REQ_GET_CONFIGURATION 8'h08
`define REQ_SET_CONFIGURATION 8'h09
`define REQ_GET_INTERFACE 8'h0A
`define REQ_SET_INTERFACE 8'h0B
`define REQ_SYNC_FRAME 8'h0C
// Descriptor types
`define DESC_DEVICE 8'h01
`define DESC_CONFIGURATION 8'h02
`define DESC_STRING 8'h03
`define DESC_INTERFACE 8'h04
`define DESC_ENDPOINT 8'h05
`define DESC_DEV_QUALIFIER 8'h06
`define DESC_OTHER_SPEED_CONF 8'h07
`define DESC_IF_POWER 8'h08
// Endpoints
`define ENDPOINT_DIR_MASK 8'h80
`define ENDPOINT_DIR_R 7
`define ENDPOINT_DIR_IN 1'b1
`define ENDPOINT_DIR_OUT 1'b0
`define ENDPOINT_ADDR_MASK 8'h7F
`define ENDPOINT_TYPE_MASK 8'h3
`define ENDPOINT_TYPE_CONTROL 0
`define ENDPOINT_TYPE_ISO 1
`define ENDPOINT_TYPE_BULK 2
`define ENDPOINT_TYPE_INTERRUPT 3
// Device Requests (bmRequestType)
`define USB_RECIPIENT_MASK 8'h1F
`define USB_RECIPIENT_DEVICE 8'h00
`define USB_RECIPIENT_INTERFACE 8'h01
`define USB_RECIPIENT_ENDPOINT 8'h02
`define USB_REQUEST_TYPE_MASK 8'h60
`define USB_STANDARD_REQUEST 8'h00
`define USB_CLASS_REQUEST 8'h20
`define USB_VENDOR_REQUEST 8'h40
// USB device addresses are 7-bits
`define USB_ADDRESS_MASK 8'h7F
// USB Feature Selectors
`define USB_FEATURE_ENDPOINT_STATE 16'h0000
`define USB_FEATURE_REMOTE_WAKEUP 16'h0001
`define USB_FEATURE_TEST_MODE 16'h0002
// String Descriptors
`define UNICODE_LANGUAGE_STR_ID 8'd0
`define MANUFACTURER_STR_ID 8'd1
`define PRODUCT_NAME_STR_ID 8'd2
`define SERIAL_NUM_STR_ID 8'd3
`define CDC_ENDPOINT_BULK_OUT 1
`define CDC_ENDPOINT_BULK_IN 2
`define CDC_ENDPOINT_INTR_IN 3
`define CDC_SEND_ENCAPSULATED_COMMAND 8'h00
`define CDC_GET_ENCAPSULATED_RESPONSE 8'h01
`define CDC_GET_LINE_CODING 8'h21
`define CDC_SET_LINE_CODING 8'h20
`define CDC_SET_CONTROL_LINE_STATE 8'h22
`define CDC_SEND_BREAK 8'h23
// Descriptor ROM offsets / sizes
`define ROM_DESC_DEVICE_ADDR 8'd0
`define ROM_DESC_DEVICE_SIZE 16'd18
`define ROM_DESC_CONF_ADDR 8'd18
`define ROM_DESC_CONF_SIZE 16'd67
`define ROM_DESC_STR_LANG_ADDR 8'd85
`define ROM_DESC_STR_LANG_SIZE 16'd4
`define ROM_DESC_STR_MAN_ADDR 8'd89
`define ROM_DESC_STR_MAN_SIZE 16'd30
`define ROM_DESC_STR_PROD_ADDR 8'd119
`define ROM_DESC_STR_PROD_SIZE 16'd30
`define ROM_DESC_STR_SERIAL_ADDR 8'd149
`define ROM_DESC_STR_SERIAL_SIZE 16'd14
`define ROM_CDC_LINE_CODING_ADDR 8'd163
`define ROM_CDC_LINE_CODING_SIZE 16'd7
//-----------------------------------------------------------------
// Wires
//-----------------------------------------------------------------
wire usb_reset_w;
reg [6:0] device_addr_q;
wire usb_ep0_tx_rd_w;
wire [7:0] usb_ep0_tx_data_w;
wire usb_ep0_tx_empty_w;
wire usb_ep0_rx_wr_w;
wire [7:0] usb_ep0_rx_data_w;
wire usb_ep0_rx_full_w;
wire usb_ep1_tx_rd_w;
wire [7:0] usb_ep1_tx_data_w;
wire usb_ep1_tx_empty_w;
wire usb_ep1_rx_wr_w;
wire [7:0] usb_ep1_rx_data_w;
wire usb_ep1_rx_full_w;
wire usb_ep2_tx_rd_w;
wire [7:0] usb_ep2_tx_data_w;
wire usb_ep2_tx_empty_w;
wire usb_ep2_rx_wr_w;
wire [7:0] usb_ep2_rx_data_w;
wire usb_ep2_rx_full_w;
wire usb_ep3_tx_rd_w;
wire [7:0] usb_ep3_tx_data_w;
wire usb_ep3_tx_empty_w;
wire usb_ep3_rx_wr_w;
wire [7:0] usb_ep3_rx_data_w;
wire usb_ep3_rx_full_w;
// Rx SIE Interface (shared)
wire rx_strb_w;
wire [7:0] rx_data_w;
wire rx_last_w;
wire rx_crc_err_w;
// EP0 Rx SIE Interface
wire ep0_rx_space_w;
wire ep0_rx_valid_w;
wire ep0_rx_setup_w;
// EP0 Tx SIE Interface
wire ep0_tx_ready_w;
wire ep0_tx_data_valid_w;
wire ep0_tx_data_strb_w;
wire [7:0] ep0_tx_data_w;
wire ep0_tx_data_last_w;
wire ep0_tx_data_accept_w;
wire ep0_tx_stall_w;
// EP1 Rx SIE Interface
wire ep1_rx_space_w;
wire ep1_rx_valid_w;
wire ep1_rx_setup_w;
// EP1 Tx SIE Interface
wire ep1_tx_ready_w;
wire ep1_tx_data_valid_w;
wire ep1_tx_data_strb_w;
wire [7:0] ep1_tx_data_w;
wire ep1_tx_data_last_w;
wire ep1_tx_data_accept_w;
wire ep1_tx_stall_w;
// EP2 Rx SIE Interface
wire ep2_rx_space_w;
wire ep2_rx_valid_w;
wire ep2_rx_setup_w;
// EP2 Tx SIE Interface
wire ep2_tx_ready_w;
wire ep2_tx_data_valid_w;
wire ep2_tx_data_strb_w;
wire [7:0] ep2_tx_data_w;
wire ep2_tx_data_last_w;
wire ep2_tx_data_accept_w;
wire ep2_tx_stall_w;
// EP3 Rx SIE Interface
wire ep3_rx_space_w;
wire ep3_rx_valid_w;
wire ep3_rx_setup_w;
// EP3 Tx SIE Interface
wire ep3_tx_ready_w;
wire ep3_tx_data_valid_w;
wire ep3_tx_data_strb_w;
wire [7:0] ep3_tx_data_w;
wire ep3_tx_data_last_w;
wire ep3_tx_data_accept_w;
wire ep3_tx_stall_w;
wire utmi_chirp_en_w;
wire usb_hs_w;
//-----------------------------------------------------------------
// Transceiver Control (high speed)
//-----------------------------------------------------------------
generate
if (USB_SPEED_HS == "True")
begin
localparam STATE_W = 3;
localparam STATE_IDLE = 3'd0;
localparam STATE_WAIT_RST = 3'd1;
localparam STATE_SEND_CHIRP_K = 3'd2;
localparam STATE_WAIT_CHIRP_JK = 3'd3;
localparam STATE_FULLSPEED = 3'd4;
localparam STATE_HIGHSPEED = 3'd5;
reg [STATE_W-1:0] state_q;
reg [STATE_W-1:0] next_state_r;
// 60MHz clock rate
`define USB_RST_W 20
reg [`USB_RST_W-1:0] usb_rst_time_q;
reg [7:0] chirp_count_q;
reg [1:0] last_linestate_q;
localparam DETACH_TIME = 20'd60000; // 1ms -> T0
localparam ATTACH_FS_TIME = 20'd180000; // T0 + 3ms = T1
localparam CHIRPK_TIME = 20'd246000; // T1 + ~1ms
localparam HS_RESET_TIME = 20'd600000; // T0 + 10ms = T9
localparam HS_CHIRP_COUNT = 8'd5;
reg [ 1:0] utmi_op_mode_r;
reg [ 1:0] utmi_xcvrselect_r;
reg utmi_termselect_r;
reg utmi_dppulldown_r;
reg utmi_dmpulldown_r;
always @ *
begin
next_state_r = state_q;
// Default - disconnect
utmi_op_mode_r = 2'd1;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b0;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
case (state_q)
STATE_IDLE:
begin
// Detached
if (enable_i && usb_rst_time_q >= DETACH_TIME)
next_state_r = STATE_WAIT_RST;
end
STATE_WAIT_RST:
begin
// Assert FS mode, check for SE0 (T0)
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd1;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// Wait for SE0 (T1), send device chirp K
if (usb_rst_time_q >= ATTACH_FS_TIME)
next_state_r = STATE_SEND_CHIRP_K;
end
STATE_SEND_CHIRP_K:
begin
// Send chirp K
utmi_op_mode_r = 2'd2;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// End of device chirp K (T2)
if (usb_rst_time_q >= CHIRPK_TIME)
next_state_r = STATE_WAIT_CHIRP_JK;
end
STATE_WAIT_CHIRP_JK:
begin
// Stop sending chirp K and wait for downstream port chirps
utmi_op_mode_r = 2'd2;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// Required number of chirps detected, move to HS mode (T7)
if (chirp_count_q >= HS_CHIRP_COUNT)
next_state_r = STATE_HIGHSPEED;
// Time out waiting for chirps, fallback to FS mode
else if (usb_rst_time_q >= HS_RESET_TIME)
next_state_r = STATE_FULLSPEED;
end
STATE_FULLSPEED:
begin
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd1;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// USB reset detected...
if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
next_state_r = STATE_WAIT_RST;
end
STATE_HIGHSPEED:
begin
// Enter HS mode
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b0;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
// Long SE0 - could be reset or suspend
// TODO: Should revert to FS mode and check...
if (usb_rst_time_q >= HS_RESET_TIME && usb_reset_w)
next_state_r = STATE_WAIT_RST;
end
default:
;
endcase
end
// Update state
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
state_q <= STATE_IDLE;
else
state_q <= next_state_r;
// Time since T0 (start of HS reset)
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
usb_rst_time_q <= `USB_RST_W'b0;
// Entering wait for reset state
else if (next_state_r == STATE_WAIT_RST && state_q != STATE_WAIT_RST)
usb_rst_time_q <= `USB_RST_W'b0;
// Waiting for reset, reset count on line state toggle
else if (state_q == STATE_WAIT_RST && (utmi_linestate_i != 2'b00))
usb_rst_time_q <= `USB_RST_W'b0;
else if (usb_rst_time_q != {(`USB_RST_W){1'b1}})
usb_rst_time_q <= usb_rst_time_q + `USB_RST_W'd1;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
last_linestate_q <= 2'b0;
else
last_linestate_q <= utmi_linestate_i;
// Chirp counter
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
chirp_count_q <= 8'b0;
else if (state_q == STATE_SEND_CHIRP_K)
chirp_count_q <= 8'b0;
else if (state_q == STATE_WAIT_CHIRP_JK && (last_linestate_q != utmi_linestate_i) && chirp_count_q != 8'hFF)
chirp_count_q <= chirp_count_q + 8'd1;
assign utmi_op_mode_o = utmi_op_mode_r;
assign utmi_xcvrselect_o = utmi_xcvrselect_r;
assign utmi_termselect_o = utmi_termselect_r;
assign utmi_dppulldown_o = utmi_dppulldown_r;
assign utmi_dmpulldown_o = utmi_dmpulldown_r;
assign utmi_chirp_en_w = (state_q == STATE_SEND_CHIRP_K);
assign usb_hs_w = (state_q == STATE_HIGHSPEED);
end
else
begin
//-----------------------------------------------------------------
// Transceiver Control
//-----------------------------------------------------------------
reg [ 1:0] utmi_op_mode_r;
reg [ 1:0] utmi_xcvrselect_r;
reg utmi_termselect_r;
reg utmi_dppulldown_r;
reg utmi_dmpulldown_r;
always @ *
begin
if (enable_i)
begin
utmi_op_mode_r = 2'd0;
utmi_xcvrselect_r = 2'd1;
utmi_termselect_r = 1'b1;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
end
else
begin
utmi_op_mode_r = 2'd1;
utmi_xcvrselect_r = 2'd0;
utmi_termselect_r = 1'b0;
utmi_dppulldown_r = 1'b0;
utmi_dmpulldown_r = 1'b0;
end
end
assign utmi_op_mode_o = utmi_op_mode_r;
assign utmi_xcvrselect_o = utmi_xcvrselect_r;
assign utmi_termselect_o = utmi_termselect_r;
assign utmi_dppulldown_o = utmi_dppulldown_r;
assign utmi_dmpulldown_o = utmi_dmpulldown_r;
assign utmi_chirp_en_w = 1'b0;
assign usb_hs_w = 1'b0;
end
endgenerate
//-----------------------------------------------------------------
// Core
//-----------------------------------------------------------------
usbf_device_core
u_core
(
.clk_i(clk_i),
.rst_i(rst_i),
.intr_o(),
// UTMI interface
.utmi_data_o(utmi_data_out_o),
.utmi_data_i(utmi_data_in_i),
.utmi_txvalid_o(utmi_txvalid_o),
.utmi_txready_i(utmi_txready_i),
.utmi_rxvalid_i(utmi_rxvalid_i),
.utmi_rxactive_i(utmi_rxactive_i),
.utmi_rxerror_i(utmi_rxerror_i),
.utmi_linestate_i(utmi_linestate_i),
.reg_chirp_en_i(utmi_chirp_en_w),
.reg_int_en_sof_i(1'b0),
.reg_dev_addr_i(device_addr_q),
// Rx SIE Interface (shared)
.rx_strb_o(rx_strb_w),
.rx_data_o(rx_data_w),
.rx_last_o(rx_last_w),
.rx_crc_err_o(rx_crc_err_w),
// EP0 Config
.ep0_iso_i(1'b0),
.ep0_stall_i(ep0_tx_stall_w),
.ep0_cfg_int_rx_i(1'b0),
.ep0_cfg_int_tx_i(1'b0),
// EP0 Rx SIE Interface
.ep0_rx_setup_o(ep0_rx_setup_w),
.ep0_rx_valid_o(ep0_rx_valid_w),
.ep0_rx_space_i(ep0_rx_space_w),
// EP0 Tx SIE Interface
.ep0_tx_ready_i(ep0_tx_ready_w),
.ep0_tx_data_valid_i(ep0_tx_data_valid_w),
.ep0_tx_data_strb_i(ep0_tx_data_strb_w),
.ep0_tx_data_i(ep0_tx_data_w),
.ep0_tx_data_last_i(ep0_tx_data_last_w),
.ep0_tx_data_accept_o(ep0_tx_data_accept_w),
// EP1 Config
.ep1_iso_i(1'b0),
.ep1_stall_i(ep1_tx_stall_w),
.ep1_cfg_int_rx_i(1'b0),
.ep1_cfg_int_tx_i(1'b0),
// EP1 Rx SIE Interface
.ep1_rx_setup_o(ep1_rx_setup_w),
.ep1_rx_valid_o(ep1_rx_valid_w),
.ep1_rx_space_i(ep1_rx_space_w),
// EP1 Tx SIE Interface
.ep1_tx_ready_i(ep1_tx_ready_w),
.ep1_tx_data_valid_i(ep1_tx_data_valid_w),
.ep1_tx_data_strb_i(ep1_tx_data_strb_w),
.ep1_tx_data_i(ep1_tx_data_w),
.ep1_tx_data_last_i(ep1_tx_data_last_w),
.ep1_tx_data_accept_o(ep1_tx_data_accept_w),
// EP2 Config
.ep2_iso_i(1'b0),
.ep2_stall_i(ep2_tx_stall_w),
.ep2_cfg_int_rx_i(1'b0),
.ep2_cfg_int_tx_i(1'b0),
// EP2 Rx SIE Interface
.ep2_rx_setup_o(ep2_rx_setup_w),
.ep2_rx_valid_o(ep2_rx_valid_w),
.ep2_rx_space_i(ep2_rx_space_w),
// EP2 Tx SIE Interface
.ep2_tx_ready_i(ep2_tx_ready_w),
.ep2_tx_data_valid_i(ep2_tx_data_valid_w),
.ep2_tx_data_strb_i(ep2_tx_data_strb_w),
.ep2_tx_data_i(ep2_tx_data_w),
.ep2_tx_data_last_i(ep2_tx_data_last_w),
.ep2_tx_data_accept_o(ep2_tx_data_accept_w),
// EP3 Config
.ep3_iso_i(1'b0),
.ep3_stall_i(ep3_tx_stall_w),
.ep3_cfg_int_rx_i(1'b0),
.ep3_cfg_int_tx_i(1'b0),
// EP3 Rx SIE Interface
.ep3_rx_setup_o(ep3_rx_setup_w),
.ep3_rx_valid_o(ep3_rx_valid_w),
.ep3_rx_space_i(ep3_rx_space_w),
// EP3 Tx SIE Interface
.ep3_tx_ready_i(ep3_tx_ready_w),
.ep3_tx_data_valid_i(ep3_tx_data_valid_w),
.ep3_tx_data_strb_i(ep3_tx_data_strb_w),
.ep3_tx_data_i(ep3_tx_data_w),
.ep3_tx_data_last_i(ep3_tx_data_last_w),
.ep3_tx_data_accept_o(ep3_tx_data_accept_w),
// Status
.reg_sts_rst_clr_i(1'b1),
.reg_sts_rst_o(usb_reset_w),
.reg_sts_frame_num_o()
);
assign ep0_rx_space_w = 1'b1;
//-----------------------------------------------------------------
// USB: Setup packet capture (limited to 8 bytes for USB-FS)
//-----------------------------------------------------------------
reg [7:0] setup_packet_q[0:7];
reg [2:0] setup_wr_idx_q;
reg setup_frame_q;
reg setup_valid_q;
reg status_ready_q; // STATUS response received
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
setup_packet_q[0] <= 8'b0;
setup_packet_q[1] <= 8'b0;
setup_packet_q[2] <= 8'b0;
setup_packet_q[3] <= 8'b0;
setup_packet_q[4] <= 8'b0;
setup_packet_q[5] <= 8'b0;
setup_packet_q[6] <= 8'b0;
setup_packet_q[7] <= 8'b0;
setup_wr_idx_q <= 3'b0;
setup_valid_q <= 1'b0;
setup_frame_q <= 1'b0;
status_ready_q <= 1'b0;
end
// SETUP token received
else if (ep0_rx_setup_w)
begin
setup_packet_q[0] <= 8'b0;
setup_packet_q[1] <= 8'b0;
setup_packet_q[2] <= 8'b0;
setup_packet_q[3] <= 8'b0;
setup_packet_q[4] <= 8'b0;
setup_packet_q[5] <= 8'b0;
setup_packet_q[6] <= 8'b0;
setup_packet_q[7] <= 8'b0;
setup_wr_idx_q <= 3'b0;
setup_valid_q <= 1'b0;
setup_frame_q <= 1'b1;
status_ready_q <= 1'b0;
end
// Valid DATA for setup frame
else if (ep0_rx_valid_w && rx_strb_w)
begin
setup_packet_q[setup_wr_idx_q] <= rx_data_w;
setup_wr_idx_q <= setup_wr_idx_q + 3'd1;
setup_valid_q <= setup_frame_q && rx_last_w;
if (rx_last_w)
setup_frame_q <= 1'b0;
end
// Detect STATUS stage (ACK for SETUP GET requests)
// TODO: Not quite correct ....
else if (ep0_rx_valid_w && !rx_strb_w && rx_last_w)
begin
setup_valid_q <= 1'b0;
status_ready_q <= 1'b1;
end
else
setup_valid_q <= 1'b0;
//-----------------------------------------------------------------
// SETUP request decode
//-----------------------------------------------------------------
wire [7:0] bmRequestType_w = setup_packet_q[0];
wire [7:0] bRequest_w = setup_packet_q[1];
wire [15:0] wValue_w = {setup_packet_q[3], setup_packet_q[2]};
wire [15:0] wIndex_w = {setup_packet_q[5], setup_packet_q[4]};
wire [15:0] wLength = {setup_packet_q[7], setup_packet_q[6]};
wire setup_get_w = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_IN);
wire setup_set_w = setup_valid_q && (bmRequestType_w[`ENDPOINT_DIR_R] == `ENDPOINT_DIR_OUT);
wire setup_no_data_w = setup_set_w && (wLength == 16'b0);
// For REQ_GET_DESCRIPTOR
wire [7:0] bDescriptorType_w = setup_packet_q[3];
wire [7:0] bDescriptorIndex_w = setup_packet_q[2];
//-----------------------------------------------------------------
// Process setup request
//-----------------------------------------------------------------
reg ctrl_stall_r; // Send STALL
reg ctrl_ack_r; // Send STATUS (ZLP)
reg [15:0] ctrl_get_len_r;
reg [7:0] desc_addr_r;
reg addressed_q;
reg addressed_r;
reg [6:0] device_addr_r;
reg configured_q;
reg configured_r;
always @ *
begin
ctrl_stall_r = 1'b0;
ctrl_get_len_r = 16'b0;
ctrl_ack_r = 1'b0;
desc_addr_r = 8'b0;
device_addr_r = device_addr_q;
addressed_r = addressed_q;
configured_r = configured_q;
if (setup_valid_q)
begin
case (bmRequestType_w & `USB_REQUEST_TYPE_MASK)
`USB_STANDARD_REQUEST:
begin
case (bRequest_w)
`REQ_GET_STATUS:
begin
$display("GET_STATUS");
end
`REQ_CLEAR_FEATURE:
begin
$display("CLEAR_FEATURE");
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
`REQ_SET_FEATURE:
begin
$display("SET_FEATURE");
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
`REQ_SET_ADDRESS:
begin
$display("SET_ADDRESS: Set device address %d", wValue_w[6:0]);
ctrl_ack_r = setup_set_w && setup_no_data_w;
device_addr_r = wValue_w[6:0];
addressed_r = 1'b1;
end
`REQ_GET_DESCRIPTOR:
begin
$display("GET_DESCRIPTOR: Type %d", bDescriptorType_w);
case (bDescriptorType_w)
`DESC_DEVICE:
begin
desc_addr_r = `ROM_DESC_DEVICE_ADDR;
ctrl_get_len_r = `ROM_DESC_DEVICE_SIZE;
end
`DESC_CONFIGURATION:
begin
desc_addr_r = `ROM_DESC_CONF_ADDR;
ctrl_get_len_r = `ROM_DESC_CONF_SIZE;
end
`DESC_STRING:
begin
case (bDescriptorIndex_w)
`UNICODE_LANGUAGE_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_LANG_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_LANG_SIZE;
end
`MANUFACTURER_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_MAN_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_MAN_SIZE;
end
`PRODUCT_NAME_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_PROD_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_PROD_SIZE;
end
`SERIAL_NUM_STR_ID:
begin
desc_addr_r = `ROM_DESC_STR_SERIAL_ADDR;
ctrl_get_len_r = `ROM_DESC_STR_SERIAL_SIZE;
end
default:
;
endcase
end
default:
;
endcase
end
`REQ_GET_CONFIGURATION:
begin
$display("GET_CONF");
end
`REQ_SET_CONFIGURATION:
begin
$display("SET_CONF: Configuration %x", wValue_w);
if (wValue_w == 16'd0)
begin
configured_r = 1'b0;
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
// Only support one configuration for now
else if (wValue_w == 16'd1)
begin
configured_r = 1'b1;
ctrl_ack_r = setup_set_w && setup_no_data_w;
end
else
ctrl_stall_r = 1'b1;
end
`REQ_GET_INTERFACE:
begin
$display("GET_INTERFACE");
ctrl_stall_r = 1'b1;
end
`REQ_SET_INTERFACE:
begin
$display("SET_INTERFACE: %x %x", wValue_w, wIndex_w);
if (wValue_w == 16'd0 && wIndex_w == 16'd0)
ctrl_ack_r = setup_set_w && setup_no_data_w;
else
ctrl_stall_r = 1'b1;
end
default:
begin
ctrl_stall_r = 1'b1;
end
endcase
end
`USB_VENDOR_REQUEST:
begin
// None supported
ctrl_stall_r = 1'b1;
end
`USB_CLASS_REQUEST:
begin
case (bRequest_w)
`CDC_GET_LINE_CODING:
begin
$display("CDC_GET_LINE_CODING");
desc_addr_r = `ROM_CDC_LINE_CODING_ADDR;
ctrl_get_len_r = `ROM_CDC_LINE_CODING_SIZE;
end
default:
ctrl_ack_r = setup_set_w && setup_no_data_w;
endcase
end
default:
begin
ctrl_stall_r = 1'b1;
end
endcase
end
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
device_addr_q <= 7'b0;
addressed_q <= 1'b0;
configured_q <= 1'b0;
end
else if (usb_reset_w)
begin
device_addr_q <= 7'b0;
addressed_q <= 1'b0;
configured_q <= 1'b0;
end
else
begin
device_addr_q <= device_addr_r;
addressed_q <= addressed_r;
configured_q <= configured_r;
end
//-----------------------------------------------------------------
// SETUP response
//-----------------------------------------------------------------
reg ctrl_sending_q;
reg [15:0] ctrl_send_idx_q;
reg [15:0] ctrl_send_len_q;
wire ctrl_send_zlp_w = ctrl_sending_q && (ctrl_send_len_q != wLength);
reg ctrl_sending_r;
reg [15:0] ctrl_send_idx_r;
reg [15:0] ctrl_send_len_r;
reg ctrl_txvalid_q;
reg [7:0] ctrl_txdata_q;
reg ctrl_txstrb_q;
reg ctrl_txlast_q;
reg ctrl_txstall_q;
reg ctrl_txvalid_r;
reg [7:0] ctrl_txdata_r;
reg ctrl_txstrb_r;
reg ctrl_txlast_r;
reg ctrl_txstall_r;
wire ctrl_send_accept_w = ep0_tx_data_accept_w || !ep0_tx_data_valid_w;
reg [7:0] desc_addr_q;
wire[7:0] desc_data_w;
always @ *
begin
ctrl_sending_r = ctrl_sending_q;
ctrl_send_idx_r = ctrl_send_idx_q;
ctrl_send_len_r = ctrl_send_len_q;
ctrl_txvalid_r = ctrl_txvalid_q;
ctrl_txdata_r = ctrl_txdata_q;
ctrl_txstrb_r = ctrl_txstrb_q;
ctrl_txlast_r = ctrl_txlast_q;
ctrl_txstall_r = ctrl_txstall_q;
// New SETUP request
if (setup_valid_q)
begin
// Send STALL
if (ctrl_stall_r)
begin
ctrl_txvalid_r = 1'b1;
ctrl_txstrb_r = 1'b0;
ctrl_txlast_r = 1'b1;
ctrl_txstall_r = 1'b1;
end
// Send STATUS response (ZLP)
else if (ctrl_ack_r)
begin
ctrl_txvalid_r = 1'b1;
ctrl_txstrb_r = 1'b0;
ctrl_txlast_r = 1'b1;
ctrl_txstall_r = 1'b0;
end
else
begin
ctrl_sending_r = setup_get_w && !ctrl_stall_r;
ctrl_send_idx_r = 16'b0;
ctrl_send_len_r = ctrl_get_len_r;
ctrl_txstall_r = 1'b0;
end
end
// Abort control send when STATUS received
else if (status_ready_q)
begin
ctrl_sending_r = 1'b0;
ctrl_send_idx_r = 16'b0;
ctrl_send_len_r = 16'b0;
ctrl_txvalid_r = 1'b0;
end
else if (ctrl_sending_r && ctrl_send_accept_w)
begin
// TODO: Send ZLP on exact multiple lengths...
ctrl_txvalid_r = 1'b1;
ctrl_txdata_r = desc_data_w;
ctrl_txstrb_r = 1'b1;
ctrl_txlast_r = usb_hs_w ? (ctrl_send_idx_r[5:0] == 6'b111111) : (ctrl_send_idx_r[2:0] == 3'b111);
// Increment send index
ctrl_send_idx_r = ctrl_send_idx_r + 16'd1;
// TODO: Detect need for ZLP
if (ctrl_send_idx_r == wLength)
begin
ctrl_sending_r = 1'b0;
ctrl_txlast_r = 1'b1;
end
end
else if (ctrl_send_accept_w)
ctrl_txvalid_r = 1'b0;
end
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
ctrl_sending_q <= 1'b0;
ctrl_send_idx_q <= 16'b0;
ctrl_send_len_q <= 16'b0;
ctrl_txvalid_q <= 1'b0;
ctrl_txdata_q <= 8'b0;
ctrl_txstrb_q <= 1'b0;
ctrl_txlast_q <= 1'b0;
ctrl_txstall_q <= 1'b0;
desc_addr_q <= 8'b0;
end
else if (usb_reset_w)
begin
ctrl_sending_q <= 1'b0;
ctrl_send_idx_q <= 16'b0;
ctrl_send_len_q <= 16'b0;
ctrl_txvalid_q <= 1'b0;
ctrl_txdata_q <= 8'b0;
ctrl_txstrb_q <= 1'b0;
ctrl_txlast_q <= 1'b0;
ctrl_txstall_q <= 1'b0;
desc_addr_q <= 8'b0;
end
else
begin
ctrl_sending_q <= ctrl_sending_r;
ctrl_send_idx_q <= ctrl_send_idx_r;
ctrl_send_len_q <= ctrl_send_len_r;
ctrl_txvalid_q <= ctrl_txvalid_r;
ctrl_txdata_q <= ctrl_txdata_r;
ctrl_txstrb_q <= ctrl_txstrb_r;
ctrl_txlast_q <= ctrl_txlast_r;
ctrl_txstall_q <= ctrl_txstall_r;
if (setup_valid_q)
desc_addr_q <= desc_addr_r;
else if (ctrl_sending_r && ctrl_send_accept_w)
desc_addr_q <= desc_addr_q + 8'd1;
end
assign ep0_tx_ready_w = ctrl_txvalid_q;
assign ep0_tx_data_valid_w = ctrl_txvalid_q;
assign ep0_tx_data_strb_w = ctrl_txstrb_q;
assign ep0_tx_data_w = ctrl_txdata_q;
assign ep0_tx_data_last_w = ctrl_txlast_q;
assign ep0_tx_stall_w = ctrl_txstall_q;
//-----------------------------------------------------------------
// Descriptor ROM
//-----------------------------------------------------------------
usb_desc_rom
u_rom
(
.hs_i(usb_hs_w),
.addr_i(desc_addr_q),
.data_o(desc_data_w)
);
//-----------------------------------------------------------------
// Unused Endpoints
//-----------------------------------------------------------------
assign ep1_tx_ready_w = 1'b0;
assign ep1_tx_data_valid_w = 1'b0;
assign ep1_tx_data_strb_w = 1'b0;
assign ep1_tx_data_w = 8'b0;
assign ep1_tx_data_last_w = 1'b0;
assign ep1_tx_stall_w = 1'b0;
assign ep3_tx_ready_w = 1'b0;
assign ep3_tx_data_valid_w = 1'b0;
assign ep3_tx_data_strb_w = 1'b0;
assign ep3_tx_data_w = 8'b0;
assign ep3_tx_data_last_w = 1'b0;
assign ep3_tx_stall_w = 1'b0;
assign ep2_rx_space_w = 1'b0;
assign ep3_rx_space_w = 1'b0;
//-----------------------------------------------------------------
// Stream I/O
//-----------------------------------------------------------------
reg inport_valid_q;
reg [7:0] inport_data_q;
wire inport_last_w = !inport_valid_i;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
begin
inport_valid_q <= 1'b0;
inport_data_q <= 8'b0;
end
else if (inport_accept_o)
begin
inport_valid_q <= inport_valid_i;
inport_data_q <= inport_data_i;
end
assign ep2_tx_data_valid_w = inport_valid_q;
assign ep2_tx_data_w = inport_data_q;
assign ep2_tx_ready_w = ep2_tx_data_valid_w;
assign ep2_tx_data_strb_w = ep2_tx_data_valid_w;
assign ep2_tx_data_last_w = inport_last_w;
assign inport_accept_o = !inport_valid_q | ep2_tx_data_accept_w;
assign outport_valid_o = ep1_rx_valid_w && rx_strb_w;
assign outport_data_o = rx_data_w;
assign ep1_rx_space_w = outport_accept_i;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Sub sub1 (.*);
Sub sub2 (.*);
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Simple cover
cover property (@(posedge clk) cyc==3);
// With statement, in generate
generate if (1) begin
cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4");
end
endgenerate
// Labeled cover
cyc_eq_5:
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required
cover property (@(posedge clk) disable iff (toggle) cyc==8)
$display("*COVER: Cyc==8");
cover property (@(posedge clk) disable iff (!toggle) cyc==8)
$stop;
always_ff @ (posedge clk) begin
labeled_icov: cover (cyc==3 || cyc==4);
end
// Immediate cover
labeled_imm0: cover #0 (cyc == 0);
labeled_immf: cover final (cyc == 0);
// Immediate assert
labeled_imas: assert #0 (1);
assert final (1);
//============================================================
// Using a macro and generate
wire reset = (cyc < 2);
`define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn))
genvar i;
generate
for (i=0; i<32; i=i+1)
begin: cycval
CycCover_i: `covclk( cyc[i] );
end
endgenerate
`ifndef verilator // Unsupported
//============================================================
// Using a more complicated property
property C1;
@(posedge clk)
disable iff (!toggle)
cyc==5;
endproperty
cover property (C1) $display("*COVER: Cyc==5");
// Using covergroup
// Note a covergroup is really inheritance of a special system "covergroup" class.
covergroup counter1 @ (posedge cyc);
// Automatic methods: stop(), start(), sample(), set_inst_name()
// Each bin value must be <= 32 bits. Strange.
cyc_value : coverpoint cyc {
}
cyc_bined : coverpoint cyc {
bins zero = {0};
bins low = {1,5};
// Note 5 is also in the bin above. Only the first bin matching is counted.
bins mid = {[5:$]};
// illegal_bins // Has precidence over "first matching bin", creates assertion
// ignore_bins // Not counted, and not part of total
}
toggle : coverpoint (toggle) {
bins off = {0};
bins on = {1};
}
cyc5 : coverpoint (cyc==5) {
bins five = {1};
}
// option.at_least = {number}; // Default 1 - Hits to be considered covered
// option.auto_bin_max = {number}; // Default 64
// option.comment = {string}
// option.goal = {number}; // Default 90%
// option.name = {string}
// option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1)
// option.weight = {number}; // Default 1
// CROSS
value_and_toggle: // else default is __<firstlabel>_X_<secondlabel>_<n>
cross cyc_value, toggle;
endgroup
counter1 c1 = new();
`endif
endmodule
module Sub
(
input clk,
input integer cyc
);
// Simple cover, per-instance
pi_sub:
cover property (@(posedge clk) cyc == 3);
endmodule
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: int_to_fp.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=32 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=11 WIDTH_INT=32 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=52 WIDTH_RESULT=64 clk_en clock dataa result
//VERSION_BEGIN 8.1 cbx_altbarrel_shift 2008:05:19:10:20:21:SJ cbx_altfp_convert 2008:09:12:02:26:36:SJ cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_altsyncram 2008:08:26:11:57:11:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_abs 2008:05:19:10:51:43:SJ cbx_lpm_add_sub 2008:05:19:10:49:01:SJ cbx_lpm_compare 2008:09:01:07:44:05:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_divide 2008:05:21:18:11:28:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_mgl 2008:08:08:15:16:18:SJ cbx_stratix 2008:08:05:17:10:23:SJ cbx_stratixii 2008:08:07:13:54:47:SJ cbx_stratixiii 2008:07:11:13:32:02:SJ cbx_util_mgl 2008:07:18:09:58:54:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix III" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=32 WIDTHDIST=5 aclr clk_en clock data distance result
//VERSION_BEGIN 8.1 cbx_altbarrel_shift 2008:05:19:10:20:21:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources = reg 66
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altbarrel_shift_mvf
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [31:0] data;
input [4:0] distance;
output [31:0] result;
reg [31:0] pipe_wl1c;
reg [31:0] pipe_wl2c;
reg sel_pipel3d1c;
reg sel_pipel4d1c;
wire direction_w;
wire [15:0] pad_w;
wire [191:0] sbit_w;
wire [4:0] sel_w;
// synopsys translate_off
initial
pipe_wl1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipe_wl1c <= 32'b0;
else if (clk_en == 1'b1) pipe_wl1c <= ((({32{(sel_w[2] & (~ direction_w))}} & {sbit_w[91:64], pad_w[3:0]}) | ({32{(sel_w[2] & direction_w)}} & {pad_w[3:0], sbit_w[95:68]})) | ({32{(~ sel_w[2])}} & sbit_w[95:64]));
// synopsys translate_off
initial
pipe_wl2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipe_wl2c <= 32'b0;
else if (clk_en == 1'b1) pipe_wl2c <= ((({32{(sel_w[4] & (~ direction_w))}} & {sbit_w[143:128], pad_w[15:0]}) | ({32{(sel_w[4] & direction_w)}} & {pad_w[15:0], sbit_w[159:144]})) | ({32{(~ sel_w[4])}} & sbit_w[159:128]));
// synopsys translate_off
initial
sel_pipel3d1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipel3d1c <= 1'b0;
else if (clk_en == 1'b1) sel_pipel3d1c <= distance[3];
// synopsys translate_off
initial
sel_pipel4d1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipel4d1c <= 1'b0;
else if (clk_en == 1'b1) sel_pipel4d1c <= distance[4];
assign
direction_w = 1'b0,
pad_w = {16{1'b0}},
result = sbit_w[191:160],
sbit_w = {pipe_wl2c, ((({32{(sel_w[3] & (~ direction_w))}} & {sbit_w[119:96], pad_w[7:0]}) | ({32{(sel_w[3] & direction_w)}} & {pad_w[7:0], sbit_w[127:104]})) | ({32{(~ sel_w[3])}} & sbit_w[127:96])), pipe_wl1c, ((({32{(sel_w[1] & (~ direction_w))}} & {sbit_w[61:32], pad_w[1:0]}) | ({32{(sel_w[1] & direction_w)}} & {pad_w[1:0], sbit_w[63:34]})) | ({32{(~ sel_w[1])}} & sbit_w[63:32])), ((({32{(sel_w[0] & (~ direction_w))}} & {sbit_w[30:0], pad_w[0]}) | ({32{(sel_w[0] & direction_w)}} & {pad_w[0], sbit_w[31:1]})) | ({32{(~ sel_w[0])}} & sbit_w[31:0])), data},
sel_w = {sel_pipel4d1c, sel_pipel3d1c, distance[2:0]};
endmodule //int_to_fp_altbarrel_shift_mvf
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //int_to_fp_altpriority_encoder_3v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //int_to_fp_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder12_q;
wire [0:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
int_to_fp_altpriority_encoder_3v7 altpriority_encoder12
(
.data(data[1:0]),
.q(wire_altpriority_encoder12_q));
int_to_fp_altpriority_encoder_3e8 altpriority_encoder13
(
.data(data[3:2]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
assign
q = {(~ wire_altpriority_encoder13_zero), ((wire_altpriority_encoder13_zero & wire_altpriority_encoder12_q) | ((~ wire_altpriority_encoder13_zero) & wire_altpriority_encoder13_q))};
endmodule //int_to_fp_altpriority_encoder_6v7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
int_to_fp_altpriority_encoder_3e8 altpriority_encoder14
(
.data(data[1:0]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
int_to_fp_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[3:2]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
assign
q = {(~ wire_altpriority_encoder15_zero), ((wire_altpriority_encoder15_zero & wire_altpriority_encoder14_q) | ((~ wire_altpriority_encoder15_zero) & wire_altpriority_encoder15_q))},
zero = (wire_altpriority_encoder14_zero & wire_altpriority_encoder15_zero);
endmodule //int_to_fp_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder10_q;
wire [1:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
int_to_fp_altpriority_encoder_6v7 altpriority_encoder10
(
.data(data[3:0]),
.q(wire_altpriority_encoder10_q));
int_to_fp_altpriority_encoder_6e8 altpriority_encoder11
(
.data(data[7:4]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
assign
q = {(~ wire_altpriority_encoder11_zero), (({2{wire_altpriority_encoder11_zero}} & wire_altpriority_encoder10_q) | ({2{(~ wire_altpriority_encoder11_zero)}} & wire_altpriority_encoder11_q))};
endmodule //int_to_fp_altpriority_encoder_bv7
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
wire [1:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
int_to_fp_altpriority_encoder_6e8 altpriority_encoder16
(
.data(data[3:0]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
int_to_fp_altpriority_encoder_6e8 altpriority_encoder17
(
.data(data[7:4]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
assign
q = {(~ wire_altpriority_encoder17_zero), (({2{wire_altpriority_encoder17_zero}} & wire_altpriority_encoder16_q) | ({2{(~ wire_altpriority_encoder17_zero)}} & wire_altpriority_encoder17_q))},
zero = (wire_altpriority_encoder16_zero & wire_altpriority_encoder17_zero);
endmodule //int_to_fp_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder8_q;
wire [2:0] wire_altpriority_encoder9_q;
wire wire_altpriority_encoder9_zero;
int_to_fp_altpriority_encoder_bv7 altpriority_encoder8
(
.data(data[7:0]),
.q(wire_altpriority_encoder8_q));
int_to_fp_altpriority_encoder_be8 altpriority_encoder9
(
.data(data[15:8]),
.q(wire_altpriority_encoder9_q),
.zero(wire_altpriority_encoder9_zero));
assign
q = {(~ wire_altpriority_encoder9_zero), (({3{wire_altpriority_encoder9_zero}} & wire_altpriority_encoder8_q) | ({3{(~ wire_altpriority_encoder9_zero)}} & wire_altpriority_encoder9_q))};
endmodule //int_to_fp_altpriority_encoder_r08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 8.1 cbx_altpriority_encoder 2008:05:19:11:01:44:SJ cbx_mgl 2008:08:08:15:16:18:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
wire [2:0] wire_altpriority_encoder19_q;
wire wire_altpriority_encoder19_zero;
int_to_fp_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[7:0]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
int_to_fp_altpriority_encoder_be8 altpriority_encoder19
(
.data(data[15:8]),
.q(wire_altpriority_encoder19_q),
.zero(wire_altpriority_encoder19_zero));
assign
q = {(~ wire_altpriority_encoder19_zero), (({3{wire_altpriority_encoder19_zero}} & wire_altpriority_encoder18_q) | ({3{(~ wire_altpriority_encoder19_zero)}} & wire_altpriority_encoder19_q))},
zero = (wire_altpriority_encoder18_zero & wire_altpriority_encoder19_zero);
endmodule //int_to_fp_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altpriority_encoder_qb6
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder6_q;
wire [3:0] wire_altpriority_encoder7_q;
wire wire_altpriority_encoder7_zero;
int_to_fp_altpriority_encoder_r08 altpriority_encoder6
(
.data(data[15:0]),
.q(wire_altpriority_encoder6_q));
int_to_fp_altpriority_encoder_rf8 altpriority_encoder7
(
.data(data[31:16]),
.q(wire_altpriority_encoder7_q),
.zero(wire_altpriority_encoder7_zero));
assign
q = {(~ wire_altpriority_encoder7_zero), (({4{wire_altpriority_encoder7_zero}} & wire_altpriority_encoder6_q) | ({4{(~ wire_altpriority_encoder7_zero)}} & wire_altpriority_encoder7_q))};
endmodule //int_to_fp_altpriority_encoder_qb6
//synthesis_resources = lpm_add_sub 2 lpm_compare 1 reg 288
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module int_to_fp_altfp_convert_bnn
(
clk_en,
clock,
dataa,
result) ;
input clk_en;
input clock;
input [31:0] dataa;
output [63:0] result;
wire [31:0] wire_altbarrel_shift5_result;
wire [4:0] wire_altpriority_encoder2_q;
reg [10:0] exponent_bus_pre_reg;
reg [10:0] exponent_bus_pre_reg2;
reg [10:0] exponent_bus_pre_reg3;
reg [30:0] mag_int_a_reg;
reg [30:0] mag_int_a_reg2;
reg [52:0] mantissa_pre_round_reg;
reg [4:0] priority_encoder_reg;
reg [63:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [30:0] wire_add_sub1_result;
wire [10:0] wire_add_sub3_result;
wire wire_cmpr4_alb;
wire aclr;
wire [10:0] bias_value_w;
wire [10:0] const_bias_value_add_width_int_w;
wire [10:0] exceptions_value;
wire [10:0] exponent_bus;
wire [10:0] exponent_bus_pre;
wire [10:0] exponent_output_w;
wire [10:0] exponent_rounded;
wire [10:0] exponent_zero_w;
wire [30:0] int_a;
wire [30:0] int_a_2s;
wire [30:0] invert_int_a;
wire [4:0] leading_zeroes;
wire [30:0] mag_int_a;
wire [51:0] mantissa_bus;
wire [52:0] mantissa_pre_round;
wire [52:0] mantissa_rounded;
wire max_neg_value_selector;
wire [10:0] max_neg_value_w;
wire [10:0] minus_leading_zero;
wire [31:0] prio_mag_int_a;
wire [63:0] result_w;
wire [30:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [5:0] zero_padding_w;
int_to_fp_altbarrel_shift_mvf altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
int_to_fp_altpriority_encoder_qb6 altpriority_encoder2
(
.data(prio_mag_int_a),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 11'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 31'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 53'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 5'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 64'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(31'b0000000000000000000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 31,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 11,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 11,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
bias_value_w = 11'b01111111111,
const_bias_value_add_width_int_w = 11'b10000011101,
exceptions_value = (({11{(~ max_neg_value_selector)}} & exponent_zero_w) | ({11{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({11{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({11{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = exponent_bus_pre_reg,
exponent_zero_w = {11{1'b0}},
int_a = dataa[30:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({31{(~ sign_int_a)}} & int_a) | ({31{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[51:0],
mantissa_pre_round = {shifted_mag_int_a[30:0], 22'b0000000000000000000000},
mantissa_rounded = mantissa_pre_round_reg,
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 11'b10000011110,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
shifted_mag_int_a = wire_altbarrel_shift5_result[30:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[31],
zero_padding_w = {6{1'b0}};
endmodule //int_to_fp_altfp_convert_bnn
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module int_to_fp (
clk_en,
clock,
dataa,
result);
input clk_en;
input clock;
input [31:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
int_to_fp_altfp_convert_bnn int_to_fp_altfp_convert_bnn_component (
.dataa (dataa),
.clk_en (clk_en),
.clock (clock),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "52"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "64"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT GND "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT GND "dataa[31..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT GND "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL int_to_fp.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
/* verilator lint_off STMTDLY */
/* verilator lint_off WIDTH */
module PLLE2_ADV #(
parameter BANDWIDTH = "OPTIMIZED",
parameter integer CLKFBOUT_MULT = 5,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter integer CLKOUT0_DIVIDE = 1,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKOUT0,
output CLKOUT1,
output CLKOUT2,
output CLKOUT3,
output CLKOUT4,
output CLKOUT5,
output [15:0] DO,
output DRDY,
output LOCKED,
output CLKFBOUT,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PWRDWN,
input RST
);
//#LOCAL DERIVED PARAMETERS
localparam real VCO_PERIOD = (CLKIN1_PERIOD * DIVCLK_DIVIDE) / CLKFBOUT_MULT;
localparam real CLK0_DELAY = VCO_PERIOD * CLKOUT0_DIVIDE * (CLKOUT0_PHASE/360);
localparam real CLK1_DELAY = VCO_PERIOD * CLKOUT1_DIVIDE * (CLKOUT1_PHASE/360);
localparam real CLK2_DELAY = VCO_PERIOD * CLKOUT2_DIVIDE * (CLKOUT2_PHASE/360);
localparam real CLK3_DELAY = VCO_PERIOD * CLKOUT3_DIVIDE * (CLKOUT3_PHASE/360);
localparam real CLK4_DELAY = VCO_PERIOD * CLKOUT4_DIVIDE * (CLKOUT4_PHASE/360);
localparam real CLK5_DELAY = VCO_PERIOD * CLKOUT5_DIVIDE * (CLKOUT5_PHASE/360);
localparam phases = CLKFBOUT_MULT / DIVCLK_DIVIDE;
//########################################################################
//# POR
//########################################################################
//ugly POR reset
reg POR;
initial
begin
POR=1'b1;
#1
POR=1'b0;
end
//async reset
wire reset;
assign reset = POR | RST;
//########################################################################
//# CLOCK MULTIPLIER
//########################################################################
//TODO: implement DIVCLK_DIVIDE
//
integer j;
reg [2*phases-1:0] delay;
always @ (CLKIN1 or reset)
if(reset)
for(j=0; j<(2*phases); j=j+1)
delay[j] <= 1'b0;
else
for(j=0; j<(2*phases); j=j+1)
delay[j] <= #(CLKIN1_PERIOD*j/(2*phases)) CLKIN1;
reg [(phases)-1:0] clk_comb;
always @ (delay)
begin
for(j=0; j<(phases); j=j+1)
clk_comb[j] <= ~reset & delay[2*j] & ~delay[2*j+1];
end
reg vco_clk;
integer k;
always @*
begin
vco_clk = 1'b0;
for(k=0; k<(phases); k=k+1)
vco_clk = vco_clk | clk_comb[k];
end
//##############
//#DIVIDERS
//##############
wire [3:0] DIVCFG[5:0];
wire [5:0] CLKOUT_DIV;
assign DIVCFG[0] = $clog2(CLKOUT0_DIVIDE);
assign DIVCFG[1] = $clog2(CLKOUT1_DIVIDE);
assign DIVCFG[2] = $clog2(CLKOUT2_DIVIDE);
assign DIVCFG[3] = $clog2(CLKOUT3_DIVIDE);
assign DIVCFG[4] = $clog2(CLKOUT4_DIVIDE);
assign DIVCFG[5] = $clog2(CLKOUT5_DIVIDE);
genvar i;
generate for(i=0; i<6; i=i+1)
begin : gen_clkdiv
CLKDIV clkdiv (// Outputs
.clkout (CLKOUT_DIV[i]),
// Inputs
.clkin (vco_clk),
.divcfg (DIVCFG[i]),
.reset (reset));
end
endgenerate
reg [5:0] CLKOUT_DIV_LOCK;
`ifdef TARGET_VERILATOR
initial
begin
$display("ERROR: PLL divider not implemented");
end
`else
always @ (posedge (CLKIN1 & vco_clk) or negedge (CLKIN1&~vco_clk))
begin
CLKOUT_DIV_LOCK[5:0] = CLKOUT_DIV[5:0];
end
`endif
//##############
//#SUB PHASE DELAY
//##############
reg CLKOUT0;
reg CLKOUT1;
reg CLKOUT2;
reg CLKOUT3;
reg CLKOUT4;
reg CLKOUT5;
always @ (CLKOUT_DIV_LOCK)
begin
CLKOUT0 = #(CLK0_DELAY) ~reset & CLKOUT_DIV_LOCK[0];
CLKOUT1 = #(CLK1_DELAY) ~reset & CLKOUT_DIV_LOCK[1];
CLKOUT2 = #(CLK2_DELAY) ~reset & CLKOUT_DIV_LOCK[2];
CLKOUT3 = #(CLK3_DELAY) ~reset & CLKOUT_DIV_LOCK[3];
CLKOUT4 = #(CLK4_DELAY) ~reset & CLKOUT_DIV_LOCK[4];
CLKOUT5 = #(CLK5_DELAY) ~reset & CLKOUT_DIV_LOCK[5];
end
//##############
//#DUMMY DRIVES
//##############
assign CLKFBOUT=CLKIN1;
//###########################
//#SANITY CHECK LOCK COUNTER
//############################
localparam LCW=4;
reg [LCW-1:0] lock_counter;
always @ (posedge CLKIN1 or posedge reset)
if(reset)
lock_counter[LCW-1:0] <= {(LCW){1'b1}};
else if(~LOCKED)
lock_counter[LCW-1:0] <= lock_counter[LCW-1:0] - 1'b1;
assign LOCKED = ~(|lock_counter[LCW-1:0]);
endmodule // PLLE2_ADV
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
// ###############################################################
// # FUNCTION: Synchronous clock divider that divides by integer
// ###############################################################
module oh_clockdiv_model(/*AUTOARG*/
// Outputs
clkout,
// Inputs
clkin, divcfg, reset
);
input clkin; // Input clock
input [3:0] divcfg; // Divide factor (1-128)
input reset; // Counter init
output clkout; // Divided clock phase aligned with clkin
reg clkout_reg;
reg [7:0] counter;
reg [7:0] divcfg_dec;
reg [3:0] divcfg_reg;
wire div_bp;
wire posedge_match;
wire negedge_match;
// ###################
// # Decode divcfg
// ###################
always @ (divcfg[3:0])
casez (divcfg[3:0])
4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
4'b0111 : divcfg_dec[7:0] = 8'b10000000; // Divide by 128
default : divcfg_dec[7:0] = 8'b00000000; // others
endcase
always @ (posedge clkin or posedge reset)
if(reset)
counter[7:0] <= 8'b00000001;
else if(posedge_match)
counter[7:0] <= 8'b00000001;// Self resetting
else
counter[7:0] <= (counter[7:0] + 8'b00000001);
assign posedge_match = (counter[7:0]==divcfg_dec[7:0]);
assign negedge_match = (counter[7:0]=={1'b0,divcfg_dec[7:1]});
always @ (posedge clkin or posedge reset)
if(reset)
clkout_reg <= 1'b0;
else if(posedge_match)
clkout_reg <= 1'b1;
else if(negedge_match)
clkout_reg <= 1'b0;
//Divide by one bypass
assign div_bp = (divcfg[3:0]==4'b0000);
assign clkout = div_bp ? clkin : clkout_reg;
endmodule // oh_clockdiv
|
// $Id: //acds/main/ip/sopc/components/primitives/altera_std_synchronizer/altera_std_synchronizer.v#8 $
// $Revision: #8 $
// $Date: 2009/02/18 $
// $Author: pscheidt $
//-----------------------------------------------------------------------------
//
// File: altera_std_synchronizer_nocut.v
//
// Abstract: Single bit clock domain crossing synchronizer. Exactly the same
// as altera_std_synchronizer.v, except that the embedded false
// path constraint is removed in this module. If you use this
// module, you will have to apply the appropriate timing
// constraints.
//
// We expect to make this a standard Quartus atom eventually.
//
// Composed of two or more flip flops connected in series.
// Random metastable condition is simulated when the
// __ALTERA_STD__METASTABLE_SIM macro is defined.
// Use +define+__ALTERA_STD__METASTABLE_SIM argument
// on the Verilog simulator compiler command line to
// enable this mode. In addition, define the macro
// __ALTERA_STD__METASTABLE_SIM_VERBOSE to get console output
// with every metastable event generated in the synchronizer.
//
// Copyright (C) Altera Corporation 2009, All Rights Reserved
//-----------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_std_synchronizer_nocut (
clk,
reset_n,
din,
dout
);
parameter depth = 3; // This value must be >= 2 !
input clk;
input reset_n;
input din;
output dout;
// QuartusII synthesis directives:
// 1. Preserve all registers ie. do not touch them.
// 2. Do not merge other flip-flops with synchronizer flip-flops.
// QuartusII TimeQuest directives:
// 1. Identify all flip-flops in this module as members of the synchronizer
// to enable automatic metastability MTBF analysis.
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON "} *) reg din_s1;
(* altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON"} *) reg [depth-2:0] dreg;
//synthesis translate_off
initial begin
if (depth <2) begin
$display("%m: Error: synchronizer length: %0d less than 2.", depth);
end
end
// the first synchronizer register is either a simple D flop for synthesis
// and non-metastable simulation or a D flop with a method to inject random
// metastable events resulting in random delay of [0,1] cycles
`ifdef __ALTERA_STD__METASTABLE_SIM
reg[31:0] RANDOM_SEED = 123456;
wire next_din_s1;
wire dout;
reg din_last;
reg random;
event metastable_event; // hook for debug monitoring
initial begin
$display("%m: Info: Metastable event injection simulation mode enabled");
end
always @(posedge clk) begin
if (reset_n == 0)
random <= $random(RANDOM_SEED);
else
random <= $random;
end
assign next_din_s1 = (din_last ^ din) ? random : din;
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_last <= 1'b0;
else
din_last <= din;
end
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= next_din_s1;
end
`else
//synthesis translate_on
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
din_s1 <= 1'b0;
else
din_s1 <= din;
end
//synthesis translate_off
`endif
`ifdef __ALTERA_STD__METASTABLE_SIM_VERBOSE
always @(*) begin
if (reset_n && (din_last != din) && (random != din)) begin
$display("%m: Verbose Info: metastable event @ time %t", $time);
->metastable_event;
end
end
`endif
//synthesis translate_on
// the remaining synchronizer registers form a simple shift register
// of length depth-1
generate
if (depth < 3) begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= din_s1;
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (reset_n == 0)
dreg <= {depth-1{1'b0}};
else
dreg <= {dreg[depth-3:0], din_s1};
end
end
endgenerate
assign dout = dreg[depth-2];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_TB_V
`define SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_TB_V
/**
* udp_isolatch_pp$PKG$s: Power isolating latch. Includes VPWR, KAPWR,
* and VGND power pins with active low sleep
* pin (SLEEP_B).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__udp_isolatch_pp_pkg_s.v"
module top();
// Inputs are registered
reg D;
reg SLEEP_B;
reg KAPWR;
reg VGND;
reg VPWR;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
KAPWR = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 KAPWR = 1'b0;
#60 SLEEP_B = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 KAPWR = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 KAPWR = 1'b0;
#260 SLEEP_B = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SLEEP_B = 1'b1;
#380 KAPWR = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SLEEP_B = 1'bx;
#480 KAPWR = 1'bx;
#500 D = 1'bx;
end
sky130_fd_sc_hs__udp_isolatch_pp$PKG$s dut (.D(D), .SLEEP_B(SLEEP_B), .KAPWR(KAPWR), .VGND(VGND), .VPWR(VPWR), .Q(Q));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_ISOLATCH_PP_PKG_S_TB_V
|
//deps: control.v
`include "cpu_constants.vh"
module control_tb;
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To uut of control.v
reg en; // To uut of control.v
reg en_mem; // To uut of control.v
reg imm; // To uut of control.v
reg mem_wait; // To uut of control.v
reg rst; // To uut of control.v
reg should_branch; // To uut of control.v
// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`CONTROL_BIT_MAX:0] control_o; // From uut of control.v
wire [1:0] pc_op; // From uut of control.v
// End of automatics
control uut(/*AUTOINST*/
// Outputs
.control_o (control_o[`CONTROL_BIT_MAX:0]),
.pc_op (pc_op[1:0]),
// Inputs
.clk (clk),
.en (en),
.rst (rst),
.en_mem (en_mem),
.mem_wait (mem_wait),
.should_branch (should_branch),
.imm (imm));
initial begin
$dumpfile("dump.vcd");
$dumpvars;
clk = 0;
rst = 1;
en = 0;
en_mem = 0;
imm = 0;
mem_wait = 0;
should_branch = 0;
#20 rst = 0;
en = 1;
#300 $finish;
end // initial begin
always #5 clk <= ~clk;
always @(posedge clk) begin
if(control_o[`BIT_ALU])
en_mem <= ~en_mem;
if(control_o[`BIT_REG_WR])
should_branch <= ~should_branch;
if(control_o[`BIT_ALU])
imm <= ~imm;
end
endmodule // control_tb
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.15 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.12 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.11 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.10 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.9 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.8 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban ([email protected])
// Company: Flextronics Semiconductor
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_wb (clk, wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
input [3:0] wb_sel_i;
input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
`ifdef DATA_BUS_WIDTH_8
input [7:0] wb_dat_i; //input WISHBONE bus
output [7:0] wb_dat_o;
reg [7:0] wb_dat_o;
wire [7:0] wb_dat_i;
reg [7:0] wb_dat_is;
`else // for 32 data bus mode
input [31:0] wb_dat_i; //input WISHBONE bus
output [31:0] wb_dat_o;
reg [31:0] wb_dat_o;
wire [31:0] wb_dat_i;
reg [31:0] wb_dat_is;
`endif // !`ifdef DATA_BUS_WIDTH_8
output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
output [7:0] wb_dat8_i;
input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
reg [7:0] wb_dat8_i;
wire [7:0] wb_dat8_o;
wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
reg wb_we_is;
reg wb_cyc_is;
reg wb_stb_is;
reg [3:0] wb_sel_is;
wire [3:0] wb_sel_i;
reg wre ;// timing control signal for write or read enable
// wb_ack_o FSM
reg [1:0] wbstate;
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_ack_o <= #1 1'b0;
wbstate <= #1 0;
wre <= #1 1'b1;
end else
case (wbstate)
0: begin
if (wb_stb_is & wb_cyc_is) begin
wre <= #1 0;
wbstate <= #1 1;
wb_ack_o <= #1 1;
end else begin
wre <= #1 1;
wb_ack_o <= #1 0;
end
end
1: begin
wb_ack_o <= #1 0;
wbstate <= #1 2;
wre <= #1 0;
end
2,3: begin
wb_ack_o <= #1 0;
wbstate <= #1 0;
wre <= #1 0;
end
endcase
assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
// Sample input signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
wb_adr_is <= #1 0;
wb_we_is <= #1 0;
wb_cyc_is <= #1 0;
wb_stb_is <= #1 0;
wb_dat_is <= #1 0;
wb_sel_is <= #1 0;
end else begin
wb_adr_is <= #1 wb_adr_i;
wb_we_is <= #1 wb_we_i;
wb_cyc_is <= #1 wb_cyc_i;
wb_stb_is <= #1 wb_stb_i;
wb_dat_is <= #1 wb_dat_i;
wb_sel_is <= #1 wb_sel_i;
end
`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 0;
else
wb_dat_o <= #1 wb_dat8_o;
always @(wb_dat_is)
wb_dat8_i = wb_dat_is;
assign wb_adr_int = wb_adr_is;
`else // 32-bit bus
// put output to the correct byte in 32 bits using select line
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
wb_dat_o <= #1 0;
else if (re_o)
case (wb_sel_is)
4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
default: wb_dat_o <= #1 0;
endcase // case(wb_sel_i)
reg [1:0] wb_adr_int_lsb;
always @(wb_sel_is or wb_dat_is)
begin
case (wb_sel_is)
4'b0001 : wb_dat8_i = wb_dat_is[7:0];
4'b0010 : wb_dat8_i = wb_dat_is[15:8];
4'b0100 : wb_dat8_i = wb_dat_is[23:16];
4'b1000 : wb_dat8_i = wb_dat_is[31:24];
default : wb_dat8_i = wb_dat_is[7:0];
endcase // case(wb_sel_i)
`ifdef LITLE_ENDIAN
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h0;
4'b0010 : wb_adr_int_lsb = 2'h1;
4'b0100 : wb_adr_int_lsb = 2'h2;
4'b1000 : wb_adr_int_lsb = 2'h3;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
`else
case (wb_sel_is)
4'b0001 : wb_adr_int_lsb = 2'h3;
4'b0010 : wb_adr_int_lsb = 2'h2;
4'b0100 : wb_adr_int_lsb = 2'h1;
4'b1000 : wb_adr_int_lsb = 2'h0;
default : wb_adr_int_lsb = 2'h0;
endcase // case(wb_sel_i)
`endif
end
assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb};
`endif // !`ifdef DATA_BUS_WIDTH_8
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
sys_rst,
sys_clk_p,
sys_clk_n,
uart_sin,
uart_sout,
ddr3_reset_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ras_n,
ddr3_we_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
sgmii_rxp,
sgmii_rxn,
sgmii_txp,
sgmii_txn,
phy_rstn,
mgt_clk_p,
mgt_clk_n,
mdio_mdc,
mdio_mdio,
linear_flash_addr,
linear_flash_adv_ldn,
linear_flash_ce_n,
linear_flash_dq_io,
linear_flash_oen,
linear_flash_wen,
fan_pwm,
gpio_lcd,
gpio_bd,
iic_rstn,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
adc_irq,
adc_fd,
spi_adc_csn,
spi_adc_clk,
spi_adc_sdio,
spi_ext_csn_0,
spi_ext_csn_1,
spi_ext_clk,
spi_ext_sdio);
input sys_rst;
input sys_clk_p;
input sys_clk_n;
input uart_sin;
output uart_sout;
output ddr3_reset_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output ddr3_ras_n;
output ddr3_we_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
input sgmii_rxp;
input sgmii_rxn;
output sgmii_txp;
output sgmii_txn;
output phy_rstn;
input mgt_clk_p;
input mgt_clk_n;
output mdio_mdc;
inout mdio_mdio;
output [26:1] linear_flash_addr;
output linear_flash_adv_ldn;
output linear_flash_ce_n;
inout [15:0] linear_flash_dq_io;
output linear_flash_oen;
output linear_flash_wen;
output fan_pwm;
inout [ 6:0] gpio_lcd;
inout [20:0] gpio_bd;
output iic_rstn;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 7:0] rx_data_p;
input [ 7:0] rx_data_n;
inout adc_irq;
inout adc_fd;
output spi_adc_csn;
output spi_adc_clk;
inout spi_adc_sdio;
output spi_ext_csn_0;
output spi_ext_csn_1;
output spi_ext_clk;
inout spi_ext_sdio;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 7:0] spi_csn;
wire spi_mosi;
wire spi_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
// spi
assign spi_adc_csn = spi_csn[0];
assign spi_adc_clk = spi_clk;
assign spi_ext_csn_0 = spi_csn[1];
assign spi_ext_csn_1 = spi_csn[2];
assign spi_ext_clk = spi_clk;
// default logic
assign fan_pwm = 1'b1;
assign iic_rstn = 1'b1;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
fmcadc2_spi i_fmcadc2_spi (
.spi_adc_csn (spi_adc_csn),
.spi_ext_csn_0 (spi_ext_csn_0),
.spi_ext_csn_1 (spi_ext_csn_1),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_adc_sdio (spi_adc_sdio),
.spi_ext_sdio (spi_ext_sdio));
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf (
.dio_t (gpio_t[33:32]),
.dio_i (gpio_o[33:32]),
.dio_o (gpio_i[33:32]),
.dio_p ({ adc_irq, // 33
adc_fd})); // 32
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio0_i (gpio_i[31:0]),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio1_i (gpio_i[63:32]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio_lcd_tri_io (gpio_lcd),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.mb_intr_06 (1'd0),
.mb_intr_07 (1'd0),
.mb_intr_08 (1'd0),
.mb_intr_14 (1'd0),
.mb_intr_15 (1'd0),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mgt_clk_clk_n (mgt_clk_n),
.mgt_clk_clk_p (mgt_clk_p),
.phy_rstn (phy_rstn),
.phy_sd (1'b1),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.sgmii_rxn (sgmii_rxn),
.sgmii_rxp (sgmii_rxp),
.sgmii_txn (sgmii_txn),
.sgmii_txp (sgmii_txp),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (spi_mosi),
.spi_sdo_o (spi_mosi),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module user_logic (
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_frame_p,
adc_frame_n,
dma_clk,
dma_valid,
dma_data,
dma_be,
dma_last,
dma_ready,
delay_clk,
dma_dbg_data,
dma_dbg_trigger,
adc_dbg_data,
adc_dbg_trigger,
adc_clk,
adc_mon_valid,
adc_mon_data,
Bus2IP_Clk,
Bus2IP_Resetn,
Bus2IP_Data,
Bus2IP_BE,
Bus2IP_RdCE,
Bus2IP_WrCE,
IP2Bus_Data,
IP2Bus_RdAck,
IP2Bus_WrAck,
IP2Bus_Error);
parameter C_NUM_REG = 32;
parameter C_SLV_DWIDTH = 32;
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_frame_p;
input adc_frame_n;
input dma_clk;
output dma_valid;
output [63:0] dma_data;
output [ 7:0] dma_be;
output dma_last;
input dma_ready;
input delay_clk;
output [63:0] dma_dbg_data;
output [ 7:0] dma_dbg_trigger;
output [63:0] adc_dbg_data;
output [ 7:0] adc_dbg_trigger;
output adc_clk;
output adc_mon_valid;
output [143:0] adc_mon_data;
input Bus2IP_Clk;
input Bus2IP_Resetn;
input [31:0] Bus2IP_Data;
input [ 3:0] Bus2IP_BE;
input [31:0] Bus2IP_RdCE;
input [31:0] Bus2IP_WrCE;
output [31:0] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
reg up_sel;
reg up_rwn;
reg [ 4:0] up_addr;
reg [31:0] up_wdata;
reg IP2Bus_RdAck;
reg IP2Bus_WrAck;
reg [31:0] IP2Bus_Data;
reg IP2Bus_Error;
wire [31:0] up_rwce_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
assign up_rwce_s = (Bus2IP_RdCE == 0) ? Bus2IP_WrCE : Bus2IP_RdCE;
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
up_sel <= 'd0;
up_rwn <= 'd0;
up_addr <= 'd0;
up_wdata <= 'd0;
end else begin
up_sel <= (up_rwce_s == 0) ? 1'b0 : 1'b1;
up_rwn <= (Bus2IP_RdCE == 0) ? 1'b0 : 1'b1;
case (up_rwce_s)
32'h80000000: up_addr <= 5'h00;
32'h40000000: up_addr <= 5'h01;
32'h20000000: up_addr <= 5'h02;
32'h10000000: up_addr <= 5'h03;
32'h08000000: up_addr <= 5'h04;
32'h04000000: up_addr <= 5'h05;
32'h02000000: up_addr <= 5'h06;
32'h01000000: up_addr <= 5'h07;
32'h00800000: up_addr <= 5'h08;
32'h00400000: up_addr <= 5'h09;
32'h00200000: up_addr <= 5'h0a;
32'h00100000: up_addr <= 5'h0b;
32'h00080000: up_addr <= 5'h0c;
32'h00040000: up_addr <= 5'h0d;
32'h00020000: up_addr <= 5'h0e;
32'h00010000: up_addr <= 5'h0f;
32'h00008000: up_addr <= 5'h10;
32'h00004000: up_addr <= 5'h11;
32'h00002000: up_addr <= 5'h12;
32'h00001000: up_addr <= 5'h13;
32'h00000800: up_addr <= 5'h14;
32'h00000400: up_addr <= 5'h15;
32'h00000200: up_addr <= 5'h16;
32'h00000100: up_addr <= 5'h17;
32'h00000080: up_addr <= 5'h18;
32'h00000040: up_addr <= 5'h19;
32'h00000020: up_addr <= 5'h1a;
32'h00000010: up_addr <= 5'h1b;
32'h00000008: up_addr <= 5'h1c;
32'h00000004: up_addr <= 5'h1d;
32'h00000002: up_addr <= 5'h1e;
32'h00000001: up_addr <= 5'h1f;
default: up_addr <= 5'h1f;
endcase
up_wdata <= Bus2IP_Data;
end
end
always @(negedge Bus2IP_Resetn or posedge Bus2IP_Clk) begin
if (Bus2IP_Resetn == 0) begin
IP2Bus_RdAck <= 'd0;
IP2Bus_WrAck <= 'd0;
IP2Bus_Data <= 'd0;
IP2Bus_Error <= 'd0;
end else begin
IP2Bus_RdAck <= (Bus2IP_RdCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_WrAck <= (Bus2IP_WrCE == 0) ? 1'b0 : up_ack_s;
IP2Bus_Data <= up_rdata_s;
IP2Bus_Error <= 'd0;
end
end
cf_adc_8c i_adc_8c (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_frame_p (adc_frame_p),
.adc_frame_n (adc_frame_n),
.dma_clk (dma_clk),
.dma_valid (dma_valid),
.dma_data (dma_data),
.dma_be (dma_be),
.dma_last (dma_last),
.dma_ready (dma_ready),
.up_rstn (Bus2IP_Resetn),
.up_clk (Bus2IP_Clk),
.up_sel (up_sel),
.up_rwn (up_rwn),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s),
.delay_clk (delay_clk),
.dma_dbg_data (dma_dbg_data),
.dma_dbg_trigger (dma_dbg_trigger),
.adc_dbg_data (adc_dbg_data),
.adc_dbg_trigger (adc_dbg_trigger),
.adc_clk (adc_clk),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// -- (c) Copyright 1995 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the fifo_generator wrapper file when simulating
// the core. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_fifo_gen #(
parameter C_FAMILY = "virtex7",
parameter integer C_COMMON_CLOCK = 1,
parameter integer C_SYNCHRONIZER_STAGE = 3,
parameter integer C_FIFO_DEPTH_LOG = 5,
parameter integer C_FIFO_WIDTH = 64,
parameter C_FIFO_TYPE = "lut"
)(
clk,
rst,
wr_clk,
wr_en,
wr_ready,
wr_data,
rd_clk,
rd_en,
rd_valid,
rd_data);
input clk;
input wr_clk;
input rd_clk;
input rst;
input [C_FIFO_WIDTH-1 : 0] wr_data;
input wr_en;
input rd_en;
output [C_FIFO_WIDTH-1 : 0] rd_data;
output wr_ready;
output rd_valid;
wire full;
wire empty;
wire rd_valid = ~empty;
wire wr_ready = ~full;
localparam C_MEMORY_TYPE = (C_FIFO_TYPE == "bram")? 1 : 2;
localparam C_IMPLEMENTATION_TYPE = (C_COMMON_CLOCK == 1)? 0 : 2;
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(C_COMMON_CLOCK),
.C_DIN_WIDTH(C_FIFO_WIDTH),
.C_DOUT_WIDTH(C_FIFO_WIDTH),
.C_FAMILY(C_FAMILY),
.C_IMPLEMENTATION_TYPE(C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE(C_MEMORY_TYPE),
.C_RD_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_RD_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_WR_DEPTH(1<<C_FIFO_DEPTH_LOG),
.C_WR_PNTR_WIDTH(C_FIFO_DEPTH_LOG),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(6),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(6),
.C_RD_FREQ(1),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(6),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.clk(clk),
.din(wr_data),
.dout(rd_data),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_empty(),
.almost_full(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(10'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(10'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.data_count(),
.dbiterr(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(),
.m_axi_arburst(),
.m_axi_arcache(),
.m_axi_arid(),
.m_axi_arlen(),
.m_axi_arlock(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arready(1'b0),
.m_axi_arregion(),
.m_axi_arsize(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_awaddr(),
.m_axi_awburst(),
.m_axi_awcache(),
.m_axi_awid(),
.m_axi_awlen(),
.m_axi_awlock(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awready(1'b0),
.m_axi_awregion(),
.m_axi_awsize(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_bid(4'b0),
.m_axi_bready(),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata(64'b0),
.m_axi_rid(4'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(),
.m_axi_rresp(2'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(),
.m_axi_wid(),
.m_axi_wlast(),
.m_axi_wready(1'b0),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full(),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.rd_data_count(),
.rd_rst(1'b0),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arburst(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arid(4'b0),
.s_axi_arlen(8'b0),
.s_axi_arlock(2'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arready(),
.s_axi_arregion(4'b0),
.s_axi_arsize(3'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awburst(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awid(4'b0),
.s_axi_awlen(8'b0),
.s_axi_awlock(2'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awready(),
.s_axi_awregion(4'b0),
.s_axi_awsize(3'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(),
.s_axi_bready(1'b0),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_rdata(),
.s_axi_rid(),
.s_axi_rlast(),
.s_axi_rready(1'b0),
.s_axi_rresp(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_wdata(64'b0),
.s_axi_wid(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(),
.s_axi_wstrb(8'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.sbiterr(),
.srst(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_data_count(),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endmodule
|
// Copyright (C) 2013 Simon Que
//
// This file is part of DuinoCube.
//
// DuinoCube is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// DuinoCube is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with DuinoCube. If not, see <http://www.gnu.org/licenses/>.
// Test bench for registers.
module Registers_Test;
parameter ADDR_WIDTH=8;
parameter DATA_WIDTH=16;
reg clk; // System clock
reg reset; // System reset
reg en; // Access enable
reg rd; // Read enable
reg wr; // Write enable
reg byte_lo; // Low byte enable
reg byte_hi; // High byte enable
reg [ADDR_WIDTH-1:0] addr;
reg [DATA_WIDTH-1:0] data_in;
wire [DATA_WIDTH-1:0] data_out;
Registers #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH))
registers(.reset(reset),
.en(en),
.rd(rd),
.wr(wr),
.be({byte_hi, byte_lo}),
.addr(addr),
.data_in(data_in),
.data_out(data_out));
// Generate clock.
always
#1 clk = ~clk;
integer i;
integer stage = 0;
initial begin
clk = 0;
reset = 0;
byte_hi = 1;
byte_lo = 1;
en = 0;
rd = 0;
wr = 0;
// Reset
#5 reset = 1;
#1 reset = 0;
#5 stage = 1;
#1 read_test();
#1 addr = 'bx;
// Test some writes
#5 stage = 2;
#1 write16(0, 'hdead);
#1 write16(2, 'hbeef);
#1 write16(4, 'hcafe);
#1 write16(8, 'hface);
#1 write16(16, 'hbead);
#1 write16(18, 'hfade);
#1 write16(24, 'hdeaf);
#1 write16(26, 'hface);
#1 write16(28, 'hface);
#1 write16(30, 'hface);
#1 addr = 'bx;
// Test some reads
#5 stage = 3;
#1 read_test();
#1 addr = 'bx;
// Test some byte writes
#5 stage = 4;
for (i = 0; i < 15; i = i + 1)
begin
#1 write8(i * 2, 'h0000);
#1 write8(i * 2 + 1, 'hffff);
end
// Test some reads
#5 stage = 5;
#1 read_test();
end
// Task to write a word.
task write16;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = data_arg;
#1 en = 1; rd = 0; wr = 1; byte_lo = 1; byte_hi = 1;
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
// Task to write a byte.
task write8;
input [ADDR_WIDTH-1:0] addr_arg;
input [DATA_WIDTH/2-1:0] data_arg;
begin
addr = addr_arg >> 1;
data_in = {data_arg, data_arg};
#1 en = 1; rd = 0; wr = 1; byte_lo = ~addr_arg[0]; byte_hi = addr_arg[0];
#1 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0; byte_lo = 0; byte_hi = 0;
end
endtask
// Task to read a word.
task read;
input [ADDR_WIDTH-1:0] addr_arg;
begin
addr = addr_arg >> 1;
data_in = 'bz;
#1 en = 1; rd = 1; wr = 0;
#3 en = 1; rd = 0; wr = 0;
#1 en = 0; rd = 0; wr = 0;
end
endtask
// Readback test for the register
task read_test;
begin
// Test some reads
#5 read(0);
#1 read(2);
#1 read(4);
#1 read(8);
#1 read(16);
#1 read(17);
#1 read(18);
#1 read(19);
#1 read(24);
#1 read(25);
#1 read(26);
#1 read(27);
end
endtask
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_tap_base.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 15 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: All your taps are belong to us.
//
//In general, this block should be able to start up with a random initialization of
//the various counters. But its probably easier, more normative and quicker time to solution
//to just initialize to zero with rst.
//
// Following deassertion of reset, endlessly increments the MMCM delay with PSEN. For
// each MMCM tap it samples the phase detector output a programmable number of times.
// When the sampling count is achieved, PSEN is pulsed and sampling of the next MMCM
// tap begins.
//
// Following a PSEN, sampling pauses for MMCM_SAMP_WAIT clocks. This is workaround
// for a bug in the MMCM where its output may have noise for a period following
// the PSEN.
//
// Samples are taken every other fabric clock. This is because the MMCM phase shift
// clock operates at half the fabric clock. The reason for this is unknown.
//
// At the end of the sampling period, a filtering step is implemented. samps_solid_thresh
// is the minumum number of samples that must be seen to declare a solid zero or one. If
// neithr the one and zero samples cross this threshold, then the sampple is declared fuzz.
//
// A "run_polarity" bit is maintained. It is set appropriately whenever a solid sample
// is observed.
//
// A "run" counter is maintained. If the current sample is fuzz, or opposite polarity
// from a previous sample, then the run counter is reset. If the current sample is the
// same polarity run_polarity, then the run counter is incremented.
//
// If a run_polarity reversal or fuzz is observed and the run counter is not zero
// then the run_end strobe is pulsed.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_tap_base #
(parameter MMCM_SAMP_WAIT = 10,
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter TCQ = 100,
parameter SAMPCNTRWIDTH = 8,
parameter TAPCNTRWIDTH = 7,
parameter TAPSPERKCLK = 112)
(/*AUTOARG*/
// Outputs
psincdec, psen, run, run_end, run_polarity, samps_hi_held, tap,
// Inputs
pd_out, clk, samples, samps_solid_thresh, psdone, rst,
poc_sample_pd
);
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
input pd_out;
input clk;
input [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;
input psdone;
input rst;
localparam ONE = 1;
localparam SAMP_WAIT_WIDTH = clogb2(MMCM_SAMP_WAIT);
reg [SAMP_WAIT_WIDTH-1:0] samp_wait_ns, samp_wait_r;
always @(posedge clk) samp_wait_r <= #TCQ samp_wait_ns;
reg pd_out_r;
always @(posedge clk) pd_out_r <= #TCQ pd_out;
wire pd_out_sel = POC_USE_METASTABLE_SAMP == "TRUE" ? pd_out_r : pd_out;
output psincdec;
assign psincdec = 1'b1;
output psen;
reg psen_int;
assign psen = psen_int;
reg [TAPCNTRWIDTH-1:0] run_r;
reg [TAPCNTRWIDTH-1:0] run_ns;
always @(posedge clk) run_r <= #TCQ run_ns;
output [TAPCNTRWIDTH-1:0] run;
assign run = run_r;
output run_end;
reg run_end_int;
assign run_end = run_end_int;
reg run_polarity_r;
reg run_polarity_ns;
always @(posedge clk) run_polarity_r <= #TCQ run_polarity_ns;
output run_polarity;
assign run_polarity = run_polarity_r;
reg [SAMPCNTRWIDTH-1:0] samp_cntr_r;
reg [SAMPCNTRWIDTH-1:0] samp_cntr_ns;
always @(posedge clk) samp_cntr_r <= #TCQ samp_cntr_ns;
reg [SAMPCNTRWIDTH:0] samps_hi_r;
reg [SAMPCNTRWIDTH:0] samps_hi_ns;
always @(posedge clk) samps_hi_r <= #TCQ samps_hi_ns;
reg [SAMPCNTRWIDTH:0] samps_hi_held_r;
reg [SAMPCNTRWIDTH:0] samps_hi_held_ns;
always @(posedge clk) samps_hi_held_r <= #TCQ samps_hi_held_ns;
output [SAMPCNTRWIDTH:0] samps_hi_held;
assign samps_hi_held = samps_hi_held_r;
reg [TAPCNTRWIDTH-1:0] tap_ns, tap_r;
always @(posedge clk) tap_r <= #TCQ tap_ns;
output [TAPCNTRWIDTH-1:0] tap;
assign tap = tap_r;
localparam SMWIDTH = 2;
reg [SMWIDTH-1:0] sm_ns;
reg [SMWIDTH-1:0] sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
reg samps_zero_ns, samps_zero_r, samps_one_ns, samps_one_r;
always @(posedge clk) samps_zero_r <= #TCQ samps_zero_ns;
always @(posedge clk)samps_one_r <= #TCQ samps_one_ns;
// Interesting corner case... what if both samps_zero and samps_one are
// hi? Could happen for small sample counts and reasonable values of
// PCT_SAMPS_SOLID. Doesn't affect samps_solid. run_polarity assignment
// consistently breaks tie with samps_one_r.
wire [SAMPCNTRWIDTH:0] samps_lo = samples + ONE[SAMPCNTRWIDTH:0] - samps_hi_r;
always @(*) begin
samps_zero_ns = samps_zero_r;
samps_one_ns = samps_one_r;
samps_zero_ns = samps_lo >= samps_solid_thresh;
samps_one_ns = samps_hi_r >= samps_solid_thresh;
end // always @ begin
wire new_polarity = run_polarity_ns ^ run_polarity_r;
input poc_sample_pd;
always @(*) begin
if (rst == 1'b1) begin
// RESET next states
psen_int = 1'b0;
sm_ns = /*AUTOLINK("SAMPLE")*/2'd0;
run_polarity_ns = 1'b0;
run_ns = {TAPCNTRWIDTH{1'b0}};
run_end_int = 1'b0;
samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}};
samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}};
tap_ns = {TAPCNTRWIDTH{1'b0}};
samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0];
samps_hi_held_ns = {SAMPCNTRWIDTH+1{1'b0}};
end else begin
// Default next states;
psen_int = 1'b0;
sm_ns = sm_r;
run_polarity_ns = run_polarity_r;
run_ns = run_r;
run_end_int = 1'b0;
samp_cntr_ns = samp_cntr_r;
samps_hi_ns = samps_hi_r;
tap_ns = tap_r;
samp_wait_ns = samp_wait_r;
if (|samp_wait_r) samp_wait_ns = samp_wait_r - ONE[SAMP_WAIT_WIDTH-1:0];
samps_hi_held_ns = samps_hi_held_r;
// State based actions and next states.
case (sm_r)
/*AL("SAMPLE")*/2'd0: begin
if (~|samp_wait_r && poc_sample_pd | POC_USE_METASTABLE_SAMP == "TRUE") begin
if (POC_USE_METASTABLE_SAMP == "TRUE") samp_wait_ns = ONE[SAMP_WAIT_WIDTH-1:0];
if ({1'b0, samp_cntr_r} == samples) sm_ns = /*AK("COMPUTE")*/2'd1;
samps_hi_ns = samps_hi_r + {{SAMPCNTRWIDTH{1'b0}}, pd_out_sel};
samp_cntr_ns = samp_cntr_r + ONE[SAMPCNTRWIDTH-1:0];
end
end
/*AL("COMPUTE")*/2'd1:begin
sm_ns = /*AK("PSEN")*/2'd2;
end
/*AL("PSEN")*/2'd2:begin
sm_ns = /*AK("PSDONE_WAIT")*/2'd3;
psen_int = 1'b1;
samp_cntr_ns = {SAMPCNTRWIDTH{1'b0}};
samps_hi_ns = {SAMPCNTRWIDTH+1{1'b0}};
samps_hi_held_ns = samps_hi_r;
tap_ns = (tap_r < TAPSPERKCLK[TAPCNTRWIDTH-1:0] - ONE[TAPCNTRWIDTH-1:0])
? tap_r + ONE[TAPCNTRWIDTH-1:0]
: {TAPCNTRWIDTH{1'b0}};
if (run_polarity_r) begin
if (samps_zero_r) run_polarity_ns = 1'b0;
end else begin
if (samps_one_r) run_polarity_ns = 1'b1;
end
if (new_polarity) begin
run_ns ={TAPCNTRWIDTH{1'b0}};
run_end_int = 1'b1;
end else run_ns = run_r + ONE[TAPCNTRWIDTH-1:0];
end
/*AL("PSDONE_WAIT")*/2'd3:begin
samp_wait_ns = MMCM_SAMP_WAIT[SAMP_WAIT_WIDTH-1:0] - ONE[SAMP_WAIT_WIDTH-1:0];
if (psdone) sm_ns = /*AK("SAMPLE")*/2'd0;
end
endcase // case (sm_r)
end // else: !if(rst == 1'b1)
end // always @ (*)
endmodule // mig_7series_v2_3_poc_tap_base
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-extensions:(".v")
// verilog-autolabel-prefix: "2'd"
// End:
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// A clock synchronization FIFO where the enqueue and dequeue sides are in
// different clock domains.
// The depth of the FIFO is strictly 1 element. Implementation uses only
// 1 register to minimize hardware
// There are no restrictions w.r.t. clock frequencies
// FULL and EMPTY signal are pessimistic, that is, they are asserted
// immediately when the FIFO becomes FULL or EMPTY, but their deassertion
// is delayed due to synchronization latency.
module SyncFIFO1(
sCLK,
sRST,
dCLK,
sENQ,
sD_IN,
sFULL_N,
dDEQ,
dD_OUT,
dEMPTY_N
) ;
parameter dataWidth = 1 ;
// input clock domain ports
input sCLK ;
input sRST ;
input sENQ ;
input [dataWidth -1 : 0] sD_IN ;
output sFULL_N ;
// destination clock domain ports
input dCLK ;
input dDEQ ;
output dEMPTY_N ;
output [dataWidth -1 : 0] dD_OUT ;
// FIFO DATA
(* ASYNC_REG = "TRUE" *)
reg [dataWidth -1 : 0] syncFIFO1Data ;
// Reset generation
wire dRST = sRST;
// sCLK registers
reg sEnqToggle, sDeqToggle, sSyncReg1;
// dCLK registers
reg dEnqToggle, dDeqToggle, dSyncReg1;
// output assignment
assign dD_OUT = syncFIFO1Data;
assign dEMPTY_N = dEnqToggle != dDeqToggle;
assign sFULL_N = sEnqToggle == sDeqToggle;
always @(posedge sCLK or `BSV_RESET_EDGE sRST) begin
if (sRST == `BSV_RESET_VALUE) begin
syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY {dataWidth {1'b0}};
sEnqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0;
sDeqToggle <= `BSV_ASSIGNMENT_DELAY 1'b1; // FIFO marked as full during reset
end
else begin
if (sENQ && (sEnqToggle == sDeqToggle)) begin
syncFIFO1Data <= `BSV_ASSIGNMENT_DELAY sD_IN;
sEnqToggle <= `BSV_ASSIGNMENT_DELAY ! sEnqToggle;
end
sSyncReg1 <= `BSV_ASSIGNMENT_DELAY dDeqToggle; // clock domain crossing
sDeqToggle <= `BSV_ASSIGNMENT_DELAY sSyncReg1;
end
end
always @(posedge dCLK or `BSV_RESET_EDGE dRST) begin
if (dRST == `BSV_RESET_VALUE) begin
dEnqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY 1'b0;
dDeqToggle <= `BSV_ASSIGNMENT_DELAY 1'b0;
end
else begin
if (dDEQ && (dEnqToggle != dDeqToggle)) begin
dDeqToggle <= `BSV_ASSIGNMENT_DELAY ! dDeqToggle;
end
dSyncReg1 <= `BSV_ASSIGNMENT_DELAY sEnqToggle; // clock domain crossing
dEnqToggle <= `BSV_ASSIGNMENT_DELAY dSyncReg1;
end
end
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin : initBlock
syncFIFO1Data = {((dataWidth + 1)/2){2'b10}} ;
sEnqToggle = 1'b0;
sDeqToggle = 1'b0;
sSyncReg1 = 1'b0;
dEnqToggle = 1'b0;
dDeqToggle = 1'b0;
dSyncReg1 = 1'b0;
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
always@(posedge sCLK)
begin: error_checks1
reg enqerror ;
enqerror = 0;
if (sRST == ! `BSV_RESET_VALUE)
begin
if ( sENQ && (sEnqToggle != sDeqToggle)) begin
enqerror = 1;
$display( "Warning: SyncFIFO1: %m -- Enqueuing to a full fifo" ) ;
end
end
end
always@(posedge dCLK)
begin: error_checks2
reg deqerror ;
deqerror = 0;
if (dRST == ! `BSV_RESET_VALUE)
begin
if ( dDEQ && (dEnqToggle == dDeqToggle)) begin
deqerror = 1;
$display( "Warning: SyncFIFO1: %m -- Dequeuing from an empty full fifo" ) ;
end
end
end // block: error_checks
// synopsys translate_on
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_req.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_req.v //
// Description : Instantiates the request buffer primitives; 8KB Dual Port //
// Request FIFO //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_req.v //
// pcie_bram_7vx_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_req #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] waddr0_i, // write address
input [8:0] waddr1_i, // write address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input wen0_i, // write enable
input wen1_i, // write enable
input wen2_i, // write enable
input wen3_i, // write enable
input [8:0] raddr0_i, // write address
input [8:0] raddr1_i, // write address
output [127:0] rdata_o, // read data
output [15:0] rdop_o, // read parity
input ren0_i, // read enable
input ren1_i, // read enable
input ren2_i, // read enable
input ren3_i // read enable
);
pcie3_7x_0_pcie_bram_7vx_8k # (
.IMPL_TARGET(IMPL_TARGET),
.NO_DECODE_LOGIC(NO_DECODE_LOGIC),
.INTERFACE_SPEED(INTERFACE_SPEED),
.COMPLETION_SPACE(COMPLETION_SPACE)
)
U0
(
.clk_i (clk_i),
.reset_i (reset_i),
.waddr0_i (waddr0_i[8:0]),
.waddr1_i (waddr1_i[8:0]),
.wdata_i (wdata_i[127:0]),
.wdip_i (wdip_i[15:0]),
.wen_i ({wen3_i, wen2_i, wen1_i, wen0_i}),
.raddr0_i (raddr0_i[8:0]),
.raddr1_i (raddr1_i[8:0]),
.rdata_o (rdata_o[127:0]),
.rdop_o (rdop_o[15:0]),
.ren_i ({ren3_i, ren2_i, ren1_i, ren0_i})
);
endmodule // pcie_bram_7vx_req
|
//Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller Bank Tracking
//
// File : alt_ddrx_bank_tracking.v
//
// Abstract : Keep track of open banks/rows
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_ddrx_bank_tracking #
( parameter
// memory interface bus sizing parameters
MEM_IF_CHIP_BITS = 2,
MEM_IF_CS_WIDTH = 2,
MEM_IF_ROW_WIDTH = 16, // max supported row bits
MEM_IF_BA_WIDTH = 3, // max supported bank bits
// controller settings
CTL_LOOK_AHEAD_DEPTH = 6, // set to 6 in halfrate and 8 in fullrate
CTL_CMD_QUEUE_DEPTH = 8
)
(
ctl_clk,
ctl_reset_n,
all_banks_closed, // needed for precharge_all before a refresh
// Per cmd entry inputs and outputs, currently set to 4, might increase to 7 or more
cmd0_is_valid,
cmd0_chip_addr,
cmd0_row_addr,
cmd0_bank_addr,
cmd0_is_a_write,
cmd0_is_a_read,
cmd0_multicast_req,
cmd1_is_valid,
cmd1_chip_addr,
cmd1_row_addr,
cmd1_bank_addr,
cmd1_is_a_write,
cmd1_is_a_read,
cmd1_multicast_req,
cmd2_is_valid,
cmd2_chip_addr,
cmd2_row_addr,
cmd2_bank_addr,
cmd2_is_a_write,
cmd2_is_a_read,
cmd2_multicast_req,
cmd3_is_valid,
cmd3_chip_addr,
cmd3_row_addr,
cmd3_bank_addr,
cmd3_is_a_write,
cmd3_is_a_read,
cmd3_multicast_req,
cmd4_is_valid,
cmd4_chip_addr,
cmd4_row_addr,
cmd4_bank_addr,
cmd4_is_a_write,
cmd4_is_a_read,
cmd4_multicast_req,
cmd5_is_valid,
cmd5_chip_addr,
cmd5_row_addr,
cmd5_bank_addr,
cmd5_is_a_write,
cmd5_is_a_read,
cmd5_multicast_req,
cmd6_is_valid,
cmd6_chip_addr,
cmd6_row_addr,
cmd6_bank_addr,
cmd6_is_a_write,
cmd6_is_a_read,
cmd6_multicast_req,
cmd7_is_valid,
cmd7_chip_addr,
cmd7_row_addr,
cmd7_bank_addr,
cmd7_is_a_write,
cmd7_is_a_read,
cmd7_multicast_req,
row_is_open,
bank_is_open,
bank_info_valid,
// used for current command
current_chip_addr,
current_row_addr,
current_bank_addr,
current_is_a_write,
current_is_a_read,
current_multicast_req,
current_row_is_open,
current_bank_is_open,
current_bank_info_valid,
// state machine command outputs
ecc_fetch_error_addr,
fetch,
flush1,
flush2,
flush3,
do_activate,
do_precharge,
do_precharge_all,
do_auto_precharge,
to_chip,
//to_cs_addr,
to_row_addr,
to_bank_addr,
// bank page open/close information
bank_information,
bank_open
);
input ctl_clk;
input ctl_reset_n;
output [MEM_IF_CS_WIDTH - 1 : 0] all_banks_closed;
// Per cmd entry inputs and outputs; currently set to 4; might increase to 7 or more
input cmd0_is_valid;
input cmd0_is_a_write;
input cmd0_is_a_read;
input cmd0_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd0_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd0_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd0_bank_addr;
input cmd1_is_valid;
input cmd1_is_a_write;
input cmd1_is_a_read;
input cmd1_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd1_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd1_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd1_bank_addr;
input cmd2_is_valid;
input cmd2_is_a_write;
input cmd2_is_a_read;
input cmd2_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd2_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd2_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd2_bank_addr;
input cmd3_is_valid;
input cmd3_is_a_write;
input cmd3_is_a_read;
input cmd3_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd3_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd3_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd3_bank_addr;
input cmd4_is_valid;
input cmd4_is_a_write;
input cmd4_is_a_read;
input cmd4_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd4_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd4_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd4_bank_addr;
input cmd5_is_valid;
input cmd5_is_a_write;
input cmd5_is_a_read;
input cmd5_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd5_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd5_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd5_bank_addr;
input cmd6_is_valid;
input cmd6_is_a_write;
input cmd6_is_a_read;
input cmd6_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd6_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd6_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd6_bank_addr;
input cmd7_is_valid;
input cmd7_is_a_write;
input cmd7_is_a_read;
input cmd7_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] cmd7_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] cmd7_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] cmd7_bank_addr;
output [CTL_LOOK_AHEAD_DEPTH - 1 : 0] row_is_open;
output [CTL_LOOK_AHEAD_DEPTH - 1 : 0] bank_is_open;
output [CTL_LOOK_AHEAD_DEPTH - 1 : 0] bank_info_valid;
input current_is_a_write;
input current_is_a_read;
input current_multicast_req;
input [MEM_IF_CHIP_BITS - 1 : 0] current_chip_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] current_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] current_bank_addr;
output current_row_is_open;
output current_bank_is_open;
output current_bank_info_valid;
// state machine command outputs
input ecc_fetch_error_addr;
input fetch;
input flush1;
input flush2;
input flush3;
input do_activate;
input do_precharge;
input do_precharge_all;
input do_auto_precharge;
input [MEM_IF_CS_WIDTH - 1 : 0] to_chip;
input [MEM_IF_ROW_WIDTH - 1 : 0] to_row_addr;
input [MEM_IF_BA_WIDTH - 1 : 0] to_bank_addr;
output [MEM_IF_CS_WIDTH * (2**MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH - 1 : 0] bank_information ;
output [MEM_IF_CS_WIDTH * (2**MEM_IF_BA_WIDTH) - 1 : 0] bank_open ;
// Registers
reg [MEM_IF_CS_WIDTH - 1 : 0] all_banks_closed;
integer ba_count;
integer cs_count1;
integer cs_count2;
reg [(2 ** MEM_IF_BA_WIDTH) - 1 : 0] bank_status [MEM_IF_CS_WIDTH - 1 : 0]; // bank status register num_of_cs * num_of_bank
reg ecc_fetch_error_addr_r1;
reg ecc_fetch_error_addr_r2;
reg fetch_r1;
reg fetch_r2;
reg flush1_r1;
reg flush2_r1;
reg flush3_r1;
reg [1 : 0] flush;
reg int_current_info_valid;
reg int_current_info_valid_r;
reg cmd_cache;
reg do_activate_r1;
reg [MEM_IF_CHIP_BITS - 1 : 0] to_chip_r1;
reg [MEM_IF_BA_WIDTH - 1 : 0] to_bank_addr_r1;
reg [MEM_IF_ROW_WIDTH - 1 : 0] to_row_addr_r1;
reg [MEM_IF_BA_WIDTH - 1 : 0] current_bank_addr_r1;
reg [MEM_IF_ROW_WIDTH - 1 : 0] current_row_addr_r1;
reg current_bank_change;
reg current_row_change;
// One big bus which will concatenate all CMD 0 - N signals where N is CTL_CMD_QUEUE_DEPTH (might set to constant value based on number of command ports)
// Also includes current cmd
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_bank_is_open;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_row_is_open;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_activate;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_precharge;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_activate_r1;
reg [CTL_LOOK_AHEAD_DEPTH : 0] cmd_do_precharge_r1;
reg [CTL_LOOK_AHEAD_DEPTH : 0] int_cmd_do_activate_cached;
reg [CTL_LOOK_AHEAD_DEPTH : 0] int_cmd_do_precharge_cached;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_activate_cached;
reg [CTL_CMD_QUEUE_DEPTH : 0] cmd_do_precharge_cached;
wire [(CTL_CMD_QUEUE_DEPTH + 1) * (MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd_addr;
wire [(CTL_CMD_QUEUE_DEPTH + 1) * MEM_IF_CHIP_BITS - 1 : 0] cmd_chip_addr;
wire [(CTL_CMD_QUEUE_DEPTH + 1) * MEM_IF_BA_WIDTH - 1 : 0] cmd_bank_addr;
wire [(CTL_CMD_QUEUE_DEPTH + 1) * MEM_IF_ROW_WIDTH - 1 : 0] cmd_row_addr;
wire [CTL_CMD_QUEUE_DEPTH : 0] cmd_is_valid;
wire [CTL_CMD_QUEUE_DEPTH : 0] cmd_info_valid;
wire [CTL_CMD_QUEUE_DEPTH : 0] is_a_write;
wire [CTL_CMD_QUEUE_DEPTH : 0] is_a_read;
wire [CTL_CMD_QUEUE_DEPTH : 0] multicast_req;
wire [CTL_CMD_QUEUE_DEPTH : 0] cmd_multicast_req;
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] current_addr = {current_chip_addr, current_bank_addr, current_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd0_addr = {cmd0_chip_addr, cmd0_bank_addr, cmd0_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd1_addr = {cmd1_chip_addr, cmd1_bank_addr, cmd1_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd2_addr = {cmd2_chip_addr, cmd2_bank_addr, cmd2_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd3_addr = {cmd3_chip_addr, cmd3_bank_addr, cmd3_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd4_addr = {cmd4_chip_addr, cmd4_bank_addr, cmd4_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd5_addr = {cmd5_chip_addr, cmd5_bank_addr, cmd5_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd6_addr = {cmd6_chip_addr, cmd6_bank_addr, cmd6_row_addr};
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] cmd7_addr = {cmd7_chip_addr, cmd7_bank_addr, cmd7_row_addr};
// CMD outputs
wire [CTL_LOOK_AHEAD_DEPTH - 1 : 0] row_is_open;
wire [CTL_LOOK_AHEAD_DEPTH - 1 : 0] bank_is_open;
wire [CTL_LOOK_AHEAD_DEPTH - 1 : 0] bank_info_valid;
reg [CTL_CMD_QUEUE_DEPTH - 1 : 0] int_row_is_open;
reg [CTL_CMD_QUEUE_DEPTH - 1 : 0] int_bank_is_open;
reg [CTL_CMD_QUEUE_DEPTH - 1 : 0] int_bank_info_valid;
reg current_bank_is_open;
reg current_row_is_open;
reg current_bank_info_valid;
assign cmd_addr = {cmd7_addr, cmd6_addr, cmd5_addr, cmd4_addr, cmd3_addr, cmd2_addr, cmd1_addr, cmd0_addr, current_addr};
assign cmd_chip_addr = {cmd7_chip_addr, cmd6_chip_addr, cmd5_chip_addr, cmd4_chip_addr, cmd3_chip_addr, cmd2_chip_addr, cmd1_chip_addr, cmd0_chip_addr, current_chip_addr};
assign cmd_bank_addr = {cmd7_bank_addr, cmd6_bank_addr, cmd5_bank_addr, cmd4_bank_addr, cmd3_bank_addr, cmd2_bank_addr, cmd1_bank_addr, cmd0_bank_addr, current_bank_addr};
assign cmd_row_addr = {cmd7_row_addr, cmd6_row_addr, cmd5_row_addr, cmd4_row_addr, cmd3_row_addr, cmd2_row_addr, cmd1_row_addr, cmd0_row_addr, current_row_addr};
assign cmd_is_valid = {cmd7_is_valid, cmd6_is_valid, cmd5_is_valid, cmd4_is_valid, cmd3_is_valid, cmd2_is_valid, cmd1_is_valid, cmd0_is_valid, 1'b0}; // current signal doesn't have valid signal
assign cmd_info_valid [0] = int_current_info_valid;
assign multicast_req = {cmd7_multicast_req, cmd6_multicast_req, cmd5_multicast_req, cmd4_multicast_req, cmd3_multicast_req, cmd2_multicast_req, cmd1_multicast_req, cmd0_multicast_req, current_multicast_req};
assign is_a_write = {cmd7_is_a_write, cmd6_is_a_write, cmd5_is_a_write, cmd4_is_a_write, cmd3_is_a_write, cmd2_is_a_write, cmd1_is_a_write, cmd0_is_a_write, current_is_a_write};
assign is_a_read = {cmd7_is_a_read, cmd6_is_a_read, cmd5_is_a_read, cmd4_is_a_read, cmd3_is_a_read, cmd2_is_a_read, cmd1_is_a_read, cmd0_is_a_read, current_is_a_read};
assign cmd_multicast_req = multicast_req & is_a_write;
assign row_is_open = int_row_is_open [CTL_LOOK_AHEAD_DEPTH - 1 : 0];
assign bank_is_open = int_bank_is_open [CTL_LOOK_AHEAD_DEPTH - 1 : 0];
assign bank_info_valid = int_bank_info_valid [CTL_LOOK_AHEAD_DEPTH - 1 : 0];
/*------------------------------------------------------------------------------
Cache
------------------------------------------------------------------------------*/
// Determine the flush value
always @ (*)
begin
if (fetch)
begin
if (flush1)
flush = 2'b01;
else if (flush2)
flush = 2'b10;
else if (flush3)
flush = 2'b11;
else
flush = 2'b00;
end
else if (fetch_r1)
begin
if (flush1_r1)
flush = 2'b01;
else if (flush2_r1)
flush = 2'b10;
else if (flush3_r1)
flush = 2'b11;
else
flush = 2'b00;
end
else
begin
// the following case is to prevent caching the wrong data during flush with no fetch state
// eg: when there is flush1 with no fetch, we should only move the data by one command instead of 2
if (flush1 || flush1_r1)
flush = 2'b00;
else if (flush2 || flush2_r1)
flush = 2'b01;
else if (flush3 || flush3_r1)
flush = 2'b10;
else
flush = 2'b00;
end
end
// Fetch registers
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_fetch_error_addr_r1 <= 1'b0;
ecc_fetch_error_addr_r2 <= 1'b0;
fetch_r1 <= 1'b0;
fetch_r2 <= 1'b0;
end
else
begin
ecc_fetch_error_addr_r1 <= ecc_fetch_error_addr;
ecc_fetch_error_addr_r2 <= ecc_fetch_error_addr_r1;
fetch_r1 <= fetch;
fetch_r2 <= fetch_r1;
end
end
// register all flush signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
flush1_r1 <= 1'b0;
flush2_r1 <= 1'b0;
flush3_r1 <= 1'b0;
end
else
begin
flush1_r1 <= flush1;
flush2_r1 <= flush2;
flush3_r1 <= flush3;
end
end
// Determine when to cache the information
always @ (*)
begin
begin
if (fetch || fetch_r1 || flush1 || flush2 || flush3 || flush1_r1 || flush2_r1 || flush3_r1)
cmd_cache = 1'b1;
else
cmd_cache = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
current_bank_is_open <= 0;
int_bank_is_open <= 0;
current_row_is_open <= 0;
int_row_is_open <= 0;
current_bank_info_valid <= 0;
int_bank_info_valid <= 0;
end
else if (cmd_cache)
begin
if (flush == 2'b01)
begin
current_bank_is_open <= cmd_bank_is_open [2];
int_bank_is_open [0] <= cmd_bank_is_open [3];
int_bank_is_open [1] <= cmd_bank_is_open [4];
int_bank_is_open [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [5];
int_bank_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [6];
int_bank_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [7];
int_bank_is_open [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [8];
int_bank_is_open [6] <= 1'b0;
int_bank_is_open [7] <= 1'b0;
current_row_is_open <= cmd_row_is_open [2];
int_row_is_open [0] <= cmd_row_is_open [3];
int_row_is_open [1] <= cmd_row_is_open [4];
int_row_is_open [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [5];
int_row_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [6];
int_row_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [7];
int_row_is_open [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [8];
int_row_is_open [6] <= 1'b0;
int_row_is_open [7] <= 1'b0;
current_bank_info_valid <= cmd_info_valid[2];
int_bank_info_valid [0] <= cmd_info_valid[3];
int_bank_info_valid [1] <= cmd_info_valid[4];
int_bank_info_valid [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [5];
int_bank_info_valid [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [6];
int_bank_info_valid [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [7];
int_bank_info_valid [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [8];
int_bank_info_valid [6] <= 1'b0;
int_bank_info_valid [7] <= 1'b0;
end
else if (flush == 2'b10)
begin
current_bank_is_open <= cmd_bank_is_open [3];
int_bank_is_open [0] <= cmd_bank_is_open [4];
int_bank_is_open [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [5];
int_bank_is_open [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [6];
int_bank_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [7];
int_bank_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [8];
int_bank_is_open [5] <= 1'b0;
int_bank_is_open [6] <= 1'b0;
int_bank_is_open [7] <= 1'b0;
current_row_is_open <= cmd_row_is_open [3];
int_row_is_open [0] <= cmd_row_is_open [4];
int_row_is_open [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [5];
int_row_is_open [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [6];
int_row_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [7];
int_row_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [8];
int_row_is_open [5] <= 1'b0;
int_row_is_open [6] <= 1'b0;
int_row_is_open [7] <= 1'b0;
current_bank_info_valid <= cmd_info_valid[3];
int_bank_info_valid [0] <= cmd_info_valid[4];
int_bank_info_valid [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [5];
int_bank_info_valid [2] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [6];
int_bank_info_valid [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [7];
int_bank_info_valid [4] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [8];
int_bank_info_valid [5] <= 1'b0;
int_bank_info_valid [6] <= 1'b0;
int_bank_info_valid [7] <= 1'b0;
end
else if (flush == 2'b11)
begin
current_bank_is_open <= cmd_bank_is_open [4];
int_bank_is_open [0] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [5];
int_bank_is_open [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [6];
int_bank_is_open [2] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [7];
int_bank_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [8];
int_bank_is_open [4] <= 1'b0;
int_bank_is_open [5] <= 1'b0;
int_bank_is_open [6] <= 1'b0;
int_bank_is_open [7] <= 1'b0;
current_row_is_open <= cmd_row_is_open [4];
int_row_is_open [0] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [5];
int_row_is_open [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [6];
int_row_is_open [2] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [7];
int_row_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [8];
int_row_is_open [4] <= 1'b0;
int_row_is_open [5] <= 1'b0;
int_row_is_open [6] <= 1'b0;
int_row_is_open [7] <= 1'b0;
current_bank_info_valid <= cmd_info_valid[4];
int_bank_info_valid [0] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [5];
int_bank_info_valid [1] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [6];
int_bank_info_valid [2] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [7];
int_bank_info_valid [3] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [8];
int_bank_info_valid [4] <= 1'b0;
int_bank_info_valid [5] <= 1'b0;
int_bank_info_valid [6] <= 1'b0;
int_bank_info_valid [7] <= 1'b0;
end
else
begin
current_bank_is_open <= cmd_bank_is_open [1];
int_bank_is_open [0] <= cmd_bank_is_open [2];
int_bank_is_open [1] <= cmd_bank_is_open [3];
int_bank_is_open [2] <= cmd_bank_is_open [4];
int_bank_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [5];
int_bank_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [6];
int_bank_is_open [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [7];
int_bank_is_open [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [8];
int_bank_is_open [7] <= 1'b0;
current_row_is_open <= cmd_row_is_open [1];
int_row_is_open [0] <= cmd_row_is_open [2];
int_row_is_open [1] <= cmd_row_is_open [3];
int_row_is_open [2] <= cmd_row_is_open [4];
int_row_is_open [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [5];
int_row_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [6];
int_row_is_open [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [7];
int_row_is_open [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [8];
int_row_is_open [7] <= 1'b0;
current_bank_info_valid <= cmd_info_valid [1];
int_bank_info_valid [0] <= cmd_info_valid [2];
int_bank_info_valid [1] <= cmd_info_valid [3];
int_bank_info_valid [2] <= cmd_info_valid [4];
int_bank_info_valid [3] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [5];
int_bank_info_valid [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [6];
int_bank_info_valid [5] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [7];
int_bank_info_valid [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [8];
int_bank_info_valid [7] <= 1'b0;
end
end
else
begin
// changes done to current information because state machine will change current row, bank and chip address
// when address reaches encd of row, bank or chip, normally happen when local size is set to a large value
// during bank or chip change, bank will definitely change, so we check for bank change only
// when there is a bank change, we will hold off valid signal for 2 clock cycles before valid data comes back from ram
if (current_bank_change)
current_bank_info_valid <= 1'b0;
else
current_bank_info_valid <= cmd_info_valid [0];
// during row change, we only need to set row_is_open to zero so that state machine will precharge and activate the current bank
if (current_row_change)
current_row_is_open <= 1'b0;
else
current_row_is_open <= cmd_row_is_open [0];
current_bank_is_open <= cmd_bank_is_open [0];
int_bank_is_open [0] <= cmd_bank_is_open [1];
int_bank_is_open [1] <= cmd_bank_is_open [2];
int_bank_is_open [2] <= cmd_bank_is_open [3];
int_bank_is_open [3] <= cmd_bank_is_open [4];
int_bank_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [5];
int_bank_is_open [5] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_bank_is_open [6];
int_bank_is_open [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [7];
int_bank_is_open [7] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_bank_is_open [8];
//current_row_is_open <= cmd_row_is_open [0];
int_row_is_open [0] <= cmd_row_is_open [1];
int_row_is_open [1] <= cmd_row_is_open [2];
int_row_is_open [2] <= cmd_row_is_open [3];
int_row_is_open [3] <= cmd_row_is_open [4];
int_row_is_open [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [5];
int_row_is_open [5] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_row_is_open [6];
int_row_is_open [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [7];
int_row_is_open [7] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_row_is_open [8];
//current_bank_info_valid <= cmd_info_valid [0];
int_bank_info_valid [0] <= cmd_info_valid [1];
int_bank_info_valid [1] <= cmd_info_valid [2];
int_bank_info_valid [2] <= cmd_info_valid [3];
int_bank_info_valid [3] <= cmd_info_valid [4];
int_bank_info_valid [4] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [5];
int_bank_info_valid [5] <= (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : cmd_info_valid [6];
int_bank_info_valid [6] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [7];
int_bank_info_valid [7] <= (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : cmd_info_valid [8];
end
end
always @ (*)
begin
if (cmd_cache)
begin
if (flush == 2'b01)
begin
// cmd do signal (registered version)
cmd_do_activate_cached [0] = 1'b0;
cmd_do_activate_cached [1] = 1'b0;
cmd_do_activate_cached [2] = int_cmd_do_activate_cached [0];
cmd_do_activate_cached [3] = int_cmd_do_activate_cached [1];
cmd_do_activate_cached [4] = int_cmd_do_activate_cached [2];
cmd_do_activate_cached [5] = int_cmd_do_activate_cached [3];
cmd_do_activate_cached [6] = int_cmd_do_activate_cached [4];
cmd_do_activate_cached [7] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_cached [5];
cmd_do_activate_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_cached [6];
cmd_do_precharge_cached [0] = 1'b0;
cmd_do_precharge_cached [1] = 1'b0;
cmd_do_precharge_cached [2] = int_cmd_do_precharge_cached [0];
cmd_do_precharge_cached [3] = int_cmd_do_precharge_cached [1];
cmd_do_precharge_cached [4] = int_cmd_do_precharge_cached [2];
cmd_do_precharge_cached [5] = int_cmd_do_precharge_cached [3];
cmd_do_precharge_cached [6] = int_cmd_do_precharge_cached [4];
cmd_do_precharge_cached [7] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_cached [5];
cmd_do_precharge_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_cached [6];
end
else if (flush == 2'b10)
begin
// cmd do signal (registered version)
cmd_do_activate_cached [0] = 1'b0;
cmd_do_activate_cached [1] = 1'b0;
cmd_do_activate_cached [2] = 1'b0;
cmd_do_activate_cached [3] = int_cmd_do_activate_cached [0];
cmd_do_activate_cached [4] = int_cmd_do_activate_cached [1];
cmd_do_activate_cached [5] = int_cmd_do_activate_cached [2];
cmd_do_activate_cached [6] = int_cmd_do_activate_cached [3];
cmd_do_activate_cached [7] = int_cmd_do_activate_cached [4];
cmd_do_activate_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_cached [5];
cmd_do_precharge_cached [0] = 1'b0;
cmd_do_precharge_cached [1] = 1'b0;
cmd_do_precharge_cached [2] = 1'b0;
cmd_do_precharge_cached [3] = int_cmd_do_precharge_cached [0];
cmd_do_precharge_cached [4] = int_cmd_do_precharge_cached [1];
cmd_do_precharge_cached [5] = int_cmd_do_precharge_cached [2];
cmd_do_precharge_cached [6] = int_cmd_do_precharge_cached [3];
cmd_do_precharge_cached [7] = int_cmd_do_precharge_cached [4];
cmd_do_precharge_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_cached [5];
end
else if (flush == 2'b11)
begin
// cmd do signal (registered version)
cmd_do_activate_cached [0] = 1'b0;
cmd_do_activate_cached [1] = 1'b0;
cmd_do_activate_cached [2] = 1'b0;
cmd_do_activate_cached [3] = 1'b0;
cmd_do_activate_cached [4] = int_cmd_do_activate_cached [0];
cmd_do_activate_cached [5] = int_cmd_do_activate_cached [1];
cmd_do_activate_cached [6] = int_cmd_do_activate_cached [2];
cmd_do_activate_cached [7] = int_cmd_do_activate_cached [3];
cmd_do_activate_cached [8] = int_cmd_do_activate_cached [4];
cmd_do_precharge_cached [0] = 1'b0;
cmd_do_precharge_cached [1] = 1'b0;
cmd_do_precharge_cached [2] = 1'b0;
cmd_do_precharge_cached [3] = 1'b0;
cmd_do_precharge_cached [4] = int_cmd_do_precharge_cached [0];
cmd_do_precharge_cached [5] = int_cmd_do_precharge_cached [1];
cmd_do_precharge_cached [6] = int_cmd_do_precharge_cached [2];
cmd_do_precharge_cached [7] = int_cmd_do_precharge_cached [3];
cmd_do_precharge_cached [8] = int_cmd_do_precharge_cached [4];
end
else
begin
// cmd do signal (registered version)
cmd_do_activate_cached [0] = 1'b0;
cmd_do_activate_cached [1] = int_cmd_do_activate_cached [0];
cmd_do_activate_cached [2] = int_cmd_do_activate_cached [1];
cmd_do_activate_cached [3] = int_cmd_do_activate_cached [2];
cmd_do_activate_cached [4] = int_cmd_do_activate_cached [3];
cmd_do_activate_cached [5] = int_cmd_do_activate_cached [4];
cmd_do_activate_cached [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_cached [5];
cmd_do_activate_cached [7] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_cached [6];
cmd_do_activate_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_cached [7];
cmd_do_precharge_cached [0] = 1'b0;
cmd_do_precharge_cached [1] = int_cmd_do_precharge_cached [0];
cmd_do_precharge_cached [2] = int_cmd_do_precharge_cached [1];
cmd_do_precharge_cached [3] = int_cmd_do_precharge_cached [2];
cmd_do_precharge_cached [4] = int_cmd_do_precharge_cached [3];
cmd_do_precharge_cached [5] = int_cmd_do_precharge_cached [4];
cmd_do_precharge_cached [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_cached [5];
cmd_do_precharge_cached [7] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_cached [6];
cmd_do_precharge_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_cached [7];
end
end
else
begin
// cmd do signal (registered version)
cmd_do_activate_cached [0] = int_cmd_do_activate_cached [0];
cmd_do_activate_cached [1] = int_cmd_do_activate_cached [1];
cmd_do_activate_cached [2] = int_cmd_do_activate_cached [2];
cmd_do_activate_cached [3] = int_cmd_do_activate_cached [3];
cmd_do_activate_cached [4] = int_cmd_do_activate_cached [4];
cmd_do_activate_cached [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_cached [5];
cmd_do_activate_cached [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_activate_cached [6];
cmd_do_activate_cached [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_cached [7];
cmd_do_activate_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_activate_cached [8];
cmd_do_precharge_cached [0] = int_cmd_do_precharge_cached [0];
cmd_do_precharge_cached [1] = int_cmd_do_precharge_cached [1];
cmd_do_precharge_cached [2] = int_cmd_do_precharge_cached [2];
cmd_do_precharge_cached [3] = int_cmd_do_precharge_cached [3];
cmd_do_precharge_cached [4] = int_cmd_do_precharge_cached [4];
cmd_do_precharge_cached [5] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_cached [5];
cmd_do_precharge_cached [6] = (CTL_LOOK_AHEAD_DEPTH <= 4) ? 1'b0 : int_cmd_do_precharge_cached [6];
cmd_do_precharge_cached [7] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_cached [7];
cmd_do_precharge_cached [8] = (CTL_LOOK_AHEAD_DEPTH <= 6) ? 1'b0 : int_cmd_do_precharge_cached [8];
end
end
// register for current address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
current_bank_addr_r1 <= 0;
current_row_addr_r1 <= 0;
end
else
begin
current_bank_addr_r1 <= current_bank_addr;
current_row_addr_r1 <= current_row_addr;
end
end
// checking for row, bank and chip change in current addresses
always @ (*)
begin
//if (!ctl_reset_n)
//begin
// current_bank_change <= 1'b0;
// current_row_change <= 1'b0;
//end
//else
begin
if (current_bank_addr != current_bank_addr_r1)
current_bank_change <= 1'b1;
else
current_bank_change <= 1'b0;
if (current_row_addr != current_row_addr_r1)
current_row_change <= 1'b1;
else
current_row_change <= 1'b0;
end
end
/*------------------------------------------------------------------------------
CMD Signals
------------------------------------------------------------------------------*/
// register the following signal to be used in row/bank is open logic
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
do_activate_r1 <= 1'b0;
end
else
begin
do_activate_r1 <= do_activate;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
to_chip_r1 <= 0;
to_bank_addr_r1 <= 0;
to_row_addr_r1 <= 0;
end
else
begin
to_chip_r1 <= to_chip;
to_bank_addr_r1 <= to_bank_addr;
to_row_addr_r1 <= to_row_addr;
end
end
// The following signals will be used to determine when there is a activate/precharge
// to each command queue address
generate
begin
genvar w;
for (w = 0;w < CTL_LOOK_AHEAD_DEPTH + 1;w = w + 1)
begin : input_do_signal_fanout_per_cmd
wire [MEM_IF_CHIP_BITS - 1 : 0] chip_addr = cmd_chip_addr [(w + 1) * MEM_IF_CHIP_BITS - 1 : w * MEM_IF_CHIP_BITS];
wire [MEM_IF_BA_WIDTH - 1 : 0] bank_addr = cmd_bank_addr [(w + 1) * MEM_IF_BA_WIDTH - 1 : w * MEM_IF_BA_WIDTH];
wire [MEM_IF_ROW_WIDTH - 1 : 0] row_addr = cmd_row_addr [(w + 1) * MEM_IF_ROW_WIDTH - 1 : w * MEM_IF_ROW_WIDTH];
always @ (*)
begin
// do_activate
if (cmd_multicast_req [w]) // don't care to_chip during multicast
begin
if (do_activate && &to_chip && to_bank_addr == bank_addr && to_row_addr == row_addr)
cmd_do_activate [w] = 1'b1;
else
cmd_do_activate [w] = 1'b0;
end
else
begin
if (do_activate && to_chip [chip_addr] && to_bank_addr == bank_addr && to_row_addr == row_addr)
cmd_do_activate [w] = 1'b1;
else
cmd_do_activate [w] = 1'b0;
end
// do_precharge
if (cmd_multicast_req [w]) // don't care to_chip during multicast
begin
if ((((do_auto_precharge || do_precharge) && to_bank_addr == bank_addr) || do_precharge_all) && &to_chip)
cmd_do_precharge [w] = 1'b1;
else
cmd_do_precharge [w] = 1'b0;
end
else
begin
if ((((do_auto_precharge || do_precharge) && to_bank_addr == bank_addr) || do_precharge_all) && to_chip [chip_addr])
cmd_do_precharge [w] = 1'b1;
else
cmd_do_precharge [w] = 1'b0;
end
end
// registered version of cmd_do
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cmd_do_activate_r1 [w] <= 1'b0;
cmd_do_precharge_r1 [w] <= 1'b0;
end
else
begin
cmd_do_activate_r1 [w] <= cmd_do_activate [w];
cmd_do_precharge_r1 [w] <= cmd_do_precharge [w];
end
end
// this signal is required when there is a fetch followed by activate
// without this signal, tRCD efficiency will be impacted
always @ (*)
begin
int_cmd_do_activate_cached [w] <= cmd_do_activate [w];
end
// this signal is required when there is a fetch followed by precharge
// without this signal, efficiency will be affected
always @ (*)
begin
int_cmd_do_precharge_cached [w] <= cmd_do_precharge [w];
end
end
end
endgenerate
/* -----------------------------------------------------------------------------
Important Notice:
Currently we remove all RAM instantiation because design doesn't meet fmax
266.67MHz. To re-design bank logic block with RAM instantiation (customer
might want to reduce LE counts), they will need to instantiate
'lookahead depth x chipselects' numbers of RAM (to support multicast, can be
reduced to 'lookahead depth' numbers of RAM)
Please refer to revision 24 in Perforce for futher reference.
------------------------------------------------------------------------------*/
reg [MEM_IF_ROW_WIDTH - 1 : 0] row_information [MEM_IF_CS_WIDTH - 1 : 0] [(2 ** MEM_IF_BA_WIDTH) - 1 : 0];
generate
genvar x_outer;
genvar x_inner;
for (x_outer = 0;x_outer < MEM_IF_CS_WIDTH;x_outer = x_outer + 1)
begin : row_information_per_chip
for (x_inner = 0;x_inner < (2 ** MEM_IF_BA_WIDTH);x_inner = x_inner + 1)
begin : row_information_per_bank
// row information is used to store row addresses during activate
// one extra bit is required for each entry to indicate whether the current entry is valid or not
// this is required to handle non-multicast to multicast request
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
row_information [x_outer][x_inner] <= 0;
end
else
begin
if (do_activate && to_chip [x_outer] && x_inner == to_bank_addr)
row_information [x_outer][x_inner] <= to_row_addr;
end
end
end
end
endgenerate
generate
genvar m_cs;
genvar m_bank;
genvar m_rowbit;
for (m_cs = 0;m_cs < MEM_IF_CS_WIDTH;m_cs = m_cs + 1)
begin : bank_information_cs
for (m_bank = 0;m_bank < (2 ** MEM_IF_BA_WIDTH);m_bank = m_bank + 1)
begin : bank_information_bank
wire [MEM_IF_ROW_WIDTH - 1 : 0] bankaware_row = row_information[m_cs] [m_bank];
wire bankaware_open = bank_status [m_cs] [m_bank];
assign bank_open[m_cs * (2 ** MEM_IF_BA_WIDTH) + m_bank] = bankaware_open;
for (m_rowbit = 0; m_rowbit < MEM_IF_ROW_WIDTH; m_rowbit = m_rowbit + 1)
begin : bank_information_row
assign bank_information[ ( (m_cs * (2 ** MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH) + (m_bank * MEM_IF_ROW_WIDTH) + m_rowbit) ] = bankaware_row[m_rowbit];
end
end
end
endgenerate
generate
genvar z;
genvar z_inner;
for (z = 0; z < CTL_LOOK_AHEAD_DEPTH + 1;z = z + 1)
begin : CMD
reg [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] int_cmd_addr_r1;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_cmd_row_is_open;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_cmd_to_chip;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_cmd_to_chip_r1;
reg [MEM_IF_CS_WIDTH - 1 : 0] int_cmd_bank_is_open;
reg int_cmd_multicast_req_r1;
wire [(MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH) - 1 : 0] int_cmd_addr;
wire [MEM_IF_CHIP_BITS - 1 : 0] int_cmd_chip_addr;
wire [MEM_IF_ROW_WIDTH - 1 : 0] int_cmd_row_addr;
wire [MEM_IF_BA_WIDTH - 1 : 0] int_cmd_bank_addr;
wire [MEM_IF_CHIP_BITS - 1 : 0] int_cmd_chip_addr_r1;
wire [MEM_IF_ROW_WIDTH - 1 : 0] int_cmd_row_addr_r1;
wire [MEM_IF_BA_WIDTH - 1 : 0] int_cmd_bank_addr_r1;
wire [MEM_IF_CS_WIDTH * MEM_IF_ROW_WIDTH - 1 : 0] int_cmd_ram_rd_data;
wire int_cmd_multicast_req;
// Addr Signals
assign int_cmd_addr = cmd_addr[((z + 1) * (MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH)) - 1 : (z * (MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH))];
assign int_cmd_chip_addr = int_cmd_addr [MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH - 1 : MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH];
assign int_cmd_bank_addr = int_cmd_addr [MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH - 1 : MEM_IF_ROW_WIDTH];
assign int_cmd_row_addr = int_cmd_addr [MEM_IF_ROW_WIDTH - 1 : 0];
assign int_cmd_chip_addr_r1 = int_cmd_addr_r1 [MEM_IF_CHIP_BITS + MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH - 1 : MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH];
assign int_cmd_bank_addr_r1 = int_cmd_addr_r1 [MEM_IF_BA_WIDTH + MEM_IF_ROW_WIDTH - 1 : MEM_IF_ROW_WIDTH];
assign int_cmd_row_addr_r1 = int_cmd_addr_r1 [MEM_IF_ROW_WIDTH - 1 : 0];
// Multicast request
assign int_cmd_multicast_req = cmd_multicast_req [z];
// Convert chip_addr to to_chip
always @ (*)
begin
// Set all to zero then set the chip bit to one
int_cmd_to_chip = 0;
int_cmd_to_chip [int_cmd_chip_addr] = 1'b1;
end
// CMD registers
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_cmd_addr_r1 <= 0;
end
else
begin
int_cmd_addr_r1 <= int_cmd_addr;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_cmd_to_chip_r1 <= 0;
end
else
begin
int_cmd_to_chip_r1 <= int_cmd_to_chip;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_cmd_multicast_req_r1 <= 1'b0;
end
else
begin
int_cmd_multicast_req_r1 <= int_cmd_multicast_req;
end
end
// bank open signal
always @ (*)
begin
// setting this signal to '0' more important than setting it to '1'
// setting it to '1' later will only cause in-efficiency but not functional failure
if (cmd_do_precharge_cached [z])
cmd_bank_is_open [z] = 1'b0;
else if (cmd_do_precharge_r1 [z])
cmd_bank_is_open [z] = 1'b0;
else if (cmd_do_activate_cached [z])
cmd_bank_is_open [z] = 1'b1;
else if (cmd_do_activate_r1 [z])
cmd_bank_is_open [z] = 1'b1;
else
begin
if (int_cmd_multicast_req_r1)
cmd_bank_is_open [z] = |int_cmd_bank_is_open;
else
cmd_bank_is_open [z] = int_cmd_bank_is_open [int_cmd_chip_addr_r1];
end
end
// row open signal
always @ (*)
begin
if (cmd_do_activate_cached [z])
cmd_row_is_open [z] = 1'b1;
else if (cmd_do_activate_r1 [z])
cmd_row_is_open [z] = 1'b1;
else
begin
if (int_cmd_multicast_req_r1)
cmd_row_is_open [z] = &int_cmd_row_is_open;
else
cmd_row_is_open [z] = int_cmd_row_is_open [int_cmd_chip_addr_r1];
end
end
for (z_inner = 0;z_inner < MEM_IF_CS_WIDTH;z_inner = z_inner + 1)
begin : row_is_open_loop
wire [MEM_IF_ROW_WIDTH - 1 : 0] int_read_data = row_information [z_inner][int_cmd_bank_addr];
wire int_bank_data = bank_status [z_inner][int_cmd_bank_addr];
// assign bank status information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_cmd_bank_is_open [z_inner] <= 1'b0;
else
int_cmd_bank_is_open [z_inner] <= int_bank_data;
end
// assign read data from row information
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_cmd_row_is_open [z_inner] <= 1'b0;
else
begin
if (int_read_data == int_cmd_row_addr)
int_cmd_row_is_open [z_inner] <= 1'b1 & int_bank_data;
else
int_cmd_row_is_open [z_inner] <= 1'b0;
end
end
end
end
endgenerate
// Valid signals for command
generate
genvar Y;
for (Y = 1; Y < CTL_LOOK_AHEAD_DEPTH + 1;Y = Y + 1)
begin : VALID
reg int_cmd_info_valid;
wire int_cmd_info_valid_r1;
reg int_cmd_is_valid_r1;
reg int_cmd_is_valid_r2;
wire int_cmd_is_valid;
assign int_cmd_is_valid = cmd_is_valid [Y];
assign int_cmd_info_valid_r1 = int_cmd_info_valid;
assign cmd_info_valid [Y] = int_cmd_info_valid_r1;
// Valid signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_cmd_info_valid <= 1'b0;
//int_cmd_info_valid_r1 <= 1'b0;
end
else
begin
int_cmd_info_valid <= int_cmd_is_valid;
//int_cmd_info_valid_r1 <= int_cmd_info_valid;
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
int_current_info_valid_r <= 1'b0;
else
int_current_info_valid_r <= int_current_info_valid;
end
// Valid signal for current command
always @ (*)
begin
//if (!ctl_reset_n)
//begin
// int_current_info_valid <= 1'b0;
//end
//else
begin
if (fetch)
int_current_info_valid <= 1'b0;
else if (fetch_r2)
int_current_info_valid <= 1'b1;
//we will need to deassert current info valid signal for 2 clock cycle so that state machine will not capture the wrong information
else if (ecc_fetch_error_addr)
int_current_info_valid <= 1'b0;
else if (ecc_fetch_error_addr_r2)
int_current_info_valid <= 1'b1;
else
int_current_info_valid <= int_current_info_valid_r;
end
end
/*------------------------------------------------------------------------------
General
------------------------------------------------------------------------------*/
// Bank status register
integer i;
integer j;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for (i = 0;i < MEM_IF_CS_WIDTH;i = i + 1'b1)
begin : bank_status_init_outer_loop
bank_status [i] <= 0;
end
end
else
begin
i <= 0;
for (cs_count2 = 0;cs_count2 < MEM_IF_CS_WIDTH;cs_count2 = cs_count2 + 1'b1)
begin : bank_status_per_chip
if (to_chip [cs_count2])
begin
if (do_precharge_all)
bank_status [cs_count2][(2 ** MEM_IF_BA_WIDTH) - 1 : 0] <= 0;
else if (do_precharge || do_auto_precharge)
bank_status [cs_count2][to_bank_addr] <= 1'b0;
else if (do_activate)
bank_status [cs_count2][to_bank_addr] <= 1'b1;
end
end
end
end
// All banks closed signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
all_banks_closed <= 0;
end
else
begin
for (cs_count1 = 0;cs_count1 < MEM_IF_CS_WIDTH;cs_count1 = cs_count1 + 1'b1)
begin : all_banks_closed_per_chip
if (do_activate && to_chip[cs_count1]) // need this because after do_activate, all banks closed signal doesn't deassert fast enough
all_banks_closed [cs_count1] <= 1'b0;
else if (!(|bank_status [cs_count1][(2 ** MEM_IF_BA_WIDTH) - 1 : 0]))
all_banks_closed [cs_count1] <= 1'b1;
else
all_banks_closed [cs_count1] <= 1'b0;
end
end
end
endmodule
/*
// This module (RAM) is not used anymore, this will be commented for future reference
// which will instantiate ram modules
module alt_ddrx_bank_mem #
( parameter
MEM_IF_CS_WIDTH = 4,
MEM_IF_CHIP_BITS = 2,
MEM_IF_BA_WIDTH = 3,
MEM_IF_ROW_WIDTH = 16
)
(
ctl_clk,
ctl_reset_n,
// Write Interface
write_req,
write_addr,
write_data,
// Read Interface
read_addr,
read_data
);
localparam RAM_ADDR_WIDTH = 5;
input ctl_clk;
input ctl_reset_n;
input [MEM_IF_CS_WIDTH - 1 : 0] write_req;
input [MEM_IF_BA_WIDTH - 1 : 0] write_addr;
input [MEM_IF_ROW_WIDTH - 1 : 0] write_data;
input [MEM_IF_BA_WIDTH - 1 : 0] read_addr;
output [(MEM_IF_CS_WIDTH * MEM_IF_ROW_WIDTH) - 1 : 0] read_data;
wire [(MEM_IF_CS_WIDTH * MEM_IF_ROW_WIDTH) - 1 : 0] read_data;
generate
genvar z;
for (z = 0;z < MEM_IF_CS_WIDTH;z = z + 1)
begin : ram_inst_per_chip
ram ram_inst
(
.clock (ctl_clk),
.wren (write_req [z]),
.wraddress ({{(RAM_ADDR_WIDTH - MEM_IF_BA_WIDTH){1'b0}}, write_addr}),
.data (write_data),
.rdaddress ({{(RAM_ADDR_WIDTH - MEM_IF_BA_WIDTH){1'b0}}, read_addr [MEM_IF_BA_WIDTH - 1 : 0]}),
.q (read_data [(z + 1) * MEM_IF_ROW_WIDTH - 1 : z * MEM_IF_ROW_WIDTH])
);
end
endgenerate
endmodule
*/
|
(** * Subtyping *)
(* $Date: 2011-05-07 21:28:52 -0400 (Sat, 07 May 2011) $ *)
Require Export MoreStlc.
(* ###################################################### *)
(** * Concepts *)
(** We now turn to the study of _subtyping_, perhaps the most
characteristic feature of the static type systems used by many
recently designed programming languages. *)
(* ###################################################### *)
(** ** A Motivating Example *)
(** In the simply typed lamdba-calculus with records, the term
<<
(\r:{y:Nat}. (r.y)+1) {x=10,y=11}
>>
is not typable: it involves an application of a function that wants
a one-field record to an argument that actually provides two
fields, while the [T_App] rule demands that the domain type of the
function being applied must match the type of the argument
precisely.
But this is silly: we're passing the function a _better_ argument
than it needs! The only thing the body of the function can
possibly do with its record argument [r] is project the field [y]
from it: nothing else is allowed by the type. So the presence or
absence of an extra [x] field should make no difference at all.
So, intuitively, it seems that this function should be applicable
to any record value that has at least a [y] field.
Looking at the same thing from another point of view, a record with
more fields is "at least as good in any context" as one with just a
subset of these fields, in the sense that any value belonging to
the longer record type can be used _safely_ in any context
expecting the shorter record type. If the context expects
something with the shorter type but we actually give it something
with the longer type, nothing bad will happen (formally, the
program will not get stuck).
The general principle at work here is called _subtyping_. We say
that "[S] is a subtype of [T]", informally written [S <: T], if a
value of type [S] can safely be used in any context where a value
of type [T] is expected. The idea of subtyping applies not only to
records, but to all of the type constructors in the language --
functions, pairs, etc. *)
(** ** Subtyping and Object-Oriented Languages *)
(** Subtyping plays a fundamental role in many programming
languages -- in particular, it is closely related to the notion of
_subclassing_ in object-oriented languages.
An _object_ (in Java, C[#], etc.) can be thought of as a record,
some of whose fields are functions ("methods") and some of whose
fields are data values ("fields" or "instance variables").
Invoking a method [m] of an object [o] on some arguments [a1..an]
consists of projecting out the [m] field of [o] and applying it to
[a1..an].
The type of an object can be given as either a _class_ or an
_interface_. Both of these provide a description of which methods
and which data fields the object offers.
Classes and interfaces are related by the _subclass_ and
_subinterface_ relations. An object belonging to a subclass (or
subinterface) is required to provide all the methods and fields of
one belonging to a superclass (or superinterface), plus possibly
some more.
The fact that an object from a subclass (or sub-interface) can be
used in place of one from a superclass (or super-interface) provides
a degree of flexibility that is is extremely handy for organizing
complex libraries. For example, a graphical user interface
toolkit like Java's Swing framework might define an abstract
interface [Component] that collects together the common fields and
methods of all objects having a graphical representation that can
be displayed on the screen and that can interact with the user.
Examples of such object would include the buttons, checkboxes, and
scrollbars of a typical GUI. A method that relies only on this
common interface can now be applied to any of these objects.
Of course, real object-oriented languages include many other
features besides these. Fields can be updated. Fields and
methods can be declared [private]. Classes also give _code_ that
is used when constructing objects and implementing their methods,
and the code in subclasses cooperate with code in superclasses via
_inheritance_. Classes can have static methods and fields,
initializers, etc., etc.
To keep things simple here, we won't deal with any of these
issues -- in fact, we won't even talk any more about objects or
classes. (There is a lot of discussion in Types and Programming
Languages, if you are interested.) Instead, we'll study the core
concepts behind the subclass / subinterface relation in the
simplified setting of the STLC. *)
(** ** The Subsumption Rule *)
(** Our goal for this chapter is to add subtyping to the simply typed
lambda-calculus (with products). This involves two steps:
- Defining a binary _subtype relation_ between types.
- Enriching the typing relation to take subtyping into account.
The second step is actually very simple. We add just a single rule
to the typing relation -- the so-called _rule of subsumption_:
[[[
Gamma |- t : S S <: T
------------------------- (T_Sub)
Gamma |- t : T
]]]
This rule says, intuitively, that we can "forget" some of the
information that we know about a term. *)
(** For example, we may know that [t] is a record with two
fields (e.g., [S = {x:A->A, y:B->B}]], but choose to forget about
one of the fields ([T = {y:B->B}]) so that we can pass [t] to a
function that expects just a single-field record. *)
(** ** The Subtype Relation *)
(** The first step -- the definition of the relation [S <: T] -- is
where all the action is. Let's look at each of the clauses of its
definition. *)
(** *** Products *)
(** First, product types. We consider one pair to be "better than"
another if each of its components is.
[[[
S1 <: T1 S2 <: T2
-------------------- (S_Prod)
S1*S2 <: T1*T2
]]]
*)
(** *** Arrows *)
(** Suppose we have two functions [f] and [g] with these types:
<<
f : C -> {x:A,y:B}
g : (C->{y:B}) -> D
>>
That is, [f] is a function that yields a record of type
[{x:A,y:B}], and [g] is a higher-order function that expects
its (function) argument to yield a record of type [{y:B}]. (And
suppose, even though we haven't yet discussed subtyping for
records, that [{x:A,y:B}] is a subtype of [{y:B}]) Then the
application [g f] is safe even though their types do not match up
precisely, because the only thing [g] can do with [f] is to apply
it to some argument (of type [C]); the result will actually be a
two-field record, while [g] will be expecting only a record with a
single field, but this is safe because the only thing [g] can then
do is to project out the single field that it knows about, and
this will certainly be among the two fields that are present.
This example suggests that the subtyping rule for arrow types
should say that two arrow types are in the subtype relation if
their results are:
[[[
S2 <: T2
---------------- (S_Arrow2)
S1->S2 <: S1->T2
]]]
We can generalize this to allow the arguments of the two arrow
types to be in the subtype relation as well:
[[[
T1 <: S1 S2 <: T2
-------------------- (S_Arrow)
S1->S2 <: T1->T2
]]]
Notice, here, that the argument types are subtypes "the other way
round": in order to conclude that [S1->S2] to be a subtype of
[T1->T2], it must be the case that [T1] is a subtype of [S1]. The
arrow constructor is said to be _contravariant_ in its first
argument and _covariant_ in its second.
The intuition is that, if we have a function [f] of type [S1->S2],
then we know that [f] accepts elements of type [S1]; clearly, [f]
will also accept elements of any subtype [T1] of [S1]. The type of
[f] also tells us that it returns elements of type [S2]; we can
also view these results belonging to any supertype [T2] of
[S2]. That is, any function [f] of type [S1->S2] can also be viewed
as having type [T1->T2]. *)
(** *** Top *)
(** It is natural to give the subtype relation a maximal element -- a
type that lies above every other type and is inhabited by
all (well-typed) values. We do this by adding to the language one
new type constant, called [Top], together with a subtyping rule
that places it above every other type in the subtype relation:
[[[
-------- (S_Top)
S <: Top
]]]
The [Top] type is an analog of the [Object] type in Java and C[#]. *)
(** *** Structural Rules *)
(** To finish off the subtype relation, we add two "structural rules"
that are independent of any particular type constructor: a rule of
_transitivity_, which says intuitively that, if [S] is better than
[U] and [U] is better than [T], then [S] is better than [T]...
[[[
S <: U U <: T
---------------- (S_Trans)
S <: T
]]]
... and a rule of _reflexivity_, since any type [T] is always just
as good as itself:
[[[
------ (S_Refl)
T <: T
]]]
*)
(** *** Records *)
(** What about subtyping for record types?
The basic intuition about subtyping for record types is that it is
always safe to use a "bigger" record in place of a "smaller" one.
That is, given a record type, adding extra fields will always
result in a subtype. If some code is expecting a record with
fields [x] and [y], it is perfectly safe for it to receive a record
with fields [x], [y], and [z]; the [z] field will simply be ignored.
For example,
<<
{x:Nat,y:Bool} <: {x:Nat}
{x:Nat} <: {}
>>
This is known as "width subtyping" for records.
We can also create a subtype of a record type by replacing the type
of one of its fields with a subtype. If some code is expecting a
record with a field [x] of type [T], it will be happy with a record
having a field [x] of type [S] as long as [S] is a subtype of
[T]. For example,
<<
{a:{x:Nat}} <: {a:{}}
>>
This is known as "depth subtyping".
Finally, although the fields of a record type are written in a
particular order, the order does not really matter. For example,
<<
{x:Nat,y:Bool} <: {y:Bool,x:Nat}
>>
This is known as "permutation subtyping".
We could try formalizing these requirements in a single subtyping
rule for records as follows:
[[[
for each jk in j1..jn,
exists ip in i1..im, such that
jk=ip and Sp <: Tk
---------------------------------- (S_Rcd)
{i1:S1...im:Sm} <: {j1:T1...jn:Tn}
]]]
That is, the record on the left should have all the field labels of
the one on the right (and possibly more), while the types of the
common fields should be in the subtype relation. However, This rule
is rather heavy and hard to read. If we like, we can decompose it
into three simpler rules, which can be combined using [S_Trans] to
achieve all the same effects.
First, adding fields to the end of a record type gives a subtype:
[[[
n > m
--------------------------------- (S_RcdWidth)
{i1:T1...in:Tn} <: {i1:T1...im:Tm}
]]]
We can use [S_RcdWidth] to drop later fields of a multi-field
record while keeping earlier fields, showing for example that
[{y:B, x:A} <: {y:B}].
Second, we can apply subtyping inside the components of a compound
record type:
[[[
S1 <: T1 ... Sn <: Tn
---------------------------------- (S_RcdDepth)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
]]]
For example, we can use [S_RcdDepth] and [S_RcdWidth] together to
show that [{y:{z:B}, x:A} <: {y:{}}].
Third, we need to be able to reorder fields. The example we
originally had in mind was [{x:A,y:B} <: {y:B}]. We
haven't quite achieved this yet: using just [S_RcdDepth] and
[S_RcdWidth] we can only drop fields from the _end_ of a record
type. So we need:
[[[
{i1:S1...in:Sn} is a permutation of {i1:T1...in:Tn}
--------------------------------------------------- (S_RcdPerm)
{i1:S1...in:Sn} <: {i1:T1...in:Tn}
]]]
Further examples:
- [{x:A,y:B}] <: [{y:B,x:A}].
- [{}->{j:A} <: {k:B}->Top]
- [Top->{k:A,j:B} <: C->{j:B}]
*)
(** It is worth noting that real languages may choose not to adopt
all of these subtyping rules. For example, in Java:
- A subclass may not change the argument or result types of a
method of its superclass (i.e., no depth subtyping or no arrow
subtyping, depending how you look at it).
- Each class has just one superclass ("single inheritance" of
classes)
- Each class member (field or method) can be assigned a single
index, adding new indices "on the right" as more members are
added in subclasses (i.e., no permutation for classes)
- A class may implement multiple interfaces -- so-called "multiple
inheritance" of interfaces (i.e., permutation is allowed for
interfaces). *)
(** *** Records, via Products and Top (optional) *)
(** Exactly how we formalize all this depends on how we are choosing
to formalize records and their types. If we are treating them as
part of the core language, then we need to write down subtyping
rules for them. The file [RecordSub.v] shows how this extension
works.
On the other hand, if we are treating them as a derived form that
is desugared in the parser, then we shouldn't need any new rules:
we should just check that the existing rules for subtyping product
and [Unit] types give rise to reasonable rules for record
subtyping via this encoding. To do this, we just need to make one
small change to the encoding described earlier: instead of using
[Unit] as the base case in the encoding of tuples and the "don't
care" placeholder in the encoding of records, we use [Top]. So:
<<
{a:Nat, b:Nat} ----> {Nat,Nat} i.e. (Nat,(Nat,Top))
{c:Nat, a:Nat} ----> {Nat,Top,Nat} i.e. (Nat,(Top,(Nat,Top)))
>>
The encoding of record values doesn't change at all. It is
easy (and instructive) to check that the subtyping rules above are
validated by the encoding. For the rest of this chapter, we'll
follow this approach. *)
(* ###################################################### *)
(** * Core definitions *)
(** We've already sketched the significant extensions that we'll need
to make to the STLC: (1) add the subtype relation and (2) extend
the typing relation with the rule of subsumption. To make
everything work smoothly, we'll also implement some technical
improvements to the presentation from the last chapter. The rest
of the definitions -- in particular, the syntax and operational
semantics of the language -- are identical to what we saw in the
last chapter. Let's first do the identical bits. *)
(* ################################### *)
(** *** Syntax *)
(** Just for the sake of more interesting examples, we'll make one
more very small extension to the pure STLC: an arbitrary set of
additional _base types_ like [String], [Person], [Window], etc.
We won't bother adding any constants belonging to these types or
any operators on them, but we could easily do so. *)
(** In the rest of the chapter, we formalize just base types,
booleans, arrow types, [Unit], and [Top], leaving product types as
an exercise. *)
Inductive ty : Type :=
| ty_Top : ty
| ty_Bool : ty
| ty_base : id -> ty
| ty_arrow : ty -> ty -> ty
| ty_Unit : ty
.
Tactic Notation "ty_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ty_Top" | Case_aux c "ty_Bool"
| Case_aux c "ty_base" | Case_aux c "ty_arrow"
| Case_aux c "ty_Unit" |
].
Inductive tm : Type :=
| tm_var : id -> tm
| tm_app : tm -> tm -> tm
| tm_abs : id -> ty -> tm -> tm
| tm_true : tm
| tm_false : tm
| tm_if : tm -> tm -> tm -> tm
| tm_unit : tm
.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tm_var" | Case_aux c "tm_app"
| Case_aux c "tm_abs" | Case_aux c "tm_true"
| Case_aux c "tm_false" | Case_aux c "tm_if"
| Case_aux c "tm_unit"
].
(* ################################### *)
(** *** Substitution *)
(** The definition of substitution remains the same as for the
ordinary STLC. *)
Fixpoint subst (s:tm) (x:id) (t:tm) : tm :=
match t with
| tm_var y =>
if beq_id x y then s else t
| tm_abs y T t1 =>
tm_abs y T (if beq_id x y then t1 else (subst s x t1))
| tm_app t1 t2 =>
tm_app (subst s x t1) (subst s x t2)
| tm_true =>
tm_true
| tm_false =>
tm_false
| tm_if t1 t2 t3 =>
tm_if (subst s x t1) (subst s x t2) (subst s x t3)
| tm_unit =>
tm_unit
end.
(* ################################### *)
(** *** Reduction *)
(** Likewise the definitions of the [value] property and the [step]
relation. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tm_abs x T t)
| t_true :
value tm_true
| t_false :
value tm_false
| v_unit :
value tm_unit
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tm_app (tm_abs x T t12) v2) ==> (subst v2 x t12)
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tm_app t1 t2) ==> (tm_app t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tm_app v1 t2) ==> (tm_app v1 t2')
| ST_IfTrue : forall t1 t2,
(tm_if tm_true t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tm_if tm_false t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tm_if t1 t2 t3) ==> (tm_if t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
].
Hint Constructors step.
(* ###################################################################### *)
(** * Subtyping *)
(** Now we come to the interesting part. We begin by defining
the subtyping relation and developing some of its important
technical properties. *)
(* ################################### *)
(** ** Definition *)
(** The definition of subtyping is just what we sketched in the
motivating discussion. *)
Inductive subtype : ty -> ty -> Prop :=
| S_Refl : forall T,
subtype T T
| S_Trans : forall S U T,
subtype S U ->
subtype U T ->
subtype S T
| S_Top : forall S,
subtype S ty_Top
| S_Arrow : forall S1 S2 T1 T2,
subtype T1 S1 ->
subtype S2 T2 ->
subtype (ty_arrow S1 S2) (ty_arrow T1 T2)
.
(** Note that we don't need any special rules for base types: they are
automatically subtypes of themselves (by [S_Refl]) and [Top] (by
[S_Top]), and that's all we want. *)
Hint Constructors subtype.
Tactic Notation "subtype_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "S_Refl" | Case_aux c "S_Trans"
| Case_aux c "S_Top" | Case_aux c "S_Arrow"
].
(* ############################################### *)
(** ** Subtyping Examples and Exercises *)
Module Examples.
Notation x := (Id 0).
Notation y := (Id 1).
Notation z := (Id 2).
Notation A := (ty_base (Id 6)).
Notation B := (ty_base (Id 7)).
Notation C := (ty_base (Id 8)).
Notation String := (ty_base (Id 9)).
Notation Float := (ty_base (Id 10)).
Notation Integer := (ty_base (Id 11)).
(** **** Exercise: 2 stars, optional (subtyping judgements) *)
(** (Do this exercise after you have added product types to the
language, at least up to this point in the file).
Using the encoding of records into pairs, define pair types
representing the record types
[[
Person := { name : String }
Student := { name : String ;
gpa : Float }
Employee := { name : String ;
ssn : Integer }
]]
*)
Definition Person : ty :=
(* FILL IN HERE *) admit.
Definition Student : ty :=
(* FILL IN HERE *) admit.
Definition Employee : ty :=
(* FILL IN HERE *) admit.
Example sub_student_person :
subtype Student Person.
Proof.
(* FILL IN HERE *) Admitted.
Example sub_employee_person :
subtype Employee Person.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Example subtyping_example_0 :
subtype (ty_arrow C Person)
(ty_arrow C ty_Top).
(* C->Person <: C->Top *)
Proof.
apply S_Arrow.
apply S_Refl. auto.
Qed.
(** The following facts are mostly easy to prove in Coq. To get
full benefit from the exercises, make sure you also
understand how to prove them on paper! *)
(** **** Exercise: 1 star, optional (subtyping_example_1) *)
Example subtyping_example_1 :
subtype (ty_arrow ty_Top Student)
(ty_arrow (ty_arrow C C) Person).
(* Top->Student <: (C->C)->Person *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (subtyping_example_2) *)
Example subtyping_example_2 :
subtype (ty_arrow ty_Top Person)
(ty_arrow Person ty_Top).
(* Top->Person <: Person->Top *)
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
End Examples.
(** **** Exercise: 1 star, optional (subtype_instances_tf_1) *)
(** Suppose we have types [S], [T], [U], and [V] with [S <: T]
and [U <: V]. Which of the following subtyping assertions
are then true? Write _true_ or _false_ after each one.
(Note that [A], [B], and [C] are base types.)
- [T->S <: T->S]
- [Top->U <: S->Top]
- [(C->C) -> (A*B) <: (C->C) -> (Top*B)]
- [T->T->U <: S->S->V]
- [(T->T)->U <: (S->S)->V]
- [((T->S)->T)->U <: ((S->T)->S)->V]
- [S*V <: T*U]
[]
*)
(** **** Exercise: 1 star (subtype_instances_tf_2) *)
(** Which of the following statements are true? Write TRUE or FALSE
after each one.
[[
forall S T,
S <: T ->
S->S <: T->T
forall S T,
S <: A->A ->
exists T,
S = T->T /\ T <: A
forall S T1 T1,
S <: T1 -> T2 ->
exists S1 S2,
S = S1 -> S2 /\ T1 <: S1 /\ S2 <: T2
exists S,
S <: S->S
exists S,
S->S <: S
forall S T2 T2,
S <: T1*T2 ->
exists S1 S2,
S = S1*S2 /\ S1 <: T1 /\ S2 <: T2
]]
[] *)
(** **** Exercise: 1 star (subtype_concepts_tf) *)
(** Which of the following statements are true, and which are false?
- There exists a type that is a supertype of every other type.
- There exists a type that is a subtype of every other type.
- There exists a pair type that is a supertype of every other
pair type.
- There exists a pair type that is a subtype of every other
pair type.
- There exists an arrow type that is a supertype of every other
arrow type.
- There exists an arrow type that is a subtype of every other
arrow type.
- There is an infinite descending chain of distinct types in the
subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a subtype of [Si].
- There is an infinite _ascending_ chain of distinct types in
the subtype relation---that is, an infinite sequence of types
[S0], [S1], etc., such that all the [Si]'s are different and
each [S(i+1)] is a supertype of [Si].
[]
*)
(** **** Exercise: 2 stars (proper_subtypes) *)
(** Is the following statement true or false? Briefly explain your
answer.
[[
forall T,
~(exists n, T = ty_base n) ->
exists S,
S <: T /\ S <> T
]]
[]
*)
(** **** Exercise: 2 stars (small_large_1) *)
(**
- What is the _smallest_ type [T] ("smallest" in the subtype
relation) that makes the following assertion true?
[[
empty |- (\p:T*Top. p.fst) ((\z:A.z), unit) : A->A
]]
- What is the _largest_ type [T] that makes the same assertion true?
[]
*)
(** **** Exercise: 2 stars (small_large_2) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
[[
empty |- (\p:(A->A * B->B). p) ((\z:A.z), (\z:B.z)) : T
]]
- What is the _largest_ type [T] that makes the same assertion true?
[]
*)
(** **** Exercise: 2 stars, optional (small_large_3) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
[[
a:A |- (\p:(A*T). (p.snd) (p.fst)) (a , \z:A.z) : A
]]
- What is the _largest_ type [T] that makes the same assertion true?
[]
*)
(** **** Exercise: 2 stars (small_large_4) *)
(**
- What is the _smallest_ type [T] that makes the following
assertion true?
[[
exists S,
empty |- (\p:(A*T). (p.snd) (p.fst)) : S
]]
- What is the _largest_ type [T] that makes the same
assertion true?
[]
*)
(** **** Exercise: 2 stars (smallest_1) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
[[
exists S, exists t,
empty |- (\x:T. x x) t : S
]]
[]
*)
(** **** Exercise: 2 stars (smallest_2) *)
(** What is the _smallest_ type [T] that makes the following
assertion true?
[[
empty |- (\x:Top. x) ((\z:A.z) , (\z:B.z)) : T
]]
[]
*)
(** **** Exercise: 3 stars, optional (count_supertypes) *)
(** How many supertypes does the record type [{x:A, y:C->C}] have? That is,
how many different types [T] are there such that [{x:A, y:C->C} <:
T]? (We consider two types to be different if they are written
differently, even if each is a subtype of the other. For example,
[{x:A,y:B}] and [{y:B,x:A}] are different.)
[]
*)
(* ###################################################################### *)
(** * Typing *)
(** The only change to the typing relation is the addition of the rule
of subsumption, [T_Sub]. *)
Definition context := id -> (option ty).
Definition empty : context := (fun _ => None).
Definition extend (Gamma : context) (x:id) (T : ty) :=
fun x' => if beq_id x x' then Some T else Gamma x'.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Same as before *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tm_var x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tm_abs x T11 t12) (ty_arrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (ty_arrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tm_app t1 t2) T2
| T_True : forall Gamma,
has_type Gamma tm_true ty_Bool
| T_False : forall Gamma,
has_type Gamma tm_false ty_Bool
| T_If : forall t1 t2 t3 T Gamma,
has_type Gamma t1 ty_Bool ->
has_type Gamma t2 T ->
has_type Gamma t3 T ->
has_type Gamma (tm_if t1 t2 t3) T
| T_Unit : forall Gamma,
has_type Gamma tm_unit ty_Unit
(* New rule of subsumption *)
| T_Sub : forall Gamma t S T,
has_type Gamma t S ->
subtype S T ->
has_type Gamma t T.
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Unit"
| Case_aux c "T_Sub" ].
(* ############################################### *)
(** ** Typing examples *)
Module Examples2.
Import Examples.
(** Do the following exercises after you have added product types to
the language. For each informal typing judgement, write it as a
formal statement in Coq and prove it. *)
(** **** Exercise: 1 star, optional (typing_example_0) *)
(* empty |- ((\z:A.z), (\z:B.z)) : (A->A * B->B) *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_1) *)
(* empty |- (\x:(Top * B->B). x.snd) ((\z:A.z), (\z:B.z)) : B->B *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional (typing_example_2) *)
(* empty |- (\z:(C->C)->(Top * B->B). (z (\x:C.x)).snd)
(\z:C->C. ((\z:A.z), (\z:B.z)))
: B->B *)
(* FILL IN HERE *)
(** [] *)
End Examples2.
(* ###################################################################### *)
(** * Properties *)
(** The fundamental properties of the system that we want to check are
the same as always: progress and preservation. Unlike the
extension of the STLC with references, we don't need to change the
_statements_ of these properties to take subtyping into account.
However, their proofs do become a little bit more involved. *)
(* ###################################################################### *)
(** ** Inversion Lemmas for Subtyping *)
(** Before we look at the properties of the typing relation, we need
to record a couple of critical structural properties of the subtype
relation:
- [Bool] is the only subtype of [Bool]
- every subtype of an arrow type _is_ an arrow type. *)
(** These are called _inversion lemmas_ because they play the same
role in later proofs as the built-in [inversion] tactic: given a
hypothesis that there exists a derivation of some subtyping
statement [S <: T] and some constraints on the shape of [S] and/or
[T], each one reasons about what this derivation must look like to
tell us something further about the shapes of [S] and [T] and the
existence of subtype relations between their parts. *)
(** **** Exercise: 2 stars, optional (sub_inversion_Bool) *)
Lemma sub_inversion_Bool : forall U,
subtype U ty_Bool ->
U = ty_Bool.
Proof with auto.
intros U Hs.
remember ty_Bool as V.
(* FILL IN HERE *) Admitted.
(** **** Exercise: 3 stars, optional (sub_inversion_arrow) *)
Lemma sub_inversion_arrow : forall U V1 V2,
subtype U (ty_arrow V1 V2) ->
exists U1, exists U2,
U = (ty_arrow U1 U2) /\ (subtype V1 U1) /\ (subtype U2 V2).
Proof with eauto.
intros U V1 V2 Hs.
remember (ty_arrow V1 V2) as V.
generalize dependent V2. generalize dependent V1.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################## *)
(** ** Canonical Forms *)
(** We'll see first that the proof of the progress theorem doesn't
change too much -- we just need one small refinement. When we're
considering the case where the term in question is an application
[t1 t2] where both [t1] and [t2] are values, we need to know that
[t1] has the _form_ of a lambda-abstraction, so that we can apply
the [ST_AppAbs] reduction rule. In the ordinary STLC, this is
obvious: we know that [t1] has a function type [T11->T12], and
there is only one rule that can be used to give a function type to
a value -- rule [T_Abs] -- and the form of the conclusion of this
rule forces [t1] to be an abstraction.
In the STLC with subtyping, this reasoning doesn't quite work
because there's another rule that can be used to show that a value
has a function type: subsumption. Fortunately, this possibility
doesn't change things much: if the last rule used to show [Gamma
|- t1 : T11->T12] is subsumption, then there is some
_sub_-derivation whose subject is also [t1], and we can reason by
induction until we finally bottom out at a use of [T_Abs].
This bit of reasoning is packaged up in the following lemma, which
tells us the possible "canonical forms" (i.e. values) of function
type. *)
(** **** Exercise: 3 stars, optional (canonical_forms_of_arrow_types) *)
Lemma canonical_forms_of_arrow_types : forall Gamma s T1 T2,
has_type Gamma s (ty_arrow T1 T2) ->
value s ->
exists x, exists S1, exists s2,
s = tm_abs x S1 s2.
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Similarly, the canonical forms of type [Bool] are the constants
[true] and [false]. *)
Lemma canonical_forms_of_Bool : forall Gamma s,
has_type Gamma s ty_Bool ->
value s ->
(s = tm_true \/ s = tm_false).
Proof with eauto.
intros Gamma s Hty Hv.
remember ty_Bool as T.
has_type_cases (induction Hty) Case; try solve by inversion...
Case "T_Sub".
subst. apply sub_inversion_Bool in H. subst...
Qed.
(* ########################################## *)
(** ** Progress *)
(** The proof of progress proceeds like the one for the pure
STLC, except that in several places we invoke canonical forms
lemmas... *)
(** _Theorem_ (Progress): For any term [t] and type [T], if [empty |-
t : T] then [t] is a value or [t ==> t'] for some term [t'].
_Proof_: Let [t] and [T] be given, with [empty |- t : T]. Proceed
by induction on the typing derivation.
The cases for [T_Abs], [T_Unit], [T_True] and [T_False] are
immediate because abstractions, [unit], [true], and [false] are
already values. The [T_Var] case is vacuous because variables
cannot be typed in the empty context. The remaining cases are
more interesting:
- If the last step in the typing derivation uses rule [T_App],
then there are terms [t1] [t2] and types [T1] and [T2] such that
[t = t1 t2], [T = T2], [empty |- t1 : T1 -> T2], and [empty |-
t2 : T1]. Moreover, by the induction hypothesis, either [t1] is
a value or it steps, and either [t2] is a value or it steps.
There are three possibilities to consider:
- Suppose [t1 ==> t1'] for some term [t1']. Then [t1 t2 ==> t1' t2]
by [ST_App1].
- Suppose [t1] is a value and [t2 ==> t2'] for some term [t2'].
Then [t1 t2 ==> t1 t2'] by rule [ST_App2] because [t1] is a
value.
- Finally, suppose [t1] and [t2] are both values. By Lemma
[canonical_forms_for_arrow_types], we know that [t1] has the
form [\x:S1.s2] for some [x], [S1], and [s2]. But then
[(\x:S1.s2) t2 ==> [t2/x]s2] by [ST_AppAbs], since [t2] is a
value.
- If the final step of the derivation uses rule [T_If], then there
are terms [t1], [t2], and [t3] such that [t = if t1 then t2 else
t3], with [empty |- t1 : Bool] and with [empty |- t2 : T] and
[empty |- t3 : T]. Moreover, by the induction hypothesis,
either [t1] is a value or it steps.
- If [t1] is a value, then by the canonical forms lemma for
booleans, either [t1 = true] or [t1 = false]. In either
case, [t] can step, using rule [ST_IfTrue] or [ST_IfFalse].
- If [t1] can step, then so can [t], by rule [ST_If].
- If the final step of the derivation is by [T_Sub], then there is
a type [S] such that [S <: T] and [empty |- t : S]. The desired
result is exactly the induction hypothesis for the typing
subderivation.
*)
Theorem progress : forall t T,
has_type empty t T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t T Ht.
remember empty as Gamma.
revert HeqGamma.
has_type_cases (induction Ht) Case;
intros HeqGamma; subst...
Case "T_Var".
inversion H.
Case "T_App".
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
destruct (canonical_forms_of_arrow_types empty t1 T1 T2)
as [x [S1 [t12 Heqt1]]]...
subst. exists (subst t2 x t12)...
SSCase "t2 steps".
destruct H0 as [t2' Hstp]. exists (tm_app t1 t2')...
SCase "t1 steps".
destruct H as [t1' Hstp]. exists (tm_app t1' t2)...
Case "T_If".
right.
destruct IHHt1.
SCase "t1 is a value"...
assert (t1 = tm_true \/ t1 = tm_false)
by (eapply canonical_forms_of_Bool; eauto).
inversion H0; subst...
destruct H. rename x into t1'. eauto.
Qed.
(* ########################################## *)
(** ** Inversion Lemmas for Typing *)
(** The proof of the preservation theorem also becomes a little more
complex with the addition of subtyping. The reason is that, as
with the "inversion lemmas for subtyping" above, there are a
number of facts about the typing relation that are "obvious from
the definition" in the pure STLC (and hence can be obtained
directly from the [inversion] tactic) but that require real proofs
in the presence of subtyping because there are multiple ways to
derive the same [has_type] statement.
The following "inversion lemma" tells us that, if we have a
derivation of some typing statement [Gamma |- \x:S1.t2 : T] whose
subject is an abstraction, then there must be some subderivation
giving a type to the body [t2]. *)
(** _Lemma_: If [Gamma |- \x:S1.t2 : T], then there is a type [S2]
such that [Gamma, x:S1 |- t2 : S2] and [S1 -> S2 <: T].
(Notice that the lemma does _not_ say, "then [T] itself is an arrow
type" -- this is tempting, but false!)
_Proof_: Let [Gamma], [x], [S1], [t2] and [T] be given as
described. Proceed by induction on the derivation of [Gamma |-
\x:S1.t2 : T]. Cases [T_Var], [T_App], are vacuous as those
rules cannot be used to give a type to a syntactic abstraction.
- If the last step of the derivation is a use of [T_Abs] then
there is a type [T12] such that [T = S1 -> T12] and [Gamma,
x:S1 |- t2 : T12]. Picking [T12] for [S2] gives us what we
need: [S1 -> T12 <: S1 -> T12] follows from [S_Refl].
- If the last step of the derivation is a use of [T_Sub] then
there is a type [S] such that [S <: T] and [Gamma |- \x:S1.t2 :
S]. The IH for the typing subderivation tell us that there is
some type [S2] with [S1 -> S2 <: S] and [Gamma, x:S1 |- t2 :
S2]. Picking type [S2] gives us what we need, since [S1 -> S2
<: T] then follows by [S_Trans]. *)
Lemma typing_inversion_abs : forall Gamma x S1 t2 T,
has_type Gamma (tm_abs x S1 t2) T ->
(exists S2, subtype (ty_arrow S1 S2) T
/\ has_type (extend Gamma x S1) t2 S2).
Proof with eauto.
intros Gamma x S1 t2 T H.
remember (tm_abs x S1 t2) as t.
has_type_cases (induction H) Case;
inversion Heqt; subst; intros; try solve by inversion.
Case "T_Abs".
exists T12...
Case "T_Sub".
destruct IHhas_type as [S2 [Hsub Hty]]...
Qed.
(** Similarly... *)
Lemma typing_inversion_var : forall Gamma x T,
has_type Gamma (tm_var x) T ->
exists S,
Gamma x = Some S /\ subtype S T.
Proof with eauto.
intros Gamma x T Hty.
remember (tm_var x) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_Var".
exists T...
Case "T_Sub".
destruct IHHty as [U [Hctx HsubU]]... Qed.
Lemma typing_inversion_app : forall Gamma t1 t2 T2,
has_type Gamma (tm_app t1 t2) T2 ->
exists T1,
has_type Gamma t1 (ty_arrow T1 T2) /\
has_type Gamma t2 T1.
Proof with eauto.
intros Gamma t1 t2 T2 Hty.
remember (tm_app t1 t2) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_App".
exists T1...
Case "T_Sub".
destruct IHHty as [U1 [Hty1 Hty2]]...
Qed.
Lemma typing_inversion_true : forall Gamma T,
has_type Gamma tm_true T ->
subtype ty_Bool T.
Proof with eauto.
intros Gamma T Htyp. remember tm_true as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_false : forall Gamma T,
has_type Gamma tm_false T ->
subtype ty_Bool T.
Proof with eauto.
intros Gamma T Htyp. remember tm_false as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
Lemma typing_inversion_if : forall Gamma t1 t2 t3 T,
has_type Gamma (tm_if t1 t2 t3) T ->
has_type Gamma t1 ty_Bool
/\ has_type Gamma t2 T
/\ has_type Gamma t3 T.
Proof with eauto.
intros Gamma t1 t2 t3 T Hty.
remember (tm_if t1 t2 t3) as t.
has_type_cases (induction Hty) Case; intros;
inversion Heqt; subst; try solve by inversion.
Case "T_If".
auto.
Case "T_Sub".
destruct (IHHty H0) as [H1 [H2 H3]]...
Qed.
Lemma typing_inversion_unit : forall Gamma T,
has_type Gamma tm_unit T ->
subtype ty_Unit T.
Proof with eauto.
intros Gamma T Htyp. remember tm_unit as tu.
has_type_cases (induction Htyp) Case;
inversion Heqtu; subst; intros...
Qed.
(** The inversion lemmas for typing and for subtyping between arrow
types can be packaged up as a useful "combination lemma" telling
us exactly what we'll actually require below. *)
Lemma abs_arrow : forall x S1 s2 T1 T2,
has_type empty (tm_abs x S1 s2) (ty_arrow T1 T2) ->
subtype T1 S1
/\ has_type (extend empty x S1) s2 T2.
Proof with eauto.
intros x S1 s2 T1 T2 Hty.
apply typing_inversion_abs in Hty.
destruct Hty as [S2 [Hsub Hty]].
apply sub_inversion_arrow in Hsub.
destruct Hsub as [U1 [U2 [Heq [Hsub1 Hsub2]]]].
inversion Heq; subst... Qed.
(* ########################################## *)
(** ** Context Invariance *)
(** The context invariance lemma follows the same pattern as in the
pure STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tm_var x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tm_app t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tm_app t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tm_abs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tm_if t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tm_if t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tm_if t1 t2 t3)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros x0 Hafi.
unfold extend. remember (beq_id x x0) as e.
destruct e...
Case "T_App".
apply T_App with T1...
Case "T_If".
apply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case;
subst; inversion Hafi; subst...
Case "T_Abs".
destruct (IHHtyp H4) as [T Hctx]. exists T.
unfold extend in Hctx. apply not_eq_beq_id_false in H2.
rewrite H2 in Hctx... Qed.
(* ########################################## *)
(** ** Substitution *)
(** The _substitution lemma_ is proved along the same lines as for the
pure STLC. The only significant change is that there are several
places where, instead of the built-in [inversion] tactic, we use
the inversion lemmas that we proved above to extract structural
information from assumptions about the well-typedness of
subterms. *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma (subst v x t) S.
Proof with eauto.
intros Gamma x U v t S Htypt Htypv.
generalize dependent S. generalize dependent Gamma.
tm_cases (induction t) Case; intros; simpl.
Case "tm_var".
rename i into y.
destruct (typing_inversion_var _ _ _ Htypt)
as [T [Hctx Hsub]].
unfold extend in Hctx.
remember (beq_id x y) as e. destruct e...
SCase "x=y".
apply beq_id_eq in Heqe. subst.
inversion Hctx; subst. clear Hctx.
apply context_invariance with empty...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra)
as [T' HT']...
inversion HT'.
Case "tm_app".
destruct (typing_inversion_app _ _ _ _ Htypt)
as [T1 [Htypt1 Htypt2]].
eapply T_App...
Case "tm_abs".
rename i into y. rename t into T1.
destruct (typing_inversion_abs _ _ _ _ _ Htypt)
as [T2 [Hsub Htypt2]].
apply T_Sub with (ty_arrow T1 T2)... apply T_Abs...
remember (beq_id x y) as e. destruct e.
SCase "x=y".
eapply context_invariance...
apply beq_id_eq in Heqe. subst.
intros x Hafi. unfold extend.
destruct (beq_id y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
remember (beq_id y z) as e0. destruct e0...
apply beq_id_eq in Heqe0. subst.
rewrite <- Heqe...
Case "tm_true".
assert (subtype ty_Bool S)
by apply (typing_inversion_true _ _ Htypt)...
Case "tm_false".
assert (subtype ty_Bool S)
by apply (typing_inversion_false _ _ Htypt)...
Case "tm_if".
assert (has_type (extend Gamma x U) t1 ty_Bool
/\ has_type (extend Gamma x U) t2 S
/\ has_type (extend Gamma x U) t3 S)
by apply (typing_inversion_if _ _ _ _ _ Htypt).
destruct H as [H1 [H2 H3]].
apply IHt1 in H1. apply IHt2 in H2. apply IHt3 in H3.
auto.
Case "tm_unit".
assert (subtype ty_Unit S)
by apply (typing_inversion_unit _ _ Htypt)...
Qed.
(* ########################################## *)
(** ** Preservation *)
(** The proof of preservation now proceeds pretty much as in earlier
chapters, using the substitution lemma at the appropriate point
and again using inversion lemmas from above to extract structural
information from typing assumptions. *)
(** _Theorem_ (Preservation): If [t], [t'] are terms and [T] is a type
such that [empty |- t : T] and [t ==> t'], then [empty |- t' :
T].
_Proof_: Let [t] and [T] be given such that [empty |- t : T]. We
go by induction on the structure of this typing derivation,
leaving [t'] general. The cases [T_Abs], [T_Unit], [T_True], and
[T_False] cases are vacuous because abstractions and constants
don't step. Case [T_Var] is vacuous as well, since the context is
empty.
- If the final step of the derivation is by [T_App], then there
are terms [t1] [t2] and types [T1] [T2] such that [t = t1 t2],
[T = T2], [empty |- t1 : T1 -> T2] and [empty |- t2 : T1].
By inspection of the definition of the step relation, there are
three ways [t1 t2] can step. Cases [ST_App1] and [ST_App2]
follow immediately by the induction hypotheses for the typing
subderivations and a use of [T_App].
Suppose instead [t1 t2] steps by [ST_AppAbs]. Then [t1 =
\x:S.t12] for some type [S] and term [t12], and [t' =
[t2/x]t12].
By lemma [abs_arrow], we have [T1 <: S] and [x:S1 |- s2 : T2].
It then follows by the substitution lemma
([substitution_preserves_typing]) that [empty |- [t2/x]
t12 : T2] as desired.
- If the final step of the derivation uses rule [T_If], then
there are terms [t1], [t2], and [t3] such that [t = if t1 then
t2 else t3], with [empty |- t1 : Bool] and with [empty |- t2 :
T] and [empty |- t3 : T]. Moreover, by the induction
hypothesis, if [t1] steps to [t1'] then [empty |- t1' : Bool].
There are three cases to consider, depending on which rule was
used to show [t ==> t'].
- If [t ==> t'] by rule [ST_If], then [t' = if t1' then t2
else t3] with [t1 ==> t1']. By the induction hypothesis,
[empty |- t1' : Bool], and so [empty |- t' : T] by [T_If].
- If [t ==> t'] by rule [ST_IfTrue] or [ST_IfFalse], then
either [t' = t2] or [t' = t3], and [empty |- t' : T]
follows by assumption.
- If the final step of the derivation is by [T_Sub], then there
is a type [S] such that [S <: T] and [empty |- t : S]. The
result is immediate by the induction hypothesis for the typing
subderivation and an application of [T_Sub]. [] *)
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
remember empty as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
inversion HE; subst...
SCase "ST_AppAbs".
destruct (abs_arrow _ _ _ _ _ HT1) as [HA1 HA2].
apply substitution_preserves_typing with T...
Qed.
(* ###################################################### *)
(** ** Exercises on Typing *)
(** **** Exercise: 2 stars (variations) *)
(** Each part of this problem suggests a different way of
changing the definition of the STLC with Unit and
subtyping. (These changes are not cumulative: each part
starts from the original language.) In each part, list which
properties (Progress, Preservation, both, or neither) become
false. If a property becomes false, give a counterexample.
- Suppose we add the following typing rule:
[[[
Gamma |- t : S1->S2
S1 <: T1 T1 <: S1 S2 <: T2
----------------------------------- (T_Funny1)
Gamma |- t : T1->T2
]]]
- Suppose we add the following reduction rule:
[[[
------------------ (ST_Funny21)
unit ==> (\x:Top. x)
]]]
- Suppose we add the following subtyping rule:
[[[
-------------- (S_Funny3)
Unit <: Top->Top
]]]
- Suppose we add the following subtyping rule:
[[[
-------------- (S_Funny4)
Top->Top <: Unit
]]]
- Suppose we add the following evaluation rule:
[[[
----------------- (ST_Funny5)
(unit t) ==> (t unit)
]]]
- Suppose we add the same evaluation rule _and_ a new typing rule:
[[[
----------------- (ST_Funny5)
(unit t) ==> (t unit)
---------------------- (T_Funny6)
empty |- Unit : Top->Top
]]]
- Suppose we _change_ the arrow subtyping rule to:
[[[
S1 <: T1 S2 <: T2
----------------------- (S_Arrow')
S1->S2 <: T1->T2
]]]
[]
*)
(* ###################################################################### *)
(** * Exercise: Adding Products *)
(** **** Exercise: 4 stars, optional (products) *)
(** Adding pairs, projections, and product types to the system we have
defined is a relatively straightforward matter. Carry out this
extension:
- Add constructors for pairs, first and second projections, and
product types to the definitions of [ty] and [tm]. (Don't
forget to add corresponding cases to [ty_cases] and [tm_cases].)
- Extend the well-formedness relation in the obvious way.
- Extend the operational semantics with the same reduction rules
as in the last chapter.
- Extend the subtyping relation with this rule:
[[[
S1 <: T1 S2 <: T2
--------------------- (Sub_Prod)
S1 * S2 <: T1 * T2
]]]
- Extend the typing relation with the same rules for pairs and
projections as in the last chapter.
- Extend the proofs of progress, preservation, and all their
supporting lemmas to deal with the new constructs. (You'll also
need to add some completely new lemmas.) []
*)
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response Up-Sizer
// Extract SI-side Data from packed and unpacked MI-side data.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_r_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_S_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_fix,
input wire cmd_modified,
input wire cmd_complete_wrap,
input wire cmd_packed_wrap,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_S_AXI_BYTES_LOG:0] cmd_step,
input wire [8-1:0] cmd_length,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
wire sel_first_word;
reg first_word;
reg [C_M_AXI_BYTES_LOG-1:0] current_word_1;
reg [C_M_AXI_BYTES_LOG-1:0] current_word_cmb;
wire [C_M_AXI_BYTES_LOG-1:0] current_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire last_beat;
wire last_word;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;
// Sub-word handling for the next cycle.
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;
reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
wire first_mi_word;
wire [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Handle wrap buffering.
wire store_in_wrap_buffer;
reg use_wrap_buffer;
reg wrap_buffer_available;
reg [2-1:0] rresp_wrap_buffer;
// Throttling help signals.
wire next_word_wrap;
wire word_complete_next_wrap;
wire word_complete_next_wrap_ready;
wire word_complete_next_wrap_pop;
wire word_complete_last_word;
wire word_complete_rest;
wire word_complete_rest_ready;
wire word_complete_rest_pop;
wire word_completed;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data;
wire si_stalling;
// Internal signals for MI-side.
reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA_I;
wire M_AXI_RLAST_I;
wire M_AXI_RVALID_I;
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Determine if a MI side word has been completely used. For FIX transactions
// the MI-side word is used to extract a single data word. This is also true
// for for an upsizer in Expander mode (Never Pack). Unmodified burst also
// only use the MI word to extract a single SI-side word (although with
// different offsets).
// Otherwise is the MI-side word considered to be used when last SI-side beat
// has been extracted or when the last (most significant) SI-side word has
// been extracted from ti MI word.
//
// Data on the SI-side is available when data is being taken from MI-side or
// from wrap buffer.
//
// The command is popped from the command queue once the last beat on the
// SI-side has been ackowledged.
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING
assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};
end else begin : NO_LARGE_UPSIZING
assign cmd_step_i = cmd_step;
end
endgenerate
generate
if ( C_FAMILY == "rtl" ||
( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED
// Detect when MI-side word is completely used.
assign word_completed = cmd_valid &
( ( cmd_fix ) |
( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( ~cmd_fix & last_word & ~use_wrap_buffer ) |
( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) |
( C_PACKING_LEVEL == C_NEVER_PACK ) );
// RTL equivalent of optimized partial extressions (address wrap for next word).
assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_complete_next_wrap_ready = word_complete_next_wrap & M_AXI_RVALID_I & ~si_stalling;
assign word_complete_next_wrap_pop = word_complete_next_wrap_ready & M_AXI_RVALID_I;
// RTL equivalent of optimized partial extressions (last word and the remaining).
assign word_complete_last_word = last_word & (~cmd_fix & ~use_wrap_buffer);
assign word_complete_rest = word_complete_last_word | cmd_fix |
( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );
assign word_complete_rest_ready = word_complete_rest & M_AXI_RVALID_I & ~si_stalling;
assign word_complete_rest_pop = word_complete_rest_ready & M_AXI_RVALID_I;
end else begin : USE_FPGA_WORD_COMPLETED
wire sel_word_complete_next_wrap;
wire sel_word_completed;
wire sel_m_axi_rready;
wire sel_word_complete_last_word;
wire sel_word_complete_rest;
// Optimize next word address wrap branch of expression.
//
generic_baseblocks_v2_1_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) next_word_wrap_inst
(
.CIN(1'b1),
.S(sel_first_word),
.A(pre_next_word_1),
.B(cmd_next_word),
.COUT(next_word_wrap)
);
assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_inst
(
.CIN(next_word_wrap),
.S(sel_word_complete_next_wrap),
.COUT(word_complete_next_wrap)
);
assign sel_m_axi_rready = cmd_valid & S_AXI_RREADY_I;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_ready_inst
(
.CIN(word_complete_next_wrap),
.S(sel_m_axi_rready),
.COUT(word_complete_next_wrap_ready)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_pop_inst
(
.CIN(word_complete_next_wrap_ready),
.S(M_AXI_RVALID_I),
.COUT(word_complete_next_wrap_pop)
);
// Optimize last word and "rest" branch of expression.
//
assign sel_word_complete_last_word = ~cmd_fix & ~use_wrap_buffer;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_last_word_inst
(
.CIN(last_word),
.S(sel_word_complete_last_word),
.COUT(word_complete_last_word)
);
assign sel_word_complete_rest = cmd_fix | ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );
generic_baseblocks_v2_1_carry_or #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_inst
(
.CIN(word_complete_last_word),
.S(sel_word_complete_rest),
.COUT(word_complete_rest)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_ready_inst
(
.CIN(word_complete_rest),
.S(sel_m_axi_rready),
.COUT(word_complete_rest_ready)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_pop_inst
(
.CIN(word_complete_rest_ready),
.S(M_AXI_RVALID_I),
.COUT(word_complete_rest_pop)
);
// Combine the two branches to generate the full signal.
assign word_completed = word_complete_next_wrap | word_complete_rest;
end
endgenerate
// Only propagate Valid when there is command information available.
assign M_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_CTRL
// Pop word from MI-side.
assign M_AXI_RREADY_I = word_completed & S_AXI_RREADY_I;
// Get MI-side data.
assign pop_mi_data = M_AXI_RVALID_I & M_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & S_AXI_RLAST_I & pop_si_data;
end else begin : USE_FPGA_CTRL
wire sel_cmd_ready;
assign M_AXI_RREADY_I = word_complete_next_wrap_ready | word_complete_rest_ready;
assign pop_mi_data = word_complete_next_wrap_pop | word_complete_rest_pop;
assign sel_cmd_ready = cmd_valid & pop_si_data;
generic_baseblocks_v2_1_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) cmd_ready_inst
(
.CIN(S_AXI_RLAST_I),
.I(sel_cmd_ready),
.O(cmd_ready_i)
);
end
endgenerate
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = ( M_AXI_RVALID_I | use_wrap_buffer );
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Assign external signals.
assign M_AXI_RREADY = M_AXI_RREADY_I;
assign cmd_ready = cmd_ready_i;
// Detect when SI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Read transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offset points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be extracted, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first SI-side data beat.
//
// First MI is set while the entire first MI-side word is processed.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each used MI word it is decreased until
// Last beat is reached.
//
// Last word is determined depending on the current command, i.e. modified
// burst has to scale since multiple words could be packed into one MI-side
// word.
// Last word is 1:1 for:
// FIX, when burst support is disabled or unmodified for Normal Pack.
// Last word is scaled for all other transactions.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple SI words per MI word
assign sel_first_word = first_word | cmd_fix;
assign current_word = sel_first_word ? cmd_first_word :
current_word_1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD
// Calculate next word.
assign pre_next_word_i = ( next_word_i + cmd_step_i );
// Calculate next word.
assign next_word_i = sel_first_word ? cmd_next_word :
pre_next_word_1;
end else begin : USE_FPGA_NEXT_WORD
wire [C_M_AXI_BYTES_LOG-1:0] next_sel;
wire [C_M_AXI_BYTES_LOG:0] next_carry_local;
// Assign input to local vectors.
assign next_carry_local[0] = 1'b0;
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
LUT6_2 # (
.INIT(64'h5A5A_5A66_F0F0_F0CC)
) LUT6_2_inst (
.O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)
.I3(first_word), // LUT input (1-bit)
.I4(cmd_fix), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY next_carry_inst
(
.O (next_carry_local[bit_cnt+1]),
.CI (next_carry_local[bit_cnt]),
.DI (cmd_step_i[bit_cnt]),
.S (next_sel[bit_cnt])
);
XORCY next_xorcy_inst
(
.O(pre_next_word_i[bit_cnt]),
.CI(next_carry_local[bit_cnt]),
.LI(next_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Calculate next word.
assign next_word = next_word_i & cmd_mask;
assign pre_next_word = pre_next_word_i & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = current_word | cmd_offset;
// Prepare next word address.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
current_word_1 <= 'b0;
pre_next_word_1 <= {C_M_AXI_BYTES_LOG{1'b0}};
end else begin
if ( pop_si_data ) begin
if ( last_word ) begin
// Prepare for next access.
first_word <= 1'b1;
end else begin
first_word <= 1'b0;
end
current_word_1 <= next_word;
pre_next_word_1 <= pre_next_word;
end
end
end
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH
reg [8-1:0] length_counter_q;
reg first_mi_word_q;
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word_q <= 1'b1;
length_counter_q <= 8'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
first_mi_word_q <= 1'b1;
end else begin
first_mi_word_q <= 1'b0;
end
length_counter_q <= next_length_counter;
end
end
end
assign first_mi_word = first_mi_word_q;
assign length_counter_1 = length_counter_q;
end else begin : USE_FPGA_LENGTH
wire [8-1:0] length_counter_i;
wire [8-1:0] length_sel;
wire [8-1:0] length_di;
wire [8:0] length_local_carry;
// Assign input to local vectors.
assign length_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6_2 # (
.INIT(64'h333C_555A_FFF0_FFF0)
) LUT6_2_inst (
.O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(length_di[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(cmd_length[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_next_wrap_pop), // LUT input (1-bit)
.I3(word_complete_rest_pop), // LUT input (1-bit)
.I4(first_mi_word), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY and_inst
(
.O (length_local_carry[bit_cnt+1]),
.CI (length_local_carry[bit_cnt]),
.DI (length_di[bit_cnt]),
.S (length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(length_counter_i[bit_cnt]),
.CI(length_local_carry[bit_cnt]),
.LI(length_sel[bit_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(length_counter_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(length_counter_i[bit_cnt]) // Data input
);
end // end for bit_cnt
wire first_mi_word_i;
LUT6 # (
.INIT(64'hAAAC_AAAC_AAAC_AAAC)
) LUT6_cnt_inst (
.O(first_mi_word_i), // 6-LUT output (1-bit)
.I0(M_AXI_RLAST), // LUT input (1-bit)
.I1(first_mi_word), // LUT input (1-bit)
.I2(word_complete_next_wrap_pop), // LUT input (1-bit)
.I3(word_complete_rest_pop), // LUT input (1-bit)
.I4(1'b1), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(first_mi_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_mi_word_i) // Data input
);
end
endgenerate
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LAST_WORD
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be extracted from this MI-side word.
assign last_word = ( last_beat & ( current_word == cmd_last_word ) & ~wrap_buffer_available & ( current_word == cmd_last_word ) ) |
( use_wrap_buffer & ( current_word == cmd_last_word ) ) |
( last_beat & ( current_word == cmd_last_word ) & ( C_PACKING_LEVEL == C_NEVER_PACK ) );
end else begin : USE_FPGA_LAST_WORD
wire sel_last_word;
wire last_beat_ii;
comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE(8'b0),
.C_DATA_WIDTH(8)
) last_beat_inst
(
.CIN(1'b1),
.S(first_mi_word),
.A(length_counter_1),
.B(cmd_length),
.COUT(last_beat)
);
if ( C_PACKING_LEVEL != C_NEVER_PACK ) begin : USE_FPGA_PACK
//
//
wire sel_last_beat;
wire last_beat_i;
assign sel_last_beat = ~wrap_buffer_available;
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_beat_inst_1
(
.CIN(last_beat),
.S(sel_last_beat),
.COUT(last_beat_i)
);
carry_or #
(
.C_FAMILY(C_FAMILY)
) last_beat_wrap_inst
(
.CIN(last_beat_i),
.S(use_wrap_buffer),
.COUT(last_beat_ii)
);
end else begin : NO_PACK
assign last_beat_ii = last_beat;
end
comparator_sel #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) last_beat_curr_word_inst
(
.CIN(last_beat_ii),
.S(sel_first_word),
.A(current_word_1),
.B(cmd_first_word),
.V(cmd_last_word),
.COUT(last_word)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle wrap buffer:
//
// The wrap buffer is used to move data around in an unaligned WRAP
// transaction. The requested read address has been rounded down, meaning
// that parts of the first MI-side data beat has to be delayed for later use.
// The extraction starts at the origian unaligned address, the remaining data
// is stored in the wrap buffer to be extracted after the last MI-side data
// beat has been fully processed.
// For example: an 32bit to 64bit read upsizing @ 0x4 will request a MI-side
// read WRAP transaction 0x0. The 0x4 data word is used at once and the 0x0
// word is delayed to be used after all data in the last MI-side beat has
// arrived.
//
/////////////////////////////////////////////////////////////////////////////
// Save data to be able to perform buffer wraping.
assign store_in_wrap_buffer = M_AXI_RVALID_I & cmd_packed_wrap & first_mi_word & ~use_wrap_buffer;
// Mark that there are data available for wrap buffering.
always @ (posedge ACLK) begin
if (ARESET) begin
wrap_buffer_available <= 1'b0;
end else begin
if ( store_in_wrap_buffer & word_completed & pop_si_data ) begin
wrap_buffer_available <= 1'b1;
end else if ( last_beat & word_completed & pop_si_data ) begin
wrap_buffer_available <= 1'b0;
end
end
end
// Start using the wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
use_wrap_buffer <= 1'b0;
end else begin
if ( wrap_buffer_available & last_beat & word_completed & pop_si_data ) begin
use_wrap_buffer <= 1'b1;
end else if ( cmd_ready_i ) begin
use_wrap_buffer <= 1'b0;
end
end
end
// Store data in wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_RDATA_I <= {C_M_AXI_DATA_WIDTH{1'b0}};
rresp_wrap_buffer <= 2'b0;
end else begin
if ( store_in_wrap_buffer ) begin
M_AXI_RDATA_I <= M_AXI_RDATA;
rresp_wrap_buffer <= M_AXI_RRESP;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to read.
//
// Everything must be multiplexed since the next transfer can be arriving
// with a different set of signals while the wrap buffer is still being
// processed for the current transaction.
//
// Non modifiable word has a 1:1 ratio, i.e. only one SI-side word is
// generated per MI-side word.
// Data is taken either directly from the incomming MI-side data or the
// wrap buffer (for packed WRAP).
//
// Last need special handling since it is the last SI-side word generated
// from the MI-side word.
//
/////////////////////////////////////////////////////////////////////////////
// ID, RESP and USER has to be multiplexed.
assign S_AXI_RID_I = cmd_id;
assign S_AXI_RRESP_I = ( use_wrap_buffer ) ?
rresp_wrap_buffer :
M_AXI_RRESP;
// Data has to be multiplexed.
generate
if ( C_RATIO == 1 ) begin : SINGLE_WORD
assign S_AXI_RDATA_I = ( use_wrap_buffer ) ?
M_AXI_RDATA_I :
M_AXI_RDATA;
end else begin : MULTIPLE_WORD
// Get the ratio bits (MI-side words vs SI-side words).
wire [C_RATIO_LOG-1:0] current_index;
assign current_index = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG];
assign S_AXI_RDATA_I = ( use_wrap_buffer ) ?
M_AXI_RDATA_I[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] :
M_AXI_RDATA[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH];
end
endgenerate
// Generate the true last flag including "keep" while using wrap buffer.
assign M_AXI_RLAST_I = ( M_AXI_RLAST | use_wrap_buffer );
// Handle last flag, i.e. set for SI-side last word.
assign S_AXI_RLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_S_AXI_REGISTER ) begin : USE_REGISTER
reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID_q;
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_q;
reg [2-1:0] S_AXI_RRESP_q;
reg S_AXI_RLAST_q;
reg S_AXI_RVALID_q;
reg S_AXI_RREADY_q;
// Register SI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RID_q <= {C_AXI_ID_WIDTH{1'b0}};
S_AXI_RDATA_q <= {C_S_AXI_DATA_WIDTH{1'b0}};
S_AXI_RRESP_q <= 2'b0;
S_AXI_RLAST_q <= 1'b0;
S_AXI_RVALID_q <= 1'b0;
end else begin
if ( S_AXI_RREADY_I ) begin
S_AXI_RID_q <= S_AXI_RID_I;
S_AXI_RDATA_q <= S_AXI_RDATA_I;
S_AXI_RRESP_q <= S_AXI_RRESP_I;
S_AXI_RLAST_q <= S_AXI_RLAST_I;
S_AXI_RVALID_q <= S_AXI_RVALID_I;
end
end
end
assign S_AXI_RID = S_AXI_RID_q;
assign S_AXI_RDATA = S_AXI_RDATA_q;
assign S_AXI_RRESP = S_AXI_RRESP_q;
assign S_AXI_RLAST = S_AXI_RLAST_q;
assign S_AXI_RVALID = S_AXI_RVALID_q;
assign S_AXI_RREADY_I = ( S_AXI_RVALID_q & S_AXI_RREADY) | ~S_AXI_RVALID_q;
end else begin : NO_REGISTER
// Combinatorial SI-side Data.
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A41OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A41OI_FUNCTIONAL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a41oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
// Local signals
wire A4 and0_out ;
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A41OI_FUNCTIONAL_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 12.2
// \ \ Application : xaw2verilog
// / / Filename : DCM_FRL.v
// /___/ /\ Timestamp : 10/19/2012 11:30:08
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st D:\\Mydev\firmwareTFS\FPGA\MIMOv1\rtl\pcie_userapp_wrapper\Sora_Fast_Radio_Link\DCM\.\DCM_FRL.xaw D:\\Mydev\firmwareTFS\FPGA\MIMOv1\rtl\pcie_userapp_wrapper\Sora_Fast_Radio_Link\DCM\.\DCM_FRL
//Design Name: DCM_FRL
//Device: xc5vlx50t-1ff1136
//
// Module DCM_FRL
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module DCM_FRL(CLKIN_IN,
RST_IN,
CLKDV_OUT,
CLK0_OUT,
LOCKED_OUT);
input CLKIN_IN;
input RST_IN;
output CLKDV_OUT;
output CLK0_OUT;
output LOCKED_OUT;
wire CLKDV_BUF;
wire CLKFB_IN;
wire CLK0_BUF;
wire GND_BIT;
wire [6:0] GND_BUS_7;
wire [15:0] GND_BUS_16;
assign GND_BIT = 0;
assign GND_BUS_7 = 7'b0000000;
assign GND_BUS_16 = 16'b0000000000000000;
assign CLK0_OUT = CLKFB_IN;
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(4.0), .CLKFX_DIVIDE(1),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(4.464),
.CLKOUT_PHASE_SHIFT("NONE"), .DCM_AUTOCALIBRATION("TRUE"),
.DCM_PERFORMANCE_MODE("MAX_SPEED"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"),
.DLL_FREQUENCY_MODE("HIGH"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IN),
.DADDR(GND_BUS_7[6:0]),
.DCLK(GND_BIT),
.DEN(GND_BIT),
.DI(GND_BUS_16[15:0]),
.DWE(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(RST_IN),
.CLKDV(CLKDV_BUF),
.CLKFX(),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.DO(),
.DRDY(),
.LOCKED(LOCKED_OUT),
.PSDONE());
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 45,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 161,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "45"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.866669"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "161"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.90908000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "45"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "161"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:29:55 08/15/2011
// Design Name:
// Module Name: RCB_FRL_RXMSG_ACK_Decoder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_RXMSG_ACK_Decoder(
input clk,
input enable, //Active low reset
input [7:0] data_in,
output reg CON_P,
output reg CON_N
);
// parameter lock_pattern = 8'hff ; //Specifies the lock pattern
// parameter pack_size = 100; // Current packet size
// parameter word_size = 8; // Not currently used in code
reg [7:0] data_reg1; //First register used to re-align the data
reg [7:0] data_reg2; //Second register used to re-align the data
reg [7:0] data_reg3; //Third register used to re-align the data
reg [2:0] shift; //designate the bit shift value of the package
reg lock; //if high, then the correct shift value has been found.
reg [7:0] byte_count; //word count in packet
reg [2:0] front_count;
reg [7:0] data_out_tmp; //pipeline register
reg data_valid;
reg [7:0] frame_length;
reg [7:0] data_out; // output register
reg data_correct;
reg data_wrong;
reg [39:0] data_all;
// wire end_pack = pack_size; // signifies end of packet
always @(negedge clk) // timing broken to set data_valid flag
begin
if (!enable)
begin
data_out_tmp <= 8'h00; //test
end
else
begin
case(shift) //Re-aligns the data depending on shift value
3'h0 : data_out_tmp <= data_reg3;
3'h1 : data_out_tmp <= ({data_reg3[6:0],data_reg2[7]});
3'h2 : data_out_tmp <= ({data_reg3[5:0],data_reg2[7:6]});
3'h3 : data_out_tmp <= ({data_reg3[4:0],data_reg2[7:5]});
3'h4 : data_out_tmp <= ({data_reg3[3:0],data_reg2[7:4]});
3'h5 : data_out_tmp <= ({data_reg3[2:0],data_reg2[7:3]});
3'h6 : data_out_tmp <= ({data_reg3[1:0],data_reg2[7:2]});
3'h7 : data_out_tmp <= ({data_reg3[0],data_reg2[7:1]});
default : data_out_tmp <= data_reg3;
endcase
end
end
// Data shift registers
always @(negedge clk) //
begin
if(!enable)
begin
data_reg1 <= 8'h00; //Initializes the registers
data_reg2 <= 8'h00;
data_reg3 <= 8'h00;
end
else
begin
data_reg1 <= data_in; // Registers incoming data, shifts to compare registers
data_reg2 <= data_reg1; // reg2 and reg3 are compare registers
data_reg3 <= data_reg2;
end
end
// Search and validate
always @(negedge clk) //
begin
if(!enable)
begin
lock <= 0;
shift <= 0;
data_out <= 8'h00;
data_valid <= 0;
frame_length <= 0;
end
else
begin
if(data_reg3 === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[6:0],data_reg2[7]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[5:0],data_reg2[7:6]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[4:0],data_reg2[7:5]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[3:0],data_reg2[7:4]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[2:0],data_reg2[7:3]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[1:0],data_reg2[7:2]} === 8'h5f)
begin
CON_P <= 1'b1;
end
else if({data_reg3[0],data_reg2[7:1]} === 8'h5f) //lock_pattern
begin
CON_P <= 1'b1;
end
else begin
CON_P <= 1'b0;
end
if(data_reg3 === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[6:0],data_reg2[7]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[5:0],data_reg2[7:6]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[4:0],data_reg2[7:5]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[3:0],data_reg2[7:4]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[2:0],data_reg2[7:3]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[1:0],data_reg2[7:2]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[0],data_reg2[7:1]} === 8'haf )//lock_pattern
begin
CON_N <= 1'b1;
end
else begin
CON_N <= 1'b0;
end
end //if (!lock) // end search
end
endmodule
|
/*
*
* Copyright (c) 2011-2012 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// Configuration Options
//
// Frequency (MHz) of the incoming clock (CLK_100MHZ)
localparam INPUT_CLOCK_FREQUENCY = 100;
// What frequency of operation Synthesis and P&R should target. If
// ISE can meet timing requirements, then this is the guaranteed
// frequency of operation.
localparam SYNTHESIS_FREQUENCY = 200;
// What frequency the FPGA should boot-up to.
localparam BOOTUP_FREQUENCY = 50;
// What is the maximum allowed overclock. User will not be able to set
// clock frequency above this threshold.
localparam MAXIMUM_FREQUENCY = 200;
// ONLY FOR DEV TESTING:
//`define DUMMY_ADDER
//`define DUMMY_HASHER
//// Clock Buffer
wire clkin_100MHZ;
IBUFG clkin1_buf ( .I (CLK_100MHZ), .O (clkin_100MHZ));
////
reg [255:0] midstate = 0;
reg [95:0] data = 0;
reg [31:0] nonce = 32'd253, nonce2 = 32'd0;
//// PLL
wire hash_clk;
wire dcm_progdata, dcm_progen, dcm_progdone;
`ifndef SIM
dynamic_clock # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.SYNTHESIS_FREQUENCY (SYNTHESIS_FREQUENCY)
) dynamic_clk_blk (
.CLK_IN1 (clkin_100MHZ),
.CLK_OUT1 (hash_clk),
.PROGCLK (clkin_100MHZ),
.PROGDATA (dcm_progdata),
.PROGEN (dcm_progen),
.PROGDONE (dcm_progdone)
);
`else
assign hash_clk = CLK_100MHZ;
`endif
//// ZTEX Hashers
`ifdef DUMMY_HASHER
wire [31:0] hash2_w;
dummy_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash2_w)
);
`else
`ifdef DUMMY_ADDR
reg [31:0] hash2_w;
reg [31:0] stage1, stage2, stage3, stage4, stage5;
always @ (posedge hash_clk)
begin
stage1 <= nonce + data[95:64] + data[63:32];
stage2 <= stage1 + data[31:0] + midstate[255:224];
stage3 <= stage2 + midstate[223:192] + midstate[191:160];
stage4 <= stage3 + midstate[159:128] + midstate[127:96];
stage5 <= stage4 + midstate[95:64] + midstate[63:32];
hash2_w <= stage5 + midstate[31:0];
end
`else
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash)
);
sha256_pipe123 p2 (
.clk (hash_clk),
.data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash (hash2_w)
);
`endif
`endif
//// Communication Module
wire comm_new_work;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg is_golden_ticket = 1'b0;
reg [31:0] golden_nonce;
reg [3:0] golden_ticket_buf = 4'b0;
reg [127:0] golden_nonce_buf;
`ifndef SIM
jtag_comm # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.MAXIMUM_FREQUENCY (MAXIMUM_FREQUENCY),
.INITIAL_FREQUENCY (BOOTUP_FREQUENCY)
) comm_blk (
.rx_hash_clk (hash_clk),
.rx_new_nonce (golden_ticket_buf[3]),
.rx_golden_nonce (golden_nonce_buf[127:96]),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_data (comm_data),
.rx_dcm_progclk (clkin_100MHZ),
.tx_dcm_progdata (dcm_progdata),
.tx_dcm_progen (dcm_progen),
.rx_dcm_progdone (dcm_progdone)
);
`endif
//// Control Unit
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~253 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 32'd253;
nonce2 <= 32'd0;
end
else
begin
nonce <= nonce + 32'd1;
nonce2 <= nonce2 + 32'd1;
end
// Give new data to the hasher
midstate <= comm_midstate;
data <= comm_data[95:0];
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
is_golden_ticket <= hash2_w == 32'hA41F32E7;
golden_nonce <= nonce2;
golden_ticket_buf <= {golden_ticket_buf[2:0], is_golden_ticket};
golden_nonce_buf <= {golden_nonce_buf[95:0], golden_nonce};
end
endmodule
|
// ============================================================================
// Copyright (c) 2010 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
// Major Functions/Design Description:
//
// Please refer to DE4_UserManual.pdf in DE4 system CD.
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |EricChen |10/06/30 |
// ============================================================================
`define NET0
`define NET1
`define NET2
`define NET3
module DE4_Ethernet(
//////// CLOCK //////////
GCLKIN,
GCLKOUT_FPGA,
OSC_50_BANK2,
OSC_50_BANK3,
OSC_50_BANK4,
OSC_50_BANK5,
OSC_50_BANK6,
OSC_50_BANK7,
PLL_CLKIN_p,
//////// External PLL //////////
MAX_I2C_SCLK,
MAX_I2C_SDAT,
//////// LED x 8 //////////
LED,
//////// BUTTON x 4, EXT_IO and CPU_RESET_n //////////
BUTTON,
CPU_RESET_n,
EXT_IO,
//////// DIP SWITCH x 8 //////////
SW,
//////// SLIDE SWITCH x 4 //////////
SLIDE_SW,
//////// SEG7 //////////
SEG0_D,
SEG0_DP,
SEG1_D,
SEG1_DP,
//////// Temperature //////////
TEMP_INT_n,
TEMP_SMCLK,
TEMP_SMDAT,
//////// Current //////////
CSENSE_ADC_FO,
CSENSE_CS_n,
CSENSE_SCK,
CSENSE_SDI,
CSENSE_SDO,
//////// Fan //////////
FAN_CTRL,
//////// EEPROM //////////
EEP_SCL,
EEP_SDA,
//////// SDCARD //////////
SD_CLK,
SD_CMD,
SD_DAT,
SD_WP_n,
//////// RS232 //////////
UART_CTS,
UART_RTS,
UART_RXD,
UART_TXD,
//////// Ethernet x 4 //////////
ETH_INT_n,
ETH_MDC,
ETH_MDIO,
ETH_RST_n,
ETH_RX_p,
ETH_TX_p,
//////// Flash and SRAM Address/Data Share Bus //////////
FSM_A,
FSM_D,
//////// Flash Control //////////
FLASH_ADV_n,
FLASH_CE_n,
FLASH_CLK,
FLASH_OE_n,
FLASH_RESET_n,
FLASH_RYBY_n,
FLASH_WE_n,
//////// SSRAM Control //////////
SSRAM_ADV,
SSRAM_BWA_n,
SSRAM_BWB_n,
SSRAM_CE_n,
SSRAM_CKE_n,
SSRAM_CLK,
SSRAM_OE_n,
SSRAM_WE_n,
///////// DRAM interfaces ///////
//////// DDR2 SODIMM //////////
M1_DDR2_addr,
M1_DDR2_ba,
M1_DDR2_cas_n,
M1_DDR2_cke,
M1_DDR2_clk,
M1_DDR2_clk_n,
M1_DDR2_cs_n,
M1_DDR2_dm,
M1_DDR2_dq,
M1_DDR2_dqs,
M1_DDR2_dqsn,
M1_DDR2_odt,
M1_DDR2_ras_n,
M1_DDR2_SA,
M1_DDR2_SCL,
M1_DDR2_SDA,
M1_DDR2_we_n,
M1_DDR2_RDN,
M1_DDR2_RUP
);
//=======================================================
// PARAMETER declarations
//=======================================================
//=======================================================
// PORT declarations
//=======================================================
//////////// CLOCK //////////
input GCLKIN;
output GCLKOUT_FPGA;
input OSC_50_BANK2;
input OSC_50_BANK3;
input OSC_50_BANK4;
input OSC_50_BANK5;
input OSC_50_BANK6;
input OSC_50_BANK7;
input PLL_CLKIN_p;
//////////// External PLL //////////
output MAX_I2C_SCLK;
inout MAX_I2C_SDAT;
//////////// LED x 8 //////////
output [7:0] LED;
//////////// BUTTON x 4, EXT_IO and CPU_RESET_n //////////
input [3:0] BUTTON;
input CPU_RESET_n;
inout EXT_IO;
//////////// DIP SWITCH x 8 //////////
input [7:0] SW;
//////////// SLIDE SWITCH x 4 //////////
input [3:0] SLIDE_SW;
//////////// SEG7 //////////
output [6:0] SEG0_D;
output SEG0_DP;
output [6:0] SEG1_D;
output SEG1_DP;
//////////// Temperature //////////
input TEMP_INT_n;
output TEMP_SMCLK;
inout TEMP_SMDAT;
//////////// Current //////////
output CSENSE_ADC_FO;
output [1:0] CSENSE_CS_n;
output CSENSE_SCK;
output CSENSE_SDI;
input CSENSE_SDO;
//////////// Fan //////////
output FAN_CTRL;
//////////// EEPROM //////////
output EEP_SCL;
inout EEP_SDA;
//////////// SDCARD //////////
output SD_CLK;
inout SD_CMD;
inout [3:0] SD_DAT;
input SD_WP_n;
//////////// RS232 //////////
output UART_CTS;
input UART_RTS;
input UART_RXD;
output UART_TXD;
//////////// Ethernet x 4 //////////
input [3:0] ETH_INT_n;
output [3:0] ETH_MDC;
inout [3:0] ETH_MDIO;
output ETH_RST_n;
input [3:0] ETH_RX_p;
output [3:0] ETH_TX_p;
//////////// Flash and SRAM Address/Data Share Bus //////////
output [25:0] FSM_A;
inout [15:0] FSM_D;
//////////// Flash Control //////////
output FLASH_ADV_n;
output FLASH_CE_n;
output FLASH_CLK;
output FLASH_OE_n;
output FLASH_RESET_n;
input FLASH_RYBY_n;
output FLASH_WE_n;
//////////// SSRAM Control //////////
output SSRAM_ADV;
output SSRAM_BWA_n;
output SSRAM_BWB_n;
output SSRAM_CE_n;
output SSRAM_CKE_n;
output SSRAM_CLK;
output SSRAM_OE_n;
output SSRAM_WE_n;
/////////// DDR2 signals /////////////
//////////// DDR2 SODIMM //////////
output [13:0] M1_DDR2_addr;
output [2:0] M1_DDR2_ba;
output M1_DDR2_cas_n;
output [1:0] M1_DDR2_cke;
output [1:0] M1_DDR2_clk;
output [1:0] M1_DDR2_clk_n;
output [1:0] M1_DDR2_cs_n;
output [7:0] M1_DDR2_dm;
inout [63:0] M1_DDR2_dq;
inout [7:0] M1_DDR2_dqs;
inout [7:0] M1_DDR2_dqsn;
output [1:0] M1_DDR2_odt;
output M1_DDR2_ras_n;
output [1:0] M1_DDR2_SA;
output M1_DDR2_SCL;
inout M1_DDR2_SDA;
output M1_DDR2_we_n;
input M1_DDR2_RDN;
input M1_DDR2_RUP;
//=======================================================
// REG/WIRE declarations
//=======================================================
wire global_reset_n;
wire enet_reset_n;
//// Ethernet
wire enet_mdc0;
wire enet_mdio_in0;
wire enet_mdio_oen0;
wire enet_mdio_out0;
wire enet_refclk_125MHz;
wire lvds_rxp0;
wire lvds_txp0;
wire enet_mdc1;
wire enet_mdio_in1;
wire enet_mdio_oen1;
wire enet_mdio_out1;
wire lvds_rxp1;
wire lvds_txp1;
wire enet_mdc2;
wire enet_mdio_in2;
wire enet_mdio_oen2;
wire enet_mdio_out2;
wire lvds_rxp2;
wire lvds_txp2;
wire enet_mdc3;
wire enet_mdio_in3;
wire enet_mdio_oen3;
wire enet_mdio_out3;
wire lvds_rxp3;
wire lvds_txp3;
//=======================================================
// External PLL Configuration ==========================
//=======================================================
// Signal declarations
wire [ 3: 0] clk1_set_wr, clk2_set_wr, clk3_set_wr;
wire rstn;
wire conf_ready;
wire counter_max;
wire [7:0] counter_inc;
reg [7:0] auto_set_counter;
reg conf_wr;
//interrupt wires
wire interrupt_in_export;
/////////////////////////////////////////////
//Interface from DRAM read interface to compute system (control)
wire control_fixed_location;
wire [30:0] read_length;
wire control_go;
wire control_done;
wire [30:0] read_base;
//Interface from DRAM read interface to compute system (user)
wire user_read_buffer;
wire [255:0] user_buffer_output_data;
wire user_data_available;
//////////////////////////////////////////////
// Structural coding
assign clk1_set_wr = 4'd4; //100 MHZ
assign clk2_set_wr = 4'd4; //100 MHZ
assign clk3_set_wr = 4'd4; //100 MHZ
assign rstn = CPU_RESET_n;
assign counter_max = &auto_set_counter;
assign counter_inc = auto_set_counter + 1'b1;
always @(posedge OSC_50_BANK2 or negedge rstn)
if(!rstn)
begin
auto_set_counter <= 0;
conf_wr <= 0;
end
else if (counter_max)
conf_wr <= 1;
else
auto_set_counter <= counter_inc;
ext_pll_ctrl ext_pll_ctrl_Inst(
.osc_50(OSC_50_BANK2), //50MHZ
.rstn(rstn),
// device 1 (HSMA_REFCLK)
.clk1_set_wr(clk1_set_wr),
.clk1_set_rd(),
// device 2 (HSMB_REFCLK)
.clk2_set_wr(clk2_set_wr),
.clk2_set_rd(),
// device 3 (PLL_CLKIN/SATA_REFCLK)
.clk3_set_wr(clk3_set_wr),
.clk3_set_rd(),
// setting trigger
.conf_wr(conf_wr), // 1T 50MHz
.conf_rd(), // 1T 50MHz
// status
.conf_ready(conf_ready),
// 2-wire interface
.max_sclk(MAX_I2C_SCLK),
.max_sdat(MAX_I2C_SDAT)
);
//=======================================================
// Structural coding
//=======================================================
//// Ethernet
assign ETH_RST_n = enet_reset_n;
`ifdef NET0
//input [0:0] ETH_RX_p;
//output [0:0] ETH_TX_p;
assign lvds_rxp0 = ETH_RX_p[0];
assign ETH_TX_p[0] = lvds_txp0;
assign enet_mdio_in0 = ETH_MDIO[0];
assign ETH_MDIO[0] = !enet_mdio_oen0 ? enet_mdio_out0 : 1'bz;
assign ETH_MDC[0] = enet_mdc0;
`endif
//`elsif NET1
`ifdef NET1
//input [1:1] ETH_RX_p;
//output [1:1] ETH_TX_p;
assign lvds_rxp1 = ETH_RX_p[1];
assign ETH_TX_p[1] = lvds_txp1;
assign enet_mdio_in1 = ETH_MDIO[1];
assign ETH_MDIO[1] = !enet_mdio_oen1 ? enet_mdio_out1 : 1'bz;
assign ETH_MDC[1] = enet_mdc1;
`endif
//`elsif NET2
`ifdef NET2
//input [2:2] ETH_RX_p;
//output [2:2] ETH_TX_p;
assign lvds_rxp2 = ETH_RX_p[2];
assign ETH_TX_p[2] = lvds_txp2;
assign enet_mdio_in2 = ETH_MDIO[2];
assign ETH_MDIO[2] = !enet_mdio_oen2 ? enet_mdio_out2 : 1'bz;
assign ETH_MDC[2] = enet_mdc2;
`endif
//`elsif NET3
`ifdef NET3
//input [3:3] ETH_RX_p;
//output [3:3] ETH_TX_p;
assign lvds_rxp3 = ETH_RX_p[3];
assign ETH_TX_p[3] = lvds_txp3;
assign enet_mdio_in3 = ETH_MDIO[3];
assign ETH_MDIO[3] = !enet_mdio_oen3 ? enet_mdio_out3 : 1'bz;
assign ETH_MDC[3] = enet_mdc3;
`endif
//// FLASH and SSRAM share bus
assign FLASH_ADV_n = 1'b0; // not used
assign FLASH_CLK = 1'b0; // not used
assign FLASH_RESET_n = global_reset_n;
//// SSRAM
//// Fan Control
assign FAN_CTRL = 1'bz; // don't control
// === Ethernet clock PLL
pll_125 pll_125_ins (
.inclk0(OSC_50_BANK3),
.c0(enet_refclk_125MHz)
);
gen_reset_n system_gen_reset_n (
.tx_clk(OSC_50_BANK3),
.reset_n_in(CPU_RESET_n),
.reset_n_out(global_reset_n)
);
gen_reset_n net_gen_reset_n(
.tx_clk(OSC_50_BANK3),
.reset_n_in(global_reset_n),
.reset_n_out(enet_reset_n)
);
DE4_SOPC SOPC_INST (
// 1) global signals:
//.ext_clk(OSC_50_BANK6), //Deepak comment
//.ext_clk_clk_in_clk(OSC_50_BANK6),
.ext_clk(OSC_50_BANK6),
.pll_peripheral_clk(),
.pll_sys_clk(),
.ext_clk_clk_in_reset_reset_n(global_reset_n),
//.reset_n(global_reset_n),
// the_flash_tristate_bridge_avalon_slave
/*
.flash_tristate_bridge_address(FSM_A[24:0]),
.flash_tristate_bridge_data(FSM_D),
.flash_tristate_bridge_readn(FLASH_OE_n),
.flash_tristate_bridge_writen(FLASH_WE_n),
.select_n_to_the_ext_flash(FLASH_CE_n),
*/
// the_tse_mac
.led_an_from_the_tse_mac(led_an_from_the_tse_mac),
.led_char_err_from_the_tse_mac(led_char_err_from_the_tse_mac),
.led_col_from_the_tse_mac(led_col_from_the_tse_mac),
.led_crs_from_the_tse_mac(led_crs_from_the_tse_mac),
.led_disp_err_from_the_tse_mac(led_disp_err_from_the_tse_mac),
.led_link_from_the_tse_mac(led_link_from_the_tse_mac),
.mdc_from_the_tse_mac(enet_mdc0),
.mdio_in_to_the_tse_mac(enet_mdio_in0),
.mdio_oen_from_the_tse_mac(enet_mdio_oen0),
.mdio_out_from_the_tse_mac(enet_mdio_out0),
.ref_clk_to_the_tse_mac(enet_refclk_125MHz),
.rxp_to_the_tse_mac(lvds_rxp0),
.txp_from_the_tse_mac(lvds_txp0),
// the_tse_mac1
.led_an_from_the_tse_mac1(),
.led_char_err_from_the_tse_mac1(),
.led_col_from_the_tse_mac1(),
.led_crs_from_the_tse_mac1(),
.led_disp_err_from_the_tse_mac1(),
.led_link_from_the_tse_mac1(),
.mdc_from_the_tse_mac1(enet_mdc1),
.mdio_in_to_the_tse_mac1(enet_mdio_in1),
.mdio_oen_from_the_tse_mac1(enet_mdio_oen1),
.mdio_out_from_the_tse_mac1(enet_mdio_out1),
.ref_clk_to_the_tse_mac1(enet_refclk_125MHz),
.rxp_to_the_tse_mac1(lvds_rxp1),
.txp_from_the_tse_mac1(lvds_txp1),
/*
// the_tse_mac2
.led_an_from_the_tse_mac2(),
.led_char_err_from_the_tse_mac2(),
.led_col_from_the_tse_mac2(),
.led_crs_from_the_tse_mac2(),
.led_disp_err_from_the_tse_mac2(),
.led_link_from_the_tse_mac2(),
.mdc_from_the_tse_mac2(enet_mdc2),
.mdio_in_to_the_tse_mac2(enet_mdio_in2),
.mdio_oen_from_the_tse_mac2(enet_mdio_oen2),
.mdio_out_from_the_tse_mac2(enet_mdio_out2),
.ref_clk_to_the_tse_mac2(enet_refclk_125MHz),
.rxp_to_the_tse_mac2(lvds_rxp2),
.txp_from_the_tse_mac2(lvds_txp2),
// the_tse_mac3
.led_an_from_the_tse_mac3(),
.led_char_err_from_the_tse_mac3(),
.led_col_from_the_tse_mac3(),
.led_crs_from_the_tse_mac3(),
.led_disp_err_from_the_tse_mac3(),
.led_link_from_the_tse_mac3(),
.mdc_from_the_tse_mac3(enet_mdc3),
.mdio_in_to_the_tse_mac3(enet_mdio_in3),
.mdio_oen_from_the_tse_mac3(enet_mdio_oen3),
.mdio_out_from_the_tse_mac3(enet_mdio_out3),
.ref_clk_to_the_tse_mac3(enet_refclk_125MHz),
.rxp_to_the_tse_mac3(lvds_rxp3),
.txp_from_the_tse_mac3(lvds_txp3),
*/
//.interrupt_in_export(interrupt_in_export),
//.dma_transfer_done_out_export(interrupt_in_export),
/*
// the_pb_pio
.in_port_to_the_pb_pio(BUTTON),
// the_sw_pio
.in_port_to_the_sw_pio(SW),
// the_seven_seg_pio
.out_port_from_the_seven_seg_pio({SEG1_DP,SEG1_D[6:0],SEG0_DP,SEG0_D[6:0]}),
// the_led_pio
.out_port_from_the_led_pio({dummy_LED,LED[6:0]})
*/
.memory_mem_a(M1_DDR2_addr),
.memory_mem_ba(M1_DDR2_ba),
.memory_mem_cas_n(M1_DDR2_cas_n),
.memory_mem_cke(M1_DDR2_cke),
.memory_mem_ck_n(M1_DDR2_clk_n),
.memory_mem_ck(M1_DDR2_clk),
.memory_mem_cs_n(M1_DDR2_cs_n),
.memory_mem_dm(M1_DDR2_dm),
.memory_mem_dq(M1_DDR2_dq),
.memory_mem_dqs(M1_DDR2_dqs),
.memory_mem_dqs_n(M1_DDR2_dqsn),
.memory_mem_odt(M1_DDR2_odt),
.memory_mem_ras_n(M1_DDR2_ras_n),
.memory_mem_we_n(M1_DDR2_we_n),
.oct_rdn(M1_DDR2_RDN),
.oct_rup(M1_DDR2_RUP),
.mem_if_ddr2_emif_0_global_reset_reset_n(1'b1), //Deepak tying dram reset to 1
.mem_if_ddr2_emif_0_soft_reset_reset_n(1'b1), //tying dram pll rset to 1
);
///////////////////////////////////////////////////////////////////////////////
assign LED[7] = count[21];
reg [31:0] count;
always @ (negedge global_reset_n or posedge OSC_50_BANK3)
begin
if (!global_reset_n) begin
count <= 0;
end
else begin
count <= count + 1;
end
end
///////////////////////////////////////////////////////////////////////////////
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NOR2_PP_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor2 (
Y ,
A ,
B ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2_PP_BLACKBOX_V
|