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//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 13
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 13;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 13;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 33333;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
module vga( input pxl_clk,
input reset_n,
output reg [9:0] hcount,
output reg [9:0] vcount,
output reg vsync,
output reg hsync );
always @ (posedge pxl_clk or negedge reset_n)
begin : hcounter
if (!reset_n) hcount <= 0;
else if (hcount <= 799) hcount <= hcount + 1'b1;
else hcount <= 0;
end
always @ (posedge pxl_clk or negedge reset_n)
begin : vcounter
if (!reset_n) vcount <= 0;
else if (hcount == 799 && vcount <= 521) vcount <= vcount + 1'b1;
else if (vcount <= 521) vcount <= vcount;
else vcount <= 0;
end
/********************************
640 pixels video
16 pixels front porch
96 pixels horizontal sync
48 pixels back porch
*********************************/
always @ (hcount)
begin : hsync_decoder
if (hcount >= 656 && hcount <= 752) hsync <= 0;
else hsync <= 1;
end
/********************************
480 lines video
2 lines front porch
10 lines vertical sync
29 lines back porch
*********************************/
always @ (vcount)
begin : vsync_decoder
if (vcount >= 482 && vcount <= 492) vsync <= 0;
else vsync <= 1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test for short-circuiting in generate "if"
//
// The given generate loops should only access valid bits of mask, since that
// is defined by SIZE. However since the loop range is larger, this only works
// if short-circuited evaluation of the generate loop is in place.
// This file ONLY is placed into the Public Domain, for any use, without
// warranty, 2012 by Jeremy Bennett.
`define MAX_SIZE 4
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Set the parameters, so that we use a size less than MAX_SIZE
test_gen
#(.SIZE (2),
.MASK (2'b11))
i_test_gen (.clk (clk));
// This is only a compilation test, but for good measure we do one clock
// cycle.
integer count;
initial begin
count = 0;
end
always @(posedge clk) begin
if (count == 1) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
count = count + 1;
end
end
endmodule // t
module test_gen
#( parameter
SIZE = `MAX_SIZE,
MASK = `MAX_SIZE'b0)
(/*AUTOARG*/
// Inputs
clk
);
input clk;
// Generate blocks that rely on short-circuiting of the logic to avoid errors.
generate
genvar g;
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ((g < SIZE) && MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical AND generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g >= SIZE) || ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical OR generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if (!((g < SIZE) -> ~MASK[g])) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Logical infer generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ( g < SIZE ? MASK[g] : 1'b0) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
// The other way round
generate
for (g = 0; g < `MAX_SIZE; g = g + 1) begin
if ( g >= SIZE ? 1'b0 : MASK[g]) begin
always @(posedge clk) begin
`ifdef TEST_VERBOSE
$write ("Conditional generate if MASK [%1d] = %d\n", g, MASK[g]);
`endif
if (g >= SIZE) begin
$stop;
end
end
end
end
endgenerate
endmodule
|
module spi_tb ();
// UUT Parameters
parameter LOG2_DEPTH = 4;
// UUT Signals
wire nCs;
wire mosi;
wire miso;
wire sck;
wire [7:0] doutMaster;
wire [7:0] doutSlave;
wire txDataPresentM;
wire txHalfFullM;
wire txFullM;
wire rxDataPresentM;
wire rxHalfFullM;
wire rxFullM;
wire txDataPresentS;
wire txHalfFullS;
wire txFullS;
wire rxDataPresentS;
wire rxHalfFullS;
wire rxFullS;
reg clk;
reg rst;
reg spiStrobe;
reg readMaster;
reg readSlave;
reg writeMaster;
reg writeSlave;
reg cpol;
reg cpha;
reg [7:0] dinMaster;
reg [7:0] dinSlave;
// Test Signals
reg [7:0] dataM;
reg [7:0] dataS;
reg [7:0] prevDataM;
reg [7:0] prevDataS;
integer i,j;
///////////////////////////////////////////////////////////////////////////
// System Setup
///////////////////////////////////////////////////////////////////////////
initial begin
clk = 1'b0;
rst = 1'b1;
spiStrobe = 1'b0;
cpol = 1'b0;
cpha = 1'b0;
end
// Clocks & Strobes
always #1 clk = ~clk;
always begin
@(posedge clk) spiStrobe <= 1'b1;
@(posedge clk) spiStrobe <= 1'b0;
@(posedge clk) spiStrobe <= 1'b0;
@(posedge clk) spiStrobe <= 1'b0;
@(posedge clk) spiStrobe <= 1'b0;
@(posedge clk) spiStrobe <= 1'b0;
@(posedge clk) spiStrobe <= 1'b0;
@(posedge clk) spiStrobe <= 1'b0;
end
initial begin
wait((j < 0) && (i == 256));
$stop();
end
///////////////////////////////////////////////////////////////////////////
// Master Control
///////////////////////////////////////////////////////////////////////////
initial begin
dataM = 0;
prevDataM = 0;
dinMaster = 'd0;
writeMaster = 1'b0;
readMaster = 1'b0;
#7 rst = 1'b0;
for (i=0; i<256; i=i+1) begin
wait(~txFullM);
wait(nCs);
dinMaster = i;
@(posedge clk) writeMaster = 1'b1;
@(posedge clk) writeMaster = 1'b0;
@(posedge clk) writeMaster = 1'b0;
end
end
always begin
prevDataM = dataM;
wait(rxDataPresentM);
dataM = doutMaster;
prevDataM = prevDataM - 8'd1;
if (prevDataM != dataM) begin
$display("Master data was $x instead of %x", dataM, prevDataM);
$stop();
end
@(posedge clk) readMaster = 1'b1;
@(posedge clk) readMaster = 1'b0;
wait(~rxDataPresentM);
end
///////////////////////////////////////////////////////////////////////////
// Slave Control
///////////////////////////////////////////////////////////////////////////
initial begin
prevDataS = 0;
dataS = 0;
dinSlave = 255;
writeSlave = 1'b0;
readSlave = 1'b0;
wait(~rst);
wait(~nCs);
for (j=254; j>=0; j=j-1) begin
wait(~txFullS);
@(posedge clk) dinSlave = j;
@(posedge clk) writeSlave = 1'b1;
@(posedge clk) writeSlave = 1'b0;
@(posedge clk) writeSlave = 1'b0;
end
end
always begin
prevDataS = dataS;
wait(rxDataPresentS);
dataS = doutSlave;
prevDataS = prevDataS + 8'd1;
if (prevDataS != dataS) begin
$display("Slave data was $x instead of %x", dataS, prevDataS);
$stop();
end
@(posedge clk) readSlave = 1'b1;
@(posedge clk) readSlave = 1'b0;
wait(~rxDataPresentS);
end
///////////////////////////////////////////////////////////////////////////
// UUT Instantiation
///////////////////////////////////////////////////////////////////////////
XcvrSpiMaster #(
.LOG2_DEPTH(LOG2_DEPTH)
)
uut (
// INPUTS
.clk(clk), ///< System Clock
.rst(rst), ///< Reset, synchronous and active high
.spiStrobe(spiStrobe), ///< Strobe at SPI data rate
// Data Interface Inputs
.dataIn(dinMaster), ///< [7:0] Data to send
.write(writeMaster), ///< Strobe to write to TX FIFO
.read(readMaster), ///< Strove to read from RX FIFO
.cpol(cpol), ///< SPI data polarity
.cpha(cpha), ///< SPI clock phase
// SPI Signals
.miso(miso), ///< Master in, slave out
.mosi(mosi), ///< Master out, slave in
.sck(sck), ///< SPI clock
.nCs(nCs), ///< ~Chip select
// FIFO Status
.txDataPresent(txDataPresentM), ///< When high, interface is busy
.txHalfFull(txHalfFullM), ///< TX FIFO is getting full
.txFull(txFullM), ///< TX FIFO is full
.rxDataPresent(rxDataPresentM), ///< RX FIFO has data available
.rxHalfFull(rxHalfFullM), ///< RX FIFO is getting full
.rxFull(rxFullM), ///< RX FIFO is full
// Data Interface Outputs
.dataOut(doutMaster) ///< [7:0] Data received
);
XcvrSpiSlave #(
.LOG2_DEPTH(LOG2_DEPTH)
)
uutSlave (
// INPUTS
.clk(clk), ///< System Clock
.rst(rst), ///< Reset, synchronous and active high
// Data Interface Inputs
.dataIn(dinSlave), ///< [7:0] Data to send
.write(writeSlave), ///< Strobe to write to TX FIFO
.read(readSlave), ///< Strove to read from RX FIFO
.cpol(cpol), ///< SPI data polarity
.cpha(cpha), ///< SPI clock phase
// SPI Signals
.nCs(nCs), ///< ~Chip select
.sck(sck), ///< SPI clock
.miso(miso), ///< Master in, slave out
.mosi(mosi), ///< Master out, slave in
// FIFO Status
.txDataPresent(txDataPresentS), ///< When high, interface has data to send back
.txHalfFull(txHalfFullS), ///< TX FIFO is getting full
.txFull(txFullS), ///< TX FIFO is full
.rxDataPresent(rxDataPresentS), ///< RX FIFO has data available
.rxHalfFull(rxHalfFullS), ///< RX FIFO is getting full
.rxFull(rxFullS), ///< RX FIFO is full
// Data Interface Outputs
.dataOut(doutSlave) ///< [7:0] Data received
);
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module counts which bits for serial audio transfers. The module *
* assume that the data format is I2S, as it is described in the audio *
* chip's datasheet. *
* *
******************************************************************************/
module altera_up_audio_bit_counter (
// Inputs
clk,
reset,
bit_clk_rising_edge,
bit_clk_falling_edge,
left_right_clk_rising_edge,
left_right_clk_falling_edge,
// Bidirectionals
// Outputs
counting
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter BIT_COUNTER_INIT = 5'h0F;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input bit_clk_rising_edge;
input bit_clk_falling_edge;
input left_right_clk_rising_edge;
input left_right_clk_falling_edge;
// Bidirectionals
// Outputs
output reg counting;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire reset_bit_counter;
// Internal Registers
reg [ 4: 0] bit_counter;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
bit_counter <= 5'h00;
else if (reset_bit_counter == 1'b1)
bit_counter <= BIT_COUNTER_INIT;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter != 5'h00))
bit_counter <= bit_counter - 5'h01;
end
always @(posedge clk)
begin
if (reset == 1'b1)
counting <= 1'b0;
else if (reset_bit_counter == 1'b1)
counting <= 1'b1;
else if ((bit_clk_falling_edge == 1'b1) && (bit_counter == 5'h00))
counting <= 1'b0;
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign reset_bit_counter = left_right_clk_rising_edge |
left_right_clk_falling_edge;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
MIPS System: CPU Core + Memory
*/
module mips_system (
input wire clk,
input wire rst,
input [15:0] sw,
output [15:0] led,
// SPI ports
input wire sdo_i,
output wire sck_o,
output wire cs_o
);
localparam [31:0] instr_addr_high = 32'h000001ff,
instr_addr_low = 32'h00000000,
data_addr_high = 32'h000003ff,
data_addr_low = 32'h00000200,
gpio_base_addr = 32'h00000400,
ioctrl_base_addr = 32'h00000800;
wire i_read_en;
wire [31:0] i_addr;
wire [31:0] i_instr;
wire d_read_en;
wire d_write_en;
wire [31:0] d_addr;
wire [31:0] d_write_data;
wire [31:0] d_read_data;
// GPIO wb signals
wire [31:0] gpio_dat_i;
wire [31:0] gpio_dat_o;
wire [31:0] gpio_adr_i;
wire gpio_we_i;
wire [3:0] gpio_sel_i;
wire gpio_cyc_i;
wire gpio_stb_i;
wire gpio_ack_o;
// IOCTRL wb signals
wire [31:0] ioctrl_dat_i;
wire [31:0] ioctrl_dat_o;
wire [31:0] ioctrl_adr_i;
wire ioctrl_we_i;
wire [3:0] ioctrl_sel_i;
wire ioctrl_cyc_i;
wire ioctrl_stb_i;
wire ioctrl_ack_o;
// MIPS wb signals
wire [31:0] mips_wbm_dat_i;
wire mips_wbm_ack_i;
wire [31:0] mips_wbm_dat_o;
wire mips_wbm_we_o;
wire [3:0] mips_wbm_sel_o;
wire [31:0] mips_wbm_adr_o;
wire mips_wbm_cyc_o;
wire mips_wbm_stb_o;
// RAM wishbone signals
wire [31:0] ram_dat_i;
wire [31:0] ram_dat_o;
wire [31:0] ram_addr_i;
wire ram_we_i;
wire [3:0] ram_sel_i;
wire ram_cyc_i;
wire ram_stb_i;
wire ram_ack_o;
wire [2:0] ram_cti_i = 0; // classic cycle
gpio_wb #(gpio_base_addr) gpio_inst(
// system signals
.clk_i(clk),
.rst_i(rst),
// wb signals
.dat_i(gpio_dat_i),
.dat_o(gpio_dat_o),
.adr_i(gpio_adr_i),
.we_i(gpio_we_i),
.sel_i(gpio_sel_i),
.cyc_i(gpio_cyc_i),
.stb_i(gpio_stb_i),
.ack_o(gpio_ack_o),
// func signals
.sw_bi(sw),
.gpio_bo(led)
);
ioctrl_wb #(ioctrl_base_addr) ioctrl_inst(
// system signals
.clk_i(clk),
.rst_i(rst),
// wb signals
.dat_i(ioctrl_dat_i),
.dat_o(ioctrl_dat_o),
.adr_i(ioctrl_adr_i),
.we_i(ioctrl_we_i),
.sel_i(ioctrl_sel_i),
.cyc_i(ioctrl_cyc_i),
.stb_i(ioctrl_stb_i),
.ack_o(ioctrl_ack_o),
// spi signals
.sdo_i(sdo_i),
.sck_o(sck_o),
.cs_o(cs_o)
);
data_ram_wb #(
.addr_high(data_addr_high),
.addr_low(data_addr_low)) ram_inst(
.dat_i(ram_dat_i),
.dat_o(ram_dat_o),
.adr_i(ram_addr_i),
.we_i(ram_we_i),
.sel_i(ram_sel_i),
.cyc_i(ram_cyc_i),
.stb_i(ram_stb_i),
.ack_o(ram_ack_o),
.cti_i(ram_cti_i),
.clk_i(clk),
.rst_i(rst));
intercon wb_inst (
// wishbone master port(s)
// mips_wbm
.mips_wbm_dat_i(mips_wbm_dat_i),
.mips_wbm_ack_i(mips_wbm_ack_i),
.mips_wbm_dat_o(mips_wbm_dat_o),
.mips_wbm_we_o(mips_wbm_we_o),
.mips_wbm_sel_o(mips_wbm_sel_o),
.mips_wbm_adr_o(mips_wbm_adr_o),
.mips_wbm_cyc_o(mips_wbm_cyc_o),
.mips_wbm_stb_o(mips_wbm_stb_o),
// wishbone slave port(s)
// ram_wbs
.ram_wbs_dat_o(ram_dat_o),
.ram_wbs_ack_o(ram_ack_o),
.ram_wbs_dat_i(ram_dat_i),
.ram_wbs_we_i(ram_we_i),
.ram_wbs_sel_i(ram_sel_i),
.ram_wbs_adr_i(ram_addr_i),
.ram_wbs_cyc_i(ram_cyc_i),
.ram_wbs_stb_i(ram_stb_i),
// wbs1
.wbs1_dat_o(gpio_dat_o),
.wbs1_ack_o(gpio_ack_o),
.wbs1_dat_i(gpio_dat_i),
.wbs1_we_i(gpio_we_i),
.wbs1_sel_i(gpio_sel_i),
.wbs1_adr_i(gpio_adr_i),
.wbs1_cyc_i(gpio_cyc_i),
.wbs1_stb_i(gpio_stb_i),
// wbs2
.wbs2_dat_o(ioctrl_dat_o),
.wbs2_ack_o(ioctrl_ack_o),
.wbs2_dat_i(ioctrl_dat_i),
.wbs2_we_i(ioctrl_we_i),
.wbs2_sel_i(ioctrl_sel_i),
.wbs2_adr_i(ioctrl_adr_i),
.wbs2_cyc_i(ioctrl_cyc_i),
.wbs2_stb_i(ioctrl_stb_i),
// clock and reset
.clk(clk),
.reset(rst)
);
pipeline pipeline_inst (
.clk(clk),
.rst(rst),
.wb_done_i(wb_done),
.i_read_en(i_read_en),
.i_addr(i_addr),
.i_instr_in(i_instr),
.d_read_en(d_read_en),
.d_write_en(d_write_en),
.d_addr(d_addr),
.d_write_data(d_write_data),
.d_data_in(d_read_data));
bus_control #(
.addr_high(instr_addr_high),
.addr_low(instr_addr_low)) memory_inst (
.clk(clk),
.rst(rst),
.i_read_en(i_read_en),
.i_addr(i_addr),
.i_instr_out(i_instr),
.d_read_en(d_read_en),
.d_write_en(d_write_en),
.d_addr(d_addr),
.d_write_data(d_write_data),
.d_data_out(d_read_data),
.wb_done_o(wb_done),
.wbm_dat_i(mips_wbm_dat_i),
.wbm_ack_i(mips_wbm_ack_i),
.wbm_dat_o(mips_wbm_dat_o),
.wbm_we_o(mips_wbm_we_o),
.wbm_sel_o(mips_wbm_sel_o),
.wbm_adr_o(mips_wbm_adr_o),
.wbm_cyc_o(mips_wbm_cyc_o),
.wbm_stb_o(mips_wbm_stb_o));
endmodule // mips_system
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_ln_double_s5 (
enable, resetn,
clock,
dataa,
result);
input enable, resetn;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
fp_ln_double_s5 inst ( .clk(clock),
.areset(1'b0),
.en(enable),
.a(dataa),
.q(sub_wire0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLCLKP_BLACKBOX_V
`define SKY130_FD_SC_HS__DLCLKP_BLACKBOX_V
/**
* dlclkp: Clock gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlclkp (
GCLK,
GATE,
CLK
);
output GCLK;
input GATE;
input CLK ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLCLKP_BLACKBOX_V
|
module peripheral_uart(clk , rst , d_in , cs , addr , rd , wr, d_out, uart_tx, ledout );
input clk;
input rst;
input [15:0]d_in;
input cs;
input [3:0]addr; // 4 LSB from j1_io_addr
input rd;
input wr;
output reg [15:0]d_out;
output uart_tx;
output reg ledout=0;
//------------------------------------ regs and wires-------------------------------
reg [2:0] s; //selector mux_4 and demux_4
reg [7:0] d_in_uart; // data in uart
wire uart_busy; // out_uart
//------------------------------------ regs and wires-------------------------------
always @(*) begin//----address_decoder------------------
case (addr)
4'h0:begin s = (cs && rd) ? 3'b001 : 3'b000 ;end //busy
4'h2:begin s = (cs && wr) ? 3'b010 : 3'b000 ;end //data
4'h4:begin s = (cs && wr) ? 3'b100 : 3'b000 ;end //ledout
default:begin s=3'b000 ; end
endcase
end//-----------------address_decoder--------------------
always @(negedge clk) begin//-------------------- escritura de registros
d_in_uart= (s[1]) ? d_in[7:0] : d_in_uart; // data in uart
ledout = (s[2]) ? d_in[0] : ledout; // write ledout register
end//------------------------------------------- escritura de registros
always @(negedge clk) begin//-----------------------mux_4 : multiplexa salidas del periferico
case (s)
3'b001: d_out[0]= uart_busy; // data out uart
default: d_out=0;
endcase
end//----------------------------------------------mux_4
//(addr != 4'h4): se hace para evitar escrituras fantasma
uart uart(.uart_busy(uart_busy), .uart_tx(uart_tx), .uart_wr_i(cs && wr && (addr != 4'h4) ), .uart_dat_i(d_in_uart), .sys_clk_i(clk), .sys_rst_i(rst));// System clock,
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFSTP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFSTP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFSTP_SYMBOL_V
|
(** * StlcProp: Properties of STLC *)
Set Warnings "-notation-overridden,-parsing".
Require Import Maps.
Require Import Types.
Require Import Stlc.
Require Import Smallstep.
Module STLCProp.
Import STLC.
(** In this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ################################################################# *)
(** * Canonical Forms *)
(** As we saw for the simple calculus in the [Types] chapter, the
first step in establishing basic properties of reduction and types
is to identify the possible _canonical forms_ (i.e., well-typed
closed values) belonging to each type. For [Bool], these are the boolean
values [ttrue] and [tfalse]. For arrow types, the canonical forms
are lambda-abstractions. *)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
(* ################################################################# *)
(** * Progress *)
(** The _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take a reduction step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. We'll give the proof in English first, then
the formal version. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
(** _Proof_: By induction on the derivation of [|- t \in T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we can see by inspecting the rule that [t]
is a value.
- If the last rule of the derivation is [T_App], then [t] has the
form [t1 t2] for some [t1] and [t2], where [|- t1 \in T2 -> T]
and [|- t2 \in T2] for some type [T2]. By the induction
hypothesis, either [t1] is a value or it can take a reduction
step.
- If [t1] is a value, then consider [t2], which by the other
induction hypothesis must also either be a value or take a
step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation is [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]). *)
Proof with eauto.
intros t T Ht.
remember (@empty ty) as Gamma.
induction Ht; subst Gamma...
- (* T_Var *)
(* contradictory: variables cannot be typed in an
empty context *)
inversion H.
- (* T_App *)
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct IHHt2...
* (* t2 is also a value *)
assert (exists x0 t0, t1 = tabs x0 T11 t0).
eapply canonical_forms_fun; eauto.
destruct H1 as [x0 [t0 Heq]]. subst.
exists ([x0:=t2]t0)...
* (* t2 steps *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
+ (* t1 steps *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
- (* T_If *)
right. destruct IHHt1...
+ (* t1 is a value *)
destruct (canonical_forms_bool t1); subst; eauto.
+ (* t1 also steps *)
inversion H as [t1' Hstp]. exists (tif t1' t2 t3)...
Qed.
(** **** Exercise: 3 stars, advanced (progress_from_term_ind) *)
(** Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof.
intros t.
induction t; intros T Ht; auto.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Preservation *)
(** The other half of the type soundness property is the
preservation of types during reduction. For this part, we'll need
to develop some technical machinery for reasoning about variables
and substitution. Working from top to bottom (from the high-level
property we are actually interested in to the lowest-level
technical lemmas that are needed by various cases of the more
interesting proofs), the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter.
The one case that is significantly different is the one for
the [ST_AppAbs] rule, whose definition uses the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, the tricky cases are the ones for
variables and for function abstractions. In both, we discover
that we need to take a term [s] that has been shown to be
well-typed in some context [Gamma] and consider the same term
[s] in a slightly different context [Gamma']. For this we
prove a...
- _context invariance_ lemma, showing that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. And finally, for this, we need a
careful definition of...
- the _free variables_ of a term -- i.e., those variables
mentioned in a term and not in the scope of an enclosing
function abstraction binding a variable of the same name.
To make Coq happy, we need to formalize the story in the opposite
order... *)
(* ================================================================= *)
(** ** Free Occurrences *)
(** A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x].
For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y]
Formally: *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Hint Constructors appears_free_in.
(** The _free variables_ of a term are just the variables that appear
free in it. A term with no free variables is said to be
_closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(** An _open_ term is one that is not closed (or not known to be
closed). *)
(** **** Exercise: 1 starM (afi) *)
(** In the space below, write out the rules of the [appears_free_in]
relation in informal inference-rule notation. (Use whatever
notational conventions you like -- the point of the exercise is
just for you to think a bit about the meaning of each rule.)
Although this is a rather low-level, technical definition,
understanding it is crucial to understanding substitution and its
properties, which are really the crux of the lambda-calculus. *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Substitution *)
(** To prove that substitution preserves typing, we first need a
technical lemma connecting free variables and typing contexts: If
a variable [x] appears free in a term [t], and if we know [t] is
well typed in context [Gamma], then it must be the case that
[Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed
under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used is [afi_var], then [t = x], and from the
assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used is [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12] and [x] appears free in [t12], and we also know
that [x] is different from [y]. The difference from the
previous cases is that, whereas [t] is well typed under
[Gamma], its body [t12] is well typed under [(Gamma, y:T11)],
so the IH allows us to conclude that [x] is assigned some type
by the extended context [(Gamma, y:T11)]. To conclude that
[Gamma] assigns a type to [x], we appeal to lemma
[update_neq], noting that [x] and [y] are different
variables. *)
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
induction H;
intros; try solve [inversion H0; eauto].
- (* afi_abs *)
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite update_neq in H7; assumption.
Qed.
(** Next, we'll need the fact that any term [t] that is well typed in
the empty context is closed (it has no free variables). *)
(** **** Exercise: 2 stars, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, when we have a proof [Gamma |- t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
(** _Proof_: By induction on the derivation of
[Gamma |- t \in T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' |- t \in T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 |- t12 \in T12]. The
induction hypothesis is that, for any context [Gamma''], if
[Gamma, y:T11] and [Gamma''] assign the same types to all the
free variables in [t12], then [t12] has type [T12] under
[Gamma'']. Let [Gamma'] be a context which agrees with
[Gamma] on the free variables in [t]; we must show [Gamma' |-
\y:T11. t12 \in T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 |- t12 \in
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must be either [y] or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, note that any variable other
than [y] that occurs free in [t12] also occurs free in [t =
\y:T11. t12], and by assumption [Gamma] and [Gamma'] agree on
all such variables; hence so do [Gamma, y:T11] and [Gamma',
y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 \in T2 -> T] and [Gamma |- t2 \in T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. But all free variables in
[t1] are also free in [t1 t2], and similarly for [t2]; hence
the desired result follows from the induction hypotheses. *)
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
- (* T_Var *)
apply T_Var. rewrite <- H0...
- (* T_Abs *)
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [update Gamma x T11] *)
unfold update. unfold t_update. destruct (beq_id x0 x1) eqn: Hx0x1...
rewrite beq_id_false_iff in Hx0x1. auto.
- (* T_App *)
apply T_App with T11...
Qed.
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types. *)
(** Formally, the so-called _substitution lemma_ says this:
Suppose we have a term [t] with a free variable [x], and suppose
we've assigned a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we can
substitute [v] for each of the occurrences of [x] in [t] and
obtain a new term that still has type [T]. *)
(** _Lemma_: If [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
update Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
(** One technical subtlety in the statement of the lemma is that
we assign [v] the type [U] in the _empty_ context -- in other
words, we assume [v] is closed. This assumption considerably
simplifies the [T_Abs] case of the proof (compared to assuming
[Gamma |- v \in U], which would be the other reasonable assumption
at this point) because the context invariance lemma then tells us
that [v] has type [U] in any context at all -- we don't have to
worry about free variables in [v] clashing with the variable being
introduced into the context by [T_Abs].
The substitution lemma can be viewed as a kind of commutation
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ] -- the result is the same either
way.
_Proof_: We show, by induction on [t], that for all [T] and
[Gamma], if [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma
|- [x:=v]t \in T].
- If [t] is a variable there are two cases to consider,
depending on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U |- x \in
T] we conclude that [U = T]. We must show that [[x:=v]x =
v] has type [T] under [Gamma], given the assumption that
[v] has type [U = T] under the empty context. This
follows from context invariance: if a closed term has type
[T] in the empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U |- t12 \in T']
and [|- v \in U], then [Gamma' |- [x:=v]t12 \in T'].
The substitution in the conclusion behaves differently
depending on whether [x] and [y] are the same variable.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma |-
t \in T]. But we know [Gamma,x:U |- t : T], and, since [y]
does not appear free in [\y:T11. t12], the context invariance
lemma yields [Gamma |- t \in T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 |- t12 \in
T12] by inversion of the typing relation, from which
[Gamma,y:T11,x:U |- t12 \in T12] follows by the context
invariance lemma, so the IH applies, giving us [Gamma,y:T11 |-
[x:=v]t12 \in T12]. By [T_Abs], [Gamma |- \y:T11. [x:=v]t12
\in T11->T12], and by the definition of substitution (noting
that [x <> y]), [Gamma |- \y:T11. [x:=v]t12 \in T11->T12] as
required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
_Technical note_: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[update Gamma x U |- t \in T] is not completely generic, in the
sense that one of the "slots" in the typing relation -- namely the
context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, is completely generic.
*)
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
- (* tvar *)
rename i into y. destruct (beq_idP x y) as [Hxy|Hxy].
+ (* x=y *)
subst.
rewrite update_eq in H2.
inversion H2; subst.
eapply context_invariance. eassumption.
apply typable_empty__closed in Ht'. unfold closed in Ht'.
intros. apply (Ht' x0) in H0. inversion H0.
+ (* x<>y *)
apply T_Var. rewrite update_neq in H2...
- (* tabs *)
rename i into y. rename t into T. apply T_Abs.
destruct (beq_idP x y) as [Hxy | Hxy].
+ (* x=y *)
subst. rewrite update_shadow in H5. apply H5.
+ (* x<>y *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold update, t_update.
destruct (beq_idP y z) as [Hyz | Hyz]; subst; trivial.
rewrite <- beq_id_false_iff in Hxy.
rewrite Hxy...
Qed.
(* ================================================================= *)
(** ** Main Theorem *)
(** We now have the tools we need to prove preservation: if a closed
term [t] has type [T] and takes a step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
reduction relation preserves types. *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
(** _Proof_: By induction on the derivation of [|- t \in T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation is [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could be used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [[x:=t2]t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis. *)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
induction HT;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
- (* T_App *)
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
+ (* ST_AppAbs *)
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
(** **** Exercise: 2 stars, recommendedM (subject_expansion_stlc) *)
(** An exercise in the [Types] chapter asked about the _subject
expansion_ property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That is,
is it always the case that, if [t ==> t'] and [has_type t' T],
then [empty |- t \in T]? If so, prove it. If not, give a
counter-example not involving conditionals.
(* FILL IN HERE *)
[]
*)
(* ################################################################# *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, optional (type_soundness) *)
(** Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################# *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 starsM (types_unique) *)
(** Another nice property of the STLC is that types are unique: a
given term (in a given context) has at most one type. *)
(** Formalize this statement and prove it. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 1 starM (progress_preservation_statement) *)
(** Without peeking at their statements above, write down the progress
and preservation theorems for the simply typed lambda-calculus (as
Coq theorems). *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 starsM (stlc_variation1) *)
(** Suppose we add a new term [zap] with the following reduction rule
--------- (ST_Zap)
t ==> zap
and the following typing rule:
---------------- (T_Zap)
Gamma |- zap : T
Which of the following properties of the STLC remain true in
the presence of these rules? For each property, write either
"remains true" or "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
(* FILL IN HERE *)
- Progress
(* FILL IN HERE *)
- Preservation
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 starsM (stlc_variation2) *)
(** Suppose instead that we add a new term [foo] with the following
reduction rules:
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
(* FILL IN HERE *)
- Progress
(* FILL IN HERE *)
- Preservation
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 starsM (stlc_variation3) *)
(** Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
(* FILL IN HERE *)
- Progress
(* FILL IN HERE *)
- Preservation
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation4) *)
(** Suppose instead that we add the following new rule to the
reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
(* FILL IN HERE *)
- Progress
(* FILL IN HERE *)
- Preservation
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation5) *)
(** Suppose instead that we add the following new rule to the typing
relation:
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
(* FILL IN HERE *)
- Progress
(* FILL IN HERE *)
- Preservation
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation6) *)
(** Suppose instead that we add the following new rule to the typing
relation:
Gamma |- t1 \in Bool
Gamma |- t2 \in Bool
--------------------- (T_FunnyApp')
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
(* FILL IN HERE *)
- Progress
(* FILL IN HERE *)
- Preservation
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars, optional (stlc_variation7) *)
(** Suppose we add the following new rule to the typing relation
of the STLC:
------------------- (T_FunnyAbs)
|- \x:Bool.t \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
(* FILL IN HERE *)
- Progress
(* FILL IN HERE *)
- Preservation
(* FILL IN HERE *)
[]
*)
End STLCProp.
(* ================================================================= *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
Import STLC.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity). *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing. *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm.
(** **** Exercise: 4 starsM (stlc_arith) *)
(** Finish formalizing the definition and properties of the STLC
extended with arithmetic. Specifically:
- Copy the core definitions and theorems for STLC that we went
through above (from the definition of values through the
Preservation theorem, inclusive), and paste it into the file at
this point. Do not copy examples, exercises, etc. (In
particular, make sure you don't copy any of the [] comments at
the end of exercises, to avoid confusing the autograder.)
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic
operators.
- Extend the proofs of all the properties (up to [preservation])
of the original STLC to deal with the new syntactic forms. Make
sure Coq accepts the whole file. *)
(* FILL IN HERE *)
(** [] *)
End STLCArith.
(** $Date: 2017-05-17 16:11:21 -0400 (Wed, 17 May 2017) $ *)
|
// This file contains behavioral Verilog that is used as the test harness for
// running simulations.
module CounterHarness;
// VPD dumping
reg [1023:0] vcdplusfile = 0;
initial
begin
if ($value$plusargs("vcdplusfile=%s", vcdplusfile))
begin
`ifdef HAVE_SYNOPSYS_VCDPLUS
$vcdplusfile(vcdplusfile);
$vcdpluson(0);
$vcdplusmemon(0);
`endif
end
end
reg clock = 1'b0;
always #(1) clock = ~clock;
reg reset = 1'b1;
initial #10 reset = 0;
reg [7:0] cycle = 0;
always @(posedge clock)
begin
cycle <= cycle + 1;
if (cycle > 250)
begin
`ifdef HAVE_SYNOPSYS_VCDPLUS
$vcdplusclose;
$dumpoff;
`endif
$finish;
end
end
reg [4:0] goldCount;
always @(posedge clock)
begin
if (reset)
goldCount <= 0;
else
goldCount <= goldCount + 1;
end
reg [4:0] dutCount;
Counter dut(
.clock(clock),
.reset(reset),
.count(dutCount)
);
always @(posedge clock)
begin
$display("cycle=%d reset=%d goldCount=%d dutCount=%d", cycle, reset, goldCount, dutCount);
if (!reset)
begin
casez (goldCount - dutCount)
0: ;
default:
begin
$display("*** FAILED ***");
`ifdef HAVE_SYNOPSYS_VCDPLUS
$vcdplusclose;
$dumpoff;
$fatal;
`endif
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_edf_p_pg/sky130_fd_sc_hs__u_edf_p_pg.v"
`celldefine
module sky130_fd_sc_hs__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_edf_p_pg `UNIT_DELAY u_edf_p_pg0 (buf_Q , D, CLK, DE, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_FUNCTIONAL_V |
// megafunction wizard: %LPM_DIVIDE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_DIVIDE
// ============================================================
// File Name: acl_int_divs.v
// Megafunction Name(s):
// LPM_DIVIDE
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_div32s (
enable,
clock,
denom,
numer,
quotient,
remain);
input enable;
input clock;
input [31:0] denom;
input [31:0] numer;
output [31:0] quotient;
output [31:0] remain;
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] remain = sub_wire0[31:0];
wire [31:0] quotient = sub_wire1[31:0];
lpm_divide LPM_DIVIDE_component (
.clock (clock),
.clken (enable),
.denom (denom),
.numer (numer),
.remain (sub_wire0),
.quotient (sub_wire1),
.aclr (1'b0));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE",
LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_pipeline = 32,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 32,
LPM_DIVIDE_component.lpm_widthn = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "FALSE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL "clken"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: denom 0 0 32 0 INPUT NODEFVAL "denom[31..0]"
// Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL "numer[31..0]"
// Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL "quotient[31..0]"
// Retrieval info: USED_PORT: remain 0 0 32 0 OUTPUT NODEFVAL "remain[31..0]"
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @denom 0 0 32 0 denom 0 0 32 0
// Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
// Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
// Retrieval info: CONNECT: remain 0 0 32 0 @remain 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_int_divs_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`timescale 1 ps / 1 ps
module song_ip_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output speaker,
output ampSD,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// Instantiation of Axi Bus Interface S00_AXI
song_ip_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) song_ip_v1_0_S00_AXI_inst (
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready),
.speaker(speaker), //our stuff
.ampSD(ampSD) // our stuff
);
// Add user logic here
// User logic ends
endmodule
|
// Check that when the right hand operand of a shift operation
// contains 'x' or 'z' bits, the result is undefined.
module test;
reg pass;
reg signed [3:0] lhs;
reg [3:0] rhs;
reg [3:0] res;
wire [3:0] res1 = lhs << rhs;
wire [3:0] res2 = lhs >> rhs;
wire [3:0] res3 = lhs >>> rhs;
wire [3:0] res4 = lhs << 4'b000x;
wire [3:0] res5 = lhs >> 4'b00x0;
wire [3:0] res6 = lhs >>> 4'b0z00;
wire [3:0] res7 = 4'd1 << 4'b000x;
wire [3:0] res8 = 4'd1 >> 4'b00x0;
wire [3:0] res9 = 4'd1 >>> 4'b0z00;
wire [3:0] res10 = 4'd0 << rhs;
wire [3:0] res11 = 4'd0 >> rhs;
wire [3:0] res12 = 4'd0 >>> rhs;
initial begin
pass = 1'b1;
lhs = 4'd1;
if (res1 !== 4'bxxxx) begin
$display("FAILED test 1, expected 4'bxxxx, got 4'b%b", res1);
pass = 1'b0;
end
if (res2 !== 4'bxxxx) begin
$display("FAILED test 2, expected 4'bxxxx, got 4'b%b", res2);
pass = 1'b0;
end
if (res3 !== 4'bxxxx) begin
$display("FAILED test 3, expected 4'bxxxx, got 4'b%b", res3);
pass = 1'b0;
end
if (res4 !== 4'bxxxx) begin
$display("FAILED test 4, expected 4'bxxxx, got 4'b%b", res4);
pass = 1'b0;
end
if (res5 !== 4'bxxxx) begin
$display("FAILED test 5, expected 4'bxxxx, got 4'b%b", res5);
pass = 1'b0;
end
if (res6 !== 4'bxxxx) begin
$display("FAILED test 6, expected 4'bxxxx, got 4'b%b", res6);
pass = 1'b0;
end
if (res7 !== 4'bxxxx) begin
$display("FAILED test 7, expected 4'bxxxx, got 4'b%b", res7);
pass = 1'b0;
end
if (res8 !== 4'bxxxx) begin
$display("FAILED test 8, expected 4'bxxxx, got 4'b%b", res8);
pass = 1'b0;
end
if (res9 !== 4'bxxxx) begin
$display("FAILED test 9, expected 4'bxxxx, got 4'b%b", res9);
pass = 1'b0;
end
if (res10 !== 4'bxxxx) begin
$display("FAILED test 10, expected 4'bxxxx, got 4'b%b", res10);
pass = 1'b0;
end
if (res11 !== 4'bxxxx) begin
$display("FAILED test 11, expected 4'bxxxx, got 4'b%b", res11);
pass = 1'b0;
end
if (res12 !== 4'bxxxx) begin
$display("FAILED test 12, expected 4'bxxxx, got 4'b%b", res12);
pass = 1'b0;
end
res = lhs << rhs;
if (res !== 4'bxxxx) begin
$display("FAILED test 13, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = lhs >> rhs;
if (res !== 4'bxxxx) begin
$display("FAILED test 14, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = lhs >>> rhs;
if (res !== 4'bxxxx) begin
$display("FAILED test 15, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = lhs << 4'b000x;
if (res !== 4'bxxxx) begin
$display("FAILED test 16, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = lhs >> 4'b00x0;
if (res !== 4'bxxxx) begin
$display("FAILED test 17, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = lhs >>> 4'b0z00;
if (res !== 4'bxxxx) begin
$display("FAILED test 18, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = 4'd1 << 4'b000x;
if (res !== 4'bxxxx) begin
$display("FAILED test 19, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = 4'd1 >> 4'b00x0;
if (res !== 4'bxxxx) begin
$display("FAILED test 20, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = 4'd1 >>> 4'b0z00;
if (res !== 4'bxxxx) begin
$display("FAILED test 21, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = 4'd0 << rhs;
if (res !== 4'bxxxx) begin
$display("FAILED test 22, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = 4'd0 >> rhs;
if (res !== 4'bxxxx) begin
$display("FAILED test 23, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
res = 4'd0 >>> rhs;
if (res !== 4'bxxxx) begin
$display("FAILED test 24, expected 4'bxxxx, got 4'b%b", res);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_8_b2s_simple_fifo
`default_nettype wire
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v12_0_bhv_ver_as
* |
* +-fifo_generator_v12_0_bhv_ver_ss
* |
* +-fifo_generator_v12_0_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign wr_rst_busy = WR_RST_BUSY;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
FIFO_GENERATOR_v12_0_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v12_0_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy (wr_rst_busy),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexum" || C_FAMILY == "zynque") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v12_0_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
end
end
assign axi_rs_rst = rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
FIFO_GENERATOR_v12_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v12_0_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v12_0_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v12_0_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
FIFO_GENERATOR_v12_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v12_0_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
FIFO_GENERATOR_v12_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v12_0_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_SLAVE_CE == 1) ? wrch_we & S_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_MASTER_CE == 1) ? wrch_re & M_ACLK_EN : wrch_re;
FIFO_GENERATOR_v12_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v12_0_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
FIFO_GENERATOR_v12_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v12_0_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_SLAVE_CE == 1) ? rdch_we & S_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_MASTER_CE == 1) ? rdch_re & M_ACLK_EN : rdch_re;
FIFO_GENERATOR_v12_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v12_0_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v12_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //FIFO_GENERATOR_v12_0
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module FIFO_GENERATOR_v12_0_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexum" || C_FAMILY == "zynque") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
reg rd_rst_asreg_d1 = 0;
reg rd_rst_asreg_d2 = 0;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
reg wr_rst_asreg_d1 = 0;
reg wr_rst_asreg_d2 = 0;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
reg rst_asreg_d1 = 0;
reg rst_asreg_d2 = 0;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v12_0_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v12_0_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v12_0_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v12_0_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v12_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= #`TCQ 1;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v12_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
generate
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed;
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg;
wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1;
end
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= #`TCQ 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg;
rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1;
end
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= #`TCQ 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed;
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
rst_asreg <= #`TCQ 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
rst_asreg_d1 <= #`TCQ rst_asreg;
rst_asreg_d2 <= #`TCQ rst_asreg_d1;
end
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= #`TCQ 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
end
// end g8s_cc_rst
endgenerate
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b0;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b0;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d4;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //FIFO_GENERATOR_v12_0_CONV_VER
module fifo_generator_v12_0_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v12_0_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v12_0_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexum" || C_FAMILY == "zynque") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= #`TCQ 1'b1;
ALMOST_EMPTY <= #`TCQ 1'b1;
rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= #`TCQ C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
valid_d1: valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= #`TCQ 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end
endgenerate
//Capture delayed version of dout
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v12_0_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v12_0_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= #`TCQ 0;
ideal_prog_empty <= #`TCQ 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
// block memory has a synchronous reset
always @(posedge RD_CLK) begin : gen_fifo_blkmemdout
// make it consistent with the core.
if (rd_rst_i) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2)
err_type <= #`TCQ 0;
// BRAM resets synchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
end //always
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type <= #`TCQ 0;
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always
endmodule // fifo_generator_v12_0_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v12_0_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v12_0_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v12_0_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexum" || C_FAMILY == "zynque") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG==1 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_HAS_SRST ? SRST : 0;
assign srst_wrst_busy = C_HAS_SRST ? (SRST || WR_RST_BUSY) : 0;
assign srst_rrst_busy = C_HAS_SRST ? (SRST || RD_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
// block memory has a synchronous reset
generate if (C_MEMORY_TYPE < 2) begin : gen_fifo_blkmemdout_emb
always @(posedge CLK) begin
// BRAM resets synchronously
// make it consistent with the core.
if ((rst_i || srst_rrst_busy) && (C_USE_DOUT_RST == 1))
ideal_dout_d1 <= #`TCQ dout_reset_val;
end //always
end endgenerate // gen_fifo_blkmemdout_emb
reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ram_rd_en_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy ) begin
if (srst_wrst_busy)
wr_pntr <= #`TCQ 0;
if (srst_rrst_busy)
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type <= #`TCQ 0;
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type <= #`TCQ 0;
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v12_0_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v12_0_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg read_data_valid_i;
wire ram_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
read_data_valid_i = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_HAS_SRST ? SRST || WR_RST_BUSY || RD_RST_BUSY : 0;
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_FIFO_TYPE != 2) begin : gnll_fifo
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN);
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
curr_state <= 1'b0;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
curr_state <= #`TCQ 1'b0;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
curr_state <= #`TCQ next_state;
ram_valid_i <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = ram_valid_i;
assign USERVALID = C_USERVALID_LOW ? ~read_data_valid_i : read_data_valid_i;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
// BRAM resets synchronously
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end else begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
endmodule
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v12_0_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
`timescale 1ns / 1ps
// UART wants the LSB first
// RX modified to accept 40 MHz clock and receive at 115200 bps
// Note 40e6 / 115200 = 347.2222 and 347.2 / 2 = 173.6 ~= 174 cycles
// For 460800
// 40e6 / 460800 = 86.8 and 86.8 / 2 =~= 43
// For 230400
// 40e6 / 230400 = 173.6 and 173.6/2 = 86.8
// Modified for 460800 baud rate
module uart_rx (
input reset,
input clk,
input [1:0] baud_rate,
input uld_rx_data,
output reg [7:0] rx_data,
input rx_enable,
input rx_in,
output reg rx_empty
);
parameter ML505 = 0; //default to 0 if not specified
// Internal registers
reg [7:0] rx_reg ;
reg [9:0] rx_sample_cnt ;
reg [3:0] rx_cnt ;
reg rx_frame_err ;
(* IOB = "TRUE" *) reg rx_d1;
reg rx_d2 ;
reg rx_busy ;
//reg rx_over_run ;
// UART RX Logic
always @ (posedge clk) begin
if (reset) begin
rx_reg <= 8'd0;
rx_data <= 8'd0;
rx_sample_cnt <= 10'd0;
rx_cnt <= 4'd0;
rx_frame_err <= 1'b0;
//rx_over_run <= 0;
rx_empty <= 1'b1;
rx_d1 <= 1'b1;
rx_d2 <= 1'b1;
rx_busy <= 1'b0;
end else begin
if (rx_enable) begin // Receive data only when rx is enabled
// Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
if (!rx_busy && !rx_d2) begin // Check if just received start of frame
rx_busy <= 1'b1;
//Start halfway through count for first (start) bit to find centre of bit
if (ML505) rx_sample_cnt <= 434;
else begin
case (baud_rate)
2'd0: rx_sample_cnt <= 174; // 115200 Baud
2'd1: rx_sample_cnt <= 87; // 230400 Baud
2'd2: rx_sample_cnt <= 43; // 460800 Baud
default: rx_sample_cnt <= 174; // 115200 Baud
endcase
end
rx_cnt <= 1'b0;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= 8'd0;
rx_data <= rx_data;
end else if (rx_busy) begin // Start of frame detected, Proceed with rest of data
if (ML505) begin
if (rx_sample_cnt == 10'd868) begin
rx_sample_cnt <= 10'd0;
rx_cnt <= rx_cnt + 1;
if (rx_cnt==4'd0) begin
rx_busy <= (rx_d2) ? 1'b0 : rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end else if (rx_cnt==4'd9) begin
rx_busy <= 1'b0;
rx_frame_err <= ~rx_d2;
rx_empty <= ~rx_d2;
rx_reg <= rx_reg;
rx_data <= rx_reg;
end else begin
rx_busy <= rx_busy;
rx_reg[rx_cnt - 1] <= rx_d2;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_data <= rx_data;
rx_frame_err <= rx_frame_err;
end
end else begin
rx_sample_cnt <= rx_sample_cnt +1;
rx_cnt <= rx_cnt;
rx_busy <= rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end
end else begin
case (baud_rate)
2'd0: begin // 115200 Baud
if (rx_sample_cnt == 10'd347) begin
rx_sample_cnt <= 10'd0;
rx_cnt <= rx_cnt + 1;
if (rx_cnt==4'd0) begin
rx_busy <= (rx_d2) ? 1'b0 : rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end else if (rx_cnt==4'd9) begin
rx_busy <= 1'b0;
rx_frame_err <= ~rx_d2;
rx_empty <= ~rx_d2;
rx_reg <= rx_reg;
rx_data <= rx_reg;
end else begin
rx_busy <= rx_busy;
rx_reg[rx_cnt - 1] <= rx_d2;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_data <= rx_data;
rx_frame_err <= rx_frame_err;
end
end else begin
rx_sample_cnt <= rx_sample_cnt +1;
rx_cnt <= rx_cnt;
rx_busy <= rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end
end
2'd1: begin // 230400 Baud
if (rx_sample_cnt == 10'd174) begin
rx_sample_cnt <= 10'd0;
rx_cnt <= rx_cnt + 1;
if (rx_cnt==4'd0) begin
rx_busy <= (rx_d2) ? 1'b0 : rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end else if (rx_cnt==4'd9) begin
rx_busy <= 1'b0;
rx_frame_err <= ~rx_d2;
rx_empty <= ~rx_d2;
rx_reg <= rx_reg;
rx_data <= rx_reg;
end else begin
rx_busy <= rx_busy;
rx_reg[rx_cnt - 1] <= rx_d2;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_data <= rx_data;
rx_frame_err <= rx_frame_err;
end
end else begin
rx_sample_cnt <= rx_sample_cnt +1;
rx_cnt <= rx_cnt;
rx_busy <= rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end
end
2'd2: begin // 460800 Baud
if (rx_sample_cnt == 10'd87) begin
rx_sample_cnt <= 10'd0;
rx_cnt <= rx_cnt + 1;
if (rx_cnt==4'd0) begin
rx_busy <= (rx_d2) ? 1'b0 : rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end else if (rx_cnt==4'd9) begin
rx_busy <= 1'b0;
rx_frame_err <= ~rx_d2;
rx_empty <= ~rx_d2;
rx_reg <= rx_reg;
rx_data <= rx_reg;
end else begin
rx_busy <= rx_busy;
rx_reg[rx_cnt - 1] <= rx_d2;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_data <= rx_data;
rx_frame_err <= rx_frame_err;
end
end else begin
rx_sample_cnt <= rx_sample_cnt +1;
rx_cnt <= rx_cnt;
rx_busy <= rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end
end
default: begin // 115200 Baud
if (rx_sample_cnt == 10'd347) begin
rx_sample_cnt <= 10'd0;
rx_cnt <= rx_cnt + 1;
if (rx_cnt==4'd0) begin
rx_busy <= (rx_d2) ? 1'b0 : rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end else if (rx_cnt==4'd9) begin
rx_busy <= 1'b0;
rx_frame_err <= ~rx_d2;
rx_empty <= ~rx_d2;
rx_reg <= rx_reg;
rx_data <= rx_reg;
end else begin
rx_busy <= rx_busy;
rx_reg[rx_cnt - 1] <= rx_d2;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_data <= rx_data;
rx_frame_err <= rx_frame_err;
end
end else begin
rx_sample_cnt <= rx_sample_cnt +1;
rx_cnt <= rx_cnt;
rx_busy <= rx_busy;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_reg <= rx_reg;
rx_data <= rx_data;
end
end
endcase
end // if (~ML505)
end else begin //if (~rx_busy)
rx_reg <= rx_reg;
rx_data <= rx_data;
rx_sample_cnt <= rx_sample_cnt;
rx_cnt <= rx_cnt;
rx_frame_err <= rx_frame_err;
rx_empty <= (uld_rx_data) ? 1'b1 : rx_empty;
rx_busy <= rx_busy;
end
end else begin
rx_reg <= 8'd0;
rx_data <= 8'd0;
rx_sample_cnt <= 10'd0;
rx_cnt <= 4'd0;
rx_frame_err <= 1'b0;
//rx_over_run <= 0;
rx_empty <= 1'b1;
rx_d1 <= 1'b1;
rx_d2 <= 1'b1;
rx_busy <= 1'b0;
end // if (~rx_enable)
end //if (~reset)
end //always
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Round-Robin Arbiter for R and B channel responses
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// arbiter_resp
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_arbiter_resp #
(
parameter C_FAMILY = "none",
parameter integer C_NUM_S = 4, // Number of requesting Slave ports = [2:16]
parameter integer C_NUM_S_LOG = 2, // Log2(C_NUM_S)
parameter integer C_GRANT_ENC = 0, // Enable encoded grant output
parameter integer C_GRANT_HOT = 1 // Enable 1-hot grant output
)
(
// Global Inputs
input wire ACLK,
input wire ARESET,
// Slave Ports
input wire [C_NUM_S-1:0] S_VALID, // Request from each slave
output wire [C_NUM_S-1:0] S_READY, // Grant response to each slave
// Master Ports
output wire [C_NUM_S_LOG-1:0] M_GRANT_ENC, // Granted slave index (encoded)
output wire [C_NUM_S-1:0] M_GRANT_HOT, // Granted slave index (1-hot)
output wire M_VALID, // Grant event
input wire M_READY
);
// Generates a binary coded from onehotone encoded
function [4:0] f_hot2enc
(
input [16:0] one_hot
);
begin
f_hot2enc[0] = |(one_hot & 17'b01010101010101010);
f_hot2enc[1] = |(one_hot & 17'b01100110011001100);
f_hot2enc[2] = |(one_hot & 17'b01111000011110000);
f_hot2enc[3] = |(one_hot & 17'b01111111100000000);
f_hot2enc[4] = |(one_hot & 17'b10000000000000000);
end
endfunction
(* use_clock_enable = "yes" *)
reg [C_NUM_S-1:0] chosen;
wire [C_NUM_S-1:0] grant_hot;
wire master_selected;
wire active_master;
wire need_arbitration;
wire m_valid_i;
wire [C_NUM_S-1:0] s_ready_i;
wire access_done;
reg [C_NUM_S-1:0] last_rr_hot;
wire [C_NUM_S-1:0] valid_rr;
reg [C_NUM_S-1:0] next_rr_hot;
reg [C_NUM_S*C_NUM_S-1:0] carry_rr;
reg [C_NUM_S*C_NUM_S-1:0] mask_rr;
integer i;
integer j;
integer n;
/////////////////////////////////////////////////////////////////////////////
//
// Implementation of the arbiter outputs independant of arbitration
//
/////////////////////////////////////////////////////////////////////////////
// Mask the current requests with the chosen master
assign grant_hot = chosen & S_VALID;
// See if we have a selected master
assign master_selected = |grant_hot[0+:C_NUM_S];
// See if we have current requests
assign active_master = |S_VALID;
// Access is completed
assign access_done = m_valid_i & M_READY;
// Need to handle if we drive S_ready combinatorial and without an IDLE state
// Drive S_READY on the master who has been chosen when we get a M_READY
assign s_ready_i = {C_NUM_S{M_READY}} & grant_hot[0+:C_NUM_S];
// Drive M_VALID if we have a selected master
assign m_valid_i = master_selected;
// If we have request and not a selected master, we need to arbitrate a new chosen
assign need_arbitration = (active_master & ~master_selected) | access_done;
// need internal signals of the output signals
assign M_VALID = m_valid_i;
assign S_READY = s_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Assign conditional onehot target output signal.
assign M_GRANT_HOT = (C_GRANT_HOT == 1) ? grant_hot[0+:C_NUM_S] : {C_NUM_S{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Assign conditional encoded target output signal.
assign M_GRANT_ENC = (C_GRANT_ENC == 1) ? f_hot2enc(grant_hot) : {C_NUM_S_LOG{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Select a new chosen when we need to arbitrate
// If we don't have a new chosen, keep the old one since it's a good chance
// that it will do another request
always @(posedge ACLK)
begin
if (ARESET) begin
chosen <= {C_NUM_S{1'b0}};
last_rr_hot <= {1'b1, {C_NUM_S-1{1'b0}}};
end else if (need_arbitration) begin
chosen <= next_rr_hot;
if (|next_rr_hot) last_rr_hot <= next_rr_hot;
end
end
assign valid_rr = S_VALID;
/////////////////////////////////////////////////////////////////////////////
// Round-robin arbiter
// Selects next request to grant from among inputs with PRIO = 0, if any.
/////////////////////////////////////////////////////////////////////////////
always @ * begin
next_rr_hot = 0;
for (i=0;i<C_NUM_S;i=i+1) begin
n = (i>0) ? (i-1) : (C_NUM_S-1);
carry_rr[i*C_NUM_S] = last_rr_hot[n];
mask_rr[i*C_NUM_S] = ~valid_rr[n];
for (j=1;j<C_NUM_S;j=j+1) begin
n = (i-j > 0) ? (i-j-1) : (C_NUM_S+i-j-1);
carry_rr[i*C_NUM_S+j] = carry_rr[i*C_NUM_S+j-1] | (last_rr_hot[n] & mask_rr[i*C_NUM_S+j-1]);
if (j < C_NUM_S-1) begin
mask_rr[i*C_NUM_S+j] = mask_rr[i*C_NUM_S+j-1] & ~valid_rr[n];
end
end
next_rr_hot[i] = valid_rr[i] & carry_rr[(i+1)*C_NUM_S-1];
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:59:54 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27,
n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41,
n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69,
n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109,
n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120,
n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131,
n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142,
n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164,
n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186,
n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208,
n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241,
n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252,
n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263,
n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274,
n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285,
n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296;
AO21X2TS U48 ( .A0(n165), .A1(n193), .B0(n164), .Y(res[32]) );
XOR2X2TS U49 ( .A(n174), .B(n173), .Y(res[28]) );
XOR2X2TS U50 ( .A(n178), .B(n177), .Y(res[27]) );
XOR2X2TS U51 ( .A(n183), .B(n182), .Y(res[29]) );
NAND2X1TS U52 ( .A(n43), .B(n176), .Y(n177) );
NAND2X1TS U53 ( .A(n42), .B(n181), .Y(n182) );
NAND2X1TS U54 ( .A(n172), .B(n171), .Y(n173) );
NAND2X1TS U55 ( .A(n202), .B(n44), .Y(n203) );
NOR2X1TS U56 ( .A(n186), .B(n184), .Y(n165) );
NAND2XLTS U57 ( .A(n40), .B(n222), .Y(n223) );
NAND2XLTS U58 ( .A(n41), .B(n194), .Y(n195) );
NAND2X1TS U59 ( .A(n15), .B(n239), .Y(n241) );
NAND2XLTS U60 ( .A(n38), .B(n207), .Y(n208) );
NAND2XLTS U61 ( .A(n216), .B(n215), .Y(n217) );
OAI21X1TS U62 ( .A0(n186), .A1(n190), .B0(n187), .Y(n164) );
INVX2TS U63 ( .A(n184), .Y(n191) );
INVX3TS U64 ( .A(n196), .Y(n218) );
INVX2TS U65 ( .A(n220), .Y(n227) );
NAND2X2TS U66 ( .A(n162), .B(in1[30]), .Y(n190) );
NAND2X4TS U67 ( .A(n22), .B(n196), .Y(n21) );
NOR2X2TS U68 ( .A(n162), .B(in1[30]), .Y(n184) );
NOR2X1TS U69 ( .A(n276), .B(in2[5]), .Y(n280) );
CLKMX2X2TS U70 ( .A(in2[30]), .B(n58), .S0(n152), .Y(n162) );
NAND2X2TS U71 ( .A(n157), .B(in1[28]), .Y(n171) );
INVX2TS U72 ( .A(n194), .Y(n175) );
NOR2X1TS U73 ( .A(n57), .B(in2[30]), .Y(n55) );
CLKINVX1TS U74 ( .A(n202), .Y(n135) );
NOR2X1TS U75 ( .A(n269), .B(in2[3]), .Y(n273) );
NAND2X4TS U76 ( .A(n216), .B(n212), .Y(n206) );
INVX6TS U77 ( .A(n124), .Y(n212) );
NAND2BX1TS U78 ( .AN(in2[29]), .B(n140), .Y(n57) );
OR2X2TS U79 ( .A(n133), .B(in1[24]), .Y(n38) );
NAND2X2TS U80 ( .A(n154), .B(in1[26]), .Y(n194) );
NAND2X2TS U81 ( .A(n129), .B(in1[22]), .Y(n215) );
NAND2X2TS U82 ( .A(n112), .B(in1[21]), .Y(n222) );
NAND2X4TS U83 ( .A(n130), .B(in1[23]), .Y(n211) );
MX2X1TS U84 ( .A(in2[29]), .B(n141), .S0(n152), .Y(n158) );
CLKMX2X4TS U85 ( .A(in2[21]), .B(n108), .S0(n152), .Y(n112) );
NOR2X6TS U86 ( .A(n130), .B(in1[23]), .Y(n124) );
OR2X4TS U87 ( .A(n154), .B(in1[26]), .Y(n41) );
XNOR2X2TS U88 ( .A(n120), .B(in2[20]), .Y(n109) );
XNOR2X1TS U89 ( .A(n100), .B(in2[18]), .Y(n97) );
XNOR2X1TS U90 ( .A(n125), .B(in2[25]), .Y(n126) );
MX2X2TS U91 ( .A(in2[17]), .B(n93), .S0(add_sub), .Y(n94) );
NOR2X2TS U92 ( .A(n54), .B(in2[24]), .Y(n125) );
NOR2X2TS U93 ( .A(n54), .B(n142), .Y(n143) );
BUFX3TS U94 ( .A(add_sub), .Y(n16) );
CLKINVX1TS U95 ( .A(n120), .Y(n116) );
INVX2TS U96 ( .A(n106), .Y(n91) );
NAND2X1TS U97 ( .A(n145), .B(n149), .Y(n142) );
BUFX8TS U98 ( .A(n88), .Y(n106) );
NOR2X2TS U99 ( .A(in2[25]), .B(in2[24]), .Y(n145) );
AND2X2TS U100 ( .A(n96), .B(n52), .Y(n105) );
NOR2X1TS U101 ( .A(in2[22]), .B(in2[23]), .Y(n53) );
NOR2X2TS U102 ( .A(in2[21]), .B(in2[20]), .Y(n121) );
NOR2X2TS U103 ( .A(in2[17]), .B(in2[16]), .Y(n96) );
BUFX6TS U104 ( .A(add_sub), .Y(n152) );
BUFX8TS U105 ( .A(add_sub), .Y(n294) );
NOR2X6TS U106 ( .A(in2[5]), .B(in2[4]), .Y(n18) );
NOR2X6TS U107 ( .A(in2[6]), .B(in2[7]), .Y(n19) );
INVX12TS U108 ( .A(in2[8]), .Y(n258) );
INVX12TS U109 ( .A(in2[9]), .Y(n49) );
NOR2X1TS U110 ( .A(in2[19]), .B(in2[18]), .Y(n52) );
NOR2X6TS U111 ( .A(in2[3]), .B(in2[2]), .Y(n17) );
XNOR2X1TS U112 ( .A(n107), .B(in2[21]), .Y(n108) );
NAND2X1TS U113 ( .A(n273), .B(n272), .Y(n276) );
CLKMX2X2TS U114 ( .A(in2[19]), .B(n102), .S0(add_sub), .Y(n103) );
INVX2TS U115 ( .A(n211), .Y(n131) );
NAND2X4TS U116 ( .A(n69), .B(in1[12]), .Y(n255) );
NAND2X1TS U117 ( .A(n111), .B(in1[20]), .Y(n225) );
OR2X2TS U118 ( .A(n134), .B(in1[25]), .Y(n44) );
NAND2X1TS U119 ( .A(n158), .B(in1[29]), .Y(n181) );
OAI21X2TS U120 ( .A0(n218), .A1(n201), .B0(n200), .Y(n204) );
AO21X4TS U121 ( .A0(n196), .A1(n139), .B0(n138), .Y(n14) );
AND2X4TS U122 ( .A(n139), .B(n23), .Y(n22) );
NAND2X4TS U123 ( .A(n42), .B(n180), .Y(n161) );
MX2X2TS U124 ( .A(in2[31]), .B(n56), .S0(n152), .Y(n163) );
NOR2X6TS U125 ( .A(n157), .B(in1[28]), .Y(n170) );
INVX2TS U126 ( .A(n207), .Y(n198) );
NAND2X2TS U127 ( .A(n134), .B(in1[25]), .Y(n202) );
MX2X4TS U128 ( .A(in2[28]), .B(n153), .S0(n152), .Y(n157) );
OAI21X4TS U129 ( .A0(n205), .A1(n137), .B0(n136), .Y(n138) );
INVX2TS U130 ( .A(n206), .Y(n197) );
NAND2X2TS U131 ( .A(n188), .B(n187), .Y(n189) );
NAND2X2TS U132 ( .A(n191), .B(n190), .Y(n192) );
AOI21X2TS U133 ( .A0(n40), .A1(n221), .B0(n113), .Y(n114) );
NAND2X4TS U134 ( .A(n43), .B(n41), .Y(n166) );
NOR2X4TS U135 ( .A(n163), .B(in1[31]), .Y(n186) );
NAND2X2TS U136 ( .A(n163), .B(in1[31]), .Y(n187) );
OR2X4TS U137 ( .A(n94), .B(in1[17]), .Y(n47) );
OR2X4TS U138 ( .A(n158), .B(in1[29]), .Y(n42) );
XNOR2X1TS U139 ( .A(n140), .B(in2[29]), .Y(n141) );
NOR2X4TS U140 ( .A(n91), .B(in2[16]), .Y(n92) );
NOR2X2TS U141 ( .A(n120), .B(in2[20]), .Y(n107) );
NOR2X4TS U142 ( .A(in2[11]), .B(in2[10]), .Y(n50) );
XOR2X1TS U143 ( .A(n224), .B(n223), .Y(res[21]) );
OAI21X1TS U144 ( .A0(n25), .A1(n32), .B0(in1[16]), .Y(n239) );
OR2X2TS U145 ( .A(n25), .B(n33), .Y(n15) );
AOI21X2TS U146 ( .A0(n44), .A1(n198), .B0(n135), .Y(n136) );
OR2X4TS U147 ( .A(n36), .B(n26), .Y(n31) );
NAND2X2TS U148 ( .A(n99), .B(in1[18]), .Y(n232) );
MX2X2TS U149 ( .A(in2[25]), .B(n126), .S0(n152), .Y(n134) );
MX2X2TS U150 ( .A(in2[27]), .B(n144), .S0(n152), .Y(n155) );
XNOR2X2TS U151 ( .A(n147), .B(in2[26]), .Y(n148) );
XNOR2X2TS U152 ( .A(n92), .B(in2[17]), .Y(n93) );
NAND2X2TS U153 ( .A(n116), .B(n121), .Y(n117) );
XNOR2X2TS U154 ( .A(n143), .B(in2[27]), .Y(n144) );
NOR2X2TS U155 ( .A(n100), .B(in2[18]), .Y(n101) );
NAND2BXLTS U156 ( .AN(in1[7]), .B(n283), .Y(res[7]) );
NAND2BXLTS U157 ( .AN(in1[6]), .B(n278), .Y(res[6]) );
MX2X2TS U158 ( .A(in2[15]), .B(n86), .S0(n152), .Y(n87) );
NAND2BXLTS U159 ( .AN(in1[11]), .B(n287), .Y(res[11]) );
NAND2BXLTS U160 ( .AN(in1[9]), .B(n296), .Y(res[9]) );
NAND2BXLTS U161 ( .AN(in1[10]), .B(n291), .Y(res[10]) );
NAND2BXLTS U162 ( .AN(in1[5]), .B(n275), .Y(res[5]) );
NAND2BXLTS U163 ( .AN(in1[4]), .B(n271), .Y(res[4]) );
NAND2BXLTS U164 ( .AN(in1[8]), .B(n260), .Y(res[8]) );
NAND2BXLTS U165 ( .AN(in1[3]), .B(n268), .Y(res[3]) );
INVX4TS U166 ( .A(n61), .Y(n68) );
NAND2BXLTS U167 ( .AN(in1[1]), .B(n262), .Y(res[1]) );
NAND2BXLTS U168 ( .AN(in1[2]), .B(n264), .Y(res[2]) );
OR2X2TS U169 ( .A(n142), .B(in2[27]), .Y(n150) );
OR2X1TS U170 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NOR2X6TS U171 ( .A(n77), .B(in1[13]), .Y(n250) );
BUFX12TS U172 ( .A(n59), .Y(n84) );
AND2X6TS U173 ( .A(n64), .B(n292), .Y(n67) );
BUFX4TS U174 ( .A(n63), .Y(n292) );
OR2X2TS U175 ( .A(n111), .B(in1[20]), .Y(n45) );
NAND2X8TS U176 ( .A(n258), .B(n49), .Y(n288) );
NAND2X4TS U177 ( .A(n84), .B(n71), .Y(n73) );
NAND2X2TS U178 ( .A(n133), .B(in1[24]), .Y(n207) );
OR2X4TS U179 ( .A(n112), .B(in1[21]), .Y(n40) );
NOR2X4TS U180 ( .A(in2[13]), .B(in2[12]), .Y(n83) );
NAND3X8TS U181 ( .A(n31), .B(n29), .C(n28), .Y(n237) );
OR2X8TS U182 ( .A(n80), .B(in1[14]), .Y(n39) );
NOR2X6TS U183 ( .A(n242), .B(n246), .Y(n35) );
NAND2X4TS U184 ( .A(in2[11]), .B(n294), .Y(n62) );
AOI21X4TS U185 ( .A0(n43), .A1(n175), .B0(n156), .Y(n167) );
NAND2X2TS U186 ( .A(n155), .B(in1[27]), .Y(n176) );
XNOR2X1TS U187 ( .A(n151), .B(in2[28]), .Y(n153) );
XNOR2X2TS U188 ( .A(n117), .B(in2[22]), .Y(n118) );
NAND2X8TS U189 ( .A(n59), .B(n83), .Y(n78) );
XNOR2X1TS U190 ( .A(n78), .B(in2[14]), .Y(n79) );
AOI21X2TS U191 ( .A0(n227), .A1(n45), .B0(n221), .Y(n224) );
XOR2X4TS U192 ( .A(n85), .B(in2[15]), .Y(n86) );
NAND3X4TS U193 ( .A(n84), .B(n83), .C(n82), .Y(n85) );
NAND2X4TS U194 ( .A(n106), .B(n96), .Y(n100) );
NAND4X4TS U195 ( .A(n88), .B(n105), .C(n121), .D(n53), .Y(n54) );
NOR3X4TS U196 ( .A(n54), .B(in2[28]), .C(n150), .Y(n140) );
XNOR2X2TS U197 ( .A(n204), .B(n203), .Y(res[25]) );
NAND2X4TS U198 ( .A(n243), .B(n34), .Y(n33) );
NOR3X8TS U199 ( .A(n78), .B(in2[15]), .C(in2[14]), .Y(n88) );
AOI21X4TS U200 ( .A0(n132), .A1(n212), .B0(n131), .Y(n205) );
MXI2X4TS U201 ( .A(n119), .B(n118), .S0(n16), .Y(n129) );
NAND2X4TS U202 ( .A(n44), .B(n38), .Y(n137) );
XOR2X1TS U203 ( .A(n24), .B(n189), .Y(res[31]) );
MX2X4TS U204 ( .A(in2[23]), .B(n123), .S0(n152), .Y(n130) );
XNOR2X2TS U205 ( .A(n122), .B(in2[23]), .Y(n123) );
NOR2X4TS U206 ( .A(n206), .B(n137), .Y(n139) );
INVX2TS U207 ( .A(in2[12]), .Y(n71) );
CLKINVX6TS U208 ( .A(n255), .Y(n70) );
NAND2X4TS U209 ( .A(n77), .B(in1[13]), .Y(n251) );
NAND2X4TS U210 ( .A(n94), .B(in1[17]), .Y(n236) );
NAND2X4TS U211 ( .A(n32), .B(in1[16]), .Y(n28) );
INVX2TS U212 ( .A(n152), .Y(n75) );
CLKBUFX2TS U213 ( .A(n35), .Y(n25) );
INVX2TS U214 ( .A(n243), .Y(n32) );
NAND2X2TS U215 ( .A(n146), .B(n145), .Y(n147) );
INVX2TS U216 ( .A(n176), .Y(n156) );
INVX2TS U217 ( .A(in2[4]), .Y(n272) );
INVX2TS U218 ( .A(in2[6]), .Y(n279) );
NAND2X4TS U219 ( .A(n87), .B(in1[15]), .Y(n243) );
INVX2TS U220 ( .A(n248), .Y(n81) );
NOR2X2TS U221 ( .A(n87), .B(in1[15]), .Y(n242) );
INVX2TS U222 ( .A(n37), .Y(n27) );
NOR2BX1TS U223 ( .AN(n90), .B(add_sub), .Y(n37) );
INVX2TS U224 ( .A(n236), .Y(n95) );
NAND2X2TS U225 ( .A(n103), .B(in1[19]), .Y(n228) );
OR2X2TS U226 ( .A(n103), .B(in1[19]), .Y(n46) );
OR2X4TS U227 ( .A(n155), .B(in1[27]), .Y(n43) );
INVX2TS U228 ( .A(n167), .Y(n168) );
NOR2X6TS U229 ( .A(n166), .B(n170), .Y(n180) );
OAI21X1TS U230 ( .A0(in2[11]), .A1(add_sub), .B0(in1[11]), .Y(n65) );
NAND2BX2TS U231 ( .AN(n62), .B(n284), .Y(n61) );
INVX2TS U232 ( .A(in2[13]), .Y(n72) );
INVX2TS U233 ( .A(in2[16]), .Y(n90) );
NAND2X4TS U234 ( .A(n36), .B(n34), .Y(n30) );
INVX2TS U235 ( .A(n33), .Y(n26) );
INVX2TS U236 ( .A(in2[18]), .Y(n98) );
NOR3BX1TS U237 ( .AN(n121), .B(n120), .C(in2[22]), .Y(n122) );
INVX2TS U238 ( .A(n161), .Y(n23) );
INVX2TS U239 ( .A(n181), .Y(n159) );
NAND2X1TS U240 ( .A(n40), .B(n45), .Y(n115) );
INVX2TS U241 ( .A(n222), .Y(n113) );
INVX2TS U242 ( .A(in2[2]), .Y(n265) );
INVX2TS U243 ( .A(n225), .Y(n221) );
CLKBUFX2TS U244 ( .A(n219), .Y(n220) );
INVX2TS U245 ( .A(n210), .Y(n216) );
NOR2X2TS U246 ( .A(n129), .B(in1[22]), .Y(n210) );
INVX2TS U247 ( .A(n215), .Y(n132) );
AOI21X1TS U248 ( .A0(n199), .A1(n38), .B0(n198), .Y(n200) );
INVX2TS U249 ( .A(n205), .Y(n199) );
XNOR2X1TS U250 ( .A(n292), .B(n258), .Y(n259) );
NOR2XLTS U251 ( .A(n292), .B(in2[8]), .Y(n293) );
NOR2XLTS U252 ( .A(n292), .B(n288), .Y(n289) );
NOR2XLTS U253 ( .A(n292), .B(n284), .Y(n285) );
NAND2X1TS U254 ( .A(n48), .B(n255), .Y(n256) );
NAND2X1TS U255 ( .A(n252), .B(n251), .Y(n254) );
INVX2TS U256 ( .A(n250), .Y(n252) );
NAND2X1TS U257 ( .A(n39), .B(n248), .Y(n249) );
NAND2X1TS U258 ( .A(n244), .B(n243), .Y(n245) );
INVX2TS U259 ( .A(n242), .Y(n244) );
INVX2TS U260 ( .A(n36), .Y(n240) );
NAND2X1TS U261 ( .A(n47), .B(n236), .Y(n238) );
XOR2XLTS U262 ( .A(n235), .B(n234), .Y(res[18]) );
NAND2X1TS U263 ( .A(n233), .B(n232), .Y(n235) );
INVX2TS U264 ( .A(n231), .Y(n233) );
NAND2X1TS U265 ( .A(n46), .B(n228), .Y(n229) );
XNOR2X1TS U266 ( .A(n227), .B(n226), .Y(res[20]) );
NAND2X1TS U267 ( .A(n45), .B(n225), .Y(n226) );
XOR2X1TS U268 ( .A(n218), .B(n217), .Y(res[22]) );
XNOR2X1TS U269 ( .A(n214), .B(n213), .Y(res[23]) );
NAND2X1TS U270 ( .A(n212), .B(n211), .Y(n213) );
OAI21X2TS U271 ( .A0(n218), .A1(n210), .B0(n215), .Y(n214) );
XNOR2X1TS U272 ( .A(n209), .B(n208), .Y(res[24]) );
OAI21X2TS U273 ( .A0(n218), .A1(n206), .B0(n205), .Y(n209) );
NAND2X1TS U274 ( .A(n197), .B(n38), .Y(n201) );
XNOR2X1TS U275 ( .A(n14), .B(n195), .Y(res[26]) );
INVX2TS U276 ( .A(n170), .Y(n172) );
XNOR2X1TS U277 ( .A(n193), .B(n192), .Y(res[30]) );
INVX2TS U278 ( .A(n186), .Y(n188) );
INVX2TS U279 ( .A(in1[16]), .Y(n34) );
NOR2X2TS U280 ( .A(n99), .B(in1[18]), .Y(n231) );
INVX2TS U281 ( .A(n190), .Y(n185) );
NAND4X8TS U282 ( .A(n266), .B(n19), .C(n18), .D(n17), .Y(n63) );
NOR2X8TS U283 ( .A(in2[0]), .B(in2[1]), .Y(n266) );
NAND3X8TS U284 ( .A(n21), .B(n160), .C(n20), .Y(n193) );
NAND2BX4TS U285 ( .AN(n161), .B(n138), .Y(n20) );
AOI21X4TS U286 ( .A0(n193), .A1(n191), .B0(n185), .Y(n24) );
OAI2BB1X4TS U287 ( .A0N(n16), .A1N(n89), .B0(n27), .Y(n36) );
NAND2X8TS U288 ( .A(n35), .B(n30), .Y(n29) );
AOI21X4TS U289 ( .A0(n237), .A1(n47), .B0(n95), .Y(n234) );
XOR2XLTS U290 ( .A(n254), .B(n253), .Y(res[13]) );
XNOR2X1TS U291 ( .A(n230), .B(n229), .Y(res[19]) );
NAND2X8TS U292 ( .A(n106), .B(n105), .Y(n120) );
XOR2XLTS U293 ( .A(n246), .B(n245), .Y(res[15]) );
OR2X8TS U294 ( .A(n69), .B(in1[12]), .Y(n48) );
NAND2X1TS U295 ( .A(n75), .B(in2[13]), .Y(n74) );
INVX2TS U296 ( .A(n228), .Y(n104) );
INVX2TS U297 ( .A(n166), .Y(n169) );
NAND2BX4TS U298 ( .AN(n288), .B(n50), .Y(n51) );
NOR2X8TS U299 ( .A(n63), .B(n51), .Y(n59) );
INVX2TS U300 ( .A(in2[26]), .Y(n149) );
XNOR2X1TS U301 ( .A(n55), .B(in2[31]), .Y(n56) );
XOR2X1TS U302 ( .A(n57), .B(in2[30]), .Y(n58) );
XOR2X4TS U303 ( .A(n84), .B(in2[12]), .Y(n60) );
MXI2X4TS U304 ( .A(n71), .B(n60), .S0(add_sub), .Y(n257) );
OR2X2TS U305 ( .A(n288), .B(in2[10]), .Y(n284) );
INVX2TS U306 ( .A(n62), .Y(n64) );
OR2X8TS U307 ( .A(n84), .B(n65), .Y(n66) );
NOR3X8TS U308 ( .A(n68), .B(n67), .C(n66), .Y(n69) );
AOI21X4TS U309 ( .A0(n257), .A1(n48), .B0(n70), .Y(n253) );
XOR2X4TS U310 ( .A(n73), .B(n72), .Y(n76) );
OAI21X4TS U311 ( .A0(n76), .A1(n75), .B0(n74), .Y(n77) );
OAI21X4TS U312 ( .A0(n253), .A1(n250), .B0(n251), .Y(n247) );
INVX2TS U313 ( .A(in2[14]), .Y(n82) );
MXI2X4TS U314 ( .A(n82), .B(n79), .S0(add_sub), .Y(n80) );
NAND2X6TS U315 ( .A(n80), .B(in1[14]), .Y(n248) );
AOI21X4TS U316 ( .A0(n247), .A1(n39), .B0(n81), .Y(n246) );
XOR2X1TS U317 ( .A(n106), .B(in2[16]), .Y(n89) );
MXI2X2TS U318 ( .A(n98), .B(n97), .S0(add_sub), .Y(n99) );
OAI21X4TS U319 ( .A0(n234), .A1(n231), .B0(n232), .Y(n230) );
XNOR2X1TS U320 ( .A(n101), .B(in2[19]), .Y(n102) );
AOI21X4TS U321 ( .A0(n230), .A1(n46), .B0(n104), .Y(n219) );
INVX2TS U322 ( .A(in2[20]), .Y(n110) );
MXI2X2TS U323 ( .A(n110), .B(n109), .S0(n16), .Y(n111) );
OAI21X4TS U324 ( .A0(n219), .A1(n115), .B0(n114), .Y(n196) );
INVX2TS U325 ( .A(in2[22]), .Y(n119) );
INVX2TS U326 ( .A(in2[24]), .Y(n128) );
XNOR2X1TS U327 ( .A(n54), .B(in2[24]), .Y(n127) );
MXI2X2TS U328 ( .A(n128), .B(n127), .S0(n16), .Y(n133) );
INVX2TS U329 ( .A(n54), .Y(n146) );
MXI2X4TS U330 ( .A(n149), .B(n148), .S0(n16), .Y(n154) );
NOR2X1TS U331 ( .A(n54), .B(n150), .Y(n151) );
OAI21X4TS U332 ( .A0(n167), .A1(n170), .B0(n171), .Y(n179) );
AOI21X4TS U333 ( .A0(n179), .A1(n42), .B0(n159), .Y(n160) );
AOI21X4TS U334 ( .A0(n14), .A1(n169), .B0(n168), .Y(n174) );
AOI21X4TS U335 ( .A0(n14), .A1(n41), .B0(n175), .Y(n178) );
AOI21X4TS U336 ( .A0(n14), .A1(n180), .B0(n179), .Y(n183) );
XNOR2X1TS U337 ( .A(n238), .B(n237), .Y(res[17]) );
XNOR2X1TS U338 ( .A(n241), .B(n240), .Y(res[16]) );
XNOR2X1TS U339 ( .A(n247), .B(n249), .Y(res[14]) );
XNOR2X1TS U340 ( .A(n257), .B(n256), .Y(res[12]) );
MXI2X1TS U341 ( .A(in2[8]), .B(n259), .S0(n294), .Y(n260) );
XOR2X1TS U342 ( .A(in2[0]), .B(in2[1]), .Y(n261) );
MXI2X1TS U343 ( .A(in2[1]), .B(n261), .S0(n16), .Y(n262) );
XNOR2X1TS U344 ( .A(n266), .B(in2[2]), .Y(n263) );
MXI2X1TS U345 ( .A(in2[2]), .B(n263), .S0(n294), .Y(n264) );
NAND2X1TS U346 ( .A(n266), .B(n265), .Y(n269) );
XOR2X1TS U347 ( .A(n269), .B(in2[3]), .Y(n267) );
MXI2X1TS U348 ( .A(in2[3]), .B(n267), .S0(n294), .Y(n268) );
XNOR2X1TS U349 ( .A(n273), .B(in2[4]), .Y(n270) );
MXI2X1TS U350 ( .A(in2[4]), .B(n270), .S0(n294), .Y(n271) );
XOR2X1TS U351 ( .A(n276), .B(in2[5]), .Y(n274) );
MXI2X1TS U352 ( .A(in2[5]), .B(n274), .S0(n294), .Y(n275) );
XNOR2X1TS U353 ( .A(n280), .B(in2[6]), .Y(n277) );
MXI2X1TS U354 ( .A(in2[6]), .B(n277), .S0(n294), .Y(n278) );
NAND2X1TS U355 ( .A(n280), .B(n279), .Y(n281) );
XOR2X1TS U356 ( .A(n281), .B(in2[7]), .Y(n282) );
MXI2X1TS U357 ( .A(in2[7]), .B(n282), .S0(n294), .Y(n283) );
XNOR2X1TS U358 ( .A(n285), .B(in2[11]), .Y(n286) );
MXI2X1TS U359 ( .A(in2[11]), .B(n286), .S0(n16), .Y(n287) );
XNOR2X1TS U360 ( .A(n289), .B(in2[10]), .Y(n290) );
MXI2X1TS U361 ( .A(in2[10]), .B(n290), .S0(n294), .Y(n291) );
XNOR2X1TS U362 ( .A(n293), .B(in2[9]), .Y(n295) );
MXI2X1TS U363 ( .A(in2[9]), .B(n295), .S0(n294), .Y(n296) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_LOALPL12_syn.sdf");
endmodule
|
//-----------------------------------------------------------------------------
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_rate.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_rate.v
// Description : PIPE Rate Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Rate Module --------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_pipe_rate #
(
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter TXDATA_WAIT_MAX = 4'd15 // TXDATA wait max
)
(
//---------- Input -------------------------------------
input RATE_CLK,
input RATE_RST_N,
input RATE_RST_IDLE,
input RATE_ACTIVE_LANE,
input [ 1:0] RATE_RATE_IN,
input RATE_CPLLLOCK,
input RATE_QPLLLOCK,
input RATE_MMCM_LOCK,
input RATE_DRP_DONE,
input RATE_RXPMARESETDONE,
input RATE_TXRESETDONE,
input RATE_RXRESETDONE,
input RATE_TXRATEDONE,
input RATE_RXRATEDONE,
input RATE_PHYSTATUS,
input RATE_RESETOVRD_DONE,
input RATE_TXSYNC_DONE,
input RATE_RXSYNC_DONE,
//---------- Output ------------------------------------
output RATE_CPLLPD,
output RATE_QPLLPD,
output RATE_CPLLRESET,
output RATE_QPLLRESET,
output RATE_TXPMARESET,
output RATE_RXPMARESET,
output RATE_DRP_START,
output [ 1:0] RATE_SYSCLKSEL,
output RATE_PCLK_SEL,
output RATE_GEN3,
output RATE_DRP_X16X20_MODE,
output RATE_DRP_X16,
output [ 2:0] RATE_RATE_OUT,
output RATE_RESETOVRD_START,
output RATE_TXSYNC_START,
output RATE_DONE,
output RATE_RXSYNC_START,
output RATE_RXSYNC,
output RATE_IDLE,
output [ 4:0] RATE_FSM
);
//---------- Input FF or Buffer ------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rst_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_in_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxratedone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg resetovrd_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_done_reg2;
//---------- Internal Signals --------------------------
wire pll_lock;
wire [ 2:0] rate;
reg [ 3:0] txdata_wait_cnt = 4'd0;
reg txratedone = 1'd0;
reg rxratedone = 1'd0;
reg phystatus = 1'd0;
reg ratedone = 1'd0;
reg gen3_exit = 1'd0;
//---------- Output FF or Buffer -----------------------
reg cpllpd = 1'd0;
reg qpllpd = 1'd0;
reg cpllreset = 1'd0;
reg qpllreset = 1'd0;
reg txpmareset = 1'd0;
reg rxpmareset = 1'd0;
reg [ 1:0] sysclksel = (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
reg gen3 = 1'd0;
reg pclk_sel = 1'd0;
reg [ 2:0] rate_out = 3'd0;
reg drp_start = 1'd0;
reg drp_x16x20_mode = 1'd0;
reg drp_x16 = 1'd0;
reg [4:0] fsm = 0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_PLL_PU = 1; // Gen 3 only
localparam FSM_PLL_PURESET = 2; // Gen 3 only
localparam FSM_PLL_LOCK = 3; // Gen 3 or reset only
localparam FSM_DRP_X16_GEN3_START = 4;
localparam FSM_DRP_X16_GEN3_DONE = 5;
localparam FSM_PMARESET_HOLD = 6; // Gen 3 or reset only
localparam FSM_PLL_SEL = 7; // Gen 3 or reset only
localparam FSM_MMCM_LOCK = 8; // Gen 3 or reset only
localparam FSM_DRP_START = 9; // Gen 3 or reset only
localparam FSM_DRP_DONE = 10; // Gen 3 or reset only
localparam FSM_PMARESET_RELEASE = 11; // Gen 3 only
localparam FSM_PMARESET_DONE = 12; // Gen 3 only
localparam FSM_TXDATA_WAIT = 13;
localparam FSM_PCLK_SEL = 14;
localparam FSM_DRP_X16_START = 15;
localparam FSM_DRP_X16_DONE = 16;
localparam FSM_RATE_SEL = 17;
localparam FSM_RXPMARESETDONE = 18;
localparam FSM_DRP_X20_START = 19;
localparam FSM_DRP_X20_DONE = 20;
localparam FSM_RATE_DONE = 21;
localparam FSM_RESETOVRD_START = 22; // PCIe use mode 1.0 only
localparam FSM_RESETOVRD_DONE = 23; // PCIe use mode 1.0 only
localparam FSM_PLL_PDRESET = 24;
localparam FSM_PLL_PD = 25;
localparam FSM_TXSYNC_START = 26;
localparam FSM_TXSYNC_DONE = 27;
localparam FSM_DONE = 28; // Must sync value to pipe_user.v
localparam FSM_RXSYNC_START = 29; // Gen 3 only
localparam FSM_RXSYNC_DONE = 30; // Gen 3 only
//---------- Input FF ----------------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= 1'd0;
rate_in_reg1 <= 2'd0;
cplllock_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
drp_done_reg1 <= 1'd0;
rxpmaresetdone_reg1 <= 1'd0;
txresetdone_reg1 <= 1'd0;
rxresetdone_reg1 <= 1'd0;
txratedone_reg1 <= 1'd0;
rxratedone_reg1 <= 1'd0;
phystatus_reg1 <= 1'd0;
resetovrd_done_reg1 <= 1'd0;
txsync_done_reg1 <= 1'd0;
rxsync_done_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= 1'd0;
rate_in_reg2 <= 2'd0;
cplllock_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
drp_done_reg2 <= 1'd0;
rxpmaresetdone_reg2 <= 1'd0;
txresetdone_reg2 <= 1'd0;
rxresetdone_reg2 <= 1'd0;
txratedone_reg2 <= 1'd0;
rxratedone_reg2 <= 1'd0;
phystatus_reg2 <= 1'd0;
resetovrd_done_reg2 <= 1'd0;
txsync_done_reg2 <= 1'd0;
rxsync_done_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
rst_idle_reg1 <= RATE_RST_IDLE;
rate_in_reg1 <= RATE_RATE_IN;
cplllock_reg1 <= RATE_CPLLLOCK;
qplllock_reg1 <= RATE_QPLLLOCK;
mmcm_lock_reg1 <= RATE_MMCM_LOCK;
drp_done_reg1 <= RATE_DRP_DONE;
rxpmaresetdone_reg1 <= RATE_RXPMARESETDONE;
txresetdone_reg1 <= RATE_TXRESETDONE;
rxresetdone_reg1 <= RATE_RXRESETDONE;
txratedone_reg1 <= RATE_TXRATEDONE;
rxratedone_reg1 <= RATE_RXRATEDONE;
phystatus_reg1 <= RATE_PHYSTATUS;
resetovrd_done_reg1 <= RATE_RESETOVRD_DONE;
txsync_done_reg1 <= RATE_TXSYNC_DONE;
rxsync_done_reg1 <= RATE_RXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
rst_idle_reg2 <= rst_idle_reg1;
rate_in_reg2 <= rate_in_reg1;
cplllock_reg2 <= cplllock_reg1;
qplllock_reg2 <= qplllock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
txresetdone_reg2 <= txresetdone_reg1;
rxresetdone_reg2 <= rxresetdone_reg1;
txratedone_reg2 <= txratedone_reg1;
rxratedone_reg2 <= rxratedone_reg1;
phystatus_reg2 <= phystatus_reg1;
resetovrd_done_reg2 <= resetovrd_done_reg1;
txsync_done_reg2 <= txsync_done_reg1;
rxsync_done_reg2 <= rxsync_done_reg1;
end
end
//---------- Select CPLL or QPLL Lock ------------------------------------------
// Gen1 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen2 : Wait for QPLL lock if QPLL is used for Gen1/Gen2, else wait for CPLL lock
// Gen3 : Wait for QPLL lock
//------------------------------------------------------------------------------
assign pll_lock = (rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL") ? qplllock_reg2 : cplllock_reg2;
//---------- Select Rate -------------------------------------------------------
// Gen1 : Div 4 using [TX/RX]OUT_DIV = 4 if QPLL is used for Gen1/Gen2, else div 2 using [TX/RX]OUT_DIV = 2
// Gen2 : Div 2 using [TX/RX]RATE = 3'd2 if QPLL is used for Gen1/Gen2, else div 1 using [TX/RX]RATE = 3'd1
// Gen3 : Div 1 using [TX/RX]OUT_DIV = 1
//------------------------------------------------------------------------------
assign rate = (rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "QPLL") ? 3'd2 :
(rate_in_reg2 == 2'd1) && (PCIE_PLL_SEL == "CPLL") ? 3'd1 : 3'd0;
//---------- TXDATA Wait Counter -----------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
txdata_wait_cnt <= 4'd0;
else
//---------- Increment Wait Counter ----------------
if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt < TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt + 4'd1;
//---------- Hold Wait Counter ---------------------
else if ((fsm == FSM_TXDATA_WAIT) && (txdata_wait_cnt == TXDATA_WAIT_MAX))
txdata_wait_cnt <= txdata_wait_cnt;
//---------- Reset Wait Counter --------------------
else
txdata_wait_cnt <= 4'd0;
end
//---------- Latch TXRATEDONE, RXRATEDONE, and PHYSTATUS -----------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
else
begin
if (fsm == FSM_RATE_DONE)
begin
//---------- Latch TXRATEDONE ------------------
if (txratedone_reg2)
txratedone <= 1'd1;
else
txratedone <= txratedone;
//---------- Latch RXRATEDONE ------------------
if (rxratedone_reg2)
rxratedone <= 1'd1;
else
rxratedone <= rxratedone;
//---------- Latch PHYSTATUS -------------------
if (phystatus_reg2)
phystatus <= 1'd1;
else
phystatus <= phystatus;
//---------- Latch Rate Done -------------------
if (rxratedone && txratedone && phystatus)
ratedone <= 1'd1;
else
ratedone <= ratedone;
end
else
begin
txratedone <= 1'd0;
rxratedone <= 1'd0;
phystatus <= 1'd0;
ratedone <= 1'd0;
end
end
end
//---------- PIPE Rate FSM -----------------------------------------------------
always @ (posedge RATE_CLK)
begin
if (!RATE_RST_N)
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Detect Rate Change ----------------
if (rate_in_reg2 != rate_in_reg1)
begin
fsm <= ((rate_in_reg2 == 2'd2) || (rate_in_reg1 == 2'd2)) ? FSM_PLL_PU : FSM_TXDATA_WAIT;
gen3_exit <= (rate_in_reg2 == 2'd2);
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
end
//---------- Power-up PLL --------------------------
FSM_PLL_PU :
begin
fsm <= FSM_PLL_PURESET;
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
qpllpd <= 1'd0;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PLL Resets --------------------
FSM_PLL_PURESET :
begin
fsm <= FSM_PLL_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL");
qpllreset <= 1'd0;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for PLL Lock ---------------------
FSM_PLL_LOCK :
begin
fsm <= (pll_lock ? ((!rst_idle_reg2 || (rate_in_reg2 == 2'd1)) ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_START) : FSM_PLL_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_GEN3_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_GEN3_DONE : FSM_DRP_X16_GEN3_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_GEN3_DONE :
begin
fsm <= drp_done_reg2 ? FSM_PMARESET_HOLD : FSM_DRP_X16_GEN3_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Hold both PMA in Reset ----------------
// Gen1 : Release PMA Reset
// Gen2 : Release PMA Reset
// Gen3 : Hold PMA Reset
//--------------------------------------------------
FSM_PMARESET_HOLD :
begin
fsm <= FSM_PLL_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
rxpmareset <= ((rate_in_reg2 == 2'd2) || gen3_exit);
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PLL ----------------------------
// Gen1 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen2 : QPLL if PCIE_PLL_SEL = QPLL, else CPLL
// Gen3 : QPLL
//--------------------------------------------------
FSM_PLL_SEL :
begin
fsm <= FSM_MMCM_LOCK;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= ((rate_in_reg2 == 2'd2) || (PCIE_PLL_SEL == "QPLL")) ? 2'd1 : 2'd0;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Check for MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm <= (mmcm_lock_reg2 && !rxpmaresetdone_reg2 ? FSM_DRP_START : FSM_MMCM_LOCK);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP -----------------------------
FSM_DRP_START:
begin
fsm <= (!drp_done_reg2 ? FSM_DRP_DONE : FSM_DRP_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= (rate_in_reg2 == 2'd2);
rate_out <= (((rate_in_reg2 == 2'd2) || gen3_exit) ? rate : rate_out);
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP Done ---------------------
FSM_DRP_DONE :
begin
fsm <= ((drp_done_reg2 && pll_lock) ? (rst_idle_reg2 ? FSM_PMARESET_RELEASE : FSM_IDLE): FSM_DRP_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Release PMA Resets --------------------
FSM_PMARESET_RELEASE :
begin
fsm <= FSM_PMARESET_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for both TX/RX PMA Reset Dones and PHYSTATUS Deassertion
FSM_PMARESET_DONE :
begin
fsm <= (((rxresetdone_reg2 && txresetdone_reg2 && !phystatus_reg2) || !RATE_ACTIVE_LANE) ? FSM_TXDATA_WAIT : FSM_PMARESET_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TXDATA to TX[P/N] Latency ----
FSM_TXDATA_WAIT :
begin
fsm <= (txdata_wait_cnt == TXDATA_WAIT_MAX) ? FSM_PCLK_SEL : FSM_TXDATA_WAIT;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Select PCLK Frequency -----------------
// Gen1 : PCLK = 125 MHz
// Gen2 : PCLK = 250 MHz
// Gen3 : PCLK = 250 MHz
//--------------------------------------------------
FSM_PCLK_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_DRP_X16_START : FSM_RATE_SEL;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= ((rate_in_reg2 == 2'd1) || (rate_in_reg2 == 2'd2));
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_SEL : FSM_DRP_X16_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd1;
end
//---------- Select Rate ---------------------------
FSM_RATE_SEL :
begin
fsm <= ((PCIE_GT_DEVICE == "GTH") && ((rate_in_reg2 == 2'd1) || ((!gen3_exit) && (rate_in_reg2 == 2'd0)))) ? FSM_RXPMARESETDONE : FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate; // Update [TX/RX]RATE
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE :
begin
fsm <= (!rxpmaresetdone_reg2) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= (!drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd1;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= drp_done_reg2 ? FSM_RATE_DONE : FSM_DRP_X20_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd1;
drp_x16 <= 1'd0;
end
//---------- Wait for Rate Change Done -------------
FSM_RATE_DONE :
begin
if (ratedone || (rate_in_reg2 == 2'd2) || (gen3_exit) || !RATE_ACTIVE_LANE)
if ((PCIE_USE_MODE == "1.0") && (rate_in_reg2 != 2'd2) && (!gen3_exit))
fsm <= FSM_RESETOVRD_START;
else
fsm <= FSM_PLL_PDRESET;
else
fsm <= FSM_RATE_DONE;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Start ------------------
FSM_RESETOVRD_START:
begin
fsm <= (!resetovrd_done_reg2 ? FSM_RESETOVRD_DONE : FSM_RESETOVRD_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Reset Override Done -------------------
FSM_RESETOVRD_DONE :
begin
fsm <= (resetovrd_done_reg2 ? FSM_PLL_PDRESET : FSM_RESETOVRD_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Hold PLL Not Used in Reset ------------
FSM_PLL_PDRESET :
begin
fsm <= FSM_PLL_PD;
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllreset <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Power-Down PLL Not Used ---------------
FSM_PLL_PD :
begin
fsm <= (((rate_in_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? FSM_TXSYNC_START : FSM_DONE);
gen3_exit <= gen3_exit;
cpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd1 : (rate_in_reg2 == 2'd2);
qpllpd <= (PCIE_PLL_SEL == "QPLL") ? 1'd0 : (rate_in_reg2 != 2'd2);
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START:
begin
fsm <= (!txsync_done_reg2 ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE:
begin
fsm <= (txsync_done_reg2 ? FSM_DONE : FSM_TXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Rate Change Done ----------------------
FSM_DONE :
begin
fsm <= (((rate_in_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE") && (PCIE_ASYNC_EN == "TRUE")) ? FSM_RXSYNC_START : FSM_IDLE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Start RX Sync -------------------------
FSM_RXSYNC_START:
begin
fsm <= (!rxsync_done_reg2 ? FSM_RXSYNC_DONE : FSM_RXSYNC_START);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Wait for RX Sync Done -----------------
FSM_RXSYNC_DONE:
begin
fsm <= (rxsync_done_reg2 ? FSM_IDLE : FSM_RXSYNC_DONE);
gen3_exit <= gen3_exit;
cpllpd <= cpllpd;
qpllpd <= qpllpd;
cpllreset <= cpllreset;
qpllreset <= qpllreset;
txpmareset <= txpmareset;
rxpmareset <= rxpmareset;
sysclksel <= sysclksel;
pclk_sel <= pclk_sel;
gen3 <= gen3;
rate_out <= rate_out;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
gen3_exit <= 1'd0;
cpllpd <= 1'd0;
qpllpd <= 1'd0;
cpllreset <= 1'd0;
qpllreset <= 1'd0;
txpmareset <= 1'd0;
rxpmareset <= 1'd0;
sysclksel <= (PCIE_PLL_SEL == "QPLL") ? 2'd1 : 2'd0;
pclk_sel <= 1'd0;
gen3 <= 1'd0;
rate_out <= 3'd0;
drp_start <= 1'd0;
drp_x16x20_mode <= 1'd0;
drp_x16 <= 1'd0;
end
endcase
end
end
//---------- PIPE Rate Output --------------------------------------------------
assign RATE_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RATE_QPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllpd);
assign RATE_CPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllreset);
assign RATE_QPLLRESET = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : qpllreset);
assign RATE_TXPMARESET = txpmareset;
assign RATE_RXPMARESET = rxpmareset;
assign RATE_SYSCLKSEL = sysclksel;
//assign RATE_DRP_START = (fsm == FSM_DRP_START) || (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
assign RATE_DRP_START = drp_start;
//assign RATE_DRP_X16X20_MODE = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) ||
// (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
assign RATE_DRP_X16X20_MODE = drp_x16x20_mode;
//assign RATE_DRP_X16 = (fsm == FSM_DRP_X16_GEN3_START) || (fsm == FSM_DRP_X16_GEN3_DONE) ||
// (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
assign RATE_DRP_X16 = drp_x16;
assign RATE_PCLK_SEL = pclk_sel;
assign RATE_GEN3 = gen3;
assign RATE_RATE_OUT = rate_out;
assign RATE_RESETOVRD_START = (fsm == FSM_RESETOVRD_START);
assign RATE_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RATE_DONE = (fsm == FSM_DONE);
assign RATE_RXSYNC_START = (fsm == FSM_RXSYNC_START);
assign RATE_RXSYNC = ((fsm == FSM_RXSYNC_START) || (fsm == FSM_RXSYNC_DONE));
assign RATE_IDLE = (fsm == FSM_IDLE);
assign RATE_FSM = fsm;
endmodule
|
module axi_master_write_stub(
output M2S_AXI_ACLK,
// Write Transaction
output M2S_AXI_AWVALID,
input M2S_AXI_AWREADY,
output [31:0] M2S_AXI_AWADDR,
output [1:0] M2S_AXI_AWBURST,
output [3:0] M2S_AXI_AWLEN,
output [1:0] M2S_AXI_AWSIZE,
//
output M2S_AXI_WVALID,
input M2S_AXI_WREADY,
output M2S_AXI_WLAST,
output [63:0] M2S_AXI_WDATA,
output [7:0] M2S_AXI_WSTRB,
//
input M2S_AXI_BVALID,
output M2S_AXI_BREADY,
input [1:0] M2S_AXI_BRESP
);
assign M2S_AXI_ACLK = 1'b0;
// Write Transaction
assign M2S_AXI_AWVALID = 1'b0;
assign M2S_AXI_AWADDR = 33'b0;
assign M2S_AXI_AWBURST = 2'b0;
assign M2S_AXI_AWLEN = 4'b0;
assign M2S_AXI_AWSIZE = 2'b0;
assign M2S_AXI_WVALID = 1'b0;
assign M2S_AXI_WLAST = 1'b0;
assign M2S_AXI_WDATA = 64'b0;
assign M2S_AXI_WSTRB = 8'b0;
assign M2S_AXI_BREADY = 1'b0;
endmodule : axi_master_write_stub
/*
axi_master_stub axi_master_XXX_stub (
.M2S_AXI_ACLK(M2S_XXX_AXI_ACLK),
// Write Transaction
.M2S_AXI_AWVALID(M2S_XXX_AXI_AWVALID),
.M2S_AXI_AWREADY(M2S_XXX_AXI_AWREADY),
.M2S_AXI_AWADDR(M2S_XXX_AXI_AWADDR[31:0]),
.M2S_AXI_AWBURST(M2S_XXX_AXI_AWBURST[1:0]),
.M2S_AXI_AWLEN(M2S_XXX_AXI_AWLEN[3:0]),
.M2S_AXI_AWSIZE(M2S_XXX_AXI_AWSIZE[1:0]),
//
.M2S_AXI_WVALID(M2S_XXX_AXI_WVALID),
.M2S_AXI_WREADY(M2S_XXX_AXI_WREADY),
.M2S_AXI_WLAST(M2S_XXX_AXI_WLAST),
.M2S_AXI_WDATA(M2S_XXX_AXI_WDATA[63:0]),
.M2S_AXI_WSTRB(M2S_XXX_AXI_WSTRB[7:0]),
//
.M2S_AXI_BVALID(M2S_XXX_AXI_BVALID),
.M2S_AXI_BREADY(M2S_XXX_AXI_BREADY),
.M2S_AXI_BRESP(M2S_XXX_AXI_BRESP[1:0])
);
*/
|
// megafunction wizard: %ALTDDIO_OUT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTDDIO_OUT
// ============================================================
// File Name: delay.v
// Megafunction Name(s):
// ALTDDIO_OUT
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 263 08/02/2012 SP 2.16 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module delay (
aclr,
datain_h,
datain_l,
outclock,
dataout);
input aclr;
input [0:0] datain_h;
input [0:0] datain_l;
input outclock;
output [0:0] dataout;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
// Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
// Retrieval info: CONSTANT: WIDTH NUMERIC "1"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
// Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
// Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
// Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
// Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
// Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
// Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
// Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.cmp TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL delay.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module host_control(reset,
clock,
emmit_command, //to sd_ctrl
command_complete, //from sd_ctrl
response, //issued by SD
error_interrupt, //whenever there's an error, must be set on high
command_index, //indez for the command
command_index_check_enable, //checks if the command index is the same for the command and the response
command_index_error,
crc_check_enable, //enable checks for response
crc_error, //in case there's a comprobation error (timeout_error=0) or the transmitter bit from the response is 1 (timeout_error=1)
end_bit_error, //when the ending bit of a response is 0
end_bit_check_enable, //when the ending bit of a response is 0
command_complete_interrupt, //register, must be set on high when the command has been properly emmited and an answer received (in case there should be one)
response_type, //lengths and busy status after complete
command_type, //normal, suspend, resume or abort
response_register, //normal response, type 10
CID, //for type 01
card_status_AUTO_CMD52 //for type 11
);
input wire reset,
clock,
command_complete,
command_index,
command_index_check_enable, //checks if the command index is the same for the command and the response
crc_check_enable, //enable checks for response
command_inhibit, //from regs, present_state
command_complete, //from sd_ctrl, interrupt
response, //issued by SD
command_type, //normal, suspend, resume or abort
response_type, //lengths and busy status after complete
output reg command_index_error,
command_complete_interrupt,
emmit_command,
crc_error,
timeout_error, //when 64 clock cycles go through without a response from the SD
command_complete_status, //
end_bit_error, //when the ending bit of a response is 0
response_register, //normal response, type 10
CID, //for type 01
card_status_AUTO_CMD52
reg [2:0] state;
reg verifications_pass;
reg verifications_end;
parameter NO_RESPONSE = 0, LONG_RESPONSE = 1, NORMAL_RESPONSE = 2, AUTO_CMD_52 = 3;
parameter RESET = 0, IDLE = 1, EMMIT_CMD = 2, WAIT_RESPONSE = 3, VERIFICATION = 4, WRITE_REGS = 5;
always @(*) begin
if(reset) begin
state = RESET;
end
end
always @(posedge clock)
case(state)
RESET:
state <= IDLE;
reset <= 0;
IDLE:
if(command_inhibit) begin
state <= EMMIT_CMD;
end
EMMIT_CMD:
command <= 1;
state <= WAIT_RESPONSE;
WAIT_RESPONSE:
if(command_complete) begin
command <= 0;
verifications_passed <= 0;
verifications_end <= 0;
state <= VERIFICATION;
end
VERIFICATION:
case(response_type)
NO_RESPONSE:
state <= IDLE;
command_complete_interrupt <= 1;
NORMAL_RESPONSE || AUTO_CMD52:
if(response[0]==0) begin
if(end_bit_check_enable) begin
verifications_end <= 1;
verifications_passed <= 0;
end
end
if(response[45:40]!=command_index) begin
if(end_bit_check_enable) begin
verifications_end <= 1;
verifications_passed <= 0;
end
end
LONG_RESPONSE:
if(response[0]==0) begin
if(end_bit_check_enable) begin
verifications_end <= 1;
verifications_passed <= 0;
end
end
endcase
if(verifications_end) begin
if(verification_passed) begin
state <= WRITE_REGS;
end else begin
state <= IDLE;
end
end
WRITE_REGS:
case(command_type)
NORMAL_RESPONSE:
response_register <= response;
LONG_RESPONSE:
CID <= response;
AUTO_CMD52:
card_status_AUTO_CMD52 <= response;
endcase
state = IDLE;
endcase
endmodule |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_best_tracks_actual (
ap_clk,
ap_rst,
phi_0_0_V_read,
phi_0_1_V_read,
phi_0_2_V_read,
phi_1_0_V_read,
phi_1_1_V_read,
phi_1_2_V_read,
phi_2_0_V_read,
phi_2_1_V_read,
phi_2_2_V_read,
phi_3_0_V_read,
phi_3_1_V_read,
phi_3_2_V_read,
theta_0_0_V_read,
theta_0_1_V_read,
theta_0_2_V_read,
theta_1_0_V_read,
theta_1_1_V_read,
theta_1_2_V_read,
theta_2_0_V_read,
theta_2_1_V_read,
theta_2_2_V_read,
theta_3_0_V_read,
theta_3_1_V_read,
theta_3_2_V_read,
cpattern_0_0_0_V_read,
cpattern_0_0_1_V_read,
cpattern_0_0_2_V_read,
cpattern_0_0_3_V_read,
cpattern_0_1_0_V_read,
cpattern_0_1_1_V_read,
cpattern_0_1_2_V_read,
cpattern_0_1_3_V_read,
cpattern_0_2_0_V_read,
cpattern_0_2_1_V_read,
cpattern_0_2_2_V_read,
cpattern_0_2_3_V_read,
cpattern_1_0_0_V_read,
cpattern_1_0_1_V_read,
cpattern_1_0_2_V_read,
cpattern_1_0_3_V_read,
cpattern_1_1_0_V_read,
cpattern_1_1_1_V_read,
cpattern_1_1_2_V_read,
cpattern_1_1_3_V_read,
cpattern_1_2_0_V_read,
cpattern_1_2_1_V_read,
cpattern_1_2_2_V_read,
cpattern_1_2_3_V_read,
cpattern_2_0_0_V_read,
cpattern_2_0_1_V_read,
cpattern_2_0_2_V_read,
cpattern_2_0_3_V_read,
cpattern_2_1_0_V_read,
cpattern_2_1_1_V_read,
cpattern_2_1_2_V_read,
cpattern_2_1_3_V_read,
cpattern_2_2_0_V_read,
cpattern_2_2_1_V_read,
cpattern_2_2_2_V_read,
cpattern_2_2_3_V_read,
cpattern_3_0_0_V_read,
cpattern_3_0_1_V_read,
cpattern_3_0_2_V_read,
cpattern_3_0_3_V_read,
cpattern_3_1_0_V_read,
cpattern_3_1_1_V_read,
cpattern_3_1_2_V_read,
cpattern_3_1_3_V_read,
cpattern_3_2_0_V_read,
cpattern_3_2_1_V_read,
cpattern_3_2_2_V_read,
cpattern_3_2_3_V_read,
delta_ph_0_0_0_V_read,
delta_ph_0_0_1_V_read,
delta_ph_0_0_2_V_read,
delta_ph_0_0_3_V_read,
delta_ph_0_0_4_V_read,
delta_ph_0_0_5_V_read,
delta_ph_0_1_0_V_read,
delta_ph_0_1_1_V_read,
delta_ph_0_1_2_V_read,
delta_ph_0_1_3_V_read,
delta_ph_0_1_4_V_read,
delta_ph_0_1_5_V_read,
delta_ph_0_2_0_V_read,
delta_ph_0_2_1_V_read,
delta_ph_0_2_2_V_read,
delta_ph_0_2_3_V_read,
delta_ph_0_2_4_V_read,
delta_ph_0_2_5_V_read,
delta_ph_1_0_0_V_read,
delta_ph_1_0_1_V_read,
delta_ph_1_0_2_V_read,
delta_ph_1_0_3_V_read,
delta_ph_1_0_4_V_read,
delta_ph_1_0_5_V_read,
delta_ph_1_1_0_V_read,
delta_ph_1_1_1_V_read,
delta_ph_1_1_2_V_read,
delta_ph_1_1_3_V_read,
delta_ph_1_1_4_V_read,
delta_ph_1_1_5_V_read,
delta_ph_1_2_0_V_read,
delta_ph_1_2_1_V_read,
delta_ph_1_2_2_V_read,
delta_ph_1_2_3_V_read,
delta_ph_1_2_4_V_read,
delta_ph_1_2_5_V_read,
delta_ph_2_0_0_V_read,
delta_ph_2_0_1_V_read,
delta_ph_2_0_2_V_read,
delta_ph_2_0_3_V_read,
delta_ph_2_0_4_V_read,
delta_ph_2_0_5_V_read,
delta_ph_2_1_0_V_read,
delta_ph_2_1_1_V_read,
delta_ph_2_1_2_V_read,
delta_ph_2_1_3_V_read,
delta_ph_2_1_4_V_read,
delta_ph_2_1_5_V_read,
delta_ph_2_2_0_V_read,
delta_ph_2_2_1_V_read,
delta_ph_2_2_2_V_read,
delta_ph_2_2_3_V_read,
delta_ph_2_2_4_V_read,
delta_ph_2_2_5_V_read,
delta_ph_3_0_0_V_read,
delta_ph_3_0_1_V_read,
delta_ph_3_0_2_V_read,
delta_ph_3_0_3_V_read,
delta_ph_3_0_4_V_read,
delta_ph_3_0_5_V_read,
delta_ph_3_1_0_V_read,
delta_ph_3_1_1_V_read,
delta_ph_3_1_2_V_read,
delta_ph_3_1_3_V_read,
delta_ph_3_1_4_V_read,
delta_ph_3_1_5_V_read,
delta_ph_3_2_0_V_read,
delta_ph_3_2_1_V_read,
delta_ph_3_2_2_V_read,
delta_ph_3_2_3_V_read,
delta_ph_3_2_4_V_read,
delta_ph_3_2_5_V_read,
delta_th_0_0_0_V_read,
delta_th_0_0_1_V_read,
delta_th_0_0_2_V_read,
delta_th_0_0_3_V_read,
delta_th_0_0_4_V_read,
delta_th_0_0_5_V_read,
delta_th_0_1_0_V_read,
delta_th_0_1_1_V_read,
delta_th_0_1_2_V_read,
delta_th_0_1_3_V_read,
delta_th_0_1_4_V_read,
delta_th_0_1_5_V_read,
delta_th_0_2_0_V_read,
delta_th_0_2_1_V_read,
delta_th_0_2_2_V_read,
delta_th_0_2_3_V_read,
delta_th_0_2_4_V_read,
delta_th_0_2_5_V_read,
delta_th_1_0_0_V_read,
delta_th_1_0_1_V_read,
delta_th_1_0_2_V_read,
delta_th_1_0_3_V_read,
delta_th_1_0_4_V_read,
delta_th_1_0_5_V_read,
delta_th_1_1_0_V_read,
delta_th_1_1_1_V_read,
delta_th_1_1_2_V_read,
delta_th_1_1_3_V_read,
delta_th_1_1_4_V_read,
delta_th_1_1_5_V_read,
delta_th_1_2_0_V_read,
delta_th_1_2_1_V_read,
delta_th_1_2_2_V_read,
delta_th_1_2_3_V_read,
delta_th_1_2_4_V_read,
delta_th_1_2_5_V_read,
delta_th_2_0_0_V_read,
delta_th_2_0_1_V_read,
delta_th_2_0_2_V_read,
delta_th_2_0_3_V_read,
delta_th_2_0_4_V_read,
delta_th_2_0_5_V_read,
delta_th_2_1_0_V_read,
delta_th_2_1_1_V_read,
delta_th_2_1_2_V_read,
delta_th_2_1_3_V_read,
delta_th_2_1_4_V_read,
delta_th_2_1_5_V_read,
delta_th_2_2_0_V_read,
delta_th_2_2_1_V_read,
delta_th_2_2_2_V_read,
delta_th_2_2_3_V_read,
delta_th_2_2_4_V_read,
delta_th_2_2_5_V_read,
delta_th_3_0_0_V_read,
delta_th_3_0_1_V_read,
delta_th_3_0_2_V_read,
delta_th_3_0_3_V_read,
delta_th_3_0_4_V_read,
delta_th_3_0_5_V_read,
delta_th_3_1_0_V_read,
delta_th_3_1_1_V_read,
delta_th_3_1_2_V_read,
delta_th_3_1_3_V_read,
delta_th_3_1_4_V_read,
delta_th_3_1_5_V_read,
delta_th_3_2_0_V_read,
delta_th_3_2_1_V_read,
delta_th_3_2_2_V_read,
delta_th_3_2_3_V_read,
delta_th_3_2_4_V_read,
delta_th_3_2_5_V_read,
sign_ph_0_0_V_read,
sign_ph_0_1_V_read,
sign_ph_0_2_V_read,
sign_ph_1_0_V_read,
sign_ph_1_1_V_read,
sign_ph_1_2_V_read,
sign_ph_2_0_V_read,
sign_ph_2_1_V_read,
sign_ph_2_2_V_read,
sign_ph_3_0_V_read,
sign_ph_3_1_V_read,
sign_ph_3_2_V_read,
sign_th_0_0_V_read,
sign_th_0_1_V_read,
sign_th_0_2_V_read,
sign_th_1_0_V_read,
sign_th_1_1_V_read,
sign_th_1_2_V_read,
sign_th_2_0_V_read,
sign_th_2_1_V_read,
sign_th_2_2_V_read,
sign_th_3_0_V_read,
sign_th_3_1_V_read,
sign_th_3_2_V_read,
rank_0_0_V_read,
rank_0_1_V_read,
rank_0_2_V_read,
rank_1_0_V_read,
rank_1_1_V_read,
rank_1_2_V_read,
rank_2_0_V_read,
rank_2_1_V_read,
rank_2_2_V_read,
rank_3_0_V_read,
rank_3_1_V_read,
rank_3_2_V_read,
si_0_0_V_read,
si_0_1_V_read,
si_0_2_V_read,
si_1_0_V_read,
si_1_1_V_read,
si_1_2_V_read,
si_2_0_V_read,
si_2_1_V_read,
si_2_2_V_read,
si_3_0_V_read,
si_3_1_V_read,
si_3_2_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3,
ap_return_4,
ap_return_5,
ap_return_6,
ap_return_7,
ap_return_8,
ap_return_9,
ap_return_10,
ap_return_11,
ap_return_12,
ap_return_13,
ap_return_14,
ap_return_15,
ap_return_16,
ap_return_17,
ap_return_18,
ap_return_19,
ap_return_20,
ap_return_21,
ap_return_22,
ap_return_23,
ap_return_24,
ap_return_25,
ap_return_26,
ap_return_27,
ap_return_28,
ap_return_29,
ap_return_30,
ap_return_31,
ap_return_32,
ap_return_33,
ap_return_34,
ap_return_35,
ap_return_36,
ap_return_37,
ap_return_38,
ap_return_39,
ap_return_40,
ap_return_41,
ap_return_42,
ap_return_43,
ap_return_44,
ap_return_45,
ap_return_46,
ap_return_47,
ap_return_48,
ap_return_49,
ap_return_50,
ap_return_51,
ap_return_52,
ap_return_53,
ap_return_54,
ap_return_55,
ap_return_56,
ap_return_57,
ap_return_58,
ap_return_59,
ap_return_60,
ap_return_61,
ap_return_62,
ap_return_63,
ap_return_64,
ap_return_65,
ap_return_66,
ap_return_67,
ap_return_68,
ap_return_69,
ap_return_70,
ap_return_71,
ap_return_72,
ap_return_73,
ap_return_74,
ap_return_75,
ap_return_76,
ap_return_77,
ap_return_78,
ap_return_79,
ap_return_80,
ap_return_81,
ap_return_82,
ap_return_83,
ap_return_84,
ap_return_85,
ap_return_86,
ap_return_87,
ap_return_88,
ap_return_89,
ap_return_90,
ap_return_91,
ap_return_92,
ap_return_93,
ap_return_94,
ap_return_95,
ap_return_96,
ap_return_97,
ap_return_98,
ap_return_99,
ap_return_100,
ap_return_101,
ap_return_102,
ap_return_103,
ap_return_104,
ap_return_105,
ap_return_106,
ap_return_107,
ap_return_108,
ap_return_109,
ap_return_110
);
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv12_3 = 12'b11;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_9 = 32'b1001;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv32_B = 32'b1011;
parameter ap_const_lv7_0 = 7'b0000000;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv12_2 = 12'b10;
parameter ap_const_lv12_5 = 12'b101;
parameter ap_const_lv12_4 = 12'b100;
parameter ap_const_lv12_9 = 12'b1001;
parameter ap_const_lv12_8 = 12'b1000;
parameter ap_const_lv12_11 = 12'b10001;
parameter ap_const_lv12_10 = 12'b10000;
parameter ap_const_lv12_21 = 12'b100001;
parameter ap_const_lv12_20 = 12'b100000;
parameter ap_const_lv12_41 = 12'b1000001;
parameter ap_const_lv12_40 = 12'b1000000;
parameter ap_const_lv12_81 = 12'b10000001;
parameter ap_const_lv12_80 = 12'b10000000;
parameter ap_const_lv12_101 = 12'b100000001;
parameter ap_const_lv12_100 = 12'b100000000;
parameter ap_const_lv12_201 = 12'b1000000001;
parameter ap_const_lv12_200 = 12'b1000000000;
parameter ap_const_lv12_401 = 12'b10000000001;
parameter ap_const_lv12_400 = 12'b10000000000;
parameter ap_const_lv12_801 = 12'b100000000001;
parameter ap_const_lv12_800 = 12'b100000000000;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv3_1 = 3'b1;
parameter ap_const_lv4_8 = 4'b1000;
parameter ap_const_lv4_1 = 4'b1;
parameter ap_const_lv5_10 = 5'b10000;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv6_20 = 6'b100000;
parameter ap_const_lv6_1 = 6'b1;
parameter ap_const_lv7_40 = 7'b1000000;
parameter ap_const_lv7_1 = 7'b1;
parameter ap_const_lv8_80 = 8'b10000000;
parameter ap_const_lv8_1 = 8'b1;
parameter ap_const_lv9_100 = 9'b100000000;
parameter ap_const_lv9_1 = 9'b1;
parameter ap_const_lv10_200 = 10'b1000000000;
parameter ap_const_lv10_1 = 10'b1;
parameter ap_const_lv11_400 = 11'b10000000000;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv3_2 = 3'b10;
parameter ap_const_lv4_2 = 4'b10;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_const_lv6_2 = 6'b10;
parameter ap_const_lv7_2 = 7'b10;
parameter ap_const_lv8_2 = 8'b10;
parameter ap_const_lv9_2 = 9'b10;
parameter ap_const_lv10_2 = 10'b10;
parameter ap_const_lv11_2 = 11'b10;
parameter ap_const_lv4_4 = 4'b100;
parameter ap_const_lv5_4 = 5'b100;
parameter ap_const_lv6_4 = 6'b100;
parameter ap_const_lv7_4 = 7'b100;
parameter ap_const_lv8_4 = 8'b100;
parameter ap_const_lv9_4 = 9'b100;
parameter ap_const_lv10_4 = 10'b100;
parameter ap_const_lv11_4 = 11'b100;
parameter ap_const_lv5_8 = 5'b1000;
parameter ap_const_lv6_8 = 6'b1000;
parameter ap_const_lv7_8 = 7'b1000;
parameter ap_const_lv8_8 = 8'b1000;
parameter ap_const_lv9_8 = 9'b1000;
parameter ap_const_lv10_8 = 10'b1000;
parameter ap_const_lv11_8 = 11'b1000;
parameter ap_const_lv6_10 = 6'b10000;
parameter ap_const_lv7_10 = 7'b10000;
parameter ap_const_lv8_10 = 8'b10000;
parameter ap_const_lv9_10 = 9'b10000;
parameter ap_const_lv10_10 = 10'b10000;
parameter ap_const_lv11_10 = 11'b10000;
parameter ap_const_lv7_20 = 7'b100000;
parameter ap_const_lv8_20 = 8'b100000;
parameter ap_const_lv9_20 = 9'b100000;
parameter ap_const_lv10_20 = 10'b100000;
parameter ap_const_lv11_20 = 11'b100000;
parameter ap_const_lv8_40 = 8'b1000000;
parameter ap_const_lv9_40 = 9'b1000000;
parameter ap_const_lv10_40 = 10'b1000000;
parameter ap_const_lv11_40 = 11'b1000000;
parameter ap_const_lv9_80 = 9'b10000000;
parameter ap_const_lv10_80 = 10'b10000000;
parameter ap_const_lv11_80 = 11'b10000000;
parameter ap_const_lv10_100 = 10'b100000000;
parameter ap_const_lv11_100 = 11'b100000000;
parameter ap_const_lv11_200 = 11'b1000000000;
parameter ap_const_lv12_FFF = 12'b111111111111;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv4_3 = 4'b11;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv36_1 = 36'b1;
parameter ap_const_lv36_0 = 36'b000000000000000000000000000000000000;
parameter ap_const_lv36_FFF = 36'b111111111111;
parameter ap_const_lv36_FFFFFFFFF = 36'b111111111111111111111111111111111111;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv3_0 = 3'b000;
parameter ap_const_lv4_7 = 4'b111;
parameter ap_const_lv3_7 = 3'b111;
parameter ap_const_lv32_C = 32'b1100;
parameter ap_const_lv32_D = 32'b1101;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_11 = 32'b10001;
parameter ap_const_lv32_12 = 32'b10010;
parameter ap_const_lv32_13 = 32'b10011;
parameter ap_const_lv32_14 = 32'b10100;
parameter ap_const_lv32_15 = 32'b10101;
parameter ap_const_lv32_16 = 32'b10110;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv32_18 = 32'b11000;
parameter ap_const_lv32_19 = 32'b11001;
parameter ap_const_lv32_1A = 32'b11010;
parameter ap_const_lv32_1B = 32'b11011;
parameter ap_const_lv32_1C = 32'b11100;
parameter ap_const_lv32_1D = 32'b11101;
parameter ap_const_lv32_1E = 32'b11110;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_20 = 32'b100000;
parameter ap_const_lv32_21 = 32'b100001;
parameter ap_const_lv32_22 = 32'b100010;
parameter ap_const_lv32_23 = 32'b100011;
input ap_clk;
input ap_rst;
input [11:0] phi_0_0_V_read;
input [11:0] phi_0_1_V_read;
input [11:0] phi_0_2_V_read;
input [11:0] phi_1_0_V_read;
input [11:0] phi_1_1_V_read;
input [11:0] phi_1_2_V_read;
input [11:0] phi_2_0_V_read;
input [11:0] phi_2_1_V_read;
input [11:0] phi_2_2_V_read;
input [11:0] phi_3_0_V_read;
input [11:0] phi_3_1_V_read;
input [11:0] phi_3_2_V_read;
input [6:0] theta_0_0_V_read;
input [6:0] theta_0_1_V_read;
input [6:0] theta_0_2_V_read;
input [6:0] theta_1_0_V_read;
input [6:0] theta_1_1_V_read;
input [6:0] theta_1_2_V_read;
input [6:0] theta_2_0_V_read;
input [6:0] theta_2_1_V_read;
input [6:0] theta_2_2_V_read;
input [6:0] theta_3_0_V_read;
input [6:0] theta_3_1_V_read;
input [6:0] theta_3_2_V_read;
input [3:0] cpattern_0_0_0_V_read;
input [3:0] cpattern_0_0_1_V_read;
input [3:0] cpattern_0_0_2_V_read;
input [3:0] cpattern_0_0_3_V_read;
input [3:0] cpattern_0_1_0_V_read;
input [3:0] cpattern_0_1_1_V_read;
input [3:0] cpattern_0_1_2_V_read;
input [3:0] cpattern_0_1_3_V_read;
input [3:0] cpattern_0_2_0_V_read;
input [3:0] cpattern_0_2_1_V_read;
input [3:0] cpattern_0_2_2_V_read;
input [3:0] cpattern_0_2_3_V_read;
input [3:0] cpattern_1_0_0_V_read;
input [3:0] cpattern_1_0_1_V_read;
input [3:0] cpattern_1_0_2_V_read;
input [3:0] cpattern_1_0_3_V_read;
input [3:0] cpattern_1_1_0_V_read;
input [3:0] cpattern_1_1_1_V_read;
input [3:0] cpattern_1_1_2_V_read;
input [3:0] cpattern_1_1_3_V_read;
input [3:0] cpattern_1_2_0_V_read;
input [3:0] cpattern_1_2_1_V_read;
input [3:0] cpattern_1_2_2_V_read;
input [3:0] cpattern_1_2_3_V_read;
input [3:0] cpattern_2_0_0_V_read;
input [3:0] cpattern_2_0_1_V_read;
input [3:0] cpattern_2_0_2_V_read;
input [3:0] cpattern_2_0_3_V_read;
input [3:0] cpattern_2_1_0_V_read;
input [3:0] cpattern_2_1_1_V_read;
input [3:0] cpattern_2_1_2_V_read;
input [3:0] cpattern_2_1_3_V_read;
input [3:0] cpattern_2_2_0_V_read;
input [3:0] cpattern_2_2_1_V_read;
input [3:0] cpattern_2_2_2_V_read;
input [3:0] cpattern_2_2_3_V_read;
input [3:0] cpattern_3_0_0_V_read;
input [3:0] cpattern_3_0_1_V_read;
input [3:0] cpattern_3_0_2_V_read;
input [3:0] cpattern_3_0_3_V_read;
input [3:0] cpattern_3_1_0_V_read;
input [3:0] cpattern_3_1_1_V_read;
input [3:0] cpattern_3_1_2_V_read;
input [3:0] cpattern_3_1_3_V_read;
input [3:0] cpattern_3_2_0_V_read;
input [3:0] cpattern_3_2_1_V_read;
input [3:0] cpattern_3_2_2_V_read;
input [3:0] cpattern_3_2_3_V_read;
input [11:0] delta_ph_0_0_0_V_read;
input [11:0] delta_ph_0_0_1_V_read;
input [11:0] delta_ph_0_0_2_V_read;
input [11:0] delta_ph_0_0_3_V_read;
input [11:0] delta_ph_0_0_4_V_read;
input [11:0] delta_ph_0_0_5_V_read;
input [11:0] delta_ph_0_1_0_V_read;
input [11:0] delta_ph_0_1_1_V_read;
input [11:0] delta_ph_0_1_2_V_read;
input [11:0] delta_ph_0_1_3_V_read;
input [11:0] delta_ph_0_1_4_V_read;
input [11:0] delta_ph_0_1_5_V_read;
input [11:0] delta_ph_0_2_0_V_read;
input [11:0] delta_ph_0_2_1_V_read;
input [11:0] delta_ph_0_2_2_V_read;
input [11:0] delta_ph_0_2_3_V_read;
input [11:0] delta_ph_0_2_4_V_read;
input [11:0] delta_ph_0_2_5_V_read;
input [11:0] delta_ph_1_0_0_V_read;
input [11:0] delta_ph_1_0_1_V_read;
input [11:0] delta_ph_1_0_2_V_read;
input [11:0] delta_ph_1_0_3_V_read;
input [11:0] delta_ph_1_0_4_V_read;
input [11:0] delta_ph_1_0_5_V_read;
input [11:0] delta_ph_1_1_0_V_read;
input [11:0] delta_ph_1_1_1_V_read;
input [11:0] delta_ph_1_1_2_V_read;
input [11:0] delta_ph_1_1_3_V_read;
input [11:0] delta_ph_1_1_4_V_read;
input [11:0] delta_ph_1_1_5_V_read;
input [11:0] delta_ph_1_2_0_V_read;
input [11:0] delta_ph_1_2_1_V_read;
input [11:0] delta_ph_1_2_2_V_read;
input [11:0] delta_ph_1_2_3_V_read;
input [11:0] delta_ph_1_2_4_V_read;
input [11:0] delta_ph_1_2_5_V_read;
input [11:0] delta_ph_2_0_0_V_read;
input [11:0] delta_ph_2_0_1_V_read;
input [11:0] delta_ph_2_0_2_V_read;
input [11:0] delta_ph_2_0_3_V_read;
input [11:0] delta_ph_2_0_4_V_read;
input [11:0] delta_ph_2_0_5_V_read;
input [11:0] delta_ph_2_1_0_V_read;
input [11:0] delta_ph_2_1_1_V_read;
input [11:0] delta_ph_2_1_2_V_read;
input [11:0] delta_ph_2_1_3_V_read;
input [11:0] delta_ph_2_1_4_V_read;
input [11:0] delta_ph_2_1_5_V_read;
input [11:0] delta_ph_2_2_0_V_read;
input [11:0] delta_ph_2_2_1_V_read;
input [11:0] delta_ph_2_2_2_V_read;
input [11:0] delta_ph_2_2_3_V_read;
input [11:0] delta_ph_2_2_4_V_read;
input [11:0] delta_ph_2_2_5_V_read;
input [11:0] delta_ph_3_0_0_V_read;
input [11:0] delta_ph_3_0_1_V_read;
input [11:0] delta_ph_3_0_2_V_read;
input [11:0] delta_ph_3_0_3_V_read;
input [11:0] delta_ph_3_0_4_V_read;
input [11:0] delta_ph_3_0_5_V_read;
input [11:0] delta_ph_3_1_0_V_read;
input [11:0] delta_ph_3_1_1_V_read;
input [11:0] delta_ph_3_1_2_V_read;
input [11:0] delta_ph_3_1_3_V_read;
input [11:0] delta_ph_3_1_4_V_read;
input [11:0] delta_ph_3_1_5_V_read;
input [11:0] delta_ph_3_2_0_V_read;
input [11:0] delta_ph_3_2_1_V_read;
input [11:0] delta_ph_3_2_2_V_read;
input [11:0] delta_ph_3_2_3_V_read;
input [11:0] delta_ph_3_2_4_V_read;
input [11:0] delta_ph_3_2_5_V_read;
input [6:0] delta_th_0_0_0_V_read;
input [6:0] delta_th_0_0_1_V_read;
input [6:0] delta_th_0_0_2_V_read;
input [6:0] delta_th_0_0_3_V_read;
input [6:0] delta_th_0_0_4_V_read;
input [6:0] delta_th_0_0_5_V_read;
input [6:0] delta_th_0_1_0_V_read;
input [6:0] delta_th_0_1_1_V_read;
input [6:0] delta_th_0_1_2_V_read;
input [6:0] delta_th_0_1_3_V_read;
input [6:0] delta_th_0_1_4_V_read;
input [6:0] delta_th_0_1_5_V_read;
input [6:0] delta_th_0_2_0_V_read;
input [6:0] delta_th_0_2_1_V_read;
input [6:0] delta_th_0_2_2_V_read;
input [6:0] delta_th_0_2_3_V_read;
input [6:0] delta_th_0_2_4_V_read;
input [6:0] delta_th_0_2_5_V_read;
input [6:0] delta_th_1_0_0_V_read;
input [6:0] delta_th_1_0_1_V_read;
input [6:0] delta_th_1_0_2_V_read;
input [6:0] delta_th_1_0_3_V_read;
input [6:0] delta_th_1_0_4_V_read;
input [6:0] delta_th_1_0_5_V_read;
input [6:0] delta_th_1_1_0_V_read;
input [6:0] delta_th_1_1_1_V_read;
input [6:0] delta_th_1_1_2_V_read;
input [6:0] delta_th_1_1_3_V_read;
input [6:0] delta_th_1_1_4_V_read;
input [6:0] delta_th_1_1_5_V_read;
input [6:0] delta_th_1_2_0_V_read;
input [6:0] delta_th_1_2_1_V_read;
input [6:0] delta_th_1_2_2_V_read;
input [6:0] delta_th_1_2_3_V_read;
input [6:0] delta_th_1_2_4_V_read;
input [6:0] delta_th_1_2_5_V_read;
input [6:0] delta_th_2_0_0_V_read;
input [6:0] delta_th_2_0_1_V_read;
input [6:0] delta_th_2_0_2_V_read;
input [6:0] delta_th_2_0_3_V_read;
input [6:0] delta_th_2_0_4_V_read;
input [6:0] delta_th_2_0_5_V_read;
input [6:0] delta_th_2_1_0_V_read;
input [6:0] delta_th_2_1_1_V_read;
input [6:0] delta_th_2_1_2_V_read;
input [6:0] delta_th_2_1_3_V_read;
input [6:0] delta_th_2_1_4_V_read;
input [6:0] delta_th_2_1_5_V_read;
input [6:0] delta_th_2_2_0_V_read;
input [6:0] delta_th_2_2_1_V_read;
input [6:0] delta_th_2_2_2_V_read;
input [6:0] delta_th_2_2_3_V_read;
input [6:0] delta_th_2_2_4_V_read;
input [6:0] delta_th_2_2_5_V_read;
input [6:0] delta_th_3_0_0_V_read;
input [6:0] delta_th_3_0_1_V_read;
input [6:0] delta_th_3_0_2_V_read;
input [6:0] delta_th_3_0_3_V_read;
input [6:0] delta_th_3_0_4_V_read;
input [6:0] delta_th_3_0_5_V_read;
input [6:0] delta_th_3_1_0_V_read;
input [6:0] delta_th_3_1_1_V_read;
input [6:0] delta_th_3_1_2_V_read;
input [6:0] delta_th_3_1_3_V_read;
input [6:0] delta_th_3_1_4_V_read;
input [6:0] delta_th_3_1_5_V_read;
input [6:0] delta_th_3_2_0_V_read;
input [6:0] delta_th_3_2_1_V_read;
input [6:0] delta_th_3_2_2_V_read;
input [6:0] delta_th_3_2_3_V_read;
input [6:0] delta_th_3_2_4_V_read;
input [6:0] delta_th_3_2_5_V_read;
input [5:0] sign_ph_0_0_V_read;
input [5:0] sign_ph_0_1_V_read;
input [5:0] sign_ph_0_2_V_read;
input [5:0] sign_ph_1_0_V_read;
input [5:0] sign_ph_1_1_V_read;
input [5:0] sign_ph_1_2_V_read;
input [5:0] sign_ph_2_0_V_read;
input [5:0] sign_ph_2_1_V_read;
input [5:0] sign_ph_2_2_V_read;
input [5:0] sign_ph_3_0_V_read;
input [5:0] sign_ph_3_1_V_read;
input [5:0] sign_ph_3_2_V_read;
input [5:0] sign_th_0_0_V_read;
input [5:0] sign_th_0_1_V_read;
input [5:0] sign_th_0_2_V_read;
input [5:0] sign_th_1_0_V_read;
input [5:0] sign_th_1_1_V_read;
input [5:0] sign_th_1_2_V_read;
input [5:0] sign_th_2_0_V_read;
input [5:0] sign_th_2_1_V_read;
input [5:0] sign_th_2_2_V_read;
input [5:0] sign_th_3_0_V_read;
input [5:0] sign_th_3_1_V_read;
input [5:0] sign_th_3_2_V_read;
input [6:0] rank_0_0_V_read;
input [6:0] rank_0_1_V_read;
input [6:0] rank_0_2_V_read;
input [6:0] rank_1_0_V_read;
input [6:0] rank_1_1_V_read;
input [6:0] rank_1_2_V_read;
input [6:0] rank_2_0_V_read;
input [6:0] rank_2_1_V_read;
input [6:0] rank_2_2_V_read;
input [6:0] rank_3_0_V_read;
input [6:0] rank_3_1_V_read;
input [6:0] rank_3_2_V_read;
input [3:0] si_0_0_V_read;
input [3:0] si_0_1_V_read;
input [3:0] si_0_2_V_read;
input [3:0] si_1_0_V_read;
input [3:0] si_1_1_V_read;
input [3:0] si_1_2_V_read;
input [3:0] si_2_0_V_read;
input [3:0] si_2_1_V_read;
input [3:0] si_2_2_V_read;
input [3:0] si_3_0_V_read;
input [3:0] si_3_1_V_read;
input [3:0] si_3_2_V_read;
output [11:0] ap_return_0;
output [11:0] ap_return_1;
output [11:0] ap_return_2;
output [6:0] ap_return_3;
output [6:0] ap_return_4;
output [6:0] ap_return_5;
output [3:0] ap_return_6;
output [3:0] ap_return_7;
output [3:0] ap_return_8;
output [3:0] ap_return_9;
output [3:0] ap_return_10;
output [3:0] ap_return_11;
output [3:0] ap_return_12;
output [3:0] ap_return_13;
output [3:0] ap_return_14;
output [3:0] ap_return_15;
output [3:0] ap_return_16;
output [3:0] ap_return_17;
output [11:0] ap_return_18;
output [11:0] ap_return_19;
output [11:0] ap_return_20;
output [11:0] ap_return_21;
output [11:0] ap_return_22;
output [11:0] ap_return_23;
output [11:0] ap_return_24;
output [11:0] ap_return_25;
output [11:0] ap_return_26;
output [11:0] ap_return_27;
output [11:0] ap_return_28;
output [11:0] ap_return_29;
output [11:0] ap_return_30;
output [11:0] ap_return_31;
output [11:0] ap_return_32;
output [11:0] ap_return_33;
output [11:0] ap_return_34;
output [11:0] ap_return_35;
output [6:0] ap_return_36;
output [6:0] ap_return_37;
output [6:0] ap_return_38;
output [6:0] ap_return_39;
output [6:0] ap_return_40;
output [6:0] ap_return_41;
output [6:0] ap_return_42;
output [6:0] ap_return_43;
output [6:0] ap_return_44;
output [6:0] ap_return_45;
output [6:0] ap_return_46;
output [6:0] ap_return_47;
output [6:0] ap_return_48;
output [6:0] ap_return_49;
output [6:0] ap_return_50;
output [6:0] ap_return_51;
output [6:0] ap_return_52;
output [6:0] ap_return_53;
output [5:0] ap_return_54;
output [5:0] ap_return_55;
output [5:0] ap_return_56;
output [5:0] ap_return_57;
output [5:0] ap_return_58;
output [5:0] ap_return_59;
output [6:0] ap_return_60;
output [6:0] ap_return_61;
output [6:0] ap_return_62;
output [1:0] ap_return_63;
output [1:0] ap_return_64;
output [1:0] ap_return_65;
output [1:0] ap_return_66;
output [1:0] ap_return_67;
output [1:0] ap_return_68;
output [1:0] ap_return_69;
output [1:0] ap_return_70;
output [1:0] ap_return_71;
output [1:0] ap_return_72;
output [1:0] ap_return_73;
output [1:0] ap_return_74;
output [1:0] ap_return_75;
output [1:0] ap_return_76;
output [1:0] ap_return_77;
output [1:0] ap_return_78;
output [1:0] ap_return_79;
output [1:0] ap_return_80;
output [1:0] ap_return_81;
output [1:0] ap_return_82;
output [1:0] ap_return_83;
output [1:0] ap_return_84;
output [1:0] ap_return_85;
output [1:0] ap_return_86;
output [1:0] ap_return_87;
output [1:0] ap_return_88;
output [1:0] ap_return_89;
output [1:0] ap_return_90;
output [1:0] ap_return_91;
output [1:0] ap_return_92;
output [3:0] ap_return_93;
output [3:0] ap_return_94;
output [3:0] ap_return_95;
output [3:0] ap_return_96;
output [3:0] ap_return_97;
output [3:0] ap_return_98;
output [3:0] ap_return_99;
output [3:0] ap_return_100;
output [3:0] ap_return_101;
output [3:0] ap_return_102;
output [3:0] ap_return_103;
output [3:0] ap_return_104;
output [3:0] ap_return_105;
output [3:0] ap_return_106;
output [3:0] ap_return_107;
output [4:0] ap_return_108;
output [4:0] ap_return_109;
output [4:0] ap_return_110;
reg [6:0] rank_3_2_V_read_1_reg_39088;
reg [6:0] ap_reg_ppstg_rank_3_2_V_read_1_reg_39088_pp0_iter1;
reg [6:0] rank_3_1_V_read_1_reg_39095;
reg [6:0] ap_reg_ppstg_rank_3_1_V_read_1_reg_39095_pp0_iter1;
reg [6:0] rank_3_0_V_read_1_reg_39102;
reg [6:0] ap_reg_ppstg_rank_3_0_V_read_1_reg_39102_pp0_iter1;
reg [6:0] rank_2_2_V_read_1_reg_39109;
reg [6:0] ap_reg_ppstg_rank_2_2_V_read_1_reg_39109_pp0_iter1;
reg [6:0] rank_2_1_V_read_1_reg_39116;
reg [6:0] ap_reg_ppstg_rank_2_1_V_read_1_reg_39116_pp0_iter1;
reg [6:0] rank_2_0_V_read_1_reg_39123;
reg [6:0] ap_reg_ppstg_rank_2_0_V_read_1_reg_39123_pp0_iter1;
reg [6:0] rank_1_2_V_read_1_reg_39130;
reg [6:0] ap_reg_ppstg_rank_1_2_V_read_1_reg_39130_pp0_iter1;
reg [6:0] rank_1_1_V_read_1_reg_39137;
reg [6:0] ap_reg_ppstg_rank_1_1_V_read_1_reg_39137_pp0_iter1;
reg [6:0] rank_1_0_V_read_1_reg_39144;
reg [6:0] ap_reg_ppstg_rank_1_0_V_read_1_reg_39144_pp0_iter1;
reg [6:0] rank_0_2_V_read_1_reg_39151;
reg [6:0] ap_reg_ppstg_rank_0_2_V_read_1_reg_39151_pp0_iter1;
reg [6:0] rank_0_1_V_read_1_reg_39158;
reg [6:0] ap_reg_ppstg_rank_0_1_V_read_1_reg_39158_pp0_iter1;
reg [6:0] rank_0_0_V_read_1_reg_39165;
reg [6:0] ap_reg_ppstg_rank_0_0_V_read_1_reg_39165_pp0_iter1;
reg [5:0] sign_th_0_0_V_read_1_reg_39172;
reg [5:0] ap_reg_ppstg_sign_th_0_0_V_read_1_reg_39172_pp0_iter1;
reg [5:0] sign_ph_0_0_V_read_1_reg_39179;
reg [5:0] ap_reg_ppstg_sign_ph_0_0_V_read_1_reg_39179_pp0_iter1;
reg [6:0] delta_th_3_2_5_V_read_1_reg_39186;
reg [6:0] ap_reg_ppstg_delta_th_3_2_5_V_read_1_reg_39186_pp0_iter1;
reg [6:0] delta_th_3_2_4_V_read_1_reg_39193;
reg [6:0] ap_reg_ppstg_delta_th_3_2_4_V_read_1_reg_39193_pp0_iter1;
reg [6:0] delta_th_3_2_3_V_read_1_reg_39200;
reg [6:0] ap_reg_ppstg_delta_th_3_2_3_V_read_1_reg_39200_pp0_iter1;
reg [6:0] delta_th_3_2_2_V_read_1_reg_39207;
reg [6:0] ap_reg_ppstg_delta_th_3_2_2_V_read_1_reg_39207_pp0_iter1;
reg [6:0] delta_th_3_2_1_V_read_1_reg_39214;
reg [6:0] ap_reg_ppstg_delta_th_3_2_1_V_read_1_reg_39214_pp0_iter1;
reg [6:0] delta_th_3_2_0_V_read_1_reg_39221;
reg [6:0] ap_reg_ppstg_delta_th_3_2_0_V_read_1_reg_39221_pp0_iter1;
reg [6:0] delta_th_3_1_5_V_read_1_reg_39228;
reg [6:0] ap_reg_ppstg_delta_th_3_1_5_V_read_1_reg_39228_pp0_iter1;
reg [6:0] delta_th_3_1_4_V_read_1_reg_39235;
reg [6:0] ap_reg_ppstg_delta_th_3_1_4_V_read_1_reg_39235_pp0_iter1;
reg [6:0] delta_th_3_1_3_V_read_1_reg_39242;
reg [6:0] ap_reg_ppstg_delta_th_3_1_3_V_read_1_reg_39242_pp0_iter1;
reg [6:0] delta_th_3_1_2_V_read_1_reg_39249;
reg [6:0] ap_reg_ppstg_delta_th_3_1_2_V_read_1_reg_39249_pp0_iter1;
reg [6:0] delta_th_3_1_1_V_read_1_reg_39256;
reg [6:0] ap_reg_ppstg_delta_th_3_1_1_V_read_1_reg_39256_pp0_iter1;
reg [6:0] delta_th_3_1_0_V_read_1_reg_39263;
reg [6:0] ap_reg_ppstg_delta_th_3_1_0_V_read_1_reg_39263_pp0_iter1;
reg [6:0] delta_th_3_0_5_V_read_1_reg_39270;
reg [6:0] ap_reg_ppstg_delta_th_3_0_5_V_read_1_reg_39270_pp0_iter1;
reg [6:0] delta_th_3_0_4_V_read_1_reg_39277;
reg [6:0] ap_reg_ppstg_delta_th_3_0_4_V_read_1_reg_39277_pp0_iter1;
reg [6:0] delta_th_3_0_3_V_read_1_reg_39284;
reg [6:0] ap_reg_ppstg_delta_th_3_0_3_V_read_1_reg_39284_pp0_iter1;
reg [6:0] delta_th_3_0_2_V_read_1_reg_39291;
reg [6:0] ap_reg_ppstg_delta_th_3_0_2_V_read_1_reg_39291_pp0_iter1;
reg [6:0] delta_th_3_0_1_V_read_1_reg_39298;
reg [6:0] ap_reg_ppstg_delta_th_3_0_1_V_read_1_reg_39298_pp0_iter1;
reg [6:0] delta_th_3_0_0_V_read_1_reg_39305;
reg [6:0] ap_reg_ppstg_delta_th_3_0_0_V_read_1_reg_39305_pp0_iter1;
reg [6:0] delta_th_2_2_5_V_read_1_reg_39312;
reg [6:0] ap_reg_ppstg_delta_th_2_2_5_V_read_1_reg_39312_pp0_iter1;
reg [6:0] delta_th_2_2_4_V_read_1_reg_39319;
reg [6:0] ap_reg_ppstg_delta_th_2_2_4_V_read_1_reg_39319_pp0_iter1;
reg [6:0] delta_th_2_2_3_V_read_1_reg_39326;
reg [6:0] ap_reg_ppstg_delta_th_2_2_3_V_read_1_reg_39326_pp0_iter1;
reg [6:0] delta_th_2_2_2_V_read_1_reg_39333;
reg [6:0] ap_reg_ppstg_delta_th_2_2_2_V_read_1_reg_39333_pp0_iter1;
reg [6:0] delta_th_2_2_1_V_read_1_reg_39340;
reg [6:0] ap_reg_ppstg_delta_th_2_2_1_V_read_1_reg_39340_pp0_iter1;
reg [6:0] delta_th_2_2_0_V_read_1_reg_39347;
reg [6:0] ap_reg_ppstg_delta_th_2_2_0_V_read_1_reg_39347_pp0_iter1;
reg [6:0] delta_th_2_1_5_V_read_1_reg_39354;
reg [6:0] ap_reg_ppstg_delta_th_2_1_5_V_read_1_reg_39354_pp0_iter1;
reg [6:0] delta_th_2_1_4_V_read_1_reg_39361;
reg [6:0] ap_reg_ppstg_delta_th_2_1_4_V_read_1_reg_39361_pp0_iter1;
reg [6:0] delta_th_2_1_3_V_read_1_reg_39368;
reg [6:0] ap_reg_ppstg_delta_th_2_1_3_V_read_1_reg_39368_pp0_iter1;
reg [6:0] delta_th_2_1_2_V_read_1_reg_39375;
reg [6:0] ap_reg_ppstg_delta_th_2_1_2_V_read_1_reg_39375_pp0_iter1;
reg [6:0] delta_th_2_1_1_V_read_1_reg_39382;
reg [6:0] ap_reg_ppstg_delta_th_2_1_1_V_read_1_reg_39382_pp0_iter1;
reg [6:0] delta_th_2_1_0_V_read_1_reg_39389;
reg [6:0] ap_reg_ppstg_delta_th_2_1_0_V_read_1_reg_39389_pp0_iter1;
reg [6:0] delta_th_2_0_5_V_read_1_reg_39396;
reg [6:0] ap_reg_ppstg_delta_th_2_0_5_V_read_1_reg_39396_pp0_iter1;
reg [6:0] delta_th_2_0_4_V_read_1_reg_39403;
reg [6:0] ap_reg_ppstg_delta_th_2_0_4_V_read_1_reg_39403_pp0_iter1;
reg [6:0] delta_th_2_0_3_V_read_1_reg_39410;
reg [6:0] ap_reg_ppstg_delta_th_2_0_3_V_read_1_reg_39410_pp0_iter1;
reg [6:0] delta_th_2_0_2_V_read_1_reg_39417;
reg [6:0] ap_reg_ppstg_delta_th_2_0_2_V_read_1_reg_39417_pp0_iter1;
reg [6:0] delta_th_2_0_1_V_read_1_reg_39424;
reg [6:0] ap_reg_ppstg_delta_th_2_0_1_V_read_1_reg_39424_pp0_iter1;
reg [6:0] delta_th_2_0_0_V_read_1_reg_39431;
reg [6:0] ap_reg_ppstg_delta_th_2_0_0_V_read_1_reg_39431_pp0_iter1;
reg [6:0] delta_th_1_2_5_V_read_1_reg_39438;
reg [6:0] ap_reg_ppstg_delta_th_1_2_5_V_read_1_reg_39438_pp0_iter1;
reg [6:0] delta_th_1_2_4_V_read_1_reg_39445;
reg [6:0] ap_reg_ppstg_delta_th_1_2_4_V_read_1_reg_39445_pp0_iter1;
reg [6:0] delta_th_1_2_3_V_read_1_reg_39452;
reg [6:0] ap_reg_ppstg_delta_th_1_2_3_V_read_1_reg_39452_pp0_iter1;
reg [6:0] delta_th_1_2_2_V_read_1_reg_39459;
reg [6:0] ap_reg_ppstg_delta_th_1_2_2_V_read_1_reg_39459_pp0_iter1;
reg [6:0] delta_th_1_2_1_V_read_1_reg_39466;
reg [6:0] ap_reg_ppstg_delta_th_1_2_1_V_read_1_reg_39466_pp0_iter1;
reg [6:0] delta_th_1_2_0_V_read_1_reg_39473;
reg [6:0] ap_reg_ppstg_delta_th_1_2_0_V_read_1_reg_39473_pp0_iter1;
reg [6:0] delta_th_1_1_5_V_read_1_reg_39480;
reg [6:0] ap_reg_ppstg_delta_th_1_1_5_V_read_1_reg_39480_pp0_iter1;
reg [6:0] delta_th_1_1_4_V_read_1_reg_39487;
reg [6:0] ap_reg_ppstg_delta_th_1_1_4_V_read_1_reg_39487_pp0_iter1;
reg [6:0] delta_th_1_1_3_V_read_1_reg_39494;
reg [6:0] ap_reg_ppstg_delta_th_1_1_3_V_read_1_reg_39494_pp0_iter1;
reg [6:0] delta_th_1_1_2_V_read_1_reg_39501;
reg [6:0] ap_reg_ppstg_delta_th_1_1_2_V_read_1_reg_39501_pp0_iter1;
reg [6:0] delta_th_1_1_1_V_read_1_reg_39508;
reg [6:0] ap_reg_ppstg_delta_th_1_1_1_V_read_1_reg_39508_pp0_iter1;
reg [6:0] delta_th_1_1_0_V_read_1_reg_39515;
reg [6:0] ap_reg_ppstg_delta_th_1_1_0_V_read_1_reg_39515_pp0_iter1;
reg [6:0] delta_th_1_0_5_V_read_1_reg_39522;
reg [6:0] ap_reg_ppstg_delta_th_1_0_5_V_read_1_reg_39522_pp0_iter1;
reg [6:0] delta_th_1_0_4_V_read_1_reg_39529;
reg [6:0] ap_reg_ppstg_delta_th_1_0_4_V_read_1_reg_39529_pp0_iter1;
reg [6:0] delta_th_1_0_3_V_read_1_reg_39536;
reg [6:0] ap_reg_ppstg_delta_th_1_0_3_V_read_1_reg_39536_pp0_iter1;
reg [6:0] delta_th_1_0_2_V_read_1_reg_39543;
reg [6:0] ap_reg_ppstg_delta_th_1_0_2_V_read_1_reg_39543_pp0_iter1;
reg [6:0] delta_th_1_0_1_V_read_1_reg_39550;
reg [6:0] ap_reg_ppstg_delta_th_1_0_1_V_read_1_reg_39550_pp0_iter1;
reg [6:0] delta_th_1_0_0_V_read_1_reg_39557;
reg [6:0] ap_reg_ppstg_delta_th_1_0_0_V_read_1_reg_39557_pp0_iter1;
reg [6:0] delta_th_0_2_5_V_read_1_reg_39564;
reg [6:0] ap_reg_ppstg_delta_th_0_2_5_V_read_1_reg_39564_pp0_iter1;
reg [6:0] delta_th_0_2_4_V_read_1_reg_39571;
reg [6:0] ap_reg_ppstg_delta_th_0_2_4_V_read_1_reg_39571_pp0_iter1;
reg [6:0] delta_th_0_2_3_V_read_1_reg_39578;
reg [6:0] ap_reg_ppstg_delta_th_0_2_3_V_read_1_reg_39578_pp0_iter1;
reg [6:0] delta_th_0_2_2_V_read_1_reg_39585;
reg [6:0] ap_reg_ppstg_delta_th_0_2_2_V_read_1_reg_39585_pp0_iter1;
reg [6:0] delta_th_0_2_1_V_read_1_reg_39592;
reg [6:0] ap_reg_ppstg_delta_th_0_2_1_V_read_1_reg_39592_pp0_iter1;
reg [6:0] delta_th_0_2_0_V_read_1_reg_39599;
reg [6:0] ap_reg_ppstg_delta_th_0_2_0_V_read_1_reg_39599_pp0_iter1;
reg [6:0] delta_th_0_1_5_V_read_1_reg_39606;
reg [6:0] ap_reg_ppstg_delta_th_0_1_5_V_read_1_reg_39606_pp0_iter1;
reg [6:0] delta_th_0_1_4_V_read_1_reg_39613;
reg [6:0] ap_reg_ppstg_delta_th_0_1_4_V_read_1_reg_39613_pp0_iter1;
reg [6:0] delta_th_0_1_3_V_read_1_reg_39620;
reg [6:0] ap_reg_ppstg_delta_th_0_1_3_V_read_1_reg_39620_pp0_iter1;
reg [6:0] delta_th_0_1_2_V_read_1_reg_39627;
reg [6:0] ap_reg_ppstg_delta_th_0_1_2_V_read_1_reg_39627_pp0_iter1;
reg [6:0] delta_th_0_1_1_V_read_1_reg_39634;
reg [6:0] ap_reg_ppstg_delta_th_0_1_1_V_read_1_reg_39634_pp0_iter1;
reg [6:0] delta_th_0_1_0_V_read_1_reg_39641;
reg [6:0] ap_reg_ppstg_delta_th_0_1_0_V_read_1_reg_39641_pp0_iter1;
reg [6:0] delta_th_0_0_5_V_read_1_reg_39648;
reg [6:0] ap_reg_ppstg_delta_th_0_0_5_V_read_1_reg_39648_pp0_iter1;
reg [6:0] delta_th_0_0_4_V_read_1_reg_39655;
reg [6:0] ap_reg_ppstg_delta_th_0_0_4_V_read_1_reg_39655_pp0_iter1;
reg [6:0] delta_th_0_0_3_V_read_1_reg_39662;
reg [6:0] ap_reg_ppstg_delta_th_0_0_3_V_read_1_reg_39662_pp0_iter1;
reg [6:0] delta_th_0_0_2_V_read_1_reg_39669;
reg [6:0] ap_reg_ppstg_delta_th_0_0_2_V_read_1_reg_39669_pp0_iter1;
reg [6:0] delta_th_0_0_1_V_read_1_reg_39676;
reg [6:0] ap_reg_ppstg_delta_th_0_0_1_V_read_1_reg_39676_pp0_iter1;
reg [6:0] delta_th_0_0_0_V_read_1_reg_39683;
reg [6:0] ap_reg_ppstg_delta_th_0_0_0_V_read_1_reg_39683_pp0_iter1;
reg [11:0] delta_ph_3_2_5_V_read_1_reg_39690;
reg [11:0] ap_reg_ppstg_delta_ph_3_2_5_V_read_1_reg_39690_pp0_iter1;
reg [11:0] delta_ph_3_2_4_V_read_1_reg_39697;
reg [11:0] ap_reg_ppstg_delta_ph_3_2_4_V_read_1_reg_39697_pp0_iter1;
reg [11:0] delta_ph_3_2_3_V_read_1_reg_39704;
reg [11:0] ap_reg_ppstg_delta_ph_3_2_3_V_read_1_reg_39704_pp0_iter1;
reg [11:0] delta_ph_3_2_2_V_read_1_reg_39711;
reg [11:0] ap_reg_ppstg_delta_ph_3_2_2_V_read_1_reg_39711_pp0_iter1;
reg [11:0] delta_ph_3_2_1_V_read_1_reg_39718;
reg [11:0] ap_reg_ppstg_delta_ph_3_2_1_V_read_1_reg_39718_pp0_iter1;
reg [11:0] delta_ph_3_2_0_V_read_1_reg_39725;
reg [11:0] ap_reg_ppstg_delta_ph_3_2_0_V_read_1_reg_39725_pp0_iter1;
reg [11:0] delta_ph_3_1_5_V_read_1_reg_39732;
reg [11:0] ap_reg_ppstg_delta_ph_3_1_5_V_read_1_reg_39732_pp0_iter1;
reg [11:0] delta_ph_3_1_4_V_read_1_reg_39739;
reg [11:0] ap_reg_ppstg_delta_ph_3_1_4_V_read_1_reg_39739_pp0_iter1;
reg [11:0] delta_ph_3_1_3_V_read_1_reg_39746;
reg [11:0] ap_reg_ppstg_delta_ph_3_1_3_V_read_1_reg_39746_pp0_iter1;
reg [11:0] delta_ph_3_1_2_V_read_1_reg_39753;
reg [11:0] ap_reg_ppstg_delta_ph_3_1_2_V_read_1_reg_39753_pp0_iter1;
reg [11:0] delta_ph_3_1_1_V_read_1_reg_39760;
reg [11:0] ap_reg_ppstg_delta_ph_3_1_1_V_read_1_reg_39760_pp0_iter1;
reg [11:0] delta_ph_3_1_0_V_read_1_reg_39767;
reg [11:0] ap_reg_ppstg_delta_ph_3_1_0_V_read_1_reg_39767_pp0_iter1;
reg [11:0] delta_ph_3_0_5_V_read_1_reg_39774;
reg [11:0] ap_reg_ppstg_delta_ph_3_0_5_V_read_1_reg_39774_pp0_iter1;
reg [11:0] delta_ph_3_0_4_V_read_1_reg_39781;
reg [11:0] ap_reg_ppstg_delta_ph_3_0_4_V_read_1_reg_39781_pp0_iter1;
reg [11:0] delta_ph_3_0_3_V_read_1_reg_39788;
reg [11:0] ap_reg_ppstg_delta_ph_3_0_3_V_read_1_reg_39788_pp0_iter1;
reg [11:0] delta_ph_3_0_2_V_read_1_reg_39795;
reg [11:0] ap_reg_ppstg_delta_ph_3_0_2_V_read_1_reg_39795_pp0_iter1;
reg [11:0] delta_ph_3_0_1_V_read_1_reg_39802;
reg [11:0] ap_reg_ppstg_delta_ph_3_0_1_V_read_1_reg_39802_pp0_iter1;
reg [11:0] delta_ph_3_0_0_V_read_1_reg_39809;
reg [11:0] ap_reg_ppstg_delta_ph_3_0_0_V_read_1_reg_39809_pp0_iter1;
reg [11:0] delta_ph_2_2_5_V_read_1_reg_39816;
reg [11:0] ap_reg_ppstg_delta_ph_2_2_5_V_read_1_reg_39816_pp0_iter1;
reg [11:0] delta_ph_2_2_4_V_read_1_reg_39823;
reg [11:0] ap_reg_ppstg_delta_ph_2_2_4_V_read_1_reg_39823_pp0_iter1;
reg [11:0] delta_ph_2_2_3_V_read_1_reg_39830;
reg [11:0] ap_reg_ppstg_delta_ph_2_2_3_V_read_1_reg_39830_pp0_iter1;
reg [11:0] delta_ph_2_2_2_V_read_1_reg_39837;
reg [11:0] ap_reg_ppstg_delta_ph_2_2_2_V_read_1_reg_39837_pp0_iter1;
reg [11:0] delta_ph_2_2_1_V_read_1_reg_39844;
reg [11:0] ap_reg_ppstg_delta_ph_2_2_1_V_read_1_reg_39844_pp0_iter1;
reg [11:0] delta_ph_2_2_0_V_read_1_reg_39851;
reg [11:0] ap_reg_ppstg_delta_ph_2_2_0_V_read_1_reg_39851_pp0_iter1;
reg [11:0] delta_ph_2_1_5_V_read_1_reg_39858;
reg [11:0] ap_reg_ppstg_delta_ph_2_1_5_V_read_1_reg_39858_pp0_iter1;
reg [11:0] delta_ph_2_1_4_V_read_1_reg_39865;
reg [11:0] ap_reg_ppstg_delta_ph_2_1_4_V_read_1_reg_39865_pp0_iter1;
reg [11:0] delta_ph_2_1_3_V_read_1_reg_39872;
reg [11:0] ap_reg_ppstg_delta_ph_2_1_3_V_read_1_reg_39872_pp0_iter1;
reg [11:0] delta_ph_2_1_2_V_read_1_reg_39879;
reg [11:0] ap_reg_ppstg_delta_ph_2_1_2_V_read_1_reg_39879_pp0_iter1;
reg [11:0] delta_ph_2_1_1_V_read_1_reg_39886;
reg [11:0] ap_reg_ppstg_delta_ph_2_1_1_V_read_1_reg_39886_pp0_iter1;
reg [11:0] delta_ph_2_1_0_V_read_1_reg_39893;
reg [11:0] ap_reg_ppstg_delta_ph_2_1_0_V_read_1_reg_39893_pp0_iter1;
reg [11:0] delta_ph_2_0_5_V_read_1_reg_39900;
reg [11:0] ap_reg_ppstg_delta_ph_2_0_5_V_read_1_reg_39900_pp0_iter1;
reg [11:0] delta_ph_2_0_4_V_read_1_reg_39907;
reg [11:0] ap_reg_ppstg_delta_ph_2_0_4_V_read_1_reg_39907_pp0_iter1;
reg [11:0] delta_ph_2_0_3_V_read_1_reg_39914;
reg [11:0] ap_reg_ppstg_delta_ph_2_0_3_V_read_1_reg_39914_pp0_iter1;
reg [11:0] delta_ph_2_0_2_V_read_1_reg_39921;
reg [11:0] ap_reg_ppstg_delta_ph_2_0_2_V_read_1_reg_39921_pp0_iter1;
reg [11:0] delta_ph_2_0_1_V_read_1_reg_39928;
reg [11:0] ap_reg_ppstg_delta_ph_2_0_1_V_read_1_reg_39928_pp0_iter1;
reg [11:0] delta_ph_2_0_0_V_read_1_reg_39935;
reg [11:0] ap_reg_ppstg_delta_ph_2_0_0_V_read_1_reg_39935_pp0_iter1;
reg [11:0] delta_ph_1_2_5_V_read_1_reg_39942;
reg [11:0] ap_reg_ppstg_delta_ph_1_2_5_V_read_1_reg_39942_pp0_iter1;
reg [11:0] delta_ph_1_2_4_V_read_1_reg_39949;
reg [11:0] ap_reg_ppstg_delta_ph_1_2_4_V_read_1_reg_39949_pp0_iter1;
reg [11:0] delta_ph_1_2_3_V_read_1_reg_39956;
reg [11:0] ap_reg_ppstg_delta_ph_1_2_3_V_read_1_reg_39956_pp0_iter1;
reg [11:0] delta_ph_1_2_2_V_read_1_reg_39963;
reg [11:0] ap_reg_ppstg_delta_ph_1_2_2_V_read_1_reg_39963_pp0_iter1;
reg [11:0] delta_ph_1_2_1_V_read_1_reg_39970;
reg [11:0] ap_reg_ppstg_delta_ph_1_2_1_V_read_1_reg_39970_pp0_iter1;
reg [11:0] delta_ph_1_2_0_V_read_1_reg_39977;
reg [11:0] ap_reg_ppstg_delta_ph_1_2_0_V_read_1_reg_39977_pp0_iter1;
reg [11:0] delta_ph_1_1_5_V_read_1_reg_39984;
reg [11:0] ap_reg_ppstg_delta_ph_1_1_5_V_read_1_reg_39984_pp0_iter1;
reg [11:0] delta_ph_1_1_4_V_read_1_reg_39991;
reg [11:0] ap_reg_ppstg_delta_ph_1_1_4_V_read_1_reg_39991_pp0_iter1;
reg [11:0] delta_ph_1_1_3_V_read_1_reg_39998;
reg [11:0] ap_reg_ppstg_delta_ph_1_1_3_V_read_1_reg_39998_pp0_iter1;
reg [11:0] delta_ph_1_1_2_V_read_1_reg_40005;
reg [11:0] ap_reg_ppstg_delta_ph_1_1_2_V_read_1_reg_40005_pp0_iter1;
reg [11:0] delta_ph_1_1_1_V_read_1_reg_40012;
reg [11:0] ap_reg_ppstg_delta_ph_1_1_1_V_read_1_reg_40012_pp0_iter1;
reg [11:0] delta_ph_1_1_0_V_read_1_reg_40019;
reg [11:0] ap_reg_ppstg_delta_ph_1_1_0_V_read_1_reg_40019_pp0_iter1;
reg [11:0] delta_ph_1_0_5_V_read_1_reg_40026;
reg [11:0] ap_reg_ppstg_delta_ph_1_0_5_V_read_1_reg_40026_pp0_iter1;
reg [11:0] delta_ph_1_0_4_V_read_1_reg_40033;
reg [11:0] ap_reg_ppstg_delta_ph_1_0_4_V_read_1_reg_40033_pp0_iter1;
reg [11:0] delta_ph_1_0_3_V_read_1_reg_40040;
reg [11:0] ap_reg_ppstg_delta_ph_1_0_3_V_read_1_reg_40040_pp0_iter1;
reg [11:0] delta_ph_1_0_2_V_read_1_reg_40047;
reg [11:0] ap_reg_ppstg_delta_ph_1_0_2_V_read_1_reg_40047_pp0_iter1;
reg [11:0] delta_ph_1_0_1_V_read_1_reg_40054;
reg [11:0] ap_reg_ppstg_delta_ph_1_0_1_V_read_1_reg_40054_pp0_iter1;
reg [11:0] delta_ph_1_0_0_V_read_1_reg_40061;
reg [11:0] ap_reg_ppstg_delta_ph_1_0_0_V_read_1_reg_40061_pp0_iter1;
reg [11:0] delta_ph_0_2_5_V_read_1_reg_40068;
reg [11:0] ap_reg_ppstg_delta_ph_0_2_5_V_read_1_reg_40068_pp0_iter1;
reg [11:0] delta_ph_0_2_4_V_read_1_reg_40075;
reg [11:0] ap_reg_ppstg_delta_ph_0_2_4_V_read_1_reg_40075_pp0_iter1;
reg [11:0] delta_ph_0_2_3_V_read_1_reg_40082;
reg [11:0] ap_reg_ppstg_delta_ph_0_2_3_V_read_1_reg_40082_pp0_iter1;
reg [11:0] delta_ph_0_2_2_V_read_1_reg_40089;
reg [11:0] ap_reg_ppstg_delta_ph_0_2_2_V_read_1_reg_40089_pp0_iter1;
reg [11:0] delta_ph_0_2_1_V_read_1_reg_40096;
reg [11:0] ap_reg_ppstg_delta_ph_0_2_1_V_read_1_reg_40096_pp0_iter1;
reg [11:0] delta_ph_0_2_0_V_read_1_reg_40103;
reg [11:0] ap_reg_ppstg_delta_ph_0_2_0_V_read_1_reg_40103_pp0_iter1;
reg [11:0] delta_ph_0_1_5_V_read_1_reg_40110;
reg [11:0] ap_reg_ppstg_delta_ph_0_1_5_V_read_1_reg_40110_pp0_iter1;
reg [11:0] delta_ph_0_1_4_V_read_1_reg_40117;
reg [11:0] ap_reg_ppstg_delta_ph_0_1_4_V_read_1_reg_40117_pp0_iter1;
reg [11:0] delta_ph_0_1_3_V_read_1_reg_40124;
reg [11:0] ap_reg_ppstg_delta_ph_0_1_3_V_read_1_reg_40124_pp0_iter1;
reg [11:0] delta_ph_0_1_2_V_read_1_reg_40131;
reg [11:0] ap_reg_ppstg_delta_ph_0_1_2_V_read_1_reg_40131_pp0_iter1;
reg [11:0] delta_ph_0_1_1_V_read_1_reg_40138;
reg [11:0] ap_reg_ppstg_delta_ph_0_1_1_V_read_1_reg_40138_pp0_iter1;
reg [11:0] delta_ph_0_1_0_V_read_1_reg_40145;
reg [11:0] ap_reg_ppstg_delta_ph_0_1_0_V_read_1_reg_40145_pp0_iter1;
reg [11:0] delta_ph_0_0_5_V_read_1_reg_40152;
reg [11:0] ap_reg_ppstg_delta_ph_0_0_5_V_read_1_reg_40152_pp0_iter1;
reg [11:0] delta_ph_0_0_4_V_read_1_reg_40159;
reg [11:0] ap_reg_ppstg_delta_ph_0_0_4_V_read_1_reg_40159_pp0_iter1;
reg [11:0] delta_ph_0_0_3_V_read_1_reg_40166;
reg [11:0] ap_reg_ppstg_delta_ph_0_0_3_V_read_1_reg_40166_pp0_iter1;
reg [11:0] delta_ph_0_0_2_V_read_1_reg_40173;
reg [11:0] ap_reg_ppstg_delta_ph_0_0_2_V_read_1_reg_40173_pp0_iter1;
reg [11:0] delta_ph_0_0_1_V_read_1_reg_40180;
reg [11:0] ap_reg_ppstg_delta_ph_0_0_1_V_read_1_reg_40180_pp0_iter1;
reg [11:0] delta_ph_0_0_0_V_read_1_reg_40187;
reg [11:0] ap_reg_ppstg_delta_ph_0_0_0_V_read_1_reg_40187_pp0_iter1;
reg [3:0] cpattern_3_2_3_V_read_1_reg_40194;
reg [3:0] ap_reg_ppstg_cpattern_3_2_3_V_read_1_reg_40194_pp0_iter1;
reg [3:0] cpattern_3_2_2_V_read_1_reg_40201;
reg [3:0] ap_reg_ppstg_cpattern_3_2_2_V_read_1_reg_40201_pp0_iter1;
reg [3:0] cpattern_3_2_1_V_read_1_reg_40208;
reg [3:0] ap_reg_ppstg_cpattern_3_2_1_V_read_1_reg_40208_pp0_iter1;
reg [3:0] cpattern_3_2_0_V_read_1_reg_40215;
reg [3:0] ap_reg_ppstg_cpattern_3_2_0_V_read_1_reg_40215_pp0_iter1;
reg [3:0] cpattern_3_1_3_V_read_1_reg_40222;
reg [3:0] ap_reg_ppstg_cpattern_3_1_3_V_read_1_reg_40222_pp0_iter1;
reg [3:0] cpattern_3_1_2_V_read_1_reg_40229;
reg [3:0] ap_reg_ppstg_cpattern_3_1_2_V_read_1_reg_40229_pp0_iter1;
reg [3:0] cpattern_3_1_1_V_read_1_reg_40236;
reg [3:0] ap_reg_ppstg_cpattern_3_1_1_V_read_1_reg_40236_pp0_iter1;
reg [3:0] cpattern_3_1_0_V_read_1_reg_40243;
reg [3:0] ap_reg_ppstg_cpattern_3_1_0_V_read_1_reg_40243_pp0_iter1;
reg [3:0] cpattern_3_0_3_V_read_1_reg_40250;
reg [3:0] ap_reg_ppstg_cpattern_3_0_3_V_read_1_reg_40250_pp0_iter1;
reg [3:0] cpattern_3_0_2_V_read_1_reg_40257;
reg [3:0] ap_reg_ppstg_cpattern_3_0_2_V_read_1_reg_40257_pp0_iter1;
reg [3:0] cpattern_3_0_1_V_read_1_reg_40264;
reg [3:0] ap_reg_ppstg_cpattern_3_0_1_V_read_1_reg_40264_pp0_iter1;
reg [3:0] cpattern_3_0_0_V_read_1_reg_40271;
reg [3:0] ap_reg_ppstg_cpattern_3_0_0_V_read_1_reg_40271_pp0_iter1;
reg [3:0] cpattern_2_2_3_V_read_1_reg_40278;
reg [3:0] ap_reg_ppstg_cpattern_2_2_3_V_read_1_reg_40278_pp0_iter1;
reg [3:0] cpattern_2_2_2_V_read_1_reg_40285;
reg [3:0] ap_reg_ppstg_cpattern_2_2_2_V_read_1_reg_40285_pp0_iter1;
reg [3:0] cpattern_2_2_1_V_read_1_reg_40292;
reg [3:0] ap_reg_ppstg_cpattern_2_2_1_V_read_1_reg_40292_pp0_iter1;
reg [3:0] cpattern_2_2_0_V_read_1_reg_40299;
reg [3:0] ap_reg_ppstg_cpattern_2_2_0_V_read_1_reg_40299_pp0_iter1;
reg [3:0] cpattern_2_1_3_V_read_1_reg_40306;
reg [3:0] ap_reg_ppstg_cpattern_2_1_3_V_read_1_reg_40306_pp0_iter1;
reg [3:0] cpattern_2_1_2_V_read_1_reg_40313;
reg [3:0] ap_reg_ppstg_cpattern_2_1_2_V_read_1_reg_40313_pp0_iter1;
reg [3:0] cpattern_2_1_1_V_read_1_reg_40320;
reg [3:0] ap_reg_ppstg_cpattern_2_1_1_V_read_1_reg_40320_pp0_iter1;
reg [3:0] cpattern_2_1_0_V_read_1_reg_40327;
reg [3:0] ap_reg_ppstg_cpattern_2_1_0_V_read_1_reg_40327_pp0_iter1;
reg [3:0] cpattern_2_0_3_V_read_1_reg_40334;
reg [3:0] ap_reg_ppstg_cpattern_2_0_3_V_read_1_reg_40334_pp0_iter1;
reg [3:0] cpattern_2_0_2_V_read_1_reg_40341;
reg [3:0] ap_reg_ppstg_cpattern_2_0_2_V_read_1_reg_40341_pp0_iter1;
reg [3:0] cpattern_2_0_1_V_read_1_reg_40348;
reg [3:0] ap_reg_ppstg_cpattern_2_0_1_V_read_1_reg_40348_pp0_iter1;
reg [3:0] cpattern_2_0_0_V_read_1_reg_40355;
reg [3:0] ap_reg_ppstg_cpattern_2_0_0_V_read_1_reg_40355_pp0_iter1;
reg [3:0] cpattern_1_2_3_V_read_1_reg_40362;
reg [3:0] ap_reg_ppstg_cpattern_1_2_3_V_read_1_reg_40362_pp0_iter1;
reg [3:0] cpattern_1_2_2_V_read_1_reg_40369;
reg [3:0] ap_reg_ppstg_cpattern_1_2_2_V_read_1_reg_40369_pp0_iter1;
reg [3:0] cpattern_1_2_1_V_read_1_reg_40376;
reg [3:0] ap_reg_ppstg_cpattern_1_2_1_V_read_1_reg_40376_pp0_iter1;
reg [3:0] cpattern_1_2_0_V_read_1_reg_40383;
reg [3:0] ap_reg_ppstg_cpattern_1_2_0_V_read_1_reg_40383_pp0_iter1;
reg [3:0] cpattern_1_1_3_V_read_1_reg_40390;
reg [3:0] ap_reg_ppstg_cpattern_1_1_3_V_read_1_reg_40390_pp0_iter1;
reg [3:0] cpattern_1_1_2_V_read_1_reg_40397;
reg [3:0] ap_reg_ppstg_cpattern_1_1_2_V_read_1_reg_40397_pp0_iter1;
reg [3:0] cpattern_1_1_1_V_read_1_reg_40404;
reg [3:0] ap_reg_ppstg_cpattern_1_1_1_V_read_1_reg_40404_pp0_iter1;
reg [3:0] cpattern_1_1_0_V_read_1_reg_40411;
reg [3:0] ap_reg_ppstg_cpattern_1_1_0_V_read_1_reg_40411_pp0_iter1;
reg [3:0] cpattern_1_0_3_V_read_1_reg_40418;
reg [3:0] ap_reg_ppstg_cpattern_1_0_3_V_read_1_reg_40418_pp0_iter1;
reg [3:0] cpattern_1_0_2_V_read_1_reg_40425;
reg [3:0] ap_reg_ppstg_cpattern_1_0_2_V_read_1_reg_40425_pp0_iter1;
reg [3:0] cpattern_1_0_1_V_read_1_reg_40432;
reg [3:0] ap_reg_ppstg_cpattern_1_0_1_V_read_1_reg_40432_pp0_iter1;
reg [3:0] cpattern_1_0_0_V_read_1_reg_40439;
reg [3:0] ap_reg_ppstg_cpattern_1_0_0_V_read_1_reg_40439_pp0_iter1;
reg [3:0] cpattern_0_2_3_V_read_1_reg_40446;
reg [3:0] ap_reg_ppstg_cpattern_0_2_3_V_read_1_reg_40446_pp0_iter1;
reg [3:0] cpattern_0_2_2_V_read_1_reg_40453;
reg [3:0] ap_reg_ppstg_cpattern_0_2_2_V_read_1_reg_40453_pp0_iter1;
reg [3:0] cpattern_0_2_1_V_read_1_reg_40460;
reg [3:0] ap_reg_ppstg_cpattern_0_2_1_V_read_1_reg_40460_pp0_iter1;
reg [3:0] cpattern_0_2_0_V_read_1_reg_40467;
reg [3:0] ap_reg_ppstg_cpattern_0_2_0_V_read_1_reg_40467_pp0_iter1;
reg [3:0] cpattern_0_1_3_V_read_1_reg_40474;
reg [3:0] ap_reg_ppstg_cpattern_0_1_3_V_read_1_reg_40474_pp0_iter1;
reg [3:0] cpattern_0_1_2_V_read_1_reg_40481;
reg [3:0] ap_reg_ppstg_cpattern_0_1_2_V_read_1_reg_40481_pp0_iter1;
reg [3:0] cpattern_0_1_1_V_read_1_reg_40488;
reg [3:0] ap_reg_ppstg_cpattern_0_1_1_V_read_1_reg_40488_pp0_iter1;
reg [3:0] cpattern_0_1_0_V_read_1_reg_40495;
reg [3:0] ap_reg_ppstg_cpattern_0_1_0_V_read_1_reg_40495_pp0_iter1;
reg [3:0] cpattern_0_0_3_V_read_1_reg_40502;
reg [3:0] ap_reg_ppstg_cpattern_0_0_3_V_read_1_reg_40502_pp0_iter1;
reg [3:0] cpattern_0_0_2_V_read_1_reg_40509;
reg [3:0] ap_reg_ppstg_cpattern_0_0_2_V_read_1_reg_40509_pp0_iter1;
reg [3:0] cpattern_0_0_1_V_read_1_reg_40516;
reg [3:0] ap_reg_ppstg_cpattern_0_0_1_V_read_1_reg_40516_pp0_iter1;
reg [3:0] cpattern_0_0_0_V_read_1_reg_40523;
reg [3:0] ap_reg_ppstg_cpattern_0_0_0_V_read_1_reg_40523_pp0_iter1;
reg [6:0] theta_3_2_V_read_1_reg_40530;
reg [6:0] ap_reg_ppstg_theta_3_2_V_read_1_reg_40530_pp0_iter1;
reg [6:0] theta_3_1_V_read_1_reg_40537;
reg [6:0] ap_reg_ppstg_theta_3_1_V_read_1_reg_40537_pp0_iter1;
reg [6:0] theta_3_0_V_read_1_reg_40544;
reg [6:0] ap_reg_ppstg_theta_3_0_V_read_1_reg_40544_pp0_iter1;
reg [6:0] theta_2_2_V_read_1_reg_40551;
reg [6:0] ap_reg_ppstg_theta_2_2_V_read_1_reg_40551_pp0_iter1;
reg [6:0] theta_2_1_V_read_1_reg_40558;
reg [6:0] ap_reg_ppstg_theta_2_1_V_read_1_reg_40558_pp0_iter1;
reg [6:0] theta_2_0_V_read_1_reg_40565;
reg [6:0] ap_reg_ppstg_theta_2_0_V_read_1_reg_40565_pp0_iter1;
reg [6:0] theta_1_2_V_read_1_reg_40572;
reg [6:0] ap_reg_ppstg_theta_1_2_V_read_1_reg_40572_pp0_iter1;
reg [6:0] theta_1_1_V_read_1_reg_40579;
reg [6:0] ap_reg_ppstg_theta_1_1_V_read_1_reg_40579_pp0_iter1;
reg [6:0] theta_1_0_V_read_1_reg_40586;
reg [6:0] ap_reg_ppstg_theta_1_0_V_read_1_reg_40586_pp0_iter1;
reg [6:0] theta_0_2_V_read_1_reg_40593;
reg [6:0] ap_reg_ppstg_theta_0_2_V_read_1_reg_40593_pp0_iter1;
reg [6:0] theta_0_1_V_read_1_reg_40600;
reg [6:0] ap_reg_ppstg_theta_0_1_V_read_1_reg_40600_pp0_iter1;
reg [6:0] theta_0_0_V_read_1_reg_40607;
reg [6:0] ap_reg_ppstg_theta_0_0_V_read_1_reg_40607_pp0_iter1;
reg [11:0] phi_3_2_V_read_1_reg_40614;
reg [11:0] ap_reg_ppstg_phi_3_2_V_read_1_reg_40614_pp0_iter1;
reg [11:0] phi_3_1_V_read_1_reg_40621;
reg [11:0] ap_reg_ppstg_phi_3_1_V_read_1_reg_40621_pp0_iter1;
reg [11:0] phi_3_0_V_read_1_reg_40628;
reg [11:0] ap_reg_ppstg_phi_3_0_V_read_1_reg_40628_pp0_iter1;
reg [11:0] phi_2_2_V_read_1_reg_40635;
reg [11:0] ap_reg_ppstg_phi_2_2_V_read_1_reg_40635_pp0_iter1;
reg [11:0] phi_2_1_V_read_1_reg_40642;
reg [11:0] ap_reg_ppstg_phi_2_1_V_read_1_reg_40642_pp0_iter1;
reg [11:0] phi_2_0_V_read_1_reg_40649;
reg [11:0] ap_reg_ppstg_phi_2_0_V_read_1_reg_40649_pp0_iter1;
reg [11:0] phi_1_2_V_read_1_reg_40656;
reg [11:0] ap_reg_ppstg_phi_1_2_V_read_1_reg_40656_pp0_iter1;
reg [11:0] phi_1_1_V_read_1_reg_40663;
reg [11:0] ap_reg_ppstg_phi_1_1_V_read_1_reg_40663_pp0_iter1;
reg [11:0] phi_1_0_V_read_1_reg_40670;
reg [11:0] ap_reg_ppstg_phi_1_0_V_read_1_reg_40670_pp0_iter1;
reg [11:0] phi_0_2_V_read_1_reg_40677;
reg [11:0] ap_reg_ppstg_phi_0_2_V_read_1_reg_40677_pp0_iter1;
reg [11:0] phi_0_1_V_read_1_reg_40684;
reg [11:0] ap_reg_ppstg_phi_0_1_V_read_1_reg_40684_pp0_iter1;
reg [11:0] phi_0_0_V_read_1_reg_40691;
reg [11:0] ap_reg_ppstg_phi_0_0_V_read_1_reg_40691_pp0_iter1;
wire [0:0] tmp_fu_2562_p1;
reg [0:0] tmp_reg_40698;
reg [0:0] ap_reg_ppstg_tmp_reg_40698_pp0_iter1;
reg [1:0] tmp_231_reg_40703;
reg [1:0] ap_reg_ppstg_tmp_231_reg_40703_pp0_iter1;
reg [0:0] tmp_1150_reg_40708;
reg [0:0] ap_reg_ppstg_tmp_1150_reg_40708_pp0_iter1;
reg [0:0] tmp_1164_reg_40715;
reg [0:0] ap_reg_ppstg_tmp_1164_reg_40715_pp0_iter1;
reg [0:0] tmp_1167_reg_40722;
reg [0:0] ap_reg_ppstg_tmp_1167_reg_40722_pp0_iter1;
reg [0:0] tmp_1169_reg_40729;
reg [0:0] ap_reg_ppstg_tmp_1169_reg_40729_pp0_iter1;
reg [0:0] tmp_1170_reg_40736;
reg [0:0] ap_reg_ppstg_tmp_1170_reg_40736_pp0_iter1;
reg [0:0] tmp_1172_reg_40743;
reg [0:0] ap_reg_ppstg_tmp_1172_reg_40743_pp0_iter1;
reg [0:0] tmp_1173_reg_40750;
reg [0:0] ap_reg_ppstg_tmp_1173_reg_40750_pp0_iter1;
reg [0:0] tmp_1188_reg_40757;
reg [0:0] ap_reg_ppstg_tmp_1188_reg_40757_pp0_iter1;
reg [0:0] tmp_1190_reg_40764;
reg [0:0] ap_reg_ppstg_tmp_1190_reg_40764_pp0_iter1;
reg [0:0] tmp_1191_reg_40771;
reg [0:0] ap_reg_ppstg_tmp_1191_reg_40771_pp0_iter1;
reg [0:0] tmp_1193_reg_40778;
reg [0:0] ap_reg_ppstg_tmp_1193_reg_40778_pp0_iter1;
reg [0:0] tmp_1195_reg_40785;
reg [0:0] ap_reg_ppstg_tmp_1195_reg_40785_pp0_iter1;
reg [0:0] tmp_1197_reg_40792;
reg [0:0] ap_reg_ppstg_tmp_1197_reg_40792_pp0_iter1;
reg [0:0] tmp_1199_reg_40799;
reg [0:0] ap_reg_ppstg_tmp_1199_reg_40799_pp0_iter1;
reg [0:0] tmp_1212_reg_40806;
reg [0:0] ap_reg_ppstg_tmp_1212_reg_40806_pp0_iter1;
reg [0:0] tmp_1216_reg_40813;
reg [0:0] ap_reg_ppstg_tmp_1216_reg_40813_pp0_iter1;
reg [0:0] tmp_1217_reg_40820;
reg [0:0] ap_reg_ppstg_tmp_1217_reg_40820_pp0_iter1;
reg [0:0] tmp_1219_reg_40827;
reg [0:0] ap_reg_ppstg_tmp_1219_reg_40827_pp0_iter1;
reg [0:0] tmp_1222_reg_40834;
reg [0:0] ap_reg_ppstg_tmp_1222_reg_40834_pp0_iter1;
reg [0:0] tmp_1236_reg_40841;
reg [0:0] ap_reg_ppstg_tmp_1236_reg_40841_pp0_iter1;
reg [0:0] tmp_1239_reg_40848;
reg [0:0] ap_reg_ppstg_tmp_1239_reg_40848_pp0_iter1;
reg [0:0] tmp_1253_reg_40855;
reg [0:0] ap_reg_ppstg_tmp_1253_reg_40855_pp0_iter1;
wire [35:0] winner_V1_fu_8658_p3;
reg [35:0] winner_V1_reg_40862;
wire [0:0] tmp_1402_1_fu_9302_p2;
reg [0:0] tmp_1402_1_reg_40869;
wire [6:0] tmp_335_fu_9332_p2;
reg [6:0] tmp_335_reg_40874;
wire [5:0] tmp_1623_fu_9338_p1;
reg [5:0] tmp_1623_reg_40879;
wire [0:0] tmp_1402_2_fu_9978_p2;
reg [0:0] tmp_1402_2_reg_40884;
wire [2:0] tmp_1644_fu_9984_p1;
reg [2:0] tmp_1644_reg_40889;
wire [0:0] tmp_1402_3_fu_10624_p2;
reg [0:0] tmp_1402_3_reg_40895;
wire [2:0] tmp_1671_fu_10630_p1;
reg [2:0] tmp_1671_reg_40900;
wire [0:0] tmp_1402_4_fu_11270_p2;
reg [0:0] tmp_1402_4_reg_40906;
wire [2:0] tmp_1698_fu_11276_p1;
reg [2:0] tmp_1698_reg_40911;
wire [0:0] tmp_1402_5_fu_11916_p2;
reg [0:0] tmp_1402_5_reg_40917;
wire [2:0] tmp_1725_fu_11922_p1;
reg [2:0] tmp_1725_reg_40922;
wire [0:0] tmp_1402_6_fu_12562_p2;
reg [0:0] tmp_1402_6_reg_40928;
wire [2:0] tmp_1752_fu_12568_p1;
reg [2:0] tmp_1752_reg_40933;
wire [0:0] tmp_1402_7_fu_13208_p2;
reg [0:0] tmp_1402_7_reg_40939;
wire [2:0] tmp_1779_fu_13214_p1;
reg [2:0] tmp_1779_reg_40944;
wire [0:0] tmp_1402_8_fu_13854_p2;
reg [0:0] tmp_1402_8_reg_40950;
reg [0:0] ap_reg_ppstg_tmp_1402_8_reg_40950_pp0_iter1;
wire [2:0] tmp_1806_fu_13860_p1;
reg [2:0] tmp_1806_reg_40955;
reg [2:0] ap_reg_ppstg_tmp_1806_reg_40955_pp0_iter1;
wire [0:0] tmp_1402_9_fu_14500_p2;
reg [0:0] tmp_1402_9_reg_40961;
reg [0:0] ap_reg_ppstg_tmp_1402_9_reg_40961_pp0_iter1;
wire [2:0] tmp_1833_fu_14506_p1;
reg [2:0] tmp_1833_reg_40966;
reg [2:0] ap_reg_ppstg_tmp_1833_reg_40966_pp0_iter1;
wire [0:0] tmp_1402_s_fu_15146_p2;
reg [0:0] tmp_1402_s_reg_40972;
reg [0:0] ap_reg_ppstg_tmp_1402_s_reg_40972_pp0_iter1;
wire [2:0] tmp_1860_fu_15152_p1;
reg [2:0] tmp_1860_reg_40977;
reg [2:0] ap_reg_ppstg_tmp_1860_reg_40977_pp0_iter1;
wire [0:0] tmp_1402_10_fu_15792_p2;
reg [0:0] tmp_1402_10_reg_40983;
reg [0:0] ap_reg_ppstg_tmp_1402_10_reg_40983_pp0_iter1;
wire [2:0] tmp_1887_fu_15798_p1;
reg [2:0] tmp_1887_reg_40988;
reg [2:0] ap_reg_ppstg_tmp_1887_reg_40988_pp0_iter1;
wire [0:0] tmp_1905_fu_15802_p1;
reg [0:0] tmp_1905_reg_40994;
reg [0:0] ap_reg_ppstg_tmp_1905_reg_40994_pp0_iter1;
wire [0:0] tmp_1907_fu_15806_p1;
reg [0:0] tmp_1907_reg_41001;
reg [0:0] ap_reg_ppstg_tmp_1907_reg_41001_pp0_iter1;
reg [0:0] tmp_1909_reg_41008;
reg [0:0] ap_reg_ppstg_tmp_1909_reg_41008_pp0_iter1;
reg [0:0] tmp_1911_reg_41015;
reg [0:0] ap_reg_ppstg_tmp_1911_reg_41015_pp0_iter1;
reg [0:0] tmp_1913_reg_41022;
reg [0:0] ap_reg_ppstg_tmp_1913_reg_41022_pp0_iter1;
reg [0:0] tmp_1915_reg_41029;
reg [0:0] ap_reg_ppstg_tmp_1915_reg_41029_pp0_iter1;
reg [0:0] tmp_1917_reg_41036;
reg [0:0] ap_reg_ppstg_tmp_1917_reg_41036_pp0_iter1;
reg [0:0] tmp_1919_reg_41043;
reg [0:0] ap_reg_ppstg_tmp_1919_reg_41043_pp0_iter1;
reg [0:0] tmp_1921_reg_41050;
reg [0:0] ap_reg_ppstg_tmp_1921_reg_41050_pp0_iter1;
reg [0:0] tmp_1923_reg_41057;
reg [0:0] ap_reg_ppstg_tmp_1923_reg_41057_pp0_iter1;
reg [0:0] tmp_1925_reg_41064;
reg [0:0] ap_reg_ppstg_tmp_1925_reg_41064_pp0_iter1;
reg [0:0] tmp_1927_reg_41071;
reg [0:0] ap_reg_ppstg_tmp_1927_reg_41071_pp0_iter1;
wire [0:0] tmp_1929_fu_15890_p1;
reg [0:0] tmp_1929_reg_41078;
reg [0:0] ap_reg_ppstg_tmp_1929_reg_41078_pp0_iter1;
wire [0:0] tmp_1936_fu_15894_p1;
reg [0:0] tmp_1936_reg_41085;
reg [0:0] ap_reg_ppstg_tmp_1936_reg_41085_pp0_iter1;
wire [0:0] tmp_1938_fu_15898_p1;
reg [0:0] tmp_1938_reg_41092;
reg [0:0] ap_reg_ppstg_tmp_1938_reg_41092_pp0_iter1;
reg [0:0] tmp_1940_reg_41099;
reg [0:0] ap_reg_ppstg_tmp_1940_reg_41099_pp0_iter1;
reg [0:0] tmp_1942_reg_41106;
reg [0:0] ap_reg_ppstg_tmp_1942_reg_41106_pp0_iter1;
reg [0:0] tmp_1944_reg_41113;
reg [0:0] ap_reg_ppstg_tmp_1944_reg_41113_pp0_iter1;
reg [0:0] tmp_1946_reg_41120;
reg [0:0] ap_reg_ppstg_tmp_1946_reg_41120_pp0_iter1;
reg [0:0] tmp_1948_reg_41127;
reg [0:0] ap_reg_ppstg_tmp_1948_reg_41127_pp0_iter1;
reg [0:0] tmp_1950_reg_41134;
reg [0:0] ap_reg_ppstg_tmp_1950_reg_41134_pp0_iter1;
reg [0:0] tmp_1952_reg_41141;
reg [0:0] ap_reg_ppstg_tmp_1952_reg_41141_pp0_iter1;
reg [0:0] tmp_1954_reg_41148;
reg [0:0] ap_reg_ppstg_tmp_1954_reg_41148_pp0_iter1;
reg [0:0] tmp_1956_reg_41155;
reg [0:0] ap_reg_ppstg_tmp_1956_reg_41155_pp0_iter1;
reg [0:0] tmp_1958_reg_41162;
reg [0:0] ap_reg_ppstg_tmp_1958_reg_41162_pp0_iter1;
wire [0:0] tmp_1960_fu_15982_p1;
reg [0:0] tmp_1960_reg_41169;
reg [0:0] ap_reg_ppstg_tmp_1960_reg_41169_pp0_iter1;
wire [0:0] tmp_1966_fu_15986_p1;
reg [0:0] tmp_1966_reg_41176;
reg [0:0] ap_reg_ppstg_tmp_1966_reg_41176_pp0_iter1;
wire [0:0] tmp_1968_fu_15990_p1;
reg [0:0] tmp_1968_reg_41183;
reg [0:0] ap_reg_ppstg_tmp_1968_reg_41183_pp0_iter1;
reg [0:0] tmp_1970_reg_41190;
reg [0:0] ap_reg_ppstg_tmp_1970_reg_41190_pp0_iter1;
reg [0:0] tmp_1972_reg_41197;
reg [0:0] ap_reg_ppstg_tmp_1972_reg_41197_pp0_iter1;
reg [0:0] tmp_1974_reg_41204;
reg [0:0] ap_reg_ppstg_tmp_1974_reg_41204_pp0_iter1;
reg [0:0] tmp_1976_reg_41211;
reg [0:0] ap_reg_ppstg_tmp_1976_reg_41211_pp0_iter1;
reg [0:0] tmp_1978_reg_41218;
reg [0:0] ap_reg_ppstg_tmp_1978_reg_41218_pp0_iter1;
reg [0:0] tmp_1980_reg_41225;
reg [0:0] ap_reg_ppstg_tmp_1980_reg_41225_pp0_iter1;
reg [0:0] tmp_1982_reg_41232;
reg [0:0] ap_reg_ppstg_tmp_1982_reg_41232_pp0_iter1;
reg [0:0] tmp_1984_reg_41239;
reg [0:0] ap_reg_ppstg_tmp_1984_reg_41239_pp0_iter1;
reg [0:0] tmp_1986_reg_41246;
reg [0:0] ap_reg_ppstg_tmp_1986_reg_41246_pp0_iter1;
reg [0:0] tmp_1988_reg_41253;
reg [0:0] ap_reg_ppstg_tmp_1988_reg_41253_pp0_iter1;
wire [0:0] tmp_1990_fu_16074_p1;
reg [0:0] tmp_1990_reg_41260;
reg [0:0] ap_reg_ppstg_tmp_1990_reg_41260_pp0_iter1;
wire [0:0] tmp_2008_fu_16078_p1;
reg [0:0] tmp_2008_reg_41267;
reg [0:0] ap_reg_ppstg_tmp_2008_reg_41267_pp0_iter1;
wire [0:0] tmp_2010_fu_16082_p1;
reg [0:0] tmp_2010_reg_41274;
reg [0:0] ap_reg_ppstg_tmp_2010_reg_41274_pp0_iter1;
reg [0:0] tmp_2012_reg_41281;
reg [0:0] ap_reg_ppstg_tmp_2012_reg_41281_pp0_iter1;
reg [0:0] tmp_2014_reg_41288;
reg [0:0] ap_reg_ppstg_tmp_2014_reg_41288_pp0_iter1;
reg [0:0] tmp_2016_reg_41295;
reg [0:0] ap_reg_ppstg_tmp_2016_reg_41295_pp0_iter1;
reg [0:0] tmp_2018_reg_41302;
reg [0:0] ap_reg_ppstg_tmp_2018_reg_41302_pp0_iter1;
reg [0:0] tmp_2020_reg_41309;
reg [0:0] ap_reg_ppstg_tmp_2020_reg_41309_pp0_iter1;
reg [0:0] tmp_2022_reg_41316;
reg [0:0] ap_reg_ppstg_tmp_2022_reg_41316_pp0_iter1;
reg [0:0] tmp_2024_reg_41323;
reg [0:0] ap_reg_ppstg_tmp_2024_reg_41323_pp0_iter1;
reg [0:0] tmp_2026_reg_41330;
reg [0:0] ap_reg_ppstg_tmp_2026_reg_41330_pp0_iter1;
reg [0:0] tmp_2028_reg_41337;
reg [0:0] ap_reg_ppstg_tmp_2028_reg_41337_pp0_iter1;
reg [0:0] tmp_2030_reg_41344;
reg [0:0] ap_reg_ppstg_tmp_2030_reg_41344_pp0_iter1;
wire [0:0] tmp_2034_fu_16166_p1;
reg [0:0] tmp_2034_reg_41351;
reg [0:0] ap_reg_ppstg_tmp_2034_reg_41351_pp0_iter1;
wire [0:0] tmp_2040_fu_16170_p1;
reg [0:0] tmp_2040_reg_41358;
reg [0:0] ap_reg_ppstg_tmp_2040_reg_41358_pp0_iter1;
wire [0:0] tmp_2042_fu_16174_p1;
reg [0:0] tmp_2042_reg_41365;
reg [0:0] ap_reg_ppstg_tmp_2042_reg_41365_pp0_iter1;
reg [0:0] tmp_2044_reg_41372;
reg [0:0] ap_reg_ppstg_tmp_2044_reg_41372_pp0_iter1;
reg [0:0] tmp_2046_reg_41379;
reg [0:0] ap_reg_ppstg_tmp_2046_reg_41379_pp0_iter1;
reg [0:0] tmp_2048_reg_41386;
reg [0:0] ap_reg_ppstg_tmp_2048_reg_41386_pp0_iter1;
reg [0:0] tmp_2050_reg_41393;
reg [0:0] ap_reg_ppstg_tmp_2050_reg_41393_pp0_iter1;
reg [0:0] tmp_2052_reg_41400;
reg [0:0] ap_reg_ppstg_tmp_2052_reg_41400_pp0_iter1;
reg [0:0] tmp_2054_reg_41407;
reg [0:0] ap_reg_ppstg_tmp_2054_reg_41407_pp0_iter1;
reg [0:0] tmp_2056_reg_41414;
reg [0:0] ap_reg_ppstg_tmp_2056_reg_41414_pp0_iter1;
reg [0:0] tmp_2058_reg_41421;
reg [0:0] ap_reg_ppstg_tmp_2058_reg_41421_pp0_iter1;
reg [0:0] tmp_2060_reg_41428;
reg [0:0] ap_reg_ppstg_tmp_2060_reg_41428_pp0_iter1;
reg [0:0] tmp_2062_reg_41435;
reg [0:0] ap_reg_ppstg_tmp_2062_reg_41435_pp0_iter1;
wire [0:0] tmp_2065_fu_16258_p1;
reg [0:0] tmp_2065_reg_41442;
reg [0:0] ap_reg_ppstg_tmp_2065_reg_41442_pp0_iter1;
wire [0:0] tmp_2073_fu_16262_p1;
reg [0:0] tmp_2073_reg_41449;
reg [0:0] ap_reg_ppstg_tmp_2073_reg_41449_pp0_iter1;
wire [0:0] tmp_2075_fu_16266_p1;
reg [0:0] tmp_2075_reg_41456;
reg [0:0] ap_reg_ppstg_tmp_2075_reg_41456_pp0_iter1;
reg [0:0] tmp_2077_reg_41463;
reg [0:0] ap_reg_ppstg_tmp_2077_reg_41463_pp0_iter1;
reg [0:0] tmp_2079_reg_41470;
reg [0:0] ap_reg_ppstg_tmp_2079_reg_41470_pp0_iter1;
reg [0:0] tmp_2081_reg_41477;
reg [0:0] ap_reg_ppstg_tmp_2081_reg_41477_pp0_iter1;
reg [0:0] tmp_2083_reg_41484;
reg [0:0] ap_reg_ppstg_tmp_2083_reg_41484_pp0_iter1;
reg [0:0] tmp_2085_reg_41491;
reg [0:0] ap_reg_ppstg_tmp_2085_reg_41491_pp0_iter1;
reg [0:0] tmp_2087_reg_41498;
reg [0:0] ap_reg_ppstg_tmp_2087_reg_41498_pp0_iter1;
reg [0:0] tmp_2089_reg_41505;
reg [0:0] ap_reg_ppstg_tmp_2089_reg_41505_pp0_iter1;
reg [0:0] tmp_2091_reg_41512;
reg [0:0] ap_reg_ppstg_tmp_2091_reg_41512_pp0_iter1;
reg [0:0] tmp_2093_reg_41519;
reg [0:0] ap_reg_ppstg_tmp_2093_reg_41519_pp0_iter1;
reg [0:0] tmp_2095_reg_41526;
reg [0:0] ap_reg_ppstg_tmp_2095_reg_41526_pp0_iter1;
wire [0:0] tmp_2097_fu_16350_p1;
reg [0:0] tmp_2097_reg_41533;
reg [0:0] ap_reg_ppstg_tmp_2097_reg_41533_pp0_iter1;
wire [0:0] tmp_2103_fu_16354_p1;
reg [0:0] tmp_2103_reg_41540;
reg [0:0] ap_reg_ppstg_tmp_2103_reg_41540_pp0_iter1;
wire [0:0] tmp_2105_fu_16358_p1;
reg [0:0] tmp_2105_reg_41547;
reg [0:0] ap_reg_ppstg_tmp_2105_reg_41547_pp0_iter1;
reg [0:0] tmp_2107_reg_41554;
reg [0:0] ap_reg_ppstg_tmp_2107_reg_41554_pp0_iter1;
reg [0:0] tmp_2109_reg_41561;
reg [0:0] ap_reg_ppstg_tmp_2109_reg_41561_pp0_iter1;
reg [0:0] tmp_2111_reg_41568;
reg [0:0] ap_reg_ppstg_tmp_2111_reg_41568_pp0_iter1;
reg [0:0] tmp_2113_reg_41575;
reg [0:0] ap_reg_ppstg_tmp_2113_reg_41575_pp0_iter1;
reg [0:0] tmp_2115_reg_41582;
reg [0:0] ap_reg_ppstg_tmp_2115_reg_41582_pp0_iter1;
reg [0:0] tmp_2117_reg_41589;
reg [0:0] ap_reg_ppstg_tmp_2117_reg_41589_pp0_iter1;
reg [0:0] tmp_2119_reg_41596;
reg [0:0] ap_reg_ppstg_tmp_2119_reg_41596_pp0_iter1;
reg [0:0] tmp_2121_reg_41603;
reg [0:0] ap_reg_ppstg_tmp_2121_reg_41603_pp0_iter1;
reg [0:0] tmp_2123_reg_41610;
reg [0:0] ap_reg_ppstg_tmp_2123_reg_41610_pp0_iter1;
reg [0:0] tmp_2125_reg_41617;
reg [0:0] ap_reg_ppstg_tmp_2125_reg_41617_pp0_iter1;
wire [0:0] tmp_2127_fu_16442_p1;
reg [0:0] tmp_2127_reg_41624;
reg [0:0] ap_reg_ppstg_tmp_2127_reg_41624_pp0_iter1;
wire [0:0] tmp_2143_fu_16446_p1;
reg [0:0] tmp_2143_reg_41631;
reg [0:0] ap_reg_ppstg_tmp_2143_reg_41631_pp0_iter1;
wire [0:0] tmp_2145_fu_16450_p1;
reg [0:0] tmp_2145_reg_41638;
reg [0:0] ap_reg_ppstg_tmp_2145_reg_41638_pp0_iter1;
reg [0:0] tmp_2147_reg_41645;
reg [0:0] ap_reg_ppstg_tmp_2147_reg_41645_pp0_iter1;
reg [0:0] tmp_2149_reg_41652;
reg [0:0] ap_reg_ppstg_tmp_2149_reg_41652_pp0_iter1;
reg [0:0] tmp_2151_reg_41659;
reg [0:0] ap_reg_ppstg_tmp_2151_reg_41659_pp0_iter1;
reg [0:0] tmp_2153_reg_41666;
reg [0:0] ap_reg_ppstg_tmp_2153_reg_41666_pp0_iter1;
reg [0:0] tmp_2155_reg_41673;
reg [0:0] ap_reg_ppstg_tmp_2155_reg_41673_pp0_iter1;
reg [0:0] tmp_2157_reg_41680;
reg [0:0] ap_reg_ppstg_tmp_2157_reg_41680_pp0_iter1;
reg [0:0] tmp_2159_reg_41687;
reg [0:0] ap_reg_ppstg_tmp_2159_reg_41687_pp0_iter1;
reg [0:0] tmp_2161_reg_41694;
reg [0:0] ap_reg_ppstg_tmp_2161_reg_41694_pp0_iter1;
reg [0:0] tmp_2163_reg_41701;
reg [0:0] ap_reg_ppstg_tmp_2163_reg_41701_pp0_iter1;
reg [0:0] tmp_2165_reg_41708;
reg [0:0] ap_reg_ppstg_tmp_2165_reg_41708_pp0_iter1;
wire [0:0] tmp_2168_fu_16534_p1;
reg [0:0] tmp_2168_reg_41715;
reg [0:0] ap_reg_ppstg_tmp_2168_reg_41715_pp0_iter1;
wire [0:0] tmp_2174_fu_16538_p1;
reg [0:0] tmp_2174_reg_41722;
reg [0:0] ap_reg_ppstg_tmp_2174_reg_41722_pp0_iter1;
wire [0:0] tmp_2176_fu_16542_p1;
reg [0:0] tmp_2176_reg_41729;
reg [0:0] ap_reg_ppstg_tmp_2176_reg_41729_pp0_iter1;
reg [0:0] tmp_2178_reg_41736;
reg [0:0] ap_reg_ppstg_tmp_2178_reg_41736_pp0_iter1;
reg [0:0] tmp_2180_reg_41743;
reg [0:0] ap_reg_ppstg_tmp_2180_reg_41743_pp0_iter1;
reg [0:0] tmp_2182_reg_41750;
reg [0:0] ap_reg_ppstg_tmp_2182_reg_41750_pp0_iter1;
reg [0:0] tmp_2184_reg_41757;
reg [0:0] ap_reg_ppstg_tmp_2184_reg_41757_pp0_iter1;
reg [0:0] tmp_2186_reg_41764;
reg [0:0] ap_reg_ppstg_tmp_2186_reg_41764_pp0_iter1;
reg [0:0] tmp_2188_reg_41771;
reg [0:0] ap_reg_ppstg_tmp_2188_reg_41771_pp0_iter1;
reg [0:0] tmp_2190_reg_41778;
reg [0:0] ap_reg_ppstg_tmp_2190_reg_41778_pp0_iter1;
reg [0:0] tmp_2192_reg_41785;
reg [0:0] ap_reg_ppstg_tmp_2192_reg_41785_pp0_iter1;
reg [0:0] tmp_2194_reg_41792;
reg [0:0] ap_reg_ppstg_tmp_2194_reg_41792_pp0_iter1;
reg [0:0] tmp_2196_reg_41799;
reg [0:0] ap_reg_ppstg_tmp_2196_reg_41799_pp0_iter1;
wire [0:0] tmp_2199_fu_16626_p1;
reg [0:0] tmp_2199_reg_41806;
reg [0:0] ap_reg_ppstg_tmp_2199_reg_41806_pp0_iter1;
wire [0:0] tmp_2207_fu_16630_p1;
reg [0:0] tmp_2207_reg_41813;
reg [0:0] ap_reg_ppstg_tmp_2207_reg_41813_pp0_iter1;
wire [0:0] tmp_2209_fu_16634_p1;
reg [0:0] tmp_2209_reg_41820;
reg [0:0] ap_reg_ppstg_tmp_2209_reg_41820_pp0_iter1;
reg [0:0] tmp_2211_reg_41827;
reg [0:0] ap_reg_ppstg_tmp_2211_reg_41827_pp0_iter1;
reg [0:0] tmp_2213_reg_41834;
reg [0:0] ap_reg_ppstg_tmp_2213_reg_41834_pp0_iter1;
reg [0:0] tmp_2215_reg_41841;
reg [0:0] ap_reg_ppstg_tmp_2215_reg_41841_pp0_iter1;
reg [0:0] tmp_2217_reg_41848;
reg [0:0] ap_reg_ppstg_tmp_2217_reg_41848_pp0_iter1;
reg [0:0] tmp_2219_reg_41855;
reg [0:0] ap_reg_ppstg_tmp_2219_reg_41855_pp0_iter1;
reg [0:0] tmp_2221_reg_41862;
reg [0:0] ap_reg_ppstg_tmp_2221_reg_41862_pp0_iter1;
reg [0:0] tmp_2223_reg_41869;
reg [0:0] ap_reg_ppstg_tmp_2223_reg_41869_pp0_iter1;
reg [0:0] tmp_2225_reg_41876;
reg [0:0] ap_reg_ppstg_tmp_2225_reg_41876_pp0_iter1;
reg [0:0] tmp_2227_reg_41883;
reg [0:0] ap_reg_ppstg_tmp_2227_reg_41883_pp0_iter1;
reg [0:0] tmp_2229_reg_41890;
reg [0:0] ap_reg_ppstg_tmp_2229_reg_41890_pp0_iter1;
wire [0:0] tmp_2231_fu_16718_p1;
reg [0:0] tmp_2231_reg_41897;
reg [0:0] ap_reg_ppstg_tmp_2231_reg_41897_pp0_iter1;
wire [0:0] tmp_2237_fu_16722_p1;
reg [0:0] tmp_2237_reg_41904;
reg [0:0] ap_reg_ppstg_tmp_2237_reg_41904_pp0_iter1;
wire [0:0] tmp_2239_fu_16726_p1;
reg [0:0] tmp_2239_reg_41911;
reg [0:0] ap_reg_ppstg_tmp_2239_reg_41911_pp0_iter1;
reg [0:0] tmp_2241_reg_41918;
reg [0:0] ap_reg_ppstg_tmp_2241_reg_41918_pp0_iter1;
reg [0:0] tmp_2243_reg_41925;
reg [0:0] ap_reg_ppstg_tmp_2243_reg_41925_pp0_iter1;
reg [0:0] tmp_2245_reg_41932;
reg [0:0] ap_reg_ppstg_tmp_2245_reg_41932_pp0_iter1;
reg [0:0] tmp_2247_reg_41939;
reg [0:0] ap_reg_ppstg_tmp_2247_reg_41939_pp0_iter1;
reg [0:0] tmp_2249_reg_41946;
reg [0:0] ap_reg_ppstg_tmp_2249_reg_41946_pp0_iter1;
reg [0:0] tmp_2251_reg_41953;
reg [0:0] ap_reg_ppstg_tmp_2251_reg_41953_pp0_iter1;
reg [0:0] tmp_2253_reg_41960;
reg [0:0] ap_reg_ppstg_tmp_2253_reg_41960_pp0_iter1;
reg [0:0] tmp_2255_reg_41967;
reg [0:0] ap_reg_ppstg_tmp_2255_reg_41967_pp0_iter1;
reg [0:0] tmp_2257_reg_41974;
reg [0:0] ap_reg_ppstg_tmp_2257_reg_41974_pp0_iter1;
reg [0:0] tmp_2259_reg_41981;
reg [0:0] ap_reg_ppstg_tmp_2259_reg_41981_pp0_iter1;
wire [0:0] tmp_2261_fu_16810_p1;
reg [0:0] tmp_2261_reg_41988;
reg [0:0] ap_reg_ppstg_tmp_2261_reg_41988_pp0_iter1;
wire [35:0] winner_V_7_fu_17481_p3;
reg [35:0] winner_V_7_reg_41995;
wire [0:0] tmp_1339_0_1_fu_2752_p2;
wire [1:0] p_cast_fu_2758_p3;
wire [2:0] tmp_1256_fu_2780_p3;
wire [0:0] tmp_1339_0_2_fu_2774_p2;
wire [11:0] p_cast_cast_fu_2766_p3;
wire [11:0] p_Result_1247_0_2_fu_2788_p1;
wire [11:0] p_Val2_388_0_3_fu_2792_p3;
wire [0:0] tmp_1339_0_3_fu_2800_p2;
reg [11:0] tmp_1258_fu_2806_p4;
wire [11:0] p_Val2_388_0_4_fu_2816_p3;
wire [0:0] tmp_1339_0_4_fu_2824_p2;
reg [11:0] tmp_1259_fu_2830_p4;
wire [11:0] p_Val2_388_0_5_fu_2840_p3;
wire [0:0] tmp_1339_0_5_fu_2848_p2;
reg [11:0] tmp_1272_fu_2854_p4;
wire [11:0] p_Val2_388_0_6_fu_2864_p3;
wire [0:0] tmp_1339_0_6_fu_2872_p2;
reg [11:0] tmp_1276_fu_2878_p4;
wire [11:0] p_Val2_388_0_7_fu_2888_p3;
wire [0:0] tmp_1339_0_7_fu_2896_p2;
reg [11:0] tmp_1277_fu_2902_p4;
wire [11:0] p_Val2_388_0_8_fu_2912_p3;
wire [0:0] tmp_1339_0_8_fu_2920_p2;
reg [11:0] tmp_1279_fu_2926_p4;
wire [11:0] p_Val2_388_0_9_fu_2936_p3;
wire [0:0] tmp_1339_0_9_fu_2944_p2;
reg [11:0] tmp_1281_fu_2950_p4;
wire [11:0] p_Val2_388_0_s_fu_2960_p3;
wire [0:0] tmp_1339_0_s_fu_2968_p2;
reg [11:0] tmp_1283_fu_2974_p4;
wire [11:0] p_Val2_388_0_1_fu_2984_p3;
wire [0:0] tmp_1339_0_10_fu_2992_p2;
reg [11:0] tmp_1285_fu_2998_p4;
wire [1:0] p_12_cast_fu_3022_p3;
wire [2:0] tmp_1298_fu_3044_p3;
wire [0:0] tmp_1339_1_2_fu_3038_p2;
wire [11:0] p_12_cast_cast_fu_3030_p3;
wire [11:0] p_Result_1247_1_2_fu_3052_p1;
wire [11:0] p_Val2_388_1_3_fu_3056_p3;
wire [0:0] tmp_1339_1_3_fu_3064_p2;
reg [11:0] tmp_1302_fu_3070_p4;
wire [11:0] p_Val2_388_1_4_fu_3080_p3;
wire [0:0] tmp_1339_1_4_fu_3088_p2;
reg [11:0] tmp_1303_fu_3094_p4;
wire [11:0] p_Val2_388_1_5_fu_3104_p3;
wire [0:0] tmp_1339_1_5_fu_3112_p2;
reg [11:0] tmp_1305_fu_3118_p4;
wire [11:0] p_Val2_388_1_6_fu_3128_p3;
wire [0:0] tmp_1339_1_6_fu_3136_p2;
reg [11:0] tmp_1308_fu_3142_p4;
wire [11:0] p_Val2_388_1_7_fu_3152_p3;
wire [0:0] tmp_1339_1_7_fu_3160_p2;
reg [11:0] tmp_1322_fu_3166_p4;
wire [11:0] p_Val2_388_1_8_fu_3176_p3;
wire [0:0] tmp_1339_1_8_fu_3184_p2;
reg [11:0] tmp_1325_fu_3190_p4;
wire [11:0] p_Val2_388_1_9_fu_3200_p3;
wire [0:0] tmp_1339_1_9_fu_3208_p2;
reg [11:0] tmp_1339_fu_3214_p4;
wire [11:0] p_Val2_388_1_s_fu_3224_p3;
wire [0:0] tmp_1339_1_s_fu_3232_p2;
reg [11:0] tmp_1342_fu_3238_p4;
wire [11:0] p_Val2_388_1_1_fu_3248_p3;
wire [0:0] tmp_1339_1_1_fu_3256_p2;
reg [11:0] tmp_1344_fu_3262_p4;
wire [11:0] p_13_cast_cast_fu_3286_p3;
reg [11:0] tmp_1345_fu_3294_p4;
wire [11:0] p_Val2_388_2_3_fu_3304_p3;
wire [0:0] tmp_1339_2_3_fu_3312_p2;
reg [11:0] tmp_1346_fu_3318_p4;
wire [11:0] p_Val2_388_2_4_fu_3328_p3;
wire [0:0] tmp_1339_2_4_fu_3336_p2;
reg [11:0] tmp_1347_fu_3342_p4;
wire [11:0] p_Val2_388_2_5_fu_3352_p3;
wire [0:0] tmp_1339_2_5_fu_3360_p2;
reg [11:0] tmp_1348_fu_3366_p4;
wire [11:0] p_Val2_388_2_6_fu_3376_p3;
wire [0:0] tmp_1339_2_6_fu_3384_p2;
reg [11:0] tmp_1349_fu_3390_p4;
wire [11:0] p_Val2_388_2_7_fu_3400_p3;
wire [0:0] tmp_1339_2_7_fu_3408_p2;
reg [11:0] tmp_1350_fu_3414_p4;
wire [11:0] p_Val2_388_2_8_fu_3424_p3;
wire [0:0] tmp_1339_2_8_fu_3432_p2;
reg [11:0] tmp_1351_fu_3438_p4;
wire [11:0] p_Val2_388_2_9_fu_3448_p3;
wire [0:0] tmp_1339_2_9_fu_3456_p2;
reg [11:0] tmp_1352_fu_3462_p4;
wire [11:0] p_Val2_388_2_s_fu_3472_p3;
wire [0:0] tmp_1339_2_s_fu_3480_p2;
reg [11:0] tmp_1353_fu_3486_p4;
wire [11:0] p_Val2_388_2_1_fu_3496_p3;
wire [0:0] tmp_1339_2_1_fu_3504_p2;
reg [11:0] tmp_1354_fu_3510_p4;
wire [11:0] p_14_cast_cast_fu_3534_p3;
reg [11:0] tmp_1355_fu_3542_p4;
wire [11:0] p_Val2_388_3_2_fu_3552_p3;
reg [11:0] tmp_1356_fu_3560_p4;
wire [11:0] p_Val2_388_3_4_fu_3570_p3;
wire [0:0] tmp_1339_3_4_fu_3578_p2;
reg [11:0] tmp_1357_fu_3584_p4;
wire [11:0] p_Val2_388_3_5_fu_3594_p3;
wire [0:0] tmp_1339_3_5_fu_3602_p2;
reg [11:0] tmp_1358_fu_3608_p4;
wire [11:0] p_Val2_388_3_6_fu_3618_p3;
wire [0:0] tmp_1339_3_6_fu_3626_p2;
reg [11:0] tmp_1359_fu_3632_p4;
wire [11:0] p_Val2_388_3_7_fu_3642_p3;
wire [0:0] tmp_1339_3_7_fu_3650_p2;
reg [11:0] tmp_1360_fu_3656_p4;
wire [11:0] p_Val2_388_3_8_fu_3666_p3;
wire [0:0] tmp_1339_3_8_fu_3674_p2;
reg [11:0] tmp_1361_fu_3680_p4;
wire [11:0] p_Val2_388_3_9_fu_3690_p3;
wire [0:0] tmp_1339_3_9_fu_3698_p2;
reg [11:0] tmp_1362_fu_3704_p4;
wire [11:0] p_Val2_388_3_s_fu_3714_p3;
wire [0:0] tmp_1339_3_s_fu_3722_p2;
reg [11:0] tmp_1363_fu_3728_p4;
wire [11:0] p_Val2_388_3_1_fu_3738_p3;
wire [0:0] tmp_1339_3_1_fu_3746_p2;
reg [11:0] tmp_1364_fu_3752_p4;
wire [11:0] p_15_cast_cast_fu_3776_p3;
reg [11:0] tmp_1365_fu_3784_p4;
wire [11:0] p_Val2_388_4_2_fu_3794_p3;
reg [11:0] tmp_1366_fu_3802_p4;
wire [11:0] p_Val2_388_4_3_fu_3812_p3;
reg [11:0] tmp_1367_fu_3820_p4;
wire [11:0] p_Val2_388_4_5_fu_3830_p3;
wire [0:0] tmp_1339_4_5_fu_3838_p2;
reg [11:0] tmp_1368_fu_3844_p4;
wire [11:0] p_Val2_388_4_6_fu_3854_p3;
wire [0:0] tmp_1339_4_6_fu_3862_p2;
reg [11:0] tmp_1369_fu_3868_p4;
wire [11:0] p_Val2_388_4_7_fu_3878_p3;
wire [0:0] tmp_1339_4_7_fu_3886_p2;
reg [11:0] tmp_1370_fu_3892_p4;
wire [11:0] p_Val2_388_4_8_fu_3902_p3;
wire [0:0] tmp_1339_4_8_fu_3910_p2;
reg [11:0] tmp_1371_fu_3916_p4;
wire [11:0] p_Val2_388_4_9_fu_3926_p3;
wire [0:0] tmp_1339_4_9_fu_3934_p2;
reg [11:0] tmp_1372_fu_3940_p4;
wire [11:0] p_Val2_388_4_s_fu_3950_p3;
wire [0:0] tmp_1339_4_s_fu_3958_p2;
reg [11:0] tmp_1373_fu_3964_p4;
wire [11:0] p_Val2_388_4_1_fu_3974_p3;
wire [0:0] tmp_1339_4_1_fu_3982_p2;
reg [11:0] tmp_1374_fu_3988_p4;
wire [11:0] p_16_cast_cast_fu_4012_p3;
reg [11:0] tmp_1375_fu_4020_p4;
wire [11:0] p_Val2_388_5_2_fu_4030_p3;
reg [11:0] tmp_1376_fu_4038_p4;
wire [11:0] p_Val2_388_5_3_fu_4048_p3;
reg [11:0] tmp_1377_fu_4056_p4;
wire [11:0] p_Val2_388_5_4_fu_4066_p3;
reg [11:0] tmp_1378_fu_4074_p4;
wire [11:0] p_Val2_388_5_6_fu_4084_p3;
wire [0:0] tmp_1339_5_6_fu_4092_p2;
reg [11:0] tmp_1379_fu_4098_p4;
wire [11:0] p_Val2_388_5_7_fu_4108_p3;
wire [0:0] tmp_1339_5_7_fu_4116_p2;
reg [11:0] tmp_1380_fu_4122_p4;
wire [11:0] p_Val2_388_5_8_fu_4132_p3;
wire [0:0] tmp_1339_5_8_fu_4140_p2;
reg [11:0] tmp_1381_fu_4146_p4;
wire [11:0] p_Val2_388_5_9_fu_4156_p3;
wire [0:0] tmp_1339_5_9_fu_4164_p2;
reg [11:0] tmp_1382_fu_4170_p4;
wire [11:0] p_Val2_388_5_s_fu_4180_p3;
wire [0:0] tmp_1339_5_s_fu_4188_p2;
reg [11:0] tmp_1383_fu_4194_p4;
wire [11:0] p_Val2_388_5_1_fu_4204_p3;
wire [0:0] tmp_1339_5_1_fu_4212_p2;
reg [11:0] tmp_1384_fu_4218_p4;
wire [11:0] p_17_cast_cast_fu_4242_p3;
reg [11:0] tmp_1385_fu_4250_p4;
wire [11:0] p_Val2_388_6_2_fu_4260_p3;
reg [11:0] tmp_1386_fu_4268_p4;
wire [11:0] p_Val2_388_6_3_fu_4278_p3;
reg [11:0] tmp_1387_fu_4286_p4;
wire [11:0] p_Val2_388_6_4_fu_4296_p3;
reg [11:0] tmp_1388_fu_4304_p4;
wire [11:0] p_Val2_388_6_5_fu_4314_p3;
reg [11:0] tmp_1389_fu_4322_p4;
wire [11:0] p_Val2_388_6_7_fu_4332_p3;
wire [0:0] tmp_1339_6_7_fu_4340_p2;
reg [11:0] tmp_1390_fu_4346_p4;
wire [11:0] p_Val2_388_6_8_fu_4356_p3;
wire [0:0] tmp_1339_6_8_fu_4364_p2;
reg [11:0] tmp_1391_fu_4370_p4;
wire [11:0] p_Val2_388_6_9_fu_4380_p3;
wire [0:0] tmp_1339_6_9_fu_4388_p2;
reg [11:0] tmp_1392_fu_4394_p4;
wire [11:0] p_Val2_388_6_s_fu_4404_p3;
wire [0:0] tmp_1339_6_s_fu_4412_p2;
reg [11:0] tmp_1393_fu_4418_p4;
wire [11:0] p_Val2_388_6_1_fu_4428_p3;
wire [0:0] tmp_1339_6_1_fu_4436_p2;
reg [11:0] tmp_1394_fu_4442_p4;
wire [11:0] p_18_cast_cast_fu_4466_p3;
reg [11:0] tmp_1395_fu_4474_p4;
wire [11:0] p_Val2_388_7_2_fu_4484_p3;
reg [11:0] tmp_1396_fu_4492_p4;
wire [11:0] p_Val2_388_7_3_fu_4502_p3;
reg [11:0] tmp_1397_fu_4510_p4;
wire [11:0] p_Val2_388_7_4_fu_4520_p3;
reg [11:0] tmp_1398_fu_4528_p4;
wire [11:0] p_Val2_388_7_5_fu_4538_p3;
reg [11:0] tmp_1399_fu_4546_p4;
wire [11:0] p_Val2_388_7_6_fu_4556_p3;
reg [11:0] tmp_1400_fu_4564_p4;
wire [11:0] p_Val2_388_7_8_fu_4574_p3;
wire [0:0] tmp_1339_7_8_fu_4582_p2;
reg [11:0] tmp_1401_fu_4588_p4;
wire [11:0] p_Val2_388_7_9_fu_4598_p3;
wire [0:0] tmp_1339_7_9_fu_4606_p2;
reg [11:0] tmp_1402_fu_4612_p4;
wire [11:0] p_Val2_388_7_s_fu_4622_p3;
wire [0:0] tmp_1339_7_s_fu_4630_p2;
reg [11:0] tmp_1403_fu_4636_p4;
wire [11:0] p_Val2_388_7_1_fu_4646_p3;
wire [0:0] tmp_1339_7_1_fu_4654_p2;
reg [11:0] tmp_1404_fu_4660_p4;
wire [11:0] p_19_cast_cast_fu_4684_p3;
reg [11:0] tmp_1405_fu_4692_p4;
wire [11:0] p_Val2_388_8_2_fu_4702_p3;
reg [11:0] tmp_1406_fu_4710_p4;
wire [11:0] p_Val2_388_8_3_fu_4720_p3;
reg [11:0] tmp_1407_fu_4728_p4;
wire [11:0] p_Val2_388_8_4_fu_4738_p3;
reg [11:0] tmp_1408_fu_4746_p4;
wire [11:0] p_Val2_388_8_5_fu_4756_p3;
reg [11:0] tmp_1409_fu_4764_p4;
wire [11:0] p_Val2_388_8_6_fu_4774_p3;
reg [11:0] tmp_1410_fu_4782_p4;
wire [11:0] p_Val2_388_8_7_fu_4792_p3;
reg [11:0] tmp_1411_fu_4800_p4;
wire [11:0] p_Val2_388_8_9_fu_4810_p3;
wire [0:0] tmp_1339_8_9_fu_4818_p2;
reg [11:0] tmp_1412_fu_4824_p4;
wire [11:0] p_Val2_388_8_s_fu_4834_p3;
wire [0:0] tmp_1339_8_s_fu_4842_p2;
reg [11:0] tmp_1413_fu_4848_p4;
wire [11:0] p_Val2_388_8_1_fu_4858_p3;
wire [0:0] tmp_1339_8_1_fu_4866_p2;
reg [11:0] tmp_1414_fu_4872_p4;
wire [11:0] p_20_cast_cast_fu_4896_p3;
reg [11:0] larger_9_V_fu_4904_p4;
wire [11:0] larger_V_9_1_fu_4914_p3;
reg [11:0] larger_9_V_1_fu_4922_p4;
wire [11:0] larger_V_9_2_fu_4932_p3;
reg [11:0] larger_9_V_2_fu_4940_p4;
wire [11:0] larger_V_9_3_fu_4950_p3;
reg [11:0] larger_9_V_3_fu_4958_p4;
wire [11:0] larger_V_9_4_fu_4968_p3;
reg [11:0] larger_9_V_4_fu_4976_p4;
wire [11:0] larger_V_9_5_fu_4986_p3;
reg [11:0] larger_9_V_5_fu_4994_p4;
wire [11:0] larger_V_9_6_fu_5004_p3;
reg [11:0] larger_9_V_6_fu_5012_p4;
wire [11:0] larger_V_9_7_fu_5022_p3;
reg [11:0] larger_9_V_7_fu_5030_p4;
wire [11:0] larger_V_9_8_fu_5040_p3;
wire [0:0] tmp_1339_9_s_fu_5048_p2;
reg [11:0] larger_9_V_8_fu_5054_p4;
wire [11:0] larger_V_9_9_fu_5064_p3;
wire [0:0] tmp_1339_9_1_fu_5072_p2;
reg [11:0] larger_9_V_9_fu_5078_p4;
wire [11:0] p_21_cast_cast_fu_5102_p3;
reg [11:0] larger_10_V_fu_5110_p4;
wire [11:0] larger_V_10_1_fu_5120_p3;
reg [11:0] larger_10_V_1_fu_5128_p4;
wire [11:0] larger_V_10_2_fu_5138_p3;
reg [11:0] larger_10_V_2_fu_5146_p4;
wire [11:0] larger_V_10_3_fu_5156_p3;
reg [11:0] larger_10_V_3_fu_5164_p4;
wire [11:0] larger_V_10_4_fu_5174_p3;
reg [11:0] larger_10_V_4_fu_5182_p4;
wire [11:0] larger_V_10_5_fu_5192_p3;
reg [11:0] larger_10_V_5_fu_5200_p4;
wire [11:0] larger_V_10_6_fu_5210_p3;
reg [11:0] larger_10_V_6_fu_5218_p4;
wire [11:0] larger_V_10_7_fu_5228_p3;
reg [11:0] larger_10_V_7_fu_5236_p4;
wire [11:0] larger_V_10_8_fu_5246_p3;
reg [11:0] larger_10_V_8_fu_5254_p4;
wire [11:0] larger_V_10_9_fu_5264_p3;
wire [0:0] tmp_1339_10_s_fu_5272_p2;
reg [11:0] larger_10_V_9_fu_5278_p4;
wire [11:0] p_s_fu_5302_p3;
reg [11:0] larger_11_V_fu_5310_p4;
wire [11:0] larger_V_11_1_fu_5320_p3;
reg [11:0] larger_11_V_1_fu_5328_p4;
wire [11:0] larger_V_11_2_fu_5338_p3;
reg [11:0] larger_11_V_2_fu_5346_p4;
wire [11:0] larger_V_11_3_fu_5356_p3;
reg [11:0] larger_11_V_3_fu_5364_p4;
wire [11:0] larger_V_11_4_fu_5374_p3;
reg [11:0] larger_11_V_4_fu_5382_p4;
wire [11:0] larger_V_11_5_fu_5392_p3;
reg [11:0] larger_11_V_5_fu_5400_p4;
wire [11:0] larger_V_11_6_fu_5410_p3;
reg [11:0] larger_11_V_6_fu_5418_p4;
wire [11:0] larger_V_11_7_fu_5428_p3;
reg [11:0] larger_11_V_7_fu_5436_p4;
wire [11:0] larger_V_11_8_fu_5446_p3;
reg [11:0] larger_11_V_8_fu_5454_p4;
wire [11:0] larger_V_11_9_fu_5464_p3;
reg [11:0] larger_11_V_9_fu_5472_p4;
wire [0:0] tmp_1333_10_fu_5490_p2;
wire [0:0] tmp_1333_s_fu_5296_p2;
wire [0:0] tmp_1333_9_fu_5096_p2;
wire [0:0] tmp_1333_8_fu_4890_p2;
wire [0:0] tmp_1333_7_fu_4678_p2;
wire [0:0] tmp_1333_6_fu_4460_p2;
wire [0:0] tmp_1333_5_fu_4236_p2;
wire [0:0] tmp_1333_4_fu_4006_p2;
wire [0:0] tmp_1333_3_fu_3770_p2;
wire [0:0] tmp_1333_2_fu_3528_p2;
wire [0:0] tmp_1333_1_fu_3280_p2;
wire [0:0] tmp_s_fu_3016_p2;
wire [11:0] larger_V_load_fu_3008_p3;
wire [0:0] tmp_1445_fu_5524_p3;
wire [0:0] tmp_1446_fu_5540_p3;
wire [0:0] tmp_1447_fu_5556_p3;
wire [0:0] tmp_1448_fu_5572_p3;
wire [0:0] tmp_1449_fu_5588_p3;
wire [0:0] tmp_1450_fu_5604_p3;
wire [0:0] tmp_1451_fu_5620_p3;
wire [0:0] tmp_1452_fu_5636_p3;
wire [0:0] tmp_1453_fu_5652_p3;
wire [0:0] tmp_1454_fu_5668_p3;
wire [0:0] tmp_1455_fu_5684_p3;
wire [11:0] p_Val2_393_1_fu_3272_p3;
wire [0:0] tmp_1456_fu_5700_p3;
wire [0:0] tmp_1457_fu_5716_p3;
wire [0:0] tmp_1458_fu_5732_p3;
wire [0:0] tmp_1459_fu_5748_p3;
wire [0:0] tmp_1460_fu_5764_p3;
wire [0:0] tmp_1461_fu_5780_p3;
wire [0:0] tmp_1462_fu_5796_p3;
wire [0:0] tmp_1463_fu_5812_p3;
wire [0:0] tmp_1464_fu_5828_p3;
wire [0:0] tmp_1465_fu_5844_p3;
wire [11:0] p_Val2_393_2_fu_3520_p3;
wire [0:0] tmp_1466_fu_5860_p3;
wire [0:0] tmp_1467_fu_5876_p3;
wire [0:0] tmp_1468_fu_5892_p3;
wire [0:0] tmp_1469_fu_5908_p3;
wire [0:0] tmp_1470_fu_5924_p3;
wire [0:0] tmp_1471_fu_5940_p3;
wire [0:0] tmp_1472_fu_5956_p3;
wire [0:0] tmp_1473_fu_5972_p3;
wire [0:0] tmp_1474_fu_5988_p3;
wire [11:0] p_Val2_393_3_fu_3762_p3;
wire [0:0] tmp_1475_fu_6004_p3;
wire [0:0] tmp_1476_fu_6020_p3;
wire [0:0] tmp_1477_fu_6036_p3;
wire [0:0] tmp_1478_fu_6052_p3;
wire [0:0] tmp_1479_fu_6068_p3;
wire [0:0] tmp_1480_fu_6084_p3;
wire [0:0] tmp_1481_fu_6100_p3;
wire [0:0] tmp_1482_fu_6116_p3;
wire [11:0] p_Val2_393_4_fu_3998_p3;
wire [0:0] tmp_1483_fu_6132_p3;
wire [0:0] tmp_1484_fu_6148_p3;
wire [0:0] tmp_1485_fu_6164_p3;
wire [0:0] tmp_1486_fu_6180_p3;
wire [0:0] tmp_1487_fu_6196_p3;
wire [0:0] tmp_1488_fu_6212_p3;
wire [0:0] tmp_1489_fu_6228_p3;
wire [11:0] p_Val2_393_5_fu_4228_p3;
wire [0:0] tmp_1490_fu_6244_p3;
wire [0:0] tmp_1491_fu_6260_p3;
wire [0:0] tmp_1492_fu_6276_p3;
wire [0:0] tmp_1493_fu_6292_p3;
wire [0:0] tmp_1494_fu_6308_p3;
wire [0:0] tmp_1495_fu_6324_p3;
wire [11:0] p_Val2_393_6_fu_4452_p3;
wire [0:0] tmp_1496_fu_6340_p3;
wire [0:0] tmp_1497_fu_6356_p3;
wire [0:0] tmp_1498_fu_6372_p3;
wire [0:0] tmp_1499_fu_6388_p3;
wire [0:0] tmp_1500_fu_6404_p3;
wire [11:0] p_Val2_393_7_fu_4670_p3;
wire [0:0] tmp_1501_fu_6420_p3;
wire [0:0] tmp_1502_fu_6436_p3;
wire [0:0] tmp_1503_fu_6452_p3;
wire [0:0] tmp_1504_fu_6468_p3;
wire [11:0] p_Val2_393_8_fu_4882_p3;
wire [0:0] tmp_1505_fu_6484_p3;
wire [0:0] tmp_1506_fu_6500_p3;
wire [0:0] tmp_1507_fu_6516_p3;
wire [11:0] larger_V_9_s_fu_5088_p3;
wire [0:0] tmp_1508_fu_6532_p3;
wire [0:0] tmp_1509_fu_6548_p3;
wire [11:0] larger_V_10_s_fu_5288_p3;
wire [0:0] tmp_1510_fu_6564_p3;
wire [11:0] kill1_t_V_9_1_fu_6556_p3;
wire [10:0] tmp_1511_fu_6580_p1;
wire [10:0] kill1_t_V_9_s_fu_6540_p3;
wire [0:0] tmp_1512_fu_6590_p3;
wire [10:0] tmp_247_fu_6584_p2;
wire [11:0] kill1_t_V_8_1_fu_6524_p3;
wire [10:0] tmp_1513_fu_6606_p1;
wire [10:0] kill1_t_V_8_s_fu_6508_p3;
wire [0:0] tmp_1514_fu_6616_p3;
wire [10:0] tmp_248_fu_6610_p2;
wire [11:0] tmp92_fu_6624_p3;
wire [11:0] tmp91_fu_6598_p3;
wire [9:0] kill1_t_V_8_9_fu_6492_p3;
wire [9:0] kill1_t_V_7_9_fu_6444_p3;
wire [11:0] kill1_t_V_7_1_fu_6476_p3;
wire [8:0] tmp_1515_fu_6644_p1;
wire [8:0] kill1_t_V_7_8_fu_6428_p3;
wire [0:0] tmp_1516_fu_6654_p3;
wire [8:0] tmp_249_fu_6648_p2;
wire [9:0] tmp_250_fu_6662_p3;
wire [9:0] tmp94_fu_6638_p2;
wire [1:0] tmp_252_fu_6676_p4;
wire [9:0] tmp_251_fu_6670_p2;
wire [11:0] tmp95_fu_6686_p3;
wire [11:0] tmp93_fu_6632_p2;
wire [10:0] kill1_t_V_7_s_fu_6460_p3;
wire [10:0] kill1_t_V_5_s_fu_6316_p3;
wire [9:0] kill1_t_V_5_9_fu_6300_p3;
wire [7:0] tmp_1517_fu_6706_p1;
wire [7:0] kill1_t_V_6_7_fu_6348_p3;
wire [1:0] tmp_254_fu_6716_p4;
wire [7:0] tmp_253_fu_6710_p2;
wire [10:0] tmp97_fu_6700_p2;
wire [9:0] tmp_1518_fu_6734_p1;
wire [9:0] tmp98_fu_6726_p3;
wire [0:0] tmp_1519_fu_6744_p3;
wire [9:0] tmp_255_fu_6738_p2;
wire [11:0] kill1_t_V_5_1_fu_6332_p3;
wire [9:0] tmp_1520_fu_6760_p1;
wire [9:0] kill1_t_V_6_9_fu_6380_p3;
wire [1:0] tmp_257_fu_6770_p4;
wire [9:0] tmp_256_fu_6764_p2;
wire [11:0] kill1_t_V_6_1_fu_6412_p3;
wire [8:0] tmp_1521_fu_6788_p1;
wire [8:0] kill1_t_V_6_8_fu_6364_p3;
wire [2:0] tmp_259_fu_6798_p4;
wire [8:0] tmp_258_fu_6792_p2;
wire [11:0] tmp101_fu_6808_p3;
wire [11:0] tmp100_fu_6780_p3;
wire [11:0] tmp102_fu_6816_p2;
wire [10:0] tmp_1522_fu_6822_p1;
wire [10:0] tmp99_fu_6752_p3;
wire [0:0] tmp_1523_fu_6832_p3;
wire [10:0] tmp_260_fu_6826_p2;
wire [11:0] tmp103_fu_6840_p3;
wire [11:0] tmp96_fu_6694_p2;
wire [10:0] kill1_t_V_6_s_fu_6396_p3;
wire [7:0] tmp_1524_fu_6854_p1;
wire [7:0] kill1_t_V_3_7_fu_6060_p3;
wire [9:0] kill1_t_V_3_9_fu_6092_p3;
wire [6:0] tmp_1525_fu_6874_p1;
wire [6:0] kill1_t_V_3_6_fu_6044_p3;
wire [2:0] tmp_264_fu_6884_p4;
wire [6:0] tmp_263_fu_6878_p2;
wire [1:0] tmp_262_fu_6864_p4;
wire [7:0] tmp_261_fu_6858_p2;
wire [9:0] tmp_265_fu_6902_p3;
wire [9:0] tmp105_fu_6894_p3;
wire [0:0] tmp_1526_fu_6916_p3;
wire [9:0] tmp_266_fu_6910_p2;
wire [11:0] kill1_t_V_3_1_fu_6124_p3;
wire [8:0] tmp_1527_fu_6932_p1;
wire [8:0] kill1_t_V_3_8_fu_6076_p3;
wire [10:0] kill1_t_V_3_s_fu_6108_p3;
wire [6:0] tmp_1528_fu_6952_p1;
wire [6:0] kill1_t_V_4_6_fu_6156_p3;
wire [3:0] tmp_270_fu_6962_p4;
wire [6:0] tmp_269_fu_6956_p2;
wire [1:0] tmp_268_fu_6942_p4;
wire [8:0] tmp_267_fu_6936_p2;
wire [10:0] tmp_271_fu_6980_p3;
wire [10:0] tmp107_fu_6972_p3;
wire [10:0] tmp_272_fu_6988_p2;
wire [10:0] tmp106_fu_6924_p3;
wire [0:0] tmp_1529_fu_6994_p3;
wire [10:0] tmp_273_fu_7002_p2;
wire [8:0] kill1_t_V_4_8_fu_6188_p3;
wire [5:0] tmp_1530_fu_7016_p1;
wire [5:0] kill1_t_V_4_5_fu_6140_p3;
wire [2:0] tmp_275_fu_7026_p4;
wire [5:0] tmp_274_fu_7020_p2;
wire [10:0] kill1_t_V_4_s_fu_6220_p3;
wire [7:0] tmp_1531_fu_7044_p1;
wire [7:0] kill1_t_V_4_7_fu_6172_p3;
wire [0:0] tmp_1532_fu_7054_p3;
wire [7:0] tmp_276_fu_7048_p2;
wire [8:0] tmp_277_fu_7062_p3;
wire [8:0] tmp109_fu_7036_p3;
wire [1:0] tmp_279_fu_7076_p4;
wire [8:0] tmp_278_fu_7070_p2;
wire [9:0] kill1_t_V_4_9_fu_6204_p3;
wire [6:0] tmp_1533_fu_7094_p1;
wire [6:0] kill1_t_V_5_6_fu_6252_p3;
wire [2:0] tmp_281_fu_7104_p4;
wire [6:0] tmp_280_fu_7098_p2;
wire [8:0] kill1_t_V_5_8_fu_6284_p3;
wire [7:0] tmp_1534_fu_7122_p1;
wire [7:0] kill1_t_V_5_7_fu_6268_p3;
wire [0:0] tmp_1535_fu_7132_p3;
wire [7:0] tmp_282_fu_7126_p2;
wire [11:0] kill1_t_V_4_1_fu_6236_p3;
wire [8:0] tmp_1536_fu_7148_p1;
wire [8:0] tmp112_fu_7140_p3;
wire [0:0] tmp_1537_fu_7158_p3;
wire [8:0] tmp_283_fu_7152_p2;
wire [9:0] tmp_284_fu_7166_p3;
wire [9:0] tmp111_fu_7114_p3;
wire [0:0] tmp_1538_fu_7180_p3;
wire [9:0] tmp_285_fu_7174_p2;
wire [10:0] tmp_286_fu_7188_p3;
wire [10:0] tmp110_fu_7086_p3;
wire [0:0] tmp_1539_fu_7202_p3;
wire [10:0] tmp_287_fu_7196_p2;
wire [11:0] tmp113_fu_7210_p3;
wire [11:0] tmp108_fu_7008_p3;
wire [11:0] tmp114_fu_7218_p2;
wire [11:0] tmp104_fu_6848_p2;
wire [2:0] kill1_t_V_0_2_fu_5548_p3;
wire [1:0] tmp_1540_fu_7230_p1;
wire [1:0] kill1_t_V_0_1_fu_5532_p3;
wire [0:0] tmp_1541_fu_7240_p3;
wire [1:0] tmp_288_fu_7234_p2;
wire [4:0] kill1_t_V_0_4_fu_5580_p3;
wire [3:0] tmp_1542_fu_7256_p1;
wire [3:0] kill1_t_V_0_3_fu_5564_p3;
wire [3:0] tmp_289_fu_7260_p2;
wire [2:0] tmp_1544_fu_7274_p1;
wire [2:0] tmp116_fu_7248_p3;
wire [0:0] tmp_1543_fu_7266_p3;
wire [0:0] tmp_1545_fu_7284_p3;
wire [2:0] tmp_290_fu_7278_p2;
wire [6:0] kill1_t_V_0_6_fu_5612_p3;
wire [5:0] tmp_1546_fu_7302_p1;
wire [5:0] kill1_t_V_0_5_fu_5596_p3;
wire [0:0] tmp_1547_fu_7312_p3;
wire [5:0] tmp_291_fu_7306_p2;
wire [8:0] kill1_t_V_0_8_fu_5644_p3;
wire [7:0] tmp_1548_fu_7328_p1;
wire [7:0] kill1_t_V_0_7_fu_5628_p3;
wire [7:0] tmp_292_fu_7332_p2;
wire [6:0] tmp_1550_fu_7346_p1;
wire [6:0] tmp118_fu_7320_p3;
wire [6:0] tmp_293_fu_7350_p2;
wire [4:0] tmp_1552_fu_7364_p1;
wire [4:0] tmp117_fu_7292_p4;
wire [0:0] tmp_1549_fu_7338_p3;
wire [0:0] tmp_1551_fu_7356_p3;
wire [1:0] tmp_295_fu_7374_p4;
wire [4:0] tmp_294_fu_7368_p2;
wire [10:0] kill1_t_V_0_s_fu_5676_p3;
wire [9:0] tmp_1553_fu_7396_p1;
wire [9:0] kill1_t_V_0_9_fu_5660_p3;
wire [0:0] tmp_1554_fu_7406_p3;
wire [9:0] tmp_296_fu_7400_p2;
wire [11:0] kill1_t_V_0_10_fu_5692_p3;
wire [2:0] tmp_1555_fu_7422_p1;
wire [2:0] kill1_t_V_1_2_fu_5708_p3;
wire [7:0] tmp_298_fu_7432_p4;
wire [2:0] tmp_297_fu_7426_p2;
wire [10:0] tmp_299_fu_7442_p3;
wire [10:0] tmp120_fu_7414_p3;
wire [10:0] tmp_300_fu_7450_p2;
wire [4:0] kill1_t_V_1_4_fu_5740_p3;
wire [3:0] tmp_1558_fu_7468_p1;
wire [3:0] kill1_t_V_1_3_fu_5724_p3;
wire [0:0] tmp_1559_fu_7478_p3;
wire [3:0] tmp_301_fu_7472_p2;
wire [6:0] kill1_t_V_1_6_fu_5772_p3;
wire [5:0] tmp_1560_fu_7494_p1;
wire [5:0] kill1_t_V_1_5_fu_5756_p3;
wire [5:0] tmp_302_fu_7498_p2;
wire [4:0] tmp_1562_fu_7512_p1;
wire [4:0] tmp121_fu_7486_p3;
wire [0:0] tmp_1561_fu_7504_p3;
wire [0:0] tmp_1563_fu_7522_p3;
wire [4:0] tmp_303_fu_7516_p2;
wire [6:0] tmp_1557_fu_7464_p1;
wire [6:0] tmp122_fu_7530_p4;
wire [1:0] tmp_305_fu_7546_p4;
wire [6:0] tmp_304_fu_7540_p2;
wire [8:0] tmp_306_fu_7556_p3;
wire [8:0] tmp119_fu_7384_p5;
wire [0:0] tmp_1556_fu_7456_p3;
wire [1:0] tmp_308_fu_7570_p4;
wire [8:0] tmp_307_fu_7564_p2;
wire [8:0] kill1_t_V_1_8_fu_5804_p3;
wire [7:0] tmp_1564_fu_7590_p1;
wire [7:0] kill1_t_V_1_7_fu_5788_p3;
wire [0:0] tmp_1565_fu_7600_p3;
wire [7:0] tmp_309_fu_7594_p2;
wire [10:0] kill1_t_V_1_s_fu_5836_p3;
wire [9:0] tmp_1566_fu_7616_p1;
wire [9:0] kill1_t_V_1_9_fu_5820_p3;
wire [9:0] tmp_310_fu_7620_p2;
wire [8:0] tmp_1568_fu_7634_p1;
wire [8:0] tmp124_fu_7608_p3;
wire [0:0] tmp_1567_fu_7626_p3;
wire [0:0] tmp_1569_fu_7644_p3;
wire [8:0] tmp_311_fu_7638_p2;
wire [11:0] kill1_t_V_1_1_fu_5852_p3;
wire [3:0] tmp_1570_fu_7662_p1;
wire [3:0] kill1_t_V_2_3_fu_5868_p3;
wire [5:0] kill1_t_V_2_5_fu_5900_p3;
wire [4:0] tmp_1571_fu_7682_p1;
wire [4:0] kill1_t_V_2_4_fu_5884_p3;
wire [0:0] tmp_1572_fu_7692_p3;
wire [4:0] tmp_314_fu_7686_p2;
wire [1:0] tmp_313_fu_7672_p4;
wire [3:0] tmp_312_fu_7666_p2;
wire [5:0] tmp_315_fu_7708_p3;
wire [5:0] tmp126_fu_7700_p3;
wire [4:0] tmp_317_fu_7722_p4;
wire [5:0] tmp_316_fu_7716_p2;
wire [10:0] tmp_318_fu_7732_p3;
wire [10:0] tmp125_fu_7652_p4;
wire [0:0] tmp_1573_fu_7746_p3;
wire [10:0] tmp_319_fu_7740_p2;
wire [7:0] kill1_t_V_2_7_fu_5932_p3;
wire [6:0] tmp_1574_fu_7762_p1;
wire [6:0] kill1_t_V_2_6_fu_5916_p3;
wire [0:0] tmp_1575_fu_7772_p3;
wire [6:0] tmp_320_fu_7766_p2;
wire [9:0] kill1_t_V_2_9_fu_5964_p3;
wire [8:0] tmp_1576_fu_7788_p1;
wire [8:0] kill1_t_V_2_8_fu_5948_p3;
wire [8:0] tmp_321_fu_7792_p2;
wire [7:0] tmp_1578_fu_7806_p1;
wire [7:0] tmp128_fu_7780_p3;
wire [0:0] tmp_1577_fu_7798_p3;
wire [0:0] tmp_1579_fu_7816_p3;
wire [7:0] tmp_322_fu_7810_p2;
wire [11:0] kill1_t_V_2_1_fu_5996_p3;
wire [10:0] tmp_1580_fu_7834_p1;
wire [10:0] kill1_t_V_2_s_fu_5980_p3;
wire [0:0] tmp_1581_fu_7844_p3;
wire [10:0] tmp_323_fu_7838_p2;
wire [11:0] kill1_t_V_10_s_fu_6572_p3;
wire [0:0] tmp_1582_fu_7860_p3;
wire [4:0] kill1_t_V_3_4_fu_6012_p3;
wire [5:0] tmp_324_fu_7868_p3;
wire [5:0] kill1_t_V_3_5_fu_6028_p3;
wire [5:0] tmp_326_fu_7882_p4;
wire [5:0] tmp_325_fu_7876_p2;
wire [11:0] tmp131_fu_7892_p3;
wire [11:0] tmp130_fu_7852_p3;
wire [11:0] tmp132_fu_7900_p2;
wire [9:0] tmp_1583_fu_7906_p1;
wire [9:0] tmp129_fu_7824_p4;
wire [1:0] tmp_328_fu_7916_p4;
wire [9:0] tmp_327_fu_7910_p2;
wire [11:0] tmp133_fu_7926_p3;
wire [11:0] tmp127_fu_7754_p3;
wire [11:0] tmp134_fu_7934_p2;
wire [11:0] tmp123_fu_7580_p4;
wire [11:0] tmp135_fu_7940_p2;
wire [11:0] tmp115_fu_7224_p2;
wire [11:0] r_V_179_11_s_fu_7946_p2;
wire [11:0] p_Result_1299_s_fu_5496_p13;
wire [11:0] rhs_i_i1_fu_7952_p2;
wire [11:0] exists_V_fu_7958_p2;
wire [11:0] p_01272_0_not_fu_7964_p2;
wire [11:0] rhs_i_i_fu_7974_p2;
wire [0:0] tmp_1584_fu_7970_p1;
wire [11:0] p_9_fu_7980_p2;
wire [11:0] p_Val2_s_fu_7986_p3;
wire [0:0] tmp_1588_fu_8018_p1;
wire [0:0] tmp_1587_fu_8010_p3;
wire [0:0] tmp_1585_fu_7994_p3;
wire [0:0] tmp_1586_fu_8002_p3;
wire [0:0] tmp137_fu_8092_p2;
wire [0:0] tmp136_fu_8086_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_fu_8104_p2;
wire [0:0] lhs_i_i147_0_i_fu_8110_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_fu_8122_p2;
wire [0:0] lhs_i_i141_0_i_fu_8134_p2;
wire [0:0] rhs_i_i140_0_i_fu_8140_p2;
wire [0:0] lhs_i_i135_0_i_fu_8152_p2;
wire [0:0] tmp139_fu_8158_p2;
wire [0:0] tmp138_fu_8146_p2;
wire [0:0] lhs_i_i145_0_i_fu_8128_p2;
wire [0:0] rhs_i138_0_i_fu_8176_p2;
wire [0:0] tmp140_fu_8182_p2;
wire [0:0] lhs_i143_0_i_fu_8116_p2;
wire [0:0] tmp142_fu_8194_p2;
wire [0:0] rhs_i_i130_0_i_fu_8170_p2;
wire [0:0] rhs_i126_0_i_fu_8200_p2;
wire [0:0] tmp143_fu_8206_p2;
wire [0:0] rhs_i132_0_i_fu_8164_p2;
wire [0:0] tmp144_fu_8212_p2;
wire [0:0] tmp141_fu_8188_p2;
wire [0:0] tmp145_fu_8224_p2;
wire [0:0] p_demorgan229722982301_i_fu_8230_p2;
wire [0:0] tmp_1592_fu_8046_p3;
wire [0:0] tmp_1591_fu_8038_p3;
wire [0:0] tmp_1589_fu_8022_p3;
wire [0:0] tmp_1590_fu_8030_p3;
wire [0:0] tmp147_fu_8248_p2;
wire [0:0] tmp146_fu_8242_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_fu_8260_p2;
wire [0:0] lhs_i_i103_0_i_fu_8266_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_fu_8278_p2;
wire [0:0] lhs_i_i97_0_i_fu_8290_p2;
wire [0:0] rhs_i_i96_0_i_fu_8296_p2;
wire [0:0] lhs_i_i91_0_i_fu_8308_p2;
wire [0:0] tmp149_fu_8314_p2;
wire [0:0] tmp148_fu_8302_p2;
wire [0:0] lhs_i_i101_0_i_fu_8284_p2;
wire [0:0] rhs_i94_0_i_fu_8332_p2;
wire [0:0] tmp150_fu_8338_p2;
wire [0:0] lhs_i99_0_i_fu_8272_p2;
wire [0:0] tmp152_fu_8350_p2;
wire [0:0] rhs_i_i86_0_i_fu_8326_p2;
wire [0:0] rhs_i82_0_i_fu_8356_p2;
wire [0:0] tmp153_fu_8362_p2;
wire [0:0] rhs_i88_0_i_fu_8320_p2;
wire [0:0] tmp154_fu_8368_p2;
wire [0:0] tmp151_fu_8344_p2;
wire [0:0] tmp155_fu_8380_p2;
wire [0:0] p_demorgan230523062309_i_fu_8386_p2;
wire [0:0] tmp_1596_fu_8078_p3;
wire [0:0] tmp_1595_fu_8070_p3;
wire [0:0] tmp_1593_fu_8054_p3;
wire [0:0] tmp_1594_fu_8062_p3;
wire [0:0] tmp157_fu_8404_p2;
wire [0:0] tmp156_fu_8398_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_fu_8416_p2;
wire [0:0] lhs_i_i59_0_i1_fu_8422_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_fu_8434_p2;
wire [0:0] lhs_i_i53_0_i_fu_8446_p2;
wire [0:0] rhs_i_i52_0_i_fu_8452_p2;
wire [0:0] lhs_i_i47_0_i_fu_8464_p2;
wire [0:0] tmp159_fu_8470_p2;
wire [0:0] tmp158_fu_8458_p2;
wire [0:0] lhs_i_i57_0_i_fu_8440_p2;
wire [0:0] rhs_i50_0_i1_fu_8488_p2;
wire [0:0] tmp160_fu_8494_p2;
wire [0:0] lhs_i55_0_i_fu_8428_p2;
wire [0:0] tmp162_fu_8506_p2;
wire [0:0] rhs_i_i42_0_i_fu_8482_p2;
wire [0:0] rhs_i38_0_i_fu_8512_p2;
wire [0:0] tmp163_fu_8518_p2;
wire [0:0] rhs_i44_0_i_fu_8476_p2;
wire [0:0] tmp164_fu_8524_p2;
wire [0:0] tmp161_fu_8500_p2;
wire [0:0] tmp165_fu_8536_p2;
wire [0:0] p_demorgan231323142317_i_fu_8542_p2;
wire [0:0] y2_V_fu_8236_p2;
wire [0:0] y1_V_fu_8218_p2;
wire [0:0] y0_V_fu_8098_p2;
wire [2:0] p_Result_s_fu_8554_p4;
wire [0:0] y2a_V_fu_8392_p2;
wire [0:0] y1a_V_fu_8374_p2;
wire [0:0] y0a_V_fu_8254_p2;
wire [2:0] p_Result_150_fu_8568_p4;
wire [0:0] y2b_V_fu_8548_p2;
wire [0:0] y1b_V_fu_8530_p2;
wire [0:0] y0b_V_fu_8410_p2;
wire [2:0] p_Result_151_fu_8582_p4;
wire [3:0] tmp_332_fu_8592_p1;
wire [3:0] tmp_330_fu_8564_p1;
wire [3:0] tmp_331_fu_8578_p1;
wire [3:0] tmp166_fu_8596_p2;
wire [3:0] p_0190_i_fu_8602_p2;
wire [2:0] tmp_1597_fu_8614_p1;
wire [1:0] tmp_1598_fu_8618_p1;
wire [4:0] p_shl4_fu_8622_p3;
wire [5:0] tmp_1599_fu_8630_p3;
wire [5:0] tmp_1600_fu_8638_p1;
wire [5:0] tmp_1601_fu_8642_p2;
wire [35:0] tmp_1602_fu_8648_p1;
wire [0:0] tmp_333_fu_8608_p2;
wire [35:0] winner_V_fu_8652_p2;
wire [0:0] tmp_1604_fu_8666_p3;
wire [11:0] p_33_1_fu_8674_p2;
wire [11:0] p_Val2_398_1_fu_8680_p3;
wire [0:0] tmp_1608_fu_8712_p1;
wire [0:0] tmp_1607_fu_8704_p3;
wire [0:0] tmp_1605_fu_8688_p3;
wire [0:0] tmp_1606_fu_8696_p3;
wire [0:0] tmp170_fu_8786_p2;
wire [0:0] tmp169_fu_8780_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_1_fu_8798_p2;
wire [0:0] lhs_i_i147_0_i_1_fu_8804_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_1_fu_8816_p2;
wire [0:0] lhs_i_i141_0_i_1_fu_8828_p2;
wire [0:0] rhs_i_i140_0_i_1_fu_8834_p2;
wire [0:0] lhs_i_i135_0_i_1_fu_8846_p2;
wire [0:0] tmp172_fu_8852_p2;
wire [0:0] tmp171_fu_8840_p2;
wire [0:0] lhs_i_i145_0_i_1_fu_8822_p2;
wire [0:0] rhs_i138_0_i_s_fu_8870_p2;
wire [0:0] tmp173_fu_8876_p2;
wire [0:0] lhs_i143_0_i_1_fu_8810_p2;
wire [0:0] tmp175_fu_8888_p2;
wire [0:0] rhs_i_i130_0_i_1_fu_8864_p2;
wire [0:0] rhs_i126_0_i_s_fu_8894_p2;
wire [0:0] tmp176_fu_8900_p2;
wire [0:0] rhs_i132_0_i_1_fu_8858_p2;
wire [0:0] tmp177_fu_8906_p2;
wire [0:0] tmp174_fu_8882_p2;
wire [0:0] tmp178_fu_8918_p2;
wire [0:0] p_demorgan229722982301_i_1_fu_8924_p2;
wire [0:0] tmp_1612_fu_8740_p3;
wire [0:0] tmp_1611_fu_8732_p3;
wire [0:0] tmp_1609_fu_8716_p3;
wire [0:0] tmp_1610_fu_8724_p3;
wire [0:0] tmp180_fu_8942_p2;
wire [0:0] tmp179_fu_8936_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_1_fu_8954_p2;
wire [0:0] lhs_i_i103_0_i_1_fu_8960_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_1_fu_8972_p2;
wire [0:0] lhs_i_i97_0_i_1_fu_8984_p2;
wire [0:0] rhs_i_i96_0_i_1_fu_8990_p2;
wire [0:0] lhs_i_i91_0_i_1_fu_9002_p2;
wire [0:0] tmp182_fu_9008_p2;
wire [0:0] tmp181_fu_8996_p2;
wire [0:0] lhs_i_i101_0_i_1_fu_8978_p2;
wire [0:0] rhs_i94_0_i_s_fu_9026_p2;
wire [0:0] tmp183_fu_9032_p2;
wire [0:0] lhs_i99_0_i_1_fu_8966_p2;
wire [0:0] tmp185_fu_9044_p2;
wire [0:0] rhs_i_i86_0_i_1_fu_9020_p2;
wire [0:0] rhs_i82_0_i_s_fu_9050_p2;
wire [0:0] tmp186_fu_9056_p2;
wire [0:0] rhs_i88_0_i_1_fu_9014_p2;
wire [0:0] tmp187_fu_9062_p2;
wire [0:0] tmp184_fu_9038_p2;
wire [0:0] tmp188_fu_9074_p2;
wire [0:0] p_demorgan230523062309_i_1_fu_9080_p2;
wire [0:0] tmp_1616_fu_8772_p3;
wire [0:0] tmp_1615_fu_8764_p3;
wire [0:0] tmp_1613_fu_8748_p3;
wire [0:0] tmp_1614_fu_8756_p3;
wire [0:0] tmp190_fu_9098_p2;
wire [0:0] tmp189_fu_9092_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_1_fu_9110_p2;
wire [0:0] lhs_i_i59_0_i1_1_fu_9116_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_1_fu_9128_p2;
wire [0:0] lhs_i_i53_0_i_1_fu_9140_p2;
wire [0:0] rhs_i_i52_0_i_1_fu_9146_p2;
wire [0:0] lhs_i_i47_0_i_1_fu_9158_p2;
wire [0:0] tmp192_fu_9164_p2;
wire [0:0] tmp191_fu_9152_p2;
wire [0:0] lhs_i_i57_0_i_1_fu_9134_p2;
wire [0:0] rhs_i50_0_i1_s_fu_9182_p2;
wire [0:0] tmp193_fu_9188_p2;
wire [0:0] lhs_i55_0_i_1_fu_9122_p2;
wire [0:0] tmp195_fu_9200_p2;
wire [0:0] rhs_i_i42_0_i_1_fu_9176_p2;
wire [0:0] rhs_i38_0_i_s_fu_9206_p2;
wire [0:0] tmp196_fu_9212_p2;
wire [0:0] rhs_i44_0_i_1_fu_9170_p2;
wire [0:0] tmp197_fu_9218_p2;
wire [0:0] tmp194_fu_9194_p2;
wire [0:0] tmp198_fu_9230_p2;
wire [0:0] p_demorgan231323142317_i_1_fu_9236_p2;
wire [0:0] y2_V_1_fu_8930_p2;
wire [0:0] y1_V_1_fu_8912_p2;
wire [0:0] y0_V_1_fu_8792_p2;
wire [2:0] p_Result_1303_1_fu_9248_p4;
wire [0:0] y2a_V_1_fu_9086_p2;
wire [0:0] y1a_V_1_fu_9068_p2;
wire [0:0] y0a_V_1_fu_8948_p2;
wire [2:0] p_Result_1307_1_fu_9262_p4;
wire [0:0] y2b_V_1_fu_9242_p2;
wire [0:0] y1b_V_1_fu_9224_p2;
wire [0:0] y0b_V_1_fu_9104_p2;
wire [2:0] p_Result_1311_1_fu_9276_p4;
wire [3:0] tmp_1399_1_fu_9286_p1;
wire [3:0] tmp_1397_1_fu_9258_p1;
wire [3:0] tmp_1398_1_fu_9272_p1;
wire [3:0] tmp199_fu_9290_p2;
wire [3:0] p_0190_i_1_fu_9296_p2;
wire [2:0] tmp_1617_fu_9308_p1;
wire [4:0] p_shl6_fu_9320_p3;
wire [6:0] p_shl5_fu_9312_p3;
wire [6:0] p_shl6_cast_fu_9328_p1;
wire [0:0] tmp_1631_fu_9342_p3;
wire [11:0] p_33_2_fu_9350_p2;
wire [11:0] p_Val2_398_2_fu_9356_p3;
wire [0:0] tmp_1635_fu_9388_p1;
wire [0:0] tmp_1634_fu_9380_p3;
wire [0:0] tmp_1632_fu_9364_p3;
wire [0:0] tmp_1633_fu_9372_p3;
wire [0:0] tmp203_fu_9462_p2;
wire [0:0] tmp202_fu_9456_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_2_fu_9474_p2;
wire [0:0] lhs_i_i147_0_i_2_fu_9480_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_2_fu_9492_p2;
wire [0:0] lhs_i_i141_0_i_2_fu_9504_p2;
wire [0:0] rhs_i_i140_0_i_2_fu_9510_p2;
wire [0:0] lhs_i_i135_0_i_2_fu_9522_p2;
wire [0:0] tmp205_fu_9528_p2;
wire [0:0] tmp204_fu_9516_p2;
wire [0:0] lhs_i_i145_0_i_2_fu_9498_p2;
wire [0:0] rhs_i138_0_i_1_fu_9546_p2;
wire [0:0] tmp206_fu_9552_p2;
wire [0:0] lhs_i143_0_i_2_fu_9486_p2;
wire [0:0] tmp208_fu_9564_p2;
wire [0:0] rhs_i_i130_0_i_2_fu_9540_p2;
wire [0:0] rhs_i126_0_i_1_fu_9570_p2;
wire [0:0] tmp209_fu_9576_p2;
wire [0:0] rhs_i132_0_i_2_fu_9534_p2;
wire [0:0] tmp210_fu_9582_p2;
wire [0:0] tmp207_fu_9558_p2;
wire [0:0] tmp211_fu_9594_p2;
wire [0:0] p_demorgan229722982301_i_2_fu_9600_p2;
wire [0:0] tmp_1639_fu_9416_p3;
wire [0:0] tmp_1638_fu_9408_p3;
wire [0:0] tmp_1636_fu_9392_p3;
wire [0:0] tmp_1637_fu_9400_p3;
wire [0:0] tmp213_fu_9618_p2;
wire [0:0] tmp212_fu_9612_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_2_fu_9630_p2;
wire [0:0] lhs_i_i103_0_i_2_fu_9636_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_2_fu_9648_p2;
wire [0:0] lhs_i_i97_0_i_2_fu_9660_p2;
wire [0:0] rhs_i_i96_0_i_2_fu_9666_p2;
wire [0:0] lhs_i_i91_0_i_2_fu_9678_p2;
wire [0:0] tmp215_fu_9684_p2;
wire [0:0] tmp214_fu_9672_p2;
wire [0:0] lhs_i_i101_0_i_2_fu_9654_p2;
wire [0:0] rhs_i94_0_i_1_fu_9702_p2;
wire [0:0] tmp216_fu_9708_p2;
wire [0:0] lhs_i99_0_i_2_fu_9642_p2;
wire [0:0] tmp218_fu_9720_p2;
wire [0:0] rhs_i_i86_0_i_2_fu_9696_p2;
wire [0:0] rhs_i82_0_i_1_fu_9726_p2;
wire [0:0] tmp219_fu_9732_p2;
wire [0:0] rhs_i88_0_i_2_fu_9690_p2;
wire [0:0] tmp220_fu_9738_p2;
wire [0:0] tmp217_fu_9714_p2;
wire [0:0] tmp221_fu_9750_p2;
wire [0:0] p_demorgan230523062309_i_2_fu_9756_p2;
wire [0:0] tmp_1643_fu_9448_p3;
wire [0:0] tmp_1642_fu_9440_p3;
wire [0:0] tmp_1640_fu_9424_p3;
wire [0:0] tmp_1641_fu_9432_p3;
wire [0:0] tmp223_fu_9774_p2;
wire [0:0] tmp222_fu_9768_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_2_fu_9786_p2;
wire [0:0] lhs_i_i59_0_i1_2_fu_9792_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_2_fu_9804_p2;
wire [0:0] lhs_i_i53_0_i_2_fu_9816_p2;
wire [0:0] rhs_i_i52_0_i_2_fu_9822_p2;
wire [0:0] lhs_i_i47_0_i_2_fu_9834_p2;
wire [0:0] tmp225_fu_9840_p2;
wire [0:0] tmp224_fu_9828_p2;
wire [0:0] lhs_i_i57_0_i_2_fu_9810_p2;
wire [0:0] rhs_i50_0_i1_1_fu_9858_p2;
wire [0:0] tmp226_fu_9864_p2;
wire [0:0] lhs_i55_0_i_2_fu_9798_p2;
wire [0:0] tmp228_fu_9876_p2;
wire [0:0] rhs_i_i42_0_i_2_fu_9852_p2;
wire [0:0] rhs_i38_0_i_1_fu_9882_p2;
wire [0:0] tmp229_fu_9888_p2;
wire [0:0] rhs_i44_0_i_2_fu_9846_p2;
wire [0:0] tmp230_fu_9894_p2;
wire [0:0] tmp227_fu_9870_p2;
wire [0:0] tmp231_fu_9906_p2;
wire [0:0] p_demorgan231323142317_i_2_fu_9912_p2;
wire [0:0] y2_V_2_fu_9606_p2;
wire [0:0] y1_V_2_fu_9588_p2;
wire [0:0] y0_V_2_fu_9468_p2;
wire [2:0] p_Result_1303_2_fu_9924_p4;
wire [0:0] y2a_V_2_fu_9762_p2;
wire [0:0] y1a_V_2_fu_9744_p2;
wire [0:0] y0a_V_2_fu_9624_p2;
wire [2:0] p_Result_1307_2_fu_9938_p4;
wire [0:0] y2b_V_2_fu_9918_p2;
wire [0:0] y1b_V_2_fu_9900_p2;
wire [0:0] y0b_V_2_fu_9780_p2;
wire [2:0] p_Result_1311_2_fu_9952_p4;
wire [3:0] tmp_1399_2_fu_9962_p1;
wire [3:0] tmp_1397_2_fu_9934_p1;
wire [3:0] tmp_1398_2_fu_9948_p1;
wire [3:0] tmp232_fu_9966_p2;
wire [3:0] p_0190_i_2_fu_9972_p2;
wire [0:0] tmp_1658_fu_9988_p3;
wire [11:0] p_33_3_fu_9996_p2;
wire [11:0] p_Val2_398_3_fu_10002_p3;
wire [0:0] tmp_1662_fu_10034_p1;
wire [0:0] tmp_1661_fu_10026_p3;
wire [0:0] tmp_1659_fu_10010_p3;
wire [0:0] tmp_1660_fu_10018_p3;
wire [0:0] tmp236_fu_10108_p2;
wire [0:0] tmp235_fu_10102_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_3_fu_10120_p2;
wire [0:0] lhs_i_i147_0_i_3_fu_10126_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_3_fu_10138_p2;
wire [0:0] lhs_i_i141_0_i_3_fu_10150_p2;
wire [0:0] rhs_i_i140_0_i_3_fu_10156_p2;
wire [0:0] lhs_i_i135_0_i_3_fu_10168_p2;
wire [0:0] tmp238_fu_10174_p2;
wire [0:0] tmp237_fu_10162_p2;
wire [0:0] lhs_i_i145_0_i_3_fu_10144_p2;
wire [0:0] rhs_i138_0_i_2_fu_10192_p2;
wire [0:0] tmp239_fu_10198_p2;
wire [0:0] lhs_i143_0_i_3_fu_10132_p2;
wire [0:0] tmp241_fu_10210_p2;
wire [0:0] rhs_i_i130_0_i_3_fu_10186_p2;
wire [0:0] rhs_i126_0_i_2_fu_10216_p2;
wire [0:0] tmp242_fu_10222_p2;
wire [0:0] rhs_i132_0_i_3_fu_10180_p2;
wire [0:0] tmp243_fu_10228_p2;
wire [0:0] tmp240_fu_10204_p2;
wire [0:0] tmp244_fu_10240_p2;
wire [0:0] p_demorgan229722982301_i_3_fu_10246_p2;
wire [0:0] tmp_1666_fu_10062_p3;
wire [0:0] tmp_1665_fu_10054_p3;
wire [0:0] tmp_1663_fu_10038_p3;
wire [0:0] tmp_1664_fu_10046_p3;
wire [0:0] tmp246_fu_10264_p2;
wire [0:0] tmp245_fu_10258_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_3_fu_10276_p2;
wire [0:0] lhs_i_i103_0_i_3_fu_10282_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_3_fu_10294_p2;
wire [0:0] lhs_i_i97_0_i_3_fu_10306_p2;
wire [0:0] rhs_i_i96_0_i_3_fu_10312_p2;
wire [0:0] lhs_i_i91_0_i_3_fu_10324_p2;
wire [0:0] tmp248_fu_10330_p2;
wire [0:0] tmp247_fu_10318_p2;
wire [0:0] lhs_i_i101_0_i_3_fu_10300_p2;
wire [0:0] rhs_i94_0_i_2_fu_10348_p2;
wire [0:0] tmp249_fu_10354_p2;
wire [0:0] lhs_i99_0_i_3_fu_10288_p2;
wire [0:0] tmp251_fu_10366_p2;
wire [0:0] rhs_i_i86_0_i_3_fu_10342_p2;
wire [0:0] rhs_i82_0_i_2_fu_10372_p2;
wire [0:0] tmp252_fu_10378_p2;
wire [0:0] rhs_i88_0_i_3_fu_10336_p2;
wire [0:0] tmp253_fu_10384_p2;
wire [0:0] tmp250_fu_10360_p2;
wire [0:0] tmp254_fu_10396_p2;
wire [0:0] p_demorgan230523062309_i_3_fu_10402_p2;
wire [0:0] tmp_1670_fu_10094_p3;
wire [0:0] tmp_1669_fu_10086_p3;
wire [0:0] tmp_1667_fu_10070_p3;
wire [0:0] tmp_1668_fu_10078_p3;
wire [0:0] tmp256_fu_10420_p2;
wire [0:0] tmp255_fu_10414_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_3_fu_10432_p2;
wire [0:0] lhs_i_i59_0_i1_3_fu_10438_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_3_fu_10450_p2;
wire [0:0] lhs_i_i53_0_i_3_fu_10462_p2;
wire [0:0] rhs_i_i52_0_i_3_fu_10468_p2;
wire [0:0] lhs_i_i47_0_i_3_fu_10480_p2;
wire [0:0] tmp258_fu_10486_p2;
wire [0:0] tmp257_fu_10474_p2;
wire [0:0] lhs_i_i57_0_i_3_fu_10456_p2;
wire [0:0] rhs_i50_0_i1_2_fu_10504_p2;
wire [0:0] tmp259_fu_10510_p2;
wire [0:0] lhs_i55_0_i_3_fu_10444_p2;
wire [0:0] tmp261_fu_10522_p2;
wire [0:0] rhs_i_i42_0_i_3_fu_10498_p2;
wire [0:0] rhs_i38_0_i_2_fu_10528_p2;
wire [0:0] tmp262_fu_10534_p2;
wire [0:0] rhs_i44_0_i_3_fu_10492_p2;
wire [0:0] tmp263_fu_10540_p2;
wire [0:0] tmp260_fu_10516_p2;
wire [0:0] tmp264_fu_10552_p2;
wire [0:0] p_demorgan231323142317_i_3_fu_10558_p2;
wire [0:0] y2_V_3_fu_10252_p2;
wire [0:0] y1_V_3_fu_10234_p2;
wire [0:0] y0_V_3_fu_10114_p2;
wire [2:0] p_Result_1303_3_fu_10570_p4;
wire [0:0] y2a_V_3_fu_10408_p2;
wire [0:0] y1a_V_3_fu_10390_p2;
wire [0:0] y0a_V_3_fu_10270_p2;
wire [2:0] p_Result_1307_3_fu_10584_p4;
wire [0:0] y2b_V_3_fu_10564_p2;
wire [0:0] y1b_V_3_fu_10546_p2;
wire [0:0] y0b_V_3_fu_10426_p2;
wire [2:0] p_Result_1311_3_fu_10598_p4;
wire [3:0] tmp_1399_3_fu_10608_p1;
wire [3:0] tmp_1397_3_fu_10580_p1;
wire [3:0] tmp_1398_3_fu_10594_p1;
wire [3:0] tmp265_fu_10612_p2;
wire [3:0] p_0190_i_3_fu_10618_p2;
wire [0:0] tmp_1685_fu_10634_p3;
wire [11:0] p_33_4_fu_10642_p2;
wire [11:0] p_Val2_398_4_fu_10648_p3;
wire [0:0] tmp_1689_fu_10680_p1;
wire [0:0] tmp_1688_fu_10672_p3;
wire [0:0] tmp_1686_fu_10656_p3;
wire [0:0] tmp_1687_fu_10664_p3;
wire [0:0] tmp599_fu_10754_p2;
wire [0:0] tmp598_fu_10748_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_4_fu_10766_p2;
wire [0:0] lhs_i_i147_0_i_4_fu_10772_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_4_fu_10784_p2;
wire [0:0] lhs_i_i141_0_i_4_fu_10796_p2;
wire [0:0] rhs_i_i140_0_i_4_fu_10802_p2;
wire [0:0] lhs_i_i135_0_i_4_fu_10814_p2;
wire [0:0] tmp601_fu_10820_p2;
wire [0:0] tmp600_fu_10808_p2;
wire [0:0] lhs_i_i145_0_i_4_fu_10790_p2;
wire [0:0] rhs_i138_0_i_3_fu_10838_p2;
wire [0:0] tmp602_fu_10844_p2;
wire [0:0] lhs_i143_0_i_4_fu_10778_p2;
wire [0:0] tmp604_fu_10856_p2;
wire [0:0] rhs_i_i130_0_i_4_fu_10832_p2;
wire [0:0] rhs_i126_0_i_3_fu_10862_p2;
wire [0:0] tmp605_fu_10868_p2;
wire [0:0] rhs_i132_0_i_4_fu_10826_p2;
wire [0:0] tmp606_fu_10874_p2;
wire [0:0] tmp603_fu_10850_p2;
wire [0:0] tmp607_fu_10886_p2;
wire [0:0] p_demorgan229722982301_i_4_fu_10892_p2;
wire [0:0] tmp_1693_fu_10708_p3;
wire [0:0] tmp_1692_fu_10700_p3;
wire [0:0] tmp_1690_fu_10684_p3;
wire [0:0] tmp_1691_fu_10692_p3;
wire [0:0] tmp609_fu_10910_p2;
wire [0:0] tmp608_fu_10904_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_4_fu_10922_p2;
wire [0:0] lhs_i_i103_0_i_4_fu_10928_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_4_fu_10940_p2;
wire [0:0] lhs_i_i97_0_i_4_fu_10952_p2;
wire [0:0] rhs_i_i96_0_i_4_fu_10958_p2;
wire [0:0] lhs_i_i91_0_i_4_fu_10970_p2;
wire [0:0] tmp611_fu_10976_p2;
wire [0:0] tmp610_fu_10964_p2;
wire [0:0] lhs_i_i101_0_i_4_fu_10946_p2;
wire [0:0] rhs_i94_0_i_3_fu_10994_p2;
wire [0:0] tmp612_fu_11000_p2;
wire [0:0] lhs_i99_0_i_4_fu_10934_p2;
wire [0:0] tmp614_fu_11012_p2;
wire [0:0] rhs_i_i86_0_i_4_fu_10988_p2;
wire [0:0] rhs_i82_0_i_3_fu_11018_p2;
wire [0:0] tmp615_fu_11024_p2;
wire [0:0] rhs_i88_0_i_4_fu_10982_p2;
wire [0:0] tmp616_fu_11030_p2;
wire [0:0] tmp613_fu_11006_p2;
wire [0:0] tmp617_fu_11042_p2;
wire [0:0] p_demorgan230523062309_i_4_fu_11048_p2;
wire [0:0] tmp_1697_fu_10740_p3;
wire [0:0] tmp_1696_fu_10732_p3;
wire [0:0] tmp_1694_fu_10716_p3;
wire [0:0] tmp_1695_fu_10724_p3;
wire [0:0] tmp619_fu_11066_p2;
wire [0:0] tmp618_fu_11060_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_4_fu_11078_p2;
wire [0:0] lhs_i_i59_0_i1_4_fu_11084_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_4_fu_11096_p2;
wire [0:0] lhs_i_i53_0_i_4_fu_11108_p2;
wire [0:0] rhs_i_i52_0_i_4_fu_11114_p2;
wire [0:0] lhs_i_i47_0_i_4_fu_11126_p2;
wire [0:0] tmp621_fu_11132_p2;
wire [0:0] tmp620_fu_11120_p2;
wire [0:0] lhs_i_i57_0_i_4_fu_11102_p2;
wire [0:0] rhs_i50_0_i1_3_fu_11150_p2;
wire [0:0] tmp622_fu_11156_p2;
wire [0:0] lhs_i55_0_i_4_fu_11090_p2;
wire [0:0] tmp624_fu_11168_p2;
wire [0:0] rhs_i_i42_0_i_4_fu_11144_p2;
wire [0:0] rhs_i38_0_i_3_fu_11174_p2;
wire [0:0] tmp625_fu_11180_p2;
wire [0:0] rhs_i44_0_i_4_fu_11138_p2;
wire [0:0] tmp626_fu_11186_p2;
wire [0:0] tmp623_fu_11162_p2;
wire [0:0] tmp627_fu_11198_p2;
wire [0:0] p_demorgan231323142317_i_4_fu_11204_p2;
wire [0:0] y2_V_4_fu_10898_p2;
wire [0:0] y1_V_4_fu_10880_p2;
wire [0:0] y0_V_4_fu_10760_p2;
wire [2:0] p_Result_1303_4_fu_11216_p4;
wire [0:0] y2a_V_4_fu_11054_p2;
wire [0:0] y1a_V_4_fu_11036_p2;
wire [0:0] y0a_V_4_fu_10916_p2;
wire [2:0] p_Result_1307_4_fu_11230_p4;
wire [0:0] y2b_V_4_fu_11210_p2;
wire [0:0] y1b_V_4_fu_11192_p2;
wire [0:0] y0b_V_4_fu_11072_p2;
wire [2:0] p_Result_1311_4_fu_11244_p4;
wire [3:0] tmp_1399_4_fu_11254_p1;
wire [3:0] tmp_1397_4_fu_11226_p1;
wire [3:0] tmp_1398_4_fu_11240_p1;
wire [3:0] tmp628_fu_11258_p2;
wire [3:0] p_0190_i_4_fu_11264_p2;
wire [0:0] tmp_1712_fu_11280_p3;
wire [11:0] p_33_5_fu_11288_p2;
wire [11:0] p_Val2_398_5_fu_11294_p3;
wire [0:0] tmp_1716_fu_11326_p1;
wire [0:0] tmp_1715_fu_11318_p3;
wire [0:0] tmp_1713_fu_11302_p3;
wire [0:0] tmp_1714_fu_11310_p3;
wire [0:0] tmp632_fu_11400_p2;
wire [0:0] tmp631_fu_11394_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_5_fu_11412_p2;
wire [0:0] lhs_i_i147_0_i_5_fu_11418_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_5_fu_11430_p2;
wire [0:0] lhs_i_i141_0_i_5_fu_11442_p2;
wire [0:0] rhs_i_i140_0_i_5_fu_11448_p2;
wire [0:0] lhs_i_i135_0_i_5_fu_11460_p2;
wire [0:0] tmp634_fu_11466_p2;
wire [0:0] tmp633_fu_11454_p2;
wire [0:0] lhs_i_i145_0_i_5_fu_11436_p2;
wire [0:0] rhs_i138_0_i_4_fu_11484_p2;
wire [0:0] tmp635_fu_11490_p2;
wire [0:0] lhs_i143_0_i_5_fu_11424_p2;
wire [0:0] tmp637_fu_11502_p2;
wire [0:0] rhs_i_i130_0_i_5_fu_11478_p2;
wire [0:0] rhs_i126_0_i_4_fu_11508_p2;
wire [0:0] tmp638_fu_11514_p2;
wire [0:0] rhs_i132_0_i_5_fu_11472_p2;
wire [0:0] tmp639_fu_11520_p2;
wire [0:0] tmp636_fu_11496_p2;
wire [0:0] tmp640_fu_11532_p2;
wire [0:0] p_demorgan229722982301_i_5_fu_11538_p2;
wire [0:0] tmp_1720_fu_11354_p3;
wire [0:0] tmp_1719_fu_11346_p3;
wire [0:0] tmp_1717_fu_11330_p3;
wire [0:0] tmp_1718_fu_11338_p3;
wire [0:0] tmp642_fu_11556_p2;
wire [0:0] tmp641_fu_11550_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_5_fu_11568_p2;
wire [0:0] lhs_i_i103_0_i_5_fu_11574_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_5_fu_11586_p2;
wire [0:0] lhs_i_i97_0_i_5_fu_11598_p2;
wire [0:0] rhs_i_i96_0_i_5_fu_11604_p2;
wire [0:0] lhs_i_i91_0_i_5_fu_11616_p2;
wire [0:0] tmp644_fu_11622_p2;
wire [0:0] tmp643_fu_11610_p2;
wire [0:0] lhs_i_i101_0_i_5_fu_11592_p2;
wire [0:0] rhs_i94_0_i_4_fu_11640_p2;
wire [0:0] tmp645_fu_11646_p2;
wire [0:0] lhs_i99_0_i_5_fu_11580_p2;
wire [0:0] tmp647_fu_11658_p2;
wire [0:0] rhs_i_i86_0_i_5_fu_11634_p2;
wire [0:0] rhs_i82_0_i_4_fu_11664_p2;
wire [0:0] tmp648_fu_11670_p2;
wire [0:0] rhs_i88_0_i_5_fu_11628_p2;
wire [0:0] tmp649_fu_11676_p2;
wire [0:0] tmp646_fu_11652_p2;
wire [0:0] tmp650_fu_11688_p2;
wire [0:0] p_demorgan230523062309_i_5_fu_11694_p2;
wire [0:0] tmp_1724_fu_11386_p3;
wire [0:0] tmp_1723_fu_11378_p3;
wire [0:0] tmp_1721_fu_11362_p3;
wire [0:0] tmp_1722_fu_11370_p3;
wire [0:0] tmp652_fu_11712_p2;
wire [0:0] tmp651_fu_11706_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_5_fu_11724_p2;
wire [0:0] lhs_i_i59_0_i1_5_fu_11730_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_5_fu_11742_p2;
wire [0:0] lhs_i_i53_0_i_5_fu_11754_p2;
wire [0:0] rhs_i_i52_0_i_5_fu_11760_p2;
wire [0:0] lhs_i_i47_0_i_5_fu_11772_p2;
wire [0:0] tmp654_fu_11778_p2;
wire [0:0] tmp653_fu_11766_p2;
wire [0:0] lhs_i_i57_0_i_5_fu_11748_p2;
wire [0:0] rhs_i50_0_i1_4_fu_11796_p2;
wire [0:0] tmp655_fu_11802_p2;
wire [0:0] lhs_i55_0_i_5_fu_11736_p2;
wire [0:0] tmp657_fu_11814_p2;
wire [0:0] rhs_i_i42_0_i_5_fu_11790_p2;
wire [0:0] rhs_i38_0_i_4_fu_11820_p2;
wire [0:0] tmp658_fu_11826_p2;
wire [0:0] rhs_i44_0_i_5_fu_11784_p2;
wire [0:0] tmp659_fu_11832_p2;
wire [0:0] tmp656_fu_11808_p2;
wire [0:0] tmp660_fu_11844_p2;
wire [0:0] p_demorgan231323142317_i_5_fu_11850_p2;
wire [0:0] y2_V_5_fu_11544_p2;
wire [0:0] y1_V_5_fu_11526_p2;
wire [0:0] y0_V_5_fu_11406_p2;
wire [2:0] p_Result_1303_5_fu_11862_p4;
wire [0:0] y2a_V_5_fu_11700_p2;
wire [0:0] y1a_V_5_fu_11682_p2;
wire [0:0] y0a_V_5_fu_11562_p2;
wire [2:0] p_Result_1307_5_fu_11876_p4;
wire [0:0] y2b_V_5_fu_11856_p2;
wire [0:0] y1b_V_5_fu_11838_p2;
wire [0:0] y0b_V_5_fu_11718_p2;
wire [2:0] p_Result_1311_5_fu_11890_p4;
wire [3:0] tmp_1399_5_fu_11900_p1;
wire [3:0] tmp_1397_5_fu_11872_p1;
wire [3:0] tmp_1398_5_fu_11886_p1;
wire [3:0] tmp661_fu_11904_p2;
wire [3:0] p_0190_i_5_fu_11910_p2;
wire [0:0] tmp_1739_fu_11926_p3;
wire [11:0] p_33_6_fu_11934_p2;
wire [11:0] p_Val2_398_6_fu_11940_p3;
wire [0:0] tmp_1743_fu_11972_p1;
wire [0:0] tmp_1742_fu_11964_p3;
wire [0:0] tmp_1740_fu_11948_p3;
wire [0:0] tmp_1741_fu_11956_p3;
wire [0:0] tmp665_fu_12046_p2;
wire [0:0] tmp664_fu_12040_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_6_fu_12058_p2;
wire [0:0] lhs_i_i147_0_i_6_fu_12064_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_6_fu_12076_p2;
wire [0:0] lhs_i_i141_0_i_6_fu_12088_p2;
wire [0:0] rhs_i_i140_0_i_6_fu_12094_p2;
wire [0:0] lhs_i_i135_0_i_6_fu_12106_p2;
wire [0:0] tmp667_fu_12112_p2;
wire [0:0] tmp666_fu_12100_p2;
wire [0:0] lhs_i_i145_0_i_6_fu_12082_p2;
wire [0:0] rhs_i138_0_i_5_fu_12130_p2;
wire [0:0] tmp668_fu_12136_p2;
wire [0:0] lhs_i143_0_i_6_fu_12070_p2;
wire [0:0] tmp670_fu_12148_p2;
wire [0:0] rhs_i_i130_0_i_6_fu_12124_p2;
wire [0:0] rhs_i126_0_i_5_fu_12154_p2;
wire [0:0] tmp671_fu_12160_p2;
wire [0:0] rhs_i132_0_i_6_fu_12118_p2;
wire [0:0] tmp672_fu_12166_p2;
wire [0:0] tmp669_fu_12142_p2;
wire [0:0] tmp673_fu_12178_p2;
wire [0:0] p_demorgan229722982301_i_6_fu_12184_p2;
wire [0:0] tmp_1747_fu_12000_p3;
wire [0:0] tmp_1746_fu_11992_p3;
wire [0:0] tmp_1744_fu_11976_p3;
wire [0:0] tmp_1745_fu_11984_p3;
wire [0:0] tmp675_fu_12202_p2;
wire [0:0] tmp674_fu_12196_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_6_fu_12214_p2;
wire [0:0] lhs_i_i103_0_i_6_fu_12220_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_6_fu_12232_p2;
wire [0:0] lhs_i_i97_0_i_6_fu_12244_p2;
wire [0:0] rhs_i_i96_0_i_6_fu_12250_p2;
wire [0:0] lhs_i_i91_0_i_6_fu_12262_p2;
wire [0:0] tmp677_fu_12268_p2;
wire [0:0] tmp676_fu_12256_p2;
wire [0:0] lhs_i_i101_0_i_6_fu_12238_p2;
wire [0:0] rhs_i94_0_i_5_fu_12286_p2;
wire [0:0] tmp678_fu_12292_p2;
wire [0:0] lhs_i99_0_i_6_fu_12226_p2;
wire [0:0] tmp680_fu_12304_p2;
wire [0:0] rhs_i_i86_0_i_6_fu_12280_p2;
wire [0:0] rhs_i82_0_i_5_fu_12310_p2;
wire [0:0] tmp681_fu_12316_p2;
wire [0:0] rhs_i88_0_i_6_fu_12274_p2;
wire [0:0] tmp682_fu_12322_p2;
wire [0:0] tmp679_fu_12298_p2;
wire [0:0] tmp683_fu_12334_p2;
wire [0:0] p_demorgan230523062309_i_6_fu_12340_p2;
wire [0:0] tmp_1751_fu_12032_p3;
wire [0:0] tmp_1750_fu_12024_p3;
wire [0:0] tmp_1748_fu_12008_p3;
wire [0:0] tmp_1749_fu_12016_p3;
wire [0:0] tmp685_fu_12358_p2;
wire [0:0] tmp684_fu_12352_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_6_fu_12370_p2;
wire [0:0] lhs_i_i59_0_i1_6_fu_12376_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_6_fu_12388_p2;
wire [0:0] lhs_i_i53_0_i_6_fu_12400_p2;
wire [0:0] rhs_i_i52_0_i_6_fu_12406_p2;
wire [0:0] lhs_i_i47_0_i_6_fu_12418_p2;
wire [0:0] tmp687_fu_12424_p2;
wire [0:0] tmp686_fu_12412_p2;
wire [0:0] lhs_i_i57_0_i_6_fu_12394_p2;
wire [0:0] rhs_i50_0_i1_5_fu_12442_p2;
wire [0:0] tmp688_fu_12448_p2;
wire [0:0] lhs_i55_0_i_6_fu_12382_p2;
wire [0:0] tmp690_fu_12460_p2;
wire [0:0] rhs_i_i42_0_i_6_fu_12436_p2;
wire [0:0] rhs_i38_0_i_5_fu_12466_p2;
wire [0:0] tmp691_fu_12472_p2;
wire [0:0] rhs_i44_0_i_6_fu_12430_p2;
wire [0:0] tmp692_fu_12478_p2;
wire [0:0] tmp689_fu_12454_p2;
wire [0:0] tmp693_fu_12490_p2;
wire [0:0] p_demorgan231323142317_i_6_fu_12496_p2;
wire [0:0] y2_V_6_fu_12190_p2;
wire [0:0] y1_V_6_fu_12172_p2;
wire [0:0] y0_V_6_fu_12052_p2;
wire [2:0] p_Result_1303_6_fu_12508_p4;
wire [0:0] y2a_V_6_fu_12346_p2;
wire [0:0] y1a_V_6_fu_12328_p2;
wire [0:0] y0a_V_6_fu_12208_p2;
wire [2:0] p_Result_1307_6_fu_12522_p4;
wire [0:0] y2b_V_6_fu_12502_p2;
wire [0:0] y1b_V_6_fu_12484_p2;
wire [0:0] y0b_V_6_fu_12364_p2;
wire [2:0] p_Result_1311_6_fu_12536_p4;
wire [3:0] tmp_1399_6_fu_12546_p1;
wire [3:0] tmp_1397_6_fu_12518_p1;
wire [3:0] tmp_1398_6_fu_12532_p1;
wire [3:0] tmp694_fu_12550_p2;
wire [3:0] p_0190_i_6_fu_12556_p2;
wire [0:0] tmp_1766_fu_12572_p3;
wire [11:0] p_33_7_fu_12580_p2;
wire [11:0] p_Val2_398_7_fu_12586_p3;
wire [0:0] tmp_1770_fu_12618_p1;
wire [0:0] tmp_1769_fu_12610_p3;
wire [0:0] tmp_1767_fu_12594_p3;
wire [0:0] tmp_1768_fu_12602_p3;
wire [0:0] tmp700_fu_12692_p2;
wire [0:0] tmp699_fu_12686_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_7_fu_12704_p2;
wire [0:0] lhs_i_i147_0_i_7_fu_12710_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_7_fu_12722_p2;
wire [0:0] lhs_i_i141_0_i_7_fu_12734_p2;
wire [0:0] rhs_i_i140_0_i_7_fu_12740_p2;
wire [0:0] lhs_i_i135_0_i_7_fu_12752_p2;
wire [0:0] tmp702_fu_12758_p2;
wire [0:0] tmp701_fu_12746_p2;
wire [0:0] lhs_i_i145_0_i_7_fu_12728_p2;
wire [0:0] rhs_i138_0_i_6_fu_12776_p2;
wire [0:0] tmp703_fu_12782_p2;
wire [0:0] lhs_i143_0_i_7_fu_12716_p2;
wire [0:0] tmp705_fu_12794_p2;
wire [0:0] rhs_i_i130_0_i_7_fu_12770_p2;
wire [0:0] rhs_i126_0_i_6_fu_12800_p2;
wire [0:0] tmp706_fu_12806_p2;
wire [0:0] rhs_i132_0_i_7_fu_12764_p2;
wire [0:0] tmp707_fu_12812_p2;
wire [0:0] tmp704_fu_12788_p2;
wire [0:0] tmp708_fu_12824_p2;
wire [0:0] p_demorgan229722982301_i_7_fu_12830_p2;
wire [0:0] tmp_1774_fu_12646_p3;
wire [0:0] tmp_1773_fu_12638_p3;
wire [0:0] tmp_1771_fu_12622_p3;
wire [0:0] tmp_1772_fu_12630_p3;
wire [0:0] tmp710_fu_12848_p2;
wire [0:0] tmp709_fu_12842_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_7_fu_12860_p2;
wire [0:0] lhs_i_i103_0_i_7_fu_12866_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_7_fu_12878_p2;
wire [0:0] lhs_i_i97_0_i_7_fu_12890_p2;
wire [0:0] rhs_i_i96_0_i_7_fu_12896_p2;
wire [0:0] lhs_i_i91_0_i_7_fu_12908_p2;
wire [0:0] tmp712_fu_12914_p2;
wire [0:0] tmp711_fu_12902_p2;
wire [0:0] lhs_i_i101_0_i_7_fu_12884_p2;
wire [0:0] rhs_i94_0_i_6_fu_12932_p2;
wire [0:0] tmp713_fu_12938_p2;
wire [0:0] lhs_i99_0_i_7_fu_12872_p2;
wire [0:0] tmp715_fu_12950_p2;
wire [0:0] rhs_i_i86_0_i_7_fu_12926_p2;
wire [0:0] rhs_i82_0_i_6_fu_12956_p2;
wire [0:0] tmp716_fu_12962_p2;
wire [0:0] rhs_i88_0_i_7_fu_12920_p2;
wire [0:0] tmp717_fu_12968_p2;
wire [0:0] tmp714_fu_12944_p2;
wire [0:0] tmp718_fu_12980_p2;
wire [0:0] p_demorgan230523062309_i_7_fu_12986_p2;
wire [0:0] tmp_1778_fu_12678_p3;
wire [0:0] tmp_1777_fu_12670_p3;
wire [0:0] tmp_1775_fu_12654_p3;
wire [0:0] tmp_1776_fu_12662_p3;
wire [0:0] tmp720_fu_13004_p2;
wire [0:0] tmp719_fu_12998_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_7_fu_13016_p2;
wire [0:0] lhs_i_i59_0_i1_7_fu_13022_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_7_fu_13034_p2;
wire [0:0] lhs_i_i53_0_i_7_fu_13046_p2;
wire [0:0] rhs_i_i52_0_i_7_fu_13052_p2;
wire [0:0] lhs_i_i47_0_i_7_fu_13064_p2;
wire [0:0] tmp722_fu_13070_p2;
wire [0:0] tmp721_fu_13058_p2;
wire [0:0] lhs_i_i57_0_i_7_fu_13040_p2;
wire [0:0] rhs_i50_0_i1_6_fu_13088_p2;
wire [0:0] tmp723_fu_13094_p2;
wire [0:0] lhs_i55_0_i_7_fu_13028_p2;
wire [0:0] tmp725_fu_13106_p2;
wire [0:0] rhs_i_i42_0_i_7_fu_13082_p2;
wire [0:0] rhs_i38_0_i_6_fu_13112_p2;
wire [0:0] tmp726_fu_13118_p2;
wire [0:0] rhs_i44_0_i_7_fu_13076_p2;
wire [0:0] tmp727_fu_13124_p2;
wire [0:0] tmp724_fu_13100_p2;
wire [0:0] tmp728_fu_13136_p2;
wire [0:0] p_demorgan231323142317_i_7_fu_13142_p2;
wire [0:0] y2_V_7_fu_12836_p2;
wire [0:0] y1_V_7_fu_12818_p2;
wire [0:0] y0_V_7_fu_12698_p2;
wire [2:0] p_Result_1303_7_fu_13154_p4;
wire [0:0] y2a_V_7_fu_12992_p2;
wire [0:0] y1a_V_7_fu_12974_p2;
wire [0:0] y0a_V_7_fu_12854_p2;
wire [2:0] p_Result_1307_7_fu_13168_p4;
wire [0:0] y2b_V_7_fu_13148_p2;
wire [0:0] y1b_V_7_fu_13130_p2;
wire [0:0] y0b_V_7_fu_13010_p2;
wire [2:0] p_Result_1311_7_fu_13182_p4;
wire [3:0] tmp_1399_7_fu_13192_p1;
wire [3:0] tmp_1397_7_fu_13164_p1;
wire [3:0] tmp_1398_7_fu_13178_p1;
wire [3:0] tmp729_fu_13196_p2;
wire [3:0] p_0190_i_7_fu_13202_p2;
wire [0:0] tmp_1793_fu_13218_p3;
wire [11:0] p_33_8_fu_13226_p2;
wire [11:0] p_Val2_398_8_fu_13232_p3;
wire [0:0] tmp_1797_fu_13264_p1;
wire [0:0] tmp_1796_fu_13256_p3;
wire [0:0] tmp_1794_fu_13240_p3;
wire [0:0] tmp_1795_fu_13248_p3;
wire [0:0] tmp893_fu_13338_p2;
wire [0:0] tmp892_fu_13332_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_8_fu_13350_p2;
wire [0:0] lhs_i_i147_0_i_8_fu_13356_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_8_fu_13368_p2;
wire [0:0] lhs_i_i141_0_i_8_fu_13380_p2;
wire [0:0] rhs_i_i140_0_i_8_fu_13386_p2;
wire [0:0] lhs_i_i135_0_i_8_fu_13398_p2;
wire [0:0] tmp895_fu_13404_p2;
wire [0:0] tmp894_fu_13392_p2;
wire [0:0] lhs_i_i145_0_i_8_fu_13374_p2;
wire [0:0] rhs_i138_0_i_7_fu_13422_p2;
wire [0:0] tmp896_fu_13428_p2;
wire [0:0] lhs_i143_0_i_8_fu_13362_p2;
wire [0:0] tmp898_fu_13440_p2;
wire [0:0] rhs_i_i130_0_i_8_fu_13416_p2;
wire [0:0] rhs_i126_0_i_7_fu_13446_p2;
wire [0:0] tmp899_fu_13452_p2;
wire [0:0] rhs_i132_0_i_8_fu_13410_p2;
wire [0:0] tmp900_fu_13458_p2;
wire [0:0] tmp897_fu_13434_p2;
wire [0:0] tmp901_fu_13470_p2;
wire [0:0] p_demorgan229722982301_i_8_fu_13476_p2;
wire [0:0] tmp_1801_fu_13292_p3;
wire [0:0] tmp_1800_fu_13284_p3;
wire [0:0] tmp_1798_fu_13268_p3;
wire [0:0] tmp_1799_fu_13276_p3;
wire [0:0] tmp903_fu_13494_p2;
wire [0:0] tmp902_fu_13488_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_8_fu_13506_p2;
wire [0:0] lhs_i_i103_0_i_8_fu_13512_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_8_fu_13524_p2;
wire [0:0] lhs_i_i97_0_i_8_fu_13536_p2;
wire [0:0] rhs_i_i96_0_i_8_fu_13542_p2;
wire [0:0] lhs_i_i91_0_i_8_fu_13554_p2;
wire [0:0] tmp905_fu_13560_p2;
wire [0:0] tmp904_fu_13548_p2;
wire [0:0] lhs_i_i101_0_i_8_fu_13530_p2;
wire [0:0] rhs_i94_0_i_7_fu_13578_p2;
wire [0:0] tmp906_fu_13584_p2;
wire [0:0] lhs_i99_0_i_8_fu_13518_p2;
wire [0:0] tmp908_fu_13596_p2;
wire [0:0] rhs_i_i86_0_i_8_fu_13572_p2;
wire [0:0] rhs_i82_0_i_7_fu_13602_p2;
wire [0:0] tmp909_fu_13608_p2;
wire [0:0] rhs_i88_0_i_8_fu_13566_p2;
wire [0:0] tmp910_fu_13614_p2;
wire [0:0] tmp907_fu_13590_p2;
wire [0:0] tmp911_fu_13626_p2;
wire [0:0] p_demorgan230523062309_i_8_fu_13632_p2;
wire [0:0] tmp_1805_fu_13324_p3;
wire [0:0] tmp_1804_fu_13316_p3;
wire [0:0] tmp_1802_fu_13300_p3;
wire [0:0] tmp_1803_fu_13308_p3;
wire [0:0] tmp913_fu_13650_p2;
wire [0:0] tmp912_fu_13644_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_8_fu_13662_p2;
wire [0:0] lhs_i_i59_0_i1_8_fu_13668_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_8_fu_13680_p2;
wire [0:0] lhs_i_i53_0_i_8_fu_13692_p2;
wire [0:0] rhs_i_i52_0_i_8_fu_13698_p2;
wire [0:0] lhs_i_i47_0_i_8_fu_13710_p2;
wire [0:0] tmp915_fu_13716_p2;
wire [0:0] tmp914_fu_13704_p2;
wire [0:0] lhs_i_i57_0_i_8_fu_13686_p2;
wire [0:0] rhs_i50_0_i1_7_fu_13734_p2;
wire [0:0] tmp916_fu_13740_p2;
wire [0:0] lhs_i55_0_i_8_fu_13674_p2;
wire [0:0] tmp918_fu_13752_p2;
wire [0:0] rhs_i_i42_0_i_8_fu_13728_p2;
wire [0:0] rhs_i38_0_i_7_fu_13758_p2;
wire [0:0] tmp919_fu_13764_p2;
wire [0:0] rhs_i44_0_i_8_fu_13722_p2;
wire [0:0] tmp920_fu_13770_p2;
wire [0:0] tmp917_fu_13746_p2;
wire [0:0] tmp921_fu_13782_p2;
wire [0:0] p_demorgan231323142317_i_8_fu_13788_p2;
wire [0:0] y2_V_8_fu_13482_p2;
wire [0:0] y1_V_8_fu_13464_p2;
wire [0:0] y0_V_8_fu_13344_p2;
wire [2:0] p_Result_1303_8_fu_13800_p4;
wire [0:0] y2a_V_8_fu_13638_p2;
wire [0:0] y1a_V_8_fu_13620_p2;
wire [0:0] y0a_V_8_fu_13500_p2;
wire [2:0] p_Result_1307_8_fu_13814_p4;
wire [0:0] y2b_V_8_fu_13794_p2;
wire [0:0] y1b_V_8_fu_13776_p2;
wire [0:0] y0b_V_8_fu_13656_p2;
wire [2:0] p_Result_1311_8_fu_13828_p4;
wire [3:0] tmp_1399_8_fu_13838_p1;
wire [3:0] tmp_1397_8_fu_13810_p1;
wire [3:0] tmp_1398_8_fu_13824_p1;
wire [3:0] tmp922_fu_13842_p2;
wire [3:0] p_0190_i_8_fu_13848_p2;
wire [0:0] tmp_1820_fu_13864_p3;
wire [11:0] p_33_9_fu_13872_p2;
wire [11:0] p_Val2_398_9_fu_13878_p3;
wire [0:0] tmp_1824_fu_13910_p1;
wire [0:0] tmp_1823_fu_13902_p3;
wire [0:0] tmp_1821_fu_13886_p3;
wire [0:0] tmp_1822_fu_13894_p3;
wire [0:0] tmp924_fu_13984_p2;
wire [0:0] tmp923_fu_13978_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_9_fu_13996_p2;
wire [0:0] lhs_i_i147_0_i_9_fu_14002_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_9_fu_14014_p2;
wire [0:0] lhs_i_i141_0_i_9_fu_14026_p2;
wire [0:0] rhs_i_i140_0_i_9_fu_14032_p2;
wire [0:0] lhs_i_i135_0_i_9_fu_14044_p2;
wire [0:0] tmp926_fu_14050_p2;
wire [0:0] tmp925_fu_14038_p2;
wire [0:0] lhs_i_i145_0_i_9_fu_14020_p2;
wire [0:0] rhs_i138_0_i_8_fu_14068_p2;
wire [0:0] tmp927_fu_14074_p2;
wire [0:0] lhs_i143_0_i_9_fu_14008_p2;
wire [0:0] tmp929_fu_14086_p2;
wire [0:0] rhs_i_i130_0_i_9_fu_14062_p2;
wire [0:0] rhs_i126_0_i_8_fu_14092_p2;
wire [0:0] tmp930_fu_14098_p2;
wire [0:0] rhs_i132_0_i_9_fu_14056_p2;
wire [0:0] tmp931_fu_14104_p2;
wire [0:0] tmp928_fu_14080_p2;
wire [0:0] tmp932_fu_14116_p2;
wire [0:0] p_demorgan229722982301_i_9_fu_14122_p2;
wire [0:0] tmp_1828_fu_13938_p3;
wire [0:0] tmp_1827_fu_13930_p3;
wire [0:0] tmp_1825_fu_13914_p3;
wire [0:0] tmp_1826_fu_13922_p3;
wire [0:0] tmp934_fu_14140_p2;
wire [0:0] tmp933_fu_14134_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_9_fu_14152_p2;
wire [0:0] lhs_i_i103_0_i_9_fu_14158_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_9_fu_14170_p2;
wire [0:0] lhs_i_i97_0_i_9_fu_14182_p2;
wire [0:0] rhs_i_i96_0_i_9_fu_14188_p2;
wire [0:0] lhs_i_i91_0_i_9_fu_14200_p2;
wire [0:0] tmp936_fu_14206_p2;
wire [0:0] tmp935_fu_14194_p2;
wire [0:0] lhs_i_i101_0_i_9_fu_14176_p2;
wire [0:0] rhs_i94_0_i_8_fu_14224_p2;
wire [0:0] tmp937_fu_14230_p2;
wire [0:0] lhs_i99_0_i_9_fu_14164_p2;
wire [0:0] tmp939_fu_14242_p2;
wire [0:0] rhs_i_i86_0_i_9_fu_14218_p2;
wire [0:0] rhs_i82_0_i_8_fu_14248_p2;
wire [0:0] tmp940_fu_14254_p2;
wire [0:0] rhs_i88_0_i_9_fu_14212_p2;
wire [0:0] tmp941_fu_14260_p2;
wire [0:0] tmp938_fu_14236_p2;
wire [0:0] tmp942_fu_14272_p2;
wire [0:0] p_demorgan230523062309_i_9_fu_14278_p2;
wire [0:0] tmp_1832_fu_13970_p3;
wire [0:0] tmp_1831_fu_13962_p3;
wire [0:0] tmp_1829_fu_13946_p3;
wire [0:0] tmp_1830_fu_13954_p3;
wire [0:0] tmp944_fu_14296_p2;
wire [0:0] tmp943_fu_14290_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_9_fu_14308_p2;
wire [0:0] lhs_i_i59_0_i1_9_fu_14314_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_9_fu_14326_p2;
wire [0:0] lhs_i_i53_0_i_9_fu_14338_p2;
wire [0:0] rhs_i_i52_0_i_9_fu_14344_p2;
wire [0:0] lhs_i_i47_0_i_9_fu_14356_p2;
wire [0:0] tmp946_fu_14362_p2;
wire [0:0] tmp945_fu_14350_p2;
wire [0:0] lhs_i_i57_0_i_9_fu_14332_p2;
wire [0:0] rhs_i50_0_i1_8_fu_14380_p2;
wire [0:0] tmp947_fu_14386_p2;
wire [0:0] lhs_i55_0_i_9_fu_14320_p2;
wire [0:0] tmp949_fu_14398_p2;
wire [0:0] rhs_i_i42_0_i_9_fu_14374_p2;
wire [0:0] rhs_i38_0_i_8_fu_14404_p2;
wire [0:0] tmp950_fu_14410_p2;
wire [0:0] rhs_i44_0_i_9_fu_14368_p2;
wire [0:0] tmp951_fu_14416_p2;
wire [0:0] tmp948_fu_14392_p2;
wire [0:0] tmp952_fu_14428_p2;
wire [0:0] p_demorgan231323142317_i_9_fu_14434_p2;
wire [0:0] y2_V_9_fu_14128_p2;
wire [0:0] y1_V_9_fu_14110_p2;
wire [0:0] y0_V_9_fu_13990_p2;
wire [2:0] p_Result_1303_9_fu_14446_p4;
wire [0:0] y2a_V_9_fu_14284_p2;
wire [0:0] y1a_V_9_fu_14266_p2;
wire [0:0] y0a_V_9_fu_14146_p2;
wire [2:0] p_Result_1307_9_fu_14460_p4;
wire [0:0] y2b_V_9_fu_14440_p2;
wire [0:0] y1b_V_9_fu_14422_p2;
wire [0:0] y0b_V_9_fu_14302_p2;
wire [2:0] p_Result_1311_9_fu_14474_p4;
wire [3:0] tmp_1399_9_fu_14484_p1;
wire [3:0] tmp_1397_9_fu_14456_p1;
wire [3:0] tmp_1398_9_fu_14470_p1;
wire [3:0] tmp953_fu_14488_p2;
wire [3:0] p_0190_i_9_fu_14494_p2;
wire [0:0] tmp_1847_fu_14510_p3;
wire [11:0] p_33_s_fu_14518_p2;
wire [11:0] p_Val2_398_s_fu_14524_p3;
wire [0:0] tmp_1851_fu_14556_p1;
wire [0:0] tmp_1850_fu_14548_p3;
wire [0:0] tmp_1848_fu_14532_p3;
wire [0:0] tmp_1849_fu_14540_p3;
wire [0:0] tmp955_fu_14630_p2;
wire [0:0] tmp954_fu_14624_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_s_fu_14642_p2;
wire [0:0] lhs_i_i147_0_i_s_fu_14648_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_s_fu_14660_p2;
wire [0:0] lhs_i_i141_0_i_s_fu_14672_p2;
wire [0:0] rhs_i_i140_0_i_s_fu_14678_p2;
wire [0:0] lhs_i_i135_0_i_s_fu_14690_p2;
wire [0:0] tmp957_fu_14696_p2;
wire [0:0] tmp956_fu_14684_p2;
wire [0:0] lhs_i_i145_0_i_s_fu_14666_p2;
wire [0:0] rhs_i138_0_i_9_fu_14714_p2;
wire [0:0] tmp958_fu_14720_p2;
wire [0:0] lhs_i143_0_i_s_fu_14654_p2;
wire [0:0] tmp960_fu_14732_p2;
wire [0:0] rhs_i_i130_0_i_s_fu_14708_p2;
wire [0:0] rhs_i126_0_i_9_fu_14738_p2;
wire [0:0] tmp961_fu_14744_p2;
wire [0:0] rhs_i132_0_i_s_fu_14702_p2;
wire [0:0] tmp962_fu_14750_p2;
wire [0:0] tmp959_fu_14726_p2;
wire [0:0] tmp963_fu_14762_p2;
wire [0:0] p_demorgan229722982301_i_s_fu_14768_p2;
wire [0:0] tmp_1855_fu_14584_p3;
wire [0:0] tmp_1854_fu_14576_p3;
wire [0:0] tmp_1852_fu_14560_p3;
wire [0:0] tmp_1853_fu_14568_p3;
wire [0:0] tmp965_fu_14786_p2;
wire [0:0] tmp964_fu_14780_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_s_fu_14798_p2;
wire [0:0] lhs_i_i103_0_i_s_fu_14804_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_s_fu_14816_p2;
wire [0:0] lhs_i_i97_0_i_s_fu_14828_p2;
wire [0:0] rhs_i_i96_0_i_s_fu_14834_p2;
wire [0:0] lhs_i_i91_0_i_s_fu_14846_p2;
wire [0:0] tmp967_fu_14852_p2;
wire [0:0] tmp966_fu_14840_p2;
wire [0:0] lhs_i_i101_0_i_s_fu_14822_p2;
wire [0:0] rhs_i94_0_i_9_fu_14870_p2;
wire [0:0] tmp968_fu_14876_p2;
wire [0:0] lhs_i99_0_i_s_fu_14810_p2;
wire [0:0] tmp970_fu_14888_p2;
wire [0:0] rhs_i_i86_0_i_s_fu_14864_p2;
wire [0:0] rhs_i82_0_i_9_fu_14894_p2;
wire [0:0] tmp971_fu_14900_p2;
wire [0:0] rhs_i88_0_i_s_fu_14858_p2;
wire [0:0] tmp972_fu_14906_p2;
wire [0:0] tmp969_fu_14882_p2;
wire [0:0] tmp973_fu_14918_p2;
wire [0:0] p_demorgan230523062309_i_s_fu_14924_p2;
wire [0:0] tmp_1859_fu_14616_p3;
wire [0:0] tmp_1858_fu_14608_p3;
wire [0:0] tmp_1856_fu_14592_p3;
wire [0:0] tmp_1857_fu_14600_p3;
wire [0:0] tmp975_fu_14942_p2;
wire [0:0] tmp974_fu_14936_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_s_fu_14954_p2;
wire [0:0] lhs_i_i59_0_i1_s_fu_14960_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_s_fu_14972_p2;
wire [0:0] lhs_i_i53_0_i_s_fu_14984_p2;
wire [0:0] rhs_i_i52_0_i_s_fu_14990_p2;
wire [0:0] lhs_i_i47_0_i_s_fu_15002_p2;
wire [0:0] tmp977_fu_15008_p2;
wire [0:0] tmp976_fu_14996_p2;
wire [0:0] lhs_i_i57_0_i_s_fu_14978_p2;
wire [0:0] rhs_i50_0_i1_9_fu_15026_p2;
wire [0:0] tmp978_fu_15032_p2;
wire [0:0] lhs_i55_0_i_s_fu_14966_p2;
wire [0:0] tmp980_fu_15044_p2;
wire [0:0] rhs_i_i42_0_i_s_fu_15020_p2;
wire [0:0] rhs_i38_0_i_9_fu_15050_p2;
wire [0:0] tmp981_fu_15056_p2;
wire [0:0] rhs_i44_0_i_s_fu_15014_p2;
wire [0:0] tmp982_fu_15062_p2;
wire [0:0] tmp979_fu_15038_p2;
wire [0:0] tmp983_fu_15074_p2;
wire [0:0] p_demorgan231323142317_i_s_fu_15080_p2;
wire [0:0] y2_V_s_fu_14774_p2;
wire [0:0] y1_V_s_fu_14756_p2;
wire [0:0] y0_V_s_fu_14636_p2;
wire [2:0] p_Result_1303_s_fu_15092_p4;
wire [0:0] y2a_V_s_fu_14930_p2;
wire [0:0] y1a_V_s_fu_14912_p2;
wire [0:0] y0a_V_s_fu_14792_p2;
wire [2:0] p_Result_1307_s_fu_15106_p4;
wire [0:0] y2b_V_s_fu_15086_p2;
wire [0:0] y1b_V_s_fu_15068_p2;
wire [0:0] y0b_V_s_fu_14948_p2;
wire [2:0] p_Result_1311_s_fu_15120_p4;
wire [3:0] tmp_1399_s_fu_15130_p1;
wire [3:0] tmp_1397_s_fu_15102_p1;
wire [3:0] tmp_1398_s_fu_15116_p1;
wire [3:0] tmp984_fu_15134_p2;
wire [3:0] p_0190_i_s_fu_15140_p2;
wire [11:0] larger_V_11_s_fu_5482_p3;
wire [0:0] tmp_1874_fu_15156_p3;
wire [11:0] p_33_10_fu_15164_p2;
wire [11:0] p_Val2_398_10_fu_15170_p3;
wire [0:0] tmp_1878_fu_15202_p1;
wire [0:0] tmp_1877_fu_15194_p3;
wire [0:0] tmp_1875_fu_15178_p3;
wire [0:0] tmp_1876_fu_15186_p3;
wire [0:0] tmp986_fu_15276_p2;
wire [0:0] tmp985_fu_15270_p2;
wire [0:0] lhs_i_i147_0_demorgan2294_i_10_fu_15288_p2;
wire [0:0] lhs_i_i147_0_i_10_fu_15294_p2;
wire [0:0] lhs_i_i145_0_demorgan2295_i_10_fu_15306_p2;
wire [0:0] lhs_i_i141_0_i_10_fu_15318_p2;
wire [0:0] rhs_i_i140_0_i_10_fu_15324_p2;
wire [0:0] lhs_i_i135_0_i_10_fu_15336_p2;
wire [0:0] tmp988_fu_15342_p2;
wire [0:0] tmp987_fu_15330_p2;
wire [0:0] lhs_i_i145_0_i_10_fu_15312_p2;
wire [0:0] rhs_i138_0_i_10_fu_15360_p2;
wire [0:0] tmp989_fu_15366_p2;
wire [0:0] lhs_i143_0_i_10_fu_15300_p2;
wire [0:0] tmp991_fu_15378_p2;
wire [0:0] rhs_i_i130_0_i_10_fu_15354_p2;
wire [0:0] rhs_i126_0_i_10_fu_15384_p2;
wire [0:0] tmp992_fu_15390_p2;
wire [0:0] rhs_i132_0_i_10_fu_15348_p2;
wire [0:0] tmp993_fu_15396_p2;
wire [0:0] tmp990_fu_15372_p2;
wire [0:0] tmp994_fu_15408_p2;
wire [0:0] p_demorgan229722982301_i_10_fu_15414_p2;
wire [0:0] tmp_1882_fu_15230_p3;
wire [0:0] tmp_1881_fu_15222_p3;
wire [0:0] tmp_1879_fu_15206_p3;
wire [0:0] tmp_1880_fu_15214_p3;
wire [0:0] tmp996_fu_15432_p2;
wire [0:0] tmp995_fu_15426_p2;
wire [0:0] lhs_i_i103_0_demorgan2302_i_10_fu_15444_p2;
wire [0:0] lhs_i_i103_0_i_10_fu_15450_p2;
wire [0:0] lhs_i_i101_0_demorgan2303_i_10_fu_15462_p2;
wire [0:0] lhs_i_i97_0_i_10_fu_15474_p2;
wire [0:0] rhs_i_i96_0_i_10_fu_15480_p2;
wire [0:0] lhs_i_i91_0_i_10_fu_15492_p2;
wire [0:0] tmp998_fu_15498_p2;
wire [0:0] tmp997_fu_15486_p2;
wire [0:0] lhs_i_i101_0_i_10_fu_15468_p2;
wire [0:0] rhs_i94_0_i_10_fu_15516_p2;
wire [0:0] tmp999_fu_15522_p2;
wire [0:0] lhs_i99_0_i_10_fu_15456_p2;
wire [0:0] tmp1001_fu_15534_p2;
wire [0:0] rhs_i_i86_0_i_10_fu_15510_p2;
wire [0:0] rhs_i82_0_i_10_fu_15540_p2;
wire [0:0] tmp1002_fu_15546_p2;
wire [0:0] rhs_i88_0_i_10_fu_15504_p2;
wire [0:0] tmp1003_fu_15552_p2;
wire [0:0] tmp1000_fu_15528_p2;
wire [0:0] tmp1004_fu_15564_p2;
wire [0:0] p_demorgan230523062309_i_10_fu_15570_p2;
wire [0:0] tmp_1886_fu_15262_p3;
wire [0:0] tmp_1885_fu_15254_p3;
wire [0:0] tmp_1883_fu_15238_p3;
wire [0:0] tmp_1884_fu_15246_p3;
wire [0:0] tmp1006_fu_15588_p2;
wire [0:0] tmp1005_fu_15582_p2;
wire [0:0] lhs_i_i59_0_demorgan2310_i_10_fu_15600_p2;
wire [0:0] lhs_i_i59_0_i1_10_fu_15606_p2;
wire [0:0] lhs_i_i57_0_demorgan2311_i_10_fu_15618_p2;
wire [0:0] lhs_i_i53_0_i_10_fu_15630_p2;
wire [0:0] rhs_i_i52_0_i_10_fu_15636_p2;
wire [0:0] lhs_i_i47_0_i_10_fu_15648_p2;
wire [0:0] tmp1008_fu_15654_p2;
wire [0:0] tmp1007_fu_15642_p2;
wire [0:0] lhs_i_i57_0_i_10_fu_15624_p2;
wire [0:0] rhs_i50_0_i1_10_fu_15672_p2;
wire [0:0] tmp1009_fu_15678_p2;
wire [0:0] lhs_i55_0_i_10_fu_15612_p2;
wire [0:0] tmp1011_fu_15690_p2;
wire [0:0] rhs_i_i42_0_i_10_fu_15666_p2;
wire [0:0] rhs_i38_0_i_10_fu_15696_p2;
wire [0:0] tmp1012_fu_15702_p2;
wire [0:0] rhs_i44_0_i_10_fu_15660_p2;
wire [0:0] tmp1013_fu_15708_p2;
wire [0:0] tmp1010_fu_15684_p2;
wire [0:0] tmp1014_fu_15720_p2;
wire [0:0] p_demorgan231323142317_i_10_fu_15726_p2;
wire [0:0] y2_V_10_fu_15420_p2;
wire [0:0] y1_V_10_fu_15402_p2;
wire [0:0] y0_V_10_fu_15282_p2;
wire [2:0] p_Result_1303_10_fu_15738_p4;
wire [0:0] y2a_V_10_fu_15576_p2;
wire [0:0] y1a_V_10_fu_15558_p2;
wire [0:0] y0a_V_10_fu_15438_p2;
wire [2:0] p_Result_1307_10_fu_15752_p4;
wire [0:0] y2b_V_10_fu_15732_p2;
wire [0:0] y1b_V_10_fu_15714_p2;
wire [0:0] y0b_V_10_fu_15594_p2;
wire [2:0] p_Result_1311_10_fu_15766_p4;
wire [3:0] tmp_1399_10_fu_15776_p1;
wire [3:0] tmp_1397_10_fu_15748_p1;
wire [3:0] tmp_1398_10_fu_15762_p1;
wire [3:0] tmp1015_fu_15780_p2;
wire [3:0] p_0190_i_10_fu_15786_p2;
wire [5:0] tmp_1618_fu_16814_p1;
wire [35:0] tmp_1619_fu_16817_p1;
wire [35:0] tmp_1620_fu_16821_p2;
wire [11:0] tmp_1621_fu_16826_p1;
wire [35:0] tmp_1624_fu_16840_p1;
wire [35:0] tmp_1625_fu_16843_p2;
wire [35:0] tmp_1626_fu_16849_p2;
reg [11:0] tmp_1622_fu_16830_p4;
wire [35:0] tmp_1628_fu_16860_p1;
wire [35:0] tmp_1627_fu_16855_p2;
wire [35:0] tmp_1629_fu_16864_p2;
wire [35:0] winner_V_11_fu_16870_p2;
wire [4:0] p_shl8_fu_16889_p3;
wire [6:0] p_shl7_fu_16882_p3;
wire [6:0] p_shl8_cast_fu_16896_p1;
wire [6:0] tmp_337_fu_16900_p2;
wire [5:0] tmp_1645_fu_16906_p1;
wire [35:0] winner_V_1_fu_16876_p3;
wire [35:0] tmp_1646_fu_16910_p1;
wire [35:0] tmp_1647_fu_16914_p2;
wire [11:0] tmp_1648_fu_16920_p1;
wire [5:0] tmp_1650_fu_16934_p1;
wire [35:0] tmp_1651_fu_16938_p1;
wire [35:0] tmp_1652_fu_16942_p2;
wire [35:0] tmp_1653_fu_16948_p2;
reg [11:0] tmp_1649_fu_16924_p4;
wire [35:0] tmp_1655_fu_16960_p1;
wire [35:0] tmp_1654_fu_16954_p2;
wire [35:0] tmp_1656_fu_16964_p2;
wire [35:0] winner_V_12_fu_16970_p2;
wire [4:0] p_shl1_fu_16990_p3;
wire [6:0] p_shl9_fu_16983_p3;
wire [6:0] p_shl1_cast_fu_16997_p1;
wire [6:0] tmp_339_fu_17001_p2;
wire [5:0] tmp_1672_fu_17007_p1;
wire [35:0] winner_V_2_fu_16976_p3;
wire [35:0] tmp_1673_fu_17011_p1;
wire [35:0] tmp_1674_fu_17015_p2;
wire [11:0] tmp_1675_fu_17021_p1;
wire [5:0] tmp_1677_fu_17035_p1;
wire [35:0] tmp_1678_fu_17039_p1;
wire [35:0] tmp_1679_fu_17043_p2;
wire [35:0] tmp_1680_fu_17049_p2;
reg [11:0] tmp_1676_fu_17025_p4;
wire [35:0] tmp_1682_fu_17061_p1;
wire [35:0] tmp_1681_fu_17055_p2;
wire [35:0] tmp_1683_fu_17065_p2;
wire [35:0] winner_V_13_fu_17071_p2;
wire [4:0] p_shl3_fu_17091_p3;
wire [6:0] p_shl2_fu_17084_p3;
wire [6:0] p_shl3_cast_fu_17098_p1;
wire [6:0] tmp_341_fu_17102_p2;
wire [5:0] tmp_1699_fu_17108_p1;
wire [35:0] winner_V_3_fu_17077_p3;
wire [35:0] tmp_1700_fu_17112_p1;
wire [35:0] tmp_1701_fu_17116_p2;
wire [11:0] tmp_1702_fu_17122_p1;
wire [5:0] tmp_1704_fu_17136_p1;
wire [35:0] tmp_1705_fu_17140_p1;
wire [35:0] tmp_1706_fu_17144_p2;
wire [35:0] tmp_1707_fu_17150_p2;
reg [11:0] tmp_1703_fu_17126_p4;
wire [35:0] tmp_1709_fu_17162_p1;
wire [35:0] tmp_1708_fu_17156_p2;
wire [35:0] tmp_1710_fu_17166_p2;
wire [35:0] winner_V_14_fu_17172_p2;
wire [4:0] p_shl10_fu_17192_p3;
wire [6:0] p_shl_fu_17185_p3;
wire [6:0] p_shl11_cast_fu_17199_p1;
wire [6:0] tmp_343_fu_17203_p2;
wire [5:0] tmp_1726_fu_17209_p1;
wire [35:0] winner_V_4_fu_17178_p3;
wire [35:0] tmp_1727_fu_17213_p1;
wire [35:0] tmp_1728_fu_17217_p2;
wire [11:0] tmp_1729_fu_17223_p1;
wire [5:0] tmp_1731_fu_17237_p1;
wire [35:0] tmp_1732_fu_17241_p1;
wire [35:0] tmp_1733_fu_17245_p2;
wire [35:0] tmp_1734_fu_17251_p2;
reg [11:0] tmp_1730_fu_17227_p4;
wire [35:0] tmp_1736_fu_17263_p1;
wire [35:0] tmp_1735_fu_17257_p2;
wire [35:0] tmp_1737_fu_17267_p2;
wire [35:0] winner_V_15_fu_17273_p2;
wire [4:0] p_shl12_fu_17293_p3;
wire [6:0] p_shl11_fu_17286_p3;
wire [6:0] p_shl13_cast_fu_17300_p1;
wire [6:0] tmp_345_fu_17304_p2;
wire [5:0] tmp_1753_fu_17310_p1;
wire [35:0] winner_V_5_fu_17279_p3;
wire [35:0] tmp_1754_fu_17314_p1;
wire [35:0] tmp_1755_fu_17318_p2;
wire [11:0] tmp_1756_fu_17324_p1;
wire [5:0] tmp_1758_fu_17338_p1;
wire [35:0] tmp_1759_fu_17342_p1;
wire [35:0] tmp_1760_fu_17346_p2;
wire [35:0] tmp_1761_fu_17352_p2;
reg [11:0] tmp_1757_fu_17328_p4;
wire [35:0] tmp_1763_fu_17364_p1;
wire [35:0] tmp_1762_fu_17358_p2;
wire [35:0] tmp_1764_fu_17368_p2;
wire [35:0] winner_V_16_fu_17374_p2;
wire [4:0] p_shl14_fu_17394_p3;
wire [6:0] p_shl13_fu_17387_p3;
wire [6:0] p_shl15_cast_fu_17401_p1;
wire [6:0] tmp_347_fu_17405_p2;
wire [5:0] tmp_1780_fu_17411_p1;
wire [35:0] winner_V_6_fu_17380_p3;
wire [35:0] tmp_1781_fu_17415_p1;
wire [35:0] tmp_1782_fu_17419_p2;
wire [11:0] tmp_1783_fu_17425_p1;
wire [5:0] tmp_1785_fu_17439_p1;
wire [35:0] tmp_1786_fu_17443_p1;
wire [35:0] tmp_1787_fu_17447_p2;
wire [35:0] tmp_1788_fu_17453_p2;
reg [11:0] tmp_1784_fu_17429_p4;
wire [35:0] tmp_1790_fu_17465_p1;
wire [35:0] tmp_1789_fu_17459_p2;
wire [35:0] tmp_1791_fu_17469_p2;
wire [35:0] winner_V_17_fu_17475_p2;
wire [4:0] p_shl16_fu_17504_p3;
wire [6:0] p_shl15_fu_17497_p3;
wire [6:0] p_shl17_cast_fu_17511_p1;
wire [6:0] tmp_349_fu_17515_p2;
wire [5:0] tmp_1807_fu_17521_p1;
wire [35:0] tmp_1808_fu_17525_p1;
wire [35:0] tmp_1809_fu_17529_p2;
wire [11:0] tmp_1810_fu_17534_p1;
wire [5:0] tmp_1812_fu_17548_p1;
wire [35:0] tmp_1813_fu_17552_p1;
wire [35:0] tmp_1814_fu_17556_p2;
wire [35:0] tmp_1815_fu_17562_p2;
reg [11:0] tmp_1811_fu_17538_p4;
wire [35:0] tmp_1817_fu_17573_p1;
wire [35:0] tmp_1816_fu_17568_p2;
wire [35:0] tmp_1818_fu_17577_p2;
wire [35:0] winner_V_18_fu_17583_p2;
wire [4:0] p_shl18_fu_17602_p3;
wire [6:0] p_shl17_fu_17595_p3;
wire [6:0] p_shl19_cast_fu_17609_p1;
wire [6:0] tmp_351_fu_17613_p2;
wire [5:0] tmp_1834_fu_17619_p1;
wire [35:0] winner_V_8_fu_17589_p3;
wire [35:0] tmp_1835_fu_17623_p1;
wire [35:0] tmp_1836_fu_17627_p2;
wire [11:0] tmp_1837_fu_17633_p1;
wire [5:0] tmp_1839_fu_17647_p1;
wire [35:0] tmp_1840_fu_17651_p1;
wire [35:0] tmp_1841_fu_17655_p2;
wire [35:0] tmp_1842_fu_17661_p2;
reg [11:0] tmp_1838_fu_17637_p4;
wire [35:0] tmp_1844_fu_17673_p1;
wire [35:0] tmp_1843_fu_17667_p2;
wire [35:0] tmp_1845_fu_17677_p2;
wire [35:0] winner_V_19_fu_17683_p2;
wire [4:0] p_shl20_fu_17703_p3;
wire [6:0] p_shl19_fu_17696_p3;
wire [6:0] p_shl21_cast_fu_17710_p1;
wire [6:0] tmp_353_fu_17714_p2;
wire [5:0] tmp_1861_fu_17720_p1;
wire [35:0] winner_V_9_fu_17689_p3;
wire [35:0] tmp_1862_fu_17724_p1;
wire [35:0] tmp_1863_fu_17728_p2;
wire [11:0] tmp_1864_fu_17734_p1;
wire [5:0] tmp_1866_fu_17748_p1;
wire [35:0] tmp_1867_fu_17752_p1;
wire [35:0] tmp_1868_fu_17756_p2;
wire [35:0] tmp_1869_fu_17762_p2;
reg [11:0] tmp_1865_fu_17738_p4;
wire [35:0] tmp_1871_fu_17774_p1;
wire [35:0] tmp_1870_fu_17768_p2;
wire [35:0] tmp_1872_fu_17778_p2;
wire [35:0] winner_V_20_fu_17784_p2;
wire [4:0] p_shl22_fu_17804_p3;
wire [6:0] p_shl21_fu_17797_p3;
wire [6:0] p_shl23_cast_fu_17811_p1;
wire [6:0] tmp_355_fu_17815_p2;
wire [5:0] tmp_1888_fu_17821_p1;
wire [35:0] winner_V_s_fu_17790_p3;
wire [35:0] tmp_1889_fu_17825_p1;
wire [35:0] tmp_1890_fu_17829_p2;
wire [11:0] tmp_1891_fu_17835_p1;
wire [5:0] tmp_1893_fu_17849_p1;
wire [35:0] tmp_1894_fu_17853_p1;
wire [35:0] tmp_1895_fu_17857_p2;
wire [35:0] tmp_1896_fu_17863_p2;
reg [11:0] tmp_1892_fu_17839_p4;
wire [35:0] tmp_1898_fu_17875_p1;
wire [35:0] tmp_1897_fu_17869_p2;
wire [35:0] tmp_1899_fu_17879_p2;
wire [35:0] winner_V_21_fu_17885_p2;
wire [35:0] winner_V_10_fu_17891_p3;
reg [4:0] cn_si_0_0_V_fu_17488_p4;
wire [1:0] tmp_1902_fu_17902_p1;
wire [0:0] tmp_1901_fu_17898_p1;
wire [4:0] p_Result_1296_0_0_4_fu_17906_p4;
wire [5:0] bt_sign_ph_V_fu_18041_p3;
wire [0:0] tmp_1904_fu_18078_p1;
wire [5:0] bt_sign_th_V_fu_18048_p3;
wire [0:0] tmp_1906_fu_18087_p1;
wire [0:0] tmp_1908_fu_18096_p3;
wire [0:0] tmp_1910_fu_18109_p3;
wire [0:0] tmp_1912_fu_18122_p3;
wire [0:0] tmp_1914_fu_18135_p3;
wire [0:0] tmp_1916_fu_18148_p3;
wire [0:0] tmp_1918_fu_18161_p3;
wire [0:0] tmp_1920_fu_18174_p3;
wire [0:0] tmp_1922_fu_18187_p3;
wire [0:0] tmp_1924_fu_18200_p3;
wire [0:0] tmp_366_fu_18208_p2;
wire [0:0] tmp_364_fu_18182_p2;
wire [0:0] tmp_362_fu_18156_p2;
wire [0:0] tmp_360_fu_18130_p2;
wire [0:0] tmp_358_fu_18104_p2;
wire [0:0] tmp_356_fu_18082_p2;
wire [0:0] tmp_1926_fu_18229_p3;
wire [0:0] tmp_367_fu_18237_p2;
wire [0:0] tmp_365_fu_18195_p2;
wire [0:0] tmp_363_fu_18169_p2;
wire [0:0] tmp_361_fu_18143_p2;
wire [0:0] tmp_359_fu_18117_p2;
wire [0:0] tmp_357_fu_18091_p2;
wire [4:0] bt_si_V_fu_18062_p3;
wire [0:0] tmp_1928_fu_18258_p1;
wire [0:0] tmp_1930_fu_18267_p3;
wire [0:0] tmp_1931_fu_18280_p3;
wire [0:0] tmp_1932_fu_18293_p3;
wire [0:0] tmp_370_fu_18288_p2;
wire [0:0] tmp_369_fu_18275_p2;
wire [0:0] tmp_368_fu_18262_p2;
wire [0:0] tmp_1903_fu_18070_p3;
wire [5:0] p_Result_1290_0_1_5_fu_18213_p7;
wire [5:0] p_Result_1293_0_1_5_fu_18242_p7;
wire [4:0] p_Result_1296_0_1_4_fu_18301_p6;
wire [5:0] bt_sign_ph_V_1_fu_18441_p3;
wire [0:0] tmp_1935_fu_18494_p1;
wire [5:0] bt_sign_th_V_1_fu_18449_p3;
wire [0:0] tmp_1937_fu_18503_p1;
wire [0:0] tmp_1939_fu_18512_p3;
wire [0:0] tmp_1941_fu_18525_p3;
wire [0:0] tmp_1943_fu_18538_p3;
wire [0:0] tmp_1945_fu_18551_p3;
wire [0:0] tmp_1947_fu_18564_p3;
wire [0:0] tmp_1949_fu_18577_p3;
wire [0:0] tmp_1951_fu_18590_p3;
wire [0:0] tmp_1953_fu_18603_p3;
wire [0:0] tmp_1955_fu_18616_p3;
wire [0:0] tmp_381_fu_18624_p2;
wire [0:0] tmp_379_fu_18598_p2;
wire [0:0] tmp_377_fu_18572_p2;
wire [0:0] tmp_375_fu_18546_p2;
wire [0:0] tmp_373_fu_18520_p2;
wire [0:0] tmp_371_fu_18498_p2;
wire [0:0] tmp_1957_fu_18645_p3;
wire [0:0] tmp_382_fu_18653_p2;
wire [0:0] tmp_380_fu_18611_p2;
wire [0:0] tmp_378_fu_18585_p2;
wire [0:0] tmp_376_fu_18559_p2;
wire [0:0] tmp_374_fu_18533_p2;
wire [0:0] tmp_372_fu_18507_p2;
wire [4:0] bt_si_V_1_fu_18478_p3;
wire [0:0] tmp_1959_fu_18674_p1;
wire [0:0] tmp_1961_fu_18683_p3;
wire [0:0] tmp_1962_fu_18696_p3;
wire [0:0] tmp_1963_fu_18709_p3;
wire [0:0] tmp_385_fu_18704_p2;
wire [0:0] tmp_384_fu_18691_p2;
wire [0:0] tmp_383_fu_18678_p2;
wire [0:0] tmp_1934_fu_18486_p3;
wire [5:0] p_Result_1290_0_2_5_fu_18629_p7;
wire [5:0] p_Result_1293_0_2_5_fu_18658_p7;
wire [4:0] p_Result_1296_0_2_4_fu_18717_p6;
wire [5:0] bt_sign_ph_V_2_fu_18857_p3;
wire [0:0] tmp_1965_fu_18904_p1;
wire [5:0] bt_sign_th_V_2_fu_18865_p3;
wire [0:0] tmp_1967_fu_18913_p1;
wire [0:0] tmp_1969_fu_18922_p3;
wire [0:0] tmp_1971_fu_18935_p3;
wire [0:0] tmp_1973_fu_18948_p3;
wire [0:0] tmp_1975_fu_18961_p3;
wire [0:0] tmp_1977_fu_18974_p3;
wire [0:0] tmp_1979_fu_18987_p3;
wire [0:0] tmp_1981_fu_19000_p3;
wire [0:0] tmp_1983_fu_19013_p3;
wire [0:0] tmp_1985_fu_19026_p3;
wire [0:0] tmp_396_fu_19034_p2;
wire [0:0] tmp_394_fu_19008_p2;
wire [0:0] tmp_392_fu_18982_p2;
wire [0:0] tmp_390_fu_18956_p2;
wire [0:0] tmp_388_fu_18930_p2;
wire [0:0] tmp_386_fu_18908_p2;
wire [0:0] tmp_1987_fu_19055_p3;
wire [0:0] tmp_397_fu_19063_p2;
wire [0:0] tmp_395_fu_19021_p2;
wire [0:0] tmp_393_fu_18995_p2;
wire [0:0] tmp_391_fu_18969_p2;
wire [0:0] tmp_389_fu_18943_p2;
wire [0:0] tmp_387_fu_18917_p2;
wire [4:0] bt_si_V_2_fu_18888_p3;
wire [0:0] tmp_1989_fu_19084_p1;
wire [0:0] tmp_1991_fu_19093_p3;
wire [0:0] tmp_1992_fu_19106_p3;
wire [0:0] tmp_1993_fu_19119_p3;
wire [0:0] tmp_400_fu_19114_p2;
wire [0:0] tmp_399_fu_19101_p2;
wire [0:0] tmp_398_fu_19088_p2;
wire [0:0] tmp_1964_fu_18896_p3;
wire [5:0] p_Result_1290_0_3_5_fu_19039_p7;
wire [5:0] p_Result_1293_0_3_5_fu_19068_p7;
wire [3:0] r_V_177_0_3_fu_19298_p3;
wire [2:0] tmp_1994_fu_19306_p1;
wire [2:0] r_V_177_0_2_fu_18880_p3;
wire [0:0] tmp_1995_fu_19316_p1;
wire [0:0] tmp_1933_fu_18472_p2;
wire [2:0] tmp_401_fu_19310_p2;
wire [1:0] tmp_1997_fu_19326_p4;
wire [0:0] tmp_1996_fu_19320_p2;
wire [0:0] tmp_1998_fu_19346_p2;
wire [0:0] tmp_1999_fu_19360_p1;
wire [2:0] tmp_2000_fu_19364_p1;
wire [2:0] tmp_2001_fu_19368_p3;
wire [2:0] tmp1033_fu_19352_p3;
wire [2:0] tmp_2002_fu_19376_p2;
wire [0:0] tmp_2003_fu_19390_p2;
wire [1:0] tmp_2004_fu_19404_p3;
wire [2:0] tmp_402_fu_19412_p3;
wire [2:0] tmp1034_fu_19396_p3;
wire [2:0] tmp_2005_fu_19420_p2;
wire [4:0] p_Result_1296_0_3_4_fu_19127_p6;
wire [5:0] bt_sign_ph_V_3_fu_19267_p3;
wire [0:0] tmp_2007_fu_19450_p1;
wire [5:0] bt_sign_th_V_3_fu_19275_p3;
wire [0:0] tmp_2009_fu_19459_p1;
wire [0:0] tmp_2011_fu_19468_p3;
wire [0:0] tmp_2013_fu_19481_p3;
wire [0:0] tmp_2015_fu_19494_p3;
wire [0:0] tmp_2017_fu_19507_p3;
wire [0:0] tmp_2019_fu_19520_p3;
wire [0:0] tmp_2021_fu_19533_p3;
wire [0:0] tmp_2023_fu_19546_p3;
wire [0:0] tmp_2025_fu_19559_p3;
wire [0:0] tmp_2027_fu_19572_p3;
wire [0:0] tmp_413_fu_19580_p2;
wire [0:0] tmp_411_fu_19554_p2;
wire [0:0] tmp_409_fu_19528_p2;
wire [0:0] tmp_407_fu_19502_p2;
wire [0:0] tmp_405_fu_19476_p2;
wire [0:0] tmp_403_fu_19454_p2;
wire [0:0] tmp_2029_fu_19601_p3;
wire [0:0] tmp_414_fu_19609_p2;
wire [0:0] tmp_412_fu_19567_p2;
wire [0:0] tmp_410_fu_19541_p2;
wire [0:0] tmp_408_fu_19515_p2;
wire [0:0] tmp_406_fu_19489_p2;
wire [0:0] tmp_404_fu_19463_p2;
wire [0:0] tmp_2031_fu_19630_p3;
wire [1:0] tmp_415_fu_19638_p3;
wire [0:0] tmp_2032_fu_19652_p3;
wire [1:0] tmp_416_fu_19646_p2;
wire [4:0] bt_si_V_3_fu_19434_p3;
wire [0:0] tmp_2033_fu_19670_p1;
wire [2:0] tmp_418_fu_19679_p2;
wire [0:0] tmp_2035_fu_19693_p3;
wire [2:0] tmp_420_fu_19706_p2;
wire [0:0] tmp_2036_fu_19720_p3;
wire [0:0] tmp_2037_fu_19733_p3;
wire [0:0] tmp_421_fu_19728_p2;
wire [0:0] tmp_419_fu_19701_p2;
wire [0:0] tmp_417_fu_19674_p2;
wire [0:0] tmp_2006_fu_19442_p3;
wire [5:0] p_Result_1290_0_4_5_fu_19585_p7;
wire [5:0] p_Result_1293_0_4_5_fu_19614_p7;
wire [3:0] r_V_177_0_4_fu_19660_p4;
wire [3:0] bt_ci_V_3_fu_19336_p4;
wire [3:0] r_V_177_0_4_2_fu_19685_p3;
wire [3:0] bt_ci_V163_3_fu_19382_p3;
wire [3:0] r_V_177_0_4_3_fu_19712_p3;
wire [3:0] bt_ci_V164_3_fu_19426_p3;
wire [4:0] p_Result_1296_0_4_4_fu_19741_p6;
wire [5:0] bt_sign_ph_V_4_fu_19881_p3;
wire [0:0] tmp_2039_fu_19952_p1;
wire [5:0] bt_sign_th_V_4_fu_19889_p3;
wire [0:0] tmp_2041_fu_19961_p1;
wire [0:0] tmp_2043_fu_19970_p3;
wire [0:0] tmp_2045_fu_19983_p3;
wire [0:0] tmp_2047_fu_19996_p3;
wire [0:0] tmp_2049_fu_20009_p3;
wire [0:0] tmp_2051_fu_20022_p3;
wire [0:0] tmp_2053_fu_20035_p3;
wire [0:0] tmp_2055_fu_20048_p3;
wire [0:0] tmp_2057_fu_20061_p3;
wire [0:0] tmp_2059_fu_20074_p3;
wire [0:0] tmp_432_fu_20082_p2;
wire [0:0] tmp_430_fu_20056_p2;
wire [0:0] tmp_428_fu_20030_p2;
wire [0:0] tmp_426_fu_20004_p2;
wire [0:0] tmp_424_fu_19978_p2;
wire [0:0] tmp_422_fu_19956_p2;
wire [0:0] tmp_2061_fu_20103_p3;
wire [0:0] tmp_433_fu_20111_p2;
wire [0:0] tmp_431_fu_20069_p2;
wire [0:0] tmp_429_fu_20043_p2;
wire [0:0] tmp_427_fu_20017_p2;
wire [0:0] tmp_425_fu_19991_p2;
wire [0:0] tmp_423_fu_19965_p2;
wire [3:0] bt_ci_V_4_fu_19912_p3;
wire [1:0] tmp_2063_fu_20132_p1;
wire [1:0] tmp_435_fu_20142_p4;
wire [1:0] tmp_434_fu_20136_p2;
wire [4:0] bt_si_V_4_fu_19936_p3;
wire [0:0] tmp_2064_fu_20160_p1;
wire [3:0] bt_ci_V163_4_fu_19920_p3;
wire [2:0] tmp_2066_fu_20169_p1;
wire [0:0] tmp_2067_fu_20179_p3;
wire [2:0] tmp_437_fu_20173_p2;
wire [0:0] tmp_2068_fu_20195_p3;
wire [0:0] tmp_2069_fu_20208_p3;
wire [0:0] tmp_2070_fu_20221_p3;
wire [0:0] tmp_439_fu_20216_p2;
wire [0:0] tmp_438_fu_20203_p2;
wire [0:0] tmp_436_fu_20164_p2;
wire [0:0] tmp_2038_fu_19944_p3;
wire [5:0] p_Result_1290_0_5_5_fu_20087_p7;
wire [5:0] p_Result_1293_0_5_5_fu_20116_p7;
wire [3:0] r_V_177_0_5_fu_20152_p3;
wire [3:0] r_V_177_0_5_2_fu_20187_p3;
wire [4:0] p_Result_1296_0_5_4_fu_20229_p6;
wire [5:0] bt_sign_ph_V_5_fu_20369_p3;
wire [0:0] tmp_2072_fu_20432_p1;
wire [5:0] bt_sign_th_V_5_fu_20377_p3;
wire [0:0] tmp_2074_fu_20441_p1;
wire [0:0] tmp_2076_fu_20450_p3;
wire [0:0] tmp_2078_fu_20463_p3;
wire [0:0] tmp_2080_fu_20476_p3;
wire [0:0] tmp_2082_fu_20489_p3;
wire [0:0] tmp_2084_fu_20502_p3;
wire [0:0] tmp_2086_fu_20515_p3;
wire [0:0] tmp_2088_fu_20528_p3;
wire [0:0] tmp_2090_fu_20541_p3;
wire [0:0] tmp_2092_fu_20554_p3;
wire [0:0] tmp_450_fu_20562_p2;
wire [0:0] tmp_448_fu_20536_p2;
wire [0:0] tmp_446_fu_20510_p2;
wire [0:0] tmp_444_fu_20484_p2;
wire [0:0] tmp_442_fu_20458_p2;
wire [0:0] tmp_440_fu_20436_p2;
wire [0:0] tmp_2094_fu_20583_p3;
wire [0:0] tmp_451_fu_20591_p2;
wire [0:0] tmp_449_fu_20549_p2;
wire [0:0] tmp_447_fu_20523_p2;
wire [0:0] tmp_445_fu_20497_p2;
wire [0:0] tmp_443_fu_20471_p2;
wire [0:0] tmp_441_fu_20445_p2;
wire [4:0] bt_si_V_5_fu_20416_p3;
wire [0:0] tmp_2096_fu_20612_p1;
wire [0:0] tmp_2098_fu_20621_p3;
wire [0:0] tmp_2099_fu_20634_p3;
wire [0:0] tmp_2100_fu_20647_p3;
wire [0:0] tmp_454_fu_20642_p2;
wire [0:0] tmp_453_fu_20629_p2;
wire [0:0] tmp_452_fu_20616_p2;
wire [0:0] tmp_2071_fu_20424_p3;
wire [5:0] p_Result_1290_0_6_5_fu_20567_p7;
wire [5:0] p_Result_1293_0_6_5_fu_20596_p7;
wire [4:0] p_Result_1296_0_6_4_fu_20655_p6;
wire [5:0] bt_sign_ph_V_6_fu_20795_p3;
wire [0:0] tmp_2102_fu_20850_p1;
wire [5:0] bt_sign_th_V_6_fu_20803_p3;
wire [0:0] tmp_2104_fu_20859_p1;
wire [0:0] tmp_2106_fu_20868_p3;
wire [0:0] tmp_2108_fu_20881_p3;
wire [0:0] tmp_2110_fu_20894_p3;
wire [0:0] tmp_2112_fu_20907_p3;
wire [0:0] tmp_2114_fu_20920_p3;
wire [0:0] tmp_2116_fu_20933_p3;
wire [0:0] tmp_2118_fu_20946_p3;
wire [0:0] tmp_2120_fu_20959_p3;
wire [0:0] tmp_2122_fu_20972_p3;
wire [0:0] tmp_465_fu_20980_p2;
wire [0:0] tmp_463_fu_20954_p2;
wire [0:0] tmp_461_fu_20928_p2;
wire [0:0] tmp_459_fu_20902_p2;
wire [0:0] tmp_457_fu_20876_p2;
wire [0:0] tmp_455_fu_20854_p2;
wire [0:0] tmp_2124_fu_21001_p3;
wire [0:0] tmp_466_fu_21009_p2;
wire [0:0] tmp_464_fu_20967_p2;
wire [0:0] tmp_462_fu_20941_p2;
wire [0:0] tmp_460_fu_20915_p2;
wire [0:0] tmp_458_fu_20889_p2;
wire [0:0] tmp_456_fu_20863_p2;
wire [4:0] bt_si_V_6_fu_20834_p3;
wire [0:0] tmp_2126_fu_21030_p1;
wire [0:0] tmp_2128_fu_21039_p3;
wire [0:0] tmp_2129_fu_21052_p3;
wire [0:0] tmp_2130_fu_21065_p3;
wire [0:0] tmp_469_fu_21060_p2;
wire [0:0] tmp_468_fu_21047_p2;
wire [0:0] tmp_467_fu_21034_p2;
wire [0:0] tmp_2101_fu_20842_p3;
wire [5:0] p_Result_1290_0_7_5_fu_20985_p7;
wire [5:0] p_Result_1293_0_7_5_fu_21014_p7;
wire [2:0] tmp_2131_fu_21236_p3;
wire [2:0] r_V_177_0_6_fu_20826_p3;
wire [2:0] tmp_470_fu_21244_p2;
wire [3:0] tmp1065_fu_21250_p3;
wire [3:0] bt_ci_V_5_fu_20400_p3;
wire [0:0] tmp_2132_fu_21272_p2;
wire [3:0] bt_ci_V163_5_fu_20408_p3;
wire [2:0] tmp_2133_fu_21286_p1;
wire [2:0] tmp1066_fu_21278_p3;
wire [0:0] tmp_2135_fu_21296_p3;
wire [2:0] tmp_2134_fu_21290_p2;
wire [0:0] tmp_2136_fu_21312_p2;
wire [3:0] bt_ci_V164_4_fu_19928_p3;
wire [2:0] tmp_2137_fu_21326_p1;
wire [2:0] r_V_177_0_7_2_fu_21264_p3;
wire [2:0] tmp_2138_fu_21330_p2;
wire [2:0] tmp1067_fu_21318_p3;
wire [0:0] tmp_2139_fu_21336_p3;
wire [2:0] tmp_2140_fu_21344_p2;
wire [4:0] p_Result_1296_0_7_4_fu_21073_p6;
wire [5:0] bt_sign_ph_V_7_fu_21213_p3;
wire [0:0] tmp_2142_fu_21374_p1;
wire [5:0] bt_sign_th_V_7_fu_21221_p3;
wire [0:0] tmp_2144_fu_21383_p1;
wire [0:0] tmp_2146_fu_21392_p3;
wire [0:0] tmp_2148_fu_21405_p3;
wire [0:0] tmp_2150_fu_21418_p3;
wire [0:0] tmp_2152_fu_21431_p3;
wire [0:0] tmp_2154_fu_21444_p3;
wire [0:0] tmp_2156_fu_21457_p3;
wire [0:0] tmp_2158_fu_21470_p3;
wire [0:0] tmp_2160_fu_21483_p3;
wire [0:0] tmp_2162_fu_21496_p3;
wire [0:0] tmp_481_fu_21504_p2;
wire [0:0] tmp_479_fu_21478_p2;
wire [0:0] tmp_477_fu_21452_p2;
wire [0:0] tmp_475_fu_21426_p2;
wire [0:0] tmp_473_fu_21400_p2;
wire [0:0] tmp_471_fu_21378_p2;
wire [0:0] tmp_2164_fu_21525_p3;
wire [0:0] tmp_482_fu_21533_p2;
wire [0:0] tmp_480_fu_21491_p2;
wire [0:0] tmp_478_fu_21465_p2;
wire [0:0] tmp_476_fu_21439_p2;
wire [0:0] tmp_474_fu_21413_p2;
wire [0:0] tmp_472_fu_21387_p2;
wire [3:0] bt_ci_V_7_fu_21258_p2;
wire [1:0] tmp_2166_fu_21554_p1;
wire [1:0] tmp_484_fu_21564_p4;
wire [1:0] tmp_483_fu_21558_p2;
wire [4:0] bt_si_V_7_fu_21358_p3;
wire [0:0] tmp_2167_fu_21582_p1;
wire [2:0] tmp_486_fu_21591_p2;
wire [0:0] tmp_2169_fu_21605_p3;
wire [2:0] tmp_488_fu_21618_p2;
wire [0:0] tmp_2170_fu_21632_p3;
wire [0:0] tmp_2171_fu_21645_p3;
wire [0:0] tmp_489_fu_21640_p2;
wire [0:0] tmp_487_fu_21613_p2;
wire [0:0] tmp_485_fu_21586_p2;
wire [0:0] tmp_2141_fu_21366_p3;
wire [5:0] p_Result_1290_0_8_5_fu_21509_p7;
wire [5:0] p_Result_1293_0_8_5_fu_21538_p7;
wire [3:0] r_V_177_0_8_fu_21574_p3;
wire [3:0] r_V_177_0_8_2_fu_21597_p3;
wire [3:0] bt_ci_V163_7_fu_21304_p3;
wire [3:0] r_V_177_0_8_3_fu_21624_p3;
wire [3:0] bt_ci_V164_7_fu_21350_p3;
wire [4:0] p_Result_1296_0_8_4_fu_21653_p6;
wire [5:0] bt_sign_ph_V_8_fu_21793_p3;
wire [0:0] tmp_2173_fu_21856_p1;
wire [5:0] bt_sign_th_V_8_fu_21801_p3;
wire [0:0] tmp_2175_fu_21865_p1;
wire [0:0] tmp_2177_fu_21874_p3;
wire [0:0] tmp_2179_fu_21887_p3;
wire [0:0] tmp_2181_fu_21900_p3;
wire [0:0] tmp_2183_fu_21913_p3;
wire [0:0] tmp_2185_fu_21926_p3;
wire [0:0] tmp_2187_fu_21939_p3;
wire [0:0] tmp_2189_fu_21952_p3;
wire [0:0] tmp_2191_fu_21965_p3;
wire [0:0] tmp_2193_fu_21978_p3;
wire [0:0] tmp_500_fu_21986_p2;
wire [0:0] tmp_498_fu_21960_p2;
wire [0:0] tmp_496_fu_21934_p2;
wire [0:0] tmp_494_fu_21908_p2;
wire [0:0] tmp_492_fu_21882_p2;
wire [0:0] tmp_490_fu_21860_p2;
wire [0:0] tmp_2195_fu_22007_p3;
wire [0:0] tmp_501_fu_22015_p2;
wire [0:0] tmp_499_fu_21973_p2;
wire [0:0] tmp_497_fu_21947_p2;
wire [0:0] tmp_495_fu_21921_p2;
wire [0:0] tmp_493_fu_21895_p2;
wire [0:0] tmp_491_fu_21869_p2;
wire [3:0] bt_ci_V_8_fu_21816_p3;
wire [1:0] tmp_2197_fu_22036_p1;
wire [1:0] tmp_503_fu_22046_p4;
wire [1:0] tmp_502_fu_22040_p2;
wire [4:0] bt_si_V_8_fu_21840_p3;
wire [0:0] tmp_2198_fu_22064_p1;
wire [3:0] bt_ci_V163_8_fu_21824_p3;
wire [2:0] tmp_2200_fu_22073_p1;
wire [0:0] tmp_2201_fu_22083_p3;
wire [2:0] tmp_505_fu_22077_p2;
wire [0:0] tmp_2202_fu_22099_p3;
wire [0:0] tmp_2203_fu_22112_p3;
wire [0:0] tmp_2204_fu_22125_p3;
wire [0:0] tmp_507_fu_22120_p2;
wire [0:0] tmp_506_fu_22107_p2;
wire [0:0] tmp_504_fu_22068_p2;
wire [0:0] tmp_2172_fu_21848_p3;
wire [5:0] p_Result_1290_0_9_5_fu_21991_p7;
wire [5:0] p_Result_1293_0_9_5_fu_22020_p7;
wire [3:0] r_V_177_0_9_fu_22056_p3;
wire [3:0] r_V_177_0_9_2_fu_22091_p3;
wire [4:0] p_Result_1296_0_9_4_fu_22133_p6;
wire [5:0] bt_sign_ph_V_9_fu_22273_p3;
wire [0:0] tmp_2206_fu_22344_p1;
wire [5:0] bt_sign_th_V_9_fu_22281_p3;
wire [0:0] tmp_2208_fu_22353_p1;
wire [0:0] tmp_2210_fu_22362_p3;
wire [0:0] tmp_2212_fu_22375_p3;
wire [0:0] tmp_2214_fu_22388_p3;
wire [0:0] tmp_2216_fu_22401_p3;
wire [0:0] tmp_2218_fu_22414_p3;
wire [0:0] tmp_2220_fu_22427_p3;
wire [0:0] tmp_2222_fu_22440_p3;
wire [0:0] tmp_2224_fu_22453_p3;
wire [0:0] tmp_2226_fu_22466_p3;
wire [0:0] tmp_518_fu_22474_p2;
wire [0:0] tmp_516_fu_22448_p2;
wire [0:0] tmp_514_fu_22422_p2;
wire [0:0] tmp_512_fu_22396_p2;
wire [0:0] tmp_510_fu_22370_p2;
wire [0:0] tmp_508_fu_22348_p2;
wire [0:0] tmp_2228_fu_22495_p3;
wire [0:0] tmp_519_fu_22503_p2;
wire [0:0] tmp_517_fu_22461_p2;
wire [0:0] tmp_515_fu_22435_p2;
wire [0:0] tmp_513_fu_22409_p2;
wire [0:0] tmp_511_fu_22383_p2;
wire [0:0] tmp_509_fu_22357_p2;
wire [4:0] bt_si_V_9_fu_22328_p3;
wire [0:0] tmp_2230_fu_22524_p1;
wire [0:0] tmp_2232_fu_22533_p3;
wire [0:0] tmp_2233_fu_22546_p3;
wire [0:0] tmp_2234_fu_22559_p3;
wire [0:0] tmp_522_fu_22554_p2;
wire [0:0] tmp_521_fu_22541_p2;
wire [0:0] tmp_520_fu_22528_p2;
wire [0:0] tmp_2205_fu_22336_p3;
wire [5:0] p_Result_1290_0_10_5_fu_22479_p7;
wire [5:0] p_Result_1293_0_10_5_fu_22508_p7;
wire [4:0] p_Result_1296_0_10_4_fu_22567_p6;
wire [5:0] bt_sign_ph_V_s_fu_22707_p3;
wire [0:0] tmp_2236_fu_22754_p1;
wire [5:0] bt_sign_th_V_s_fu_22715_p3;
wire [0:0] tmp_2238_fu_22763_p1;
wire [0:0] tmp_2240_fu_22772_p3;
wire [0:0] tmp_2242_fu_22785_p3;
wire [0:0] tmp_2244_fu_22798_p3;
wire [0:0] tmp_2246_fu_22811_p3;
wire [0:0] tmp_2248_fu_22824_p3;
wire [0:0] tmp_2250_fu_22837_p3;
wire [0:0] tmp_2252_fu_22850_p3;
wire [0:0] tmp_2254_fu_22863_p3;
wire [0:0] tmp_2256_fu_22876_p3;
wire [0:0] tmp_533_fu_22884_p2;
wire [0:0] tmp_531_fu_22858_p2;
wire [0:0] tmp_529_fu_22832_p2;
wire [0:0] tmp_527_fu_22806_p2;
wire [0:0] tmp_525_fu_22780_p2;
wire [0:0] tmp_523_fu_22758_p2;
wire [0:0] tmp_2258_fu_22905_p3;
wire [0:0] tmp_534_fu_22913_p2;
wire [0:0] tmp_532_fu_22871_p2;
wire [0:0] tmp_530_fu_22845_p2;
wire [0:0] tmp_528_fu_22819_p2;
wire [0:0] tmp_526_fu_22793_p2;
wire [0:0] tmp_524_fu_22767_p2;
wire [4:0] bt_si_V_s_fu_22738_p3;
wire [0:0] tmp_2260_fu_22934_p1;
wire [0:0] tmp_2262_fu_22943_p3;
wire [0:0] tmp_2263_fu_22956_p3;
wire [0:0] tmp_2264_fu_22969_p3;
wire [0:0] tmp_537_fu_22964_p2;
wire [0:0] tmp_536_fu_22951_p2;
wire [0:0] tmp_535_fu_22938_p2;
wire [0:0] tmp_2235_fu_22746_p3;
wire [11:0] r_V_170_0_1_fu_18315_p3;
wire [11:0] r_V_170_0_2_fu_18731_p3;
wire [11:0] tmp1069_fu_22998_p2;
wire [11:0] bt_phi_V_fu_17915_p3;
wire [11:0] r_V_170_0_4_fu_19755_p3;
wire [11:0] r_V_170_0_5_fu_20243_p3;
wire [11:0] tmp1071_fu_23010_p2;
wire [11:0] r_V_170_0_3_fu_19141_p3;
wire [11:0] tmp1072_fu_23016_p2;
wire [11:0] tmp1070_fu_23004_p2;
wire [11:0] r_V_170_0_7_fu_21087_p3;
wire [11:0] r_V_170_0_8_fu_21667_p3;
wire [11:0] tmp1074_fu_23028_p2;
wire [11:0] r_V_170_0_6_fu_20669_p3;
wire [11:0] r_V_170_0_s_fu_22581_p3;
wire [11:0] r_V_170_0_10_fu_22991_p3;
wire [11:0] tmp1076_fu_23040_p2;
wire [11:0] r_V_170_0_9_fu_22147_p3;
wire [11:0] tmp1077_fu_23046_p2;
wire [11:0] tmp1075_fu_23034_p2;
wire [11:0] tmp1078_fu_23052_p2;
wire [11:0] tmp1073_fu_23022_p2;
wire [6:0] r_V_171_0_1_fu_18322_p3;
wire [6:0] r_V_171_0_2_fu_18738_p3;
wire [6:0] tmp1079_fu_23071_p2;
wire [6:0] bt_theta_V_fu_17922_p3;
wire [6:0] r_V_171_0_4_fu_19762_p3;
wire [6:0] r_V_171_0_5_fu_20250_p3;
wire [6:0] tmp1081_fu_23083_p2;
wire [6:0] r_V_171_0_3_fu_19148_p3;
wire [6:0] tmp1082_fu_23089_p2;
wire [6:0] tmp1080_fu_23077_p2;
wire [6:0] r_V_171_0_7_fu_21094_p3;
wire [6:0] r_V_171_0_8_fu_21674_p3;
wire [6:0] tmp1084_fu_23101_p2;
wire [6:0] r_V_171_0_6_fu_20676_p3;
wire [6:0] r_V_171_0_s_fu_22588_p3;
wire [6:0] r_V_171_0_10_fu_23064_p3;
wire [6:0] tmp1086_fu_23113_p2;
wire [6:0] r_V_171_0_9_fu_22154_p3;
wire [6:0] tmp1087_fu_23119_p2;
wire [6:0] tmp1085_fu_23107_p2;
wire [6:0] tmp1088_fu_23125_p2;
wire [6:0] tmp1083_fu_23095_p2;
wire [3:0] r_V_172_0_1_fu_18329_p3;
wire [3:0] r_V_172_0_2_fu_18745_p3;
wire [3:0] tmp1089_fu_23144_p2;
wire [3:0] bt_cpattern_V_fu_17929_p3;
wire [3:0] r_V_172_0_4_fu_19769_p3;
wire [3:0] r_V_172_0_5_fu_20257_p3;
wire [3:0] tmp1091_fu_23156_p2;
wire [3:0] r_V_172_0_3_fu_19155_p3;
wire [3:0] tmp1092_fu_23162_p2;
wire [3:0] tmp1090_fu_23150_p2;
wire [3:0] r_V_172_0_7_fu_21101_p3;
wire [3:0] r_V_172_0_8_fu_21681_p3;
wire [3:0] tmp1094_fu_23174_p2;
wire [3:0] r_V_172_0_6_fu_20683_p3;
wire [3:0] r_V_172_0_s_fu_22595_p3;
wire [3:0] r_V_172_0_10_fu_23137_p3;
wire [3:0] tmp1096_fu_23186_p2;
wire [3:0] r_V_172_0_9_fu_22161_p3;
wire [3:0] tmp1097_fu_23192_p2;
wire [3:0] tmp1095_fu_23180_p2;
wire [3:0] tmp1098_fu_23198_p2;
wire [3:0] tmp1093_fu_23168_p2;
wire [3:0] r_V_172_0_1_1_fu_18336_p3;
wire [3:0] r_V_172_0_2_1_fu_18752_p3;
wire [3:0] tmp1099_fu_23217_p2;
wire [3:0] bt_cpattern_V1_fu_17936_p3;
wire [3:0] r_V_172_0_4_1_fu_19776_p3;
wire [3:0] r_V_172_0_5_1_fu_20264_p3;
wire [3:0] tmp1101_fu_23229_p2;
wire [3:0] r_V_172_0_3_1_fu_19162_p3;
wire [3:0] tmp1102_fu_23235_p2;
wire [3:0] tmp1100_fu_23223_p2;
wire [3:0] r_V_172_0_7_1_fu_21108_p3;
wire [3:0] r_V_172_0_8_1_fu_21688_p3;
wire [3:0] tmp1104_fu_23247_p2;
wire [3:0] r_V_172_0_6_1_fu_20690_p3;
wire [3:0] r_V_172_0_10_1_fu_22602_p3;
wire [3:0] r_V_172_0_11_1_fu_23210_p3;
wire [3:0] tmp1106_fu_23259_p2;
wire [3:0] r_V_172_0_9_1_fu_22168_p3;
wire [3:0] tmp1107_fu_23265_p2;
wire [3:0] tmp1105_fu_23253_p2;
wire [3:0] tmp1108_fu_23271_p2;
wire [3:0] tmp1103_fu_23241_p2;
wire [3:0] r_V_172_0_1_2_fu_18343_p3;
wire [3:0] r_V_172_0_2_2_fu_18759_p3;
wire [3:0] tmp1109_fu_23290_p2;
wire [3:0] bt_cpattern_V2_fu_17943_p3;
wire [3:0] r_V_172_0_4_2_fu_19783_p3;
wire [3:0] r_V_172_0_5_2_fu_20271_p3;
wire [3:0] tmp1111_fu_23302_p2;
wire [3:0] r_V_172_0_3_2_fu_19169_p3;
wire [3:0] tmp1112_fu_23308_p2;
wire [3:0] tmp1110_fu_23296_p2;
wire [3:0] r_V_172_0_7_2_fu_21115_p3;
wire [3:0] r_V_172_0_8_2_fu_21695_p3;
wire [3:0] tmp1114_fu_23320_p2;
wire [3:0] r_V_172_0_6_2_fu_20697_p3;
wire [3:0] r_V_172_0_10_2_fu_22609_p3;
wire [3:0] r_V_172_0_11_2_fu_23283_p3;
wire [3:0] tmp1116_fu_23332_p2;
wire [3:0] r_V_172_0_9_2_fu_22175_p3;
wire [3:0] tmp1117_fu_23338_p2;
wire [3:0] tmp1115_fu_23326_p2;
wire [3:0] tmp1118_fu_23344_p2;
wire [3:0] tmp1113_fu_23314_p2;
wire [3:0] r_V_172_0_1_3_fu_18350_p3;
wire [3:0] r_V_172_0_2_3_fu_18766_p3;
wire [3:0] tmp1119_fu_23363_p2;
wire [3:0] bt_cpattern_V3_fu_17950_p3;
wire [3:0] r_V_172_0_4_3_fu_19790_p3;
wire [3:0] r_V_172_0_5_3_fu_20278_p3;
wire [3:0] tmp1121_fu_23375_p2;
wire [3:0] r_V_172_0_3_3_fu_19176_p3;
wire [3:0] tmp1122_fu_23381_p2;
wire [3:0] tmp1120_fu_23369_p2;
wire [3:0] r_V_172_0_7_3_fu_21122_p3;
wire [3:0] r_V_172_0_8_3_fu_21702_p3;
wire [3:0] tmp1124_fu_23393_p2;
wire [3:0] r_V_172_0_6_3_fu_20704_p3;
wire [3:0] r_V_172_0_10_3_fu_22616_p3;
wire [3:0] r_V_172_0_11_3_fu_23356_p3;
wire [3:0] tmp1126_fu_23405_p2;
wire [3:0] r_V_172_0_9_3_fu_22182_p3;
wire [3:0] tmp1127_fu_23411_p2;
wire [3:0] tmp1125_fu_23399_p2;
wire [3:0] tmp1128_fu_23417_p2;
wire [3:0] tmp1123_fu_23387_p2;
wire [11:0] r_V_173_0_1_fu_18357_p3;
wire [11:0] r_V_173_0_2_fu_18773_p3;
wire [11:0] tmp1129_fu_23436_p2;
wire [11:0] bt_delta_ph_V_fu_17957_p3;
wire [11:0] r_V_173_0_4_fu_19797_p3;
wire [11:0] r_V_173_0_5_fu_20285_p3;
wire [11:0] tmp1131_fu_23448_p2;
wire [11:0] r_V_173_0_3_fu_19183_p3;
wire [11:0] tmp1132_fu_23454_p2;
wire [11:0] tmp1130_fu_23442_p2;
wire [11:0] r_V_173_0_7_fu_21129_p3;
wire [11:0] r_V_173_0_8_fu_21709_p3;
wire [11:0] tmp1134_fu_23466_p2;
wire [11:0] r_V_173_0_6_fu_20711_p3;
wire [11:0] r_V_173_0_s_fu_22623_p3;
wire [11:0] r_V_173_0_10_fu_23429_p3;
wire [11:0] tmp1136_fu_23478_p2;
wire [11:0] r_V_173_0_9_fu_22189_p3;
wire [11:0] tmp1137_fu_23484_p2;
wire [11:0] tmp1135_fu_23472_p2;
wire [11:0] tmp1138_fu_23490_p2;
wire [11:0] tmp1133_fu_23460_p2;
wire [11:0] r_V_173_0_1_1_fu_18364_p3;
wire [11:0] r_V_173_0_2_1_fu_18780_p3;
wire [11:0] tmp1139_fu_23509_p2;
wire [11:0] bt_delta_ph_V1_fu_17964_p3;
wire [11:0] r_V_173_0_4_1_fu_19804_p3;
wire [11:0] r_V_173_0_5_1_fu_20292_p3;
wire [11:0] tmp1141_fu_23521_p2;
wire [11:0] r_V_173_0_3_1_fu_19190_p3;
wire [11:0] tmp1142_fu_23527_p2;
wire [11:0] tmp1140_fu_23515_p2;
wire [11:0] r_V_173_0_7_1_fu_21136_p3;
wire [11:0] r_V_173_0_8_1_fu_21716_p3;
wire [11:0] tmp1144_fu_23539_p2;
wire [11:0] r_V_173_0_6_1_fu_20718_p3;
wire [11:0] r_V_173_0_10_1_fu_22630_p3;
wire [11:0] r_V_173_0_11_1_fu_23502_p3;
wire [11:0] tmp1146_fu_23551_p2;
wire [11:0] r_V_173_0_9_1_fu_22196_p3;
wire [11:0] tmp1147_fu_23557_p2;
wire [11:0] tmp1145_fu_23545_p2;
wire [11:0] tmp1148_fu_23563_p2;
wire [11:0] tmp1143_fu_23533_p2;
wire [11:0] r_V_173_0_1_2_fu_18371_p3;
wire [11:0] r_V_173_0_2_2_fu_18787_p3;
wire [11:0] tmp1149_fu_23582_p2;
wire [11:0] bt_delta_ph_V2_fu_17971_p3;
wire [11:0] r_V_173_0_4_2_fu_19811_p3;
wire [11:0] r_V_173_0_5_2_fu_20299_p3;
wire [11:0] tmp1151_fu_23594_p2;
wire [11:0] r_V_173_0_3_2_fu_19197_p3;
wire [11:0] tmp1152_fu_23600_p2;
wire [11:0] tmp1150_fu_23588_p2;
wire [11:0] r_V_173_0_7_2_fu_21143_p3;
wire [11:0] r_V_173_0_8_2_fu_21723_p3;
wire [11:0] tmp1154_fu_23612_p2;
wire [11:0] r_V_173_0_6_2_fu_20725_p3;
wire [11:0] r_V_173_0_10_2_fu_22637_p3;
wire [11:0] r_V_173_0_11_2_fu_23575_p3;
wire [11:0] tmp1156_fu_23624_p2;
wire [11:0] r_V_173_0_9_2_fu_22203_p3;
wire [11:0] tmp1157_fu_23630_p2;
wire [11:0] tmp1155_fu_23618_p2;
wire [11:0] tmp1158_fu_23636_p2;
wire [11:0] tmp1153_fu_23606_p2;
wire [11:0] r_V_173_0_1_3_fu_18378_p3;
wire [11:0] r_V_173_0_2_3_fu_18794_p3;
wire [11:0] tmp1159_fu_23655_p2;
wire [11:0] bt_delta_ph_V3_fu_17978_p3;
wire [11:0] r_V_173_0_4_3_fu_19818_p3;
wire [11:0] r_V_173_0_5_3_fu_20306_p3;
wire [11:0] tmp1161_fu_23667_p2;
wire [11:0] r_V_173_0_3_3_fu_19204_p3;
wire [11:0] tmp1162_fu_23673_p2;
wire [11:0] tmp1160_fu_23661_p2;
wire [11:0] r_V_173_0_7_3_fu_21150_p3;
wire [11:0] r_V_173_0_8_3_fu_21730_p3;
wire [11:0] tmp1164_fu_23685_p2;
wire [11:0] r_V_173_0_6_3_fu_20732_p3;
wire [11:0] r_V_173_0_10_3_fu_22644_p3;
wire [11:0] r_V_173_0_11_3_fu_23648_p3;
wire [11:0] tmp1166_fu_23697_p2;
wire [11:0] r_V_173_0_9_3_fu_22210_p3;
wire [11:0] tmp1167_fu_23703_p2;
wire [11:0] tmp1165_fu_23691_p2;
wire [11:0] tmp1168_fu_23709_p2;
wire [11:0] tmp1163_fu_23679_p2;
wire [11:0] r_V_173_0_1_4_fu_18385_p3;
wire [11:0] r_V_173_0_2_4_fu_18801_p3;
wire [11:0] tmp1169_fu_23728_p2;
wire [11:0] bt_delta_ph_V4_fu_17985_p3;
wire [11:0] r_V_173_0_4_4_fu_19825_p3;
wire [11:0] r_V_173_0_5_4_fu_20313_p3;
wire [11:0] tmp1171_fu_23740_p2;
wire [11:0] r_V_173_0_3_4_fu_19211_p3;
wire [11:0] tmp1172_fu_23746_p2;
wire [11:0] tmp1170_fu_23734_p2;
wire [11:0] r_V_173_0_7_4_fu_21157_p3;
wire [11:0] r_V_173_0_8_4_fu_21737_p3;
wire [11:0] tmp1174_fu_23758_p2;
wire [11:0] r_V_173_0_6_4_fu_20739_p3;
wire [11:0] r_V_173_0_10_4_fu_22651_p3;
wire [11:0] r_V_173_0_11_4_fu_23721_p3;
wire [11:0] tmp1176_fu_23770_p2;
wire [11:0] r_V_173_0_9_4_fu_22217_p3;
wire [11:0] tmp1177_fu_23776_p2;
wire [11:0] tmp1175_fu_23764_p2;
wire [11:0] tmp1178_fu_23782_p2;
wire [11:0] tmp1173_fu_23752_p2;
wire [11:0] r_V_173_0_1_5_fu_18392_p3;
wire [11:0] r_V_173_0_2_5_fu_18808_p3;
wire [11:0] tmp1179_fu_23801_p2;
wire [11:0] bt_delta_ph_V5_fu_17992_p3;
wire [11:0] r_V_173_0_4_5_fu_19832_p3;
wire [11:0] r_V_173_0_5_5_fu_20320_p3;
wire [11:0] tmp1181_fu_23813_p2;
wire [11:0] r_V_173_0_3_5_fu_19218_p3;
wire [11:0] tmp1182_fu_23819_p2;
wire [11:0] tmp1180_fu_23807_p2;
wire [11:0] r_V_173_0_7_5_fu_21164_p3;
wire [11:0] r_V_173_0_8_5_fu_21744_p3;
wire [11:0] tmp1184_fu_23831_p2;
wire [11:0] r_V_173_0_6_5_fu_20746_p3;
wire [11:0] r_V_173_0_10_5_fu_22658_p3;
wire [11:0] r_V_173_0_11_5_fu_23794_p3;
wire [11:0] tmp1186_fu_23843_p2;
wire [11:0] r_V_173_0_9_5_fu_22224_p3;
wire [11:0] tmp1187_fu_23849_p2;
wire [11:0] tmp1185_fu_23837_p2;
wire [11:0] tmp1188_fu_23855_p2;
wire [11:0] tmp1183_fu_23825_p2;
wire [6:0] r_V_174_0_1_fu_18399_p3;
wire [6:0] r_V_174_0_2_fu_18815_p3;
wire [6:0] tmp1189_fu_23874_p2;
wire [6:0] bt_delta_th_V_fu_17999_p3;
wire [6:0] r_V_174_0_4_fu_19839_p3;
wire [6:0] r_V_174_0_5_fu_20327_p3;
wire [6:0] tmp1191_fu_23886_p2;
wire [6:0] r_V_174_0_3_fu_19225_p3;
wire [6:0] tmp1192_fu_23892_p2;
wire [6:0] tmp1190_fu_23880_p2;
wire [6:0] r_V_174_0_7_fu_21171_p3;
wire [6:0] r_V_174_0_8_fu_21751_p3;
wire [6:0] tmp1194_fu_23904_p2;
wire [6:0] r_V_174_0_6_fu_20753_p3;
wire [6:0] r_V_174_0_s_fu_22665_p3;
wire [6:0] r_V_174_0_10_fu_23867_p3;
wire [6:0] tmp1196_fu_23916_p2;
wire [6:0] r_V_174_0_9_fu_22231_p3;
wire [6:0] tmp1197_fu_23922_p2;
wire [6:0] tmp1195_fu_23910_p2;
wire [6:0] tmp1198_fu_23928_p2;
wire [6:0] tmp1193_fu_23898_p2;
wire [6:0] r_V_174_0_1_1_fu_18406_p3;
wire [6:0] r_V_174_0_2_1_fu_18822_p3;
wire [6:0] tmp1199_fu_23947_p2;
wire [6:0] bt_delta_th_V1_fu_18006_p3;
wire [6:0] r_V_174_0_4_1_fu_19846_p3;
wire [6:0] r_V_174_0_5_1_fu_20334_p3;
wire [6:0] tmp1201_fu_23959_p2;
wire [6:0] r_V_174_0_3_1_fu_19232_p3;
wire [6:0] tmp1202_fu_23965_p2;
wire [6:0] tmp1200_fu_23953_p2;
wire [6:0] r_V_174_0_7_1_fu_21178_p3;
wire [6:0] r_V_174_0_8_1_fu_21758_p3;
wire [6:0] tmp1204_fu_23977_p2;
wire [6:0] r_V_174_0_6_1_fu_20760_p3;
wire [6:0] r_V_174_0_10_1_fu_22672_p3;
wire [6:0] r_V_174_0_11_1_fu_23940_p3;
wire [6:0] tmp1206_fu_23989_p2;
wire [6:0] r_V_174_0_9_1_fu_22238_p3;
wire [6:0] tmp1207_fu_23995_p2;
wire [6:0] tmp1205_fu_23983_p2;
wire [6:0] tmp1208_fu_24001_p2;
wire [6:0] tmp1203_fu_23971_p2;
wire [6:0] r_V_174_0_1_2_fu_18413_p3;
wire [6:0] r_V_174_0_2_2_fu_18829_p3;
wire [6:0] tmp1209_fu_24020_p2;
wire [6:0] bt_delta_th_V2_fu_18013_p3;
wire [6:0] r_V_174_0_4_2_fu_19853_p3;
wire [6:0] r_V_174_0_5_2_fu_20341_p3;
wire [6:0] tmp1211_fu_24032_p2;
wire [6:0] r_V_174_0_3_2_fu_19239_p3;
wire [6:0] tmp1212_fu_24038_p2;
wire [6:0] tmp1210_fu_24026_p2;
wire [6:0] r_V_174_0_7_2_fu_21185_p3;
wire [6:0] r_V_174_0_8_2_fu_21765_p3;
wire [6:0] tmp1214_fu_24050_p2;
wire [6:0] r_V_174_0_6_2_fu_20767_p3;
wire [6:0] r_V_174_0_10_2_fu_22679_p3;
wire [6:0] r_V_174_0_11_2_fu_24013_p3;
wire [6:0] tmp1216_fu_24062_p2;
wire [6:0] r_V_174_0_9_2_fu_22245_p3;
wire [6:0] tmp1217_fu_24068_p2;
wire [6:0] tmp1215_fu_24056_p2;
wire [6:0] tmp1218_fu_24074_p2;
wire [6:0] tmp1213_fu_24044_p2;
wire [6:0] r_V_174_0_1_3_fu_18420_p3;
wire [6:0] r_V_174_0_2_3_fu_18836_p3;
wire [6:0] tmp1219_fu_24093_p2;
wire [6:0] bt_delta_th_V3_fu_18020_p3;
wire [6:0] r_V_174_0_4_3_fu_19860_p3;
wire [6:0] r_V_174_0_5_3_fu_20348_p3;
wire [6:0] tmp1221_fu_24105_p2;
wire [6:0] r_V_174_0_3_3_fu_19246_p3;
wire [6:0] tmp1222_fu_24111_p2;
wire [6:0] tmp1220_fu_24099_p2;
wire [6:0] r_V_174_0_7_3_fu_21192_p3;
wire [6:0] r_V_174_0_8_3_fu_21772_p3;
wire [6:0] tmp1224_fu_24123_p2;
wire [6:0] r_V_174_0_6_3_fu_20774_p3;
wire [6:0] r_V_174_0_10_3_fu_22686_p3;
wire [6:0] r_V_174_0_11_3_fu_24086_p3;
wire [6:0] tmp1226_fu_24135_p2;
wire [6:0] r_V_174_0_9_3_fu_22252_p3;
wire [6:0] tmp1227_fu_24141_p2;
wire [6:0] tmp1225_fu_24129_p2;
wire [6:0] tmp1228_fu_24147_p2;
wire [6:0] tmp1223_fu_24117_p2;
wire [6:0] r_V_174_0_1_4_fu_18427_p3;
wire [6:0] r_V_174_0_2_4_fu_18843_p3;
wire [6:0] tmp1229_fu_24166_p2;
wire [6:0] bt_delta_th_V4_fu_18027_p3;
wire [6:0] r_V_174_0_4_4_fu_19867_p3;
wire [6:0] r_V_174_0_5_4_fu_20355_p3;
wire [6:0] tmp1231_fu_24178_p2;
wire [6:0] r_V_174_0_3_4_fu_19253_p3;
wire [6:0] tmp1232_fu_24184_p2;
wire [6:0] tmp1230_fu_24172_p2;
wire [6:0] r_V_174_0_7_4_fu_21199_p3;
wire [6:0] r_V_174_0_8_4_fu_21779_p3;
wire [6:0] tmp1234_fu_24196_p2;
wire [6:0] r_V_174_0_6_4_fu_20781_p3;
wire [6:0] r_V_174_0_10_4_fu_22693_p3;
wire [6:0] r_V_174_0_11_4_fu_24159_p3;
wire [6:0] tmp1236_fu_24208_p2;
wire [6:0] r_V_174_0_9_4_fu_22259_p3;
wire [6:0] tmp1237_fu_24214_p2;
wire [6:0] tmp1235_fu_24202_p2;
wire [6:0] tmp1238_fu_24220_p2;
wire [6:0] tmp1233_fu_24190_p2;
wire [6:0] r_V_174_0_1_5_fu_18434_p3;
wire [6:0] r_V_174_0_2_5_fu_18850_p3;
wire [6:0] tmp1239_fu_24239_p2;
wire [6:0] bt_delta_th_V5_fu_18034_p3;
wire [6:0] r_V_174_0_4_5_fu_19874_p3;
wire [6:0] r_V_174_0_5_5_fu_20362_p3;
wire [6:0] tmp1241_fu_24251_p2;
wire [6:0] r_V_174_0_3_5_fu_19260_p3;
wire [6:0] tmp1242_fu_24257_p2;
wire [6:0] tmp1240_fu_24245_p2;
wire [6:0] r_V_174_0_7_5_fu_21206_p3;
wire [6:0] r_V_174_0_8_5_fu_21786_p3;
wire [6:0] tmp1244_fu_24269_p2;
wire [6:0] r_V_174_0_6_5_fu_20788_p3;
wire [6:0] r_V_174_0_10_5_fu_22700_p3;
wire [6:0] r_V_174_0_11_5_fu_24232_p3;
wire [6:0] tmp1246_fu_24281_p2;
wire [6:0] r_V_174_0_9_5_fu_22266_p3;
wire [6:0] tmp1247_fu_24287_p2;
wire [6:0] tmp1245_fu_24275_p2;
wire [6:0] tmp1248_fu_24293_p2;
wire [6:0] tmp1243_fu_24263_p2;
wire [5:0] p_Result_1290_0_11_5_fu_22889_p7;
wire [5:0] p_Result_1293_0_11_5_fu_22918_p7;
wire [6:0] r_V_169_0_1_fu_18457_p3;
wire [6:0] r_V_169_0_2_fu_18873_p3;
wire [6:0] tmp1249_fu_24328_p2;
wire [6:0] bt_rank_V_fu_18055_p3;
wire [6:0] r_V_169_0_4_fu_19897_p3;
wire [6:0] r_V_169_0_5_fu_20385_p3;
wire [6:0] tmp1251_fu_24340_p2;
wire [6:0] r_V_169_0_3_fu_19283_p3;
wire [6:0] tmp1252_fu_24346_p2;
wire [6:0] tmp1250_fu_24334_p2;
wire [6:0] r_V_169_0_7_fu_21229_p3;
wire [6:0] r_V_169_0_8_fu_21809_p3;
wire [6:0] tmp1254_fu_24358_p2;
wire [6:0] r_V_169_0_6_fu_20811_p3;
wire [6:0] r_V_169_0_s_fu_22723_p3;
wire [6:0] r_V_169_0_10_fu_24321_p3;
wire [6:0] tmp1256_fu_24370_p2;
wire [6:0] r_V_169_0_9_fu_22289_p3;
wire [6:0] tmp1257_fu_24376_p2;
wire [6:0] tmp1255_fu_24364_p2;
wire [6:0] tmp1258_fu_24382_p2;
wire [6:0] tmp1253_fu_24352_p2;
wire [0:0] tmp_2265_fu_24394_p2;
wire [1:0] tmp1259_fu_24400_p3;
wire [1:0] r_V_176_0_9_fu_22296_p3;
wire [1:0] tmp1261_fu_24414_p3;
wire [1:0] r_V_176_0_5_fu_20392_p3;
wire [1:0] tmp1262_fu_24422_p2;
wire [1:0] tmp1260_fu_24408_p2;
wire [0:0] tmp_2266_fu_24434_p2;
wire [1:0] tmp1264_fu_24440_p3;
wire [1:0] r_V_176_0_1_fu_18464_p3;
wire [0:0] tmp_2267_fu_24454_p2;
wire [1:0] tmp1266_fu_24460_p3;
wire [1:0] r_V_176_0_4_fu_19904_p3;
wire [1:0] tmp1267_fu_24468_p2;
wire [1:0] tmp1265_fu_24448_p2;
wire [1:0] tmp1268_fu_24474_p2;
wire [1:0] tmp1263_fu_24428_p2;
wire [0:0] tmp_2268_fu_24486_p3;
wire [0:0] tmp_2269_fu_24494_p2;
wire [1:0] r_V_176_0_3_fu_19290_p3;
wire [0:0] tmp_2271_fu_24514_p3;
wire [0:0] tmp_2270_fu_24508_p2;
wire [1:0] tmp1272_fu_24522_p3;
wire [1:0] tmp1270_fu_24500_p3;
wire [0:0] tmp_2272_fu_24536_p3;
wire [1:0] tmp1274_fu_24544_p3;
wire [1:0] r_V_176_0_6_fu_20818_p3;
wire [0:0] tmp_2273_fu_24558_p2;
wire [1:0] tmp1277_fu_24572_p3;
wire [1:0] tmp1275_fu_24552_p2;
wire [1:0] tmp1278_fu_24580_p2;
wire [1:0] tmp1273_fu_24530_p2;
wire [0:0] tmp_2274_fu_24600_p3;
wire [1:0] tmp1281_fu_24608_p3;
wire [1:0] tmp1282_fu_24616_p2;
wire [1:0] tmp1280_fu_24592_p3;
wire [1:0] tmp1276_fu_24564_p3;
wire [1:0] tmp1287_fu_24628_p2;
wire [1:0] tmp1288_fu_24634_p2;
wire [1:0] tmp1283_fu_24622_p2;
wire [2:0] tmp_2275_fu_24646_p3;
wire [2:0] r_V_177_0_s_fu_22730_p3;
wire [2:0] tmp_538_fu_24654_p2;
wire [3:0] tmp1299_fu_24660_p3;
wire [3:0] bt_ci_V_9_fu_22304_p3;
wire [3:0] bt_ci_V163_9_fu_22312_p3;
wire [2:0] tmp_2276_fu_24682_p1;
wire [2:0] tmp1300_fu_24674_p3;
wire [0:0] tmp_2278_fu_24692_p3;
wire [2:0] tmp_2277_fu_24686_p2;
wire [3:0] bt_ci_V164_8_fu_21832_p3;
wire [2:0] tmp_2279_fu_24708_p1;
wire [2:0] r_V_177_0_9_3_fu_22320_p3;
wire [2:0] tmp_2280_fu_24712_p2;
wire [0:0] tmp_2281_fu_24718_p3;
wire [2:0] tmp_2282_fu_24726_p2;
wire [4:0] p_Result_1296_0_11_4_fu_22977_p6;
wire [0:0] tmp_2283_fu_24748_p3;
wire [5:0] bt_sign_ph_V1_fu_24882_p3;
wire [0:0] tmp_2285_fu_24919_p1;
wire [5:0] bt_sign_th_V1_fu_24889_p3;
wire [0:0] tmp_2286_fu_24928_p1;
wire [0:0] tmp_2287_fu_24937_p3;
wire [0:0] tmp_2288_fu_24950_p3;
wire [0:0] tmp_2289_fu_24963_p3;
wire [0:0] tmp_2290_fu_24976_p3;
wire [0:0] tmp_2291_fu_24989_p3;
wire [0:0] tmp_2292_fu_25002_p3;
wire [0:0] tmp_2293_fu_25015_p3;
wire [0:0] tmp_2294_fu_25028_p3;
wire [0:0] tmp_2295_fu_25041_p3;
wire [0:0] tmp_549_fu_25049_p2;
wire [0:0] tmp_547_fu_25023_p2;
wire [0:0] tmp_545_fu_24997_p2;
wire [0:0] tmp_543_fu_24971_p2;
wire [0:0] tmp_541_fu_24945_p2;
wire [0:0] tmp_539_fu_24923_p2;
wire [0:0] tmp_2296_fu_25070_p3;
wire [0:0] tmp_550_fu_25078_p2;
wire [0:0] tmp_548_fu_25036_p2;
wire [0:0] tmp_546_fu_25010_p2;
wire [0:0] tmp_544_fu_24984_p2;
wire [0:0] tmp_542_fu_24958_p2;
wire [0:0] tmp_540_fu_24932_p2;
wire [4:0] bt_si_V1_fu_24903_p3;
wire [0:0] tmp_2297_fu_25099_p1;
wire [0:0] tmp_2298_fu_25108_p3;
wire [0:0] tmp_2299_fu_25121_p3;
wire [0:0] tmp_2300_fu_25134_p3;
wire [0:0] tmp_553_fu_25129_p2;
wire [0:0] tmp_552_fu_25116_p2;
wire [0:0] tmp_551_fu_25103_p2;
wire [0:0] tmp_2284_fu_24911_p3;
wire [5:0] p_Result_1290_1_1_5_fu_25054_p7;
wire [5:0] p_Result_1293_1_1_5_fu_25083_p7;
wire [4:0] p_Result_1296_1_1_4_fu_25142_p6;
wire [5:0] bt_sign_ph_V47_1_fu_25282_p3;
wire [0:0] tmp_2303_fu_25335_p1;
wire [5:0] bt_sign_th_V49_1_fu_25290_p3;
wire [0:0] tmp_2304_fu_25344_p1;
wire [0:0] tmp_2305_fu_25353_p3;
wire [0:0] tmp_2306_fu_25366_p3;
wire [0:0] tmp_2307_fu_25379_p3;
wire [0:0] tmp_2308_fu_25392_p3;
wire [0:0] tmp_2309_fu_25405_p3;
wire [0:0] tmp_2310_fu_25418_p3;
wire [0:0] tmp_2311_fu_25431_p3;
wire [0:0] tmp_2312_fu_25444_p3;
wire [0:0] tmp_2313_fu_25457_p3;
wire [0:0] tmp_564_fu_25465_p2;
wire [0:0] tmp_562_fu_25439_p2;
wire [0:0] tmp_560_fu_25413_p2;
wire [0:0] tmp_558_fu_25387_p2;
wire [0:0] tmp_556_fu_25361_p2;
wire [0:0] tmp_554_fu_25339_p2;
wire [0:0] tmp_2314_fu_25486_p3;
wire [0:0] tmp_565_fu_25494_p2;
wire [0:0] tmp_563_fu_25452_p2;
wire [0:0] tmp_561_fu_25426_p2;
wire [0:0] tmp_559_fu_25400_p2;
wire [0:0] tmp_557_fu_25374_p2;
wire [0:0] tmp_555_fu_25348_p2;
wire [4:0] bt_si_V59_1_fu_25319_p3;
wire [0:0] tmp_2315_fu_25515_p1;
wire [0:0] tmp_2316_fu_25524_p3;
wire [0:0] tmp_2317_fu_25537_p3;
wire [0:0] tmp_2318_fu_25550_p3;
wire [0:0] tmp_568_fu_25545_p2;
wire [0:0] tmp_567_fu_25532_p2;
wire [0:0] tmp_566_fu_25519_p2;
wire [0:0] tmp_2302_fu_25327_p3;
wire [5:0] p_Result_1290_1_2_5_fu_25470_p7;
wire [5:0] p_Result_1293_1_2_5_fu_25499_p7;
wire [4:0] p_Result_1296_1_2_4_fu_25558_p6;
wire [5:0] bt_sign_ph_V47_2_fu_25698_p3;
wire [0:0] tmp_2320_fu_25745_p1;
wire [5:0] bt_sign_th_V49_2_fu_25706_p3;
wire [0:0] tmp_2321_fu_25754_p1;
wire [0:0] tmp_2322_fu_25763_p3;
wire [0:0] tmp_2323_fu_25776_p3;
wire [0:0] tmp_2324_fu_25789_p3;
wire [0:0] tmp_2325_fu_25802_p3;
wire [0:0] tmp_2326_fu_25815_p3;
wire [0:0] tmp_2327_fu_25828_p3;
wire [0:0] tmp_2328_fu_25841_p3;
wire [0:0] tmp_2329_fu_25854_p3;
wire [0:0] tmp_2330_fu_25867_p3;
wire [0:0] tmp_579_fu_25875_p2;
wire [0:0] tmp_577_fu_25849_p2;
wire [0:0] tmp_575_fu_25823_p2;
wire [0:0] tmp_573_fu_25797_p2;
wire [0:0] tmp_571_fu_25771_p2;
wire [0:0] tmp_569_fu_25749_p2;
wire [0:0] tmp_2331_fu_25896_p3;
wire [0:0] tmp_580_fu_25904_p2;
wire [0:0] tmp_578_fu_25862_p2;
wire [0:0] tmp_576_fu_25836_p2;
wire [0:0] tmp_574_fu_25810_p2;
wire [0:0] tmp_572_fu_25784_p2;
wire [0:0] tmp_570_fu_25758_p2;
wire [4:0] bt_si_V59_2_fu_25729_p3;
wire [0:0] tmp_2332_fu_25925_p1;
wire [0:0] tmp_2333_fu_25934_p3;
wire [0:0] tmp_2334_fu_25947_p3;
wire [0:0] tmp_2335_fu_25960_p3;
wire [0:0] tmp_583_fu_25955_p2;
wire [0:0] tmp_582_fu_25942_p2;
wire [0:0] tmp_581_fu_25929_p2;
wire [0:0] tmp_2319_fu_25737_p3;
wire [5:0] p_Result_1290_1_3_5_fu_25880_p7;
wire [5:0] p_Result_1293_1_3_5_fu_25909_p7;
wire [3:0] r_V_177_1_3_fu_26139_p3;
wire [2:0] tmp_2336_fu_26147_p1;
wire [2:0] r_V_177_1_2_fu_25721_p3;
wire [0:0] tmp_2337_fu_26157_p1;
wire [0:0] tmp_2301_fu_25313_p2;
wire [2:0] tmp_584_fu_26151_p2;
wire [1:0] tmp_2339_fu_26167_p4;
wire [0:0] tmp_2338_fu_26161_p2;
wire [0:0] tmp_2340_fu_26187_p2;
wire [2:0] tmp_2341_fu_26201_p1;
wire [2:0] tmp_2342_fu_26205_p3;
wire [2:0] tmp1360_fu_26193_p3;
wire [2:0] tmp_2343_fu_26213_p2;
wire [0:0] tmp_2344_fu_26227_p2;
wire [1:0] tmp_2345_fu_26241_p3;
wire [2:0] tmp_585_fu_26249_p3;
wire [2:0] tmp1361_fu_26233_p3;
wire [2:0] tmp_2346_fu_26257_p2;
wire [4:0] p_Result_1296_1_3_4_fu_25968_p6;
wire [5:0] bt_sign_ph_V47_3_fu_26108_p3;
wire [0:0] tmp_2348_fu_26287_p1;
wire [5:0] bt_sign_th_V49_3_fu_26116_p3;
wire [0:0] tmp_2349_fu_26296_p1;
wire [0:0] tmp_2350_fu_26305_p3;
wire [0:0] tmp_2351_fu_26318_p3;
wire [0:0] tmp_2352_fu_26331_p3;
wire [0:0] tmp_2353_fu_26344_p3;
wire [0:0] tmp_2354_fu_26357_p3;
wire [0:0] tmp_2355_fu_26370_p3;
wire [0:0] tmp_2356_fu_26383_p3;
wire [0:0] tmp_2357_fu_26396_p3;
wire [0:0] tmp_2358_fu_26409_p3;
wire [0:0] tmp_596_fu_26417_p2;
wire [0:0] tmp_594_fu_26391_p2;
wire [0:0] tmp_592_fu_26365_p2;
wire [0:0] tmp_590_fu_26339_p2;
wire [0:0] tmp_588_fu_26313_p2;
wire [0:0] tmp_586_fu_26291_p2;
wire [0:0] tmp_2359_fu_26438_p3;
wire [0:0] tmp_597_fu_26446_p2;
wire [0:0] tmp_595_fu_26404_p2;
wire [0:0] tmp_593_fu_26378_p2;
wire [0:0] tmp_591_fu_26352_p2;
wire [0:0] tmp_589_fu_26326_p2;
wire [0:0] tmp_587_fu_26300_p2;
wire [0:0] tmp_2360_fu_26467_p3;
wire [1:0] tmp_598_fu_26475_p3;
wire [0:0] tmp_2361_fu_26489_p3;
wire [1:0] tmp_599_fu_26483_p2;
wire [4:0] bt_si_V59_3_fu_26271_p3;
wire [0:0] tmp_2362_fu_26507_p1;
wire [2:0] tmp_601_fu_26516_p2;
wire [0:0] tmp_2363_fu_26530_p3;
wire [2:0] tmp_603_fu_26543_p2;
wire [0:0] tmp_2364_fu_26557_p3;
wire [0:0] tmp_2365_fu_26570_p3;
wire [0:0] tmp_604_fu_26565_p2;
wire [0:0] tmp_602_fu_26538_p2;
wire [0:0] tmp_600_fu_26511_p2;
wire [0:0] tmp_2347_fu_26279_p3;
wire [5:0] p_Result_1290_1_4_5_fu_26422_p7;
wire [5:0] p_Result_1293_1_4_5_fu_26451_p7;
wire [3:0] r_V_177_1_4_fu_26497_p4;
wire [3:0] bt_ci_V57_3_fu_26177_p4;
wire [3:0] r_V_177_1_4_2_fu_26522_p3;
wire [3:0] bt_ci_V57167_3_fu_26219_p3;
wire [3:0] r_V_177_1_4_3_fu_26549_p3;
wire [3:0] bt_ci_V57168_3_fu_26263_p3;
wire [4:0] p_Result_1296_1_4_4_fu_26578_p6;
wire [5:0] bt_sign_ph_V47_4_fu_26718_p3;
wire [0:0] tmp_2367_fu_26789_p1;
wire [5:0] bt_sign_th_V49_4_fu_26726_p3;
wire [0:0] tmp_2368_fu_26798_p1;
wire [0:0] tmp_2369_fu_26807_p3;
wire [0:0] tmp_2370_fu_26820_p3;
wire [0:0] tmp_2371_fu_26833_p3;
wire [0:0] tmp_2372_fu_26846_p3;
wire [0:0] tmp_2373_fu_26859_p3;
wire [0:0] tmp_2374_fu_26872_p3;
wire [0:0] tmp_2375_fu_26885_p3;
wire [0:0] tmp_2376_fu_26898_p3;
wire [0:0] tmp_2377_fu_26911_p3;
wire [0:0] tmp_615_fu_26919_p2;
wire [0:0] tmp_613_fu_26893_p2;
wire [0:0] tmp_611_fu_26867_p2;
wire [0:0] tmp_609_fu_26841_p2;
wire [0:0] tmp_607_fu_26815_p2;
wire [0:0] tmp_605_fu_26793_p2;
wire [0:0] tmp_2378_fu_26940_p3;
wire [0:0] tmp_616_fu_26948_p2;
wire [0:0] tmp_614_fu_26906_p2;
wire [0:0] tmp_612_fu_26880_p2;
wire [0:0] tmp_610_fu_26854_p2;
wire [0:0] tmp_608_fu_26828_p2;
wire [0:0] tmp_606_fu_26802_p2;
wire [3:0] bt_ci_V57_4_fu_26749_p3;
wire [1:0] tmp_2379_fu_26969_p1;
wire [1:0] tmp_618_fu_26979_p4;
wire [1:0] tmp_617_fu_26973_p2;
wire [4:0] bt_si_V59_4_fu_26773_p3;
wire [0:0] tmp_2380_fu_26997_p1;
wire [3:0] bt_ci_V57167_4_fu_26757_p3;
wire [2:0] tmp_2381_fu_27006_p1;
wire [0:0] tmp_2382_fu_27016_p3;
wire [2:0] tmp_620_fu_27010_p2;
wire [0:0] tmp_2383_fu_27032_p3;
wire [0:0] tmp_2384_fu_27045_p3;
wire [0:0] tmp_2385_fu_27058_p3;
wire [0:0] tmp_622_fu_27053_p2;
wire [0:0] tmp_621_fu_27040_p2;
wire [0:0] tmp_619_fu_27001_p2;
wire [0:0] tmp_2366_fu_26781_p3;
wire [5:0] p_Result_1290_1_5_5_fu_26924_p7;
wire [5:0] p_Result_1293_1_5_5_fu_26953_p7;
wire [3:0] r_V_177_1_5_fu_26989_p3;
wire [3:0] r_V_177_1_5_2_fu_27024_p3;
wire [4:0] p_Result_1296_1_5_4_fu_27066_p6;
wire [5:0] bt_sign_ph_V47_5_fu_27206_p3;
wire [0:0] tmp_2387_fu_27269_p1;
wire [5:0] bt_sign_th_V49_5_fu_27214_p3;
wire [0:0] tmp_2388_fu_27278_p1;
wire [0:0] tmp_2389_fu_27287_p3;
wire [0:0] tmp_2390_fu_27300_p3;
wire [0:0] tmp_2391_fu_27313_p3;
wire [0:0] tmp_2392_fu_27326_p3;
wire [0:0] tmp_2393_fu_27339_p3;
wire [0:0] tmp_2394_fu_27352_p3;
wire [0:0] tmp_2395_fu_27365_p3;
wire [0:0] tmp_2396_fu_27378_p3;
wire [0:0] tmp_2397_fu_27391_p3;
wire [0:0] tmp_633_fu_27399_p2;
wire [0:0] tmp_631_fu_27373_p2;
wire [0:0] tmp_629_fu_27347_p2;
wire [0:0] tmp_627_fu_27321_p2;
wire [0:0] tmp_625_fu_27295_p2;
wire [0:0] tmp_623_fu_27273_p2;
wire [0:0] tmp_2398_fu_27420_p3;
wire [0:0] tmp_634_fu_27428_p2;
wire [0:0] tmp_632_fu_27386_p2;
wire [0:0] tmp_630_fu_27360_p2;
wire [0:0] tmp_628_fu_27334_p2;
wire [0:0] tmp_626_fu_27308_p2;
wire [0:0] tmp_624_fu_27282_p2;
wire [4:0] bt_si_V59_5_fu_27253_p3;
wire [0:0] tmp_2399_fu_27449_p1;
wire [0:0] tmp_2400_fu_27458_p3;
wire [0:0] tmp_2401_fu_27471_p3;
wire [0:0] tmp_2402_fu_27484_p3;
wire [0:0] tmp_637_fu_27479_p2;
wire [0:0] tmp_636_fu_27466_p2;
wire [0:0] tmp_635_fu_27453_p2;
wire [0:0] tmp_2386_fu_27261_p3;
wire [5:0] p_Result_1290_1_6_5_fu_27404_p7;
wire [5:0] p_Result_1293_1_6_5_fu_27433_p7;
wire [4:0] p_Result_1296_1_6_4_fu_27492_p6;
wire [5:0] bt_sign_ph_V47_6_fu_27632_p3;
wire [0:0] tmp_2404_fu_27687_p1;
wire [5:0] bt_sign_th_V49_6_fu_27640_p3;
wire [0:0] tmp_2405_fu_27696_p1;
wire [0:0] tmp_2406_fu_27705_p3;
wire [0:0] tmp_2407_fu_27718_p3;
wire [0:0] tmp_2408_fu_27731_p3;
wire [0:0] tmp_2409_fu_27744_p3;
wire [0:0] tmp_2410_fu_27757_p3;
wire [0:0] tmp_2411_fu_27770_p3;
wire [0:0] tmp_2412_fu_27783_p3;
wire [0:0] tmp_2413_fu_27796_p3;
wire [0:0] tmp_2414_fu_27809_p3;
wire [0:0] tmp_648_fu_27817_p2;
wire [0:0] tmp_646_fu_27791_p2;
wire [0:0] tmp_644_fu_27765_p2;
wire [0:0] tmp_642_fu_27739_p2;
wire [0:0] tmp_640_fu_27713_p2;
wire [0:0] tmp_638_fu_27691_p2;
wire [0:0] tmp_2415_fu_27838_p3;
wire [0:0] tmp_649_fu_27846_p2;
wire [0:0] tmp_647_fu_27804_p2;
wire [0:0] tmp_645_fu_27778_p2;
wire [0:0] tmp_643_fu_27752_p2;
wire [0:0] tmp_641_fu_27726_p2;
wire [0:0] tmp_639_fu_27700_p2;
wire [4:0] bt_si_V59_6_fu_27671_p3;
wire [0:0] tmp_2416_fu_27867_p1;
wire [0:0] tmp_2417_fu_27876_p3;
wire [0:0] tmp_2418_fu_27889_p3;
wire [0:0] tmp_2419_fu_27902_p3;
wire [0:0] tmp_652_fu_27897_p2;
wire [0:0] tmp_651_fu_27884_p2;
wire [0:0] tmp_650_fu_27871_p2;
wire [0:0] tmp_2403_fu_27679_p3;
wire [5:0] p_Result_1290_1_7_5_fu_27822_p7;
wire [5:0] p_Result_1293_1_7_5_fu_27851_p7;
wire [2:0] tmp_2420_fu_28073_p3;
wire [2:0] r_V_177_1_6_fu_27663_p3;
wire [2:0] tmp_653_fu_28081_p2;
wire [3:0] tmp1392_fu_28087_p3;
wire [3:0] bt_ci_V57_5_fu_27237_p3;
wire [0:0] tmp_2421_fu_28109_p2;
wire [3:0] bt_ci_V57167_5_fu_27245_p3;
wire [2:0] tmp_2422_fu_28123_p1;
wire [2:0] tmp1393_fu_28115_p3;
wire [0:0] tmp_2424_fu_28133_p3;
wire [2:0] tmp_2423_fu_28127_p2;
wire [0:0] tmp_2425_fu_28149_p2;
wire [3:0] bt_ci_V57168_4_fu_26765_p3;
wire [2:0] tmp_2426_fu_28163_p1;
wire [2:0] r_V_177_1_7_2_fu_28101_p3;
wire [2:0] tmp_2427_fu_28167_p2;
wire [2:0] tmp1394_fu_28155_p3;
wire [0:0] tmp_2428_fu_28173_p3;
wire [2:0] tmp_2429_fu_28181_p2;
wire [4:0] p_Result_1296_1_7_4_fu_27910_p6;
wire [5:0] bt_sign_ph_V47_7_fu_28050_p3;
wire [0:0] tmp_2431_fu_28211_p1;
wire [5:0] bt_sign_th_V49_7_fu_28058_p3;
wire [0:0] tmp_2432_fu_28220_p1;
wire [0:0] tmp_2433_fu_28229_p3;
wire [0:0] tmp_2434_fu_28242_p3;
wire [0:0] tmp_2435_fu_28255_p3;
wire [0:0] tmp_2436_fu_28268_p3;
wire [0:0] tmp_2437_fu_28281_p3;
wire [0:0] tmp_2438_fu_28294_p3;
wire [0:0] tmp_2439_fu_28307_p3;
wire [0:0] tmp_2440_fu_28320_p3;
wire [0:0] tmp_2441_fu_28333_p3;
wire [0:0] tmp_664_fu_28341_p2;
wire [0:0] tmp_662_fu_28315_p2;
wire [0:0] tmp_660_fu_28289_p2;
wire [0:0] tmp_658_fu_28263_p2;
wire [0:0] tmp_656_fu_28237_p2;
wire [0:0] tmp_654_fu_28215_p2;
wire [0:0] tmp_2442_fu_28362_p3;
wire [0:0] tmp_665_fu_28370_p2;
wire [0:0] tmp_663_fu_28328_p2;
wire [0:0] tmp_661_fu_28302_p2;
wire [0:0] tmp_659_fu_28276_p2;
wire [0:0] tmp_657_fu_28250_p2;
wire [0:0] tmp_655_fu_28224_p2;
wire [3:0] bt_ci_V57_7_fu_28095_p2;
wire [1:0] tmp_2443_fu_28391_p1;
wire [1:0] tmp_667_fu_28401_p4;
wire [1:0] tmp_666_fu_28395_p2;
wire [4:0] bt_si_V59_7_fu_28195_p3;
wire [0:0] tmp_2444_fu_28419_p1;
wire [2:0] tmp_669_fu_28428_p2;
wire [0:0] tmp_2445_fu_28442_p3;
wire [2:0] tmp_671_fu_28455_p2;
wire [0:0] tmp_2446_fu_28469_p3;
wire [0:0] tmp_2447_fu_28482_p3;
wire [0:0] tmp_672_fu_28477_p2;
wire [0:0] tmp_670_fu_28450_p2;
wire [0:0] tmp_668_fu_28423_p2;
wire [0:0] tmp_2430_fu_28203_p3;
wire [5:0] p_Result_1290_1_8_5_fu_28346_p7;
wire [5:0] p_Result_1293_1_8_5_fu_28375_p7;
wire [3:0] r_V_177_1_8_fu_28411_p3;
wire [3:0] r_V_177_1_8_2_fu_28434_p3;
wire [3:0] bt_ci_V57167_7_fu_28141_p3;
wire [3:0] r_V_177_1_8_3_fu_28461_p3;
wire [3:0] bt_ci_V57168_7_fu_28187_p3;
wire [4:0] p_Result_1296_1_8_4_fu_28490_p6;
wire [5:0] bt_sign_ph_V47_8_fu_28630_p3;
wire [0:0] tmp_2449_fu_28693_p1;
wire [5:0] bt_sign_th_V49_8_fu_28638_p3;
wire [0:0] tmp_2450_fu_28702_p1;
wire [0:0] tmp_2451_fu_28711_p3;
wire [0:0] tmp_2452_fu_28724_p3;
wire [0:0] tmp_2453_fu_28737_p3;
wire [0:0] tmp_2454_fu_28750_p3;
wire [0:0] tmp_2455_fu_28763_p3;
wire [0:0] tmp_2456_fu_28776_p3;
wire [0:0] tmp_2457_fu_28789_p3;
wire [0:0] tmp_2458_fu_28802_p3;
wire [0:0] tmp_2459_fu_28815_p3;
wire [0:0] tmp_683_fu_28823_p2;
wire [0:0] tmp_681_fu_28797_p2;
wire [0:0] tmp_679_fu_28771_p2;
wire [0:0] tmp_677_fu_28745_p2;
wire [0:0] tmp_675_fu_28719_p2;
wire [0:0] tmp_673_fu_28697_p2;
wire [0:0] tmp_2460_fu_28844_p3;
wire [0:0] tmp_684_fu_28852_p2;
wire [0:0] tmp_682_fu_28810_p2;
wire [0:0] tmp_680_fu_28784_p2;
wire [0:0] tmp_678_fu_28758_p2;
wire [0:0] tmp_676_fu_28732_p2;
wire [0:0] tmp_674_fu_28706_p2;
wire [3:0] bt_ci_V57_8_fu_28653_p3;
wire [1:0] tmp_2461_fu_28873_p1;
wire [1:0] tmp_686_fu_28883_p4;
wire [1:0] tmp_685_fu_28877_p2;
wire [4:0] bt_si_V59_8_fu_28677_p3;
wire [0:0] tmp_2462_fu_28901_p1;
wire [3:0] bt_ci_V57167_8_fu_28661_p3;
wire [2:0] tmp_2463_fu_28910_p1;
wire [0:0] tmp_2464_fu_28920_p3;
wire [2:0] tmp_688_fu_28914_p2;
wire [0:0] tmp_2465_fu_28936_p3;
wire [0:0] tmp_2466_fu_28949_p3;
wire [0:0] tmp_2467_fu_28962_p3;
wire [0:0] tmp_690_fu_28957_p2;
wire [0:0] tmp_689_fu_28944_p2;
wire [0:0] tmp_687_fu_28905_p2;
wire [0:0] tmp_2448_fu_28685_p3;
wire [5:0] p_Result_1290_1_9_5_fu_28828_p7;
wire [5:0] p_Result_1293_1_9_5_fu_28857_p7;
wire [3:0] r_V_177_1_9_fu_28893_p3;
wire [3:0] r_V_177_1_9_2_fu_28928_p3;
wire [4:0] p_Result_1296_1_9_4_fu_28970_p6;
wire [5:0] bt_sign_ph_V47_9_fu_29110_p3;
wire [0:0] tmp_2469_fu_29181_p1;
wire [5:0] bt_sign_th_V49_9_fu_29118_p3;
wire [0:0] tmp_2470_fu_29190_p1;
wire [0:0] tmp_2471_fu_29199_p3;
wire [0:0] tmp_2472_fu_29212_p3;
wire [0:0] tmp_2473_fu_29225_p3;
wire [0:0] tmp_2474_fu_29238_p3;
wire [0:0] tmp_2475_fu_29251_p3;
wire [0:0] tmp_2476_fu_29264_p3;
wire [0:0] tmp_2477_fu_29277_p3;
wire [0:0] tmp_2478_fu_29290_p3;
wire [0:0] tmp_2479_fu_29303_p3;
wire [0:0] tmp_701_fu_29311_p2;
wire [0:0] tmp_699_fu_29285_p2;
wire [0:0] tmp_697_fu_29259_p2;
wire [0:0] tmp_695_fu_29233_p2;
wire [0:0] tmp_693_fu_29207_p2;
wire [0:0] tmp_691_fu_29185_p2;
wire [0:0] tmp_2480_fu_29332_p3;
wire [0:0] tmp_702_fu_29340_p2;
wire [0:0] tmp_700_fu_29298_p2;
wire [0:0] tmp_698_fu_29272_p2;
wire [0:0] tmp_696_fu_29246_p2;
wire [0:0] tmp_694_fu_29220_p2;
wire [0:0] tmp_692_fu_29194_p2;
wire [4:0] bt_si_V59_9_fu_29165_p3;
wire [0:0] tmp_2481_fu_29361_p1;
wire [0:0] tmp_2482_fu_29370_p3;
wire [0:0] tmp_2483_fu_29383_p3;
wire [0:0] tmp_2484_fu_29396_p3;
wire [0:0] tmp_705_fu_29391_p2;
wire [0:0] tmp_704_fu_29378_p2;
wire [0:0] tmp_703_fu_29365_p2;
wire [0:0] tmp_2468_fu_29173_p3;
wire [5:0] p_Result_1290_1_10_5_fu_29316_p7;
wire [5:0] p_Result_1293_1_10_5_fu_29345_p7;
wire [4:0] p_Result_1296_1_10_4_fu_29404_p6;
wire [5:0] bt_sign_ph_V47_s_fu_29544_p3;
wire [0:0] tmp_2486_fu_29591_p1;
wire [5:0] bt_sign_th_V49_s_fu_29552_p3;
wire [0:0] tmp_2487_fu_29600_p1;
wire [0:0] tmp_2488_fu_29609_p3;
wire [0:0] tmp_2489_fu_29622_p3;
wire [0:0] tmp_2490_fu_29635_p3;
wire [0:0] tmp_2491_fu_29648_p3;
wire [0:0] tmp_2492_fu_29661_p3;
wire [0:0] tmp_2493_fu_29674_p3;
wire [0:0] tmp_2494_fu_29687_p3;
wire [0:0] tmp_2495_fu_29700_p3;
wire [0:0] tmp_2496_fu_29713_p3;
wire [0:0] tmp_716_fu_29721_p2;
wire [0:0] tmp_714_fu_29695_p2;
wire [0:0] tmp_712_fu_29669_p2;
wire [0:0] tmp_710_fu_29643_p2;
wire [0:0] tmp_708_fu_29617_p2;
wire [0:0] tmp_706_fu_29595_p2;
wire [0:0] tmp_2497_fu_29742_p3;
wire [0:0] tmp_717_fu_29750_p2;
wire [0:0] tmp_715_fu_29708_p2;
wire [0:0] tmp_713_fu_29682_p2;
wire [0:0] tmp_711_fu_29656_p2;
wire [0:0] tmp_709_fu_29630_p2;
wire [0:0] tmp_707_fu_29604_p2;
wire [4:0] bt_si_V59_s_fu_29575_p3;
wire [0:0] tmp_2498_fu_29771_p1;
wire [0:0] tmp_2499_fu_29780_p3;
wire [0:0] tmp_2500_fu_29793_p3;
wire [0:0] tmp_2501_fu_29806_p3;
wire [0:0] tmp_720_fu_29801_p2;
wire [0:0] tmp_719_fu_29788_p2;
wire [0:0] tmp_718_fu_29775_p2;
wire [0:0] tmp_2485_fu_29583_p3;
wire [11:0] r_V_170_1_1_fu_25156_p3;
wire [11:0] r_V_170_1_2_fu_25572_p3;
wire [11:0] tmp1396_fu_29835_p2;
wire [11:0] bt_phi_V1_fu_24756_p3;
wire [11:0] r_V_170_1_4_fu_26592_p3;
wire [11:0] r_V_170_1_5_fu_27080_p3;
wire [11:0] tmp1398_fu_29847_p2;
wire [11:0] r_V_170_1_3_fu_25982_p3;
wire [11:0] tmp1399_fu_29853_p2;
wire [11:0] tmp1397_fu_29841_p2;
wire [11:0] r_V_170_1_7_fu_27924_p3;
wire [11:0] r_V_170_1_8_fu_28504_p3;
wire [11:0] tmp1401_fu_29865_p2;
wire [11:0] r_V_170_1_6_fu_27506_p3;
wire [11:0] r_V_170_1_s_fu_29418_p3;
wire [11:0] r_V_170_1_10_fu_29828_p3;
wire [11:0] tmp1403_fu_29877_p2;
wire [11:0] r_V_170_1_9_fu_28984_p3;
wire [11:0] tmp1404_fu_29883_p2;
wire [11:0] tmp1402_fu_29871_p2;
wire [11:0] tmp1405_fu_29889_p2;
wire [11:0] tmp1400_fu_29859_p2;
wire [6:0] r_V_171_1_1_fu_25163_p3;
wire [6:0] r_V_171_1_2_fu_25579_p3;
wire [6:0] tmp1406_fu_29908_p2;
wire [6:0] bt_theta_V1_fu_24763_p3;
wire [6:0] r_V_171_1_4_fu_26599_p3;
wire [6:0] r_V_171_1_5_fu_27087_p3;
wire [6:0] tmp1408_fu_29920_p2;
wire [6:0] r_V_171_1_3_fu_25989_p3;
wire [6:0] tmp1409_fu_29926_p2;
wire [6:0] tmp1407_fu_29914_p2;
wire [6:0] r_V_171_1_7_fu_27931_p3;
wire [6:0] r_V_171_1_8_fu_28511_p3;
wire [6:0] tmp1411_fu_29938_p2;
wire [6:0] r_V_171_1_6_fu_27513_p3;
wire [6:0] r_V_171_1_s_fu_29425_p3;
wire [6:0] r_V_171_1_10_fu_29901_p3;
wire [6:0] tmp1413_fu_29950_p2;
wire [6:0] r_V_171_1_9_fu_28991_p3;
wire [6:0] tmp1414_fu_29956_p2;
wire [6:0] tmp1412_fu_29944_p2;
wire [6:0] tmp1415_fu_29962_p2;
wire [6:0] tmp1410_fu_29932_p2;
wire [3:0] r_V_172_1_1_fu_25170_p3;
wire [3:0] r_V_172_1_2_fu_25586_p3;
wire [3:0] tmp1416_fu_29981_p2;
wire [3:0] bt_cpattern_V4_fu_24770_p3;
wire [3:0] r_V_172_1_4_fu_26606_p3;
wire [3:0] r_V_172_1_5_fu_27094_p3;
wire [3:0] tmp1418_fu_29993_p2;
wire [3:0] r_V_172_1_3_fu_25996_p3;
wire [3:0] tmp1419_fu_29999_p2;
wire [3:0] tmp1417_fu_29987_p2;
wire [3:0] r_V_172_1_7_fu_27938_p3;
wire [3:0] r_V_172_1_8_fu_28518_p3;
wire [3:0] tmp1421_fu_30011_p2;
wire [3:0] r_V_172_1_6_fu_27520_p3;
wire [3:0] r_V_172_1_s_fu_29432_p3;
wire [3:0] r_V_172_1_10_fu_29974_p3;
wire [3:0] tmp1423_fu_30023_p2;
wire [3:0] r_V_172_1_9_fu_28998_p3;
wire [3:0] tmp1424_fu_30029_p2;
wire [3:0] tmp1422_fu_30017_p2;
wire [3:0] tmp1425_fu_30035_p2;
wire [3:0] tmp1420_fu_30005_p2;
wire [3:0] r_V_172_1_1_1_fu_25177_p3;
wire [3:0] r_V_172_1_2_1_fu_25593_p3;
wire [3:0] tmp1426_fu_30054_p2;
wire [3:0] bt_cpattern_V5_fu_24777_p3;
wire [3:0] r_V_172_1_4_1_fu_26613_p3;
wire [3:0] r_V_172_1_5_1_fu_27101_p3;
wire [3:0] tmp1428_fu_30066_p2;
wire [3:0] r_V_172_1_3_1_fu_26003_p3;
wire [3:0] tmp1429_fu_30072_p2;
wire [3:0] tmp1427_fu_30060_p2;
wire [3:0] r_V_172_1_7_1_fu_27945_p3;
wire [3:0] r_V_172_1_8_1_fu_28525_p3;
wire [3:0] tmp1431_fu_30084_p2;
wire [3:0] r_V_172_1_6_1_fu_27527_p3;
wire [3:0] r_V_172_1_10_1_fu_29439_p3;
wire [3:0] r_V_172_1_11_1_fu_30047_p3;
wire [3:0] tmp1433_fu_30096_p2;
wire [3:0] r_V_172_1_9_1_fu_29005_p3;
wire [3:0] tmp1434_fu_30102_p2;
wire [3:0] tmp1432_fu_30090_p2;
wire [3:0] tmp1435_fu_30108_p2;
wire [3:0] tmp1430_fu_30078_p2;
wire [3:0] r_V_172_1_1_2_fu_25184_p3;
wire [3:0] r_V_172_1_2_2_fu_25600_p3;
wire [3:0] tmp1436_fu_30127_p2;
wire [3:0] bt_cpattern_V6_fu_24784_p3;
wire [3:0] r_V_172_1_4_2_fu_26620_p3;
wire [3:0] r_V_172_1_5_2_fu_27108_p3;
wire [3:0] tmp1438_fu_30139_p2;
wire [3:0] r_V_172_1_3_2_fu_26010_p3;
wire [3:0] tmp1439_fu_30145_p2;
wire [3:0] tmp1437_fu_30133_p2;
wire [3:0] r_V_172_1_7_2_fu_27952_p3;
wire [3:0] r_V_172_1_8_2_fu_28532_p3;
wire [3:0] tmp1441_fu_30157_p2;
wire [3:0] r_V_172_1_6_2_fu_27534_p3;
wire [3:0] r_V_172_1_10_2_fu_29446_p3;
wire [3:0] r_V_172_1_11_2_fu_30120_p3;
wire [3:0] tmp1443_fu_30169_p2;
wire [3:0] r_V_172_1_9_2_fu_29012_p3;
wire [3:0] tmp1444_fu_30175_p2;
wire [3:0] tmp1442_fu_30163_p2;
wire [3:0] tmp1445_fu_30181_p2;
wire [3:0] tmp1440_fu_30151_p2;
wire [3:0] r_V_172_1_1_3_fu_25191_p3;
wire [3:0] r_V_172_1_2_3_fu_25607_p3;
wire [3:0] tmp1446_fu_30200_p2;
wire [3:0] bt_cpattern_V7_fu_24791_p3;
wire [3:0] r_V_172_1_4_3_fu_26627_p3;
wire [3:0] r_V_172_1_5_3_fu_27115_p3;
wire [3:0] tmp1448_fu_30212_p2;
wire [3:0] r_V_172_1_3_3_fu_26017_p3;
wire [3:0] tmp1449_fu_30218_p2;
wire [3:0] tmp1447_fu_30206_p2;
wire [3:0] r_V_172_1_7_3_fu_27959_p3;
wire [3:0] r_V_172_1_8_3_fu_28539_p3;
wire [3:0] tmp1451_fu_30230_p2;
wire [3:0] r_V_172_1_6_3_fu_27541_p3;
wire [3:0] r_V_172_1_10_3_fu_29453_p3;
wire [3:0] r_V_172_1_11_3_fu_30193_p3;
wire [3:0] tmp1453_fu_30242_p2;
wire [3:0] r_V_172_1_9_3_fu_29019_p3;
wire [3:0] tmp1454_fu_30248_p2;
wire [3:0] tmp1452_fu_30236_p2;
wire [3:0] tmp1455_fu_30254_p2;
wire [3:0] tmp1450_fu_30224_p2;
wire [11:0] r_V_173_1_1_fu_25198_p3;
wire [11:0] r_V_173_1_2_fu_25614_p3;
wire [11:0] tmp1456_fu_30273_p2;
wire [11:0] bt_delta_ph_V6_fu_24798_p3;
wire [11:0] r_V_173_1_4_fu_26634_p3;
wire [11:0] r_V_173_1_5_fu_27122_p3;
wire [11:0] tmp1458_fu_30285_p2;
wire [11:0] r_V_173_1_3_fu_26024_p3;
wire [11:0] tmp1459_fu_30291_p2;
wire [11:0] tmp1457_fu_30279_p2;
wire [11:0] r_V_173_1_7_fu_27966_p3;
wire [11:0] r_V_173_1_8_fu_28546_p3;
wire [11:0] tmp1461_fu_30303_p2;
wire [11:0] r_V_173_1_6_fu_27548_p3;
wire [11:0] r_V_173_1_s_fu_29460_p3;
wire [11:0] r_V_173_1_10_fu_30266_p3;
wire [11:0] tmp1463_fu_30315_p2;
wire [11:0] r_V_173_1_9_fu_29026_p3;
wire [11:0] tmp1464_fu_30321_p2;
wire [11:0] tmp1462_fu_30309_p2;
wire [11:0] tmp1465_fu_30327_p2;
wire [11:0] tmp1460_fu_30297_p2;
wire [11:0] r_V_173_1_1_1_fu_25205_p3;
wire [11:0] r_V_173_1_2_1_fu_25621_p3;
wire [11:0] tmp1466_fu_30346_p2;
wire [11:0] bt_delta_ph_V7_fu_24805_p3;
wire [11:0] r_V_173_1_4_1_fu_26641_p3;
wire [11:0] r_V_173_1_5_1_fu_27129_p3;
wire [11:0] tmp1468_fu_30358_p2;
wire [11:0] r_V_173_1_3_1_fu_26031_p3;
wire [11:0] tmp1469_fu_30364_p2;
wire [11:0] tmp1467_fu_30352_p2;
wire [11:0] r_V_173_1_7_1_fu_27973_p3;
wire [11:0] r_V_173_1_8_1_fu_28553_p3;
wire [11:0] tmp1471_fu_30376_p2;
wire [11:0] r_V_173_1_6_1_fu_27555_p3;
wire [11:0] r_V_173_1_10_1_fu_29467_p3;
wire [11:0] r_V_173_1_11_1_fu_30339_p3;
wire [11:0] tmp1473_fu_30388_p2;
wire [11:0] r_V_173_1_9_1_fu_29033_p3;
wire [11:0] tmp1474_fu_30394_p2;
wire [11:0] tmp1472_fu_30382_p2;
wire [11:0] tmp1475_fu_30400_p2;
wire [11:0] tmp1470_fu_30370_p2;
wire [11:0] r_V_173_1_1_2_fu_25212_p3;
wire [11:0] r_V_173_1_2_2_fu_25628_p3;
wire [11:0] tmp1476_fu_30419_p2;
wire [11:0] bt_delta_ph_V8_fu_24812_p3;
wire [11:0] r_V_173_1_4_2_fu_26648_p3;
wire [11:0] r_V_173_1_5_2_fu_27136_p3;
wire [11:0] tmp1478_fu_30431_p2;
wire [11:0] r_V_173_1_3_2_fu_26038_p3;
wire [11:0] tmp1479_fu_30437_p2;
wire [11:0] tmp1477_fu_30425_p2;
wire [11:0] r_V_173_1_7_2_fu_27980_p3;
wire [11:0] r_V_173_1_8_2_fu_28560_p3;
wire [11:0] tmp1481_fu_30449_p2;
wire [11:0] r_V_173_1_6_2_fu_27562_p3;
wire [11:0] r_V_173_1_10_2_fu_29474_p3;
wire [11:0] r_V_173_1_11_2_fu_30412_p3;
wire [11:0] tmp1483_fu_30461_p2;
wire [11:0] r_V_173_1_9_2_fu_29040_p3;
wire [11:0] tmp1484_fu_30467_p2;
wire [11:0] tmp1482_fu_30455_p2;
wire [11:0] tmp1485_fu_30473_p2;
wire [11:0] tmp1480_fu_30443_p2;
wire [11:0] r_V_173_1_1_3_fu_25219_p3;
wire [11:0] r_V_173_1_2_3_fu_25635_p3;
wire [11:0] tmp1486_fu_30492_p2;
wire [11:0] bt_delta_ph_V9_fu_24819_p3;
wire [11:0] r_V_173_1_4_3_fu_26655_p3;
wire [11:0] r_V_173_1_5_3_fu_27143_p3;
wire [11:0] tmp1488_fu_30504_p2;
wire [11:0] r_V_173_1_3_3_fu_26045_p3;
wire [11:0] tmp1489_fu_30510_p2;
wire [11:0] tmp1487_fu_30498_p2;
wire [11:0] r_V_173_1_7_3_fu_27987_p3;
wire [11:0] r_V_173_1_8_3_fu_28567_p3;
wire [11:0] tmp1491_fu_30522_p2;
wire [11:0] r_V_173_1_6_3_fu_27569_p3;
wire [11:0] r_V_173_1_10_3_fu_29481_p3;
wire [11:0] r_V_173_1_11_3_fu_30485_p3;
wire [11:0] tmp1493_fu_30534_p2;
wire [11:0] r_V_173_1_9_3_fu_29047_p3;
wire [11:0] tmp1494_fu_30540_p2;
wire [11:0] tmp1492_fu_30528_p2;
wire [11:0] tmp1495_fu_30546_p2;
wire [11:0] tmp1490_fu_30516_p2;
wire [11:0] r_V_173_1_1_4_fu_25226_p3;
wire [11:0] r_V_173_1_2_4_fu_25642_p3;
wire [11:0] tmp1496_fu_30565_p2;
wire [11:0] bt_delta_ph_V10_fu_24826_p3;
wire [11:0] r_V_173_1_4_4_fu_26662_p3;
wire [11:0] r_V_173_1_5_4_fu_27150_p3;
wire [11:0] tmp1498_fu_30577_p2;
wire [11:0] r_V_173_1_3_4_fu_26052_p3;
wire [11:0] tmp1499_fu_30583_p2;
wire [11:0] tmp1497_fu_30571_p2;
wire [11:0] r_V_173_1_7_4_fu_27994_p3;
wire [11:0] r_V_173_1_8_4_fu_28574_p3;
wire [11:0] tmp1501_fu_30595_p2;
wire [11:0] r_V_173_1_6_4_fu_27576_p3;
wire [11:0] r_V_173_1_10_4_fu_29488_p3;
wire [11:0] r_V_173_1_11_4_fu_30558_p3;
wire [11:0] tmp1503_fu_30607_p2;
wire [11:0] r_V_173_1_9_4_fu_29054_p3;
wire [11:0] tmp1504_fu_30613_p2;
wire [11:0] tmp1502_fu_30601_p2;
wire [11:0] tmp1505_fu_30619_p2;
wire [11:0] tmp1500_fu_30589_p2;
wire [11:0] r_V_173_1_1_5_fu_25233_p3;
wire [11:0] r_V_173_1_2_5_fu_25649_p3;
wire [11:0] tmp1506_fu_30638_p2;
wire [11:0] bt_delta_ph_V11_fu_24833_p3;
wire [11:0] r_V_173_1_4_5_fu_26669_p3;
wire [11:0] r_V_173_1_5_5_fu_27157_p3;
wire [11:0] tmp1508_fu_30650_p2;
wire [11:0] r_V_173_1_3_5_fu_26059_p3;
wire [11:0] tmp1509_fu_30656_p2;
wire [11:0] tmp1507_fu_30644_p2;
wire [11:0] r_V_173_1_7_5_fu_28001_p3;
wire [11:0] r_V_173_1_8_5_fu_28581_p3;
wire [11:0] tmp1511_fu_30668_p2;
wire [11:0] r_V_173_1_6_5_fu_27583_p3;
wire [11:0] r_V_173_1_10_5_fu_29495_p3;
wire [11:0] r_V_173_1_11_5_fu_30631_p3;
wire [11:0] tmp1513_fu_30680_p2;
wire [11:0] r_V_173_1_9_5_fu_29061_p3;
wire [11:0] tmp1514_fu_30686_p2;
wire [11:0] tmp1512_fu_30674_p2;
wire [11:0] tmp1515_fu_30692_p2;
wire [11:0] tmp1510_fu_30662_p2;
wire [6:0] r_V_174_1_1_fu_25240_p3;
wire [6:0] r_V_174_1_2_fu_25656_p3;
wire [6:0] tmp1516_fu_30711_p2;
wire [6:0] bt_delta_th_V6_fu_24840_p3;
wire [6:0] r_V_174_1_4_fu_26676_p3;
wire [6:0] r_V_174_1_5_fu_27164_p3;
wire [6:0] tmp1518_fu_30723_p2;
wire [6:0] r_V_174_1_3_fu_26066_p3;
wire [6:0] tmp1519_fu_30729_p2;
wire [6:0] tmp1517_fu_30717_p2;
wire [6:0] r_V_174_1_7_fu_28008_p3;
wire [6:0] r_V_174_1_8_fu_28588_p3;
wire [6:0] tmp1521_fu_30741_p2;
wire [6:0] r_V_174_1_6_fu_27590_p3;
wire [6:0] r_V_174_1_s_fu_29502_p3;
wire [6:0] r_V_174_1_10_fu_30704_p3;
wire [6:0] tmp1523_fu_30753_p2;
wire [6:0] r_V_174_1_9_fu_29068_p3;
wire [6:0] tmp1524_fu_30759_p2;
wire [6:0] tmp1522_fu_30747_p2;
wire [6:0] tmp1525_fu_30765_p2;
wire [6:0] tmp1520_fu_30735_p2;
wire [6:0] r_V_174_1_1_1_fu_25247_p3;
wire [6:0] r_V_174_1_2_1_fu_25663_p3;
wire [6:0] tmp1526_fu_30784_p2;
wire [6:0] bt_delta_th_V7_fu_24847_p3;
wire [6:0] r_V_174_1_4_1_fu_26683_p3;
wire [6:0] r_V_174_1_5_1_fu_27171_p3;
wire [6:0] tmp1528_fu_30796_p2;
wire [6:0] r_V_174_1_3_1_fu_26073_p3;
wire [6:0] tmp1529_fu_30802_p2;
wire [6:0] tmp1527_fu_30790_p2;
wire [6:0] r_V_174_1_7_1_fu_28015_p3;
wire [6:0] r_V_174_1_8_1_fu_28595_p3;
wire [6:0] tmp1531_fu_30814_p2;
wire [6:0] r_V_174_1_6_1_fu_27597_p3;
wire [6:0] r_V_174_1_10_1_fu_29509_p3;
wire [6:0] r_V_174_1_11_1_fu_30777_p3;
wire [6:0] tmp1533_fu_30826_p2;
wire [6:0] r_V_174_1_9_1_fu_29075_p3;
wire [6:0] tmp1534_fu_30832_p2;
wire [6:0] tmp1532_fu_30820_p2;
wire [6:0] tmp1535_fu_30838_p2;
wire [6:0] tmp1530_fu_30808_p2;
wire [6:0] r_V_174_1_1_2_fu_25254_p3;
wire [6:0] r_V_174_1_2_2_fu_25670_p3;
wire [6:0] tmp1536_fu_30857_p2;
wire [6:0] bt_delta_th_V8_fu_24854_p3;
wire [6:0] r_V_174_1_4_2_fu_26690_p3;
wire [6:0] r_V_174_1_5_2_fu_27178_p3;
wire [6:0] tmp1538_fu_30869_p2;
wire [6:0] r_V_174_1_3_2_fu_26080_p3;
wire [6:0] tmp1539_fu_30875_p2;
wire [6:0] tmp1537_fu_30863_p2;
wire [6:0] r_V_174_1_7_2_fu_28022_p3;
wire [6:0] r_V_174_1_8_2_fu_28602_p3;
wire [6:0] tmp1541_fu_30887_p2;
wire [6:0] r_V_174_1_6_2_fu_27604_p3;
wire [6:0] r_V_174_1_10_2_fu_29516_p3;
wire [6:0] r_V_174_1_11_2_fu_30850_p3;
wire [6:0] tmp1543_fu_30899_p2;
wire [6:0] r_V_174_1_9_2_fu_29082_p3;
wire [6:0] tmp1544_fu_30905_p2;
wire [6:0] tmp1542_fu_30893_p2;
wire [6:0] tmp1545_fu_30911_p2;
wire [6:0] tmp1540_fu_30881_p2;
wire [6:0] r_V_174_1_1_3_fu_25261_p3;
wire [6:0] r_V_174_1_2_3_fu_25677_p3;
wire [6:0] tmp1546_fu_30930_p2;
wire [6:0] bt_delta_th_V9_fu_24861_p3;
wire [6:0] r_V_174_1_4_3_fu_26697_p3;
wire [6:0] r_V_174_1_5_3_fu_27185_p3;
wire [6:0] tmp1548_fu_30942_p2;
wire [6:0] r_V_174_1_3_3_fu_26087_p3;
wire [6:0] tmp1549_fu_30948_p2;
wire [6:0] tmp1547_fu_30936_p2;
wire [6:0] r_V_174_1_7_3_fu_28029_p3;
wire [6:0] r_V_174_1_8_3_fu_28609_p3;
wire [6:0] tmp1551_fu_30960_p2;
wire [6:0] r_V_174_1_6_3_fu_27611_p3;
wire [6:0] r_V_174_1_10_3_fu_29523_p3;
wire [6:0] r_V_174_1_11_3_fu_30923_p3;
wire [6:0] tmp1553_fu_30972_p2;
wire [6:0] r_V_174_1_9_3_fu_29089_p3;
wire [6:0] tmp1554_fu_30978_p2;
wire [6:0] tmp1552_fu_30966_p2;
wire [6:0] tmp1555_fu_30984_p2;
wire [6:0] tmp1550_fu_30954_p2;
wire [6:0] r_V_174_1_1_4_fu_25268_p3;
wire [6:0] r_V_174_1_2_4_fu_25684_p3;
wire [6:0] tmp1556_fu_31003_p2;
wire [6:0] bt_delta_th_V10_fu_24868_p3;
wire [6:0] r_V_174_1_4_4_fu_26704_p3;
wire [6:0] r_V_174_1_5_4_fu_27192_p3;
wire [6:0] tmp1558_fu_31015_p2;
wire [6:0] r_V_174_1_3_4_fu_26094_p3;
wire [6:0] tmp1559_fu_31021_p2;
wire [6:0] tmp1557_fu_31009_p2;
wire [6:0] r_V_174_1_7_4_fu_28036_p3;
wire [6:0] r_V_174_1_8_4_fu_28616_p3;
wire [6:0] tmp1561_fu_31033_p2;
wire [6:0] r_V_174_1_6_4_fu_27618_p3;
wire [6:0] r_V_174_1_10_4_fu_29530_p3;
wire [6:0] r_V_174_1_11_4_fu_30996_p3;
wire [6:0] tmp1563_fu_31045_p2;
wire [6:0] r_V_174_1_9_4_fu_29096_p3;
wire [6:0] tmp1564_fu_31051_p2;
wire [6:0] tmp1562_fu_31039_p2;
wire [6:0] tmp1565_fu_31057_p2;
wire [6:0] tmp1560_fu_31027_p2;
wire [6:0] r_V_174_1_1_5_fu_25275_p3;
wire [6:0] r_V_174_1_2_5_fu_25691_p3;
wire [6:0] tmp1566_fu_31076_p2;
wire [6:0] bt_delta_th_V11_fu_24875_p3;
wire [6:0] r_V_174_1_4_5_fu_26711_p3;
wire [6:0] r_V_174_1_5_5_fu_27199_p3;
wire [6:0] tmp1568_fu_31088_p2;
wire [6:0] r_V_174_1_3_5_fu_26101_p3;
wire [6:0] tmp1569_fu_31094_p2;
wire [6:0] tmp1567_fu_31082_p2;
wire [6:0] r_V_174_1_7_5_fu_28043_p3;
wire [6:0] r_V_174_1_8_5_fu_28623_p3;
wire [6:0] tmp1571_fu_31106_p2;
wire [6:0] r_V_174_1_6_5_fu_27625_p3;
wire [6:0] r_V_174_1_10_5_fu_29537_p3;
wire [6:0] r_V_174_1_11_5_fu_31069_p3;
wire [6:0] tmp1573_fu_31118_p2;
wire [6:0] r_V_174_1_9_5_fu_29103_p3;
wire [6:0] tmp1574_fu_31124_p2;
wire [6:0] tmp1572_fu_31112_p2;
wire [6:0] tmp1575_fu_31130_p2;
wire [6:0] tmp1570_fu_31100_p2;
wire [5:0] p_Result_1290_1_11_5_fu_29726_p7;
wire [5:0] p_Result_1293_1_11_5_fu_29755_p7;
wire [6:0] r_V_169_1_1_fu_25298_p3;
wire [6:0] r_V_169_1_2_fu_25714_p3;
wire [6:0] tmp1576_fu_31165_p2;
wire [6:0] bt_rank_V1_fu_24896_p3;
wire [6:0] r_V_169_1_4_fu_26734_p3;
wire [6:0] r_V_169_1_5_fu_27222_p3;
wire [6:0] tmp1578_fu_31177_p2;
wire [6:0] r_V_169_1_3_fu_26124_p3;
wire [6:0] tmp1579_fu_31183_p2;
wire [6:0] tmp1577_fu_31171_p2;
wire [6:0] r_V_169_1_7_fu_28066_p3;
wire [6:0] r_V_169_1_8_fu_28646_p3;
wire [6:0] tmp1581_fu_31195_p2;
wire [6:0] r_V_169_1_6_fu_27648_p3;
wire [6:0] r_V_169_1_s_fu_29560_p3;
wire [6:0] r_V_169_1_10_fu_31158_p3;
wire [6:0] tmp1583_fu_31207_p2;
wire [6:0] r_V_169_1_9_fu_29126_p3;
wire [6:0] tmp1584_fu_31213_p2;
wire [6:0] tmp1582_fu_31201_p2;
wire [6:0] tmp1585_fu_31219_p2;
wire [6:0] tmp1580_fu_31189_p2;
wire [0:0] tmp_2502_fu_31231_p2;
wire [1:0] tmp1586_fu_31237_p3;
wire [1:0] r_V_176_1_9_fu_29133_p3;
wire [1:0] tmp1588_fu_31251_p3;
wire [1:0] r_V_176_1_5_fu_27229_p3;
wire [1:0] tmp1589_fu_31259_p2;
wire [1:0] tmp1587_fu_31245_p2;
wire [0:0] tmp_2503_fu_31271_p2;
wire [1:0] tmp1591_fu_31277_p3;
wire [1:0] r_V_176_1_1_fu_25305_p3;
wire [0:0] tmp_2504_fu_31291_p2;
wire [1:0] tmp1593_fu_31297_p3;
wire [1:0] r_V_176_1_4_fu_26741_p3;
wire [1:0] tmp1594_fu_31305_p2;
wire [1:0] tmp1592_fu_31285_p2;
wire [1:0] tmp1595_fu_31311_p2;
wire [1:0] tmp1590_fu_31265_p2;
wire [0:0] tmp_2505_fu_31323_p3;
wire [0:0] tmp_2506_fu_31331_p2;
wire [1:0] r_V_176_1_3_fu_26131_p3;
wire [0:0] tmp_2508_fu_31351_p3;
wire [0:0] tmp_2507_fu_31345_p2;
wire [1:0] tmp1599_fu_31359_p3;
wire [1:0] tmp1597_fu_31337_p3;
wire [0:0] tmp_2509_fu_31373_p3;
wire [1:0] tmp1601_fu_31381_p3;
wire [1:0] r_V_176_1_6_fu_27655_p3;
wire [0:0] tmp_2510_fu_31395_p2;
wire [1:0] tmp1604_fu_31409_p3;
wire [1:0] tmp1602_fu_31389_p2;
wire [1:0] tmp1605_fu_31417_p2;
wire [1:0] tmp1600_fu_31367_p2;
wire [0:0] tmp_2511_fu_31437_p3;
wire [1:0] tmp1608_fu_31445_p3;
wire [1:0] tmp1609_fu_31453_p2;
wire [1:0] tmp1607_fu_31429_p3;
wire [1:0] tmp1603_fu_31401_p3;
wire [1:0] tmp1614_fu_31465_p2;
wire [1:0] tmp1615_fu_31471_p2;
wire [1:0] tmp1610_fu_31459_p2;
wire [2:0] tmp_2512_fu_31483_p3;
wire [2:0] r_V_177_1_s_fu_29567_p3;
wire [2:0] tmp_721_fu_31491_p2;
wire [3:0] tmp1616_fu_31497_p3;
wire [3:0] bt_ci_V57_9_fu_29141_p3;
wire [3:0] bt_ci_V57167_9_fu_29149_p3;
wire [2:0] tmp_2513_fu_31519_p1;
wire [2:0] tmp1617_fu_31511_p3;
wire [0:0] tmp_2515_fu_31529_p3;
wire [2:0] tmp_2514_fu_31523_p2;
wire [3:0] bt_ci_V57168_8_fu_28669_p3;
wire [2:0] tmp_2516_fu_31545_p1;
wire [2:0] r_V_177_1_9_3_fu_29157_p3;
wire [2:0] tmp_2517_fu_31549_p2;
wire [0:0] tmp_2518_fu_31555_p3;
wire [2:0] tmp_2519_fu_31563_p2;
wire [4:0] p_Result_1296_1_11_4_fu_29814_p6;
wire [0:0] tmp_2520_fu_31585_p3;
wire [5:0] bt_sign_ph_V2_fu_31719_p3;
wire [0:0] tmp_2522_fu_31756_p1;
wire [5:0] bt_sign_th_V2_fu_31726_p3;
wire [0:0] tmp_2523_fu_31765_p1;
wire [0:0] tmp_2524_fu_31774_p3;
wire [0:0] tmp_2525_fu_31787_p3;
wire [0:0] tmp_2526_fu_31800_p3;
wire [0:0] tmp_2527_fu_31813_p3;
wire [0:0] tmp_2528_fu_31826_p3;
wire [0:0] tmp_2529_fu_31839_p3;
wire [0:0] tmp_2530_fu_31852_p3;
wire [0:0] tmp_2531_fu_31865_p3;
wire [0:0] tmp_2532_fu_31878_p3;
wire [0:0] tmp_732_fu_31886_p2;
wire [0:0] tmp_730_fu_31860_p2;
wire [0:0] tmp_728_fu_31834_p2;
wire [0:0] tmp_726_fu_31808_p2;
wire [0:0] tmp_724_fu_31782_p2;
wire [0:0] tmp_722_fu_31760_p2;
wire [0:0] tmp_2533_fu_31907_p3;
wire [0:0] tmp_733_fu_31915_p2;
wire [0:0] tmp_731_fu_31873_p2;
wire [0:0] tmp_729_fu_31847_p2;
wire [0:0] tmp_727_fu_31821_p2;
wire [0:0] tmp_725_fu_31795_p2;
wire [0:0] tmp_723_fu_31769_p2;
wire [4:0] bt_si_V2_fu_31740_p3;
wire [0:0] tmp_2534_fu_31936_p1;
wire [0:0] tmp_2535_fu_31945_p3;
wire [0:0] tmp_2536_fu_31958_p3;
wire [0:0] tmp_2537_fu_31971_p3;
wire [0:0] tmp_736_fu_31966_p2;
wire [0:0] tmp_735_fu_31953_p2;
wire [0:0] tmp_734_fu_31940_p2;
wire [0:0] tmp_2521_fu_31748_p3;
wire [5:0] p_Result_1290_2_1_5_fu_31891_p7;
wire [5:0] p_Result_1293_2_1_5_fu_31920_p7;
wire [4:0] p_Result_1296_2_1_4_fu_31979_p6;
wire [5:0] bt_sign_ph_V48_1_fu_32119_p3;
wire [0:0] tmp_2540_fu_32172_p1;
wire [5:0] bt_sign_th_V50_1_fu_32127_p3;
wire [0:0] tmp_2541_fu_32181_p1;
wire [0:0] tmp_2542_fu_32190_p3;
wire [0:0] tmp_2543_fu_32203_p3;
wire [0:0] tmp_2544_fu_32216_p3;
wire [0:0] tmp_2545_fu_32229_p3;
wire [0:0] tmp_2546_fu_32242_p3;
wire [0:0] tmp_2547_fu_32255_p3;
wire [0:0] tmp_2548_fu_32268_p3;
wire [0:0] tmp_2549_fu_32281_p3;
wire [0:0] tmp_2550_fu_32294_p3;
wire [0:0] tmp_747_fu_32302_p2;
wire [0:0] tmp_745_fu_32276_p2;
wire [0:0] tmp_743_fu_32250_p2;
wire [0:0] tmp_741_fu_32224_p2;
wire [0:0] tmp_739_fu_32198_p2;
wire [0:0] tmp_737_fu_32176_p2;
wire [0:0] tmp_2551_fu_32323_p3;
wire [0:0] tmp_748_fu_32331_p2;
wire [0:0] tmp_746_fu_32289_p2;
wire [0:0] tmp_744_fu_32263_p2;
wire [0:0] tmp_742_fu_32237_p2;
wire [0:0] tmp_740_fu_32211_p2;
wire [0:0] tmp_738_fu_32185_p2;
wire [4:0] bt_si_V60_1_fu_32156_p3;
wire [0:0] tmp_2552_fu_32352_p1;
wire [0:0] tmp_2553_fu_32361_p3;
wire [0:0] tmp_2554_fu_32374_p3;
wire [0:0] tmp_2555_fu_32387_p3;
wire [0:0] tmp_751_fu_32382_p2;
wire [0:0] tmp_750_fu_32369_p2;
wire [0:0] tmp_749_fu_32356_p2;
wire [0:0] tmp_2539_fu_32164_p3;
wire [5:0] p_Result_1290_2_2_5_fu_32307_p7;
wire [5:0] p_Result_1293_2_2_5_fu_32336_p7;
wire [4:0] p_Result_1296_2_2_4_fu_32395_p6;
wire [5:0] bt_sign_ph_V48_2_fu_32535_p3;
wire [0:0] tmp_2557_fu_32582_p1;
wire [5:0] bt_sign_th_V50_2_fu_32543_p3;
wire [0:0] tmp_2558_fu_32591_p1;
wire [0:0] tmp_2559_fu_32600_p3;
wire [0:0] tmp_2560_fu_32613_p3;
wire [0:0] tmp_2561_fu_32626_p3;
wire [0:0] tmp_2562_fu_32639_p3;
wire [0:0] tmp_2563_fu_32652_p3;
wire [0:0] tmp_2564_fu_32665_p3;
wire [0:0] tmp_2565_fu_32678_p3;
wire [0:0] tmp_2566_fu_32691_p3;
wire [0:0] tmp_2567_fu_32704_p3;
wire [0:0] tmp_762_fu_32712_p2;
wire [0:0] tmp_760_fu_32686_p2;
wire [0:0] tmp_758_fu_32660_p2;
wire [0:0] tmp_756_fu_32634_p2;
wire [0:0] tmp_754_fu_32608_p2;
wire [0:0] tmp_752_fu_32586_p2;
wire [0:0] tmp_2568_fu_32733_p3;
wire [0:0] tmp_763_fu_32741_p2;
wire [0:0] tmp_761_fu_32699_p2;
wire [0:0] tmp_759_fu_32673_p2;
wire [0:0] tmp_757_fu_32647_p2;
wire [0:0] tmp_755_fu_32621_p2;
wire [0:0] tmp_753_fu_32595_p2;
wire [4:0] bt_si_V60_2_fu_32566_p3;
wire [0:0] tmp_2569_fu_32762_p1;
wire [0:0] tmp_2570_fu_32771_p3;
wire [0:0] tmp_2571_fu_32784_p3;
wire [0:0] tmp_2572_fu_32797_p3;
wire [0:0] tmp_766_fu_32792_p2;
wire [0:0] tmp_765_fu_32779_p2;
wire [0:0] tmp_764_fu_32766_p2;
wire [0:0] tmp_2556_fu_32574_p3;
wire [5:0] p_Result_1290_2_3_5_fu_32717_p7;
wire [5:0] p_Result_1293_2_3_5_fu_32746_p7;
wire [3:0] r_V_177_2_3_fu_32976_p3;
wire [2:0] tmp_2573_fu_32984_p1;
wire [2:0] r_V_177_2_2_fu_32558_p3;
wire [0:0] tmp_2574_fu_32994_p1;
wire [0:0] tmp_2538_fu_32150_p2;
wire [2:0] tmp_767_fu_32988_p2;
wire [1:0] tmp_2576_fu_33004_p4;
wire [0:0] tmp_2575_fu_32998_p2;
wire [0:0] tmp_2577_fu_33024_p2;
wire [2:0] tmp_2578_fu_33038_p1;
wire [2:0] tmp_2579_fu_33042_p3;
wire [2:0] tmp1621_fu_33030_p3;
wire [2:0] tmp_2580_fu_33050_p2;
wire [0:0] tmp_2581_fu_33064_p2;
wire [1:0] tmp_2582_fu_33078_p3;
wire [2:0] tmp_768_fu_33086_p3;
wire [2:0] tmp1622_fu_33070_p3;
wire [2:0] tmp_2583_fu_33094_p2;
wire [4:0] p_Result_1296_2_3_4_fu_32805_p6;
wire [5:0] bt_sign_ph_V48_3_fu_32945_p3;
wire [0:0] tmp_2585_fu_33124_p1;
wire [5:0] bt_sign_th_V50_3_fu_32953_p3;
wire [0:0] tmp_2586_fu_33133_p1;
wire [0:0] tmp_2587_fu_33142_p3;
wire [0:0] tmp_2588_fu_33155_p3;
wire [0:0] tmp_2589_fu_33168_p3;
wire [0:0] tmp_2590_fu_33181_p3;
wire [0:0] tmp_2591_fu_33194_p3;
wire [0:0] tmp_2592_fu_33207_p3;
wire [0:0] tmp_2593_fu_33220_p3;
wire [0:0] tmp_2594_fu_33233_p3;
wire [0:0] tmp_2595_fu_33246_p3;
wire [0:0] tmp_779_fu_33254_p2;
wire [0:0] tmp_777_fu_33228_p2;
wire [0:0] tmp_775_fu_33202_p2;
wire [0:0] tmp_773_fu_33176_p2;
wire [0:0] tmp_771_fu_33150_p2;
wire [0:0] tmp_769_fu_33128_p2;
wire [0:0] tmp_2596_fu_33275_p3;
wire [0:0] tmp_780_fu_33283_p2;
wire [0:0] tmp_778_fu_33241_p2;
wire [0:0] tmp_776_fu_33215_p2;
wire [0:0] tmp_774_fu_33189_p2;
wire [0:0] tmp_772_fu_33163_p2;
wire [0:0] tmp_770_fu_33137_p2;
wire [0:0] tmp_2597_fu_33304_p3;
wire [1:0] tmp_781_fu_33312_p3;
wire [0:0] tmp_2598_fu_33326_p3;
wire [1:0] tmp_782_fu_33320_p2;
wire [4:0] bt_si_V60_3_fu_33108_p3;
wire [0:0] tmp_2599_fu_33344_p1;
wire [2:0] tmp_784_fu_33353_p2;
wire [0:0] tmp_2600_fu_33367_p3;
wire [2:0] tmp_786_fu_33380_p2;
wire [0:0] tmp_2601_fu_33394_p3;
wire [0:0] tmp_2602_fu_33407_p3;
wire [0:0] tmp_787_fu_33402_p2;
wire [0:0] tmp_785_fu_33375_p2;
wire [0:0] tmp_783_fu_33348_p2;
wire [0:0] tmp_2584_fu_33116_p3;
wire [5:0] p_Result_1290_2_4_5_fu_33259_p7;
wire [5:0] p_Result_1293_2_4_5_fu_33288_p7;
wire [3:0] r_V_177_2_4_fu_33334_p4;
wire [3:0] bt_ci_V58_3_fu_33014_p4;
wire [3:0] r_V_177_2_4_2_fu_33359_p3;
wire [3:0] bt_ci_V58171_3_fu_33056_p3;
wire [3:0] r_V_177_2_4_3_fu_33386_p3;
wire [3:0] bt_ci_V58172_3_fu_33100_p3;
wire [4:0] p_Result_1296_2_4_4_fu_33415_p6;
wire [5:0] bt_sign_ph_V48_4_fu_33555_p3;
wire [0:0] tmp_2604_fu_33626_p1;
wire [5:0] bt_sign_th_V50_4_fu_33563_p3;
wire [0:0] tmp_2605_fu_33635_p1;
wire [0:0] tmp_2606_fu_33644_p3;
wire [0:0] tmp_2607_fu_33657_p3;
wire [0:0] tmp_2608_fu_33670_p3;
wire [0:0] tmp_2609_fu_33683_p3;
wire [0:0] tmp_2610_fu_33696_p3;
wire [0:0] tmp_2611_fu_33709_p3;
wire [0:0] tmp_2612_fu_33722_p3;
wire [0:0] tmp_2613_fu_33735_p3;
wire [0:0] tmp_2614_fu_33748_p3;
wire [0:0] tmp_798_fu_33756_p2;
wire [0:0] tmp_796_fu_33730_p2;
wire [0:0] tmp_794_fu_33704_p2;
wire [0:0] tmp_792_fu_33678_p2;
wire [0:0] tmp_790_fu_33652_p2;
wire [0:0] tmp_788_fu_33630_p2;
wire [0:0] tmp_2615_fu_33777_p3;
wire [0:0] tmp_799_fu_33785_p2;
wire [0:0] tmp_797_fu_33743_p2;
wire [0:0] tmp_795_fu_33717_p2;
wire [0:0] tmp_793_fu_33691_p2;
wire [0:0] tmp_791_fu_33665_p2;
wire [0:0] tmp_789_fu_33639_p2;
wire [3:0] bt_ci_V58_4_fu_33586_p3;
wire [1:0] tmp_2616_fu_33806_p1;
wire [1:0] tmp_801_fu_33816_p4;
wire [1:0] tmp_800_fu_33810_p2;
wire [4:0] bt_si_V60_4_fu_33610_p3;
wire [0:0] tmp_2617_fu_33834_p1;
wire [3:0] bt_ci_V58171_4_fu_33594_p3;
wire [2:0] tmp_2618_fu_33843_p1;
wire [0:0] tmp_2619_fu_33853_p3;
wire [2:0] tmp_803_fu_33847_p2;
wire [0:0] tmp_2620_fu_33869_p3;
wire [0:0] tmp_2621_fu_33882_p3;
wire [0:0] tmp_2622_fu_33895_p3;
wire [0:0] tmp_805_fu_33890_p2;
wire [0:0] tmp_804_fu_33877_p2;
wire [0:0] tmp_802_fu_33838_p2;
wire [0:0] tmp_2603_fu_33618_p3;
wire [5:0] p_Result_1290_2_5_5_fu_33761_p7;
wire [5:0] p_Result_1293_2_5_5_fu_33790_p7;
wire [3:0] r_V_177_2_5_fu_33826_p3;
wire [3:0] r_V_177_2_5_2_fu_33861_p3;
wire [4:0] p_Result_1296_2_5_4_fu_33903_p6;
wire [5:0] bt_sign_ph_V48_5_fu_34043_p3;
wire [0:0] tmp_2624_fu_34106_p1;
wire [5:0] bt_sign_th_V50_5_fu_34051_p3;
wire [0:0] tmp_2625_fu_34115_p1;
wire [0:0] tmp_2626_fu_34124_p3;
wire [0:0] tmp_2627_fu_34137_p3;
wire [0:0] tmp_2628_fu_34150_p3;
wire [0:0] tmp_2629_fu_34163_p3;
wire [0:0] tmp_2630_fu_34176_p3;
wire [0:0] tmp_2631_fu_34189_p3;
wire [0:0] tmp_2632_fu_34202_p3;
wire [0:0] tmp_2633_fu_34215_p3;
wire [0:0] tmp_2634_fu_34228_p3;
wire [0:0] tmp_816_fu_34236_p2;
wire [0:0] tmp_814_fu_34210_p2;
wire [0:0] tmp_812_fu_34184_p2;
wire [0:0] tmp_810_fu_34158_p2;
wire [0:0] tmp_808_fu_34132_p2;
wire [0:0] tmp_806_fu_34110_p2;
wire [0:0] tmp_2635_fu_34257_p3;
wire [0:0] tmp_817_fu_34265_p2;
wire [0:0] tmp_815_fu_34223_p2;
wire [0:0] tmp_813_fu_34197_p2;
wire [0:0] tmp_811_fu_34171_p2;
wire [0:0] tmp_809_fu_34145_p2;
wire [0:0] tmp_807_fu_34119_p2;
wire [4:0] bt_si_V60_5_fu_34090_p3;
wire [0:0] tmp_2636_fu_34286_p1;
wire [0:0] tmp_2637_fu_34295_p3;
wire [0:0] tmp_2638_fu_34308_p3;
wire [0:0] tmp_2639_fu_34321_p3;
wire [0:0] tmp_820_fu_34316_p2;
wire [0:0] tmp_819_fu_34303_p2;
wire [0:0] tmp_818_fu_34290_p2;
wire [0:0] tmp_2623_fu_34098_p3;
wire [5:0] p_Result_1290_2_6_5_fu_34241_p7;
wire [5:0] p_Result_1293_2_6_5_fu_34270_p7;
wire [4:0] p_Result_1296_2_6_4_fu_34329_p6;
wire [5:0] bt_sign_ph_V48_6_fu_34469_p3;
wire [0:0] tmp_2641_fu_34524_p1;
wire [5:0] bt_sign_th_V50_6_fu_34477_p3;
wire [0:0] tmp_2642_fu_34533_p1;
wire [0:0] tmp_2643_fu_34542_p3;
wire [0:0] tmp_2644_fu_34555_p3;
wire [0:0] tmp_2645_fu_34568_p3;
wire [0:0] tmp_2646_fu_34581_p3;
wire [0:0] tmp_2647_fu_34594_p3;
wire [0:0] tmp_2648_fu_34607_p3;
wire [0:0] tmp_2649_fu_34620_p3;
wire [0:0] tmp_2650_fu_34633_p3;
wire [0:0] tmp_2651_fu_34646_p3;
wire [0:0] tmp_831_fu_34654_p2;
wire [0:0] tmp_829_fu_34628_p2;
wire [0:0] tmp_827_fu_34602_p2;
wire [0:0] tmp_825_fu_34576_p2;
wire [0:0] tmp_823_fu_34550_p2;
wire [0:0] tmp_821_fu_34528_p2;
wire [0:0] tmp_2652_fu_34675_p3;
wire [0:0] tmp_832_fu_34683_p2;
wire [0:0] tmp_830_fu_34641_p2;
wire [0:0] tmp_828_fu_34615_p2;
wire [0:0] tmp_826_fu_34589_p2;
wire [0:0] tmp_824_fu_34563_p2;
wire [0:0] tmp_822_fu_34537_p2;
wire [4:0] bt_si_V60_6_fu_34508_p3;
wire [0:0] tmp_2653_fu_34704_p1;
wire [0:0] tmp_2654_fu_34713_p3;
wire [0:0] tmp_2655_fu_34726_p3;
wire [0:0] tmp_2656_fu_34739_p3;
wire [0:0] tmp_835_fu_34734_p2;
wire [0:0] tmp_834_fu_34721_p2;
wire [0:0] tmp_833_fu_34708_p2;
wire [0:0] tmp_2640_fu_34516_p3;
wire [5:0] p_Result_1290_2_7_5_fu_34659_p7;
wire [5:0] p_Result_1293_2_7_5_fu_34688_p7;
wire [2:0] tmp_2657_fu_34910_p3;
wire [2:0] r_V_177_2_6_fu_34500_p3;
wire [2:0] tmp_836_fu_34918_p2;
wire [3:0] tmp1624_fu_34924_p3;
wire [3:0] bt_ci_V58_5_fu_34074_p3;
wire [0:0] tmp_2658_fu_34946_p2;
wire [3:0] bt_ci_V58171_5_fu_34082_p3;
wire [2:0] tmp_2659_fu_34960_p1;
wire [2:0] tmp1625_fu_34952_p3;
wire [0:0] tmp_2661_fu_34970_p3;
wire [2:0] tmp_2660_fu_34964_p2;
wire [0:0] tmp_2662_fu_34986_p2;
wire [3:0] bt_ci_V58172_4_fu_33602_p3;
wire [2:0] tmp_2663_fu_35000_p1;
wire [2:0] r_V_177_2_7_2_fu_34938_p3;
wire [2:0] tmp_2664_fu_35004_p2;
wire [2:0] tmp1626_fu_34992_p3;
wire [0:0] tmp_2665_fu_35010_p3;
wire [2:0] tmp_2666_fu_35018_p2;
wire [4:0] p_Result_1296_2_7_4_fu_34747_p6;
wire [5:0] bt_sign_ph_V48_7_fu_34887_p3;
wire [0:0] tmp_2668_fu_35048_p1;
wire [5:0] bt_sign_th_V50_7_fu_34895_p3;
wire [0:0] tmp_2669_fu_35057_p1;
wire [0:0] tmp_2670_fu_35066_p3;
wire [0:0] tmp_2671_fu_35079_p3;
wire [0:0] tmp_2672_fu_35092_p3;
wire [0:0] tmp_2673_fu_35105_p3;
wire [0:0] tmp_2674_fu_35118_p3;
wire [0:0] tmp_2675_fu_35131_p3;
wire [0:0] tmp_2676_fu_35144_p3;
wire [0:0] tmp_2677_fu_35157_p3;
wire [0:0] tmp_2678_fu_35170_p3;
wire [0:0] tmp_847_fu_35178_p2;
wire [0:0] tmp_845_fu_35152_p2;
wire [0:0] tmp_843_fu_35126_p2;
wire [0:0] tmp_841_fu_35100_p2;
wire [0:0] tmp_839_fu_35074_p2;
wire [0:0] tmp_837_fu_35052_p2;
wire [0:0] tmp_2679_fu_35199_p3;
wire [0:0] tmp_848_fu_35207_p2;
wire [0:0] tmp_846_fu_35165_p2;
wire [0:0] tmp_844_fu_35139_p2;
wire [0:0] tmp_842_fu_35113_p2;
wire [0:0] tmp_840_fu_35087_p2;
wire [0:0] tmp_838_fu_35061_p2;
wire [3:0] bt_ci_V58_7_fu_34932_p2;
wire [1:0] tmp_2680_fu_35228_p1;
wire [1:0] tmp_850_fu_35238_p4;
wire [1:0] tmp_849_fu_35232_p2;
wire [4:0] bt_si_V60_7_fu_35032_p3;
wire [0:0] tmp_2681_fu_35256_p1;
wire [2:0] tmp_852_fu_35265_p2;
wire [0:0] tmp_2682_fu_35279_p3;
wire [2:0] tmp_854_fu_35292_p2;
wire [0:0] tmp_2683_fu_35306_p3;
wire [0:0] tmp_2684_fu_35319_p3;
wire [0:0] tmp_855_fu_35314_p2;
wire [0:0] tmp_853_fu_35287_p2;
wire [0:0] tmp_851_fu_35260_p2;
wire [0:0] tmp_2667_fu_35040_p3;
wire [5:0] p_Result_1290_2_8_5_fu_35183_p7;
wire [5:0] p_Result_1293_2_8_5_fu_35212_p7;
wire [3:0] r_V_177_2_8_fu_35248_p3;
wire [3:0] r_V_177_2_8_2_fu_35271_p3;
wire [3:0] bt_ci_V58171_7_fu_34978_p3;
wire [3:0] r_V_177_2_8_3_fu_35298_p3;
wire [3:0] bt_ci_V58172_7_fu_35024_p3;
wire [4:0] p_Result_1296_2_8_4_fu_35327_p6;
wire [5:0] bt_sign_ph_V48_8_fu_35467_p3;
wire [0:0] tmp_2686_fu_35530_p1;
wire [5:0] bt_sign_th_V50_8_fu_35475_p3;
wire [0:0] tmp_2687_fu_35539_p1;
wire [0:0] tmp_2688_fu_35548_p3;
wire [0:0] tmp_2689_fu_35561_p3;
wire [0:0] tmp_2690_fu_35574_p3;
wire [0:0] tmp_2691_fu_35587_p3;
wire [0:0] tmp_2692_fu_35600_p3;
wire [0:0] tmp_2693_fu_35613_p3;
wire [0:0] tmp_2694_fu_35626_p3;
wire [0:0] tmp_2695_fu_35639_p3;
wire [0:0] tmp_2696_fu_35652_p3;
wire [0:0] tmp_866_fu_35660_p2;
wire [0:0] tmp_864_fu_35634_p2;
wire [0:0] tmp_862_fu_35608_p2;
wire [0:0] tmp_860_fu_35582_p2;
wire [0:0] tmp_858_fu_35556_p2;
wire [0:0] tmp_856_fu_35534_p2;
wire [0:0] tmp_2697_fu_35681_p3;
wire [0:0] tmp_867_fu_35689_p2;
wire [0:0] tmp_865_fu_35647_p2;
wire [0:0] tmp_863_fu_35621_p2;
wire [0:0] tmp_861_fu_35595_p2;
wire [0:0] tmp_859_fu_35569_p2;
wire [0:0] tmp_857_fu_35543_p2;
wire [3:0] bt_ci_V58_8_fu_35490_p3;
wire [1:0] tmp_2698_fu_35710_p1;
wire [1:0] tmp_869_fu_35720_p4;
wire [1:0] tmp_868_fu_35714_p2;
wire [4:0] bt_si_V60_8_fu_35514_p3;
wire [0:0] tmp_2699_fu_35738_p1;
wire [3:0] bt_ci_V58171_8_fu_35498_p3;
wire [2:0] tmp_2700_fu_35747_p1;
wire [0:0] tmp_2701_fu_35757_p3;
wire [2:0] tmp_871_fu_35751_p2;
wire [0:0] tmp_2702_fu_35773_p3;
wire [0:0] tmp_2703_fu_35786_p3;
wire [0:0] tmp_2704_fu_35799_p3;
wire [0:0] tmp_873_fu_35794_p2;
wire [0:0] tmp_872_fu_35781_p2;
wire [0:0] tmp_870_fu_35742_p2;
wire [0:0] tmp_2685_fu_35522_p3;
wire [5:0] p_Result_1290_2_9_5_fu_35665_p7;
wire [5:0] p_Result_1293_2_9_5_fu_35694_p7;
wire [3:0] r_V_177_2_9_fu_35730_p3;
wire [3:0] r_V_177_2_9_2_fu_35765_p3;
wire [4:0] p_Result_1296_2_9_4_fu_35807_p6;
wire [5:0] bt_sign_ph_V48_9_fu_35947_p3;
wire [0:0] tmp_2706_fu_36018_p1;
wire [5:0] bt_sign_th_V50_9_fu_35955_p3;
wire [0:0] tmp_2707_fu_36027_p1;
wire [0:0] tmp_2708_fu_36036_p3;
wire [0:0] tmp_2709_fu_36049_p3;
wire [0:0] tmp_2710_fu_36062_p3;
wire [0:0] tmp_2711_fu_36075_p3;
wire [0:0] tmp_2712_fu_36088_p3;
wire [0:0] tmp_2713_fu_36101_p3;
wire [0:0] tmp_2714_fu_36114_p3;
wire [0:0] tmp_2715_fu_36127_p3;
wire [0:0] tmp_2716_fu_36140_p3;
wire [0:0] tmp_884_fu_36148_p2;
wire [0:0] tmp_882_fu_36122_p2;
wire [0:0] tmp_880_fu_36096_p2;
wire [0:0] tmp_878_fu_36070_p2;
wire [0:0] tmp_876_fu_36044_p2;
wire [0:0] tmp_874_fu_36022_p2;
wire [0:0] tmp_2717_fu_36169_p3;
wire [0:0] tmp_885_fu_36177_p2;
wire [0:0] tmp_883_fu_36135_p2;
wire [0:0] tmp_881_fu_36109_p2;
wire [0:0] tmp_879_fu_36083_p2;
wire [0:0] tmp_877_fu_36057_p2;
wire [0:0] tmp_875_fu_36031_p2;
wire [4:0] bt_si_V60_9_fu_36002_p3;
wire [0:0] tmp_2718_fu_36198_p1;
wire [0:0] tmp_2719_fu_36207_p3;
wire [0:0] tmp_2720_fu_36220_p3;
wire [0:0] tmp_2721_fu_36233_p3;
wire [0:0] tmp_888_fu_36228_p2;
wire [0:0] tmp_887_fu_36215_p2;
wire [0:0] tmp_886_fu_36202_p2;
wire [0:0] tmp_2705_fu_36010_p3;
wire [5:0] p_Result_1290_2_10_5_fu_36153_p7;
wire [5:0] p_Result_1293_2_10_5_fu_36182_p7;
wire [4:0] p_Result_1296_2_10_4_fu_36241_p6;
wire [5:0] bt_sign_ph_V48_s_fu_36381_p3;
wire [0:0] tmp_2723_fu_36428_p1;
wire [5:0] bt_sign_th_V50_s_fu_36389_p3;
wire [0:0] tmp_2724_fu_36437_p1;
wire [0:0] tmp_2725_fu_36446_p3;
wire [0:0] tmp_2726_fu_36459_p3;
wire [0:0] tmp_2727_fu_36472_p3;
wire [0:0] tmp_2728_fu_36485_p3;
wire [0:0] tmp_2729_fu_36498_p3;
wire [0:0] tmp_2730_fu_36511_p3;
wire [0:0] tmp_2731_fu_36524_p3;
wire [0:0] tmp_2732_fu_36537_p3;
wire [0:0] tmp_2733_fu_36550_p3;
wire [0:0] tmp_899_fu_36558_p2;
wire [0:0] tmp_897_fu_36532_p2;
wire [0:0] tmp_895_fu_36506_p2;
wire [0:0] tmp_893_fu_36480_p2;
wire [0:0] tmp_891_fu_36454_p2;
wire [0:0] tmp_889_fu_36432_p2;
wire [0:0] tmp_2734_fu_36579_p3;
wire [0:0] tmp_900_fu_36587_p2;
wire [0:0] tmp_898_fu_36545_p2;
wire [0:0] tmp_896_fu_36519_p2;
wire [0:0] tmp_894_fu_36493_p2;
wire [0:0] tmp_892_fu_36467_p2;
wire [0:0] tmp_890_fu_36441_p2;
wire [4:0] bt_si_V60_s_fu_36412_p3;
wire [0:0] tmp_2735_fu_36608_p1;
wire [0:0] tmp_2736_fu_36617_p3;
wire [0:0] tmp_2737_fu_36630_p3;
wire [0:0] tmp_2738_fu_36643_p3;
wire [0:0] tmp_903_fu_36638_p2;
wire [0:0] tmp_902_fu_36625_p2;
wire [0:0] tmp_901_fu_36612_p2;
wire [0:0] tmp_2722_fu_36420_p3;
wire [11:0] r_V_170_2_1_fu_31993_p3;
wire [11:0] r_V_170_2_2_fu_32409_p3;
wire [11:0] tmp1628_fu_36672_p2;
wire [11:0] bt_phi_V2_fu_31593_p3;
wire [11:0] r_V_170_2_4_fu_33429_p3;
wire [11:0] r_V_170_2_5_fu_33917_p3;
wire [11:0] tmp1630_fu_36684_p2;
wire [11:0] r_V_170_2_3_fu_32819_p3;
wire [11:0] tmp1631_fu_36690_p2;
wire [11:0] tmp1629_fu_36678_p2;
wire [11:0] r_V_170_2_7_fu_34761_p3;
wire [11:0] r_V_170_2_8_fu_35341_p3;
wire [11:0] tmp1633_fu_36702_p2;
wire [11:0] r_V_170_2_6_fu_34343_p3;
wire [11:0] r_V_170_2_s_fu_36255_p3;
wire [11:0] r_V_170_2_10_fu_36665_p3;
wire [11:0] tmp1635_fu_36714_p2;
wire [11:0] r_V_170_2_9_fu_35821_p3;
wire [11:0] tmp1636_fu_36720_p2;
wire [11:0] tmp1634_fu_36708_p2;
wire [11:0] tmp1637_fu_36726_p2;
wire [11:0] tmp1632_fu_36696_p2;
wire [6:0] r_V_171_2_1_fu_32000_p3;
wire [6:0] r_V_171_2_2_fu_32416_p3;
wire [6:0] tmp1638_fu_36745_p2;
wire [6:0] bt_theta_V2_fu_31600_p3;
wire [6:0] r_V_171_2_4_fu_33436_p3;
wire [6:0] r_V_171_2_5_fu_33924_p3;
wire [6:0] tmp1640_fu_36757_p2;
wire [6:0] r_V_171_2_3_fu_32826_p3;
wire [6:0] tmp1641_fu_36763_p2;
wire [6:0] tmp1639_fu_36751_p2;
wire [6:0] r_V_171_2_7_fu_34768_p3;
wire [6:0] r_V_171_2_8_fu_35348_p3;
wire [6:0] tmp1643_fu_36775_p2;
wire [6:0] r_V_171_2_6_fu_34350_p3;
wire [6:0] r_V_171_2_s_fu_36262_p3;
wire [6:0] r_V_171_2_10_fu_36738_p3;
wire [6:0] tmp1645_fu_36787_p2;
wire [6:0] r_V_171_2_9_fu_35828_p3;
wire [6:0] tmp1646_fu_36793_p2;
wire [6:0] tmp1644_fu_36781_p2;
wire [6:0] tmp1647_fu_36799_p2;
wire [6:0] tmp1642_fu_36769_p2;
wire [3:0] r_V_172_2_1_fu_32007_p3;
wire [3:0] r_V_172_2_2_fu_32423_p3;
wire [3:0] tmp1648_fu_36818_p2;
wire [3:0] bt_cpattern_V8_fu_31607_p3;
wire [3:0] r_V_172_2_4_fu_33443_p3;
wire [3:0] r_V_172_2_5_fu_33931_p3;
wire [3:0] tmp1650_fu_36830_p2;
wire [3:0] r_V_172_2_3_fu_32833_p3;
wire [3:0] tmp1651_fu_36836_p2;
wire [3:0] tmp1649_fu_36824_p2;
wire [3:0] r_V_172_2_7_fu_34775_p3;
wire [3:0] r_V_172_2_8_fu_35355_p3;
wire [3:0] tmp1653_fu_36848_p2;
wire [3:0] r_V_172_2_6_fu_34357_p3;
wire [3:0] r_V_172_2_s_fu_36269_p3;
wire [3:0] r_V_172_2_10_fu_36811_p3;
wire [3:0] tmp1655_fu_36860_p2;
wire [3:0] r_V_172_2_9_fu_35835_p3;
wire [3:0] tmp1656_fu_36866_p2;
wire [3:0] tmp1654_fu_36854_p2;
wire [3:0] tmp1657_fu_36872_p2;
wire [3:0] tmp1652_fu_36842_p2;
wire [3:0] r_V_172_2_1_1_fu_32014_p3;
wire [3:0] r_V_172_2_2_1_fu_32430_p3;
wire [3:0] tmp1658_fu_36891_p2;
wire [3:0] bt_cpattern_V9_fu_31614_p3;
wire [3:0] r_V_172_2_4_1_fu_33450_p3;
wire [3:0] r_V_172_2_5_1_fu_33938_p3;
wire [3:0] tmp1660_fu_36903_p2;
wire [3:0] r_V_172_2_3_1_fu_32840_p3;
wire [3:0] tmp1661_fu_36909_p2;
wire [3:0] tmp1659_fu_36897_p2;
wire [3:0] r_V_172_2_7_1_fu_34782_p3;
wire [3:0] r_V_172_2_8_1_fu_35362_p3;
wire [3:0] tmp1663_fu_36921_p2;
wire [3:0] r_V_172_2_6_1_fu_34364_p3;
wire [3:0] r_V_172_2_10_1_fu_36276_p3;
wire [3:0] r_V_172_2_11_1_fu_36884_p3;
wire [3:0] tmp1665_fu_36933_p2;
wire [3:0] r_V_172_2_9_1_fu_35842_p3;
wire [3:0] tmp1666_fu_36939_p2;
wire [3:0] tmp1664_fu_36927_p2;
wire [3:0] tmp1667_fu_36945_p2;
wire [3:0] tmp1662_fu_36915_p2;
wire [3:0] r_V_172_2_1_2_fu_32021_p3;
wire [3:0] r_V_172_2_2_2_fu_32437_p3;
wire [3:0] tmp1668_fu_36964_p2;
wire [3:0] bt_cpattern_V10_fu_31621_p3;
wire [3:0] r_V_172_2_4_2_fu_33457_p3;
wire [3:0] r_V_172_2_5_2_fu_33945_p3;
wire [3:0] tmp1670_fu_36976_p2;
wire [3:0] r_V_172_2_3_2_fu_32847_p3;
wire [3:0] tmp1671_fu_36982_p2;
wire [3:0] tmp1669_fu_36970_p2;
wire [3:0] r_V_172_2_7_2_fu_34789_p3;
wire [3:0] r_V_172_2_8_2_fu_35369_p3;
wire [3:0] tmp1673_fu_36994_p2;
wire [3:0] r_V_172_2_6_2_fu_34371_p3;
wire [3:0] r_V_172_2_10_2_fu_36283_p3;
wire [3:0] r_V_172_2_11_2_fu_36957_p3;
wire [3:0] tmp1675_fu_37006_p2;
wire [3:0] r_V_172_2_9_2_fu_35849_p3;
wire [3:0] tmp1676_fu_37012_p2;
wire [3:0] tmp1674_fu_37000_p2;
wire [3:0] tmp1677_fu_37018_p2;
wire [3:0] tmp1672_fu_36988_p2;
wire [3:0] r_V_172_2_1_3_fu_32028_p3;
wire [3:0] r_V_172_2_2_3_fu_32444_p3;
wire [3:0] tmp1678_fu_37037_p2;
wire [3:0] bt_cpattern_V11_fu_31628_p3;
wire [3:0] r_V_172_2_4_3_fu_33464_p3;
wire [3:0] r_V_172_2_5_3_fu_33952_p3;
wire [3:0] tmp1680_fu_37049_p2;
wire [3:0] r_V_172_2_3_3_fu_32854_p3;
wire [3:0] tmp1681_fu_37055_p2;
wire [3:0] tmp1679_fu_37043_p2;
wire [3:0] r_V_172_2_7_3_fu_34796_p3;
wire [3:0] r_V_172_2_8_3_fu_35376_p3;
wire [3:0] tmp1683_fu_37067_p2;
wire [3:0] r_V_172_2_6_3_fu_34378_p3;
wire [3:0] r_V_172_2_10_3_fu_36290_p3;
wire [3:0] r_V_172_2_11_3_fu_37030_p3;
wire [3:0] tmp1685_fu_37079_p2;
wire [3:0] r_V_172_2_9_3_fu_35856_p3;
wire [3:0] tmp1686_fu_37085_p2;
wire [3:0] tmp1684_fu_37073_p2;
wire [3:0] tmp1687_fu_37091_p2;
wire [3:0] tmp1682_fu_37061_p2;
wire [11:0] r_V_173_2_1_fu_32035_p3;
wire [11:0] r_V_173_2_2_fu_32451_p3;
wire [11:0] tmp1688_fu_37110_p2;
wire [11:0] bt_delta_ph_V12_fu_31635_p3;
wire [11:0] r_V_173_2_4_fu_33471_p3;
wire [11:0] r_V_173_2_5_fu_33959_p3;
wire [11:0] tmp1690_fu_37122_p2;
wire [11:0] r_V_173_2_3_fu_32861_p3;
wire [11:0] tmp1691_fu_37128_p2;
wire [11:0] tmp1689_fu_37116_p2;
wire [11:0] r_V_173_2_7_fu_34803_p3;
wire [11:0] r_V_173_2_8_fu_35383_p3;
wire [11:0] tmp1693_fu_37140_p2;
wire [11:0] r_V_173_2_6_fu_34385_p3;
wire [11:0] r_V_173_2_s_fu_36297_p3;
wire [11:0] r_V_173_2_10_fu_37103_p3;
wire [11:0] tmp1695_fu_37152_p2;
wire [11:0] r_V_173_2_9_fu_35863_p3;
wire [11:0] tmp1696_fu_37158_p2;
wire [11:0] tmp1694_fu_37146_p2;
wire [11:0] tmp1697_fu_37164_p2;
wire [11:0] tmp1692_fu_37134_p2;
wire [11:0] r_V_173_2_1_1_fu_32042_p3;
wire [11:0] r_V_173_2_2_1_fu_32458_p3;
wire [11:0] tmp1698_fu_37183_p2;
wire [11:0] bt_delta_ph_V13_fu_31642_p3;
wire [11:0] r_V_173_2_4_1_fu_33478_p3;
wire [11:0] r_V_173_2_5_1_fu_33966_p3;
wire [11:0] tmp1700_fu_37195_p2;
wire [11:0] r_V_173_2_3_1_fu_32868_p3;
wire [11:0] tmp1701_fu_37201_p2;
wire [11:0] tmp1699_fu_37189_p2;
wire [11:0] r_V_173_2_7_1_fu_34810_p3;
wire [11:0] r_V_173_2_8_1_fu_35390_p3;
wire [11:0] tmp1703_fu_37213_p2;
wire [11:0] r_V_173_2_6_1_fu_34392_p3;
wire [11:0] r_V_173_2_10_1_fu_36304_p3;
wire [11:0] r_V_173_2_11_1_fu_37176_p3;
wire [11:0] tmp1705_fu_37225_p2;
wire [11:0] r_V_173_2_9_1_fu_35870_p3;
wire [11:0] tmp1706_fu_37231_p2;
wire [11:0] tmp1704_fu_37219_p2;
wire [11:0] tmp1707_fu_37237_p2;
wire [11:0] tmp1702_fu_37207_p2;
wire [11:0] r_V_173_2_1_2_fu_32049_p3;
wire [11:0] r_V_173_2_2_2_fu_32465_p3;
wire [11:0] tmp1708_fu_37256_p2;
wire [11:0] bt_delta_ph_V14_fu_31649_p3;
wire [11:0] r_V_173_2_4_2_fu_33485_p3;
wire [11:0] r_V_173_2_5_2_fu_33973_p3;
wire [11:0] tmp1710_fu_37268_p2;
wire [11:0] r_V_173_2_3_2_fu_32875_p3;
wire [11:0] tmp1711_fu_37274_p2;
wire [11:0] tmp1709_fu_37262_p2;
wire [11:0] r_V_173_2_7_2_fu_34817_p3;
wire [11:0] r_V_173_2_8_2_fu_35397_p3;
wire [11:0] tmp1713_fu_37286_p2;
wire [11:0] r_V_173_2_6_2_fu_34399_p3;
wire [11:0] r_V_173_2_10_2_fu_36311_p3;
wire [11:0] r_V_173_2_11_2_fu_37249_p3;
wire [11:0] tmp1715_fu_37298_p2;
wire [11:0] r_V_173_2_9_2_fu_35877_p3;
wire [11:0] tmp1716_fu_37304_p2;
wire [11:0] tmp1714_fu_37292_p2;
wire [11:0] tmp1717_fu_37310_p2;
wire [11:0] tmp1712_fu_37280_p2;
wire [11:0] r_V_173_2_1_3_fu_32056_p3;
wire [11:0] r_V_173_2_2_3_fu_32472_p3;
wire [11:0] tmp1718_fu_37329_p2;
wire [11:0] bt_delta_ph_V15_fu_31656_p3;
wire [11:0] r_V_173_2_4_3_fu_33492_p3;
wire [11:0] r_V_173_2_5_3_fu_33980_p3;
wire [11:0] tmp1720_fu_37341_p2;
wire [11:0] r_V_173_2_3_3_fu_32882_p3;
wire [11:0] tmp1721_fu_37347_p2;
wire [11:0] tmp1719_fu_37335_p2;
wire [11:0] r_V_173_2_7_3_fu_34824_p3;
wire [11:0] r_V_173_2_8_3_fu_35404_p3;
wire [11:0] tmp1723_fu_37359_p2;
wire [11:0] r_V_173_2_6_3_fu_34406_p3;
wire [11:0] r_V_173_2_10_3_fu_36318_p3;
wire [11:0] r_V_173_2_11_3_fu_37322_p3;
wire [11:0] tmp1725_fu_37371_p2;
wire [11:0] r_V_173_2_9_3_fu_35884_p3;
wire [11:0] tmp1726_fu_37377_p2;
wire [11:0] tmp1724_fu_37365_p2;
wire [11:0] tmp1727_fu_37383_p2;
wire [11:0] tmp1722_fu_37353_p2;
wire [11:0] r_V_173_2_1_4_fu_32063_p3;
wire [11:0] r_V_173_2_2_4_fu_32479_p3;
wire [11:0] tmp1728_fu_37402_p2;
wire [11:0] bt_delta_ph_V16_fu_31663_p3;
wire [11:0] r_V_173_2_4_4_fu_33499_p3;
wire [11:0] r_V_173_2_5_4_fu_33987_p3;
wire [11:0] tmp1730_fu_37414_p2;
wire [11:0] r_V_173_2_3_4_fu_32889_p3;
wire [11:0] tmp1731_fu_37420_p2;
wire [11:0] tmp1729_fu_37408_p2;
wire [11:0] r_V_173_2_7_4_fu_34831_p3;
wire [11:0] r_V_173_2_8_4_fu_35411_p3;
wire [11:0] tmp1733_fu_37432_p2;
wire [11:0] r_V_173_2_6_4_fu_34413_p3;
wire [11:0] r_V_173_2_10_4_fu_36325_p3;
wire [11:0] r_V_173_2_11_4_fu_37395_p3;
wire [11:0] tmp1735_fu_37444_p2;
wire [11:0] r_V_173_2_9_4_fu_35891_p3;
wire [11:0] tmp1736_fu_37450_p2;
wire [11:0] tmp1734_fu_37438_p2;
wire [11:0] tmp1737_fu_37456_p2;
wire [11:0] tmp1732_fu_37426_p2;
wire [11:0] r_V_173_2_1_5_fu_32070_p3;
wire [11:0] r_V_173_2_2_5_fu_32486_p3;
wire [11:0] tmp1738_fu_37475_p2;
wire [11:0] bt_delta_ph_V17_fu_31670_p3;
wire [11:0] r_V_173_2_4_5_fu_33506_p3;
wire [11:0] r_V_173_2_5_5_fu_33994_p3;
wire [11:0] tmp1740_fu_37487_p2;
wire [11:0] r_V_173_2_3_5_fu_32896_p3;
wire [11:0] tmp1741_fu_37493_p2;
wire [11:0] tmp1739_fu_37481_p2;
wire [11:0] r_V_173_2_7_5_fu_34838_p3;
wire [11:0] r_V_173_2_8_5_fu_35418_p3;
wire [11:0] tmp1743_fu_37505_p2;
wire [11:0] r_V_173_2_6_5_fu_34420_p3;
wire [11:0] r_V_173_2_10_5_fu_36332_p3;
wire [11:0] r_V_173_2_11_5_fu_37468_p3;
wire [11:0] tmp1745_fu_37517_p2;
wire [11:0] r_V_173_2_9_5_fu_35898_p3;
wire [11:0] tmp1746_fu_37523_p2;
wire [11:0] tmp1744_fu_37511_p2;
wire [11:0] tmp1747_fu_37529_p2;
wire [11:0] tmp1742_fu_37499_p2;
wire [6:0] r_V_174_2_1_fu_32077_p3;
wire [6:0] r_V_174_2_2_fu_32493_p3;
wire [6:0] tmp1748_fu_37548_p2;
wire [6:0] bt_delta_th_V12_fu_31677_p3;
wire [6:0] r_V_174_2_4_fu_33513_p3;
wire [6:0] r_V_174_2_5_fu_34001_p3;
wire [6:0] tmp1750_fu_37560_p2;
wire [6:0] r_V_174_2_3_fu_32903_p3;
wire [6:0] tmp1751_fu_37566_p2;
wire [6:0] tmp1749_fu_37554_p2;
wire [6:0] r_V_174_2_7_fu_34845_p3;
wire [6:0] r_V_174_2_8_fu_35425_p3;
wire [6:0] tmp1753_fu_37578_p2;
wire [6:0] r_V_174_2_6_fu_34427_p3;
wire [6:0] r_V_174_2_s_fu_36339_p3;
wire [6:0] r_V_174_2_10_fu_37541_p3;
wire [6:0] tmp1755_fu_37590_p2;
wire [6:0] r_V_174_2_9_fu_35905_p3;
wire [6:0] tmp1756_fu_37596_p2;
wire [6:0] tmp1754_fu_37584_p2;
wire [6:0] tmp1757_fu_37602_p2;
wire [6:0] tmp1752_fu_37572_p2;
wire [6:0] r_V_174_2_1_1_fu_32084_p3;
wire [6:0] r_V_174_2_2_1_fu_32500_p3;
wire [6:0] tmp1758_fu_37621_p2;
wire [6:0] bt_delta_th_V13_fu_31684_p3;
wire [6:0] r_V_174_2_4_1_fu_33520_p3;
wire [6:0] r_V_174_2_5_1_fu_34008_p3;
wire [6:0] tmp1760_fu_37633_p2;
wire [6:0] r_V_174_2_3_1_fu_32910_p3;
wire [6:0] tmp1761_fu_37639_p2;
wire [6:0] tmp1759_fu_37627_p2;
wire [6:0] r_V_174_2_7_1_fu_34852_p3;
wire [6:0] r_V_174_2_8_1_fu_35432_p3;
wire [6:0] tmp1763_fu_37651_p2;
wire [6:0] r_V_174_2_6_1_fu_34434_p3;
wire [6:0] r_V_174_2_10_1_fu_36346_p3;
wire [6:0] r_V_174_2_11_1_fu_37614_p3;
wire [6:0] tmp1765_fu_37663_p2;
wire [6:0] r_V_174_2_9_1_fu_35912_p3;
wire [6:0] tmp1766_fu_37669_p2;
wire [6:0] tmp1764_fu_37657_p2;
wire [6:0] tmp1767_fu_37675_p2;
wire [6:0] tmp1762_fu_37645_p2;
wire [6:0] r_V_174_2_1_2_fu_32091_p3;
wire [6:0] r_V_174_2_2_2_fu_32507_p3;
wire [6:0] tmp1768_fu_37694_p2;
wire [6:0] bt_delta_th_V14_fu_31691_p3;
wire [6:0] r_V_174_2_4_2_fu_33527_p3;
wire [6:0] r_V_174_2_5_2_fu_34015_p3;
wire [6:0] tmp1770_fu_37706_p2;
wire [6:0] r_V_174_2_3_2_fu_32917_p3;
wire [6:0] tmp1771_fu_37712_p2;
wire [6:0] tmp1769_fu_37700_p2;
wire [6:0] r_V_174_2_7_2_fu_34859_p3;
wire [6:0] r_V_174_2_8_2_fu_35439_p3;
wire [6:0] tmp1773_fu_37724_p2;
wire [6:0] r_V_174_2_6_2_fu_34441_p3;
wire [6:0] r_V_174_2_10_2_fu_36353_p3;
wire [6:0] r_V_174_2_11_2_fu_37687_p3;
wire [6:0] tmp1775_fu_37736_p2;
wire [6:0] r_V_174_2_9_2_fu_35919_p3;
wire [6:0] tmp1776_fu_37742_p2;
wire [6:0] tmp1774_fu_37730_p2;
wire [6:0] tmp1777_fu_37748_p2;
wire [6:0] tmp1772_fu_37718_p2;
wire [6:0] r_V_174_2_1_3_fu_32098_p3;
wire [6:0] r_V_174_2_2_3_fu_32514_p3;
wire [6:0] tmp1778_fu_37767_p2;
wire [6:0] bt_delta_th_V15_fu_31698_p3;
wire [6:0] r_V_174_2_4_3_fu_33534_p3;
wire [6:0] r_V_174_2_5_3_fu_34022_p3;
wire [6:0] tmp1780_fu_37779_p2;
wire [6:0] r_V_174_2_3_3_fu_32924_p3;
wire [6:0] tmp1781_fu_37785_p2;
wire [6:0] tmp1779_fu_37773_p2;
wire [6:0] r_V_174_2_7_3_fu_34866_p3;
wire [6:0] r_V_174_2_8_3_fu_35446_p3;
wire [6:0] tmp1783_fu_37797_p2;
wire [6:0] r_V_174_2_6_3_fu_34448_p3;
wire [6:0] r_V_174_2_10_3_fu_36360_p3;
wire [6:0] r_V_174_2_11_3_fu_37760_p3;
wire [6:0] tmp1785_fu_37809_p2;
wire [6:0] r_V_174_2_9_3_fu_35926_p3;
wire [6:0] tmp1786_fu_37815_p2;
wire [6:0] tmp1784_fu_37803_p2;
wire [6:0] tmp1787_fu_37821_p2;
wire [6:0] tmp1782_fu_37791_p2;
wire [6:0] r_V_174_2_1_4_fu_32105_p3;
wire [6:0] r_V_174_2_2_4_fu_32521_p3;
wire [6:0] tmp1788_fu_37840_p2;
wire [6:0] bt_delta_th_V16_fu_31705_p3;
wire [6:0] r_V_174_2_4_4_fu_33541_p3;
wire [6:0] r_V_174_2_5_4_fu_34029_p3;
wire [6:0] tmp1790_fu_37852_p2;
wire [6:0] r_V_174_2_3_4_fu_32931_p3;
wire [6:0] tmp1791_fu_37858_p2;
wire [6:0] tmp1789_fu_37846_p2;
wire [6:0] r_V_174_2_7_4_fu_34873_p3;
wire [6:0] r_V_174_2_8_4_fu_35453_p3;
wire [6:0] tmp1793_fu_37870_p2;
wire [6:0] r_V_174_2_6_4_fu_34455_p3;
wire [6:0] r_V_174_2_10_4_fu_36367_p3;
wire [6:0] r_V_174_2_11_4_fu_37833_p3;
wire [6:0] tmp1795_fu_37882_p2;
wire [6:0] r_V_174_2_9_4_fu_35933_p3;
wire [6:0] tmp1796_fu_37888_p2;
wire [6:0] tmp1794_fu_37876_p2;
wire [6:0] tmp1797_fu_37894_p2;
wire [6:0] tmp1792_fu_37864_p2;
wire [6:0] r_V_174_2_1_5_fu_32112_p3;
wire [6:0] r_V_174_2_2_5_fu_32528_p3;
wire [6:0] tmp1798_fu_37913_p2;
wire [6:0] bt_delta_th_V17_fu_31712_p3;
wire [6:0] r_V_174_2_4_5_fu_33548_p3;
wire [6:0] r_V_174_2_5_5_fu_34036_p3;
wire [6:0] tmp1800_fu_37925_p2;
wire [6:0] r_V_174_2_3_5_fu_32938_p3;
wire [6:0] tmp1801_fu_37931_p2;
wire [6:0] tmp1799_fu_37919_p2;
wire [6:0] r_V_174_2_7_5_fu_34880_p3;
wire [6:0] r_V_174_2_8_5_fu_35460_p3;
wire [6:0] tmp1803_fu_37943_p2;
wire [6:0] r_V_174_2_6_5_fu_34462_p3;
wire [6:0] r_V_174_2_10_5_fu_36374_p3;
wire [6:0] r_V_174_2_11_5_fu_37906_p3;
wire [6:0] tmp1805_fu_37955_p2;
wire [6:0] r_V_174_2_9_5_fu_35940_p3;
wire [6:0] tmp1806_fu_37961_p2;
wire [6:0] tmp1804_fu_37949_p2;
wire [6:0] tmp1807_fu_37967_p2;
wire [6:0] tmp1802_fu_37937_p2;
wire [5:0] p_Result_1290_2_11_5_fu_36563_p7;
wire [5:0] p_Result_1293_2_11_5_fu_36592_p7;
wire [6:0] r_V_169_2_1_fu_32135_p3;
wire [6:0] r_V_169_2_2_fu_32551_p3;
wire [6:0] tmp1808_fu_38002_p2;
wire [6:0] bt_rank_V2_fu_31733_p3;
wire [6:0] r_V_169_2_4_fu_33571_p3;
wire [6:0] r_V_169_2_5_fu_34059_p3;
wire [6:0] tmp1810_fu_38014_p2;
wire [6:0] r_V_169_2_3_fu_32961_p3;
wire [6:0] tmp1811_fu_38020_p2;
wire [6:0] tmp1809_fu_38008_p2;
wire [6:0] r_V_169_2_7_fu_34903_p3;
wire [6:0] r_V_169_2_8_fu_35483_p3;
wire [6:0] tmp1813_fu_38032_p2;
wire [6:0] r_V_169_2_6_fu_34485_p3;
wire [6:0] r_V_169_2_s_fu_36397_p3;
wire [6:0] r_V_169_2_10_fu_37995_p3;
wire [6:0] tmp1815_fu_38044_p2;
wire [6:0] r_V_169_2_9_fu_35963_p3;
wire [6:0] tmp1816_fu_38050_p2;
wire [6:0] tmp1814_fu_38038_p2;
wire [6:0] tmp1817_fu_38056_p2;
wire [6:0] tmp1812_fu_38026_p2;
wire [0:0] tmp_2739_fu_38068_p2;
wire [1:0] tmp1818_fu_38074_p3;
wire [1:0] r_V_176_2_9_fu_35970_p3;
wire [1:0] tmp1820_fu_38088_p3;
wire [1:0] r_V_176_2_5_fu_34066_p3;
wire [1:0] tmp1821_fu_38096_p2;
wire [1:0] tmp1819_fu_38082_p2;
wire [0:0] tmp_2740_fu_38108_p2;
wire [1:0] tmp1823_fu_38114_p3;
wire [1:0] r_V_176_2_1_fu_32142_p3;
wire [0:0] tmp_2741_fu_38128_p2;
wire [1:0] tmp1825_fu_38134_p3;
wire [1:0] r_V_176_2_4_fu_33578_p3;
wire [1:0] tmp1826_fu_38142_p2;
wire [1:0] tmp1824_fu_38122_p2;
wire [1:0] tmp1827_fu_38148_p2;
wire [1:0] tmp1822_fu_38102_p2;
wire [0:0] tmp_2742_fu_38160_p3;
wire [0:0] tmp_2743_fu_38168_p2;
wire [1:0] r_V_176_2_3_fu_32968_p3;
wire [0:0] tmp_2745_fu_38188_p3;
wire [0:0] tmp_2744_fu_38182_p2;
wire [1:0] tmp1831_fu_38196_p3;
wire [1:0] tmp1829_fu_38174_p3;
wire [0:0] tmp_2746_fu_38210_p3;
wire [1:0] tmp1833_fu_38218_p3;
wire [1:0] r_V_176_2_6_fu_34492_p3;
wire [0:0] tmp_2747_fu_38232_p2;
wire [1:0] tmp1836_fu_38246_p3;
wire [1:0] tmp1834_fu_38226_p2;
wire [1:0] tmp1837_fu_38254_p2;
wire [1:0] tmp1832_fu_38204_p2;
wire [0:0] tmp_2748_fu_38274_p3;
wire [1:0] tmp1840_fu_38282_p3;
wire [1:0] tmp1841_fu_38290_p2;
wire [1:0] tmp1839_fu_38266_p3;
wire [1:0] tmp1835_fu_38238_p3;
wire [1:0] tmp1846_fu_38302_p2;
wire [1:0] tmp1847_fu_38308_p2;
wire [1:0] tmp1842_fu_38296_p2;
wire [2:0] tmp_2749_fu_38320_p3;
wire [2:0] r_V_177_2_s_fu_36404_p3;
wire [2:0] tmp_904_fu_38328_p2;
wire [3:0] tmp1848_fu_38334_p3;
wire [3:0] bt_ci_V58_9_fu_35978_p3;
wire [3:0] bt_ci_V58171_9_fu_35986_p3;
wire [2:0] tmp_2750_fu_38356_p1;
wire [2:0] tmp1849_fu_38348_p3;
wire [0:0] tmp_2752_fu_38366_p3;
wire [2:0] tmp_2751_fu_38360_p2;
wire [3:0] bt_ci_V58172_8_fu_35506_p3;
wire [2:0] tmp_2753_fu_38382_p1;
wire [2:0] r_V_177_2_9_3_fu_35994_p3;
wire [2:0] tmp_2754_fu_38386_p2;
wire [0:0] tmp_2755_fu_38392_p3;
wire [2:0] tmp_2756_fu_38400_p2;
wire [4:0] p_Result_1296_2_11_4_fu_36651_p6;
wire [11:0] bt_phi_V_s_fu_23058_p2;
wire [11:0] bt_phi_V37_s_fu_29895_p2;
wire [11:0] bt_phi_V38_s_fu_36732_p2;
wire [6:0] bt_theta_V_s_fu_23131_p2;
wire [6:0] bt_theta_V39_s_fu_29968_p2;
wire [6:0] bt_theta_V40_s_fu_36805_p2;
wire [3:0] bt_cpattern_V_s_fu_23204_p2;
wire [3:0] bt_cpattern_V99_s_fu_23277_p2;
wire [3:0] bt_cpattern_V100_s_fu_23350_p2;
wire [3:0] bt_cpattern_V101_s_fu_23423_p2;
wire [3:0] bt_cpattern_V41_s_fu_30041_p2;
wire [3:0] bt_cpattern_V41102_s_fu_30114_p2;
wire [3:0] bt_cpattern_V41103_s_fu_30187_p2;
wire [3:0] bt_cpattern_V41104_s_fu_30260_p2;
wire [3:0] bt_cpattern_V42_s_fu_36878_p2;
wire [3:0] bt_cpattern_V42105_s_fu_36951_p2;
wire [3:0] bt_cpattern_V42106_s_fu_37024_p2;
wire [3:0] bt_cpattern_V42107_s_fu_37097_p2;
wire [11:0] bt_delta_ph_V_s_fu_23496_p2;
wire [11:0] bt_delta_ph_V108_s_fu_23569_p2;
wire [11:0] bt_delta_ph_V109_s_fu_23642_p2;
wire [11:0] bt_delta_ph_V110_s_fu_23715_p2;
wire [11:0] bt_delta_ph_V111_s_fu_23788_p2;
wire [11:0] bt_delta_ph_V112_s_fu_23861_p2;
wire [11:0] bt_delta_ph_V43_s_fu_30333_p2;
wire [11:0] bt_delta_ph_V43113_s_fu_30406_p2;
wire [11:0] bt_delta_ph_V43114_s_fu_30479_p2;
wire [11:0] bt_delta_ph_V43115_s_fu_30552_p2;
wire [11:0] bt_delta_ph_V43116_s_fu_30625_p2;
wire [11:0] bt_delta_ph_V43117_s_fu_30698_p2;
wire [11:0] bt_delta_ph_V44_s_fu_37170_p2;
wire [11:0] bt_delta_ph_V44118_s_fu_37243_p2;
wire [11:0] bt_delta_ph_V44119_s_fu_37316_p2;
wire [11:0] bt_delta_ph_V44120_s_fu_37389_p2;
wire [11:0] bt_delta_ph_V44121_s_fu_37462_p2;
wire [11:0] bt_delta_ph_V44122_s_fu_37535_p2;
wire [6:0] bt_delta_th_V_s_fu_23934_p2;
wire [6:0] bt_delta_th_V123_s_fu_24007_p2;
wire [6:0] bt_delta_th_V124_s_fu_24080_p2;
wire [6:0] bt_delta_th_V125_s_fu_24153_p2;
wire [6:0] bt_delta_th_V126_s_fu_24226_p2;
wire [6:0] bt_delta_th_V127_s_fu_24299_p2;
wire [6:0] bt_delta_th_V45_s_fu_30771_p2;
wire [6:0] bt_delta_th_V45128_s_fu_30844_p2;
wire [6:0] bt_delta_th_V45129_s_fu_30917_p2;
wire [6:0] bt_delta_th_V45130_s_fu_30990_p2;
wire [6:0] bt_delta_th_V45131_s_fu_31063_p2;
wire [6:0] bt_delta_th_V45132_s_fu_31136_p2;
wire [6:0] bt_delta_th_V46_s_fu_37608_p2;
wire [6:0] bt_delta_th_V46133_s_fu_37681_p2;
wire [6:0] bt_delta_th_V46134_s_fu_37754_p2;
wire [6:0] bt_delta_th_V46135_s_fu_37827_p2;
wire [6:0] bt_delta_th_V46136_s_fu_37900_p2;
wire [6:0] bt_delta_th_V46137_s_fu_37973_p2;
wire [5:0] bt_sign_ph_V_10_fu_24305_p3;
wire [5:0] bt_sign_ph_V47_10_fu_31142_p3;
wire [5:0] bt_sign_ph_V48_10_fu_37979_p3;
wire [5:0] bt_sign_th_V_10_fu_24313_p3;
wire [5:0] bt_sign_th_V49_10_fu_31150_p3;
wire [5:0] bt_sign_th_V50_10_fu_37987_p3;
wire [6:0] bt_rank_V_s_fu_24388_p2;
wire [6:0] bt_rank_V51_s_fu_31225_p2;
wire [6:0] bt_rank_V52_s_fu_38062_p2;
wire [1:0] bt_hi_V_s_fu_24480_p2;
wire [1:0] bt_hi_V151_s_fu_24586_p2;
wire [1:0] bt_hi_V152_s_fu_24640_p2;
wire [1:0] bt_hi_V55_s_fu_31317_p2;
wire [1:0] bt_hi_V55155_s_fu_31423_p2;
wire [1:0] bt_hi_V55156_s_fu_31477_p2;
wire [1:0] bt_hi_V56_s_fu_38154_p2;
wire [1:0] bt_hi_V56159_s_fu_38260_p2;
wire [1:0] bt_hi_V56160_s_fu_38314_p2;
wire [3:0] bt_ci_V_s_fu_24668_p2;
wire [3:0] bt_ci_V163_s_fu_24700_p3;
wire [3:0] bt_ci_V164_s_fu_24732_p3;
wire [3:0] bt_ci_V57_s_fu_31505_p2;
wire [3:0] bt_ci_V57167_s_fu_31537_p3;
wire [3:0] bt_ci_V57168_s_fu_31569_p3;
wire [3:0] bt_ci_V58_s_fu_38342_p2;
wire [3:0] bt_ci_V58171_s_fu_38374_p3;
wire [3:0] bt_ci_V58172_s_fu_38406_p3;
wire [4:0] bt_si_V_10_fu_24740_p3;
wire [4:0] bt_si_V59_10_fu_31577_p3;
wire [4:0] bt_si_V60_10_fu_38414_p3;
always @ (posedge ap_clk) begin
if ((1'b1 == 1'b1)) begin
ap_reg_ppstg_cpattern_0_0_0_V_read_1_reg_40523_pp0_iter1 <= cpattern_0_0_0_V_read_1_reg_40523;
ap_reg_ppstg_cpattern_0_0_1_V_read_1_reg_40516_pp0_iter1 <= cpattern_0_0_1_V_read_1_reg_40516;
ap_reg_ppstg_cpattern_0_0_2_V_read_1_reg_40509_pp0_iter1 <= cpattern_0_0_2_V_read_1_reg_40509;
ap_reg_ppstg_cpattern_0_0_3_V_read_1_reg_40502_pp0_iter1 <= cpattern_0_0_3_V_read_1_reg_40502;
ap_reg_ppstg_cpattern_0_1_0_V_read_1_reg_40495_pp0_iter1 <= cpattern_0_1_0_V_read_1_reg_40495;
ap_reg_ppstg_cpattern_0_1_1_V_read_1_reg_40488_pp0_iter1 <= cpattern_0_1_1_V_read_1_reg_40488;
ap_reg_ppstg_cpattern_0_1_2_V_read_1_reg_40481_pp0_iter1 <= cpattern_0_1_2_V_read_1_reg_40481;
ap_reg_ppstg_cpattern_0_1_3_V_read_1_reg_40474_pp0_iter1 <= cpattern_0_1_3_V_read_1_reg_40474;
ap_reg_ppstg_cpattern_0_2_0_V_read_1_reg_40467_pp0_iter1 <= cpattern_0_2_0_V_read_1_reg_40467;
ap_reg_ppstg_cpattern_0_2_1_V_read_1_reg_40460_pp0_iter1 <= cpattern_0_2_1_V_read_1_reg_40460;
ap_reg_ppstg_cpattern_0_2_2_V_read_1_reg_40453_pp0_iter1 <= cpattern_0_2_2_V_read_1_reg_40453;
ap_reg_ppstg_cpattern_0_2_3_V_read_1_reg_40446_pp0_iter1 <= cpattern_0_2_3_V_read_1_reg_40446;
ap_reg_ppstg_cpattern_1_0_0_V_read_1_reg_40439_pp0_iter1 <= cpattern_1_0_0_V_read_1_reg_40439;
ap_reg_ppstg_cpattern_1_0_1_V_read_1_reg_40432_pp0_iter1 <= cpattern_1_0_1_V_read_1_reg_40432;
ap_reg_ppstg_cpattern_1_0_2_V_read_1_reg_40425_pp0_iter1 <= cpattern_1_0_2_V_read_1_reg_40425;
ap_reg_ppstg_cpattern_1_0_3_V_read_1_reg_40418_pp0_iter1 <= cpattern_1_0_3_V_read_1_reg_40418;
ap_reg_ppstg_cpattern_1_1_0_V_read_1_reg_40411_pp0_iter1 <= cpattern_1_1_0_V_read_1_reg_40411;
ap_reg_ppstg_cpattern_1_1_1_V_read_1_reg_40404_pp0_iter1 <= cpattern_1_1_1_V_read_1_reg_40404;
ap_reg_ppstg_cpattern_1_1_2_V_read_1_reg_40397_pp0_iter1 <= cpattern_1_1_2_V_read_1_reg_40397;
ap_reg_ppstg_cpattern_1_1_3_V_read_1_reg_40390_pp0_iter1 <= cpattern_1_1_3_V_read_1_reg_40390;
ap_reg_ppstg_cpattern_1_2_0_V_read_1_reg_40383_pp0_iter1 <= cpattern_1_2_0_V_read_1_reg_40383;
ap_reg_ppstg_cpattern_1_2_1_V_read_1_reg_40376_pp0_iter1 <= cpattern_1_2_1_V_read_1_reg_40376;
ap_reg_ppstg_cpattern_1_2_2_V_read_1_reg_40369_pp0_iter1 <= cpattern_1_2_2_V_read_1_reg_40369;
ap_reg_ppstg_cpattern_1_2_3_V_read_1_reg_40362_pp0_iter1 <= cpattern_1_2_3_V_read_1_reg_40362;
ap_reg_ppstg_cpattern_2_0_0_V_read_1_reg_40355_pp0_iter1 <= cpattern_2_0_0_V_read_1_reg_40355;
ap_reg_ppstg_cpattern_2_0_1_V_read_1_reg_40348_pp0_iter1 <= cpattern_2_0_1_V_read_1_reg_40348;
ap_reg_ppstg_cpattern_2_0_2_V_read_1_reg_40341_pp0_iter1 <= cpattern_2_0_2_V_read_1_reg_40341;
ap_reg_ppstg_cpattern_2_0_3_V_read_1_reg_40334_pp0_iter1 <= cpattern_2_0_3_V_read_1_reg_40334;
ap_reg_ppstg_cpattern_2_1_0_V_read_1_reg_40327_pp0_iter1 <= cpattern_2_1_0_V_read_1_reg_40327;
ap_reg_ppstg_cpattern_2_1_1_V_read_1_reg_40320_pp0_iter1 <= cpattern_2_1_1_V_read_1_reg_40320;
ap_reg_ppstg_cpattern_2_1_2_V_read_1_reg_40313_pp0_iter1 <= cpattern_2_1_2_V_read_1_reg_40313;
ap_reg_ppstg_cpattern_2_1_3_V_read_1_reg_40306_pp0_iter1 <= cpattern_2_1_3_V_read_1_reg_40306;
ap_reg_ppstg_cpattern_2_2_0_V_read_1_reg_40299_pp0_iter1 <= cpattern_2_2_0_V_read_1_reg_40299;
ap_reg_ppstg_cpattern_2_2_1_V_read_1_reg_40292_pp0_iter1 <= cpattern_2_2_1_V_read_1_reg_40292;
ap_reg_ppstg_cpattern_2_2_2_V_read_1_reg_40285_pp0_iter1 <= cpattern_2_2_2_V_read_1_reg_40285;
ap_reg_ppstg_cpattern_2_2_3_V_read_1_reg_40278_pp0_iter1 <= cpattern_2_2_3_V_read_1_reg_40278;
ap_reg_ppstg_cpattern_3_0_0_V_read_1_reg_40271_pp0_iter1 <= cpattern_3_0_0_V_read_1_reg_40271;
ap_reg_ppstg_cpattern_3_0_1_V_read_1_reg_40264_pp0_iter1 <= cpattern_3_0_1_V_read_1_reg_40264;
ap_reg_ppstg_cpattern_3_0_2_V_read_1_reg_40257_pp0_iter1 <= cpattern_3_0_2_V_read_1_reg_40257;
ap_reg_ppstg_cpattern_3_0_3_V_read_1_reg_40250_pp0_iter1 <= cpattern_3_0_3_V_read_1_reg_40250;
ap_reg_ppstg_cpattern_3_1_0_V_read_1_reg_40243_pp0_iter1 <= cpattern_3_1_0_V_read_1_reg_40243;
ap_reg_ppstg_cpattern_3_1_1_V_read_1_reg_40236_pp0_iter1 <= cpattern_3_1_1_V_read_1_reg_40236;
ap_reg_ppstg_cpattern_3_1_2_V_read_1_reg_40229_pp0_iter1 <= cpattern_3_1_2_V_read_1_reg_40229;
ap_reg_ppstg_cpattern_3_1_3_V_read_1_reg_40222_pp0_iter1 <= cpattern_3_1_3_V_read_1_reg_40222;
ap_reg_ppstg_cpattern_3_2_0_V_read_1_reg_40215_pp0_iter1 <= cpattern_3_2_0_V_read_1_reg_40215;
ap_reg_ppstg_cpattern_3_2_1_V_read_1_reg_40208_pp0_iter1 <= cpattern_3_2_1_V_read_1_reg_40208;
ap_reg_ppstg_cpattern_3_2_2_V_read_1_reg_40201_pp0_iter1 <= cpattern_3_2_2_V_read_1_reg_40201;
ap_reg_ppstg_cpattern_3_2_3_V_read_1_reg_40194_pp0_iter1 <= cpattern_3_2_3_V_read_1_reg_40194;
ap_reg_ppstg_delta_ph_0_0_0_V_read_1_reg_40187_pp0_iter1 <= delta_ph_0_0_0_V_read_1_reg_40187;
ap_reg_ppstg_delta_ph_0_0_1_V_read_1_reg_40180_pp0_iter1 <= delta_ph_0_0_1_V_read_1_reg_40180;
ap_reg_ppstg_delta_ph_0_0_2_V_read_1_reg_40173_pp0_iter1 <= delta_ph_0_0_2_V_read_1_reg_40173;
ap_reg_ppstg_delta_ph_0_0_3_V_read_1_reg_40166_pp0_iter1 <= delta_ph_0_0_3_V_read_1_reg_40166;
ap_reg_ppstg_delta_ph_0_0_4_V_read_1_reg_40159_pp0_iter1 <= delta_ph_0_0_4_V_read_1_reg_40159;
ap_reg_ppstg_delta_ph_0_0_5_V_read_1_reg_40152_pp0_iter1 <= delta_ph_0_0_5_V_read_1_reg_40152;
ap_reg_ppstg_delta_ph_0_1_0_V_read_1_reg_40145_pp0_iter1 <= delta_ph_0_1_0_V_read_1_reg_40145;
ap_reg_ppstg_delta_ph_0_1_1_V_read_1_reg_40138_pp0_iter1 <= delta_ph_0_1_1_V_read_1_reg_40138;
ap_reg_ppstg_delta_ph_0_1_2_V_read_1_reg_40131_pp0_iter1 <= delta_ph_0_1_2_V_read_1_reg_40131;
ap_reg_ppstg_delta_ph_0_1_3_V_read_1_reg_40124_pp0_iter1 <= delta_ph_0_1_3_V_read_1_reg_40124;
ap_reg_ppstg_delta_ph_0_1_4_V_read_1_reg_40117_pp0_iter1 <= delta_ph_0_1_4_V_read_1_reg_40117;
ap_reg_ppstg_delta_ph_0_1_5_V_read_1_reg_40110_pp0_iter1 <= delta_ph_0_1_5_V_read_1_reg_40110;
ap_reg_ppstg_delta_ph_0_2_0_V_read_1_reg_40103_pp0_iter1 <= delta_ph_0_2_0_V_read_1_reg_40103;
ap_reg_ppstg_delta_ph_0_2_1_V_read_1_reg_40096_pp0_iter1 <= delta_ph_0_2_1_V_read_1_reg_40096;
ap_reg_ppstg_delta_ph_0_2_2_V_read_1_reg_40089_pp0_iter1 <= delta_ph_0_2_2_V_read_1_reg_40089;
ap_reg_ppstg_delta_ph_0_2_3_V_read_1_reg_40082_pp0_iter1 <= delta_ph_0_2_3_V_read_1_reg_40082;
ap_reg_ppstg_delta_ph_0_2_4_V_read_1_reg_40075_pp0_iter1 <= delta_ph_0_2_4_V_read_1_reg_40075;
ap_reg_ppstg_delta_ph_0_2_5_V_read_1_reg_40068_pp0_iter1 <= delta_ph_0_2_5_V_read_1_reg_40068;
ap_reg_ppstg_delta_ph_1_0_0_V_read_1_reg_40061_pp0_iter1 <= delta_ph_1_0_0_V_read_1_reg_40061;
ap_reg_ppstg_delta_ph_1_0_1_V_read_1_reg_40054_pp0_iter1 <= delta_ph_1_0_1_V_read_1_reg_40054;
ap_reg_ppstg_delta_ph_1_0_2_V_read_1_reg_40047_pp0_iter1 <= delta_ph_1_0_2_V_read_1_reg_40047;
ap_reg_ppstg_delta_ph_1_0_3_V_read_1_reg_40040_pp0_iter1 <= delta_ph_1_0_3_V_read_1_reg_40040;
ap_reg_ppstg_delta_ph_1_0_4_V_read_1_reg_40033_pp0_iter1 <= delta_ph_1_0_4_V_read_1_reg_40033;
ap_reg_ppstg_delta_ph_1_0_5_V_read_1_reg_40026_pp0_iter1 <= delta_ph_1_0_5_V_read_1_reg_40026;
ap_reg_ppstg_delta_ph_1_1_0_V_read_1_reg_40019_pp0_iter1 <= delta_ph_1_1_0_V_read_1_reg_40019;
ap_reg_ppstg_delta_ph_1_1_1_V_read_1_reg_40012_pp0_iter1 <= delta_ph_1_1_1_V_read_1_reg_40012;
ap_reg_ppstg_delta_ph_1_1_2_V_read_1_reg_40005_pp0_iter1 <= delta_ph_1_1_2_V_read_1_reg_40005;
ap_reg_ppstg_delta_ph_1_1_3_V_read_1_reg_39998_pp0_iter1 <= delta_ph_1_1_3_V_read_1_reg_39998;
ap_reg_ppstg_delta_ph_1_1_4_V_read_1_reg_39991_pp0_iter1 <= delta_ph_1_1_4_V_read_1_reg_39991;
ap_reg_ppstg_delta_ph_1_1_5_V_read_1_reg_39984_pp0_iter1 <= delta_ph_1_1_5_V_read_1_reg_39984;
ap_reg_ppstg_delta_ph_1_2_0_V_read_1_reg_39977_pp0_iter1 <= delta_ph_1_2_0_V_read_1_reg_39977;
ap_reg_ppstg_delta_ph_1_2_1_V_read_1_reg_39970_pp0_iter1 <= delta_ph_1_2_1_V_read_1_reg_39970;
ap_reg_ppstg_delta_ph_1_2_2_V_read_1_reg_39963_pp0_iter1 <= delta_ph_1_2_2_V_read_1_reg_39963;
ap_reg_ppstg_delta_ph_1_2_3_V_read_1_reg_39956_pp0_iter1 <= delta_ph_1_2_3_V_read_1_reg_39956;
ap_reg_ppstg_delta_ph_1_2_4_V_read_1_reg_39949_pp0_iter1 <= delta_ph_1_2_4_V_read_1_reg_39949;
ap_reg_ppstg_delta_ph_1_2_5_V_read_1_reg_39942_pp0_iter1 <= delta_ph_1_2_5_V_read_1_reg_39942;
ap_reg_ppstg_delta_ph_2_0_0_V_read_1_reg_39935_pp0_iter1 <= delta_ph_2_0_0_V_read_1_reg_39935;
ap_reg_ppstg_delta_ph_2_0_1_V_read_1_reg_39928_pp0_iter1 <= delta_ph_2_0_1_V_read_1_reg_39928;
ap_reg_ppstg_delta_ph_2_0_2_V_read_1_reg_39921_pp0_iter1 <= delta_ph_2_0_2_V_read_1_reg_39921;
ap_reg_ppstg_delta_ph_2_0_3_V_read_1_reg_39914_pp0_iter1 <= delta_ph_2_0_3_V_read_1_reg_39914;
ap_reg_ppstg_delta_ph_2_0_4_V_read_1_reg_39907_pp0_iter1 <= delta_ph_2_0_4_V_read_1_reg_39907;
ap_reg_ppstg_delta_ph_2_0_5_V_read_1_reg_39900_pp0_iter1 <= delta_ph_2_0_5_V_read_1_reg_39900;
ap_reg_ppstg_delta_ph_2_1_0_V_read_1_reg_39893_pp0_iter1 <= delta_ph_2_1_0_V_read_1_reg_39893;
ap_reg_ppstg_delta_ph_2_1_1_V_read_1_reg_39886_pp0_iter1 <= delta_ph_2_1_1_V_read_1_reg_39886;
ap_reg_ppstg_delta_ph_2_1_2_V_read_1_reg_39879_pp0_iter1 <= delta_ph_2_1_2_V_read_1_reg_39879;
ap_reg_ppstg_delta_ph_2_1_3_V_read_1_reg_39872_pp0_iter1 <= delta_ph_2_1_3_V_read_1_reg_39872;
ap_reg_ppstg_delta_ph_2_1_4_V_read_1_reg_39865_pp0_iter1 <= delta_ph_2_1_4_V_read_1_reg_39865;
ap_reg_ppstg_delta_ph_2_1_5_V_read_1_reg_39858_pp0_iter1 <= delta_ph_2_1_5_V_read_1_reg_39858;
ap_reg_ppstg_delta_ph_2_2_0_V_read_1_reg_39851_pp0_iter1 <= delta_ph_2_2_0_V_read_1_reg_39851;
ap_reg_ppstg_delta_ph_2_2_1_V_read_1_reg_39844_pp0_iter1 <= delta_ph_2_2_1_V_read_1_reg_39844;
ap_reg_ppstg_delta_ph_2_2_2_V_read_1_reg_39837_pp0_iter1 <= delta_ph_2_2_2_V_read_1_reg_39837;
ap_reg_ppstg_delta_ph_2_2_3_V_read_1_reg_39830_pp0_iter1 <= delta_ph_2_2_3_V_read_1_reg_39830;
ap_reg_ppstg_delta_ph_2_2_4_V_read_1_reg_39823_pp0_iter1 <= delta_ph_2_2_4_V_read_1_reg_39823;
ap_reg_ppstg_delta_ph_2_2_5_V_read_1_reg_39816_pp0_iter1 <= delta_ph_2_2_5_V_read_1_reg_39816;
ap_reg_ppstg_delta_ph_3_0_0_V_read_1_reg_39809_pp0_iter1 <= delta_ph_3_0_0_V_read_1_reg_39809;
ap_reg_ppstg_delta_ph_3_0_1_V_read_1_reg_39802_pp0_iter1 <= delta_ph_3_0_1_V_read_1_reg_39802;
ap_reg_ppstg_delta_ph_3_0_2_V_read_1_reg_39795_pp0_iter1 <= delta_ph_3_0_2_V_read_1_reg_39795;
ap_reg_ppstg_delta_ph_3_0_3_V_read_1_reg_39788_pp0_iter1 <= delta_ph_3_0_3_V_read_1_reg_39788;
ap_reg_ppstg_delta_ph_3_0_4_V_read_1_reg_39781_pp0_iter1 <= delta_ph_3_0_4_V_read_1_reg_39781;
ap_reg_ppstg_delta_ph_3_0_5_V_read_1_reg_39774_pp0_iter1 <= delta_ph_3_0_5_V_read_1_reg_39774;
ap_reg_ppstg_delta_ph_3_1_0_V_read_1_reg_39767_pp0_iter1 <= delta_ph_3_1_0_V_read_1_reg_39767;
ap_reg_ppstg_delta_ph_3_1_1_V_read_1_reg_39760_pp0_iter1 <= delta_ph_3_1_1_V_read_1_reg_39760;
ap_reg_ppstg_delta_ph_3_1_2_V_read_1_reg_39753_pp0_iter1 <= delta_ph_3_1_2_V_read_1_reg_39753;
ap_reg_ppstg_delta_ph_3_1_3_V_read_1_reg_39746_pp0_iter1 <= delta_ph_3_1_3_V_read_1_reg_39746;
ap_reg_ppstg_delta_ph_3_1_4_V_read_1_reg_39739_pp0_iter1 <= delta_ph_3_1_4_V_read_1_reg_39739;
ap_reg_ppstg_delta_ph_3_1_5_V_read_1_reg_39732_pp0_iter1 <= delta_ph_3_1_5_V_read_1_reg_39732;
ap_reg_ppstg_delta_ph_3_2_0_V_read_1_reg_39725_pp0_iter1 <= delta_ph_3_2_0_V_read_1_reg_39725;
ap_reg_ppstg_delta_ph_3_2_1_V_read_1_reg_39718_pp0_iter1 <= delta_ph_3_2_1_V_read_1_reg_39718;
ap_reg_ppstg_delta_ph_3_2_2_V_read_1_reg_39711_pp0_iter1 <= delta_ph_3_2_2_V_read_1_reg_39711;
ap_reg_ppstg_delta_ph_3_2_3_V_read_1_reg_39704_pp0_iter1 <= delta_ph_3_2_3_V_read_1_reg_39704;
ap_reg_ppstg_delta_ph_3_2_4_V_read_1_reg_39697_pp0_iter1 <= delta_ph_3_2_4_V_read_1_reg_39697;
ap_reg_ppstg_delta_ph_3_2_5_V_read_1_reg_39690_pp0_iter1 <= delta_ph_3_2_5_V_read_1_reg_39690;
ap_reg_ppstg_delta_th_0_0_0_V_read_1_reg_39683_pp0_iter1 <= delta_th_0_0_0_V_read_1_reg_39683;
ap_reg_ppstg_delta_th_0_0_1_V_read_1_reg_39676_pp0_iter1 <= delta_th_0_0_1_V_read_1_reg_39676;
ap_reg_ppstg_delta_th_0_0_2_V_read_1_reg_39669_pp0_iter1 <= delta_th_0_0_2_V_read_1_reg_39669;
ap_reg_ppstg_delta_th_0_0_3_V_read_1_reg_39662_pp0_iter1 <= delta_th_0_0_3_V_read_1_reg_39662;
ap_reg_ppstg_delta_th_0_0_4_V_read_1_reg_39655_pp0_iter1 <= delta_th_0_0_4_V_read_1_reg_39655;
ap_reg_ppstg_delta_th_0_0_5_V_read_1_reg_39648_pp0_iter1 <= delta_th_0_0_5_V_read_1_reg_39648;
ap_reg_ppstg_delta_th_0_1_0_V_read_1_reg_39641_pp0_iter1 <= delta_th_0_1_0_V_read_1_reg_39641;
ap_reg_ppstg_delta_th_0_1_1_V_read_1_reg_39634_pp0_iter1 <= delta_th_0_1_1_V_read_1_reg_39634;
ap_reg_ppstg_delta_th_0_1_2_V_read_1_reg_39627_pp0_iter1 <= delta_th_0_1_2_V_read_1_reg_39627;
ap_reg_ppstg_delta_th_0_1_3_V_read_1_reg_39620_pp0_iter1 <= delta_th_0_1_3_V_read_1_reg_39620;
ap_reg_ppstg_delta_th_0_1_4_V_read_1_reg_39613_pp0_iter1 <= delta_th_0_1_4_V_read_1_reg_39613;
ap_reg_ppstg_delta_th_0_1_5_V_read_1_reg_39606_pp0_iter1 <= delta_th_0_1_5_V_read_1_reg_39606;
ap_reg_ppstg_delta_th_0_2_0_V_read_1_reg_39599_pp0_iter1 <= delta_th_0_2_0_V_read_1_reg_39599;
ap_reg_ppstg_delta_th_0_2_1_V_read_1_reg_39592_pp0_iter1 <= delta_th_0_2_1_V_read_1_reg_39592;
ap_reg_ppstg_delta_th_0_2_2_V_read_1_reg_39585_pp0_iter1 <= delta_th_0_2_2_V_read_1_reg_39585;
ap_reg_ppstg_delta_th_0_2_3_V_read_1_reg_39578_pp0_iter1 <= delta_th_0_2_3_V_read_1_reg_39578;
ap_reg_ppstg_delta_th_0_2_4_V_read_1_reg_39571_pp0_iter1 <= delta_th_0_2_4_V_read_1_reg_39571;
ap_reg_ppstg_delta_th_0_2_5_V_read_1_reg_39564_pp0_iter1 <= delta_th_0_2_5_V_read_1_reg_39564;
ap_reg_ppstg_delta_th_1_0_0_V_read_1_reg_39557_pp0_iter1 <= delta_th_1_0_0_V_read_1_reg_39557;
ap_reg_ppstg_delta_th_1_0_1_V_read_1_reg_39550_pp0_iter1 <= delta_th_1_0_1_V_read_1_reg_39550;
ap_reg_ppstg_delta_th_1_0_2_V_read_1_reg_39543_pp0_iter1 <= delta_th_1_0_2_V_read_1_reg_39543;
ap_reg_ppstg_delta_th_1_0_3_V_read_1_reg_39536_pp0_iter1 <= delta_th_1_0_3_V_read_1_reg_39536;
ap_reg_ppstg_delta_th_1_0_4_V_read_1_reg_39529_pp0_iter1 <= delta_th_1_0_4_V_read_1_reg_39529;
ap_reg_ppstg_delta_th_1_0_5_V_read_1_reg_39522_pp0_iter1 <= delta_th_1_0_5_V_read_1_reg_39522;
ap_reg_ppstg_delta_th_1_1_0_V_read_1_reg_39515_pp0_iter1 <= delta_th_1_1_0_V_read_1_reg_39515;
ap_reg_ppstg_delta_th_1_1_1_V_read_1_reg_39508_pp0_iter1 <= delta_th_1_1_1_V_read_1_reg_39508;
ap_reg_ppstg_delta_th_1_1_2_V_read_1_reg_39501_pp0_iter1 <= delta_th_1_1_2_V_read_1_reg_39501;
ap_reg_ppstg_delta_th_1_1_3_V_read_1_reg_39494_pp0_iter1 <= delta_th_1_1_3_V_read_1_reg_39494;
ap_reg_ppstg_delta_th_1_1_4_V_read_1_reg_39487_pp0_iter1 <= delta_th_1_1_4_V_read_1_reg_39487;
ap_reg_ppstg_delta_th_1_1_5_V_read_1_reg_39480_pp0_iter1 <= delta_th_1_1_5_V_read_1_reg_39480;
ap_reg_ppstg_delta_th_1_2_0_V_read_1_reg_39473_pp0_iter1 <= delta_th_1_2_0_V_read_1_reg_39473;
ap_reg_ppstg_delta_th_1_2_1_V_read_1_reg_39466_pp0_iter1 <= delta_th_1_2_1_V_read_1_reg_39466;
ap_reg_ppstg_delta_th_1_2_2_V_read_1_reg_39459_pp0_iter1 <= delta_th_1_2_2_V_read_1_reg_39459;
ap_reg_ppstg_delta_th_1_2_3_V_read_1_reg_39452_pp0_iter1 <= delta_th_1_2_3_V_read_1_reg_39452;
ap_reg_ppstg_delta_th_1_2_4_V_read_1_reg_39445_pp0_iter1 <= delta_th_1_2_4_V_read_1_reg_39445;
ap_reg_ppstg_delta_th_1_2_5_V_read_1_reg_39438_pp0_iter1 <= delta_th_1_2_5_V_read_1_reg_39438;
ap_reg_ppstg_delta_th_2_0_0_V_read_1_reg_39431_pp0_iter1 <= delta_th_2_0_0_V_read_1_reg_39431;
ap_reg_ppstg_delta_th_2_0_1_V_read_1_reg_39424_pp0_iter1 <= delta_th_2_0_1_V_read_1_reg_39424;
ap_reg_ppstg_delta_th_2_0_2_V_read_1_reg_39417_pp0_iter1 <= delta_th_2_0_2_V_read_1_reg_39417;
ap_reg_ppstg_delta_th_2_0_3_V_read_1_reg_39410_pp0_iter1 <= delta_th_2_0_3_V_read_1_reg_39410;
ap_reg_ppstg_delta_th_2_0_4_V_read_1_reg_39403_pp0_iter1 <= delta_th_2_0_4_V_read_1_reg_39403;
ap_reg_ppstg_delta_th_2_0_5_V_read_1_reg_39396_pp0_iter1 <= delta_th_2_0_5_V_read_1_reg_39396;
ap_reg_ppstg_delta_th_2_1_0_V_read_1_reg_39389_pp0_iter1 <= delta_th_2_1_0_V_read_1_reg_39389;
ap_reg_ppstg_delta_th_2_1_1_V_read_1_reg_39382_pp0_iter1 <= delta_th_2_1_1_V_read_1_reg_39382;
ap_reg_ppstg_delta_th_2_1_2_V_read_1_reg_39375_pp0_iter1 <= delta_th_2_1_2_V_read_1_reg_39375;
ap_reg_ppstg_delta_th_2_1_3_V_read_1_reg_39368_pp0_iter1 <= delta_th_2_1_3_V_read_1_reg_39368;
ap_reg_ppstg_delta_th_2_1_4_V_read_1_reg_39361_pp0_iter1 <= delta_th_2_1_4_V_read_1_reg_39361;
ap_reg_ppstg_delta_th_2_1_5_V_read_1_reg_39354_pp0_iter1 <= delta_th_2_1_5_V_read_1_reg_39354;
ap_reg_ppstg_delta_th_2_2_0_V_read_1_reg_39347_pp0_iter1 <= delta_th_2_2_0_V_read_1_reg_39347;
ap_reg_ppstg_delta_th_2_2_1_V_read_1_reg_39340_pp0_iter1 <= delta_th_2_2_1_V_read_1_reg_39340;
ap_reg_ppstg_delta_th_2_2_2_V_read_1_reg_39333_pp0_iter1 <= delta_th_2_2_2_V_read_1_reg_39333;
ap_reg_ppstg_delta_th_2_2_3_V_read_1_reg_39326_pp0_iter1 <= delta_th_2_2_3_V_read_1_reg_39326;
ap_reg_ppstg_delta_th_2_2_4_V_read_1_reg_39319_pp0_iter1 <= delta_th_2_2_4_V_read_1_reg_39319;
ap_reg_ppstg_delta_th_2_2_5_V_read_1_reg_39312_pp0_iter1 <= delta_th_2_2_5_V_read_1_reg_39312;
ap_reg_ppstg_delta_th_3_0_0_V_read_1_reg_39305_pp0_iter1 <= delta_th_3_0_0_V_read_1_reg_39305;
ap_reg_ppstg_delta_th_3_0_1_V_read_1_reg_39298_pp0_iter1 <= delta_th_3_0_1_V_read_1_reg_39298;
ap_reg_ppstg_delta_th_3_0_2_V_read_1_reg_39291_pp0_iter1 <= delta_th_3_0_2_V_read_1_reg_39291;
ap_reg_ppstg_delta_th_3_0_3_V_read_1_reg_39284_pp0_iter1 <= delta_th_3_0_3_V_read_1_reg_39284;
ap_reg_ppstg_delta_th_3_0_4_V_read_1_reg_39277_pp0_iter1 <= delta_th_3_0_4_V_read_1_reg_39277;
ap_reg_ppstg_delta_th_3_0_5_V_read_1_reg_39270_pp0_iter1 <= delta_th_3_0_5_V_read_1_reg_39270;
ap_reg_ppstg_delta_th_3_1_0_V_read_1_reg_39263_pp0_iter1 <= delta_th_3_1_0_V_read_1_reg_39263;
ap_reg_ppstg_delta_th_3_1_1_V_read_1_reg_39256_pp0_iter1 <= delta_th_3_1_1_V_read_1_reg_39256;
ap_reg_ppstg_delta_th_3_1_2_V_read_1_reg_39249_pp0_iter1 <= delta_th_3_1_2_V_read_1_reg_39249;
ap_reg_ppstg_delta_th_3_1_3_V_read_1_reg_39242_pp0_iter1 <= delta_th_3_1_3_V_read_1_reg_39242;
ap_reg_ppstg_delta_th_3_1_4_V_read_1_reg_39235_pp0_iter1 <= delta_th_3_1_4_V_read_1_reg_39235;
ap_reg_ppstg_delta_th_3_1_5_V_read_1_reg_39228_pp0_iter1 <= delta_th_3_1_5_V_read_1_reg_39228;
ap_reg_ppstg_delta_th_3_2_0_V_read_1_reg_39221_pp0_iter1 <= delta_th_3_2_0_V_read_1_reg_39221;
ap_reg_ppstg_delta_th_3_2_1_V_read_1_reg_39214_pp0_iter1 <= delta_th_3_2_1_V_read_1_reg_39214;
ap_reg_ppstg_delta_th_3_2_2_V_read_1_reg_39207_pp0_iter1 <= delta_th_3_2_2_V_read_1_reg_39207;
ap_reg_ppstg_delta_th_3_2_3_V_read_1_reg_39200_pp0_iter1 <= delta_th_3_2_3_V_read_1_reg_39200;
ap_reg_ppstg_delta_th_3_2_4_V_read_1_reg_39193_pp0_iter1 <= delta_th_3_2_4_V_read_1_reg_39193;
ap_reg_ppstg_delta_th_3_2_5_V_read_1_reg_39186_pp0_iter1 <= delta_th_3_2_5_V_read_1_reg_39186;
ap_reg_ppstg_phi_0_0_V_read_1_reg_40691_pp0_iter1 <= phi_0_0_V_read_1_reg_40691;
ap_reg_ppstg_phi_0_1_V_read_1_reg_40684_pp0_iter1 <= phi_0_1_V_read_1_reg_40684;
ap_reg_ppstg_phi_0_2_V_read_1_reg_40677_pp0_iter1 <= phi_0_2_V_read_1_reg_40677;
ap_reg_ppstg_phi_1_0_V_read_1_reg_40670_pp0_iter1 <= phi_1_0_V_read_1_reg_40670;
ap_reg_ppstg_phi_1_1_V_read_1_reg_40663_pp0_iter1 <= phi_1_1_V_read_1_reg_40663;
ap_reg_ppstg_phi_1_2_V_read_1_reg_40656_pp0_iter1 <= phi_1_2_V_read_1_reg_40656;
ap_reg_ppstg_phi_2_0_V_read_1_reg_40649_pp0_iter1 <= phi_2_0_V_read_1_reg_40649;
ap_reg_ppstg_phi_2_1_V_read_1_reg_40642_pp0_iter1 <= phi_2_1_V_read_1_reg_40642;
ap_reg_ppstg_phi_2_2_V_read_1_reg_40635_pp0_iter1 <= phi_2_2_V_read_1_reg_40635;
ap_reg_ppstg_phi_3_0_V_read_1_reg_40628_pp0_iter1 <= phi_3_0_V_read_1_reg_40628;
ap_reg_ppstg_phi_3_1_V_read_1_reg_40621_pp0_iter1 <= phi_3_1_V_read_1_reg_40621;
ap_reg_ppstg_phi_3_2_V_read_1_reg_40614_pp0_iter1 <= phi_3_2_V_read_1_reg_40614;
ap_reg_ppstg_rank_0_0_V_read_1_reg_39165_pp0_iter1 <= rank_0_0_V_read_1_reg_39165;
ap_reg_ppstg_rank_0_1_V_read_1_reg_39158_pp0_iter1 <= rank_0_1_V_read_1_reg_39158;
ap_reg_ppstg_rank_0_2_V_read_1_reg_39151_pp0_iter1 <= rank_0_2_V_read_1_reg_39151;
ap_reg_ppstg_rank_1_0_V_read_1_reg_39144_pp0_iter1 <= rank_1_0_V_read_1_reg_39144;
ap_reg_ppstg_rank_1_1_V_read_1_reg_39137_pp0_iter1 <= rank_1_1_V_read_1_reg_39137;
ap_reg_ppstg_rank_1_2_V_read_1_reg_39130_pp0_iter1 <= rank_1_2_V_read_1_reg_39130;
ap_reg_ppstg_rank_2_0_V_read_1_reg_39123_pp0_iter1 <= rank_2_0_V_read_1_reg_39123;
ap_reg_ppstg_rank_2_1_V_read_1_reg_39116_pp0_iter1 <= rank_2_1_V_read_1_reg_39116;
ap_reg_ppstg_rank_2_2_V_read_1_reg_39109_pp0_iter1 <= rank_2_2_V_read_1_reg_39109;
ap_reg_ppstg_rank_3_0_V_read_1_reg_39102_pp0_iter1 <= rank_3_0_V_read_1_reg_39102;
ap_reg_ppstg_rank_3_1_V_read_1_reg_39095_pp0_iter1 <= rank_3_1_V_read_1_reg_39095;
ap_reg_ppstg_rank_3_2_V_read_1_reg_39088_pp0_iter1 <= rank_3_2_V_read_1_reg_39088;
ap_reg_ppstg_sign_ph_0_0_V_read_1_reg_39179_pp0_iter1 <= sign_ph_0_0_V_read_1_reg_39179;
ap_reg_ppstg_sign_th_0_0_V_read_1_reg_39172_pp0_iter1 <= sign_th_0_0_V_read_1_reg_39172;
ap_reg_ppstg_theta_0_0_V_read_1_reg_40607_pp0_iter1 <= theta_0_0_V_read_1_reg_40607;
ap_reg_ppstg_theta_0_1_V_read_1_reg_40600_pp0_iter1 <= theta_0_1_V_read_1_reg_40600;
ap_reg_ppstg_theta_0_2_V_read_1_reg_40593_pp0_iter1 <= theta_0_2_V_read_1_reg_40593;
ap_reg_ppstg_theta_1_0_V_read_1_reg_40586_pp0_iter1 <= theta_1_0_V_read_1_reg_40586;
ap_reg_ppstg_theta_1_1_V_read_1_reg_40579_pp0_iter1 <= theta_1_1_V_read_1_reg_40579;
ap_reg_ppstg_theta_1_2_V_read_1_reg_40572_pp0_iter1 <= theta_1_2_V_read_1_reg_40572;
ap_reg_ppstg_theta_2_0_V_read_1_reg_40565_pp0_iter1 <= theta_2_0_V_read_1_reg_40565;
ap_reg_ppstg_theta_2_1_V_read_1_reg_40558_pp0_iter1 <= theta_2_1_V_read_1_reg_40558;
ap_reg_ppstg_theta_2_2_V_read_1_reg_40551_pp0_iter1 <= theta_2_2_V_read_1_reg_40551;
ap_reg_ppstg_theta_3_0_V_read_1_reg_40544_pp0_iter1 <= theta_3_0_V_read_1_reg_40544;
ap_reg_ppstg_theta_3_1_V_read_1_reg_40537_pp0_iter1 <= theta_3_1_V_read_1_reg_40537;
ap_reg_ppstg_theta_3_2_V_read_1_reg_40530_pp0_iter1 <= theta_3_2_V_read_1_reg_40530;
ap_reg_ppstg_tmp_1150_reg_40708_pp0_iter1 <= tmp_1150_reg_40708;
ap_reg_ppstg_tmp_1164_reg_40715_pp0_iter1 <= tmp_1164_reg_40715;
ap_reg_ppstg_tmp_1167_reg_40722_pp0_iter1 <= tmp_1167_reg_40722;
ap_reg_ppstg_tmp_1169_reg_40729_pp0_iter1 <= tmp_1169_reg_40729;
ap_reg_ppstg_tmp_1170_reg_40736_pp0_iter1 <= tmp_1170_reg_40736;
ap_reg_ppstg_tmp_1172_reg_40743_pp0_iter1 <= tmp_1172_reg_40743;
ap_reg_ppstg_tmp_1173_reg_40750_pp0_iter1 <= tmp_1173_reg_40750;
ap_reg_ppstg_tmp_1188_reg_40757_pp0_iter1 <= tmp_1188_reg_40757;
ap_reg_ppstg_tmp_1190_reg_40764_pp0_iter1 <= tmp_1190_reg_40764;
ap_reg_ppstg_tmp_1191_reg_40771_pp0_iter1 <= tmp_1191_reg_40771;
ap_reg_ppstg_tmp_1193_reg_40778_pp0_iter1 <= tmp_1193_reg_40778;
ap_reg_ppstg_tmp_1195_reg_40785_pp0_iter1 <= tmp_1195_reg_40785;
ap_reg_ppstg_tmp_1197_reg_40792_pp0_iter1 <= tmp_1197_reg_40792;
ap_reg_ppstg_tmp_1199_reg_40799_pp0_iter1 <= tmp_1199_reg_40799;
ap_reg_ppstg_tmp_1212_reg_40806_pp0_iter1 <= tmp_1212_reg_40806;
ap_reg_ppstg_tmp_1216_reg_40813_pp0_iter1 <= tmp_1216_reg_40813;
ap_reg_ppstg_tmp_1217_reg_40820_pp0_iter1 <= tmp_1217_reg_40820;
ap_reg_ppstg_tmp_1219_reg_40827_pp0_iter1 <= tmp_1219_reg_40827;
ap_reg_ppstg_tmp_1222_reg_40834_pp0_iter1 <= tmp_1222_reg_40834;
ap_reg_ppstg_tmp_1236_reg_40841_pp0_iter1 <= tmp_1236_reg_40841;
ap_reg_ppstg_tmp_1239_reg_40848_pp0_iter1 <= tmp_1239_reg_40848;
ap_reg_ppstg_tmp_1253_reg_40855_pp0_iter1 <= tmp_1253_reg_40855;
ap_reg_ppstg_tmp_1402_10_reg_40983_pp0_iter1 <= tmp_1402_10_reg_40983;
ap_reg_ppstg_tmp_1402_8_reg_40950_pp0_iter1 <= tmp_1402_8_reg_40950;
ap_reg_ppstg_tmp_1402_9_reg_40961_pp0_iter1 <= tmp_1402_9_reg_40961;
ap_reg_ppstg_tmp_1402_s_reg_40972_pp0_iter1 <= tmp_1402_s_reg_40972;
ap_reg_ppstg_tmp_1806_reg_40955_pp0_iter1 <= tmp_1806_reg_40955;
ap_reg_ppstg_tmp_1833_reg_40966_pp0_iter1 <= tmp_1833_reg_40966;
ap_reg_ppstg_tmp_1860_reg_40977_pp0_iter1 <= tmp_1860_reg_40977;
ap_reg_ppstg_tmp_1887_reg_40988_pp0_iter1 <= tmp_1887_reg_40988;
ap_reg_ppstg_tmp_1905_reg_40994_pp0_iter1 <= tmp_1905_reg_40994;
ap_reg_ppstg_tmp_1907_reg_41001_pp0_iter1 <= tmp_1907_reg_41001;
ap_reg_ppstg_tmp_1909_reg_41008_pp0_iter1 <= tmp_1909_reg_41008;
ap_reg_ppstg_tmp_1911_reg_41015_pp0_iter1 <= tmp_1911_reg_41015;
ap_reg_ppstg_tmp_1913_reg_41022_pp0_iter1 <= tmp_1913_reg_41022;
ap_reg_ppstg_tmp_1915_reg_41029_pp0_iter1 <= tmp_1915_reg_41029;
ap_reg_ppstg_tmp_1917_reg_41036_pp0_iter1 <= tmp_1917_reg_41036;
ap_reg_ppstg_tmp_1919_reg_41043_pp0_iter1 <= tmp_1919_reg_41043;
ap_reg_ppstg_tmp_1921_reg_41050_pp0_iter1 <= tmp_1921_reg_41050;
ap_reg_ppstg_tmp_1923_reg_41057_pp0_iter1 <= tmp_1923_reg_41057;
ap_reg_ppstg_tmp_1925_reg_41064_pp0_iter1 <= tmp_1925_reg_41064;
ap_reg_ppstg_tmp_1927_reg_41071_pp0_iter1 <= tmp_1927_reg_41071;
ap_reg_ppstg_tmp_1929_reg_41078_pp0_iter1 <= tmp_1929_reg_41078;
ap_reg_ppstg_tmp_1936_reg_41085_pp0_iter1 <= tmp_1936_reg_41085;
ap_reg_ppstg_tmp_1938_reg_41092_pp0_iter1 <= tmp_1938_reg_41092;
ap_reg_ppstg_tmp_1940_reg_41099_pp0_iter1 <= tmp_1940_reg_41099;
ap_reg_ppstg_tmp_1942_reg_41106_pp0_iter1 <= tmp_1942_reg_41106;
ap_reg_ppstg_tmp_1944_reg_41113_pp0_iter1 <= tmp_1944_reg_41113;
ap_reg_ppstg_tmp_1946_reg_41120_pp0_iter1 <= tmp_1946_reg_41120;
ap_reg_ppstg_tmp_1948_reg_41127_pp0_iter1 <= tmp_1948_reg_41127;
ap_reg_ppstg_tmp_1950_reg_41134_pp0_iter1 <= tmp_1950_reg_41134;
ap_reg_ppstg_tmp_1952_reg_41141_pp0_iter1 <= tmp_1952_reg_41141;
ap_reg_ppstg_tmp_1954_reg_41148_pp0_iter1 <= tmp_1954_reg_41148;
ap_reg_ppstg_tmp_1956_reg_41155_pp0_iter1 <= tmp_1956_reg_41155;
ap_reg_ppstg_tmp_1958_reg_41162_pp0_iter1 <= tmp_1958_reg_41162;
ap_reg_ppstg_tmp_1960_reg_41169_pp0_iter1 <= tmp_1960_reg_41169;
ap_reg_ppstg_tmp_1966_reg_41176_pp0_iter1 <= tmp_1966_reg_41176;
ap_reg_ppstg_tmp_1968_reg_41183_pp0_iter1 <= tmp_1968_reg_41183;
ap_reg_ppstg_tmp_1970_reg_41190_pp0_iter1 <= tmp_1970_reg_41190;
ap_reg_ppstg_tmp_1972_reg_41197_pp0_iter1 <= tmp_1972_reg_41197;
ap_reg_ppstg_tmp_1974_reg_41204_pp0_iter1 <= tmp_1974_reg_41204;
ap_reg_ppstg_tmp_1976_reg_41211_pp0_iter1 <= tmp_1976_reg_41211;
ap_reg_ppstg_tmp_1978_reg_41218_pp0_iter1 <= tmp_1978_reg_41218;
ap_reg_ppstg_tmp_1980_reg_41225_pp0_iter1 <= tmp_1980_reg_41225;
ap_reg_ppstg_tmp_1982_reg_41232_pp0_iter1 <= tmp_1982_reg_41232;
ap_reg_ppstg_tmp_1984_reg_41239_pp0_iter1 <= tmp_1984_reg_41239;
ap_reg_ppstg_tmp_1986_reg_41246_pp0_iter1 <= tmp_1986_reg_41246;
ap_reg_ppstg_tmp_1988_reg_41253_pp0_iter1 <= tmp_1988_reg_41253;
ap_reg_ppstg_tmp_1990_reg_41260_pp0_iter1 <= tmp_1990_reg_41260;
ap_reg_ppstg_tmp_2008_reg_41267_pp0_iter1 <= tmp_2008_reg_41267;
ap_reg_ppstg_tmp_2010_reg_41274_pp0_iter1 <= tmp_2010_reg_41274;
ap_reg_ppstg_tmp_2012_reg_41281_pp0_iter1 <= tmp_2012_reg_41281;
ap_reg_ppstg_tmp_2014_reg_41288_pp0_iter1 <= tmp_2014_reg_41288;
ap_reg_ppstg_tmp_2016_reg_41295_pp0_iter1 <= tmp_2016_reg_41295;
ap_reg_ppstg_tmp_2018_reg_41302_pp0_iter1 <= tmp_2018_reg_41302;
ap_reg_ppstg_tmp_2020_reg_41309_pp0_iter1 <= tmp_2020_reg_41309;
ap_reg_ppstg_tmp_2022_reg_41316_pp0_iter1 <= tmp_2022_reg_41316;
ap_reg_ppstg_tmp_2024_reg_41323_pp0_iter1 <= tmp_2024_reg_41323;
ap_reg_ppstg_tmp_2026_reg_41330_pp0_iter1 <= tmp_2026_reg_41330;
ap_reg_ppstg_tmp_2028_reg_41337_pp0_iter1 <= tmp_2028_reg_41337;
ap_reg_ppstg_tmp_2030_reg_41344_pp0_iter1 <= tmp_2030_reg_41344;
ap_reg_ppstg_tmp_2034_reg_41351_pp0_iter1 <= tmp_2034_reg_41351;
ap_reg_ppstg_tmp_2040_reg_41358_pp0_iter1 <= tmp_2040_reg_41358;
ap_reg_ppstg_tmp_2042_reg_41365_pp0_iter1 <= tmp_2042_reg_41365;
ap_reg_ppstg_tmp_2044_reg_41372_pp0_iter1 <= tmp_2044_reg_41372;
ap_reg_ppstg_tmp_2046_reg_41379_pp0_iter1 <= tmp_2046_reg_41379;
ap_reg_ppstg_tmp_2048_reg_41386_pp0_iter1 <= tmp_2048_reg_41386;
ap_reg_ppstg_tmp_2050_reg_41393_pp0_iter1 <= tmp_2050_reg_41393;
ap_reg_ppstg_tmp_2052_reg_41400_pp0_iter1 <= tmp_2052_reg_41400;
ap_reg_ppstg_tmp_2054_reg_41407_pp0_iter1 <= tmp_2054_reg_41407;
ap_reg_ppstg_tmp_2056_reg_41414_pp0_iter1 <= tmp_2056_reg_41414;
ap_reg_ppstg_tmp_2058_reg_41421_pp0_iter1 <= tmp_2058_reg_41421;
ap_reg_ppstg_tmp_2060_reg_41428_pp0_iter1 <= tmp_2060_reg_41428;
ap_reg_ppstg_tmp_2062_reg_41435_pp0_iter1 <= tmp_2062_reg_41435;
ap_reg_ppstg_tmp_2065_reg_41442_pp0_iter1 <= tmp_2065_reg_41442;
ap_reg_ppstg_tmp_2073_reg_41449_pp0_iter1 <= tmp_2073_reg_41449;
ap_reg_ppstg_tmp_2075_reg_41456_pp0_iter1 <= tmp_2075_reg_41456;
ap_reg_ppstg_tmp_2077_reg_41463_pp0_iter1 <= tmp_2077_reg_41463;
ap_reg_ppstg_tmp_2079_reg_41470_pp0_iter1 <= tmp_2079_reg_41470;
ap_reg_ppstg_tmp_2081_reg_41477_pp0_iter1 <= tmp_2081_reg_41477;
ap_reg_ppstg_tmp_2083_reg_41484_pp0_iter1 <= tmp_2083_reg_41484;
ap_reg_ppstg_tmp_2085_reg_41491_pp0_iter1 <= tmp_2085_reg_41491;
ap_reg_ppstg_tmp_2087_reg_41498_pp0_iter1 <= tmp_2087_reg_41498;
ap_reg_ppstg_tmp_2089_reg_41505_pp0_iter1 <= tmp_2089_reg_41505;
ap_reg_ppstg_tmp_2091_reg_41512_pp0_iter1 <= tmp_2091_reg_41512;
ap_reg_ppstg_tmp_2093_reg_41519_pp0_iter1 <= tmp_2093_reg_41519;
ap_reg_ppstg_tmp_2095_reg_41526_pp0_iter1 <= tmp_2095_reg_41526;
ap_reg_ppstg_tmp_2097_reg_41533_pp0_iter1 <= tmp_2097_reg_41533;
ap_reg_ppstg_tmp_2103_reg_41540_pp0_iter1 <= tmp_2103_reg_41540;
ap_reg_ppstg_tmp_2105_reg_41547_pp0_iter1 <= tmp_2105_reg_41547;
ap_reg_ppstg_tmp_2107_reg_41554_pp0_iter1 <= tmp_2107_reg_41554;
ap_reg_ppstg_tmp_2109_reg_41561_pp0_iter1 <= tmp_2109_reg_41561;
ap_reg_ppstg_tmp_2111_reg_41568_pp0_iter1 <= tmp_2111_reg_41568;
ap_reg_ppstg_tmp_2113_reg_41575_pp0_iter1 <= tmp_2113_reg_41575;
ap_reg_ppstg_tmp_2115_reg_41582_pp0_iter1 <= tmp_2115_reg_41582;
ap_reg_ppstg_tmp_2117_reg_41589_pp0_iter1 <= tmp_2117_reg_41589;
ap_reg_ppstg_tmp_2119_reg_41596_pp0_iter1 <= tmp_2119_reg_41596;
ap_reg_ppstg_tmp_2121_reg_41603_pp0_iter1 <= tmp_2121_reg_41603;
ap_reg_ppstg_tmp_2123_reg_41610_pp0_iter1 <= tmp_2123_reg_41610;
ap_reg_ppstg_tmp_2125_reg_41617_pp0_iter1 <= tmp_2125_reg_41617;
ap_reg_ppstg_tmp_2127_reg_41624_pp0_iter1 <= tmp_2127_reg_41624;
ap_reg_ppstg_tmp_2143_reg_41631_pp0_iter1 <= tmp_2143_reg_41631;
ap_reg_ppstg_tmp_2145_reg_41638_pp0_iter1 <= tmp_2145_reg_41638;
ap_reg_ppstg_tmp_2147_reg_41645_pp0_iter1 <= tmp_2147_reg_41645;
ap_reg_ppstg_tmp_2149_reg_41652_pp0_iter1 <= tmp_2149_reg_41652;
ap_reg_ppstg_tmp_2151_reg_41659_pp0_iter1 <= tmp_2151_reg_41659;
ap_reg_ppstg_tmp_2153_reg_41666_pp0_iter1 <= tmp_2153_reg_41666;
ap_reg_ppstg_tmp_2155_reg_41673_pp0_iter1 <= tmp_2155_reg_41673;
ap_reg_ppstg_tmp_2157_reg_41680_pp0_iter1 <= tmp_2157_reg_41680;
ap_reg_ppstg_tmp_2159_reg_41687_pp0_iter1 <= tmp_2159_reg_41687;
ap_reg_ppstg_tmp_2161_reg_41694_pp0_iter1 <= tmp_2161_reg_41694;
ap_reg_ppstg_tmp_2163_reg_41701_pp0_iter1 <= tmp_2163_reg_41701;
ap_reg_ppstg_tmp_2165_reg_41708_pp0_iter1 <= tmp_2165_reg_41708;
ap_reg_ppstg_tmp_2168_reg_41715_pp0_iter1 <= tmp_2168_reg_41715;
ap_reg_ppstg_tmp_2174_reg_41722_pp0_iter1 <= tmp_2174_reg_41722;
ap_reg_ppstg_tmp_2176_reg_41729_pp0_iter1 <= tmp_2176_reg_41729;
ap_reg_ppstg_tmp_2178_reg_41736_pp0_iter1 <= tmp_2178_reg_41736;
ap_reg_ppstg_tmp_2180_reg_41743_pp0_iter1 <= tmp_2180_reg_41743;
ap_reg_ppstg_tmp_2182_reg_41750_pp0_iter1 <= tmp_2182_reg_41750;
ap_reg_ppstg_tmp_2184_reg_41757_pp0_iter1 <= tmp_2184_reg_41757;
ap_reg_ppstg_tmp_2186_reg_41764_pp0_iter1 <= tmp_2186_reg_41764;
ap_reg_ppstg_tmp_2188_reg_41771_pp0_iter1 <= tmp_2188_reg_41771;
ap_reg_ppstg_tmp_2190_reg_41778_pp0_iter1 <= tmp_2190_reg_41778;
ap_reg_ppstg_tmp_2192_reg_41785_pp0_iter1 <= tmp_2192_reg_41785;
ap_reg_ppstg_tmp_2194_reg_41792_pp0_iter1 <= tmp_2194_reg_41792;
ap_reg_ppstg_tmp_2196_reg_41799_pp0_iter1 <= tmp_2196_reg_41799;
ap_reg_ppstg_tmp_2199_reg_41806_pp0_iter1 <= tmp_2199_reg_41806;
ap_reg_ppstg_tmp_2207_reg_41813_pp0_iter1 <= tmp_2207_reg_41813;
ap_reg_ppstg_tmp_2209_reg_41820_pp0_iter1 <= tmp_2209_reg_41820;
ap_reg_ppstg_tmp_2211_reg_41827_pp0_iter1 <= tmp_2211_reg_41827;
ap_reg_ppstg_tmp_2213_reg_41834_pp0_iter1 <= tmp_2213_reg_41834;
ap_reg_ppstg_tmp_2215_reg_41841_pp0_iter1 <= tmp_2215_reg_41841;
ap_reg_ppstg_tmp_2217_reg_41848_pp0_iter1 <= tmp_2217_reg_41848;
ap_reg_ppstg_tmp_2219_reg_41855_pp0_iter1 <= tmp_2219_reg_41855;
ap_reg_ppstg_tmp_2221_reg_41862_pp0_iter1 <= tmp_2221_reg_41862;
ap_reg_ppstg_tmp_2223_reg_41869_pp0_iter1 <= tmp_2223_reg_41869;
ap_reg_ppstg_tmp_2225_reg_41876_pp0_iter1 <= tmp_2225_reg_41876;
ap_reg_ppstg_tmp_2227_reg_41883_pp0_iter1 <= tmp_2227_reg_41883;
ap_reg_ppstg_tmp_2229_reg_41890_pp0_iter1 <= tmp_2229_reg_41890;
ap_reg_ppstg_tmp_2231_reg_41897_pp0_iter1 <= tmp_2231_reg_41897;
ap_reg_ppstg_tmp_2237_reg_41904_pp0_iter1 <= tmp_2237_reg_41904;
ap_reg_ppstg_tmp_2239_reg_41911_pp0_iter1 <= tmp_2239_reg_41911;
ap_reg_ppstg_tmp_2241_reg_41918_pp0_iter1 <= tmp_2241_reg_41918;
ap_reg_ppstg_tmp_2243_reg_41925_pp0_iter1 <= tmp_2243_reg_41925;
ap_reg_ppstg_tmp_2245_reg_41932_pp0_iter1 <= tmp_2245_reg_41932;
ap_reg_ppstg_tmp_2247_reg_41939_pp0_iter1 <= tmp_2247_reg_41939;
ap_reg_ppstg_tmp_2249_reg_41946_pp0_iter1 <= tmp_2249_reg_41946;
ap_reg_ppstg_tmp_2251_reg_41953_pp0_iter1 <= tmp_2251_reg_41953;
ap_reg_ppstg_tmp_2253_reg_41960_pp0_iter1 <= tmp_2253_reg_41960;
ap_reg_ppstg_tmp_2255_reg_41967_pp0_iter1 <= tmp_2255_reg_41967;
ap_reg_ppstg_tmp_2257_reg_41974_pp0_iter1 <= tmp_2257_reg_41974;
ap_reg_ppstg_tmp_2259_reg_41981_pp0_iter1 <= tmp_2259_reg_41981;
ap_reg_ppstg_tmp_2261_reg_41988_pp0_iter1 <= tmp_2261_reg_41988;
ap_reg_ppstg_tmp_231_reg_40703_pp0_iter1 <= tmp_231_reg_40703;
ap_reg_ppstg_tmp_reg_40698_pp0_iter1 <= tmp_reg_40698;
cpattern_0_0_0_V_read_1_reg_40523 <= cpattern_0_0_0_V_read;
cpattern_0_0_1_V_read_1_reg_40516 <= cpattern_0_0_1_V_read;
cpattern_0_0_2_V_read_1_reg_40509 <= cpattern_0_0_2_V_read;
cpattern_0_0_3_V_read_1_reg_40502 <= cpattern_0_0_3_V_read;
cpattern_0_1_0_V_read_1_reg_40495 <= cpattern_0_1_0_V_read;
cpattern_0_1_1_V_read_1_reg_40488 <= cpattern_0_1_1_V_read;
cpattern_0_1_2_V_read_1_reg_40481 <= cpattern_0_1_2_V_read;
cpattern_0_1_3_V_read_1_reg_40474 <= cpattern_0_1_3_V_read;
cpattern_0_2_0_V_read_1_reg_40467 <= cpattern_0_2_0_V_read;
cpattern_0_2_1_V_read_1_reg_40460 <= cpattern_0_2_1_V_read;
cpattern_0_2_2_V_read_1_reg_40453 <= cpattern_0_2_2_V_read;
cpattern_0_2_3_V_read_1_reg_40446 <= cpattern_0_2_3_V_read;
cpattern_1_0_0_V_read_1_reg_40439 <= cpattern_1_0_0_V_read;
cpattern_1_0_1_V_read_1_reg_40432 <= cpattern_1_0_1_V_read;
cpattern_1_0_2_V_read_1_reg_40425 <= cpattern_1_0_2_V_read;
cpattern_1_0_3_V_read_1_reg_40418 <= cpattern_1_0_3_V_read;
cpattern_1_1_0_V_read_1_reg_40411 <= cpattern_1_1_0_V_read;
cpattern_1_1_1_V_read_1_reg_40404 <= cpattern_1_1_1_V_read;
cpattern_1_1_2_V_read_1_reg_40397 <= cpattern_1_1_2_V_read;
cpattern_1_1_3_V_read_1_reg_40390 <= cpattern_1_1_3_V_read;
cpattern_1_2_0_V_read_1_reg_40383 <= cpattern_1_2_0_V_read;
cpattern_1_2_1_V_read_1_reg_40376 <= cpattern_1_2_1_V_read;
cpattern_1_2_2_V_read_1_reg_40369 <= cpattern_1_2_2_V_read;
cpattern_1_2_3_V_read_1_reg_40362 <= cpattern_1_2_3_V_read;
cpattern_2_0_0_V_read_1_reg_40355 <= cpattern_2_0_0_V_read;
cpattern_2_0_1_V_read_1_reg_40348 <= cpattern_2_0_1_V_read;
cpattern_2_0_2_V_read_1_reg_40341 <= cpattern_2_0_2_V_read;
cpattern_2_0_3_V_read_1_reg_40334 <= cpattern_2_0_3_V_read;
cpattern_2_1_0_V_read_1_reg_40327 <= cpattern_2_1_0_V_read;
cpattern_2_1_1_V_read_1_reg_40320 <= cpattern_2_1_1_V_read;
cpattern_2_1_2_V_read_1_reg_40313 <= cpattern_2_1_2_V_read;
cpattern_2_1_3_V_read_1_reg_40306 <= cpattern_2_1_3_V_read;
cpattern_2_2_0_V_read_1_reg_40299 <= cpattern_2_2_0_V_read;
cpattern_2_2_1_V_read_1_reg_40292 <= cpattern_2_2_1_V_read;
cpattern_2_2_2_V_read_1_reg_40285 <= cpattern_2_2_2_V_read;
cpattern_2_2_3_V_read_1_reg_40278 <= cpattern_2_2_3_V_read;
cpattern_3_0_0_V_read_1_reg_40271 <= cpattern_3_0_0_V_read;
cpattern_3_0_1_V_read_1_reg_40264 <= cpattern_3_0_1_V_read;
cpattern_3_0_2_V_read_1_reg_40257 <= cpattern_3_0_2_V_read;
cpattern_3_0_3_V_read_1_reg_40250 <= cpattern_3_0_3_V_read;
cpattern_3_1_0_V_read_1_reg_40243 <= cpattern_3_1_0_V_read;
cpattern_3_1_1_V_read_1_reg_40236 <= cpattern_3_1_1_V_read;
cpattern_3_1_2_V_read_1_reg_40229 <= cpattern_3_1_2_V_read;
cpattern_3_1_3_V_read_1_reg_40222 <= cpattern_3_1_3_V_read;
cpattern_3_2_0_V_read_1_reg_40215 <= cpattern_3_2_0_V_read;
cpattern_3_2_1_V_read_1_reg_40208 <= cpattern_3_2_1_V_read;
cpattern_3_2_2_V_read_1_reg_40201 <= cpattern_3_2_2_V_read;
cpattern_3_2_3_V_read_1_reg_40194 <= cpattern_3_2_3_V_read;
delta_ph_0_0_0_V_read_1_reg_40187 <= delta_ph_0_0_0_V_read;
delta_ph_0_0_1_V_read_1_reg_40180 <= delta_ph_0_0_1_V_read;
delta_ph_0_0_2_V_read_1_reg_40173 <= delta_ph_0_0_2_V_read;
delta_ph_0_0_3_V_read_1_reg_40166 <= delta_ph_0_0_3_V_read;
delta_ph_0_0_4_V_read_1_reg_40159 <= delta_ph_0_0_4_V_read;
delta_ph_0_0_5_V_read_1_reg_40152 <= delta_ph_0_0_5_V_read;
delta_ph_0_1_0_V_read_1_reg_40145 <= delta_ph_0_1_0_V_read;
delta_ph_0_1_1_V_read_1_reg_40138 <= delta_ph_0_1_1_V_read;
delta_ph_0_1_2_V_read_1_reg_40131 <= delta_ph_0_1_2_V_read;
delta_ph_0_1_3_V_read_1_reg_40124 <= delta_ph_0_1_3_V_read;
delta_ph_0_1_4_V_read_1_reg_40117 <= delta_ph_0_1_4_V_read;
delta_ph_0_1_5_V_read_1_reg_40110 <= delta_ph_0_1_5_V_read;
delta_ph_0_2_0_V_read_1_reg_40103 <= delta_ph_0_2_0_V_read;
delta_ph_0_2_1_V_read_1_reg_40096 <= delta_ph_0_2_1_V_read;
delta_ph_0_2_2_V_read_1_reg_40089 <= delta_ph_0_2_2_V_read;
delta_ph_0_2_3_V_read_1_reg_40082 <= delta_ph_0_2_3_V_read;
delta_ph_0_2_4_V_read_1_reg_40075 <= delta_ph_0_2_4_V_read;
delta_ph_0_2_5_V_read_1_reg_40068 <= delta_ph_0_2_5_V_read;
delta_ph_1_0_0_V_read_1_reg_40061 <= delta_ph_1_0_0_V_read;
delta_ph_1_0_1_V_read_1_reg_40054 <= delta_ph_1_0_1_V_read;
delta_ph_1_0_2_V_read_1_reg_40047 <= delta_ph_1_0_2_V_read;
delta_ph_1_0_3_V_read_1_reg_40040 <= delta_ph_1_0_3_V_read;
delta_ph_1_0_4_V_read_1_reg_40033 <= delta_ph_1_0_4_V_read;
delta_ph_1_0_5_V_read_1_reg_40026 <= delta_ph_1_0_5_V_read;
delta_ph_1_1_0_V_read_1_reg_40019 <= delta_ph_1_1_0_V_read;
delta_ph_1_1_1_V_read_1_reg_40012 <= delta_ph_1_1_1_V_read;
delta_ph_1_1_2_V_read_1_reg_40005 <= delta_ph_1_1_2_V_read;
delta_ph_1_1_3_V_read_1_reg_39998 <= delta_ph_1_1_3_V_read;
delta_ph_1_1_4_V_read_1_reg_39991 <= delta_ph_1_1_4_V_read;
delta_ph_1_1_5_V_read_1_reg_39984 <= delta_ph_1_1_5_V_read;
delta_ph_1_2_0_V_read_1_reg_39977 <= delta_ph_1_2_0_V_read;
delta_ph_1_2_1_V_read_1_reg_39970 <= delta_ph_1_2_1_V_read;
delta_ph_1_2_2_V_read_1_reg_39963 <= delta_ph_1_2_2_V_read;
delta_ph_1_2_3_V_read_1_reg_39956 <= delta_ph_1_2_3_V_read;
delta_ph_1_2_4_V_read_1_reg_39949 <= delta_ph_1_2_4_V_read;
delta_ph_1_2_5_V_read_1_reg_39942 <= delta_ph_1_2_5_V_read;
delta_ph_2_0_0_V_read_1_reg_39935 <= delta_ph_2_0_0_V_read;
delta_ph_2_0_1_V_read_1_reg_39928 <= delta_ph_2_0_1_V_read;
delta_ph_2_0_2_V_read_1_reg_39921 <= delta_ph_2_0_2_V_read;
delta_ph_2_0_3_V_read_1_reg_39914 <= delta_ph_2_0_3_V_read;
delta_ph_2_0_4_V_read_1_reg_39907 <= delta_ph_2_0_4_V_read;
delta_ph_2_0_5_V_read_1_reg_39900 <= delta_ph_2_0_5_V_read;
delta_ph_2_1_0_V_read_1_reg_39893 <= delta_ph_2_1_0_V_read;
delta_ph_2_1_1_V_read_1_reg_39886 <= delta_ph_2_1_1_V_read;
delta_ph_2_1_2_V_read_1_reg_39879 <= delta_ph_2_1_2_V_read;
delta_ph_2_1_3_V_read_1_reg_39872 <= delta_ph_2_1_3_V_read;
delta_ph_2_1_4_V_read_1_reg_39865 <= delta_ph_2_1_4_V_read;
delta_ph_2_1_5_V_read_1_reg_39858 <= delta_ph_2_1_5_V_read;
delta_ph_2_2_0_V_read_1_reg_39851 <= delta_ph_2_2_0_V_read;
delta_ph_2_2_1_V_read_1_reg_39844 <= delta_ph_2_2_1_V_read;
delta_ph_2_2_2_V_read_1_reg_39837 <= delta_ph_2_2_2_V_read;
delta_ph_2_2_3_V_read_1_reg_39830 <= delta_ph_2_2_3_V_read;
delta_ph_2_2_4_V_read_1_reg_39823 <= delta_ph_2_2_4_V_read;
delta_ph_2_2_5_V_read_1_reg_39816 <= delta_ph_2_2_5_V_read;
delta_ph_3_0_0_V_read_1_reg_39809 <= delta_ph_3_0_0_V_read;
delta_ph_3_0_1_V_read_1_reg_39802 <= delta_ph_3_0_1_V_read;
delta_ph_3_0_2_V_read_1_reg_39795 <= delta_ph_3_0_2_V_read;
delta_ph_3_0_3_V_read_1_reg_39788 <= delta_ph_3_0_3_V_read;
delta_ph_3_0_4_V_read_1_reg_39781 <= delta_ph_3_0_4_V_read;
delta_ph_3_0_5_V_read_1_reg_39774 <= delta_ph_3_0_5_V_read;
delta_ph_3_1_0_V_read_1_reg_39767 <= delta_ph_3_1_0_V_read;
delta_ph_3_1_1_V_read_1_reg_39760 <= delta_ph_3_1_1_V_read;
delta_ph_3_1_2_V_read_1_reg_39753 <= delta_ph_3_1_2_V_read;
delta_ph_3_1_3_V_read_1_reg_39746 <= delta_ph_3_1_3_V_read;
delta_ph_3_1_4_V_read_1_reg_39739 <= delta_ph_3_1_4_V_read;
delta_ph_3_1_5_V_read_1_reg_39732 <= delta_ph_3_1_5_V_read;
delta_ph_3_2_0_V_read_1_reg_39725 <= delta_ph_3_2_0_V_read;
delta_ph_3_2_1_V_read_1_reg_39718 <= delta_ph_3_2_1_V_read;
delta_ph_3_2_2_V_read_1_reg_39711 <= delta_ph_3_2_2_V_read;
delta_ph_3_2_3_V_read_1_reg_39704 <= delta_ph_3_2_3_V_read;
delta_ph_3_2_4_V_read_1_reg_39697 <= delta_ph_3_2_4_V_read;
delta_ph_3_2_5_V_read_1_reg_39690 <= delta_ph_3_2_5_V_read;
delta_th_0_0_0_V_read_1_reg_39683 <= delta_th_0_0_0_V_read;
delta_th_0_0_1_V_read_1_reg_39676 <= delta_th_0_0_1_V_read;
delta_th_0_0_2_V_read_1_reg_39669 <= delta_th_0_0_2_V_read;
delta_th_0_0_3_V_read_1_reg_39662 <= delta_th_0_0_3_V_read;
delta_th_0_0_4_V_read_1_reg_39655 <= delta_th_0_0_4_V_read;
delta_th_0_0_5_V_read_1_reg_39648 <= delta_th_0_0_5_V_read;
delta_th_0_1_0_V_read_1_reg_39641 <= delta_th_0_1_0_V_read;
delta_th_0_1_1_V_read_1_reg_39634 <= delta_th_0_1_1_V_read;
delta_th_0_1_2_V_read_1_reg_39627 <= delta_th_0_1_2_V_read;
delta_th_0_1_3_V_read_1_reg_39620 <= delta_th_0_1_3_V_read;
delta_th_0_1_4_V_read_1_reg_39613 <= delta_th_0_1_4_V_read;
delta_th_0_1_5_V_read_1_reg_39606 <= delta_th_0_1_5_V_read;
delta_th_0_2_0_V_read_1_reg_39599 <= delta_th_0_2_0_V_read;
delta_th_0_2_1_V_read_1_reg_39592 <= delta_th_0_2_1_V_read;
delta_th_0_2_2_V_read_1_reg_39585 <= delta_th_0_2_2_V_read;
delta_th_0_2_3_V_read_1_reg_39578 <= delta_th_0_2_3_V_read;
delta_th_0_2_4_V_read_1_reg_39571 <= delta_th_0_2_4_V_read;
delta_th_0_2_5_V_read_1_reg_39564 <= delta_th_0_2_5_V_read;
delta_th_1_0_0_V_read_1_reg_39557 <= delta_th_1_0_0_V_read;
delta_th_1_0_1_V_read_1_reg_39550 <= delta_th_1_0_1_V_read;
delta_th_1_0_2_V_read_1_reg_39543 <= delta_th_1_0_2_V_read;
delta_th_1_0_3_V_read_1_reg_39536 <= delta_th_1_0_3_V_read;
delta_th_1_0_4_V_read_1_reg_39529 <= delta_th_1_0_4_V_read;
delta_th_1_0_5_V_read_1_reg_39522 <= delta_th_1_0_5_V_read;
delta_th_1_1_0_V_read_1_reg_39515 <= delta_th_1_1_0_V_read;
delta_th_1_1_1_V_read_1_reg_39508 <= delta_th_1_1_1_V_read;
delta_th_1_1_2_V_read_1_reg_39501 <= delta_th_1_1_2_V_read;
delta_th_1_1_3_V_read_1_reg_39494 <= delta_th_1_1_3_V_read;
delta_th_1_1_4_V_read_1_reg_39487 <= delta_th_1_1_4_V_read;
delta_th_1_1_5_V_read_1_reg_39480 <= delta_th_1_1_5_V_read;
delta_th_1_2_0_V_read_1_reg_39473 <= delta_th_1_2_0_V_read;
delta_th_1_2_1_V_read_1_reg_39466 <= delta_th_1_2_1_V_read;
delta_th_1_2_2_V_read_1_reg_39459 <= delta_th_1_2_2_V_read;
delta_th_1_2_3_V_read_1_reg_39452 <= delta_th_1_2_3_V_read;
delta_th_1_2_4_V_read_1_reg_39445 <= delta_th_1_2_4_V_read;
delta_th_1_2_5_V_read_1_reg_39438 <= delta_th_1_2_5_V_read;
delta_th_2_0_0_V_read_1_reg_39431 <= delta_th_2_0_0_V_read;
delta_th_2_0_1_V_read_1_reg_39424 <= delta_th_2_0_1_V_read;
delta_th_2_0_2_V_read_1_reg_39417 <= delta_th_2_0_2_V_read;
delta_th_2_0_3_V_read_1_reg_39410 <= delta_th_2_0_3_V_read;
delta_th_2_0_4_V_read_1_reg_39403 <= delta_th_2_0_4_V_read;
delta_th_2_0_5_V_read_1_reg_39396 <= delta_th_2_0_5_V_read;
delta_th_2_1_0_V_read_1_reg_39389 <= delta_th_2_1_0_V_read;
delta_th_2_1_1_V_read_1_reg_39382 <= delta_th_2_1_1_V_read;
delta_th_2_1_2_V_read_1_reg_39375 <= delta_th_2_1_2_V_read;
delta_th_2_1_3_V_read_1_reg_39368 <= delta_th_2_1_3_V_read;
delta_th_2_1_4_V_read_1_reg_39361 <= delta_th_2_1_4_V_read;
delta_th_2_1_5_V_read_1_reg_39354 <= delta_th_2_1_5_V_read;
delta_th_2_2_0_V_read_1_reg_39347 <= delta_th_2_2_0_V_read;
delta_th_2_2_1_V_read_1_reg_39340 <= delta_th_2_2_1_V_read;
delta_th_2_2_2_V_read_1_reg_39333 <= delta_th_2_2_2_V_read;
delta_th_2_2_3_V_read_1_reg_39326 <= delta_th_2_2_3_V_read;
delta_th_2_2_4_V_read_1_reg_39319 <= delta_th_2_2_4_V_read;
delta_th_2_2_5_V_read_1_reg_39312 <= delta_th_2_2_5_V_read;
delta_th_3_0_0_V_read_1_reg_39305 <= delta_th_3_0_0_V_read;
delta_th_3_0_1_V_read_1_reg_39298 <= delta_th_3_0_1_V_read;
delta_th_3_0_2_V_read_1_reg_39291 <= delta_th_3_0_2_V_read;
delta_th_3_0_3_V_read_1_reg_39284 <= delta_th_3_0_3_V_read;
delta_th_3_0_4_V_read_1_reg_39277 <= delta_th_3_0_4_V_read;
delta_th_3_0_5_V_read_1_reg_39270 <= delta_th_3_0_5_V_read;
delta_th_3_1_0_V_read_1_reg_39263 <= delta_th_3_1_0_V_read;
delta_th_3_1_1_V_read_1_reg_39256 <= delta_th_3_1_1_V_read;
delta_th_3_1_2_V_read_1_reg_39249 <= delta_th_3_1_2_V_read;
delta_th_3_1_3_V_read_1_reg_39242 <= delta_th_3_1_3_V_read;
delta_th_3_1_4_V_read_1_reg_39235 <= delta_th_3_1_4_V_read;
delta_th_3_1_5_V_read_1_reg_39228 <= delta_th_3_1_5_V_read;
delta_th_3_2_0_V_read_1_reg_39221 <= delta_th_3_2_0_V_read;
delta_th_3_2_1_V_read_1_reg_39214 <= delta_th_3_2_1_V_read;
delta_th_3_2_2_V_read_1_reg_39207 <= delta_th_3_2_2_V_read;
delta_th_3_2_3_V_read_1_reg_39200 <= delta_th_3_2_3_V_read;
delta_th_3_2_4_V_read_1_reg_39193 <= delta_th_3_2_4_V_read;
delta_th_3_2_5_V_read_1_reg_39186 <= delta_th_3_2_5_V_read;
phi_0_0_V_read_1_reg_40691 <= phi_0_0_V_read;
phi_0_1_V_read_1_reg_40684 <= phi_0_1_V_read;
phi_0_2_V_read_1_reg_40677 <= phi_0_2_V_read;
phi_1_0_V_read_1_reg_40670 <= phi_1_0_V_read;
phi_1_1_V_read_1_reg_40663 <= phi_1_1_V_read;
phi_1_2_V_read_1_reg_40656 <= phi_1_2_V_read;
phi_2_0_V_read_1_reg_40649 <= phi_2_0_V_read;
phi_2_1_V_read_1_reg_40642 <= phi_2_1_V_read;
phi_2_2_V_read_1_reg_40635 <= phi_2_2_V_read;
phi_3_0_V_read_1_reg_40628 <= phi_3_0_V_read;
phi_3_1_V_read_1_reg_40621 <= phi_3_1_V_read;
phi_3_2_V_read_1_reg_40614 <= phi_3_2_V_read;
rank_0_0_V_read_1_reg_39165 <= rank_0_0_V_read;
rank_0_1_V_read_1_reg_39158 <= rank_0_1_V_read;
rank_0_2_V_read_1_reg_39151 <= rank_0_2_V_read;
rank_1_0_V_read_1_reg_39144 <= rank_1_0_V_read;
rank_1_1_V_read_1_reg_39137 <= rank_1_1_V_read;
rank_1_2_V_read_1_reg_39130 <= rank_1_2_V_read;
rank_2_0_V_read_1_reg_39123 <= rank_2_0_V_read;
rank_2_1_V_read_1_reg_39116 <= rank_2_1_V_read;
rank_2_2_V_read_1_reg_39109 <= rank_2_2_V_read;
rank_3_0_V_read_1_reg_39102 <= rank_3_0_V_read;
rank_3_1_V_read_1_reg_39095 <= rank_3_1_V_read;
rank_3_2_V_read_1_reg_39088 <= rank_3_2_V_read;
sign_ph_0_0_V_read_1_reg_39179 <= sign_ph_0_0_V_read;
sign_th_0_0_V_read_1_reg_39172 <= sign_th_0_0_V_read;
theta_0_0_V_read_1_reg_40607 <= theta_0_0_V_read;
theta_0_1_V_read_1_reg_40600 <= theta_0_1_V_read;
theta_0_2_V_read_1_reg_40593 <= theta_0_2_V_read;
theta_1_0_V_read_1_reg_40586 <= theta_1_0_V_read;
theta_1_1_V_read_1_reg_40579 <= theta_1_1_V_read;
theta_1_2_V_read_1_reg_40572 <= theta_1_2_V_read;
theta_2_0_V_read_1_reg_40565 <= theta_2_0_V_read;
theta_2_1_V_read_1_reg_40558 <= theta_2_1_V_read;
theta_2_2_V_read_1_reg_40551 <= theta_2_2_V_read;
theta_3_0_V_read_1_reg_40544 <= theta_3_0_V_read;
theta_3_1_V_read_1_reg_40537 <= theta_3_1_V_read;
theta_3_2_V_read_1_reg_40530 <= theta_3_2_V_read;
tmp_1150_reg_40708 <= si_0_1_V_read[ap_const_lv32_1];
tmp_1164_reg_40715 <= si_0_1_V_read[ap_const_lv32_2];
tmp_1167_reg_40722 <= si_0_2_V_read[ap_const_lv32_1];
tmp_1169_reg_40729 <= si_0_2_V_read[ap_const_lv32_2];
tmp_1170_reg_40736 <= si_1_0_V_read[ap_const_lv32_1];
tmp_1172_reg_40743 <= si_1_0_V_read[ap_const_lv32_2];
tmp_1173_reg_40750 <= si_1_1_V_read[ap_const_lv32_1];
tmp_1188_reg_40757 <= si_1_1_V_read[ap_const_lv32_2];
tmp_1190_reg_40764 <= si_1_2_V_read[ap_const_lv32_1];
tmp_1191_reg_40771 <= si_1_2_V_read[ap_const_lv32_2];
tmp_1193_reg_40778 <= si_2_0_V_read[ap_const_lv32_1];
tmp_1195_reg_40785 <= si_2_0_V_read[ap_const_lv32_2];
tmp_1197_reg_40792 <= si_2_1_V_read[ap_const_lv32_1];
tmp_1199_reg_40799 <= si_2_1_V_read[ap_const_lv32_2];
tmp_1212_reg_40806 <= si_2_2_V_read[ap_const_lv32_1];
tmp_1216_reg_40813 <= si_2_2_V_read[ap_const_lv32_2];
tmp_1217_reg_40820 <= si_3_0_V_read[ap_const_lv32_1];
tmp_1219_reg_40827 <= si_3_0_V_read[ap_const_lv32_2];
tmp_1222_reg_40834 <= si_3_1_V_read[ap_const_lv32_1];
tmp_1236_reg_40841 <= si_3_1_V_read[ap_const_lv32_2];
tmp_1239_reg_40848 <= si_3_2_V_read[ap_const_lv32_1];
tmp_1253_reg_40855 <= si_3_2_V_read[ap_const_lv32_2];
tmp_1402_10_reg_40983 <= tmp_1402_10_fu_15792_p2;
tmp_1402_1_reg_40869 <= tmp_1402_1_fu_9302_p2;
tmp_1402_2_reg_40884 <= tmp_1402_2_fu_9978_p2;
tmp_1402_3_reg_40895 <= tmp_1402_3_fu_10624_p2;
tmp_1402_4_reg_40906 <= tmp_1402_4_fu_11270_p2;
tmp_1402_5_reg_40917 <= tmp_1402_5_fu_11916_p2;
tmp_1402_6_reg_40928 <= tmp_1402_6_fu_12562_p2;
tmp_1402_7_reg_40939 <= tmp_1402_7_fu_13208_p2;
tmp_1402_8_reg_40950 <= tmp_1402_8_fu_13854_p2;
tmp_1402_9_reg_40961 <= tmp_1402_9_fu_14500_p2;
tmp_1402_s_reg_40972 <= tmp_1402_s_fu_15146_p2;
tmp_1623_reg_40879[5 : 2] <= tmp_1623_fu_9338_p1[5 : 2];
tmp_1644_reg_40889 <= tmp_1644_fu_9984_p1;
tmp_1671_reg_40900 <= tmp_1671_fu_10630_p1;
tmp_1698_reg_40911 <= tmp_1698_fu_11276_p1;
tmp_1725_reg_40922 <= tmp_1725_fu_11922_p1;
tmp_1752_reg_40933 <= tmp_1752_fu_12568_p1;
tmp_1779_reg_40944 <= tmp_1779_fu_13214_p1;
tmp_1806_reg_40955 <= tmp_1806_fu_13860_p1;
tmp_1833_reg_40966 <= tmp_1833_fu_14506_p1;
tmp_1860_reg_40977 <= tmp_1860_fu_15152_p1;
tmp_1887_reg_40988 <= tmp_1887_fu_15798_p1;
tmp_1905_reg_40994 <= tmp_1905_fu_15802_p1;
tmp_1907_reg_41001 <= tmp_1907_fu_15806_p1;
tmp_1909_reg_41008 <= sign_ph_1_0_V_read[ap_const_lv32_1];
tmp_1911_reg_41015 <= sign_th_1_0_V_read[ap_const_lv32_1];
tmp_1913_reg_41022 <= sign_ph_1_0_V_read[ap_const_lv32_2];
tmp_1915_reg_41029 <= sign_th_1_0_V_read[ap_const_lv32_2];
tmp_1917_reg_41036 <= sign_ph_1_0_V_read[ap_const_lv32_3];
tmp_1919_reg_41043 <= sign_th_1_0_V_read[ap_const_lv32_3];
tmp_1921_reg_41050 <= sign_ph_1_0_V_read[ap_const_lv32_4];
tmp_1923_reg_41057 <= sign_th_1_0_V_read[ap_const_lv32_4];
tmp_1925_reg_41064 <= sign_ph_1_0_V_read[ap_const_lv32_5];
tmp_1927_reg_41071 <= sign_th_1_0_V_read[ap_const_lv32_5];
tmp_1929_reg_41078 <= tmp_1929_fu_15890_p1;
tmp_1936_reg_41085 <= tmp_1936_fu_15894_p1;
tmp_1938_reg_41092 <= tmp_1938_fu_15898_p1;
tmp_1940_reg_41099 <= sign_ph_2_0_V_read[ap_const_lv32_1];
tmp_1942_reg_41106 <= sign_th_2_0_V_read[ap_const_lv32_1];
tmp_1944_reg_41113 <= sign_ph_2_0_V_read[ap_const_lv32_2];
tmp_1946_reg_41120 <= sign_th_2_0_V_read[ap_const_lv32_2];
tmp_1948_reg_41127 <= sign_ph_2_0_V_read[ap_const_lv32_3];
tmp_1950_reg_41134 <= sign_th_2_0_V_read[ap_const_lv32_3];
tmp_1952_reg_41141 <= sign_ph_2_0_V_read[ap_const_lv32_4];
tmp_1954_reg_41148 <= sign_th_2_0_V_read[ap_const_lv32_4];
tmp_1956_reg_41155 <= sign_ph_2_0_V_read[ap_const_lv32_5];
tmp_1958_reg_41162 <= sign_th_2_0_V_read[ap_const_lv32_5];
tmp_1960_reg_41169 <= tmp_1960_fu_15982_p1;
tmp_1966_reg_41176 <= tmp_1966_fu_15986_p1;
tmp_1968_reg_41183 <= tmp_1968_fu_15990_p1;
tmp_1970_reg_41190 <= sign_ph_3_0_V_read[ap_const_lv32_1];
tmp_1972_reg_41197 <= sign_th_3_0_V_read[ap_const_lv32_1];
tmp_1974_reg_41204 <= sign_ph_3_0_V_read[ap_const_lv32_2];
tmp_1976_reg_41211 <= sign_th_3_0_V_read[ap_const_lv32_2];
tmp_1978_reg_41218 <= sign_ph_3_0_V_read[ap_const_lv32_3];
tmp_1980_reg_41225 <= sign_th_3_0_V_read[ap_const_lv32_3];
tmp_1982_reg_41232 <= sign_ph_3_0_V_read[ap_const_lv32_4];
tmp_1984_reg_41239 <= sign_th_3_0_V_read[ap_const_lv32_4];
tmp_1986_reg_41246 <= sign_ph_3_0_V_read[ap_const_lv32_5];
tmp_1988_reg_41253 <= sign_th_3_0_V_read[ap_const_lv32_5];
tmp_1990_reg_41260 <= tmp_1990_fu_16074_p1;
tmp_2008_reg_41267 <= tmp_2008_fu_16078_p1;
tmp_2010_reg_41274 <= tmp_2010_fu_16082_p1;
tmp_2012_reg_41281 <= sign_ph_0_1_V_read[ap_const_lv32_1];
tmp_2014_reg_41288 <= sign_th_0_1_V_read[ap_const_lv32_1];
tmp_2016_reg_41295 <= sign_ph_0_1_V_read[ap_const_lv32_2];
tmp_2018_reg_41302 <= sign_th_0_1_V_read[ap_const_lv32_2];
tmp_2020_reg_41309 <= sign_ph_0_1_V_read[ap_const_lv32_3];
tmp_2022_reg_41316 <= sign_th_0_1_V_read[ap_const_lv32_3];
tmp_2024_reg_41323 <= sign_ph_0_1_V_read[ap_const_lv32_4];
tmp_2026_reg_41330 <= sign_th_0_1_V_read[ap_const_lv32_4];
tmp_2028_reg_41337 <= sign_ph_0_1_V_read[ap_const_lv32_5];
tmp_2030_reg_41344 <= sign_th_0_1_V_read[ap_const_lv32_5];
tmp_2034_reg_41351 <= tmp_2034_fu_16166_p1;
tmp_2040_reg_41358 <= tmp_2040_fu_16170_p1;
tmp_2042_reg_41365 <= tmp_2042_fu_16174_p1;
tmp_2044_reg_41372 <= sign_ph_1_1_V_read[ap_const_lv32_1];
tmp_2046_reg_41379 <= sign_th_1_1_V_read[ap_const_lv32_1];
tmp_2048_reg_41386 <= sign_ph_1_1_V_read[ap_const_lv32_2];
tmp_2050_reg_41393 <= sign_th_1_1_V_read[ap_const_lv32_2];
tmp_2052_reg_41400 <= sign_ph_1_1_V_read[ap_const_lv32_3];
tmp_2054_reg_41407 <= sign_th_1_1_V_read[ap_const_lv32_3];
tmp_2056_reg_41414 <= sign_ph_1_1_V_read[ap_const_lv32_4];
tmp_2058_reg_41421 <= sign_th_1_1_V_read[ap_const_lv32_4];
tmp_2060_reg_41428 <= sign_ph_1_1_V_read[ap_const_lv32_5];
tmp_2062_reg_41435 <= sign_th_1_1_V_read[ap_const_lv32_5];
tmp_2065_reg_41442 <= tmp_2065_fu_16258_p1;
tmp_2073_reg_41449 <= tmp_2073_fu_16262_p1;
tmp_2075_reg_41456 <= tmp_2075_fu_16266_p1;
tmp_2077_reg_41463 <= sign_ph_2_1_V_read[ap_const_lv32_1];
tmp_2079_reg_41470 <= sign_th_2_1_V_read[ap_const_lv32_1];
tmp_2081_reg_41477 <= sign_ph_2_1_V_read[ap_const_lv32_2];
tmp_2083_reg_41484 <= sign_th_2_1_V_read[ap_const_lv32_2];
tmp_2085_reg_41491 <= sign_ph_2_1_V_read[ap_const_lv32_3];
tmp_2087_reg_41498 <= sign_th_2_1_V_read[ap_const_lv32_3];
tmp_2089_reg_41505 <= sign_ph_2_1_V_read[ap_const_lv32_4];
tmp_2091_reg_41512 <= sign_th_2_1_V_read[ap_const_lv32_4];
tmp_2093_reg_41519 <= sign_ph_2_1_V_read[ap_const_lv32_5];
tmp_2095_reg_41526 <= sign_th_2_1_V_read[ap_const_lv32_5];
tmp_2097_reg_41533 <= tmp_2097_fu_16350_p1;
tmp_2103_reg_41540 <= tmp_2103_fu_16354_p1;
tmp_2105_reg_41547 <= tmp_2105_fu_16358_p1;
tmp_2107_reg_41554 <= sign_ph_3_1_V_read[ap_const_lv32_1];
tmp_2109_reg_41561 <= sign_th_3_1_V_read[ap_const_lv32_1];
tmp_2111_reg_41568 <= sign_ph_3_1_V_read[ap_const_lv32_2];
tmp_2113_reg_41575 <= sign_th_3_1_V_read[ap_const_lv32_2];
tmp_2115_reg_41582 <= sign_ph_3_1_V_read[ap_const_lv32_3];
tmp_2117_reg_41589 <= sign_th_3_1_V_read[ap_const_lv32_3];
tmp_2119_reg_41596 <= sign_ph_3_1_V_read[ap_const_lv32_4];
tmp_2121_reg_41603 <= sign_th_3_1_V_read[ap_const_lv32_4];
tmp_2123_reg_41610 <= sign_ph_3_1_V_read[ap_const_lv32_5];
tmp_2125_reg_41617 <= sign_th_3_1_V_read[ap_const_lv32_5];
tmp_2127_reg_41624 <= tmp_2127_fu_16442_p1;
tmp_2143_reg_41631 <= tmp_2143_fu_16446_p1;
tmp_2145_reg_41638 <= tmp_2145_fu_16450_p1;
tmp_2147_reg_41645 <= sign_ph_0_2_V_read[ap_const_lv32_1];
tmp_2149_reg_41652 <= sign_th_0_2_V_read[ap_const_lv32_1];
tmp_2151_reg_41659 <= sign_ph_0_2_V_read[ap_const_lv32_2];
tmp_2153_reg_41666 <= sign_th_0_2_V_read[ap_const_lv32_2];
tmp_2155_reg_41673 <= sign_ph_0_2_V_read[ap_const_lv32_3];
tmp_2157_reg_41680 <= sign_th_0_2_V_read[ap_const_lv32_3];
tmp_2159_reg_41687 <= sign_ph_0_2_V_read[ap_const_lv32_4];
tmp_2161_reg_41694 <= sign_th_0_2_V_read[ap_const_lv32_4];
tmp_2163_reg_41701 <= sign_ph_0_2_V_read[ap_const_lv32_5];
tmp_2165_reg_41708 <= sign_th_0_2_V_read[ap_const_lv32_5];
tmp_2168_reg_41715 <= tmp_2168_fu_16534_p1;
tmp_2174_reg_41722 <= tmp_2174_fu_16538_p1;
tmp_2176_reg_41729 <= tmp_2176_fu_16542_p1;
tmp_2178_reg_41736 <= sign_ph_1_2_V_read[ap_const_lv32_1];
tmp_2180_reg_41743 <= sign_th_1_2_V_read[ap_const_lv32_1];
tmp_2182_reg_41750 <= sign_ph_1_2_V_read[ap_const_lv32_2];
tmp_2184_reg_41757 <= sign_th_1_2_V_read[ap_const_lv32_2];
tmp_2186_reg_41764 <= sign_ph_1_2_V_read[ap_const_lv32_3];
tmp_2188_reg_41771 <= sign_th_1_2_V_read[ap_const_lv32_3];
tmp_2190_reg_41778 <= sign_ph_1_2_V_read[ap_const_lv32_4];
tmp_2192_reg_41785 <= sign_th_1_2_V_read[ap_const_lv32_4];
tmp_2194_reg_41792 <= sign_ph_1_2_V_read[ap_const_lv32_5];
tmp_2196_reg_41799 <= sign_th_1_2_V_read[ap_const_lv32_5];
tmp_2199_reg_41806 <= tmp_2199_fu_16626_p1;
tmp_2207_reg_41813 <= tmp_2207_fu_16630_p1;
tmp_2209_reg_41820 <= tmp_2209_fu_16634_p1;
tmp_2211_reg_41827 <= sign_ph_2_2_V_read[ap_const_lv32_1];
tmp_2213_reg_41834 <= sign_th_2_2_V_read[ap_const_lv32_1];
tmp_2215_reg_41841 <= sign_ph_2_2_V_read[ap_const_lv32_2];
tmp_2217_reg_41848 <= sign_th_2_2_V_read[ap_const_lv32_2];
tmp_2219_reg_41855 <= sign_ph_2_2_V_read[ap_const_lv32_3];
tmp_2221_reg_41862 <= sign_th_2_2_V_read[ap_const_lv32_3];
tmp_2223_reg_41869 <= sign_ph_2_2_V_read[ap_const_lv32_4];
tmp_2225_reg_41876 <= sign_th_2_2_V_read[ap_const_lv32_4];
tmp_2227_reg_41883 <= sign_ph_2_2_V_read[ap_const_lv32_5];
tmp_2229_reg_41890 <= sign_th_2_2_V_read[ap_const_lv32_5];
tmp_2231_reg_41897 <= tmp_2231_fu_16718_p1;
tmp_2237_reg_41904 <= tmp_2237_fu_16722_p1;
tmp_2239_reg_41911 <= tmp_2239_fu_16726_p1;
tmp_2241_reg_41918 <= sign_ph_3_2_V_read[ap_const_lv32_1];
tmp_2243_reg_41925 <= sign_th_3_2_V_read[ap_const_lv32_1];
tmp_2245_reg_41932 <= sign_ph_3_2_V_read[ap_const_lv32_2];
tmp_2247_reg_41939 <= sign_th_3_2_V_read[ap_const_lv32_2];
tmp_2249_reg_41946 <= sign_ph_3_2_V_read[ap_const_lv32_3];
tmp_2251_reg_41953 <= sign_th_3_2_V_read[ap_const_lv32_3];
tmp_2253_reg_41960 <= sign_ph_3_2_V_read[ap_const_lv32_4];
tmp_2255_reg_41967 <= sign_th_3_2_V_read[ap_const_lv32_4];
tmp_2257_reg_41974 <= sign_ph_3_2_V_read[ap_const_lv32_5];
tmp_2259_reg_41981 <= sign_th_3_2_V_read[ap_const_lv32_5];
tmp_2261_reg_41988 <= tmp_2261_fu_16810_p1;
tmp_231_reg_40703 <= {{si_0_0_V_read[ap_const_lv32_2 : ap_const_lv32_1]}};
tmp_335_reg_40874[6 : 2] <= tmp_335_fu_9332_p2[6 : 2];
tmp_reg_40698 <= tmp_fu_2562_p1;
winner_V1_reg_40862 <= winner_V1_fu_8658_p3;
winner_V_7_reg_41995 <= winner_V_7_fu_17481_p3;
end
end
assign ap_return_0 = bt_phi_V_s_fu_23058_p2;
assign ap_return_1 = bt_phi_V37_s_fu_29895_p2;
assign ap_return_10 = bt_cpattern_V41_s_fu_30041_p2;
assign ap_return_100 = bt_ci_V57167_s_fu_31537_p3;
assign ap_return_101 = bt_ci_V57168_s_fu_31569_p3;
assign ap_return_102 = ap_const_lv4_0;
assign ap_return_103 = bt_ci_V58_s_fu_38342_p2;
assign ap_return_104 = bt_ci_V58_s_fu_38342_p2;
assign ap_return_105 = bt_ci_V58171_s_fu_38374_p3;
assign ap_return_106 = bt_ci_V58172_s_fu_38406_p3;
assign ap_return_107 = ap_const_lv4_0;
assign ap_return_108 = bt_si_V_10_fu_24740_p3;
assign ap_return_109 = bt_si_V59_10_fu_31577_p3;
assign ap_return_11 = bt_cpattern_V41102_s_fu_30114_p2;
assign ap_return_110 = bt_si_V60_10_fu_38414_p3;
assign ap_return_12 = bt_cpattern_V41103_s_fu_30187_p2;
assign ap_return_13 = bt_cpattern_V41104_s_fu_30260_p2;
assign ap_return_14 = bt_cpattern_V42_s_fu_36878_p2;
assign ap_return_15 = bt_cpattern_V42105_s_fu_36951_p2;
assign ap_return_16 = bt_cpattern_V42106_s_fu_37024_p2;
assign ap_return_17 = bt_cpattern_V42107_s_fu_37097_p2;
assign ap_return_18 = bt_delta_ph_V_s_fu_23496_p2;
assign ap_return_19 = bt_delta_ph_V108_s_fu_23569_p2;
assign ap_return_2 = bt_phi_V38_s_fu_36732_p2;
assign ap_return_20 = bt_delta_ph_V109_s_fu_23642_p2;
assign ap_return_21 = bt_delta_ph_V110_s_fu_23715_p2;
assign ap_return_22 = bt_delta_ph_V111_s_fu_23788_p2;
assign ap_return_23 = bt_delta_ph_V112_s_fu_23861_p2;
assign ap_return_24 = bt_delta_ph_V43_s_fu_30333_p2;
assign ap_return_25 = bt_delta_ph_V43113_s_fu_30406_p2;
assign ap_return_26 = bt_delta_ph_V43114_s_fu_30479_p2;
assign ap_return_27 = bt_delta_ph_V43115_s_fu_30552_p2;
assign ap_return_28 = bt_delta_ph_V43116_s_fu_30625_p2;
assign ap_return_29 = bt_delta_ph_V43117_s_fu_30698_p2;
assign ap_return_3 = bt_theta_V_s_fu_23131_p2;
assign ap_return_30 = bt_delta_ph_V44_s_fu_37170_p2;
assign ap_return_31 = bt_delta_ph_V44118_s_fu_37243_p2;
assign ap_return_32 = bt_delta_ph_V44119_s_fu_37316_p2;
assign ap_return_33 = bt_delta_ph_V44120_s_fu_37389_p2;
assign ap_return_34 = bt_delta_ph_V44121_s_fu_37462_p2;
assign ap_return_35 = bt_delta_ph_V44122_s_fu_37535_p2;
assign ap_return_36 = bt_delta_th_V_s_fu_23934_p2;
assign ap_return_37 = bt_delta_th_V123_s_fu_24007_p2;
assign ap_return_38 = bt_delta_th_V124_s_fu_24080_p2;
assign ap_return_39 = bt_delta_th_V125_s_fu_24153_p2;
assign ap_return_4 = bt_theta_V39_s_fu_29968_p2;
assign ap_return_40 = bt_delta_th_V126_s_fu_24226_p2;
assign ap_return_41 = bt_delta_th_V127_s_fu_24299_p2;
assign ap_return_42 = bt_delta_th_V45_s_fu_30771_p2;
assign ap_return_43 = bt_delta_th_V45128_s_fu_30844_p2;
assign ap_return_44 = bt_delta_th_V45129_s_fu_30917_p2;
assign ap_return_45 = bt_delta_th_V45130_s_fu_30990_p2;
assign ap_return_46 = bt_delta_th_V45131_s_fu_31063_p2;
assign ap_return_47 = bt_delta_th_V45132_s_fu_31136_p2;
assign ap_return_48 = bt_delta_th_V46_s_fu_37608_p2;
assign ap_return_49 = bt_delta_th_V46133_s_fu_37681_p2;
assign ap_return_5 = bt_theta_V40_s_fu_36805_p2;
assign ap_return_50 = bt_delta_th_V46134_s_fu_37754_p2;
assign ap_return_51 = bt_delta_th_V46135_s_fu_37827_p2;
assign ap_return_52 = bt_delta_th_V46136_s_fu_37900_p2;
assign ap_return_53 = bt_delta_th_V46137_s_fu_37973_p2;
assign ap_return_54 = bt_sign_ph_V_10_fu_24305_p3;
assign ap_return_55 = bt_sign_ph_V47_10_fu_31142_p3;
assign ap_return_56 = bt_sign_ph_V48_10_fu_37979_p3;
assign ap_return_57 = bt_sign_th_V_10_fu_24313_p3;
assign ap_return_58 = bt_sign_th_V49_10_fu_31150_p3;
assign ap_return_59 = bt_sign_th_V50_10_fu_37987_p3;
assign ap_return_6 = bt_cpattern_V_s_fu_23204_p2;
assign ap_return_60 = bt_rank_V_s_fu_24388_p2;
assign ap_return_61 = bt_rank_V51_s_fu_31225_p2;
assign ap_return_62 = bt_rank_V52_s_fu_38062_p2;
assign ap_return_63 = ap_const_lv2_0;
assign ap_return_64 = ap_const_lv2_0;
assign ap_return_65 = ap_const_lv2_0;
assign ap_return_66 = ap_const_lv2_0;
assign ap_return_67 = ap_const_lv2_0;
assign ap_return_68 = ap_const_lv2_0;
assign ap_return_69 = ap_const_lv2_0;
assign ap_return_7 = bt_cpattern_V99_s_fu_23277_p2;
assign ap_return_70 = ap_const_lv2_0;
assign ap_return_71 = ap_const_lv2_0;
assign ap_return_72 = ap_const_lv2_0;
assign ap_return_73 = ap_const_lv2_0;
assign ap_return_74 = ap_const_lv2_0;
assign ap_return_75 = ap_const_lv2_0;
assign ap_return_76 = ap_const_lv2_0;
assign ap_return_77 = ap_const_lv2_0;
assign ap_return_78 = bt_hi_V_s_fu_24480_p2;
assign ap_return_79 = bt_hi_V_s_fu_24480_p2;
assign ap_return_8 = bt_cpattern_V100_s_fu_23350_p2;
assign ap_return_80 = bt_hi_V151_s_fu_24586_p2;
assign ap_return_81 = bt_hi_V152_s_fu_24640_p2;
assign ap_return_82 = ap_const_lv2_0;
assign ap_return_83 = bt_hi_V55_s_fu_31317_p2;
assign ap_return_84 = bt_hi_V55_s_fu_31317_p2;
assign ap_return_85 = bt_hi_V55155_s_fu_31423_p2;
assign ap_return_86 = bt_hi_V55156_s_fu_31477_p2;
assign ap_return_87 = ap_const_lv2_0;
assign ap_return_88 = bt_hi_V56_s_fu_38154_p2;
assign ap_return_89 = bt_hi_V56_s_fu_38154_p2;
assign ap_return_9 = bt_cpattern_V101_s_fu_23423_p2;
assign ap_return_90 = bt_hi_V56159_s_fu_38260_p2;
assign ap_return_91 = bt_hi_V56160_s_fu_38314_p2;
assign ap_return_92 = ap_const_lv2_0;
assign ap_return_93 = bt_ci_V_s_fu_24668_p2;
assign ap_return_94 = bt_ci_V_s_fu_24668_p2;
assign ap_return_95 = bt_ci_V163_s_fu_24700_p3;
assign ap_return_96 = bt_ci_V164_s_fu_24732_p3;
assign ap_return_97 = ap_const_lv4_0;
assign ap_return_98 = bt_ci_V57_s_fu_31505_p2;
assign ap_return_99 = bt_ci_V57_s_fu_31505_p2;
assign bt_ci_V163_3_fu_19382_p3 = {{1'b0}, {tmp_2002_fu_19376_p2}};
assign bt_ci_V163_4_fu_19920_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? r_V_177_0_4_2_fu_19685_p3 : bt_ci_V163_3_fu_19382_p3);
assign bt_ci_V163_5_fu_20408_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? r_V_177_0_5_2_fu_20187_p3 : bt_ci_V163_4_fu_19920_p3);
assign bt_ci_V163_7_fu_21304_p3 = {{tmp_2135_fu_21296_p3}, {tmp_2134_fu_21290_p2}};
assign bt_ci_V163_8_fu_21824_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? r_V_177_0_8_2_fu_21597_p3 : bt_ci_V163_7_fu_21304_p3);
assign bt_ci_V163_9_fu_22312_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? r_V_177_0_9_2_fu_22091_p3 : bt_ci_V163_8_fu_21824_p3);
assign bt_ci_V163_s_fu_24700_p3 = {{tmp_2278_fu_24692_p3}, {tmp_2277_fu_24686_p2}};
assign bt_ci_V164_3_fu_19426_p3 = {{1'b0}, {tmp_2005_fu_19420_p2}};
assign bt_ci_V164_4_fu_19928_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? r_V_177_0_4_3_fu_19712_p3 : bt_ci_V164_3_fu_19426_p3);
assign bt_ci_V164_7_fu_21350_p3 = {{tmp_2139_fu_21336_p3}, {tmp_2140_fu_21344_p2}};
assign bt_ci_V164_8_fu_21832_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? r_V_177_0_8_3_fu_21624_p3 : bt_ci_V164_7_fu_21350_p3);
assign bt_ci_V164_s_fu_24732_p3 = {{tmp_2281_fu_24718_p3}, {tmp_2282_fu_24726_p2}};
assign bt_ci_V57167_3_fu_26219_p3 = {{1'b0}, {tmp_2343_fu_26213_p2}};
assign bt_ci_V57167_4_fu_26757_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? r_V_177_1_4_2_fu_26522_p3 : bt_ci_V57167_3_fu_26219_p3);
assign bt_ci_V57167_5_fu_27245_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? r_V_177_1_5_2_fu_27024_p3 : bt_ci_V57167_4_fu_26757_p3);
assign bt_ci_V57167_7_fu_28141_p3 = {{tmp_2424_fu_28133_p3}, {tmp_2423_fu_28127_p2}};
assign bt_ci_V57167_8_fu_28661_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? r_V_177_1_8_2_fu_28434_p3 : bt_ci_V57167_7_fu_28141_p3);
assign bt_ci_V57167_9_fu_29149_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? r_V_177_1_9_2_fu_28928_p3 : bt_ci_V57167_8_fu_28661_p3);
assign bt_ci_V57167_s_fu_31537_p3 = {{tmp_2515_fu_31529_p3}, {tmp_2514_fu_31523_p2}};
assign bt_ci_V57168_3_fu_26263_p3 = {{1'b0}, {tmp_2346_fu_26257_p2}};
assign bt_ci_V57168_4_fu_26765_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? r_V_177_1_4_3_fu_26549_p3 : bt_ci_V57168_3_fu_26263_p3);
assign bt_ci_V57168_7_fu_28187_p3 = {{tmp_2428_fu_28173_p3}, {tmp_2429_fu_28181_p2}};
assign bt_ci_V57168_8_fu_28669_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? r_V_177_1_8_3_fu_28461_p3 : bt_ci_V57168_7_fu_28187_p3);
assign bt_ci_V57168_s_fu_31569_p3 = {{tmp_2518_fu_31555_p3}, {tmp_2519_fu_31563_p2}};
assign bt_ci_V57_3_fu_26177_p4 = {{{{1'b0}, {tmp_2339_fu_26167_p4}}}, {tmp_2338_fu_26161_p2}};
assign bt_ci_V57_4_fu_26749_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? r_V_177_1_4_fu_26497_p4 : bt_ci_V57_3_fu_26177_p4);
assign bt_ci_V57_5_fu_27237_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? r_V_177_1_5_fu_26989_p3 : bt_ci_V57_4_fu_26749_p3);
assign bt_ci_V57_7_fu_28095_p2 = (tmp1392_fu_28087_p3 | bt_ci_V57_5_fu_27237_p3);
assign bt_ci_V57_8_fu_28653_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? r_V_177_1_8_fu_28411_p3 : bt_ci_V57_7_fu_28095_p2);
assign bt_ci_V57_9_fu_29141_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? r_V_177_1_9_fu_28893_p3 : bt_ci_V57_8_fu_28653_p3);
assign bt_ci_V57_s_fu_31505_p2 = (tmp1616_fu_31497_p3 | bt_ci_V57_9_fu_29141_p3);
assign bt_ci_V58171_3_fu_33056_p3 = {{1'b0}, {tmp_2580_fu_33050_p2}};
assign bt_ci_V58171_4_fu_33594_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? r_V_177_2_4_2_fu_33359_p3 : bt_ci_V58171_3_fu_33056_p3);
assign bt_ci_V58171_5_fu_34082_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? r_V_177_2_5_2_fu_33861_p3 : bt_ci_V58171_4_fu_33594_p3);
assign bt_ci_V58171_7_fu_34978_p3 = {{tmp_2661_fu_34970_p3}, {tmp_2660_fu_34964_p2}};
assign bt_ci_V58171_8_fu_35498_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? r_V_177_2_8_2_fu_35271_p3 : bt_ci_V58171_7_fu_34978_p3);
assign bt_ci_V58171_9_fu_35986_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? r_V_177_2_9_2_fu_35765_p3 : bt_ci_V58171_8_fu_35498_p3);
assign bt_ci_V58171_s_fu_38374_p3 = {{tmp_2752_fu_38366_p3}, {tmp_2751_fu_38360_p2}};
assign bt_ci_V58172_3_fu_33100_p3 = {{1'b0}, {tmp_2583_fu_33094_p2}};
assign bt_ci_V58172_4_fu_33602_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? r_V_177_2_4_3_fu_33386_p3 : bt_ci_V58172_3_fu_33100_p3);
assign bt_ci_V58172_7_fu_35024_p3 = {{tmp_2665_fu_35010_p3}, {tmp_2666_fu_35018_p2}};
assign bt_ci_V58172_8_fu_35506_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? r_V_177_2_8_3_fu_35298_p3 : bt_ci_V58172_7_fu_35024_p3);
assign bt_ci_V58172_s_fu_38406_p3 = {{tmp_2755_fu_38392_p3}, {tmp_2756_fu_38400_p2}};
assign bt_ci_V58_3_fu_33014_p4 = {{{{1'b0}, {tmp_2576_fu_33004_p4}}}, {tmp_2575_fu_32998_p2}};
assign bt_ci_V58_4_fu_33586_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? r_V_177_2_4_fu_33334_p4 : bt_ci_V58_3_fu_33014_p4);
assign bt_ci_V58_5_fu_34074_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? r_V_177_2_5_fu_33826_p3 : bt_ci_V58_4_fu_33586_p3);
assign bt_ci_V58_7_fu_34932_p2 = (tmp1624_fu_34924_p3 | bt_ci_V58_5_fu_34074_p3);
assign bt_ci_V58_8_fu_35490_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? r_V_177_2_8_fu_35248_p3 : bt_ci_V58_7_fu_34932_p2);
assign bt_ci_V58_9_fu_35978_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? r_V_177_2_9_fu_35730_p3 : bt_ci_V58_8_fu_35490_p3);
assign bt_ci_V58_s_fu_38342_p2 = (tmp1848_fu_38334_p3 | bt_ci_V58_9_fu_35978_p3);
assign bt_ci_V_3_fu_19336_p4 = {{{{1'b0}, {tmp_1997_fu_19326_p4}}}, {tmp_1996_fu_19320_p2}};
assign bt_ci_V_4_fu_19912_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? r_V_177_0_4_fu_19660_p4 : bt_ci_V_3_fu_19336_p4);
assign bt_ci_V_5_fu_20400_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? r_V_177_0_5_fu_20152_p3 : bt_ci_V_4_fu_19912_p3);
assign bt_ci_V_7_fu_21258_p2 = (tmp1065_fu_21250_p3 | bt_ci_V_5_fu_20400_p3);
assign bt_ci_V_8_fu_21816_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? r_V_177_0_8_fu_21574_p3 : bt_ci_V_7_fu_21258_p2);
assign bt_ci_V_9_fu_22304_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? r_V_177_0_9_fu_22056_p3 : bt_ci_V_8_fu_21816_p3);
assign bt_ci_V_s_fu_24668_p2 = (tmp1299_fu_24660_p3 | bt_ci_V_9_fu_22304_p3);
assign bt_cpattern_V100_s_fu_23350_p2 = (tmp1118_fu_23344_p2 | tmp1113_fu_23314_p2);
assign bt_cpattern_V101_s_fu_23423_p2 = (tmp1128_fu_23417_p2 | tmp1123_fu_23387_p2);
assign bt_cpattern_V10_fu_31621_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_2_V_read_1_reg_40509_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V11_fu_31628_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_3_V_read_1_reg_40502_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V1_fu_17936_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_1_V_read_1_reg_40516_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V2_fu_17943_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_2_V_read_1_reg_40509_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V3_fu_17950_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_3_V_read_1_reg_40502_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V41102_s_fu_30114_p2 = (tmp1435_fu_30108_p2 | tmp1430_fu_30078_p2);
assign bt_cpattern_V41103_s_fu_30187_p2 = (tmp1445_fu_30181_p2 | tmp1440_fu_30151_p2);
assign bt_cpattern_V41104_s_fu_30260_p2 = (tmp1455_fu_30254_p2 | tmp1450_fu_30224_p2);
assign bt_cpattern_V41_s_fu_30041_p2 = (tmp1425_fu_30035_p2 | tmp1420_fu_30005_p2);
assign bt_cpattern_V42105_s_fu_36951_p2 = (tmp1667_fu_36945_p2 | tmp1662_fu_36915_p2);
assign bt_cpattern_V42106_s_fu_37024_p2 = (tmp1677_fu_37018_p2 | tmp1672_fu_36988_p2);
assign bt_cpattern_V42107_s_fu_37097_p2 = (tmp1687_fu_37091_p2 | tmp1682_fu_37061_p2);
assign bt_cpattern_V42_s_fu_36878_p2 = (tmp1657_fu_36872_p2 | tmp1652_fu_36842_p2);
assign bt_cpattern_V4_fu_24770_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_0_V_read_1_reg_40523_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V5_fu_24777_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_1_V_read_1_reg_40516_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V6_fu_24784_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_2_V_read_1_reg_40509_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V7_fu_24791_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_3_V_read_1_reg_40502_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V8_fu_31607_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_0_V_read_1_reg_40523_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V99_s_fu_23277_p2 = (tmp1108_fu_23271_p2 | tmp1103_fu_23241_p2);
assign bt_cpattern_V9_fu_31614_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_1_V_read_1_reg_40516_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V_fu_17929_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_0_0_V_read_1_reg_40523_pp0_iter1 : ap_const_lv4_0);
assign bt_cpattern_V_s_fu_23204_p2 = (tmp1098_fu_23198_p2 | tmp1093_fu_23168_p2);
assign bt_delta_ph_V108_s_fu_23569_p2 = (tmp1148_fu_23563_p2 | tmp1143_fu_23533_p2);
assign bt_delta_ph_V109_s_fu_23642_p2 = (tmp1158_fu_23636_p2 | tmp1153_fu_23606_p2);
assign bt_delta_ph_V10_fu_24826_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_4_V_read_1_reg_40159_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V110_s_fu_23715_p2 = (tmp1168_fu_23709_p2 | tmp1163_fu_23679_p2);
assign bt_delta_ph_V111_s_fu_23788_p2 = (tmp1178_fu_23782_p2 | tmp1173_fu_23752_p2);
assign bt_delta_ph_V112_s_fu_23861_p2 = (tmp1188_fu_23855_p2 | tmp1183_fu_23825_p2);
assign bt_delta_ph_V11_fu_24833_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_5_V_read_1_reg_40152_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V12_fu_31635_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_0_V_read_1_reg_40187_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V13_fu_31642_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_1_V_read_1_reg_40180_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V14_fu_31649_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_2_V_read_1_reg_40173_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V15_fu_31656_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_3_V_read_1_reg_40166_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V16_fu_31663_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_4_V_read_1_reg_40159_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V17_fu_31670_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_5_V_read_1_reg_40152_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V1_fu_17964_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_1_V_read_1_reg_40180_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V2_fu_17971_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_2_V_read_1_reg_40173_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V3_fu_17978_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_3_V_read_1_reg_40166_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V43113_s_fu_30406_p2 = (tmp1475_fu_30400_p2 | tmp1470_fu_30370_p2);
assign bt_delta_ph_V43114_s_fu_30479_p2 = (tmp1485_fu_30473_p2 | tmp1480_fu_30443_p2);
assign bt_delta_ph_V43115_s_fu_30552_p2 = (tmp1495_fu_30546_p2 | tmp1490_fu_30516_p2);
assign bt_delta_ph_V43116_s_fu_30625_p2 = (tmp1505_fu_30619_p2 | tmp1500_fu_30589_p2);
assign bt_delta_ph_V43117_s_fu_30698_p2 = (tmp1515_fu_30692_p2 | tmp1510_fu_30662_p2);
assign bt_delta_ph_V43_s_fu_30333_p2 = (tmp1465_fu_30327_p2 | tmp1460_fu_30297_p2);
assign bt_delta_ph_V44118_s_fu_37243_p2 = (tmp1707_fu_37237_p2 | tmp1702_fu_37207_p2);
assign bt_delta_ph_V44119_s_fu_37316_p2 = (tmp1717_fu_37310_p2 | tmp1712_fu_37280_p2);
assign bt_delta_ph_V44120_s_fu_37389_p2 = (tmp1727_fu_37383_p2 | tmp1722_fu_37353_p2);
assign bt_delta_ph_V44121_s_fu_37462_p2 = (tmp1737_fu_37456_p2 | tmp1732_fu_37426_p2);
assign bt_delta_ph_V44122_s_fu_37535_p2 = (tmp1747_fu_37529_p2 | tmp1742_fu_37499_p2);
assign bt_delta_ph_V44_s_fu_37170_p2 = (tmp1697_fu_37164_p2 | tmp1692_fu_37134_p2);
assign bt_delta_ph_V4_fu_17985_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_4_V_read_1_reg_40159_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V5_fu_17992_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_5_V_read_1_reg_40152_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V6_fu_24798_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_0_V_read_1_reg_40187_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V7_fu_24805_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_1_V_read_1_reg_40180_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V8_fu_24812_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_2_V_read_1_reg_40173_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V9_fu_24819_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_3_V_read_1_reg_40166_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V_fu_17957_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_0_0_V_read_1_reg_40187_pp0_iter1 : ap_const_lv12_0);
assign bt_delta_ph_V_s_fu_23496_p2 = (tmp1138_fu_23490_p2 | tmp1133_fu_23460_p2);
assign bt_delta_th_V10_fu_24868_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_4_V_read_1_reg_39655_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V11_fu_24875_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_5_V_read_1_reg_39648_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V123_s_fu_24007_p2 = (tmp1208_fu_24001_p2 | tmp1203_fu_23971_p2);
assign bt_delta_th_V124_s_fu_24080_p2 = (tmp1218_fu_24074_p2 | tmp1213_fu_24044_p2);
assign bt_delta_th_V125_s_fu_24153_p2 = (tmp1228_fu_24147_p2 | tmp1223_fu_24117_p2);
assign bt_delta_th_V126_s_fu_24226_p2 = (tmp1238_fu_24220_p2 | tmp1233_fu_24190_p2);
assign bt_delta_th_V127_s_fu_24299_p2 = (tmp1248_fu_24293_p2 | tmp1243_fu_24263_p2);
assign bt_delta_th_V12_fu_31677_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_0_V_read_1_reg_39683_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V13_fu_31684_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_1_V_read_1_reg_39676_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V14_fu_31691_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_2_V_read_1_reg_39669_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V15_fu_31698_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_3_V_read_1_reg_39662_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V16_fu_31705_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_4_V_read_1_reg_39655_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V17_fu_31712_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_5_V_read_1_reg_39648_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V1_fu_18006_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_1_V_read_1_reg_39676_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V2_fu_18013_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_2_V_read_1_reg_39669_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V3_fu_18020_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_3_V_read_1_reg_39662_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V45128_s_fu_30844_p2 = (tmp1535_fu_30838_p2 | tmp1530_fu_30808_p2);
assign bt_delta_th_V45129_s_fu_30917_p2 = (tmp1545_fu_30911_p2 | tmp1540_fu_30881_p2);
assign bt_delta_th_V45130_s_fu_30990_p2 = (tmp1555_fu_30984_p2 | tmp1550_fu_30954_p2);
assign bt_delta_th_V45131_s_fu_31063_p2 = (tmp1565_fu_31057_p2 | tmp1560_fu_31027_p2);
assign bt_delta_th_V45132_s_fu_31136_p2 = (tmp1575_fu_31130_p2 | tmp1570_fu_31100_p2);
assign bt_delta_th_V45_s_fu_30771_p2 = (tmp1525_fu_30765_p2 | tmp1520_fu_30735_p2);
assign bt_delta_th_V46133_s_fu_37681_p2 = (tmp1767_fu_37675_p2 | tmp1762_fu_37645_p2);
assign bt_delta_th_V46134_s_fu_37754_p2 = (tmp1777_fu_37748_p2 | tmp1772_fu_37718_p2);
assign bt_delta_th_V46135_s_fu_37827_p2 = (tmp1787_fu_37821_p2 | tmp1782_fu_37791_p2);
assign bt_delta_th_V46136_s_fu_37900_p2 = (tmp1797_fu_37894_p2 | tmp1792_fu_37864_p2);
assign bt_delta_th_V46137_s_fu_37973_p2 = (tmp1807_fu_37967_p2 | tmp1802_fu_37937_p2);
assign bt_delta_th_V46_s_fu_37608_p2 = (tmp1757_fu_37602_p2 | tmp1752_fu_37572_p2);
assign bt_delta_th_V4_fu_18027_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_4_V_read_1_reg_39655_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V5_fu_18034_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_5_V_read_1_reg_39648_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V6_fu_24840_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_0_V_read_1_reg_39683_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V7_fu_24847_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_1_V_read_1_reg_39676_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V8_fu_24854_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_2_V_read_1_reg_39669_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V9_fu_24861_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_3_V_read_1_reg_39662_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V_fu_17999_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_0_0_V_read_1_reg_39683_pp0_iter1 : ap_const_lv7_0);
assign bt_delta_th_V_s_fu_23934_p2 = (tmp1198_fu_23928_p2 | tmp1193_fu_23898_p2);
assign bt_hi_V151_s_fu_24586_p2 = (tmp1278_fu_24580_p2 | tmp1273_fu_24530_p2);
assign bt_hi_V152_s_fu_24640_p2 = (tmp1288_fu_24634_p2 | tmp1283_fu_24622_p2);
assign bt_hi_V55155_s_fu_31423_p2 = (tmp1605_fu_31417_p2 | tmp1600_fu_31367_p2);
assign bt_hi_V55156_s_fu_31477_p2 = (tmp1615_fu_31471_p2 | tmp1610_fu_31459_p2);
assign bt_hi_V55_s_fu_31317_p2 = (tmp1595_fu_31311_p2 | tmp1590_fu_31265_p2);
assign bt_hi_V56159_s_fu_38260_p2 = (tmp1837_fu_38254_p2 | tmp1832_fu_38204_p2);
assign bt_hi_V56160_s_fu_38314_p2 = (tmp1847_fu_38308_p2 | tmp1842_fu_38296_p2);
assign bt_hi_V56_s_fu_38154_p2 = (tmp1827_fu_38148_p2 | tmp1822_fu_38102_p2);
assign bt_hi_V_s_fu_24480_p2 = (tmp1268_fu_24474_p2 | tmp1263_fu_24428_p2);
assign bt_phi_V1_fu_24756_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_0_V_read_1_reg_40691_pp0_iter1 : ap_const_lv12_0);
assign bt_phi_V2_fu_31593_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_0_V_read_1_reg_40691_pp0_iter1 : ap_const_lv12_0);
assign bt_phi_V37_s_fu_29895_p2 = (tmp1405_fu_29889_p2 | tmp1400_fu_29859_p2);
assign bt_phi_V38_s_fu_36732_p2 = (tmp1637_fu_36726_p2 | tmp1632_fu_36696_p2);
assign bt_phi_V_fu_17915_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_0_V_read_1_reg_40691_pp0_iter1 : ap_const_lv12_0);
assign bt_phi_V_s_fu_23058_p2 = (tmp1078_fu_23052_p2 | tmp1073_fu_23022_p2);
assign bt_rank_V1_fu_24896_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_0_V_read_1_reg_39165_pp0_iter1 : ap_const_lv7_0);
assign bt_rank_V2_fu_31733_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_0_V_read_1_reg_39165_pp0_iter1 : ap_const_lv7_0);
assign bt_rank_V51_s_fu_31225_p2 = (tmp1585_fu_31219_p2 | tmp1580_fu_31189_p2);
assign bt_rank_V52_s_fu_38062_p2 = (tmp1817_fu_38056_p2 | tmp1812_fu_38026_p2);
assign bt_rank_V_fu_18055_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_0_V_read_1_reg_39165_pp0_iter1 : ap_const_lv7_0);
assign bt_rank_V_s_fu_24388_p2 = (tmp1258_fu_24382_p2 | tmp1253_fu_24352_p2);
assign bt_si_V1_fu_24903_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? p_Result_1296_0_0_4_fu_17906_p4 : ap_const_lv5_0);
assign bt_si_V2_fu_31740_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? p_Result_1296_0_0_4_fu_17906_p4 : ap_const_lv5_0);
assign bt_si_V59_10_fu_31577_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? p_Result_1296_1_11_4_fu_29814_p6 : bt_si_V59_s_fu_29575_p3);
assign bt_si_V59_1_fu_25319_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? p_Result_1296_1_1_4_fu_25142_p6 : bt_si_V1_fu_24903_p3);
assign bt_si_V59_2_fu_25729_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? p_Result_1296_1_2_4_fu_25558_p6 : bt_si_V59_1_fu_25319_p3);
assign bt_si_V59_3_fu_26271_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? p_Result_1296_1_3_4_fu_25968_p6 : bt_si_V59_2_fu_25729_p3);
assign bt_si_V59_4_fu_26773_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? p_Result_1296_1_4_4_fu_26578_p6 : bt_si_V59_3_fu_26271_p3);
assign bt_si_V59_5_fu_27253_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? p_Result_1296_1_5_4_fu_27066_p6 : bt_si_V59_4_fu_26773_p3);
assign bt_si_V59_6_fu_27671_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? p_Result_1296_1_6_4_fu_27492_p6 : bt_si_V59_5_fu_27253_p3);
assign bt_si_V59_7_fu_28195_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? p_Result_1296_1_7_4_fu_27910_p6 : bt_si_V59_6_fu_27671_p3);
assign bt_si_V59_8_fu_28677_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? p_Result_1296_1_8_4_fu_28490_p6 : bt_si_V59_7_fu_28195_p3);
assign bt_si_V59_9_fu_29165_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? p_Result_1296_1_9_4_fu_28970_p6 : bt_si_V59_8_fu_28677_p3);
assign bt_si_V59_s_fu_29575_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? p_Result_1296_1_10_4_fu_29404_p6 : bt_si_V59_9_fu_29165_p3);
assign bt_si_V60_10_fu_38414_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? p_Result_1296_2_11_4_fu_36651_p6 : bt_si_V60_s_fu_36412_p3);
assign bt_si_V60_1_fu_32156_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? p_Result_1296_2_1_4_fu_31979_p6 : bt_si_V2_fu_31740_p3);
assign bt_si_V60_2_fu_32566_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? p_Result_1296_2_2_4_fu_32395_p6 : bt_si_V60_1_fu_32156_p3);
assign bt_si_V60_3_fu_33108_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? p_Result_1296_2_3_4_fu_32805_p6 : bt_si_V60_2_fu_32566_p3);
assign bt_si_V60_4_fu_33610_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? p_Result_1296_2_4_4_fu_33415_p6 : bt_si_V60_3_fu_33108_p3);
assign bt_si_V60_5_fu_34090_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? p_Result_1296_2_5_4_fu_33903_p6 : bt_si_V60_4_fu_33610_p3);
assign bt_si_V60_6_fu_34508_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? p_Result_1296_2_6_4_fu_34329_p6 : bt_si_V60_5_fu_34090_p3);
assign bt_si_V60_7_fu_35032_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? p_Result_1296_2_7_4_fu_34747_p6 : bt_si_V60_6_fu_34508_p3);
assign bt_si_V60_8_fu_35514_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? p_Result_1296_2_8_4_fu_35327_p6 : bt_si_V60_7_fu_35032_p3);
assign bt_si_V60_9_fu_36002_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? p_Result_1296_2_9_4_fu_35807_p6 : bt_si_V60_8_fu_35514_p3);
assign bt_si_V60_s_fu_36412_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? p_Result_1296_2_10_4_fu_36241_p6 : bt_si_V60_9_fu_36002_p3);
assign bt_si_V_10_fu_24740_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? p_Result_1296_0_11_4_fu_22977_p6 : bt_si_V_s_fu_22738_p3);
assign bt_si_V_1_fu_18478_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? p_Result_1296_0_1_4_fu_18301_p6 : bt_si_V_fu_18062_p3);
assign bt_si_V_2_fu_18888_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? p_Result_1296_0_2_4_fu_18717_p6 : bt_si_V_1_fu_18478_p3);
assign bt_si_V_3_fu_19434_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? p_Result_1296_0_3_4_fu_19127_p6 : bt_si_V_2_fu_18888_p3);
assign bt_si_V_4_fu_19936_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? p_Result_1296_0_4_4_fu_19741_p6 : bt_si_V_3_fu_19434_p3);
assign bt_si_V_5_fu_20416_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? p_Result_1296_0_5_4_fu_20229_p6 : bt_si_V_4_fu_19936_p3);
assign bt_si_V_6_fu_20834_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? p_Result_1296_0_6_4_fu_20655_p6 : bt_si_V_5_fu_20416_p3);
assign bt_si_V_7_fu_21358_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? p_Result_1296_0_7_4_fu_21073_p6 : bt_si_V_6_fu_20834_p3);
assign bt_si_V_8_fu_21840_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? p_Result_1296_0_8_4_fu_21653_p6 : bt_si_V_7_fu_21358_p3);
assign bt_si_V_9_fu_22328_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? p_Result_1296_0_9_4_fu_22133_p6 : bt_si_V_8_fu_21840_p3);
assign bt_si_V_fu_18062_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? p_Result_1296_0_0_4_fu_17906_p4 : ap_const_lv5_0);
assign bt_si_V_s_fu_22738_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? p_Result_1296_0_10_4_fu_22567_p6 : bt_si_V_9_fu_22328_p3);
assign bt_sign_ph_V1_fu_24882_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_sign_ph_0_0_V_read_1_reg_39179_pp0_iter1 : ap_const_lv6_0);
assign bt_sign_ph_V2_fu_31719_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_sign_ph_0_0_V_read_1_reg_39179_pp0_iter1 : ap_const_lv6_0);
assign bt_sign_ph_V47_10_fu_31142_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? p_Result_1290_1_11_5_fu_29726_p7 : bt_sign_ph_V47_s_fu_29544_p3);
assign bt_sign_ph_V47_1_fu_25282_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? p_Result_1290_1_1_5_fu_25054_p7 : bt_sign_ph_V1_fu_24882_p3);
assign bt_sign_ph_V47_2_fu_25698_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? p_Result_1290_1_2_5_fu_25470_p7 : bt_sign_ph_V47_1_fu_25282_p3);
assign bt_sign_ph_V47_3_fu_26108_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? p_Result_1290_1_3_5_fu_25880_p7 : bt_sign_ph_V47_2_fu_25698_p3);
assign bt_sign_ph_V47_4_fu_26718_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? p_Result_1290_1_4_5_fu_26422_p7 : bt_sign_ph_V47_3_fu_26108_p3);
assign bt_sign_ph_V47_5_fu_27206_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? p_Result_1290_1_5_5_fu_26924_p7 : bt_sign_ph_V47_4_fu_26718_p3);
assign bt_sign_ph_V47_6_fu_27632_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? p_Result_1290_1_6_5_fu_27404_p7 : bt_sign_ph_V47_5_fu_27206_p3);
assign bt_sign_ph_V47_7_fu_28050_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? p_Result_1290_1_7_5_fu_27822_p7 : bt_sign_ph_V47_6_fu_27632_p3);
assign bt_sign_ph_V47_8_fu_28630_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? p_Result_1290_1_8_5_fu_28346_p7 : bt_sign_ph_V47_7_fu_28050_p3);
assign bt_sign_ph_V47_9_fu_29110_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? p_Result_1290_1_9_5_fu_28828_p7 : bt_sign_ph_V47_8_fu_28630_p3);
assign bt_sign_ph_V47_s_fu_29544_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? p_Result_1290_1_10_5_fu_29316_p7 : bt_sign_ph_V47_9_fu_29110_p3);
assign bt_sign_ph_V48_10_fu_37979_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? p_Result_1290_2_11_5_fu_36563_p7 : bt_sign_ph_V48_s_fu_36381_p3);
assign bt_sign_ph_V48_1_fu_32119_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? p_Result_1290_2_1_5_fu_31891_p7 : bt_sign_ph_V2_fu_31719_p3);
assign bt_sign_ph_V48_2_fu_32535_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? p_Result_1290_2_2_5_fu_32307_p7 : bt_sign_ph_V48_1_fu_32119_p3);
assign bt_sign_ph_V48_3_fu_32945_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? p_Result_1290_2_3_5_fu_32717_p7 : bt_sign_ph_V48_2_fu_32535_p3);
assign bt_sign_ph_V48_4_fu_33555_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? p_Result_1290_2_4_5_fu_33259_p7 : bt_sign_ph_V48_3_fu_32945_p3);
assign bt_sign_ph_V48_5_fu_34043_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? p_Result_1290_2_5_5_fu_33761_p7 : bt_sign_ph_V48_4_fu_33555_p3);
assign bt_sign_ph_V48_6_fu_34469_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? p_Result_1290_2_6_5_fu_34241_p7 : bt_sign_ph_V48_5_fu_34043_p3);
assign bt_sign_ph_V48_7_fu_34887_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? p_Result_1290_2_7_5_fu_34659_p7 : bt_sign_ph_V48_6_fu_34469_p3);
assign bt_sign_ph_V48_8_fu_35467_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? p_Result_1290_2_8_5_fu_35183_p7 : bt_sign_ph_V48_7_fu_34887_p3);
assign bt_sign_ph_V48_9_fu_35947_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? p_Result_1290_2_9_5_fu_35665_p7 : bt_sign_ph_V48_8_fu_35467_p3);
assign bt_sign_ph_V48_s_fu_36381_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? p_Result_1290_2_10_5_fu_36153_p7 : bt_sign_ph_V48_9_fu_35947_p3);
assign bt_sign_ph_V_10_fu_24305_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? p_Result_1290_0_11_5_fu_22889_p7 : bt_sign_ph_V_s_fu_22707_p3);
assign bt_sign_ph_V_1_fu_18441_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? p_Result_1290_0_1_5_fu_18213_p7 : bt_sign_ph_V_fu_18041_p3);
assign bt_sign_ph_V_2_fu_18857_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? p_Result_1290_0_2_5_fu_18629_p7 : bt_sign_ph_V_1_fu_18441_p3);
assign bt_sign_ph_V_3_fu_19267_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? p_Result_1290_0_3_5_fu_19039_p7 : bt_sign_ph_V_2_fu_18857_p3);
assign bt_sign_ph_V_4_fu_19881_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? p_Result_1290_0_4_5_fu_19585_p7 : bt_sign_ph_V_3_fu_19267_p3);
assign bt_sign_ph_V_5_fu_20369_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? p_Result_1290_0_5_5_fu_20087_p7 : bt_sign_ph_V_4_fu_19881_p3);
assign bt_sign_ph_V_6_fu_20795_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? p_Result_1290_0_6_5_fu_20567_p7 : bt_sign_ph_V_5_fu_20369_p3);
assign bt_sign_ph_V_7_fu_21213_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? p_Result_1290_0_7_5_fu_20985_p7 : bt_sign_ph_V_6_fu_20795_p3);
assign bt_sign_ph_V_8_fu_21793_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? p_Result_1290_0_8_5_fu_21509_p7 : bt_sign_ph_V_7_fu_21213_p3);
assign bt_sign_ph_V_9_fu_22273_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? p_Result_1290_0_9_5_fu_21991_p7 : bt_sign_ph_V_8_fu_21793_p3);
assign bt_sign_ph_V_fu_18041_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_sign_ph_0_0_V_read_1_reg_39179_pp0_iter1 : ap_const_lv6_0);
assign bt_sign_ph_V_s_fu_22707_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? p_Result_1290_0_10_5_fu_22479_p7 : bt_sign_ph_V_9_fu_22273_p3);
assign bt_sign_th_V1_fu_24889_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_sign_th_0_0_V_read_1_reg_39172_pp0_iter1 : ap_const_lv6_0);
assign bt_sign_th_V2_fu_31726_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_sign_th_0_0_V_read_1_reg_39172_pp0_iter1 : ap_const_lv6_0);
assign bt_sign_th_V49_10_fu_31150_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? p_Result_1293_1_11_5_fu_29755_p7 : bt_sign_th_V49_s_fu_29552_p3);
assign bt_sign_th_V49_1_fu_25290_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? p_Result_1293_1_1_5_fu_25083_p7 : bt_sign_th_V1_fu_24889_p3);
assign bt_sign_th_V49_2_fu_25706_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? p_Result_1293_1_2_5_fu_25499_p7 : bt_sign_th_V49_1_fu_25290_p3);
assign bt_sign_th_V49_3_fu_26116_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? p_Result_1293_1_3_5_fu_25909_p7 : bt_sign_th_V49_2_fu_25706_p3);
assign bt_sign_th_V49_4_fu_26726_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? p_Result_1293_1_4_5_fu_26451_p7 : bt_sign_th_V49_3_fu_26116_p3);
assign bt_sign_th_V49_5_fu_27214_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? p_Result_1293_1_5_5_fu_26953_p7 : bt_sign_th_V49_4_fu_26726_p3);
assign bt_sign_th_V49_6_fu_27640_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? p_Result_1293_1_6_5_fu_27433_p7 : bt_sign_th_V49_5_fu_27214_p3);
assign bt_sign_th_V49_7_fu_28058_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? p_Result_1293_1_7_5_fu_27851_p7 : bt_sign_th_V49_6_fu_27640_p3);
assign bt_sign_th_V49_8_fu_28638_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? p_Result_1293_1_8_5_fu_28375_p7 : bt_sign_th_V49_7_fu_28058_p3);
assign bt_sign_th_V49_9_fu_29118_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? p_Result_1293_1_9_5_fu_28857_p7 : bt_sign_th_V49_8_fu_28638_p3);
assign bt_sign_th_V49_s_fu_29552_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? p_Result_1293_1_10_5_fu_29345_p7 : bt_sign_th_V49_9_fu_29118_p3);
assign bt_sign_th_V50_10_fu_37987_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? p_Result_1293_2_11_5_fu_36592_p7 : bt_sign_th_V50_s_fu_36389_p3);
assign bt_sign_th_V50_1_fu_32127_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? p_Result_1293_2_1_5_fu_31920_p7 : bt_sign_th_V2_fu_31726_p3);
assign bt_sign_th_V50_2_fu_32543_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? p_Result_1293_2_2_5_fu_32336_p7 : bt_sign_th_V50_1_fu_32127_p3);
assign bt_sign_th_V50_3_fu_32953_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? p_Result_1293_2_3_5_fu_32746_p7 : bt_sign_th_V50_2_fu_32543_p3);
assign bt_sign_th_V50_4_fu_33563_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? p_Result_1293_2_4_5_fu_33288_p7 : bt_sign_th_V50_3_fu_32953_p3);
assign bt_sign_th_V50_5_fu_34051_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? p_Result_1293_2_5_5_fu_33790_p7 : bt_sign_th_V50_4_fu_33563_p3);
assign bt_sign_th_V50_6_fu_34477_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? p_Result_1293_2_6_5_fu_34270_p7 : bt_sign_th_V50_5_fu_34051_p3);
assign bt_sign_th_V50_7_fu_34895_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? p_Result_1293_2_7_5_fu_34688_p7 : bt_sign_th_V50_6_fu_34477_p3);
assign bt_sign_th_V50_8_fu_35475_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? p_Result_1293_2_8_5_fu_35212_p7 : bt_sign_th_V50_7_fu_34895_p3);
assign bt_sign_th_V50_9_fu_35955_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? p_Result_1293_2_9_5_fu_35694_p7 : bt_sign_th_V50_8_fu_35475_p3);
assign bt_sign_th_V50_s_fu_36389_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? p_Result_1293_2_10_5_fu_36182_p7 : bt_sign_th_V50_9_fu_35955_p3);
assign bt_sign_th_V_10_fu_24313_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? p_Result_1293_0_11_5_fu_22918_p7 : bt_sign_th_V_s_fu_22715_p3);
assign bt_sign_th_V_1_fu_18449_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? p_Result_1293_0_1_5_fu_18242_p7 : bt_sign_th_V_fu_18048_p3);
assign bt_sign_th_V_2_fu_18865_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? p_Result_1293_0_2_5_fu_18658_p7 : bt_sign_th_V_1_fu_18449_p3);
assign bt_sign_th_V_3_fu_19275_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? p_Result_1293_0_3_5_fu_19068_p7 : bt_sign_th_V_2_fu_18865_p3);
assign bt_sign_th_V_4_fu_19889_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? p_Result_1293_0_4_5_fu_19614_p7 : bt_sign_th_V_3_fu_19275_p3);
assign bt_sign_th_V_5_fu_20377_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? p_Result_1293_0_5_5_fu_20116_p7 : bt_sign_th_V_4_fu_19889_p3);
assign bt_sign_th_V_6_fu_20803_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? p_Result_1293_0_6_5_fu_20596_p7 : bt_sign_th_V_5_fu_20377_p3);
assign bt_sign_th_V_7_fu_21221_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? p_Result_1293_0_7_5_fu_21014_p7 : bt_sign_th_V_6_fu_20803_p3);
assign bt_sign_th_V_8_fu_21801_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? p_Result_1293_0_8_5_fu_21538_p7 : bt_sign_th_V_7_fu_21221_p3);
assign bt_sign_th_V_9_fu_22281_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? p_Result_1293_0_9_5_fu_22020_p7 : bt_sign_th_V_8_fu_21801_p3);
assign bt_sign_th_V_fu_18048_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_sign_th_0_0_V_read_1_reg_39172_pp0_iter1 : ap_const_lv6_0);
assign bt_sign_th_V_s_fu_22715_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? p_Result_1293_0_10_5_fu_22508_p7 : bt_sign_th_V_9_fu_22281_p3);
assign bt_theta_V1_fu_24763_p3 = ((tmp_2283_fu_24748_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_0_V_read_1_reg_40607_pp0_iter1 : ap_const_lv7_0);
assign bt_theta_V2_fu_31600_p3 = ((tmp_2520_fu_31585_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_0_V_read_1_reg_40607_pp0_iter1 : ap_const_lv7_0);
assign bt_theta_V39_s_fu_29968_p2 = (tmp1415_fu_29962_p2 | tmp1410_fu_29932_p2);
assign bt_theta_V40_s_fu_36805_p2 = (tmp1647_fu_36799_p2 | tmp1642_fu_36769_p2);
assign bt_theta_V_fu_17922_p3 = ((tmp_1901_fu_17898_p1[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_0_V_read_1_reg_40607_pp0_iter1 : ap_const_lv7_0);
assign bt_theta_V_s_fu_23131_p2 = (tmp1088_fu_23125_p2 | tmp1083_fu_23095_p2);
always @ (*) begin
cn_si_0_0_V_fu_17488_p4 = ap_const_lv5_0;
cn_si_0_0_V_fu_17488_p4[ap_const_lv32_0] = |(ap_reg_ppstg_tmp_reg_40698_pp0_iter1);
end
assign exists_V_fu_7958_p2 = (p_Result_1299_s_fu_5496_p13 & rhs_i_i1_fu_7952_p2);
assign kill1_t_V_0_10_fu_5692_p3 = ((tmp_1455_fu_5684_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_1);
assign kill1_t_V_0_1_fu_5532_p3 = ((tmp_1445_fu_5524_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_1);
assign kill1_t_V_0_2_fu_5548_p3 = ((tmp_1446_fu_5540_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_1);
assign kill1_t_V_0_3_fu_5564_p3 = ((tmp_1447_fu_5556_p3[0:0] === 1'b1) ? ap_const_lv4_8 : ap_const_lv4_1);
assign kill1_t_V_0_4_fu_5580_p3 = ((tmp_1448_fu_5572_p3[0:0] === 1'b1) ? ap_const_lv5_10 : ap_const_lv5_1);
assign kill1_t_V_0_5_fu_5596_p3 = ((tmp_1449_fu_5588_p3[0:0] === 1'b1) ? ap_const_lv6_20 : ap_const_lv6_1);
assign kill1_t_V_0_6_fu_5612_p3 = ((tmp_1450_fu_5604_p3[0:0] === 1'b1) ? ap_const_lv7_40 : ap_const_lv7_1);
assign kill1_t_V_0_7_fu_5628_p3 = ((tmp_1451_fu_5620_p3[0:0] === 1'b1) ? ap_const_lv8_80 : ap_const_lv8_1);
assign kill1_t_V_0_8_fu_5644_p3 = ((tmp_1452_fu_5636_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_1);
assign kill1_t_V_0_9_fu_5660_p3 = ((tmp_1453_fu_5652_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_1);
assign kill1_t_V_0_s_fu_5676_p3 = ((tmp_1454_fu_5668_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_1);
assign kill1_t_V_10_s_fu_6572_p3 = ((tmp_1510_fu_6564_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_400);
assign kill1_t_V_1_1_fu_5852_p3 = ((tmp_1465_fu_5844_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_2);
assign kill1_t_V_1_2_fu_5708_p3 = ((tmp_1456_fu_5700_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_2);
assign kill1_t_V_1_3_fu_5724_p3 = ((tmp_1457_fu_5716_p3[0:0] === 1'b1) ? ap_const_lv4_8 : ap_const_lv4_2);
assign kill1_t_V_1_4_fu_5740_p3 = ((tmp_1458_fu_5732_p3[0:0] === 1'b1) ? ap_const_lv5_10 : ap_const_lv5_2);
assign kill1_t_V_1_5_fu_5756_p3 = ((tmp_1459_fu_5748_p3[0:0] === 1'b1) ? ap_const_lv6_20 : ap_const_lv6_2);
assign kill1_t_V_1_6_fu_5772_p3 = ((tmp_1460_fu_5764_p3[0:0] === 1'b1) ? ap_const_lv7_40 : ap_const_lv7_2);
assign kill1_t_V_1_7_fu_5788_p3 = ((tmp_1461_fu_5780_p3[0:0] === 1'b1) ? ap_const_lv8_80 : ap_const_lv8_2);
assign kill1_t_V_1_8_fu_5804_p3 = ((tmp_1462_fu_5796_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_2);
assign kill1_t_V_1_9_fu_5820_p3 = ((tmp_1463_fu_5812_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_2);
assign kill1_t_V_1_s_fu_5836_p3 = ((tmp_1464_fu_5828_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_2);
assign kill1_t_V_2_1_fu_5996_p3 = ((tmp_1474_fu_5988_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_4);
assign kill1_t_V_2_3_fu_5868_p3 = ((tmp_1466_fu_5860_p3[0:0] === 1'b1) ? ap_const_lv4_8 : ap_const_lv4_4);
assign kill1_t_V_2_4_fu_5884_p3 = ((tmp_1467_fu_5876_p3[0:0] === 1'b1) ? ap_const_lv5_10 : ap_const_lv5_4);
assign kill1_t_V_2_5_fu_5900_p3 = ((tmp_1468_fu_5892_p3[0:0] === 1'b1) ? ap_const_lv6_20 : ap_const_lv6_4);
assign kill1_t_V_2_6_fu_5916_p3 = ((tmp_1469_fu_5908_p3[0:0] === 1'b1) ? ap_const_lv7_40 : ap_const_lv7_4);
assign kill1_t_V_2_7_fu_5932_p3 = ((tmp_1470_fu_5924_p3[0:0] === 1'b1) ? ap_const_lv8_80 : ap_const_lv8_4);
assign kill1_t_V_2_8_fu_5948_p3 = ((tmp_1471_fu_5940_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_4);
assign kill1_t_V_2_9_fu_5964_p3 = ((tmp_1472_fu_5956_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_4);
assign kill1_t_V_2_s_fu_5980_p3 = ((tmp_1473_fu_5972_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_4);
assign kill1_t_V_3_1_fu_6124_p3 = ((tmp_1482_fu_6116_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_8);
assign kill1_t_V_3_4_fu_6012_p3 = ((tmp_1475_fu_6004_p3[0:0] === 1'b1) ? ap_const_lv5_10 : ap_const_lv5_8);
assign kill1_t_V_3_5_fu_6028_p3 = ((tmp_1476_fu_6020_p3[0:0] === 1'b1) ? ap_const_lv6_20 : ap_const_lv6_8);
assign kill1_t_V_3_6_fu_6044_p3 = ((tmp_1477_fu_6036_p3[0:0] === 1'b1) ? ap_const_lv7_40 : ap_const_lv7_8);
assign kill1_t_V_3_7_fu_6060_p3 = ((tmp_1478_fu_6052_p3[0:0] === 1'b1) ? ap_const_lv8_80 : ap_const_lv8_8);
assign kill1_t_V_3_8_fu_6076_p3 = ((tmp_1479_fu_6068_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_8);
assign kill1_t_V_3_9_fu_6092_p3 = ((tmp_1480_fu_6084_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_8);
assign kill1_t_V_3_s_fu_6108_p3 = ((tmp_1481_fu_6100_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_8);
assign kill1_t_V_4_1_fu_6236_p3 = ((tmp_1489_fu_6228_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_10);
assign kill1_t_V_4_5_fu_6140_p3 = ((tmp_1483_fu_6132_p3[0:0] === 1'b1) ? ap_const_lv6_20 : ap_const_lv6_10);
assign kill1_t_V_4_6_fu_6156_p3 = ((tmp_1484_fu_6148_p3[0:0] === 1'b1) ? ap_const_lv7_40 : ap_const_lv7_10);
assign kill1_t_V_4_7_fu_6172_p3 = ((tmp_1485_fu_6164_p3[0:0] === 1'b1) ? ap_const_lv8_80 : ap_const_lv8_10);
assign kill1_t_V_4_8_fu_6188_p3 = ((tmp_1486_fu_6180_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_10);
assign kill1_t_V_4_9_fu_6204_p3 = ((tmp_1487_fu_6196_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_10);
assign kill1_t_V_4_s_fu_6220_p3 = ((tmp_1488_fu_6212_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_10);
assign kill1_t_V_5_1_fu_6332_p3 = ((tmp_1495_fu_6324_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_20);
assign kill1_t_V_5_6_fu_6252_p3 = ((tmp_1490_fu_6244_p3[0:0] === 1'b1) ? ap_const_lv7_40 : ap_const_lv7_20);
assign kill1_t_V_5_7_fu_6268_p3 = ((tmp_1491_fu_6260_p3[0:0] === 1'b1) ? ap_const_lv8_80 : ap_const_lv8_20);
assign kill1_t_V_5_8_fu_6284_p3 = ((tmp_1492_fu_6276_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_20);
assign kill1_t_V_5_9_fu_6300_p3 = ((tmp_1493_fu_6292_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_20);
assign kill1_t_V_5_s_fu_6316_p3 = ((tmp_1494_fu_6308_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_20);
assign kill1_t_V_6_1_fu_6412_p3 = ((tmp_1500_fu_6404_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_40);
assign kill1_t_V_6_7_fu_6348_p3 = ((tmp_1496_fu_6340_p3[0:0] === 1'b1) ? ap_const_lv8_80 : ap_const_lv8_40);
assign kill1_t_V_6_8_fu_6364_p3 = ((tmp_1497_fu_6356_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_40);
assign kill1_t_V_6_9_fu_6380_p3 = ((tmp_1498_fu_6372_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_40);
assign kill1_t_V_6_s_fu_6396_p3 = ((tmp_1499_fu_6388_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_40);
assign kill1_t_V_7_1_fu_6476_p3 = ((tmp_1504_fu_6468_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_80);
assign kill1_t_V_7_8_fu_6428_p3 = ((tmp_1501_fu_6420_p3[0:0] === 1'b1) ? ap_const_lv9_100 : ap_const_lv9_80);
assign kill1_t_V_7_9_fu_6444_p3 = ((tmp_1502_fu_6436_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_80);
assign kill1_t_V_7_s_fu_6460_p3 = ((tmp_1503_fu_6452_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_80);
assign kill1_t_V_8_1_fu_6524_p3 = ((tmp_1507_fu_6516_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_100);
assign kill1_t_V_8_9_fu_6492_p3 = ((tmp_1505_fu_6484_p3[0:0] === 1'b1) ? ap_const_lv10_200 : ap_const_lv10_100);
assign kill1_t_V_8_s_fu_6508_p3 = ((tmp_1506_fu_6500_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_100);
assign kill1_t_V_9_1_fu_6556_p3 = ((tmp_1509_fu_6548_p3[0:0] === 1'b1) ? ap_const_lv12_800 : ap_const_lv12_200);
assign kill1_t_V_9_s_fu_6540_p3 = ((tmp_1508_fu_6532_p3[0:0] === 1'b1) ? ap_const_lv11_400 : ap_const_lv11_200);
always @ (*) begin
larger_10_V_1_fu_5128_p4 = larger_V_10_1_fu_5120_p3;
larger_10_V_1_fu_5128_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
larger_10_V_2_fu_5146_p4 = larger_V_10_2_fu_5138_p3;
larger_10_V_2_fu_5146_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
larger_10_V_3_fu_5164_p4 = larger_V_10_3_fu_5156_p3;
larger_10_V_3_fu_5164_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
larger_10_V_4_fu_5182_p4 = larger_V_10_4_fu_5174_p3;
larger_10_V_4_fu_5182_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
larger_10_V_5_fu_5200_p4 = larger_V_10_5_fu_5192_p3;
larger_10_V_5_fu_5200_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
larger_10_V_6_fu_5218_p4 = larger_V_10_6_fu_5210_p3;
larger_10_V_6_fu_5218_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
larger_10_V_7_fu_5236_p4 = larger_V_10_7_fu_5228_p3;
larger_10_V_7_fu_5236_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
larger_10_V_8_fu_5254_p4 = larger_V_10_8_fu_5246_p3;
larger_10_V_8_fu_5254_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
larger_10_V_9_fu_5278_p4 = larger_V_10_9_fu_5264_p3;
larger_10_V_9_fu_5278_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
larger_10_V_fu_5110_p4 = p_21_cast_cast_fu_5102_p3;
larger_10_V_fu_5110_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
larger_11_V_1_fu_5328_p4 = larger_V_11_1_fu_5320_p3;
larger_11_V_1_fu_5328_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
larger_11_V_2_fu_5346_p4 = larger_V_11_2_fu_5338_p3;
larger_11_V_2_fu_5346_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
larger_11_V_3_fu_5364_p4 = larger_V_11_3_fu_5356_p3;
larger_11_V_3_fu_5364_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
larger_11_V_4_fu_5382_p4 = larger_V_11_4_fu_5374_p3;
larger_11_V_4_fu_5382_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
larger_11_V_5_fu_5400_p4 = larger_V_11_5_fu_5392_p3;
larger_11_V_5_fu_5400_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
larger_11_V_6_fu_5418_p4 = larger_V_11_6_fu_5410_p3;
larger_11_V_6_fu_5418_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
larger_11_V_7_fu_5436_p4 = larger_V_11_7_fu_5428_p3;
larger_11_V_7_fu_5436_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
larger_11_V_8_fu_5454_p4 = larger_V_11_8_fu_5446_p3;
larger_11_V_8_fu_5454_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
larger_11_V_9_fu_5472_p4 = larger_V_11_9_fu_5464_p3;
larger_11_V_9_fu_5472_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
larger_11_V_fu_5310_p4 = p_s_fu_5302_p3;
larger_11_V_fu_5310_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
larger_9_V_1_fu_4922_p4 = larger_V_9_1_fu_4914_p3;
larger_9_V_1_fu_4922_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
larger_9_V_2_fu_4940_p4 = larger_V_9_2_fu_4932_p3;
larger_9_V_2_fu_4940_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
larger_9_V_3_fu_4958_p4 = larger_V_9_3_fu_4950_p3;
larger_9_V_3_fu_4958_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
larger_9_V_4_fu_4976_p4 = larger_V_9_4_fu_4968_p3;
larger_9_V_4_fu_4976_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
larger_9_V_5_fu_4994_p4 = larger_V_9_5_fu_4986_p3;
larger_9_V_5_fu_4994_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
larger_9_V_6_fu_5012_p4 = larger_V_9_6_fu_5004_p3;
larger_9_V_6_fu_5012_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
larger_9_V_7_fu_5030_p4 = larger_V_9_7_fu_5022_p3;
larger_9_V_7_fu_5030_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
larger_9_V_8_fu_5054_p4 = larger_V_9_8_fu_5040_p3;
larger_9_V_8_fu_5054_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
larger_9_V_9_fu_5078_p4 = larger_V_9_9_fu_5064_p3;
larger_9_V_9_fu_5078_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
larger_9_V_fu_4904_p4 = p_20_cast_cast_fu_4896_p3;
larger_9_V_fu_4904_p4[ap_const_lv32_1] = |(1'b1);
end
assign larger_V_10_1_fu_5120_p3 = ((tmp_1339_1_s_fu_3232_p2[0:0] === 1'b1) ? larger_10_V_fu_5110_p4 : p_21_cast_cast_fu_5102_p3);
assign larger_V_10_2_fu_5138_p3 = ((tmp_1339_2_s_fu_3480_p2[0:0] === 1'b1) ? larger_10_V_1_fu_5128_p4 : larger_V_10_1_fu_5120_p3);
assign larger_V_10_3_fu_5156_p3 = ((tmp_1339_3_s_fu_3722_p2[0:0] === 1'b1) ? larger_10_V_2_fu_5146_p4 : larger_V_10_2_fu_5138_p3);
assign larger_V_10_4_fu_5174_p3 = ((tmp_1339_4_s_fu_3958_p2[0:0] === 1'b1) ? larger_10_V_3_fu_5164_p4 : larger_V_10_3_fu_5156_p3);
assign larger_V_10_5_fu_5192_p3 = ((tmp_1339_5_s_fu_4188_p2[0:0] === 1'b1) ? larger_10_V_4_fu_5182_p4 : larger_V_10_4_fu_5174_p3);
assign larger_V_10_6_fu_5210_p3 = ((tmp_1339_6_s_fu_4412_p2[0:0] === 1'b1) ? larger_10_V_5_fu_5200_p4 : larger_V_10_5_fu_5192_p3);
assign larger_V_10_7_fu_5228_p3 = ((tmp_1339_7_s_fu_4630_p2[0:0] === 1'b1) ? larger_10_V_6_fu_5218_p4 : larger_V_10_6_fu_5210_p3);
assign larger_V_10_8_fu_5246_p3 = ((tmp_1339_8_s_fu_4842_p2[0:0] === 1'b1) ? larger_10_V_7_fu_5236_p4 : larger_V_10_7_fu_5228_p3);
assign larger_V_10_9_fu_5264_p3 = ((tmp_1339_9_s_fu_5048_p2[0:0] === 1'b1) ? larger_10_V_8_fu_5254_p4 : larger_V_10_8_fu_5246_p3);
assign larger_V_10_s_fu_5288_p3 = ((tmp_1339_10_s_fu_5272_p2[0:0] === 1'b1) ? larger_V_10_9_fu_5264_p3 : larger_10_V_9_fu_5278_p4);
assign larger_V_11_1_fu_5320_p3 = ((tmp_1339_1_1_fu_3256_p2[0:0] === 1'b1) ? larger_11_V_fu_5310_p4 : p_s_fu_5302_p3);
assign larger_V_11_2_fu_5338_p3 = ((tmp_1339_2_1_fu_3504_p2[0:0] === 1'b1) ? larger_11_V_1_fu_5328_p4 : larger_V_11_1_fu_5320_p3);
assign larger_V_11_3_fu_5356_p3 = ((tmp_1339_3_1_fu_3746_p2[0:0] === 1'b1) ? larger_11_V_2_fu_5346_p4 : larger_V_11_2_fu_5338_p3);
assign larger_V_11_4_fu_5374_p3 = ((tmp_1339_4_1_fu_3982_p2[0:0] === 1'b1) ? larger_11_V_3_fu_5364_p4 : larger_V_11_3_fu_5356_p3);
assign larger_V_11_5_fu_5392_p3 = ((tmp_1339_5_1_fu_4212_p2[0:0] === 1'b1) ? larger_11_V_4_fu_5382_p4 : larger_V_11_4_fu_5374_p3);
assign larger_V_11_6_fu_5410_p3 = ((tmp_1339_6_1_fu_4436_p2[0:0] === 1'b1) ? larger_11_V_5_fu_5400_p4 : larger_V_11_5_fu_5392_p3);
assign larger_V_11_7_fu_5428_p3 = ((tmp_1339_7_1_fu_4654_p2[0:0] === 1'b1) ? larger_11_V_6_fu_5418_p4 : larger_V_11_6_fu_5410_p3);
assign larger_V_11_8_fu_5446_p3 = ((tmp_1339_8_1_fu_4866_p2[0:0] === 1'b1) ? larger_11_V_7_fu_5436_p4 : larger_V_11_7_fu_5428_p3);
assign larger_V_11_9_fu_5464_p3 = ((tmp_1339_9_1_fu_5072_p2[0:0] === 1'b1) ? larger_11_V_8_fu_5454_p4 : larger_V_11_8_fu_5446_p3);
assign larger_V_11_s_fu_5482_p3 = ((tmp_1339_10_s_fu_5272_p2[0:0] === 1'b1) ? larger_11_V_9_fu_5472_p4 : larger_V_11_9_fu_5464_p3);
assign larger_V_9_1_fu_4914_p3 = ((tmp_1339_1_9_fu_3208_p2[0:0] === 1'b1) ? larger_9_V_fu_4904_p4 : p_20_cast_cast_fu_4896_p3);
assign larger_V_9_2_fu_4932_p3 = ((tmp_1339_2_9_fu_3456_p2[0:0] === 1'b1) ? larger_9_V_1_fu_4922_p4 : larger_V_9_1_fu_4914_p3);
assign larger_V_9_3_fu_4950_p3 = ((tmp_1339_3_9_fu_3698_p2[0:0] === 1'b1) ? larger_9_V_2_fu_4940_p4 : larger_V_9_2_fu_4932_p3);
assign larger_V_9_4_fu_4968_p3 = ((tmp_1339_4_9_fu_3934_p2[0:0] === 1'b1) ? larger_9_V_3_fu_4958_p4 : larger_V_9_3_fu_4950_p3);
assign larger_V_9_5_fu_4986_p3 = ((tmp_1339_5_9_fu_4164_p2[0:0] === 1'b1) ? larger_9_V_4_fu_4976_p4 : larger_V_9_4_fu_4968_p3);
assign larger_V_9_6_fu_5004_p3 = ((tmp_1339_6_9_fu_4388_p2[0:0] === 1'b1) ? larger_9_V_5_fu_4994_p4 : larger_V_9_5_fu_4986_p3);
assign larger_V_9_7_fu_5022_p3 = ((tmp_1339_7_9_fu_4606_p2[0:0] === 1'b1) ? larger_9_V_6_fu_5012_p4 : larger_V_9_6_fu_5004_p3);
assign larger_V_9_8_fu_5040_p3 = ((tmp_1339_8_9_fu_4818_p2[0:0] === 1'b1) ? larger_9_V_7_fu_5030_p4 : larger_V_9_7_fu_5022_p3);
assign larger_V_9_9_fu_5064_p3 = ((tmp_1339_9_s_fu_5048_p2[0:0] === 1'b1) ? larger_V_9_8_fu_5040_p3 : larger_9_V_8_fu_5054_p4);
assign larger_V_9_s_fu_5088_p3 = ((tmp_1339_9_1_fu_5072_p2[0:0] === 1'b1) ? larger_V_9_9_fu_5064_p3 : larger_9_V_9_fu_5078_p4);
assign larger_V_load_fu_3008_p3 = ((tmp_1339_0_10_fu_2992_p2[0:0] === 1'b1) ? p_Val2_388_0_1_fu_2984_p3 : tmp_1285_fu_2998_p4);
assign lhs_i143_0_i_10_fu_15300_p2 = (tmp_1878_fu_15202_p1 & lhs_i_i147_0_i_10_fu_15294_p2);
assign lhs_i143_0_i_1_fu_8810_p2 = (tmp_1608_fu_8712_p1 & lhs_i_i147_0_i_1_fu_8804_p2);
assign lhs_i143_0_i_2_fu_9486_p2 = (tmp_1635_fu_9388_p1 & lhs_i_i147_0_i_2_fu_9480_p2);
assign lhs_i143_0_i_3_fu_10132_p2 = (tmp_1662_fu_10034_p1 & lhs_i_i147_0_i_3_fu_10126_p2);
assign lhs_i143_0_i_4_fu_10778_p2 = (tmp_1689_fu_10680_p1 & lhs_i_i147_0_i_4_fu_10772_p2);
assign lhs_i143_0_i_5_fu_11424_p2 = (tmp_1716_fu_11326_p1 & lhs_i_i147_0_i_5_fu_11418_p2);
assign lhs_i143_0_i_6_fu_12070_p2 = (tmp_1743_fu_11972_p1 & lhs_i_i147_0_i_6_fu_12064_p2);
assign lhs_i143_0_i_7_fu_12716_p2 = (tmp_1770_fu_12618_p1 & lhs_i_i147_0_i_7_fu_12710_p2);
assign lhs_i143_0_i_8_fu_13362_p2 = (tmp_1797_fu_13264_p1 & lhs_i_i147_0_i_8_fu_13356_p2);
assign lhs_i143_0_i_9_fu_14008_p2 = (tmp_1824_fu_13910_p1 & lhs_i_i147_0_i_9_fu_14002_p2);
assign lhs_i143_0_i_fu_8116_p2 = (tmp_1588_fu_8018_p1 & lhs_i_i147_0_i_fu_8110_p2);
assign lhs_i143_0_i_s_fu_14654_p2 = (tmp_1851_fu_14556_p1 & lhs_i_i147_0_i_s_fu_14648_p2);
assign lhs_i55_0_i_10_fu_15612_p2 = (tmp_1886_fu_15262_p3 & lhs_i_i59_0_i1_10_fu_15606_p2);
assign lhs_i55_0_i_1_fu_9122_p2 = (tmp_1616_fu_8772_p3 & lhs_i_i59_0_i1_1_fu_9116_p2);
assign lhs_i55_0_i_2_fu_9798_p2 = (tmp_1643_fu_9448_p3 & lhs_i_i59_0_i1_2_fu_9792_p2);
assign lhs_i55_0_i_3_fu_10444_p2 = (tmp_1670_fu_10094_p3 & lhs_i_i59_0_i1_3_fu_10438_p2);
assign lhs_i55_0_i_4_fu_11090_p2 = (tmp_1697_fu_10740_p3 & lhs_i_i59_0_i1_4_fu_11084_p2);
assign lhs_i55_0_i_5_fu_11736_p2 = (tmp_1724_fu_11386_p3 & lhs_i_i59_0_i1_5_fu_11730_p2);
assign lhs_i55_0_i_6_fu_12382_p2 = (tmp_1751_fu_12032_p3 & lhs_i_i59_0_i1_6_fu_12376_p2);
assign lhs_i55_0_i_7_fu_13028_p2 = (tmp_1778_fu_12678_p3 & lhs_i_i59_0_i1_7_fu_13022_p2);
assign lhs_i55_0_i_8_fu_13674_p2 = (tmp_1805_fu_13324_p3 & lhs_i_i59_0_i1_8_fu_13668_p2);
assign lhs_i55_0_i_9_fu_14320_p2 = (tmp_1832_fu_13970_p3 & lhs_i_i59_0_i1_9_fu_14314_p2);
assign lhs_i55_0_i_fu_8428_p2 = (tmp_1596_fu_8078_p3 & lhs_i_i59_0_i1_fu_8422_p2);
assign lhs_i55_0_i_s_fu_14966_p2 = (tmp_1859_fu_14616_p3 & lhs_i_i59_0_i1_s_fu_14960_p2);
assign lhs_i99_0_i_10_fu_15456_p2 = (tmp_1882_fu_15230_p3 & lhs_i_i103_0_i_10_fu_15450_p2);
assign lhs_i99_0_i_1_fu_8966_p2 = (tmp_1612_fu_8740_p3 & lhs_i_i103_0_i_1_fu_8960_p2);
assign lhs_i99_0_i_2_fu_9642_p2 = (tmp_1639_fu_9416_p3 & lhs_i_i103_0_i_2_fu_9636_p2);
assign lhs_i99_0_i_3_fu_10288_p2 = (tmp_1666_fu_10062_p3 & lhs_i_i103_0_i_3_fu_10282_p2);
assign lhs_i99_0_i_4_fu_10934_p2 = (tmp_1693_fu_10708_p3 & lhs_i_i103_0_i_4_fu_10928_p2);
assign lhs_i99_0_i_5_fu_11580_p2 = (tmp_1720_fu_11354_p3 & lhs_i_i103_0_i_5_fu_11574_p2);
assign lhs_i99_0_i_6_fu_12226_p2 = (tmp_1747_fu_12000_p3 & lhs_i_i103_0_i_6_fu_12220_p2);
assign lhs_i99_0_i_7_fu_12872_p2 = (tmp_1774_fu_12646_p3 & lhs_i_i103_0_i_7_fu_12866_p2);
assign lhs_i99_0_i_8_fu_13518_p2 = (tmp_1801_fu_13292_p3 & lhs_i_i103_0_i_8_fu_13512_p2);
assign lhs_i99_0_i_9_fu_14164_p2 = (tmp_1828_fu_13938_p3 & lhs_i_i103_0_i_9_fu_14158_p2);
assign lhs_i99_0_i_fu_8272_p2 = (tmp_1592_fu_8046_p3 & lhs_i_i103_0_i_fu_8266_p2);
assign lhs_i99_0_i_s_fu_14810_p2 = (tmp_1855_fu_14584_p3 & lhs_i_i103_0_i_s_fu_14804_p2);
assign lhs_i_i101_0_demorgan2303_i_10_fu_15462_p2 = (tmp_1879_fu_15206_p3 | tmp_1880_fu_15214_p3);
assign lhs_i_i101_0_demorgan2303_i_1_fu_8972_p2 = (tmp_1609_fu_8716_p3 | tmp_1610_fu_8724_p3);
assign lhs_i_i101_0_demorgan2303_i_2_fu_9648_p2 = (tmp_1636_fu_9392_p3 | tmp_1637_fu_9400_p3);
assign lhs_i_i101_0_demorgan2303_i_3_fu_10294_p2 = (tmp_1663_fu_10038_p3 | tmp_1664_fu_10046_p3);
assign lhs_i_i101_0_demorgan2303_i_4_fu_10940_p2 = (tmp_1690_fu_10684_p3 | tmp_1691_fu_10692_p3);
assign lhs_i_i101_0_demorgan2303_i_5_fu_11586_p2 = (tmp_1717_fu_11330_p3 | tmp_1718_fu_11338_p3);
assign lhs_i_i101_0_demorgan2303_i_6_fu_12232_p2 = (tmp_1744_fu_11976_p3 | tmp_1745_fu_11984_p3);
assign lhs_i_i101_0_demorgan2303_i_7_fu_12878_p2 = (tmp_1771_fu_12622_p3 | tmp_1772_fu_12630_p3);
assign lhs_i_i101_0_demorgan2303_i_8_fu_13524_p2 = (tmp_1798_fu_13268_p3 | tmp_1799_fu_13276_p3);
assign lhs_i_i101_0_demorgan2303_i_9_fu_14170_p2 = (tmp_1825_fu_13914_p3 | tmp_1826_fu_13922_p3);
assign lhs_i_i101_0_demorgan2303_i_fu_8278_p2 = (tmp_1589_fu_8022_p3 | tmp_1590_fu_8030_p3);
assign lhs_i_i101_0_demorgan2303_i_s_fu_14816_p2 = (tmp_1852_fu_14560_p3 | tmp_1853_fu_14568_p3);
assign lhs_i_i101_0_i_10_fu_15468_p2 = (lhs_i_i101_0_demorgan2303_i_10_fu_15462_p2 ^ 1'b1);
assign lhs_i_i101_0_i_1_fu_8978_p2 = (lhs_i_i101_0_demorgan2303_i_1_fu_8972_p2 ^ 1'b1);
assign lhs_i_i101_0_i_2_fu_9654_p2 = (lhs_i_i101_0_demorgan2303_i_2_fu_9648_p2 ^ 1'b1);
assign lhs_i_i101_0_i_3_fu_10300_p2 = (lhs_i_i101_0_demorgan2303_i_3_fu_10294_p2 ^ 1'b1);
assign lhs_i_i101_0_i_4_fu_10946_p2 = (lhs_i_i101_0_demorgan2303_i_4_fu_10940_p2 ^ 1'b1);
assign lhs_i_i101_0_i_5_fu_11592_p2 = (lhs_i_i101_0_demorgan2303_i_5_fu_11586_p2 ^ 1'b1);
assign lhs_i_i101_0_i_6_fu_12238_p2 = (lhs_i_i101_0_demorgan2303_i_6_fu_12232_p2 ^ 1'b1);
assign lhs_i_i101_0_i_7_fu_12884_p2 = (lhs_i_i101_0_demorgan2303_i_7_fu_12878_p2 ^ 1'b1);
assign lhs_i_i101_0_i_8_fu_13530_p2 = (lhs_i_i101_0_demorgan2303_i_8_fu_13524_p2 ^ 1'b1);
assign lhs_i_i101_0_i_9_fu_14176_p2 = (lhs_i_i101_0_demorgan2303_i_9_fu_14170_p2 ^ 1'b1);
assign lhs_i_i101_0_i_fu_8284_p2 = (lhs_i_i101_0_demorgan2303_i_fu_8278_p2 ^ 1'b1);
assign lhs_i_i101_0_i_s_fu_14822_p2 = (lhs_i_i101_0_demorgan2303_i_s_fu_14816_p2 ^ 1'b1);
assign lhs_i_i103_0_demorgan2302_i_10_fu_15444_p2 = (tmp_1879_fu_15206_p3 | tmp_1881_fu_15222_p3);
assign lhs_i_i103_0_demorgan2302_i_1_fu_8954_p2 = (tmp_1609_fu_8716_p3 | tmp_1611_fu_8732_p3);
assign lhs_i_i103_0_demorgan2302_i_2_fu_9630_p2 = (tmp_1636_fu_9392_p3 | tmp_1638_fu_9408_p3);
assign lhs_i_i103_0_demorgan2302_i_3_fu_10276_p2 = (tmp_1663_fu_10038_p3 | tmp_1665_fu_10054_p3);
assign lhs_i_i103_0_demorgan2302_i_4_fu_10922_p2 = (tmp_1690_fu_10684_p3 | tmp_1692_fu_10700_p3);
assign lhs_i_i103_0_demorgan2302_i_5_fu_11568_p2 = (tmp_1717_fu_11330_p3 | tmp_1719_fu_11346_p3);
assign lhs_i_i103_0_demorgan2302_i_6_fu_12214_p2 = (tmp_1744_fu_11976_p3 | tmp_1746_fu_11992_p3);
assign lhs_i_i103_0_demorgan2302_i_7_fu_12860_p2 = (tmp_1771_fu_12622_p3 | tmp_1773_fu_12638_p3);
assign lhs_i_i103_0_demorgan2302_i_8_fu_13506_p2 = (tmp_1798_fu_13268_p3 | tmp_1800_fu_13284_p3);
assign lhs_i_i103_0_demorgan2302_i_9_fu_14152_p2 = (tmp_1825_fu_13914_p3 | tmp_1827_fu_13930_p3);
assign lhs_i_i103_0_demorgan2302_i_fu_8260_p2 = (tmp_1589_fu_8022_p3 | tmp_1591_fu_8038_p3);
assign lhs_i_i103_0_demorgan2302_i_s_fu_14798_p2 = (tmp_1852_fu_14560_p3 | tmp_1854_fu_14576_p3);
assign lhs_i_i103_0_i_10_fu_15450_p2 = (lhs_i_i103_0_demorgan2302_i_10_fu_15444_p2 ^ 1'b1);
assign lhs_i_i103_0_i_1_fu_8960_p2 = (lhs_i_i103_0_demorgan2302_i_1_fu_8954_p2 ^ 1'b1);
assign lhs_i_i103_0_i_2_fu_9636_p2 = (lhs_i_i103_0_demorgan2302_i_2_fu_9630_p2 ^ 1'b1);
assign lhs_i_i103_0_i_3_fu_10282_p2 = (lhs_i_i103_0_demorgan2302_i_3_fu_10276_p2 ^ 1'b1);
assign lhs_i_i103_0_i_4_fu_10928_p2 = (lhs_i_i103_0_demorgan2302_i_4_fu_10922_p2 ^ 1'b1);
assign lhs_i_i103_0_i_5_fu_11574_p2 = (lhs_i_i103_0_demorgan2302_i_5_fu_11568_p2 ^ 1'b1);
assign lhs_i_i103_0_i_6_fu_12220_p2 = (lhs_i_i103_0_demorgan2302_i_6_fu_12214_p2 ^ 1'b1);
assign lhs_i_i103_0_i_7_fu_12866_p2 = (lhs_i_i103_0_demorgan2302_i_7_fu_12860_p2 ^ 1'b1);
assign lhs_i_i103_0_i_8_fu_13512_p2 = (lhs_i_i103_0_demorgan2302_i_8_fu_13506_p2 ^ 1'b1);
assign lhs_i_i103_0_i_9_fu_14158_p2 = (lhs_i_i103_0_demorgan2302_i_9_fu_14152_p2 ^ 1'b1);
assign lhs_i_i103_0_i_fu_8266_p2 = (lhs_i_i103_0_demorgan2302_i_fu_8260_p2 ^ 1'b1);
assign lhs_i_i103_0_i_s_fu_14804_p2 = (lhs_i_i103_0_demorgan2302_i_s_fu_14798_p2 ^ 1'b1);
assign lhs_i_i135_0_i_10_fu_15336_p2 = (tmp_1876_fu_15186_p3 ^ 1'b1);
assign lhs_i_i135_0_i_1_fu_8846_p2 = (tmp_1606_fu_8696_p3 ^ 1'b1);
assign lhs_i_i135_0_i_2_fu_9522_p2 = (tmp_1633_fu_9372_p3 ^ 1'b1);
assign lhs_i_i135_0_i_3_fu_10168_p2 = (tmp_1660_fu_10018_p3 ^ 1'b1);
assign lhs_i_i135_0_i_4_fu_10814_p2 = (tmp_1687_fu_10664_p3 ^ 1'b1);
assign lhs_i_i135_0_i_5_fu_11460_p2 = (tmp_1714_fu_11310_p3 ^ 1'b1);
assign lhs_i_i135_0_i_6_fu_12106_p2 = (tmp_1741_fu_11956_p3 ^ 1'b1);
assign lhs_i_i135_0_i_7_fu_12752_p2 = (tmp_1768_fu_12602_p3 ^ 1'b1);
assign lhs_i_i135_0_i_8_fu_13398_p2 = (tmp_1795_fu_13248_p3 ^ 1'b1);
assign lhs_i_i135_0_i_9_fu_14044_p2 = (tmp_1822_fu_13894_p3 ^ 1'b1);
assign lhs_i_i135_0_i_fu_8152_p2 = (tmp_1586_fu_8002_p3 ^ 1'b1);
assign lhs_i_i135_0_i_s_fu_14690_p2 = (tmp_1849_fu_14540_p3 ^ 1'b1);
assign lhs_i_i141_0_i_10_fu_15318_p2 = (tmp_1875_fu_15178_p3 ^ 1'b1);
assign lhs_i_i141_0_i_1_fu_8828_p2 = (tmp_1605_fu_8688_p3 ^ 1'b1);
assign lhs_i_i141_0_i_2_fu_9504_p2 = (tmp_1632_fu_9364_p3 ^ 1'b1);
assign lhs_i_i141_0_i_3_fu_10150_p2 = (tmp_1659_fu_10010_p3 ^ 1'b1);
assign lhs_i_i141_0_i_4_fu_10796_p2 = (tmp_1686_fu_10656_p3 ^ 1'b1);
assign lhs_i_i141_0_i_5_fu_11442_p2 = (tmp_1713_fu_11302_p3 ^ 1'b1);
assign lhs_i_i141_0_i_6_fu_12088_p2 = (tmp_1740_fu_11948_p3 ^ 1'b1);
assign lhs_i_i141_0_i_7_fu_12734_p2 = (tmp_1767_fu_12594_p3 ^ 1'b1);
assign lhs_i_i141_0_i_8_fu_13380_p2 = (tmp_1794_fu_13240_p3 ^ 1'b1);
assign lhs_i_i141_0_i_9_fu_14026_p2 = (tmp_1821_fu_13886_p3 ^ 1'b1);
assign lhs_i_i141_0_i_fu_8134_p2 = (tmp_1585_fu_7994_p3 ^ 1'b1);
assign lhs_i_i141_0_i_s_fu_14672_p2 = (tmp_1848_fu_14532_p3 ^ 1'b1);
assign lhs_i_i145_0_demorgan2295_i_10_fu_15306_p2 = (tmp_1875_fu_15178_p3 | tmp_1876_fu_15186_p3);
assign lhs_i_i145_0_demorgan2295_i_1_fu_8816_p2 = (tmp_1605_fu_8688_p3 | tmp_1606_fu_8696_p3);
assign lhs_i_i145_0_demorgan2295_i_2_fu_9492_p2 = (tmp_1632_fu_9364_p3 | tmp_1633_fu_9372_p3);
assign lhs_i_i145_0_demorgan2295_i_3_fu_10138_p2 = (tmp_1659_fu_10010_p3 | tmp_1660_fu_10018_p3);
assign lhs_i_i145_0_demorgan2295_i_4_fu_10784_p2 = (tmp_1686_fu_10656_p3 | tmp_1687_fu_10664_p3);
assign lhs_i_i145_0_demorgan2295_i_5_fu_11430_p2 = (tmp_1713_fu_11302_p3 | tmp_1714_fu_11310_p3);
assign lhs_i_i145_0_demorgan2295_i_6_fu_12076_p2 = (tmp_1740_fu_11948_p3 | tmp_1741_fu_11956_p3);
assign lhs_i_i145_0_demorgan2295_i_7_fu_12722_p2 = (tmp_1767_fu_12594_p3 | tmp_1768_fu_12602_p3);
assign lhs_i_i145_0_demorgan2295_i_8_fu_13368_p2 = (tmp_1794_fu_13240_p3 | tmp_1795_fu_13248_p3);
assign lhs_i_i145_0_demorgan2295_i_9_fu_14014_p2 = (tmp_1821_fu_13886_p3 | tmp_1822_fu_13894_p3);
assign lhs_i_i145_0_demorgan2295_i_fu_8122_p2 = (tmp_1585_fu_7994_p3 | tmp_1586_fu_8002_p3);
assign lhs_i_i145_0_demorgan2295_i_s_fu_14660_p2 = (tmp_1848_fu_14532_p3 | tmp_1849_fu_14540_p3);
assign lhs_i_i145_0_i_10_fu_15312_p2 = (lhs_i_i145_0_demorgan2295_i_10_fu_15306_p2 ^ 1'b1);
assign lhs_i_i145_0_i_1_fu_8822_p2 = (lhs_i_i145_0_demorgan2295_i_1_fu_8816_p2 ^ 1'b1);
assign lhs_i_i145_0_i_2_fu_9498_p2 = (lhs_i_i145_0_demorgan2295_i_2_fu_9492_p2 ^ 1'b1);
assign lhs_i_i145_0_i_3_fu_10144_p2 = (lhs_i_i145_0_demorgan2295_i_3_fu_10138_p2 ^ 1'b1);
assign lhs_i_i145_0_i_4_fu_10790_p2 = (lhs_i_i145_0_demorgan2295_i_4_fu_10784_p2 ^ 1'b1);
assign lhs_i_i145_0_i_5_fu_11436_p2 = (lhs_i_i145_0_demorgan2295_i_5_fu_11430_p2 ^ 1'b1);
assign lhs_i_i145_0_i_6_fu_12082_p2 = (lhs_i_i145_0_demorgan2295_i_6_fu_12076_p2 ^ 1'b1);
assign lhs_i_i145_0_i_7_fu_12728_p2 = (lhs_i_i145_0_demorgan2295_i_7_fu_12722_p2 ^ 1'b1);
assign lhs_i_i145_0_i_8_fu_13374_p2 = (lhs_i_i145_0_demorgan2295_i_8_fu_13368_p2 ^ 1'b1);
assign lhs_i_i145_0_i_9_fu_14020_p2 = (lhs_i_i145_0_demorgan2295_i_9_fu_14014_p2 ^ 1'b1);
assign lhs_i_i145_0_i_fu_8128_p2 = (lhs_i_i145_0_demorgan2295_i_fu_8122_p2 ^ 1'b1);
assign lhs_i_i145_0_i_s_fu_14666_p2 = (lhs_i_i145_0_demorgan2295_i_s_fu_14660_p2 ^ 1'b1);
assign lhs_i_i147_0_demorgan2294_i_10_fu_15288_p2 = (tmp_1875_fu_15178_p3 | tmp_1877_fu_15194_p3);
assign lhs_i_i147_0_demorgan2294_i_1_fu_8798_p2 = (tmp_1605_fu_8688_p3 | tmp_1607_fu_8704_p3);
assign lhs_i_i147_0_demorgan2294_i_2_fu_9474_p2 = (tmp_1632_fu_9364_p3 | tmp_1634_fu_9380_p3);
assign lhs_i_i147_0_demorgan2294_i_3_fu_10120_p2 = (tmp_1659_fu_10010_p3 | tmp_1661_fu_10026_p3);
assign lhs_i_i147_0_demorgan2294_i_4_fu_10766_p2 = (tmp_1686_fu_10656_p3 | tmp_1688_fu_10672_p3);
assign lhs_i_i147_0_demorgan2294_i_5_fu_11412_p2 = (tmp_1713_fu_11302_p3 | tmp_1715_fu_11318_p3);
assign lhs_i_i147_0_demorgan2294_i_6_fu_12058_p2 = (tmp_1740_fu_11948_p3 | tmp_1742_fu_11964_p3);
assign lhs_i_i147_0_demorgan2294_i_7_fu_12704_p2 = (tmp_1767_fu_12594_p3 | tmp_1769_fu_12610_p3);
assign lhs_i_i147_0_demorgan2294_i_8_fu_13350_p2 = (tmp_1794_fu_13240_p3 | tmp_1796_fu_13256_p3);
assign lhs_i_i147_0_demorgan2294_i_9_fu_13996_p2 = (tmp_1821_fu_13886_p3 | tmp_1823_fu_13902_p3);
assign lhs_i_i147_0_demorgan2294_i_fu_8104_p2 = (tmp_1585_fu_7994_p3 | tmp_1587_fu_8010_p3);
assign lhs_i_i147_0_demorgan2294_i_s_fu_14642_p2 = (tmp_1848_fu_14532_p3 | tmp_1850_fu_14548_p3);
assign lhs_i_i147_0_i_10_fu_15294_p2 = (lhs_i_i147_0_demorgan2294_i_10_fu_15288_p2 ^ 1'b1);
assign lhs_i_i147_0_i_1_fu_8804_p2 = (lhs_i_i147_0_demorgan2294_i_1_fu_8798_p2 ^ 1'b1);
assign lhs_i_i147_0_i_2_fu_9480_p2 = (lhs_i_i147_0_demorgan2294_i_2_fu_9474_p2 ^ 1'b1);
assign lhs_i_i147_0_i_3_fu_10126_p2 = (lhs_i_i147_0_demorgan2294_i_3_fu_10120_p2 ^ 1'b1);
assign lhs_i_i147_0_i_4_fu_10772_p2 = (lhs_i_i147_0_demorgan2294_i_4_fu_10766_p2 ^ 1'b1);
assign lhs_i_i147_0_i_5_fu_11418_p2 = (lhs_i_i147_0_demorgan2294_i_5_fu_11412_p2 ^ 1'b1);
assign lhs_i_i147_0_i_6_fu_12064_p2 = (lhs_i_i147_0_demorgan2294_i_6_fu_12058_p2 ^ 1'b1);
assign lhs_i_i147_0_i_7_fu_12710_p2 = (lhs_i_i147_0_demorgan2294_i_7_fu_12704_p2 ^ 1'b1);
assign lhs_i_i147_0_i_8_fu_13356_p2 = (lhs_i_i147_0_demorgan2294_i_8_fu_13350_p2 ^ 1'b1);
assign lhs_i_i147_0_i_9_fu_14002_p2 = (lhs_i_i147_0_demorgan2294_i_9_fu_13996_p2 ^ 1'b1);
assign lhs_i_i147_0_i_fu_8110_p2 = (lhs_i_i147_0_demorgan2294_i_fu_8104_p2 ^ 1'b1);
assign lhs_i_i147_0_i_s_fu_14648_p2 = (lhs_i_i147_0_demorgan2294_i_s_fu_14642_p2 ^ 1'b1);
assign lhs_i_i47_0_i_10_fu_15648_p2 = (tmp_1884_fu_15246_p3 ^ 1'b1);
assign lhs_i_i47_0_i_1_fu_9158_p2 = (tmp_1614_fu_8756_p3 ^ 1'b1);
assign lhs_i_i47_0_i_2_fu_9834_p2 = (tmp_1641_fu_9432_p3 ^ 1'b1);
assign lhs_i_i47_0_i_3_fu_10480_p2 = (tmp_1668_fu_10078_p3 ^ 1'b1);
assign lhs_i_i47_0_i_4_fu_11126_p2 = (tmp_1695_fu_10724_p3 ^ 1'b1);
assign lhs_i_i47_0_i_5_fu_11772_p2 = (tmp_1722_fu_11370_p3 ^ 1'b1);
assign lhs_i_i47_0_i_6_fu_12418_p2 = (tmp_1749_fu_12016_p3 ^ 1'b1);
assign lhs_i_i47_0_i_7_fu_13064_p2 = (tmp_1776_fu_12662_p3 ^ 1'b1);
assign lhs_i_i47_0_i_8_fu_13710_p2 = (tmp_1803_fu_13308_p3 ^ 1'b1);
assign lhs_i_i47_0_i_9_fu_14356_p2 = (tmp_1830_fu_13954_p3 ^ 1'b1);
assign lhs_i_i47_0_i_fu_8464_p2 = (tmp_1594_fu_8062_p3 ^ 1'b1);
assign lhs_i_i47_0_i_s_fu_15002_p2 = (tmp_1857_fu_14600_p3 ^ 1'b1);
assign lhs_i_i53_0_i_10_fu_15630_p2 = (tmp_1883_fu_15238_p3 ^ 1'b1);
assign lhs_i_i53_0_i_1_fu_9140_p2 = (tmp_1613_fu_8748_p3 ^ 1'b1);
assign lhs_i_i53_0_i_2_fu_9816_p2 = (tmp_1640_fu_9424_p3 ^ 1'b1);
assign lhs_i_i53_0_i_3_fu_10462_p2 = (tmp_1667_fu_10070_p3 ^ 1'b1);
assign lhs_i_i53_0_i_4_fu_11108_p2 = (tmp_1694_fu_10716_p3 ^ 1'b1);
assign lhs_i_i53_0_i_5_fu_11754_p2 = (tmp_1721_fu_11362_p3 ^ 1'b1);
assign lhs_i_i53_0_i_6_fu_12400_p2 = (tmp_1748_fu_12008_p3 ^ 1'b1);
assign lhs_i_i53_0_i_7_fu_13046_p2 = (tmp_1775_fu_12654_p3 ^ 1'b1);
assign lhs_i_i53_0_i_8_fu_13692_p2 = (tmp_1802_fu_13300_p3 ^ 1'b1);
assign lhs_i_i53_0_i_9_fu_14338_p2 = (tmp_1829_fu_13946_p3 ^ 1'b1);
assign lhs_i_i53_0_i_fu_8446_p2 = (tmp_1593_fu_8054_p3 ^ 1'b1);
assign lhs_i_i53_0_i_s_fu_14984_p2 = (tmp_1856_fu_14592_p3 ^ 1'b1);
assign lhs_i_i57_0_demorgan2311_i_10_fu_15618_p2 = (tmp_1883_fu_15238_p3 | tmp_1884_fu_15246_p3);
assign lhs_i_i57_0_demorgan2311_i_1_fu_9128_p2 = (tmp_1613_fu_8748_p3 | tmp_1614_fu_8756_p3);
assign lhs_i_i57_0_demorgan2311_i_2_fu_9804_p2 = (tmp_1640_fu_9424_p3 | tmp_1641_fu_9432_p3);
assign lhs_i_i57_0_demorgan2311_i_3_fu_10450_p2 = (tmp_1667_fu_10070_p3 | tmp_1668_fu_10078_p3);
assign lhs_i_i57_0_demorgan2311_i_4_fu_11096_p2 = (tmp_1694_fu_10716_p3 | tmp_1695_fu_10724_p3);
assign lhs_i_i57_0_demorgan2311_i_5_fu_11742_p2 = (tmp_1721_fu_11362_p3 | tmp_1722_fu_11370_p3);
assign lhs_i_i57_0_demorgan2311_i_6_fu_12388_p2 = (tmp_1748_fu_12008_p3 | tmp_1749_fu_12016_p3);
assign lhs_i_i57_0_demorgan2311_i_7_fu_13034_p2 = (tmp_1775_fu_12654_p3 | tmp_1776_fu_12662_p3);
assign lhs_i_i57_0_demorgan2311_i_8_fu_13680_p2 = (tmp_1802_fu_13300_p3 | tmp_1803_fu_13308_p3);
assign lhs_i_i57_0_demorgan2311_i_9_fu_14326_p2 = (tmp_1829_fu_13946_p3 | tmp_1830_fu_13954_p3);
assign lhs_i_i57_0_demorgan2311_i_fu_8434_p2 = (tmp_1593_fu_8054_p3 | tmp_1594_fu_8062_p3);
assign lhs_i_i57_0_demorgan2311_i_s_fu_14972_p2 = (tmp_1856_fu_14592_p3 | tmp_1857_fu_14600_p3);
assign lhs_i_i57_0_i_10_fu_15624_p2 = (lhs_i_i57_0_demorgan2311_i_10_fu_15618_p2 ^ 1'b1);
assign lhs_i_i57_0_i_1_fu_9134_p2 = (lhs_i_i57_0_demorgan2311_i_1_fu_9128_p2 ^ 1'b1);
assign lhs_i_i57_0_i_2_fu_9810_p2 = (lhs_i_i57_0_demorgan2311_i_2_fu_9804_p2 ^ 1'b1);
assign lhs_i_i57_0_i_3_fu_10456_p2 = (lhs_i_i57_0_demorgan2311_i_3_fu_10450_p2 ^ 1'b1);
assign lhs_i_i57_0_i_4_fu_11102_p2 = (lhs_i_i57_0_demorgan2311_i_4_fu_11096_p2 ^ 1'b1);
assign lhs_i_i57_0_i_5_fu_11748_p2 = (lhs_i_i57_0_demorgan2311_i_5_fu_11742_p2 ^ 1'b1);
assign lhs_i_i57_0_i_6_fu_12394_p2 = (lhs_i_i57_0_demorgan2311_i_6_fu_12388_p2 ^ 1'b1);
assign lhs_i_i57_0_i_7_fu_13040_p2 = (lhs_i_i57_0_demorgan2311_i_7_fu_13034_p2 ^ 1'b1);
assign lhs_i_i57_0_i_8_fu_13686_p2 = (lhs_i_i57_0_demorgan2311_i_8_fu_13680_p2 ^ 1'b1);
assign lhs_i_i57_0_i_9_fu_14332_p2 = (lhs_i_i57_0_demorgan2311_i_9_fu_14326_p2 ^ 1'b1);
assign lhs_i_i57_0_i_fu_8440_p2 = (lhs_i_i57_0_demorgan2311_i_fu_8434_p2 ^ 1'b1);
assign lhs_i_i57_0_i_s_fu_14978_p2 = (lhs_i_i57_0_demorgan2311_i_s_fu_14972_p2 ^ 1'b1);
assign lhs_i_i59_0_demorgan2310_i_10_fu_15600_p2 = (tmp_1883_fu_15238_p3 | tmp_1885_fu_15254_p3);
assign lhs_i_i59_0_demorgan2310_i_1_fu_9110_p2 = (tmp_1613_fu_8748_p3 | tmp_1615_fu_8764_p3);
assign lhs_i_i59_0_demorgan2310_i_2_fu_9786_p2 = (tmp_1640_fu_9424_p3 | tmp_1642_fu_9440_p3);
assign lhs_i_i59_0_demorgan2310_i_3_fu_10432_p2 = (tmp_1667_fu_10070_p3 | tmp_1669_fu_10086_p3);
assign lhs_i_i59_0_demorgan2310_i_4_fu_11078_p2 = (tmp_1694_fu_10716_p3 | tmp_1696_fu_10732_p3);
assign lhs_i_i59_0_demorgan2310_i_5_fu_11724_p2 = (tmp_1721_fu_11362_p3 | tmp_1723_fu_11378_p3);
assign lhs_i_i59_0_demorgan2310_i_6_fu_12370_p2 = (tmp_1748_fu_12008_p3 | tmp_1750_fu_12024_p3);
assign lhs_i_i59_0_demorgan2310_i_7_fu_13016_p2 = (tmp_1775_fu_12654_p3 | tmp_1777_fu_12670_p3);
assign lhs_i_i59_0_demorgan2310_i_8_fu_13662_p2 = (tmp_1802_fu_13300_p3 | tmp_1804_fu_13316_p3);
assign lhs_i_i59_0_demorgan2310_i_9_fu_14308_p2 = (tmp_1829_fu_13946_p3 | tmp_1831_fu_13962_p3);
assign lhs_i_i59_0_demorgan2310_i_fu_8416_p2 = (tmp_1593_fu_8054_p3 | tmp_1595_fu_8070_p3);
assign lhs_i_i59_0_demorgan2310_i_s_fu_14954_p2 = (tmp_1856_fu_14592_p3 | tmp_1858_fu_14608_p3);
assign lhs_i_i59_0_i1_10_fu_15606_p2 = (lhs_i_i59_0_demorgan2310_i_10_fu_15600_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_1_fu_9116_p2 = (lhs_i_i59_0_demorgan2310_i_1_fu_9110_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_2_fu_9792_p2 = (lhs_i_i59_0_demorgan2310_i_2_fu_9786_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_3_fu_10438_p2 = (lhs_i_i59_0_demorgan2310_i_3_fu_10432_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_4_fu_11084_p2 = (lhs_i_i59_0_demorgan2310_i_4_fu_11078_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_5_fu_11730_p2 = (lhs_i_i59_0_demorgan2310_i_5_fu_11724_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_6_fu_12376_p2 = (lhs_i_i59_0_demorgan2310_i_6_fu_12370_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_7_fu_13022_p2 = (lhs_i_i59_0_demorgan2310_i_7_fu_13016_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_8_fu_13668_p2 = (lhs_i_i59_0_demorgan2310_i_8_fu_13662_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_9_fu_14314_p2 = (lhs_i_i59_0_demorgan2310_i_9_fu_14308_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_fu_8422_p2 = (lhs_i_i59_0_demorgan2310_i_fu_8416_p2 ^ 1'b1);
assign lhs_i_i59_0_i1_s_fu_14960_p2 = (lhs_i_i59_0_demorgan2310_i_s_fu_14954_p2 ^ 1'b1);
assign lhs_i_i91_0_i_10_fu_15492_p2 = (tmp_1880_fu_15214_p3 ^ 1'b1);
assign lhs_i_i91_0_i_1_fu_9002_p2 = (tmp_1610_fu_8724_p3 ^ 1'b1);
assign lhs_i_i91_0_i_2_fu_9678_p2 = (tmp_1637_fu_9400_p3 ^ 1'b1);
assign lhs_i_i91_0_i_3_fu_10324_p2 = (tmp_1664_fu_10046_p3 ^ 1'b1);
assign lhs_i_i91_0_i_4_fu_10970_p2 = (tmp_1691_fu_10692_p3 ^ 1'b1);
assign lhs_i_i91_0_i_5_fu_11616_p2 = (tmp_1718_fu_11338_p3 ^ 1'b1);
assign lhs_i_i91_0_i_6_fu_12262_p2 = (tmp_1745_fu_11984_p3 ^ 1'b1);
assign lhs_i_i91_0_i_7_fu_12908_p2 = (tmp_1772_fu_12630_p3 ^ 1'b1);
assign lhs_i_i91_0_i_8_fu_13554_p2 = (tmp_1799_fu_13276_p3 ^ 1'b1);
assign lhs_i_i91_0_i_9_fu_14200_p2 = (tmp_1826_fu_13922_p3 ^ 1'b1);
assign lhs_i_i91_0_i_fu_8308_p2 = (tmp_1590_fu_8030_p3 ^ 1'b1);
assign lhs_i_i91_0_i_s_fu_14846_p2 = (tmp_1853_fu_14568_p3 ^ 1'b1);
assign lhs_i_i97_0_i_10_fu_15474_p2 = (tmp_1879_fu_15206_p3 ^ 1'b1);
assign lhs_i_i97_0_i_1_fu_8984_p2 = (tmp_1609_fu_8716_p3 ^ 1'b1);
assign lhs_i_i97_0_i_2_fu_9660_p2 = (tmp_1636_fu_9392_p3 ^ 1'b1);
assign lhs_i_i97_0_i_3_fu_10306_p2 = (tmp_1663_fu_10038_p3 ^ 1'b1);
assign lhs_i_i97_0_i_4_fu_10952_p2 = (tmp_1690_fu_10684_p3 ^ 1'b1);
assign lhs_i_i97_0_i_5_fu_11598_p2 = (tmp_1717_fu_11330_p3 ^ 1'b1);
assign lhs_i_i97_0_i_6_fu_12244_p2 = (tmp_1744_fu_11976_p3 ^ 1'b1);
assign lhs_i_i97_0_i_7_fu_12890_p2 = (tmp_1771_fu_12622_p3 ^ 1'b1);
assign lhs_i_i97_0_i_8_fu_13536_p2 = (tmp_1798_fu_13268_p3 ^ 1'b1);
assign lhs_i_i97_0_i_9_fu_14182_p2 = (tmp_1825_fu_13914_p3 ^ 1'b1);
assign lhs_i_i97_0_i_fu_8290_p2 = (tmp_1589_fu_8022_p3 ^ 1'b1);
assign lhs_i_i97_0_i_s_fu_14828_p2 = (tmp_1852_fu_14560_p3 ^ 1'b1);
assign p_01272_0_not_fu_7964_p2 = (p_Result_1299_s_fu_5496_p13 ^ ap_const_lv12_FFF);
assign p_0190_i_10_fu_15786_p2 = (tmp_1398_10_fu_15762_p1 + tmp1015_fu_15780_p2);
assign p_0190_i_1_fu_9296_p2 = (tmp_1398_1_fu_9272_p1 + tmp199_fu_9290_p2);
assign p_0190_i_2_fu_9972_p2 = (tmp_1398_2_fu_9948_p1 + tmp232_fu_9966_p2);
assign p_0190_i_3_fu_10618_p2 = (tmp_1398_3_fu_10594_p1 + tmp265_fu_10612_p2);
assign p_0190_i_4_fu_11264_p2 = (tmp_1398_4_fu_11240_p1 + tmp628_fu_11258_p2);
assign p_0190_i_5_fu_11910_p2 = (tmp_1398_5_fu_11886_p1 + tmp661_fu_11904_p2);
assign p_0190_i_6_fu_12556_p2 = (tmp_1398_6_fu_12532_p1 + tmp694_fu_12550_p2);
assign p_0190_i_7_fu_13202_p2 = (tmp_1398_7_fu_13178_p1 + tmp729_fu_13196_p2);
assign p_0190_i_8_fu_13848_p2 = (tmp_1398_8_fu_13824_p1 + tmp922_fu_13842_p2);
assign p_0190_i_9_fu_14494_p2 = (tmp_1398_9_fu_14470_p1 + tmp953_fu_14488_p2);
assign p_0190_i_fu_8602_p2 = (tmp_331_fu_8578_p1 + tmp166_fu_8596_p2);
assign p_0190_i_s_fu_15140_p2 = (tmp_1398_s_fu_15116_p1 + tmp984_fu_15134_p2);
assign p_12_cast_cast_fu_3030_p3 = ((tmp_1339_0_1_fu_2752_p2[0:0] === 1'b1) ? ap_const_lv12_3 : ap_const_lv12_2);
assign p_12_cast_fu_3022_p3 = ((tmp_1339_0_1_fu_2752_p2[0:0] === 1'b1) ? ap_const_lv2_3 : ap_const_lv2_2);
assign p_13_cast_cast_fu_3286_p3 = ((tmp_1339_0_2_fu_2774_p2[0:0] === 1'b1) ? ap_const_lv12_5 : ap_const_lv12_4);
assign p_14_cast_cast_fu_3534_p3 = ((tmp_1339_0_3_fu_2800_p2[0:0] === 1'b1) ? ap_const_lv12_9 : ap_const_lv12_8);
assign p_15_cast_cast_fu_3776_p3 = ((tmp_1339_0_4_fu_2824_p2[0:0] === 1'b1) ? ap_const_lv12_11 : ap_const_lv12_10);
assign p_16_cast_cast_fu_4012_p3 = ((tmp_1339_0_5_fu_2848_p2[0:0] === 1'b1) ? ap_const_lv12_21 : ap_const_lv12_20);
assign p_17_cast_cast_fu_4242_p3 = ((tmp_1339_0_6_fu_2872_p2[0:0] === 1'b1) ? ap_const_lv12_41 : ap_const_lv12_40);
assign p_18_cast_cast_fu_4466_p3 = ((tmp_1339_0_7_fu_2896_p2[0:0] === 1'b1) ? ap_const_lv12_81 : ap_const_lv12_80);
assign p_19_cast_cast_fu_4684_p3 = ((tmp_1339_0_8_fu_2920_p2[0:0] === 1'b1) ? ap_const_lv12_101 : ap_const_lv12_100);
assign p_20_cast_cast_fu_4896_p3 = ((tmp_1339_0_9_fu_2944_p2[0:0] === 1'b1) ? ap_const_lv12_201 : ap_const_lv12_200);
assign p_21_cast_cast_fu_5102_p3 = ((tmp_1339_0_s_fu_2968_p2[0:0] === 1'b1) ? ap_const_lv12_401 : ap_const_lv12_400);
assign p_33_10_fu_15164_p2 = (rhs_i_i_fu_7974_p2 | larger_V_11_s_fu_5482_p3);
assign p_33_1_fu_8674_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_1_fu_3272_p3);
assign p_33_2_fu_9350_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_2_fu_3520_p3);
assign p_33_3_fu_9996_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_3_fu_3762_p3);
assign p_33_4_fu_10642_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_4_fu_3998_p3);
assign p_33_5_fu_11288_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_5_fu_4228_p3);
assign p_33_6_fu_11934_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_6_fu_4452_p3);
assign p_33_7_fu_12580_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_7_fu_4670_p3);
assign p_33_8_fu_13226_p2 = (rhs_i_i_fu_7974_p2 | p_Val2_393_8_fu_4882_p3);
assign p_33_9_fu_13872_p2 = (rhs_i_i_fu_7974_p2 | larger_V_9_s_fu_5088_p3);
assign p_33_s_fu_14518_p2 = (rhs_i_i_fu_7974_p2 | larger_V_10_s_fu_5288_p3);
assign p_9_fu_7980_p2 = (rhs_i_i_fu_7974_p2 | larger_V_load_fu_3008_p3);
assign p_Result_1247_0_2_fu_2788_p1 = tmp_1256_fu_2780_p3;
assign p_Result_1247_1_2_fu_3052_p1 = tmp_1298_fu_3044_p3;
assign p_Result_1290_0_10_5_fu_22479_p7 = {{{{{{tmp_518_fu_22474_p2}, {tmp_516_fu_22448_p2}}, {tmp_514_fu_22422_p2}}, {tmp_512_fu_22396_p2}}, {tmp_510_fu_22370_p2}}, {tmp_508_fu_22348_p2}};
assign p_Result_1290_0_11_5_fu_22889_p7 = {{{{{{tmp_533_fu_22884_p2}, {tmp_531_fu_22858_p2}}, {tmp_529_fu_22832_p2}}, {tmp_527_fu_22806_p2}}, {tmp_525_fu_22780_p2}}, {tmp_523_fu_22758_p2}};
assign p_Result_1290_0_1_5_fu_18213_p7 = {{{{{{tmp_366_fu_18208_p2}, {tmp_364_fu_18182_p2}}, {tmp_362_fu_18156_p2}}, {tmp_360_fu_18130_p2}}, {tmp_358_fu_18104_p2}}, {tmp_356_fu_18082_p2}};
assign p_Result_1290_0_2_5_fu_18629_p7 = {{{{{{tmp_381_fu_18624_p2}, {tmp_379_fu_18598_p2}}, {tmp_377_fu_18572_p2}}, {tmp_375_fu_18546_p2}}, {tmp_373_fu_18520_p2}}, {tmp_371_fu_18498_p2}};
assign p_Result_1290_0_3_5_fu_19039_p7 = {{{{{{tmp_396_fu_19034_p2}, {tmp_394_fu_19008_p2}}, {tmp_392_fu_18982_p2}}, {tmp_390_fu_18956_p2}}, {tmp_388_fu_18930_p2}}, {tmp_386_fu_18908_p2}};
assign p_Result_1290_0_4_5_fu_19585_p7 = {{{{{{tmp_413_fu_19580_p2}, {tmp_411_fu_19554_p2}}, {tmp_409_fu_19528_p2}}, {tmp_407_fu_19502_p2}}, {tmp_405_fu_19476_p2}}, {tmp_403_fu_19454_p2}};
assign p_Result_1290_0_5_5_fu_20087_p7 = {{{{{{tmp_432_fu_20082_p2}, {tmp_430_fu_20056_p2}}, {tmp_428_fu_20030_p2}}, {tmp_426_fu_20004_p2}}, {tmp_424_fu_19978_p2}}, {tmp_422_fu_19956_p2}};
assign p_Result_1290_0_6_5_fu_20567_p7 = {{{{{{tmp_450_fu_20562_p2}, {tmp_448_fu_20536_p2}}, {tmp_446_fu_20510_p2}}, {tmp_444_fu_20484_p2}}, {tmp_442_fu_20458_p2}}, {tmp_440_fu_20436_p2}};
assign p_Result_1290_0_7_5_fu_20985_p7 = {{{{{{tmp_465_fu_20980_p2}, {tmp_463_fu_20954_p2}}, {tmp_461_fu_20928_p2}}, {tmp_459_fu_20902_p2}}, {tmp_457_fu_20876_p2}}, {tmp_455_fu_20854_p2}};
assign p_Result_1290_0_8_5_fu_21509_p7 = {{{{{{tmp_481_fu_21504_p2}, {tmp_479_fu_21478_p2}}, {tmp_477_fu_21452_p2}}, {tmp_475_fu_21426_p2}}, {tmp_473_fu_21400_p2}}, {tmp_471_fu_21378_p2}};
assign p_Result_1290_0_9_5_fu_21991_p7 = {{{{{{tmp_500_fu_21986_p2}, {tmp_498_fu_21960_p2}}, {tmp_496_fu_21934_p2}}, {tmp_494_fu_21908_p2}}, {tmp_492_fu_21882_p2}}, {tmp_490_fu_21860_p2}};
assign p_Result_1290_1_10_5_fu_29316_p7 = {{{{{{tmp_701_fu_29311_p2}, {tmp_699_fu_29285_p2}}, {tmp_697_fu_29259_p2}}, {tmp_695_fu_29233_p2}}, {tmp_693_fu_29207_p2}}, {tmp_691_fu_29185_p2}};
assign p_Result_1290_1_11_5_fu_29726_p7 = {{{{{{tmp_716_fu_29721_p2}, {tmp_714_fu_29695_p2}}, {tmp_712_fu_29669_p2}}, {tmp_710_fu_29643_p2}}, {tmp_708_fu_29617_p2}}, {tmp_706_fu_29595_p2}};
assign p_Result_1290_1_1_5_fu_25054_p7 = {{{{{{tmp_549_fu_25049_p2}, {tmp_547_fu_25023_p2}}, {tmp_545_fu_24997_p2}}, {tmp_543_fu_24971_p2}}, {tmp_541_fu_24945_p2}}, {tmp_539_fu_24923_p2}};
assign p_Result_1290_1_2_5_fu_25470_p7 = {{{{{{tmp_564_fu_25465_p2}, {tmp_562_fu_25439_p2}}, {tmp_560_fu_25413_p2}}, {tmp_558_fu_25387_p2}}, {tmp_556_fu_25361_p2}}, {tmp_554_fu_25339_p2}};
assign p_Result_1290_1_3_5_fu_25880_p7 = {{{{{{tmp_579_fu_25875_p2}, {tmp_577_fu_25849_p2}}, {tmp_575_fu_25823_p2}}, {tmp_573_fu_25797_p2}}, {tmp_571_fu_25771_p2}}, {tmp_569_fu_25749_p2}};
assign p_Result_1290_1_4_5_fu_26422_p7 = {{{{{{tmp_596_fu_26417_p2}, {tmp_594_fu_26391_p2}}, {tmp_592_fu_26365_p2}}, {tmp_590_fu_26339_p2}}, {tmp_588_fu_26313_p2}}, {tmp_586_fu_26291_p2}};
assign p_Result_1290_1_5_5_fu_26924_p7 = {{{{{{tmp_615_fu_26919_p2}, {tmp_613_fu_26893_p2}}, {tmp_611_fu_26867_p2}}, {tmp_609_fu_26841_p2}}, {tmp_607_fu_26815_p2}}, {tmp_605_fu_26793_p2}};
assign p_Result_1290_1_6_5_fu_27404_p7 = {{{{{{tmp_633_fu_27399_p2}, {tmp_631_fu_27373_p2}}, {tmp_629_fu_27347_p2}}, {tmp_627_fu_27321_p2}}, {tmp_625_fu_27295_p2}}, {tmp_623_fu_27273_p2}};
assign p_Result_1290_1_7_5_fu_27822_p7 = {{{{{{tmp_648_fu_27817_p2}, {tmp_646_fu_27791_p2}}, {tmp_644_fu_27765_p2}}, {tmp_642_fu_27739_p2}}, {tmp_640_fu_27713_p2}}, {tmp_638_fu_27691_p2}};
assign p_Result_1290_1_8_5_fu_28346_p7 = {{{{{{tmp_664_fu_28341_p2}, {tmp_662_fu_28315_p2}}, {tmp_660_fu_28289_p2}}, {tmp_658_fu_28263_p2}}, {tmp_656_fu_28237_p2}}, {tmp_654_fu_28215_p2}};
assign p_Result_1290_1_9_5_fu_28828_p7 = {{{{{{tmp_683_fu_28823_p2}, {tmp_681_fu_28797_p2}}, {tmp_679_fu_28771_p2}}, {tmp_677_fu_28745_p2}}, {tmp_675_fu_28719_p2}}, {tmp_673_fu_28697_p2}};
assign p_Result_1290_2_10_5_fu_36153_p7 = {{{{{{tmp_884_fu_36148_p2}, {tmp_882_fu_36122_p2}}, {tmp_880_fu_36096_p2}}, {tmp_878_fu_36070_p2}}, {tmp_876_fu_36044_p2}}, {tmp_874_fu_36022_p2}};
assign p_Result_1290_2_11_5_fu_36563_p7 = {{{{{{tmp_899_fu_36558_p2}, {tmp_897_fu_36532_p2}}, {tmp_895_fu_36506_p2}}, {tmp_893_fu_36480_p2}}, {tmp_891_fu_36454_p2}}, {tmp_889_fu_36432_p2}};
assign p_Result_1290_2_1_5_fu_31891_p7 = {{{{{{tmp_732_fu_31886_p2}, {tmp_730_fu_31860_p2}}, {tmp_728_fu_31834_p2}}, {tmp_726_fu_31808_p2}}, {tmp_724_fu_31782_p2}}, {tmp_722_fu_31760_p2}};
assign p_Result_1290_2_2_5_fu_32307_p7 = {{{{{{tmp_747_fu_32302_p2}, {tmp_745_fu_32276_p2}}, {tmp_743_fu_32250_p2}}, {tmp_741_fu_32224_p2}}, {tmp_739_fu_32198_p2}}, {tmp_737_fu_32176_p2}};
assign p_Result_1290_2_3_5_fu_32717_p7 = {{{{{{tmp_762_fu_32712_p2}, {tmp_760_fu_32686_p2}}, {tmp_758_fu_32660_p2}}, {tmp_756_fu_32634_p2}}, {tmp_754_fu_32608_p2}}, {tmp_752_fu_32586_p2}};
assign p_Result_1290_2_4_5_fu_33259_p7 = {{{{{{tmp_779_fu_33254_p2}, {tmp_777_fu_33228_p2}}, {tmp_775_fu_33202_p2}}, {tmp_773_fu_33176_p2}}, {tmp_771_fu_33150_p2}}, {tmp_769_fu_33128_p2}};
assign p_Result_1290_2_5_5_fu_33761_p7 = {{{{{{tmp_798_fu_33756_p2}, {tmp_796_fu_33730_p2}}, {tmp_794_fu_33704_p2}}, {tmp_792_fu_33678_p2}}, {tmp_790_fu_33652_p2}}, {tmp_788_fu_33630_p2}};
assign p_Result_1290_2_6_5_fu_34241_p7 = {{{{{{tmp_816_fu_34236_p2}, {tmp_814_fu_34210_p2}}, {tmp_812_fu_34184_p2}}, {tmp_810_fu_34158_p2}}, {tmp_808_fu_34132_p2}}, {tmp_806_fu_34110_p2}};
assign p_Result_1290_2_7_5_fu_34659_p7 = {{{{{{tmp_831_fu_34654_p2}, {tmp_829_fu_34628_p2}}, {tmp_827_fu_34602_p2}}, {tmp_825_fu_34576_p2}}, {tmp_823_fu_34550_p2}}, {tmp_821_fu_34528_p2}};
assign p_Result_1290_2_8_5_fu_35183_p7 = {{{{{{tmp_847_fu_35178_p2}, {tmp_845_fu_35152_p2}}, {tmp_843_fu_35126_p2}}, {tmp_841_fu_35100_p2}}, {tmp_839_fu_35074_p2}}, {tmp_837_fu_35052_p2}};
assign p_Result_1290_2_9_5_fu_35665_p7 = {{{{{{tmp_866_fu_35660_p2}, {tmp_864_fu_35634_p2}}, {tmp_862_fu_35608_p2}}, {tmp_860_fu_35582_p2}}, {tmp_858_fu_35556_p2}}, {tmp_856_fu_35534_p2}};
assign p_Result_1293_0_10_5_fu_22508_p7 = {{{{{{tmp_519_fu_22503_p2}, {tmp_517_fu_22461_p2}}, {tmp_515_fu_22435_p2}}, {tmp_513_fu_22409_p2}}, {tmp_511_fu_22383_p2}}, {tmp_509_fu_22357_p2}};
assign p_Result_1293_0_11_5_fu_22918_p7 = {{{{{{tmp_534_fu_22913_p2}, {tmp_532_fu_22871_p2}}, {tmp_530_fu_22845_p2}}, {tmp_528_fu_22819_p2}}, {tmp_526_fu_22793_p2}}, {tmp_524_fu_22767_p2}};
assign p_Result_1293_0_1_5_fu_18242_p7 = {{{{{{tmp_367_fu_18237_p2}, {tmp_365_fu_18195_p2}}, {tmp_363_fu_18169_p2}}, {tmp_361_fu_18143_p2}}, {tmp_359_fu_18117_p2}}, {tmp_357_fu_18091_p2}};
assign p_Result_1293_0_2_5_fu_18658_p7 = {{{{{{tmp_382_fu_18653_p2}, {tmp_380_fu_18611_p2}}, {tmp_378_fu_18585_p2}}, {tmp_376_fu_18559_p2}}, {tmp_374_fu_18533_p2}}, {tmp_372_fu_18507_p2}};
assign p_Result_1293_0_3_5_fu_19068_p7 = {{{{{{tmp_397_fu_19063_p2}, {tmp_395_fu_19021_p2}}, {tmp_393_fu_18995_p2}}, {tmp_391_fu_18969_p2}}, {tmp_389_fu_18943_p2}}, {tmp_387_fu_18917_p2}};
assign p_Result_1293_0_4_5_fu_19614_p7 = {{{{{{tmp_414_fu_19609_p2}, {tmp_412_fu_19567_p2}}, {tmp_410_fu_19541_p2}}, {tmp_408_fu_19515_p2}}, {tmp_406_fu_19489_p2}}, {tmp_404_fu_19463_p2}};
assign p_Result_1293_0_5_5_fu_20116_p7 = {{{{{{tmp_433_fu_20111_p2}, {tmp_431_fu_20069_p2}}, {tmp_429_fu_20043_p2}}, {tmp_427_fu_20017_p2}}, {tmp_425_fu_19991_p2}}, {tmp_423_fu_19965_p2}};
assign p_Result_1293_0_6_5_fu_20596_p7 = {{{{{{tmp_451_fu_20591_p2}, {tmp_449_fu_20549_p2}}, {tmp_447_fu_20523_p2}}, {tmp_445_fu_20497_p2}}, {tmp_443_fu_20471_p2}}, {tmp_441_fu_20445_p2}};
assign p_Result_1293_0_7_5_fu_21014_p7 = {{{{{{tmp_466_fu_21009_p2}, {tmp_464_fu_20967_p2}}, {tmp_462_fu_20941_p2}}, {tmp_460_fu_20915_p2}}, {tmp_458_fu_20889_p2}}, {tmp_456_fu_20863_p2}};
assign p_Result_1293_0_8_5_fu_21538_p7 = {{{{{{tmp_482_fu_21533_p2}, {tmp_480_fu_21491_p2}}, {tmp_478_fu_21465_p2}}, {tmp_476_fu_21439_p2}}, {tmp_474_fu_21413_p2}}, {tmp_472_fu_21387_p2}};
assign p_Result_1293_0_9_5_fu_22020_p7 = {{{{{{tmp_501_fu_22015_p2}, {tmp_499_fu_21973_p2}}, {tmp_497_fu_21947_p2}}, {tmp_495_fu_21921_p2}}, {tmp_493_fu_21895_p2}}, {tmp_491_fu_21869_p2}};
assign p_Result_1293_1_10_5_fu_29345_p7 = {{{{{{tmp_702_fu_29340_p2}, {tmp_700_fu_29298_p2}}, {tmp_698_fu_29272_p2}}, {tmp_696_fu_29246_p2}}, {tmp_694_fu_29220_p2}}, {tmp_692_fu_29194_p2}};
assign p_Result_1293_1_11_5_fu_29755_p7 = {{{{{{tmp_717_fu_29750_p2}, {tmp_715_fu_29708_p2}}, {tmp_713_fu_29682_p2}}, {tmp_711_fu_29656_p2}}, {tmp_709_fu_29630_p2}}, {tmp_707_fu_29604_p2}};
assign p_Result_1293_1_1_5_fu_25083_p7 = {{{{{{tmp_550_fu_25078_p2}, {tmp_548_fu_25036_p2}}, {tmp_546_fu_25010_p2}}, {tmp_544_fu_24984_p2}}, {tmp_542_fu_24958_p2}}, {tmp_540_fu_24932_p2}};
assign p_Result_1293_1_2_5_fu_25499_p7 = {{{{{{tmp_565_fu_25494_p2}, {tmp_563_fu_25452_p2}}, {tmp_561_fu_25426_p2}}, {tmp_559_fu_25400_p2}}, {tmp_557_fu_25374_p2}}, {tmp_555_fu_25348_p2}};
assign p_Result_1293_1_3_5_fu_25909_p7 = {{{{{{tmp_580_fu_25904_p2}, {tmp_578_fu_25862_p2}}, {tmp_576_fu_25836_p2}}, {tmp_574_fu_25810_p2}}, {tmp_572_fu_25784_p2}}, {tmp_570_fu_25758_p2}};
assign p_Result_1293_1_4_5_fu_26451_p7 = {{{{{{tmp_597_fu_26446_p2}, {tmp_595_fu_26404_p2}}, {tmp_593_fu_26378_p2}}, {tmp_591_fu_26352_p2}}, {tmp_589_fu_26326_p2}}, {tmp_587_fu_26300_p2}};
assign p_Result_1293_1_5_5_fu_26953_p7 = {{{{{{tmp_616_fu_26948_p2}, {tmp_614_fu_26906_p2}}, {tmp_612_fu_26880_p2}}, {tmp_610_fu_26854_p2}}, {tmp_608_fu_26828_p2}}, {tmp_606_fu_26802_p2}};
assign p_Result_1293_1_6_5_fu_27433_p7 = {{{{{{tmp_634_fu_27428_p2}, {tmp_632_fu_27386_p2}}, {tmp_630_fu_27360_p2}}, {tmp_628_fu_27334_p2}}, {tmp_626_fu_27308_p2}}, {tmp_624_fu_27282_p2}};
assign p_Result_1293_1_7_5_fu_27851_p7 = {{{{{{tmp_649_fu_27846_p2}, {tmp_647_fu_27804_p2}}, {tmp_645_fu_27778_p2}}, {tmp_643_fu_27752_p2}}, {tmp_641_fu_27726_p2}}, {tmp_639_fu_27700_p2}};
assign p_Result_1293_1_8_5_fu_28375_p7 = {{{{{{tmp_665_fu_28370_p2}, {tmp_663_fu_28328_p2}}, {tmp_661_fu_28302_p2}}, {tmp_659_fu_28276_p2}}, {tmp_657_fu_28250_p2}}, {tmp_655_fu_28224_p2}};
assign p_Result_1293_1_9_5_fu_28857_p7 = {{{{{{tmp_684_fu_28852_p2}, {tmp_682_fu_28810_p2}}, {tmp_680_fu_28784_p2}}, {tmp_678_fu_28758_p2}}, {tmp_676_fu_28732_p2}}, {tmp_674_fu_28706_p2}};
assign p_Result_1293_2_10_5_fu_36182_p7 = {{{{{{tmp_885_fu_36177_p2}, {tmp_883_fu_36135_p2}}, {tmp_881_fu_36109_p2}}, {tmp_879_fu_36083_p2}}, {tmp_877_fu_36057_p2}}, {tmp_875_fu_36031_p2}};
assign p_Result_1293_2_11_5_fu_36592_p7 = {{{{{{tmp_900_fu_36587_p2}, {tmp_898_fu_36545_p2}}, {tmp_896_fu_36519_p2}}, {tmp_894_fu_36493_p2}}, {tmp_892_fu_36467_p2}}, {tmp_890_fu_36441_p2}};
assign p_Result_1293_2_1_5_fu_31920_p7 = {{{{{{tmp_733_fu_31915_p2}, {tmp_731_fu_31873_p2}}, {tmp_729_fu_31847_p2}}, {tmp_727_fu_31821_p2}}, {tmp_725_fu_31795_p2}}, {tmp_723_fu_31769_p2}};
assign p_Result_1293_2_2_5_fu_32336_p7 = {{{{{{tmp_748_fu_32331_p2}, {tmp_746_fu_32289_p2}}, {tmp_744_fu_32263_p2}}, {tmp_742_fu_32237_p2}}, {tmp_740_fu_32211_p2}}, {tmp_738_fu_32185_p2}};
assign p_Result_1293_2_3_5_fu_32746_p7 = {{{{{{tmp_763_fu_32741_p2}, {tmp_761_fu_32699_p2}}, {tmp_759_fu_32673_p2}}, {tmp_757_fu_32647_p2}}, {tmp_755_fu_32621_p2}}, {tmp_753_fu_32595_p2}};
assign p_Result_1293_2_4_5_fu_33288_p7 = {{{{{{tmp_780_fu_33283_p2}, {tmp_778_fu_33241_p2}}, {tmp_776_fu_33215_p2}}, {tmp_774_fu_33189_p2}}, {tmp_772_fu_33163_p2}}, {tmp_770_fu_33137_p2}};
assign p_Result_1293_2_5_5_fu_33790_p7 = {{{{{{tmp_799_fu_33785_p2}, {tmp_797_fu_33743_p2}}, {tmp_795_fu_33717_p2}}, {tmp_793_fu_33691_p2}}, {tmp_791_fu_33665_p2}}, {tmp_789_fu_33639_p2}};
assign p_Result_1293_2_6_5_fu_34270_p7 = {{{{{{tmp_817_fu_34265_p2}, {tmp_815_fu_34223_p2}}, {tmp_813_fu_34197_p2}}, {tmp_811_fu_34171_p2}}, {tmp_809_fu_34145_p2}}, {tmp_807_fu_34119_p2}};
assign p_Result_1293_2_7_5_fu_34688_p7 = {{{{{{tmp_832_fu_34683_p2}, {tmp_830_fu_34641_p2}}, {tmp_828_fu_34615_p2}}, {tmp_826_fu_34589_p2}}, {tmp_824_fu_34563_p2}}, {tmp_822_fu_34537_p2}};
assign p_Result_1293_2_8_5_fu_35212_p7 = {{{{{{tmp_848_fu_35207_p2}, {tmp_846_fu_35165_p2}}, {tmp_844_fu_35139_p2}}, {tmp_842_fu_35113_p2}}, {tmp_840_fu_35087_p2}}, {tmp_838_fu_35061_p2}};
assign p_Result_1293_2_9_5_fu_35694_p7 = {{{{{{tmp_867_fu_35689_p2}, {tmp_865_fu_35647_p2}}, {tmp_863_fu_35621_p2}}, {tmp_861_fu_35595_p2}}, {tmp_859_fu_35569_p2}}, {tmp_857_fu_35543_p2}};
assign p_Result_1296_0_0_4_fu_17906_p4 = {{{{1'b0}, {ap_reg_ppstg_tmp_231_reg_40703_pp0_iter1}}}, {tmp_1902_fu_17902_p1}};
assign p_Result_1296_0_10_4_fu_22567_p6 = {{{{{tmp_2234_fu_22559_p3}, {tmp_522_fu_22554_p2}}, {tmp_521_fu_22541_p2}}, {1'b1}}, {tmp_520_fu_22528_p2}};
assign p_Result_1296_0_11_4_fu_22977_p6 = {{{{{tmp_2264_fu_22969_p3}, {tmp_537_fu_22964_p2}}, {tmp_536_fu_22951_p2}}, {1'b1}}, {tmp_535_fu_22938_p2}};
assign p_Result_1296_0_1_4_fu_18301_p6 = {{{{{tmp_1932_fu_18293_p3}, {tmp_370_fu_18288_p2}}, {tmp_369_fu_18275_p2}}, {1'b1}}, {tmp_368_fu_18262_p2}};
assign p_Result_1296_0_2_4_fu_18717_p6 = {{{{{tmp_1963_fu_18709_p3}, {tmp_385_fu_18704_p2}}, {tmp_384_fu_18691_p2}}, {1'b1}}, {tmp_383_fu_18678_p2}};
assign p_Result_1296_0_3_4_fu_19127_p6 = {{{{{tmp_1993_fu_19119_p3}, {tmp_400_fu_19114_p2}}, {tmp_399_fu_19101_p2}}, {1'b1}}, {tmp_398_fu_19088_p2}};
assign p_Result_1296_0_4_4_fu_19741_p6 = {{{{{tmp_2037_fu_19733_p3}, {tmp_421_fu_19728_p2}}, {tmp_419_fu_19701_p2}}, {1'b1}}, {tmp_417_fu_19674_p2}};
assign p_Result_1296_0_5_4_fu_20229_p6 = {{{{{tmp_2070_fu_20221_p3}, {tmp_439_fu_20216_p2}}, {tmp_438_fu_20203_p2}}, {1'b1}}, {tmp_436_fu_20164_p2}};
assign p_Result_1296_0_6_4_fu_20655_p6 = {{{{{tmp_2100_fu_20647_p3}, {tmp_454_fu_20642_p2}}, {tmp_453_fu_20629_p2}}, {1'b1}}, {tmp_452_fu_20616_p2}};
assign p_Result_1296_0_7_4_fu_21073_p6 = {{{{{tmp_2130_fu_21065_p3}, {tmp_469_fu_21060_p2}}, {tmp_468_fu_21047_p2}}, {1'b1}}, {tmp_467_fu_21034_p2}};
assign p_Result_1296_0_8_4_fu_21653_p6 = {{{{{tmp_2171_fu_21645_p3}, {tmp_489_fu_21640_p2}}, {tmp_487_fu_21613_p2}}, {1'b1}}, {tmp_485_fu_21586_p2}};
assign p_Result_1296_0_9_4_fu_22133_p6 = {{{{{tmp_2204_fu_22125_p3}, {tmp_507_fu_22120_p2}}, {tmp_506_fu_22107_p2}}, {1'b1}}, {tmp_504_fu_22068_p2}};
assign p_Result_1296_1_10_4_fu_29404_p6 = {{{{{tmp_2484_fu_29396_p3}, {tmp_705_fu_29391_p2}}, {tmp_704_fu_29378_p2}}, {1'b1}}, {tmp_703_fu_29365_p2}};
assign p_Result_1296_1_11_4_fu_29814_p6 = {{{{{tmp_2501_fu_29806_p3}, {tmp_720_fu_29801_p2}}, {tmp_719_fu_29788_p2}}, {1'b1}}, {tmp_718_fu_29775_p2}};
assign p_Result_1296_1_1_4_fu_25142_p6 = {{{{{tmp_2300_fu_25134_p3}, {tmp_553_fu_25129_p2}}, {tmp_552_fu_25116_p2}}, {1'b1}}, {tmp_551_fu_25103_p2}};
assign p_Result_1296_1_2_4_fu_25558_p6 = {{{{{tmp_2318_fu_25550_p3}, {tmp_568_fu_25545_p2}}, {tmp_567_fu_25532_p2}}, {1'b1}}, {tmp_566_fu_25519_p2}};
assign p_Result_1296_1_3_4_fu_25968_p6 = {{{{{tmp_2335_fu_25960_p3}, {tmp_583_fu_25955_p2}}, {tmp_582_fu_25942_p2}}, {1'b1}}, {tmp_581_fu_25929_p2}};
assign p_Result_1296_1_4_4_fu_26578_p6 = {{{{{tmp_2365_fu_26570_p3}, {tmp_604_fu_26565_p2}}, {tmp_602_fu_26538_p2}}, {1'b1}}, {tmp_600_fu_26511_p2}};
assign p_Result_1296_1_5_4_fu_27066_p6 = {{{{{tmp_2385_fu_27058_p3}, {tmp_622_fu_27053_p2}}, {tmp_621_fu_27040_p2}}, {1'b1}}, {tmp_619_fu_27001_p2}};
assign p_Result_1296_1_6_4_fu_27492_p6 = {{{{{tmp_2402_fu_27484_p3}, {tmp_637_fu_27479_p2}}, {tmp_636_fu_27466_p2}}, {1'b1}}, {tmp_635_fu_27453_p2}};
assign p_Result_1296_1_7_4_fu_27910_p6 = {{{{{tmp_2419_fu_27902_p3}, {tmp_652_fu_27897_p2}}, {tmp_651_fu_27884_p2}}, {1'b1}}, {tmp_650_fu_27871_p2}};
assign p_Result_1296_1_8_4_fu_28490_p6 = {{{{{tmp_2447_fu_28482_p3}, {tmp_672_fu_28477_p2}}, {tmp_670_fu_28450_p2}}, {1'b1}}, {tmp_668_fu_28423_p2}};
assign p_Result_1296_1_9_4_fu_28970_p6 = {{{{{tmp_2467_fu_28962_p3}, {tmp_690_fu_28957_p2}}, {tmp_689_fu_28944_p2}}, {1'b1}}, {tmp_687_fu_28905_p2}};
assign p_Result_1296_2_10_4_fu_36241_p6 = {{{{{tmp_2721_fu_36233_p3}, {tmp_888_fu_36228_p2}}, {tmp_887_fu_36215_p2}}, {1'b1}}, {tmp_886_fu_36202_p2}};
assign p_Result_1296_2_11_4_fu_36651_p6 = {{{{{tmp_2738_fu_36643_p3}, {tmp_903_fu_36638_p2}}, {tmp_902_fu_36625_p2}}, {1'b1}}, {tmp_901_fu_36612_p2}};
assign p_Result_1296_2_1_4_fu_31979_p6 = {{{{{tmp_2537_fu_31971_p3}, {tmp_736_fu_31966_p2}}, {tmp_735_fu_31953_p2}}, {1'b1}}, {tmp_734_fu_31940_p2}};
assign p_Result_1296_2_2_4_fu_32395_p6 = {{{{{tmp_2555_fu_32387_p3}, {tmp_751_fu_32382_p2}}, {tmp_750_fu_32369_p2}}, {1'b1}}, {tmp_749_fu_32356_p2}};
assign p_Result_1296_2_3_4_fu_32805_p6 = {{{{{tmp_2572_fu_32797_p3}, {tmp_766_fu_32792_p2}}, {tmp_765_fu_32779_p2}}, {1'b1}}, {tmp_764_fu_32766_p2}};
assign p_Result_1296_2_4_4_fu_33415_p6 = {{{{{tmp_2602_fu_33407_p3}, {tmp_787_fu_33402_p2}}, {tmp_785_fu_33375_p2}}, {1'b1}}, {tmp_783_fu_33348_p2}};
assign p_Result_1296_2_5_4_fu_33903_p6 = {{{{{tmp_2622_fu_33895_p3}, {tmp_805_fu_33890_p2}}, {tmp_804_fu_33877_p2}}, {1'b1}}, {tmp_802_fu_33838_p2}};
assign p_Result_1296_2_6_4_fu_34329_p6 = {{{{{tmp_2639_fu_34321_p3}, {tmp_820_fu_34316_p2}}, {tmp_819_fu_34303_p2}}, {1'b1}}, {tmp_818_fu_34290_p2}};
assign p_Result_1296_2_7_4_fu_34747_p6 = {{{{{tmp_2656_fu_34739_p3}, {tmp_835_fu_34734_p2}}, {tmp_834_fu_34721_p2}}, {1'b1}}, {tmp_833_fu_34708_p2}};
assign p_Result_1296_2_8_4_fu_35327_p6 = {{{{{tmp_2684_fu_35319_p3}, {tmp_855_fu_35314_p2}}, {tmp_853_fu_35287_p2}}, {1'b1}}, {tmp_851_fu_35260_p2}};
assign p_Result_1296_2_9_4_fu_35807_p6 = {{{{{tmp_2704_fu_35799_p3}, {tmp_873_fu_35794_p2}}, {tmp_872_fu_35781_p2}}, {1'b1}}, {tmp_870_fu_35742_p2}};
assign p_Result_1299_s_fu_5496_p13 = {{{{{{{{{{{{tmp_1333_10_fu_5490_p2}, {tmp_1333_s_fu_5296_p2}}, {tmp_1333_9_fu_5096_p2}}, {tmp_1333_8_fu_4890_p2}}, {tmp_1333_7_fu_4678_p2}}, {tmp_1333_6_fu_4460_p2}}, {tmp_1333_5_fu_4236_p2}}, {tmp_1333_4_fu_4006_p2}}, {tmp_1333_3_fu_3770_p2}}, {tmp_1333_2_fu_3528_p2}}, {tmp_1333_1_fu_3280_p2}}, {tmp_s_fu_3016_p2}};
assign p_Result_1303_10_fu_15738_p4 = {{{y2_V_10_fu_15420_p2}, {y1_V_10_fu_15402_p2}}, {y0_V_10_fu_15282_p2}};
assign p_Result_1303_1_fu_9248_p4 = {{{y2_V_1_fu_8930_p2}, {y1_V_1_fu_8912_p2}}, {y0_V_1_fu_8792_p2}};
assign p_Result_1303_2_fu_9924_p4 = {{{y2_V_2_fu_9606_p2}, {y1_V_2_fu_9588_p2}}, {y0_V_2_fu_9468_p2}};
assign p_Result_1303_3_fu_10570_p4 = {{{y2_V_3_fu_10252_p2}, {y1_V_3_fu_10234_p2}}, {y0_V_3_fu_10114_p2}};
assign p_Result_1303_4_fu_11216_p4 = {{{y2_V_4_fu_10898_p2}, {y1_V_4_fu_10880_p2}}, {y0_V_4_fu_10760_p2}};
assign p_Result_1303_5_fu_11862_p4 = {{{y2_V_5_fu_11544_p2}, {y1_V_5_fu_11526_p2}}, {y0_V_5_fu_11406_p2}};
assign p_Result_1303_6_fu_12508_p4 = {{{y2_V_6_fu_12190_p2}, {y1_V_6_fu_12172_p2}}, {y0_V_6_fu_12052_p2}};
assign p_Result_1303_7_fu_13154_p4 = {{{y2_V_7_fu_12836_p2}, {y1_V_7_fu_12818_p2}}, {y0_V_7_fu_12698_p2}};
assign p_Result_1303_8_fu_13800_p4 = {{{y2_V_8_fu_13482_p2}, {y1_V_8_fu_13464_p2}}, {y0_V_8_fu_13344_p2}};
assign p_Result_1303_9_fu_14446_p4 = {{{y2_V_9_fu_14128_p2}, {y1_V_9_fu_14110_p2}}, {y0_V_9_fu_13990_p2}};
assign p_Result_1303_s_fu_15092_p4 = {{{y2_V_s_fu_14774_p2}, {y1_V_s_fu_14756_p2}}, {y0_V_s_fu_14636_p2}};
assign p_Result_1307_10_fu_15752_p4 = {{{y2a_V_10_fu_15576_p2}, {y1a_V_10_fu_15558_p2}}, {y0a_V_10_fu_15438_p2}};
assign p_Result_1307_1_fu_9262_p4 = {{{y2a_V_1_fu_9086_p2}, {y1a_V_1_fu_9068_p2}}, {y0a_V_1_fu_8948_p2}};
assign p_Result_1307_2_fu_9938_p4 = {{{y2a_V_2_fu_9762_p2}, {y1a_V_2_fu_9744_p2}}, {y0a_V_2_fu_9624_p2}};
assign p_Result_1307_3_fu_10584_p4 = {{{y2a_V_3_fu_10408_p2}, {y1a_V_3_fu_10390_p2}}, {y0a_V_3_fu_10270_p2}};
assign p_Result_1307_4_fu_11230_p4 = {{{y2a_V_4_fu_11054_p2}, {y1a_V_4_fu_11036_p2}}, {y0a_V_4_fu_10916_p2}};
assign p_Result_1307_5_fu_11876_p4 = {{{y2a_V_5_fu_11700_p2}, {y1a_V_5_fu_11682_p2}}, {y0a_V_5_fu_11562_p2}};
assign p_Result_1307_6_fu_12522_p4 = {{{y2a_V_6_fu_12346_p2}, {y1a_V_6_fu_12328_p2}}, {y0a_V_6_fu_12208_p2}};
assign p_Result_1307_7_fu_13168_p4 = {{{y2a_V_7_fu_12992_p2}, {y1a_V_7_fu_12974_p2}}, {y0a_V_7_fu_12854_p2}};
assign p_Result_1307_8_fu_13814_p4 = {{{y2a_V_8_fu_13638_p2}, {y1a_V_8_fu_13620_p2}}, {y0a_V_8_fu_13500_p2}};
assign p_Result_1307_9_fu_14460_p4 = {{{y2a_V_9_fu_14284_p2}, {y1a_V_9_fu_14266_p2}}, {y0a_V_9_fu_14146_p2}};
assign p_Result_1307_s_fu_15106_p4 = {{{y2a_V_s_fu_14930_p2}, {y1a_V_s_fu_14912_p2}}, {y0a_V_s_fu_14792_p2}};
assign p_Result_1311_10_fu_15766_p4 = {{{y2b_V_10_fu_15732_p2}, {y1b_V_10_fu_15714_p2}}, {y0b_V_10_fu_15594_p2}};
assign p_Result_1311_1_fu_9276_p4 = {{{y2b_V_1_fu_9242_p2}, {y1b_V_1_fu_9224_p2}}, {y0b_V_1_fu_9104_p2}};
assign p_Result_1311_2_fu_9952_p4 = {{{y2b_V_2_fu_9918_p2}, {y1b_V_2_fu_9900_p2}}, {y0b_V_2_fu_9780_p2}};
assign p_Result_1311_3_fu_10598_p4 = {{{y2b_V_3_fu_10564_p2}, {y1b_V_3_fu_10546_p2}}, {y0b_V_3_fu_10426_p2}};
assign p_Result_1311_4_fu_11244_p4 = {{{y2b_V_4_fu_11210_p2}, {y1b_V_4_fu_11192_p2}}, {y0b_V_4_fu_11072_p2}};
assign p_Result_1311_5_fu_11890_p4 = {{{y2b_V_5_fu_11856_p2}, {y1b_V_5_fu_11838_p2}}, {y0b_V_5_fu_11718_p2}};
assign p_Result_1311_6_fu_12536_p4 = {{{y2b_V_6_fu_12502_p2}, {y1b_V_6_fu_12484_p2}}, {y0b_V_6_fu_12364_p2}};
assign p_Result_1311_7_fu_13182_p4 = {{{y2b_V_7_fu_13148_p2}, {y1b_V_7_fu_13130_p2}}, {y0b_V_7_fu_13010_p2}};
assign p_Result_1311_8_fu_13828_p4 = {{{y2b_V_8_fu_13794_p2}, {y1b_V_8_fu_13776_p2}}, {y0b_V_8_fu_13656_p2}};
assign p_Result_1311_9_fu_14474_p4 = {{{y2b_V_9_fu_14440_p2}, {y1b_V_9_fu_14422_p2}}, {y0b_V_9_fu_14302_p2}};
assign p_Result_1311_s_fu_15120_p4 = {{{y2b_V_s_fu_15086_p2}, {y1b_V_s_fu_15068_p2}}, {y0b_V_s_fu_14948_p2}};
assign p_Result_150_fu_8568_p4 = {{{y2a_V_fu_8392_p2}, {y1a_V_fu_8374_p2}}, {y0a_V_fu_8254_p2}};
assign p_Result_151_fu_8582_p4 = {{{y2b_V_fu_8548_p2}, {y1b_V_fu_8530_p2}}, {y0b_V_fu_8410_p2}};
assign p_Result_s_fu_8554_p4 = {{{y2_V_fu_8236_p2}, {y1_V_fu_8218_p2}}, {y0_V_fu_8098_p2}};
assign p_Val2_388_0_1_fu_2984_p3 = ((tmp_1339_0_s_fu_2968_p2[0:0] === 1'b1) ? p_Val2_388_0_s_fu_2960_p3 : tmp_1283_fu_2974_p4);
assign p_Val2_388_0_3_fu_2792_p3 = ((tmp_1339_0_2_fu_2774_p2[0:0] === 1'b1) ? p_cast_cast_fu_2766_p3 : p_Result_1247_0_2_fu_2788_p1);
assign p_Val2_388_0_4_fu_2816_p3 = ((tmp_1339_0_3_fu_2800_p2[0:0] === 1'b1) ? p_Val2_388_0_3_fu_2792_p3 : tmp_1258_fu_2806_p4);
assign p_Val2_388_0_5_fu_2840_p3 = ((tmp_1339_0_4_fu_2824_p2[0:0] === 1'b1) ? p_Val2_388_0_4_fu_2816_p3 : tmp_1259_fu_2830_p4);
assign p_Val2_388_0_6_fu_2864_p3 = ((tmp_1339_0_5_fu_2848_p2[0:0] === 1'b1) ? p_Val2_388_0_5_fu_2840_p3 : tmp_1272_fu_2854_p4);
assign p_Val2_388_0_7_fu_2888_p3 = ((tmp_1339_0_6_fu_2872_p2[0:0] === 1'b1) ? p_Val2_388_0_6_fu_2864_p3 : tmp_1276_fu_2878_p4);
assign p_Val2_388_0_8_fu_2912_p3 = ((tmp_1339_0_7_fu_2896_p2[0:0] === 1'b1) ? p_Val2_388_0_7_fu_2888_p3 : tmp_1277_fu_2902_p4);
assign p_Val2_388_0_9_fu_2936_p3 = ((tmp_1339_0_8_fu_2920_p2[0:0] === 1'b1) ? p_Val2_388_0_8_fu_2912_p3 : tmp_1279_fu_2926_p4);
assign p_Val2_388_0_s_fu_2960_p3 = ((tmp_1339_0_9_fu_2944_p2[0:0] === 1'b1) ? p_Val2_388_0_9_fu_2936_p3 : tmp_1281_fu_2950_p4);
assign p_Val2_388_1_1_fu_3248_p3 = ((tmp_1339_1_s_fu_3232_p2[0:0] === 1'b1) ? p_Val2_388_1_s_fu_3224_p3 : tmp_1342_fu_3238_p4);
assign p_Val2_388_1_3_fu_3056_p3 = ((tmp_1339_1_2_fu_3038_p2[0:0] === 1'b1) ? p_12_cast_cast_fu_3030_p3 : p_Result_1247_1_2_fu_3052_p1);
assign p_Val2_388_1_4_fu_3080_p3 = ((tmp_1339_1_3_fu_3064_p2[0:0] === 1'b1) ? p_Val2_388_1_3_fu_3056_p3 : tmp_1302_fu_3070_p4);
assign p_Val2_388_1_5_fu_3104_p3 = ((tmp_1339_1_4_fu_3088_p2[0:0] === 1'b1) ? p_Val2_388_1_4_fu_3080_p3 : tmp_1303_fu_3094_p4);
assign p_Val2_388_1_6_fu_3128_p3 = ((tmp_1339_1_5_fu_3112_p2[0:0] === 1'b1) ? p_Val2_388_1_5_fu_3104_p3 : tmp_1305_fu_3118_p4);
assign p_Val2_388_1_7_fu_3152_p3 = ((tmp_1339_1_6_fu_3136_p2[0:0] === 1'b1) ? p_Val2_388_1_6_fu_3128_p3 : tmp_1308_fu_3142_p4);
assign p_Val2_388_1_8_fu_3176_p3 = ((tmp_1339_1_7_fu_3160_p2[0:0] === 1'b1) ? p_Val2_388_1_7_fu_3152_p3 : tmp_1322_fu_3166_p4);
assign p_Val2_388_1_9_fu_3200_p3 = ((tmp_1339_1_8_fu_3184_p2[0:0] === 1'b1) ? p_Val2_388_1_8_fu_3176_p3 : tmp_1325_fu_3190_p4);
assign p_Val2_388_1_s_fu_3224_p3 = ((tmp_1339_1_9_fu_3208_p2[0:0] === 1'b1) ? p_Val2_388_1_9_fu_3200_p3 : tmp_1339_fu_3214_p4);
assign p_Val2_388_2_1_fu_3496_p3 = ((tmp_1339_2_s_fu_3480_p2[0:0] === 1'b1) ? p_Val2_388_2_s_fu_3472_p3 : tmp_1353_fu_3486_p4);
assign p_Val2_388_2_3_fu_3304_p3 = ((tmp_1339_1_2_fu_3038_p2[0:0] === 1'b1) ? tmp_1345_fu_3294_p4 : p_13_cast_cast_fu_3286_p3);
assign p_Val2_388_2_4_fu_3328_p3 = ((tmp_1339_2_3_fu_3312_p2[0:0] === 1'b1) ? p_Val2_388_2_3_fu_3304_p3 : tmp_1346_fu_3318_p4);
assign p_Val2_388_2_5_fu_3352_p3 = ((tmp_1339_2_4_fu_3336_p2[0:0] === 1'b1) ? p_Val2_388_2_4_fu_3328_p3 : tmp_1347_fu_3342_p4);
assign p_Val2_388_2_6_fu_3376_p3 = ((tmp_1339_2_5_fu_3360_p2[0:0] === 1'b1) ? p_Val2_388_2_5_fu_3352_p3 : tmp_1348_fu_3366_p4);
assign p_Val2_388_2_7_fu_3400_p3 = ((tmp_1339_2_6_fu_3384_p2[0:0] === 1'b1) ? p_Val2_388_2_6_fu_3376_p3 : tmp_1349_fu_3390_p4);
assign p_Val2_388_2_8_fu_3424_p3 = ((tmp_1339_2_7_fu_3408_p2[0:0] === 1'b1) ? p_Val2_388_2_7_fu_3400_p3 : tmp_1350_fu_3414_p4);
assign p_Val2_388_2_9_fu_3448_p3 = ((tmp_1339_2_8_fu_3432_p2[0:0] === 1'b1) ? p_Val2_388_2_8_fu_3424_p3 : tmp_1351_fu_3438_p4);
assign p_Val2_388_2_s_fu_3472_p3 = ((tmp_1339_2_9_fu_3456_p2[0:0] === 1'b1) ? p_Val2_388_2_9_fu_3448_p3 : tmp_1352_fu_3462_p4);
assign p_Val2_388_3_1_fu_3738_p3 = ((tmp_1339_3_s_fu_3722_p2[0:0] === 1'b1) ? p_Val2_388_3_s_fu_3714_p3 : tmp_1363_fu_3728_p4);
assign p_Val2_388_3_2_fu_3552_p3 = ((tmp_1339_1_3_fu_3064_p2[0:0] === 1'b1) ? tmp_1355_fu_3542_p4 : p_14_cast_cast_fu_3534_p3);
assign p_Val2_388_3_4_fu_3570_p3 = ((tmp_1339_2_3_fu_3312_p2[0:0] === 1'b1) ? tmp_1356_fu_3560_p4 : p_Val2_388_3_2_fu_3552_p3);
assign p_Val2_388_3_5_fu_3594_p3 = ((tmp_1339_3_4_fu_3578_p2[0:0] === 1'b1) ? p_Val2_388_3_4_fu_3570_p3 : tmp_1357_fu_3584_p4);
assign p_Val2_388_3_6_fu_3618_p3 = ((tmp_1339_3_5_fu_3602_p2[0:0] === 1'b1) ? p_Val2_388_3_5_fu_3594_p3 : tmp_1358_fu_3608_p4);
assign p_Val2_388_3_7_fu_3642_p3 = ((tmp_1339_3_6_fu_3626_p2[0:0] === 1'b1) ? p_Val2_388_3_6_fu_3618_p3 : tmp_1359_fu_3632_p4);
assign p_Val2_388_3_8_fu_3666_p3 = ((tmp_1339_3_7_fu_3650_p2[0:0] === 1'b1) ? p_Val2_388_3_7_fu_3642_p3 : tmp_1360_fu_3656_p4);
assign p_Val2_388_3_9_fu_3690_p3 = ((tmp_1339_3_8_fu_3674_p2[0:0] === 1'b1) ? p_Val2_388_3_8_fu_3666_p3 : tmp_1361_fu_3680_p4);
assign p_Val2_388_3_s_fu_3714_p3 = ((tmp_1339_3_9_fu_3698_p2[0:0] === 1'b1) ? p_Val2_388_3_9_fu_3690_p3 : tmp_1362_fu_3704_p4);
assign p_Val2_388_4_1_fu_3974_p3 = ((tmp_1339_4_s_fu_3958_p2[0:0] === 1'b1) ? p_Val2_388_4_s_fu_3950_p3 : tmp_1373_fu_3964_p4);
assign p_Val2_388_4_2_fu_3794_p3 = ((tmp_1339_1_4_fu_3088_p2[0:0] === 1'b1) ? tmp_1365_fu_3784_p4 : p_15_cast_cast_fu_3776_p3);
assign p_Val2_388_4_3_fu_3812_p3 = ((tmp_1339_2_4_fu_3336_p2[0:0] === 1'b1) ? tmp_1366_fu_3802_p4 : p_Val2_388_4_2_fu_3794_p3);
assign p_Val2_388_4_5_fu_3830_p3 = ((tmp_1339_3_4_fu_3578_p2[0:0] === 1'b1) ? tmp_1367_fu_3820_p4 : p_Val2_388_4_3_fu_3812_p3);
assign p_Val2_388_4_6_fu_3854_p3 = ((tmp_1339_4_5_fu_3838_p2[0:0] === 1'b1) ? p_Val2_388_4_5_fu_3830_p3 : tmp_1368_fu_3844_p4);
assign p_Val2_388_4_7_fu_3878_p3 = ((tmp_1339_4_6_fu_3862_p2[0:0] === 1'b1) ? p_Val2_388_4_6_fu_3854_p3 : tmp_1369_fu_3868_p4);
assign p_Val2_388_4_8_fu_3902_p3 = ((tmp_1339_4_7_fu_3886_p2[0:0] === 1'b1) ? p_Val2_388_4_7_fu_3878_p3 : tmp_1370_fu_3892_p4);
assign p_Val2_388_4_9_fu_3926_p3 = ((tmp_1339_4_8_fu_3910_p2[0:0] === 1'b1) ? p_Val2_388_4_8_fu_3902_p3 : tmp_1371_fu_3916_p4);
assign p_Val2_388_4_s_fu_3950_p3 = ((tmp_1339_4_9_fu_3934_p2[0:0] === 1'b1) ? p_Val2_388_4_9_fu_3926_p3 : tmp_1372_fu_3940_p4);
assign p_Val2_388_5_1_fu_4204_p3 = ((tmp_1339_5_s_fu_4188_p2[0:0] === 1'b1) ? p_Val2_388_5_s_fu_4180_p3 : tmp_1383_fu_4194_p4);
assign p_Val2_388_5_2_fu_4030_p3 = ((tmp_1339_1_5_fu_3112_p2[0:0] === 1'b1) ? tmp_1375_fu_4020_p4 : p_16_cast_cast_fu_4012_p3);
assign p_Val2_388_5_3_fu_4048_p3 = ((tmp_1339_2_5_fu_3360_p2[0:0] === 1'b1) ? tmp_1376_fu_4038_p4 : p_Val2_388_5_2_fu_4030_p3);
assign p_Val2_388_5_4_fu_4066_p3 = ((tmp_1339_3_5_fu_3602_p2[0:0] === 1'b1) ? tmp_1377_fu_4056_p4 : p_Val2_388_5_3_fu_4048_p3);
assign p_Val2_388_5_6_fu_4084_p3 = ((tmp_1339_4_5_fu_3838_p2[0:0] === 1'b1) ? tmp_1378_fu_4074_p4 : p_Val2_388_5_4_fu_4066_p3);
assign p_Val2_388_5_7_fu_4108_p3 = ((tmp_1339_5_6_fu_4092_p2[0:0] === 1'b1) ? p_Val2_388_5_6_fu_4084_p3 : tmp_1379_fu_4098_p4);
assign p_Val2_388_5_8_fu_4132_p3 = ((tmp_1339_5_7_fu_4116_p2[0:0] === 1'b1) ? p_Val2_388_5_7_fu_4108_p3 : tmp_1380_fu_4122_p4);
assign p_Val2_388_5_9_fu_4156_p3 = ((tmp_1339_5_8_fu_4140_p2[0:0] === 1'b1) ? p_Val2_388_5_8_fu_4132_p3 : tmp_1381_fu_4146_p4);
assign p_Val2_388_5_s_fu_4180_p3 = ((tmp_1339_5_9_fu_4164_p2[0:0] === 1'b1) ? p_Val2_388_5_9_fu_4156_p3 : tmp_1382_fu_4170_p4);
assign p_Val2_388_6_1_fu_4428_p3 = ((tmp_1339_6_s_fu_4412_p2[0:0] === 1'b1) ? p_Val2_388_6_s_fu_4404_p3 : tmp_1393_fu_4418_p4);
assign p_Val2_388_6_2_fu_4260_p3 = ((tmp_1339_1_6_fu_3136_p2[0:0] === 1'b1) ? tmp_1385_fu_4250_p4 : p_17_cast_cast_fu_4242_p3);
assign p_Val2_388_6_3_fu_4278_p3 = ((tmp_1339_2_6_fu_3384_p2[0:0] === 1'b1) ? tmp_1386_fu_4268_p4 : p_Val2_388_6_2_fu_4260_p3);
assign p_Val2_388_6_4_fu_4296_p3 = ((tmp_1339_3_6_fu_3626_p2[0:0] === 1'b1) ? tmp_1387_fu_4286_p4 : p_Val2_388_6_3_fu_4278_p3);
assign p_Val2_388_6_5_fu_4314_p3 = ((tmp_1339_4_6_fu_3862_p2[0:0] === 1'b1) ? tmp_1388_fu_4304_p4 : p_Val2_388_6_4_fu_4296_p3);
assign p_Val2_388_6_7_fu_4332_p3 = ((tmp_1339_5_6_fu_4092_p2[0:0] === 1'b1) ? tmp_1389_fu_4322_p4 : p_Val2_388_6_5_fu_4314_p3);
assign p_Val2_388_6_8_fu_4356_p3 = ((tmp_1339_6_7_fu_4340_p2[0:0] === 1'b1) ? p_Val2_388_6_7_fu_4332_p3 : tmp_1390_fu_4346_p4);
assign p_Val2_388_6_9_fu_4380_p3 = ((tmp_1339_6_8_fu_4364_p2[0:0] === 1'b1) ? p_Val2_388_6_8_fu_4356_p3 : tmp_1391_fu_4370_p4);
assign p_Val2_388_6_s_fu_4404_p3 = ((tmp_1339_6_9_fu_4388_p2[0:0] === 1'b1) ? p_Val2_388_6_9_fu_4380_p3 : tmp_1392_fu_4394_p4);
assign p_Val2_388_7_1_fu_4646_p3 = ((tmp_1339_7_s_fu_4630_p2[0:0] === 1'b1) ? p_Val2_388_7_s_fu_4622_p3 : tmp_1403_fu_4636_p4);
assign p_Val2_388_7_2_fu_4484_p3 = ((tmp_1339_1_7_fu_3160_p2[0:0] === 1'b1) ? tmp_1395_fu_4474_p4 : p_18_cast_cast_fu_4466_p3);
assign p_Val2_388_7_3_fu_4502_p3 = ((tmp_1339_2_7_fu_3408_p2[0:0] === 1'b1) ? tmp_1396_fu_4492_p4 : p_Val2_388_7_2_fu_4484_p3);
assign p_Val2_388_7_4_fu_4520_p3 = ((tmp_1339_3_7_fu_3650_p2[0:0] === 1'b1) ? tmp_1397_fu_4510_p4 : p_Val2_388_7_3_fu_4502_p3);
assign p_Val2_388_7_5_fu_4538_p3 = ((tmp_1339_4_7_fu_3886_p2[0:0] === 1'b1) ? tmp_1398_fu_4528_p4 : p_Val2_388_7_4_fu_4520_p3);
assign p_Val2_388_7_6_fu_4556_p3 = ((tmp_1339_5_7_fu_4116_p2[0:0] === 1'b1) ? tmp_1399_fu_4546_p4 : p_Val2_388_7_5_fu_4538_p3);
assign p_Val2_388_7_8_fu_4574_p3 = ((tmp_1339_6_7_fu_4340_p2[0:0] === 1'b1) ? tmp_1400_fu_4564_p4 : p_Val2_388_7_6_fu_4556_p3);
assign p_Val2_388_7_9_fu_4598_p3 = ((tmp_1339_7_8_fu_4582_p2[0:0] === 1'b1) ? p_Val2_388_7_8_fu_4574_p3 : tmp_1401_fu_4588_p4);
assign p_Val2_388_7_s_fu_4622_p3 = ((tmp_1339_7_9_fu_4606_p2[0:0] === 1'b1) ? p_Val2_388_7_9_fu_4598_p3 : tmp_1402_fu_4612_p4);
assign p_Val2_388_8_1_fu_4858_p3 = ((tmp_1339_8_s_fu_4842_p2[0:0] === 1'b1) ? p_Val2_388_8_s_fu_4834_p3 : tmp_1413_fu_4848_p4);
assign p_Val2_388_8_2_fu_4702_p3 = ((tmp_1339_1_8_fu_3184_p2[0:0] === 1'b1) ? tmp_1405_fu_4692_p4 : p_19_cast_cast_fu_4684_p3);
assign p_Val2_388_8_3_fu_4720_p3 = ((tmp_1339_2_8_fu_3432_p2[0:0] === 1'b1) ? tmp_1406_fu_4710_p4 : p_Val2_388_8_2_fu_4702_p3);
assign p_Val2_388_8_4_fu_4738_p3 = ((tmp_1339_3_8_fu_3674_p2[0:0] === 1'b1) ? tmp_1407_fu_4728_p4 : p_Val2_388_8_3_fu_4720_p3);
assign p_Val2_388_8_5_fu_4756_p3 = ((tmp_1339_4_8_fu_3910_p2[0:0] === 1'b1) ? tmp_1408_fu_4746_p4 : p_Val2_388_8_4_fu_4738_p3);
assign p_Val2_388_8_6_fu_4774_p3 = ((tmp_1339_5_8_fu_4140_p2[0:0] === 1'b1) ? tmp_1409_fu_4764_p4 : p_Val2_388_8_5_fu_4756_p3);
assign p_Val2_388_8_7_fu_4792_p3 = ((tmp_1339_6_8_fu_4364_p2[0:0] === 1'b1) ? tmp_1410_fu_4782_p4 : p_Val2_388_8_6_fu_4774_p3);
assign p_Val2_388_8_9_fu_4810_p3 = ((tmp_1339_7_8_fu_4582_p2[0:0] === 1'b1) ? tmp_1411_fu_4800_p4 : p_Val2_388_8_7_fu_4792_p3);
assign p_Val2_388_8_s_fu_4834_p3 = ((tmp_1339_8_9_fu_4818_p2[0:0] === 1'b1) ? p_Val2_388_8_9_fu_4810_p3 : tmp_1412_fu_4824_p4);
assign p_Val2_393_1_fu_3272_p3 = ((tmp_1339_1_1_fu_3256_p2[0:0] === 1'b1) ? p_Val2_388_1_1_fu_3248_p3 : tmp_1344_fu_3262_p4);
assign p_Val2_393_2_fu_3520_p3 = ((tmp_1339_2_1_fu_3504_p2[0:0] === 1'b1) ? p_Val2_388_2_1_fu_3496_p3 : tmp_1354_fu_3510_p4);
assign p_Val2_393_3_fu_3762_p3 = ((tmp_1339_3_1_fu_3746_p2[0:0] === 1'b1) ? p_Val2_388_3_1_fu_3738_p3 : tmp_1364_fu_3752_p4);
assign p_Val2_393_4_fu_3998_p3 = ((tmp_1339_4_1_fu_3982_p2[0:0] === 1'b1) ? p_Val2_388_4_1_fu_3974_p3 : tmp_1374_fu_3988_p4);
assign p_Val2_393_5_fu_4228_p3 = ((tmp_1339_5_1_fu_4212_p2[0:0] === 1'b1) ? p_Val2_388_5_1_fu_4204_p3 : tmp_1384_fu_4218_p4);
assign p_Val2_393_6_fu_4452_p3 = ((tmp_1339_6_1_fu_4436_p2[0:0] === 1'b1) ? p_Val2_388_6_1_fu_4428_p3 : tmp_1394_fu_4442_p4);
assign p_Val2_393_7_fu_4670_p3 = ((tmp_1339_7_1_fu_4654_p2[0:0] === 1'b1) ? p_Val2_388_7_1_fu_4646_p3 : tmp_1404_fu_4660_p4);
assign p_Val2_393_8_fu_4882_p3 = ((tmp_1339_8_1_fu_4866_p2[0:0] === 1'b1) ? p_Val2_388_8_1_fu_4858_p3 : tmp_1414_fu_4872_p4);
assign p_Val2_398_10_fu_15170_p3 = ((tmp_1874_fu_15156_p3[0:0] === 1'b1) ? p_33_10_fu_15164_p2 : ap_const_lv12_0);
assign p_Val2_398_1_fu_8680_p3 = ((tmp_1604_fu_8666_p3[0:0] === 1'b1) ? p_33_1_fu_8674_p2 : ap_const_lv12_0);
assign p_Val2_398_2_fu_9356_p3 = ((tmp_1631_fu_9342_p3[0:0] === 1'b1) ? p_33_2_fu_9350_p2 : ap_const_lv12_0);
assign p_Val2_398_3_fu_10002_p3 = ((tmp_1658_fu_9988_p3[0:0] === 1'b1) ? p_33_3_fu_9996_p2 : ap_const_lv12_0);
assign p_Val2_398_4_fu_10648_p3 = ((tmp_1685_fu_10634_p3[0:0] === 1'b1) ? p_33_4_fu_10642_p2 : ap_const_lv12_0);
assign p_Val2_398_5_fu_11294_p3 = ((tmp_1712_fu_11280_p3[0:0] === 1'b1) ? p_33_5_fu_11288_p2 : ap_const_lv12_0);
assign p_Val2_398_6_fu_11940_p3 = ((tmp_1739_fu_11926_p3[0:0] === 1'b1) ? p_33_6_fu_11934_p2 : ap_const_lv12_0);
assign p_Val2_398_7_fu_12586_p3 = ((tmp_1766_fu_12572_p3[0:0] === 1'b1) ? p_33_7_fu_12580_p2 : ap_const_lv12_0);
assign p_Val2_398_8_fu_13232_p3 = ((tmp_1793_fu_13218_p3[0:0] === 1'b1) ? p_33_8_fu_13226_p2 : ap_const_lv12_0);
assign p_Val2_398_9_fu_13878_p3 = ((tmp_1820_fu_13864_p3[0:0] === 1'b1) ? p_33_9_fu_13872_p2 : ap_const_lv12_0);
assign p_Val2_398_s_fu_14524_p3 = ((tmp_1847_fu_14510_p3[0:0] === 1'b1) ? p_33_s_fu_14518_p2 : ap_const_lv12_0);
assign p_Val2_s_fu_7986_p3 = ((tmp_1584_fu_7970_p1[0:0] === 1'b1) ? p_9_fu_7980_p2 : ap_const_lv12_0);
assign p_cast_cast_fu_2766_p3 = ((tmp_1339_0_1_fu_2752_p2[0:0] === 1'b1) ? ap_const_lv12_1 : ap_const_lv12_3);
assign p_cast_fu_2758_p3 = ((tmp_1339_0_1_fu_2752_p2[0:0] === 1'b1) ? ap_const_lv2_1 : ap_const_lv2_3);
assign p_demorgan229722982301_i_10_fu_15414_p2 = (tmp994_fu_15408_p2 | lhs_i_i145_0_demorgan2295_i_10_fu_15306_p2);
assign p_demorgan229722982301_i_1_fu_8924_p2 = (tmp178_fu_8918_p2 | lhs_i_i145_0_demorgan2295_i_1_fu_8816_p2);
assign p_demorgan229722982301_i_2_fu_9600_p2 = (tmp211_fu_9594_p2 | lhs_i_i145_0_demorgan2295_i_2_fu_9492_p2);
assign p_demorgan229722982301_i_3_fu_10246_p2 = (tmp244_fu_10240_p2 | lhs_i_i145_0_demorgan2295_i_3_fu_10138_p2);
assign p_demorgan229722982301_i_4_fu_10892_p2 = (tmp607_fu_10886_p2 | lhs_i_i145_0_demorgan2295_i_4_fu_10784_p2);
assign p_demorgan229722982301_i_5_fu_11538_p2 = (tmp640_fu_11532_p2 | lhs_i_i145_0_demorgan2295_i_5_fu_11430_p2);
assign p_demorgan229722982301_i_6_fu_12184_p2 = (tmp673_fu_12178_p2 | lhs_i_i145_0_demorgan2295_i_6_fu_12076_p2);
assign p_demorgan229722982301_i_7_fu_12830_p2 = (tmp708_fu_12824_p2 | lhs_i_i145_0_demorgan2295_i_7_fu_12722_p2);
assign p_demorgan229722982301_i_8_fu_13476_p2 = (tmp901_fu_13470_p2 | lhs_i_i145_0_demorgan2295_i_8_fu_13368_p2);
assign p_demorgan229722982301_i_9_fu_14122_p2 = (tmp932_fu_14116_p2 | lhs_i_i145_0_demorgan2295_i_9_fu_14014_p2);
assign p_demorgan229722982301_i_fu_8230_p2 = (tmp145_fu_8224_p2 | lhs_i_i145_0_demorgan2295_i_fu_8122_p2);
assign p_demorgan229722982301_i_s_fu_14768_p2 = (tmp963_fu_14762_p2 | lhs_i_i145_0_demorgan2295_i_s_fu_14660_p2);
assign p_demorgan230523062309_i_10_fu_15570_p2 = (tmp1004_fu_15564_p2 | lhs_i_i101_0_demorgan2303_i_10_fu_15462_p2);
assign p_demorgan230523062309_i_1_fu_9080_p2 = (tmp188_fu_9074_p2 | lhs_i_i101_0_demorgan2303_i_1_fu_8972_p2);
assign p_demorgan230523062309_i_2_fu_9756_p2 = (tmp221_fu_9750_p2 | lhs_i_i101_0_demorgan2303_i_2_fu_9648_p2);
assign p_demorgan230523062309_i_3_fu_10402_p2 = (tmp254_fu_10396_p2 | lhs_i_i101_0_demorgan2303_i_3_fu_10294_p2);
assign p_demorgan230523062309_i_4_fu_11048_p2 = (tmp617_fu_11042_p2 | lhs_i_i101_0_demorgan2303_i_4_fu_10940_p2);
assign p_demorgan230523062309_i_5_fu_11694_p2 = (tmp650_fu_11688_p2 | lhs_i_i101_0_demorgan2303_i_5_fu_11586_p2);
assign p_demorgan230523062309_i_6_fu_12340_p2 = (tmp683_fu_12334_p2 | lhs_i_i101_0_demorgan2303_i_6_fu_12232_p2);
assign p_demorgan230523062309_i_7_fu_12986_p2 = (tmp718_fu_12980_p2 | lhs_i_i101_0_demorgan2303_i_7_fu_12878_p2);
assign p_demorgan230523062309_i_8_fu_13632_p2 = (tmp911_fu_13626_p2 | lhs_i_i101_0_demorgan2303_i_8_fu_13524_p2);
assign p_demorgan230523062309_i_9_fu_14278_p2 = (tmp942_fu_14272_p2 | lhs_i_i101_0_demorgan2303_i_9_fu_14170_p2);
assign p_demorgan230523062309_i_fu_8386_p2 = (tmp155_fu_8380_p2 | lhs_i_i101_0_demorgan2303_i_fu_8278_p2);
assign p_demorgan230523062309_i_s_fu_14924_p2 = (tmp973_fu_14918_p2 | lhs_i_i101_0_demorgan2303_i_s_fu_14816_p2);
assign p_demorgan231323142317_i_10_fu_15726_p2 = (tmp1014_fu_15720_p2 | lhs_i_i57_0_demorgan2311_i_10_fu_15618_p2);
assign p_demorgan231323142317_i_1_fu_9236_p2 = (tmp198_fu_9230_p2 | lhs_i_i57_0_demorgan2311_i_1_fu_9128_p2);
assign p_demorgan231323142317_i_2_fu_9912_p2 = (tmp231_fu_9906_p2 | lhs_i_i57_0_demorgan2311_i_2_fu_9804_p2);
assign p_demorgan231323142317_i_3_fu_10558_p2 = (tmp264_fu_10552_p2 | lhs_i_i57_0_demorgan2311_i_3_fu_10450_p2);
assign p_demorgan231323142317_i_4_fu_11204_p2 = (tmp627_fu_11198_p2 | lhs_i_i57_0_demorgan2311_i_4_fu_11096_p2);
assign p_demorgan231323142317_i_5_fu_11850_p2 = (tmp660_fu_11844_p2 | lhs_i_i57_0_demorgan2311_i_5_fu_11742_p2);
assign p_demorgan231323142317_i_6_fu_12496_p2 = (tmp693_fu_12490_p2 | lhs_i_i57_0_demorgan2311_i_6_fu_12388_p2);
assign p_demorgan231323142317_i_7_fu_13142_p2 = (tmp728_fu_13136_p2 | lhs_i_i57_0_demorgan2311_i_7_fu_13034_p2);
assign p_demorgan231323142317_i_8_fu_13788_p2 = (tmp921_fu_13782_p2 | lhs_i_i57_0_demorgan2311_i_8_fu_13680_p2);
assign p_demorgan231323142317_i_9_fu_14434_p2 = (tmp952_fu_14428_p2 | lhs_i_i57_0_demorgan2311_i_9_fu_14326_p2);
assign p_demorgan231323142317_i_fu_8542_p2 = (tmp165_fu_8536_p2 | lhs_i_i57_0_demorgan2311_i_fu_8434_p2);
assign p_demorgan231323142317_i_s_fu_15080_p2 = (tmp983_fu_15074_p2 | lhs_i_i57_0_demorgan2311_i_s_fu_14972_p2);
assign p_s_fu_5302_p3 = ((tmp_1339_0_10_fu_2992_p2[0:0] === 1'b1) ? ap_const_lv12_801 : ap_const_lv12_800);
assign p_shl10_fu_17192_p3 = {{tmp_1725_reg_40922}, {ap_const_lv2_0}};
assign p_shl11_cast_fu_17199_p1 = p_shl10_fu_17192_p3;
assign p_shl11_fu_17286_p3 = {{tmp_1752_reg_40933}, {ap_const_lv4_0}};
assign p_shl12_fu_17293_p3 = {{tmp_1752_reg_40933}, {ap_const_lv2_0}};
assign p_shl13_cast_fu_17300_p1 = p_shl12_fu_17293_p3;
assign p_shl13_fu_17387_p3 = {{tmp_1779_reg_40944}, {ap_const_lv4_0}};
assign p_shl14_fu_17394_p3 = {{tmp_1779_reg_40944}, {ap_const_lv2_0}};
assign p_shl15_cast_fu_17401_p1 = p_shl14_fu_17394_p3;
assign p_shl15_fu_17497_p3 = {{ap_reg_ppstg_tmp_1806_reg_40955_pp0_iter1}, {ap_const_lv4_0}};
assign p_shl16_fu_17504_p3 = {{ap_reg_ppstg_tmp_1806_reg_40955_pp0_iter1}, {ap_const_lv2_0}};
assign p_shl17_cast_fu_17511_p1 = p_shl16_fu_17504_p3;
assign p_shl17_fu_17595_p3 = {{ap_reg_ppstg_tmp_1833_reg_40966_pp0_iter1}, {ap_const_lv4_0}};
assign p_shl18_fu_17602_p3 = {{ap_reg_ppstg_tmp_1833_reg_40966_pp0_iter1}, {ap_const_lv2_0}};
assign p_shl19_cast_fu_17609_p1 = p_shl18_fu_17602_p3;
assign p_shl19_fu_17696_p3 = {{ap_reg_ppstg_tmp_1860_reg_40977_pp0_iter1}, {ap_const_lv4_0}};
assign p_shl1_cast_fu_16997_p1 = p_shl1_fu_16990_p3;
assign p_shl1_fu_16990_p3 = {{tmp_1671_reg_40900}, {ap_const_lv2_0}};
assign p_shl20_fu_17703_p3 = {{ap_reg_ppstg_tmp_1860_reg_40977_pp0_iter1}, {ap_const_lv2_0}};
assign p_shl21_cast_fu_17710_p1 = p_shl20_fu_17703_p3;
assign p_shl21_fu_17797_p3 = {{ap_reg_ppstg_tmp_1887_reg_40988_pp0_iter1}, {ap_const_lv4_0}};
assign p_shl22_fu_17804_p3 = {{ap_reg_ppstg_tmp_1887_reg_40988_pp0_iter1}, {ap_const_lv2_0}};
assign p_shl23_cast_fu_17811_p1 = p_shl22_fu_17804_p3;
assign p_shl2_fu_17084_p3 = {{tmp_1698_reg_40911}, {ap_const_lv4_0}};
assign p_shl3_cast_fu_17098_p1 = p_shl3_fu_17091_p3;
assign p_shl3_fu_17091_p3 = {{tmp_1698_reg_40911}, {ap_const_lv2_0}};
assign p_shl4_fu_8622_p3 = {{tmp_1597_fu_8614_p1}, {ap_const_lv2_0}};
assign p_shl5_fu_9312_p3 = {{tmp_1617_fu_9308_p1}, {ap_const_lv4_0}};
assign p_shl6_cast_fu_9328_p1 = p_shl6_fu_9320_p3;
assign p_shl6_fu_9320_p3 = {{tmp_1617_fu_9308_p1}, {ap_const_lv2_0}};
assign p_shl7_fu_16882_p3 = {{tmp_1644_reg_40889}, {ap_const_lv4_0}};
assign p_shl8_cast_fu_16896_p1 = p_shl8_fu_16889_p3;
assign p_shl8_fu_16889_p3 = {{tmp_1644_reg_40889}, {ap_const_lv2_0}};
assign p_shl9_fu_16983_p3 = {{tmp_1671_reg_40900}, {ap_const_lv4_0}};
assign p_shl_fu_17185_p3 = {{tmp_1725_reg_40922}, {ap_const_lv4_0}};
assign r_V_169_0_10_fu_24321_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_2_V_read_1_reg_39088_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_1_fu_18457_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_0_V_read_1_reg_39144_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_2_fu_18873_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_0_V_read_1_reg_39123_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_3_fu_19283_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_0_V_read_1_reg_39102_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_4_fu_19897_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_1_V_read_1_reg_39158_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_5_fu_20385_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_1_V_read_1_reg_39137_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_6_fu_20811_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_1_V_read_1_reg_39116_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_7_fu_21229_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_1_V_read_1_reg_39095_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_8_fu_21809_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_2_V_read_1_reg_39151_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_9_fu_22289_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_2_V_read_1_reg_39130_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_0_s_fu_22723_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_2_V_read_1_reg_39109_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_10_fu_31158_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_2_V_read_1_reg_39088_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_1_fu_25298_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_0_V_read_1_reg_39144_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_2_fu_25714_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_0_V_read_1_reg_39123_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_3_fu_26124_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_0_V_read_1_reg_39102_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_4_fu_26734_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_1_V_read_1_reg_39158_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_5_fu_27222_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_1_V_read_1_reg_39137_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_6_fu_27648_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_1_V_read_1_reg_39116_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_7_fu_28066_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_1_V_read_1_reg_39095_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_8_fu_28646_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_2_V_read_1_reg_39151_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_9_fu_29126_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_2_V_read_1_reg_39130_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_1_s_fu_29560_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_2_V_read_1_reg_39109_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_10_fu_37995_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_2_V_read_1_reg_39088_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_1_fu_32135_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_0_V_read_1_reg_39144_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_2_fu_32551_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_0_V_read_1_reg_39123_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_3_fu_32961_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_0_V_read_1_reg_39102_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_4_fu_33571_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_1_V_read_1_reg_39158_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_5_fu_34059_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_1_V_read_1_reg_39137_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_6_fu_34485_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_1_V_read_1_reg_39116_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_7_fu_34903_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_3_1_V_read_1_reg_39095_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_8_fu_35483_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_0_2_V_read_1_reg_39151_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_9_fu_35963_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_1_2_V_read_1_reg_39130_pp0_iter1 : ap_const_lv7_0);
assign r_V_169_2_s_fu_36397_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_rank_2_2_V_read_1_reg_39109_pp0_iter1 : ap_const_lv7_0);
assign r_V_170_0_10_fu_22991_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_2_V_read_1_reg_40614_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_1_fu_18315_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_0_V_read_1_reg_40670_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_2_fu_18731_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_0_V_read_1_reg_40649_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_3_fu_19141_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_0_V_read_1_reg_40628_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_4_fu_19755_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_1_V_read_1_reg_40684_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_5_fu_20243_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_1_V_read_1_reg_40663_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_6_fu_20669_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_1_V_read_1_reg_40642_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_7_fu_21087_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_1_V_read_1_reg_40621_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_8_fu_21667_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_2_V_read_1_reg_40677_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_9_fu_22147_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_2_V_read_1_reg_40656_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_0_s_fu_22581_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_2_V_read_1_reg_40635_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_10_fu_29828_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_2_V_read_1_reg_40614_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_1_fu_25156_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_0_V_read_1_reg_40670_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_2_fu_25572_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_0_V_read_1_reg_40649_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_3_fu_25982_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_0_V_read_1_reg_40628_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_4_fu_26592_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_1_V_read_1_reg_40684_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_5_fu_27080_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_1_V_read_1_reg_40663_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_6_fu_27506_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_1_V_read_1_reg_40642_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_7_fu_27924_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_1_V_read_1_reg_40621_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_8_fu_28504_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_2_V_read_1_reg_40677_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_9_fu_28984_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_2_V_read_1_reg_40656_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_1_s_fu_29418_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_2_V_read_1_reg_40635_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_10_fu_36665_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_2_V_read_1_reg_40614_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_1_fu_31993_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_0_V_read_1_reg_40670_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_2_fu_32409_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_0_V_read_1_reg_40649_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_3_fu_32819_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_0_V_read_1_reg_40628_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_4_fu_33429_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_1_V_read_1_reg_40684_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_5_fu_33917_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_1_V_read_1_reg_40663_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_6_fu_34343_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_1_V_read_1_reg_40642_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_7_fu_34761_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_3_1_V_read_1_reg_40621_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_8_fu_35341_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_0_2_V_read_1_reg_40677_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_9_fu_35821_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_1_2_V_read_1_reg_40656_pp0_iter1 : ap_const_lv12_0);
assign r_V_170_2_s_fu_36255_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_phi_2_2_V_read_1_reg_40635_pp0_iter1 : ap_const_lv12_0);
assign r_V_171_0_10_fu_23064_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_2_V_read_1_reg_40530_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_1_fu_18322_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_0_V_read_1_reg_40586_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_2_fu_18738_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_0_V_read_1_reg_40565_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_3_fu_19148_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_0_V_read_1_reg_40544_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_4_fu_19762_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_1_V_read_1_reg_40600_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_5_fu_20250_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_1_V_read_1_reg_40579_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_6_fu_20676_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_1_V_read_1_reg_40558_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_7_fu_21094_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_1_V_read_1_reg_40537_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_8_fu_21674_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_2_V_read_1_reg_40593_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_9_fu_22154_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_2_V_read_1_reg_40572_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_0_s_fu_22588_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_2_V_read_1_reg_40551_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_10_fu_29901_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_2_V_read_1_reg_40530_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_1_fu_25163_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_0_V_read_1_reg_40586_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_2_fu_25579_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_0_V_read_1_reg_40565_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_3_fu_25989_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_0_V_read_1_reg_40544_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_4_fu_26599_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_1_V_read_1_reg_40600_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_5_fu_27087_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_1_V_read_1_reg_40579_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_6_fu_27513_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_1_V_read_1_reg_40558_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_7_fu_27931_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_1_V_read_1_reg_40537_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_8_fu_28511_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_2_V_read_1_reg_40593_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_9_fu_28991_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_2_V_read_1_reg_40572_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_1_s_fu_29425_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_2_V_read_1_reg_40551_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_10_fu_36738_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_2_V_read_1_reg_40530_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_1_fu_32000_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_0_V_read_1_reg_40586_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_2_fu_32416_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_0_V_read_1_reg_40565_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_3_fu_32826_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_0_V_read_1_reg_40544_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_4_fu_33436_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_1_V_read_1_reg_40600_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_5_fu_33924_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_1_V_read_1_reg_40579_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_6_fu_34350_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_1_V_read_1_reg_40558_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_7_fu_34768_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_3_1_V_read_1_reg_40537_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_8_fu_35348_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_0_2_V_read_1_reg_40593_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_9_fu_35828_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_1_2_V_read_1_reg_40572_pp0_iter1 : ap_const_lv7_0);
assign r_V_171_2_s_fu_36262_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_theta_2_2_V_read_1_reg_40551_pp0_iter1 : ap_const_lv7_0);
assign r_V_172_0_10_1_fu_22602_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_1_V_read_1_reg_40292_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_10_2_fu_22609_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_2_V_read_1_reg_40285_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_10_3_fu_22616_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_3_V_read_1_reg_40278_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_10_fu_23137_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_0_V_read_1_reg_40215_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_11_1_fu_23210_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_1_V_read_1_reg_40208_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_11_2_fu_23283_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_2_V_read_1_reg_40201_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_11_3_fu_23356_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_3_V_read_1_reg_40194_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_1_1_fu_18336_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_1_V_read_1_reg_40432_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_1_2_fu_18343_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_2_V_read_1_reg_40425_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_1_3_fu_18350_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_3_V_read_1_reg_40418_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_1_fu_18329_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_0_V_read_1_reg_40439_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_2_1_fu_18752_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_1_V_read_1_reg_40348_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_2_2_fu_18759_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_2_V_read_1_reg_40341_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_2_3_fu_18766_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_3_V_read_1_reg_40334_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_2_fu_18745_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_0_V_read_1_reg_40355_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_3_1_fu_19162_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_1_V_read_1_reg_40264_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_3_2_fu_19169_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_2_V_read_1_reg_40257_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_3_3_fu_19176_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_3_V_read_1_reg_40250_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_3_fu_19155_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_0_V_read_1_reg_40271_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_4_1_fu_19776_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_1_V_read_1_reg_40488_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_4_2_fu_19783_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_2_V_read_1_reg_40481_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_4_3_fu_19790_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_3_V_read_1_reg_40474_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_4_fu_19769_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_0_V_read_1_reg_40495_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_5_1_fu_20264_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_1_V_read_1_reg_40404_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_5_2_fu_20271_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_2_V_read_1_reg_40397_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_5_3_fu_20278_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_3_V_read_1_reg_40390_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_5_fu_20257_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_0_V_read_1_reg_40411_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_6_1_fu_20690_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_1_V_read_1_reg_40320_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_6_2_fu_20697_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_2_V_read_1_reg_40313_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_6_3_fu_20704_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_3_V_read_1_reg_40306_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_6_fu_20683_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_0_V_read_1_reg_40327_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_7_1_fu_21108_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_1_V_read_1_reg_40236_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_7_2_fu_21115_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_2_V_read_1_reg_40229_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_7_3_fu_21122_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_3_V_read_1_reg_40222_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_7_fu_21101_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_0_V_read_1_reg_40243_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_8_1_fu_21688_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_1_V_read_1_reg_40460_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_8_2_fu_21695_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_2_V_read_1_reg_40453_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_8_3_fu_21702_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_3_V_read_1_reg_40446_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_8_fu_21681_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_0_V_read_1_reg_40467_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_9_1_fu_22168_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_1_V_read_1_reg_40376_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_9_2_fu_22175_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_2_V_read_1_reg_40369_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_9_3_fu_22182_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_3_V_read_1_reg_40362_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_9_fu_22161_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_0_V_read_1_reg_40383_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_0_s_fu_22595_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_0_V_read_1_reg_40299_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_10_1_fu_29439_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_1_V_read_1_reg_40292_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_10_2_fu_29446_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_2_V_read_1_reg_40285_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_10_3_fu_29453_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_3_V_read_1_reg_40278_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_10_fu_29974_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_0_V_read_1_reg_40215_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_11_1_fu_30047_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_1_V_read_1_reg_40208_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_11_2_fu_30120_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_2_V_read_1_reg_40201_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_11_3_fu_30193_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_3_V_read_1_reg_40194_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_1_1_fu_25177_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_1_V_read_1_reg_40432_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_1_2_fu_25184_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_2_V_read_1_reg_40425_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_1_3_fu_25191_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_3_V_read_1_reg_40418_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_1_fu_25170_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_0_V_read_1_reg_40439_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_2_1_fu_25593_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_1_V_read_1_reg_40348_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_2_2_fu_25600_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_2_V_read_1_reg_40341_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_2_3_fu_25607_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_3_V_read_1_reg_40334_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_2_fu_25586_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_0_V_read_1_reg_40355_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_3_1_fu_26003_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_1_V_read_1_reg_40264_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_3_2_fu_26010_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_2_V_read_1_reg_40257_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_3_3_fu_26017_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_3_V_read_1_reg_40250_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_3_fu_25996_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_0_V_read_1_reg_40271_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_4_1_fu_26613_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_1_V_read_1_reg_40488_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_4_2_fu_26620_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_2_V_read_1_reg_40481_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_4_3_fu_26627_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_3_V_read_1_reg_40474_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_4_fu_26606_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_0_V_read_1_reg_40495_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_5_1_fu_27101_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_1_V_read_1_reg_40404_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_5_2_fu_27108_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_2_V_read_1_reg_40397_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_5_3_fu_27115_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_3_V_read_1_reg_40390_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_5_fu_27094_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_0_V_read_1_reg_40411_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_6_1_fu_27527_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_1_V_read_1_reg_40320_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_6_2_fu_27534_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_2_V_read_1_reg_40313_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_6_3_fu_27541_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_3_V_read_1_reg_40306_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_6_fu_27520_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_0_V_read_1_reg_40327_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_7_1_fu_27945_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_1_V_read_1_reg_40236_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_7_2_fu_27952_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_2_V_read_1_reg_40229_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_7_3_fu_27959_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_3_V_read_1_reg_40222_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_7_fu_27938_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_0_V_read_1_reg_40243_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_8_1_fu_28525_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_1_V_read_1_reg_40460_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_8_2_fu_28532_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_2_V_read_1_reg_40453_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_8_3_fu_28539_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_3_V_read_1_reg_40446_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_8_fu_28518_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_0_V_read_1_reg_40467_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_9_1_fu_29005_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_1_V_read_1_reg_40376_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_9_2_fu_29012_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_2_V_read_1_reg_40369_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_9_3_fu_29019_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_3_V_read_1_reg_40362_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_9_fu_28998_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_0_V_read_1_reg_40383_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_1_s_fu_29432_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_0_V_read_1_reg_40299_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_10_1_fu_36276_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_1_V_read_1_reg_40292_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_10_2_fu_36283_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_2_V_read_1_reg_40285_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_10_3_fu_36290_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_3_V_read_1_reg_40278_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_10_fu_36811_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_0_V_read_1_reg_40215_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_11_1_fu_36884_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_1_V_read_1_reg_40208_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_11_2_fu_36957_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_2_V_read_1_reg_40201_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_11_3_fu_37030_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_2_3_V_read_1_reg_40194_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_1_1_fu_32014_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_1_V_read_1_reg_40432_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_1_2_fu_32021_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_2_V_read_1_reg_40425_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_1_3_fu_32028_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_3_V_read_1_reg_40418_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_1_fu_32007_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_0_0_V_read_1_reg_40439_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_2_1_fu_32430_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_1_V_read_1_reg_40348_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_2_2_fu_32437_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_2_V_read_1_reg_40341_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_2_3_fu_32444_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_3_V_read_1_reg_40334_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_2_fu_32423_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_0_0_V_read_1_reg_40355_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_3_1_fu_32840_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_1_V_read_1_reg_40264_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_3_2_fu_32847_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_2_V_read_1_reg_40257_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_3_3_fu_32854_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_3_V_read_1_reg_40250_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_3_fu_32833_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_0_0_V_read_1_reg_40271_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_4_1_fu_33450_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_1_V_read_1_reg_40488_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_4_2_fu_33457_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_2_V_read_1_reg_40481_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_4_3_fu_33464_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_3_V_read_1_reg_40474_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_4_fu_33443_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_1_0_V_read_1_reg_40495_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_5_1_fu_33938_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_1_V_read_1_reg_40404_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_5_2_fu_33945_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_2_V_read_1_reg_40397_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_5_3_fu_33952_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_3_V_read_1_reg_40390_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_5_fu_33931_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_1_0_V_read_1_reg_40411_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_6_1_fu_34364_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_1_V_read_1_reg_40320_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_6_2_fu_34371_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_2_V_read_1_reg_40313_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_6_3_fu_34378_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_3_V_read_1_reg_40306_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_6_fu_34357_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_1_0_V_read_1_reg_40327_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_7_1_fu_34782_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_1_V_read_1_reg_40236_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_7_2_fu_34789_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_2_V_read_1_reg_40229_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_7_3_fu_34796_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_3_V_read_1_reg_40222_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_7_fu_34775_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_3_1_0_V_read_1_reg_40243_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_8_1_fu_35362_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_1_V_read_1_reg_40460_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_8_2_fu_35369_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_2_V_read_1_reg_40453_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_8_3_fu_35376_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_3_V_read_1_reg_40446_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_8_fu_35355_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_0_2_0_V_read_1_reg_40467_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_9_1_fu_35842_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_1_V_read_1_reg_40376_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_9_2_fu_35849_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_2_V_read_1_reg_40369_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_9_3_fu_35856_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_3_V_read_1_reg_40362_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_9_fu_35835_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_1_2_0_V_read_1_reg_40383_pp0_iter1 : ap_const_lv4_0);
assign r_V_172_2_s_fu_36269_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_cpattern_2_2_0_V_read_1_reg_40299_pp0_iter1 : ap_const_lv4_0);
assign r_V_173_0_10_1_fu_22630_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_1_V_read_1_reg_39844_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_10_2_fu_22637_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_2_V_read_1_reg_39837_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_10_3_fu_22644_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_3_V_read_1_reg_39830_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_10_4_fu_22651_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_4_V_read_1_reg_39823_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_10_5_fu_22658_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_5_V_read_1_reg_39816_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_10_fu_23429_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_0_V_read_1_reg_39725_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_11_1_fu_23502_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_1_V_read_1_reg_39718_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_11_2_fu_23575_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_2_V_read_1_reg_39711_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_11_3_fu_23648_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_3_V_read_1_reg_39704_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_11_4_fu_23721_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_4_V_read_1_reg_39697_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_11_5_fu_23794_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_5_V_read_1_reg_39690_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_1_1_fu_18364_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_1_V_read_1_reg_40054_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_1_2_fu_18371_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_2_V_read_1_reg_40047_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_1_3_fu_18378_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_3_V_read_1_reg_40040_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_1_4_fu_18385_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_4_V_read_1_reg_40033_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_1_5_fu_18392_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_5_V_read_1_reg_40026_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_1_fu_18357_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_0_V_read_1_reg_40061_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_2_1_fu_18780_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_1_V_read_1_reg_39928_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_2_2_fu_18787_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_2_V_read_1_reg_39921_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_2_3_fu_18794_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_3_V_read_1_reg_39914_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_2_4_fu_18801_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_4_V_read_1_reg_39907_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_2_5_fu_18808_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_5_V_read_1_reg_39900_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_2_fu_18773_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_0_V_read_1_reg_39935_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_3_1_fu_19190_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_1_V_read_1_reg_39802_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_3_2_fu_19197_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_2_V_read_1_reg_39795_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_3_3_fu_19204_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_3_V_read_1_reg_39788_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_3_4_fu_19211_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_4_V_read_1_reg_39781_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_3_5_fu_19218_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_5_V_read_1_reg_39774_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_3_fu_19183_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_0_V_read_1_reg_39809_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_4_1_fu_19804_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_1_V_read_1_reg_40138_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_4_2_fu_19811_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_2_V_read_1_reg_40131_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_4_3_fu_19818_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_3_V_read_1_reg_40124_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_4_4_fu_19825_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_4_V_read_1_reg_40117_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_4_5_fu_19832_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_5_V_read_1_reg_40110_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_4_fu_19797_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_0_V_read_1_reg_40145_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_5_1_fu_20292_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_1_V_read_1_reg_40012_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_5_2_fu_20299_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_2_V_read_1_reg_40005_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_5_3_fu_20306_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_3_V_read_1_reg_39998_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_5_4_fu_20313_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_4_V_read_1_reg_39991_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_5_5_fu_20320_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_5_V_read_1_reg_39984_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_5_fu_20285_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_0_V_read_1_reg_40019_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_6_1_fu_20718_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_1_V_read_1_reg_39886_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_6_2_fu_20725_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_2_V_read_1_reg_39879_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_6_3_fu_20732_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_3_V_read_1_reg_39872_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_6_4_fu_20739_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_4_V_read_1_reg_39865_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_6_5_fu_20746_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_5_V_read_1_reg_39858_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_6_fu_20711_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_0_V_read_1_reg_39893_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_7_1_fu_21136_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_1_V_read_1_reg_39760_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_7_2_fu_21143_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_2_V_read_1_reg_39753_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_7_3_fu_21150_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_3_V_read_1_reg_39746_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_7_4_fu_21157_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_4_V_read_1_reg_39739_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_7_5_fu_21164_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_5_V_read_1_reg_39732_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_7_fu_21129_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_0_V_read_1_reg_39767_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_8_1_fu_21716_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_1_V_read_1_reg_40096_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_8_2_fu_21723_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_2_V_read_1_reg_40089_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_8_3_fu_21730_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_3_V_read_1_reg_40082_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_8_4_fu_21737_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_4_V_read_1_reg_40075_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_8_5_fu_21744_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_5_V_read_1_reg_40068_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_8_fu_21709_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_0_V_read_1_reg_40103_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_9_1_fu_22196_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_1_V_read_1_reg_39970_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_9_2_fu_22203_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_2_V_read_1_reg_39963_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_9_3_fu_22210_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_3_V_read_1_reg_39956_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_9_4_fu_22217_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_4_V_read_1_reg_39949_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_9_5_fu_22224_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_5_V_read_1_reg_39942_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_9_fu_22189_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_0_V_read_1_reg_39977_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_0_s_fu_22623_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_0_V_read_1_reg_39851_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_10_1_fu_29467_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_1_V_read_1_reg_39844_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_10_2_fu_29474_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_2_V_read_1_reg_39837_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_10_3_fu_29481_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_3_V_read_1_reg_39830_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_10_4_fu_29488_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_4_V_read_1_reg_39823_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_10_5_fu_29495_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_5_V_read_1_reg_39816_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_10_fu_30266_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_0_V_read_1_reg_39725_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_11_1_fu_30339_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_1_V_read_1_reg_39718_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_11_2_fu_30412_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_2_V_read_1_reg_39711_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_11_3_fu_30485_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_3_V_read_1_reg_39704_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_11_4_fu_30558_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_4_V_read_1_reg_39697_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_11_5_fu_30631_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_5_V_read_1_reg_39690_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_1_1_fu_25205_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_1_V_read_1_reg_40054_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_1_2_fu_25212_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_2_V_read_1_reg_40047_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_1_3_fu_25219_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_3_V_read_1_reg_40040_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_1_4_fu_25226_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_4_V_read_1_reg_40033_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_1_5_fu_25233_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_5_V_read_1_reg_40026_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_1_fu_25198_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_0_V_read_1_reg_40061_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_2_1_fu_25621_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_1_V_read_1_reg_39928_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_2_2_fu_25628_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_2_V_read_1_reg_39921_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_2_3_fu_25635_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_3_V_read_1_reg_39914_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_2_4_fu_25642_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_4_V_read_1_reg_39907_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_2_5_fu_25649_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_5_V_read_1_reg_39900_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_2_fu_25614_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_0_V_read_1_reg_39935_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_3_1_fu_26031_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_1_V_read_1_reg_39802_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_3_2_fu_26038_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_2_V_read_1_reg_39795_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_3_3_fu_26045_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_3_V_read_1_reg_39788_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_3_4_fu_26052_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_4_V_read_1_reg_39781_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_3_5_fu_26059_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_5_V_read_1_reg_39774_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_3_fu_26024_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_0_V_read_1_reg_39809_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_4_1_fu_26641_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_1_V_read_1_reg_40138_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_4_2_fu_26648_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_2_V_read_1_reg_40131_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_4_3_fu_26655_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_3_V_read_1_reg_40124_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_4_4_fu_26662_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_4_V_read_1_reg_40117_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_4_5_fu_26669_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_5_V_read_1_reg_40110_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_4_fu_26634_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_0_V_read_1_reg_40145_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_5_1_fu_27129_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_1_V_read_1_reg_40012_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_5_2_fu_27136_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_2_V_read_1_reg_40005_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_5_3_fu_27143_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_3_V_read_1_reg_39998_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_5_4_fu_27150_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_4_V_read_1_reg_39991_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_5_5_fu_27157_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_5_V_read_1_reg_39984_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_5_fu_27122_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_0_V_read_1_reg_40019_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_6_1_fu_27555_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_1_V_read_1_reg_39886_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_6_2_fu_27562_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_2_V_read_1_reg_39879_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_6_3_fu_27569_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_3_V_read_1_reg_39872_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_6_4_fu_27576_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_4_V_read_1_reg_39865_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_6_5_fu_27583_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_5_V_read_1_reg_39858_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_6_fu_27548_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_0_V_read_1_reg_39893_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_7_1_fu_27973_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_1_V_read_1_reg_39760_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_7_2_fu_27980_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_2_V_read_1_reg_39753_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_7_3_fu_27987_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_3_V_read_1_reg_39746_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_7_4_fu_27994_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_4_V_read_1_reg_39739_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_7_5_fu_28001_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_5_V_read_1_reg_39732_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_7_fu_27966_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_0_V_read_1_reg_39767_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_8_1_fu_28553_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_1_V_read_1_reg_40096_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_8_2_fu_28560_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_2_V_read_1_reg_40089_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_8_3_fu_28567_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_3_V_read_1_reg_40082_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_8_4_fu_28574_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_4_V_read_1_reg_40075_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_8_5_fu_28581_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_5_V_read_1_reg_40068_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_8_fu_28546_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_0_V_read_1_reg_40103_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_9_1_fu_29033_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_1_V_read_1_reg_39970_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_9_2_fu_29040_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_2_V_read_1_reg_39963_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_9_3_fu_29047_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_3_V_read_1_reg_39956_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_9_4_fu_29054_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_4_V_read_1_reg_39949_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_9_5_fu_29061_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_5_V_read_1_reg_39942_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_9_fu_29026_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_0_V_read_1_reg_39977_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_1_s_fu_29460_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_0_V_read_1_reg_39851_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_10_1_fu_36304_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_1_V_read_1_reg_39844_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_10_2_fu_36311_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_2_V_read_1_reg_39837_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_10_3_fu_36318_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_3_V_read_1_reg_39830_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_10_4_fu_36325_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_4_V_read_1_reg_39823_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_10_5_fu_36332_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_5_V_read_1_reg_39816_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_10_fu_37103_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_0_V_read_1_reg_39725_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_11_1_fu_37176_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_1_V_read_1_reg_39718_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_11_2_fu_37249_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_2_V_read_1_reg_39711_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_11_3_fu_37322_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_3_V_read_1_reg_39704_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_11_4_fu_37395_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_4_V_read_1_reg_39697_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_11_5_fu_37468_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_2_5_V_read_1_reg_39690_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_1_1_fu_32042_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_1_V_read_1_reg_40054_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_1_2_fu_32049_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_2_V_read_1_reg_40047_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_1_3_fu_32056_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_3_V_read_1_reg_40040_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_1_4_fu_32063_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_4_V_read_1_reg_40033_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_1_5_fu_32070_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_5_V_read_1_reg_40026_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_1_fu_32035_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_0_0_V_read_1_reg_40061_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_2_1_fu_32458_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_1_V_read_1_reg_39928_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_2_2_fu_32465_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_2_V_read_1_reg_39921_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_2_3_fu_32472_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_3_V_read_1_reg_39914_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_2_4_fu_32479_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_4_V_read_1_reg_39907_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_2_5_fu_32486_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_5_V_read_1_reg_39900_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_2_fu_32451_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_0_0_V_read_1_reg_39935_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_3_1_fu_32868_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_1_V_read_1_reg_39802_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_3_2_fu_32875_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_2_V_read_1_reg_39795_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_3_3_fu_32882_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_3_V_read_1_reg_39788_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_3_4_fu_32889_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_4_V_read_1_reg_39781_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_3_5_fu_32896_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_5_V_read_1_reg_39774_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_3_fu_32861_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_0_0_V_read_1_reg_39809_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_4_1_fu_33478_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_1_V_read_1_reg_40138_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_4_2_fu_33485_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_2_V_read_1_reg_40131_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_4_3_fu_33492_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_3_V_read_1_reg_40124_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_4_4_fu_33499_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_4_V_read_1_reg_40117_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_4_5_fu_33506_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_5_V_read_1_reg_40110_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_4_fu_33471_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_1_0_V_read_1_reg_40145_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_5_1_fu_33966_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_1_V_read_1_reg_40012_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_5_2_fu_33973_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_2_V_read_1_reg_40005_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_5_3_fu_33980_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_3_V_read_1_reg_39998_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_5_4_fu_33987_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_4_V_read_1_reg_39991_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_5_5_fu_33994_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_5_V_read_1_reg_39984_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_5_fu_33959_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_1_0_V_read_1_reg_40019_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_6_1_fu_34392_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_1_V_read_1_reg_39886_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_6_2_fu_34399_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_2_V_read_1_reg_39879_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_6_3_fu_34406_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_3_V_read_1_reg_39872_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_6_4_fu_34413_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_4_V_read_1_reg_39865_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_6_5_fu_34420_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_5_V_read_1_reg_39858_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_6_fu_34385_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_1_0_V_read_1_reg_39893_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_7_1_fu_34810_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_1_V_read_1_reg_39760_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_7_2_fu_34817_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_2_V_read_1_reg_39753_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_7_3_fu_34824_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_3_V_read_1_reg_39746_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_7_4_fu_34831_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_4_V_read_1_reg_39739_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_7_5_fu_34838_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_5_V_read_1_reg_39732_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_7_fu_34803_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_3_1_0_V_read_1_reg_39767_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_8_1_fu_35390_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_1_V_read_1_reg_40096_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_8_2_fu_35397_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_2_V_read_1_reg_40089_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_8_3_fu_35404_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_3_V_read_1_reg_40082_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_8_4_fu_35411_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_4_V_read_1_reg_40075_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_8_5_fu_35418_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_5_V_read_1_reg_40068_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_8_fu_35383_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_0_2_0_V_read_1_reg_40103_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_9_1_fu_35870_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_1_V_read_1_reg_39970_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_9_2_fu_35877_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_2_V_read_1_reg_39963_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_9_3_fu_35884_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_3_V_read_1_reg_39956_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_9_4_fu_35891_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_4_V_read_1_reg_39949_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_9_5_fu_35898_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_5_V_read_1_reg_39942_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_9_fu_35863_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_1_2_0_V_read_1_reg_39977_pp0_iter1 : ap_const_lv12_0);
assign r_V_173_2_s_fu_36297_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_ph_2_2_0_V_read_1_reg_39851_pp0_iter1 : ap_const_lv12_0);
assign r_V_174_0_10_1_fu_22672_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_1_V_read_1_reg_39340_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_10_2_fu_22679_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_2_V_read_1_reg_39333_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_10_3_fu_22686_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_3_V_read_1_reg_39326_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_10_4_fu_22693_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_4_V_read_1_reg_39319_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_10_5_fu_22700_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_5_V_read_1_reg_39312_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_10_fu_23867_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_0_V_read_1_reg_39221_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_11_1_fu_23940_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_1_V_read_1_reg_39214_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_11_2_fu_24013_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_2_V_read_1_reg_39207_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_11_3_fu_24086_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_3_V_read_1_reg_39200_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_11_4_fu_24159_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_4_V_read_1_reg_39193_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_11_5_fu_24232_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_5_V_read_1_reg_39186_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_1_1_fu_18406_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_1_V_read_1_reg_39550_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_1_2_fu_18413_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_2_V_read_1_reg_39543_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_1_3_fu_18420_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_3_V_read_1_reg_39536_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_1_4_fu_18427_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_4_V_read_1_reg_39529_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_1_5_fu_18434_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_5_V_read_1_reg_39522_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_1_fu_18399_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_0_V_read_1_reg_39557_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_2_1_fu_18822_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_1_V_read_1_reg_39424_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_2_2_fu_18829_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_2_V_read_1_reg_39417_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_2_3_fu_18836_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_3_V_read_1_reg_39410_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_2_4_fu_18843_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_4_V_read_1_reg_39403_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_2_5_fu_18850_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_5_V_read_1_reg_39396_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_2_fu_18815_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_0_V_read_1_reg_39431_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_3_1_fu_19232_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_1_V_read_1_reg_39298_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_3_2_fu_19239_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_2_V_read_1_reg_39291_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_3_3_fu_19246_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_3_V_read_1_reg_39284_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_3_4_fu_19253_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_4_V_read_1_reg_39277_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_3_5_fu_19260_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_5_V_read_1_reg_39270_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_3_fu_19225_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_0_V_read_1_reg_39305_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_4_1_fu_19846_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_1_V_read_1_reg_39634_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_4_2_fu_19853_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_2_V_read_1_reg_39627_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_4_3_fu_19860_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_3_V_read_1_reg_39620_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_4_4_fu_19867_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_4_V_read_1_reg_39613_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_4_5_fu_19874_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_5_V_read_1_reg_39606_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_4_fu_19839_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_0_V_read_1_reg_39641_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_5_1_fu_20334_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_1_V_read_1_reg_39508_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_5_2_fu_20341_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_2_V_read_1_reg_39501_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_5_3_fu_20348_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_3_V_read_1_reg_39494_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_5_4_fu_20355_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_4_V_read_1_reg_39487_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_5_5_fu_20362_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_5_V_read_1_reg_39480_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_5_fu_20327_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_0_V_read_1_reg_39515_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_6_1_fu_20760_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_1_V_read_1_reg_39382_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_6_2_fu_20767_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_2_V_read_1_reg_39375_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_6_3_fu_20774_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_3_V_read_1_reg_39368_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_6_4_fu_20781_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_4_V_read_1_reg_39361_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_6_5_fu_20788_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_5_V_read_1_reg_39354_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_6_fu_20753_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_0_V_read_1_reg_39389_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_7_1_fu_21178_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_1_V_read_1_reg_39256_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_7_2_fu_21185_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_2_V_read_1_reg_39249_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_7_3_fu_21192_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_3_V_read_1_reg_39242_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_7_4_fu_21199_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_4_V_read_1_reg_39235_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_7_5_fu_21206_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_5_V_read_1_reg_39228_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_7_fu_21171_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_0_V_read_1_reg_39263_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_8_1_fu_21758_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_1_V_read_1_reg_39592_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_8_2_fu_21765_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_2_V_read_1_reg_39585_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_8_3_fu_21772_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_3_V_read_1_reg_39578_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_8_4_fu_21779_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_4_V_read_1_reg_39571_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_8_5_fu_21786_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_5_V_read_1_reg_39564_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_8_fu_21751_p3 = ((tmp_2141_fu_21366_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_0_V_read_1_reg_39599_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_9_1_fu_22238_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_1_V_read_1_reg_39466_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_9_2_fu_22245_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_2_V_read_1_reg_39459_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_9_3_fu_22252_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_3_V_read_1_reg_39452_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_9_4_fu_22259_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_4_V_read_1_reg_39445_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_9_5_fu_22266_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_5_V_read_1_reg_39438_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_9_fu_22231_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_0_V_read_1_reg_39473_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_0_s_fu_22665_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_0_V_read_1_reg_39347_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_10_1_fu_29509_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_1_V_read_1_reg_39340_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_10_2_fu_29516_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_2_V_read_1_reg_39333_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_10_3_fu_29523_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_3_V_read_1_reg_39326_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_10_4_fu_29530_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_4_V_read_1_reg_39319_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_10_5_fu_29537_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_5_V_read_1_reg_39312_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_10_fu_30704_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_0_V_read_1_reg_39221_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_11_1_fu_30777_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_1_V_read_1_reg_39214_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_11_2_fu_30850_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_2_V_read_1_reg_39207_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_11_3_fu_30923_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_3_V_read_1_reg_39200_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_11_4_fu_30996_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_4_V_read_1_reg_39193_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_11_5_fu_31069_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_5_V_read_1_reg_39186_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_1_1_fu_25247_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_1_V_read_1_reg_39550_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_1_2_fu_25254_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_2_V_read_1_reg_39543_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_1_3_fu_25261_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_3_V_read_1_reg_39536_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_1_4_fu_25268_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_4_V_read_1_reg_39529_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_1_5_fu_25275_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_5_V_read_1_reg_39522_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_1_fu_25240_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_0_V_read_1_reg_39557_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_2_1_fu_25663_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_1_V_read_1_reg_39424_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_2_2_fu_25670_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_2_V_read_1_reg_39417_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_2_3_fu_25677_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_3_V_read_1_reg_39410_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_2_4_fu_25684_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_4_V_read_1_reg_39403_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_2_5_fu_25691_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_5_V_read_1_reg_39396_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_2_fu_25656_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_0_V_read_1_reg_39431_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_3_1_fu_26073_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_1_V_read_1_reg_39298_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_3_2_fu_26080_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_2_V_read_1_reg_39291_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_3_3_fu_26087_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_3_V_read_1_reg_39284_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_3_4_fu_26094_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_4_V_read_1_reg_39277_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_3_5_fu_26101_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_5_V_read_1_reg_39270_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_3_fu_26066_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_0_V_read_1_reg_39305_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_4_1_fu_26683_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_1_V_read_1_reg_39634_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_4_2_fu_26690_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_2_V_read_1_reg_39627_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_4_3_fu_26697_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_3_V_read_1_reg_39620_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_4_4_fu_26704_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_4_V_read_1_reg_39613_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_4_5_fu_26711_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_5_V_read_1_reg_39606_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_4_fu_26676_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_0_V_read_1_reg_39641_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_5_1_fu_27171_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_1_V_read_1_reg_39508_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_5_2_fu_27178_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_2_V_read_1_reg_39501_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_5_3_fu_27185_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_3_V_read_1_reg_39494_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_5_4_fu_27192_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_4_V_read_1_reg_39487_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_5_5_fu_27199_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_5_V_read_1_reg_39480_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_5_fu_27164_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_0_V_read_1_reg_39515_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_6_1_fu_27597_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_1_V_read_1_reg_39382_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_6_2_fu_27604_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_2_V_read_1_reg_39375_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_6_3_fu_27611_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_3_V_read_1_reg_39368_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_6_4_fu_27618_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_4_V_read_1_reg_39361_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_6_5_fu_27625_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_5_V_read_1_reg_39354_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_6_fu_27590_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_0_V_read_1_reg_39389_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_7_1_fu_28015_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_1_V_read_1_reg_39256_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_7_2_fu_28022_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_2_V_read_1_reg_39249_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_7_3_fu_28029_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_3_V_read_1_reg_39242_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_7_4_fu_28036_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_4_V_read_1_reg_39235_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_7_5_fu_28043_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_5_V_read_1_reg_39228_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_7_fu_28008_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_0_V_read_1_reg_39263_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_8_1_fu_28595_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_1_V_read_1_reg_39592_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_8_2_fu_28602_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_2_V_read_1_reg_39585_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_8_3_fu_28609_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_3_V_read_1_reg_39578_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_8_4_fu_28616_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_4_V_read_1_reg_39571_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_8_5_fu_28623_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_5_V_read_1_reg_39564_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_8_fu_28588_p3 = ((tmp_2430_fu_28203_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_0_V_read_1_reg_39599_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_9_1_fu_29075_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_1_V_read_1_reg_39466_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_9_2_fu_29082_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_2_V_read_1_reg_39459_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_9_3_fu_29089_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_3_V_read_1_reg_39452_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_9_4_fu_29096_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_4_V_read_1_reg_39445_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_9_5_fu_29103_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_5_V_read_1_reg_39438_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_9_fu_29068_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_0_V_read_1_reg_39473_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_1_s_fu_29502_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_0_V_read_1_reg_39347_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_10_1_fu_36346_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_1_V_read_1_reg_39340_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_10_2_fu_36353_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_2_V_read_1_reg_39333_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_10_3_fu_36360_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_3_V_read_1_reg_39326_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_10_4_fu_36367_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_4_V_read_1_reg_39319_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_10_5_fu_36374_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_5_V_read_1_reg_39312_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_10_fu_37541_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_0_V_read_1_reg_39221_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_11_1_fu_37614_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_1_V_read_1_reg_39214_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_11_2_fu_37687_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_2_V_read_1_reg_39207_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_11_3_fu_37760_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_3_V_read_1_reg_39200_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_11_4_fu_37833_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_4_V_read_1_reg_39193_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_11_5_fu_37906_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_2_5_V_read_1_reg_39186_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_1_1_fu_32084_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_1_V_read_1_reg_39550_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_1_2_fu_32091_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_2_V_read_1_reg_39543_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_1_3_fu_32098_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_3_V_read_1_reg_39536_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_1_4_fu_32105_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_4_V_read_1_reg_39529_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_1_5_fu_32112_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_5_V_read_1_reg_39522_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_1_fu_32077_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_0_0_V_read_1_reg_39557_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_2_1_fu_32500_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_1_V_read_1_reg_39424_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_2_2_fu_32507_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_2_V_read_1_reg_39417_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_2_3_fu_32514_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_3_V_read_1_reg_39410_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_2_4_fu_32521_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_4_V_read_1_reg_39403_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_2_5_fu_32528_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_5_V_read_1_reg_39396_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_2_fu_32493_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_0_0_V_read_1_reg_39431_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_3_1_fu_32910_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_1_V_read_1_reg_39298_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_3_2_fu_32917_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_2_V_read_1_reg_39291_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_3_3_fu_32924_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_3_V_read_1_reg_39284_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_3_4_fu_32931_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_4_V_read_1_reg_39277_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_3_5_fu_32938_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_5_V_read_1_reg_39270_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_3_fu_32903_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_0_0_V_read_1_reg_39305_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_4_1_fu_33520_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_1_V_read_1_reg_39634_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_4_2_fu_33527_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_2_V_read_1_reg_39627_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_4_3_fu_33534_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_3_V_read_1_reg_39620_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_4_4_fu_33541_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_4_V_read_1_reg_39613_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_4_5_fu_33548_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_5_V_read_1_reg_39606_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_4_fu_33513_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_1_0_V_read_1_reg_39641_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_5_1_fu_34008_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_1_V_read_1_reg_39508_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_5_2_fu_34015_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_2_V_read_1_reg_39501_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_5_3_fu_34022_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_3_V_read_1_reg_39494_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_5_4_fu_34029_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_4_V_read_1_reg_39487_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_5_5_fu_34036_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_5_V_read_1_reg_39480_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_5_fu_34001_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_1_0_V_read_1_reg_39515_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_6_1_fu_34434_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_1_V_read_1_reg_39382_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_6_2_fu_34441_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_2_V_read_1_reg_39375_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_6_3_fu_34448_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_3_V_read_1_reg_39368_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_6_4_fu_34455_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_4_V_read_1_reg_39361_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_6_5_fu_34462_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_5_V_read_1_reg_39354_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_6_fu_34427_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_1_0_V_read_1_reg_39389_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_7_1_fu_34852_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_1_V_read_1_reg_39256_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_7_2_fu_34859_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_2_V_read_1_reg_39249_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_7_3_fu_34866_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_3_V_read_1_reg_39242_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_7_4_fu_34873_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_4_V_read_1_reg_39235_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_7_5_fu_34880_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_5_V_read_1_reg_39228_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_7_fu_34845_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_3_1_0_V_read_1_reg_39263_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_8_1_fu_35432_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_1_V_read_1_reg_39592_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_8_2_fu_35439_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_2_V_read_1_reg_39585_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_8_3_fu_35446_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_3_V_read_1_reg_39578_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_8_4_fu_35453_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_4_V_read_1_reg_39571_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_8_5_fu_35460_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_5_V_read_1_reg_39564_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_8_fu_35425_p3 = ((tmp_2667_fu_35040_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_0_2_0_V_read_1_reg_39599_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_9_1_fu_35912_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_1_V_read_1_reg_39466_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_9_2_fu_35919_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_2_V_read_1_reg_39459_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_9_3_fu_35926_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_3_V_read_1_reg_39452_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_9_4_fu_35933_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_4_V_read_1_reg_39445_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_9_5_fu_35940_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_5_V_read_1_reg_39438_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_9_fu_35905_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_1_2_0_V_read_1_reg_39473_pp0_iter1 : ap_const_lv7_0);
assign r_V_174_2_s_fu_36339_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_reg_ppstg_delta_th_2_2_0_V_read_1_reg_39347_pp0_iter1 : ap_const_lv7_0);
assign r_V_176_0_1_fu_18464_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_0_3_fu_19290_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_0_4_fu_19904_p3 = ((tmp_2006_fu_19442_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_0_5_fu_20392_p3 = ((tmp_2038_fu_19944_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_0_6_fu_20818_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_0_9_fu_22296_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_1_1_fu_25305_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_1_3_fu_26131_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_1_4_fu_26741_p3 = ((tmp_2347_fu_26279_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_1_5_fu_27229_p3 = ((tmp_2366_fu_26781_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_1_6_fu_27655_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_1_9_fu_29133_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_2_1_fu_32142_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_2_3_fu_32968_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_2_4_fu_33578_p3 = ((tmp_2584_fu_33116_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_2_5_fu_34066_p3 = ((tmp_2603_fu_33618_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_2_6_fu_34492_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_176_2_9_fu_35970_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign r_V_177_0_2_fu_18880_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_0_3_fu_19298_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_const_lv4_7 : ap_const_lv4_0);
assign r_V_177_0_4_2_fu_19685_p3 = {{1'b0}, {tmp_418_fu_19679_p2}};
assign r_V_177_0_4_3_fu_19712_p3 = {{1'b0}, {tmp_420_fu_19706_p2}};
assign r_V_177_0_4_fu_19660_p4 = {{{{1'b0}, {tmp_2032_fu_19652_p3}}}, {tmp_416_fu_19646_p2}};
assign r_V_177_0_5_2_fu_20187_p3 = {{tmp_2067_fu_20179_p3}, {tmp_437_fu_20173_p2}};
assign r_V_177_0_5_fu_20152_p3 = {{tmp_435_fu_20142_p4}, {tmp_434_fu_20136_p2}};
assign r_V_177_0_6_fu_20826_p3 = ((tmp_2071_fu_20424_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_0_7_2_fu_21264_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_0_8_2_fu_21597_p3 = {{tmp_2135_fu_21296_p3}, {tmp_486_fu_21591_p2}};
assign r_V_177_0_8_3_fu_21624_p3 = {{tmp_2139_fu_21336_p3}, {tmp_488_fu_21618_p2}};
assign r_V_177_0_8_fu_21574_p3 = {{tmp_484_fu_21564_p4}, {tmp_483_fu_21558_p2}};
assign r_V_177_0_9_2_fu_22091_p3 = {{tmp_2201_fu_22083_p3}, {tmp_505_fu_22077_p2}};
assign r_V_177_0_9_3_fu_22320_p3 = ((tmp_2172_fu_21848_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_0_9_fu_22056_p3 = {{tmp_503_fu_22046_p4}, {tmp_502_fu_22040_p2}};
assign r_V_177_0_s_fu_22730_p3 = ((tmp_2205_fu_22336_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_1_2_fu_25721_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_1_3_fu_26139_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_const_lv4_7 : ap_const_lv4_0);
assign r_V_177_1_4_2_fu_26522_p3 = {{1'b0}, {tmp_601_fu_26516_p2}};
assign r_V_177_1_4_3_fu_26549_p3 = {{1'b0}, {tmp_603_fu_26543_p2}};
assign r_V_177_1_4_fu_26497_p4 = {{{{1'b0}, {tmp_2361_fu_26489_p3}}}, {tmp_599_fu_26483_p2}};
assign r_V_177_1_5_2_fu_27024_p3 = {{tmp_2382_fu_27016_p3}, {tmp_620_fu_27010_p2}};
assign r_V_177_1_5_fu_26989_p3 = {{tmp_618_fu_26979_p4}, {tmp_617_fu_26973_p2}};
assign r_V_177_1_6_fu_27663_p3 = ((tmp_2386_fu_27261_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_1_7_2_fu_28101_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_1_8_2_fu_28434_p3 = {{tmp_2424_fu_28133_p3}, {tmp_669_fu_28428_p2}};
assign r_V_177_1_8_3_fu_28461_p3 = {{tmp_2428_fu_28173_p3}, {tmp_671_fu_28455_p2}};
assign r_V_177_1_8_fu_28411_p3 = {{tmp_667_fu_28401_p4}, {tmp_666_fu_28395_p2}};
assign r_V_177_1_9_2_fu_28928_p3 = {{tmp_2464_fu_28920_p3}, {tmp_688_fu_28914_p2}};
assign r_V_177_1_9_3_fu_29157_p3 = ((tmp_2448_fu_28685_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_1_9_fu_28893_p3 = {{tmp_686_fu_28883_p4}, {tmp_685_fu_28877_p2}};
assign r_V_177_1_s_fu_29567_p3 = ((tmp_2468_fu_29173_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_2_2_fu_32558_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_2_3_fu_32976_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_const_lv4_7 : ap_const_lv4_0);
assign r_V_177_2_4_2_fu_33359_p3 = {{1'b0}, {tmp_784_fu_33353_p2}};
assign r_V_177_2_4_3_fu_33386_p3 = {{1'b0}, {tmp_786_fu_33380_p2}};
assign r_V_177_2_4_fu_33334_p4 = {{{{1'b0}, {tmp_2598_fu_33326_p3}}}, {tmp_782_fu_33320_p2}};
assign r_V_177_2_5_2_fu_33861_p3 = {{tmp_2619_fu_33853_p3}, {tmp_803_fu_33847_p2}};
assign r_V_177_2_5_fu_33826_p3 = {{tmp_801_fu_33816_p4}, {tmp_800_fu_33810_p2}};
assign r_V_177_2_6_fu_34500_p3 = ((tmp_2623_fu_34098_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_2_7_2_fu_34938_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_2_8_2_fu_35271_p3 = {{tmp_2661_fu_34970_p3}, {tmp_852_fu_35265_p2}};
assign r_V_177_2_8_3_fu_35298_p3 = {{tmp_2665_fu_35010_p3}, {tmp_854_fu_35292_p2}};
assign r_V_177_2_8_fu_35248_p3 = {{tmp_850_fu_35238_p4}, {tmp_849_fu_35232_p2}};
assign r_V_177_2_9_2_fu_35765_p3 = {{tmp_2701_fu_35757_p3}, {tmp_871_fu_35751_p2}};
assign r_V_177_2_9_3_fu_35994_p3 = ((tmp_2685_fu_35522_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_177_2_9_fu_35730_p3 = {{tmp_869_fu_35720_p4}, {tmp_868_fu_35714_p2}};
assign r_V_177_2_s_fu_36404_p3 = ((tmp_2705_fu_36010_p3[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_0);
assign r_V_179_11_s_fu_7946_p2 = (tmp135_fu_7940_p2 | tmp115_fu_7224_p2);
assign rhs_i126_0_i_10_fu_15384_p2 = (tmp991_fu_15378_p2 & rhs_i_i130_0_i_10_fu_15354_p2);
assign rhs_i126_0_i_1_fu_9570_p2 = (tmp208_fu_9564_p2 & rhs_i_i130_0_i_2_fu_9540_p2);
assign rhs_i126_0_i_2_fu_10216_p2 = (tmp241_fu_10210_p2 & rhs_i_i130_0_i_3_fu_10186_p2);
assign rhs_i126_0_i_3_fu_10862_p2 = (tmp604_fu_10856_p2 & rhs_i_i130_0_i_4_fu_10832_p2);
assign rhs_i126_0_i_4_fu_11508_p2 = (tmp637_fu_11502_p2 & rhs_i_i130_0_i_5_fu_11478_p2);
assign rhs_i126_0_i_5_fu_12154_p2 = (tmp670_fu_12148_p2 & rhs_i_i130_0_i_6_fu_12124_p2);
assign rhs_i126_0_i_6_fu_12800_p2 = (tmp705_fu_12794_p2 & rhs_i_i130_0_i_7_fu_12770_p2);
assign rhs_i126_0_i_7_fu_13446_p2 = (tmp898_fu_13440_p2 & rhs_i_i130_0_i_8_fu_13416_p2);
assign rhs_i126_0_i_8_fu_14092_p2 = (tmp929_fu_14086_p2 & rhs_i_i130_0_i_9_fu_14062_p2);
assign rhs_i126_0_i_9_fu_14738_p2 = (tmp960_fu_14732_p2 & rhs_i_i130_0_i_s_fu_14708_p2);
assign rhs_i126_0_i_fu_8200_p2 = (tmp142_fu_8194_p2 & rhs_i_i130_0_i_fu_8170_p2);
assign rhs_i126_0_i_s_fu_8894_p2 = (tmp175_fu_8888_p2 & rhs_i_i130_0_i_1_fu_8864_p2);
assign rhs_i132_0_i_10_fu_15348_p2 = (tmp988_fu_15342_p2 & tmp_1877_fu_15194_p3);
assign rhs_i132_0_i_1_fu_8858_p2 = (tmp172_fu_8852_p2 & tmp_1607_fu_8704_p3);
assign rhs_i132_0_i_2_fu_9534_p2 = (tmp205_fu_9528_p2 & tmp_1634_fu_9380_p3);
assign rhs_i132_0_i_3_fu_10180_p2 = (tmp238_fu_10174_p2 & tmp_1661_fu_10026_p3);
assign rhs_i132_0_i_4_fu_10826_p2 = (tmp601_fu_10820_p2 & tmp_1688_fu_10672_p3);
assign rhs_i132_0_i_5_fu_11472_p2 = (tmp634_fu_11466_p2 & tmp_1715_fu_11318_p3);
assign rhs_i132_0_i_6_fu_12118_p2 = (tmp667_fu_12112_p2 & tmp_1742_fu_11964_p3);
assign rhs_i132_0_i_7_fu_12764_p2 = (tmp702_fu_12758_p2 & tmp_1769_fu_12610_p3);
assign rhs_i132_0_i_8_fu_13410_p2 = (tmp895_fu_13404_p2 & tmp_1796_fu_13256_p3);
assign rhs_i132_0_i_9_fu_14056_p2 = (tmp926_fu_14050_p2 & tmp_1823_fu_13902_p3);
assign rhs_i132_0_i_fu_8164_p2 = (tmp139_fu_8158_p2 & tmp_1587_fu_8010_p3);
assign rhs_i132_0_i_s_fu_14702_p2 = (tmp957_fu_14696_p2 & tmp_1850_fu_14548_p3);
assign rhs_i138_0_i_10_fu_15360_p2 = (tmp987_fu_15330_p2 | lhs_i_i145_0_i_10_fu_15312_p2);
assign rhs_i138_0_i_1_fu_9546_p2 = (tmp204_fu_9516_p2 | lhs_i_i145_0_i_2_fu_9498_p2);
assign rhs_i138_0_i_2_fu_10192_p2 = (tmp237_fu_10162_p2 | lhs_i_i145_0_i_3_fu_10144_p2);
assign rhs_i138_0_i_3_fu_10838_p2 = (tmp600_fu_10808_p2 | lhs_i_i145_0_i_4_fu_10790_p2);
assign rhs_i138_0_i_4_fu_11484_p2 = (tmp633_fu_11454_p2 | lhs_i_i145_0_i_5_fu_11436_p2);
assign rhs_i138_0_i_5_fu_12130_p2 = (tmp666_fu_12100_p2 | lhs_i_i145_0_i_6_fu_12082_p2);
assign rhs_i138_0_i_6_fu_12776_p2 = (tmp701_fu_12746_p2 | lhs_i_i145_0_i_7_fu_12728_p2);
assign rhs_i138_0_i_7_fu_13422_p2 = (tmp894_fu_13392_p2 | lhs_i_i145_0_i_8_fu_13374_p2);
assign rhs_i138_0_i_8_fu_14068_p2 = (tmp925_fu_14038_p2 | lhs_i_i145_0_i_9_fu_14020_p2);
assign rhs_i138_0_i_9_fu_14714_p2 = (tmp956_fu_14684_p2 | lhs_i_i145_0_i_s_fu_14666_p2);
assign rhs_i138_0_i_fu_8176_p2 = (tmp138_fu_8146_p2 | lhs_i_i145_0_i_fu_8128_p2);
assign rhs_i138_0_i_s_fu_8870_p2 = (tmp171_fu_8840_p2 | lhs_i_i145_0_i_1_fu_8822_p2);
assign rhs_i38_0_i_10_fu_15696_p2 = (tmp1011_fu_15690_p2 & rhs_i_i42_0_i_10_fu_15666_p2);
assign rhs_i38_0_i_1_fu_9882_p2 = (tmp228_fu_9876_p2 & rhs_i_i42_0_i_2_fu_9852_p2);
assign rhs_i38_0_i_2_fu_10528_p2 = (tmp261_fu_10522_p2 & rhs_i_i42_0_i_3_fu_10498_p2);
assign rhs_i38_0_i_3_fu_11174_p2 = (tmp624_fu_11168_p2 & rhs_i_i42_0_i_4_fu_11144_p2);
assign rhs_i38_0_i_4_fu_11820_p2 = (tmp657_fu_11814_p2 & rhs_i_i42_0_i_5_fu_11790_p2);
assign rhs_i38_0_i_5_fu_12466_p2 = (tmp690_fu_12460_p2 & rhs_i_i42_0_i_6_fu_12436_p2);
assign rhs_i38_0_i_6_fu_13112_p2 = (tmp725_fu_13106_p2 & rhs_i_i42_0_i_7_fu_13082_p2);
assign rhs_i38_0_i_7_fu_13758_p2 = (tmp918_fu_13752_p2 & rhs_i_i42_0_i_8_fu_13728_p2);
assign rhs_i38_0_i_8_fu_14404_p2 = (tmp949_fu_14398_p2 & rhs_i_i42_0_i_9_fu_14374_p2);
assign rhs_i38_0_i_9_fu_15050_p2 = (tmp980_fu_15044_p2 & rhs_i_i42_0_i_s_fu_15020_p2);
assign rhs_i38_0_i_fu_8512_p2 = (tmp162_fu_8506_p2 & rhs_i_i42_0_i_fu_8482_p2);
assign rhs_i38_0_i_s_fu_9206_p2 = (tmp195_fu_9200_p2 & rhs_i_i42_0_i_1_fu_9176_p2);
assign rhs_i44_0_i_10_fu_15660_p2 = (tmp1008_fu_15654_p2 & tmp_1885_fu_15254_p3);
assign rhs_i44_0_i_1_fu_9170_p2 = (tmp192_fu_9164_p2 & tmp_1615_fu_8764_p3);
assign rhs_i44_0_i_2_fu_9846_p2 = (tmp225_fu_9840_p2 & tmp_1642_fu_9440_p3);
assign rhs_i44_0_i_3_fu_10492_p2 = (tmp258_fu_10486_p2 & tmp_1669_fu_10086_p3);
assign rhs_i44_0_i_4_fu_11138_p2 = (tmp621_fu_11132_p2 & tmp_1696_fu_10732_p3);
assign rhs_i44_0_i_5_fu_11784_p2 = (tmp654_fu_11778_p2 & tmp_1723_fu_11378_p3);
assign rhs_i44_0_i_6_fu_12430_p2 = (tmp687_fu_12424_p2 & tmp_1750_fu_12024_p3);
assign rhs_i44_0_i_7_fu_13076_p2 = (tmp722_fu_13070_p2 & tmp_1777_fu_12670_p3);
assign rhs_i44_0_i_8_fu_13722_p2 = (tmp915_fu_13716_p2 & tmp_1804_fu_13316_p3);
assign rhs_i44_0_i_9_fu_14368_p2 = (tmp946_fu_14362_p2 & tmp_1831_fu_13962_p3);
assign rhs_i44_0_i_fu_8476_p2 = (tmp159_fu_8470_p2 & tmp_1595_fu_8070_p3);
assign rhs_i44_0_i_s_fu_15014_p2 = (tmp977_fu_15008_p2 & tmp_1858_fu_14608_p3);
assign rhs_i50_0_i1_10_fu_15672_p2 = (tmp1007_fu_15642_p2 | lhs_i_i57_0_i_10_fu_15624_p2);
assign rhs_i50_0_i1_1_fu_9858_p2 = (tmp224_fu_9828_p2 | lhs_i_i57_0_i_2_fu_9810_p2);
assign rhs_i50_0_i1_2_fu_10504_p2 = (tmp257_fu_10474_p2 | lhs_i_i57_0_i_3_fu_10456_p2);
assign rhs_i50_0_i1_3_fu_11150_p2 = (tmp620_fu_11120_p2 | lhs_i_i57_0_i_4_fu_11102_p2);
assign rhs_i50_0_i1_4_fu_11796_p2 = (tmp653_fu_11766_p2 | lhs_i_i57_0_i_5_fu_11748_p2);
assign rhs_i50_0_i1_5_fu_12442_p2 = (tmp686_fu_12412_p2 | lhs_i_i57_0_i_6_fu_12394_p2);
assign rhs_i50_0_i1_6_fu_13088_p2 = (tmp721_fu_13058_p2 | lhs_i_i57_0_i_7_fu_13040_p2);
assign rhs_i50_0_i1_7_fu_13734_p2 = (tmp914_fu_13704_p2 | lhs_i_i57_0_i_8_fu_13686_p2);
assign rhs_i50_0_i1_8_fu_14380_p2 = (tmp945_fu_14350_p2 | lhs_i_i57_0_i_9_fu_14332_p2);
assign rhs_i50_0_i1_9_fu_15026_p2 = (tmp976_fu_14996_p2 | lhs_i_i57_0_i_s_fu_14978_p2);
assign rhs_i50_0_i1_fu_8488_p2 = (tmp158_fu_8458_p2 | lhs_i_i57_0_i_fu_8440_p2);
assign rhs_i50_0_i1_s_fu_9182_p2 = (tmp191_fu_9152_p2 | lhs_i_i57_0_i_1_fu_9134_p2);
assign rhs_i82_0_i_10_fu_15540_p2 = (tmp1001_fu_15534_p2 & rhs_i_i86_0_i_10_fu_15510_p2);
assign rhs_i82_0_i_1_fu_9726_p2 = (tmp218_fu_9720_p2 & rhs_i_i86_0_i_2_fu_9696_p2);
assign rhs_i82_0_i_2_fu_10372_p2 = (tmp251_fu_10366_p2 & rhs_i_i86_0_i_3_fu_10342_p2);
assign rhs_i82_0_i_3_fu_11018_p2 = (tmp614_fu_11012_p2 & rhs_i_i86_0_i_4_fu_10988_p2);
assign rhs_i82_0_i_4_fu_11664_p2 = (tmp647_fu_11658_p2 & rhs_i_i86_0_i_5_fu_11634_p2);
assign rhs_i82_0_i_5_fu_12310_p2 = (tmp680_fu_12304_p2 & rhs_i_i86_0_i_6_fu_12280_p2);
assign rhs_i82_0_i_6_fu_12956_p2 = (tmp715_fu_12950_p2 & rhs_i_i86_0_i_7_fu_12926_p2);
assign rhs_i82_0_i_7_fu_13602_p2 = (tmp908_fu_13596_p2 & rhs_i_i86_0_i_8_fu_13572_p2);
assign rhs_i82_0_i_8_fu_14248_p2 = (tmp939_fu_14242_p2 & rhs_i_i86_0_i_9_fu_14218_p2);
assign rhs_i82_0_i_9_fu_14894_p2 = (tmp970_fu_14888_p2 & rhs_i_i86_0_i_s_fu_14864_p2);
assign rhs_i82_0_i_fu_8356_p2 = (tmp152_fu_8350_p2 & rhs_i_i86_0_i_fu_8326_p2);
assign rhs_i82_0_i_s_fu_9050_p2 = (tmp185_fu_9044_p2 & rhs_i_i86_0_i_1_fu_9020_p2);
assign rhs_i88_0_i_10_fu_15504_p2 = (tmp998_fu_15498_p2 & tmp_1881_fu_15222_p3);
assign rhs_i88_0_i_1_fu_9014_p2 = (tmp182_fu_9008_p2 & tmp_1611_fu_8732_p3);
assign rhs_i88_0_i_2_fu_9690_p2 = (tmp215_fu_9684_p2 & tmp_1638_fu_9408_p3);
assign rhs_i88_0_i_3_fu_10336_p2 = (tmp248_fu_10330_p2 & tmp_1665_fu_10054_p3);
assign rhs_i88_0_i_4_fu_10982_p2 = (tmp611_fu_10976_p2 & tmp_1692_fu_10700_p3);
assign rhs_i88_0_i_5_fu_11628_p2 = (tmp644_fu_11622_p2 & tmp_1719_fu_11346_p3);
assign rhs_i88_0_i_6_fu_12274_p2 = (tmp677_fu_12268_p2 & tmp_1746_fu_11992_p3);
assign rhs_i88_0_i_7_fu_12920_p2 = (tmp712_fu_12914_p2 & tmp_1773_fu_12638_p3);
assign rhs_i88_0_i_8_fu_13566_p2 = (tmp905_fu_13560_p2 & tmp_1800_fu_13284_p3);
assign rhs_i88_0_i_9_fu_14212_p2 = (tmp936_fu_14206_p2 & tmp_1827_fu_13930_p3);
assign rhs_i88_0_i_fu_8320_p2 = (tmp149_fu_8314_p2 & tmp_1591_fu_8038_p3);
assign rhs_i88_0_i_s_fu_14858_p2 = (tmp967_fu_14852_p2 & tmp_1854_fu_14576_p3);
assign rhs_i94_0_i_10_fu_15516_p2 = (tmp997_fu_15486_p2 | lhs_i_i101_0_i_10_fu_15468_p2);
assign rhs_i94_0_i_1_fu_9702_p2 = (tmp214_fu_9672_p2 | lhs_i_i101_0_i_2_fu_9654_p2);
assign rhs_i94_0_i_2_fu_10348_p2 = (tmp247_fu_10318_p2 | lhs_i_i101_0_i_3_fu_10300_p2);
assign rhs_i94_0_i_3_fu_10994_p2 = (tmp610_fu_10964_p2 | lhs_i_i101_0_i_4_fu_10946_p2);
assign rhs_i94_0_i_4_fu_11640_p2 = (tmp643_fu_11610_p2 | lhs_i_i101_0_i_5_fu_11592_p2);
assign rhs_i94_0_i_5_fu_12286_p2 = (tmp676_fu_12256_p2 | lhs_i_i101_0_i_6_fu_12238_p2);
assign rhs_i94_0_i_6_fu_12932_p2 = (tmp711_fu_12902_p2 | lhs_i_i101_0_i_7_fu_12884_p2);
assign rhs_i94_0_i_7_fu_13578_p2 = (tmp904_fu_13548_p2 | lhs_i_i101_0_i_8_fu_13530_p2);
assign rhs_i94_0_i_8_fu_14224_p2 = (tmp935_fu_14194_p2 | lhs_i_i101_0_i_9_fu_14176_p2);
assign rhs_i94_0_i_9_fu_14870_p2 = (tmp966_fu_14840_p2 | lhs_i_i101_0_i_s_fu_14822_p2);
assign rhs_i94_0_i_fu_8332_p2 = (tmp148_fu_8302_p2 | lhs_i_i101_0_i_fu_8284_p2);
assign rhs_i94_0_i_s_fu_9026_p2 = (tmp181_fu_8996_p2 | lhs_i_i101_0_i_1_fu_8978_p2);
assign rhs_i_i130_0_i_10_fu_15354_p2 = (tmp_1877_fu_15194_p3 ^ 1'b1);
assign rhs_i_i130_0_i_1_fu_8864_p2 = (tmp_1607_fu_8704_p3 ^ 1'b1);
assign rhs_i_i130_0_i_2_fu_9540_p2 = (tmp_1634_fu_9380_p3 ^ 1'b1);
assign rhs_i_i130_0_i_3_fu_10186_p2 = (tmp_1661_fu_10026_p3 ^ 1'b1);
assign rhs_i_i130_0_i_4_fu_10832_p2 = (tmp_1688_fu_10672_p3 ^ 1'b1);
assign rhs_i_i130_0_i_5_fu_11478_p2 = (tmp_1715_fu_11318_p3 ^ 1'b1);
assign rhs_i_i130_0_i_6_fu_12124_p2 = (tmp_1742_fu_11964_p3 ^ 1'b1);
assign rhs_i_i130_0_i_7_fu_12770_p2 = (tmp_1769_fu_12610_p3 ^ 1'b1);
assign rhs_i_i130_0_i_8_fu_13416_p2 = (tmp_1796_fu_13256_p3 ^ 1'b1);
assign rhs_i_i130_0_i_9_fu_14062_p2 = (tmp_1823_fu_13902_p3 ^ 1'b1);
assign rhs_i_i130_0_i_fu_8170_p2 = (tmp_1587_fu_8010_p3 ^ 1'b1);
assign rhs_i_i130_0_i_s_fu_14708_p2 = (tmp_1850_fu_14548_p3 ^ 1'b1);
assign rhs_i_i140_0_i_10_fu_15324_p2 = (tmp_1878_fu_15202_p1 ^ 1'b1);
assign rhs_i_i140_0_i_1_fu_8834_p2 = (tmp_1608_fu_8712_p1 ^ 1'b1);
assign rhs_i_i140_0_i_2_fu_9510_p2 = (tmp_1635_fu_9388_p1 ^ 1'b1);
assign rhs_i_i140_0_i_3_fu_10156_p2 = (tmp_1662_fu_10034_p1 ^ 1'b1);
assign rhs_i_i140_0_i_4_fu_10802_p2 = (tmp_1689_fu_10680_p1 ^ 1'b1);
assign rhs_i_i140_0_i_5_fu_11448_p2 = (tmp_1716_fu_11326_p1 ^ 1'b1);
assign rhs_i_i140_0_i_6_fu_12094_p2 = (tmp_1743_fu_11972_p1 ^ 1'b1);
assign rhs_i_i140_0_i_7_fu_12740_p2 = (tmp_1770_fu_12618_p1 ^ 1'b1);
assign rhs_i_i140_0_i_8_fu_13386_p2 = (tmp_1797_fu_13264_p1 ^ 1'b1);
assign rhs_i_i140_0_i_9_fu_14032_p2 = (tmp_1824_fu_13910_p1 ^ 1'b1);
assign rhs_i_i140_0_i_fu_8140_p2 = (tmp_1588_fu_8018_p1 ^ 1'b1);
assign rhs_i_i140_0_i_s_fu_14678_p2 = (tmp_1851_fu_14556_p1 ^ 1'b1);
assign rhs_i_i1_fu_7952_p2 = (r_V_179_11_s_fu_7946_p2 ^ ap_const_lv12_FFF);
assign rhs_i_i42_0_i_10_fu_15666_p2 = (tmp_1885_fu_15254_p3 ^ 1'b1);
assign rhs_i_i42_0_i_1_fu_9176_p2 = (tmp_1615_fu_8764_p3 ^ 1'b1);
assign rhs_i_i42_0_i_2_fu_9852_p2 = (tmp_1642_fu_9440_p3 ^ 1'b1);
assign rhs_i_i42_0_i_3_fu_10498_p2 = (tmp_1669_fu_10086_p3 ^ 1'b1);
assign rhs_i_i42_0_i_4_fu_11144_p2 = (tmp_1696_fu_10732_p3 ^ 1'b1);
assign rhs_i_i42_0_i_5_fu_11790_p2 = (tmp_1723_fu_11378_p3 ^ 1'b1);
assign rhs_i_i42_0_i_6_fu_12436_p2 = (tmp_1750_fu_12024_p3 ^ 1'b1);
assign rhs_i_i42_0_i_7_fu_13082_p2 = (tmp_1777_fu_12670_p3 ^ 1'b1);
assign rhs_i_i42_0_i_8_fu_13728_p2 = (tmp_1804_fu_13316_p3 ^ 1'b1);
assign rhs_i_i42_0_i_9_fu_14374_p2 = (tmp_1831_fu_13962_p3 ^ 1'b1);
assign rhs_i_i42_0_i_fu_8482_p2 = (tmp_1595_fu_8070_p3 ^ 1'b1);
assign rhs_i_i42_0_i_s_fu_15020_p2 = (tmp_1858_fu_14608_p3 ^ 1'b1);
assign rhs_i_i52_0_i_10_fu_15636_p2 = (tmp_1886_fu_15262_p3 ^ 1'b1);
assign rhs_i_i52_0_i_1_fu_9146_p2 = (tmp_1616_fu_8772_p3 ^ 1'b1);
assign rhs_i_i52_0_i_2_fu_9822_p2 = (tmp_1643_fu_9448_p3 ^ 1'b1);
assign rhs_i_i52_0_i_3_fu_10468_p2 = (tmp_1670_fu_10094_p3 ^ 1'b1);
assign rhs_i_i52_0_i_4_fu_11114_p2 = (tmp_1697_fu_10740_p3 ^ 1'b1);
assign rhs_i_i52_0_i_5_fu_11760_p2 = (tmp_1724_fu_11386_p3 ^ 1'b1);
assign rhs_i_i52_0_i_6_fu_12406_p2 = (tmp_1751_fu_12032_p3 ^ 1'b1);
assign rhs_i_i52_0_i_7_fu_13052_p2 = (tmp_1778_fu_12678_p3 ^ 1'b1);
assign rhs_i_i52_0_i_8_fu_13698_p2 = (tmp_1805_fu_13324_p3 ^ 1'b1);
assign rhs_i_i52_0_i_9_fu_14344_p2 = (tmp_1832_fu_13970_p3 ^ 1'b1);
assign rhs_i_i52_0_i_fu_8452_p2 = (tmp_1596_fu_8078_p3 ^ 1'b1);
assign rhs_i_i52_0_i_s_fu_14990_p2 = (tmp_1859_fu_14616_p3 ^ 1'b1);
assign rhs_i_i86_0_i_10_fu_15510_p2 = (tmp_1881_fu_15222_p3 ^ 1'b1);
assign rhs_i_i86_0_i_1_fu_9020_p2 = (tmp_1611_fu_8732_p3 ^ 1'b1);
assign rhs_i_i86_0_i_2_fu_9696_p2 = (tmp_1638_fu_9408_p3 ^ 1'b1);
assign rhs_i_i86_0_i_3_fu_10342_p2 = (tmp_1665_fu_10054_p3 ^ 1'b1);
assign rhs_i_i86_0_i_4_fu_10988_p2 = (tmp_1692_fu_10700_p3 ^ 1'b1);
assign rhs_i_i86_0_i_5_fu_11634_p2 = (tmp_1719_fu_11346_p3 ^ 1'b1);
assign rhs_i_i86_0_i_6_fu_12280_p2 = (tmp_1746_fu_11992_p3 ^ 1'b1);
assign rhs_i_i86_0_i_7_fu_12926_p2 = (tmp_1773_fu_12638_p3 ^ 1'b1);
assign rhs_i_i86_0_i_8_fu_13572_p2 = (tmp_1800_fu_13284_p3 ^ 1'b1);
assign rhs_i_i86_0_i_9_fu_14218_p2 = (tmp_1827_fu_13930_p3 ^ 1'b1);
assign rhs_i_i86_0_i_fu_8326_p2 = (tmp_1591_fu_8038_p3 ^ 1'b1);
assign rhs_i_i86_0_i_s_fu_14864_p2 = (tmp_1854_fu_14576_p3 ^ 1'b1);
assign rhs_i_i96_0_i_10_fu_15480_p2 = (tmp_1882_fu_15230_p3 ^ 1'b1);
assign rhs_i_i96_0_i_1_fu_8990_p2 = (tmp_1612_fu_8740_p3 ^ 1'b1);
assign rhs_i_i96_0_i_2_fu_9666_p2 = (tmp_1639_fu_9416_p3 ^ 1'b1);
assign rhs_i_i96_0_i_3_fu_10312_p2 = (tmp_1666_fu_10062_p3 ^ 1'b1);
assign rhs_i_i96_0_i_4_fu_10958_p2 = (tmp_1693_fu_10708_p3 ^ 1'b1);
assign rhs_i_i96_0_i_5_fu_11604_p2 = (tmp_1720_fu_11354_p3 ^ 1'b1);
assign rhs_i_i96_0_i_6_fu_12250_p2 = (tmp_1747_fu_12000_p3 ^ 1'b1);
assign rhs_i_i96_0_i_7_fu_12896_p2 = (tmp_1774_fu_12646_p3 ^ 1'b1);
assign rhs_i_i96_0_i_8_fu_13542_p2 = (tmp_1801_fu_13292_p3 ^ 1'b1);
assign rhs_i_i96_0_i_9_fu_14188_p2 = (tmp_1828_fu_13938_p3 ^ 1'b1);
assign rhs_i_i96_0_i_fu_8296_p2 = (tmp_1592_fu_8046_p3 ^ 1'b1);
assign rhs_i_i96_0_i_s_fu_14834_p2 = (tmp_1855_fu_14584_p3 ^ 1'b1);
assign rhs_i_i_fu_7974_p2 = (r_V_179_11_s_fu_7946_p2 | p_01272_0_not_fu_7964_p2);
assign tmp1000_fu_15528_p2 = (tmp999_fu_15522_p2 | lhs_i99_0_i_10_fu_15456_p2);
assign tmp1001_fu_15534_p2 = (rhs_i_i96_0_i_10_fu_15480_p2 | lhs_i_i91_0_i_10_fu_15492_p2);
assign tmp1002_fu_15546_p2 = (rhs_i82_0_i_10_fu_15540_p2 & tmp_1879_fu_15206_p3);
assign tmp1003_fu_15552_p2 = (tmp1002_fu_15546_p2 | rhs_i88_0_i_10_fu_15504_p2);
assign tmp1004_fu_15564_p2 = (tmp_1881_fu_15222_p3 | tmp_1882_fu_15230_p3);
assign tmp1005_fu_15582_p2 = (tmp_1886_fu_15262_p3 ^ tmp_1885_fu_15254_p3);
assign tmp1006_fu_15588_p2 = (tmp_1883_fu_15238_p3 ^ tmp_1884_fu_15246_p3);
assign tmp1007_fu_15642_p2 = (lhs_i_i53_0_i_10_fu_15630_p2 & rhs_i_i52_0_i_10_fu_15636_p2);
assign tmp1008_fu_15654_p2 = (lhs_i_i47_0_i_10_fu_15648_p2 & rhs_i_i52_0_i_10_fu_15636_p2);
assign tmp1009_fu_15678_p2 = (tmp_1885_fu_15254_p3 & rhs_i50_0_i1_10_fu_15672_p2);
assign tmp100_fu_6780_p3 = {{tmp_257_fu_6770_p4}, {tmp_256_fu_6764_p2}};
assign tmp1010_fu_15684_p2 = (tmp1009_fu_15678_p2 | lhs_i55_0_i_10_fu_15612_p2);
assign tmp1011_fu_15690_p2 = (rhs_i_i52_0_i_10_fu_15636_p2 | lhs_i_i47_0_i_10_fu_15648_p2);
assign tmp1012_fu_15702_p2 = (rhs_i38_0_i_10_fu_15696_p2 & tmp_1883_fu_15238_p3);
assign tmp1013_fu_15708_p2 = (tmp1012_fu_15702_p2 | rhs_i44_0_i_10_fu_15660_p2);
assign tmp1014_fu_15720_p2 = (tmp_1885_fu_15254_p3 | tmp_1886_fu_15262_p3);
assign tmp1015_fu_15780_p2 = (tmp_1399_10_fu_15776_p1 + tmp_1397_10_fu_15748_p1);
assign tmp101_fu_6808_p3 = {{tmp_259_fu_6798_p4}, {tmp_258_fu_6792_p2}};
assign tmp102_fu_6816_p2 = (tmp101_fu_6808_p3 | tmp100_fu_6780_p3);
assign tmp1033_fu_19352_p3 = {{tmp_1998_fu_19346_p2}, {ap_const_lv2_0}};
assign tmp1034_fu_19396_p3 = {{tmp_2003_fu_19390_p2}, {ap_const_lv2_0}};
assign tmp103_fu_6840_p3 = {{tmp_1523_fu_6832_p3}, {tmp_260_fu_6826_p2}};
assign tmp104_fu_6848_p2 = (tmp103_fu_6840_p3 | tmp96_fu_6694_p2);
assign tmp105_fu_6894_p3 = {{tmp_264_fu_6884_p4}, {tmp_263_fu_6878_p2}};
assign tmp1065_fu_21250_p3 = {{1'b0}, {tmp_470_fu_21244_p2}};
assign tmp1066_fu_21278_p3 = {{tmp_2132_fu_21272_p2}, {ap_const_lv2_0}};
assign tmp1067_fu_21318_p3 = {{tmp_2136_fu_21312_p2}, {ap_const_lv2_0}};
assign tmp1069_fu_22998_p2 = (r_V_170_0_1_fu_18315_p3 | r_V_170_0_2_fu_18731_p3);
assign tmp106_fu_6924_p3 = {{tmp_1526_fu_6916_p3}, {tmp_266_fu_6910_p2}};
assign tmp1070_fu_23004_p2 = (tmp1069_fu_22998_p2 | bt_phi_V_fu_17915_p3);
assign tmp1071_fu_23010_p2 = (r_V_170_0_4_fu_19755_p3 | r_V_170_0_5_fu_20243_p3);
assign tmp1072_fu_23016_p2 = (tmp1071_fu_23010_p2 | r_V_170_0_3_fu_19141_p3);
assign tmp1073_fu_23022_p2 = (tmp1072_fu_23016_p2 | tmp1070_fu_23004_p2);
assign tmp1074_fu_23028_p2 = (r_V_170_0_7_fu_21087_p3 | r_V_170_0_8_fu_21667_p3);
assign tmp1075_fu_23034_p2 = (tmp1074_fu_23028_p2 | r_V_170_0_6_fu_20669_p3);
assign tmp1076_fu_23040_p2 = (r_V_170_0_s_fu_22581_p3 | r_V_170_0_10_fu_22991_p3);
assign tmp1077_fu_23046_p2 = (tmp1076_fu_23040_p2 | r_V_170_0_9_fu_22147_p3);
assign tmp1078_fu_23052_p2 = (tmp1077_fu_23046_p2 | tmp1075_fu_23034_p2);
assign tmp1079_fu_23071_p2 = (r_V_171_0_1_fu_18322_p3 | r_V_171_0_2_fu_18738_p3);
assign tmp107_fu_6972_p3 = {{tmp_270_fu_6962_p4}, {tmp_269_fu_6956_p2}};
assign tmp1080_fu_23077_p2 = (tmp1079_fu_23071_p2 | bt_theta_V_fu_17922_p3);
assign tmp1081_fu_23083_p2 = (r_V_171_0_4_fu_19762_p3 | r_V_171_0_5_fu_20250_p3);
assign tmp1082_fu_23089_p2 = (tmp1081_fu_23083_p2 | r_V_171_0_3_fu_19148_p3);
assign tmp1083_fu_23095_p2 = (tmp1082_fu_23089_p2 | tmp1080_fu_23077_p2);
assign tmp1084_fu_23101_p2 = (r_V_171_0_7_fu_21094_p3 | r_V_171_0_8_fu_21674_p3);
assign tmp1085_fu_23107_p2 = (tmp1084_fu_23101_p2 | r_V_171_0_6_fu_20676_p3);
assign tmp1086_fu_23113_p2 = (r_V_171_0_s_fu_22588_p3 | r_V_171_0_10_fu_23064_p3);
assign tmp1087_fu_23119_p2 = (tmp1086_fu_23113_p2 | r_V_171_0_9_fu_22154_p3);
assign tmp1088_fu_23125_p2 = (tmp1087_fu_23119_p2 | tmp1085_fu_23107_p2);
assign tmp1089_fu_23144_p2 = (r_V_172_0_1_fu_18329_p3 | r_V_172_0_2_fu_18745_p3);
assign tmp108_fu_7008_p3 = {{tmp_1529_fu_6994_p3}, {tmp_273_fu_7002_p2}};
assign tmp1090_fu_23150_p2 = (tmp1089_fu_23144_p2 | bt_cpattern_V_fu_17929_p3);
assign tmp1091_fu_23156_p2 = (r_V_172_0_4_fu_19769_p3 | r_V_172_0_5_fu_20257_p3);
assign tmp1092_fu_23162_p2 = (tmp1091_fu_23156_p2 | r_V_172_0_3_fu_19155_p3);
assign tmp1093_fu_23168_p2 = (tmp1092_fu_23162_p2 | tmp1090_fu_23150_p2);
assign tmp1094_fu_23174_p2 = (r_V_172_0_7_fu_21101_p3 | r_V_172_0_8_fu_21681_p3);
assign tmp1095_fu_23180_p2 = (tmp1094_fu_23174_p2 | r_V_172_0_6_fu_20683_p3);
assign tmp1096_fu_23186_p2 = (r_V_172_0_s_fu_22595_p3 | r_V_172_0_10_fu_23137_p3);
assign tmp1097_fu_23192_p2 = (tmp1096_fu_23186_p2 | r_V_172_0_9_fu_22161_p3);
assign tmp1098_fu_23198_p2 = (tmp1097_fu_23192_p2 | tmp1095_fu_23180_p2);
assign tmp1099_fu_23217_p2 = (r_V_172_0_1_1_fu_18336_p3 | r_V_172_0_2_1_fu_18752_p3);
assign tmp109_fu_7036_p3 = {{tmp_275_fu_7026_p4}, {tmp_274_fu_7020_p2}};
assign tmp1100_fu_23223_p2 = (tmp1099_fu_23217_p2 | bt_cpattern_V1_fu_17936_p3);
assign tmp1101_fu_23229_p2 = (r_V_172_0_4_1_fu_19776_p3 | r_V_172_0_5_1_fu_20264_p3);
assign tmp1102_fu_23235_p2 = (tmp1101_fu_23229_p2 | r_V_172_0_3_1_fu_19162_p3);
assign tmp1103_fu_23241_p2 = (tmp1102_fu_23235_p2 | tmp1100_fu_23223_p2);
assign tmp1104_fu_23247_p2 = (r_V_172_0_7_1_fu_21108_p3 | r_V_172_0_8_1_fu_21688_p3);
assign tmp1105_fu_23253_p2 = (tmp1104_fu_23247_p2 | r_V_172_0_6_1_fu_20690_p3);
assign tmp1106_fu_23259_p2 = (r_V_172_0_10_1_fu_22602_p3 | r_V_172_0_11_1_fu_23210_p3);
assign tmp1107_fu_23265_p2 = (tmp1106_fu_23259_p2 | r_V_172_0_9_1_fu_22168_p3);
assign tmp1108_fu_23271_p2 = (tmp1107_fu_23265_p2 | tmp1105_fu_23253_p2);
assign tmp1109_fu_23290_p2 = (r_V_172_0_1_2_fu_18343_p3 | r_V_172_0_2_2_fu_18759_p3);
assign tmp110_fu_7086_p3 = {{tmp_279_fu_7076_p4}, {tmp_278_fu_7070_p2}};
assign tmp1110_fu_23296_p2 = (tmp1109_fu_23290_p2 | bt_cpattern_V2_fu_17943_p3);
assign tmp1111_fu_23302_p2 = (r_V_172_0_4_2_fu_19783_p3 | r_V_172_0_5_2_fu_20271_p3);
assign tmp1112_fu_23308_p2 = (tmp1111_fu_23302_p2 | r_V_172_0_3_2_fu_19169_p3);
assign tmp1113_fu_23314_p2 = (tmp1112_fu_23308_p2 | tmp1110_fu_23296_p2);
assign tmp1114_fu_23320_p2 = (r_V_172_0_7_2_fu_21115_p3 | r_V_172_0_8_2_fu_21695_p3);
assign tmp1115_fu_23326_p2 = (tmp1114_fu_23320_p2 | r_V_172_0_6_2_fu_20697_p3);
assign tmp1116_fu_23332_p2 = (r_V_172_0_10_2_fu_22609_p3 | r_V_172_0_11_2_fu_23283_p3);
assign tmp1117_fu_23338_p2 = (tmp1116_fu_23332_p2 | r_V_172_0_9_2_fu_22175_p3);
assign tmp1118_fu_23344_p2 = (tmp1117_fu_23338_p2 | tmp1115_fu_23326_p2);
assign tmp1119_fu_23363_p2 = (r_V_172_0_1_3_fu_18350_p3 | r_V_172_0_2_3_fu_18766_p3);
assign tmp111_fu_7114_p3 = {{tmp_281_fu_7104_p4}, {tmp_280_fu_7098_p2}};
assign tmp1120_fu_23369_p2 = (tmp1119_fu_23363_p2 | bt_cpattern_V3_fu_17950_p3);
assign tmp1121_fu_23375_p2 = (r_V_172_0_4_3_fu_19790_p3 | r_V_172_0_5_3_fu_20278_p3);
assign tmp1122_fu_23381_p2 = (tmp1121_fu_23375_p2 | r_V_172_0_3_3_fu_19176_p3);
assign tmp1123_fu_23387_p2 = (tmp1122_fu_23381_p2 | tmp1120_fu_23369_p2);
assign tmp1124_fu_23393_p2 = (r_V_172_0_7_3_fu_21122_p3 | r_V_172_0_8_3_fu_21702_p3);
assign tmp1125_fu_23399_p2 = (tmp1124_fu_23393_p2 | r_V_172_0_6_3_fu_20704_p3);
assign tmp1126_fu_23405_p2 = (r_V_172_0_10_3_fu_22616_p3 | r_V_172_0_11_3_fu_23356_p3);
assign tmp1127_fu_23411_p2 = (tmp1126_fu_23405_p2 | r_V_172_0_9_3_fu_22182_p3);
assign tmp1128_fu_23417_p2 = (tmp1127_fu_23411_p2 | tmp1125_fu_23399_p2);
assign tmp1129_fu_23436_p2 = (r_V_173_0_1_fu_18357_p3 | r_V_173_0_2_fu_18773_p3);
assign tmp112_fu_7140_p3 = {{tmp_1535_fu_7132_p3}, {tmp_282_fu_7126_p2}};
assign tmp1130_fu_23442_p2 = (tmp1129_fu_23436_p2 | bt_delta_ph_V_fu_17957_p3);
assign tmp1131_fu_23448_p2 = (r_V_173_0_4_fu_19797_p3 | r_V_173_0_5_fu_20285_p3);
assign tmp1132_fu_23454_p2 = (tmp1131_fu_23448_p2 | r_V_173_0_3_fu_19183_p3);
assign tmp1133_fu_23460_p2 = (tmp1132_fu_23454_p2 | tmp1130_fu_23442_p2);
assign tmp1134_fu_23466_p2 = (r_V_173_0_7_fu_21129_p3 | r_V_173_0_8_fu_21709_p3);
assign tmp1135_fu_23472_p2 = (tmp1134_fu_23466_p2 | r_V_173_0_6_fu_20711_p3);
assign tmp1136_fu_23478_p2 = (r_V_173_0_s_fu_22623_p3 | r_V_173_0_10_fu_23429_p3);
assign tmp1137_fu_23484_p2 = (tmp1136_fu_23478_p2 | r_V_173_0_9_fu_22189_p3);
assign tmp1138_fu_23490_p2 = (tmp1137_fu_23484_p2 | tmp1135_fu_23472_p2);
assign tmp1139_fu_23509_p2 = (r_V_173_0_1_1_fu_18364_p3 | r_V_173_0_2_1_fu_18780_p3);
assign tmp113_fu_7210_p3 = {{tmp_1539_fu_7202_p3}, {tmp_287_fu_7196_p2}};
assign tmp1140_fu_23515_p2 = (tmp1139_fu_23509_p2 | bt_delta_ph_V1_fu_17964_p3);
assign tmp1141_fu_23521_p2 = (r_V_173_0_4_1_fu_19804_p3 | r_V_173_0_5_1_fu_20292_p3);
assign tmp1142_fu_23527_p2 = (tmp1141_fu_23521_p2 | r_V_173_0_3_1_fu_19190_p3);
assign tmp1143_fu_23533_p2 = (tmp1142_fu_23527_p2 | tmp1140_fu_23515_p2);
assign tmp1144_fu_23539_p2 = (r_V_173_0_7_1_fu_21136_p3 | r_V_173_0_8_1_fu_21716_p3);
assign tmp1145_fu_23545_p2 = (tmp1144_fu_23539_p2 | r_V_173_0_6_1_fu_20718_p3);
assign tmp1146_fu_23551_p2 = (r_V_173_0_10_1_fu_22630_p3 | r_V_173_0_11_1_fu_23502_p3);
assign tmp1147_fu_23557_p2 = (tmp1146_fu_23551_p2 | r_V_173_0_9_1_fu_22196_p3);
assign tmp1148_fu_23563_p2 = (tmp1147_fu_23557_p2 | tmp1145_fu_23545_p2);
assign tmp1149_fu_23582_p2 = (r_V_173_0_1_2_fu_18371_p3 | r_V_173_0_2_2_fu_18787_p3);
assign tmp114_fu_7218_p2 = (tmp113_fu_7210_p3 | tmp108_fu_7008_p3);
assign tmp1150_fu_23588_p2 = (tmp1149_fu_23582_p2 | bt_delta_ph_V2_fu_17971_p3);
assign tmp1151_fu_23594_p2 = (r_V_173_0_4_2_fu_19811_p3 | r_V_173_0_5_2_fu_20299_p3);
assign tmp1152_fu_23600_p2 = (tmp1151_fu_23594_p2 | r_V_173_0_3_2_fu_19197_p3);
assign tmp1153_fu_23606_p2 = (tmp1152_fu_23600_p2 | tmp1150_fu_23588_p2);
assign tmp1154_fu_23612_p2 = (r_V_173_0_7_2_fu_21143_p3 | r_V_173_0_8_2_fu_21723_p3);
assign tmp1155_fu_23618_p2 = (tmp1154_fu_23612_p2 | r_V_173_0_6_2_fu_20725_p3);
assign tmp1156_fu_23624_p2 = (r_V_173_0_10_2_fu_22637_p3 | r_V_173_0_11_2_fu_23575_p3);
assign tmp1157_fu_23630_p2 = (tmp1156_fu_23624_p2 | r_V_173_0_9_2_fu_22203_p3);
assign tmp1158_fu_23636_p2 = (tmp1157_fu_23630_p2 | tmp1155_fu_23618_p2);
assign tmp1159_fu_23655_p2 = (r_V_173_0_1_3_fu_18378_p3 | r_V_173_0_2_3_fu_18794_p3);
assign tmp115_fu_7224_p2 = (tmp114_fu_7218_p2 | tmp104_fu_6848_p2);
assign tmp1160_fu_23661_p2 = (tmp1159_fu_23655_p2 | bt_delta_ph_V3_fu_17978_p3);
assign tmp1161_fu_23667_p2 = (r_V_173_0_4_3_fu_19818_p3 | r_V_173_0_5_3_fu_20306_p3);
assign tmp1162_fu_23673_p2 = (tmp1161_fu_23667_p2 | r_V_173_0_3_3_fu_19204_p3);
assign tmp1163_fu_23679_p2 = (tmp1162_fu_23673_p2 | tmp1160_fu_23661_p2);
assign tmp1164_fu_23685_p2 = (r_V_173_0_7_3_fu_21150_p3 | r_V_173_0_8_3_fu_21730_p3);
assign tmp1165_fu_23691_p2 = (tmp1164_fu_23685_p2 | r_V_173_0_6_3_fu_20732_p3);
assign tmp1166_fu_23697_p2 = (r_V_173_0_10_3_fu_22644_p3 | r_V_173_0_11_3_fu_23648_p3);
assign tmp1167_fu_23703_p2 = (tmp1166_fu_23697_p2 | r_V_173_0_9_3_fu_22210_p3);
assign tmp1168_fu_23709_p2 = (tmp1167_fu_23703_p2 | tmp1165_fu_23691_p2);
assign tmp1169_fu_23728_p2 = (r_V_173_0_1_4_fu_18385_p3 | r_V_173_0_2_4_fu_18801_p3);
assign tmp116_fu_7248_p3 = {{tmp_1541_fu_7240_p3}, {tmp_288_fu_7234_p2}};
assign tmp1170_fu_23734_p2 = (tmp1169_fu_23728_p2 | bt_delta_ph_V4_fu_17985_p3);
assign tmp1171_fu_23740_p2 = (r_V_173_0_4_4_fu_19825_p3 | r_V_173_0_5_4_fu_20313_p3);
assign tmp1172_fu_23746_p2 = (tmp1171_fu_23740_p2 | r_V_173_0_3_4_fu_19211_p3);
assign tmp1173_fu_23752_p2 = (tmp1172_fu_23746_p2 | tmp1170_fu_23734_p2);
assign tmp1174_fu_23758_p2 = (r_V_173_0_7_4_fu_21157_p3 | r_V_173_0_8_4_fu_21737_p3);
assign tmp1175_fu_23764_p2 = (tmp1174_fu_23758_p2 | r_V_173_0_6_4_fu_20739_p3);
assign tmp1176_fu_23770_p2 = (r_V_173_0_10_4_fu_22651_p3 | r_V_173_0_11_4_fu_23721_p3);
assign tmp1177_fu_23776_p2 = (tmp1176_fu_23770_p2 | r_V_173_0_9_4_fu_22217_p3);
assign tmp1178_fu_23782_p2 = (tmp1177_fu_23776_p2 | tmp1175_fu_23764_p2);
assign tmp1179_fu_23801_p2 = (r_V_173_0_1_5_fu_18392_p3 | r_V_173_0_2_5_fu_18808_p3);
assign tmp117_fu_7292_p4 = {{{tmp_1543_fu_7266_p3}, {tmp_1545_fu_7284_p3}}, {tmp_290_fu_7278_p2}};
assign tmp1180_fu_23807_p2 = (tmp1179_fu_23801_p2 | bt_delta_ph_V5_fu_17992_p3);
assign tmp1181_fu_23813_p2 = (r_V_173_0_4_5_fu_19832_p3 | r_V_173_0_5_5_fu_20320_p3);
assign tmp1182_fu_23819_p2 = (tmp1181_fu_23813_p2 | r_V_173_0_3_5_fu_19218_p3);
assign tmp1183_fu_23825_p2 = (tmp1182_fu_23819_p2 | tmp1180_fu_23807_p2);
assign tmp1184_fu_23831_p2 = (r_V_173_0_7_5_fu_21164_p3 | r_V_173_0_8_5_fu_21744_p3);
assign tmp1185_fu_23837_p2 = (tmp1184_fu_23831_p2 | r_V_173_0_6_5_fu_20746_p3);
assign tmp1186_fu_23843_p2 = (r_V_173_0_10_5_fu_22658_p3 | r_V_173_0_11_5_fu_23794_p3);
assign tmp1187_fu_23849_p2 = (tmp1186_fu_23843_p2 | r_V_173_0_9_5_fu_22224_p3);
assign tmp1188_fu_23855_p2 = (tmp1187_fu_23849_p2 | tmp1185_fu_23837_p2);
assign tmp1189_fu_23874_p2 = (r_V_174_0_1_fu_18399_p3 | r_V_174_0_2_fu_18815_p3);
assign tmp118_fu_7320_p3 = {{tmp_1547_fu_7312_p3}, {tmp_291_fu_7306_p2}};
assign tmp1190_fu_23880_p2 = (tmp1189_fu_23874_p2 | bt_delta_th_V_fu_17999_p3);
assign tmp1191_fu_23886_p2 = (r_V_174_0_4_fu_19839_p3 | r_V_174_0_5_fu_20327_p3);
assign tmp1192_fu_23892_p2 = (tmp1191_fu_23886_p2 | r_V_174_0_3_fu_19225_p3);
assign tmp1193_fu_23898_p2 = (tmp1192_fu_23892_p2 | tmp1190_fu_23880_p2);
assign tmp1194_fu_23904_p2 = (r_V_174_0_7_fu_21171_p3 | r_V_174_0_8_fu_21751_p3);
assign tmp1195_fu_23910_p2 = (tmp1194_fu_23904_p2 | r_V_174_0_6_fu_20753_p3);
assign tmp1196_fu_23916_p2 = (r_V_174_0_s_fu_22665_p3 | r_V_174_0_10_fu_23867_p3);
assign tmp1197_fu_23922_p2 = (tmp1196_fu_23916_p2 | r_V_174_0_9_fu_22231_p3);
assign tmp1198_fu_23928_p2 = (tmp1197_fu_23922_p2 | tmp1195_fu_23910_p2);
assign tmp1199_fu_23947_p2 = (r_V_174_0_1_1_fu_18406_p3 | r_V_174_0_2_1_fu_18822_p3);
assign tmp119_fu_7384_p5 = {{{{tmp_1549_fu_7338_p3}, {tmp_1551_fu_7356_p3}}, {tmp_295_fu_7374_p4}}, {tmp_294_fu_7368_p2}};
assign tmp1200_fu_23953_p2 = (tmp1199_fu_23947_p2 | bt_delta_th_V1_fu_18006_p3);
assign tmp1201_fu_23959_p2 = (r_V_174_0_4_1_fu_19846_p3 | r_V_174_0_5_1_fu_20334_p3);
assign tmp1202_fu_23965_p2 = (tmp1201_fu_23959_p2 | r_V_174_0_3_1_fu_19232_p3);
assign tmp1203_fu_23971_p2 = (tmp1202_fu_23965_p2 | tmp1200_fu_23953_p2);
assign tmp1204_fu_23977_p2 = (r_V_174_0_7_1_fu_21178_p3 | r_V_174_0_8_1_fu_21758_p3);
assign tmp1205_fu_23983_p2 = (tmp1204_fu_23977_p2 | r_V_174_0_6_1_fu_20760_p3);
assign tmp1206_fu_23989_p2 = (r_V_174_0_10_1_fu_22672_p3 | r_V_174_0_11_1_fu_23940_p3);
assign tmp1207_fu_23995_p2 = (tmp1206_fu_23989_p2 | r_V_174_0_9_1_fu_22238_p3);
assign tmp1208_fu_24001_p2 = (tmp1207_fu_23995_p2 | tmp1205_fu_23983_p2);
assign tmp1209_fu_24020_p2 = (r_V_174_0_1_2_fu_18413_p3 | r_V_174_0_2_2_fu_18829_p3);
assign tmp120_fu_7414_p3 = {{tmp_1554_fu_7406_p3}, {tmp_296_fu_7400_p2}};
assign tmp1210_fu_24026_p2 = (tmp1209_fu_24020_p2 | bt_delta_th_V2_fu_18013_p3);
assign tmp1211_fu_24032_p2 = (r_V_174_0_4_2_fu_19853_p3 | r_V_174_0_5_2_fu_20341_p3);
assign tmp1212_fu_24038_p2 = (tmp1211_fu_24032_p2 | r_V_174_0_3_2_fu_19239_p3);
assign tmp1213_fu_24044_p2 = (tmp1212_fu_24038_p2 | tmp1210_fu_24026_p2);
assign tmp1214_fu_24050_p2 = (r_V_174_0_7_2_fu_21185_p3 | r_V_174_0_8_2_fu_21765_p3);
assign tmp1215_fu_24056_p2 = (tmp1214_fu_24050_p2 | r_V_174_0_6_2_fu_20767_p3);
assign tmp1216_fu_24062_p2 = (r_V_174_0_10_2_fu_22679_p3 | r_V_174_0_11_2_fu_24013_p3);
assign tmp1217_fu_24068_p2 = (tmp1216_fu_24062_p2 | r_V_174_0_9_2_fu_22245_p3);
assign tmp1218_fu_24074_p2 = (tmp1217_fu_24068_p2 | tmp1215_fu_24056_p2);
assign tmp1219_fu_24093_p2 = (r_V_174_0_1_3_fu_18420_p3 | r_V_174_0_2_3_fu_18836_p3);
assign tmp121_fu_7486_p3 = {{tmp_1559_fu_7478_p3}, {tmp_301_fu_7472_p2}};
assign tmp1220_fu_24099_p2 = (tmp1219_fu_24093_p2 | bt_delta_th_V3_fu_18020_p3);
assign tmp1221_fu_24105_p2 = (r_V_174_0_4_3_fu_19860_p3 | r_V_174_0_5_3_fu_20348_p3);
assign tmp1222_fu_24111_p2 = (tmp1221_fu_24105_p2 | r_V_174_0_3_3_fu_19246_p3);
assign tmp1223_fu_24117_p2 = (tmp1222_fu_24111_p2 | tmp1220_fu_24099_p2);
assign tmp1224_fu_24123_p2 = (r_V_174_0_7_3_fu_21192_p3 | r_V_174_0_8_3_fu_21772_p3);
assign tmp1225_fu_24129_p2 = (tmp1224_fu_24123_p2 | r_V_174_0_6_3_fu_20774_p3);
assign tmp1226_fu_24135_p2 = (r_V_174_0_10_3_fu_22686_p3 | r_V_174_0_11_3_fu_24086_p3);
assign tmp1227_fu_24141_p2 = (tmp1226_fu_24135_p2 | r_V_174_0_9_3_fu_22252_p3);
assign tmp1228_fu_24147_p2 = (tmp1227_fu_24141_p2 | tmp1225_fu_24129_p2);
assign tmp1229_fu_24166_p2 = (r_V_174_0_1_4_fu_18427_p3 | r_V_174_0_2_4_fu_18843_p3);
assign tmp122_fu_7530_p4 = {{{tmp_1561_fu_7504_p3}, {tmp_1563_fu_7522_p3}}, {tmp_303_fu_7516_p2}};
assign tmp1230_fu_24172_p2 = (tmp1229_fu_24166_p2 | bt_delta_th_V4_fu_18027_p3);
assign tmp1231_fu_24178_p2 = (r_V_174_0_4_4_fu_19867_p3 | r_V_174_0_5_4_fu_20355_p3);
assign tmp1232_fu_24184_p2 = (tmp1231_fu_24178_p2 | r_V_174_0_3_4_fu_19253_p3);
assign tmp1233_fu_24190_p2 = (tmp1232_fu_24184_p2 | tmp1230_fu_24172_p2);
assign tmp1234_fu_24196_p2 = (r_V_174_0_7_4_fu_21199_p3 | r_V_174_0_8_4_fu_21779_p3);
assign tmp1235_fu_24202_p2 = (tmp1234_fu_24196_p2 | r_V_174_0_6_4_fu_20781_p3);
assign tmp1236_fu_24208_p2 = (r_V_174_0_10_4_fu_22693_p3 | r_V_174_0_11_4_fu_24159_p3);
assign tmp1237_fu_24214_p2 = (tmp1236_fu_24208_p2 | r_V_174_0_9_4_fu_22259_p3);
assign tmp1238_fu_24220_p2 = (tmp1237_fu_24214_p2 | tmp1235_fu_24202_p2);
assign tmp1239_fu_24239_p2 = (r_V_174_0_1_5_fu_18434_p3 | r_V_174_0_2_5_fu_18850_p3);
assign tmp123_fu_7580_p4 = {{{tmp_1556_fu_7456_p3}, {tmp_308_fu_7570_p4}}, {tmp_307_fu_7564_p2}};
assign tmp1240_fu_24245_p2 = (tmp1239_fu_24239_p2 | bt_delta_th_V5_fu_18034_p3);
assign tmp1241_fu_24251_p2 = (r_V_174_0_4_5_fu_19874_p3 | r_V_174_0_5_5_fu_20362_p3);
assign tmp1242_fu_24257_p2 = (tmp1241_fu_24251_p2 | r_V_174_0_3_5_fu_19260_p3);
assign tmp1243_fu_24263_p2 = (tmp1242_fu_24257_p2 | tmp1240_fu_24245_p2);
assign tmp1244_fu_24269_p2 = (r_V_174_0_7_5_fu_21206_p3 | r_V_174_0_8_5_fu_21786_p3);
assign tmp1245_fu_24275_p2 = (tmp1244_fu_24269_p2 | r_V_174_0_6_5_fu_20788_p3);
assign tmp1246_fu_24281_p2 = (r_V_174_0_10_5_fu_22700_p3 | r_V_174_0_11_5_fu_24232_p3);
assign tmp1247_fu_24287_p2 = (tmp1246_fu_24281_p2 | r_V_174_0_9_5_fu_22266_p3);
assign tmp1248_fu_24293_p2 = (tmp1247_fu_24287_p2 | tmp1245_fu_24275_p2);
assign tmp1249_fu_24328_p2 = (r_V_169_0_1_fu_18457_p3 | r_V_169_0_2_fu_18873_p3);
assign tmp124_fu_7608_p3 = {{tmp_1565_fu_7600_p3}, {tmp_309_fu_7594_p2}};
assign tmp1250_fu_24334_p2 = (tmp1249_fu_24328_p2 | bt_rank_V_fu_18055_p3);
assign tmp1251_fu_24340_p2 = (r_V_169_0_4_fu_19897_p3 | r_V_169_0_5_fu_20385_p3);
assign tmp1252_fu_24346_p2 = (tmp1251_fu_24340_p2 | r_V_169_0_3_fu_19283_p3);
assign tmp1253_fu_24352_p2 = (tmp1252_fu_24346_p2 | tmp1250_fu_24334_p2);
assign tmp1254_fu_24358_p2 = (r_V_169_0_7_fu_21229_p3 | r_V_169_0_8_fu_21809_p3);
assign tmp1255_fu_24364_p2 = (tmp1254_fu_24358_p2 | r_V_169_0_6_fu_20811_p3);
assign tmp1256_fu_24370_p2 = (r_V_169_0_s_fu_22723_p3 | r_V_169_0_10_fu_24321_p3);
assign tmp1257_fu_24376_p2 = (tmp1256_fu_24370_p2 | r_V_169_0_9_fu_22289_p3);
assign tmp1258_fu_24382_p2 = (tmp1257_fu_24376_p2 | tmp1255_fu_24364_p2);
assign tmp1259_fu_24400_p3 = {{tmp_2265_fu_24394_p2}, {1'b0}};
assign tmp125_fu_7652_p4 = {{{tmp_1567_fu_7626_p3}, {tmp_1569_fu_7644_p3}}, {tmp_311_fu_7638_p2}};
assign tmp1260_fu_24408_p2 = (tmp1259_fu_24400_p3 | r_V_176_0_9_fu_22296_p3);
assign tmp1261_fu_24414_p3 = {{tmp_2132_fu_21272_p2}, {1'b0}};
assign tmp1262_fu_24422_p2 = (tmp1261_fu_24414_p3 | r_V_176_0_5_fu_20392_p3);
assign tmp1263_fu_24428_p2 = (tmp1262_fu_24422_p2 | tmp1260_fu_24408_p2);
assign tmp1264_fu_24440_p3 = {{tmp_2266_fu_24434_p2}, {1'b0}};
assign tmp1265_fu_24448_p2 = (tmp1264_fu_24440_p3 | r_V_176_0_1_fu_18464_p3);
assign tmp1266_fu_24460_p3 = {{tmp_2267_fu_24454_p2}, {1'b0}};
assign tmp1267_fu_24468_p2 = (tmp1266_fu_24460_p3 | r_V_176_0_4_fu_19904_p3);
assign tmp1268_fu_24474_p2 = (tmp1267_fu_24468_p2 | tmp1265_fu_24448_p2);
assign tmp126_fu_7700_p3 = {{tmp_1572_fu_7692_p3}, {tmp_314_fu_7686_p2}};
assign tmp1270_fu_24500_p3 = {{tmp_2268_fu_24486_p3}, {tmp_2269_fu_24494_p2}};
assign tmp1272_fu_24522_p3 = {{tmp_2271_fu_24514_p3}, {tmp_2270_fu_24508_p2}};
assign tmp1273_fu_24530_p2 = (tmp1272_fu_24522_p3 | tmp1270_fu_24500_p3);
assign tmp1274_fu_24544_p3 = {{tmp_2272_fu_24536_p3}, {tmp_2141_fu_21366_p3}};
assign tmp1275_fu_24552_p2 = (tmp1274_fu_24544_p3 | r_V_176_0_6_fu_20818_p3);
assign tmp1276_fu_24564_p3 = {{tmp_2273_fu_24558_p2}, {1'b0}};
assign tmp1277_fu_24572_p3 = {{tmp_2273_fu_24558_p2}, {tmp_2172_fu_21848_p3}};
assign tmp1278_fu_24580_p2 = (tmp1277_fu_24572_p3 | tmp1275_fu_24552_p2);
assign tmp127_fu_7754_p3 = {{tmp_1573_fu_7746_p3}, {tmp_319_fu_7740_p2}};
assign tmp1280_fu_24592_p3 = {{tmp_2003_fu_19390_p2}, {tmp_1901_fu_17898_p1}};
assign tmp1281_fu_24608_p3 = {{tmp_2274_fu_24600_p3}, {tmp_2006_fu_19442_p3}};
assign tmp1282_fu_24616_p2 = (tmp1281_fu_24608_p3 | r_V_176_0_3_fu_19290_p3);
assign tmp1283_fu_24622_p2 = (tmp1282_fu_24616_p2 | tmp1280_fu_24592_p3);
assign tmp1287_fu_24628_p2 = (tmp1276_fu_24564_p3 | r_V_176_0_9_fu_22296_p3);
assign tmp1288_fu_24634_p2 = (tmp1287_fu_24628_p2 | tmp1275_fu_24552_p2);
assign tmp128_fu_7780_p3 = {{tmp_1575_fu_7772_p3}, {tmp_320_fu_7766_p2}};
assign tmp1299_fu_24660_p3 = {{1'b0}, {tmp_538_fu_24654_p2}};
assign tmp129_fu_7824_p4 = {{{tmp_1577_fu_7798_p3}, {tmp_1579_fu_7816_p3}}, {tmp_322_fu_7810_p2}};
assign tmp1300_fu_24674_p3 = {{tmp_2273_fu_24558_p2}, {ap_const_lv2_0}};
assign tmp130_fu_7852_p3 = {{tmp_1581_fu_7844_p3}, {tmp_323_fu_7838_p2}};
assign tmp131_fu_7892_p3 = {{tmp_326_fu_7882_p4}, {tmp_325_fu_7876_p2}};
assign tmp132_fu_7900_p2 = (tmp131_fu_7892_p3 | tmp130_fu_7852_p3);
assign tmp133_fu_7926_p3 = {{tmp_328_fu_7916_p4}, {tmp_327_fu_7910_p2}};
assign tmp134_fu_7934_p2 = (tmp133_fu_7926_p3 | tmp127_fu_7754_p3);
assign tmp135_fu_7940_p2 = (tmp134_fu_7934_p2 | tmp123_fu_7580_p4);
assign tmp1360_fu_26193_p3 = {{tmp_2340_fu_26187_p2}, {ap_const_lv2_0}};
assign tmp1361_fu_26233_p3 = {{tmp_2344_fu_26227_p2}, {ap_const_lv2_0}};
assign tmp136_fu_8086_p2 = (tmp_1588_fu_8018_p1 ^ tmp_1587_fu_8010_p3);
assign tmp137_fu_8092_p2 = (tmp_1585_fu_7994_p3 ^ tmp_1586_fu_8002_p3);
assign tmp138_fu_8146_p2 = (lhs_i_i141_0_i_fu_8134_p2 & rhs_i_i140_0_i_fu_8140_p2);
assign tmp1392_fu_28087_p3 = {{1'b0}, {tmp_653_fu_28081_p2}};
assign tmp1393_fu_28115_p3 = {{tmp_2421_fu_28109_p2}, {ap_const_lv2_0}};
assign tmp1394_fu_28155_p3 = {{tmp_2425_fu_28149_p2}, {ap_const_lv2_0}};
assign tmp1396_fu_29835_p2 = (r_V_170_1_1_fu_25156_p3 | r_V_170_1_2_fu_25572_p3);
assign tmp1397_fu_29841_p2 = (tmp1396_fu_29835_p2 | bt_phi_V1_fu_24756_p3);
assign tmp1398_fu_29847_p2 = (r_V_170_1_4_fu_26592_p3 | r_V_170_1_5_fu_27080_p3);
assign tmp1399_fu_29853_p2 = (tmp1398_fu_29847_p2 | r_V_170_1_3_fu_25982_p3);
assign tmp139_fu_8158_p2 = (lhs_i_i135_0_i_fu_8152_p2 & rhs_i_i140_0_i_fu_8140_p2);
assign tmp1400_fu_29859_p2 = (tmp1399_fu_29853_p2 | tmp1397_fu_29841_p2);
assign tmp1401_fu_29865_p2 = (r_V_170_1_7_fu_27924_p3 | r_V_170_1_8_fu_28504_p3);
assign tmp1402_fu_29871_p2 = (tmp1401_fu_29865_p2 | r_V_170_1_6_fu_27506_p3);
assign tmp1403_fu_29877_p2 = (r_V_170_1_s_fu_29418_p3 | r_V_170_1_10_fu_29828_p3);
assign tmp1404_fu_29883_p2 = (tmp1403_fu_29877_p2 | r_V_170_1_9_fu_28984_p3);
assign tmp1405_fu_29889_p2 = (tmp1404_fu_29883_p2 | tmp1402_fu_29871_p2);
assign tmp1406_fu_29908_p2 = (r_V_171_1_1_fu_25163_p3 | r_V_171_1_2_fu_25579_p3);
assign tmp1407_fu_29914_p2 = (tmp1406_fu_29908_p2 | bt_theta_V1_fu_24763_p3);
assign tmp1408_fu_29920_p2 = (r_V_171_1_4_fu_26599_p3 | r_V_171_1_5_fu_27087_p3);
assign tmp1409_fu_29926_p2 = (tmp1408_fu_29920_p2 | r_V_171_1_3_fu_25989_p3);
assign tmp140_fu_8182_p2 = (tmp_1587_fu_8010_p3 & rhs_i138_0_i_fu_8176_p2);
assign tmp1410_fu_29932_p2 = (tmp1409_fu_29926_p2 | tmp1407_fu_29914_p2);
assign tmp1411_fu_29938_p2 = (r_V_171_1_7_fu_27931_p3 | r_V_171_1_8_fu_28511_p3);
assign tmp1412_fu_29944_p2 = (tmp1411_fu_29938_p2 | r_V_171_1_6_fu_27513_p3);
assign tmp1413_fu_29950_p2 = (r_V_171_1_s_fu_29425_p3 | r_V_171_1_10_fu_29901_p3);
assign tmp1414_fu_29956_p2 = (tmp1413_fu_29950_p2 | r_V_171_1_9_fu_28991_p3);
assign tmp1415_fu_29962_p2 = (tmp1414_fu_29956_p2 | tmp1412_fu_29944_p2);
assign tmp1416_fu_29981_p2 = (r_V_172_1_1_fu_25170_p3 | r_V_172_1_2_fu_25586_p3);
assign tmp1417_fu_29987_p2 = (tmp1416_fu_29981_p2 | bt_cpattern_V4_fu_24770_p3);
assign tmp1418_fu_29993_p2 = (r_V_172_1_4_fu_26606_p3 | r_V_172_1_5_fu_27094_p3);
assign tmp1419_fu_29999_p2 = (tmp1418_fu_29993_p2 | r_V_172_1_3_fu_25996_p3);
assign tmp141_fu_8188_p2 = (tmp140_fu_8182_p2 | lhs_i143_0_i_fu_8116_p2);
assign tmp1420_fu_30005_p2 = (tmp1419_fu_29999_p2 | tmp1417_fu_29987_p2);
assign tmp1421_fu_30011_p2 = (r_V_172_1_7_fu_27938_p3 | r_V_172_1_8_fu_28518_p3);
assign tmp1422_fu_30017_p2 = (tmp1421_fu_30011_p2 | r_V_172_1_6_fu_27520_p3);
assign tmp1423_fu_30023_p2 = (r_V_172_1_s_fu_29432_p3 | r_V_172_1_10_fu_29974_p3);
assign tmp1424_fu_30029_p2 = (tmp1423_fu_30023_p2 | r_V_172_1_9_fu_28998_p3);
assign tmp1425_fu_30035_p2 = (tmp1424_fu_30029_p2 | tmp1422_fu_30017_p2);
assign tmp1426_fu_30054_p2 = (r_V_172_1_1_1_fu_25177_p3 | r_V_172_1_2_1_fu_25593_p3);
assign tmp1427_fu_30060_p2 = (tmp1426_fu_30054_p2 | bt_cpattern_V5_fu_24777_p3);
assign tmp1428_fu_30066_p2 = (r_V_172_1_4_1_fu_26613_p3 | r_V_172_1_5_1_fu_27101_p3);
assign tmp1429_fu_30072_p2 = (tmp1428_fu_30066_p2 | r_V_172_1_3_1_fu_26003_p3);
assign tmp142_fu_8194_p2 = (rhs_i_i140_0_i_fu_8140_p2 | lhs_i_i135_0_i_fu_8152_p2);
assign tmp1430_fu_30078_p2 = (tmp1429_fu_30072_p2 | tmp1427_fu_30060_p2);
assign tmp1431_fu_30084_p2 = (r_V_172_1_7_1_fu_27945_p3 | r_V_172_1_8_1_fu_28525_p3);
assign tmp1432_fu_30090_p2 = (tmp1431_fu_30084_p2 | r_V_172_1_6_1_fu_27527_p3);
assign tmp1433_fu_30096_p2 = (r_V_172_1_10_1_fu_29439_p3 | r_V_172_1_11_1_fu_30047_p3);
assign tmp1434_fu_30102_p2 = (tmp1433_fu_30096_p2 | r_V_172_1_9_1_fu_29005_p3);
assign tmp1435_fu_30108_p2 = (tmp1434_fu_30102_p2 | tmp1432_fu_30090_p2);
assign tmp1436_fu_30127_p2 = (r_V_172_1_1_2_fu_25184_p3 | r_V_172_1_2_2_fu_25600_p3);
assign tmp1437_fu_30133_p2 = (tmp1436_fu_30127_p2 | bt_cpattern_V6_fu_24784_p3);
assign tmp1438_fu_30139_p2 = (r_V_172_1_4_2_fu_26620_p3 | r_V_172_1_5_2_fu_27108_p3);
assign tmp1439_fu_30145_p2 = (tmp1438_fu_30139_p2 | r_V_172_1_3_2_fu_26010_p3);
assign tmp143_fu_8206_p2 = (rhs_i126_0_i_fu_8200_p2 & tmp_1585_fu_7994_p3);
assign tmp1440_fu_30151_p2 = (tmp1439_fu_30145_p2 | tmp1437_fu_30133_p2);
assign tmp1441_fu_30157_p2 = (r_V_172_1_7_2_fu_27952_p3 | r_V_172_1_8_2_fu_28532_p3);
assign tmp1442_fu_30163_p2 = (tmp1441_fu_30157_p2 | r_V_172_1_6_2_fu_27534_p3);
assign tmp1443_fu_30169_p2 = (r_V_172_1_10_2_fu_29446_p3 | r_V_172_1_11_2_fu_30120_p3);
assign tmp1444_fu_30175_p2 = (tmp1443_fu_30169_p2 | r_V_172_1_9_2_fu_29012_p3);
assign tmp1445_fu_30181_p2 = (tmp1444_fu_30175_p2 | tmp1442_fu_30163_p2);
assign tmp1446_fu_30200_p2 = (r_V_172_1_1_3_fu_25191_p3 | r_V_172_1_2_3_fu_25607_p3);
assign tmp1447_fu_30206_p2 = (tmp1446_fu_30200_p2 | bt_cpattern_V7_fu_24791_p3);
assign tmp1448_fu_30212_p2 = (r_V_172_1_4_3_fu_26627_p3 | r_V_172_1_5_3_fu_27115_p3);
assign tmp1449_fu_30218_p2 = (tmp1448_fu_30212_p2 | r_V_172_1_3_3_fu_26017_p3);
assign tmp144_fu_8212_p2 = (tmp143_fu_8206_p2 | rhs_i132_0_i_fu_8164_p2);
assign tmp1450_fu_30224_p2 = (tmp1449_fu_30218_p2 | tmp1447_fu_30206_p2);
assign tmp1451_fu_30230_p2 = (r_V_172_1_7_3_fu_27959_p3 | r_V_172_1_8_3_fu_28539_p3);
assign tmp1452_fu_30236_p2 = (tmp1451_fu_30230_p2 | r_V_172_1_6_3_fu_27541_p3);
assign tmp1453_fu_30242_p2 = (r_V_172_1_10_3_fu_29453_p3 | r_V_172_1_11_3_fu_30193_p3);
assign tmp1454_fu_30248_p2 = (tmp1453_fu_30242_p2 | r_V_172_1_9_3_fu_29019_p3);
assign tmp1455_fu_30254_p2 = (tmp1454_fu_30248_p2 | tmp1452_fu_30236_p2);
assign tmp1456_fu_30273_p2 = (r_V_173_1_1_fu_25198_p3 | r_V_173_1_2_fu_25614_p3);
assign tmp1457_fu_30279_p2 = (tmp1456_fu_30273_p2 | bt_delta_ph_V6_fu_24798_p3);
assign tmp1458_fu_30285_p2 = (r_V_173_1_4_fu_26634_p3 | r_V_173_1_5_fu_27122_p3);
assign tmp1459_fu_30291_p2 = (tmp1458_fu_30285_p2 | r_V_173_1_3_fu_26024_p3);
assign tmp145_fu_8224_p2 = (tmp_1587_fu_8010_p3 | tmp_1588_fu_8018_p1);
assign tmp1460_fu_30297_p2 = (tmp1459_fu_30291_p2 | tmp1457_fu_30279_p2);
assign tmp1461_fu_30303_p2 = (r_V_173_1_7_fu_27966_p3 | r_V_173_1_8_fu_28546_p3);
assign tmp1462_fu_30309_p2 = (tmp1461_fu_30303_p2 | r_V_173_1_6_fu_27548_p3);
assign tmp1463_fu_30315_p2 = (r_V_173_1_s_fu_29460_p3 | r_V_173_1_10_fu_30266_p3);
assign tmp1464_fu_30321_p2 = (tmp1463_fu_30315_p2 | r_V_173_1_9_fu_29026_p3);
assign tmp1465_fu_30327_p2 = (tmp1464_fu_30321_p2 | tmp1462_fu_30309_p2);
assign tmp1466_fu_30346_p2 = (r_V_173_1_1_1_fu_25205_p3 | r_V_173_1_2_1_fu_25621_p3);
assign tmp1467_fu_30352_p2 = (tmp1466_fu_30346_p2 | bt_delta_ph_V7_fu_24805_p3);
assign tmp1468_fu_30358_p2 = (r_V_173_1_4_1_fu_26641_p3 | r_V_173_1_5_1_fu_27129_p3);
assign tmp1469_fu_30364_p2 = (tmp1468_fu_30358_p2 | r_V_173_1_3_1_fu_26031_p3);
assign tmp146_fu_8242_p2 = (tmp_1592_fu_8046_p3 ^ tmp_1591_fu_8038_p3);
assign tmp1470_fu_30370_p2 = (tmp1469_fu_30364_p2 | tmp1467_fu_30352_p2);
assign tmp1471_fu_30376_p2 = (r_V_173_1_7_1_fu_27973_p3 | r_V_173_1_8_1_fu_28553_p3);
assign tmp1472_fu_30382_p2 = (tmp1471_fu_30376_p2 | r_V_173_1_6_1_fu_27555_p3);
assign tmp1473_fu_30388_p2 = (r_V_173_1_10_1_fu_29467_p3 | r_V_173_1_11_1_fu_30339_p3);
assign tmp1474_fu_30394_p2 = (tmp1473_fu_30388_p2 | r_V_173_1_9_1_fu_29033_p3);
assign tmp1475_fu_30400_p2 = (tmp1474_fu_30394_p2 | tmp1472_fu_30382_p2);
assign tmp1476_fu_30419_p2 = (r_V_173_1_1_2_fu_25212_p3 | r_V_173_1_2_2_fu_25628_p3);
assign tmp1477_fu_30425_p2 = (tmp1476_fu_30419_p2 | bt_delta_ph_V8_fu_24812_p3);
assign tmp1478_fu_30431_p2 = (r_V_173_1_4_2_fu_26648_p3 | r_V_173_1_5_2_fu_27136_p3);
assign tmp1479_fu_30437_p2 = (tmp1478_fu_30431_p2 | r_V_173_1_3_2_fu_26038_p3);
assign tmp147_fu_8248_p2 = (tmp_1589_fu_8022_p3 ^ tmp_1590_fu_8030_p3);
assign tmp1480_fu_30443_p2 = (tmp1479_fu_30437_p2 | tmp1477_fu_30425_p2);
assign tmp1481_fu_30449_p2 = (r_V_173_1_7_2_fu_27980_p3 | r_V_173_1_8_2_fu_28560_p3);
assign tmp1482_fu_30455_p2 = (tmp1481_fu_30449_p2 | r_V_173_1_6_2_fu_27562_p3);
assign tmp1483_fu_30461_p2 = (r_V_173_1_10_2_fu_29474_p3 | r_V_173_1_11_2_fu_30412_p3);
assign tmp1484_fu_30467_p2 = (tmp1483_fu_30461_p2 | r_V_173_1_9_2_fu_29040_p3);
assign tmp1485_fu_30473_p2 = (tmp1484_fu_30467_p2 | tmp1482_fu_30455_p2);
assign tmp1486_fu_30492_p2 = (r_V_173_1_1_3_fu_25219_p3 | r_V_173_1_2_3_fu_25635_p3);
assign tmp1487_fu_30498_p2 = (tmp1486_fu_30492_p2 | bt_delta_ph_V9_fu_24819_p3);
assign tmp1488_fu_30504_p2 = (r_V_173_1_4_3_fu_26655_p3 | r_V_173_1_5_3_fu_27143_p3);
assign tmp1489_fu_30510_p2 = (tmp1488_fu_30504_p2 | r_V_173_1_3_3_fu_26045_p3);
assign tmp148_fu_8302_p2 = (lhs_i_i97_0_i_fu_8290_p2 & rhs_i_i96_0_i_fu_8296_p2);
assign tmp1490_fu_30516_p2 = (tmp1489_fu_30510_p2 | tmp1487_fu_30498_p2);
assign tmp1491_fu_30522_p2 = (r_V_173_1_7_3_fu_27987_p3 | r_V_173_1_8_3_fu_28567_p3);
assign tmp1492_fu_30528_p2 = (tmp1491_fu_30522_p2 | r_V_173_1_6_3_fu_27569_p3);
assign tmp1493_fu_30534_p2 = (r_V_173_1_10_3_fu_29481_p3 | r_V_173_1_11_3_fu_30485_p3);
assign tmp1494_fu_30540_p2 = (tmp1493_fu_30534_p2 | r_V_173_1_9_3_fu_29047_p3);
assign tmp1495_fu_30546_p2 = (tmp1494_fu_30540_p2 | tmp1492_fu_30528_p2);
assign tmp1496_fu_30565_p2 = (r_V_173_1_1_4_fu_25226_p3 | r_V_173_1_2_4_fu_25642_p3);
assign tmp1497_fu_30571_p2 = (tmp1496_fu_30565_p2 | bt_delta_ph_V10_fu_24826_p3);
assign tmp1498_fu_30577_p2 = (r_V_173_1_4_4_fu_26662_p3 | r_V_173_1_5_4_fu_27150_p3);
assign tmp1499_fu_30583_p2 = (tmp1498_fu_30577_p2 | r_V_173_1_3_4_fu_26052_p3);
assign tmp149_fu_8314_p2 = (lhs_i_i91_0_i_fu_8308_p2 & rhs_i_i96_0_i_fu_8296_p2);
assign tmp1500_fu_30589_p2 = (tmp1499_fu_30583_p2 | tmp1497_fu_30571_p2);
assign tmp1501_fu_30595_p2 = (r_V_173_1_7_4_fu_27994_p3 | r_V_173_1_8_4_fu_28574_p3);
assign tmp1502_fu_30601_p2 = (tmp1501_fu_30595_p2 | r_V_173_1_6_4_fu_27576_p3);
assign tmp1503_fu_30607_p2 = (r_V_173_1_10_4_fu_29488_p3 | r_V_173_1_11_4_fu_30558_p3);
assign tmp1504_fu_30613_p2 = (tmp1503_fu_30607_p2 | r_V_173_1_9_4_fu_29054_p3);
assign tmp1505_fu_30619_p2 = (tmp1504_fu_30613_p2 | tmp1502_fu_30601_p2);
assign tmp1506_fu_30638_p2 = (r_V_173_1_1_5_fu_25233_p3 | r_V_173_1_2_5_fu_25649_p3);
assign tmp1507_fu_30644_p2 = (tmp1506_fu_30638_p2 | bt_delta_ph_V11_fu_24833_p3);
assign tmp1508_fu_30650_p2 = (r_V_173_1_4_5_fu_26669_p3 | r_V_173_1_5_5_fu_27157_p3);
assign tmp1509_fu_30656_p2 = (tmp1508_fu_30650_p2 | r_V_173_1_3_5_fu_26059_p3);
assign tmp150_fu_8338_p2 = (tmp_1591_fu_8038_p3 & rhs_i94_0_i_fu_8332_p2);
assign tmp1510_fu_30662_p2 = (tmp1509_fu_30656_p2 | tmp1507_fu_30644_p2);
assign tmp1511_fu_30668_p2 = (r_V_173_1_7_5_fu_28001_p3 | r_V_173_1_8_5_fu_28581_p3);
assign tmp1512_fu_30674_p2 = (tmp1511_fu_30668_p2 | r_V_173_1_6_5_fu_27583_p3);
assign tmp1513_fu_30680_p2 = (r_V_173_1_10_5_fu_29495_p3 | r_V_173_1_11_5_fu_30631_p3);
assign tmp1514_fu_30686_p2 = (tmp1513_fu_30680_p2 | r_V_173_1_9_5_fu_29061_p3);
assign tmp1515_fu_30692_p2 = (tmp1514_fu_30686_p2 | tmp1512_fu_30674_p2);
assign tmp1516_fu_30711_p2 = (r_V_174_1_1_fu_25240_p3 | r_V_174_1_2_fu_25656_p3);
assign tmp1517_fu_30717_p2 = (tmp1516_fu_30711_p2 | bt_delta_th_V6_fu_24840_p3);
assign tmp1518_fu_30723_p2 = (r_V_174_1_4_fu_26676_p3 | r_V_174_1_5_fu_27164_p3);
assign tmp1519_fu_30729_p2 = (tmp1518_fu_30723_p2 | r_V_174_1_3_fu_26066_p3);
assign tmp151_fu_8344_p2 = (tmp150_fu_8338_p2 | lhs_i99_0_i_fu_8272_p2);
assign tmp1520_fu_30735_p2 = (tmp1519_fu_30729_p2 | tmp1517_fu_30717_p2);
assign tmp1521_fu_30741_p2 = (r_V_174_1_7_fu_28008_p3 | r_V_174_1_8_fu_28588_p3);
assign tmp1522_fu_30747_p2 = (tmp1521_fu_30741_p2 | r_V_174_1_6_fu_27590_p3);
assign tmp1523_fu_30753_p2 = (r_V_174_1_s_fu_29502_p3 | r_V_174_1_10_fu_30704_p3);
assign tmp1524_fu_30759_p2 = (tmp1523_fu_30753_p2 | r_V_174_1_9_fu_29068_p3);
assign tmp1525_fu_30765_p2 = (tmp1524_fu_30759_p2 | tmp1522_fu_30747_p2);
assign tmp1526_fu_30784_p2 = (r_V_174_1_1_1_fu_25247_p3 | r_V_174_1_2_1_fu_25663_p3);
assign tmp1527_fu_30790_p2 = (tmp1526_fu_30784_p2 | bt_delta_th_V7_fu_24847_p3);
assign tmp1528_fu_30796_p2 = (r_V_174_1_4_1_fu_26683_p3 | r_V_174_1_5_1_fu_27171_p3);
assign tmp1529_fu_30802_p2 = (tmp1528_fu_30796_p2 | r_V_174_1_3_1_fu_26073_p3);
assign tmp152_fu_8350_p2 = (rhs_i_i96_0_i_fu_8296_p2 | lhs_i_i91_0_i_fu_8308_p2);
assign tmp1530_fu_30808_p2 = (tmp1529_fu_30802_p2 | tmp1527_fu_30790_p2);
assign tmp1531_fu_30814_p2 = (r_V_174_1_7_1_fu_28015_p3 | r_V_174_1_8_1_fu_28595_p3);
assign tmp1532_fu_30820_p2 = (tmp1531_fu_30814_p2 | r_V_174_1_6_1_fu_27597_p3);
assign tmp1533_fu_30826_p2 = (r_V_174_1_10_1_fu_29509_p3 | r_V_174_1_11_1_fu_30777_p3);
assign tmp1534_fu_30832_p2 = (tmp1533_fu_30826_p2 | r_V_174_1_9_1_fu_29075_p3);
assign tmp1535_fu_30838_p2 = (tmp1534_fu_30832_p2 | tmp1532_fu_30820_p2);
assign tmp1536_fu_30857_p2 = (r_V_174_1_1_2_fu_25254_p3 | r_V_174_1_2_2_fu_25670_p3);
assign tmp1537_fu_30863_p2 = (tmp1536_fu_30857_p2 | bt_delta_th_V8_fu_24854_p3);
assign tmp1538_fu_30869_p2 = (r_V_174_1_4_2_fu_26690_p3 | r_V_174_1_5_2_fu_27178_p3);
assign tmp1539_fu_30875_p2 = (tmp1538_fu_30869_p2 | r_V_174_1_3_2_fu_26080_p3);
assign tmp153_fu_8362_p2 = (rhs_i82_0_i_fu_8356_p2 & tmp_1589_fu_8022_p3);
assign tmp1540_fu_30881_p2 = (tmp1539_fu_30875_p2 | tmp1537_fu_30863_p2);
assign tmp1541_fu_30887_p2 = (r_V_174_1_7_2_fu_28022_p3 | r_V_174_1_8_2_fu_28602_p3);
assign tmp1542_fu_30893_p2 = (tmp1541_fu_30887_p2 | r_V_174_1_6_2_fu_27604_p3);
assign tmp1543_fu_30899_p2 = (r_V_174_1_10_2_fu_29516_p3 | r_V_174_1_11_2_fu_30850_p3);
assign tmp1544_fu_30905_p2 = (tmp1543_fu_30899_p2 | r_V_174_1_9_2_fu_29082_p3);
assign tmp1545_fu_30911_p2 = (tmp1544_fu_30905_p2 | tmp1542_fu_30893_p2);
assign tmp1546_fu_30930_p2 = (r_V_174_1_1_3_fu_25261_p3 | r_V_174_1_2_3_fu_25677_p3);
assign tmp1547_fu_30936_p2 = (tmp1546_fu_30930_p2 | bt_delta_th_V9_fu_24861_p3);
assign tmp1548_fu_30942_p2 = (r_V_174_1_4_3_fu_26697_p3 | r_V_174_1_5_3_fu_27185_p3);
assign tmp1549_fu_30948_p2 = (tmp1548_fu_30942_p2 | r_V_174_1_3_3_fu_26087_p3);
assign tmp154_fu_8368_p2 = (tmp153_fu_8362_p2 | rhs_i88_0_i_fu_8320_p2);
assign tmp1550_fu_30954_p2 = (tmp1549_fu_30948_p2 | tmp1547_fu_30936_p2);
assign tmp1551_fu_30960_p2 = (r_V_174_1_7_3_fu_28029_p3 | r_V_174_1_8_3_fu_28609_p3);
assign tmp1552_fu_30966_p2 = (tmp1551_fu_30960_p2 | r_V_174_1_6_3_fu_27611_p3);
assign tmp1553_fu_30972_p2 = (r_V_174_1_10_3_fu_29523_p3 | r_V_174_1_11_3_fu_30923_p3);
assign tmp1554_fu_30978_p2 = (tmp1553_fu_30972_p2 | r_V_174_1_9_3_fu_29089_p3);
assign tmp1555_fu_30984_p2 = (tmp1554_fu_30978_p2 | tmp1552_fu_30966_p2);
assign tmp1556_fu_31003_p2 = (r_V_174_1_1_4_fu_25268_p3 | r_V_174_1_2_4_fu_25684_p3);
assign tmp1557_fu_31009_p2 = (tmp1556_fu_31003_p2 | bt_delta_th_V10_fu_24868_p3);
assign tmp1558_fu_31015_p2 = (r_V_174_1_4_4_fu_26704_p3 | r_V_174_1_5_4_fu_27192_p3);
assign tmp1559_fu_31021_p2 = (tmp1558_fu_31015_p2 | r_V_174_1_3_4_fu_26094_p3);
assign tmp155_fu_8380_p2 = (tmp_1591_fu_8038_p3 | tmp_1592_fu_8046_p3);
assign tmp1560_fu_31027_p2 = (tmp1559_fu_31021_p2 | tmp1557_fu_31009_p2);
assign tmp1561_fu_31033_p2 = (r_V_174_1_7_4_fu_28036_p3 | r_V_174_1_8_4_fu_28616_p3);
assign tmp1562_fu_31039_p2 = (tmp1561_fu_31033_p2 | r_V_174_1_6_4_fu_27618_p3);
assign tmp1563_fu_31045_p2 = (r_V_174_1_10_4_fu_29530_p3 | r_V_174_1_11_4_fu_30996_p3);
assign tmp1564_fu_31051_p2 = (tmp1563_fu_31045_p2 | r_V_174_1_9_4_fu_29096_p3);
assign tmp1565_fu_31057_p2 = (tmp1564_fu_31051_p2 | tmp1562_fu_31039_p2);
assign tmp1566_fu_31076_p2 = (r_V_174_1_1_5_fu_25275_p3 | r_V_174_1_2_5_fu_25691_p3);
assign tmp1567_fu_31082_p2 = (tmp1566_fu_31076_p2 | bt_delta_th_V11_fu_24875_p3);
assign tmp1568_fu_31088_p2 = (r_V_174_1_4_5_fu_26711_p3 | r_V_174_1_5_5_fu_27199_p3);
assign tmp1569_fu_31094_p2 = (tmp1568_fu_31088_p2 | r_V_174_1_3_5_fu_26101_p3);
assign tmp156_fu_8398_p2 = (tmp_1596_fu_8078_p3 ^ tmp_1595_fu_8070_p3);
assign tmp1570_fu_31100_p2 = (tmp1569_fu_31094_p2 | tmp1567_fu_31082_p2);
assign tmp1571_fu_31106_p2 = (r_V_174_1_7_5_fu_28043_p3 | r_V_174_1_8_5_fu_28623_p3);
assign tmp1572_fu_31112_p2 = (tmp1571_fu_31106_p2 | r_V_174_1_6_5_fu_27625_p3);
assign tmp1573_fu_31118_p2 = (r_V_174_1_10_5_fu_29537_p3 | r_V_174_1_11_5_fu_31069_p3);
assign tmp1574_fu_31124_p2 = (tmp1573_fu_31118_p2 | r_V_174_1_9_5_fu_29103_p3);
assign tmp1575_fu_31130_p2 = (tmp1574_fu_31124_p2 | tmp1572_fu_31112_p2);
assign tmp1576_fu_31165_p2 = (r_V_169_1_1_fu_25298_p3 | r_V_169_1_2_fu_25714_p3);
assign tmp1577_fu_31171_p2 = (tmp1576_fu_31165_p2 | bt_rank_V1_fu_24896_p3);
assign tmp1578_fu_31177_p2 = (r_V_169_1_4_fu_26734_p3 | r_V_169_1_5_fu_27222_p3);
assign tmp1579_fu_31183_p2 = (tmp1578_fu_31177_p2 | r_V_169_1_3_fu_26124_p3);
assign tmp157_fu_8404_p2 = (tmp_1593_fu_8054_p3 ^ tmp_1594_fu_8062_p3);
assign tmp1580_fu_31189_p2 = (tmp1579_fu_31183_p2 | tmp1577_fu_31171_p2);
assign tmp1581_fu_31195_p2 = (r_V_169_1_7_fu_28066_p3 | r_V_169_1_8_fu_28646_p3);
assign tmp1582_fu_31201_p2 = (tmp1581_fu_31195_p2 | r_V_169_1_6_fu_27648_p3);
assign tmp1583_fu_31207_p2 = (r_V_169_1_s_fu_29560_p3 | r_V_169_1_10_fu_31158_p3);
assign tmp1584_fu_31213_p2 = (tmp1583_fu_31207_p2 | r_V_169_1_9_fu_29126_p3);
assign tmp1585_fu_31219_p2 = (tmp1584_fu_31213_p2 | tmp1582_fu_31201_p2);
assign tmp1586_fu_31237_p3 = {{tmp_2502_fu_31231_p2}, {1'b0}};
assign tmp1587_fu_31245_p2 = (tmp1586_fu_31237_p3 | r_V_176_1_9_fu_29133_p3);
assign tmp1588_fu_31251_p3 = {{tmp_2421_fu_28109_p2}, {1'b0}};
assign tmp1589_fu_31259_p2 = (tmp1588_fu_31251_p3 | r_V_176_1_5_fu_27229_p3);
assign tmp158_fu_8458_p2 = (lhs_i_i53_0_i_fu_8446_p2 & rhs_i_i52_0_i_fu_8452_p2);
assign tmp1590_fu_31265_p2 = (tmp1589_fu_31259_p2 | tmp1587_fu_31245_p2);
assign tmp1591_fu_31277_p3 = {{tmp_2503_fu_31271_p2}, {1'b0}};
assign tmp1592_fu_31285_p2 = (tmp1591_fu_31277_p3 | r_V_176_1_1_fu_25305_p3);
assign tmp1593_fu_31297_p3 = {{tmp_2504_fu_31291_p2}, {1'b0}};
assign tmp1594_fu_31305_p2 = (tmp1593_fu_31297_p3 | r_V_176_1_4_fu_26741_p3);
assign tmp1595_fu_31311_p2 = (tmp1594_fu_31305_p2 | tmp1592_fu_31285_p2);
assign tmp1597_fu_31337_p3 = {{tmp_2505_fu_31323_p3}, {tmp_2506_fu_31331_p2}};
assign tmp1599_fu_31359_p3 = {{tmp_2508_fu_31351_p3}, {tmp_2507_fu_31345_p2}};
assign tmp159_fu_8470_p2 = (lhs_i_i47_0_i_fu_8464_p2 & rhs_i_i52_0_i_fu_8452_p2);
assign tmp1600_fu_31367_p2 = (tmp1599_fu_31359_p3 | tmp1597_fu_31337_p3);
assign tmp1601_fu_31381_p3 = {{tmp_2509_fu_31373_p3}, {tmp_2430_fu_28203_p3}};
assign tmp1602_fu_31389_p2 = (tmp1601_fu_31381_p3 | r_V_176_1_6_fu_27655_p3);
assign tmp1603_fu_31401_p3 = {{tmp_2510_fu_31395_p2}, {1'b0}};
assign tmp1604_fu_31409_p3 = {{tmp_2510_fu_31395_p2}, {tmp_2448_fu_28685_p3}};
assign tmp1605_fu_31417_p2 = (tmp1604_fu_31409_p3 | tmp1602_fu_31389_p2);
assign tmp1607_fu_31429_p3 = {{tmp_2344_fu_26227_p2}, {tmp_2283_fu_24748_p3}};
assign tmp1608_fu_31445_p3 = {{tmp_2511_fu_31437_p3}, {tmp_2347_fu_26279_p3}};
assign tmp1609_fu_31453_p2 = (tmp1608_fu_31445_p3 | r_V_176_1_3_fu_26131_p3);
assign tmp160_fu_8494_p2 = (tmp_1595_fu_8070_p3 & rhs_i50_0_i1_fu_8488_p2);
assign tmp1610_fu_31459_p2 = (tmp1609_fu_31453_p2 | tmp1607_fu_31429_p3);
assign tmp1614_fu_31465_p2 = (tmp1603_fu_31401_p3 | r_V_176_1_9_fu_29133_p3);
assign tmp1615_fu_31471_p2 = (tmp1614_fu_31465_p2 | tmp1602_fu_31389_p2);
assign tmp1616_fu_31497_p3 = {{1'b0}, {tmp_721_fu_31491_p2}};
assign tmp1617_fu_31511_p3 = {{tmp_2510_fu_31395_p2}, {ap_const_lv2_0}};
assign tmp161_fu_8500_p2 = (tmp160_fu_8494_p2 | lhs_i55_0_i_fu_8428_p2);
assign tmp1621_fu_33030_p3 = {{tmp_2577_fu_33024_p2}, {ap_const_lv2_0}};
assign tmp1622_fu_33070_p3 = {{tmp_2581_fu_33064_p2}, {ap_const_lv2_0}};
assign tmp1624_fu_34924_p3 = {{1'b0}, {tmp_836_fu_34918_p2}};
assign tmp1625_fu_34952_p3 = {{tmp_2658_fu_34946_p2}, {ap_const_lv2_0}};
assign tmp1626_fu_34992_p3 = {{tmp_2662_fu_34986_p2}, {ap_const_lv2_0}};
assign tmp1628_fu_36672_p2 = (r_V_170_2_1_fu_31993_p3 | r_V_170_2_2_fu_32409_p3);
assign tmp1629_fu_36678_p2 = (tmp1628_fu_36672_p2 | bt_phi_V2_fu_31593_p3);
assign tmp162_fu_8506_p2 = (rhs_i_i52_0_i_fu_8452_p2 | lhs_i_i47_0_i_fu_8464_p2);
assign tmp1630_fu_36684_p2 = (r_V_170_2_4_fu_33429_p3 | r_V_170_2_5_fu_33917_p3);
assign tmp1631_fu_36690_p2 = (tmp1630_fu_36684_p2 | r_V_170_2_3_fu_32819_p3);
assign tmp1632_fu_36696_p2 = (tmp1631_fu_36690_p2 | tmp1629_fu_36678_p2);
assign tmp1633_fu_36702_p2 = (r_V_170_2_7_fu_34761_p3 | r_V_170_2_8_fu_35341_p3);
assign tmp1634_fu_36708_p2 = (tmp1633_fu_36702_p2 | r_V_170_2_6_fu_34343_p3);
assign tmp1635_fu_36714_p2 = (r_V_170_2_s_fu_36255_p3 | r_V_170_2_10_fu_36665_p3);
assign tmp1636_fu_36720_p2 = (tmp1635_fu_36714_p2 | r_V_170_2_9_fu_35821_p3);
assign tmp1637_fu_36726_p2 = (tmp1636_fu_36720_p2 | tmp1634_fu_36708_p2);
assign tmp1638_fu_36745_p2 = (r_V_171_2_1_fu_32000_p3 | r_V_171_2_2_fu_32416_p3);
assign tmp1639_fu_36751_p2 = (tmp1638_fu_36745_p2 | bt_theta_V2_fu_31600_p3);
assign tmp163_fu_8518_p2 = (rhs_i38_0_i_fu_8512_p2 & tmp_1593_fu_8054_p3);
assign tmp1640_fu_36757_p2 = (r_V_171_2_4_fu_33436_p3 | r_V_171_2_5_fu_33924_p3);
assign tmp1641_fu_36763_p2 = (tmp1640_fu_36757_p2 | r_V_171_2_3_fu_32826_p3);
assign tmp1642_fu_36769_p2 = (tmp1641_fu_36763_p2 | tmp1639_fu_36751_p2);
assign tmp1643_fu_36775_p2 = (r_V_171_2_7_fu_34768_p3 | r_V_171_2_8_fu_35348_p3);
assign tmp1644_fu_36781_p2 = (tmp1643_fu_36775_p2 | r_V_171_2_6_fu_34350_p3);
assign tmp1645_fu_36787_p2 = (r_V_171_2_s_fu_36262_p3 | r_V_171_2_10_fu_36738_p3);
assign tmp1646_fu_36793_p2 = (tmp1645_fu_36787_p2 | r_V_171_2_9_fu_35828_p3);
assign tmp1647_fu_36799_p2 = (tmp1646_fu_36793_p2 | tmp1644_fu_36781_p2);
assign tmp1648_fu_36818_p2 = (r_V_172_2_1_fu_32007_p3 | r_V_172_2_2_fu_32423_p3);
assign tmp1649_fu_36824_p2 = (tmp1648_fu_36818_p2 | bt_cpattern_V8_fu_31607_p3);
assign tmp164_fu_8524_p2 = (tmp163_fu_8518_p2 | rhs_i44_0_i_fu_8476_p2);
assign tmp1650_fu_36830_p2 = (r_V_172_2_4_fu_33443_p3 | r_V_172_2_5_fu_33931_p3);
assign tmp1651_fu_36836_p2 = (tmp1650_fu_36830_p2 | r_V_172_2_3_fu_32833_p3);
assign tmp1652_fu_36842_p2 = (tmp1651_fu_36836_p2 | tmp1649_fu_36824_p2);
assign tmp1653_fu_36848_p2 = (r_V_172_2_7_fu_34775_p3 | r_V_172_2_8_fu_35355_p3);
assign tmp1654_fu_36854_p2 = (tmp1653_fu_36848_p2 | r_V_172_2_6_fu_34357_p3);
assign tmp1655_fu_36860_p2 = (r_V_172_2_s_fu_36269_p3 | r_V_172_2_10_fu_36811_p3);
assign tmp1656_fu_36866_p2 = (tmp1655_fu_36860_p2 | r_V_172_2_9_fu_35835_p3);
assign tmp1657_fu_36872_p2 = (tmp1656_fu_36866_p2 | tmp1654_fu_36854_p2);
assign tmp1658_fu_36891_p2 = (r_V_172_2_1_1_fu_32014_p3 | r_V_172_2_2_1_fu_32430_p3);
assign tmp1659_fu_36897_p2 = (tmp1658_fu_36891_p2 | bt_cpattern_V9_fu_31614_p3);
assign tmp165_fu_8536_p2 = (tmp_1595_fu_8070_p3 | tmp_1596_fu_8078_p3);
assign tmp1660_fu_36903_p2 = (r_V_172_2_4_1_fu_33450_p3 | r_V_172_2_5_1_fu_33938_p3);
assign tmp1661_fu_36909_p2 = (tmp1660_fu_36903_p2 | r_V_172_2_3_1_fu_32840_p3);
assign tmp1662_fu_36915_p2 = (tmp1661_fu_36909_p2 | tmp1659_fu_36897_p2);
assign tmp1663_fu_36921_p2 = (r_V_172_2_7_1_fu_34782_p3 | r_V_172_2_8_1_fu_35362_p3);
assign tmp1664_fu_36927_p2 = (tmp1663_fu_36921_p2 | r_V_172_2_6_1_fu_34364_p3);
assign tmp1665_fu_36933_p2 = (r_V_172_2_10_1_fu_36276_p3 | r_V_172_2_11_1_fu_36884_p3);
assign tmp1666_fu_36939_p2 = (tmp1665_fu_36933_p2 | r_V_172_2_9_1_fu_35842_p3);
assign tmp1667_fu_36945_p2 = (tmp1666_fu_36939_p2 | tmp1664_fu_36927_p2);
assign tmp1668_fu_36964_p2 = (r_V_172_2_1_2_fu_32021_p3 | r_V_172_2_2_2_fu_32437_p3);
assign tmp1669_fu_36970_p2 = (tmp1668_fu_36964_p2 | bt_cpattern_V10_fu_31621_p3);
assign tmp166_fu_8596_p2 = (tmp_332_fu_8592_p1 + tmp_330_fu_8564_p1);
assign tmp1670_fu_36976_p2 = (r_V_172_2_4_2_fu_33457_p3 | r_V_172_2_5_2_fu_33945_p3);
assign tmp1671_fu_36982_p2 = (tmp1670_fu_36976_p2 | r_V_172_2_3_2_fu_32847_p3);
assign tmp1672_fu_36988_p2 = (tmp1671_fu_36982_p2 | tmp1669_fu_36970_p2);
assign tmp1673_fu_36994_p2 = (r_V_172_2_7_2_fu_34789_p3 | r_V_172_2_8_2_fu_35369_p3);
assign tmp1674_fu_37000_p2 = (tmp1673_fu_36994_p2 | r_V_172_2_6_2_fu_34371_p3);
assign tmp1675_fu_37006_p2 = (r_V_172_2_10_2_fu_36283_p3 | r_V_172_2_11_2_fu_36957_p3);
assign tmp1676_fu_37012_p2 = (tmp1675_fu_37006_p2 | r_V_172_2_9_2_fu_35849_p3);
assign tmp1677_fu_37018_p2 = (tmp1676_fu_37012_p2 | tmp1674_fu_37000_p2);
assign tmp1678_fu_37037_p2 = (r_V_172_2_1_3_fu_32028_p3 | r_V_172_2_2_3_fu_32444_p3);
assign tmp1679_fu_37043_p2 = (tmp1678_fu_37037_p2 | bt_cpattern_V11_fu_31628_p3);
assign tmp1680_fu_37049_p2 = (r_V_172_2_4_3_fu_33464_p3 | r_V_172_2_5_3_fu_33952_p3);
assign tmp1681_fu_37055_p2 = (tmp1680_fu_37049_p2 | r_V_172_2_3_3_fu_32854_p3);
assign tmp1682_fu_37061_p2 = (tmp1681_fu_37055_p2 | tmp1679_fu_37043_p2);
assign tmp1683_fu_37067_p2 = (r_V_172_2_7_3_fu_34796_p3 | r_V_172_2_8_3_fu_35376_p3);
assign tmp1684_fu_37073_p2 = (tmp1683_fu_37067_p2 | r_V_172_2_6_3_fu_34378_p3);
assign tmp1685_fu_37079_p2 = (r_V_172_2_10_3_fu_36290_p3 | r_V_172_2_11_3_fu_37030_p3);
assign tmp1686_fu_37085_p2 = (tmp1685_fu_37079_p2 | r_V_172_2_9_3_fu_35856_p3);
assign tmp1687_fu_37091_p2 = (tmp1686_fu_37085_p2 | tmp1684_fu_37073_p2);
assign tmp1688_fu_37110_p2 = (r_V_173_2_1_fu_32035_p3 | r_V_173_2_2_fu_32451_p3);
assign tmp1689_fu_37116_p2 = (tmp1688_fu_37110_p2 | bt_delta_ph_V12_fu_31635_p3);
assign tmp1690_fu_37122_p2 = (r_V_173_2_4_fu_33471_p3 | r_V_173_2_5_fu_33959_p3);
assign tmp1691_fu_37128_p2 = (tmp1690_fu_37122_p2 | r_V_173_2_3_fu_32861_p3);
assign tmp1692_fu_37134_p2 = (tmp1691_fu_37128_p2 | tmp1689_fu_37116_p2);
assign tmp1693_fu_37140_p2 = (r_V_173_2_7_fu_34803_p3 | r_V_173_2_8_fu_35383_p3);
assign tmp1694_fu_37146_p2 = (tmp1693_fu_37140_p2 | r_V_173_2_6_fu_34385_p3);
assign tmp1695_fu_37152_p2 = (r_V_173_2_s_fu_36297_p3 | r_V_173_2_10_fu_37103_p3);
assign tmp1696_fu_37158_p2 = (tmp1695_fu_37152_p2 | r_V_173_2_9_fu_35863_p3);
assign tmp1697_fu_37164_p2 = (tmp1696_fu_37158_p2 | tmp1694_fu_37146_p2);
assign tmp1698_fu_37183_p2 = (r_V_173_2_1_1_fu_32042_p3 | r_V_173_2_2_1_fu_32458_p3);
assign tmp1699_fu_37189_p2 = (tmp1698_fu_37183_p2 | bt_delta_ph_V13_fu_31642_p3);
assign tmp169_fu_8780_p2 = (tmp_1608_fu_8712_p1 ^ tmp_1607_fu_8704_p3);
assign tmp1700_fu_37195_p2 = (r_V_173_2_4_1_fu_33478_p3 | r_V_173_2_5_1_fu_33966_p3);
assign tmp1701_fu_37201_p2 = (tmp1700_fu_37195_p2 | r_V_173_2_3_1_fu_32868_p3);
assign tmp1702_fu_37207_p2 = (tmp1701_fu_37201_p2 | tmp1699_fu_37189_p2);
assign tmp1703_fu_37213_p2 = (r_V_173_2_7_1_fu_34810_p3 | r_V_173_2_8_1_fu_35390_p3);
assign tmp1704_fu_37219_p2 = (tmp1703_fu_37213_p2 | r_V_173_2_6_1_fu_34392_p3);
assign tmp1705_fu_37225_p2 = (r_V_173_2_10_1_fu_36304_p3 | r_V_173_2_11_1_fu_37176_p3);
assign tmp1706_fu_37231_p2 = (tmp1705_fu_37225_p2 | r_V_173_2_9_1_fu_35870_p3);
assign tmp1707_fu_37237_p2 = (tmp1706_fu_37231_p2 | tmp1704_fu_37219_p2);
assign tmp1708_fu_37256_p2 = (r_V_173_2_1_2_fu_32049_p3 | r_V_173_2_2_2_fu_32465_p3);
assign tmp1709_fu_37262_p2 = (tmp1708_fu_37256_p2 | bt_delta_ph_V14_fu_31649_p3);
assign tmp170_fu_8786_p2 = (tmp_1605_fu_8688_p3 ^ tmp_1606_fu_8696_p3);
assign tmp1710_fu_37268_p2 = (r_V_173_2_4_2_fu_33485_p3 | r_V_173_2_5_2_fu_33973_p3);
assign tmp1711_fu_37274_p2 = (tmp1710_fu_37268_p2 | r_V_173_2_3_2_fu_32875_p3);
assign tmp1712_fu_37280_p2 = (tmp1711_fu_37274_p2 | tmp1709_fu_37262_p2);
assign tmp1713_fu_37286_p2 = (r_V_173_2_7_2_fu_34817_p3 | r_V_173_2_8_2_fu_35397_p3);
assign tmp1714_fu_37292_p2 = (tmp1713_fu_37286_p2 | r_V_173_2_6_2_fu_34399_p3);
assign tmp1715_fu_37298_p2 = (r_V_173_2_10_2_fu_36311_p3 | r_V_173_2_11_2_fu_37249_p3);
assign tmp1716_fu_37304_p2 = (tmp1715_fu_37298_p2 | r_V_173_2_9_2_fu_35877_p3);
assign tmp1717_fu_37310_p2 = (tmp1716_fu_37304_p2 | tmp1714_fu_37292_p2);
assign tmp1718_fu_37329_p2 = (r_V_173_2_1_3_fu_32056_p3 | r_V_173_2_2_3_fu_32472_p3);
assign tmp1719_fu_37335_p2 = (tmp1718_fu_37329_p2 | bt_delta_ph_V15_fu_31656_p3);
assign tmp171_fu_8840_p2 = (lhs_i_i141_0_i_1_fu_8828_p2 & rhs_i_i140_0_i_1_fu_8834_p2);
assign tmp1720_fu_37341_p2 = (r_V_173_2_4_3_fu_33492_p3 | r_V_173_2_5_3_fu_33980_p3);
assign tmp1721_fu_37347_p2 = (tmp1720_fu_37341_p2 | r_V_173_2_3_3_fu_32882_p3);
assign tmp1722_fu_37353_p2 = (tmp1721_fu_37347_p2 | tmp1719_fu_37335_p2);
assign tmp1723_fu_37359_p2 = (r_V_173_2_7_3_fu_34824_p3 | r_V_173_2_8_3_fu_35404_p3);
assign tmp1724_fu_37365_p2 = (tmp1723_fu_37359_p2 | r_V_173_2_6_3_fu_34406_p3);
assign tmp1725_fu_37371_p2 = (r_V_173_2_10_3_fu_36318_p3 | r_V_173_2_11_3_fu_37322_p3);
assign tmp1726_fu_37377_p2 = (tmp1725_fu_37371_p2 | r_V_173_2_9_3_fu_35884_p3);
assign tmp1727_fu_37383_p2 = (tmp1726_fu_37377_p2 | tmp1724_fu_37365_p2);
assign tmp1728_fu_37402_p2 = (r_V_173_2_1_4_fu_32063_p3 | r_V_173_2_2_4_fu_32479_p3);
assign tmp1729_fu_37408_p2 = (tmp1728_fu_37402_p2 | bt_delta_ph_V16_fu_31663_p3);
assign tmp172_fu_8852_p2 = (lhs_i_i135_0_i_1_fu_8846_p2 & rhs_i_i140_0_i_1_fu_8834_p2);
assign tmp1730_fu_37414_p2 = (r_V_173_2_4_4_fu_33499_p3 | r_V_173_2_5_4_fu_33987_p3);
assign tmp1731_fu_37420_p2 = (tmp1730_fu_37414_p2 | r_V_173_2_3_4_fu_32889_p3);
assign tmp1732_fu_37426_p2 = (tmp1731_fu_37420_p2 | tmp1729_fu_37408_p2);
assign tmp1733_fu_37432_p2 = (r_V_173_2_7_4_fu_34831_p3 | r_V_173_2_8_4_fu_35411_p3);
assign tmp1734_fu_37438_p2 = (tmp1733_fu_37432_p2 | r_V_173_2_6_4_fu_34413_p3);
assign tmp1735_fu_37444_p2 = (r_V_173_2_10_4_fu_36325_p3 | r_V_173_2_11_4_fu_37395_p3);
assign tmp1736_fu_37450_p2 = (tmp1735_fu_37444_p2 | r_V_173_2_9_4_fu_35891_p3);
assign tmp1737_fu_37456_p2 = (tmp1736_fu_37450_p2 | tmp1734_fu_37438_p2);
assign tmp1738_fu_37475_p2 = (r_V_173_2_1_5_fu_32070_p3 | r_V_173_2_2_5_fu_32486_p3);
assign tmp1739_fu_37481_p2 = (tmp1738_fu_37475_p2 | bt_delta_ph_V17_fu_31670_p3);
assign tmp173_fu_8876_p2 = (tmp_1607_fu_8704_p3 & rhs_i138_0_i_s_fu_8870_p2);
assign tmp1740_fu_37487_p2 = (r_V_173_2_4_5_fu_33506_p3 | r_V_173_2_5_5_fu_33994_p3);
assign tmp1741_fu_37493_p2 = (tmp1740_fu_37487_p2 | r_V_173_2_3_5_fu_32896_p3);
assign tmp1742_fu_37499_p2 = (tmp1741_fu_37493_p2 | tmp1739_fu_37481_p2);
assign tmp1743_fu_37505_p2 = (r_V_173_2_7_5_fu_34838_p3 | r_V_173_2_8_5_fu_35418_p3);
assign tmp1744_fu_37511_p2 = (tmp1743_fu_37505_p2 | r_V_173_2_6_5_fu_34420_p3);
assign tmp1745_fu_37517_p2 = (r_V_173_2_10_5_fu_36332_p3 | r_V_173_2_11_5_fu_37468_p3);
assign tmp1746_fu_37523_p2 = (tmp1745_fu_37517_p2 | r_V_173_2_9_5_fu_35898_p3);
assign tmp1747_fu_37529_p2 = (tmp1746_fu_37523_p2 | tmp1744_fu_37511_p2);
assign tmp1748_fu_37548_p2 = (r_V_174_2_1_fu_32077_p3 | r_V_174_2_2_fu_32493_p3);
assign tmp1749_fu_37554_p2 = (tmp1748_fu_37548_p2 | bt_delta_th_V12_fu_31677_p3);
assign tmp174_fu_8882_p2 = (tmp173_fu_8876_p2 | lhs_i143_0_i_1_fu_8810_p2);
assign tmp1750_fu_37560_p2 = (r_V_174_2_4_fu_33513_p3 | r_V_174_2_5_fu_34001_p3);
assign tmp1751_fu_37566_p2 = (tmp1750_fu_37560_p2 | r_V_174_2_3_fu_32903_p3);
assign tmp1752_fu_37572_p2 = (tmp1751_fu_37566_p2 | tmp1749_fu_37554_p2);
assign tmp1753_fu_37578_p2 = (r_V_174_2_7_fu_34845_p3 | r_V_174_2_8_fu_35425_p3);
assign tmp1754_fu_37584_p2 = (tmp1753_fu_37578_p2 | r_V_174_2_6_fu_34427_p3);
assign tmp1755_fu_37590_p2 = (r_V_174_2_s_fu_36339_p3 | r_V_174_2_10_fu_37541_p3);
assign tmp1756_fu_37596_p2 = (tmp1755_fu_37590_p2 | r_V_174_2_9_fu_35905_p3);
assign tmp1757_fu_37602_p2 = (tmp1756_fu_37596_p2 | tmp1754_fu_37584_p2);
assign tmp1758_fu_37621_p2 = (r_V_174_2_1_1_fu_32084_p3 | r_V_174_2_2_1_fu_32500_p3);
assign tmp1759_fu_37627_p2 = (tmp1758_fu_37621_p2 | bt_delta_th_V13_fu_31684_p3);
assign tmp175_fu_8888_p2 = (rhs_i_i140_0_i_1_fu_8834_p2 | lhs_i_i135_0_i_1_fu_8846_p2);
assign tmp1760_fu_37633_p2 = (r_V_174_2_4_1_fu_33520_p3 | r_V_174_2_5_1_fu_34008_p3);
assign tmp1761_fu_37639_p2 = (tmp1760_fu_37633_p2 | r_V_174_2_3_1_fu_32910_p3);
assign tmp1762_fu_37645_p2 = (tmp1761_fu_37639_p2 | tmp1759_fu_37627_p2);
assign tmp1763_fu_37651_p2 = (r_V_174_2_7_1_fu_34852_p3 | r_V_174_2_8_1_fu_35432_p3);
assign tmp1764_fu_37657_p2 = (tmp1763_fu_37651_p2 | r_V_174_2_6_1_fu_34434_p3);
assign tmp1765_fu_37663_p2 = (r_V_174_2_10_1_fu_36346_p3 | r_V_174_2_11_1_fu_37614_p3);
assign tmp1766_fu_37669_p2 = (tmp1765_fu_37663_p2 | r_V_174_2_9_1_fu_35912_p3);
assign tmp1767_fu_37675_p2 = (tmp1766_fu_37669_p2 | tmp1764_fu_37657_p2);
assign tmp1768_fu_37694_p2 = (r_V_174_2_1_2_fu_32091_p3 | r_V_174_2_2_2_fu_32507_p3);
assign tmp1769_fu_37700_p2 = (tmp1768_fu_37694_p2 | bt_delta_th_V14_fu_31691_p3);
assign tmp176_fu_8900_p2 = (rhs_i126_0_i_s_fu_8894_p2 & tmp_1605_fu_8688_p3);
assign tmp1770_fu_37706_p2 = (r_V_174_2_4_2_fu_33527_p3 | r_V_174_2_5_2_fu_34015_p3);
assign tmp1771_fu_37712_p2 = (tmp1770_fu_37706_p2 | r_V_174_2_3_2_fu_32917_p3);
assign tmp1772_fu_37718_p2 = (tmp1771_fu_37712_p2 | tmp1769_fu_37700_p2);
assign tmp1773_fu_37724_p2 = (r_V_174_2_7_2_fu_34859_p3 | r_V_174_2_8_2_fu_35439_p3);
assign tmp1774_fu_37730_p2 = (tmp1773_fu_37724_p2 | r_V_174_2_6_2_fu_34441_p3);
assign tmp1775_fu_37736_p2 = (r_V_174_2_10_2_fu_36353_p3 | r_V_174_2_11_2_fu_37687_p3);
assign tmp1776_fu_37742_p2 = (tmp1775_fu_37736_p2 | r_V_174_2_9_2_fu_35919_p3);
assign tmp1777_fu_37748_p2 = (tmp1776_fu_37742_p2 | tmp1774_fu_37730_p2);
assign tmp1778_fu_37767_p2 = (r_V_174_2_1_3_fu_32098_p3 | r_V_174_2_2_3_fu_32514_p3);
assign tmp1779_fu_37773_p2 = (tmp1778_fu_37767_p2 | bt_delta_th_V15_fu_31698_p3);
assign tmp177_fu_8906_p2 = (tmp176_fu_8900_p2 | rhs_i132_0_i_1_fu_8858_p2);
assign tmp1780_fu_37779_p2 = (r_V_174_2_4_3_fu_33534_p3 | r_V_174_2_5_3_fu_34022_p3);
assign tmp1781_fu_37785_p2 = (tmp1780_fu_37779_p2 | r_V_174_2_3_3_fu_32924_p3);
assign tmp1782_fu_37791_p2 = (tmp1781_fu_37785_p2 | tmp1779_fu_37773_p2);
assign tmp1783_fu_37797_p2 = (r_V_174_2_7_3_fu_34866_p3 | r_V_174_2_8_3_fu_35446_p3);
assign tmp1784_fu_37803_p2 = (tmp1783_fu_37797_p2 | r_V_174_2_6_3_fu_34448_p3);
assign tmp1785_fu_37809_p2 = (r_V_174_2_10_3_fu_36360_p3 | r_V_174_2_11_3_fu_37760_p3);
assign tmp1786_fu_37815_p2 = (tmp1785_fu_37809_p2 | r_V_174_2_9_3_fu_35926_p3);
assign tmp1787_fu_37821_p2 = (tmp1786_fu_37815_p2 | tmp1784_fu_37803_p2);
assign tmp1788_fu_37840_p2 = (r_V_174_2_1_4_fu_32105_p3 | r_V_174_2_2_4_fu_32521_p3);
assign tmp1789_fu_37846_p2 = (tmp1788_fu_37840_p2 | bt_delta_th_V16_fu_31705_p3);
assign tmp178_fu_8918_p2 = (tmp_1607_fu_8704_p3 | tmp_1608_fu_8712_p1);
assign tmp1790_fu_37852_p2 = (r_V_174_2_4_4_fu_33541_p3 | r_V_174_2_5_4_fu_34029_p3);
assign tmp1791_fu_37858_p2 = (tmp1790_fu_37852_p2 | r_V_174_2_3_4_fu_32931_p3);
assign tmp1792_fu_37864_p2 = (tmp1791_fu_37858_p2 | tmp1789_fu_37846_p2);
assign tmp1793_fu_37870_p2 = (r_V_174_2_7_4_fu_34873_p3 | r_V_174_2_8_4_fu_35453_p3);
assign tmp1794_fu_37876_p2 = (tmp1793_fu_37870_p2 | r_V_174_2_6_4_fu_34455_p3);
assign tmp1795_fu_37882_p2 = (r_V_174_2_10_4_fu_36367_p3 | r_V_174_2_11_4_fu_37833_p3);
assign tmp1796_fu_37888_p2 = (tmp1795_fu_37882_p2 | r_V_174_2_9_4_fu_35933_p3);
assign tmp1797_fu_37894_p2 = (tmp1796_fu_37888_p2 | tmp1794_fu_37876_p2);
assign tmp1798_fu_37913_p2 = (r_V_174_2_1_5_fu_32112_p3 | r_V_174_2_2_5_fu_32528_p3);
assign tmp1799_fu_37919_p2 = (tmp1798_fu_37913_p2 | bt_delta_th_V17_fu_31712_p3);
assign tmp179_fu_8936_p2 = (tmp_1612_fu_8740_p3 ^ tmp_1611_fu_8732_p3);
assign tmp1800_fu_37925_p2 = (r_V_174_2_4_5_fu_33548_p3 | r_V_174_2_5_5_fu_34036_p3);
assign tmp1801_fu_37931_p2 = (tmp1800_fu_37925_p2 | r_V_174_2_3_5_fu_32938_p3);
assign tmp1802_fu_37937_p2 = (tmp1801_fu_37931_p2 | tmp1799_fu_37919_p2);
assign tmp1803_fu_37943_p2 = (r_V_174_2_7_5_fu_34880_p3 | r_V_174_2_8_5_fu_35460_p3);
assign tmp1804_fu_37949_p2 = (tmp1803_fu_37943_p2 | r_V_174_2_6_5_fu_34462_p3);
assign tmp1805_fu_37955_p2 = (r_V_174_2_10_5_fu_36374_p3 | r_V_174_2_11_5_fu_37906_p3);
assign tmp1806_fu_37961_p2 = (tmp1805_fu_37955_p2 | r_V_174_2_9_5_fu_35940_p3);
assign tmp1807_fu_37967_p2 = (tmp1806_fu_37961_p2 | tmp1804_fu_37949_p2);
assign tmp1808_fu_38002_p2 = (r_V_169_2_1_fu_32135_p3 | r_V_169_2_2_fu_32551_p3);
assign tmp1809_fu_38008_p2 = (tmp1808_fu_38002_p2 | bt_rank_V2_fu_31733_p3);
assign tmp180_fu_8942_p2 = (tmp_1609_fu_8716_p3 ^ tmp_1610_fu_8724_p3);
assign tmp1810_fu_38014_p2 = (r_V_169_2_4_fu_33571_p3 | r_V_169_2_5_fu_34059_p3);
assign tmp1811_fu_38020_p2 = (tmp1810_fu_38014_p2 | r_V_169_2_3_fu_32961_p3);
assign tmp1812_fu_38026_p2 = (tmp1811_fu_38020_p2 | tmp1809_fu_38008_p2);
assign tmp1813_fu_38032_p2 = (r_V_169_2_7_fu_34903_p3 | r_V_169_2_8_fu_35483_p3);
assign tmp1814_fu_38038_p2 = (tmp1813_fu_38032_p2 | r_V_169_2_6_fu_34485_p3);
assign tmp1815_fu_38044_p2 = (r_V_169_2_s_fu_36397_p3 | r_V_169_2_10_fu_37995_p3);
assign tmp1816_fu_38050_p2 = (tmp1815_fu_38044_p2 | r_V_169_2_9_fu_35963_p3);
assign tmp1817_fu_38056_p2 = (tmp1816_fu_38050_p2 | tmp1814_fu_38038_p2);
assign tmp1818_fu_38074_p3 = {{tmp_2739_fu_38068_p2}, {1'b0}};
assign tmp1819_fu_38082_p2 = (tmp1818_fu_38074_p3 | r_V_176_2_9_fu_35970_p3);
assign tmp181_fu_8996_p2 = (lhs_i_i97_0_i_1_fu_8984_p2 & rhs_i_i96_0_i_1_fu_8990_p2);
assign tmp1820_fu_38088_p3 = {{tmp_2658_fu_34946_p2}, {1'b0}};
assign tmp1821_fu_38096_p2 = (tmp1820_fu_38088_p3 | r_V_176_2_5_fu_34066_p3);
assign tmp1822_fu_38102_p2 = (tmp1821_fu_38096_p2 | tmp1819_fu_38082_p2);
assign tmp1823_fu_38114_p3 = {{tmp_2740_fu_38108_p2}, {1'b0}};
assign tmp1824_fu_38122_p2 = (tmp1823_fu_38114_p3 | r_V_176_2_1_fu_32142_p3);
assign tmp1825_fu_38134_p3 = {{tmp_2741_fu_38128_p2}, {1'b0}};
assign tmp1826_fu_38142_p2 = (tmp1825_fu_38134_p3 | r_V_176_2_4_fu_33578_p3);
assign tmp1827_fu_38148_p2 = (tmp1826_fu_38142_p2 | tmp1824_fu_38122_p2);
assign tmp1829_fu_38174_p3 = {{tmp_2742_fu_38160_p3}, {tmp_2743_fu_38168_p2}};
assign tmp182_fu_9008_p2 = (lhs_i_i91_0_i_1_fu_9002_p2 & rhs_i_i96_0_i_1_fu_8990_p2);
assign tmp1831_fu_38196_p3 = {{tmp_2745_fu_38188_p3}, {tmp_2744_fu_38182_p2}};
assign tmp1832_fu_38204_p2 = (tmp1831_fu_38196_p3 | tmp1829_fu_38174_p3);
assign tmp1833_fu_38218_p3 = {{tmp_2746_fu_38210_p3}, {tmp_2667_fu_35040_p3}};
assign tmp1834_fu_38226_p2 = (tmp1833_fu_38218_p3 | r_V_176_2_6_fu_34492_p3);
assign tmp1835_fu_38238_p3 = {{tmp_2747_fu_38232_p2}, {1'b0}};
assign tmp1836_fu_38246_p3 = {{tmp_2747_fu_38232_p2}, {tmp_2685_fu_35522_p3}};
assign tmp1837_fu_38254_p2 = (tmp1836_fu_38246_p3 | tmp1834_fu_38226_p2);
assign tmp1839_fu_38266_p3 = {{tmp_2581_fu_33064_p2}, {tmp_2520_fu_31585_p3}};
assign tmp183_fu_9032_p2 = (tmp_1611_fu_8732_p3 & rhs_i94_0_i_s_fu_9026_p2);
assign tmp1840_fu_38282_p3 = {{tmp_2748_fu_38274_p3}, {tmp_2584_fu_33116_p3}};
assign tmp1841_fu_38290_p2 = (tmp1840_fu_38282_p3 | r_V_176_2_3_fu_32968_p3);
assign tmp1842_fu_38296_p2 = (tmp1841_fu_38290_p2 | tmp1839_fu_38266_p3);
assign tmp1846_fu_38302_p2 = (tmp1835_fu_38238_p3 | r_V_176_2_9_fu_35970_p3);
assign tmp1847_fu_38308_p2 = (tmp1846_fu_38302_p2 | tmp1834_fu_38226_p2);
assign tmp1848_fu_38334_p3 = {{1'b0}, {tmp_904_fu_38328_p2}};
assign tmp1849_fu_38348_p3 = {{tmp_2747_fu_38232_p2}, {ap_const_lv2_0}};
assign tmp184_fu_9038_p2 = (tmp183_fu_9032_p2 | lhs_i99_0_i_1_fu_8966_p2);
assign tmp185_fu_9044_p2 = (rhs_i_i96_0_i_1_fu_8990_p2 | lhs_i_i91_0_i_1_fu_9002_p2);
assign tmp186_fu_9056_p2 = (rhs_i82_0_i_s_fu_9050_p2 & tmp_1609_fu_8716_p3);
assign tmp187_fu_9062_p2 = (tmp186_fu_9056_p2 | rhs_i88_0_i_1_fu_9014_p2);
assign tmp188_fu_9074_p2 = (tmp_1611_fu_8732_p3 | tmp_1612_fu_8740_p3);
assign tmp189_fu_9092_p2 = (tmp_1616_fu_8772_p3 ^ tmp_1615_fu_8764_p3);
assign tmp190_fu_9098_p2 = (tmp_1613_fu_8748_p3 ^ tmp_1614_fu_8756_p3);
assign tmp191_fu_9152_p2 = (lhs_i_i53_0_i_1_fu_9140_p2 & rhs_i_i52_0_i_1_fu_9146_p2);
assign tmp192_fu_9164_p2 = (lhs_i_i47_0_i_1_fu_9158_p2 & rhs_i_i52_0_i_1_fu_9146_p2);
assign tmp193_fu_9188_p2 = (tmp_1615_fu_8764_p3 & rhs_i50_0_i1_s_fu_9182_p2);
assign tmp194_fu_9194_p2 = (tmp193_fu_9188_p2 | lhs_i55_0_i_1_fu_9122_p2);
assign tmp195_fu_9200_p2 = (rhs_i_i52_0_i_1_fu_9146_p2 | lhs_i_i47_0_i_1_fu_9158_p2);
assign tmp196_fu_9212_p2 = (rhs_i38_0_i_s_fu_9206_p2 & tmp_1613_fu_8748_p3);
assign tmp197_fu_9218_p2 = (tmp196_fu_9212_p2 | rhs_i44_0_i_1_fu_9170_p2);
assign tmp198_fu_9230_p2 = (tmp_1615_fu_8764_p3 | tmp_1616_fu_8772_p3);
assign tmp199_fu_9290_p2 = (tmp_1399_1_fu_9286_p1 + tmp_1397_1_fu_9258_p1);
assign tmp202_fu_9456_p2 = (tmp_1635_fu_9388_p1 ^ tmp_1634_fu_9380_p3);
assign tmp203_fu_9462_p2 = (tmp_1632_fu_9364_p3 ^ tmp_1633_fu_9372_p3);
assign tmp204_fu_9516_p2 = (lhs_i_i141_0_i_2_fu_9504_p2 & rhs_i_i140_0_i_2_fu_9510_p2);
assign tmp205_fu_9528_p2 = (lhs_i_i135_0_i_2_fu_9522_p2 & rhs_i_i140_0_i_2_fu_9510_p2);
assign tmp206_fu_9552_p2 = (tmp_1634_fu_9380_p3 & rhs_i138_0_i_1_fu_9546_p2);
assign tmp207_fu_9558_p2 = (tmp206_fu_9552_p2 | lhs_i143_0_i_2_fu_9486_p2);
assign tmp208_fu_9564_p2 = (rhs_i_i140_0_i_2_fu_9510_p2 | lhs_i_i135_0_i_2_fu_9522_p2);
assign tmp209_fu_9576_p2 = (rhs_i126_0_i_1_fu_9570_p2 & tmp_1632_fu_9364_p3);
assign tmp210_fu_9582_p2 = (tmp209_fu_9576_p2 | rhs_i132_0_i_2_fu_9534_p2);
assign tmp211_fu_9594_p2 = (tmp_1634_fu_9380_p3 | tmp_1635_fu_9388_p1);
assign tmp212_fu_9612_p2 = (tmp_1639_fu_9416_p3 ^ tmp_1638_fu_9408_p3);
assign tmp213_fu_9618_p2 = (tmp_1636_fu_9392_p3 ^ tmp_1637_fu_9400_p3);
assign tmp214_fu_9672_p2 = (lhs_i_i97_0_i_2_fu_9660_p2 & rhs_i_i96_0_i_2_fu_9666_p2);
assign tmp215_fu_9684_p2 = (lhs_i_i91_0_i_2_fu_9678_p2 & rhs_i_i96_0_i_2_fu_9666_p2);
assign tmp216_fu_9708_p2 = (tmp_1638_fu_9408_p3 & rhs_i94_0_i_1_fu_9702_p2);
assign tmp217_fu_9714_p2 = (tmp216_fu_9708_p2 | lhs_i99_0_i_2_fu_9642_p2);
assign tmp218_fu_9720_p2 = (rhs_i_i96_0_i_2_fu_9666_p2 | lhs_i_i91_0_i_2_fu_9678_p2);
assign tmp219_fu_9732_p2 = (rhs_i82_0_i_1_fu_9726_p2 & tmp_1636_fu_9392_p3);
assign tmp220_fu_9738_p2 = (tmp219_fu_9732_p2 | rhs_i88_0_i_2_fu_9690_p2);
assign tmp221_fu_9750_p2 = (tmp_1638_fu_9408_p3 | tmp_1639_fu_9416_p3);
assign tmp222_fu_9768_p2 = (tmp_1643_fu_9448_p3 ^ tmp_1642_fu_9440_p3);
assign tmp223_fu_9774_p2 = (tmp_1640_fu_9424_p3 ^ tmp_1641_fu_9432_p3);
assign tmp224_fu_9828_p2 = (lhs_i_i53_0_i_2_fu_9816_p2 & rhs_i_i52_0_i_2_fu_9822_p2);
assign tmp225_fu_9840_p2 = (lhs_i_i47_0_i_2_fu_9834_p2 & rhs_i_i52_0_i_2_fu_9822_p2);
assign tmp226_fu_9864_p2 = (tmp_1642_fu_9440_p3 & rhs_i50_0_i1_1_fu_9858_p2);
assign tmp227_fu_9870_p2 = (tmp226_fu_9864_p2 | lhs_i55_0_i_2_fu_9798_p2);
assign tmp228_fu_9876_p2 = (rhs_i_i52_0_i_2_fu_9822_p2 | lhs_i_i47_0_i_2_fu_9834_p2);
assign tmp229_fu_9888_p2 = (rhs_i38_0_i_1_fu_9882_p2 & tmp_1640_fu_9424_p3);
assign tmp230_fu_9894_p2 = (tmp229_fu_9888_p2 | rhs_i44_0_i_2_fu_9846_p2);
assign tmp231_fu_9906_p2 = (tmp_1642_fu_9440_p3 | tmp_1643_fu_9448_p3);
assign tmp232_fu_9966_p2 = (tmp_1399_2_fu_9962_p1 + tmp_1397_2_fu_9934_p1);
assign tmp235_fu_10102_p2 = (tmp_1662_fu_10034_p1 ^ tmp_1661_fu_10026_p3);
assign tmp236_fu_10108_p2 = (tmp_1659_fu_10010_p3 ^ tmp_1660_fu_10018_p3);
assign tmp237_fu_10162_p2 = (lhs_i_i141_0_i_3_fu_10150_p2 & rhs_i_i140_0_i_3_fu_10156_p2);
assign tmp238_fu_10174_p2 = (lhs_i_i135_0_i_3_fu_10168_p2 & rhs_i_i140_0_i_3_fu_10156_p2);
assign tmp239_fu_10198_p2 = (tmp_1661_fu_10026_p3 & rhs_i138_0_i_2_fu_10192_p2);
assign tmp240_fu_10204_p2 = (tmp239_fu_10198_p2 | lhs_i143_0_i_3_fu_10132_p2);
assign tmp241_fu_10210_p2 = (rhs_i_i140_0_i_3_fu_10156_p2 | lhs_i_i135_0_i_3_fu_10168_p2);
assign tmp242_fu_10222_p2 = (rhs_i126_0_i_2_fu_10216_p2 & tmp_1659_fu_10010_p3);
assign tmp243_fu_10228_p2 = (tmp242_fu_10222_p2 | rhs_i132_0_i_3_fu_10180_p2);
assign tmp244_fu_10240_p2 = (tmp_1661_fu_10026_p3 | tmp_1662_fu_10034_p1);
assign tmp245_fu_10258_p2 = (tmp_1666_fu_10062_p3 ^ tmp_1665_fu_10054_p3);
assign tmp246_fu_10264_p2 = (tmp_1663_fu_10038_p3 ^ tmp_1664_fu_10046_p3);
assign tmp247_fu_10318_p2 = (lhs_i_i97_0_i_3_fu_10306_p2 & rhs_i_i96_0_i_3_fu_10312_p2);
assign tmp248_fu_10330_p2 = (lhs_i_i91_0_i_3_fu_10324_p2 & rhs_i_i96_0_i_3_fu_10312_p2);
assign tmp249_fu_10354_p2 = (tmp_1665_fu_10054_p3 & rhs_i94_0_i_2_fu_10348_p2);
assign tmp250_fu_10360_p2 = (tmp249_fu_10354_p2 | lhs_i99_0_i_3_fu_10288_p2);
assign tmp251_fu_10366_p2 = (rhs_i_i96_0_i_3_fu_10312_p2 | lhs_i_i91_0_i_3_fu_10324_p2);
assign tmp252_fu_10378_p2 = (rhs_i82_0_i_2_fu_10372_p2 & tmp_1663_fu_10038_p3);
assign tmp253_fu_10384_p2 = (tmp252_fu_10378_p2 | rhs_i88_0_i_3_fu_10336_p2);
assign tmp254_fu_10396_p2 = (tmp_1665_fu_10054_p3 | tmp_1666_fu_10062_p3);
assign tmp255_fu_10414_p2 = (tmp_1670_fu_10094_p3 ^ tmp_1669_fu_10086_p3);
assign tmp256_fu_10420_p2 = (tmp_1667_fu_10070_p3 ^ tmp_1668_fu_10078_p3);
assign tmp257_fu_10474_p2 = (lhs_i_i53_0_i_3_fu_10462_p2 & rhs_i_i52_0_i_3_fu_10468_p2);
assign tmp258_fu_10486_p2 = (lhs_i_i47_0_i_3_fu_10480_p2 & rhs_i_i52_0_i_3_fu_10468_p2);
assign tmp259_fu_10510_p2 = (tmp_1669_fu_10086_p3 & rhs_i50_0_i1_2_fu_10504_p2);
assign tmp260_fu_10516_p2 = (tmp259_fu_10510_p2 | lhs_i55_0_i_3_fu_10444_p2);
assign tmp261_fu_10522_p2 = (rhs_i_i52_0_i_3_fu_10468_p2 | lhs_i_i47_0_i_3_fu_10480_p2);
assign tmp262_fu_10534_p2 = (rhs_i38_0_i_2_fu_10528_p2 & tmp_1667_fu_10070_p3);
assign tmp263_fu_10540_p2 = (tmp262_fu_10534_p2 | rhs_i44_0_i_3_fu_10492_p2);
assign tmp264_fu_10552_p2 = (tmp_1669_fu_10086_p3 | tmp_1670_fu_10094_p3);
assign tmp265_fu_10612_p2 = (tmp_1399_3_fu_10608_p1 + tmp_1397_3_fu_10580_p1);
assign tmp598_fu_10748_p2 = (tmp_1689_fu_10680_p1 ^ tmp_1688_fu_10672_p3);
assign tmp599_fu_10754_p2 = (tmp_1686_fu_10656_p3 ^ tmp_1687_fu_10664_p3);
assign tmp600_fu_10808_p2 = (lhs_i_i141_0_i_4_fu_10796_p2 & rhs_i_i140_0_i_4_fu_10802_p2);
assign tmp601_fu_10820_p2 = (lhs_i_i135_0_i_4_fu_10814_p2 & rhs_i_i140_0_i_4_fu_10802_p2);
assign tmp602_fu_10844_p2 = (tmp_1688_fu_10672_p3 & rhs_i138_0_i_3_fu_10838_p2);
assign tmp603_fu_10850_p2 = (tmp602_fu_10844_p2 | lhs_i143_0_i_4_fu_10778_p2);
assign tmp604_fu_10856_p2 = (rhs_i_i140_0_i_4_fu_10802_p2 | lhs_i_i135_0_i_4_fu_10814_p2);
assign tmp605_fu_10868_p2 = (rhs_i126_0_i_3_fu_10862_p2 & tmp_1686_fu_10656_p3);
assign tmp606_fu_10874_p2 = (tmp605_fu_10868_p2 | rhs_i132_0_i_4_fu_10826_p2);
assign tmp607_fu_10886_p2 = (tmp_1688_fu_10672_p3 | tmp_1689_fu_10680_p1);
assign tmp608_fu_10904_p2 = (tmp_1693_fu_10708_p3 ^ tmp_1692_fu_10700_p3);
assign tmp609_fu_10910_p2 = (tmp_1690_fu_10684_p3 ^ tmp_1691_fu_10692_p3);
assign tmp610_fu_10964_p2 = (lhs_i_i97_0_i_4_fu_10952_p2 & rhs_i_i96_0_i_4_fu_10958_p2);
assign tmp611_fu_10976_p2 = (lhs_i_i91_0_i_4_fu_10970_p2 & rhs_i_i96_0_i_4_fu_10958_p2);
assign tmp612_fu_11000_p2 = (tmp_1692_fu_10700_p3 & rhs_i94_0_i_3_fu_10994_p2);
assign tmp613_fu_11006_p2 = (tmp612_fu_11000_p2 | lhs_i99_0_i_4_fu_10934_p2);
assign tmp614_fu_11012_p2 = (rhs_i_i96_0_i_4_fu_10958_p2 | lhs_i_i91_0_i_4_fu_10970_p2);
assign tmp615_fu_11024_p2 = (rhs_i82_0_i_3_fu_11018_p2 & tmp_1690_fu_10684_p3);
assign tmp616_fu_11030_p2 = (tmp615_fu_11024_p2 | rhs_i88_0_i_4_fu_10982_p2);
assign tmp617_fu_11042_p2 = (tmp_1692_fu_10700_p3 | tmp_1693_fu_10708_p3);
assign tmp618_fu_11060_p2 = (tmp_1697_fu_10740_p3 ^ tmp_1696_fu_10732_p3);
assign tmp619_fu_11066_p2 = (tmp_1694_fu_10716_p3 ^ tmp_1695_fu_10724_p3);
assign tmp620_fu_11120_p2 = (lhs_i_i53_0_i_4_fu_11108_p2 & rhs_i_i52_0_i_4_fu_11114_p2);
assign tmp621_fu_11132_p2 = (lhs_i_i47_0_i_4_fu_11126_p2 & rhs_i_i52_0_i_4_fu_11114_p2);
assign tmp622_fu_11156_p2 = (tmp_1696_fu_10732_p3 & rhs_i50_0_i1_3_fu_11150_p2);
assign tmp623_fu_11162_p2 = (tmp622_fu_11156_p2 | lhs_i55_0_i_4_fu_11090_p2);
assign tmp624_fu_11168_p2 = (rhs_i_i52_0_i_4_fu_11114_p2 | lhs_i_i47_0_i_4_fu_11126_p2);
assign tmp625_fu_11180_p2 = (rhs_i38_0_i_3_fu_11174_p2 & tmp_1694_fu_10716_p3);
assign tmp626_fu_11186_p2 = (tmp625_fu_11180_p2 | rhs_i44_0_i_4_fu_11138_p2);
assign tmp627_fu_11198_p2 = (tmp_1696_fu_10732_p3 | tmp_1697_fu_10740_p3);
assign tmp628_fu_11258_p2 = (tmp_1399_4_fu_11254_p1 + tmp_1397_4_fu_11226_p1);
assign tmp631_fu_11394_p2 = (tmp_1716_fu_11326_p1 ^ tmp_1715_fu_11318_p3);
assign tmp632_fu_11400_p2 = (tmp_1713_fu_11302_p3 ^ tmp_1714_fu_11310_p3);
assign tmp633_fu_11454_p2 = (lhs_i_i141_0_i_5_fu_11442_p2 & rhs_i_i140_0_i_5_fu_11448_p2);
assign tmp634_fu_11466_p2 = (lhs_i_i135_0_i_5_fu_11460_p2 & rhs_i_i140_0_i_5_fu_11448_p2);
assign tmp635_fu_11490_p2 = (tmp_1715_fu_11318_p3 & rhs_i138_0_i_4_fu_11484_p2);
assign tmp636_fu_11496_p2 = (tmp635_fu_11490_p2 | lhs_i143_0_i_5_fu_11424_p2);
assign tmp637_fu_11502_p2 = (rhs_i_i140_0_i_5_fu_11448_p2 | lhs_i_i135_0_i_5_fu_11460_p2);
assign tmp638_fu_11514_p2 = (rhs_i126_0_i_4_fu_11508_p2 & tmp_1713_fu_11302_p3);
assign tmp639_fu_11520_p2 = (tmp638_fu_11514_p2 | rhs_i132_0_i_5_fu_11472_p2);
assign tmp640_fu_11532_p2 = (tmp_1715_fu_11318_p3 | tmp_1716_fu_11326_p1);
assign tmp641_fu_11550_p2 = (tmp_1720_fu_11354_p3 ^ tmp_1719_fu_11346_p3);
assign tmp642_fu_11556_p2 = (tmp_1717_fu_11330_p3 ^ tmp_1718_fu_11338_p3);
assign tmp643_fu_11610_p2 = (lhs_i_i97_0_i_5_fu_11598_p2 & rhs_i_i96_0_i_5_fu_11604_p2);
assign tmp644_fu_11622_p2 = (lhs_i_i91_0_i_5_fu_11616_p2 & rhs_i_i96_0_i_5_fu_11604_p2);
assign tmp645_fu_11646_p2 = (tmp_1719_fu_11346_p3 & rhs_i94_0_i_4_fu_11640_p2);
assign tmp646_fu_11652_p2 = (tmp645_fu_11646_p2 | lhs_i99_0_i_5_fu_11580_p2);
assign tmp647_fu_11658_p2 = (rhs_i_i96_0_i_5_fu_11604_p2 | lhs_i_i91_0_i_5_fu_11616_p2);
assign tmp648_fu_11670_p2 = (rhs_i82_0_i_4_fu_11664_p2 & tmp_1717_fu_11330_p3);
assign tmp649_fu_11676_p2 = (tmp648_fu_11670_p2 | rhs_i88_0_i_5_fu_11628_p2);
assign tmp650_fu_11688_p2 = (tmp_1719_fu_11346_p3 | tmp_1720_fu_11354_p3);
assign tmp651_fu_11706_p2 = (tmp_1724_fu_11386_p3 ^ tmp_1723_fu_11378_p3);
assign tmp652_fu_11712_p2 = (tmp_1721_fu_11362_p3 ^ tmp_1722_fu_11370_p3);
assign tmp653_fu_11766_p2 = (lhs_i_i53_0_i_5_fu_11754_p2 & rhs_i_i52_0_i_5_fu_11760_p2);
assign tmp654_fu_11778_p2 = (lhs_i_i47_0_i_5_fu_11772_p2 & rhs_i_i52_0_i_5_fu_11760_p2);
assign tmp655_fu_11802_p2 = (tmp_1723_fu_11378_p3 & rhs_i50_0_i1_4_fu_11796_p2);
assign tmp656_fu_11808_p2 = (tmp655_fu_11802_p2 | lhs_i55_0_i_5_fu_11736_p2);
assign tmp657_fu_11814_p2 = (rhs_i_i52_0_i_5_fu_11760_p2 | lhs_i_i47_0_i_5_fu_11772_p2);
assign tmp658_fu_11826_p2 = (rhs_i38_0_i_4_fu_11820_p2 & tmp_1721_fu_11362_p3);
assign tmp659_fu_11832_p2 = (tmp658_fu_11826_p2 | rhs_i44_0_i_5_fu_11784_p2);
assign tmp660_fu_11844_p2 = (tmp_1723_fu_11378_p3 | tmp_1724_fu_11386_p3);
assign tmp661_fu_11904_p2 = (tmp_1399_5_fu_11900_p1 + tmp_1397_5_fu_11872_p1);
assign tmp664_fu_12040_p2 = (tmp_1743_fu_11972_p1 ^ tmp_1742_fu_11964_p3);
assign tmp665_fu_12046_p2 = (tmp_1740_fu_11948_p3 ^ tmp_1741_fu_11956_p3);
assign tmp666_fu_12100_p2 = (lhs_i_i141_0_i_6_fu_12088_p2 & rhs_i_i140_0_i_6_fu_12094_p2);
assign tmp667_fu_12112_p2 = (lhs_i_i135_0_i_6_fu_12106_p2 & rhs_i_i140_0_i_6_fu_12094_p2);
assign tmp668_fu_12136_p2 = (tmp_1742_fu_11964_p3 & rhs_i138_0_i_5_fu_12130_p2);
assign tmp669_fu_12142_p2 = (tmp668_fu_12136_p2 | lhs_i143_0_i_6_fu_12070_p2);
assign tmp670_fu_12148_p2 = (rhs_i_i140_0_i_6_fu_12094_p2 | lhs_i_i135_0_i_6_fu_12106_p2);
assign tmp671_fu_12160_p2 = (rhs_i126_0_i_5_fu_12154_p2 & tmp_1740_fu_11948_p3);
assign tmp672_fu_12166_p2 = (tmp671_fu_12160_p2 | rhs_i132_0_i_6_fu_12118_p2);
assign tmp673_fu_12178_p2 = (tmp_1742_fu_11964_p3 | tmp_1743_fu_11972_p1);
assign tmp674_fu_12196_p2 = (tmp_1747_fu_12000_p3 ^ tmp_1746_fu_11992_p3);
assign tmp675_fu_12202_p2 = (tmp_1744_fu_11976_p3 ^ tmp_1745_fu_11984_p3);
assign tmp676_fu_12256_p2 = (lhs_i_i97_0_i_6_fu_12244_p2 & rhs_i_i96_0_i_6_fu_12250_p2);
assign tmp677_fu_12268_p2 = (lhs_i_i91_0_i_6_fu_12262_p2 & rhs_i_i96_0_i_6_fu_12250_p2);
assign tmp678_fu_12292_p2 = (tmp_1746_fu_11992_p3 & rhs_i94_0_i_5_fu_12286_p2);
assign tmp679_fu_12298_p2 = (tmp678_fu_12292_p2 | lhs_i99_0_i_6_fu_12226_p2);
assign tmp680_fu_12304_p2 = (rhs_i_i96_0_i_6_fu_12250_p2 | lhs_i_i91_0_i_6_fu_12262_p2);
assign tmp681_fu_12316_p2 = (rhs_i82_0_i_5_fu_12310_p2 & tmp_1744_fu_11976_p3);
assign tmp682_fu_12322_p2 = (tmp681_fu_12316_p2 | rhs_i88_0_i_6_fu_12274_p2);
assign tmp683_fu_12334_p2 = (tmp_1746_fu_11992_p3 | tmp_1747_fu_12000_p3);
assign tmp684_fu_12352_p2 = (tmp_1751_fu_12032_p3 ^ tmp_1750_fu_12024_p3);
assign tmp685_fu_12358_p2 = (tmp_1748_fu_12008_p3 ^ tmp_1749_fu_12016_p3);
assign tmp686_fu_12412_p2 = (lhs_i_i53_0_i_6_fu_12400_p2 & rhs_i_i52_0_i_6_fu_12406_p2);
assign tmp687_fu_12424_p2 = (lhs_i_i47_0_i_6_fu_12418_p2 & rhs_i_i52_0_i_6_fu_12406_p2);
assign tmp688_fu_12448_p2 = (tmp_1750_fu_12024_p3 & rhs_i50_0_i1_5_fu_12442_p2);
assign tmp689_fu_12454_p2 = (tmp688_fu_12448_p2 | lhs_i55_0_i_6_fu_12382_p2);
assign tmp690_fu_12460_p2 = (rhs_i_i52_0_i_6_fu_12406_p2 | lhs_i_i47_0_i_6_fu_12418_p2);
assign tmp691_fu_12472_p2 = (rhs_i38_0_i_5_fu_12466_p2 & tmp_1748_fu_12008_p3);
assign tmp692_fu_12478_p2 = (tmp691_fu_12472_p2 | rhs_i44_0_i_6_fu_12430_p2);
assign tmp693_fu_12490_p2 = (tmp_1750_fu_12024_p3 | tmp_1751_fu_12032_p3);
assign tmp694_fu_12550_p2 = (tmp_1399_6_fu_12546_p1 + tmp_1397_6_fu_12518_p1);
assign tmp699_fu_12686_p2 = (tmp_1770_fu_12618_p1 ^ tmp_1769_fu_12610_p3);
assign tmp700_fu_12692_p2 = (tmp_1767_fu_12594_p3 ^ tmp_1768_fu_12602_p3);
assign tmp701_fu_12746_p2 = (lhs_i_i141_0_i_7_fu_12734_p2 & rhs_i_i140_0_i_7_fu_12740_p2);
assign tmp702_fu_12758_p2 = (lhs_i_i135_0_i_7_fu_12752_p2 & rhs_i_i140_0_i_7_fu_12740_p2);
assign tmp703_fu_12782_p2 = (tmp_1769_fu_12610_p3 & rhs_i138_0_i_6_fu_12776_p2);
assign tmp704_fu_12788_p2 = (tmp703_fu_12782_p2 | lhs_i143_0_i_7_fu_12716_p2);
assign tmp705_fu_12794_p2 = (rhs_i_i140_0_i_7_fu_12740_p2 | lhs_i_i135_0_i_7_fu_12752_p2);
assign tmp706_fu_12806_p2 = (rhs_i126_0_i_6_fu_12800_p2 & tmp_1767_fu_12594_p3);
assign tmp707_fu_12812_p2 = (tmp706_fu_12806_p2 | rhs_i132_0_i_7_fu_12764_p2);
assign tmp708_fu_12824_p2 = (tmp_1769_fu_12610_p3 | tmp_1770_fu_12618_p1);
assign tmp709_fu_12842_p2 = (tmp_1774_fu_12646_p3 ^ tmp_1773_fu_12638_p3);
assign tmp710_fu_12848_p2 = (tmp_1771_fu_12622_p3 ^ tmp_1772_fu_12630_p3);
assign tmp711_fu_12902_p2 = (lhs_i_i97_0_i_7_fu_12890_p2 & rhs_i_i96_0_i_7_fu_12896_p2);
assign tmp712_fu_12914_p2 = (lhs_i_i91_0_i_7_fu_12908_p2 & rhs_i_i96_0_i_7_fu_12896_p2);
assign tmp713_fu_12938_p2 = (tmp_1773_fu_12638_p3 & rhs_i94_0_i_6_fu_12932_p2);
assign tmp714_fu_12944_p2 = (tmp713_fu_12938_p2 | lhs_i99_0_i_7_fu_12872_p2);
assign tmp715_fu_12950_p2 = (rhs_i_i96_0_i_7_fu_12896_p2 | lhs_i_i91_0_i_7_fu_12908_p2);
assign tmp716_fu_12962_p2 = (rhs_i82_0_i_6_fu_12956_p2 & tmp_1771_fu_12622_p3);
assign tmp717_fu_12968_p2 = (tmp716_fu_12962_p2 | rhs_i88_0_i_7_fu_12920_p2);
assign tmp718_fu_12980_p2 = (tmp_1773_fu_12638_p3 | tmp_1774_fu_12646_p3);
assign tmp719_fu_12998_p2 = (tmp_1778_fu_12678_p3 ^ tmp_1777_fu_12670_p3);
assign tmp720_fu_13004_p2 = (tmp_1775_fu_12654_p3 ^ tmp_1776_fu_12662_p3);
assign tmp721_fu_13058_p2 = (lhs_i_i53_0_i_7_fu_13046_p2 & rhs_i_i52_0_i_7_fu_13052_p2);
assign tmp722_fu_13070_p2 = (lhs_i_i47_0_i_7_fu_13064_p2 & rhs_i_i52_0_i_7_fu_13052_p2);
assign tmp723_fu_13094_p2 = (tmp_1777_fu_12670_p3 & rhs_i50_0_i1_6_fu_13088_p2);
assign tmp724_fu_13100_p2 = (tmp723_fu_13094_p2 | lhs_i55_0_i_7_fu_13028_p2);
assign tmp725_fu_13106_p2 = (rhs_i_i52_0_i_7_fu_13052_p2 | lhs_i_i47_0_i_7_fu_13064_p2);
assign tmp726_fu_13118_p2 = (rhs_i38_0_i_6_fu_13112_p2 & tmp_1775_fu_12654_p3);
assign tmp727_fu_13124_p2 = (tmp726_fu_13118_p2 | rhs_i44_0_i_7_fu_13076_p2);
assign tmp728_fu_13136_p2 = (tmp_1777_fu_12670_p3 | tmp_1778_fu_12678_p3);
assign tmp729_fu_13196_p2 = (tmp_1399_7_fu_13192_p1 + tmp_1397_7_fu_13164_p1);
assign tmp892_fu_13332_p2 = (tmp_1797_fu_13264_p1 ^ tmp_1796_fu_13256_p3);
assign tmp893_fu_13338_p2 = (tmp_1794_fu_13240_p3 ^ tmp_1795_fu_13248_p3);
assign tmp894_fu_13392_p2 = (lhs_i_i141_0_i_8_fu_13380_p2 & rhs_i_i140_0_i_8_fu_13386_p2);
assign tmp895_fu_13404_p2 = (lhs_i_i135_0_i_8_fu_13398_p2 & rhs_i_i140_0_i_8_fu_13386_p2);
assign tmp896_fu_13428_p2 = (tmp_1796_fu_13256_p3 & rhs_i138_0_i_7_fu_13422_p2);
assign tmp897_fu_13434_p2 = (tmp896_fu_13428_p2 | lhs_i143_0_i_8_fu_13362_p2);
assign tmp898_fu_13440_p2 = (rhs_i_i140_0_i_8_fu_13386_p2 | lhs_i_i135_0_i_8_fu_13398_p2);
assign tmp899_fu_13452_p2 = (rhs_i126_0_i_7_fu_13446_p2 & tmp_1794_fu_13240_p3);
assign tmp900_fu_13458_p2 = (tmp899_fu_13452_p2 | rhs_i132_0_i_8_fu_13410_p2);
assign tmp901_fu_13470_p2 = (tmp_1796_fu_13256_p3 | tmp_1797_fu_13264_p1);
assign tmp902_fu_13488_p2 = (tmp_1801_fu_13292_p3 ^ tmp_1800_fu_13284_p3);
assign tmp903_fu_13494_p2 = (tmp_1798_fu_13268_p3 ^ tmp_1799_fu_13276_p3);
assign tmp904_fu_13548_p2 = (lhs_i_i97_0_i_8_fu_13536_p2 & rhs_i_i96_0_i_8_fu_13542_p2);
assign tmp905_fu_13560_p2 = (lhs_i_i91_0_i_8_fu_13554_p2 & rhs_i_i96_0_i_8_fu_13542_p2);
assign tmp906_fu_13584_p2 = (tmp_1800_fu_13284_p3 & rhs_i94_0_i_7_fu_13578_p2);
assign tmp907_fu_13590_p2 = (tmp906_fu_13584_p2 | lhs_i99_0_i_8_fu_13518_p2);
assign tmp908_fu_13596_p2 = (rhs_i_i96_0_i_8_fu_13542_p2 | lhs_i_i91_0_i_8_fu_13554_p2);
assign tmp909_fu_13608_p2 = (rhs_i82_0_i_7_fu_13602_p2 & tmp_1798_fu_13268_p3);
assign tmp910_fu_13614_p2 = (tmp909_fu_13608_p2 | rhs_i88_0_i_8_fu_13566_p2);
assign tmp911_fu_13626_p2 = (tmp_1800_fu_13284_p3 | tmp_1801_fu_13292_p3);
assign tmp912_fu_13644_p2 = (tmp_1805_fu_13324_p3 ^ tmp_1804_fu_13316_p3);
assign tmp913_fu_13650_p2 = (tmp_1802_fu_13300_p3 ^ tmp_1803_fu_13308_p3);
assign tmp914_fu_13704_p2 = (lhs_i_i53_0_i_8_fu_13692_p2 & rhs_i_i52_0_i_8_fu_13698_p2);
assign tmp915_fu_13716_p2 = (lhs_i_i47_0_i_8_fu_13710_p2 & rhs_i_i52_0_i_8_fu_13698_p2);
assign tmp916_fu_13740_p2 = (tmp_1804_fu_13316_p3 & rhs_i50_0_i1_7_fu_13734_p2);
assign tmp917_fu_13746_p2 = (tmp916_fu_13740_p2 | lhs_i55_0_i_8_fu_13674_p2);
assign tmp918_fu_13752_p2 = (rhs_i_i52_0_i_8_fu_13698_p2 | lhs_i_i47_0_i_8_fu_13710_p2);
assign tmp919_fu_13764_p2 = (rhs_i38_0_i_7_fu_13758_p2 & tmp_1802_fu_13300_p3);
assign tmp91_fu_6598_p3 = {{tmp_1512_fu_6590_p3}, {tmp_247_fu_6584_p2}};
assign tmp920_fu_13770_p2 = (tmp919_fu_13764_p2 | rhs_i44_0_i_8_fu_13722_p2);
assign tmp921_fu_13782_p2 = (tmp_1804_fu_13316_p3 | tmp_1805_fu_13324_p3);
assign tmp922_fu_13842_p2 = (tmp_1399_8_fu_13838_p1 + tmp_1397_8_fu_13810_p1);
assign tmp923_fu_13978_p2 = (tmp_1824_fu_13910_p1 ^ tmp_1823_fu_13902_p3);
assign tmp924_fu_13984_p2 = (tmp_1821_fu_13886_p3 ^ tmp_1822_fu_13894_p3);
assign tmp925_fu_14038_p2 = (lhs_i_i141_0_i_9_fu_14026_p2 & rhs_i_i140_0_i_9_fu_14032_p2);
assign tmp926_fu_14050_p2 = (lhs_i_i135_0_i_9_fu_14044_p2 & rhs_i_i140_0_i_9_fu_14032_p2);
assign tmp927_fu_14074_p2 = (tmp_1823_fu_13902_p3 & rhs_i138_0_i_8_fu_14068_p2);
assign tmp928_fu_14080_p2 = (tmp927_fu_14074_p2 | lhs_i143_0_i_9_fu_14008_p2);
assign tmp929_fu_14086_p2 = (rhs_i_i140_0_i_9_fu_14032_p2 | lhs_i_i135_0_i_9_fu_14044_p2);
assign tmp92_fu_6624_p3 = {{tmp_1514_fu_6616_p3}, {tmp_248_fu_6610_p2}};
assign tmp930_fu_14098_p2 = (rhs_i126_0_i_8_fu_14092_p2 & tmp_1821_fu_13886_p3);
assign tmp931_fu_14104_p2 = (tmp930_fu_14098_p2 | rhs_i132_0_i_9_fu_14056_p2);
assign tmp932_fu_14116_p2 = (tmp_1823_fu_13902_p3 | tmp_1824_fu_13910_p1);
assign tmp933_fu_14134_p2 = (tmp_1828_fu_13938_p3 ^ tmp_1827_fu_13930_p3);
assign tmp934_fu_14140_p2 = (tmp_1825_fu_13914_p3 ^ tmp_1826_fu_13922_p3);
assign tmp935_fu_14194_p2 = (lhs_i_i97_0_i_9_fu_14182_p2 & rhs_i_i96_0_i_9_fu_14188_p2);
assign tmp936_fu_14206_p2 = (lhs_i_i91_0_i_9_fu_14200_p2 & rhs_i_i96_0_i_9_fu_14188_p2);
assign tmp937_fu_14230_p2 = (tmp_1827_fu_13930_p3 & rhs_i94_0_i_8_fu_14224_p2);
assign tmp938_fu_14236_p2 = (tmp937_fu_14230_p2 | lhs_i99_0_i_9_fu_14164_p2);
assign tmp939_fu_14242_p2 = (rhs_i_i96_0_i_9_fu_14188_p2 | lhs_i_i91_0_i_9_fu_14200_p2);
assign tmp93_fu_6632_p2 = (tmp92_fu_6624_p3 | tmp91_fu_6598_p3);
assign tmp940_fu_14254_p2 = (rhs_i82_0_i_8_fu_14248_p2 & tmp_1825_fu_13914_p3);
assign tmp941_fu_14260_p2 = (tmp940_fu_14254_p2 | rhs_i88_0_i_9_fu_14212_p2);
assign tmp942_fu_14272_p2 = (tmp_1827_fu_13930_p3 | tmp_1828_fu_13938_p3);
assign tmp943_fu_14290_p2 = (tmp_1832_fu_13970_p3 ^ tmp_1831_fu_13962_p3);
assign tmp944_fu_14296_p2 = (tmp_1829_fu_13946_p3 ^ tmp_1830_fu_13954_p3);
assign tmp945_fu_14350_p2 = (lhs_i_i53_0_i_9_fu_14338_p2 & rhs_i_i52_0_i_9_fu_14344_p2);
assign tmp946_fu_14362_p2 = (lhs_i_i47_0_i_9_fu_14356_p2 & rhs_i_i52_0_i_9_fu_14344_p2);
assign tmp947_fu_14386_p2 = (tmp_1831_fu_13962_p3 & rhs_i50_0_i1_8_fu_14380_p2);
assign tmp948_fu_14392_p2 = (tmp947_fu_14386_p2 | lhs_i55_0_i_9_fu_14320_p2);
assign tmp949_fu_14398_p2 = (rhs_i_i52_0_i_9_fu_14344_p2 | lhs_i_i47_0_i_9_fu_14356_p2);
assign tmp94_fu_6638_p2 = (kill1_t_V_8_9_fu_6492_p3 | kill1_t_V_7_9_fu_6444_p3);
assign tmp950_fu_14410_p2 = (rhs_i38_0_i_8_fu_14404_p2 & tmp_1829_fu_13946_p3);
assign tmp951_fu_14416_p2 = (tmp950_fu_14410_p2 | rhs_i44_0_i_9_fu_14368_p2);
assign tmp952_fu_14428_p2 = (tmp_1831_fu_13962_p3 | tmp_1832_fu_13970_p3);
assign tmp953_fu_14488_p2 = (tmp_1399_9_fu_14484_p1 + tmp_1397_9_fu_14456_p1);
assign tmp954_fu_14624_p2 = (tmp_1851_fu_14556_p1 ^ tmp_1850_fu_14548_p3);
assign tmp955_fu_14630_p2 = (tmp_1848_fu_14532_p3 ^ tmp_1849_fu_14540_p3);
assign tmp956_fu_14684_p2 = (lhs_i_i141_0_i_s_fu_14672_p2 & rhs_i_i140_0_i_s_fu_14678_p2);
assign tmp957_fu_14696_p2 = (lhs_i_i135_0_i_s_fu_14690_p2 & rhs_i_i140_0_i_s_fu_14678_p2);
assign tmp958_fu_14720_p2 = (tmp_1850_fu_14548_p3 & rhs_i138_0_i_9_fu_14714_p2);
assign tmp959_fu_14726_p2 = (tmp958_fu_14720_p2 | lhs_i143_0_i_s_fu_14654_p2);
assign tmp95_fu_6686_p3 = {{tmp_252_fu_6676_p4}, {tmp_251_fu_6670_p2}};
assign tmp960_fu_14732_p2 = (rhs_i_i140_0_i_s_fu_14678_p2 | lhs_i_i135_0_i_s_fu_14690_p2);
assign tmp961_fu_14744_p2 = (rhs_i126_0_i_9_fu_14738_p2 & tmp_1848_fu_14532_p3);
assign tmp962_fu_14750_p2 = (tmp961_fu_14744_p2 | rhs_i132_0_i_s_fu_14702_p2);
assign tmp963_fu_14762_p2 = (tmp_1850_fu_14548_p3 | tmp_1851_fu_14556_p1);
assign tmp964_fu_14780_p2 = (tmp_1855_fu_14584_p3 ^ tmp_1854_fu_14576_p3);
assign tmp965_fu_14786_p2 = (tmp_1852_fu_14560_p3 ^ tmp_1853_fu_14568_p3);
assign tmp966_fu_14840_p2 = (lhs_i_i97_0_i_s_fu_14828_p2 & rhs_i_i96_0_i_s_fu_14834_p2);
assign tmp967_fu_14852_p2 = (lhs_i_i91_0_i_s_fu_14846_p2 & rhs_i_i96_0_i_s_fu_14834_p2);
assign tmp968_fu_14876_p2 = (tmp_1854_fu_14576_p3 & rhs_i94_0_i_9_fu_14870_p2);
assign tmp969_fu_14882_p2 = (tmp968_fu_14876_p2 | lhs_i99_0_i_s_fu_14810_p2);
assign tmp96_fu_6694_p2 = (tmp95_fu_6686_p3 | tmp93_fu_6632_p2);
assign tmp970_fu_14888_p2 = (rhs_i_i96_0_i_s_fu_14834_p2 | lhs_i_i91_0_i_s_fu_14846_p2);
assign tmp971_fu_14900_p2 = (rhs_i82_0_i_9_fu_14894_p2 & tmp_1852_fu_14560_p3);
assign tmp972_fu_14906_p2 = (tmp971_fu_14900_p2 | rhs_i88_0_i_s_fu_14858_p2);
assign tmp973_fu_14918_p2 = (tmp_1854_fu_14576_p3 | tmp_1855_fu_14584_p3);
assign tmp974_fu_14936_p2 = (tmp_1859_fu_14616_p3 ^ tmp_1858_fu_14608_p3);
assign tmp975_fu_14942_p2 = (tmp_1856_fu_14592_p3 ^ tmp_1857_fu_14600_p3);
assign tmp976_fu_14996_p2 = (lhs_i_i53_0_i_s_fu_14984_p2 & rhs_i_i52_0_i_s_fu_14990_p2);
assign tmp977_fu_15008_p2 = (lhs_i_i47_0_i_s_fu_15002_p2 & rhs_i_i52_0_i_s_fu_14990_p2);
assign tmp978_fu_15032_p2 = (tmp_1858_fu_14608_p3 & rhs_i50_0_i1_9_fu_15026_p2);
assign tmp979_fu_15038_p2 = (tmp978_fu_15032_p2 | lhs_i55_0_i_s_fu_14966_p2);
assign tmp97_fu_6700_p2 = (kill1_t_V_7_s_fu_6460_p3 | kill1_t_V_5_s_fu_6316_p3);
assign tmp980_fu_15044_p2 = (rhs_i_i52_0_i_s_fu_14990_p2 | lhs_i_i47_0_i_s_fu_15002_p2);
assign tmp981_fu_15056_p2 = (rhs_i38_0_i_9_fu_15050_p2 & tmp_1856_fu_14592_p3);
assign tmp982_fu_15062_p2 = (tmp981_fu_15056_p2 | rhs_i44_0_i_s_fu_15014_p2);
assign tmp983_fu_15074_p2 = (tmp_1858_fu_14608_p3 | tmp_1859_fu_14616_p3);
assign tmp984_fu_15134_p2 = (tmp_1399_s_fu_15130_p1 + tmp_1397_s_fu_15102_p1);
assign tmp985_fu_15270_p2 = (tmp_1878_fu_15202_p1 ^ tmp_1877_fu_15194_p3);
assign tmp986_fu_15276_p2 = (tmp_1875_fu_15178_p3 ^ tmp_1876_fu_15186_p3);
assign tmp987_fu_15330_p2 = (lhs_i_i141_0_i_10_fu_15318_p2 & rhs_i_i140_0_i_10_fu_15324_p2);
assign tmp988_fu_15342_p2 = (lhs_i_i135_0_i_10_fu_15336_p2 & rhs_i_i140_0_i_10_fu_15324_p2);
assign tmp989_fu_15366_p2 = (tmp_1877_fu_15194_p3 & rhs_i138_0_i_10_fu_15360_p2);
assign tmp98_fu_6726_p3 = {{tmp_254_fu_6716_p4}, {tmp_253_fu_6710_p2}};
assign tmp990_fu_15372_p2 = (tmp989_fu_15366_p2 | lhs_i143_0_i_10_fu_15300_p2);
assign tmp991_fu_15378_p2 = (rhs_i_i140_0_i_10_fu_15324_p2 | lhs_i_i135_0_i_10_fu_15336_p2);
assign tmp992_fu_15390_p2 = (rhs_i126_0_i_10_fu_15384_p2 & tmp_1875_fu_15178_p3);
assign tmp993_fu_15396_p2 = (tmp992_fu_15390_p2 | rhs_i132_0_i_10_fu_15348_p2);
assign tmp994_fu_15408_p2 = (tmp_1877_fu_15194_p3 | tmp_1878_fu_15202_p1);
assign tmp995_fu_15426_p2 = (tmp_1882_fu_15230_p3 ^ tmp_1881_fu_15222_p3);
assign tmp996_fu_15432_p2 = (tmp_1879_fu_15206_p3 ^ tmp_1880_fu_15214_p3);
assign tmp997_fu_15486_p2 = (lhs_i_i97_0_i_10_fu_15474_p2 & rhs_i_i96_0_i_10_fu_15480_p2);
assign tmp998_fu_15498_p2 = (lhs_i_i91_0_i_10_fu_15492_p2 & rhs_i_i96_0_i_10_fu_15480_p2);
assign tmp999_fu_15522_p2 = (tmp_1881_fu_15222_p3 & rhs_i94_0_i_10_fu_15516_p2);
assign tmp99_fu_6752_p3 = {{tmp_1519_fu_6744_p3}, {tmp_255_fu_6738_p2}};
assign tmp_1256_fu_2780_p3 = {{1'b1}, {p_cast_fu_2758_p3}};
always @ (*) begin
tmp_1258_fu_2806_p4 = p_Val2_388_0_3_fu_2792_p3;
tmp_1258_fu_2806_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
tmp_1259_fu_2830_p4 = p_Val2_388_0_4_fu_2816_p3;
tmp_1259_fu_2830_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
tmp_1272_fu_2854_p4 = p_Val2_388_0_5_fu_2840_p3;
tmp_1272_fu_2854_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
tmp_1276_fu_2878_p4 = p_Val2_388_0_6_fu_2864_p3;
tmp_1276_fu_2878_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1277_fu_2902_p4 = p_Val2_388_0_7_fu_2888_p3;
tmp_1277_fu_2902_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1279_fu_2926_p4 = p_Val2_388_0_8_fu_2912_p3;
tmp_1279_fu_2926_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
tmp_1281_fu_2950_p4 = p_Val2_388_0_9_fu_2936_p3;
tmp_1281_fu_2950_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1283_fu_2974_p4 = p_Val2_388_0_s_fu_2960_p3;
tmp_1283_fu_2974_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1285_fu_2998_p4 = p_Val2_388_0_1_fu_2984_p3;
tmp_1285_fu_2998_p4[ap_const_lv32_B] = |(1'b1);
end
assign tmp_1298_fu_3044_p3 = {{1'b1}, {p_12_cast_fu_3022_p3}};
always @ (*) begin
tmp_1302_fu_3070_p4 = p_Val2_388_1_3_fu_3056_p3;
tmp_1302_fu_3070_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
tmp_1303_fu_3094_p4 = p_Val2_388_1_4_fu_3080_p3;
tmp_1303_fu_3094_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
tmp_1305_fu_3118_p4 = p_Val2_388_1_5_fu_3104_p3;
tmp_1305_fu_3118_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
tmp_1308_fu_3142_p4 = p_Val2_388_1_6_fu_3128_p3;
tmp_1308_fu_3142_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1322_fu_3166_p4 = p_Val2_388_1_7_fu_3152_p3;
tmp_1322_fu_3166_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1325_fu_3190_p4 = p_Val2_388_1_8_fu_3176_p3;
tmp_1325_fu_3190_p4[ap_const_lv32_8] = |(1'b1);
end
assign tmp_1333_10_fu_5490_p2 = ((rank_3_2_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_1_fu_3280_p2 = ((rank_1_0_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_2_fu_3528_p2 = ((rank_2_0_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_3_fu_3770_p2 = ((rank_3_0_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_4_fu_4006_p2 = ((rank_0_1_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_5_fu_4236_p2 = ((rank_1_1_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_6_fu_4460_p2 = ((rank_2_1_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_7_fu_4678_p2 = ((rank_3_1_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_8_fu_4890_p2 = ((rank_0_2_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_9_fu_5096_p2 = ((rank_1_2_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1333_s_fu_5296_p2 = ((rank_2_2_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign tmp_1339_0_10_fu_2992_p2 = ((rank_0_0_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_1_fu_2752_p2 = ((rank_0_0_V_read < rank_1_0_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_2_fu_2774_p2 = ((rank_0_0_V_read < rank_2_0_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_3_fu_2800_p2 = ((rank_0_0_V_read < rank_3_0_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_4_fu_2824_p2 = ((rank_0_0_V_read < rank_0_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_5_fu_2848_p2 = ((rank_0_0_V_read < rank_1_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_6_fu_2872_p2 = ((rank_0_0_V_read < rank_2_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_7_fu_2896_p2 = ((rank_0_0_V_read < rank_3_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_8_fu_2920_p2 = ((rank_0_0_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_9_fu_2944_p2 = ((rank_0_0_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_0_s_fu_2968_p2 = ((rank_0_0_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_10_s_fu_5272_p2 = ((rank_2_2_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_1_fu_3256_p2 = ((rank_1_0_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_2_fu_3038_p2 = ((rank_1_0_V_read < rank_2_0_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_3_fu_3064_p2 = ((rank_1_0_V_read < rank_3_0_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_4_fu_3088_p2 = ((rank_1_0_V_read < rank_0_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_5_fu_3112_p2 = ((rank_1_0_V_read < rank_1_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_6_fu_3136_p2 = ((rank_1_0_V_read < rank_2_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_7_fu_3160_p2 = ((rank_1_0_V_read < rank_3_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_8_fu_3184_p2 = ((rank_1_0_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_9_fu_3208_p2 = ((rank_1_0_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_1_s_fu_3232_p2 = ((rank_1_0_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_1_fu_3504_p2 = ((rank_2_0_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_3_fu_3312_p2 = ((rank_2_0_V_read < rank_3_0_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_4_fu_3336_p2 = ((rank_2_0_V_read < rank_0_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_5_fu_3360_p2 = ((rank_2_0_V_read < rank_1_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_6_fu_3384_p2 = ((rank_2_0_V_read < rank_2_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_7_fu_3408_p2 = ((rank_2_0_V_read < rank_3_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_8_fu_3432_p2 = ((rank_2_0_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_9_fu_3456_p2 = ((rank_2_0_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_2_s_fu_3480_p2 = ((rank_2_0_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_1_fu_3746_p2 = ((rank_3_0_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_4_fu_3578_p2 = ((rank_3_0_V_read < rank_0_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_5_fu_3602_p2 = ((rank_3_0_V_read < rank_1_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_6_fu_3626_p2 = ((rank_3_0_V_read < rank_2_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_7_fu_3650_p2 = ((rank_3_0_V_read < rank_3_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_8_fu_3674_p2 = ((rank_3_0_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_9_fu_3698_p2 = ((rank_3_0_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_3_s_fu_3722_p2 = ((rank_3_0_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_4_1_fu_3982_p2 = ((rank_0_1_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_4_5_fu_3838_p2 = ((rank_0_1_V_read < rank_1_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_4_6_fu_3862_p2 = ((rank_0_1_V_read < rank_2_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_4_7_fu_3886_p2 = ((rank_0_1_V_read < rank_3_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_4_8_fu_3910_p2 = ((rank_0_1_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_4_9_fu_3934_p2 = ((rank_0_1_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_4_s_fu_3958_p2 = ((rank_0_1_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_5_1_fu_4212_p2 = ((rank_1_1_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_5_6_fu_4092_p2 = ((rank_1_1_V_read < rank_2_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_5_7_fu_4116_p2 = ((rank_1_1_V_read < rank_3_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_5_8_fu_4140_p2 = ((rank_1_1_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_5_9_fu_4164_p2 = ((rank_1_1_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_5_s_fu_4188_p2 = ((rank_1_1_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_6_1_fu_4436_p2 = ((rank_2_1_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_6_7_fu_4340_p2 = ((rank_2_1_V_read < rank_3_1_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_6_8_fu_4364_p2 = ((rank_2_1_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_6_9_fu_4388_p2 = ((rank_2_1_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_6_s_fu_4412_p2 = ((rank_2_1_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_7_1_fu_4654_p2 = ((rank_3_1_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_7_8_fu_4582_p2 = ((rank_3_1_V_read < rank_0_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_7_9_fu_4606_p2 = ((rank_3_1_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_7_s_fu_4630_p2 = ((rank_3_1_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_8_1_fu_4866_p2 = ((rank_0_2_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_8_9_fu_4818_p2 = ((rank_0_2_V_read < rank_1_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_8_s_fu_4842_p2 = ((rank_0_2_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_9_1_fu_5072_p2 = ((rank_1_2_V_read < rank_3_2_V_read) ? 1'b1 : 1'b0);
assign tmp_1339_9_s_fu_5048_p2 = ((rank_1_2_V_read < rank_2_2_V_read) ? 1'b1 : 1'b0);
always @ (*) begin
tmp_1339_fu_3214_p4 = p_Val2_388_1_9_fu_3200_p3;
tmp_1339_fu_3214_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1342_fu_3238_p4 = p_Val2_388_1_s_fu_3224_p3;
tmp_1342_fu_3238_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1344_fu_3262_p4 = p_Val2_388_1_1_fu_3248_p3;
tmp_1344_fu_3262_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
tmp_1345_fu_3294_p4 = p_13_cast_cast_fu_3286_p3;
tmp_1345_fu_3294_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_1346_fu_3318_p4 = p_Val2_388_2_3_fu_3304_p3;
tmp_1346_fu_3318_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
tmp_1347_fu_3342_p4 = p_Val2_388_2_4_fu_3328_p3;
tmp_1347_fu_3342_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
tmp_1348_fu_3366_p4 = p_Val2_388_2_5_fu_3352_p3;
tmp_1348_fu_3366_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
tmp_1349_fu_3390_p4 = p_Val2_388_2_6_fu_3376_p3;
tmp_1349_fu_3390_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1350_fu_3414_p4 = p_Val2_388_2_7_fu_3400_p3;
tmp_1350_fu_3414_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1351_fu_3438_p4 = p_Val2_388_2_8_fu_3424_p3;
tmp_1351_fu_3438_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
tmp_1352_fu_3462_p4 = p_Val2_388_2_9_fu_3448_p3;
tmp_1352_fu_3462_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1353_fu_3486_p4 = p_Val2_388_2_s_fu_3472_p3;
tmp_1353_fu_3486_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1354_fu_3510_p4 = p_Val2_388_2_1_fu_3496_p3;
tmp_1354_fu_3510_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
tmp_1355_fu_3542_p4 = p_14_cast_cast_fu_3534_p3;
tmp_1355_fu_3542_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_1356_fu_3560_p4 = p_Val2_388_3_2_fu_3552_p3;
tmp_1356_fu_3560_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_1357_fu_3584_p4 = p_Val2_388_3_4_fu_3570_p3;
tmp_1357_fu_3584_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
tmp_1358_fu_3608_p4 = p_Val2_388_3_5_fu_3594_p3;
tmp_1358_fu_3608_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
tmp_1359_fu_3632_p4 = p_Val2_388_3_6_fu_3618_p3;
tmp_1359_fu_3632_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1360_fu_3656_p4 = p_Val2_388_3_7_fu_3642_p3;
tmp_1360_fu_3656_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1361_fu_3680_p4 = p_Val2_388_3_8_fu_3666_p3;
tmp_1361_fu_3680_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
tmp_1362_fu_3704_p4 = p_Val2_388_3_9_fu_3690_p3;
tmp_1362_fu_3704_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1363_fu_3728_p4 = p_Val2_388_3_s_fu_3714_p3;
tmp_1363_fu_3728_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1364_fu_3752_p4 = p_Val2_388_3_1_fu_3738_p3;
tmp_1364_fu_3752_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
tmp_1365_fu_3784_p4 = p_15_cast_cast_fu_3776_p3;
tmp_1365_fu_3784_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_1366_fu_3802_p4 = p_Val2_388_4_2_fu_3794_p3;
tmp_1366_fu_3802_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_1367_fu_3820_p4 = p_Val2_388_4_3_fu_3812_p3;
tmp_1367_fu_3820_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
tmp_1368_fu_3844_p4 = p_Val2_388_4_5_fu_3830_p3;
tmp_1368_fu_3844_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
tmp_1369_fu_3868_p4 = p_Val2_388_4_6_fu_3854_p3;
tmp_1369_fu_3868_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1370_fu_3892_p4 = p_Val2_388_4_7_fu_3878_p3;
tmp_1370_fu_3892_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1371_fu_3916_p4 = p_Val2_388_4_8_fu_3902_p3;
tmp_1371_fu_3916_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
tmp_1372_fu_3940_p4 = p_Val2_388_4_9_fu_3926_p3;
tmp_1372_fu_3940_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1373_fu_3964_p4 = p_Val2_388_4_s_fu_3950_p3;
tmp_1373_fu_3964_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1374_fu_3988_p4 = p_Val2_388_4_1_fu_3974_p3;
tmp_1374_fu_3988_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
tmp_1375_fu_4020_p4 = p_16_cast_cast_fu_4012_p3;
tmp_1375_fu_4020_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_1376_fu_4038_p4 = p_Val2_388_5_2_fu_4030_p3;
tmp_1376_fu_4038_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_1377_fu_4056_p4 = p_Val2_388_5_3_fu_4048_p3;
tmp_1377_fu_4056_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
tmp_1378_fu_4074_p4 = p_Val2_388_5_4_fu_4066_p3;
tmp_1378_fu_4074_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
tmp_1379_fu_4098_p4 = p_Val2_388_5_6_fu_4084_p3;
tmp_1379_fu_4098_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1380_fu_4122_p4 = p_Val2_388_5_7_fu_4108_p3;
tmp_1380_fu_4122_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1381_fu_4146_p4 = p_Val2_388_5_8_fu_4132_p3;
tmp_1381_fu_4146_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
tmp_1382_fu_4170_p4 = p_Val2_388_5_9_fu_4156_p3;
tmp_1382_fu_4170_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1383_fu_4194_p4 = p_Val2_388_5_s_fu_4180_p3;
tmp_1383_fu_4194_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1384_fu_4218_p4 = p_Val2_388_5_1_fu_4204_p3;
tmp_1384_fu_4218_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
tmp_1385_fu_4250_p4 = p_17_cast_cast_fu_4242_p3;
tmp_1385_fu_4250_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_1386_fu_4268_p4 = p_Val2_388_6_2_fu_4260_p3;
tmp_1386_fu_4268_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_1387_fu_4286_p4 = p_Val2_388_6_3_fu_4278_p3;
tmp_1387_fu_4286_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
tmp_1388_fu_4304_p4 = p_Val2_388_6_4_fu_4296_p3;
tmp_1388_fu_4304_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
tmp_1389_fu_4322_p4 = p_Val2_388_6_5_fu_4314_p3;
tmp_1389_fu_4322_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
tmp_1390_fu_4346_p4 = p_Val2_388_6_7_fu_4332_p3;
tmp_1390_fu_4346_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1391_fu_4370_p4 = p_Val2_388_6_8_fu_4356_p3;
tmp_1391_fu_4370_p4[ap_const_lv32_8] = |(1'b1);
end
always @ (*) begin
tmp_1392_fu_4394_p4 = p_Val2_388_6_9_fu_4380_p3;
tmp_1392_fu_4394_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1393_fu_4418_p4 = p_Val2_388_6_s_fu_4404_p3;
tmp_1393_fu_4418_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1394_fu_4442_p4 = p_Val2_388_6_1_fu_4428_p3;
tmp_1394_fu_4442_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
tmp_1395_fu_4474_p4 = p_18_cast_cast_fu_4466_p3;
tmp_1395_fu_4474_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_1396_fu_4492_p4 = p_Val2_388_7_2_fu_4484_p3;
tmp_1396_fu_4492_p4[ap_const_lv32_2] = |(1'b1);
end
assign tmp_1397_10_fu_15748_p1 = p_Result_1303_10_fu_15738_p4;
assign tmp_1397_1_fu_9258_p1 = p_Result_1303_1_fu_9248_p4;
assign tmp_1397_2_fu_9934_p1 = p_Result_1303_2_fu_9924_p4;
assign tmp_1397_3_fu_10580_p1 = p_Result_1303_3_fu_10570_p4;
assign tmp_1397_4_fu_11226_p1 = p_Result_1303_4_fu_11216_p4;
assign tmp_1397_5_fu_11872_p1 = p_Result_1303_5_fu_11862_p4;
assign tmp_1397_6_fu_12518_p1 = p_Result_1303_6_fu_12508_p4;
assign tmp_1397_7_fu_13164_p1 = p_Result_1303_7_fu_13154_p4;
assign tmp_1397_8_fu_13810_p1 = p_Result_1303_8_fu_13800_p4;
assign tmp_1397_9_fu_14456_p1 = p_Result_1303_9_fu_14446_p4;
always @ (*) begin
tmp_1397_fu_4510_p4 = p_Val2_388_7_3_fu_4502_p3;
tmp_1397_fu_4510_p4[ap_const_lv32_3] = |(1'b1);
end
assign tmp_1397_s_fu_15102_p1 = p_Result_1303_s_fu_15092_p4;
assign tmp_1398_10_fu_15762_p1 = p_Result_1307_10_fu_15752_p4;
assign tmp_1398_1_fu_9272_p1 = p_Result_1307_1_fu_9262_p4;
assign tmp_1398_2_fu_9948_p1 = p_Result_1307_2_fu_9938_p4;
assign tmp_1398_3_fu_10594_p1 = p_Result_1307_3_fu_10584_p4;
assign tmp_1398_4_fu_11240_p1 = p_Result_1307_4_fu_11230_p4;
assign tmp_1398_5_fu_11886_p1 = p_Result_1307_5_fu_11876_p4;
assign tmp_1398_6_fu_12532_p1 = p_Result_1307_6_fu_12522_p4;
assign tmp_1398_7_fu_13178_p1 = p_Result_1307_7_fu_13168_p4;
assign tmp_1398_8_fu_13824_p1 = p_Result_1307_8_fu_13814_p4;
assign tmp_1398_9_fu_14470_p1 = p_Result_1307_9_fu_14460_p4;
always @ (*) begin
tmp_1398_fu_4528_p4 = p_Val2_388_7_4_fu_4520_p3;
tmp_1398_fu_4528_p4[ap_const_lv32_4] = |(1'b1);
end
assign tmp_1398_s_fu_15116_p1 = p_Result_1307_s_fu_15106_p4;
assign tmp_1399_10_fu_15776_p1 = p_Result_1311_10_fu_15766_p4;
assign tmp_1399_1_fu_9286_p1 = p_Result_1311_1_fu_9276_p4;
assign tmp_1399_2_fu_9962_p1 = p_Result_1311_2_fu_9952_p4;
assign tmp_1399_3_fu_10608_p1 = p_Result_1311_3_fu_10598_p4;
assign tmp_1399_4_fu_11254_p1 = p_Result_1311_4_fu_11244_p4;
assign tmp_1399_5_fu_11900_p1 = p_Result_1311_5_fu_11890_p4;
assign tmp_1399_6_fu_12546_p1 = p_Result_1311_6_fu_12536_p4;
assign tmp_1399_7_fu_13192_p1 = p_Result_1311_7_fu_13182_p4;
assign tmp_1399_8_fu_13838_p1 = p_Result_1311_8_fu_13828_p4;
assign tmp_1399_9_fu_14484_p1 = p_Result_1311_9_fu_14474_p4;
always @ (*) begin
tmp_1399_fu_4546_p4 = p_Val2_388_7_5_fu_4538_p3;
tmp_1399_fu_4546_p4[ap_const_lv32_5] = |(1'b1);
end
assign tmp_1399_s_fu_15130_p1 = p_Result_1311_s_fu_15120_p4;
always @ (*) begin
tmp_1400_fu_4564_p4 = p_Val2_388_7_6_fu_4556_p3;
tmp_1400_fu_4564_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1401_fu_4588_p4 = p_Val2_388_7_8_fu_4574_p3;
tmp_1401_fu_4588_p4[ap_const_lv32_8] = |(1'b1);
end
assign tmp_1402_10_fu_15792_p2 = ((p_0190_i_10_fu_15786_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_1_fu_9302_p2 = ((p_0190_i_1_fu_9296_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_2_fu_9978_p2 = ((p_0190_i_2_fu_9972_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_3_fu_10624_p2 = ((p_0190_i_3_fu_10618_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_4_fu_11270_p2 = ((p_0190_i_4_fu_11264_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_5_fu_11916_p2 = ((p_0190_i_5_fu_11910_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_6_fu_12562_p2 = ((p_0190_i_6_fu_12556_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_7_fu_13208_p2 = ((p_0190_i_7_fu_13202_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_8_fu_13854_p2 = ((p_0190_i_8_fu_13848_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_1402_9_fu_14500_p2 = ((p_0190_i_9_fu_14494_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
always @ (*) begin
tmp_1402_fu_4612_p4 = p_Val2_388_7_9_fu_4598_p3;
tmp_1402_fu_4612_p4[ap_const_lv32_9] = |(1'b1);
end
assign tmp_1402_s_fu_15146_p2 = ((p_0190_i_s_fu_15140_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
always @ (*) begin
tmp_1403_fu_4636_p4 = p_Val2_388_7_s_fu_4622_p3;
tmp_1403_fu_4636_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1404_fu_4660_p4 = p_Val2_388_7_1_fu_4646_p3;
tmp_1404_fu_4660_p4[ap_const_lv32_B] = |(1'b1);
end
always @ (*) begin
tmp_1405_fu_4692_p4 = p_19_cast_cast_fu_4684_p3;
tmp_1405_fu_4692_p4[ap_const_lv32_1] = |(1'b1);
end
always @ (*) begin
tmp_1406_fu_4710_p4 = p_Val2_388_8_2_fu_4702_p3;
tmp_1406_fu_4710_p4[ap_const_lv32_2] = |(1'b1);
end
always @ (*) begin
tmp_1407_fu_4728_p4 = p_Val2_388_8_3_fu_4720_p3;
tmp_1407_fu_4728_p4[ap_const_lv32_3] = |(1'b1);
end
always @ (*) begin
tmp_1408_fu_4746_p4 = p_Val2_388_8_4_fu_4738_p3;
tmp_1408_fu_4746_p4[ap_const_lv32_4] = |(1'b1);
end
always @ (*) begin
tmp_1409_fu_4764_p4 = p_Val2_388_8_5_fu_4756_p3;
tmp_1409_fu_4764_p4[ap_const_lv32_5] = |(1'b1);
end
always @ (*) begin
tmp_1410_fu_4782_p4 = p_Val2_388_8_6_fu_4774_p3;
tmp_1410_fu_4782_p4[ap_const_lv32_6] = |(1'b1);
end
always @ (*) begin
tmp_1411_fu_4800_p4 = p_Val2_388_8_7_fu_4792_p3;
tmp_1411_fu_4800_p4[ap_const_lv32_7] = |(1'b1);
end
always @ (*) begin
tmp_1412_fu_4824_p4 = p_Val2_388_8_9_fu_4810_p3;
tmp_1412_fu_4824_p4[ap_const_lv32_9] = |(1'b1);
end
always @ (*) begin
tmp_1413_fu_4848_p4 = p_Val2_388_8_s_fu_4834_p3;
tmp_1413_fu_4848_p4[ap_const_lv32_A] = |(1'b1);
end
always @ (*) begin
tmp_1414_fu_4872_p4 = p_Val2_388_8_1_fu_4858_p3;
tmp_1414_fu_4872_p4[ap_const_lv32_B] = |(1'b1);
end
assign tmp_1445_fu_5524_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_1];
assign tmp_1446_fu_5540_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_2];
assign tmp_1447_fu_5556_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_3];
assign tmp_1448_fu_5572_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_4];
assign tmp_1449_fu_5588_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_5];
assign tmp_1450_fu_5604_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_6];
assign tmp_1451_fu_5620_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_7];
assign tmp_1452_fu_5636_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_8];
assign tmp_1453_fu_5652_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_9];
assign tmp_1454_fu_5668_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_A];
assign tmp_1455_fu_5684_p3 = larger_V_load_fu_3008_p3[ap_const_lv32_B];
assign tmp_1456_fu_5700_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_2];
assign tmp_1457_fu_5716_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_3];
assign tmp_1458_fu_5732_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_4];
assign tmp_1459_fu_5748_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_5];
assign tmp_1460_fu_5764_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_6];
assign tmp_1461_fu_5780_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_7];
assign tmp_1462_fu_5796_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_8];
assign tmp_1463_fu_5812_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_9];
assign tmp_1464_fu_5828_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_A];
assign tmp_1465_fu_5844_p3 = p_Val2_393_1_fu_3272_p3[ap_const_lv32_B];
assign tmp_1466_fu_5860_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_3];
assign tmp_1467_fu_5876_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_4];
assign tmp_1468_fu_5892_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_5];
assign tmp_1469_fu_5908_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_6];
assign tmp_1470_fu_5924_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_7];
assign tmp_1471_fu_5940_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_8];
assign tmp_1472_fu_5956_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_9];
assign tmp_1473_fu_5972_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_A];
assign tmp_1474_fu_5988_p3 = p_Val2_393_2_fu_3520_p3[ap_const_lv32_B];
assign tmp_1475_fu_6004_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_4];
assign tmp_1476_fu_6020_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_5];
assign tmp_1477_fu_6036_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_6];
assign tmp_1478_fu_6052_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_7];
assign tmp_1479_fu_6068_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_8];
assign tmp_1480_fu_6084_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_9];
assign tmp_1481_fu_6100_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_A];
assign tmp_1482_fu_6116_p3 = p_Val2_393_3_fu_3762_p3[ap_const_lv32_B];
assign tmp_1483_fu_6132_p3 = p_Val2_393_4_fu_3998_p3[ap_const_lv32_5];
assign tmp_1484_fu_6148_p3 = p_Val2_393_4_fu_3998_p3[ap_const_lv32_6];
assign tmp_1485_fu_6164_p3 = p_Val2_393_4_fu_3998_p3[ap_const_lv32_7];
assign tmp_1486_fu_6180_p3 = p_Val2_393_4_fu_3998_p3[ap_const_lv32_8];
assign tmp_1487_fu_6196_p3 = p_Val2_393_4_fu_3998_p3[ap_const_lv32_9];
assign tmp_1488_fu_6212_p3 = p_Val2_393_4_fu_3998_p3[ap_const_lv32_A];
assign tmp_1489_fu_6228_p3 = p_Val2_393_4_fu_3998_p3[ap_const_lv32_B];
assign tmp_1490_fu_6244_p3 = p_Val2_393_5_fu_4228_p3[ap_const_lv32_6];
assign tmp_1491_fu_6260_p3 = p_Val2_393_5_fu_4228_p3[ap_const_lv32_7];
assign tmp_1492_fu_6276_p3 = p_Val2_393_5_fu_4228_p3[ap_const_lv32_8];
assign tmp_1493_fu_6292_p3 = p_Val2_393_5_fu_4228_p3[ap_const_lv32_9];
assign tmp_1494_fu_6308_p3 = p_Val2_393_5_fu_4228_p3[ap_const_lv32_A];
assign tmp_1495_fu_6324_p3 = p_Val2_393_5_fu_4228_p3[ap_const_lv32_B];
assign tmp_1496_fu_6340_p3 = p_Val2_393_6_fu_4452_p3[ap_const_lv32_7];
assign tmp_1497_fu_6356_p3 = p_Val2_393_6_fu_4452_p3[ap_const_lv32_8];
assign tmp_1498_fu_6372_p3 = p_Val2_393_6_fu_4452_p3[ap_const_lv32_9];
assign tmp_1499_fu_6388_p3 = p_Val2_393_6_fu_4452_p3[ap_const_lv32_A];
assign tmp_1500_fu_6404_p3 = p_Val2_393_6_fu_4452_p3[ap_const_lv32_B];
assign tmp_1501_fu_6420_p3 = p_Val2_393_7_fu_4670_p3[ap_const_lv32_8];
assign tmp_1502_fu_6436_p3 = p_Val2_393_7_fu_4670_p3[ap_const_lv32_9];
assign tmp_1503_fu_6452_p3 = p_Val2_393_7_fu_4670_p3[ap_const_lv32_A];
assign tmp_1504_fu_6468_p3 = p_Val2_393_7_fu_4670_p3[ap_const_lv32_B];
assign tmp_1505_fu_6484_p3 = p_Val2_393_8_fu_4882_p3[ap_const_lv32_9];
assign tmp_1506_fu_6500_p3 = p_Val2_393_8_fu_4882_p3[ap_const_lv32_A];
assign tmp_1507_fu_6516_p3 = p_Val2_393_8_fu_4882_p3[ap_const_lv32_B];
assign tmp_1508_fu_6532_p3 = larger_V_9_s_fu_5088_p3[ap_const_lv32_A];
assign tmp_1509_fu_6548_p3 = larger_V_9_s_fu_5088_p3[ap_const_lv32_B];
assign tmp_1510_fu_6564_p3 = larger_V_10_s_fu_5288_p3[ap_const_lv32_B];
assign tmp_1511_fu_6580_p1 = kill1_t_V_9_1_fu_6556_p3[10:0];
assign tmp_1512_fu_6590_p3 = kill1_t_V_9_1_fu_6556_p3[ap_const_lv32_B];
assign tmp_1513_fu_6606_p1 = kill1_t_V_8_1_fu_6524_p3[10:0];
assign tmp_1514_fu_6616_p3 = kill1_t_V_8_1_fu_6524_p3[ap_const_lv32_B];
assign tmp_1515_fu_6644_p1 = kill1_t_V_7_1_fu_6476_p3[8:0];
assign tmp_1516_fu_6654_p3 = kill1_t_V_7_1_fu_6476_p3[ap_const_lv32_9];
assign tmp_1517_fu_6706_p1 = kill1_t_V_5_9_fu_6300_p3[7:0];
assign tmp_1518_fu_6734_p1 = tmp97_fu_6700_p2[9:0];
assign tmp_1519_fu_6744_p3 = tmp97_fu_6700_p2[ap_const_lv32_A];
assign tmp_1520_fu_6760_p1 = kill1_t_V_5_1_fu_6332_p3[9:0];
assign tmp_1521_fu_6788_p1 = kill1_t_V_6_1_fu_6412_p3[8:0];
assign tmp_1522_fu_6822_p1 = tmp102_fu_6816_p2[10:0];
assign tmp_1523_fu_6832_p3 = tmp102_fu_6816_p2[ap_const_lv32_B];
assign tmp_1524_fu_6854_p1 = kill1_t_V_6_s_fu_6396_p3[7:0];
assign tmp_1525_fu_6874_p1 = kill1_t_V_3_9_fu_6092_p3[6:0];
assign tmp_1526_fu_6916_p3 = kill1_t_V_6_s_fu_6396_p3[ap_const_lv32_A];
assign tmp_1527_fu_6932_p1 = kill1_t_V_3_1_fu_6124_p3[8:0];
assign tmp_1528_fu_6952_p1 = kill1_t_V_3_s_fu_6108_p3[6:0];
assign tmp_1529_fu_6994_p3 = kill1_t_V_3_1_fu_6124_p3[ap_const_lv32_B];
assign tmp_1530_fu_7016_p1 = kill1_t_V_4_8_fu_6188_p3[5:0];
assign tmp_1531_fu_7044_p1 = kill1_t_V_4_s_fu_6220_p3[7:0];
assign tmp_1532_fu_7054_p3 = kill1_t_V_4_s_fu_6220_p3[ap_const_lv32_8];
assign tmp_1533_fu_7094_p1 = kill1_t_V_4_9_fu_6204_p3[6:0];
assign tmp_1534_fu_7122_p1 = kill1_t_V_5_8_fu_6284_p3[7:0];
assign tmp_1535_fu_7132_p3 = kill1_t_V_5_8_fu_6284_p3[ap_const_lv32_8];
assign tmp_1536_fu_7148_p1 = kill1_t_V_4_1_fu_6236_p3[8:0];
assign tmp_1537_fu_7158_p3 = kill1_t_V_4_1_fu_6236_p3[ap_const_lv32_9];
assign tmp_1538_fu_7180_p3 = kill1_t_V_4_1_fu_6236_p3[ap_const_lv32_A];
assign tmp_1539_fu_7202_p3 = kill1_t_V_4_1_fu_6236_p3[ap_const_lv32_B];
assign tmp_1540_fu_7230_p1 = kill1_t_V_0_2_fu_5548_p3[1:0];
assign tmp_1541_fu_7240_p3 = kill1_t_V_0_2_fu_5548_p3[ap_const_lv32_2];
assign tmp_1542_fu_7256_p1 = kill1_t_V_0_4_fu_5580_p3[3:0];
assign tmp_1543_fu_7266_p3 = kill1_t_V_0_4_fu_5580_p3[ap_const_lv32_4];
assign tmp_1544_fu_7274_p1 = tmp_289_fu_7260_p2[2:0];
assign tmp_1545_fu_7284_p3 = tmp_289_fu_7260_p2[ap_const_lv32_3];
assign tmp_1546_fu_7302_p1 = kill1_t_V_0_6_fu_5612_p3[5:0];
assign tmp_1547_fu_7312_p3 = kill1_t_V_0_6_fu_5612_p3[ap_const_lv32_6];
assign tmp_1548_fu_7328_p1 = kill1_t_V_0_8_fu_5644_p3[7:0];
assign tmp_1549_fu_7338_p3 = kill1_t_V_0_8_fu_5644_p3[ap_const_lv32_8];
assign tmp_1550_fu_7346_p1 = tmp_292_fu_7332_p2[6:0];
assign tmp_1551_fu_7356_p3 = tmp_292_fu_7332_p2[ap_const_lv32_7];
assign tmp_1552_fu_7364_p1 = tmp_293_fu_7350_p2[4:0];
assign tmp_1553_fu_7396_p1 = kill1_t_V_0_s_fu_5676_p3[9:0];
assign tmp_1554_fu_7406_p3 = kill1_t_V_0_s_fu_5676_p3[ap_const_lv32_A];
assign tmp_1555_fu_7422_p1 = kill1_t_V_0_10_fu_5692_p3[2:0];
assign tmp_1556_fu_7456_p3 = kill1_t_V_0_10_fu_5692_p3[ap_const_lv32_B];
assign tmp_1557_fu_7464_p1 = tmp_300_fu_7450_p2[6:0];
assign tmp_1558_fu_7468_p1 = kill1_t_V_1_4_fu_5740_p3[3:0];
assign tmp_1559_fu_7478_p3 = kill1_t_V_1_4_fu_5740_p3[ap_const_lv32_4];
assign tmp_1560_fu_7494_p1 = kill1_t_V_1_6_fu_5772_p3[5:0];
assign tmp_1561_fu_7504_p3 = kill1_t_V_1_6_fu_5772_p3[ap_const_lv32_6];
assign tmp_1562_fu_7512_p1 = tmp_302_fu_7498_p2[4:0];
assign tmp_1563_fu_7522_p3 = tmp_302_fu_7498_p2[ap_const_lv32_5];
assign tmp_1564_fu_7590_p1 = kill1_t_V_1_8_fu_5804_p3[7:0];
assign tmp_1565_fu_7600_p3 = kill1_t_V_1_8_fu_5804_p3[ap_const_lv32_8];
assign tmp_1566_fu_7616_p1 = kill1_t_V_1_s_fu_5836_p3[9:0];
assign tmp_1567_fu_7626_p3 = kill1_t_V_1_s_fu_5836_p3[ap_const_lv32_A];
assign tmp_1568_fu_7634_p1 = tmp_310_fu_7620_p2[8:0];
assign tmp_1569_fu_7644_p3 = tmp_310_fu_7620_p2[ap_const_lv32_9];
assign tmp_1570_fu_7662_p1 = kill1_t_V_1_1_fu_5852_p3[3:0];
assign tmp_1571_fu_7682_p1 = kill1_t_V_2_5_fu_5900_p3[4:0];
assign tmp_1572_fu_7692_p3 = kill1_t_V_2_5_fu_5900_p3[ap_const_lv32_5];
assign tmp_1573_fu_7746_p3 = kill1_t_V_1_1_fu_5852_p3[ap_const_lv32_B];
assign tmp_1574_fu_7762_p1 = kill1_t_V_2_7_fu_5932_p3[6:0];
assign tmp_1575_fu_7772_p3 = kill1_t_V_2_7_fu_5932_p3[ap_const_lv32_7];
assign tmp_1576_fu_7788_p1 = kill1_t_V_2_9_fu_5964_p3[8:0];
assign tmp_1577_fu_7798_p3 = kill1_t_V_2_9_fu_5964_p3[ap_const_lv32_9];
assign tmp_1578_fu_7806_p1 = tmp_321_fu_7792_p2[7:0];
assign tmp_1579_fu_7816_p3 = tmp_321_fu_7792_p2[ap_const_lv32_8];
assign tmp_1580_fu_7834_p1 = kill1_t_V_2_1_fu_5996_p3[10:0];
assign tmp_1581_fu_7844_p3 = kill1_t_V_2_1_fu_5996_p3[ap_const_lv32_B];
assign tmp_1582_fu_7860_p3 = kill1_t_V_10_s_fu_6572_p3[ap_const_lv32_5];
assign tmp_1583_fu_7906_p1 = tmp132_fu_7900_p2[9:0];
assign tmp_1584_fu_7970_p1 = exists_V_fu_7958_p2[0:0];
assign tmp_1585_fu_7994_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_3];
assign tmp_1586_fu_8002_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_2];
assign tmp_1587_fu_8010_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_1];
assign tmp_1588_fu_8018_p1 = p_Val2_s_fu_7986_p3[0:0];
assign tmp_1589_fu_8022_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_7];
assign tmp_1590_fu_8030_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_6];
assign tmp_1591_fu_8038_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_5];
assign tmp_1592_fu_8046_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_4];
assign tmp_1593_fu_8054_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_B];
assign tmp_1594_fu_8062_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_A];
assign tmp_1595_fu_8070_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_9];
assign tmp_1596_fu_8078_p3 = p_Val2_s_fu_7986_p3[ap_const_lv32_8];
assign tmp_1597_fu_8614_p1 = p_0190_i_fu_8602_p2[2:0];
assign tmp_1598_fu_8618_p1 = p_0190_i_fu_8602_p2[1:0];
assign tmp_1599_fu_8630_p3 = {{tmp_1598_fu_8618_p1}, {ap_const_lv4_0}};
assign tmp_1600_fu_8638_p1 = p_shl4_fu_8622_p3;
assign tmp_1601_fu_8642_p2 = (tmp_1599_fu_8630_p3 - tmp_1600_fu_8638_p1);
assign tmp_1602_fu_8648_p1 = tmp_1601_fu_8642_p2;
assign tmp_1604_fu_8666_p3 = exists_V_fu_7958_p2[ap_const_lv32_1];
assign tmp_1605_fu_8688_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_3];
assign tmp_1606_fu_8696_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_2];
assign tmp_1607_fu_8704_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_1];
assign tmp_1608_fu_8712_p1 = p_Val2_398_1_fu_8680_p3[0:0];
assign tmp_1609_fu_8716_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_7];
assign tmp_1610_fu_8724_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_6];
assign tmp_1611_fu_8732_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_5];
assign tmp_1612_fu_8740_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_4];
assign tmp_1613_fu_8748_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_B];
assign tmp_1614_fu_8756_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_A];
assign tmp_1615_fu_8764_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_9];
assign tmp_1616_fu_8772_p3 = p_Val2_398_1_fu_8680_p3[ap_const_lv32_8];
assign tmp_1617_fu_9308_p1 = p_0190_i_1_fu_9296_p2[2:0];
assign tmp_1618_fu_16814_p1 = tmp_335_reg_40874[5:0];
assign tmp_1619_fu_16817_p1 = tmp_1618_fu_16814_p1;
assign tmp_1620_fu_16821_p2 = winner_V1_reg_40862 >> tmp_1619_fu_16817_p1;
assign tmp_1621_fu_16826_p1 = tmp_1620_fu_16821_p2[11:0];
always @ (*) begin
tmp_1622_fu_16830_p4 = tmp_1621_fu_16826_p1;
tmp_1622_fu_16830_p4[ap_const_lv32_1] = |(1'b1);
end
assign tmp_1623_fu_9338_p1 = tmp_335_fu_9332_p2[5:0];
assign tmp_1624_fu_16840_p1 = tmp_1623_reg_40879;
assign tmp_1625_fu_16843_p2 = ap_const_lv36_FFF << tmp_1624_fu_16840_p1;
assign tmp_1626_fu_16849_p2 = (tmp_1625_fu_16843_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1627_fu_16855_p2 = (winner_V1_reg_40862 & tmp_1626_fu_16849_p2);
assign tmp_1628_fu_16860_p1 = tmp_1622_fu_16830_p4;
assign tmp_1629_fu_16864_p2 = tmp_1628_fu_16860_p1 << tmp_1624_fu_16840_p1;
assign tmp_1631_fu_9342_p3 = exists_V_fu_7958_p2[ap_const_lv32_2];
assign tmp_1632_fu_9364_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_3];
assign tmp_1633_fu_9372_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_2];
assign tmp_1634_fu_9380_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_1];
assign tmp_1635_fu_9388_p1 = p_Val2_398_2_fu_9356_p3[0:0];
assign tmp_1636_fu_9392_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_7];
assign tmp_1637_fu_9400_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_6];
assign tmp_1638_fu_9408_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_5];
assign tmp_1639_fu_9416_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_4];
assign tmp_1640_fu_9424_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_B];
assign tmp_1641_fu_9432_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_A];
assign tmp_1642_fu_9440_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_9];
assign tmp_1643_fu_9448_p3 = p_Val2_398_2_fu_9356_p3[ap_const_lv32_8];
assign tmp_1644_fu_9984_p1 = p_0190_i_2_fu_9972_p2[2:0];
assign tmp_1645_fu_16906_p1 = tmp_337_fu_16900_p2[5:0];
assign tmp_1646_fu_16910_p1 = tmp_1645_fu_16906_p1;
assign tmp_1647_fu_16914_p2 = winner_V_1_fu_16876_p3 >> tmp_1646_fu_16910_p1;
assign tmp_1648_fu_16920_p1 = tmp_1647_fu_16914_p2[11:0];
always @ (*) begin
tmp_1649_fu_16924_p4 = tmp_1648_fu_16920_p1;
tmp_1649_fu_16924_p4[ap_const_lv32_2] = |(1'b1);
end
assign tmp_1650_fu_16934_p1 = tmp_337_fu_16900_p2[5:0];
assign tmp_1651_fu_16938_p1 = tmp_1650_fu_16934_p1;
assign tmp_1652_fu_16942_p2 = ap_const_lv36_FFF << tmp_1651_fu_16938_p1;
assign tmp_1653_fu_16948_p2 = (tmp_1652_fu_16942_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1654_fu_16954_p2 = (winner_V_1_fu_16876_p3 & tmp_1653_fu_16948_p2);
assign tmp_1655_fu_16960_p1 = tmp_1649_fu_16924_p4;
assign tmp_1656_fu_16964_p2 = tmp_1655_fu_16960_p1 << tmp_1651_fu_16938_p1;
assign tmp_1658_fu_9988_p3 = exists_V_fu_7958_p2[ap_const_lv32_3];
assign tmp_1659_fu_10010_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_3];
assign tmp_1660_fu_10018_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_2];
assign tmp_1661_fu_10026_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_1];
assign tmp_1662_fu_10034_p1 = p_Val2_398_3_fu_10002_p3[0:0];
assign tmp_1663_fu_10038_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_7];
assign tmp_1664_fu_10046_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_6];
assign tmp_1665_fu_10054_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_5];
assign tmp_1666_fu_10062_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_4];
assign tmp_1667_fu_10070_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_B];
assign tmp_1668_fu_10078_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_A];
assign tmp_1669_fu_10086_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_9];
assign tmp_1670_fu_10094_p3 = p_Val2_398_3_fu_10002_p3[ap_const_lv32_8];
assign tmp_1671_fu_10630_p1 = p_0190_i_3_fu_10618_p2[2:0];
assign tmp_1672_fu_17007_p1 = tmp_339_fu_17001_p2[5:0];
assign tmp_1673_fu_17011_p1 = tmp_1672_fu_17007_p1;
assign tmp_1674_fu_17015_p2 = winner_V_2_fu_16976_p3 >> tmp_1673_fu_17011_p1;
assign tmp_1675_fu_17021_p1 = tmp_1674_fu_17015_p2[11:0];
always @ (*) begin
tmp_1676_fu_17025_p4 = tmp_1675_fu_17021_p1;
tmp_1676_fu_17025_p4[ap_const_lv32_3] = |(1'b1);
end
assign tmp_1677_fu_17035_p1 = tmp_339_fu_17001_p2[5:0];
assign tmp_1678_fu_17039_p1 = tmp_1677_fu_17035_p1;
assign tmp_1679_fu_17043_p2 = ap_const_lv36_FFF << tmp_1678_fu_17039_p1;
assign tmp_1680_fu_17049_p2 = (tmp_1679_fu_17043_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1681_fu_17055_p2 = (winner_V_2_fu_16976_p3 & tmp_1680_fu_17049_p2);
assign tmp_1682_fu_17061_p1 = tmp_1676_fu_17025_p4;
assign tmp_1683_fu_17065_p2 = tmp_1682_fu_17061_p1 << tmp_1678_fu_17039_p1;
assign tmp_1685_fu_10634_p3 = exists_V_fu_7958_p2[ap_const_lv32_4];
assign tmp_1686_fu_10656_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_3];
assign tmp_1687_fu_10664_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_2];
assign tmp_1688_fu_10672_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_1];
assign tmp_1689_fu_10680_p1 = p_Val2_398_4_fu_10648_p3[0:0];
assign tmp_1690_fu_10684_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_7];
assign tmp_1691_fu_10692_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_6];
assign tmp_1692_fu_10700_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_5];
assign tmp_1693_fu_10708_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_4];
assign tmp_1694_fu_10716_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_B];
assign tmp_1695_fu_10724_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_A];
assign tmp_1696_fu_10732_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_9];
assign tmp_1697_fu_10740_p3 = p_Val2_398_4_fu_10648_p3[ap_const_lv32_8];
assign tmp_1698_fu_11276_p1 = p_0190_i_4_fu_11264_p2[2:0];
assign tmp_1699_fu_17108_p1 = tmp_341_fu_17102_p2[5:0];
assign tmp_1700_fu_17112_p1 = tmp_1699_fu_17108_p1;
assign tmp_1701_fu_17116_p2 = winner_V_3_fu_17077_p3 >> tmp_1700_fu_17112_p1;
assign tmp_1702_fu_17122_p1 = tmp_1701_fu_17116_p2[11:0];
always @ (*) begin
tmp_1703_fu_17126_p4 = tmp_1702_fu_17122_p1;
tmp_1703_fu_17126_p4[ap_const_lv32_4] = |(1'b1);
end
assign tmp_1704_fu_17136_p1 = tmp_341_fu_17102_p2[5:0];
assign tmp_1705_fu_17140_p1 = tmp_1704_fu_17136_p1;
assign tmp_1706_fu_17144_p2 = ap_const_lv36_FFF << tmp_1705_fu_17140_p1;
assign tmp_1707_fu_17150_p2 = (tmp_1706_fu_17144_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1708_fu_17156_p2 = (winner_V_3_fu_17077_p3 & tmp_1707_fu_17150_p2);
assign tmp_1709_fu_17162_p1 = tmp_1703_fu_17126_p4;
assign tmp_1710_fu_17166_p2 = tmp_1709_fu_17162_p1 << tmp_1705_fu_17140_p1;
assign tmp_1712_fu_11280_p3 = exists_V_fu_7958_p2[ap_const_lv32_5];
assign tmp_1713_fu_11302_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_3];
assign tmp_1714_fu_11310_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_2];
assign tmp_1715_fu_11318_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_1];
assign tmp_1716_fu_11326_p1 = p_Val2_398_5_fu_11294_p3[0:0];
assign tmp_1717_fu_11330_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_7];
assign tmp_1718_fu_11338_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_6];
assign tmp_1719_fu_11346_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_5];
assign tmp_1720_fu_11354_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_4];
assign tmp_1721_fu_11362_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_B];
assign tmp_1722_fu_11370_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_A];
assign tmp_1723_fu_11378_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_9];
assign tmp_1724_fu_11386_p3 = p_Val2_398_5_fu_11294_p3[ap_const_lv32_8];
assign tmp_1725_fu_11922_p1 = p_0190_i_5_fu_11910_p2[2:0];
assign tmp_1726_fu_17209_p1 = tmp_343_fu_17203_p2[5:0];
assign tmp_1727_fu_17213_p1 = tmp_1726_fu_17209_p1;
assign tmp_1728_fu_17217_p2 = winner_V_4_fu_17178_p3 >> tmp_1727_fu_17213_p1;
assign tmp_1729_fu_17223_p1 = tmp_1728_fu_17217_p2[11:0];
always @ (*) begin
tmp_1730_fu_17227_p4 = tmp_1729_fu_17223_p1;
tmp_1730_fu_17227_p4[ap_const_lv32_5] = |(1'b1);
end
assign tmp_1731_fu_17237_p1 = tmp_343_fu_17203_p2[5:0];
assign tmp_1732_fu_17241_p1 = tmp_1731_fu_17237_p1;
assign tmp_1733_fu_17245_p2 = ap_const_lv36_FFF << tmp_1732_fu_17241_p1;
assign tmp_1734_fu_17251_p2 = (tmp_1733_fu_17245_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1735_fu_17257_p2 = (winner_V_4_fu_17178_p3 & tmp_1734_fu_17251_p2);
assign tmp_1736_fu_17263_p1 = tmp_1730_fu_17227_p4;
assign tmp_1737_fu_17267_p2 = tmp_1736_fu_17263_p1 << tmp_1732_fu_17241_p1;
assign tmp_1739_fu_11926_p3 = exists_V_fu_7958_p2[ap_const_lv32_6];
assign tmp_1740_fu_11948_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_3];
assign tmp_1741_fu_11956_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_2];
assign tmp_1742_fu_11964_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_1];
assign tmp_1743_fu_11972_p1 = p_Val2_398_6_fu_11940_p3[0:0];
assign tmp_1744_fu_11976_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_7];
assign tmp_1745_fu_11984_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_6];
assign tmp_1746_fu_11992_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_5];
assign tmp_1747_fu_12000_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_4];
assign tmp_1748_fu_12008_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_B];
assign tmp_1749_fu_12016_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_A];
assign tmp_1750_fu_12024_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_9];
assign tmp_1751_fu_12032_p3 = p_Val2_398_6_fu_11940_p3[ap_const_lv32_8];
assign tmp_1752_fu_12568_p1 = p_0190_i_6_fu_12556_p2[2:0];
assign tmp_1753_fu_17310_p1 = tmp_345_fu_17304_p2[5:0];
assign tmp_1754_fu_17314_p1 = tmp_1753_fu_17310_p1;
assign tmp_1755_fu_17318_p2 = winner_V_5_fu_17279_p3 >> tmp_1754_fu_17314_p1;
assign tmp_1756_fu_17324_p1 = tmp_1755_fu_17318_p2[11:0];
always @ (*) begin
tmp_1757_fu_17328_p4 = tmp_1756_fu_17324_p1;
tmp_1757_fu_17328_p4[ap_const_lv32_6] = |(1'b1);
end
assign tmp_1758_fu_17338_p1 = tmp_345_fu_17304_p2[5:0];
assign tmp_1759_fu_17342_p1 = tmp_1758_fu_17338_p1;
assign tmp_1760_fu_17346_p2 = ap_const_lv36_FFF << tmp_1759_fu_17342_p1;
assign tmp_1761_fu_17352_p2 = (tmp_1760_fu_17346_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1762_fu_17358_p2 = (winner_V_5_fu_17279_p3 & tmp_1761_fu_17352_p2);
assign tmp_1763_fu_17364_p1 = tmp_1757_fu_17328_p4;
assign tmp_1764_fu_17368_p2 = tmp_1763_fu_17364_p1 << tmp_1759_fu_17342_p1;
assign tmp_1766_fu_12572_p3 = exists_V_fu_7958_p2[ap_const_lv32_7];
assign tmp_1767_fu_12594_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_3];
assign tmp_1768_fu_12602_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_2];
assign tmp_1769_fu_12610_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_1];
assign tmp_1770_fu_12618_p1 = p_Val2_398_7_fu_12586_p3[0:0];
assign tmp_1771_fu_12622_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_7];
assign tmp_1772_fu_12630_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_6];
assign tmp_1773_fu_12638_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_5];
assign tmp_1774_fu_12646_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_4];
assign tmp_1775_fu_12654_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_B];
assign tmp_1776_fu_12662_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_A];
assign tmp_1777_fu_12670_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_9];
assign tmp_1778_fu_12678_p3 = p_Val2_398_7_fu_12586_p3[ap_const_lv32_8];
assign tmp_1779_fu_13214_p1 = p_0190_i_7_fu_13202_p2[2:0];
assign tmp_1780_fu_17411_p1 = tmp_347_fu_17405_p2[5:0];
assign tmp_1781_fu_17415_p1 = tmp_1780_fu_17411_p1;
assign tmp_1782_fu_17419_p2 = winner_V_6_fu_17380_p3 >> tmp_1781_fu_17415_p1;
assign tmp_1783_fu_17425_p1 = tmp_1782_fu_17419_p2[11:0];
always @ (*) begin
tmp_1784_fu_17429_p4 = tmp_1783_fu_17425_p1;
tmp_1784_fu_17429_p4[ap_const_lv32_7] = |(1'b1);
end
assign tmp_1785_fu_17439_p1 = tmp_347_fu_17405_p2[5:0];
assign tmp_1786_fu_17443_p1 = tmp_1785_fu_17439_p1;
assign tmp_1787_fu_17447_p2 = ap_const_lv36_FFF << tmp_1786_fu_17443_p1;
assign tmp_1788_fu_17453_p2 = (tmp_1787_fu_17447_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1789_fu_17459_p2 = (winner_V_6_fu_17380_p3 & tmp_1788_fu_17453_p2);
assign tmp_1790_fu_17465_p1 = tmp_1784_fu_17429_p4;
assign tmp_1791_fu_17469_p2 = tmp_1790_fu_17465_p1 << tmp_1786_fu_17443_p1;
assign tmp_1793_fu_13218_p3 = exists_V_fu_7958_p2[ap_const_lv32_8];
assign tmp_1794_fu_13240_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_3];
assign tmp_1795_fu_13248_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_2];
assign tmp_1796_fu_13256_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_1];
assign tmp_1797_fu_13264_p1 = p_Val2_398_8_fu_13232_p3[0:0];
assign tmp_1798_fu_13268_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_7];
assign tmp_1799_fu_13276_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_6];
assign tmp_1800_fu_13284_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_5];
assign tmp_1801_fu_13292_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_4];
assign tmp_1802_fu_13300_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_B];
assign tmp_1803_fu_13308_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_A];
assign tmp_1804_fu_13316_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_9];
assign tmp_1805_fu_13324_p3 = p_Val2_398_8_fu_13232_p3[ap_const_lv32_8];
assign tmp_1806_fu_13860_p1 = p_0190_i_8_fu_13848_p2[2:0];
assign tmp_1807_fu_17521_p1 = tmp_349_fu_17515_p2[5:0];
assign tmp_1808_fu_17525_p1 = tmp_1807_fu_17521_p1;
assign tmp_1809_fu_17529_p2 = winner_V_7_reg_41995 >> tmp_1808_fu_17525_p1;
assign tmp_1810_fu_17534_p1 = tmp_1809_fu_17529_p2[11:0];
always @ (*) begin
tmp_1811_fu_17538_p4 = tmp_1810_fu_17534_p1;
tmp_1811_fu_17538_p4[ap_const_lv32_8] = |(1'b1);
end
assign tmp_1812_fu_17548_p1 = tmp_349_fu_17515_p2[5:0];
assign tmp_1813_fu_17552_p1 = tmp_1812_fu_17548_p1;
assign tmp_1814_fu_17556_p2 = ap_const_lv36_FFF << tmp_1813_fu_17552_p1;
assign tmp_1815_fu_17562_p2 = (tmp_1814_fu_17556_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1816_fu_17568_p2 = (winner_V_7_reg_41995 & tmp_1815_fu_17562_p2);
assign tmp_1817_fu_17573_p1 = tmp_1811_fu_17538_p4;
assign tmp_1818_fu_17577_p2 = tmp_1817_fu_17573_p1 << tmp_1813_fu_17552_p1;
assign tmp_1820_fu_13864_p3 = exists_V_fu_7958_p2[ap_const_lv32_9];
assign tmp_1821_fu_13886_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_3];
assign tmp_1822_fu_13894_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_2];
assign tmp_1823_fu_13902_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_1];
assign tmp_1824_fu_13910_p1 = p_Val2_398_9_fu_13878_p3[0:0];
assign tmp_1825_fu_13914_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_7];
assign tmp_1826_fu_13922_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_6];
assign tmp_1827_fu_13930_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_5];
assign tmp_1828_fu_13938_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_4];
assign tmp_1829_fu_13946_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_B];
assign tmp_1830_fu_13954_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_A];
assign tmp_1831_fu_13962_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_9];
assign tmp_1832_fu_13970_p3 = p_Val2_398_9_fu_13878_p3[ap_const_lv32_8];
assign tmp_1833_fu_14506_p1 = p_0190_i_9_fu_14494_p2[2:0];
assign tmp_1834_fu_17619_p1 = tmp_351_fu_17613_p2[5:0];
assign tmp_1835_fu_17623_p1 = tmp_1834_fu_17619_p1;
assign tmp_1836_fu_17627_p2 = winner_V_8_fu_17589_p3 >> tmp_1835_fu_17623_p1;
assign tmp_1837_fu_17633_p1 = tmp_1836_fu_17627_p2[11:0];
always @ (*) begin
tmp_1838_fu_17637_p4 = tmp_1837_fu_17633_p1;
tmp_1838_fu_17637_p4[ap_const_lv32_9] = |(1'b1);
end
assign tmp_1839_fu_17647_p1 = tmp_351_fu_17613_p2[5:0];
assign tmp_1840_fu_17651_p1 = tmp_1839_fu_17647_p1;
assign tmp_1841_fu_17655_p2 = ap_const_lv36_FFF << tmp_1840_fu_17651_p1;
assign tmp_1842_fu_17661_p2 = (tmp_1841_fu_17655_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1843_fu_17667_p2 = (winner_V_8_fu_17589_p3 & tmp_1842_fu_17661_p2);
assign tmp_1844_fu_17673_p1 = tmp_1838_fu_17637_p4;
assign tmp_1845_fu_17677_p2 = tmp_1844_fu_17673_p1 << tmp_1840_fu_17651_p1;
assign tmp_1847_fu_14510_p3 = exists_V_fu_7958_p2[ap_const_lv32_A];
assign tmp_1848_fu_14532_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_3];
assign tmp_1849_fu_14540_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_2];
assign tmp_1850_fu_14548_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_1];
assign tmp_1851_fu_14556_p1 = p_Val2_398_s_fu_14524_p3[0:0];
assign tmp_1852_fu_14560_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_7];
assign tmp_1853_fu_14568_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_6];
assign tmp_1854_fu_14576_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_5];
assign tmp_1855_fu_14584_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_4];
assign tmp_1856_fu_14592_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_B];
assign tmp_1857_fu_14600_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_A];
assign tmp_1858_fu_14608_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_9];
assign tmp_1859_fu_14616_p3 = p_Val2_398_s_fu_14524_p3[ap_const_lv32_8];
assign tmp_1860_fu_15152_p1 = p_0190_i_s_fu_15140_p2[2:0];
assign tmp_1861_fu_17720_p1 = tmp_353_fu_17714_p2[5:0];
assign tmp_1862_fu_17724_p1 = tmp_1861_fu_17720_p1;
assign tmp_1863_fu_17728_p2 = winner_V_9_fu_17689_p3 >> tmp_1862_fu_17724_p1;
assign tmp_1864_fu_17734_p1 = tmp_1863_fu_17728_p2[11:0];
always @ (*) begin
tmp_1865_fu_17738_p4 = tmp_1864_fu_17734_p1;
tmp_1865_fu_17738_p4[ap_const_lv32_A] = |(1'b1);
end
assign tmp_1866_fu_17748_p1 = tmp_353_fu_17714_p2[5:0];
assign tmp_1867_fu_17752_p1 = tmp_1866_fu_17748_p1;
assign tmp_1868_fu_17756_p2 = ap_const_lv36_FFF << tmp_1867_fu_17752_p1;
assign tmp_1869_fu_17762_p2 = (tmp_1868_fu_17756_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1870_fu_17768_p2 = (winner_V_9_fu_17689_p3 & tmp_1869_fu_17762_p2);
assign tmp_1871_fu_17774_p1 = tmp_1865_fu_17738_p4;
assign tmp_1872_fu_17778_p2 = tmp_1871_fu_17774_p1 << tmp_1867_fu_17752_p1;
assign tmp_1874_fu_15156_p3 = exists_V_fu_7958_p2[ap_const_lv32_B];
assign tmp_1875_fu_15178_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_3];
assign tmp_1876_fu_15186_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_2];
assign tmp_1877_fu_15194_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_1];
assign tmp_1878_fu_15202_p1 = p_Val2_398_10_fu_15170_p3[0:0];
assign tmp_1879_fu_15206_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_7];
assign tmp_1880_fu_15214_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_6];
assign tmp_1881_fu_15222_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_5];
assign tmp_1882_fu_15230_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_4];
assign tmp_1883_fu_15238_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_B];
assign tmp_1884_fu_15246_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_A];
assign tmp_1885_fu_15254_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_9];
assign tmp_1886_fu_15262_p3 = p_Val2_398_10_fu_15170_p3[ap_const_lv32_8];
assign tmp_1887_fu_15798_p1 = p_0190_i_10_fu_15786_p2[2:0];
assign tmp_1888_fu_17821_p1 = tmp_355_fu_17815_p2[5:0];
assign tmp_1889_fu_17825_p1 = tmp_1888_fu_17821_p1;
assign tmp_1890_fu_17829_p2 = winner_V_s_fu_17790_p3 >> tmp_1889_fu_17825_p1;
assign tmp_1891_fu_17835_p1 = tmp_1890_fu_17829_p2[11:0];
always @ (*) begin
tmp_1892_fu_17839_p4 = tmp_1891_fu_17835_p1;
tmp_1892_fu_17839_p4[ap_const_lv32_B] = |(1'b1);
end
assign tmp_1893_fu_17849_p1 = tmp_355_fu_17815_p2[5:0];
assign tmp_1894_fu_17853_p1 = tmp_1893_fu_17849_p1;
assign tmp_1895_fu_17857_p2 = ap_const_lv36_FFF << tmp_1894_fu_17853_p1;
assign tmp_1896_fu_17863_p2 = (tmp_1895_fu_17857_p2 ^ ap_const_lv36_FFFFFFFFF);
assign tmp_1897_fu_17869_p2 = (winner_V_s_fu_17790_p3 & tmp_1896_fu_17863_p2);
assign tmp_1898_fu_17875_p1 = tmp_1892_fu_17839_p4;
assign tmp_1899_fu_17879_p2 = tmp_1898_fu_17875_p1 << tmp_1894_fu_17853_p1;
assign tmp_1901_fu_17898_p1 = winner_V_10_fu_17891_p3[0:0];
assign tmp_1902_fu_17902_p1 = cn_si_0_0_V_fu_17488_p4[1:0];
assign tmp_1903_fu_18070_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_1];
assign tmp_1904_fu_18078_p1 = bt_sign_ph_V_fu_18041_p3[0:0];
assign tmp_1905_fu_15802_p1 = sign_ph_1_0_V_read[0:0];
assign tmp_1906_fu_18087_p1 = bt_sign_th_V_fu_18048_p3[0:0];
assign tmp_1907_fu_15806_p1 = sign_th_1_0_V_read[0:0];
assign tmp_1908_fu_18096_p3 = bt_sign_ph_V_fu_18041_p3[ap_const_lv32_1];
assign tmp_1910_fu_18109_p3 = bt_sign_th_V_fu_18048_p3[ap_const_lv32_1];
assign tmp_1912_fu_18122_p3 = bt_sign_ph_V_fu_18041_p3[ap_const_lv32_2];
assign tmp_1914_fu_18135_p3 = bt_sign_th_V_fu_18048_p3[ap_const_lv32_2];
assign tmp_1916_fu_18148_p3 = bt_sign_ph_V_fu_18041_p3[ap_const_lv32_3];
assign tmp_1918_fu_18161_p3 = bt_sign_th_V_fu_18048_p3[ap_const_lv32_3];
assign tmp_1920_fu_18174_p3 = bt_sign_ph_V_fu_18041_p3[ap_const_lv32_4];
assign tmp_1922_fu_18187_p3 = bt_sign_th_V_fu_18048_p3[ap_const_lv32_4];
assign tmp_1924_fu_18200_p3 = bt_sign_ph_V_fu_18041_p3[ap_const_lv32_5];
assign tmp_1926_fu_18229_p3 = bt_sign_th_V_fu_18048_p3[ap_const_lv32_5];
assign tmp_1928_fu_18258_p1 = bt_si_V_fu_18062_p3[0:0];
assign tmp_1929_fu_15890_p1 = si_1_0_V_read[0:0];
assign tmp_1930_fu_18267_p3 = bt_si_V_fu_18062_p3[ap_const_lv32_2];
assign tmp_1931_fu_18280_p3 = bt_si_V_fu_18062_p3[ap_const_lv32_3];
assign tmp_1932_fu_18293_p3 = bt_si_V_fu_18062_p3[ap_const_lv32_4];
assign tmp_1933_fu_18472_p2 = (tmp_1903_fu_18070_p3 | tmp_1901_fu_17898_p1);
assign tmp_1934_fu_18486_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_2];
assign tmp_1935_fu_18494_p1 = bt_sign_ph_V_1_fu_18441_p3[0:0];
assign tmp_1936_fu_15894_p1 = sign_ph_2_0_V_read[0:0];
assign tmp_1937_fu_18503_p1 = bt_sign_th_V_1_fu_18449_p3[0:0];
assign tmp_1938_fu_15898_p1 = sign_th_2_0_V_read[0:0];
assign tmp_1939_fu_18512_p3 = bt_sign_ph_V_1_fu_18441_p3[ap_const_lv32_1];
assign tmp_1941_fu_18525_p3 = bt_sign_th_V_1_fu_18449_p3[ap_const_lv32_1];
assign tmp_1943_fu_18538_p3 = bt_sign_ph_V_1_fu_18441_p3[ap_const_lv32_2];
assign tmp_1945_fu_18551_p3 = bt_sign_th_V_1_fu_18449_p3[ap_const_lv32_2];
assign tmp_1947_fu_18564_p3 = bt_sign_ph_V_1_fu_18441_p3[ap_const_lv32_3];
assign tmp_1949_fu_18577_p3 = bt_sign_th_V_1_fu_18449_p3[ap_const_lv32_3];
assign tmp_1951_fu_18590_p3 = bt_sign_ph_V_1_fu_18441_p3[ap_const_lv32_4];
assign tmp_1953_fu_18603_p3 = bt_sign_th_V_1_fu_18449_p3[ap_const_lv32_4];
assign tmp_1955_fu_18616_p3 = bt_sign_ph_V_1_fu_18441_p3[ap_const_lv32_5];
assign tmp_1957_fu_18645_p3 = bt_sign_th_V_1_fu_18449_p3[ap_const_lv32_5];
assign tmp_1959_fu_18674_p1 = bt_si_V_1_fu_18478_p3[0:0];
assign tmp_1960_fu_15982_p1 = si_2_0_V_read[0:0];
assign tmp_1961_fu_18683_p3 = bt_si_V_1_fu_18478_p3[ap_const_lv32_2];
assign tmp_1962_fu_18696_p3 = bt_si_V_1_fu_18478_p3[ap_const_lv32_3];
assign tmp_1963_fu_18709_p3 = bt_si_V_1_fu_18478_p3[ap_const_lv32_4];
assign tmp_1964_fu_18896_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_3];
assign tmp_1965_fu_18904_p1 = bt_sign_ph_V_2_fu_18857_p3[0:0];
assign tmp_1966_fu_15986_p1 = sign_ph_3_0_V_read[0:0];
assign tmp_1967_fu_18913_p1 = bt_sign_th_V_2_fu_18865_p3[0:0];
assign tmp_1968_fu_15990_p1 = sign_th_3_0_V_read[0:0];
assign tmp_1969_fu_18922_p3 = bt_sign_ph_V_2_fu_18857_p3[ap_const_lv32_1];
assign tmp_1971_fu_18935_p3 = bt_sign_th_V_2_fu_18865_p3[ap_const_lv32_1];
assign tmp_1973_fu_18948_p3 = bt_sign_ph_V_2_fu_18857_p3[ap_const_lv32_2];
assign tmp_1975_fu_18961_p3 = bt_sign_th_V_2_fu_18865_p3[ap_const_lv32_2];
assign tmp_1977_fu_18974_p3 = bt_sign_ph_V_2_fu_18857_p3[ap_const_lv32_3];
assign tmp_1979_fu_18987_p3 = bt_sign_th_V_2_fu_18865_p3[ap_const_lv32_3];
assign tmp_1981_fu_19000_p3 = bt_sign_ph_V_2_fu_18857_p3[ap_const_lv32_4];
assign tmp_1983_fu_19013_p3 = bt_sign_th_V_2_fu_18865_p3[ap_const_lv32_4];
assign tmp_1985_fu_19026_p3 = bt_sign_ph_V_2_fu_18857_p3[ap_const_lv32_5];
assign tmp_1987_fu_19055_p3 = bt_sign_th_V_2_fu_18865_p3[ap_const_lv32_5];
assign tmp_1989_fu_19084_p1 = bt_si_V_2_fu_18888_p3[0:0];
assign tmp_1990_fu_16074_p1 = si_3_0_V_read[0:0];
assign tmp_1991_fu_19093_p3 = bt_si_V_2_fu_18888_p3[ap_const_lv32_2];
assign tmp_1992_fu_19106_p3 = bt_si_V_2_fu_18888_p3[ap_const_lv32_3];
assign tmp_1993_fu_19119_p3 = bt_si_V_2_fu_18888_p3[ap_const_lv32_4];
assign tmp_1994_fu_19306_p1 = r_V_177_0_3_fu_19298_p3[2:0];
assign tmp_1995_fu_19316_p1 = r_V_177_0_3_fu_19298_p3[0:0];
assign tmp_1996_fu_19320_p2 = (tmp_1995_fu_19316_p1 | tmp_1933_fu_18472_p2);
assign tmp_1997_fu_19326_p4 = {{tmp_401_fu_19310_p2[ap_const_lv32_2 : ap_const_lv32_1]}};
assign tmp_1998_fu_19346_p2 = (tmp_1934_fu_18486_p3 | tmp_1964_fu_18896_p3);
assign tmp_1999_fu_19360_p1 = winner_V_10_fu_17891_p3[0:0];
assign tmp_2000_fu_19364_p1 = tmp_1999_fu_19360_p1;
assign tmp_2001_fu_19368_p3 = ((tmp_1903_fu_18070_p3[0:0] === 1'b1) ? ap_const_lv3_1 : tmp_2000_fu_19364_p1);
assign tmp_2002_fu_19376_p2 = (tmp_2001_fu_19368_p3 | tmp1033_fu_19352_p3);
assign tmp_2003_fu_19390_p2 = (tmp_1903_fu_18070_p3 | tmp_1934_fu_18486_p3);
assign tmp_2004_fu_19404_p3 = ((tmp_1964_fu_18896_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign tmp_2005_fu_19420_p2 = (tmp_402_fu_19412_p3 | tmp1034_fu_19396_p3);
assign tmp_2006_fu_19442_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_4];
assign tmp_2007_fu_19450_p1 = bt_sign_ph_V_3_fu_19267_p3[0:0];
assign tmp_2008_fu_16078_p1 = sign_ph_0_1_V_read[0:0];
assign tmp_2009_fu_19459_p1 = bt_sign_th_V_3_fu_19275_p3[0:0];
assign tmp_2010_fu_16082_p1 = sign_th_0_1_V_read[0:0];
assign tmp_2011_fu_19468_p3 = bt_sign_ph_V_3_fu_19267_p3[ap_const_lv32_1];
assign tmp_2013_fu_19481_p3 = bt_sign_th_V_3_fu_19275_p3[ap_const_lv32_1];
assign tmp_2015_fu_19494_p3 = bt_sign_ph_V_3_fu_19267_p3[ap_const_lv32_2];
assign tmp_2017_fu_19507_p3 = bt_sign_th_V_3_fu_19275_p3[ap_const_lv32_2];
assign tmp_2019_fu_19520_p3 = bt_sign_ph_V_3_fu_19267_p3[ap_const_lv32_3];
assign tmp_2021_fu_19533_p3 = bt_sign_th_V_3_fu_19275_p3[ap_const_lv32_3];
assign tmp_2023_fu_19546_p3 = bt_sign_ph_V_3_fu_19267_p3[ap_const_lv32_4];
assign tmp_2025_fu_19559_p3 = bt_sign_th_V_3_fu_19275_p3[ap_const_lv32_4];
assign tmp_2027_fu_19572_p3 = bt_sign_ph_V_3_fu_19267_p3[ap_const_lv32_5];
assign tmp_2029_fu_19601_p3 = bt_sign_th_V_3_fu_19275_p3[ap_const_lv32_5];
assign tmp_2031_fu_19630_p3 = tmp_401_fu_19310_p2[ap_const_lv32_1];
assign tmp_2032_fu_19652_p3 = tmp_401_fu_19310_p2[ap_const_lv32_2];
assign tmp_2033_fu_19670_p1 = bt_si_V_3_fu_19434_p3[0:0];
assign tmp_2034_fu_16166_p1 = si_0_1_V_read[0:0];
assign tmp_2035_fu_19693_p3 = bt_si_V_3_fu_19434_p3[ap_const_lv32_2];
assign tmp_2036_fu_19720_p3 = bt_si_V_3_fu_19434_p3[ap_const_lv32_3];
assign tmp_2037_fu_19733_p3 = bt_si_V_3_fu_19434_p3[ap_const_lv32_4];
assign tmp_2038_fu_19944_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_5];
assign tmp_2039_fu_19952_p1 = bt_sign_ph_V_4_fu_19881_p3[0:0];
assign tmp_2040_fu_16170_p1 = sign_ph_1_1_V_read[0:0];
assign tmp_2041_fu_19961_p1 = bt_sign_th_V_4_fu_19889_p3[0:0];
assign tmp_2042_fu_16174_p1 = sign_th_1_1_V_read[0:0];
assign tmp_2043_fu_19970_p3 = bt_sign_ph_V_4_fu_19881_p3[ap_const_lv32_1];
assign tmp_2045_fu_19983_p3 = bt_sign_th_V_4_fu_19889_p3[ap_const_lv32_1];
assign tmp_2047_fu_19996_p3 = bt_sign_ph_V_4_fu_19881_p3[ap_const_lv32_2];
assign tmp_2049_fu_20009_p3 = bt_sign_th_V_4_fu_19889_p3[ap_const_lv32_2];
assign tmp_2051_fu_20022_p3 = bt_sign_ph_V_4_fu_19881_p3[ap_const_lv32_3];
assign tmp_2053_fu_20035_p3 = bt_sign_th_V_4_fu_19889_p3[ap_const_lv32_3];
assign tmp_2055_fu_20048_p3 = bt_sign_ph_V_4_fu_19881_p3[ap_const_lv32_4];
assign tmp_2057_fu_20061_p3 = bt_sign_th_V_4_fu_19889_p3[ap_const_lv32_4];
assign tmp_2059_fu_20074_p3 = bt_sign_ph_V_4_fu_19881_p3[ap_const_lv32_5];
assign tmp_2061_fu_20103_p3 = bt_sign_th_V_4_fu_19889_p3[ap_const_lv32_5];
assign tmp_2063_fu_20132_p1 = bt_ci_V_4_fu_19912_p3[1:0];
assign tmp_2064_fu_20160_p1 = bt_si_V_4_fu_19936_p3[0:0];
assign tmp_2065_fu_16258_p1 = si_1_1_V_read[0:0];
assign tmp_2066_fu_20169_p1 = bt_ci_V163_4_fu_19920_p3[2:0];
assign tmp_2067_fu_20179_p3 = bt_ci_V163_4_fu_19920_p3[ap_const_lv32_3];
assign tmp_2068_fu_20195_p3 = bt_si_V_4_fu_19936_p3[ap_const_lv32_2];
assign tmp_2069_fu_20208_p3 = bt_si_V_4_fu_19936_p3[ap_const_lv32_3];
assign tmp_2070_fu_20221_p3 = bt_si_V_4_fu_19936_p3[ap_const_lv32_4];
assign tmp_2071_fu_20424_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_6];
assign tmp_2072_fu_20432_p1 = bt_sign_ph_V_5_fu_20369_p3[0:0];
assign tmp_2073_fu_16262_p1 = sign_ph_2_1_V_read[0:0];
assign tmp_2074_fu_20441_p1 = bt_sign_th_V_5_fu_20377_p3[0:0];
assign tmp_2075_fu_16266_p1 = sign_th_2_1_V_read[0:0];
assign tmp_2076_fu_20450_p3 = bt_sign_ph_V_5_fu_20369_p3[ap_const_lv32_1];
assign tmp_2078_fu_20463_p3 = bt_sign_th_V_5_fu_20377_p3[ap_const_lv32_1];
assign tmp_2080_fu_20476_p3 = bt_sign_ph_V_5_fu_20369_p3[ap_const_lv32_2];
assign tmp_2082_fu_20489_p3 = bt_sign_th_V_5_fu_20377_p3[ap_const_lv32_2];
assign tmp_2084_fu_20502_p3 = bt_sign_ph_V_5_fu_20369_p3[ap_const_lv32_3];
assign tmp_2086_fu_20515_p3 = bt_sign_th_V_5_fu_20377_p3[ap_const_lv32_3];
assign tmp_2088_fu_20528_p3 = bt_sign_ph_V_5_fu_20369_p3[ap_const_lv32_4];
assign tmp_2090_fu_20541_p3 = bt_sign_th_V_5_fu_20377_p3[ap_const_lv32_4];
assign tmp_2092_fu_20554_p3 = bt_sign_ph_V_5_fu_20369_p3[ap_const_lv32_5];
assign tmp_2094_fu_20583_p3 = bt_sign_th_V_5_fu_20377_p3[ap_const_lv32_5];
assign tmp_2096_fu_20612_p1 = bt_si_V_5_fu_20416_p3[0:0];
assign tmp_2097_fu_16350_p1 = si_2_1_V_read[0:0];
assign tmp_2098_fu_20621_p3 = bt_si_V_5_fu_20416_p3[ap_const_lv32_2];
assign tmp_2099_fu_20634_p3 = bt_si_V_5_fu_20416_p3[ap_const_lv32_3];
assign tmp_2100_fu_20647_p3 = bt_si_V_5_fu_20416_p3[ap_const_lv32_4];
assign tmp_2101_fu_20842_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_7];
assign tmp_2102_fu_20850_p1 = bt_sign_ph_V_6_fu_20795_p3[0:0];
assign tmp_2103_fu_16354_p1 = sign_ph_3_1_V_read[0:0];
assign tmp_2104_fu_20859_p1 = bt_sign_th_V_6_fu_20803_p3[0:0];
assign tmp_2105_fu_16358_p1 = sign_th_3_1_V_read[0:0];
assign tmp_2106_fu_20868_p3 = bt_sign_ph_V_6_fu_20795_p3[ap_const_lv32_1];
assign tmp_2108_fu_20881_p3 = bt_sign_th_V_6_fu_20803_p3[ap_const_lv32_1];
assign tmp_2110_fu_20894_p3 = bt_sign_ph_V_6_fu_20795_p3[ap_const_lv32_2];
assign tmp_2112_fu_20907_p3 = bt_sign_th_V_6_fu_20803_p3[ap_const_lv32_2];
assign tmp_2114_fu_20920_p3 = bt_sign_ph_V_6_fu_20795_p3[ap_const_lv32_3];
assign tmp_2116_fu_20933_p3 = bt_sign_th_V_6_fu_20803_p3[ap_const_lv32_3];
assign tmp_2118_fu_20946_p3 = bt_sign_ph_V_6_fu_20795_p3[ap_const_lv32_4];
assign tmp_2120_fu_20959_p3 = bt_sign_th_V_6_fu_20803_p3[ap_const_lv32_4];
assign tmp_2122_fu_20972_p3 = bt_sign_ph_V_6_fu_20795_p3[ap_const_lv32_5];
assign tmp_2124_fu_21001_p3 = bt_sign_th_V_6_fu_20803_p3[ap_const_lv32_5];
assign tmp_2126_fu_21030_p1 = bt_si_V_6_fu_20834_p3[0:0];
assign tmp_2127_fu_16442_p1 = si_3_1_V_read[0:0];
assign tmp_2128_fu_21039_p3 = bt_si_V_6_fu_20834_p3[ap_const_lv32_2];
assign tmp_2129_fu_21052_p3 = bt_si_V_6_fu_20834_p3[ap_const_lv32_3];
assign tmp_2130_fu_21065_p3 = bt_si_V_6_fu_20834_p3[ap_const_lv32_4];
assign tmp_2131_fu_21236_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_0);
assign tmp_2132_fu_21272_p2 = (tmp_2071_fu_20424_p3 | tmp_2101_fu_20842_p3);
assign tmp_2133_fu_21286_p1 = bt_ci_V163_5_fu_20408_p3[2:0];
assign tmp_2134_fu_21290_p2 = (tmp_2133_fu_21286_p1 | tmp1066_fu_21278_p3);
assign tmp_2135_fu_21296_p3 = bt_ci_V163_5_fu_20408_p3[ap_const_lv32_3];
assign tmp_2136_fu_21312_p2 = (tmp_2038_fu_19944_p3 | tmp_2071_fu_20424_p3);
assign tmp_2137_fu_21326_p1 = bt_ci_V164_4_fu_19928_p3[2:0];
assign tmp_2138_fu_21330_p2 = (tmp_2137_fu_21326_p1 | r_V_177_0_7_2_fu_21264_p3);
assign tmp_2139_fu_21336_p3 = bt_ci_V164_4_fu_19928_p3[ap_const_lv32_3];
assign tmp_2140_fu_21344_p2 = (tmp_2138_fu_21330_p2 | tmp1067_fu_21318_p3);
assign tmp_2141_fu_21366_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_8];
assign tmp_2142_fu_21374_p1 = bt_sign_ph_V_7_fu_21213_p3[0:0];
assign tmp_2143_fu_16446_p1 = sign_ph_0_2_V_read[0:0];
assign tmp_2144_fu_21383_p1 = bt_sign_th_V_7_fu_21221_p3[0:0];
assign tmp_2145_fu_16450_p1 = sign_th_0_2_V_read[0:0];
assign tmp_2146_fu_21392_p3 = bt_sign_ph_V_7_fu_21213_p3[ap_const_lv32_1];
assign tmp_2148_fu_21405_p3 = bt_sign_th_V_7_fu_21221_p3[ap_const_lv32_1];
assign tmp_2150_fu_21418_p3 = bt_sign_ph_V_7_fu_21213_p3[ap_const_lv32_2];
assign tmp_2152_fu_21431_p3 = bt_sign_th_V_7_fu_21221_p3[ap_const_lv32_2];
assign tmp_2154_fu_21444_p3 = bt_sign_ph_V_7_fu_21213_p3[ap_const_lv32_3];
assign tmp_2156_fu_21457_p3 = bt_sign_th_V_7_fu_21221_p3[ap_const_lv32_3];
assign tmp_2158_fu_21470_p3 = bt_sign_ph_V_7_fu_21213_p3[ap_const_lv32_4];
assign tmp_2160_fu_21483_p3 = bt_sign_th_V_7_fu_21221_p3[ap_const_lv32_4];
assign tmp_2162_fu_21496_p3 = bt_sign_ph_V_7_fu_21213_p3[ap_const_lv32_5];
assign tmp_2164_fu_21525_p3 = bt_sign_th_V_7_fu_21221_p3[ap_const_lv32_5];
assign tmp_2166_fu_21554_p1 = bt_ci_V_7_fu_21258_p2[1:0];
assign tmp_2167_fu_21582_p1 = bt_si_V_7_fu_21358_p3[0:0];
assign tmp_2168_fu_16534_p1 = si_0_2_V_read[0:0];
assign tmp_2169_fu_21605_p3 = bt_si_V_7_fu_21358_p3[ap_const_lv32_2];
assign tmp_2170_fu_21632_p3 = bt_si_V_7_fu_21358_p3[ap_const_lv32_3];
assign tmp_2171_fu_21645_p3 = bt_si_V_7_fu_21358_p3[ap_const_lv32_4];
assign tmp_2172_fu_21848_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_9];
assign tmp_2173_fu_21856_p1 = bt_sign_ph_V_8_fu_21793_p3[0:0];
assign tmp_2174_fu_16538_p1 = sign_ph_1_2_V_read[0:0];
assign tmp_2175_fu_21865_p1 = bt_sign_th_V_8_fu_21801_p3[0:0];
assign tmp_2176_fu_16542_p1 = sign_th_1_2_V_read[0:0];
assign tmp_2177_fu_21874_p3 = bt_sign_ph_V_8_fu_21793_p3[ap_const_lv32_1];
assign tmp_2179_fu_21887_p3 = bt_sign_th_V_8_fu_21801_p3[ap_const_lv32_1];
assign tmp_2181_fu_21900_p3 = bt_sign_ph_V_8_fu_21793_p3[ap_const_lv32_2];
assign tmp_2183_fu_21913_p3 = bt_sign_th_V_8_fu_21801_p3[ap_const_lv32_2];
assign tmp_2185_fu_21926_p3 = bt_sign_ph_V_8_fu_21793_p3[ap_const_lv32_3];
assign tmp_2187_fu_21939_p3 = bt_sign_th_V_8_fu_21801_p3[ap_const_lv32_3];
assign tmp_2189_fu_21952_p3 = bt_sign_ph_V_8_fu_21793_p3[ap_const_lv32_4];
assign tmp_2191_fu_21965_p3 = bt_sign_th_V_8_fu_21801_p3[ap_const_lv32_4];
assign tmp_2193_fu_21978_p3 = bt_sign_ph_V_8_fu_21793_p3[ap_const_lv32_5];
assign tmp_2195_fu_22007_p3 = bt_sign_th_V_8_fu_21801_p3[ap_const_lv32_5];
assign tmp_2197_fu_22036_p1 = bt_ci_V_8_fu_21816_p3[1:0];
assign tmp_2198_fu_22064_p1 = bt_si_V_8_fu_21840_p3[0:0];
assign tmp_2199_fu_16626_p1 = si_1_2_V_read[0:0];
assign tmp_2200_fu_22073_p1 = bt_ci_V163_8_fu_21824_p3[2:0];
assign tmp_2201_fu_22083_p3 = bt_ci_V163_8_fu_21824_p3[ap_const_lv32_3];
assign tmp_2202_fu_22099_p3 = bt_si_V_8_fu_21840_p3[ap_const_lv32_2];
assign tmp_2203_fu_22112_p3 = bt_si_V_8_fu_21840_p3[ap_const_lv32_3];
assign tmp_2204_fu_22125_p3 = bt_si_V_8_fu_21840_p3[ap_const_lv32_4];
assign tmp_2205_fu_22336_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_A];
assign tmp_2206_fu_22344_p1 = bt_sign_ph_V_9_fu_22273_p3[0:0];
assign tmp_2207_fu_16630_p1 = sign_ph_2_2_V_read[0:0];
assign tmp_2208_fu_22353_p1 = bt_sign_th_V_9_fu_22281_p3[0:0];
assign tmp_2209_fu_16634_p1 = sign_th_2_2_V_read[0:0];
assign tmp_2210_fu_22362_p3 = bt_sign_ph_V_9_fu_22273_p3[ap_const_lv32_1];
assign tmp_2212_fu_22375_p3 = bt_sign_th_V_9_fu_22281_p3[ap_const_lv32_1];
assign tmp_2214_fu_22388_p3 = bt_sign_ph_V_9_fu_22273_p3[ap_const_lv32_2];
assign tmp_2216_fu_22401_p3 = bt_sign_th_V_9_fu_22281_p3[ap_const_lv32_2];
assign tmp_2218_fu_22414_p3 = bt_sign_ph_V_9_fu_22273_p3[ap_const_lv32_3];
assign tmp_2220_fu_22427_p3 = bt_sign_th_V_9_fu_22281_p3[ap_const_lv32_3];
assign tmp_2222_fu_22440_p3 = bt_sign_ph_V_9_fu_22273_p3[ap_const_lv32_4];
assign tmp_2224_fu_22453_p3 = bt_sign_th_V_9_fu_22281_p3[ap_const_lv32_4];
assign tmp_2226_fu_22466_p3 = bt_sign_ph_V_9_fu_22273_p3[ap_const_lv32_5];
assign tmp_2228_fu_22495_p3 = bt_sign_th_V_9_fu_22281_p3[ap_const_lv32_5];
assign tmp_2230_fu_22524_p1 = bt_si_V_9_fu_22328_p3[0:0];
assign tmp_2231_fu_16718_p1 = si_2_2_V_read[0:0];
assign tmp_2232_fu_22533_p3 = bt_si_V_9_fu_22328_p3[ap_const_lv32_2];
assign tmp_2233_fu_22546_p3 = bt_si_V_9_fu_22328_p3[ap_const_lv32_3];
assign tmp_2234_fu_22559_p3 = bt_si_V_9_fu_22328_p3[ap_const_lv32_4];
assign tmp_2235_fu_22746_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_B];
assign tmp_2236_fu_22754_p1 = bt_sign_ph_V_s_fu_22707_p3[0:0];
assign tmp_2237_fu_16722_p1 = sign_ph_3_2_V_read[0:0];
assign tmp_2238_fu_22763_p1 = bt_sign_th_V_s_fu_22715_p3[0:0];
assign tmp_2239_fu_16726_p1 = sign_th_3_2_V_read[0:0];
assign tmp_2240_fu_22772_p3 = bt_sign_ph_V_s_fu_22707_p3[ap_const_lv32_1];
assign tmp_2242_fu_22785_p3 = bt_sign_th_V_s_fu_22715_p3[ap_const_lv32_1];
assign tmp_2244_fu_22798_p3 = bt_sign_ph_V_s_fu_22707_p3[ap_const_lv32_2];
assign tmp_2246_fu_22811_p3 = bt_sign_th_V_s_fu_22715_p3[ap_const_lv32_2];
assign tmp_2248_fu_22824_p3 = bt_sign_ph_V_s_fu_22707_p3[ap_const_lv32_3];
assign tmp_2250_fu_22837_p3 = bt_sign_th_V_s_fu_22715_p3[ap_const_lv32_3];
assign tmp_2252_fu_22850_p3 = bt_sign_ph_V_s_fu_22707_p3[ap_const_lv32_4];
assign tmp_2254_fu_22863_p3 = bt_sign_th_V_s_fu_22715_p3[ap_const_lv32_4];
assign tmp_2256_fu_22876_p3 = bt_sign_ph_V_s_fu_22707_p3[ap_const_lv32_5];
assign tmp_2258_fu_22905_p3 = bt_sign_th_V_s_fu_22715_p3[ap_const_lv32_5];
assign tmp_2260_fu_22934_p1 = bt_si_V_s_fu_22738_p3[0:0];
assign tmp_2261_fu_16810_p1 = si_3_2_V_read[0:0];
assign tmp_2262_fu_22943_p3 = bt_si_V_s_fu_22738_p3[ap_const_lv32_2];
assign tmp_2263_fu_22956_p3 = bt_si_V_s_fu_22738_p3[ap_const_lv32_3];
assign tmp_2264_fu_22969_p3 = bt_si_V_s_fu_22738_p3[ap_const_lv32_4];
assign tmp_2265_fu_24394_p2 = (tmp_2205_fu_22336_p3 | tmp_2141_fu_21366_p3);
assign tmp_2266_fu_24434_p2 = (tmp_1901_fu_17898_p1 | tmp_1934_fu_18486_p3);
assign tmp_2267_fu_24454_p2 = (tmp_1964_fu_18896_p3 | tmp_2235_fu_22746_p3);
assign tmp_2268_fu_24486_p3 = ((tmp_1934_fu_18486_p3[0:0] === 1'b1) ? 1'b1 : 1'b0);
assign tmp_2269_fu_24494_p2 = (tmp_1903_fu_18070_p3 | tmp_1901_fu_17898_p1);
assign tmp_2270_fu_24508_p2 = (tmp_2006_fu_19442_p3 | tmp_2038_fu_19944_p3);
assign tmp_2271_fu_24514_p3 = r_V_176_0_3_fu_19290_p3[ap_const_lv32_1];
assign tmp_2272_fu_24536_p3 = ((tmp_2101_fu_20842_p3[0:0] === 1'b1) ? 1'b1 : 1'b0);
assign tmp_2273_fu_24558_p2 = (tmp_2205_fu_22336_p3 | tmp_2235_fu_22746_p3);
assign tmp_2274_fu_24600_p3 = r_V_176_0_5_fu_20392_p3[ap_const_lv32_1];
assign tmp_2275_fu_24646_p3 = ((tmp_2235_fu_22746_p3[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_0);
assign tmp_2276_fu_24682_p1 = bt_ci_V163_9_fu_22312_p3[2:0];
assign tmp_2277_fu_24686_p2 = (tmp_2276_fu_24682_p1 | tmp1300_fu_24674_p3);
assign tmp_2278_fu_24692_p3 = bt_ci_V163_9_fu_22312_p3[ap_const_lv32_3];
assign tmp_2279_fu_24708_p1 = bt_ci_V164_8_fu_21832_p3[2:0];
assign tmp_2280_fu_24712_p2 = (tmp_2279_fu_24708_p1 | r_V_177_0_9_3_fu_22320_p3);
assign tmp_2281_fu_24718_p3 = bt_ci_V164_8_fu_21832_p3[ap_const_lv32_3];
assign tmp_2282_fu_24726_p2 = (tmp_2280_fu_24712_p2 | tmp1300_fu_24674_p3);
assign tmp_2283_fu_24748_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_C];
assign tmp_2284_fu_24911_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_D];
assign tmp_2285_fu_24919_p1 = bt_sign_ph_V1_fu_24882_p3[0:0];
assign tmp_2286_fu_24928_p1 = bt_sign_th_V1_fu_24889_p3[0:0];
assign tmp_2287_fu_24937_p3 = bt_sign_ph_V1_fu_24882_p3[ap_const_lv32_1];
assign tmp_2288_fu_24950_p3 = bt_sign_th_V1_fu_24889_p3[ap_const_lv32_1];
assign tmp_2289_fu_24963_p3 = bt_sign_ph_V1_fu_24882_p3[ap_const_lv32_2];
assign tmp_2290_fu_24976_p3 = bt_sign_th_V1_fu_24889_p3[ap_const_lv32_2];
assign tmp_2291_fu_24989_p3 = bt_sign_ph_V1_fu_24882_p3[ap_const_lv32_3];
assign tmp_2292_fu_25002_p3 = bt_sign_th_V1_fu_24889_p3[ap_const_lv32_3];
assign tmp_2293_fu_25015_p3 = bt_sign_ph_V1_fu_24882_p3[ap_const_lv32_4];
assign tmp_2294_fu_25028_p3 = bt_sign_th_V1_fu_24889_p3[ap_const_lv32_4];
assign tmp_2295_fu_25041_p3 = bt_sign_ph_V1_fu_24882_p3[ap_const_lv32_5];
assign tmp_2296_fu_25070_p3 = bt_sign_th_V1_fu_24889_p3[ap_const_lv32_5];
assign tmp_2297_fu_25099_p1 = bt_si_V1_fu_24903_p3[0:0];
assign tmp_2298_fu_25108_p3 = bt_si_V1_fu_24903_p3[ap_const_lv32_2];
assign tmp_2299_fu_25121_p3 = bt_si_V1_fu_24903_p3[ap_const_lv32_3];
assign tmp_2300_fu_25134_p3 = bt_si_V1_fu_24903_p3[ap_const_lv32_4];
assign tmp_2301_fu_25313_p2 = (tmp_2284_fu_24911_p3 | tmp_2283_fu_24748_p3);
assign tmp_2302_fu_25327_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_E];
assign tmp_2303_fu_25335_p1 = bt_sign_ph_V47_1_fu_25282_p3[0:0];
assign tmp_2304_fu_25344_p1 = bt_sign_th_V49_1_fu_25290_p3[0:0];
assign tmp_2305_fu_25353_p3 = bt_sign_ph_V47_1_fu_25282_p3[ap_const_lv32_1];
assign tmp_2306_fu_25366_p3 = bt_sign_th_V49_1_fu_25290_p3[ap_const_lv32_1];
assign tmp_2307_fu_25379_p3 = bt_sign_ph_V47_1_fu_25282_p3[ap_const_lv32_2];
assign tmp_2308_fu_25392_p3 = bt_sign_th_V49_1_fu_25290_p3[ap_const_lv32_2];
assign tmp_2309_fu_25405_p3 = bt_sign_ph_V47_1_fu_25282_p3[ap_const_lv32_3];
assign tmp_2310_fu_25418_p3 = bt_sign_th_V49_1_fu_25290_p3[ap_const_lv32_3];
assign tmp_2311_fu_25431_p3 = bt_sign_ph_V47_1_fu_25282_p3[ap_const_lv32_4];
assign tmp_2312_fu_25444_p3 = bt_sign_th_V49_1_fu_25290_p3[ap_const_lv32_4];
assign tmp_2313_fu_25457_p3 = bt_sign_ph_V47_1_fu_25282_p3[ap_const_lv32_5];
assign tmp_2314_fu_25486_p3 = bt_sign_th_V49_1_fu_25290_p3[ap_const_lv32_5];
assign tmp_2315_fu_25515_p1 = bt_si_V59_1_fu_25319_p3[0:0];
assign tmp_2316_fu_25524_p3 = bt_si_V59_1_fu_25319_p3[ap_const_lv32_2];
assign tmp_2317_fu_25537_p3 = bt_si_V59_1_fu_25319_p3[ap_const_lv32_3];
assign tmp_2318_fu_25550_p3 = bt_si_V59_1_fu_25319_p3[ap_const_lv32_4];
assign tmp_2319_fu_25737_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_F];
assign tmp_2320_fu_25745_p1 = bt_sign_ph_V47_2_fu_25698_p3[0:0];
assign tmp_2321_fu_25754_p1 = bt_sign_th_V49_2_fu_25706_p3[0:0];
assign tmp_2322_fu_25763_p3 = bt_sign_ph_V47_2_fu_25698_p3[ap_const_lv32_1];
assign tmp_2323_fu_25776_p3 = bt_sign_th_V49_2_fu_25706_p3[ap_const_lv32_1];
assign tmp_2324_fu_25789_p3 = bt_sign_ph_V47_2_fu_25698_p3[ap_const_lv32_2];
assign tmp_2325_fu_25802_p3 = bt_sign_th_V49_2_fu_25706_p3[ap_const_lv32_2];
assign tmp_2326_fu_25815_p3 = bt_sign_ph_V47_2_fu_25698_p3[ap_const_lv32_3];
assign tmp_2327_fu_25828_p3 = bt_sign_th_V49_2_fu_25706_p3[ap_const_lv32_3];
assign tmp_2328_fu_25841_p3 = bt_sign_ph_V47_2_fu_25698_p3[ap_const_lv32_4];
assign tmp_2329_fu_25854_p3 = bt_sign_th_V49_2_fu_25706_p3[ap_const_lv32_4];
assign tmp_2330_fu_25867_p3 = bt_sign_ph_V47_2_fu_25698_p3[ap_const_lv32_5];
assign tmp_2331_fu_25896_p3 = bt_sign_th_V49_2_fu_25706_p3[ap_const_lv32_5];
assign tmp_2332_fu_25925_p1 = bt_si_V59_2_fu_25729_p3[0:0];
assign tmp_2333_fu_25934_p3 = bt_si_V59_2_fu_25729_p3[ap_const_lv32_2];
assign tmp_2334_fu_25947_p3 = bt_si_V59_2_fu_25729_p3[ap_const_lv32_3];
assign tmp_2335_fu_25960_p3 = bt_si_V59_2_fu_25729_p3[ap_const_lv32_4];
assign tmp_2336_fu_26147_p1 = r_V_177_1_3_fu_26139_p3[2:0];
assign tmp_2337_fu_26157_p1 = r_V_177_1_3_fu_26139_p3[0:0];
assign tmp_2338_fu_26161_p2 = (tmp_2337_fu_26157_p1 | tmp_2301_fu_25313_p2);
assign tmp_2339_fu_26167_p4 = {{tmp_584_fu_26151_p2[ap_const_lv32_2 : ap_const_lv32_1]}};
assign tmp_2340_fu_26187_p2 = (tmp_2302_fu_25327_p3 | tmp_2319_fu_25737_p3);
assign tmp_2341_fu_26201_p1 = tmp_2283_fu_24748_p3;
assign tmp_2342_fu_26205_p3 = ((tmp_2284_fu_24911_p3[0:0] === 1'b1) ? ap_const_lv3_1 : tmp_2341_fu_26201_p1);
assign tmp_2343_fu_26213_p2 = (tmp_2342_fu_26205_p3 | tmp1360_fu_26193_p3);
assign tmp_2344_fu_26227_p2 = (tmp_2284_fu_24911_p3 | tmp_2302_fu_25327_p3);
assign tmp_2345_fu_26241_p3 = ((tmp_2319_fu_25737_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign tmp_2346_fu_26257_p2 = (tmp_585_fu_26249_p3 | tmp1361_fu_26233_p3);
assign tmp_2347_fu_26279_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_10];
assign tmp_2348_fu_26287_p1 = bt_sign_ph_V47_3_fu_26108_p3[0:0];
assign tmp_2349_fu_26296_p1 = bt_sign_th_V49_3_fu_26116_p3[0:0];
assign tmp_2350_fu_26305_p3 = bt_sign_ph_V47_3_fu_26108_p3[ap_const_lv32_1];
assign tmp_2351_fu_26318_p3 = bt_sign_th_V49_3_fu_26116_p3[ap_const_lv32_1];
assign tmp_2352_fu_26331_p3 = bt_sign_ph_V47_3_fu_26108_p3[ap_const_lv32_2];
assign tmp_2353_fu_26344_p3 = bt_sign_th_V49_3_fu_26116_p3[ap_const_lv32_2];
assign tmp_2354_fu_26357_p3 = bt_sign_ph_V47_3_fu_26108_p3[ap_const_lv32_3];
assign tmp_2355_fu_26370_p3 = bt_sign_th_V49_3_fu_26116_p3[ap_const_lv32_3];
assign tmp_2356_fu_26383_p3 = bt_sign_ph_V47_3_fu_26108_p3[ap_const_lv32_4];
assign tmp_2357_fu_26396_p3 = bt_sign_th_V49_3_fu_26116_p3[ap_const_lv32_4];
assign tmp_2358_fu_26409_p3 = bt_sign_ph_V47_3_fu_26108_p3[ap_const_lv32_5];
assign tmp_2359_fu_26438_p3 = bt_sign_th_V49_3_fu_26116_p3[ap_const_lv32_5];
assign tmp_2360_fu_26467_p3 = tmp_584_fu_26151_p2[ap_const_lv32_1];
assign tmp_2361_fu_26489_p3 = tmp_584_fu_26151_p2[ap_const_lv32_2];
assign tmp_2362_fu_26507_p1 = bt_si_V59_3_fu_26271_p3[0:0];
assign tmp_2363_fu_26530_p3 = bt_si_V59_3_fu_26271_p3[ap_const_lv32_2];
assign tmp_2364_fu_26557_p3 = bt_si_V59_3_fu_26271_p3[ap_const_lv32_3];
assign tmp_2365_fu_26570_p3 = bt_si_V59_3_fu_26271_p3[ap_const_lv32_4];
assign tmp_2366_fu_26781_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_11];
assign tmp_2367_fu_26789_p1 = bt_sign_ph_V47_4_fu_26718_p3[0:0];
assign tmp_2368_fu_26798_p1 = bt_sign_th_V49_4_fu_26726_p3[0:0];
assign tmp_2369_fu_26807_p3 = bt_sign_ph_V47_4_fu_26718_p3[ap_const_lv32_1];
assign tmp_2370_fu_26820_p3 = bt_sign_th_V49_4_fu_26726_p3[ap_const_lv32_1];
assign tmp_2371_fu_26833_p3 = bt_sign_ph_V47_4_fu_26718_p3[ap_const_lv32_2];
assign tmp_2372_fu_26846_p3 = bt_sign_th_V49_4_fu_26726_p3[ap_const_lv32_2];
assign tmp_2373_fu_26859_p3 = bt_sign_ph_V47_4_fu_26718_p3[ap_const_lv32_3];
assign tmp_2374_fu_26872_p3 = bt_sign_th_V49_4_fu_26726_p3[ap_const_lv32_3];
assign tmp_2375_fu_26885_p3 = bt_sign_ph_V47_4_fu_26718_p3[ap_const_lv32_4];
assign tmp_2376_fu_26898_p3 = bt_sign_th_V49_4_fu_26726_p3[ap_const_lv32_4];
assign tmp_2377_fu_26911_p3 = bt_sign_ph_V47_4_fu_26718_p3[ap_const_lv32_5];
assign tmp_2378_fu_26940_p3 = bt_sign_th_V49_4_fu_26726_p3[ap_const_lv32_5];
assign tmp_2379_fu_26969_p1 = bt_ci_V57_4_fu_26749_p3[1:0];
assign tmp_2380_fu_26997_p1 = bt_si_V59_4_fu_26773_p3[0:0];
assign tmp_2381_fu_27006_p1 = bt_ci_V57167_4_fu_26757_p3[2:0];
assign tmp_2382_fu_27016_p3 = bt_ci_V57167_4_fu_26757_p3[ap_const_lv32_3];
assign tmp_2383_fu_27032_p3 = bt_si_V59_4_fu_26773_p3[ap_const_lv32_2];
assign tmp_2384_fu_27045_p3 = bt_si_V59_4_fu_26773_p3[ap_const_lv32_3];
assign tmp_2385_fu_27058_p3 = bt_si_V59_4_fu_26773_p3[ap_const_lv32_4];
assign tmp_2386_fu_27261_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_12];
assign tmp_2387_fu_27269_p1 = bt_sign_ph_V47_5_fu_27206_p3[0:0];
assign tmp_2388_fu_27278_p1 = bt_sign_th_V49_5_fu_27214_p3[0:0];
assign tmp_2389_fu_27287_p3 = bt_sign_ph_V47_5_fu_27206_p3[ap_const_lv32_1];
assign tmp_2390_fu_27300_p3 = bt_sign_th_V49_5_fu_27214_p3[ap_const_lv32_1];
assign tmp_2391_fu_27313_p3 = bt_sign_ph_V47_5_fu_27206_p3[ap_const_lv32_2];
assign tmp_2392_fu_27326_p3 = bt_sign_th_V49_5_fu_27214_p3[ap_const_lv32_2];
assign tmp_2393_fu_27339_p3 = bt_sign_ph_V47_5_fu_27206_p3[ap_const_lv32_3];
assign tmp_2394_fu_27352_p3 = bt_sign_th_V49_5_fu_27214_p3[ap_const_lv32_3];
assign tmp_2395_fu_27365_p3 = bt_sign_ph_V47_5_fu_27206_p3[ap_const_lv32_4];
assign tmp_2396_fu_27378_p3 = bt_sign_th_V49_5_fu_27214_p3[ap_const_lv32_4];
assign tmp_2397_fu_27391_p3 = bt_sign_ph_V47_5_fu_27206_p3[ap_const_lv32_5];
assign tmp_2398_fu_27420_p3 = bt_sign_th_V49_5_fu_27214_p3[ap_const_lv32_5];
assign tmp_2399_fu_27449_p1 = bt_si_V59_5_fu_27253_p3[0:0];
assign tmp_2400_fu_27458_p3 = bt_si_V59_5_fu_27253_p3[ap_const_lv32_2];
assign tmp_2401_fu_27471_p3 = bt_si_V59_5_fu_27253_p3[ap_const_lv32_3];
assign tmp_2402_fu_27484_p3 = bt_si_V59_5_fu_27253_p3[ap_const_lv32_4];
assign tmp_2403_fu_27679_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_13];
assign tmp_2404_fu_27687_p1 = bt_sign_ph_V47_6_fu_27632_p3[0:0];
assign tmp_2405_fu_27696_p1 = bt_sign_th_V49_6_fu_27640_p3[0:0];
assign tmp_2406_fu_27705_p3 = bt_sign_ph_V47_6_fu_27632_p3[ap_const_lv32_1];
assign tmp_2407_fu_27718_p3 = bt_sign_th_V49_6_fu_27640_p3[ap_const_lv32_1];
assign tmp_2408_fu_27731_p3 = bt_sign_ph_V47_6_fu_27632_p3[ap_const_lv32_2];
assign tmp_2409_fu_27744_p3 = bt_sign_th_V49_6_fu_27640_p3[ap_const_lv32_2];
assign tmp_2410_fu_27757_p3 = bt_sign_ph_V47_6_fu_27632_p3[ap_const_lv32_3];
assign tmp_2411_fu_27770_p3 = bt_sign_th_V49_6_fu_27640_p3[ap_const_lv32_3];
assign tmp_2412_fu_27783_p3 = bt_sign_ph_V47_6_fu_27632_p3[ap_const_lv32_4];
assign tmp_2413_fu_27796_p3 = bt_sign_th_V49_6_fu_27640_p3[ap_const_lv32_4];
assign tmp_2414_fu_27809_p3 = bt_sign_ph_V47_6_fu_27632_p3[ap_const_lv32_5];
assign tmp_2415_fu_27838_p3 = bt_sign_th_V49_6_fu_27640_p3[ap_const_lv32_5];
assign tmp_2416_fu_27867_p1 = bt_si_V59_6_fu_27671_p3[0:0];
assign tmp_2417_fu_27876_p3 = bt_si_V59_6_fu_27671_p3[ap_const_lv32_2];
assign tmp_2418_fu_27889_p3 = bt_si_V59_6_fu_27671_p3[ap_const_lv32_3];
assign tmp_2419_fu_27902_p3 = bt_si_V59_6_fu_27671_p3[ap_const_lv32_4];
assign tmp_2420_fu_28073_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_0);
assign tmp_2421_fu_28109_p2 = (tmp_2386_fu_27261_p3 | tmp_2403_fu_27679_p3);
assign tmp_2422_fu_28123_p1 = bt_ci_V57167_5_fu_27245_p3[2:0];
assign tmp_2423_fu_28127_p2 = (tmp_2422_fu_28123_p1 | tmp1393_fu_28115_p3);
assign tmp_2424_fu_28133_p3 = bt_ci_V57167_5_fu_27245_p3[ap_const_lv32_3];
assign tmp_2425_fu_28149_p2 = (tmp_2366_fu_26781_p3 | tmp_2386_fu_27261_p3);
assign tmp_2426_fu_28163_p1 = bt_ci_V57168_4_fu_26765_p3[2:0];
assign tmp_2427_fu_28167_p2 = (tmp_2426_fu_28163_p1 | r_V_177_1_7_2_fu_28101_p3);
assign tmp_2428_fu_28173_p3 = bt_ci_V57168_4_fu_26765_p3[ap_const_lv32_3];
assign tmp_2429_fu_28181_p2 = (tmp_2427_fu_28167_p2 | tmp1394_fu_28155_p3);
assign tmp_2430_fu_28203_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_14];
assign tmp_2431_fu_28211_p1 = bt_sign_ph_V47_7_fu_28050_p3[0:0];
assign tmp_2432_fu_28220_p1 = bt_sign_th_V49_7_fu_28058_p3[0:0];
assign tmp_2433_fu_28229_p3 = bt_sign_ph_V47_7_fu_28050_p3[ap_const_lv32_1];
assign tmp_2434_fu_28242_p3 = bt_sign_th_V49_7_fu_28058_p3[ap_const_lv32_1];
assign tmp_2435_fu_28255_p3 = bt_sign_ph_V47_7_fu_28050_p3[ap_const_lv32_2];
assign tmp_2436_fu_28268_p3 = bt_sign_th_V49_7_fu_28058_p3[ap_const_lv32_2];
assign tmp_2437_fu_28281_p3 = bt_sign_ph_V47_7_fu_28050_p3[ap_const_lv32_3];
assign tmp_2438_fu_28294_p3 = bt_sign_th_V49_7_fu_28058_p3[ap_const_lv32_3];
assign tmp_2439_fu_28307_p3 = bt_sign_ph_V47_7_fu_28050_p3[ap_const_lv32_4];
assign tmp_2440_fu_28320_p3 = bt_sign_th_V49_7_fu_28058_p3[ap_const_lv32_4];
assign tmp_2441_fu_28333_p3 = bt_sign_ph_V47_7_fu_28050_p3[ap_const_lv32_5];
assign tmp_2442_fu_28362_p3 = bt_sign_th_V49_7_fu_28058_p3[ap_const_lv32_5];
assign tmp_2443_fu_28391_p1 = bt_ci_V57_7_fu_28095_p2[1:0];
assign tmp_2444_fu_28419_p1 = bt_si_V59_7_fu_28195_p3[0:0];
assign tmp_2445_fu_28442_p3 = bt_si_V59_7_fu_28195_p3[ap_const_lv32_2];
assign tmp_2446_fu_28469_p3 = bt_si_V59_7_fu_28195_p3[ap_const_lv32_3];
assign tmp_2447_fu_28482_p3 = bt_si_V59_7_fu_28195_p3[ap_const_lv32_4];
assign tmp_2448_fu_28685_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_15];
assign tmp_2449_fu_28693_p1 = bt_sign_ph_V47_8_fu_28630_p3[0:0];
assign tmp_2450_fu_28702_p1 = bt_sign_th_V49_8_fu_28638_p3[0:0];
assign tmp_2451_fu_28711_p3 = bt_sign_ph_V47_8_fu_28630_p3[ap_const_lv32_1];
assign tmp_2452_fu_28724_p3 = bt_sign_th_V49_8_fu_28638_p3[ap_const_lv32_1];
assign tmp_2453_fu_28737_p3 = bt_sign_ph_V47_8_fu_28630_p3[ap_const_lv32_2];
assign tmp_2454_fu_28750_p3 = bt_sign_th_V49_8_fu_28638_p3[ap_const_lv32_2];
assign tmp_2455_fu_28763_p3 = bt_sign_ph_V47_8_fu_28630_p3[ap_const_lv32_3];
assign tmp_2456_fu_28776_p3 = bt_sign_th_V49_8_fu_28638_p3[ap_const_lv32_3];
assign tmp_2457_fu_28789_p3 = bt_sign_ph_V47_8_fu_28630_p3[ap_const_lv32_4];
assign tmp_2458_fu_28802_p3 = bt_sign_th_V49_8_fu_28638_p3[ap_const_lv32_4];
assign tmp_2459_fu_28815_p3 = bt_sign_ph_V47_8_fu_28630_p3[ap_const_lv32_5];
assign tmp_2460_fu_28844_p3 = bt_sign_th_V49_8_fu_28638_p3[ap_const_lv32_5];
assign tmp_2461_fu_28873_p1 = bt_ci_V57_8_fu_28653_p3[1:0];
assign tmp_2462_fu_28901_p1 = bt_si_V59_8_fu_28677_p3[0:0];
assign tmp_2463_fu_28910_p1 = bt_ci_V57167_8_fu_28661_p3[2:0];
assign tmp_2464_fu_28920_p3 = bt_ci_V57167_8_fu_28661_p3[ap_const_lv32_3];
assign tmp_2465_fu_28936_p3 = bt_si_V59_8_fu_28677_p3[ap_const_lv32_2];
assign tmp_2466_fu_28949_p3 = bt_si_V59_8_fu_28677_p3[ap_const_lv32_3];
assign tmp_2467_fu_28962_p3 = bt_si_V59_8_fu_28677_p3[ap_const_lv32_4];
assign tmp_2468_fu_29173_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_16];
assign tmp_2469_fu_29181_p1 = bt_sign_ph_V47_9_fu_29110_p3[0:0];
assign tmp_2470_fu_29190_p1 = bt_sign_th_V49_9_fu_29118_p3[0:0];
assign tmp_2471_fu_29199_p3 = bt_sign_ph_V47_9_fu_29110_p3[ap_const_lv32_1];
assign tmp_2472_fu_29212_p3 = bt_sign_th_V49_9_fu_29118_p3[ap_const_lv32_1];
assign tmp_2473_fu_29225_p3 = bt_sign_ph_V47_9_fu_29110_p3[ap_const_lv32_2];
assign tmp_2474_fu_29238_p3 = bt_sign_th_V49_9_fu_29118_p3[ap_const_lv32_2];
assign tmp_2475_fu_29251_p3 = bt_sign_ph_V47_9_fu_29110_p3[ap_const_lv32_3];
assign tmp_2476_fu_29264_p3 = bt_sign_th_V49_9_fu_29118_p3[ap_const_lv32_3];
assign tmp_2477_fu_29277_p3 = bt_sign_ph_V47_9_fu_29110_p3[ap_const_lv32_4];
assign tmp_2478_fu_29290_p3 = bt_sign_th_V49_9_fu_29118_p3[ap_const_lv32_4];
assign tmp_2479_fu_29303_p3 = bt_sign_ph_V47_9_fu_29110_p3[ap_const_lv32_5];
assign tmp_247_fu_6584_p2 = (tmp_1511_fu_6580_p1 | kill1_t_V_9_s_fu_6540_p3);
assign tmp_2480_fu_29332_p3 = bt_sign_th_V49_9_fu_29118_p3[ap_const_lv32_5];
assign tmp_2481_fu_29361_p1 = bt_si_V59_9_fu_29165_p3[0:0];
assign tmp_2482_fu_29370_p3 = bt_si_V59_9_fu_29165_p3[ap_const_lv32_2];
assign tmp_2483_fu_29383_p3 = bt_si_V59_9_fu_29165_p3[ap_const_lv32_3];
assign tmp_2484_fu_29396_p3 = bt_si_V59_9_fu_29165_p3[ap_const_lv32_4];
assign tmp_2485_fu_29583_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_17];
assign tmp_2486_fu_29591_p1 = bt_sign_ph_V47_s_fu_29544_p3[0:0];
assign tmp_2487_fu_29600_p1 = bt_sign_th_V49_s_fu_29552_p3[0:0];
assign tmp_2488_fu_29609_p3 = bt_sign_ph_V47_s_fu_29544_p3[ap_const_lv32_1];
assign tmp_2489_fu_29622_p3 = bt_sign_th_V49_s_fu_29552_p3[ap_const_lv32_1];
assign tmp_248_fu_6610_p2 = (tmp_1513_fu_6606_p1 | kill1_t_V_8_s_fu_6508_p3);
assign tmp_2490_fu_29635_p3 = bt_sign_ph_V47_s_fu_29544_p3[ap_const_lv32_2];
assign tmp_2491_fu_29648_p3 = bt_sign_th_V49_s_fu_29552_p3[ap_const_lv32_2];
assign tmp_2492_fu_29661_p3 = bt_sign_ph_V47_s_fu_29544_p3[ap_const_lv32_3];
assign tmp_2493_fu_29674_p3 = bt_sign_th_V49_s_fu_29552_p3[ap_const_lv32_3];
assign tmp_2494_fu_29687_p3 = bt_sign_ph_V47_s_fu_29544_p3[ap_const_lv32_4];
assign tmp_2495_fu_29700_p3 = bt_sign_th_V49_s_fu_29552_p3[ap_const_lv32_4];
assign tmp_2496_fu_29713_p3 = bt_sign_ph_V47_s_fu_29544_p3[ap_const_lv32_5];
assign tmp_2497_fu_29742_p3 = bt_sign_th_V49_s_fu_29552_p3[ap_const_lv32_5];
assign tmp_2498_fu_29771_p1 = bt_si_V59_s_fu_29575_p3[0:0];
assign tmp_2499_fu_29780_p3 = bt_si_V59_s_fu_29575_p3[ap_const_lv32_2];
assign tmp_249_fu_6648_p2 = (tmp_1515_fu_6644_p1 | kill1_t_V_7_8_fu_6428_p3);
assign tmp_2500_fu_29793_p3 = bt_si_V59_s_fu_29575_p3[ap_const_lv32_3];
assign tmp_2501_fu_29806_p3 = bt_si_V59_s_fu_29575_p3[ap_const_lv32_4];
assign tmp_2502_fu_31231_p2 = (tmp_2468_fu_29173_p3 | tmp_2430_fu_28203_p3);
assign tmp_2503_fu_31271_p2 = (tmp_2283_fu_24748_p3 | tmp_2302_fu_25327_p3);
assign tmp_2504_fu_31291_p2 = (tmp_2319_fu_25737_p3 | tmp_2485_fu_29583_p3);
assign tmp_2505_fu_31323_p3 = ((tmp_2302_fu_25327_p3[0:0] === 1'b1) ? 1'b1 : 1'b0);
assign tmp_2506_fu_31331_p2 = (tmp_2284_fu_24911_p3 | tmp_2283_fu_24748_p3);
assign tmp_2507_fu_31345_p2 = (tmp_2347_fu_26279_p3 | tmp_2366_fu_26781_p3);
assign tmp_2508_fu_31351_p3 = r_V_176_1_3_fu_26131_p3[ap_const_lv32_1];
assign tmp_2509_fu_31373_p3 = ((tmp_2403_fu_27679_p3[0:0] === 1'b1) ? 1'b1 : 1'b0);
assign tmp_250_fu_6662_p3 = {{tmp_1516_fu_6654_p3}, {tmp_249_fu_6648_p2}};
assign tmp_2510_fu_31395_p2 = (tmp_2468_fu_29173_p3 | tmp_2485_fu_29583_p3);
assign tmp_2511_fu_31437_p3 = r_V_176_1_5_fu_27229_p3[ap_const_lv32_1];
assign tmp_2512_fu_31483_p3 = ((tmp_2485_fu_29583_p3[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_0);
assign tmp_2513_fu_31519_p1 = bt_ci_V57167_9_fu_29149_p3[2:0];
assign tmp_2514_fu_31523_p2 = (tmp_2513_fu_31519_p1 | tmp1617_fu_31511_p3);
assign tmp_2515_fu_31529_p3 = bt_ci_V57167_9_fu_29149_p3[ap_const_lv32_3];
assign tmp_2516_fu_31545_p1 = bt_ci_V57168_8_fu_28669_p3[2:0];
assign tmp_2517_fu_31549_p2 = (tmp_2516_fu_31545_p1 | r_V_177_1_9_3_fu_29157_p3);
assign tmp_2518_fu_31555_p3 = bt_ci_V57168_8_fu_28669_p3[ap_const_lv32_3];
assign tmp_2519_fu_31563_p2 = (tmp_2517_fu_31549_p2 | tmp1617_fu_31511_p3);
assign tmp_251_fu_6670_p2 = (tmp_250_fu_6662_p3 | tmp94_fu_6638_p2);
assign tmp_2520_fu_31585_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_18];
assign tmp_2521_fu_31748_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_19];
assign tmp_2522_fu_31756_p1 = bt_sign_ph_V2_fu_31719_p3[0:0];
assign tmp_2523_fu_31765_p1 = bt_sign_th_V2_fu_31726_p3[0:0];
assign tmp_2524_fu_31774_p3 = bt_sign_ph_V2_fu_31719_p3[ap_const_lv32_1];
assign tmp_2525_fu_31787_p3 = bt_sign_th_V2_fu_31726_p3[ap_const_lv32_1];
assign tmp_2526_fu_31800_p3 = bt_sign_ph_V2_fu_31719_p3[ap_const_lv32_2];
assign tmp_2527_fu_31813_p3 = bt_sign_th_V2_fu_31726_p3[ap_const_lv32_2];
assign tmp_2528_fu_31826_p3 = bt_sign_ph_V2_fu_31719_p3[ap_const_lv32_3];
assign tmp_2529_fu_31839_p3 = bt_sign_th_V2_fu_31726_p3[ap_const_lv32_3];
assign tmp_252_fu_6676_p4 = {{kill1_t_V_7_1_fu_6476_p3[ap_const_lv32_B : ap_const_lv32_A]}};
assign tmp_2530_fu_31852_p3 = bt_sign_ph_V2_fu_31719_p3[ap_const_lv32_4];
assign tmp_2531_fu_31865_p3 = bt_sign_th_V2_fu_31726_p3[ap_const_lv32_4];
assign tmp_2532_fu_31878_p3 = bt_sign_ph_V2_fu_31719_p3[ap_const_lv32_5];
assign tmp_2533_fu_31907_p3 = bt_sign_th_V2_fu_31726_p3[ap_const_lv32_5];
assign tmp_2534_fu_31936_p1 = bt_si_V2_fu_31740_p3[0:0];
assign tmp_2535_fu_31945_p3 = bt_si_V2_fu_31740_p3[ap_const_lv32_2];
assign tmp_2536_fu_31958_p3 = bt_si_V2_fu_31740_p3[ap_const_lv32_3];
assign tmp_2537_fu_31971_p3 = bt_si_V2_fu_31740_p3[ap_const_lv32_4];
assign tmp_2538_fu_32150_p2 = (tmp_2521_fu_31748_p3 | tmp_2520_fu_31585_p3);
assign tmp_2539_fu_32164_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_1A];
assign tmp_253_fu_6710_p2 = (tmp_1517_fu_6706_p1 | kill1_t_V_6_7_fu_6348_p3);
assign tmp_2540_fu_32172_p1 = bt_sign_ph_V48_1_fu_32119_p3[0:0];
assign tmp_2541_fu_32181_p1 = bt_sign_th_V50_1_fu_32127_p3[0:0];
assign tmp_2542_fu_32190_p3 = bt_sign_ph_V48_1_fu_32119_p3[ap_const_lv32_1];
assign tmp_2543_fu_32203_p3 = bt_sign_th_V50_1_fu_32127_p3[ap_const_lv32_1];
assign tmp_2544_fu_32216_p3 = bt_sign_ph_V48_1_fu_32119_p3[ap_const_lv32_2];
assign tmp_2545_fu_32229_p3 = bt_sign_th_V50_1_fu_32127_p3[ap_const_lv32_2];
assign tmp_2546_fu_32242_p3 = bt_sign_ph_V48_1_fu_32119_p3[ap_const_lv32_3];
assign tmp_2547_fu_32255_p3 = bt_sign_th_V50_1_fu_32127_p3[ap_const_lv32_3];
assign tmp_2548_fu_32268_p3 = bt_sign_ph_V48_1_fu_32119_p3[ap_const_lv32_4];
assign tmp_2549_fu_32281_p3 = bt_sign_th_V50_1_fu_32127_p3[ap_const_lv32_4];
assign tmp_254_fu_6716_p4 = {{kill1_t_V_5_9_fu_6300_p3[ap_const_lv32_9 : ap_const_lv32_8]}};
assign tmp_2550_fu_32294_p3 = bt_sign_ph_V48_1_fu_32119_p3[ap_const_lv32_5];
assign tmp_2551_fu_32323_p3 = bt_sign_th_V50_1_fu_32127_p3[ap_const_lv32_5];
assign tmp_2552_fu_32352_p1 = bt_si_V60_1_fu_32156_p3[0:0];
assign tmp_2553_fu_32361_p3 = bt_si_V60_1_fu_32156_p3[ap_const_lv32_2];
assign tmp_2554_fu_32374_p3 = bt_si_V60_1_fu_32156_p3[ap_const_lv32_3];
assign tmp_2555_fu_32387_p3 = bt_si_V60_1_fu_32156_p3[ap_const_lv32_4];
assign tmp_2556_fu_32574_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_1B];
assign tmp_2557_fu_32582_p1 = bt_sign_ph_V48_2_fu_32535_p3[0:0];
assign tmp_2558_fu_32591_p1 = bt_sign_th_V50_2_fu_32543_p3[0:0];
assign tmp_2559_fu_32600_p3 = bt_sign_ph_V48_2_fu_32535_p3[ap_const_lv32_1];
assign tmp_255_fu_6738_p2 = (tmp_1518_fu_6734_p1 | tmp98_fu_6726_p3);
assign tmp_2560_fu_32613_p3 = bt_sign_th_V50_2_fu_32543_p3[ap_const_lv32_1];
assign tmp_2561_fu_32626_p3 = bt_sign_ph_V48_2_fu_32535_p3[ap_const_lv32_2];
assign tmp_2562_fu_32639_p3 = bt_sign_th_V50_2_fu_32543_p3[ap_const_lv32_2];
assign tmp_2563_fu_32652_p3 = bt_sign_ph_V48_2_fu_32535_p3[ap_const_lv32_3];
assign tmp_2564_fu_32665_p3 = bt_sign_th_V50_2_fu_32543_p3[ap_const_lv32_3];
assign tmp_2565_fu_32678_p3 = bt_sign_ph_V48_2_fu_32535_p3[ap_const_lv32_4];
assign tmp_2566_fu_32691_p3 = bt_sign_th_V50_2_fu_32543_p3[ap_const_lv32_4];
assign tmp_2567_fu_32704_p3 = bt_sign_ph_V48_2_fu_32535_p3[ap_const_lv32_5];
assign tmp_2568_fu_32733_p3 = bt_sign_th_V50_2_fu_32543_p3[ap_const_lv32_5];
assign tmp_2569_fu_32762_p1 = bt_si_V60_2_fu_32566_p3[0:0];
assign tmp_256_fu_6764_p2 = (tmp_1520_fu_6760_p1 | kill1_t_V_6_9_fu_6380_p3);
assign tmp_2570_fu_32771_p3 = bt_si_V60_2_fu_32566_p3[ap_const_lv32_2];
assign tmp_2571_fu_32784_p3 = bt_si_V60_2_fu_32566_p3[ap_const_lv32_3];
assign tmp_2572_fu_32797_p3 = bt_si_V60_2_fu_32566_p3[ap_const_lv32_4];
assign tmp_2573_fu_32984_p1 = r_V_177_2_3_fu_32976_p3[2:0];
assign tmp_2574_fu_32994_p1 = r_V_177_2_3_fu_32976_p3[0:0];
assign tmp_2575_fu_32998_p2 = (tmp_2574_fu_32994_p1 | tmp_2538_fu_32150_p2);
assign tmp_2576_fu_33004_p4 = {{tmp_767_fu_32988_p2[ap_const_lv32_2 : ap_const_lv32_1]}};
assign tmp_2577_fu_33024_p2 = (tmp_2539_fu_32164_p3 | tmp_2556_fu_32574_p3);
assign tmp_2578_fu_33038_p1 = tmp_2520_fu_31585_p3;
assign tmp_2579_fu_33042_p3 = ((tmp_2521_fu_31748_p3[0:0] === 1'b1) ? ap_const_lv3_1 : tmp_2578_fu_33038_p1);
assign tmp_257_fu_6770_p4 = {{kill1_t_V_5_1_fu_6332_p3[ap_const_lv32_B : ap_const_lv32_A]}};
assign tmp_2580_fu_33050_p2 = (tmp_2579_fu_33042_p3 | tmp1621_fu_33030_p3);
assign tmp_2581_fu_33064_p2 = (tmp_2521_fu_31748_p3 | tmp_2539_fu_32164_p3);
assign tmp_2582_fu_33078_p3 = ((tmp_2556_fu_32574_p3[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_0);
assign tmp_2583_fu_33094_p2 = (tmp_768_fu_33086_p3 | tmp1622_fu_33070_p3);
assign tmp_2584_fu_33116_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_1C];
assign tmp_2585_fu_33124_p1 = bt_sign_ph_V48_3_fu_32945_p3[0:0];
assign tmp_2586_fu_33133_p1 = bt_sign_th_V50_3_fu_32953_p3[0:0];
assign tmp_2587_fu_33142_p3 = bt_sign_ph_V48_3_fu_32945_p3[ap_const_lv32_1];
assign tmp_2588_fu_33155_p3 = bt_sign_th_V50_3_fu_32953_p3[ap_const_lv32_1];
assign tmp_2589_fu_33168_p3 = bt_sign_ph_V48_3_fu_32945_p3[ap_const_lv32_2];
assign tmp_258_fu_6792_p2 = (tmp_1521_fu_6788_p1 | kill1_t_V_6_8_fu_6364_p3);
assign tmp_2590_fu_33181_p3 = bt_sign_th_V50_3_fu_32953_p3[ap_const_lv32_2];
assign tmp_2591_fu_33194_p3 = bt_sign_ph_V48_3_fu_32945_p3[ap_const_lv32_3];
assign tmp_2592_fu_33207_p3 = bt_sign_th_V50_3_fu_32953_p3[ap_const_lv32_3];
assign tmp_2593_fu_33220_p3 = bt_sign_ph_V48_3_fu_32945_p3[ap_const_lv32_4];
assign tmp_2594_fu_33233_p3 = bt_sign_th_V50_3_fu_32953_p3[ap_const_lv32_4];
assign tmp_2595_fu_33246_p3 = bt_sign_ph_V48_3_fu_32945_p3[ap_const_lv32_5];
assign tmp_2596_fu_33275_p3 = bt_sign_th_V50_3_fu_32953_p3[ap_const_lv32_5];
assign tmp_2597_fu_33304_p3 = tmp_767_fu_32988_p2[ap_const_lv32_1];
assign tmp_2598_fu_33326_p3 = tmp_767_fu_32988_p2[ap_const_lv32_2];
assign tmp_2599_fu_33344_p1 = bt_si_V60_3_fu_33108_p3[0:0];
assign tmp_259_fu_6798_p4 = {{kill1_t_V_6_1_fu_6412_p3[ap_const_lv32_B : ap_const_lv32_9]}};
assign tmp_2600_fu_33367_p3 = bt_si_V60_3_fu_33108_p3[ap_const_lv32_2];
assign tmp_2601_fu_33394_p3 = bt_si_V60_3_fu_33108_p3[ap_const_lv32_3];
assign tmp_2602_fu_33407_p3 = bt_si_V60_3_fu_33108_p3[ap_const_lv32_4];
assign tmp_2603_fu_33618_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_1D];
assign tmp_2604_fu_33626_p1 = bt_sign_ph_V48_4_fu_33555_p3[0:0];
assign tmp_2605_fu_33635_p1 = bt_sign_th_V50_4_fu_33563_p3[0:0];
assign tmp_2606_fu_33644_p3 = bt_sign_ph_V48_4_fu_33555_p3[ap_const_lv32_1];
assign tmp_2607_fu_33657_p3 = bt_sign_th_V50_4_fu_33563_p3[ap_const_lv32_1];
assign tmp_2608_fu_33670_p3 = bt_sign_ph_V48_4_fu_33555_p3[ap_const_lv32_2];
assign tmp_2609_fu_33683_p3 = bt_sign_th_V50_4_fu_33563_p3[ap_const_lv32_2];
assign tmp_260_fu_6826_p2 = (tmp_1522_fu_6822_p1 | tmp99_fu_6752_p3);
assign tmp_2610_fu_33696_p3 = bt_sign_ph_V48_4_fu_33555_p3[ap_const_lv32_3];
assign tmp_2611_fu_33709_p3 = bt_sign_th_V50_4_fu_33563_p3[ap_const_lv32_3];
assign tmp_2612_fu_33722_p3 = bt_sign_ph_V48_4_fu_33555_p3[ap_const_lv32_4];
assign tmp_2613_fu_33735_p3 = bt_sign_th_V50_4_fu_33563_p3[ap_const_lv32_4];
assign tmp_2614_fu_33748_p3 = bt_sign_ph_V48_4_fu_33555_p3[ap_const_lv32_5];
assign tmp_2615_fu_33777_p3 = bt_sign_th_V50_4_fu_33563_p3[ap_const_lv32_5];
assign tmp_2616_fu_33806_p1 = bt_ci_V58_4_fu_33586_p3[1:0];
assign tmp_2617_fu_33834_p1 = bt_si_V60_4_fu_33610_p3[0:0];
assign tmp_2618_fu_33843_p1 = bt_ci_V58171_4_fu_33594_p3[2:0];
assign tmp_2619_fu_33853_p3 = bt_ci_V58171_4_fu_33594_p3[ap_const_lv32_3];
assign tmp_261_fu_6858_p2 = (tmp_1524_fu_6854_p1 | kill1_t_V_3_7_fu_6060_p3);
assign tmp_2620_fu_33869_p3 = bt_si_V60_4_fu_33610_p3[ap_const_lv32_2];
assign tmp_2621_fu_33882_p3 = bt_si_V60_4_fu_33610_p3[ap_const_lv32_3];
assign tmp_2622_fu_33895_p3 = bt_si_V60_4_fu_33610_p3[ap_const_lv32_4];
assign tmp_2623_fu_34098_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_1E];
assign tmp_2624_fu_34106_p1 = bt_sign_ph_V48_5_fu_34043_p3[0:0];
assign tmp_2625_fu_34115_p1 = bt_sign_th_V50_5_fu_34051_p3[0:0];
assign tmp_2626_fu_34124_p3 = bt_sign_ph_V48_5_fu_34043_p3[ap_const_lv32_1];
assign tmp_2627_fu_34137_p3 = bt_sign_th_V50_5_fu_34051_p3[ap_const_lv32_1];
assign tmp_2628_fu_34150_p3 = bt_sign_ph_V48_5_fu_34043_p3[ap_const_lv32_2];
assign tmp_2629_fu_34163_p3 = bt_sign_th_V50_5_fu_34051_p3[ap_const_lv32_2];
assign tmp_262_fu_6864_p4 = {{kill1_t_V_6_s_fu_6396_p3[ap_const_lv32_9 : ap_const_lv32_8]}};
assign tmp_2630_fu_34176_p3 = bt_sign_ph_V48_5_fu_34043_p3[ap_const_lv32_3];
assign tmp_2631_fu_34189_p3 = bt_sign_th_V50_5_fu_34051_p3[ap_const_lv32_3];
assign tmp_2632_fu_34202_p3 = bt_sign_ph_V48_5_fu_34043_p3[ap_const_lv32_4];
assign tmp_2633_fu_34215_p3 = bt_sign_th_V50_5_fu_34051_p3[ap_const_lv32_4];
assign tmp_2634_fu_34228_p3 = bt_sign_ph_V48_5_fu_34043_p3[ap_const_lv32_5];
assign tmp_2635_fu_34257_p3 = bt_sign_th_V50_5_fu_34051_p3[ap_const_lv32_5];
assign tmp_2636_fu_34286_p1 = bt_si_V60_5_fu_34090_p3[0:0];
assign tmp_2637_fu_34295_p3 = bt_si_V60_5_fu_34090_p3[ap_const_lv32_2];
assign tmp_2638_fu_34308_p3 = bt_si_V60_5_fu_34090_p3[ap_const_lv32_3];
assign tmp_2639_fu_34321_p3 = bt_si_V60_5_fu_34090_p3[ap_const_lv32_4];
assign tmp_263_fu_6878_p2 = (tmp_1525_fu_6874_p1 | kill1_t_V_3_6_fu_6044_p3);
assign tmp_2640_fu_34516_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_1F];
assign tmp_2641_fu_34524_p1 = bt_sign_ph_V48_6_fu_34469_p3[0:0];
assign tmp_2642_fu_34533_p1 = bt_sign_th_V50_6_fu_34477_p3[0:0];
assign tmp_2643_fu_34542_p3 = bt_sign_ph_V48_6_fu_34469_p3[ap_const_lv32_1];
assign tmp_2644_fu_34555_p3 = bt_sign_th_V50_6_fu_34477_p3[ap_const_lv32_1];
assign tmp_2645_fu_34568_p3 = bt_sign_ph_V48_6_fu_34469_p3[ap_const_lv32_2];
assign tmp_2646_fu_34581_p3 = bt_sign_th_V50_6_fu_34477_p3[ap_const_lv32_2];
assign tmp_2647_fu_34594_p3 = bt_sign_ph_V48_6_fu_34469_p3[ap_const_lv32_3];
assign tmp_2648_fu_34607_p3 = bt_sign_th_V50_6_fu_34477_p3[ap_const_lv32_3];
assign tmp_2649_fu_34620_p3 = bt_sign_ph_V48_6_fu_34469_p3[ap_const_lv32_4];
assign tmp_264_fu_6884_p4 = {{kill1_t_V_3_9_fu_6092_p3[ap_const_lv32_9 : ap_const_lv32_7]}};
assign tmp_2650_fu_34633_p3 = bt_sign_th_V50_6_fu_34477_p3[ap_const_lv32_4];
assign tmp_2651_fu_34646_p3 = bt_sign_ph_V48_6_fu_34469_p3[ap_const_lv32_5];
assign tmp_2652_fu_34675_p3 = bt_sign_th_V50_6_fu_34477_p3[ap_const_lv32_5];
assign tmp_2653_fu_34704_p1 = bt_si_V60_6_fu_34508_p3[0:0];
assign tmp_2654_fu_34713_p3 = bt_si_V60_6_fu_34508_p3[ap_const_lv32_2];
assign tmp_2655_fu_34726_p3 = bt_si_V60_6_fu_34508_p3[ap_const_lv32_3];
assign tmp_2656_fu_34739_p3 = bt_si_V60_6_fu_34508_p3[ap_const_lv32_4];
assign tmp_2657_fu_34910_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_0);
assign tmp_2658_fu_34946_p2 = (tmp_2623_fu_34098_p3 | tmp_2640_fu_34516_p3);
assign tmp_2659_fu_34960_p1 = bt_ci_V58171_5_fu_34082_p3[2:0];
assign tmp_265_fu_6902_p3 = {{tmp_262_fu_6864_p4}, {tmp_261_fu_6858_p2}};
assign tmp_2660_fu_34964_p2 = (tmp_2659_fu_34960_p1 | tmp1625_fu_34952_p3);
assign tmp_2661_fu_34970_p3 = bt_ci_V58171_5_fu_34082_p3[ap_const_lv32_3];
assign tmp_2662_fu_34986_p2 = (tmp_2603_fu_33618_p3 | tmp_2623_fu_34098_p3);
assign tmp_2663_fu_35000_p1 = bt_ci_V58172_4_fu_33602_p3[2:0];
assign tmp_2664_fu_35004_p2 = (tmp_2663_fu_35000_p1 | r_V_177_2_7_2_fu_34938_p3);
assign tmp_2665_fu_35010_p3 = bt_ci_V58172_4_fu_33602_p3[ap_const_lv32_3];
assign tmp_2666_fu_35018_p2 = (tmp_2664_fu_35004_p2 | tmp1626_fu_34992_p3);
assign tmp_2667_fu_35040_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_20];
assign tmp_2668_fu_35048_p1 = bt_sign_ph_V48_7_fu_34887_p3[0:0];
assign tmp_2669_fu_35057_p1 = bt_sign_th_V50_7_fu_34895_p3[0:0];
assign tmp_266_fu_6910_p2 = (tmp_265_fu_6902_p3 | tmp105_fu_6894_p3);
assign tmp_2670_fu_35066_p3 = bt_sign_ph_V48_7_fu_34887_p3[ap_const_lv32_1];
assign tmp_2671_fu_35079_p3 = bt_sign_th_V50_7_fu_34895_p3[ap_const_lv32_1];
assign tmp_2672_fu_35092_p3 = bt_sign_ph_V48_7_fu_34887_p3[ap_const_lv32_2];
assign tmp_2673_fu_35105_p3 = bt_sign_th_V50_7_fu_34895_p3[ap_const_lv32_2];
assign tmp_2674_fu_35118_p3 = bt_sign_ph_V48_7_fu_34887_p3[ap_const_lv32_3];
assign tmp_2675_fu_35131_p3 = bt_sign_th_V50_7_fu_34895_p3[ap_const_lv32_3];
assign tmp_2676_fu_35144_p3 = bt_sign_ph_V48_7_fu_34887_p3[ap_const_lv32_4];
assign tmp_2677_fu_35157_p3 = bt_sign_th_V50_7_fu_34895_p3[ap_const_lv32_4];
assign tmp_2678_fu_35170_p3 = bt_sign_ph_V48_7_fu_34887_p3[ap_const_lv32_5];
assign tmp_2679_fu_35199_p3 = bt_sign_th_V50_7_fu_34895_p3[ap_const_lv32_5];
assign tmp_267_fu_6936_p2 = (tmp_1527_fu_6932_p1 | kill1_t_V_3_8_fu_6076_p3);
assign tmp_2680_fu_35228_p1 = bt_ci_V58_7_fu_34932_p2[1:0];
assign tmp_2681_fu_35256_p1 = bt_si_V60_7_fu_35032_p3[0:0];
assign tmp_2682_fu_35279_p3 = bt_si_V60_7_fu_35032_p3[ap_const_lv32_2];
assign tmp_2683_fu_35306_p3 = bt_si_V60_7_fu_35032_p3[ap_const_lv32_3];
assign tmp_2684_fu_35319_p3 = bt_si_V60_7_fu_35032_p3[ap_const_lv32_4];
assign tmp_2685_fu_35522_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_21];
assign tmp_2686_fu_35530_p1 = bt_sign_ph_V48_8_fu_35467_p3[0:0];
assign tmp_2687_fu_35539_p1 = bt_sign_th_V50_8_fu_35475_p3[0:0];
assign tmp_2688_fu_35548_p3 = bt_sign_ph_V48_8_fu_35467_p3[ap_const_lv32_1];
assign tmp_2689_fu_35561_p3 = bt_sign_th_V50_8_fu_35475_p3[ap_const_lv32_1];
assign tmp_268_fu_6942_p4 = {{kill1_t_V_3_1_fu_6124_p3[ap_const_lv32_A : ap_const_lv32_9]}};
assign tmp_2690_fu_35574_p3 = bt_sign_ph_V48_8_fu_35467_p3[ap_const_lv32_2];
assign tmp_2691_fu_35587_p3 = bt_sign_th_V50_8_fu_35475_p3[ap_const_lv32_2];
assign tmp_2692_fu_35600_p3 = bt_sign_ph_V48_8_fu_35467_p3[ap_const_lv32_3];
assign tmp_2693_fu_35613_p3 = bt_sign_th_V50_8_fu_35475_p3[ap_const_lv32_3];
assign tmp_2694_fu_35626_p3 = bt_sign_ph_V48_8_fu_35467_p3[ap_const_lv32_4];
assign tmp_2695_fu_35639_p3 = bt_sign_th_V50_8_fu_35475_p3[ap_const_lv32_4];
assign tmp_2696_fu_35652_p3 = bt_sign_ph_V48_8_fu_35467_p3[ap_const_lv32_5];
assign tmp_2697_fu_35681_p3 = bt_sign_th_V50_8_fu_35475_p3[ap_const_lv32_5];
assign tmp_2698_fu_35710_p1 = bt_ci_V58_8_fu_35490_p3[1:0];
assign tmp_2699_fu_35738_p1 = bt_si_V60_8_fu_35514_p3[0:0];
assign tmp_269_fu_6956_p2 = (tmp_1528_fu_6952_p1 | kill1_t_V_4_6_fu_6156_p3);
assign tmp_2700_fu_35747_p1 = bt_ci_V58171_8_fu_35498_p3[2:0];
assign tmp_2701_fu_35757_p3 = bt_ci_V58171_8_fu_35498_p3[ap_const_lv32_3];
assign tmp_2702_fu_35773_p3 = bt_si_V60_8_fu_35514_p3[ap_const_lv32_2];
assign tmp_2703_fu_35786_p3 = bt_si_V60_8_fu_35514_p3[ap_const_lv32_3];
assign tmp_2704_fu_35799_p3 = bt_si_V60_8_fu_35514_p3[ap_const_lv32_4];
assign tmp_2705_fu_36010_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_22];
assign tmp_2706_fu_36018_p1 = bt_sign_ph_V48_9_fu_35947_p3[0:0];
assign tmp_2707_fu_36027_p1 = bt_sign_th_V50_9_fu_35955_p3[0:0];
assign tmp_2708_fu_36036_p3 = bt_sign_ph_V48_9_fu_35947_p3[ap_const_lv32_1];
assign tmp_2709_fu_36049_p3 = bt_sign_th_V50_9_fu_35955_p3[ap_const_lv32_1];
assign tmp_270_fu_6962_p4 = {{kill1_t_V_3_s_fu_6108_p3[ap_const_lv32_A : ap_const_lv32_7]}};
assign tmp_2710_fu_36062_p3 = bt_sign_ph_V48_9_fu_35947_p3[ap_const_lv32_2];
assign tmp_2711_fu_36075_p3 = bt_sign_th_V50_9_fu_35955_p3[ap_const_lv32_2];
assign tmp_2712_fu_36088_p3 = bt_sign_ph_V48_9_fu_35947_p3[ap_const_lv32_3];
assign tmp_2713_fu_36101_p3 = bt_sign_th_V50_9_fu_35955_p3[ap_const_lv32_3];
assign tmp_2714_fu_36114_p3 = bt_sign_ph_V48_9_fu_35947_p3[ap_const_lv32_4];
assign tmp_2715_fu_36127_p3 = bt_sign_th_V50_9_fu_35955_p3[ap_const_lv32_4];
assign tmp_2716_fu_36140_p3 = bt_sign_ph_V48_9_fu_35947_p3[ap_const_lv32_5];
assign tmp_2717_fu_36169_p3 = bt_sign_th_V50_9_fu_35955_p3[ap_const_lv32_5];
assign tmp_2718_fu_36198_p1 = bt_si_V60_9_fu_36002_p3[0:0];
assign tmp_2719_fu_36207_p3 = bt_si_V60_9_fu_36002_p3[ap_const_lv32_2];
assign tmp_271_fu_6980_p3 = {{tmp_268_fu_6942_p4}, {tmp_267_fu_6936_p2}};
assign tmp_2720_fu_36220_p3 = bt_si_V60_9_fu_36002_p3[ap_const_lv32_3];
assign tmp_2721_fu_36233_p3 = bt_si_V60_9_fu_36002_p3[ap_const_lv32_4];
assign tmp_2722_fu_36420_p3 = winner_V_10_fu_17891_p3[ap_const_lv32_23];
assign tmp_2723_fu_36428_p1 = bt_sign_ph_V48_s_fu_36381_p3[0:0];
assign tmp_2724_fu_36437_p1 = bt_sign_th_V50_s_fu_36389_p3[0:0];
assign tmp_2725_fu_36446_p3 = bt_sign_ph_V48_s_fu_36381_p3[ap_const_lv32_1];
assign tmp_2726_fu_36459_p3 = bt_sign_th_V50_s_fu_36389_p3[ap_const_lv32_1];
assign tmp_2727_fu_36472_p3 = bt_sign_ph_V48_s_fu_36381_p3[ap_const_lv32_2];
assign tmp_2728_fu_36485_p3 = bt_sign_th_V50_s_fu_36389_p3[ap_const_lv32_2];
assign tmp_2729_fu_36498_p3 = bt_sign_ph_V48_s_fu_36381_p3[ap_const_lv32_3];
assign tmp_272_fu_6988_p2 = (tmp_271_fu_6980_p3 | tmp107_fu_6972_p3);
assign tmp_2730_fu_36511_p3 = bt_sign_th_V50_s_fu_36389_p3[ap_const_lv32_3];
assign tmp_2731_fu_36524_p3 = bt_sign_ph_V48_s_fu_36381_p3[ap_const_lv32_4];
assign tmp_2732_fu_36537_p3 = bt_sign_th_V50_s_fu_36389_p3[ap_const_lv32_4];
assign tmp_2733_fu_36550_p3 = bt_sign_ph_V48_s_fu_36381_p3[ap_const_lv32_5];
assign tmp_2734_fu_36579_p3 = bt_sign_th_V50_s_fu_36389_p3[ap_const_lv32_5];
assign tmp_2735_fu_36608_p1 = bt_si_V60_s_fu_36412_p3[0:0];
assign tmp_2736_fu_36617_p3 = bt_si_V60_s_fu_36412_p3[ap_const_lv32_2];
assign tmp_2737_fu_36630_p3 = bt_si_V60_s_fu_36412_p3[ap_const_lv32_3];
assign tmp_2738_fu_36643_p3 = bt_si_V60_s_fu_36412_p3[ap_const_lv32_4];
assign tmp_2739_fu_38068_p2 = (tmp_2705_fu_36010_p3 | tmp_2667_fu_35040_p3);
assign tmp_273_fu_7002_p2 = (tmp_272_fu_6988_p2 | tmp106_fu_6924_p3);
assign tmp_2740_fu_38108_p2 = (tmp_2520_fu_31585_p3 | tmp_2539_fu_32164_p3);
assign tmp_2741_fu_38128_p2 = (tmp_2556_fu_32574_p3 | tmp_2722_fu_36420_p3);
assign tmp_2742_fu_38160_p3 = ((tmp_2539_fu_32164_p3[0:0] === 1'b1) ? 1'b1 : 1'b0);
assign tmp_2743_fu_38168_p2 = (tmp_2521_fu_31748_p3 | tmp_2520_fu_31585_p3);
assign tmp_2744_fu_38182_p2 = (tmp_2584_fu_33116_p3 | tmp_2603_fu_33618_p3);
assign tmp_2745_fu_38188_p3 = r_V_176_2_3_fu_32968_p3[ap_const_lv32_1];
assign tmp_2746_fu_38210_p3 = ((tmp_2640_fu_34516_p3[0:0] === 1'b1) ? 1'b1 : 1'b0);
assign tmp_2747_fu_38232_p2 = (tmp_2705_fu_36010_p3 | tmp_2722_fu_36420_p3);
assign tmp_2748_fu_38274_p3 = r_V_176_2_5_fu_34066_p3[ap_const_lv32_1];
assign tmp_2749_fu_38320_p3 = ((tmp_2722_fu_36420_p3[0:0] === 1'b1) ? ap_const_lv3_7 : ap_const_lv3_0);
assign tmp_274_fu_7020_p2 = (tmp_1530_fu_7016_p1 | kill1_t_V_4_5_fu_6140_p3);
assign tmp_2750_fu_38356_p1 = bt_ci_V58171_9_fu_35986_p3[2:0];
assign tmp_2751_fu_38360_p2 = (tmp_2750_fu_38356_p1 | tmp1849_fu_38348_p3);
assign tmp_2752_fu_38366_p3 = bt_ci_V58171_9_fu_35986_p3[ap_const_lv32_3];
assign tmp_2753_fu_38382_p1 = bt_ci_V58172_8_fu_35506_p3[2:0];
assign tmp_2754_fu_38386_p2 = (tmp_2753_fu_38382_p1 | r_V_177_2_9_3_fu_35994_p3);
assign tmp_2755_fu_38392_p3 = bt_ci_V58172_8_fu_35506_p3[ap_const_lv32_3];
assign tmp_2756_fu_38400_p2 = (tmp_2754_fu_38386_p2 | tmp1849_fu_38348_p3);
assign tmp_275_fu_7026_p4 = {{kill1_t_V_4_8_fu_6188_p3[ap_const_lv32_8 : ap_const_lv32_6]}};
assign tmp_276_fu_7048_p2 = (tmp_1531_fu_7044_p1 | kill1_t_V_4_7_fu_6172_p3);
assign tmp_277_fu_7062_p3 = {{tmp_1532_fu_7054_p3}, {tmp_276_fu_7048_p2}};
assign tmp_278_fu_7070_p2 = (tmp_277_fu_7062_p3 | tmp109_fu_7036_p3);
assign tmp_279_fu_7076_p4 = {{kill1_t_V_4_s_fu_6220_p3[ap_const_lv32_A : ap_const_lv32_9]}};
assign tmp_280_fu_7098_p2 = (tmp_1533_fu_7094_p1 | kill1_t_V_5_6_fu_6252_p3);
assign tmp_281_fu_7104_p4 = {{kill1_t_V_4_9_fu_6204_p3[ap_const_lv32_9 : ap_const_lv32_7]}};
assign tmp_282_fu_7126_p2 = (tmp_1534_fu_7122_p1 | kill1_t_V_5_7_fu_6268_p3);
assign tmp_283_fu_7152_p2 = (tmp_1536_fu_7148_p1 | tmp112_fu_7140_p3);
assign tmp_284_fu_7166_p3 = {{tmp_1537_fu_7158_p3}, {tmp_283_fu_7152_p2}};
assign tmp_285_fu_7174_p2 = (tmp_284_fu_7166_p3 | tmp111_fu_7114_p3);
assign tmp_286_fu_7188_p3 = {{tmp_1538_fu_7180_p3}, {tmp_285_fu_7174_p2}};
assign tmp_287_fu_7196_p2 = (tmp_286_fu_7188_p3 | tmp110_fu_7086_p3);
assign tmp_288_fu_7234_p2 = (tmp_1540_fu_7230_p1 | kill1_t_V_0_1_fu_5532_p3);
assign tmp_289_fu_7260_p2 = (tmp_1542_fu_7256_p1 | kill1_t_V_0_3_fu_5564_p3);
assign tmp_290_fu_7278_p2 = (tmp_1544_fu_7274_p1 | tmp116_fu_7248_p3);
assign tmp_291_fu_7306_p2 = (tmp_1546_fu_7302_p1 | kill1_t_V_0_5_fu_5596_p3);
assign tmp_292_fu_7332_p2 = (tmp_1548_fu_7328_p1 | kill1_t_V_0_7_fu_5628_p3);
assign tmp_293_fu_7350_p2 = (tmp_1550_fu_7346_p1 | tmp118_fu_7320_p3);
assign tmp_294_fu_7368_p2 = (tmp_1552_fu_7364_p1 | tmp117_fu_7292_p4);
assign tmp_295_fu_7374_p4 = {{tmp_293_fu_7350_p2[ap_const_lv32_6 : ap_const_lv32_5]}};
assign tmp_296_fu_7400_p2 = (tmp_1553_fu_7396_p1 | kill1_t_V_0_9_fu_5660_p3);
assign tmp_297_fu_7426_p2 = (tmp_1555_fu_7422_p1 | kill1_t_V_1_2_fu_5708_p3);
assign tmp_298_fu_7432_p4 = {{kill1_t_V_0_10_fu_5692_p3[ap_const_lv32_A : ap_const_lv32_3]}};
assign tmp_299_fu_7442_p3 = {{tmp_298_fu_7432_p4}, {tmp_297_fu_7426_p2}};
assign tmp_300_fu_7450_p2 = (tmp_299_fu_7442_p3 | tmp120_fu_7414_p3);
assign tmp_301_fu_7472_p2 = (tmp_1558_fu_7468_p1 | kill1_t_V_1_3_fu_5724_p3);
assign tmp_302_fu_7498_p2 = (tmp_1560_fu_7494_p1 | kill1_t_V_1_5_fu_5756_p3);
assign tmp_303_fu_7516_p2 = (tmp_1562_fu_7512_p1 | tmp121_fu_7486_p3);
assign tmp_304_fu_7540_p2 = (tmp_1557_fu_7464_p1 | tmp122_fu_7530_p4);
assign tmp_305_fu_7546_p4 = {{tmp_300_fu_7450_p2[ap_const_lv32_8 : ap_const_lv32_7]}};
assign tmp_306_fu_7556_p3 = {{tmp_305_fu_7546_p4}, {tmp_304_fu_7540_p2}};
assign tmp_307_fu_7564_p2 = (tmp_306_fu_7556_p3 | tmp119_fu_7384_p5);
assign tmp_308_fu_7570_p4 = {{tmp_300_fu_7450_p2[ap_const_lv32_A : ap_const_lv32_9]}};
assign tmp_309_fu_7594_p2 = (tmp_1564_fu_7590_p1 | kill1_t_V_1_7_fu_5788_p3);
assign tmp_310_fu_7620_p2 = (tmp_1566_fu_7616_p1 | kill1_t_V_1_9_fu_5820_p3);
assign tmp_311_fu_7638_p2 = (tmp_1568_fu_7634_p1 | tmp124_fu_7608_p3);
assign tmp_312_fu_7666_p2 = (tmp_1570_fu_7662_p1 | kill1_t_V_2_3_fu_5868_p3);
assign tmp_313_fu_7672_p4 = {{kill1_t_V_1_1_fu_5852_p3[ap_const_lv32_5 : ap_const_lv32_4]}};
assign tmp_314_fu_7686_p2 = (tmp_1571_fu_7682_p1 | kill1_t_V_2_4_fu_5884_p3);
assign tmp_315_fu_7708_p3 = {{tmp_313_fu_7672_p4}, {tmp_312_fu_7666_p2}};
assign tmp_316_fu_7716_p2 = (tmp_315_fu_7708_p3 | tmp126_fu_7700_p3);
assign tmp_317_fu_7722_p4 = {{kill1_t_V_1_1_fu_5852_p3[ap_const_lv32_A : ap_const_lv32_6]}};
assign tmp_318_fu_7732_p3 = {{tmp_317_fu_7722_p4}, {tmp_316_fu_7716_p2}};
assign tmp_319_fu_7740_p2 = (tmp_318_fu_7732_p3 | tmp125_fu_7652_p4);
assign tmp_320_fu_7766_p2 = (tmp_1574_fu_7762_p1 | kill1_t_V_2_6_fu_5916_p3);
assign tmp_321_fu_7792_p2 = (tmp_1576_fu_7788_p1 | kill1_t_V_2_8_fu_5948_p3);
assign tmp_322_fu_7810_p2 = (tmp_1578_fu_7806_p1 | tmp128_fu_7780_p3);
assign tmp_323_fu_7838_p2 = (tmp_1580_fu_7834_p1 | kill1_t_V_2_s_fu_5980_p3);
assign tmp_324_fu_7868_p3 = {{tmp_1582_fu_7860_p3}, {kill1_t_V_3_4_fu_6012_p3}};
assign tmp_325_fu_7876_p2 = (tmp_324_fu_7868_p3 | kill1_t_V_3_5_fu_6028_p3);
assign tmp_326_fu_7882_p4 = {{kill1_t_V_10_s_fu_6572_p3[ap_const_lv32_B : ap_const_lv32_6]}};
assign tmp_327_fu_7910_p2 = (tmp_1583_fu_7906_p1 | tmp129_fu_7824_p4);
assign tmp_328_fu_7916_p4 = {{tmp132_fu_7900_p2[ap_const_lv32_B : ap_const_lv32_A]}};
assign tmp_330_fu_8564_p1 = p_Result_s_fu_8554_p4;
assign tmp_331_fu_8578_p1 = p_Result_150_fu_8568_p4;
assign tmp_332_fu_8592_p1 = p_Result_151_fu_8582_p4;
assign tmp_333_fu_8608_p2 = ((p_0190_i_fu_8602_p2 < ap_const_lv4_3) ? 1'b1 : 1'b0);
assign tmp_335_fu_9332_p2 = (p_shl5_fu_9312_p3 - p_shl6_cast_fu_9328_p1);
assign tmp_337_fu_16900_p2 = (p_shl7_fu_16882_p3 - p_shl8_cast_fu_16896_p1);
assign tmp_339_fu_17001_p2 = (p_shl9_fu_16983_p3 - p_shl1_cast_fu_16997_p1);
assign tmp_341_fu_17102_p2 = (p_shl2_fu_17084_p3 - p_shl3_cast_fu_17098_p1);
assign tmp_343_fu_17203_p2 = (p_shl_fu_17185_p3 - p_shl11_cast_fu_17199_p1);
assign tmp_345_fu_17304_p2 = (p_shl11_fu_17286_p3 - p_shl13_cast_fu_17300_p1);
assign tmp_347_fu_17405_p2 = (p_shl13_fu_17387_p3 - p_shl15_cast_fu_17401_p1);
assign tmp_349_fu_17515_p2 = (p_shl15_fu_17497_p3 - p_shl17_cast_fu_17511_p1);
assign tmp_351_fu_17613_p2 = (p_shl17_fu_17595_p3 - p_shl19_cast_fu_17609_p1);
assign tmp_353_fu_17714_p2 = (p_shl19_fu_17696_p3 - p_shl21_cast_fu_17710_p1);
assign tmp_355_fu_17815_p2 = (p_shl21_fu_17797_p3 - p_shl23_cast_fu_17811_p1);
assign tmp_356_fu_18082_p2 = (ap_reg_ppstg_tmp_1905_reg_40994_pp0_iter1 | tmp_1904_fu_18078_p1);
assign tmp_357_fu_18091_p2 = (ap_reg_ppstg_tmp_1907_reg_41001_pp0_iter1 | tmp_1906_fu_18087_p1);
assign tmp_358_fu_18104_p2 = (ap_reg_ppstg_tmp_1909_reg_41008_pp0_iter1 | tmp_1908_fu_18096_p3);
assign tmp_359_fu_18117_p2 = (ap_reg_ppstg_tmp_1911_reg_41015_pp0_iter1 | tmp_1910_fu_18109_p3);
assign tmp_360_fu_18130_p2 = (ap_reg_ppstg_tmp_1913_reg_41022_pp0_iter1 | tmp_1912_fu_18122_p3);
assign tmp_361_fu_18143_p2 = (ap_reg_ppstg_tmp_1915_reg_41029_pp0_iter1 | tmp_1914_fu_18135_p3);
assign tmp_362_fu_18156_p2 = (ap_reg_ppstg_tmp_1917_reg_41036_pp0_iter1 | tmp_1916_fu_18148_p3);
assign tmp_363_fu_18169_p2 = (ap_reg_ppstg_tmp_1919_reg_41043_pp0_iter1 | tmp_1918_fu_18161_p3);
assign tmp_364_fu_18182_p2 = (ap_reg_ppstg_tmp_1921_reg_41050_pp0_iter1 | tmp_1920_fu_18174_p3);
assign tmp_365_fu_18195_p2 = (ap_reg_ppstg_tmp_1923_reg_41057_pp0_iter1 | tmp_1922_fu_18187_p3);
assign tmp_366_fu_18208_p2 = (ap_reg_ppstg_tmp_1925_reg_41064_pp0_iter1 | tmp_1924_fu_18200_p3);
assign tmp_367_fu_18237_p2 = (ap_reg_ppstg_tmp_1927_reg_41071_pp0_iter1 | tmp_1926_fu_18229_p3);
assign tmp_368_fu_18262_p2 = (ap_reg_ppstg_tmp_1929_reg_41078_pp0_iter1 | tmp_1928_fu_18258_p1);
assign tmp_369_fu_18275_p2 = (ap_reg_ppstg_tmp_1170_reg_40736_pp0_iter1 | tmp_1930_fu_18267_p3);
assign tmp_370_fu_18288_p2 = (ap_reg_ppstg_tmp_1172_reg_40743_pp0_iter1 | tmp_1931_fu_18280_p3);
assign tmp_371_fu_18498_p2 = (ap_reg_ppstg_tmp_1936_reg_41085_pp0_iter1 | tmp_1935_fu_18494_p1);
assign tmp_372_fu_18507_p2 = (ap_reg_ppstg_tmp_1938_reg_41092_pp0_iter1 | tmp_1937_fu_18503_p1);
assign tmp_373_fu_18520_p2 = (ap_reg_ppstg_tmp_1940_reg_41099_pp0_iter1 | tmp_1939_fu_18512_p3);
assign tmp_374_fu_18533_p2 = (ap_reg_ppstg_tmp_1942_reg_41106_pp0_iter1 | tmp_1941_fu_18525_p3);
assign tmp_375_fu_18546_p2 = (ap_reg_ppstg_tmp_1944_reg_41113_pp0_iter1 | tmp_1943_fu_18538_p3);
assign tmp_376_fu_18559_p2 = (ap_reg_ppstg_tmp_1946_reg_41120_pp0_iter1 | tmp_1945_fu_18551_p3);
assign tmp_377_fu_18572_p2 = (ap_reg_ppstg_tmp_1948_reg_41127_pp0_iter1 | tmp_1947_fu_18564_p3);
assign tmp_378_fu_18585_p2 = (ap_reg_ppstg_tmp_1950_reg_41134_pp0_iter1 | tmp_1949_fu_18577_p3);
assign tmp_379_fu_18598_p2 = (ap_reg_ppstg_tmp_1952_reg_41141_pp0_iter1 | tmp_1951_fu_18590_p3);
assign tmp_380_fu_18611_p2 = (ap_reg_ppstg_tmp_1954_reg_41148_pp0_iter1 | tmp_1953_fu_18603_p3);
assign tmp_381_fu_18624_p2 = (ap_reg_ppstg_tmp_1956_reg_41155_pp0_iter1 | tmp_1955_fu_18616_p3);
assign tmp_382_fu_18653_p2 = (ap_reg_ppstg_tmp_1958_reg_41162_pp0_iter1 | tmp_1957_fu_18645_p3);
assign tmp_383_fu_18678_p2 = (ap_reg_ppstg_tmp_1960_reg_41169_pp0_iter1 | tmp_1959_fu_18674_p1);
assign tmp_384_fu_18691_p2 = (ap_reg_ppstg_tmp_1193_reg_40778_pp0_iter1 | tmp_1961_fu_18683_p3);
assign tmp_385_fu_18704_p2 = (ap_reg_ppstg_tmp_1195_reg_40785_pp0_iter1 | tmp_1962_fu_18696_p3);
assign tmp_386_fu_18908_p2 = (ap_reg_ppstg_tmp_1966_reg_41176_pp0_iter1 | tmp_1965_fu_18904_p1);
assign tmp_387_fu_18917_p2 = (ap_reg_ppstg_tmp_1968_reg_41183_pp0_iter1 | tmp_1967_fu_18913_p1);
assign tmp_388_fu_18930_p2 = (ap_reg_ppstg_tmp_1970_reg_41190_pp0_iter1 | tmp_1969_fu_18922_p3);
assign tmp_389_fu_18943_p2 = (ap_reg_ppstg_tmp_1972_reg_41197_pp0_iter1 | tmp_1971_fu_18935_p3);
assign tmp_390_fu_18956_p2 = (ap_reg_ppstg_tmp_1974_reg_41204_pp0_iter1 | tmp_1973_fu_18948_p3);
assign tmp_391_fu_18969_p2 = (ap_reg_ppstg_tmp_1976_reg_41211_pp0_iter1 | tmp_1975_fu_18961_p3);
assign tmp_392_fu_18982_p2 = (ap_reg_ppstg_tmp_1978_reg_41218_pp0_iter1 | tmp_1977_fu_18974_p3);
assign tmp_393_fu_18995_p2 = (ap_reg_ppstg_tmp_1980_reg_41225_pp0_iter1 | tmp_1979_fu_18987_p3);
assign tmp_394_fu_19008_p2 = (ap_reg_ppstg_tmp_1982_reg_41232_pp0_iter1 | tmp_1981_fu_19000_p3);
assign tmp_395_fu_19021_p2 = (ap_reg_ppstg_tmp_1984_reg_41239_pp0_iter1 | tmp_1983_fu_19013_p3);
assign tmp_396_fu_19034_p2 = (ap_reg_ppstg_tmp_1986_reg_41246_pp0_iter1 | tmp_1985_fu_19026_p3);
assign tmp_397_fu_19063_p2 = (ap_reg_ppstg_tmp_1988_reg_41253_pp0_iter1 | tmp_1987_fu_19055_p3);
assign tmp_398_fu_19088_p2 = (ap_reg_ppstg_tmp_1990_reg_41260_pp0_iter1 | tmp_1989_fu_19084_p1);
assign tmp_399_fu_19101_p2 = (ap_reg_ppstg_tmp_1217_reg_40820_pp0_iter1 | tmp_1991_fu_19093_p3);
assign tmp_400_fu_19114_p2 = (ap_reg_ppstg_tmp_1219_reg_40827_pp0_iter1 | tmp_1992_fu_19106_p3);
assign tmp_401_fu_19310_p2 = (tmp_1994_fu_19306_p1 | r_V_177_0_2_fu_18880_p3);
assign tmp_402_fu_19412_p3 = {{tmp_2004_fu_19404_p3}, {tmp_1901_fu_17898_p1}};
assign tmp_403_fu_19454_p2 = (ap_reg_ppstg_tmp_2008_reg_41267_pp0_iter1 | tmp_2007_fu_19450_p1);
assign tmp_404_fu_19463_p2 = (ap_reg_ppstg_tmp_2010_reg_41274_pp0_iter1 | tmp_2009_fu_19459_p1);
assign tmp_405_fu_19476_p2 = (ap_reg_ppstg_tmp_2012_reg_41281_pp0_iter1 | tmp_2011_fu_19468_p3);
assign tmp_406_fu_19489_p2 = (ap_reg_ppstg_tmp_2014_reg_41288_pp0_iter1 | tmp_2013_fu_19481_p3);
assign tmp_407_fu_19502_p2 = (ap_reg_ppstg_tmp_2016_reg_41295_pp0_iter1 | tmp_2015_fu_19494_p3);
assign tmp_408_fu_19515_p2 = (ap_reg_ppstg_tmp_2018_reg_41302_pp0_iter1 | tmp_2017_fu_19507_p3);
assign tmp_409_fu_19528_p2 = (ap_reg_ppstg_tmp_2020_reg_41309_pp0_iter1 | tmp_2019_fu_19520_p3);
assign tmp_410_fu_19541_p2 = (ap_reg_ppstg_tmp_2022_reg_41316_pp0_iter1 | tmp_2021_fu_19533_p3);
assign tmp_411_fu_19554_p2 = (ap_reg_ppstg_tmp_2024_reg_41323_pp0_iter1 | tmp_2023_fu_19546_p3);
assign tmp_412_fu_19567_p2 = (ap_reg_ppstg_tmp_2026_reg_41330_pp0_iter1 | tmp_2025_fu_19559_p3);
assign tmp_413_fu_19580_p2 = (ap_reg_ppstg_tmp_2028_reg_41337_pp0_iter1 | tmp_2027_fu_19572_p3);
assign tmp_414_fu_19609_p2 = (ap_reg_ppstg_tmp_2030_reg_41344_pp0_iter1 | tmp_2029_fu_19601_p3);
assign tmp_415_fu_19638_p3 = {{tmp_2031_fu_19630_p3}, {tmp_1996_fu_19320_p2}};
assign tmp_416_fu_19646_p2 = (tmp_415_fu_19638_p3 | ap_const_lv2_1);
assign tmp_417_fu_19674_p2 = (ap_reg_ppstg_tmp_2034_reg_41351_pp0_iter1 | tmp_2033_fu_19670_p1);
assign tmp_418_fu_19679_p2 = (tmp1033_fu_19352_p3 | ap_const_lv3_1);
assign tmp_419_fu_19701_p2 = (ap_reg_ppstg_tmp_1150_reg_40708_pp0_iter1 | tmp_2035_fu_19693_p3);
assign tmp_420_fu_19706_p2 = (tmp_2005_fu_19420_p2 | ap_const_lv3_1);
assign tmp_421_fu_19728_p2 = (ap_reg_ppstg_tmp_1164_reg_40715_pp0_iter1 | tmp_2036_fu_19720_p3);
assign tmp_422_fu_19956_p2 = (ap_reg_ppstg_tmp_2040_reg_41358_pp0_iter1 | tmp_2039_fu_19952_p1);
assign tmp_423_fu_19965_p2 = (ap_reg_ppstg_tmp_2042_reg_41365_pp0_iter1 | tmp_2041_fu_19961_p1);
assign tmp_424_fu_19978_p2 = (ap_reg_ppstg_tmp_2044_reg_41372_pp0_iter1 | tmp_2043_fu_19970_p3);
assign tmp_425_fu_19991_p2 = (ap_reg_ppstg_tmp_2046_reg_41379_pp0_iter1 | tmp_2045_fu_19983_p3);
assign tmp_426_fu_20004_p2 = (ap_reg_ppstg_tmp_2048_reg_41386_pp0_iter1 | tmp_2047_fu_19996_p3);
assign tmp_427_fu_20017_p2 = (ap_reg_ppstg_tmp_2050_reg_41393_pp0_iter1 | tmp_2049_fu_20009_p3);
assign tmp_428_fu_20030_p2 = (ap_reg_ppstg_tmp_2052_reg_41400_pp0_iter1 | tmp_2051_fu_20022_p3);
assign tmp_429_fu_20043_p2 = (ap_reg_ppstg_tmp_2054_reg_41407_pp0_iter1 | tmp_2053_fu_20035_p3);
assign tmp_430_fu_20056_p2 = (ap_reg_ppstg_tmp_2056_reg_41414_pp0_iter1 | tmp_2055_fu_20048_p3);
assign tmp_431_fu_20069_p2 = (ap_reg_ppstg_tmp_2058_reg_41421_pp0_iter1 | tmp_2057_fu_20061_p3);
assign tmp_432_fu_20082_p2 = (ap_reg_ppstg_tmp_2060_reg_41428_pp0_iter1 | tmp_2059_fu_20074_p3);
assign tmp_433_fu_20111_p2 = (ap_reg_ppstg_tmp_2062_reg_41435_pp0_iter1 | tmp_2061_fu_20103_p3);
assign tmp_434_fu_20136_p2 = (tmp_2063_fu_20132_p1 | ap_const_lv2_1);
assign tmp_435_fu_20142_p4 = {{bt_ci_V_4_fu_19912_p3[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_436_fu_20164_p2 = (ap_reg_ppstg_tmp_2065_reg_41442_pp0_iter1 | tmp_2064_fu_20160_p1);
assign tmp_437_fu_20173_p2 = (tmp_2066_fu_20169_p1 | ap_const_lv3_1);
assign tmp_438_fu_20203_p2 = (ap_reg_ppstg_tmp_1173_reg_40750_pp0_iter1 | tmp_2068_fu_20195_p3);
assign tmp_439_fu_20216_p2 = (ap_reg_ppstg_tmp_1188_reg_40757_pp0_iter1 | tmp_2069_fu_20208_p3);
assign tmp_440_fu_20436_p2 = (ap_reg_ppstg_tmp_2073_reg_41449_pp0_iter1 | tmp_2072_fu_20432_p1);
assign tmp_441_fu_20445_p2 = (ap_reg_ppstg_tmp_2075_reg_41456_pp0_iter1 | tmp_2074_fu_20441_p1);
assign tmp_442_fu_20458_p2 = (ap_reg_ppstg_tmp_2077_reg_41463_pp0_iter1 | tmp_2076_fu_20450_p3);
assign tmp_443_fu_20471_p2 = (ap_reg_ppstg_tmp_2079_reg_41470_pp0_iter1 | tmp_2078_fu_20463_p3);
assign tmp_444_fu_20484_p2 = (ap_reg_ppstg_tmp_2081_reg_41477_pp0_iter1 | tmp_2080_fu_20476_p3);
assign tmp_445_fu_20497_p2 = (ap_reg_ppstg_tmp_2083_reg_41484_pp0_iter1 | tmp_2082_fu_20489_p3);
assign tmp_446_fu_20510_p2 = (ap_reg_ppstg_tmp_2085_reg_41491_pp0_iter1 | tmp_2084_fu_20502_p3);
assign tmp_447_fu_20523_p2 = (ap_reg_ppstg_tmp_2087_reg_41498_pp0_iter1 | tmp_2086_fu_20515_p3);
assign tmp_448_fu_20536_p2 = (ap_reg_ppstg_tmp_2089_reg_41505_pp0_iter1 | tmp_2088_fu_20528_p3);
assign tmp_449_fu_20549_p2 = (ap_reg_ppstg_tmp_2091_reg_41512_pp0_iter1 | tmp_2090_fu_20541_p3);
assign tmp_450_fu_20562_p2 = (ap_reg_ppstg_tmp_2093_reg_41519_pp0_iter1 | tmp_2092_fu_20554_p3);
assign tmp_451_fu_20591_p2 = (ap_reg_ppstg_tmp_2095_reg_41526_pp0_iter1 | tmp_2094_fu_20583_p3);
assign tmp_452_fu_20616_p2 = (ap_reg_ppstg_tmp_2097_reg_41533_pp0_iter1 | tmp_2096_fu_20612_p1);
assign tmp_453_fu_20629_p2 = (ap_reg_ppstg_tmp_1197_reg_40792_pp0_iter1 | tmp_2098_fu_20621_p3);
assign tmp_454_fu_20642_p2 = (ap_reg_ppstg_tmp_1199_reg_40799_pp0_iter1 | tmp_2099_fu_20634_p3);
assign tmp_455_fu_20854_p2 = (ap_reg_ppstg_tmp_2103_reg_41540_pp0_iter1 | tmp_2102_fu_20850_p1);
assign tmp_456_fu_20863_p2 = (ap_reg_ppstg_tmp_2105_reg_41547_pp0_iter1 | tmp_2104_fu_20859_p1);
assign tmp_457_fu_20876_p2 = (ap_reg_ppstg_tmp_2107_reg_41554_pp0_iter1 | tmp_2106_fu_20868_p3);
assign tmp_458_fu_20889_p2 = (ap_reg_ppstg_tmp_2109_reg_41561_pp0_iter1 | tmp_2108_fu_20881_p3);
assign tmp_459_fu_20902_p2 = (ap_reg_ppstg_tmp_2111_reg_41568_pp0_iter1 | tmp_2110_fu_20894_p3);
assign tmp_460_fu_20915_p2 = (ap_reg_ppstg_tmp_2113_reg_41575_pp0_iter1 | tmp_2112_fu_20907_p3);
assign tmp_461_fu_20928_p2 = (ap_reg_ppstg_tmp_2115_reg_41582_pp0_iter1 | tmp_2114_fu_20920_p3);
assign tmp_462_fu_20941_p2 = (ap_reg_ppstg_tmp_2117_reg_41589_pp0_iter1 | tmp_2116_fu_20933_p3);
assign tmp_463_fu_20954_p2 = (ap_reg_ppstg_tmp_2119_reg_41596_pp0_iter1 | tmp_2118_fu_20946_p3);
assign tmp_464_fu_20967_p2 = (ap_reg_ppstg_tmp_2121_reg_41603_pp0_iter1 | tmp_2120_fu_20959_p3);
assign tmp_465_fu_20980_p2 = (ap_reg_ppstg_tmp_2123_reg_41610_pp0_iter1 | tmp_2122_fu_20972_p3);
assign tmp_466_fu_21009_p2 = (ap_reg_ppstg_tmp_2125_reg_41617_pp0_iter1 | tmp_2124_fu_21001_p3);
assign tmp_467_fu_21034_p2 = (ap_reg_ppstg_tmp_2127_reg_41624_pp0_iter1 | tmp_2126_fu_21030_p1);
assign tmp_468_fu_21047_p2 = (ap_reg_ppstg_tmp_1222_reg_40834_pp0_iter1 | tmp_2128_fu_21039_p3);
assign tmp_469_fu_21060_p2 = (ap_reg_ppstg_tmp_1236_reg_40841_pp0_iter1 | tmp_2129_fu_21052_p3);
assign tmp_470_fu_21244_p2 = (tmp_2131_fu_21236_p3 | r_V_177_0_6_fu_20826_p3);
assign tmp_471_fu_21378_p2 = (ap_reg_ppstg_tmp_2143_reg_41631_pp0_iter1 | tmp_2142_fu_21374_p1);
assign tmp_472_fu_21387_p2 = (ap_reg_ppstg_tmp_2145_reg_41638_pp0_iter1 | tmp_2144_fu_21383_p1);
assign tmp_473_fu_21400_p2 = (ap_reg_ppstg_tmp_2147_reg_41645_pp0_iter1 | tmp_2146_fu_21392_p3);
assign tmp_474_fu_21413_p2 = (ap_reg_ppstg_tmp_2149_reg_41652_pp0_iter1 | tmp_2148_fu_21405_p3);
assign tmp_475_fu_21426_p2 = (ap_reg_ppstg_tmp_2151_reg_41659_pp0_iter1 | tmp_2150_fu_21418_p3);
assign tmp_476_fu_21439_p2 = (ap_reg_ppstg_tmp_2153_reg_41666_pp0_iter1 | tmp_2152_fu_21431_p3);
assign tmp_477_fu_21452_p2 = (ap_reg_ppstg_tmp_2155_reg_41673_pp0_iter1 | tmp_2154_fu_21444_p3);
assign tmp_478_fu_21465_p2 = (ap_reg_ppstg_tmp_2157_reg_41680_pp0_iter1 | tmp_2156_fu_21457_p3);
assign tmp_479_fu_21478_p2 = (ap_reg_ppstg_tmp_2159_reg_41687_pp0_iter1 | tmp_2158_fu_21470_p3);
assign tmp_480_fu_21491_p2 = (ap_reg_ppstg_tmp_2161_reg_41694_pp0_iter1 | tmp_2160_fu_21483_p3);
assign tmp_481_fu_21504_p2 = (ap_reg_ppstg_tmp_2163_reg_41701_pp0_iter1 | tmp_2162_fu_21496_p3);
assign tmp_482_fu_21533_p2 = (ap_reg_ppstg_tmp_2165_reg_41708_pp0_iter1 | tmp_2164_fu_21525_p3);
assign tmp_483_fu_21558_p2 = (tmp_2166_fu_21554_p1 | ap_const_lv2_1);
assign tmp_484_fu_21564_p4 = {{bt_ci_V_7_fu_21258_p2[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_485_fu_21586_p2 = (ap_reg_ppstg_tmp_2168_reg_41715_pp0_iter1 | tmp_2167_fu_21582_p1);
assign tmp_486_fu_21591_p2 = (tmp_2134_fu_21290_p2 | ap_const_lv3_1);
assign tmp_487_fu_21613_p2 = (ap_reg_ppstg_tmp_1167_reg_40722_pp0_iter1 | tmp_2169_fu_21605_p3);
assign tmp_488_fu_21618_p2 = (tmp_2140_fu_21344_p2 | ap_const_lv3_1);
assign tmp_489_fu_21640_p2 = (ap_reg_ppstg_tmp_1169_reg_40729_pp0_iter1 | tmp_2170_fu_21632_p3);
assign tmp_490_fu_21860_p2 = (ap_reg_ppstg_tmp_2174_reg_41722_pp0_iter1 | tmp_2173_fu_21856_p1);
assign tmp_491_fu_21869_p2 = (ap_reg_ppstg_tmp_2176_reg_41729_pp0_iter1 | tmp_2175_fu_21865_p1);
assign tmp_492_fu_21882_p2 = (ap_reg_ppstg_tmp_2178_reg_41736_pp0_iter1 | tmp_2177_fu_21874_p3);
assign tmp_493_fu_21895_p2 = (ap_reg_ppstg_tmp_2180_reg_41743_pp0_iter1 | tmp_2179_fu_21887_p3);
assign tmp_494_fu_21908_p2 = (ap_reg_ppstg_tmp_2182_reg_41750_pp0_iter1 | tmp_2181_fu_21900_p3);
assign tmp_495_fu_21921_p2 = (ap_reg_ppstg_tmp_2184_reg_41757_pp0_iter1 | tmp_2183_fu_21913_p3);
assign tmp_496_fu_21934_p2 = (ap_reg_ppstg_tmp_2186_reg_41764_pp0_iter1 | tmp_2185_fu_21926_p3);
assign tmp_497_fu_21947_p2 = (ap_reg_ppstg_tmp_2188_reg_41771_pp0_iter1 | tmp_2187_fu_21939_p3);
assign tmp_498_fu_21960_p2 = (ap_reg_ppstg_tmp_2190_reg_41778_pp0_iter1 | tmp_2189_fu_21952_p3);
assign tmp_499_fu_21973_p2 = (ap_reg_ppstg_tmp_2192_reg_41785_pp0_iter1 | tmp_2191_fu_21965_p3);
assign tmp_500_fu_21986_p2 = (ap_reg_ppstg_tmp_2194_reg_41792_pp0_iter1 | tmp_2193_fu_21978_p3);
assign tmp_501_fu_22015_p2 = (ap_reg_ppstg_tmp_2196_reg_41799_pp0_iter1 | tmp_2195_fu_22007_p3);
assign tmp_502_fu_22040_p2 = (tmp_2197_fu_22036_p1 | ap_const_lv2_1);
assign tmp_503_fu_22046_p4 = {{bt_ci_V_8_fu_21816_p3[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_504_fu_22068_p2 = (ap_reg_ppstg_tmp_2199_reg_41806_pp0_iter1 | tmp_2198_fu_22064_p1);
assign tmp_505_fu_22077_p2 = (tmp_2200_fu_22073_p1 | ap_const_lv3_1);
assign tmp_506_fu_22107_p2 = (ap_reg_ppstg_tmp_1190_reg_40764_pp0_iter1 | tmp_2202_fu_22099_p3);
assign tmp_507_fu_22120_p2 = (ap_reg_ppstg_tmp_1191_reg_40771_pp0_iter1 | tmp_2203_fu_22112_p3);
assign tmp_508_fu_22348_p2 = (ap_reg_ppstg_tmp_2207_reg_41813_pp0_iter1 | tmp_2206_fu_22344_p1);
assign tmp_509_fu_22357_p2 = (ap_reg_ppstg_tmp_2209_reg_41820_pp0_iter1 | tmp_2208_fu_22353_p1);
assign tmp_510_fu_22370_p2 = (ap_reg_ppstg_tmp_2211_reg_41827_pp0_iter1 | tmp_2210_fu_22362_p3);
assign tmp_511_fu_22383_p2 = (ap_reg_ppstg_tmp_2213_reg_41834_pp0_iter1 | tmp_2212_fu_22375_p3);
assign tmp_512_fu_22396_p2 = (ap_reg_ppstg_tmp_2215_reg_41841_pp0_iter1 | tmp_2214_fu_22388_p3);
assign tmp_513_fu_22409_p2 = (ap_reg_ppstg_tmp_2217_reg_41848_pp0_iter1 | tmp_2216_fu_22401_p3);
assign tmp_514_fu_22422_p2 = (ap_reg_ppstg_tmp_2219_reg_41855_pp0_iter1 | tmp_2218_fu_22414_p3);
assign tmp_515_fu_22435_p2 = (ap_reg_ppstg_tmp_2221_reg_41862_pp0_iter1 | tmp_2220_fu_22427_p3);
assign tmp_516_fu_22448_p2 = (ap_reg_ppstg_tmp_2223_reg_41869_pp0_iter1 | tmp_2222_fu_22440_p3);
assign tmp_517_fu_22461_p2 = (ap_reg_ppstg_tmp_2225_reg_41876_pp0_iter1 | tmp_2224_fu_22453_p3);
assign tmp_518_fu_22474_p2 = (ap_reg_ppstg_tmp_2227_reg_41883_pp0_iter1 | tmp_2226_fu_22466_p3);
assign tmp_519_fu_22503_p2 = (ap_reg_ppstg_tmp_2229_reg_41890_pp0_iter1 | tmp_2228_fu_22495_p3);
assign tmp_520_fu_22528_p2 = (ap_reg_ppstg_tmp_2231_reg_41897_pp0_iter1 | tmp_2230_fu_22524_p1);
assign tmp_521_fu_22541_p2 = (ap_reg_ppstg_tmp_1212_reg_40806_pp0_iter1 | tmp_2232_fu_22533_p3);
assign tmp_522_fu_22554_p2 = (ap_reg_ppstg_tmp_1216_reg_40813_pp0_iter1 | tmp_2233_fu_22546_p3);
assign tmp_523_fu_22758_p2 = (ap_reg_ppstg_tmp_2237_reg_41904_pp0_iter1 | tmp_2236_fu_22754_p1);
assign tmp_524_fu_22767_p2 = (ap_reg_ppstg_tmp_2239_reg_41911_pp0_iter1 | tmp_2238_fu_22763_p1);
assign tmp_525_fu_22780_p2 = (ap_reg_ppstg_tmp_2241_reg_41918_pp0_iter1 | tmp_2240_fu_22772_p3);
assign tmp_526_fu_22793_p2 = (ap_reg_ppstg_tmp_2243_reg_41925_pp0_iter1 | tmp_2242_fu_22785_p3);
assign tmp_527_fu_22806_p2 = (ap_reg_ppstg_tmp_2245_reg_41932_pp0_iter1 | tmp_2244_fu_22798_p3);
assign tmp_528_fu_22819_p2 = (ap_reg_ppstg_tmp_2247_reg_41939_pp0_iter1 | tmp_2246_fu_22811_p3);
assign tmp_529_fu_22832_p2 = (ap_reg_ppstg_tmp_2249_reg_41946_pp0_iter1 | tmp_2248_fu_22824_p3);
assign tmp_530_fu_22845_p2 = (ap_reg_ppstg_tmp_2251_reg_41953_pp0_iter1 | tmp_2250_fu_22837_p3);
assign tmp_531_fu_22858_p2 = (ap_reg_ppstg_tmp_2253_reg_41960_pp0_iter1 | tmp_2252_fu_22850_p3);
assign tmp_532_fu_22871_p2 = (ap_reg_ppstg_tmp_2255_reg_41967_pp0_iter1 | tmp_2254_fu_22863_p3);
assign tmp_533_fu_22884_p2 = (ap_reg_ppstg_tmp_2257_reg_41974_pp0_iter1 | tmp_2256_fu_22876_p3);
assign tmp_534_fu_22913_p2 = (ap_reg_ppstg_tmp_2259_reg_41981_pp0_iter1 | tmp_2258_fu_22905_p3);
assign tmp_535_fu_22938_p2 = (ap_reg_ppstg_tmp_2261_reg_41988_pp0_iter1 | tmp_2260_fu_22934_p1);
assign tmp_536_fu_22951_p2 = (ap_reg_ppstg_tmp_1239_reg_40848_pp0_iter1 | tmp_2262_fu_22943_p3);
assign tmp_537_fu_22964_p2 = (ap_reg_ppstg_tmp_1253_reg_40855_pp0_iter1 | tmp_2263_fu_22956_p3);
assign tmp_538_fu_24654_p2 = (tmp_2275_fu_24646_p3 | r_V_177_0_s_fu_22730_p3);
assign tmp_539_fu_24923_p2 = (ap_reg_ppstg_tmp_1905_reg_40994_pp0_iter1 | tmp_2285_fu_24919_p1);
assign tmp_540_fu_24932_p2 = (ap_reg_ppstg_tmp_1907_reg_41001_pp0_iter1 | tmp_2286_fu_24928_p1);
assign tmp_541_fu_24945_p2 = (ap_reg_ppstg_tmp_1909_reg_41008_pp0_iter1 | tmp_2287_fu_24937_p3);
assign tmp_542_fu_24958_p2 = (ap_reg_ppstg_tmp_1911_reg_41015_pp0_iter1 | tmp_2288_fu_24950_p3);
assign tmp_543_fu_24971_p2 = (ap_reg_ppstg_tmp_1913_reg_41022_pp0_iter1 | tmp_2289_fu_24963_p3);
assign tmp_544_fu_24984_p2 = (ap_reg_ppstg_tmp_1915_reg_41029_pp0_iter1 | tmp_2290_fu_24976_p3);
assign tmp_545_fu_24997_p2 = (ap_reg_ppstg_tmp_1917_reg_41036_pp0_iter1 | tmp_2291_fu_24989_p3);
assign tmp_546_fu_25010_p2 = (ap_reg_ppstg_tmp_1919_reg_41043_pp0_iter1 | tmp_2292_fu_25002_p3);
assign tmp_547_fu_25023_p2 = (ap_reg_ppstg_tmp_1921_reg_41050_pp0_iter1 | tmp_2293_fu_25015_p3);
assign tmp_548_fu_25036_p2 = (ap_reg_ppstg_tmp_1923_reg_41057_pp0_iter1 | tmp_2294_fu_25028_p3);
assign tmp_549_fu_25049_p2 = (ap_reg_ppstg_tmp_1925_reg_41064_pp0_iter1 | tmp_2295_fu_25041_p3);
assign tmp_550_fu_25078_p2 = (ap_reg_ppstg_tmp_1927_reg_41071_pp0_iter1 | tmp_2296_fu_25070_p3);
assign tmp_551_fu_25103_p2 = (ap_reg_ppstg_tmp_1929_reg_41078_pp0_iter1 | tmp_2297_fu_25099_p1);
assign tmp_552_fu_25116_p2 = (ap_reg_ppstg_tmp_1170_reg_40736_pp0_iter1 | tmp_2298_fu_25108_p3);
assign tmp_553_fu_25129_p2 = (ap_reg_ppstg_tmp_1172_reg_40743_pp0_iter1 | tmp_2299_fu_25121_p3);
assign tmp_554_fu_25339_p2 = (ap_reg_ppstg_tmp_1936_reg_41085_pp0_iter1 | tmp_2303_fu_25335_p1);
assign tmp_555_fu_25348_p2 = (ap_reg_ppstg_tmp_1938_reg_41092_pp0_iter1 | tmp_2304_fu_25344_p1);
assign tmp_556_fu_25361_p2 = (ap_reg_ppstg_tmp_1940_reg_41099_pp0_iter1 | tmp_2305_fu_25353_p3);
assign tmp_557_fu_25374_p2 = (ap_reg_ppstg_tmp_1942_reg_41106_pp0_iter1 | tmp_2306_fu_25366_p3);
assign tmp_558_fu_25387_p2 = (ap_reg_ppstg_tmp_1944_reg_41113_pp0_iter1 | tmp_2307_fu_25379_p3);
assign tmp_559_fu_25400_p2 = (ap_reg_ppstg_tmp_1946_reg_41120_pp0_iter1 | tmp_2308_fu_25392_p3);
assign tmp_560_fu_25413_p2 = (ap_reg_ppstg_tmp_1948_reg_41127_pp0_iter1 | tmp_2309_fu_25405_p3);
assign tmp_561_fu_25426_p2 = (ap_reg_ppstg_tmp_1950_reg_41134_pp0_iter1 | tmp_2310_fu_25418_p3);
assign tmp_562_fu_25439_p2 = (ap_reg_ppstg_tmp_1952_reg_41141_pp0_iter1 | tmp_2311_fu_25431_p3);
assign tmp_563_fu_25452_p2 = (ap_reg_ppstg_tmp_1954_reg_41148_pp0_iter1 | tmp_2312_fu_25444_p3);
assign tmp_564_fu_25465_p2 = (ap_reg_ppstg_tmp_1956_reg_41155_pp0_iter1 | tmp_2313_fu_25457_p3);
assign tmp_565_fu_25494_p2 = (ap_reg_ppstg_tmp_1958_reg_41162_pp0_iter1 | tmp_2314_fu_25486_p3);
assign tmp_566_fu_25519_p2 = (ap_reg_ppstg_tmp_1960_reg_41169_pp0_iter1 | tmp_2315_fu_25515_p1);
assign tmp_567_fu_25532_p2 = (ap_reg_ppstg_tmp_1193_reg_40778_pp0_iter1 | tmp_2316_fu_25524_p3);
assign tmp_568_fu_25545_p2 = (ap_reg_ppstg_tmp_1195_reg_40785_pp0_iter1 | tmp_2317_fu_25537_p3);
assign tmp_569_fu_25749_p2 = (ap_reg_ppstg_tmp_1966_reg_41176_pp0_iter1 | tmp_2320_fu_25745_p1);
assign tmp_570_fu_25758_p2 = (ap_reg_ppstg_tmp_1968_reg_41183_pp0_iter1 | tmp_2321_fu_25754_p1);
assign tmp_571_fu_25771_p2 = (ap_reg_ppstg_tmp_1970_reg_41190_pp0_iter1 | tmp_2322_fu_25763_p3);
assign tmp_572_fu_25784_p2 = (ap_reg_ppstg_tmp_1972_reg_41197_pp0_iter1 | tmp_2323_fu_25776_p3);
assign tmp_573_fu_25797_p2 = (ap_reg_ppstg_tmp_1974_reg_41204_pp0_iter1 | tmp_2324_fu_25789_p3);
assign tmp_574_fu_25810_p2 = (ap_reg_ppstg_tmp_1976_reg_41211_pp0_iter1 | tmp_2325_fu_25802_p3);
assign tmp_575_fu_25823_p2 = (ap_reg_ppstg_tmp_1978_reg_41218_pp0_iter1 | tmp_2326_fu_25815_p3);
assign tmp_576_fu_25836_p2 = (ap_reg_ppstg_tmp_1980_reg_41225_pp0_iter1 | tmp_2327_fu_25828_p3);
assign tmp_577_fu_25849_p2 = (ap_reg_ppstg_tmp_1982_reg_41232_pp0_iter1 | tmp_2328_fu_25841_p3);
assign tmp_578_fu_25862_p2 = (ap_reg_ppstg_tmp_1984_reg_41239_pp0_iter1 | tmp_2329_fu_25854_p3);
assign tmp_579_fu_25875_p2 = (ap_reg_ppstg_tmp_1986_reg_41246_pp0_iter1 | tmp_2330_fu_25867_p3);
assign tmp_580_fu_25904_p2 = (ap_reg_ppstg_tmp_1988_reg_41253_pp0_iter1 | tmp_2331_fu_25896_p3);
assign tmp_581_fu_25929_p2 = (ap_reg_ppstg_tmp_1990_reg_41260_pp0_iter1 | tmp_2332_fu_25925_p1);
assign tmp_582_fu_25942_p2 = (ap_reg_ppstg_tmp_1217_reg_40820_pp0_iter1 | tmp_2333_fu_25934_p3);
assign tmp_583_fu_25955_p2 = (ap_reg_ppstg_tmp_1219_reg_40827_pp0_iter1 | tmp_2334_fu_25947_p3);
assign tmp_584_fu_26151_p2 = (tmp_2336_fu_26147_p1 | r_V_177_1_2_fu_25721_p3);
assign tmp_585_fu_26249_p3 = {{tmp_2345_fu_26241_p3}, {tmp_2283_fu_24748_p3}};
assign tmp_586_fu_26291_p2 = (ap_reg_ppstg_tmp_2008_reg_41267_pp0_iter1 | tmp_2348_fu_26287_p1);
assign tmp_587_fu_26300_p2 = (ap_reg_ppstg_tmp_2010_reg_41274_pp0_iter1 | tmp_2349_fu_26296_p1);
assign tmp_588_fu_26313_p2 = (ap_reg_ppstg_tmp_2012_reg_41281_pp0_iter1 | tmp_2350_fu_26305_p3);
assign tmp_589_fu_26326_p2 = (ap_reg_ppstg_tmp_2014_reg_41288_pp0_iter1 | tmp_2351_fu_26318_p3);
assign tmp_590_fu_26339_p2 = (ap_reg_ppstg_tmp_2016_reg_41295_pp0_iter1 | tmp_2352_fu_26331_p3);
assign tmp_591_fu_26352_p2 = (ap_reg_ppstg_tmp_2018_reg_41302_pp0_iter1 | tmp_2353_fu_26344_p3);
assign tmp_592_fu_26365_p2 = (ap_reg_ppstg_tmp_2020_reg_41309_pp0_iter1 | tmp_2354_fu_26357_p3);
assign tmp_593_fu_26378_p2 = (ap_reg_ppstg_tmp_2022_reg_41316_pp0_iter1 | tmp_2355_fu_26370_p3);
assign tmp_594_fu_26391_p2 = (ap_reg_ppstg_tmp_2024_reg_41323_pp0_iter1 | tmp_2356_fu_26383_p3);
assign tmp_595_fu_26404_p2 = (ap_reg_ppstg_tmp_2026_reg_41330_pp0_iter1 | tmp_2357_fu_26396_p3);
assign tmp_596_fu_26417_p2 = (ap_reg_ppstg_tmp_2028_reg_41337_pp0_iter1 | tmp_2358_fu_26409_p3);
assign tmp_597_fu_26446_p2 = (ap_reg_ppstg_tmp_2030_reg_41344_pp0_iter1 | tmp_2359_fu_26438_p3);
assign tmp_598_fu_26475_p3 = {{tmp_2360_fu_26467_p3}, {tmp_2338_fu_26161_p2}};
assign tmp_599_fu_26483_p2 = (tmp_598_fu_26475_p3 | ap_const_lv2_1);
assign tmp_600_fu_26511_p2 = (ap_reg_ppstg_tmp_2034_reg_41351_pp0_iter1 | tmp_2362_fu_26507_p1);
assign tmp_601_fu_26516_p2 = (tmp1360_fu_26193_p3 | ap_const_lv3_1);
assign tmp_602_fu_26538_p2 = (ap_reg_ppstg_tmp_1150_reg_40708_pp0_iter1 | tmp_2363_fu_26530_p3);
assign tmp_603_fu_26543_p2 = (tmp_2346_fu_26257_p2 | ap_const_lv3_1);
assign tmp_604_fu_26565_p2 = (ap_reg_ppstg_tmp_1164_reg_40715_pp0_iter1 | tmp_2364_fu_26557_p3);
assign tmp_605_fu_26793_p2 = (ap_reg_ppstg_tmp_2040_reg_41358_pp0_iter1 | tmp_2367_fu_26789_p1);
assign tmp_606_fu_26802_p2 = (ap_reg_ppstg_tmp_2042_reg_41365_pp0_iter1 | tmp_2368_fu_26798_p1);
assign tmp_607_fu_26815_p2 = (ap_reg_ppstg_tmp_2044_reg_41372_pp0_iter1 | tmp_2369_fu_26807_p3);
assign tmp_608_fu_26828_p2 = (ap_reg_ppstg_tmp_2046_reg_41379_pp0_iter1 | tmp_2370_fu_26820_p3);
assign tmp_609_fu_26841_p2 = (ap_reg_ppstg_tmp_2048_reg_41386_pp0_iter1 | tmp_2371_fu_26833_p3);
assign tmp_610_fu_26854_p2 = (ap_reg_ppstg_tmp_2050_reg_41393_pp0_iter1 | tmp_2372_fu_26846_p3);
assign tmp_611_fu_26867_p2 = (ap_reg_ppstg_tmp_2052_reg_41400_pp0_iter1 | tmp_2373_fu_26859_p3);
assign tmp_612_fu_26880_p2 = (ap_reg_ppstg_tmp_2054_reg_41407_pp0_iter1 | tmp_2374_fu_26872_p3);
assign tmp_613_fu_26893_p2 = (ap_reg_ppstg_tmp_2056_reg_41414_pp0_iter1 | tmp_2375_fu_26885_p3);
assign tmp_614_fu_26906_p2 = (ap_reg_ppstg_tmp_2058_reg_41421_pp0_iter1 | tmp_2376_fu_26898_p3);
assign tmp_615_fu_26919_p2 = (ap_reg_ppstg_tmp_2060_reg_41428_pp0_iter1 | tmp_2377_fu_26911_p3);
assign tmp_616_fu_26948_p2 = (ap_reg_ppstg_tmp_2062_reg_41435_pp0_iter1 | tmp_2378_fu_26940_p3);
assign tmp_617_fu_26973_p2 = (tmp_2379_fu_26969_p1 | ap_const_lv2_1);
assign tmp_618_fu_26979_p4 = {{bt_ci_V57_4_fu_26749_p3[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_619_fu_27001_p2 = (ap_reg_ppstg_tmp_2065_reg_41442_pp0_iter1 | tmp_2380_fu_26997_p1);
assign tmp_620_fu_27010_p2 = (tmp_2381_fu_27006_p1 | ap_const_lv3_1);
assign tmp_621_fu_27040_p2 = (ap_reg_ppstg_tmp_1173_reg_40750_pp0_iter1 | tmp_2383_fu_27032_p3);
assign tmp_622_fu_27053_p2 = (ap_reg_ppstg_tmp_1188_reg_40757_pp0_iter1 | tmp_2384_fu_27045_p3);
assign tmp_623_fu_27273_p2 = (ap_reg_ppstg_tmp_2073_reg_41449_pp0_iter1 | tmp_2387_fu_27269_p1);
assign tmp_624_fu_27282_p2 = (ap_reg_ppstg_tmp_2075_reg_41456_pp0_iter1 | tmp_2388_fu_27278_p1);
assign tmp_625_fu_27295_p2 = (ap_reg_ppstg_tmp_2077_reg_41463_pp0_iter1 | tmp_2389_fu_27287_p3);
assign tmp_626_fu_27308_p2 = (ap_reg_ppstg_tmp_2079_reg_41470_pp0_iter1 | tmp_2390_fu_27300_p3);
assign tmp_627_fu_27321_p2 = (ap_reg_ppstg_tmp_2081_reg_41477_pp0_iter1 | tmp_2391_fu_27313_p3);
assign tmp_628_fu_27334_p2 = (ap_reg_ppstg_tmp_2083_reg_41484_pp0_iter1 | tmp_2392_fu_27326_p3);
assign tmp_629_fu_27347_p2 = (ap_reg_ppstg_tmp_2085_reg_41491_pp0_iter1 | tmp_2393_fu_27339_p3);
assign tmp_630_fu_27360_p2 = (ap_reg_ppstg_tmp_2087_reg_41498_pp0_iter1 | tmp_2394_fu_27352_p3);
assign tmp_631_fu_27373_p2 = (ap_reg_ppstg_tmp_2089_reg_41505_pp0_iter1 | tmp_2395_fu_27365_p3);
assign tmp_632_fu_27386_p2 = (ap_reg_ppstg_tmp_2091_reg_41512_pp0_iter1 | tmp_2396_fu_27378_p3);
assign tmp_633_fu_27399_p2 = (ap_reg_ppstg_tmp_2093_reg_41519_pp0_iter1 | tmp_2397_fu_27391_p3);
assign tmp_634_fu_27428_p2 = (ap_reg_ppstg_tmp_2095_reg_41526_pp0_iter1 | tmp_2398_fu_27420_p3);
assign tmp_635_fu_27453_p2 = (ap_reg_ppstg_tmp_2097_reg_41533_pp0_iter1 | tmp_2399_fu_27449_p1);
assign tmp_636_fu_27466_p2 = (ap_reg_ppstg_tmp_1197_reg_40792_pp0_iter1 | tmp_2400_fu_27458_p3);
assign tmp_637_fu_27479_p2 = (ap_reg_ppstg_tmp_1199_reg_40799_pp0_iter1 | tmp_2401_fu_27471_p3);
assign tmp_638_fu_27691_p2 = (ap_reg_ppstg_tmp_2103_reg_41540_pp0_iter1 | tmp_2404_fu_27687_p1);
assign tmp_639_fu_27700_p2 = (ap_reg_ppstg_tmp_2105_reg_41547_pp0_iter1 | tmp_2405_fu_27696_p1);
assign tmp_640_fu_27713_p2 = (ap_reg_ppstg_tmp_2107_reg_41554_pp0_iter1 | tmp_2406_fu_27705_p3);
assign tmp_641_fu_27726_p2 = (ap_reg_ppstg_tmp_2109_reg_41561_pp0_iter1 | tmp_2407_fu_27718_p3);
assign tmp_642_fu_27739_p2 = (ap_reg_ppstg_tmp_2111_reg_41568_pp0_iter1 | tmp_2408_fu_27731_p3);
assign tmp_643_fu_27752_p2 = (ap_reg_ppstg_tmp_2113_reg_41575_pp0_iter1 | tmp_2409_fu_27744_p3);
assign tmp_644_fu_27765_p2 = (ap_reg_ppstg_tmp_2115_reg_41582_pp0_iter1 | tmp_2410_fu_27757_p3);
assign tmp_645_fu_27778_p2 = (ap_reg_ppstg_tmp_2117_reg_41589_pp0_iter1 | tmp_2411_fu_27770_p3);
assign tmp_646_fu_27791_p2 = (ap_reg_ppstg_tmp_2119_reg_41596_pp0_iter1 | tmp_2412_fu_27783_p3);
assign tmp_647_fu_27804_p2 = (ap_reg_ppstg_tmp_2121_reg_41603_pp0_iter1 | tmp_2413_fu_27796_p3);
assign tmp_648_fu_27817_p2 = (ap_reg_ppstg_tmp_2123_reg_41610_pp0_iter1 | tmp_2414_fu_27809_p3);
assign tmp_649_fu_27846_p2 = (ap_reg_ppstg_tmp_2125_reg_41617_pp0_iter1 | tmp_2415_fu_27838_p3);
assign tmp_650_fu_27871_p2 = (ap_reg_ppstg_tmp_2127_reg_41624_pp0_iter1 | tmp_2416_fu_27867_p1);
assign tmp_651_fu_27884_p2 = (ap_reg_ppstg_tmp_1222_reg_40834_pp0_iter1 | tmp_2417_fu_27876_p3);
assign tmp_652_fu_27897_p2 = (ap_reg_ppstg_tmp_1236_reg_40841_pp0_iter1 | tmp_2418_fu_27889_p3);
assign tmp_653_fu_28081_p2 = (tmp_2420_fu_28073_p3 | r_V_177_1_6_fu_27663_p3);
assign tmp_654_fu_28215_p2 = (ap_reg_ppstg_tmp_2143_reg_41631_pp0_iter1 | tmp_2431_fu_28211_p1);
assign tmp_655_fu_28224_p2 = (ap_reg_ppstg_tmp_2145_reg_41638_pp0_iter1 | tmp_2432_fu_28220_p1);
assign tmp_656_fu_28237_p2 = (ap_reg_ppstg_tmp_2147_reg_41645_pp0_iter1 | tmp_2433_fu_28229_p3);
assign tmp_657_fu_28250_p2 = (ap_reg_ppstg_tmp_2149_reg_41652_pp0_iter1 | tmp_2434_fu_28242_p3);
assign tmp_658_fu_28263_p2 = (ap_reg_ppstg_tmp_2151_reg_41659_pp0_iter1 | tmp_2435_fu_28255_p3);
assign tmp_659_fu_28276_p2 = (ap_reg_ppstg_tmp_2153_reg_41666_pp0_iter1 | tmp_2436_fu_28268_p3);
assign tmp_660_fu_28289_p2 = (ap_reg_ppstg_tmp_2155_reg_41673_pp0_iter1 | tmp_2437_fu_28281_p3);
assign tmp_661_fu_28302_p2 = (ap_reg_ppstg_tmp_2157_reg_41680_pp0_iter1 | tmp_2438_fu_28294_p3);
assign tmp_662_fu_28315_p2 = (ap_reg_ppstg_tmp_2159_reg_41687_pp0_iter1 | tmp_2439_fu_28307_p3);
assign tmp_663_fu_28328_p2 = (ap_reg_ppstg_tmp_2161_reg_41694_pp0_iter1 | tmp_2440_fu_28320_p3);
assign tmp_664_fu_28341_p2 = (ap_reg_ppstg_tmp_2163_reg_41701_pp0_iter1 | tmp_2441_fu_28333_p3);
assign tmp_665_fu_28370_p2 = (ap_reg_ppstg_tmp_2165_reg_41708_pp0_iter1 | tmp_2442_fu_28362_p3);
assign tmp_666_fu_28395_p2 = (tmp_2443_fu_28391_p1 | ap_const_lv2_1);
assign tmp_667_fu_28401_p4 = {{bt_ci_V57_7_fu_28095_p2[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_668_fu_28423_p2 = (ap_reg_ppstg_tmp_2168_reg_41715_pp0_iter1 | tmp_2444_fu_28419_p1);
assign tmp_669_fu_28428_p2 = (tmp_2423_fu_28127_p2 | ap_const_lv3_1);
assign tmp_670_fu_28450_p2 = (ap_reg_ppstg_tmp_1167_reg_40722_pp0_iter1 | tmp_2445_fu_28442_p3);
assign tmp_671_fu_28455_p2 = (tmp_2429_fu_28181_p2 | ap_const_lv3_1);
assign tmp_672_fu_28477_p2 = (ap_reg_ppstg_tmp_1169_reg_40729_pp0_iter1 | tmp_2446_fu_28469_p3);
assign tmp_673_fu_28697_p2 = (ap_reg_ppstg_tmp_2174_reg_41722_pp0_iter1 | tmp_2449_fu_28693_p1);
assign tmp_674_fu_28706_p2 = (ap_reg_ppstg_tmp_2176_reg_41729_pp0_iter1 | tmp_2450_fu_28702_p1);
assign tmp_675_fu_28719_p2 = (ap_reg_ppstg_tmp_2178_reg_41736_pp0_iter1 | tmp_2451_fu_28711_p3);
assign tmp_676_fu_28732_p2 = (ap_reg_ppstg_tmp_2180_reg_41743_pp0_iter1 | tmp_2452_fu_28724_p3);
assign tmp_677_fu_28745_p2 = (ap_reg_ppstg_tmp_2182_reg_41750_pp0_iter1 | tmp_2453_fu_28737_p3);
assign tmp_678_fu_28758_p2 = (ap_reg_ppstg_tmp_2184_reg_41757_pp0_iter1 | tmp_2454_fu_28750_p3);
assign tmp_679_fu_28771_p2 = (ap_reg_ppstg_tmp_2186_reg_41764_pp0_iter1 | tmp_2455_fu_28763_p3);
assign tmp_680_fu_28784_p2 = (ap_reg_ppstg_tmp_2188_reg_41771_pp0_iter1 | tmp_2456_fu_28776_p3);
assign tmp_681_fu_28797_p2 = (ap_reg_ppstg_tmp_2190_reg_41778_pp0_iter1 | tmp_2457_fu_28789_p3);
assign tmp_682_fu_28810_p2 = (ap_reg_ppstg_tmp_2192_reg_41785_pp0_iter1 | tmp_2458_fu_28802_p3);
assign tmp_683_fu_28823_p2 = (ap_reg_ppstg_tmp_2194_reg_41792_pp0_iter1 | tmp_2459_fu_28815_p3);
assign tmp_684_fu_28852_p2 = (ap_reg_ppstg_tmp_2196_reg_41799_pp0_iter1 | tmp_2460_fu_28844_p3);
assign tmp_685_fu_28877_p2 = (tmp_2461_fu_28873_p1 | ap_const_lv2_1);
assign tmp_686_fu_28883_p4 = {{bt_ci_V57_8_fu_28653_p3[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_687_fu_28905_p2 = (ap_reg_ppstg_tmp_2199_reg_41806_pp0_iter1 | tmp_2462_fu_28901_p1);
assign tmp_688_fu_28914_p2 = (tmp_2463_fu_28910_p1 | ap_const_lv3_1);
assign tmp_689_fu_28944_p2 = (ap_reg_ppstg_tmp_1190_reg_40764_pp0_iter1 | tmp_2465_fu_28936_p3);
assign tmp_690_fu_28957_p2 = (ap_reg_ppstg_tmp_1191_reg_40771_pp0_iter1 | tmp_2466_fu_28949_p3);
assign tmp_691_fu_29185_p2 = (ap_reg_ppstg_tmp_2207_reg_41813_pp0_iter1 | tmp_2469_fu_29181_p1);
assign tmp_692_fu_29194_p2 = (ap_reg_ppstg_tmp_2209_reg_41820_pp0_iter1 | tmp_2470_fu_29190_p1);
assign tmp_693_fu_29207_p2 = (ap_reg_ppstg_tmp_2211_reg_41827_pp0_iter1 | tmp_2471_fu_29199_p3);
assign tmp_694_fu_29220_p2 = (ap_reg_ppstg_tmp_2213_reg_41834_pp0_iter1 | tmp_2472_fu_29212_p3);
assign tmp_695_fu_29233_p2 = (ap_reg_ppstg_tmp_2215_reg_41841_pp0_iter1 | tmp_2473_fu_29225_p3);
assign tmp_696_fu_29246_p2 = (ap_reg_ppstg_tmp_2217_reg_41848_pp0_iter1 | tmp_2474_fu_29238_p3);
assign tmp_697_fu_29259_p2 = (ap_reg_ppstg_tmp_2219_reg_41855_pp0_iter1 | tmp_2475_fu_29251_p3);
assign tmp_698_fu_29272_p2 = (ap_reg_ppstg_tmp_2221_reg_41862_pp0_iter1 | tmp_2476_fu_29264_p3);
assign tmp_699_fu_29285_p2 = (ap_reg_ppstg_tmp_2223_reg_41869_pp0_iter1 | tmp_2477_fu_29277_p3);
assign tmp_700_fu_29298_p2 = (ap_reg_ppstg_tmp_2225_reg_41876_pp0_iter1 | tmp_2478_fu_29290_p3);
assign tmp_701_fu_29311_p2 = (ap_reg_ppstg_tmp_2227_reg_41883_pp0_iter1 | tmp_2479_fu_29303_p3);
assign tmp_702_fu_29340_p2 = (ap_reg_ppstg_tmp_2229_reg_41890_pp0_iter1 | tmp_2480_fu_29332_p3);
assign tmp_703_fu_29365_p2 = (ap_reg_ppstg_tmp_2231_reg_41897_pp0_iter1 | tmp_2481_fu_29361_p1);
assign tmp_704_fu_29378_p2 = (ap_reg_ppstg_tmp_1212_reg_40806_pp0_iter1 | tmp_2482_fu_29370_p3);
assign tmp_705_fu_29391_p2 = (ap_reg_ppstg_tmp_1216_reg_40813_pp0_iter1 | tmp_2483_fu_29383_p3);
assign tmp_706_fu_29595_p2 = (ap_reg_ppstg_tmp_2237_reg_41904_pp0_iter1 | tmp_2486_fu_29591_p1);
assign tmp_707_fu_29604_p2 = (ap_reg_ppstg_tmp_2239_reg_41911_pp0_iter1 | tmp_2487_fu_29600_p1);
assign tmp_708_fu_29617_p2 = (ap_reg_ppstg_tmp_2241_reg_41918_pp0_iter1 | tmp_2488_fu_29609_p3);
assign tmp_709_fu_29630_p2 = (ap_reg_ppstg_tmp_2243_reg_41925_pp0_iter1 | tmp_2489_fu_29622_p3);
assign tmp_710_fu_29643_p2 = (ap_reg_ppstg_tmp_2245_reg_41932_pp0_iter1 | tmp_2490_fu_29635_p3);
assign tmp_711_fu_29656_p2 = (ap_reg_ppstg_tmp_2247_reg_41939_pp0_iter1 | tmp_2491_fu_29648_p3);
assign tmp_712_fu_29669_p2 = (ap_reg_ppstg_tmp_2249_reg_41946_pp0_iter1 | tmp_2492_fu_29661_p3);
assign tmp_713_fu_29682_p2 = (ap_reg_ppstg_tmp_2251_reg_41953_pp0_iter1 | tmp_2493_fu_29674_p3);
assign tmp_714_fu_29695_p2 = (ap_reg_ppstg_tmp_2253_reg_41960_pp0_iter1 | tmp_2494_fu_29687_p3);
assign tmp_715_fu_29708_p2 = (ap_reg_ppstg_tmp_2255_reg_41967_pp0_iter1 | tmp_2495_fu_29700_p3);
assign tmp_716_fu_29721_p2 = (ap_reg_ppstg_tmp_2257_reg_41974_pp0_iter1 | tmp_2496_fu_29713_p3);
assign tmp_717_fu_29750_p2 = (ap_reg_ppstg_tmp_2259_reg_41981_pp0_iter1 | tmp_2497_fu_29742_p3);
assign tmp_718_fu_29775_p2 = (ap_reg_ppstg_tmp_2261_reg_41988_pp0_iter1 | tmp_2498_fu_29771_p1);
assign tmp_719_fu_29788_p2 = (ap_reg_ppstg_tmp_1239_reg_40848_pp0_iter1 | tmp_2499_fu_29780_p3);
assign tmp_720_fu_29801_p2 = (ap_reg_ppstg_tmp_1253_reg_40855_pp0_iter1 | tmp_2500_fu_29793_p3);
assign tmp_721_fu_31491_p2 = (tmp_2512_fu_31483_p3 | r_V_177_1_s_fu_29567_p3);
assign tmp_722_fu_31760_p2 = (ap_reg_ppstg_tmp_1905_reg_40994_pp0_iter1 | tmp_2522_fu_31756_p1);
assign tmp_723_fu_31769_p2 = (ap_reg_ppstg_tmp_1907_reg_41001_pp0_iter1 | tmp_2523_fu_31765_p1);
assign tmp_724_fu_31782_p2 = (ap_reg_ppstg_tmp_1909_reg_41008_pp0_iter1 | tmp_2524_fu_31774_p3);
assign tmp_725_fu_31795_p2 = (ap_reg_ppstg_tmp_1911_reg_41015_pp0_iter1 | tmp_2525_fu_31787_p3);
assign tmp_726_fu_31808_p2 = (ap_reg_ppstg_tmp_1913_reg_41022_pp0_iter1 | tmp_2526_fu_31800_p3);
assign tmp_727_fu_31821_p2 = (ap_reg_ppstg_tmp_1915_reg_41029_pp0_iter1 | tmp_2527_fu_31813_p3);
assign tmp_728_fu_31834_p2 = (ap_reg_ppstg_tmp_1917_reg_41036_pp0_iter1 | tmp_2528_fu_31826_p3);
assign tmp_729_fu_31847_p2 = (ap_reg_ppstg_tmp_1919_reg_41043_pp0_iter1 | tmp_2529_fu_31839_p3);
assign tmp_730_fu_31860_p2 = (ap_reg_ppstg_tmp_1921_reg_41050_pp0_iter1 | tmp_2530_fu_31852_p3);
assign tmp_731_fu_31873_p2 = (ap_reg_ppstg_tmp_1923_reg_41057_pp0_iter1 | tmp_2531_fu_31865_p3);
assign tmp_732_fu_31886_p2 = (ap_reg_ppstg_tmp_1925_reg_41064_pp0_iter1 | tmp_2532_fu_31878_p3);
assign tmp_733_fu_31915_p2 = (ap_reg_ppstg_tmp_1927_reg_41071_pp0_iter1 | tmp_2533_fu_31907_p3);
assign tmp_734_fu_31940_p2 = (ap_reg_ppstg_tmp_1929_reg_41078_pp0_iter1 | tmp_2534_fu_31936_p1);
assign tmp_735_fu_31953_p2 = (ap_reg_ppstg_tmp_1170_reg_40736_pp0_iter1 | tmp_2535_fu_31945_p3);
assign tmp_736_fu_31966_p2 = (ap_reg_ppstg_tmp_1172_reg_40743_pp0_iter1 | tmp_2536_fu_31958_p3);
assign tmp_737_fu_32176_p2 = (ap_reg_ppstg_tmp_1936_reg_41085_pp0_iter1 | tmp_2540_fu_32172_p1);
assign tmp_738_fu_32185_p2 = (ap_reg_ppstg_tmp_1938_reg_41092_pp0_iter1 | tmp_2541_fu_32181_p1);
assign tmp_739_fu_32198_p2 = (ap_reg_ppstg_tmp_1940_reg_41099_pp0_iter1 | tmp_2542_fu_32190_p3);
assign tmp_740_fu_32211_p2 = (ap_reg_ppstg_tmp_1942_reg_41106_pp0_iter1 | tmp_2543_fu_32203_p3);
assign tmp_741_fu_32224_p2 = (ap_reg_ppstg_tmp_1944_reg_41113_pp0_iter1 | tmp_2544_fu_32216_p3);
assign tmp_742_fu_32237_p2 = (ap_reg_ppstg_tmp_1946_reg_41120_pp0_iter1 | tmp_2545_fu_32229_p3);
assign tmp_743_fu_32250_p2 = (ap_reg_ppstg_tmp_1948_reg_41127_pp0_iter1 | tmp_2546_fu_32242_p3);
assign tmp_744_fu_32263_p2 = (ap_reg_ppstg_tmp_1950_reg_41134_pp0_iter1 | tmp_2547_fu_32255_p3);
assign tmp_745_fu_32276_p2 = (ap_reg_ppstg_tmp_1952_reg_41141_pp0_iter1 | tmp_2548_fu_32268_p3);
assign tmp_746_fu_32289_p2 = (ap_reg_ppstg_tmp_1954_reg_41148_pp0_iter1 | tmp_2549_fu_32281_p3);
assign tmp_747_fu_32302_p2 = (ap_reg_ppstg_tmp_1956_reg_41155_pp0_iter1 | tmp_2550_fu_32294_p3);
assign tmp_748_fu_32331_p2 = (ap_reg_ppstg_tmp_1958_reg_41162_pp0_iter1 | tmp_2551_fu_32323_p3);
assign tmp_749_fu_32356_p2 = (ap_reg_ppstg_tmp_1960_reg_41169_pp0_iter1 | tmp_2552_fu_32352_p1);
assign tmp_750_fu_32369_p2 = (ap_reg_ppstg_tmp_1193_reg_40778_pp0_iter1 | tmp_2553_fu_32361_p3);
assign tmp_751_fu_32382_p2 = (ap_reg_ppstg_tmp_1195_reg_40785_pp0_iter1 | tmp_2554_fu_32374_p3);
assign tmp_752_fu_32586_p2 = (ap_reg_ppstg_tmp_1966_reg_41176_pp0_iter1 | tmp_2557_fu_32582_p1);
assign tmp_753_fu_32595_p2 = (ap_reg_ppstg_tmp_1968_reg_41183_pp0_iter1 | tmp_2558_fu_32591_p1);
assign tmp_754_fu_32608_p2 = (ap_reg_ppstg_tmp_1970_reg_41190_pp0_iter1 | tmp_2559_fu_32600_p3);
assign tmp_755_fu_32621_p2 = (ap_reg_ppstg_tmp_1972_reg_41197_pp0_iter1 | tmp_2560_fu_32613_p3);
assign tmp_756_fu_32634_p2 = (ap_reg_ppstg_tmp_1974_reg_41204_pp0_iter1 | tmp_2561_fu_32626_p3);
assign tmp_757_fu_32647_p2 = (ap_reg_ppstg_tmp_1976_reg_41211_pp0_iter1 | tmp_2562_fu_32639_p3);
assign tmp_758_fu_32660_p2 = (ap_reg_ppstg_tmp_1978_reg_41218_pp0_iter1 | tmp_2563_fu_32652_p3);
assign tmp_759_fu_32673_p2 = (ap_reg_ppstg_tmp_1980_reg_41225_pp0_iter1 | tmp_2564_fu_32665_p3);
assign tmp_760_fu_32686_p2 = (ap_reg_ppstg_tmp_1982_reg_41232_pp0_iter1 | tmp_2565_fu_32678_p3);
assign tmp_761_fu_32699_p2 = (ap_reg_ppstg_tmp_1984_reg_41239_pp0_iter1 | tmp_2566_fu_32691_p3);
assign tmp_762_fu_32712_p2 = (ap_reg_ppstg_tmp_1986_reg_41246_pp0_iter1 | tmp_2567_fu_32704_p3);
assign tmp_763_fu_32741_p2 = (ap_reg_ppstg_tmp_1988_reg_41253_pp0_iter1 | tmp_2568_fu_32733_p3);
assign tmp_764_fu_32766_p2 = (ap_reg_ppstg_tmp_1990_reg_41260_pp0_iter1 | tmp_2569_fu_32762_p1);
assign tmp_765_fu_32779_p2 = (ap_reg_ppstg_tmp_1217_reg_40820_pp0_iter1 | tmp_2570_fu_32771_p3);
assign tmp_766_fu_32792_p2 = (ap_reg_ppstg_tmp_1219_reg_40827_pp0_iter1 | tmp_2571_fu_32784_p3);
assign tmp_767_fu_32988_p2 = (tmp_2573_fu_32984_p1 | r_V_177_2_2_fu_32558_p3);
assign tmp_768_fu_33086_p3 = {{tmp_2582_fu_33078_p3}, {tmp_2520_fu_31585_p3}};
assign tmp_769_fu_33128_p2 = (ap_reg_ppstg_tmp_2008_reg_41267_pp0_iter1 | tmp_2585_fu_33124_p1);
assign tmp_770_fu_33137_p2 = (ap_reg_ppstg_tmp_2010_reg_41274_pp0_iter1 | tmp_2586_fu_33133_p1);
assign tmp_771_fu_33150_p2 = (ap_reg_ppstg_tmp_2012_reg_41281_pp0_iter1 | tmp_2587_fu_33142_p3);
assign tmp_772_fu_33163_p2 = (ap_reg_ppstg_tmp_2014_reg_41288_pp0_iter1 | tmp_2588_fu_33155_p3);
assign tmp_773_fu_33176_p2 = (ap_reg_ppstg_tmp_2016_reg_41295_pp0_iter1 | tmp_2589_fu_33168_p3);
assign tmp_774_fu_33189_p2 = (ap_reg_ppstg_tmp_2018_reg_41302_pp0_iter1 | tmp_2590_fu_33181_p3);
assign tmp_775_fu_33202_p2 = (ap_reg_ppstg_tmp_2020_reg_41309_pp0_iter1 | tmp_2591_fu_33194_p3);
assign tmp_776_fu_33215_p2 = (ap_reg_ppstg_tmp_2022_reg_41316_pp0_iter1 | tmp_2592_fu_33207_p3);
assign tmp_777_fu_33228_p2 = (ap_reg_ppstg_tmp_2024_reg_41323_pp0_iter1 | tmp_2593_fu_33220_p3);
assign tmp_778_fu_33241_p2 = (ap_reg_ppstg_tmp_2026_reg_41330_pp0_iter1 | tmp_2594_fu_33233_p3);
assign tmp_779_fu_33254_p2 = (ap_reg_ppstg_tmp_2028_reg_41337_pp0_iter1 | tmp_2595_fu_33246_p3);
assign tmp_780_fu_33283_p2 = (ap_reg_ppstg_tmp_2030_reg_41344_pp0_iter1 | tmp_2596_fu_33275_p3);
assign tmp_781_fu_33312_p3 = {{tmp_2597_fu_33304_p3}, {tmp_2575_fu_32998_p2}};
assign tmp_782_fu_33320_p2 = (tmp_781_fu_33312_p3 | ap_const_lv2_1);
assign tmp_783_fu_33348_p2 = (ap_reg_ppstg_tmp_2034_reg_41351_pp0_iter1 | tmp_2599_fu_33344_p1);
assign tmp_784_fu_33353_p2 = (tmp1621_fu_33030_p3 | ap_const_lv3_1);
assign tmp_785_fu_33375_p2 = (ap_reg_ppstg_tmp_1150_reg_40708_pp0_iter1 | tmp_2600_fu_33367_p3);
assign tmp_786_fu_33380_p2 = (tmp_2583_fu_33094_p2 | ap_const_lv3_1);
assign tmp_787_fu_33402_p2 = (ap_reg_ppstg_tmp_1164_reg_40715_pp0_iter1 | tmp_2601_fu_33394_p3);
assign tmp_788_fu_33630_p2 = (ap_reg_ppstg_tmp_2040_reg_41358_pp0_iter1 | tmp_2604_fu_33626_p1);
assign tmp_789_fu_33639_p2 = (ap_reg_ppstg_tmp_2042_reg_41365_pp0_iter1 | tmp_2605_fu_33635_p1);
assign tmp_790_fu_33652_p2 = (ap_reg_ppstg_tmp_2044_reg_41372_pp0_iter1 | tmp_2606_fu_33644_p3);
assign tmp_791_fu_33665_p2 = (ap_reg_ppstg_tmp_2046_reg_41379_pp0_iter1 | tmp_2607_fu_33657_p3);
assign tmp_792_fu_33678_p2 = (ap_reg_ppstg_tmp_2048_reg_41386_pp0_iter1 | tmp_2608_fu_33670_p3);
assign tmp_793_fu_33691_p2 = (ap_reg_ppstg_tmp_2050_reg_41393_pp0_iter1 | tmp_2609_fu_33683_p3);
assign tmp_794_fu_33704_p2 = (ap_reg_ppstg_tmp_2052_reg_41400_pp0_iter1 | tmp_2610_fu_33696_p3);
assign tmp_795_fu_33717_p2 = (ap_reg_ppstg_tmp_2054_reg_41407_pp0_iter1 | tmp_2611_fu_33709_p3);
assign tmp_796_fu_33730_p2 = (ap_reg_ppstg_tmp_2056_reg_41414_pp0_iter1 | tmp_2612_fu_33722_p3);
assign tmp_797_fu_33743_p2 = (ap_reg_ppstg_tmp_2058_reg_41421_pp0_iter1 | tmp_2613_fu_33735_p3);
assign tmp_798_fu_33756_p2 = (ap_reg_ppstg_tmp_2060_reg_41428_pp0_iter1 | tmp_2614_fu_33748_p3);
assign tmp_799_fu_33785_p2 = (ap_reg_ppstg_tmp_2062_reg_41435_pp0_iter1 | tmp_2615_fu_33777_p3);
assign tmp_800_fu_33810_p2 = (tmp_2616_fu_33806_p1 | ap_const_lv2_1);
assign tmp_801_fu_33816_p4 = {{bt_ci_V58_4_fu_33586_p3[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_802_fu_33838_p2 = (ap_reg_ppstg_tmp_2065_reg_41442_pp0_iter1 | tmp_2617_fu_33834_p1);
assign tmp_803_fu_33847_p2 = (tmp_2618_fu_33843_p1 | ap_const_lv3_1);
assign tmp_804_fu_33877_p2 = (ap_reg_ppstg_tmp_1173_reg_40750_pp0_iter1 | tmp_2620_fu_33869_p3);
assign tmp_805_fu_33890_p2 = (ap_reg_ppstg_tmp_1188_reg_40757_pp0_iter1 | tmp_2621_fu_33882_p3);
assign tmp_806_fu_34110_p2 = (ap_reg_ppstg_tmp_2073_reg_41449_pp0_iter1 | tmp_2624_fu_34106_p1);
assign tmp_807_fu_34119_p2 = (ap_reg_ppstg_tmp_2075_reg_41456_pp0_iter1 | tmp_2625_fu_34115_p1);
assign tmp_808_fu_34132_p2 = (ap_reg_ppstg_tmp_2077_reg_41463_pp0_iter1 | tmp_2626_fu_34124_p3);
assign tmp_809_fu_34145_p2 = (ap_reg_ppstg_tmp_2079_reg_41470_pp0_iter1 | tmp_2627_fu_34137_p3);
assign tmp_810_fu_34158_p2 = (ap_reg_ppstg_tmp_2081_reg_41477_pp0_iter1 | tmp_2628_fu_34150_p3);
assign tmp_811_fu_34171_p2 = (ap_reg_ppstg_tmp_2083_reg_41484_pp0_iter1 | tmp_2629_fu_34163_p3);
assign tmp_812_fu_34184_p2 = (ap_reg_ppstg_tmp_2085_reg_41491_pp0_iter1 | tmp_2630_fu_34176_p3);
assign tmp_813_fu_34197_p2 = (ap_reg_ppstg_tmp_2087_reg_41498_pp0_iter1 | tmp_2631_fu_34189_p3);
assign tmp_814_fu_34210_p2 = (ap_reg_ppstg_tmp_2089_reg_41505_pp0_iter1 | tmp_2632_fu_34202_p3);
assign tmp_815_fu_34223_p2 = (ap_reg_ppstg_tmp_2091_reg_41512_pp0_iter1 | tmp_2633_fu_34215_p3);
assign tmp_816_fu_34236_p2 = (ap_reg_ppstg_tmp_2093_reg_41519_pp0_iter1 | tmp_2634_fu_34228_p3);
assign tmp_817_fu_34265_p2 = (ap_reg_ppstg_tmp_2095_reg_41526_pp0_iter1 | tmp_2635_fu_34257_p3);
assign tmp_818_fu_34290_p2 = (ap_reg_ppstg_tmp_2097_reg_41533_pp0_iter1 | tmp_2636_fu_34286_p1);
assign tmp_819_fu_34303_p2 = (ap_reg_ppstg_tmp_1197_reg_40792_pp0_iter1 | tmp_2637_fu_34295_p3);
assign tmp_820_fu_34316_p2 = (ap_reg_ppstg_tmp_1199_reg_40799_pp0_iter1 | tmp_2638_fu_34308_p3);
assign tmp_821_fu_34528_p2 = (ap_reg_ppstg_tmp_2103_reg_41540_pp0_iter1 | tmp_2641_fu_34524_p1);
assign tmp_822_fu_34537_p2 = (ap_reg_ppstg_tmp_2105_reg_41547_pp0_iter1 | tmp_2642_fu_34533_p1);
assign tmp_823_fu_34550_p2 = (ap_reg_ppstg_tmp_2107_reg_41554_pp0_iter1 | tmp_2643_fu_34542_p3);
assign tmp_824_fu_34563_p2 = (ap_reg_ppstg_tmp_2109_reg_41561_pp0_iter1 | tmp_2644_fu_34555_p3);
assign tmp_825_fu_34576_p2 = (ap_reg_ppstg_tmp_2111_reg_41568_pp0_iter1 | tmp_2645_fu_34568_p3);
assign tmp_826_fu_34589_p2 = (ap_reg_ppstg_tmp_2113_reg_41575_pp0_iter1 | tmp_2646_fu_34581_p3);
assign tmp_827_fu_34602_p2 = (ap_reg_ppstg_tmp_2115_reg_41582_pp0_iter1 | tmp_2647_fu_34594_p3);
assign tmp_828_fu_34615_p2 = (ap_reg_ppstg_tmp_2117_reg_41589_pp0_iter1 | tmp_2648_fu_34607_p3);
assign tmp_829_fu_34628_p2 = (ap_reg_ppstg_tmp_2119_reg_41596_pp0_iter1 | tmp_2649_fu_34620_p3);
assign tmp_830_fu_34641_p2 = (ap_reg_ppstg_tmp_2121_reg_41603_pp0_iter1 | tmp_2650_fu_34633_p3);
assign tmp_831_fu_34654_p2 = (ap_reg_ppstg_tmp_2123_reg_41610_pp0_iter1 | tmp_2651_fu_34646_p3);
assign tmp_832_fu_34683_p2 = (ap_reg_ppstg_tmp_2125_reg_41617_pp0_iter1 | tmp_2652_fu_34675_p3);
assign tmp_833_fu_34708_p2 = (ap_reg_ppstg_tmp_2127_reg_41624_pp0_iter1 | tmp_2653_fu_34704_p1);
assign tmp_834_fu_34721_p2 = (ap_reg_ppstg_tmp_1222_reg_40834_pp0_iter1 | tmp_2654_fu_34713_p3);
assign tmp_835_fu_34734_p2 = (ap_reg_ppstg_tmp_1236_reg_40841_pp0_iter1 | tmp_2655_fu_34726_p3);
assign tmp_836_fu_34918_p2 = (tmp_2657_fu_34910_p3 | r_V_177_2_6_fu_34500_p3);
assign tmp_837_fu_35052_p2 = (ap_reg_ppstg_tmp_2143_reg_41631_pp0_iter1 | tmp_2668_fu_35048_p1);
assign tmp_838_fu_35061_p2 = (ap_reg_ppstg_tmp_2145_reg_41638_pp0_iter1 | tmp_2669_fu_35057_p1);
assign tmp_839_fu_35074_p2 = (ap_reg_ppstg_tmp_2147_reg_41645_pp0_iter1 | tmp_2670_fu_35066_p3);
assign tmp_840_fu_35087_p2 = (ap_reg_ppstg_tmp_2149_reg_41652_pp0_iter1 | tmp_2671_fu_35079_p3);
assign tmp_841_fu_35100_p2 = (ap_reg_ppstg_tmp_2151_reg_41659_pp0_iter1 | tmp_2672_fu_35092_p3);
assign tmp_842_fu_35113_p2 = (ap_reg_ppstg_tmp_2153_reg_41666_pp0_iter1 | tmp_2673_fu_35105_p3);
assign tmp_843_fu_35126_p2 = (ap_reg_ppstg_tmp_2155_reg_41673_pp0_iter1 | tmp_2674_fu_35118_p3);
assign tmp_844_fu_35139_p2 = (ap_reg_ppstg_tmp_2157_reg_41680_pp0_iter1 | tmp_2675_fu_35131_p3);
assign tmp_845_fu_35152_p2 = (ap_reg_ppstg_tmp_2159_reg_41687_pp0_iter1 | tmp_2676_fu_35144_p3);
assign tmp_846_fu_35165_p2 = (ap_reg_ppstg_tmp_2161_reg_41694_pp0_iter1 | tmp_2677_fu_35157_p3);
assign tmp_847_fu_35178_p2 = (ap_reg_ppstg_tmp_2163_reg_41701_pp0_iter1 | tmp_2678_fu_35170_p3);
assign tmp_848_fu_35207_p2 = (ap_reg_ppstg_tmp_2165_reg_41708_pp0_iter1 | tmp_2679_fu_35199_p3);
assign tmp_849_fu_35232_p2 = (tmp_2680_fu_35228_p1 | ap_const_lv2_1);
assign tmp_850_fu_35238_p4 = {{bt_ci_V58_7_fu_34932_p2[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_851_fu_35260_p2 = (ap_reg_ppstg_tmp_2168_reg_41715_pp0_iter1 | tmp_2681_fu_35256_p1);
assign tmp_852_fu_35265_p2 = (tmp_2660_fu_34964_p2 | ap_const_lv3_1);
assign tmp_853_fu_35287_p2 = (ap_reg_ppstg_tmp_1167_reg_40722_pp0_iter1 | tmp_2682_fu_35279_p3);
assign tmp_854_fu_35292_p2 = (tmp_2666_fu_35018_p2 | ap_const_lv3_1);
assign tmp_855_fu_35314_p2 = (ap_reg_ppstg_tmp_1169_reg_40729_pp0_iter1 | tmp_2683_fu_35306_p3);
assign tmp_856_fu_35534_p2 = (ap_reg_ppstg_tmp_2174_reg_41722_pp0_iter1 | tmp_2686_fu_35530_p1);
assign tmp_857_fu_35543_p2 = (ap_reg_ppstg_tmp_2176_reg_41729_pp0_iter1 | tmp_2687_fu_35539_p1);
assign tmp_858_fu_35556_p2 = (ap_reg_ppstg_tmp_2178_reg_41736_pp0_iter1 | tmp_2688_fu_35548_p3);
assign tmp_859_fu_35569_p2 = (ap_reg_ppstg_tmp_2180_reg_41743_pp0_iter1 | tmp_2689_fu_35561_p3);
assign tmp_860_fu_35582_p2 = (ap_reg_ppstg_tmp_2182_reg_41750_pp0_iter1 | tmp_2690_fu_35574_p3);
assign tmp_861_fu_35595_p2 = (ap_reg_ppstg_tmp_2184_reg_41757_pp0_iter1 | tmp_2691_fu_35587_p3);
assign tmp_862_fu_35608_p2 = (ap_reg_ppstg_tmp_2186_reg_41764_pp0_iter1 | tmp_2692_fu_35600_p3);
assign tmp_863_fu_35621_p2 = (ap_reg_ppstg_tmp_2188_reg_41771_pp0_iter1 | tmp_2693_fu_35613_p3);
assign tmp_864_fu_35634_p2 = (ap_reg_ppstg_tmp_2190_reg_41778_pp0_iter1 | tmp_2694_fu_35626_p3);
assign tmp_865_fu_35647_p2 = (ap_reg_ppstg_tmp_2192_reg_41785_pp0_iter1 | tmp_2695_fu_35639_p3);
assign tmp_866_fu_35660_p2 = (ap_reg_ppstg_tmp_2194_reg_41792_pp0_iter1 | tmp_2696_fu_35652_p3);
assign tmp_867_fu_35689_p2 = (ap_reg_ppstg_tmp_2196_reg_41799_pp0_iter1 | tmp_2697_fu_35681_p3);
assign tmp_868_fu_35714_p2 = (tmp_2698_fu_35710_p1 | ap_const_lv2_1);
assign tmp_869_fu_35720_p4 = {{bt_ci_V58_8_fu_35490_p3[ap_const_lv32_3 : ap_const_lv32_2]}};
assign tmp_870_fu_35742_p2 = (ap_reg_ppstg_tmp_2199_reg_41806_pp0_iter1 | tmp_2699_fu_35738_p1);
assign tmp_871_fu_35751_p2 = (tmp_2700_fu_35747_p1 | ap_const_lv3_1);
assign tmp_872_fu_35781_p2 = (ap_reg_ppstg_tmp_1190_reg_40764_pp0_iter1 | tmp_2702_fu_35773_p3);
assign tmp_873_fu_35794_p2 = (ap_reg_ppstg_tmp_1191_reg_40771_pp0_iter1 | tmp_2703_fu_35786_p3);
assign tmp_874_fu_36022_p2 = (ap_reg_ppstg_tmp_2207_reg_41813_pp0_iter1 | tmp_2706_fu_36018_p1);
assign tmp_875_fu_36031_p2 = (ap_reg_ppstg_tmp_2209_reg_41820_pp0_iter1 | tmp_2707_fu_36027_p1);
assign tmp_876_fu_36044_p2 = (ap_reg_ppstg_tmp_2211_reg_41827_pp0_iter1 | tmp_2708_fu_36036_p3);
assign tmp_877_fu_36057_p2 = (ap_reg_ppstg_tmp_2213_reg_41834_pp0_iter1 | tmp_2709_fu_36049_p3);
assign tmp_878_fu_36070_p2 = (ap_reg_ppstg_tmp_2215_reg_41841_pp0_iter1 | tmp_2710_fu_36062_p3);
assign tmp_879_fu_36083_p2 = (ap_reg_ppstg_tmp_2217_reg_41848_pp0_iter1 | tmp_2711_fu_36075_p3);
assign tmp_880_fu_36096_p2 = (ap_reg_ppstg_tmp_2219_reg_41855_pp0_iter1 | tmp_2712_fu_36088_p3);
assign tmp_881_fu_36109_p2 = (ap_reg_ppstg_tmp_2221_reg_41862_pp0_iter1 | tmp_2713_fu_36101_p3);
assign tmp_882_fu_36122_p2 = (ap_reg_ppstg_tmp_2223_reg_41869_pp0_iter1 | tmp_2714_fu_36114_p3);
assign tmp_883_fu_36135_p2 = (ap_reg_ppstg_tmp_2225_reg_41876_pp0_iter1 | tmp_2715_fu_36127_p3);
assign tmp_884_fu_36148_p2 = (ap_reg_ppstg_tmp_2227_reg_41883_pp0_iter1 | tmp_2716_fu_36140_p3);
assign tmp_885_fu_36177_p2 = (ap_reg_ppstg_tmp_2229_reg_41890_pp0_iter1 | tmp_2717_fu_36169_p3);
assign tmp_886_fu_36202_p2 = (ap_reg_ppstg_tmp_2231_reg_41897_pp0_iter1 | tmp_2718_fu_36198_p1);
assign tmp_887_fu_36215_p2 = (ap_reg_ppstg_tmp_1212_reg_40806_pp0_iter1 | tmp_2719_fu_36207_p3);
assign tmp_888_fu_36228_p2 = (ap_reg_ppstg_tmp_1216_reg_40813_pp0_iter1 | tmp_2720_fu_36220_p3);
assign tmp_889_fu_36432_p2 = (ap_reg_ppstg_tmp_2237_reg_41904_pp0_iter1 | tmp_2723_fu_36428_p1);
assign tmp_890_fu_36441_p2 = (ap_reg_ppstg_tmp_2239_reg_41911_pp0_iter1 | tmp_2724_fu_36437_p1);
assign tmp_891_fu_36454_p2 = (ap_reg_ppstg_tmp_2241_reg_41918_pp0_iter1 | tmp_2725_fu_36446_p3);
assign tmp_892_fu_36467_p2 = (ap_reg_ppstg_tmp_2243_reg_41925_pp0_iter1 | tmp_2726_fu_36459_p3);
assign tmp_893_fu_36480_p2 = (ap_reg_ppstg_tmp_2245_reg_41932_pp0_iter1 | tmp_2727_fu_36472_p3);
assign tmp_894_fu_36493_p2 = (ap_reg_ppstg_tmp_2247_reg_41939_pp0_iter1 | tmp_2728_fu_36485_p3);
assign tmp_895_fu_36506_p2 = (ap_reg_ppstg_tmp_2249_reg_41946_pp0_iter1 | tmp_2729_fu_36498_p3);
assign tmp_896_fu_36519_p2 = (ap_reg_ppstg_tmp_2251_reg_41953_pp0_iter1 | tmp_2730_fu_36511_p3);
assign tmp_897_fu_36532_p2 = (ap_reg_ppstg_tmp_2253_reg_41960_pp0_iter1 | tmp_2731_fu_36524_p3);
assign tmp_898_fu_36545_p2 = (ap_reg_ppstg_tmp_2255_reg_41967_pp0_iter1 | tmp_2732_fu_36537_p3);
assign tmp_899_fu_36558_p2 = (ap_reg_ppstg_tmp_2257_reg_41974_pp0_iter1 | tmp_2733_fu_36550_p3);
assign tmp_900_fu_36587_p2 = (ap_reg_ppstg_tmp_2259_reg_41981_pp0_iter1 | tmp_2734_fu_36579_p3);
assign tmp_901_fu_36612_p2 = (ap_reg_ppstg_tmp_2261_reg_41988_pp0_iter1 | tmp_2735_fu_36608_p1);
assign tmp_902_fu_36625_p2 = (ap_reg_ppstg_tmp_1239_reg_40848_pp0_iter1 | tmp_2736_fu_36617_p3);
assign tmp_903_fu_36638_p2 = (ap_reg_ppstg_tmp_1253_reg_40855_pp0_iter1 | tmp_2737_fu_36630_p3);
assign tmp_904_fu_38328_p2 = (tmp_2749_fu_38320_p3 | r_V_177_2_s_fu_36404_p3);
assign tmp_fu_2562_p1 = si_0_0_V_read[0:0];
assign tmp_s_fu_3016_p2 = ((rank_0_0_V_read != ap_const_lv7_0) ? 1'b1 : 1'b0);
assign winner_V1_fu_8658_p3 = ((tmp_333_fu_8608_p2[0:0] === 1'b1) ? winner_V_fu_8652_p2 : ap_const_lv36_0);
assign winner_V_10_fu_17891_p3 = ((ap_reg_ppstg_tmp_1402_10_reg_40983_pp0_iter1[0:0] === 1'b1) ? winner_V_21_fu_17885_p2 : winner_V_s_fu_17790_p3);
assign winner_V_11_fu_16870_p2 = (tmp_1627_fu_16855_p2 | tmp_1629_fu_16864_p2);
assign winner_V_12_fu_16970_p2 = (tmp_1654_fu_16954_p2 | tmp_1656_fu_16964_p2);
assign winner_V_13_fu_17071_p2 = (tmp_1681_fu_17055_p2 | tmp_1683_fu_17065_p2);
assign winner_V_14_fu_17172_p2 = (tmp_1708_fu_17156_p2 | tmp_1710_fu_17166_p2);
assign winner_V_15_fu_17273_p2 = (tmp_1735_fu_17257_p2 | tmp_1737_fu_17267_p2);
assign winner_V_16_fu_17374_p2 = (tmp_1762_fu_17358_p2 | tmp_1764_fu_17368_p2);
assign winner_V_17_fu_17475_p2 = (tmp_1789_fu_17459_p2 | tmp_1791_fu_17469_p2);
assign winner_V_18_fu_17583_p2 = (tmp_1816_fu_17568_p2 | tmp_1818_fu_17577_p2);
assign winner_V_19_fu_17683_p2 = (tmp_1843_fu_17667_p2 | tmp_1845_fu_17677_p2);
assign winner_V_1_fu_16876_p3 = ((tmp_1402_1_reg_40869[0:0] === 1'b1) ? winner_V_11_fu_16870_p2 : winner_V1_reg_40862);
assign winner_V_20_fu_17784_p2 = (tmp_1870_fu_17768_p2 | tmp_1872_fu_17778_p2);
assign winner_V_21_fu_17885_p2 = (tmp_1897_fu_17869_p2 | tmp_1899_fu_17879_p2);
assign winner_V_2_fu_16976_p3 = ((tmp_1402_2_reg_40884[0:0] === 1'b1) ? winner_V_12_fu_16970_p2 : winner_V_1_fu_16876_p3);
assign winner_V_3_fu_17077_p3 = ((tmp_1402_3_reg_40895[0:0] === 1'b1) ? winner_V_13_fu_17071_p2 : winner_V_2_fu_16976_p3);
assign winner_V_4_fu_17178_p3 = ((tmp_1402_4_reg_40906[0:0] === 1'b1) ? winner_V_14_fu_17172_p2 : winner_V_3_fu_17077_p3);
assign winner_V_5_fu_17279_p3 = ((tmp_1402_5_reg_40917[0:0] === 1'b1) ? winner_V_15_fu_17273_p2 : winner_V_4_fu_17178_p3);
assign winner_V_6_fu_17380_p3 = ((tmp_1402_6_reg_40928[0:0] === 1'b1) ? winner_V_16_fu_17374_p2 : winner_V_5_fu_17279_p3);
assign winner_V_7_fu_17481_p3 = ((tmp_1402_7_reg_40939[0:0] === 1'b1) ? winner_V_17_fu_17475_p2 : winner_V_6_fu_17380_p3);
assign winner_V_8_fu_17589_p3 = ((ap_reg_ppstg_tmp_1402_8_reg_40950_pp0_iter1[0:0] === 1'b1) ? winner_V_18_fu_17583_p2 : winner_V_7_reg_41995);
assign winner_V_9_fu_17689_p3 = ((ap_reg_ppstg_tmp_1402_9_reg_40961_pp0_iter1[0:0] === 1'b1) ? winner_V_19_fu_17683_p2 : winner_V_8_fu_17589_p3);
assign winner_V_fu_8652_p2 = ap_const_lv36_1 << tmp_1602_fu_8648_p1;
assign winner_V_s_fu_17790_p3 = ((ap_reg_ppstg_tmp_1402_s_reg_40972_pp0_iter1[0:0] === 1'b1) ? winner_V_20_fu_17784_p2 : winner_V_9_fu_17689_p3);
assign y0_V_10_fu_15282_p2 = (tmp986_fu_15276_p2 ^ tmp985_fu_15270_p2);
assign y0_V_1_fu_8792_p2 = (tmp170_fu_8786_p2 ^ tmp169_fu_8780_p2);
assign y0_V_2_fu_9468_p2 = (tmp203_fu_9462_p2 ^ tmp202_fu_9456_p2);
assign y0_V_3_fu_10114_p2 = (tmp236_fu_10108_p2 ^ tmp235_fu_10102_p2);
assign y0_V_4_fu_10760_p2 = (tmp599_fu_10754_p2 ^ tmp598_fu_10748_p2);
assign y0_V_5_fu_11406_p2 = (tmp632_fu_11400_p2 ^ tmp631_fu_11394_p2);
assign y0_V_6_fu_12052_p2 = (tmp665_fu_12046_p2 ^ tmp664_fu_12040_p2);
assign y0_V_7_fu_12698_p2 = (tmp700_fu_12692_p2 ^ tmp699_fu_12686_p2);
assign y0_V_8_fu_13344_p2 = (tmp893_fu_13338_p2 ^ tmp892_fu_13332_p2);
assign y0_V_9_fu_13990_p2 = (tmp924_fu_13984_p2 ^ tmp923_fu_13978_p2);
assign y0_V_fu_8098_p2 = (tmp137_fu_8092_p2 ^ tmp136_fu_8086_p2);
assign y0_V_s_fu_14636_p2 = (tmp955_fu_14630_p2 ^ tmp954_fu_14624_p2);
assign y0a_V_10_fu_15438_p2 = (tmp996_fu_15432_p2 ^ tmp995_fu_15426_p2);
assign y0a_V_1_fu_8948_p2 = (tmp180_fu_8942_p2 ^ tmp179_fu_8936_p2);
assign y0a_V_2_fu_9624_p2 = (tmp213_fu_9618_p2 ^ tmp212_fu_9612_p2);
assign y0a_V_3_fu_10270_p2 = (tmp246_fu_10264_p2 ^ tmp245_fu_10258_p2);
assign y0a_V_4_fu_10916_p2 = (tmp609_fu_10910_p2 ^ tmp608_fu_10904_p2);
assign y0a_V_5_fu_11562_p2 = (tmp642_fu_11556_p2 ^ tmp641_fu_11550_p2);
assign y0a_V_6_fu_12208_p2 = (tmp675_fu_12202_p2 ^ tmp674_fu_12196_p2);
assign y0a_V_7_fu_12854_p2 = (tmp710_fu_12848_p2 ^ tmp709_fu_12842_p2);
assign y0a_V_8_fu_13500_p2 = (tmp903_fu_13494_p2 ^ tmp902_fu_13488_p2);
assign y0a_V_9_fu_14146_p2 = (tmp934_fu_14140_p2 ^ tmp933_fu_14134_p2);
assign y0a_V_fu_8254_p2 = (tmp147_fu_8248_p2 ^ tmp146_fu_8242_p2);
assign y0a_V_s_fu_14792_p2 = (tmp965_fu_14786_p2 ^ tmp964_fu_14780_p2);
assign y0b_V_10_fu_15594_p2 = (tmp1006_fu_15588_p2 ^ tmp1005_fu_15582_p2);
assign y0b_V_1_fu_9104_p2 = (tmp190_fu_9098_p2 ^ tmp189_fu_9092_p2);
assign y0b_V_2_fu_9780_p2 = (tmp223_fu_9774_p2 ^ tmp222_fu_9768_p2);
assign y0b_V_3_fu_10426_p2 = (tmp256_fu_10420_p2 ^ tmp255_fu_10414_p2);
assign y0b_V_4_fu_11072_p2 = (tmp619_fu_11066_p2 ^ tmp618_fu_11060_p2);
assign y0b_V_5_fu_11718_p2 = (tmp652_fu_11712_p2 ^ tmp651_fu_11706_p2);
assign y0b_V_6_fu_12364_p2 = (tmp685_fu_12358_p2 ^ tmp684_fu_12352_p2);
assign y0b_V_7_fu_13010_p2 = (tmp720_fu_13004_p2 ^ tmp719_fu_12998_p2);
assign y0b_V_8_fu_13656_p2 = (tmp913_fu_13650_p2 ^ tmp912_fu_13644_p2);
assign y0b_V_9_fu_14302_p2 = (tmp944_fu_14296_p2 ^ tmp943_fu_14290_p2);
assign y0b_V_fu_8410_p2 = (tmp157_fu_8404_p2 ^ tmp156_fu_8398_p2);
assign y0b_V_s_fu_14948_p2 = (tmp975_fu_14942_p2 ^ tmp974_fu_14936_p2);
assign y1_V_10_fu_15402_p2 = (tmp993_fu_15396_p2 | tmp990_fu_15372_p2);
assign y1_V_1_fu_8912_p2 = (tmp177_fu_8906_p2 | tmp174_fu_8882_p2);
assign y1_V_2_fu_9588_p2 = (tmp210_fu_9582_p2 | tmp207_fu_9558_p2);
assign y1_V_3_fu_10234_p2 = (tmp243_fu_10228_p2 | tmp240_fu_10204_p2);
assign y1_V_4_fu_10880_p2 = (tmp606_fu_10874_p2 | tmp603_fu_10850_p2);
assign y1_V_5_fu_11526_p2 = (tmp639_fu_11520_p2 | tmp636_fu_11496_p2);
assign y1_V_6_fu_12172_p2 = (tmp672_fu_12166_p2 | tmp669_fu_12142_p2);
assign y1_V_7_fu_12818_p2 = (tmp707_fu_12812_p2 | tmp704_fu_12788_p2);
assign y1_V_8_fu_13464_p2 = (tmp900_fu_13458_p2 | tmp897_fu_13434_p2);
assign y1_V_9_fu_14110_p2 = (tmp931_fu_14104_p2 | tmp928_fu_14080_p2);
assign y1_V_fu_8218_p2 = (tmp144_fu_8212_p2 | tmp141_fu_8188_p2);
assign y1_V_s_fu_14756_p2 = (tmp962_fu_14750_p2 | tmp959_fu_14726_p2);
assign y1a_V_10_fu_15558_p2 = (tmp1003_fu_15552_p2 | tmp1000_fu_15528_p2);
assign y1a_V_1_fu_9068_p2 = (tmp187_fu_9062_p2 | tmp184_fu_9038_p2);
assign y1a_V_2_fu_9744_p2 = (tmp220_fu_9738_p2 | tmp217_fu_9714_p2);
assign y1a_V_3_fu_10390_p2 = (tmp253_fu_10384_p2 | tmp250_fu_10360_p2);
assign y1a_V_4_fu_11036_p2 = (tmp616_fu_11030_p2 | tmp613_fu_11006_p2);
assign y1a_V_5_fu_11682_p2 = (tmp649_fu_11676_p2 | tmp646_fu_11652_p2);
assign y1a_V_6_fu_12328_p2 = (tmp682_fu_12322_p2 | tmp679_fu_12298_p2);
assign y1a_V_7_fu_12974_p2 = (tmp717_fu_12968_p2 | tmp714_fu_12944_p2);
assign y1a_V_8_fu_13620_p2 = (tmp910_fu_13614_p2 | tmp907_fu_13590_p2);
assign y1a_V_9_fu_14266_p2 = (tmp941_fu_14260_p2 | tmp938_fu_14236_p2);
assign y1a_V_fu_8374_p2 = (tmp154_fu_8368_p2 | tmp151_fu_8344_p2);
assign y1a_V_s_fu_14912_p2 = (tmp972_fu_14906_p2 | tmp969_fu_14882_p2);
assign y1b_V_10_fu_15714_p2 = (tmp1013_fu_15708_p2 | tmp1010_fu_15684_p2);
assign y1b_V_1_fu_9224_p2 = (tmp197_fu_9218_p2 | tmp194_fu_9194_p2);
assign y1b_V_2_fu_9900_p2 = (tmp230_fu_9894_p2 | tmp227_fu_9870_p2);
assign y1b_V_3_fu_10546_p2 = (tmp263_fu_10540_p2 | tmp260_fu_10516_p2);
assign y1b_V_4_fu_11192_p2 = (tmp626_fu_11186_p2 | tmp623_fu_11162_p2);
assign y1b_V_5_fu_11838_p2 = (tmp659_fu_11832_p2 | tmp656_fu_11808_p2);
assign y1b_V_6_fu_12484_p2 = (tmp692_fu_12478_p2 | tmp689_fu_12454_p2);
assign y1b_V_7_fu_13130_p2 = (tmp727_fu_13124_p2 | tmp724_fu_13100_p2);
assign y1b_V_8_fu_13776_p2 = (tmp920_fu_13770_p2 | tmp917_fu_13746_p2);
assign y1b_V_9_fu_14422_p2 = (tmp951_fu_14416_p2 | tmp948_fu_14392_p2);
assign y1b_V_fu_8530_p2 = (tmp164_fu_8524_p2 | tmp161_fu_8500_p2);
assign y1b_V_s_fu_15068_p2 = (tmp982_fu_15062_p2 | tmp979_fu_15038_p2);
assign y2_V_10_fu_15420_p2 = (p_demorgan229722982301_i_10_fu_15414_p2 ^ 1'b1);
assign y2_V_1_fu_8930_p2 = (p_demorgan229722982301_i_1_fu_8924_p2 ^ 1'b1);
assign y2_V_2_fu_9606_p2 = (p_demorgan229722982301_i_2_fu_9600_p2 ^ 1'b1);
assign y2_V_3_fu_10252_p2 = (p_demorgan229722982301_i_3_fu_10246_p2 ^ 1'b1);
assign y2_V_4_fu_10898_p2 = (p_demorgan229722982301_i_4_fu_10892_p2 ^ 1'b1);
assign y2_V_5_fu_11544_p2 = (p_demorgan229722982301_i_5_fu_11538_p2 ^ 1'b1);
assign y2_V_6_fu_12190_p2 = (p_demorgan229722982301_i_6_fu_12184_p2 ^ 1'b1);
assign y2_V_7_fu_12836_p2 = (p_demorgan229722982301_i_7_fu_12830_p2 ^ 1'b1);
assign y2_V_8_fu_13482_p2 = (p_demorgan229722982301_i_8_fu_13476_p2 ^ 1'b1);
assign y2_V_9_fu_14128_p2 = (p_demorgan229722982301_i_9_fu_14122_p2 ^ 1'b1);
assign y2_V_fu_8236_p2 = (p_demorgan229722982301_i_fu_8230_p2 ^ 1'b1);
assign y2_V_s_fu_14774_p2 = (p_demorgan229722982301_i_s_fu_14768_p2 ^ 1'b1);
assign y2a_V_10_fu_15576_p2 = (p_demorgan230523062309_i_10_fu_15570_p2 ^ 1'b1);
assign y2a_V_1_fu_9086_p2 = (p_demorgan230523062309_i_1_fu_9080_p2 ^ 1'b1);
assign y2a_V_2_fu_9762_p2 = (p_demorgan230523062309_i_2_fu_9756_p2 ^ 1'b1);
assign y2a_V_3_fu_10408_p2 = (p_demorgan230523062309_i_3_fu_10402_p2 ^ 1'b1);
assign y2a_V_4_fu_11054_p2 = (p_demorgan230523062309_i_4_fu_11048_p2 ^ 1'b1);
assign y2a_V_5_fu_11700_p2 = (p_demorgan230523062309_i_5_fu_11694_p2 ^ 1'b1);
assign y2a_V_6_fu_12346_p2 = (p_demorgan230523062309_i_6_fu_12340_p2 ^ 1'b1);
assign y2a_V_7_fu_12992_p2 = (p_demorgan230523062309_i_7_fu_12986_p2 ^ 1'b1);
assign y2a_V_8_fu_13638_p2 = (p_demorgan230523062309_i_8_fu_13632_p2 ^ 1'b1);
assign y2a_V_9_fu_14284_p2 = (p_demorgan230523062309_i_9_fu_14278_p2 ^ 1'b1);
assign y2a_V_fu_8392_p2 = (p_demorgan230523062309_i_fu_8386_p2 ^ 1'b1);
assign y2a_V_s_fu_14930_p2 = (p_demorgan230523062309_i_s_fu_14924_p2 ^ 1'b1);
assign y2b_V_10_fu_15732_p2 = (p_demorgan231323142317_i_10_fu_15726_p2 ^ 1'b1);
assign y2b_V_1_fu_9242_p2 = (p_demorgan231323142317_i_1_fu_9236_p2 ^ 1'b1);
assign y2b_V_2_fu_9918_p2 = (p_demorgan231323142317_i_2_fu_9912_p2 ^ 1'b1);
assign y2b_V_3_fu_10564_p2 = (p_demorgan231323142317_i_3_fu_10558_p2 ^ 1'b1);
assign y2b_V_4_fu_11210_p2 = (p_demorgan231323142317_i_4_fu_11204_p2 ^ 1'b1);
assign y2b_V_5_fu_11856_p2 = (p_demorgan231323142317_i_5_fu_11850_p2 ^ 1'b1);
assign y2b_V_6_fu_12502_p2 = (p_demorgan231323142317_i_6_fu_12496_p2 ^ 1'b1);
assign y2b_V_7_fu_13148_p2 = (p_demorgan231323142317_i_7_fu_13142_p2 ^ 1'b1);
assign y2b_V_8_fu_13794_p2 = (p_demorgan231323142317_i_8_fu_13788_p2 ^ 1'b1);
assign y2b_V_9_fu_14440_p2 = (p_demorgan231323142317_i_9_fu_14434_p2 ^ 1'b1);
assign y2b_V_fu_8548_p2 = (p_demorgan231323142317_i_fu_8542_p2 ^ 1'b1);
assign y2b_V_s_fu_15086_p2 = (p_demorgan231323142317_i_s_fu_15080_p2 ^ 1'b1);
always @ (posedge ap_clk) begin
tmp_335_reg_40874[1:0] <= 2'b00;
tmp_1623_reg_40879[1:0] <= 2'b00;
end
endmodule //sp_best_tracks_actual
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOBUFSRC_4_V
`define SKY130_FD_SC_LP__ISOBUFSRC_4_V
/**
* isobufsrc: Input isolation, noninverted sleep.
*
* X = (!A | SLEEP)
*
* Verilog wrapper for isobufsrc with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__isobufsrc.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__isobufsrc_4 (
X ,
SLEEP,
A ,
VPWR ,
VGND ,
VPB ,
VNB
);
output X ;
input SLEEP;
input A ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__isobufsrc_4 (
X ,
SLEEP,
A
);
output X ;
input SLEEP;
input A ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__isobufsrc base (
.X(X),
.SLEEP(SLEEP),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOBUFSRC_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311O_4_V
`define SKY130_FD_SC_LP__A311O_4_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311O_4_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ROM_4K.v when simulating
// the core, ROM_4K. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ROM_4K(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [11 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(1),
.C_DISABLE_WARN_BHV_RANGE(1),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("ROM_4K.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_TX_FIFO.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Jacob Gorban, [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_wb.v,v $
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban ([email protected])
// Company: Flextronics Semiconductor
//
`include "timescale.v"
module uart_wb (clk,
wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
wb_ack_o <= #1 1'b0;
end
else
begin
// wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers
wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
end
end
assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:31 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_sim_netlist.v
// Design : system_auto_cc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_auto_cc_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [0:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [27:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [127:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [15:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [0:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [0:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [27:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [0:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [127:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *) input m_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *) input m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [0:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [27:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [127:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [15:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [0:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [0:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [27:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [0:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [127:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire m_axi_aclk;
wire [27:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire m_axi_aresetn;
wire [0:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [27:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [0:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [15:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_axi_aclk;
wire [27:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [27:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [127:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [127:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [15:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_ARADDR_RIGHT = "29" *)
(* C_ARADDR_WIDTH = "28" *)
(* C_ARBURST_RIGHT = "16" *)
(* C_ARBURST_WIDTH = "2" *)
(* C_ARCACHE_RIGHT = "11" *)
(* C_ARCACHE_WIDTH = "4" *)
(* C_ARID_RIGHT = "57" *)
(* C_ARID_WIDTH = "1" *)
(* C_ARLEN_RIGHT = "21" *)
(* C_ARLEN_WIDTH = "8" *)
(* C_ARLOCK_RIGHT = "15" *)
(* C_ARLOCK_WIDTH = "1" *)
(* C_ARPROT_RIGHT = "8" *)
(* C_ARPROT_WIDTH = "3" *)
(* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "4" *)
(* C_ARREGION_RIGHT = "4" *)
(* C_ARREGION_WIDTH = "4" *)
(* C_ARSIZE_RIGHT = "18" *)
(* C_ARSIZE_WIDTH = "3" *)
(* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *)
(* C_AR_WIDTH = "58" *)
(* C_AWADDR_RIGHT = "29" *)
(* C_AWADDR_WIDTH = "28" *)
(* C_AWBURST_RIGHT = "16" *)
(* C_AWBURST_WIDTH = "2" *)
(* C_AWCACHE_RIGHT = "11" *)
(* C_AWCACHE_WIDTH = "4" *)
(* C_AWID_RIGHT = "57" *)
(* C_AWID_WIDTH = "1" *)
(* C_AWLEN_RIGHT = "21" *)
(* C_AWLEN_WIDTH = "8" *)
(* C_AWLOCK_RIGHT = "15" *)
(* C_AWLOCK_WIDTH = "1" *)
(* C_AWPROT_RIGHT = "8" *)
(* C_AWPROT_WIDTH = "3" *)
(* C_AWQOS_RIGHT = "0" *)
(* C_AWQOS_WIDTH = "4" *)
(* C_AWREGION_RIGHT = "4" *)
(* C_AWREGION_WIDTH = "4" *)
(* C_AWSIZE_RIGHT = "18" *)
(* C_AWSIZE_WIDTH = "3" *)
(* C_AWUSER_RIGHT = "0" *)
(* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "58" *)
(* C_AXI_ADDR_WIDTH = "28" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "128" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_IS_ACLK_ASYNC = "1" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "1" *)
(* C_BRESP_RIGHT = "0" *)
(* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *)
(* C_BUSER_WIDTH = "0" *)
(* C_B_WIDTH = "3" *)
(* C_FAMILY = "artix7" *)
(* C_FIFO_AR_WIDTH = "58" *)
(* C_FIFO_AW_WIDTH = "58" *)
(* C_FIFO_B_WIDTH = "3" *)
(* C_FIFO_R_WIDTH = "132" *)
(* C_FIFO_W_WIDTH = "145" *)
(* C_M_AXI_ACLK_RATIO = "2" *)
(* C_RDATA_RIGHT = "3" *)
(* C_RDATA_WIDTH = "128" *)
(* C_RID_RIGHT = "131" *)
(* C_RID_WIDTH = "1" *)
(* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "1" *)
(* C_RRESP_RIGHT = "1" *)
(* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *)
(* C_RUSER_WIDTH = "0" *)
(* C_R_WIDTH = "132" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_S_AXI_ACLK_RATIO = "1" *)
(* C_WDATA_RIGHT = "17" *)
(* C_WDATA_WIDTH = "128" *)
(* C_WID_RIGHT = "145" *)
(* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *)
(* C_WLAST_WIDTH = "1" *)
(* C_WSTRB_RIGHT = "1" *)
(* C_WSTRB_WIDTH = "16" *)
(* C_WUSER_RIGHT = "0" *)
(* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "145" *)
(* P_ACLK_RATIO = "2" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_FULLY_REG = "1" *)
(* P_LIGHT_WT = "0" *)
(* P_LUTRAM_ASYNC = "12" *)
(* P_ROUNDING_OFFSET = "0" *)
(* P_SI_LT_MI = "1'b1" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter inst
(.m_axi_aclk(m_axi_aclk),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_ARADDR_RIGHT = "29" *) (* C_ARADDR_WIDTH = "28" *) (* C_ARBURST_RIGHT = "16" *)
(* C_ARBURST_WIDTH = "2" *) (* C_ARCACHE_RIGHT = "11" *) (* C_ARCACHE_WIDTH = "4" *)
(* C_ARID_RIGHT = "57" *) (* C_ARID_WIDTH = "1" *) (* C_ARLEN_RIGHT = "21" *)
(* C_ARLEN_WIDTH = "8" *) (* C_ARLOCK_RIGHT = "15" *) (* C_ARLOCK_WIDTH = "1" *)
(* C_ARPROT_RIGHT = "8" *) (* C_ARPROT_WIDTH = "3" *) (* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "4" *) (* C_ARREGION_RIGHT = "4" *) (* C_ARREGION_WIDTH = "4" *)
(* C_ARSIZE_RIGHT = "18" *) (* C_ARSIZE_WIDTH = "3" *) (* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *) (* C_AR_WIDTH = "58" *) (* C_AWADDR_RIGHT = "29" *)
(* C_AWADDR_WIDTH = "28" *) (* C_AWBURST_RIGHT = "16" *) (* C_AWBURST_WIDTH = "2" *)
(* C_AWCACHE_RIGHT = "11" *) (* C_AWCACHE_WIDTH = "4" *) (* C_AWID_RIGHT = "57" *)
(* C_AWID_WIDTH = "1" *) (* C_AWLEN_RIGHT = "21" *) (* C_AWLEN_WIDTH = "8" *)
(* C_AWLOCK_RIGHT = "15" *) (* C_AWLOCK_WIDTH = "1" *) (* C_AWPROT_RIGHT = "8" *)
(* C_AWPROT_WIDTH = "3" *) (* C_AWQOS_RIGHT = "0" *) (* C_AWQOS_WIDTH = "4" *)
(* C_AWREGION_RIGHT = "4" *) (* C_AWREGION_WIDTH = "4" *) (* C_AWSIZE_RIGHT = "18" *)
(* C_AWSIZE_WIDTH = "3" *) (* C_AWUSER_RIGHT = "0" *) (* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "58" *) (* C_AXI_ADDR_WIDTH = "28" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "128" *)
(* C_AXI_ID_WIDTH = "1" *) (* C_AXI_IS_ACLK_ASYNC = "1" *) (* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "1" *) (* C_BRESP_RIGHT = "0" *) (* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *) (* C_BUSER_WIDTH = "0" *) (* C_B_WIDTH = "3" *)
(* C_FAMILY = "artix7" *) (* C_FIFO_AR_WIDTH = "58" *) (* C_FIFO_AW_WIDTH = "58" *)
(* C_FIFO_B_WIDTH = "3" *) (* C_FIFO_R_WIDTH = "132" *) (* C_FIFO_W_WIDTH = "145" *)
(* C_M_AXI_ACLK_RATIO = "2" *) (* C_RDATA_RIGHT = "3" *) (* C_RDATA_WIDTH = "128" *)
(* C_RID_RIGHT = "131" *) (* C_RID_WIDTH = "1" *) (* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "1" *) (* C_RRESP_RIGHT = "1" *) (* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *) (* C_RUSER_WIDTH = "0" *) (* C_R_WIDTH = "132" *)
(* C_SYNCHRONIZER_STAGE = "3" *) (* C_S_AXI_ACLK_RATIO = "1" *) (* C_WDATA_RIGHT = "17" *)
(* C_WDATA_WIDTH = "128" *) (* C_WID_RIGHT = "145" *) (* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *) (* C_WLAST_WIDTH = "1" *) (* C_WSTRB_RIGHT = "1" *)
(* C_WSTRB_WIDTH = "16" *) (* C_WUSER_RIGHT = "0" *) (* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "145" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_axi_clock_converter" *)
(* P_ACLK_RATIO = "2" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *)
(* P_AXILITE = "2" *) (* P_FULLY_REG = "1" *) (* P_LIGHT_WT = "0" *)
(* P_LUTRAM_ASYNC = "12" *) (* P_ROUNDING_OFFSET = "0" *) (* P_SI_LT_MI = "1'b1" *)
module system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
(* keep = "true" *) input s_axi_aclk;
(* keep = "true" *) input s_axi_aresetn;
input [0:0]s_axi_awid;
input [27:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [127:0]s_axi_wdata;
input [15:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [27:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [127:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
(* keep = "true" *) input m_axi_aclk;
(* keep = "true" *) input m_axi_aresetn;
output [0:0]m_axi_awid;
output [27:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [27:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire async_conv_reset_n;
(* RTL_KEEP = "true" *) wire m_axi_aclk;
wire [27:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
(* RTL_KEEP = "true" *) wire m_axi_aresetn;
wire [0:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [27:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [0:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [15:0]m_axi_wstrb;
wire m_axi_wvalid;
(* RTL_KEEP = "true" *) wire s_axi_aclk;
wire [27:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
(* RTL_KEEP = "true" *) wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [27:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [127:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [127:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [15:0]s_axi_wstrb;
wire s_axi_wvalid;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED ;
wire [17:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED ;
wire [7:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED ;
wire [3:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "28" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "128" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "18" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "58" *)
(* C_DIN_WIDTH_RDCH = "132" *)
(* C_DIN_WIDTH_WACH = "58" *)
(* C_DIN_WIDTH_WDCH = "145" *)
(* C_DIN_WIDTH_WRCH = "3" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "18" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "1" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "11" *)
(* C_IMPLEMENTATION_TYPE_RACH = "12" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WACH = "12" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "12" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "2" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx4" *)
(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1021" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "13" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "16" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "16" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "4" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "4" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
system_auto_cc_0_fifo_generator_v13_1_3 \gen_clock_conv.gen_async_conv.asyncfifo_axi
(.almost_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED ),
.almost_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED ),
.axi_ar_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED [4:0]),
.axi_ar_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED ),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED ),
.axi_ar_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED ),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED ),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED [4:0]),
.axi_ar_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED ),
.axi_ar_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED ),
.axi_ar_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED [4:0]),
.axi_aw_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED [4:0]),
.axi_aw_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED ),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED ),
.axi_aw_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED ),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED ),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED [4:0]),
.axi_aw_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED ),
.axi_aw_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED ),
.axi_aw_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED [4:0]),
.axi_b_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED [4:0]),
.axi_b_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED ),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED ),
.axi_b_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED ),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED ),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED [4:0]),
.axi_b_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED ),
.axi_b_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED ),
.axi_b_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED [4:0]),
.axi_r_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED [4:0]),
.axi_r_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED ),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED ),
.axi_r_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED ),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED ),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED [4:0]),
.axi_r_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED ),
.axi_r_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED ),
.axi_r_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED [4:0]),
.axi_w_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED [4:0]),
.axi_w_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED ),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED ),
.axi_w_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED ),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED ),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED [4:0]),
.axi_w_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED ),
.axi_w_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED ),
.axi_w_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED [4:0]),
.axis_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED [10:0]),
.axis_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED ),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED ),
.axis_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED ),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED ),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED [10:0]),
.axis_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED ),
.axis_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED ),
.axis_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED [10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED [9:0]),
.dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED ),
.din({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dout(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED [17:0]),
.empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED ),
.full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED ),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(m_axi_aclk),
.m_aclk_en(1'b1),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED [0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED [0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED [0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED [0]),
.m_axi_wvalid(m_axi_wvalid),
.m_axis_tdata(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED [7:0]),
.m_axis_tdest(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED [0]),
.m_axis_tid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED [0]),
.m_axis_tkeep(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED [0]),
.m_axis_tlast(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED ),
.m_axis_tready(1'b0),
.m_axis_tstrb(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED [0]),
.m_axis_tuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED [3:0]),
.m_axis_tvalid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED ),
.overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED ),
.prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED ),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED ),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED [9:0]),
.rd_en(1'b0),
.rd_rst(1'b0),
.rd_rst_busy(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED ),
.rst(1'b0),
.s_aclk(s_axi_aclk),
.s_aclk_en(1'b1),
.s_aresetn(async_conv_reset_n),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED [0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED [0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED ),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED ),
.sleep(1'b0),
.srst(1'b0),
.underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED ),
.valid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED ),
.wr_ack(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED ),
.wr_clk(1'b0),
.wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED [9:0]),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED ));
LUT2 #(
.INIT(4'h8))
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1
(.I0(s_axi_aresetn),
.I1(m_axi_aresetn),
.O(async_conv_reset_n));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs
(out,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_full_fb_i_reg_1,
Q,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
m_aclk,
AR,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
output ram_empty_i_reg;
output [3:0]ram_empty_i_reg_0;
input ram_full_fb_i_reg_1;
input [3:0]Q;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [2:0]\gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input m_aclk;
input [0:0]AR;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire [3:0]ram_empty_i_reg_0;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2_n_0;
wire ram_full_i_i_4_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized5 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.m_aclk(m_aclk),
.out(p_8_out));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(ram_empty_i_reg_0[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(ram_empty_i_reg_0[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(ram_empty_i_reg_0[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(ram_empty_i_reg_0[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__2
(.I0(ram_empty_i_reg_0[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(ram_empty_i_reg_0[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(ram_empty_i_reg_0[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1
(.I0(ram_full_i_i_2_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(Q[3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4
(.I0(p_23_out[2]),
.I1(Q[2]),
.I2(p_23_out[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_27
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
D,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
\gc0.count_d1_reg[2] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [0:0]D;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]\gc0.count_d1_reg[2] ;
wire [0:0]AR;
wire [0:0]D;
wire [3:0]Q;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [2:0]\gc0.count_d1_reg[2] ;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire [1:1]gray2bin;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire p_0_out;
wire [2:0]p_23_out_1;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__1_n_0;
wire ram_full_i_i_4__1_n_0;
wire [3:0]rd_pntr_gc;
wire s_aclk;
wire [3:0]wr_pntr_gc;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(gray2bin));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_42 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized1_43 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_44 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized3_45 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_46 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(p_0_out),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
system_auto_cc_0_synchronizer_ff__parameterized5_47 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out_1[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out_1[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out_1[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [0]),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [1]),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [2]),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(wr_pntr_gc[3]));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__1
(.I0(ram_full_i_i_2__1_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__1_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__1
(.I0(p_23_out_1[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out_1[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out_1[0]),
.O(ram_full_i_i_2__1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__1
(.I0(p_23_out_1[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out_1[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out_1[0]),
.O(ram_full_i_i_4__1_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_48
(out,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_full_fb_i_reg_1,
Q,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
m_aclk,
AR,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
output ram_empty_i_reg;
output [3:0]ram_empty_i_reg_0;
input ram_full_fb_i_reg_1;
input [3:0]Q;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [2:0]\gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input m_aclk;
input [0:0]AR;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire [3:0]ram_empty_i_reg_0;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__0_n_0;
wire ram_full_i_i_4__0_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_63 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized1_64 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_65 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized3_66 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_67 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized5_68 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.m_aclk(m_aclk),
.out(p_8_out));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(ram_empty_i_reg_0[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(ram_empty_i_reg_0[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(ram_empty_i_reg_0[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(ram_empty_i_reg_0[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__3
(.I0(ram_empty_i_reg_0[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(ram_empty_i_reg_0[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(ram_empty_i_reg_0[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__0
(.I0(ram_full_i_i_2__0_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(Q[3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__0_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__0
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__0
(.I0(p_23_out[2]),
.I1(Q[2]),
.I2(p_23_out[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__0_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_6
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__2_n_0;
wire ram_full_i_i_4__2_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_21 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized1_22 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_23 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized3_24 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_25 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
system_auto_cc_0_synchronizer_ff__parameterized5_26 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__0
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__2
(.I0(ram_full_i_i_2__2_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__2_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__2_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_70
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__3_n_0;
wire ram_full_i_i_4__3_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_87 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized1_88 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_89 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized3_90 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_91 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
system_auto_cc_0_synchronizer_ff__parameterized5_92 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__1
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__3
(.I0(ram_full_i_i_2__3_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__3_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__3
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__3
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__3_n_0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem
(dout_i,
s_aclk,
ram_full_fb_i_reg,
DI,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [57:0]dout_i;
input s_aclk;
input [0:0]ram_full_fb_i_reg;
input [57:0]DI;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [57:0]DI;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_57_n_0;
wire RAM_reg_0_15_54_57_n_1;
wire RAM_reg_0_15_54_57_n_2;
wire RAM_reg_0_15_54_57_n_3;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [57:0]dout_i;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]ram_full_fb_i_reg;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[1:0]),
.DIB(DI[3:2]),
.DIC(DI[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[13:12]),
.DIB(DI[15:14]),
.DIC(DI[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[19:18]),
.DIB(DI[21:20]),
.DIC(DI[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[25:24]),
.DIB(DI[27:26]),
.DIC(DI[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[31:30]),
.DIB(DI[33:32]),
.DIC(DI[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[37:36]),
.DIB(DI[39:38]),
.DIC(DI[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[43:42]),
.DIB(DI[45:44]),
.DIC(DI[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[49:48]),
.DIB(DI[51:50]),
.DIC(DI[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_57
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[55:54]),
.DIB(DI[57:56]),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_57_n_0,RAM_reg_0_15_54_57_n_1}),
.DOB({RAM_reg_0_15_54_57_n_2,RAM_reg_0_15_54_57_n_3}),
.DOC(NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[7:6]),
.DIB(DI[9:8]),
.DIC(DI[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(dout_i[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(dout_i[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(dout_i[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(dout_i[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(dout_i[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(dout_i[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(dout_i[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(dout_i[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(dout_i[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(dout_i[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(dout_i[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(dout_i[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(dout_i[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(dout_i[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(dout_i[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(dout_i[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(dout_i[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(dout_i[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(dout_i[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(dout_i[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(dout_i[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(dout_i[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(dout_i[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(dout_i[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(dout_i[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(dout_i[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(dout_i[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(dout_i[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(dout_i[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(dout_i[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(dout_i[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(dout_i[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(dout_i[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(dout_i[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(dout_i[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(dout_i[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(dout_i[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(dout_i[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(dout_i[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(dout_i[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(dout_i[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(dout_i[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(dout_i[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(dout_i[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(dout_i[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(dout_i[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(dout_i[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(dout_i[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(dout_i[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_1),
.Q(dout_i[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_0),
.Q(dout_i[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_3),
.Q(dout_i[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_2),
.Q(dout_i[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(dout_i[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(dout_i[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(dout_i[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(dout_i[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(dout_i[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem_81
(Q,
s_aclk,
E,
I123,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [57:0]Q;
input s_aclk;
input [0:0]E;
input [57:0]I123;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [0:0]E;
wire [57:0]I123;
wire [57:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_57_n_0;
wire RAM_reg_0_15_54_57_n_1;
wire RAM_reg_0_15_54_57_n_2;
wire RAM_reg_0_15_54_57_n_3;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[1:0]),
.DIB(I123[3:2]),
.DIC(I123[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[13:12]),
.DIB(I123[15:14]),
.DIC(I123[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[19:18]),
.DIB(I123[21:20]),
.DIC(I123[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[25:24]),
.DIB(I123[27:26]),
.DIC(I123[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[31:30]),
.DIB(I123[33:32]),
.DIC(I123[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[37:36]),
.DIB(I123[39:38]),
.DIC(I123[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[43:42]),
.DIB(I123[45:44]),
.DIC(I123[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[49:48]),
.DIB(I123[51:50]),
.DIC(I123[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_57
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[55:54]),
.DIB(I123[57:56]),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_57_n_0,RAM_reg_0_15_54_57_n_1}),
.DOB({RAM_reg_0_15_54_57_n_2,RAM_reg_0_15_54_57_n_3}),
.DOC(NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[7:6]),
.DIB(I123[9:8]),
.DIC(I123[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_1),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_0),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_3),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_2),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem__parameterized0
(Q,
s_aclk,
E,
I115,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [144:0]Q;
input s_aclk;
input [0:0]E;
input [144:0]I115;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [0:0]E;
wire [144:0]I115;
wire [144:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_102_107_n_0;
wire RAM_reg_0_15_102_107_n_1;
wire RAM_reg_0_15_102_107_n_2;
wire RAM_reg_0_15_102_107_n_3;
wire RAM_reg_0_15_102_107_n_4;
wire RAM_reg_0_15_102_107_n_5;
wire RAM_reg_0_15_108_113_n_0;
wire RAM_reg_0_15_108_113_n_1;
wire RAM_reg_0_15_108_113_n_2;
wire RAM_reg_0_15_108_113_n_3;
wire RAM_reg_0_15_108_113_n_4;
wire RAM_reg_0_15_108_113_n_5;
wire RAM_reg_0_15_114_119_n_0;
wire RAM_reg_0_15_114_119_n_1;
wire RAM_reg_0_15_114_119_n_2;
wire RAM_reg_0_15_114_119_n_3;
wire RAM_reg_0_15_114_119_n_4;
wire RAM_reg_0_15_114_119_n_5;
wire RAM_reg_0_15_120_125_n_0;
wire RAM_reg_0_15_120_125_n_1;
wire RAM_reg_0_15_120_125_n_2;
wire RAM_reg_0_15_120_125_n_3;
wire RAM_reg_0_15_120_125_n_4;
wire RAM_reg_0_15_120_125_n_5;
wire RAM_reg_0_15_126_131_n_0;
wire RAM_reg_0_15_126_131_n_1;
wire RAM_reg_0_15_126_131_n_2;
wire RAM_reg_0_15_126_131_n_3;
wire RAM_reg_0_15_126_131_n_4;
wire RAM_reg_0_15_126_131_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_132_137_n_0;
wire RAM_reg_0_15_132_137_n_1;
wire RAM_reg_0_15_132_137_n_2;
wire RAM_reg_0_15_132_137_n_3;
wire RAM_reg_0_15_132_137_n_4;
wire RAM_reg_0_15_132_137_n_5;
wire RAM_reg_0_15_138_143_n_0;
wire RAM_reg_0_15_138_143_n_1;
wire RAM_reg_0_15_138_143_n_2;
wire RAM_reg_0_15_138_143_n_3;
wire RAM_reg_0_15_138_143_n_4;
wire RAM_reg_0_15_138_143_n_5;
wire RAM_reg_0_15_144_144_n_1;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_59_n_0;
wire RAM_reg_0_15_54_59_n_1;
wire RAM_reg_0_15_54_59_n_2;
wire RAM_reg_0_15_54_59_n_3;
wire RAM_reg_0_15_54_59_n_4;
wire RAM_reg_0_15_54_59_n_5;
wire RAM_reg_0_15_60_65_n_0;
wire RAM_reg_0_15_60_65_n_1;
wire RAM_reg_0_15_60_65_n_2;
wire RAM_reg_0_15_60_65_n_3;
wire RAM_reg_0_15_60_65_n_4;
wire RAM_reg_0_15_60_65_n_5;
wire RAM_reg_0_15_66_71_n_0;
wire RAM_reg_0_15_66_71_n_1;
wire RAM_reg_0_15_66_71_n_2;
wire RAM_reg_0_15_66_71_n_3;
wire RAM_reg_0_15_66_71_n_4;
wire RAM_reg_0_15_66_71_n_5;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire RAM_reg_0_15_72_77_n_0;
wire RAM_reg_0_15_72_77_n_1;
wire RAM_reg_0_15_72_77_n_2;
wire RAM_reg_0_15_72_77_n_3;
wire RAM_reg_0_15_72_77_n_4;
wire RAM_reg_0_15_72_77_n_5;
wire RAM_reg_0_15_78_83_n_0;
wire RAM_reg_0_15_78_83_n_1;
wire RAM_reg_0_15_78_83_n_2;
wire RAM_reg_0_15_78_83_n_3;
wire RAM_reg_0_15_78_83_n_4;
wire RAM_reg_0_15_78_83_n_5;
wire RAM_reg_0_15_84_89_n_0;
wire RAM_reg_0_15_84_89_n_1;
wire RAM_reg_0_15_84_89_n_2;
wire RAM_reg_0_15_84_89_n_3;
wire RAM_reg_0_15_84_89_n_4;
wire RAM_reg_0_15_84_89_n_5;
wire RAM_reg_0_15_90_95_n_0;
wire RAM_reg_0_15_90_95_n_1;
wire RAM_reg_0_15_90_95_n_2;
wire RAM_reg_0_15_90_95_n_3;
wire RAM_reg_0_15_90_95_n_4;
wire RAM_reg_0_15_90_95_n_5;
wire RAM_reg_0_15_96_101_n_0;
wire RAM_reg_0_15_96_101_n_1;
wire RAM_reg_0_15_96_101_n_2;
wire RAM_reg_0_15_96_101_n_3;
wire RAM_reg_0_15_96_101_n_4;
wire RAM_reg_0_15_96_101_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED;
wire [1:1]NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[1:0]),
.DIB(I115[3:2]),
.DIC(I115[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_102_107
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[103:102]),
.DIB(I115[105:104]),
.DIC(I115[107:106]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_102_107_n_0,RAM_reg_0_15_102_107_n_1}),
.DOB({RAM_reg_0_15_102_107_n_2,RAM_reg_0_15_102_107_n_3}),
.DOC({RAM_reg_0_15_102_107_n_4,RAM_reg_0_15_102_107_n_5}),
.DOD(NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_108_113
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[109:108]),
.DIB(I115[111:110]),
.DIC(I115[113:112]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_108_113_n_0,RAM_reg_0_15_108_113_n_1}),
.DOB({RAM_reg_0_15_108_113_n_2,RAM_reg_0_15_108_113_n_3}),
.DOC({RAM_reg_0_15_108_113_n_4,RAM_reg_0_15_108_113_n_5}),
.DOD(NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_114_119
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[115:114]),
.DIB(I115[117:116]),
.DIC(I115[119:118]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_114_119_n_0,RAM_reg_0_15_114_119_n_1}),
.DOB({RAM_reg_0_15_114_119_n_2,RAM_reg_0_15_114_119_n_3}),
.DOC({RAM_reg_0_15_114_119_n_4,RAM_reg_0_15_114_119_n_5}),
.DOD(NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_120_125
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[121:120]),
.DIB(I115[123:122]),
.DIC(I115[125:124]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_120_125_n_0,RAM_reg_0_15_120_125_n_1}),
.DOB({RAM_reg_0_15_120_125_n_2,RAM_reg_0_15_120_125_n_3}),
.DOC({RAM_reg_0_15_120_125_n_4,RAM_reg_0_15_120_125_n_5}),
.DOD(NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_126_131
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[127:126]),
.DIB(I115[129:128]),
.DIC(I115[131:130]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_126_131_n_0,RAM_reg_0_15_126_131_n_1}),
.DOB({RAM_reg_0_15_126_131_n_2,RAM_reg_0_15_126_131_n_3}),
.DOC({RAM_reg_0_15_126_131_n_4,RAM_reg_0_15_126_131_n_5}),
.DOD(NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[13:12]),
.DIB(I115[15:14]),
.DIC(I115[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_132_137
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[133:132]),
.DIB(I115[135:134]),
.DIC(I115[137:136]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_132_137_n_0,RAM_reg_0_15_132_137_n_1}),
.DOB({RAM_reg_0_15_132_137_n_2,RAM_reg_0_15_132_137_n_3}),
.DOC({RAM_reg_0_15_132_137_n_4,RAM_reg_0_15_132_137_n_5}),
.DOD(NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_138_143
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[139:138]),
.DIB(I115[141:140]),
.DIC(I115[143:142]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_138_143_n_0,RAM_reg_0_15_138_143_n_1}),
.DOB({RAM_reg_0_15_138_143_n_2,RAM_reg_0_15_138_143_n_3}),
.DOC({RAM_reg_0_15_138_143_n_4,RAM_reg_0_15_138_143_n_5}),
.DOD(NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_144_144
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA({1'b0,I115[144]}),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED[1],RAM_reg_0_15_144_144_n_1}),
.DOB(NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED[1:0]),
.DOC(NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[19:18]),
.DIB(I115[21:20]),
.DIC(I115[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[25:24]),
.DIB(I115[27:26]),
.DIC(I115[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[31:30]),
.DIB(I115[33:32]),
.DIC(I115[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[37:36]),
.DIB(I115[39:38]),
.DIC(I115[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[43:42]),
.DIB(I115[45:44]),
.DIC(I115[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[49:48]),
.DIB(I115[51:50]),
.DIC(I115[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_59
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[55:54]),
.DIB(I115[57:56]),
.DIC(I115[59:58]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_59_n_0,RAM_reg_0_15_54_59_n_1}),
.DOB({RAM_reg_0_15_54_59_n_2,RAM_reg_0_15_54_59_n_3}),
.DOC({RAM_reg_0_15_54_59_n_4,RAM_reg_0_15_54_59_n_5}),
.DOD(NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_60_65
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[61:60]),
.DIB(I115[63:62]),
.DIC(I115[65:64]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_60_65_n_0,RAM_reg_0_15_60_65_n_1}),
.DOB({RAM_reg_0_15_60_65_n_2,RAM_reg_0_15_60_65_n_3}),
.DOC({RAM_reg_0_15_60_65_n_4,RAM_reg_0_15_60_65_n_5}),
.DOD(NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_66_71
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[67:66]),
.DIB(I115[69:68]),
.DIC(I115[71:70]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_66_71_n_0,RAM_reg_0_15_66_71_n_1}),
.DOB({RAM_reg_0_15_66_71_n_2,RAM_reg_0_15_66_71_n_3}),
.DOC({RAM_reg_0_15_66_71_n_4,RAM_reg_0_15_66_71_n_5}),
.DOD(NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[7:6]),
.DIB(I115[9:8]),
.DIC(I115[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_72_77
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[73:72]),
.DIB(I115[75:74]),
.DIC(I115[77:76]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_72_77_n_0,RAM_reg_0_15_72_77_n_1}),
.DOB({RAM_reg_0_15_72_77_n_2,RAM_reg_0_15_72_77_n_3}),
.DOC({RAM_reg_0_15_72_77_n_4,RAM_reg_0_15_72_77_n_5}),
.DOD(NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_78_83
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[79:78]),
.DIB(I115[81:80]),
.DIC(I115[83:82]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_78_83_n_0,RAM_reg_0_15_78_83_n_1}),
.DOB({RAM_reg_0_15_78_83_n_2,RAM_reg_0_15_78_83_n_3}),
.DOC({RAM_reg_0_15_78_83_n_4,RAM_reg_0_15_78_83_n_5}),
.DOD(NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_84_89
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[85:84]),
.DIB(I115[87:86]),
.DIC(I115[89:88]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_84_89_n_0,RAM_reg_0_15_84_89_n_1}),
.DOB({RAM_reg_0_15_84_89_n_2,RAM_reg_0_15_84_89_n_3}),
.DOC({RAM_reg_0_15_84_89_n_4,RAM_reg_0_15_84_89_n_5}),
.DOD(NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_90_95
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[91:90]),
.DIB(I115[93:92]),
.DIC(I115[95:94]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_90_95_n_0,RAM_reg_0_15_90_95_n_1}),
.DOB({RAM_reg_0_15_90_95_n_2,RAM_reg_0_15_90_95_n_3}),
.DOC({RAM_reg_0_15_90_95_n_4,RAM_reg_0_15_90_95_n_5}),
.DOD(NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_96_101
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[97:96]),
.DIB(I115[99:98]),
.DIC(I115[101:100]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_96_101_n_0,RAM_reg_0_15_96_101_n_1}),
.DOB({RAM_reg_0_15_96_101_n_2,RAM_reg_0_15_96_101_n_3}),
.DOC({RAM_reg_0_15_96_101_n_4,RAM_reg_0_15_96_101_n_5}),
.DOD(NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[100]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_5),
.Q(Q[100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[101]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_4),
.Q(Q[101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[102]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_1),
.Q(Q[102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[103]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_0),
.Q(Q[103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[104]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_3),
.Q(Q[104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[105]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_2),
.Q(Q[105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[106]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_5),
.Q(Q[106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[107]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_4),
.Q(Q[107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[108]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_1),
.Q(Q[108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[109]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_0),
.Q(Q[109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[110]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_3),
.Q(Q[110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[111]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_2),
.Q(Q[111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[112]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_5),
.Q(Q[112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[113]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_4),
.Q(Q[113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[114]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_1),
.Q(Q[114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[115]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_0),
.Q(Q[115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[116]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_3),
.Q(Q[116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[117]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_2),
.Q(Q[117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[118]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_5),
.Q(Q[118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[119]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_4),
.Q(Q[119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[120]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_1),
.Q(Q[120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[121]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_0),
.Q(Q[121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[122]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_3),
.Q(Q[122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[123]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_2),
.Q(Q[123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[124]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_5),
.Q(Q[124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[125]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_4),
.Q(Q[125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[126]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_1),
.Q(Q[126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[127]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_0),
.Q(Q[127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[128]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_3),
.Q(Q[128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[129]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_2),
.Q(Q[129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[130]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_5),
.Q(Q[130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[131]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_4),
.Q(Q[131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[132]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_1),
.Q(Q[132]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[133]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_0),
.Q(Q[133]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[134]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_3),
.Q(Q[134]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[135]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_2),
.Q(Q[135]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[136]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_5),
.Q(Q[136]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[137]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_4),
.Q(Q[137]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[138]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_1),
.Q(Q[138]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[139]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_0),
.Q(Q[139]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[140]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_3),
.Q(Q[140]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[141]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_2),
.Q(Q[141]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[142]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_5),
.Q(Q[142]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[143]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_4),
.Q(Q[143]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[144]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_144_144_n_1),
.Q(Q[144]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_1),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_0),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_3),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_2),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_5),
.Q(Q[58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_4),
.Q(Q[59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_1),
.Q(Q[60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_0),
.Q(Q[61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_3),
.Q(Q[62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_2),
.Q(Q[63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_5),
.Q(Q[64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[65]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_4),
.Q(Q[65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[66]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_1),
.Q(Q[66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[67]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_0),
.Q(Q[67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[68]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_3),
.Q(Q[68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[69]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_2),
.Q(Q[69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[70]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_5),
.Q(Q[70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[71]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_4),
.Q(Q[71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[72]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_1),
.Q(Q[72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[73]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_0),
.Q(Q[73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[74]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_3),
.Q(Q[74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[75]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_2),
.Q(Q[75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[76]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_5),
.Q(Q[76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[77]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_4),
.Q(Q[77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[78]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_1),
.Q(Q[78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[79]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_0),
.Q(Q[79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[80]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_3),
.Q(Q[80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[81]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_2),
.Q(Q[81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[82]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_5),
.Q(Q[82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[83]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_4),
.Q(Q[83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[84]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_1),
.Q(Q[84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[85]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_0),
.Q(Q[85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[86]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_3),
.Q(Q[86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[87]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_2),
.Q(Q[87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[88]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_5),
.Q(Q[88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[89]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_4),
.Q(Q[89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[90]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_1),
.Q(Q[90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[91]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_0),
.Q(Q[91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[92]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_3),
.Q(Q[92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[93]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_2),
.Q(Q[93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[94]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_5),
.Q(Q[94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[95]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_4),
.Q(Q[95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[96]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_1),
.Q(Q[96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[97]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_0),
.Q(Q[97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[98]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_3),
.Q(Q[98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[99]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_2),
.Q(Q[99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem__parameterized1
(Q,
m_aclk,
E,
m_axi_bresp,
m_axi_bid,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk);
output [2:0]Q;
input m_aclk;
input [0:0]E;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
wire [0:0]E;
wire [2:0]Q;
wire RAM_reg_0_15_0_2_n_0;
wire RAM_reg_0_15_0_2_n_1;
wire RAM_reg_0_15_0_2_n_3;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire s_aclk;
wire [1:1]NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_2
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(m_axi_bresp),
.DIB({1'b0,m_axi_bid}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_2_n_0,RAM_reg_0_15_0_2_n_1}),
.DOB({NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED[1],RAM_reg_0_15_0_2_n_3}),
.DOC(NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_2_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_2_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_2_n_3),
.Q(Q[2]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem__parameterized2
(Q,
m_aclk,
E,
I127,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk);
output [131:0]Q;
input m_aclk;
input [0:0]E;
input [131:0]I127;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
wire [0:0]E;
wire [131:0]I127;
wire [131:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_102_107_n_0;
wire RAM_reg_0_15_102_107_n_1;
wire RAM_reg_0_15_102_107_n_2;
wire RAM_reg_0_15_102_107_n_3;
wire RAM_reg_0_15_102_107_n_4;
wire RAM_reg_0_15_102_107_n_5;
wire RAM_reg_0_15_108_113_n_0;
wire RAM_reg_0_15_108_113_n_1;
wire RAM_reg_0_15_108_113_n_2;
wire RAM_reg_0_15_108_113_n_3;
wire RAM_reg_0_15_108_113_n_4;
wire RAM_reg_0_15_108_113_n_5;
wire RAM_reg_0_15_114_119_n_0;
wire RAM_reg_0_15_114_119_n_1;
wire RAM_reg_0_15_114_119_n_2;
wire RAM_reg_0_15_114_119_n_3;
wire RAM_reg_0_15_114_119_n_4;
wire RAM_reg_0_15_114_119_n_5;
wire RAM_reg_0_15_120_125_n_0;
wire RAM_reg_0_15_120_125_n_1;
wire RAM_reg_0_15_120_125_n_2;
wire RAM_reg_0_15_120_125_n_3;
wire RAM_reg_0_15_120_125_n_4;
wire RAM_reg_0_15_120_125_n_5;
wire RAM_reg_0_15_126_131_n_0;
wire RAM_reg_0_15_126_131_n_1;
wire RAM_reg_0_15_126_131_n_2;
wire RAM_reg_0_15_126_131_n_3;
wire RAM_reg_0_15_126_131_n_4;
wire RAM_reg_0_15_126_131_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_59_n_0;
wire RAM_reg_0_15_54_59_n_1;
wire RAM_reg_0_15_54_59_n_2;
wire RAM_reg_0_15_54_59_n_3;
wire RAM_reg_0_15_54_59_n_4;
wire RAM_reg_0_15_54_59_n_5;
wire RAM_reg_0_15_60_65_n_0;
wire RAM_reg_0_15_60_65_n_1;
wire RAM_reg_0_15_60_65_n_2;
wire RAM_reg_0_15_60_65_n_3;
wire RAM_reg_0_15_60_65_n_4;
wire RAM_reg_0_15_60_65_n_5;
wire RAM_reg_0_15_66_71_n_0;
wire RAM_reg_0_15_66_71_n_1;
wire RAM_reg_0_15_66_71_n_2;
wire RAM_reg_0_15_66_71_n_3;
wire RAM_reg_0_15_66_71_n_4;
wire RAM_reg_0_15_66_71_n_5;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire RAM_reg_0_15_72_77_n_0;
wire RAM_reg_0_15_72_77_n_1;
wire RAM_reg_0_15_72_77_n_2;
wire RAM_reg_0_15_72_77_n_3;
wire RAM_reg_0_15_72_77_n_4;
wire RAM_reg_0_15_72_77_n_5;
wire RAM_reg_0_15_78_83_n_0;
wire RAM_reg_0_15_78_83_n_1;
wire RAM_reg_0_15_78_83_n_2;
wire RAM_reg_0_15_78_83_n_3;
wire RAM_reg_0_15_78_83_n_4;
wire RAM_reg_0_15_78_83_n_5;
wire RAM_reg_0_15_84_89_n_0;
wire RAM_reg_0_15_84_89_n_1;
wire RAM_reg_0_15_84_89_n_2;
wire RAM_reg_0_15_84_89_n_3;
wire RAM_reg_0_15_84_89_n_4;
wire RAM_reg_0_15_84_89_n_5;
wire RAM_reg_0_15_90_95_n_0;
wire RAM_reg_0_15_90_95_n_1;
wire RAM_reg_0_15_90_95_n_2;
wire RAM_reg_0_15_90_95_n_3;
wire RAM_reg_0_15_90_95_n_4;
wire RAM_reg_0_15_90_95_n_5;
wire RAM_reg_0_15_96_101_n_0;
wire RAM_reg_0_15_96_101_n_1;
wire RAM_reg_0_15_96_101_n_2;
wire RAM_reg_0_15_96_101_n_3;
wire RAM_reg_0_15_96_101_n_4;
wire RAM_reg_0_15_96_101_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[1:0]),
.DIB(I127[3:2]),
.DIC(I127[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_102_107
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[103:102]),
.DIB(I127[105:104]),
.DIC(I127[107:106]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_102_107_n_0,RAM_reg_0_15_102_107_n_1}),
.DOB({RAM_reg_0_15_102_107_n_2,RAM_reg_0_15_102_107_n_3}),
.DOC({RAM_reg_0_15_102_107_n_4,RAM_reg_0_15_102_107_n_5}),
.DOD(NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_108_113
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[109:108]),
.DIB(I127[111:110]),
.DIC(I127[113:112]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_108_113_n_0,RAM_reg_0_15_108_113_n_1}),
.DOB({RAM_reg_0_15_108_113_n_2,RAM_reg_0_15_108_113_n_3}),
.DOC({RAM_reg_0_15_108_113_n_4,RAM_reg_0_15_108_113_n_5}),
.DOD(NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_114_119
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[115:114]),
.DIB(I127[117:116]),
.DIC(I127[119:118]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_114_119_n_0,RAM_reg_0_15_114_119_n_1}),
.DOB({RAM_reg_0_15_114_119_n_2,RAM_reg_0_15_114_119_n_3}),
.DOC({RAM_reg_0_15_114_119_n_4,RAM_reg_0_15_114_119_n_5}),
.DOD(NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_120_125
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[121:120]),
.DIB(I127[123:122]),
.DIC(I127[125:124]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_120_125_n_0,RAM_reg_0_15_120_125_n_1}),
.DOB({RAM_reg_0_15_120_125_n_2,RAM_reg_0_15_120_125_n_3}),
.DOC({RAM_reg_0_15_120_125_n_4,RAM_reg_0_15_120_125_n_5}),
.DOD(NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_126_131
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[127:126]),
.DIB(I127[129:128]),
.DIC(I127[131:130]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_126_131_n_0,RAM_reg_0_15_126_131_n_1}),
.DOB({RAM_reg_0_15_126_131_n_2,RAM_reg_0_15_126_131_n_3}),
.DOC({RAM_reg_0_15_126_131_n_4,RAM_reg_0_15_126_131_n_5}),
.DOD(NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[13:12]),
.DIB(I127[15:14]),
.DIC(I127[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[19:18]),
.DIB(I127[21:20]),
.DIC(I127[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[25:24]),
.DIB(I127[27:26]),
.DIC(I127[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[31:30]),
.DIB(I127[33:32]),
.DIC(I127[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[37:36]),
.DIB(I127[39:38]),
.DIC(I127[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[43:42]),
.DIB(I127[45:44]),
.DIC(I127[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[49:48]),
.DIB(I127[51:50]),
.DIC(I127[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_59
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[55:54]),
.DIB(I127[57:56]),
.DIC(I127[59:58]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_59_n_0,RAM_reg_0_15_54_59_n_1}),
.DOB({RAM_reg_0_15_54_59_n_2,RAM_reg_0_15_54_59_n_3}),
.DOC({RAM_reg_0_15_54_59_n_4,RAM_reg_0_15_54_59_n_5}),
.DOD(NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_60_65
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[61:60]),
.DIB(I127[63:62]),
.DIC(I127[65:64]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_60_65_n_0,RAM_reg_0_15_60_65_n_1}),
.DOB({RAM_reg_0_15_60_65_n_2,RAM_reg_0_15_60_65_n_3}),
.DOC({RAM_reg_0_15_60_65_n_4,RAM_reg_0_15_60_65_n_5}),
.DOD(NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_66_71
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[67:66]),
.DIB(I127[69:68]),
.DIC(I127[71:70]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_66_71_n_0,RAM_reg_0_15_66_71_n_1}),
.DOB({RAM_reg_0_15_66_71_n_2,RAM_reg_0_15_66_71_n_3}),
.DOC({RAM_reg_0_15_66_71_n_4,RAM_reg_0_15_66_71_n_5}),
.DOD(NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[7:6]),
.DIB(I127[9:8]),
.DIC(I127[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_72_77
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[73:72]),
.DIB(I127[75:74]),
.DIC(I127[77:76]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_72_77_n_0,RAM_reg_0_15_72_77_n_1}),
.DOB({RAM_reg_0_15_72_77_n_2,RAM_reg_0_15_72_77_n_3}),
.DOC({RAM_reg_0_15_72_77_n_4,RAM_reg_0_15_72_77_n_5}),
.DOD(NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_78_83
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[79:78]),
.DIB(I127[81:80]),
.DIC(I127[83:82]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_78_83_n_0,RAM_reg_0_15_78_83_n_1}),
.DOB({RAM_reg_0_15_78_83_n_2,RAM_reg_0_15_78_83_n_3}),
.DOC({RAM_reg_0_15_78_83_n_4,RAM_reg_0_15_78_83_n_5}),
.DOD(NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_84_89
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[85:84]),
.DIB(I127[87:86]),
.DIC(I127[89:88]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_84_89_n_0,RAM_reg_0_15_84_89_n_1}),
.DOB({RAM_reg_0_15_84_89_n_2,RAM_reg_0_15_84_89_n_3}),
.DOC({RAM_reg_0_15_84_89_n_4,RAM_reg_0_15_84_89_n_5}),
.DOD(NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_90_95
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[91:90]),
.DIB(I127[93:92]),
.DIC(I127[95:94]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_90_95_n_0,RAM_reg_0_15_90_95_n_1}),
.DOB({RAM_reg_0_15_90_95_n_2,RAM_reg_0_15_90_95_n_3}),
.DOC({RAM_reg_0_15_90_95_n_4,RAM_reg_0_15_90_95_n_5}),
.DOD(NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_96_101
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[97:96]),
.DIB(I127[99:98]),
.DIC(I127[101:100]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_96_101_n_0,RAM_reg_0_15_96_101_n_1}),
.DOB({RAM_reg_0_15_96_101_n_2,RAM_reg_0_15_96_101_n_3}),
.DOC({RAM_reg_0_15_96_101_n_4,RAM_reg_0_15_96_101_n_5}),
.DOD(NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[100]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_5),
.Q(Q[100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[101]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_4),
.Q(Q[101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[102]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_1),
.Q(Q[102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[103]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_0),
.Q(Q[103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[104]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_3),
.Q(Q[104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[105]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_2),
.Q(Q[105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[106]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_5),
.Q(Q[106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[107]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_4),
.Q(Q[107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[108]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_1),
.Q(Q[108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[109]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_0),
.Q(Q[109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[110]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_3),
.Q(Q[110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[111]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_2),
.Q(Q[111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[112]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_5),
.Q(Q[112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[113]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_4),
.Q(Q[113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[114]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_1),
.Q(Q[114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[115]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_0),
.Q(Q[115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[116]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_3),
.Q(Q[116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[117]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_2),
.Q(Q[117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[118]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_5),
.Q(Q[118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[119]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_4),
.Q(Q[119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[120]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_1),
.Q(Q[120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[121]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_0),
.Q(Q[121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[122]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_3),
.Q(Q[122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[123]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_2),
.Q(Q[123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[124]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_5),
.Q(Q[124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[125]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_4),
.Q(Q[125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[126]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_1),
.Q(Q[126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[127]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_0),
.Q(Q[127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[128]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_3),
.Q(Q[128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[129]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_2),
.Q(Q[129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[130]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_5),
.Q(Q[130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[131]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_4),
.Q(Q[131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_1),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_0),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_3),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_2),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_5),
.Q(Q[58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_4),
.Q(Q[59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_1),
.Q(Q[60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_0),
.Q(Q[61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_3),
.Q(Q[62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_2),
.Q(Q[63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_5),
.Q(Q[64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[65]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_4),
.Q(Q[65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[66]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_1),
.Q(Q[66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[67]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_0),
.Q(Q[67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[68]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_3),
.Q(Q[68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[69]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_2),
.Q(Q[69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[70]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_5),
.Q(Q[70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[71]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_4),
.Q(Q[71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[72]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_1),
.Q(Q[72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[73]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_0),
.Q(Q[73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[74]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_3),
.Q(Q[74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[75]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_2),
.Q(Q[75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[76]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_5),
.Q(Q[76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[77]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_4),
.Q(Q[77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[78]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_1),
.Q(Q[78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[79]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_0),
.Q(Q[79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[80]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_3),
.Q(Q[80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[81]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_2),
.Q(Q[81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[82]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_5),
.Q(Q[82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[83]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_4),
.Q(Q[83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[84]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_1),
.Q(Q[84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[85]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_0),
.Q(Q[85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[86]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_3),
.Q(Q[86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[87]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_2),
.Q(Q[87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[88]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_5),
.Q(Q[88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[89]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_4),
.Q(Q[89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[90]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_1),
.Q(Q[90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[91]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_0),
.Q(Q[91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[92]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_3),
.Q(Q[92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[93]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_2),
.Q(Q[93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[94]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_5),
.Q(Q[94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[95]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_4),
.Q(Q[95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[96]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_1),
.Q(Q[96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[97]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_0),
.Q(Q[97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[98]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_3),
.Q(Q[98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[99]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_2),
.Q(Q[99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo
(s_axi_awready,
m_axi_awvalid,
Q,
m_aclk,
s_aclk,
inverted_reset,
m_axi_awready,
s_axi_awvalid,
DI);
output s_axi_awready;
output m_axi_awvalid;
output [57:0]Q;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_awready;
input s_axi_awvalid;
input [57:0]DI;
wire [57:0]DI;
wire [57:0]Q;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire [0:0]gray2bin;
wire inverted_reset;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [3:0]p_0_out_0;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire p_23_out;
wire [3:3]p_23_out_1;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
wire [2:0]wr_pntr_plus2;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_27 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D(gray2bin),
.Q(p_22_out),
.\gc0.count_d1_reg[2] ({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.\gc0.count_d1_reg[3] (p_0_out_0[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (p_23_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out_1),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(gray2bin));
system_auto_cc_0_rd_logic_28 \gntv_or_sync_fifo.gl0.rd
(.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[2] ({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out_0),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[57] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
system_auto_cc_0_wr_logic_29 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out_1),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
system_auto_cc_0_memory \gntv_or_sync_fifo.mem
(.DI(DI),
.E(\gntv_or_sync_fifo.gl0.rd_n_4 ),
.Q(Q),
.\gc0.count_d1_reg[3] (p_0_out_0),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.ram_full_fb_i_reg(p_18_out),
.s_aclk(s_aclk));
system_auto_cc_0_reset_blk_ramfifo_30 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(p_23_out),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo_69
(s_axi_arready,
m_axi_arvalid,
\m_axi_arid[0] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_arready,
s_axi_arvalid,
I123);
output s_axi_arready;
output m_axi_arvalid;
output [57:0]\m_axi_arid[0] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_arready;
input s_axi_arvalid;
input [57:0]I123;
wire [57:0]I123;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire inverted_reset;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_rach;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_70 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_22_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rach),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic_71 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[57] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
system_auto_cc_0_wr_logic_72 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
system_auto_cc_0_memory_73 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I123(I123),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\m_axi_arid[0] (\m_axi_arid[0] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk));
system_auto_cc_0_reset_blk_ramfifo_74 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_rach),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo__parameterized0
(s_axi_wready,
m_axi_wvalid,
\m_axi_wdata[127] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_wready,
s_axi_wvalid,
I115);
output s_axi_wready;
output m_axi_wvalid;
output [144:0]\m_axi_wdata[127] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_wready;
input s_axi_wvalid;
input [144:0]I115;
wire [144:0]I115;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire inverted_reset;
wire m_aclk;
wire [144:0]\m_axi_wdata[127] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_15_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
wire [2:0]wr_pntr_plus2;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_6 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_22_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (p_15_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic_7 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[144] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
system_auto_cc_0_wr_logic_8 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
system_auto_cc_0_memory__parameterized0 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I115(I115),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\m_axi_wdata[127] (\m_axi_wdata[127] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk));
system_auto_cc_0_reset_blk_ramfifo_9 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(p_15_out),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo__parameterized1
(s_axi_bvalid,
m_axi_bready,
s_axi_bid,
s_axi_bresp,
s_aclk,
m_aclk,
inverted_reset,
m_axi_bresp,
m_axi_bid,
m_axi_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_axi_bready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input s_aclk;
input m_aclk;
input inverted_reset;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input m_axi_bvalid;
input s_axi_bready;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_0 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.rd_n_8 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire [0:0]\gr1.gr1_int.rfwft/p_0_in ;
wire inverted_reset;
wire m_aclk;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_wrch;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 ,\gntv_or_sync_fifo.gl0.rd_n_8 }),
.Q(p_13_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_wrch),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.ram_empty_i_reg_0(p_22_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.D({\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 ,\gntv_or_sync_fifo.gl0.rd_n_8 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.out({\gntv_or_sync_fifo.gl0.rd_n_0 ,\gr1.gr1_int.rfwft/p_0_in }),
.s_aclk(s_aclk),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
system_auto_cc_0_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.m_aclk(m_aclk),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ));
system_auto_cc_0_memory__parameterized1 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.\gpregsm1.curr_fwft_state_reg[1]_0 ({\gntv_or_sync_fifo.gl0.rd_n_0 ,\gr1.gr1_int.rfwft/p_0_in }),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.out(rd_rst_i[0]),
.s_aclk(s_aclk),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp));
system_auto_cc_0_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_wrch),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo__parameterized2
(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ,
s_axi_rvalid,
m_axi_rready,
\s_axi_rid[0] ,
s_aclk,
m_aclk,
m_axi_rvalid,
s_axi_rready,
s_aresetn,
I127);
output \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ;
output s_axi_rvalid;
output m_axi_rready;
output [131:0]\s_axi_rid[0] ;
input s_aclk;
input m_aclk;
input m_axi_rvalid;
input s_axi_rready;
input s_aresetn;
input [131:0]I127;
wire [131:0]I127;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_aresetn;
wire [131:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_rdch;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_48 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_13_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rdch),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.ram_empty_i_reg_0(p_22_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic_49 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[131] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.out({rd_rst_i[2],rd_rst_i[0]}),
.s_aclk(s_aclk),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
system_auto_cc_0_wr_logic_50 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ));
system_auto_cc_0_memory__parameterized2 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I127(I127),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk),
.\s_axi_rid[0] (\s_axi_rid[0] ));
system_auto_cc_0_reset_blk_ramfifo_51 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 (\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_rdch),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top
(s_axi_arready,
m_axi_arvalid,
\m_axi_arid[0] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_arready,
s_axi_arvalid,
I123);
output s_axi_arready;
output m_axi_arvalid;
output [57:0]\m_axi_arid[0] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_arready;
input s_axi_arvalid;
input [57:0]I123;
wire [57:0]I123;
wire inverted_reset;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
system_auto_cc_0_fifo_generator_ramfifo_69 \grf.rf
(.I123(I123),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_arid[0] (\m_axi_arid[0] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top_0
(s_axi_awready,
m_axi_awvalid,
Q,
m_aclk,
s_aclk,
inverted_reset,
m_axi_awready,
s_axi_awvalid,
DI);
output s_axi_awready;
output m_axi_awvalid;
output [57:0]Q;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_awready;
input s_axi_awvalid;
input [57:0]DI;
wire [57:0]DI;
wire [57:0]Q;
wire inverted_reset;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
system_auto_cc_0_fifo_generator_ramfifo \grf.rf
(.DI(DI),
.Q(Q),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top__parameterized0
(s_axi_wready,
m_axi_wvalid,
\m_axi_wdata[127] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_wready,
s_axi_wvalid,
I115);
output s_axi_wready;
output m_axi_wvalid;
output [144:0]\m_axi_wdata[127] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_wready;
input s_axi_wvalid;
input [144:0]I115;
wire [144:0]I115;
wire inverted_reset;
wire m_aclk;
wire [144:0]\m_axi_wdata[127] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
system_auto_cc_0_fifo_generator_ramfifo__parameterized0 \grf.rf
(.I115(I115),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_wdata[127] (\m_axi_wdata[127] ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top__parameterized1
(s_axi_bvalid,
m_axi_bready,
s_axi_bid,
s_axi_bresp,
s_aclk,
m_aclk,
inverted_reset,
m_axi_bresp,
m_axi_bid,
m_axi_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_axi_bready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input s_aclk;
input m_aclk;
input inverted_reset;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input m_axi_bvalid;
input s_axi_bready;
wire inverted_reset;
wire m_aclk;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire s_aclk;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
system_auto_cc_0_fifo_generator_ramfifo__parameterized1 \grf.rf
(.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.s_aclk(s_aclk),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top__parameterized2
(inverted_reset,
s_axi_rvalid,
m_axi_rready,
\s_axi_rid[0] ,
s_aclk,
m_aclk,
m_axi_rvalid,
s_axi_rready,
s_aresetn,
I127);
output inverted_reset;
output s_axi_rvalid;
output m_axi_rready;
output [131:0]\s_axi_rid[0] ;
input s_aclk;
input m_aclk;
input m_axi_rvalid;
input s_axi_rready;
input s_aresetn;
input [131:0]I127;
wire [131:0]I127;
wire inverted_reset;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire s_aclk;
wire s_aresetn;
wire [131:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
system_auto_cc_0_fifo_generator_ramfifo__parameterized2 \grf.rf
(.I127(I127),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg (inverted_reset),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "28" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "128" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "18" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "58" *) (* C_DIN_WIDTH_RDCH = "132" *)
(* C_DIN_WIDTH_WACH = "58" *) (* C_DIN_WIDTH_WDCH = "145" *) (* C_DIN_WIDTH_WRCH = "3" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "18" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "11" *) (* C_IMPLEMENTATION_TYPE_RACH = "12" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "12" *) (* C_IMPLEMENTATION_TYPE_WACH = "12" *) (* C_IMPLEMENTATION_TYPE_WDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "12" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "2" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "4kx4" *)
(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1021" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "13" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "13" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "13" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "15" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "3" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "16" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "16" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "4" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "4" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *)
module system_auto_cc_0_fifo_generator_v13_1_3
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [17:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [17:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [27:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [127:0]s_axi_wdata;
input [15:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [27:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [27:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [127:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [27:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [3:0]axi_w_prog_full_thresh;
input [3:0]axi_w_prog_empty_thresh;
output [4:0]axi_w_data_count;
output [4:0]axi_w_wr_data_count;
output [4:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [3:0]axi_r_prog_full_thresh;
input [3:0]axi_r_prog_empty_thresh;
output [4:0]axi_r_data_count;
output [4:0]axi_r_wr_data_count;
output [4:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire m_aclk;
wire [27:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire [0:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [27:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [0:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [15:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_aclk;
wire s_aresetn;
wire [27:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [27:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [127:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [127:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [15:0]s_axi_wstrb;
wire s_axi_wvalid;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const0> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const0> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const0> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const0> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const0> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const0> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign dout[17] = \<const0> ;
assign dout[16] = \<const0> ;
assign dout[15] = \<const0> ;
assign dout[14] = \<const0> ;
assign dout[13] = \<const0> ;
assign dout[12] = \<const0> ;
assign dout[11] = \<const0> ;
assign dout[10] = \<const0> ;
assign dout[9] = \<const0> ;
assign dout[8] = \<const0> ;
assign dout[7] = \<const0> ;
assign dout[6] = \<const0> ;
assign dout[5] = \<const0> ;
assign dout[4] = \<const0> ;
assign dout[3] = \<const0> ;
assign dout[2] = \<const0> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
assign empty = \<const0> ;
assign full = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
system_auto_cc_0_fifo_generator_v13_1_3_synth inst_fifo_gen
(.DI({s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awregion}),
.I115({s_axi_wdata,s_axi_wstrb,s_axi_wlast}),
.I123({s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arregion}),
.I127({m_axi_rid,m_axi_rdata,m_axi_rresp,m_axi_rlast}),
.Q({m_axi_awid,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awqos,m_axi_awregion}),
.m_aclk(m_aclk),
.\m_axi_arid[0] ({m_axi_arid,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arqos,m_axi_arregion}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.\m_axi_wdata[127] ({m_axi_wdata,m_axi_wstrb,m_axi_wlast}),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[0] ({s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *)
module system_auto_cc_0_fifo_generator_v13_1_3_synth
(Q,
\m_axi_wdata[127] ,
s_axi_bid,
s_axi_bresp,
\m_axi_arid[0] ,
\s_axi_rid[0] ,
s_axi_awready,
s_axi_wready,
s_axi_bvalid,
m_axi_awvalid,
m_axi_wvalid,
m_axi_bready,
s_axi_arready,
s_axi_rvalid,
m_axi_arvalid,
m_axi_rready,
m_aclk,
s_aclk,
I115,
m_axi_bresp,
m_axi_bid,
s_axi_bready,
I123,
I127,
DI,
m_axi_awready,
m_axi_wready,
m_axi_bvalid,
m_axi_arready,
m_axi_rvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_arvalid,
s_axi_rready,
s_aresetn);
output [57:0]Q;
output [144:0]\m_axi_wdata[127] ;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [57:0]\m_axi_arid[0] ;
output [131:0]\s_axi_rid[0] ;
output s_axi_awready;
output s_axi_wready;
output s_axi_bvalid;
output m_axi_awvalid;
output m_axi_wvalid;
output m_axi_bready;
output s_axi_arready;
output s_axi_rvalid;
output m_axi_arvalid;
output m_axi_rready;
input m_aclk;
input s_aclk;
input [144:0]I115;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input s_axi_bready;
input [57:0]I123;
input [131:0]I127;
input [57:0]DI;
input m_axi_awready;
input m_axi_wready;
input m_axi_bvalid;
input m_axi_arready;
input m_axi_rvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_arvalid;
input s_axi_rready;
input s_aresetn;
wire [57:0]DI;
wire [144:0]I115;
wire [57:0]I123;
wire [131:0]I127;
wire [57:0]Q;
wire inverted_reset;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire [144:0]\m_axi_wdata[127] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire s_aclk;
wire s_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [131:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
system_auto_cc_0_fifo_generator_top \gaxi_full_lite.gread_ch.grach2.axi_rach
(.I123(I123),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_arid[0] (\m_axi_arid[0] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
system_auto_cc_0_fifo_generator_top__parameterized2 \gaxi_full_lite.gread_ch.grdch2.axi_rdch
(.I127(I127),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
system_auto_cc_0_fifo_generator_top_0 \gaxi_full_lite.gwrite_ch.gwach2.axi_wach
(.DI(DI),
.Q(Q),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
system_auto_cc_0_fifo_generator_top__parameterized0 \gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch
(.I115(I115),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_wdata[127] (\m_axi_wdata[127] ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
system_auto_cc_0_fifo_generator_top__parameterized1 \gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch
(.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.s_aclk(s_aclk),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory
(Q,
E,
m_aclk,
s_aclk,
ram_full_fb_i_reg,
DI,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] );
output [57:0]Q;
input [0:0]E;
input m_aclk;
input s_aclk;
input [0:0]ram_full_fb_i_reg;
input [57:0]DI;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [57:0]DI;
wire [0:0]E;
wire [57:0]Q;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]ram_full_fb_i_reg;
wire s_aclk;
system_auto_cc_0_dmem \gdm.dm_gen.dm
(.DI(DI),
.dout_i({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory_73
(\m_axi_arid[0] ,
s_aclk,
E,
I123,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [57:0]\m_axi_arid[0] ;
input s_aclk;
input [0:0]E;
input [57:0]I123;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [57:0]I123;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
system_auto_cc_0_dmem_81 \gdm.dm_gen.dm
(.E(E),
.I123(I123),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(\m_axi_arid[0] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(\m_axi_arid[0] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(\m_axi_arid[0] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(\m_axi_arid[0] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(\m_axi_arid[0] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(\m_axi_arid[0] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(\m_axi_arid[0] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(\m_axi_arid[0] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(\m_axi_arid[0] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(\m_axi_arid[0] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\m_axi_arid[0] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(\m_axi_arid[0] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\m_axi_arid[0] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\m_axi_arid[0] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\m_axi_arid[0] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\m_axi_arid[0] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\m_axi_arid[0] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\m_axi_arid[0] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\m_axi_arid[0] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\m_axi_arid[0] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\m_axi_arid[0] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\m_axi_arid[0] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(\m_axi_arid[0] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\m_axi_arid[0] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\m_axi_arid[0] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\m_axi_arid[0] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\m_axi_arid[0] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\m_axi_arid[0] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\m_axi_arid[0] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\m_axi_arid[0] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\m_axi_arid[0] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\m_axi_arid[0] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\m_axi_arid[0] [39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(\m_axi_arid[0] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\m_axi_arid[0] [40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\m_axi_arid[0] [41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\m_axi_arid[0] [42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\m_axi_arid[0] [43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\m_axi_arid[0] [44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\m_axi_arid[0] [45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\m_axi_arid[0] [46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\m_axi_arid[0] [47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\m_axi_arid[0] [48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\m_axi_arid[0] [49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(\m_axi_arid[0] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\m_axi_arid[0] [50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\m_axi_arid[0] [51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\m_axi_arid[0] [52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\m_axi_arid[0] [53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\m_axi_arid[0] [54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\m_axi_arid[0] [55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\m_axi_arid[0] [56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\m_axi_arid[0] [57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(\m_axi_arid[0] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(\m_axi_arid[0] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(\m_axi_arid[0] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(\m_axi_arid[0] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(\m_axi_arid[0] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory__parameterized0
(\m_axi_wdata[127] ,
s_aclk,
E,
I115,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [144:0]\m_axi_wdata[127] ;
input s_aclk;
input [0:0]E;
input [144:0]I115;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [144:0]I115;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_100 ;
wire \gdm.dm_gen.dm_n_101 ;
wire \gdm.dm_gen.dm_n_102 ;
wire \gdm.dm_gen.dm_n_103 ;
wire \gdm.dm_gen.dm_n_104 ;
wire \gdm.dm_gen.dm_n_105 ;
wire \gdm.dm_gen.dm_n_106 ;
wire \gdm.dm_gen.dm_n_107 ;
wire \gdm.dm_gen.dm_n_108 ;
wire \gdm.dm_gen.dm_n_109 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_110 ;
wire \gdm.dm_gen.dm_n_111 ;
wire \gdm.dm_gen.dm_n_112 ;
wire \gdm.dm_gen.dm_n_113 ;
wire \gdm.dm_gen.dm_n_114 ;
wire \gdm.dm_gen.dm_n_115 ;
wire \gdm.dm_gen.dm_n_116 ;
wire \gdm.dm_gen.dm_n_117 ;
wire \gdm.dm_gen.dm_n_118 ;
wire \gdm.dm_gen.dm_n_119 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_120 ;
wire \gdm.dm_gen.dm_n_121 ;
wire \gdm.dm_gen.dm_n_122 ;
wire \gdm.dm_gen.dm_n_123 ;
wire \gdm.dm_gen.dm_n_124 ;
wire \gdm.dm_gen.dm_n_125 ;
wire \gdm.dm_gen.dm_n_126 ;
wire \gdm.dm_gen.dm_n_127 ;
wire \gdm.dm_gen.dm_n_128 ;
wire \gdm.dm_gen.dm_n_129 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_130 ;
wire \gdm.dm_gen.dm_n_131 ;
wire \gdm.dm_gen.dm_n_132 ;
wire \gdm.dm_gen.dm_n_133 ;
wire \gdm.dm_gen.dm_n_134 ;
wire \gdm.dm_gen.dm_n_135 ;
wire \gdm.dm_gen.dm_n_136 ;
wire \gdm.dm_gen.dm_n_137 ;
wire \gdm.dm_gen.dm_n_138 ;
wire \gdm.dm_gen.dm_n_139 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_140 ;
wire \gdm.dm_gen.dm_n_141 ;
wire \gdm.dm_gen.dm_n_142 ;
wire \gdm.dm_gen.dm_n_143 ;
wire \gdm.dm_gen.dm_n_144 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_58 ;
wire \gdm.dm_gen.dm_n_59 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_60 ;
wire \gdm.dm_gen.dm_n_61 ;
wire \gdm.dm_gen.dm_n_62 ;
wire \gdm.dm_gen.dm_n_63 ;
wire \gdm.dm_gen.dm_n_64 ;
wire \gdm.dm_gen.dm_n_65 ;
wire \gdm.dm_gen.dm_n_66 ;
wire \gdm.dm_gen.dm_n_67 ;
wire \gdm.dm_gen.dm_n_68 ;
wire \gdm.dm_gen.dm_n_69 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_70 ;
wire \gdm.dm_gen.dm_n_71 ;
wire \gdm.dm_gen.dm_n_72 ;
wire \gdm.dm_gen.dm_n_73 ;
wire \gdm.dm_gen.dm_n_74 ;
wire \gdm.dm_gen.dm_n_75 ;
wire \gdm.dm_gen.dm_n_76 ;
wire \gdm.dm_gen.dm_n_77 ;
wire \gdm.dm_gen.dm_n_78 ;
wire \gdm.dm_gen.dm_n_79 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_80 ;
wire \gdm.dm_gen.dm_n_81 ;
wire \gdm.dm_gen.dm_n_82 ;
wire \gdm.dm_gen.dm_n_83 ;
wire \gdm.dm_gen.dm_n_84 ;
wire \gdm.dm_gen.dm_n_85 ;
wire \gdm.dm_gen.dm_n_86 ;
wire \gdm.dm_gen.dm_n_87 ;
wire \gdm.dm_gen.dm_n_88 ;
wire \gdm.dm_gen.dm_n_89 ;
wire \gdm.dm_gen.dm_n_9 ;
wire \gdm.dm_gen.dm_n_90 ;
wire \gdm.dm_gen.dm_n_91 ;
wire \gdm.dm_gen.dm_n_92 ;
wire \gdm.dm_gen.dm_n_93 ;
wire \gdm.dm_gen.dm_n_94 ;
wire \gdm.dm_gen.dm_n_95 ;
wire \gdm.dm_gen.dm_n_96 ;
wire \gdm.dm_gen.dm_n_97 ;
wire \gdm.dm_gen.dm_n_98 ;
wire \gdm.dm_gen.dm_n_99 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [144:0]\m_axi_wdata[127] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
system_auto_cc_0_dmem__parameterized0 \gdm.dm_gen.dm
(.E(E),
.I115(I115),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 ,\gdm.dm_gen.dm_n_58 ,\gdm.dm_gen.dm_n_59 ,\gdm.dm_gen.dm_n_60 ,\gdm.dm_gen.dm_n_61 ,\gdm.dm_gen.dm_n_62 ,\gdm.dm_gen.dm_n_63 ,\gdm.dm_gen.dm_n_64 ,\gdm.dm_gen.dm_n_65 ,\gdm.dm_gen.dm_n_66 ,\gdm.dm_gen.dm_n_67 ,\gdm.dm_gen.dm_n_68 ,\gdm.dm_gen.dm_n_69 ,\gdm.dm_gen.dm_n_70 ,\gdm.dm_gen.dm_n_71 ,\gdm.dm_gen.dm_n_72 ,\gdm.dm_gen.dm_n_73 ,\gdm.dm_gen.dm_n_74 ,\gdm.dm_gen.dm_n_75 ,\gdm.dm_gen.dm_n_76 ,\gdm.dm_gen.dm_n_77 ,\gdm.dm_gen.dm_n_78 ,\gdm.dm_gen.dm_n_79 ,\gdm.dm_gen.dm_n_80 ,\gdm.dm_gen.dm_n_81 ,\gdm.dm_gen.dm_n_82 ,\gdm.dm_gen.dm_n_83 ,\gdm.dm_gen.dm_n_84 ,\gdm.dm_gen.dm_n_85 ,\gdm.dm_gen.dm_n_86 ,\gdm.dm_gen.dm_n_87 ,\gdm.dm_gen.dm_n_88 ,\gdm.dm_gen.dm_n_89 ,\gdm.dm_gen.dm_n_90 ,\gdm.dm_gen.dm_n_91 ,\gdm.dm_gen.dm_n_92 ,\gdm.dm_gen.dm_n_93 ,\gdm.dm_gen.dm_n_94 ,\gdm.dm_gen.dm_n_95 ,\gdm.dm_gen.dm_n_96 ,\gdm.dm_gen.dm_n_97 ,\gdm.dm_gen.dm_n_98 ,\gdm.dm_gen.dm_n_99 ,\gdm.dm_gen.dm_n_100 ,\gdm.dm_gen.dm_n_101 ,\gdm.dm_gen.dm_n_102 ,\gdm.dm_gen.dm_n_103 ,\gdm.dm_gen.dm_n_104 ,\gdm.dm_gen.dm_n_105 ,\gdm.dm_gen.dm_n_106 ,\gdm.dm_gen.dm_n_107 ,\gdm.dm_gen.dm_n_108 ,\gdm.dm_gen.dm_n_109 ,\gdm.dm_gen.dm_n_110 ,\gdm.dm_gen.dm_n_111 ,\gdm.dm_gen.dm_n_112 ,\gdm.dm_gen.dm_n_113 ,\gdm.dm_gen.dm_n_114 ,\gdm.dm_gen.dm_n_115 ,\gdm.dm_gen.dm_n_116 ,\gdm.dm_gen.dm_n_117 ,\gdm.dm_gen.dm_n_118 ,\gdm.dm_gen.dm_n_119 ,\gdm.dm_gen.dm_n_120 ,\gdm.dm_gen.dm_n_121 ,\gdm.dm_gen.dm_n_122 ,\gdm.dm_gen.dm_n_123 ,\gdm.dm_gen.dm_n_124 ,\gdm.dm_gen.dm_n_125 ,\gdm.dm_gen.dm_n_126 ,\gdm.dm_gen.dm_n_127 ,\gdm.dm_gen.dm_n_128 ,\gdm.dm_gen.dm_n_129 ,\gdm.dm_gen.dm_n_130 ,\gdm.dm_gen.dm_n_131 ,\gdm.dm_gen.dm_n_132 ,\gdm.dm_gen.dm_n_133 ,\gdm.dm_gen.dm_n_134 ,\gdm.dm_gen.dm_n_135 ,\gdm.dm_gen.dm_n_136 ,\gdm.dm_gen.dm_n_137 ,\gdm.dm_gen.dm_n_138 ,\gdm.dm_gen.dm_n_139 ,\gdm.dm_gen.dm_n_140 ,\gdm.dm_gen.dm_n_141 ,\gdm.dm_gen.dm_n_142 ,\gdm.dm_gen.dm_n_143 ,\gdm.dm_gen.dm_n_144 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_144 ),
.Q(\m_axi_wdata[127] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[100]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(\m_axi_wdata[127] [100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[101]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(\m_axi_wdata[127] [101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[102]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(\m_axi_wdata[127] [102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[103]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(\m_axi_wdata[127] [103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[104]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(\m_axi_wdata[127] [104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[105]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(\m_axi_wdata[127] [105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[106]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\m_axi_wdata[127] [106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[107]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\m_axi_wdata[127] [107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[108]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\m_axi_wdata[127] [108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[109]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\m_axi_wdata[127] [109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_134 ),
.Q(\m_axi_wdata[127] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[110]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\m_axi_wdata[127] [110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[111]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\m_axi_wdata[127] [111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[112]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\m_axi_wdata[127] [112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[113]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\m_axi_wdata[127] [113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[114]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\m_axi_wdata[127] [114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[115]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\m_axi_wdata[127] [115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[116]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\m_axi_wdata[127] [116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[117]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\m_axi_wdata[127] [117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[118]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\m_axi_wdata[127] [118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[119]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\m_axi_wdata[127] [119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_133 ),
.Q(\m_axi_wdata[127] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[120]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\m_axi_wdata[127] [120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[121]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\m_axi_wdata[127] [121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[122]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\m_axi_wdata[127] [122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[123]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\m_axi_wdata[127] [123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[124]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\m_axi_wdata[127] [124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[125]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\m_axi_wdata[127] [125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[126]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\m_axi_wdata[127] [126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[127]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\m_axi_wdata[127] [127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[128]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\m_axi_wdata[127] [128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[129]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\m_axi_wdata[127] [129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_132 ),
.Q(\m_axi_wdata[127] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[130]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\m_axi_wdata[127] [130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[131]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\m_axi_wdata[127] [131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[132]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\m_axi_wdata[127] [132]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[133]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\m_axi_wdata[127] [133]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[134]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\m_axi_wdata[127] [134]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[135]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\m_axi_wdata[127] [135]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[136]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\m_axi_wdata[127] [136]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[137]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\m_axi_wdata[127] [137]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[138]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\m_axi_wdata[127] [138]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[139]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\m_axi_wdata[127] [139]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_131 ),
.Q(\m_axi_wdata[127] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[140]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\m_axi_wdata[127] [140]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[141]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\m_axi_wdata[127] [141]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[142]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\m_axi_wdata[127] [142]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[143]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\m_axi_wdata[127] [143]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[144]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\m_axi_wdata[127] [144]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_130 ),
.Q(\m_axi_wdata[127] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_129 ),
.Q(\m_axi_wdata[127] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_128 ),
.Q(\m_axi_wdata[127] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_127 ),
.Q(\m_axi_wdata[127] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_126 ),
.Q(\m_axi_wdata[127] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_125 ),
.Q(\m_axi_wdata[127] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_143 ),
.Q(\m_axi_wdata[127] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_124 ),
.Q(\m_axi_wdata[127] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_123 ),
.Q(\m_axi_wdata[127] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_122 ),
.Q(\m_axi_wdata[127] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_121 ),
.Q(\m_axi_wdata[127] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_120 ),
.Q(\m_axi_wdata[127] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_119 ),
.Q(\m_axi_wdata[127] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_118 ),
.Q(\m_axi_wdata[127] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_117 ),
.Q(\m_axi_wdata[127] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_116 ),
.Q(\m_axi_wdata[127] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_115 ),
.Q(\m_axi_wdata[127] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_142 ),
.Q(\m_axi_wdata[127] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_114 ),
.Q(\m_axi_wdata[127] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_113 ),
.Q(\m_axi_wdata[127] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_112 ),
.Q(\m_axi_wdata[127] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_111 ),
.Q(\m_axi_wdata[127] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_110 ),
.Q(\m_axi_wdata[127] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_109 ),
.Q(\m_axi_wdata[127] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_108 ),
.Q(\m_axi_wdata[127] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_107 ),
.Q(\m_axi_wdata[127] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_106 ),
.Q(\m_axi_wdata[127] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_105 ),
.Q(\m_axi_wdata[127] [39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_141 ),
.Q(\m_axi_wdata[127] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_104 ),
.Q(\m_axi_wdata[127] [40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_103 ),
.Q(\m_axi_wdata[127] [41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_102 ),
.Q(\m_axi_wdata[127] [42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_101 ),
.Q(\m_axi_wdata[127] [43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_100 ),
.Q(\m_axi_wdata[127] [44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_99 ),
.Q(\m_axi_wdata[127] [45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_98 ),
.Q(\m_axi_wdata[127] [46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_97 ),
.Q(\m_axi_wdata[127] [47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_96 ),
.Q(\m_axi_wdata[127] [48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_95 ),
.Q(\m_axi_wdata[127] [49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_140 ),
.Q(\m_axi_wdata[127] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_94 ),
.Q(\m_axi_wdata[127] [50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_93 ),
.Q(\m_axi_wdata[127] [51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_92 ),
.Q(\m_axi_wdata[127] [52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_91 ),
.Q(\m_axi_wdata[127] [53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_90 ),
.Q(\m_axi_wdata[127] [54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_89 ),
.Q(\m_axi_wdata[127] [55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_88 ),
.Q(\m_axi_wdata[127] [56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_87 ),
.Q(\m_axi_wdata[127] [57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[58]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_86 ),
.Q(\m_axi_wdata[127] [58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[59]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_85 ),
.Q(\m_axi_wdata[127] [59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_139 ),
.Q(\m_axi_wdata[127] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[60]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_84 ),
.Q(\m_axi_wdata[127] [60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[61]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_83 ),
.Q(\m_axi_wdata[127] [61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[62]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_82 ),
.Q(\m_axi_wdata[127] [62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[63]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_81 ),
.Q(\m_axi_wdata[127] [63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[64]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_80 ),
.Q(\m_axi_wdata[127] [64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[65]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_79 ),
.Q(\m_axi_wdata[127] [65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[66]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_78 ),
.Q(\m_axi_wdata[127] [66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[67]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_77 ),
.Q(\m_axi_wdata[127] [67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[68]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_76 ),
.Q(\m_axi_wdata[127] [68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[69]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_75 ),
.Q(\m_axi_wdata[127] [69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_138 ),
.Q(\m_axi_wdata[127] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[70]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_74 ),
.Q(\m_axi_wdata[127] [70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[71]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_73 ),
.Q(\m_axi_wdata[127] [71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[72]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_72 ),
.Q(\m_axi_wdata[127] [72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[73]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_71 ),
.Q(\m_axi_wdata[127] [73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[74]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_70 ),
.Q(\m_axi_wdata[127] [74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[75]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_69 ),
.Q(\m_axi_wdata[127] [75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[76]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_68 ),
.Q(\m_axi_wdata[127] [76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[77]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_67 ),
.Q(\m_axi_wdata[127] [77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[78]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_66 ),
.Q(\m_axi_wdata[127] [78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[79]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_65 ),
.Q(\m_axi_wdata[127] [79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_137 ),
.Q(\m_axi_wdata[127] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[80]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_64 ),
.Q(\m_axi_wdata[127] [80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[81]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_63 ),
.Q(\m_axi_wdata[127] [81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[82]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_62 ),
.Q(\m_axi_wdata[127] [82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[83]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_61 ),
.Q(\m_axi_wdata[127] [83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[84]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_60 ),
.Q(\m_axi_wdata[127] [84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[85]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_59 ),
.Q(\m_axi_wdata[127] [85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[86]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_58 ),
.Q(\m_axi_wdata[127] [86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[87]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(\m_axi_wdata[127] [87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[88]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(\m_axi_wdata[127] [88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[89]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(\m_axi_wdata[127] [89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_136 ),
.Q(\m_axi_wdata[127] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[90]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(\m_axi_wdata[127] [90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[91]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(\m_axi_wdata[127] [91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[92]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(\m_axi_wdata[127] [92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[93]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(\m_axi_wdata[127] [93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[94]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(\m_axi_wdata[127] [94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[95]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(\m_axi_wdata[127] [95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[96]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(\m_axi_wdata[127] [96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[97]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(\m_axi_wdata[127] [97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[98]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(\m_axi_wdata[127] [98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[99]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(\m_axi_wdata[127] [99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_135 ),
.Q(\m_axi_wdata[127] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory__parameterized1
(s_axi_bid,
s_axi_bresp,
m_aclk,
E,
m_axi_bresp,
m_axi_bid,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk,
out,
\gpregsm1.curr_fwft_state_reg[1]_0 ,
s_axi_bready);
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input m_aclk;
input [0:0]E;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
input [0:0]out;
input [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ;
input s_axi_bready;
wire [0:0]E;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_2 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire \goreg_dm.dout_i[0]_i_1_n_0 ;
wire \goreg_dm.dout_i[1]_i_1_n_0 ;
wire \goreg_dm.dout_i[2]_i_1_n_0 ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ;
wire m_aclk;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]out;
wire s_aclk;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
system_auto_cc_0_dmem__parameterized1 \gdm.dm_gen.dm
(.E(E),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.s_aclk(s_aclk));
LUT6 #(
.INIT(64'hEFEFFFEF20200020))
\goreg_dm.dout_i[0]_i_1
(.I0(\gdm.dm_gen.dm_n_2 ),
.I1(out),
.I2(\gpregsm1.curr_fwft_state_reg[1]_0 [1]),
.I3(\gpregsm1.curr_fwft_state_reg[1]_0 [0]),
.I4(s_axi_bready),
.I5(s_axi_bresp[0]),
.O(\goreg_dm.dout_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEFEFFFEF20200020))
\goreg_dm.dout_i[1]_i_1
(.I0(\gdm.dm_gen.dm_n_1 ),
.I1(out),
.I2(\gpregsm1.curr_fwft_state_reg[1]_0 [1]),
.I3(\gpregsm1.curr_fwft_state_reg[1]_0 [0]),
.I4(s_axi_bready),
.I5(s_axi_bresp[1]),
.O(\goreg_dm.dout_i[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEFEFFFEF20200020))
\goreg_dm.dout_i[2]_i_1
(.I0(\gdm.dm_gen.dm_n_0 ),
.I1(out),
.I2(\gpregsm1.curr_fwft_state_reg[1]_0 [1]),
.I3(\gpregsm1.curr_fwft_state_reg[1]_0 [0]),
.I4(s_axi_bready),
.I5(s_axi_bid),
.O(\goreg_dm.dout_i[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\goreg_dm.dout_i[0]_i_1_n_0 ),
.Q(s_axi_bresp[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(\goreg_dm.dout_i[1]_i_1_n_0 ),
.Q(s_axi_bresp[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(\goreg_dm.dout_i[2]_i_1_n_0 ),
.Q(s_axi_bid),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory__parameterized2
(\s_axi_rid[0] ,
m_aclk,
E,
I127,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [131:0]\s_axi_rid[0] ;
input m_aclk;
input [0:0]E;
input [131:0]I127;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [131:0]I127;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_100 ;
wire \gdm.dm_gen.dm_n_101 ;
wire \gdm.dm_gen.dm_n_102 ;
wire \gdm.dm_gen.dm_n_103 ;
wire \gdm.dm_gen.dm_n_104 ;
wire \gdm.dm_gen.dm_n_105 ;
wire \gdm.dm_gen.dm_n_106 ;
wire \gdm.dm_gen.dm_n_107 ;
wire \gdm.dm_gen.dm_n_108 ;
wire \gdm.dm_gen.dm_n_109 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_110 ;
wire \gdm.dm_gen.dm_n_111 ;
wire \gdm.dm_gen.dm_n_112 ;
wire \gdm.dm_gen.dm_n_113 ;
wire \gdm.dm_gen.dm_n_114 ;
wire \gdm.dm_gen.dm_n_115 ;
wire \gdm.dm_gen.dm_n_116 ;
wire \gdm.dm_gen.dm_n_117 ;
wire \gdm.dm_gen.dm_n_118 ;
wire \gdm.dm_gen.dm_n_119 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_120 ;
wire \gdm.dm_gen.dm_n_121 ;
wire \gdm.dm_gen.dm_n_122 ;
wire \gdm.dm_gen.dm_n_123 ;
wire \gdm.dm_gen.dm_n_124 ;
wire \gdm.dm_gen.dm_n_125 ;
wire \gdm.dm_gen.dm_n_126 ;
wire \gdm.dm_gen.dm_n_127 ;
wire \gdm.dm_gen.dm_n_128 ;
wire \gdm.dm_gen.dm_n_129 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_130 ;
wire \gdm.dm_gen.dm_n_131 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_58 ;
wire \gdm.dm_gen.dm_n_59 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_60 ;
wire \gdm.dm_gen.dm_n_61 ;
wire \gdm.dm_gen.dm_n_62 ;
wire \gdm.dm_gen.dm_n_63 ;
wire \gdm.dm_gen.dm_n_64 ;
wire \gdm.dm_gen.dm_n_65 ;
wire \gdm.dm_gen.dm_n_66 ;
wire \gdm.dm_gen.dm_n_67 ;
wire \gdm.dm_gen.dm_n_68 ;
wire \gdm.dm_gen.dm_n_69 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_70 ;
wire \gdm.dm_gen.dm_n_71 ;
wire \gdm.dm_gen.dm_n_72 ;
wire \gdm.dm_gen.dm_n_73 ;
wire \gdm.dm_gen.dm_n_74 ;
wire \gdm.dm_gen.dm_n_75 ;
wire \gdm.dm_gen.dm_n_76 ;
wire \gdm.dm_gen.dm_n_77 ;
wire \gdm.dm_gen.dm_n_78 ;
wire \gdm.dm_gen.dm_n_79 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_80 ;
wire \gdm.dm_gen.dm_n_81 ;
wire \gdm.dm_gen.dm_n_82 ;
wire \gdm.dm_gen.dm_n_83 ;
wire \gdm.dm_gen.dm_n_84 ;
wire \gdm.dm_gen.dm_n_85 ;
wire \gdm.dm_gen.dm_n_86 ;
wire \gdm.dm_gen.dm_n_87 ;
wire \gdm.dm_gen.dm_n_88 ;
wire \gdm.dm_gen.dm_n_89 ;
wire \gdm.dm_gen.dm_n_9 ;
wire \gdm.dm_gen.dm_n_90 ;
wire \gdm.dm_gen.dm_n_91 ;
wire \gdm.dm_gen.dm_n_92 ;
wire \gdm.dm_gen.dm_n_93 ;
wire \gdm.dm_gen.dm_n_94 ;
wire \gdm.dm_gen.dm_n_95 ;
wire \gdm.dm_gen.dm_n_96 ;
wire \gdm.dm_gen.dm_n_97 ;
wire \gdm.dm_gen.dm_n_98 ;
wire \gdm.dm_gen.dm_n_99 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
wire [131:0]\s_axi_rid[0] ;
system_auto_cc_0_dmem__parameterized2 \gdm.dm_gen.dm
(.E(E),
.I127(I127),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 ,\gdm.dm_gen.dm_n_58 ,\gdm.dm_gen.dm_n_59 ,\gdm.dm_gen.dm_n_60 ,\gdm.dm_gen.dm_n_61 ,\gdm.dm_gen.dm_n_62 ,\gdm.dm_gen.dm_n_63 ,\gdm.dm_gen.dm_n_64 ,\gdm.dm_gen.dm_n_65 ,\gdm.dm_gen.dm_n_66 ,\gdm.dm_gen.dm_n_67 ,\gdm.dm_gen.dm_n_68 ,\gdm.dm_gen.dm_n_69 ,\gdm.dm_gen.dm_n_70 ,\gdm.dm_gen.dm_n_71 ,\gdm.dm_gen.dm_n_72 ,\gdm.dm_gen.dm_n_73 ,\gdm.dm_gen.dm_n_74 ,\gdm.dm_gen.dm_n_75 ,\gdm.dm_gen.dm_n_76 ,\gdm.dm_gen.dm_n_77 ,\gdm.dm_gen.dm_n_78 ,\gdm.dm_gen.dm_n_79 ,\gdm.dm_gen.dm_n_80 ,\gdm.dm_gen.dm_n_81 ,\gdm.dm_gen.dm_n_82 ,\gdm.dm_gen.dm_n_83 ,\gdm.dm_gen.dm_n_84 ,\gdm.dm_gen.dm_n_85 ,\gdm.dm_gen.dm_n_86 ,\gdm.dm_gen.dm_n_87 ,\gdm.dm_gen.dm_n_88 ,\gdm.dm_gen.dm_n_89 ,\gdm.dm_gen.dm_n_90 ,\gdm.dm_gen.dm_n_91 ,\gdm.dm_gen.dm_n_92 ,\gdm.dm_gen.dm_n_93 ,\gdm.dm_gen.dm_n_94 ,\gdm.dm_gen.dm_n_95 ,\gdm.dm_gen.dm_n_96 ,\gdm.dm_gen.dm_n_97 ,\gdm.dm_gen.dm_n_98 ,\gdm.dm_gen.dm_n_99 ,\gdm.dm_gen.dm_n_100 ,\gdm.dm_gen.dm_n_101 ,\gdm.dm_gen.dm_n_102 ,\gdm.dm_gen.dm_n_103 ,\gdm.dm_gen.dm_n_104 ,\gdm.dm_gen.dm_n_105 ,\gdm.dm_gen.dm_n_106 ,\gdm.dm_gen.dm_n_107 ,\gdm.dm_gen.dm_n_108 ,\gdm.dm_gen.dm_n_109 ,\gdm.dm_gen.dm_n_110 ,\gdm.dm_gen.dm_n_111 ,\gdm.dm_gen.dm_n_112 ,\gdm.dm_gen.dm_n_113 ,\gdm.dm_gen.dm_n_114 ,\gdm.dm_gen.dm_n_115 ,\gdm.dm_gen.dm_n_116 ,\gdm.dm_gen.dm_n_117 ,\gdm.dm_gen.dm_n_118 ,\gdm.dm_gen.dm_n_119 ,\gdm.dm_gen.dm_n_120 ,\gdm.dm_gen.dm_n_121 ,\gdm.dm_gen.dm_n_122 ,\gdm.dm_gen.dm_n_123 ,\gdm.dm_gen.dm_n_124 ,\gdm.dm_gen.dm_n_125 ,\gdm.dm_gen.dm_n_126 ,\gdm.dm_gen.dm_n_127 ,\gdm.dm_gen.dm_n_128 ,\gdm.dm_gen.dm_n_129 ,\gdm.dm_gen.dm_n_130 ,\gdm.dm_gen.dm_n_131 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_131 ),
.Q(\s_axi_rid[0] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[100]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\s_axi_rid[0] [100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[101]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\s_axi_rid[0] [101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[102]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\s_axi_rid[0] [102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[103]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\s_axi_rid[0] [103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[104]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\s_axi_rid[0] [104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[105]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\s_axi_rid[0] [105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[106]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\s_axi_rid[0] [106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[107]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\s_axi_rid[0] [107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[108]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\s_axi_rid[0] [108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[109]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\s_axi_rid[0] [109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_121 ),
.Q(\s_axi_rid[0] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[110]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\s_axi_rid[0] [110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[111]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\s_axi_rid[0] [111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[112]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\s_axi_rid[0] [112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[113]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\s_axi_rid[0] [113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[114]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\s_axi_rid[0] [114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[115]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\s_axi_rid[0] [115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[116]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\s_axi_rid[0] [116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[117]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\s_axi_rid[0] [117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[118]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\s_axi_rid[0] [118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[119]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\s_axi_rid[0] [119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_120 ),
.Q(\s_axi_rid[0] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[120]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\s_axi_rid[0] [120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[121]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\s_axi_rid[0] [121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[122]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\s_axi_rid[0] [122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[123]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\s_axi_rid[0] [123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[124]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\s_axi_rid[0] [124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[125]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\s_axi_rid[0] [125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[126]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\s_axi_rid[0] [126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[127]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\s_axi_rid[0] [127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[128]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\s_axi_rid[0] [128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[129]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\s_axi_rid[0] [129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_119 ),
.Q(\s_axi_rid[0] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[130]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\s_axi_rid[0] [130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[131]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\s_axi_rid[0] [131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_118 ),
.Q(\s_axi_rid[0] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_117 ),
.Q(\s_axi_rid[0] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_116 ),
.Q(\s_axi_rid[0] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_115 ),
.Q(\s_axi_rid[0] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_114 ),
.Q(\s_axi_rid[0] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_113 ),
.Q(\s_axi_rid[0] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_112 ),
.Q(\s_axi_rid[0] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_130 ),
.Q(\s_axi_rid[0] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_111 ),
.Q(\s_axi_rid[0] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_110 ),
.Q(\s_axi_rid[0] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_109 ),
.Q(\s_axi_rid[0] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_108 ),
.Q(\s_axi_rid[0] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_107 ),
.Q(\s_axi_rid[0] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_106 ),
.Q(\s_axi_rid[0] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_105 ),
.Q(\s_axi_rid[0] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_104 ),
.Q(\s_axi_rid[0] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_103 ),
.Q(\s_axi_rid[0] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_102 ),
.Q(\s_axi_rid[0] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_129 ),
.Q(\s_axi_rid[0] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_101 ),
.Q(\s_axi_rid[0] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_100 ),
.Q(\s_axi_rid[0] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_99 ),
.Q(\s_axi_rid[0] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_98 ),
.Q(\s_axi_rid[0] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_97 ),
.Q(\s_axi_rid[0] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_96 ),
.Q(\s_axi_rid[0] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_95 ),
.Q(\s_axi_rid[0] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_94 ),
.Q(\s_axi_rid[0] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_93 ),
.Q(\s_axi_rid[0] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_92 ),
.Q(\s_axi_rid[0] [39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_128 ),
.Q(\s_axi_rid[0] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_91 ),
.Q(\s_axi_rid[0] [40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_90 ),
.Q(\s_axi_rid[0] [41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_89 ),
.Q(\s_axi_rid[0] [42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_88 ),
.Q(\s_axi_rid[0] [43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_87 ),
.Q(\s_axi_rid[0] [44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_86 ),
.Q(\s_axi_rid[0] [45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_85 ),
.Q(\s_axi_rid[0] [46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_84 ),
.Q(\s_axi_rid[0] [47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_83 ),
.Q(\s_axi_rid[0] [48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_82 ),
.Q(\s_axi_rid[0] [49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_127 ),
.Q(\s_axi_rid[0] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_81 ),
.Q(\s_axi_rid[0] [50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_80 ),
.Q(\s_axi_rid[0] [51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_79 ),
.Q(\s_axi_rid[0] [52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_78 ),
.Q(\s_axi_rid[0] [53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_77 ),
.Q(\s_axi_rid[0] [54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_76 ),
.Q(\s_axi_rid[0] [55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_75 ),
.Q(\s_axi_rid[0] [56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_74 ),
.Q(\s_axi_rid[0] [57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[58]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_73 ),
.Q(\s_axi_rid[0] [58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[59]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_72 ),
.Q(\s_axi_rid[0] [59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_126 ),
.Q(\s_axi_rid[0] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[60]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_71 ),
.Q(\s_axi_rid[0] [60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[61]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_70 ),
.Q(\s_axi_rid[0] [61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[62]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_69 ),
.Q(\s_axi_rid[0] [62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[63]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_68 ),
.Q(\s_axi_rid[0] [63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[64]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_67 ),
.Q(\s_axi_rid[0] [64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[65]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_66 ),
.Q(\s_axi_rid[0] [65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[66]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_65 ),
.Q(\s_axi_rid[0] [66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[67]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_64 ),
.Q(\s_axi_rid[0] [67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[68]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_63 ),
.Q(\s_axi_rid[0] [68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[69]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_62 ),
.Q(\s_axi_rid[0] [69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_125 ),
.Q(\s_axi_rid[0] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[70]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_61 ),
.Q(\s_axi_rid[0] [70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[71]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_60 ),
.Q(\s_axi_rid[0] [71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[72]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_59 ),
.Q(\s_axi_rid[0] [72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[73]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_58 ),
.Q(\s_axi_rid[0] [73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[74]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(\s_axi_rid[0] [74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[75]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(\s_axi_rid[0] [75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[76]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(\s_axi_rid[0] [76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[77]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(\s_axi_rid[0] [77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[78]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(\s_axi_rid[0] [78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[79]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(\s_axi_rid[0] [79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_124 ),
.Q(\s_axi_rid[0] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[80]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(\s_axi_rid[0] [80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[81]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(\s_axi_rid[0] [81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[82]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(\s_axi_rid[0] [82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[83]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(\s_axi_rid[0] [83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[84]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(\s_axi_rid[0] [84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[85]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(\s_axi_rid[0] [85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[86]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(\s_axi_rid[0] [86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[87]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(\s_axi_rid[0] [87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[88]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(\s_axi_rid[0] [88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[89]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(\s_axi_rid[0] [89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_123 ),
.Q(\s_axi_rid[0] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[90]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(\s_axi_rid[0] [90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[91]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(\s_axi_rid[0] [91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[92]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(\s_axi_rid[0] [92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[93]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\s_axi_rid[0] [93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[94]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\s_axi_rid[0] [94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[95]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\s_axi_rid[0] [95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[96]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\s_axi_rid[0] [96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[97]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\s_axi_rid[0] [97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[98]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\s_axi_rid[0] [98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[99]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\s_axi_rid[0] [99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_122 ),
.Q(\s_axi_rid[0] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire [3:0]plusOp__6;
wire ram_empty_i_i_2__2_n_0;
wire ram_empty_i_i_3__2_n_0;
wire ram_empty_i_reg;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__2
(.I0(Q[0]),
.O(plusOp__6[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__6[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__6[2]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__6[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.D(plusOp__6[0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__6[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__6[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__6[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__2
(.I0(ram_empty_i_i_2__2_n_0),
.I1(ram_empty_i_i_3__2_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__2_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_20
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp__0;
wire ram_empty_i_i_2__0_n_0;
wire ram_empty_i_i_3__0_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__0
(.I0(Q[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__0[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp__0[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__0
(.I0(ram_empty_i_i_2__0_n_0),
.I1(ram_empty_i_i_3__0_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__0_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_41
(Q,
ram_empty_i_reg,
\gnxpm_cdc.rd_pntr_gc_reg[2] ,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [0:0]E;
wire [3:0]Q;
wire [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp;
wire ram_empty_i_i_2_n_0;
wire ram_empty_i_i_3_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1
(.I0(ram_empty_i_i_2_n_0),
.I1(ram_empty_i_i_3_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_62
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
s_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]out;
wire [3:0]plusOp__8;
wire ram_empty_i_i_2__3_n_0;
wire ram_empty_i_i_3__3_n_0;
wire ram_empty_i_reg;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__3
(.I0(Q[0]),
.O(plusOp__8[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__3
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__8[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__3
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__8[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__3
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__8[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.D(plusOp__8[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__3
(.I0(ram_empty_i_i_2__3_n_0),
.I1(ram_empty_i_i_3__3_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__3_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_86
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp__2;
wire ram_empty_i_i_2__1_n_0;
wire ram_empty_i_i_3__1_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__1
(.I0(Q[0]),
.O(plusOp__2[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__2[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__2[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__2[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp__2[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__1
(.I0(ram_empty_i_i_2__1_n_0),
.I1(ram_empty_i_i_3__1_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__1_n_0));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft
(out,
ram_empty_i_reg,
E,
s_axi_bvalid,
s_aclk,
AR,
s_axi_bready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output [1:0]out;
output ram_empty_i_reg;
output [0:0]E;
output s_axi_bvalid;
input s_aclk;
input [0:0]AR;
input s_axi_bready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]AR;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [1:0]next_fwft_state;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire s_aclk;
wire s_axi_bready;
wire s_axi_bvalid;
(* DONT_TOUCH *) wire user_valid;
assign out[1:0] = curr_fwft_state;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__2
(.I0(ram_empty_fb_i_reg),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(AR),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(AR),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__2
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_bready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(AR),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__2
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_bready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(AR),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(AR),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(s_axi_bready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
LUT1 #(
.INIT(2'h1))
s_axi_bvalid_INST_0
(.I0(empty_fwft_i),
.O(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_18
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[144] ,
m_axi_wvalid,
m_aclk,
out,
m_axi_wready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[144] ;
output m_axi_wvalid;
input m_aclk;
input [1:0]out;
input m_axi_wready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[144] ;
wire m_aclk;
wire m_axi_wready;
wire m_axi_wvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__0
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__0
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__0
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[144]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(\goreg_dm.dout_i_reg[144] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_wready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_wvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_wvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_39
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[57] ,
m_axi_awvalid,
m_aclk,
out,
m_axi_awready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output m_axi_awvalid;
input m_aclk;
input [1:0]out;
input m_axi_awready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[57]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(\goreg_dm.dout_i_reg[57] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_awready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_awvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_awvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_60
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[131] ,
s_axi_rvalid,
s_aclk,
out,
s_axi_rready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[131] ;
output s_axi_rvalid;
input s_aclk;
input [1:0]out;
input s_axi_rready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[131] ;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire s_aclk;
wire s_axi_rready;
wire s_axi_rvalid;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__3
(.I0(ram_empty_fb_i_reg),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__3
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__3
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[131]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(\goreg_dm.dout_i_reg[131] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(s_axi_rready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
LUT1 #(
.INIT(2'h1))
s_axi_rvalid_INST_0
(.I0(empty_fwft_i),
.O(s_axi_rvalid));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_84
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[57] ,
m_axi_arvalid,
m_aclk,
out,
m_axi_arready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output m_axi_arvalid;
input m_aclk;
input [1:0]out;
input m_axi_arready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire m_aclk;
wire m_axi_arready;
wire m_axi_arvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__1
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__1
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__1
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[57]_i_1__0
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(\goreg_dm.dout_i_reg[57] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_arready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_arvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_arvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic
(out,
Q,
E,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
s_axi_bvalid,
s_aclk,
AR,
s_axi_bready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [1:0]out;
output [2:0]Q;
output [0:0]E;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output s_axi_bvalid;
input s_aclk;
input [0:0]AR;
input s_axi_bready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]AR;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gr1.gr1_int.rfwft_n_2 ;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
wire s_aclk;
wire s_axi_bready;
wire s_axi_bvalid;
system_auto_cc_0_rd_fwft \gr1.gr1_int.rfwft
(.AR(AR),
.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_2 ),
.s_aclk(s_aclk),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
system_auto_cc_0_rd_status_flags_as \gras.rsts
(.AR(AR),
.\gc0.count_d1_reg[2] (rpntr_n_4),
.out(p_2_out),
.s_aclk(s_aclk));
system_auto_cc_0_rd_bin_cntr rpntr
(.AR(AR),
.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_2 ),
.ram_empty_i_reg(rpntr_n_4),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_28
(Q,
E,
\goreg_dm.dout_i_reg[57] ,
\gnxpm_cdc.rd_pntr_gc_reg[2] ,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_awvalid,
m_aclk,
out,
m_axi_awready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_awvalid;
input m_aclk;
input [1:0]out;
input m_axi_awready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]E;
wire [2:0]Q;
wire [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
system_auto_cc_0_rd_fwft_39 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[57] (\goreg_dm.dout_i_reg[57] ),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
system_auto_cc_0_rd_status_flags_as_40 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
system_auto_cc_0_rd_bin_cntr_41 rpntr
(.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[2] (\gnxpm_cdc.rd_pntr_gc_reg[2] ),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_49
(Q,
E,
\goreg_dm.dout_i_reg[131] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
s_axi_rvalid,
s_aclk,
out,
s_axi_rready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[131] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output s_axi_rvalid;
input s_aclk;
input [1:0]out;
input s_axi_rready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[131] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
wire s_aclk;
wire s_axi_rready;
wire s_axi_rvalid;
system_auto_cc_0_rd_fwft_60 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[131] (\goreg_dm.dout_i_reg[131] ),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ),
.s_aclk(s_aclk),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
system_auto_cc_0_rd_status_flags_as_61 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out),
.s_aclk(s_aclk));
system_auto_cc_0_rd_bin_cntr_62 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_7
(Q,
E,
\goreg_dm.dout_i_reg[144] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_wvalid,
m_aclk,
out,
m_axi_wready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[144] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_wvalid;
input m_aclk;
input [1:0]out;
input m_axi_wready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[144] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_wready;
wire m_axi_wvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
system_auto_cc_0_rd_fwft_18 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[144] (\goreg_dm.dout_i_reg[144] ),
.m_aclk(m_aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
system_auto_cc_0_rd_status_flags_as_19 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
system_auto_cc_0_rd_bin_cntr_20 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_71
(Q,
E,
\goreg_dm.dout_i_reg[57] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_arvalid,
m_aclk,
out,
m_axi_arready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_arvalid;
input m_aclk;
input [1:0]out;
input m_axi_arready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_arready;
wire m_axi_arvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
system_auto_cc_0_rd_fwft_84 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[57] (\goreg_dm.dout_i_reg[57] ),
.m_aclk(m_aclk),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
system_auto_cc_0_rd_status_flags_as_85 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
system_auto_cc_0_rd_bin_cntr_86 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as
(out,
\gc0.count_d1_reg[2] ,
s_aclk,
AR);
output out;
input \gc0.count_d1_reg[2] ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire \gc0.count_d1_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire s_aclk;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(AR),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_19
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_40
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_61
(out,
\gc0.count_d1_reg[2] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire s_aclk;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_85
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
s_aclk,
m_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input s_aclk;
input m_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_3 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_4 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_5 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.m_aclk(m_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_30
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_31 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_32 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_33 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_34 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_35 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff_36 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_51
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ,
s_aclk,
m_aclk,
s_aresetn);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
output \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ;
input s_aclk;
input m_aclk;
input s_aresetn;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_52 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_53 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_54 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_55 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_56 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_57 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.m_aclk(m_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_74
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_75 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_76 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_77 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_78 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_79 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff_80 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_9
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_10 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_11 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_12 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_13 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_14 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff_15 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_1
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_10
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_11
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_12
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_13
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_14
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_15
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_2
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_3
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_31
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_32
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_33
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_34
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_35
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_36
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_4
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_5
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_52
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_53
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_54
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_55
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_56
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_57
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_75
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_76
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_77
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_78
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_79
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_80
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0
(D,
Q,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_21
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_42
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_63
(D,
Q,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_87
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1
(D,
Q,
m_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_22
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_43
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_64
(D,
Q,
m_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_88
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_23
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_44
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_65
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_89
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_24
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_45
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_66
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_90
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_25
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_46
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_67
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_91
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_26
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_47
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_68
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_92
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
m_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire [3:0]plusOp__1;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__1[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__1[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.D(plusOp__1[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_17
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__5;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__2
(.I0(Q[0]),
.O(plusOp__5[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__5[1]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__5[2]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__5[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__5[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_38
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__4;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__1
(.I0(Q[0]),
.O(plusOp__4[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__4[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__4[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__4[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__4[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_59
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
m_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire [3:0]plusOp__3;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__0
(.I0(Q[0]),
.O(plusOp__3[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__3[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__3[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__3[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.D(plusOp__3[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_83
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__7;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__3
(.I0(Q[0]),
.O(plusOp__7[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__3
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__7[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__3
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__7[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__3
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__7[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__7[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic
(Q,
ram_full_fb_i_reg,
E,
m_axi_bready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_bvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output m_axi_bready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_bvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire m_axi_bready;
wire m_axi_bvalid;
wire out;
wire ram_full_fb_i_reg;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.m_aclk(m_aclk),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg));
system_auto_cc_0_wr_bin_cntr wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.m_aclk(m_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_29
(Q,
ram_full_fb_i_reg,
E,
s_axi_awready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_awvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_awready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_awvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_37 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
system_auto_cc_0_wr_bin_cntr_38 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_50
(Q,
ram_full_fb_i_reg,
E,
m_axi_rready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_rvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output m_axi_rready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_rvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire out;
wire ram_full_fb_i_reg;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_58 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg));
system_auto_cc_0_wr_bin_cntr_59 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.m_aclk(m_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_72
(Q,
ram_full_fb_i_reg,
E,
s_axi_arready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_arvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_arready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_arvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_82 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
system_auto_cc_0_wr_bin_cntr_83 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_8
(Q,
ram_full_fb_i_reg,
E,
s_axi_wready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_wvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_wready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_wvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_16 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
system_auto_cc_0_wr_bin_cntr_17 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as
(ram_full_fb_i_reg_0,
E,
m_axi_bready,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_bvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output m_axi_bready;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_bvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire m_aclk;
wire m_axi_bready;
wire m_axi_bvalid;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1
(.I0(m_axi_bvalid),
.I1(ram_full_fb_i),
.O(E));
LUT1 #(
.INIT(2'h1))
m_axi_bready_INST_0
(.I0(ram_full_i),
.O(m_axi_bready));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3
(.I0(ram_full_fb_i),
.I1(m_axi_bvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_16
(ram_full_fb_i_reg_0,
E,
s_axi_wready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_wvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_wready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_wvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__2
(.I0(s_axi_wvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__2
(.I0(ram_full_fb_i),
.I1(s_axi_wvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_wready_INST_0
(.I0(ram_full_i),
.O(s_axi_wready));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_37
(ram_full_fb_i_reg_0,
E,
s_axi_awready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_awvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_awready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_awvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__1
(.I0(s_axi_awvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__1
(.I0(ram_full_fb_i),
.I1(s_axi_awvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_awready_INST_0
(.I0(ram_full_i),
.O(s_axi_awready));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_58
(ram_full_fb_i_reg_0,
E,
m_axi_rready,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_rvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output m_axi_rready;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_rvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__0
(.I0(m_axi_rvalid),
.I1(ram_full_fb_i),
.O(E));
LUT1 #(
.INIT(2'h1))
m_axi_rready_INST_0
(.I0(ram_full_i),
.O(m_axi_rready));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__0
(.I0(ram_full_fb_i),
.I1(m_axi_rvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_82
(ram_full_fb_i_reg_0,
E,
s_axi_arready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_arvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_arready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_arvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__3
(.I0(s_axi_arvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__3
(.I0(ram_full_fb_i),
.I1(s_axi_arvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_arready_INST_0
(.I0(ram_full_i),
.O(s_axi_arready));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module wg_resource_table (/*AUTOARG*/
// Outputs
wg_res_tbl_wg_slot_id, wg_res_tbl_wg_count_out,
// Inputs
rst, clk, wg_res_tbl_alloc_en, wg_res_tbl_dealloc_en,
wg_res_tbl_cu_id, wg_res_tbl_wg_id, wg_res_tbl_alloc_wg_wf_count,
wg_res_tbl_inflight_res_tbl_id
) ;
parameter NUMBER_CU = 64;
parameter CU_ID_WIDTH = 6;
parameter WG_ID_WIDTH = 10;
parameter WF_COUNT_WIDTH = 4;
parameter WG_SLOT_ID_WIDTH = 6;
parameter NUMBER_WF_SLOTS = 40;
parameter RES_TABLE_ADDR_WIDTH = 3;
localparam NUMBER_RES_TABLES = 2**RES_TABLE_ADDR_WIDTH;
input rst,clk;
input wg_res_tbl_alloc_en, wg_res_tbl_dealloc_en;
input [CU_ID_WIDTH-1:0] wg_res_tbl_cu_id;
input [WG_ID_WIDTH-1:0] wg_res_tbl_wg_id;
input [WF_COUNT_WIDTH-1:0] wg_res_tbl_alloc_wg_wf_count;
output [WG_SLOT_ID_WIDTH-1:0] wg_res_tbl_wg_slot_id;
input [RES_TABLE_ADDR_WIDTH-1:0] wg_res_tbl_inflight_res_tbl_id;
output [WG_SLOT_ID_WIDTH:0] wg_res_tbl_wg_count_out;
reg [NUMBER_CU-1:0] cu_initialized;
wire [NUMBER_WF_SLOTS-1:0] wg_slot_bitmap_out;
// Deallocation searching for the wg_slot_id
wire [WG_SLOT_ID_WIDTH-1:0] wg_slot_tbl_rd_data;
// allocation calculating wg_slot_id
reg alloc_calculated_wg_slot_valid;
reg [WG_SLOT_ID_WIDTH-1:0] alloc_calculated_wg_slot_id;
reg [CU_ID_WIDTH-1:0] alloc_calc_cu_id_calc,
alloc_calc_cu_id;
reg [WF_COUNT_WIDTH-1:0] alloc_calc_wf_count_calc,
alloc_calc_wf_count;
reg alloc_calc_wr_en;
reg [WG_ID_WIDTH-1:0] alloc_calc_wg_id, alloc_calc_wg_id_calc;
reg [WG_SLOT_ID_WIDTH-1:0] alloc_calc_wg_slot_data;
// Bitmap update
reg bitmap_update_allocating,
bitmap_update_deallocating;
reg [CU_ID_WIDTH-1:0] bitmap_update_cu_id_calc, bitmap_update_cu_id;
reg bitmap_update_wr_en;
reg [NUMBER_WF_SLOTS-1:0] bitmap_update_data_comb, bitmap_update_data ;
// wf count update
reg wf_count_update_alloc_en_calc,
wf_count_update_alloc_en_f1,
wf_count_update_alloc_en_f2,
wf_count_update_dealloc_en_calc,
wf_count_update_dealloc_en_f1,
wf_count_update_dealloc_en_f2;
reg wf_count_update_wr_en;
reg [CU_ID_WIDTH-1:0] wf_count_update_cu_id_calc,
wf_count_update_cu_id_f1,
wf_count_update_cu_id_f2,
wf_count_update_cu_id_f3;
reg [WG_SLOT_ID_WIDTH-1:0] wf_count_wg_slot_id_f1,
wf_count_wg_slot_id_f2,
wf_count_wg_slot_id_f3;
reg [WG_SLOT_ID_WIDTH:0] wf_count_update_wr_data,
wf_count_update_inflight_wr_data;
reg [WF_COUNT_WIDTH-1:0] wf_count_alloc_count_f1, wf_count_alloc_count_f2,
wf_count_alloc_count_calc;
wire [WF_COUNT_WIDTH-1:0] wf_count_dealloc_count;
wire [WG_SLOT_ID_WIDTH:0] wf_count_update_rd_data;
// ram that keeps information for inflight wf allocations/deallocations
// this is because there is a pipeline concurrent with this block that
// does not have a fixed number of cycles for execution
ram_2_port
#(
// Parameters
.WORD_SIZE (WG_SLOT_ID_WIDTH+1),
.ADDR_SIZE (RES_TABLE_ADDR_WIDTH),
.NUM_WORDS (NUMBER_RES_TABLES))
wf_slot_count_inflight_ram
(
// Outputs
.rd_word (wg_res_tbl_wg_count_out),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (wf_count_update_wr_en),
.wr_addr (wf_count_update_cu_id_f3
[CU_ID_WIDTH-1:CU_ID_WIDTH-RES_TABLE_ADDR_WIDTH]),
.wr_word (wf_count_update_inflight_wr_data),
.rd_en (1'b1),
.rd_addr (wg_res_tbl_inflight_res_tbl_id));
// ram that keeps track of the amount of wf currently allocated on each cu for
// each workgroup
ram_2_port
#(
// Parameters
.WORD_SIZE (WF_COUNT_WIDTH),
.ADDR_SIZE (WG_SLOT_ID_WIDTH+CU_ID_WIDTH),
.NUM_WORDS (NUMBER_WF_SLOTS*NUMBER_CU))
wf_slot_count_ram1
(
// Outputs
.rd_word (wf_count_dealloc_count),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (alloc_calc_wr_en),
.wr_addr ({alloc_calc_wg_slot_data,
alloc_calc_cu_id}),
.wr_word (alloc_calc_wf_count),
.rd_en (wf_count_update_dealloc_en_f1),
.rd_addr ({wf_count_wg_slot_id_f1,
wf_count_update_cu_id_f1}));
// ram that keeps track of the amount of free resources on each cu
ram_2_port
#(
// Parameters
.WORD_SIZE (WG_SLOT_ID_WIDTH+1),
.ADDR_SIZE (CU_ID_WIDTH),
.NUM_WORDS (NUMBER_CU))
wf_slot_used
(
// Outputs
.rd_word (wf_count_update_rd_data),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (wf_count_update_wr_en),
.wr_addr (wf_count_update_cu_id_f3),
.wr_word (wf_count_update_wr_data),
.rd_en ( wf_count_update_alloc_en_f1 |
wf_count_update_dealloc_en_f1),
.rd_addr (wf_count_update_cu_id_f1));
// Ram that keeps the wg slot bitmap
// A bit on the bitmap is set on allocation and cleared on deallocation
// Allocation reads it to generate a new wg_slot_id
ram_2_port
#(
// Parameters
.WORD_SIZE (NUMBER_WF_SLOTS),
.ADDR_SIZE (CU_ID_WIDTH),
.NUM_WORDS (NUMBER_CU))
wg_slot_bitmap_ram
(
// Outputs
.rd_word (wg_slot_bitmap_out),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (bitmap_update_wr_en),
.wr_addr (bitmap_update_cu_id),
.wr_word (bitmap_update_data),
.rd_en (wg_res_tbl_alloc_en | wg_res_tbl_dealloc_en),
.rd_addr (wg_res_tbl_cu_id));
// Ram to convert wg_id to wg_slot_id
// written on allocation and read by deallocation
ram_2_port
#(
// Parameters
.WORD_SIZE (WG_SLOT_ID_WIDTH),
.ADDR_SIZE (WG_ID_WIDTH),
.NUM_WORDS (2**WG_ID_WIDTH))
wg_id_to_wg_slot_id_ram
(
// Outputs
.rd_word (wg_slot_tbl_rd_data),
// Inputs
.rst (rst),
.clk (clk),
.wr_en (alloc_calc_wr_en),
.wr_addr (alloc_calc_wg_id),
.wr_word (alloc_calc_wg_slot_data),
.rd_en (wg_res_tbl_dealloc_en),
.rd_addr (wg_res_tbl_wg_id));
//////////////////////////////////////////////////////////
// clocked always block
//////////////////////////////////////////////////////////
always @( posedge clk or posedge rst ) begin
if (rst) begin
alloc_calculated_wg_slot_valid <= 0;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
alloc_calc_cu_id <= {CU_ID_WIDTH{1'b0}};
alloc_calc_cu_id_calc <= {CU_ID_WIDTH{1'b0}};
alloc_calc_wf_count <= {WF_COUNT_WIDTH{1'b0}};
alloc_calc_wf_count_calc <= {WF_COUNT_WIDTH{1'b0}};
alloc_calc_wg_id <= {WG_ID_WIDTH{1'b0}};
alloc_calc_wg_id_calc <= {WG_ID_WIDTH{1'b0}};
alloc_calc_wg_slot_data <= {WG_SLOT_ID_WIDTH{1'b0}};
alloc_calc_wr_en <= 1'h0;
bitmap_update_allocating <= 1'h0;
bitmap_update_cu_id <= {CU_ID_WIDTH{1'b0}};
bitmap_update_cu_id_calc <= {CU_ID_WIDTH{1'b0}};
bitmap_update_data <= {NUMBER_WF_SLOTS{1'b0}};
bitmap_update_deallocating <= 1'h0;
bitmap_update_wr_en <= 1'h0;
cu_initialized <= {NUMBER_CU{1'b0}};
wf_count_alloc_count_calc <= {WF_COUNT_WIDTH{1'b0}};
wf_count_alloc_count_f1 <= {WF_COUNT_WIDTH{1'b0}};
wf_count_alloc_count_f2 <= {WF_COUNT_WIDTH{1'b0}};
wf_count_update_alloc_en_calc <= 1'h0;
wf_count_update_alloc_en_f1 <= 1'h0;
wf_count_update_alloc_en_f2 <= 1'h0;
wf_count_update_cu_id_calc <= {CU_ID_WIDTH{1'b0}};
wf_count_update_cu_id_f1 <= {CU_ID_WIDTH{1'b0}};
wf_count_update_cu_id_f2 <= {CU_ID_WIDTH{1'b0}};
wf_count_update_cu_id_f3 <= {CU_ID_WIDTH{1'b0}};
wf_count_update_dealloc_en_calc <= 1'h0;
wf_count_update_dealloc_en_f1 <= 1'h0;
wf_count_update_dealloc_en_f2 <= 1'h0;
wf_count_update_inflight_wr_data <= {(1+(WG_SLOT_ID_WIDTH)){1'b0}};
wf_count_update_wr_data <= {(1+(WG_SLOT_ID_WIDTH)){1'b0}};
wf_count_update_wr_en <= 1'h0;
wf_count_wg_slot_id_f1 <= {WG_SLOT_ID_WIDTH{1'b0}};
wf_count_wg_slot_id_f2 <= {WG_SLOT_ID_WIDTH{1'b0}};
wf_count_wg_slot_id_f3 <= {WG_SLOT_ID_WIDTH{1'b0}};
// End of automatics
end
else begin
alloc_calculated_wg_slot_valid <= wg_res_tbl_alloc_en;
alloc_calc_wg_id_calc <= wg_res_tbl_wg_id;
alloc_calc_cu_id_calc <= wg_res_tbl_cu_id;
alloc_calc_wf_count_calc <= wg_res_tbl_alloc_wg_wf_count;
alloc_calc_wr_en <= alloc_calculated_wg_slot_valid;
alloc_calc_wg_id <= alloc_calc_wg_id_calc;
alloc_calc_cu_id <= alloc_calc_cu_id_calc;
alloc_calc_wg_slot_data <= alloc_calculated_wg_slot_id;
alloc_calc_wf_count <= alloc_calc_wf_count_calc;
bitmap_update_allocating <= wg_res_tbl_alloc_en;
bitmap_update_deallocating <= wg_res_tbl_dealloc_en;
bitmap_update_wr_en <= bitmap_update_allocating |
bitmap_update_deallocating;
// extra cycle delay to wait for wg_slot_id calculation
bitmap_update_cu_id_calc <= wg_res_tbl_cu_id;
bitmap_update_cu_id <= bitmap_update_cu_id_calc;
bitmap_update_data <= bitmap_update_data_comb;
// wf count logic - we can only update the wf count reg after we
// have calculated/searched the wf_id.
// extra cycle delay to wait for wg_slot_id calculation
wf_count_update_alloc_en_calc <= wg_res_tbl_alloc_en;
wf_count_update_dealloc_en_calc <= wg_res_tbl_dealloc_en;
wf_count_update_cu_id_calc <= wg_res_tbl_cu_id;
wf_count_alloc_count_calc <= wg_res_tbl_alloc_wg_wf_count;
// cycle when the wg_slots id are calculated
wf_count_update_alloc_en_f1 <= wf_count_update_alloc_en_calc;
wf_count_update_dealloc_en_f1 <= wf_count_update_dealloc_en_calc;
wf_count_update_cu_id_f1 <= wf_count_update_cu_id_calc;
if(wf_count_update_alloc_en_calc) begin
wf_count_wg_slot_id_f1 <= alloc_calculated_wg_slot_id;
end else begin
wf_count_wg_slot_id_f1 <= wg_slot_tbl_rd_data;
end // else: !if(wf_count_update_alloc_en_calc)
wf_count_alloc_count_f1 <= wf_count_alloc_count_calc;
// cycle when old data is read
wf_count_update_alloc_en_f2 <= wf_count_update_alloc_en_f1;
wf_count_update_dealloc_en_f2 <= wf_count_update_dealloc_en_f1;
wf_count_update_cu_id_f2 <= wf_count_update_cu_id_f1;
wf_count_wg_slot_id_f2 <= wf_count_wg_slot_id_f1;
wf_count_alloc_count_f2 <= wf_count_alloc_count_f1;
// cycle when update data is written
wf_count_update_cu_id_f3 <= wf_count_update_cu_id_f2;
wf_count_wg_slot_id_f3 <= wf_count_wg_slot_id_f2;
wf_count_update_wr_en <= wf_count_update_alloc_en_f2 |
wf_count_update_dealloc_en_f2;
if(wf_count_update_alloc_en_f2) begin
if(cu_initialized[wf_count_update_cu_id_f2]) begin
wf_count_update_inflight_wr_data <= NUMBER_WF_SLOTS -
(wf_count_update_rd_data + wf_count_alloc_count_f2);
wf_count_update_wr_data <= wf_count_update_rd_data +
wf_count_alloc_count_f2;
end
else begin
cu_initialized[wf_count_update_cu_id_f2] <= 1'b1;
wf_count_update_inflight_wr_data <= NUMBER_WF_SLOTS - wf_count_alloc_count_f2;
wf_count_update_wr_data <= wf_count_alloc_count_f2;
end
end
else begin
// No need to check for initialization here, if we are deallocing,
// we must have allocated at some point
wf_count_update_inflight_wr_data <= NUMBER_WF_SLOTS -
(wf_count_update_rd_data - wf_count_dealloc_count);
wf_count_update_wr_data <= wf_count_update_rd_data -
wf_count_dealloc_count;
end // else: !if(wf_count_update_alloc_en_f2)
end // else: !if(rst)
end // always @ ( posedge clk or posedge rst )
assign wg_res_tbl_wg_slot_id = (alloc_calculated_wg_slot_valid)?
alloc_calculated_wg_slot_id :
wg_slot_tbl_rd_data;
//////////////////////////////////////////////////////////
// priority encoder that generates the next wf_slot_id
//////////////////////////////////////////////////////////
always @ ( /*AUTOSENSE*/bitmap_update_allocating
or bitmap_update_cu_id_calc or bitmap_update_deallocating
or cu_initialized or wg_slot_bitmap_out
or wg_slot_tbl_rd_data) begin : PRI_ENC_NEXT_WF_SLOT_ID
integer wg_slot_i;
reg [WG_SLOT_ID_WIDTH-1:0] wg_slot_found;
reg wg_slot_valid;
reg [NUMBER_WF_SLOTS-1:0] wg_slot_bitmap_set, wg_slot_bitmap_clear;
wg_slot_bitmap_set = 0;
wg_slot_bitmap_clear = 0;
wg_slot_found = 0;
alloc_calculated_wg_slot_id = 0;
bitmap_update_data_comb = 0;
// clear the flag if it is deallocating the current wg
if(bitmap_update_deallocating)
wg_slot_bitmap_clear[wg_slot_tbl_rd_data] = 1'b1;
// priority encoder that takes the output of the bitmap table
// and generates the wg_slot_id
wg_slot_valid = 1'b0;
for (wg_slot_i = 0; wg_slot_i < NUMBER_WF_SLOTS; wg_slot_i = wg_slot_i + 1) begin
if((~wg_slot_bitmap_out[wg_slot_i]) && !wg_slot_valid) begin
wg_slot_valid = 1'b1;
wg_slot_found = wg_slot_i;
end
end
if(cu_initialized[bitmap_update_cu_id_calc]) begin
// set the flat if it is allocating the curreng wg
if(bitmap_update_allocating)
wg_slot_bitmap_set[wg_slot_found] = 1'b1;
// do the set and clear
bitmap_update_data_comb = (wg_slot_bitmap_out | wg_slot_bitmap_set) &
~wg_slot_bitmap_clear;
alloc_calculated_wg_slot_id = wg_slot_found;
end // if (cu_initialized[bitmap_update_cu_id_calc])
else begin
if(bitmap_update_allocating)
wg_slot_bitmap_set[0] = 1'b1;
// do the set and clear
bitmap_update_data_comb = wg_slot_bitmap_set;
alloc_calculated_wg_slot_id = 0;
end // else: !if(cu_initialized[bitmap_update_cu_id_calc])
end // block: PRI_ENC_NEXT_WF_SLOT_ID
endmodule // wg_resource_table
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EBUFN_2_V
`define SKY130_FD_SC_HD__EBUFN_2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ebufn_2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__ebufn_2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__EBUFN_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (clk);
input clk;
reg [0:0] d1;
reg [2:0] d3;
reg [7:0] d8;
wire [0:0] q1;
wire [2:0] q3;
wire [7:0] q8;
// verilator lint_off UNOPTFLAT
reg ena;
// verilator lint_on UNOPTFLAT
condff #(12) condff
(.clk(clk), .sen(1'b0), .ena(ena),
.d({d8,d3,d1}),
.q({q8,q3,q1}));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
//$write("%x %x %x %x\n", cyc, q8, q3, q1);
cyc <= cyc + 1;
if (cyc==1) begin
d1 <= 1'b1; d3<=3'h1; d8<=8'h11;
ena <= 1'b1;
end
if (cyc==2) begin
d1 <= 1'b0; d3<=3'h2; d8<=8'h33;
ena <= 1'b0;
end
if (cyc==3) begin
d1 <= 1'b1; d3<=3'h3; d8<=8'h44;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==4) begin
d1 <= 1'b1; d3<=3'h4; d8<=8'h77;
ena <= 1'b1;
if (q8 != 8'h11) $stop;
end
if (cyc==5) begin
d1 <= 1'b1; d3<=3'h0; d8<=8'h88;
ena <= 1'b1;
if (q8 != 8'h44) $stop;
end
if (cyc==6) begin
if (q8 != 8'h77) $stop;
end
if (cyc==7) begin
if (q8 != 8'h88) $stop;
end
//
if (cyc==20) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module condff (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
condffimp #(.WIDTH(WIDTH))
imp (.clk(clk), .sen(sen), .ena(ena), .d(d), .q(q));
endmodule
module condffimp (clk, sen, ena, d, q);
parameter WIDTH = 1;
input clk;
input sen;
input ena;
input [WIDTH-1:0] d;
output reg [WIDTH-1:0] q;
wire gatedclk;
clockgate clockgate (.clk(clk), .sen(sen), .ena(ena), .gatedclk(gatedclk));
always @(posedge gatedclk) begin
if (gatedclk === 1'bX) begin
q <= {WIDTH{1'bX}};
end
else begin
q <= d;
end
end
endmodule
module clockgate (clk, sen, ena, gatedclk);
input clk;
input sen;
input ena;
output gatedclk;
reg ena_b;
wire gatedclk = clk & ena_b;
// verilator lint_off COMBDLY
always @(clk or ena or sen) begin
if (~clk) begin
ena_b <= ena | sen;
end
else begin
if ((clk^sen)===1'bX) ena_b <= 1'bX;
end
end
// verilator lint_on COMBDLY
endmodule
|
/*
* integer3gt - a verilog test for integer greater-than conditional >
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module integer3gt;
integer a;
integer b;
reg error;
initial begin
error = 0;
a = 1;
if(a > 2) begin
$display("FAILED 1 > 2");
error = 1;
end // if (a < 2)
a = 2;
if(a > 2) begin
$display("FAILED 2 > 2");
error = 1;
end
a = 3;
if(a > 2) begin
b = 1;
end else begin
$display("FAILED 3 > 2");
error = 1;
end
b = 0;
for(a = 10; a > 5; a = a - 1) begin
b = b + a;
end
if(b != 40) begin
$display("FAILED forloop b=%d expected 40", b);
error = 1;
end
if(error == 0)
$display("PASSED");
$finish;
end // initial begin
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A222O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__A222O_BEHAVIORAL_PP_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a222o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
// Local signals
wire B2 and0_out ;
wire B2 and1_out ;
wire B2 and2_out ;
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
and and2 (and2_out , C1, C2 );
or or0 (or0_out_X , and1_out, and0_out, and2_out);
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND );
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A222O_BEHAVIORAL_PP_V |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_axic_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
// C_REG_CONFIG:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_gen.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
// Generate the ecc code. Note that the synthesizer should
// generate this as a static logic. Code in this block should
// never run during simulation phase, or directly impact timing.
//
// The code generated is a single correct, double detect code.
// It is the classic Hamming code. Instead, the code is
// optimized for minimal/balanced tree depth and size. See
// Hsiao IBM Technial Journal 1970.
//
// The code is returned as a single bit vector, h_rows. This was
// the only way to "subroutinize" this with the restrictions of
// disallowed include files and that matrices cannot be passed
// in ports.
//
// Factorial and the combos functions are defined. Combos
// simply computes the number of combinations from the set
// size and elements at a time.
//
// The function next_combo computes the next combination in
// lexicographical order given the "current" combination. Its
// output is undefined if given the last combination in the
// lexicographical order.
//
// next_combo is insensitive to the number of elements in the
// combinations.
//
// An H transpose matrix is generated because that's the easiest
// way to do it. The H transpose matrix is generated by taking
// the one at a time combinations, then the 3 at a time, then
// the 5 at a time. The number combinations used is equal to
// the width of the code (CODE_WIDTH). The boundaries between
// the 1, 3 and 5 groups are hardcoded in the for loop.
//
// At the same time the h_rows vector is generated from the
// H transpose matrix.
module mig_7series_v2_0_ecc_gen
#(
parameter CODE_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter DATA_WIDTH = 64
)
(
/*AUTOARG*/
// Outputs
h_rows
);
function integer factorial (input integer i);
integer index;
if (i == 1) factorial = 1;
else begin
factorial = 1;
for (index=2; index<=i; index=index+1)
factorial = factorial * index;
end
endfunction // factorial
function integer combos (input integer n, k);
combos = factorial(n)/(factorial(k)*factorial(n-k));
endfunction // combinations
// function next_combo
// Given a combination, return the next combo in lexicographical
// order. Scans from right to left. Assumes the first combination
// is k ones all of the way to the left.
//
// Upon entry, initialize seen0, trig1, and ones. "seen0" means
// that a zero has been observed while scanning from right to left.
// "trig1" means that a one have been observed _after_ seen0 is set.
// "ones" counts the number of ones observed while scanning the input.
//
// If trig1 is one, just copy the input bit to the output and increment
// to the next bit. Otherwise set the the output bit to zero, if the
// input is a one, increment ones. If the input bit is a one and seen0
// is true, dump out the accumulated ones. Set seen0 to the complement
// of the input bit. Note that seen0 is not used subsequent to trig1
// getting set.
function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i);
integer index;
integer dump_index;
reg seen0;
reg trig1;
// integer ones;
reg [ECC_WIDTH-1:0] ones;
begin
seen0 = 1'b0;
trig1 = 1'b0;
ones = 0;
for (index=0; index<ECC_WIDTH; index=index+1)
begin
// The "== 1'bx" is so this will converge at time zero.
// XST assumes false, which should be OK.
if ((&i == 1'bx) || trig1) next_combo[index] = i[index];
else begin
next_combo[index] = 1'b0;
ones = ones + i[index];
if (i[index] && seen0) begin
trig1 = 1'b1;
for (dump_index=index-1; dump_index>=0;dump_index=dump_index-1)
if (dump_index>=index-ones) next_combo[dump_index] = 1'b1;
end
seen0 = ~i[index];
end // else: !if(trig1)
end
end // function
endfunction // next_combo
wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0];
output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
localparam COMBOS_3 = combos(ECC_WIDTH, 3);
localparam COMBOS_5 = combos(ECC_WIDTH, 5);
genvar n;
genvar s;
generate
for (n=0; n<CODE_WIDTH; n=n+1) begin : ht
if (n == 0)
assign ht_matrix[n] = {{3{1'b1}}, {ECC_WIDTH-3{1'b0}}};
else if (n == COMBOS_3 && n < DATA_WIDTH)
assign ht_matrix[n] = {{5{1'b1}}, {ECC_WIDTH-5{1'b0}}};
else if ((n == COMBOS_3+COMBOS_5) && n < DATA_WIDTH)
assign ht_matrix[n] = {{7{1'b1}}, {ECC_WIDTH-7{1'b0}}};
else if (n == DATA_WIDTH)
assign ht_matrix[n] = {{1{1'b1}}, {ECC_WIDTH-1{1'b0}}};
else assign ht_matrix[n] = next_combo(ht_matrix[n-1]);
for (s=0; s<ECC_WIDTH; s=s+1) begin : h_row
assign h_rows[s*CODE_WIDTH+n] = ht_matrix[n][s];
end
end
endgenerate
endmodule // ecc_gen
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_addr_cmd_pads(
/*
config_data_in,
config_clock_in,
config_io_ena,
config_update,
*/
reset_n,
reset_n_afi_clk,
pll_hr_clk,
pll_avl_phy_clk,
pll_afi_clk,
pll_mem_clk,
pll_write_clk,
phy_ddio_address,
dll_delayctrl_in,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
phy_mem_ck,
phy_mem_ck_n
);
parameter DEVICE_FAMILY = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_BANK_WIDTH = "";
parameter AFI_CHIP_SELECT_WIDTH = "";
parameter AFI_CLK_EN_WIDTH = "";
parameter AFI_ODT_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter DLL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
/*
input config_data_in;
input config_clock_in;
input config_io_ena;
input config_update;
*/
input reset_n;
input reset_n_afi_clk;
input pll_afi_clk;
input pll_hr_clk;
input pll_avl_phy_clk;
input pll_mem_clk;
input pll_write_clk;
input [DLL_WIDTH-1:0] dll_delayctrl_in;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
/* ********* *
* A/C Logic *
* ********* */
localparam CMD_WIDTH =
MEM_CHIP_SELECT_WIDTH +
MEM_CLK_EN_WIDTH +
MEM_ODT_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH +
MEM_CONTROL_WIDTH;
localparam AC_CLK_WIDTH = MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH + 1;
localparam IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC = "false";
wire [AC_CLK_WIDTH-1:0] ac_clk;
generate
genvar i;
for (i = 0; i < AC_CLK_WIDTH; i = i + 1)
begin: address_gen
wire addr_cmd_clk;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ac_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(ac_clk[i])
);
end
endgenerate
hps_sdram_p0_generic_ddio uaddress_pad(
.datain(phy_ddio_address),
.halfratebypass(1'b1),
.dataout(phy_mem_address),
.clk_hr({MEM_ADDRESS_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH-1:0])
);
defparam uaddress_pad.WIDTH = MEM_ADDRESS_WIDTH;
hps_sdram_p0_generic_ddio ubank_pad(
.datain(phy_ddio_bank),
.halfratebypass(1'b1),
.dataout(phy_mem_bank),
.clk_hr({MEM_BANK_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH - 1: MEM_ADDRESS_WIDTH])
);
defparam ubank_pad.WIDTH = MEM_BANK_WIDTH;
hps_sdram_p0_generic_ddio ucmd_pad(
.datain({
phy_ddio_we_n,
phy_ddio_cas_n,
phy_ddio_ras_n,
phy_ddio_odt,
phy_ddio_cke,
phy_ddio_cs_n
}),
.halfratebypass(1'b1),
.dataout({
phy_mem_we_n,
phy_mem_cas_n,
phy_mem_ras_n,
phy_mem_odt,
phy_mem_cke,
phy_mem_cs_n
}),
.clk_hr({CMD_WIDTH{pll_hr_clk}}),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH - 1: MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH])
);
defparam ucmd_pad.WIDTH = CMD_WIDTH;
hps_sdram_p0_generic_ddio ureset_n_pad(
.datain(phy_ddio_reset_n),
.halfratebypass(1'b1),
.dataout(phy_mem_reset_n),
.clk_hr(pll_hr_clk),
.clk_fr(ac_clk[MEM_ADDRESS_WIDTH + MEM_BANK_WIDTH + CMD_WIDTH])
);
defparam ureset_n_pad.WIDTH = 1;
/* ************ *
* Config Logic *
* ************ */
wire [4:0] outputdelaysetting;
wire [4:0] outputenabledelaysetting;
wire outputhalfratebypass;
wire [4:0] inputdelaysetting;
wire [1:0] rfifo_clock_select;
wire [2:0] rfifo_mode;
/*
cyclonev_io_config ioconfig (
.datain(config_data_in),
.clk(config_clock_in),
.ena(config_io_ena),
.update(config_update),
.outputregdelaysetting(outputdelaysetting),
.outputenabledelaysetting(outputenabledelaysetting),
.outputhalfratebypass(outputhalfratebypass),
.readfiforeadclockselect(rfifo_clock_select),
.readfifomode(rfifo_mode),
.padtoinputregisterdelaysetting(inputdelaysetting),
.dataout()
);
*/
/* *************** *
* Mem Clock Logic *
* *************** */
wire [MEM_CK_WIDTH-1:0] mem_ck_source;
wire [MEM_CK_WIDTH-1:0] mem_ck;
generate
genvar clock_width;
for (clock_width=0; clock_width<MEM_CK_WIDTH; clock_width=clock_width+1)
begin: clock_gen
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH(DLL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) acv_ck_ldc (
.pll_hr_clk(pll_avl_phy_clk),
.pll_dq_clk(pll_write_clk),
.pll_dqs_clk (pll_mem_clk),
.dll_phy_delayctrl(dll_delayctrl_in),
.adc_clk_cps(mem_ck_source[clock_width])
);
end
else
begin
wire [3:0] phy_clk_in;
wire [3:0] phy_clk_out;
assign phy_clk_in = {pll_avl_phy_clk,pll_write_clk,pll_mem_clk,1'b0};
if (IS_HHP_HPS == "true") begin
assign phy_clk_out = phy_clk_in;
end else begin
cyclonev_phy_clkbuf phy_clkbuf (
.inclk (phy_clk_in),
.outclk (phy_clk_out)
);
end
wire [3:0] leveled_dqs_clocks;
cyclonev_leveling_delay_chain leveling_delay_chain_dqs (
.clkin (phy_clk_out[1]),
.delayctrlin (dll_delayctrl_in),
.clkout(leveled_dqs_clocks)
);
defparam leveling_delay_chain_dqs.physical_clock_source = "DQS";
cyclonev_clk_phase_select clk_phase_select_dqs (
`ifndef SIMGEN
.clkin (leveled_dqs_clocks[0]),
`else
.clkin (leveled_dqs_clocks),
`endif
.clkout (mem_ck_source[clock_width])
);
defparam clk_phase_select_dqs.physical_clock_source = "DQS";
defparam clk_phase_select_dqs.use_phasectrlin = "false";
defparam clk_phase_select_dqs.phase_setting = 0;
end
wire mem_ck_hi;
wire mem_ck_lo;
if(IMPLEMENT_MEM_CLK_IN_SOFT_LOGIC == "true")
begin
assign mem_ck_hi = 1'b0;
assign mem_ck_lo = 1'b1;
end
else
begin
assign mem_ck_hi = phy_ddio_ck[0];
assign mem_ck_lo = phy_ddio_ck[1];
end
altddio_out umem_ck_pad(
.aclr (1'b0),
.aset (1'b0),
.datain_h (mem_ck_hi),
.datain_l (mem_ck_lo),
.dataout (mem_ck[clock_width]),
.oe (1'b1),
.outclock (mem_ck_source[clock_width]),
.outclocken (1'b1)
);
defparam
umem_ck_pad.extend_oe_disable = "UNUSED",
umem_ck_pad.intended_device_family = DEVICE_FAMILY,
umem_ck_pad.invert_output = "OFF",
umem_ck_pad.lpm_hint = "UNUSED",
umem_ck_pad.lpm_type = "altddio_out",
umem_ck_pad.oe_reg = "UNUSED",
umem_ck_pad.power_up_high = "OFF",
umem_ck_pad.width = 1;
wire mem_ck_temp;
assign mem_ck_temp = mem_ck[clock_width];
hps_sdram_p0_clock_pair_generator uclk_generator(
.datain (mem_ck_temp),
.dataout (phy_mem_ck[clock_width]),
.dataout_b (phy_mem_ck_n[clock_width])
);
end
endgenerate
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_phy4_62p5.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_phy4_62p5 (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire locked = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.areset (areset),
.clk (sub_wire0),
.locked (sub_wire4),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 2,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "1500",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "1500",
altpll_component.clk2_divide_by = 4,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "1500",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 4000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "250.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "250.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "500.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "250.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "1.50000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "1.50000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "1.50000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy4_62p5.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "1500"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "1500"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "1500"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "4000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy4_62p5_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//////////////////////////////////////////////////////////////////
////
////
//// CRCAHB CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// crcahb IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Julio Cesar
////
/////////////////////////////////////////////////////////////////
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module host_interface
(
//OUTPUTS
output [31:0] HRDATA,
output HREADYOUT,
output HRESP,
output [31:0] bus_wr,
output [ 1:0] crc_poly_size,
output [ 1:0] bus_size,
output [ 1:0] rev_in_type,
output rev_out_type,
output crc_init_en,
output crc_idr_en,
output crc_poly_en,
output buffer_write_en,
output reset_chain,
//INPUTS
input [31:0] HWDATA,
input [31:0] HADDR,
input [ 2:0] HSIZE,
input [ 1:0] HTRANS,
input HWRITE,
input HSElx,
input HREADY,
input HRESETn,
input HCLK,
input [31:0] crc_poly_out,
input [31:0] crc_out,
input [31:0] crc_init_out,
input [ 7:0] crc_idr_out,
input buffer_full,
input reset_pending,
input read_wait
);
//Reset Values
localparam RESET_CRC_CR = 6'h00;
//CRC Register Map
localparam CRC_DR = 3'h0;
localparam CRC_IDR = 3'h1;
localparam CRC_CR = 3'h2;
localparam CRC_INIT = 3'h4;
localparam CRC_POL = 3'h5;
//Transfer Type Encoding
localparam IDLE = 2'b00;
localparam BUSY = 2'b01;
localparam NON_SEQ = 2'b10;
localparam SEQ = 2'b11;
//HRESP Encoding
localparam OK = 1'b0;
localparam ERROR = 1'b1;
//Pipeline flops
reg [2:0] haddr_pp;
reg [2:0] hsize_pp;
reg [1:0] htrans_pp;
reg hwrite_pp;
reg hselx_pp;
//Flops
reg [4:0] crc_cr_ff;
//Internal Signals
wire [31:0] crc_cr_rd;
wire crc_dr_sel;
wire crc_init_sel;
wire crc_idr_sel;
wire crc_poly_sel;
wire crc_cr_sel;
wire ahb_enable;
wire write_en;
wire read_en;
wire crc_cr_en;
wire sample_bus;
wire buffer_read_en;
//Pipeline Registers for Address Phase of AHB Protocol
always @(posedge HCLK)
begin
if(!HRESETn)
begin
hselx_pp <= 1'b0;
end
else
if(sample_bus)
begin
haddr_pp <= HADDR[4:2];
hsize_pp <= HSIZE;
htrans_pp <= HTRANS;
hwrite_pp <= HWRITE;
hselx_pp <= HSElx;
end
end
//Enable Signals
assign ahb_enable = (htrans_pp == NON_SEQ);
assign write_en = hselx_pp && hwrite_pp && ahb_enable;
assign read_en = hselx_pp && !hwrite_pp && ahb_enable;
//Registers decoding
assign crc_dr_sel = (haddr_pp == CRC_DR );
assign crc_init_sel = (haddr_pp == CRC_INIT);
assign crc_idr_sel = (haddr_pp == CRC_IDR );
assign crc_poly_sel = (haddr_pp == CRC_POL );
assign crc_cr_sel = (haddr_pp == CRC_CR );
//Write Esnables Signals for Registers
assign buffer_write_en = crc_dr_sel && write_en;
assign crc_init_en = crc_init_sel && write_en;
assign crc_idr_en = crc_idr_sel && write_en;
assign crc_poly_en = crc_poly_sel && write_en;
assign crc_cr_en = crc_cr_sel && write_en;
//Indicates reading operation request to crc_dr register
assign buffer_read_en = crc_dr_sel && read_en;
//Bus Size is the output of HSIZE pipeline register
assign bus_size = hsize_pp;
//The Write Bus is not pipelined
assign bus_wr = HWDATA;
//HREADY Signal outputed to Master
assign HREADYOUT = !((buffer_write_en && buffer_full ) ||
(buffer_read_en && read_wait ) ||
(crc_init_en && reset_pending ) );
//Signal to control sampling of bus
assign sample_bus = HREADYOUT && HREADY;
//HRESP Signal outputed to Master
//This implementation never signalize bus error to master
assign HRESP = OK;
//CRC_CR Data Read
assign crc_cr_rd = {24'h0, crc_cr_ff[4:0], 3'h0};
//Mux to HRDATA
assign HRDATA = ({32{crc_dr_sel }} & crc_out ) |
({32{crc_init_sel}} & crc_init_out ) |
({32{crc_idr_sel }} & {24'h0, crc_idr_out}) |
({32{crc_poly_sel}} & crc_poly_out ) |
({32{crc_cr_sel }} & crc_cr_rd ) ;
//Control Register
always @(posedge HCLK)
begin
if(!HRESETn)
crc_cr_ff <= RESET_CRC_CR;
else
if(crc_cr_en)
crc_cr_ff <= {HWDATA[7], HWDATA[6:5], HWDATA[4:3]};
end
//Configuration Signals
assign reset_chain = (crc_cr_en && HWDATA[0]);
assign crc_poly_size = crc_cr_ff[1:0];
assign rev_in_type = crc_cr_ff[3:2];
assign rev_out_type = crc_cr_ff[4];
endmodule
|
`timescale 1ns / 1ps
module simple_ddr3_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg rst;
reg [27:0] addr;
reg [31:0] wdata;
reg we;
reg pop;
wire [31:0] mig_rd_data = 32'h12345678;
reg [6:0] mig_rd_count;
simple_ddr3 uut(
.clk(clk),
.rst(rst),
.addr_i(addr),
.data_i(wdata),
.we_i(we),
.pop_i(pop),
.mig_cmd_empty(1'b1),
.mig_cmd_full(1'b0),
.mig_wr_full(1'b1),
.mig_wr_empty(1'b0),
// .mig_wr_count,
// .mig_wr_underrun,
// .mig_wr_error,
.mig_rd_data(mig_rd_data),
// .mig_rd_full,
// .mig_rd_empty,
.mig_rd_count(mig_rd_count)
// .mig_rd_overflow,
// .mig_rd_error,
);
initial begin
$dumpfile("simple_ddr3_t.lxt");
$dumpvars(0, simple_ddr3_t);
addr = 28'h1234567;
wdata = 32'hdeadbeef;
we = 1'b0;
pop = 1'b0;
rst = 1'b1;
#(TCLK);
rst = 1'b0;
mig_rd_count = 'b0;
#(TCLK*3);
we = 1'b1;
#(TCLK);
we = 1'b0;
#(TCLK*10);
pop = 1'b1;
#(TCLK);
pop = 1'b0;
#(TCLK*10);
$finish(2);
end
always @(posedge clk) begin
if (uut.mig_cmd_en == 1'b1 && uut.mig_cmd_instr[0] == 1'b1) begin
#(TCLK*5)
mig_rd_count = 'd1;
#(TCLK)
mig_rd_count = 'd0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_SYMBOL_V
`define SKY130_FD_SC_HDLL__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_SYMBOL_V
|
// ghrd_10as066n2_mm_bridge_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_mm_bridge_0 #(
parameter DATA_WIDTH = 512,
parameter SYMBOL_WIDTH = 8,
parameter HDL_ADDR_WIDTH = 32,
parameter BURSTCOUNT_WIDTH = 5,
parameter PIPELINE_COMMAND = 1,
parameter PIPELINE_RESPONSE = 1
) (
input wire clk, // clk.clk
input wire m0_waitrequest, // m0.waitrequest
input wire [DATA_WIDTH-1:0] m0_readdata, // .readdata
input wire m0_readdatavalid, // .readdatavalid
output wire [BURSTCOUNT_WIDTH-1:0] m0_burstcount, // .burstcount
output wire [DATA_WIDTH-1:0] m0_writedata, // .writedata
output wire [HDL_ADDR_WIDTH-1:0] m0_address, // .address
output wire m0_write, // .write
output wire m0_read, // .read
output wire [63:0] m0_byteenable, // .byteenable
output wire m0_debugaccess, // .debugaccess
input wire reset, // reset.reset
output wire s0_waitrequest, // s0.waitrequest
output wire [DATA_WIDTH-1:0] s0_readdata, // .readdata
output wire s0_readdatavalid, // .readdatavalid
input wire [BURSTCOUNT_WIDTH-1:0] s0_burstcount, // .burstcount
input wire [DATA_WIDTH-1:0] s0_writedata, // .writedata
input wire [HDL_ADDR_WIDTH-1:0] s0_address, // .address
input wire s0_write, // .write
input wire s0_read, // .read
input wire [63:0] s0_byteenable, // .byteenable
input wire s0_debugaccess // .debugaccess
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (DATA_WIDTH),
.SYMBOL_WIDTH (SYMBOL_WIDTH),
.HDL_ADDR_WIDTH (HDL_ADDR_WIDTH),
.BURSTCOUNT_WIDTH (BURSTCOUNT_WIDTH),
.PIPELINE_COMMAND (PIPELINE_COMMAND),
.PIPELINE_RESPONSE (PIPELINE_RESPONSE)
) mm_bridge_0 (
.clk (clk), // input, width = 1, clk.clk
.reset (reset), // input, width = 1, reset.reset
.s0_waitrequest (s0_waitrequest), // output, width = 1, s0.waitrequest
.s0_readdata (s0_readdata), // output, width = DATA_WIDTH, .readdata
.s0_readdatavalid (s0_readdatavalid), // output, width = 1, .readdatavalid
.s0_burstcount (s0_burstcount), // input, width = BURSTCOUNT_WIDTH, .burstcount
.s0_writedata (s0_writedata), // input, width = DATA_WIDTH, .writedata
.s0_address (s0_address), // input, width = HDL_ADDR_WIDTH, .address
.s0_write (s0_write), // input, width = 1, .write
.s0_read (s0_read), // input, width = 1, .read
.s0_byteenable (s0_byteenable), // input, width = 64, .byteenable
.s0_debugaccess (s0_debugaccess), // input, width = 1, .debugaccess
.m0_waitrequest (m0_waitrequest), // input, width = 1, m0.waitrequest
.m0_readdata (m0_readdata), // input, width = DATA_WIDTH, .readdata
.m0_readdatavalid (m0_readdatavalid), // input, width = 1, .readdatavalid
.m0_burstcount (m0_burstcount), // output, width = BURSTCOUNT_WIDTH, .burstcount
.m0_writedata (m0_writedata), // output, width = DATA_WIDTH, .writedata
.m0_address (m0_address), // output, width = HDL_ADDR_WIDTH, .address
.m0_write (m0_write), // output, width = 1, .write
.m0_read (m0_read), // output, width = 1, .read
.m0_byteenable (m0_byteenable), // output, width = 64, .byteenable
.m0_debugaccess (m0_debugaccess), // output, width = 1, .debugaccess
.s0_response (), // (terminated),
.m0_response (2'b00) // (terminated),
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:29:07 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_0_stub.v
// Design : zqynq_lab_1_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [1:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Force stmt validation
//
// D: This code verifies the force statement
// D: It is intended to be self checking.
//
module main ();
reg working;
reg timer;
initial
begin
timer = 1;
# 5;
timer = 0;
# 5 ;
timer = 1;
# 5 ;
end
initial
begin
working = 1;
#2 ; // Validate that force occurs
force timer = 0;
if( timer == 1) working = 0;
#10 ; // Validate that force stays in effect
if( timer == 1) working = 0;
end
initial
begin
#20;
if(!working)
$display("FAILED\n");
else
$display("PASSED\n");
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off GENCLK
reg printclk;
// verilator lint_on GENCLK
ps ps (printclk);
reg [7:0] a;
wire [7:0] z;
l1 u (~a,z);
always @ (posedge clk) begin
printclk <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
printclk <= 1'b1;
end
if (cyc==2) begin
a <= 8'b1;
end
if (cyc==3) begin
if (z !== 8'hf8) $stop;
//if (u.u1.u1.u1.u0.PARAM !== 1) $stop;
//if (u.u1.u1.u1.u1.PARAM !== 2) $stop;
//if (u.u0.u0.u0.u0.z !== 8'hfe) $stop;
//if (u.u0.u0.u0.u1.z !== 8'hff) $stop;
//if (u.u1.u1.u1.u0.z !== 8'h00) $stop;
//if (u.u1.u1.u1.u1.z !== 8'h01) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`endif
`ifdef USE_PUBLIC
`define PUBLIC /*verilator public*/
`else
`define PUBLIC
`endif
module ps (input printclk);
`INLINE_MODULE
// Check that %m stays correct across inlines
always @ (posedge printclk) $write("[%0t] %m: Clocked\n", $time);
endmodule
module l1 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
l2 u0 (a, z0); l2 u1 (a, z1);
endmodule
module l2 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l3 u0 (a, z0); l3 u1 (a1, z1);
endmodule
module l3 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l4 u0 (a, z0); l4 u1 (a1, z1);
endmodule
module l4 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = z0+z1;
wire [7:0] a1 = a+8'd1;
l5 #(1) u0 (a, z0); l5 #(2) u1 (a1, z1);
endmodule
module l5 (input [7:0] a, output [7:0] z);
`INLINE_MODULE
parameter PARAM = 5;
wire [7:0] z0 `PUBLIC; wire [7:0] z1 `PUBLIC;
wire [7:0] z `PUBLIC; assign z = a;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Exception logic ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Handles all OR1K exceptions inside CPU block. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.15.4.1 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.15 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.14 2002/09/03 22:28:21 lampret
// As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy.
//
// Revision 1.13 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
// Revision 1.12 2002/08/22 02:16:45 lampret
// Fixed IMMU bug.
//
// Revision 1.11 2002/08/18 19:54:28 lampret
// Added store buffer.
//
// Revision 1.10 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.9 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.8 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.7 2002/01/23 07:52:36 lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.6 2002/01/18 14:21:43 lampret
// Fixed 'the NPC single-step fix'.
//
// Revision 1.5 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.4 2002/01/14 21:11:50 lampret
// Changed alignment exception EPCR. Not tested yet.
//
// Revision 1.3 2002/01/14 19:09:57 lampret
// Fixed order of syscall and range exceptions.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.15 2001/11/27 23:13:11 lampret
// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
//
// Revision 1.14 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.13 2001/11/20 18:46:15 simons
// Break point bug fixed
//
// Revision 1.12 2001/11/18 09:58:28 lampret
// Fixed some l.trap typos.
//
// Revision 1.11 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.10 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.9 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
`define OR1200_EXCEPTFSM_WIDTH 3
`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
//
// Exception recognition and sequencing
//
module or1200_except(
// Clock and reset
clk, rst,
// Internal i/f
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze, if_stall,
if_pc, id_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
except_started, except_stop, ex_void,
spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
esr, sr_we, to_sr, sr, lsu_addr, abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i
);
//
// I/O
//
input clk;
input rst;
input sig_ibuserr;
input sig_dbuserr;
input sig_illegal;
input sig_align;
input sig_range;
input sig_dtlbmiss;
input sig_dmmufault;
input sig_int;
input sig_syscall;
input sig_trap;
input sig_itlbmiss;
input sig_immufault;
input sig_tick;
input branch_taken;
input genpc_freeze;
input id_freeze;
input ex_freeze;
input wb_freeze;
input if_stall;
input [31:0] if_pc;
output [31:0] id_pc;
output [31:2] lr_sav;
input [31:0] datain;
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
input epcr_we;
input eear_we;
input esr_we;
input pc_we;
output [31:0] epcr;
output [31:0] eear;
output [`OR1200_SR_WIDTH-1:0] esr;
input [`OR1200_SR_WIDTH-1:0] to_sr;
input sr_we;
input [`OR1200_SR_WIDTH-1:0] sr;
input [31:0] lsu_addr;
output flushpipe;
output extend_flush;
output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
output except_start;
output except_started;
output [12:0] except_stop;
input ex_void;
output [31:0] spr_dat_ppc;
output [31:0] spr_dat_npc;
output abort_ex;
input icpu_ack_i;
input icpu_err_i;
input dcpu_ack_i;
input dcpu_err_i;
//
// Internal regs and wires
//
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
reg [31:0] id_pc;
reg [31:0] ex_pc;
reg [31:0] wb_pc;
reg [31:0] epcr;
reg [31:0] eear;
reg [`OR1200_SR_WIDTH-1:0] esr;
reg [2:0] id_exceptflags;
reg [2:0] ex_exceptflags;
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
reg extend_flush;
reg extend_flush_last;
reg ex_dslot;
reg delayed1_ex_dslot;
reg delayed2_ex_dslot;
wire except_started;
wire [12:0] except_trig;
wire except_flushpipe;
reg [2:0] delayed_iee;
reg [2:0] delayed_tee;
wire int_pending;
wire tick_pending;
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
assign lr_sav = ex_pc[31:2];
assign spr_dat_ppc = wb_pc;
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we;
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~sr_we;
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
//
// Order defines exception detection priority
//
assign except_trig = {
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
};
assign except_stop = {
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
int_pending & du_dsr[`OR1200_DU_DSR_IE],
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
sig_align & du_dsr[`OR1200_DU_DSR_AE],
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
sig_range & du_dsr[`OR1200_DU_DSR_RE],
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
};
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
if (rst) begin
id_pc <= #1 32'd0;
id_exceptflags <= #1 3'b000;
end
else if (flushpipe) begin
id_pc <= #1 32'h0000_0000;
id_exceptflags <= #1 3'b000;
end
else if (!id_freeze) begin
id_pc <= #1 if_pc;
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
end
end
//
// delayed_iee
//
// SR[IEE] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_iee
// together with SR[IEE] enables interrupts once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
if (rst)
delayed_iee <= #1 3'b000;
else if (!sr[`OR1200_SR_IEE])
delayed_iee <= #1 3'b000;
else
delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
//
// delayed_tee
//
// SR[TEE] should not enable tick exceptions right away
// when it is restored with l.rfe. Instead delayed_tee
// together with SR[TEE] enables tick exceptions once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
if (rst)
delayed_tee <= #1 3'b000;
else if (!sr[`OR1200_SR_TEE])
delayed_tee <= #1 3'b000;
else
delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
if (rst) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 32'd0;
ex_exceptflags <= #1 3'b000;
delayed1_ex_dslot <= #1 1'b0;
delayed2_ex_dslot <= #1 1'b0;
end
else if (flushpipe) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 32'h0000_0000;
ex_exceptflags <= #1 3'b000;
delayed1_ex_dslot <= #1 1'b0;
delayed2_ex_dslot <= #1 1'b0;
end
else if (!ex_freeze & id_freeze) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 id_pc;
ex_exceptflags <= #1 3'b000;
delayed1_ex_dslot <= #1 ex_dslot;
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
end
else if (!ex_freeze) begin
ex_dslot <= #1 branch_taken;
ex_pc <= #1 id_pc;
ex_exceptflags <= #1 id_exceptflags;
delayed1_ex_dslot <= #1 ex_dslot;
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
end
end
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
if (rst) begin
wb_pc <= #1 32'd0;
end
else if (!wb_freeze) begin
wb_pc <= #1 ex_pc;
end
end
//
// Flush pipeline
//
assign flushpipe = except_flushpipe | pc_we | extend_flush;
//
// We have started execution of exception handler:
// 1. Asserted for 3 clock cycles
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & ~|state;
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
// 1. Asserted in next clock cycle after exception is recognized
//
always @(posedge clk or posedge rst) begin
if (rst) begin
state <= #1 `OR1200_EXCEPTFSM_IDLE;
except_type <= #1 `OR1200_EXCEPT_NONE;
extend_flush <= #1 1'b0;
epcr <= #1 32'b0;
eear <= #1 32'b0;
esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
extend_flush_last <= #1 1'b0;
end
else begin
`ifdef OR1200_CASE_DEFAULT
case (state) // synopsys parallel_case
`else
case (state) // synopsys full_case parallel_case
`endif
`OR1200_EXCEPTFSM_IDLE:
if (except_flushpipe) begin
state <= #1 `OR1200_EXCEPTFSM_FLU1;
extend_flush <= #1 1'b1;
esr <= #1 sr_we ? to_sr : sr;
casex (except_trig)
`ifdef OR1200_EXCEPT_TICK
13'b1_xxxx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_TICK;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_INT
13'b0_1xxx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_INT;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_ITLBMISS
13'b0_01xx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
//
// itlb miss exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
// mmu-icdc-O2 ex_pc only OK when no ex_dslot eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
// mmu-icdc-O2 ex_pc only OK when no ex_dslot epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
eear <= #1 ex_dslot ? ex_pc : ex_pc;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
// eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
// epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_IPF
13'b0_001x_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_IPF;
//
// ipf exception and active ex_dslot caused wb_pc to put into eear instead of +4 address of ex_pc (or id_pc since it was equal to ex_pc?)
// eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
eear <= #1 ex_dslot ? ex_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
13'b0_0001_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_BUSERR;
eear <= #1 ex_dslot ? wb_pc : ex_pc;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
13'b0_0000_1xxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
eear <= #1 ex_pc;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_ALIGN
13'b0_0000_01xx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_ALIGN;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
13'b0_0000_001x_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_DPF
13'b0_0000_0001_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_DPF;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
13'b0_0000_0000_1xxx: begin // Data Bus Error
except_type <= #1 `OR1200_EXCEPT_BUSERR;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_RANGE
13'b0_0000_0000_01xx: begin
except_type <= #1 `OR1200_EXCEPT_RANGE;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
`ifdef OR1200_EXCEPT_TRAP 13'b0_0000_0000_001x: begin
except_type <= #1 `OR1200_EXCEPT_TRAP;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
`endif
`ifdef OR1200_EXCEPT_SYSCALL
13'b0_0000_0000_0001: begin
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
`endif
default:
except_type <= #1 `OR1200_EXCEPT_NONE;
endcase
end
else if (pc_we) begin
state <= #1 `OR1200_EXCEPTFSM_FLU1;
extend_flush <= #1 1'b1;
end
else begin
if (epcr_we)
epcr <= #1 datain;
if (eear_we)
eear <= #1 datain;
if (esr_we)
esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
end
`OR1200_EXCEPTFSM_FLU1:
if (icpu_ack_i | icpu_err_i | genpc_freeze)
state <= #1 `OR1200_EXCEPTFSM_FLU2;
`OR1200_EXCEPTFSM_FLU2:
`ifdef OR1200_EXCEPT_TRAP
if (except_type == `OR1200_EXCEPT_TRAP) begin
state <= #1 `OR1200_EXCEPTFSM_IDLE;
extend_flush <= #1 1'b0;
extend_flush_last <= #1 1'b0;
except_type <= #1 `OR1200_EXCEPT_NONE;
end
else
`endif
state <= #1 `OR1200_EXCEPTFSM_FLU3;
`OR1200_EXCEPTFSM_FLU3:
begin
state <= #1 `OR1200_EXCEPTFSM_FLU4;
end
`OR1200_EXCEPTFSM_FLU4: begin
state <= #1 `OR1200_EXCEPTFSM_FLU5;
extend_flush <= #1 1'b0;
extend_flush_last <= #1 1'b0; // damjan
end
`ifdef OR1200_CASE_DEFAULT
default: begin
`else
`OR1200_EXCEPTFSM_FLU5: begin
`endif
if (!if_stall && !id_freeze) begin
state <= #1 `OR1200_EXCEPTFSM_IDLE;
except_type <= #1 `OR1200_EXCEPT_NONE;
extend_flush_last <= #1 1'b0;
end
end
endcase
end
end
endmodule
|
// ======================================================================
// USB-UART.v generated from TopDesign.cysch
// 12/08/2014 at 16:15
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// SCB_P4_v1_20(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=1600, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=1600, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, PinName0Unconfig=spi_mosi_i2c_scl_uart_rx, PinName1Unconfig=spi_miso_i2c_sda_uart_tx, RemoveI2cPins=true, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=true, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=false, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=false, ScbClkFreqDes=1382.4, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=4, ScbModeHw=2, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=1, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=1382.4, UartClockFromTerm=false, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=true, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=4, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=UART, CY_INSTANCE_SHORT_NAME=UART, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=UART, )
module SCB_P4_v1_20_0 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("723379629.62963"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_379;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
tx
(.oe(tmpOE__tx_net),
.y({Net_656}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
endmodule
// Component: OneTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`endif
// IDAC_P4_v1_0(IDACRange=0, IDACValue=14, Polarity=1, Resolution=7, CY_COMPONENT_NAME=IDAC_P4_v1_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=CapSense:IDAC2, CY_INSTANCE_SHORT_NAME=IDAC2, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=true, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=CapSense_IDAC2, )
module IDAC_P4_v1_0_1 (
Iout);
inout Iout;
electrical Iout;
wire Net_3;
cy_psoc4_csidac_v1_0 cy_psoc4_idac (
.en(Net_3),
.iout(Iout));
defparam cy_psoc4_idac.resolution = 7;
OneTerminal OneTerminal_1 (
.o(Net_3));
endmodule
// IDAC_P4_v1_0(IDACRange=0, IDACValue=16, Polarity=1, Resolution=8, CY_COMPONENT_NAME=IDAC_P4_v1_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=CapSense:IDAC1, CY_INSTANCE_SHORT_NAME=IDAC1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=true, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=CapSense_IDAC1, )
module IDAC_P4_v1_0_2 (
Iout);
inout Iout;
electrical Iout;
wire Net_3;
cy_psoc4_csidac_v1_0 cy_psoc4_idac (
.en(Net_3),
.iout(Iout));
defparam cy_psoc4_idac.resolution = 8;
OneTerminal OneTerminal_1 (
.o(Net_3));
endmodule
// CapSense_CSD_P4_v2_0(AnalogSwitchDivider=12, AvgSamplesNumber=1, CalibrationResulution=7, CmodPrecharge=1, ConnectInactiveSensors=0, CshTankPrecharge=1, CurrentSource=0, CustomEzI2CInstanceName=SCB_1, DbPwmMode=0, DbPwmPeriod=0, DfbEnable=false, DynamicButtonNumber=5, EmcSensorNumber=10, EnableAutoCalibration=false, EnableBIST=false, EnableTuneHelper=true, GuardSensorEnable=false, I2cCommunication=0, IDACRange=0, IDACsCount=2, ImmunityLevel=1, InputClkFreq=3, IsStreetFighter=false, KValueScalingFactor=8, LowBaselineReset=5, M0S8CSD_BLOCK_NUM=1, M0S8CSD_BLOCK_VER=0, M0S8GPIO2_BLOCK_NUM=1, M0S8GPIO2_BLOCK_VER=0, M0S8HSIOM4A_BLOCK_NUM=1, M0S8HSIOM4A_BLOCK_VER=0, M0S8IOSS_BLOCK_NUM=0, M0S8IOSS_BLOCK_VER=-1, M0S8PCLK_BLOCK_NUM=1, M0S8PCLK_BLOCK_VER=0, M0S8PERI_BLOCK_NUM=0, M0S8PERI_BLOCK_VER=-1, ModulatorClkDivider=12, NegativeNoiseThreshold=20, OversamplingEn=true, PrechargeClkDivider=12, PrechargeClkFreq=3, PrsOptions=0, PrtRegNameReplacementString=CYREG, RawDataFilterType=8, SensorAutoReset=false, SensorNumber=4, SensorsFreqSettingsInd=true, ShieldDelay=0, ShieldEnable=false, ShieldTankEnable=false, SizeReplacementString=uint8, SliderThresholdsUpdateManual=false, SnsAlias=Button0__BTN, Button1__BTN, Button2__BTN, Button3__BTN, ThresholdMode=true, TunerIntfAddress=8, TunerIntfDataRate=400, TunerProperties=, TuningMethod=0, WaterProofingEnabled=false, WidgetResolution=8, WidgetsData=<?xml version="1.0" encoding="utf-16"?> <CyWidgetsList xmlns:Version="2_0"> <ListMainTerminal> <CyTerminal NameIndex="0" WidgetName="Button0__BTN" /> <CyTerminal NameIndex="0" WidgetName="Button1__BTN" /> <CyTerminal NameIndex="0" WidgetName="Button2__BTN" /> <CyTerminal NameIndex="0" WidgetName="Button3__BTN" /> </ListMainTerminal> <ListButtons> <CyButton Name="Button0" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> <CyButton Name="Button1" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> <CyButton Name="Button2" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> <CyButton Name="Button3" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> </ListButtons> <ListMatrixButtons /> <ListTouchPads /> <ListSliders /> <GuardSensor Name="GuardSensor" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_12</ScanResolution> </Properties> </GuardSensor> <GuardSensorTerminal NameIndex="0" WidgetName="GuardSensor__GRD" /> <CyScanSlotsList> <ListScanSlots> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button0__BTN"> <ListTerminalsNames> <string>Button0__BTN</string> </ListTerminalsNames> </CyScanSlot> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button1__BTN"> <ListTerminalsNames> <string>Button1__BTN</string> </ListTerminalsNames> </CyScanSlot> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button2__BTN"> <ListTerminalsNames> <string>Button2__BTN</string> </ListTerminalsNames> </CyScanSlot> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button3__BTN"> <ListTerminalsNames> <string>Button3__BTN</string> </ListTerminalsNames> </CyScanSlot> </ListScanSlots> <GuardSensorScanSlot IDAC1Settings="120" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="2" ModulatorDivider="2" WidgetName="GuardSensor__GRD"> <ListTerminalsNames> <string>GuardSensor__GRD</string> </ListTerminalsNames> </GuardSensorScanSlot> </CyScanSlotsList> </CyWidgetsList>, CY_COMPONENT_NAME=CapSense_CSD_P4_v2_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=CapSense, CY_INSTANCE_SHORT_NAME=CapSense, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=CapSense, )
module CapSense_CSD_P4_v2_0_3 (
sclk2);
output sclk2;
wire Net_534;
wire Net_474;
wire Net_540;
wire Net_329;
wire Net_312;
wire Net_104;
wire Net_328;
electrical Net_398;
electrical Net_241;
electrical Net_246;
wire Net_420;
wire Net_429;
electrical [3:0] Net_245;
wire Net_248;
electrical Net_270;
cy_psoc4_csd_v1_0 CSD_FFB (
.source(Net_245[3:0]),
.csh(Net_246),
.shield(Net_241),
.cmod(Net_398),
.sample_out(Net_328),
.sense_in(Net_104),
.clk1(Net_429),
.clk2(Net_420),
.irq(Net_248),
.sample_in(Net_312),
.sense_out(Net_329),
.amuxa(Net_270));
defparam CSD_FFB.sensors_count = 4;
defparam CSD_FFB.shield_count = 1;
cy_clock_v1_0
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/74063576-f256-4f8f-8a82-9abdee876261"),
.source_clock_id("413DE2EF-D9F2-4233-A808-DFAF137FD877"),
.divisor(255),
.period("0"),
.is_direct(0),
.is_digital(0))
SampleClk
(.clock_out(Net_420));
wire [0:0] tmpOE__Cmod_net;
wire [0:0] tmpFB_0__Cmod_net;
wire [0:0] tmpIO_0__Cmod_net;
wire [0:0] tmpINTERRUPT_0__Cmod_net;
electrical [0:0] tmpSIOVREF__Cmod_net;
cy_psoc3_pins_v1_10
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/899719c0-e797-4403-a44f-07a66de2cbeb"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases("Cmod"),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Cmod
(.oe(tmpOE__Cmod_net),
.y({1'b0}),
.fb({tmpFB_0__Cmod_net[0:0]}),
.analog({Net_398}),
.io({tmpIO_0__Cmod_net[0:0]}),
.siovref(tmpSIOVREF__Cmod_net),
.interrupt({tmpINTERRUPT_0__Cmod_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Cmod_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
ISR
(.int_signal(Net_248));
IDAC_P4_v1_0_1 IDAC2 (
.Iout(Net_270));
wire [3:0] tmpOE__Sns_net;
wire [3:0] tmpFB_3__Sns_net;
wire [3:0] tmpIO_3__Sns_net;
wire [0:0] tmpINTERRUPT_0__Sns_net;
electrical [0:0] tmpSIOVREF__Sns_net;
cy_psoc3_pins_v1_10
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/73b612cd-240c-4d8e-8340-ea28aabf4b11"),
.drive_mode(12'b000_000_000_000),
.ibuf_enabled(4'b0_0_0_0),
.init_dr_st(4'b1_1_1_1),
.input_clk_en(0),
.input_sync(4'b1_1_1_1),
.input_sync_mode(4'b0_0_0_0),
.intr_mode(8'b00_00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(",,,"),
.layout_mode("NONCONTIGUOUS"),
.oe_conn(4'b0_0_0_0),
.oe_reset(0),
.oe_sync(4'b0_0_0_0),
.output_clk_en(0),
.output_clock_mode(4'b0_0_0_0),
.output_conn(4'b0_0_0_0),
.output_mode(4'b0_0_0_0),
.output_reset(0),
.output_sync(4'b0_0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases("Button0__BTN,Button1__BTN,Button2__BTN,Button3__BTN"),
.pin_mode("AAAA"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(4'b0_0_0_0),
.sio_ibuf(""),
.sio_info(8'b00_00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(4'b0_0_0_0),
.spanning(1),
.use_annotation(4'b0_0_0_0),
.vtrip(8'b10_10_10_10),
.width(4))
Sns
(.oe(tmpOE__Sns_net),
.y({4'b0}),
.fb({tmpFB_3__Sns_net[3:0]}),
.analog({Net_245[3:0]}),
.io({tmpIO_3__Sns_net[3:0]}),
.siovref(tmpSIOVREF__Sns_net),
.interrupt({tmpINTERRUPT_0__Sns_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Sns_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{4'b1111} : {4'b1111};
IDAC_P4_v1_0_2 IDAC1 (
.Iout(Net_270));
ZeroTerminal ZeroTerminal_1 (
.z(Net_312));
ZeroTerminal ZeroTerminal_2 (
.z(Net_104));
assign sclk2 = Net_420 | Net_474;
ZeroTerminal ZeroTerminal_7 (
.z(Net_474));
cy_clock_v1_0
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/9a635726-510c-483c-9c5c-3e233ee2906a"),
.source_clock_id("413DE2EF-D9F2-4233-A808-DFAF137FD877"),
.divisor(255),
.period("0"),
.is_direct(0),
.is_digital(0))
SenseClk
(.clock_out(Net_429));
endmodule
// SCB_P4_v1_20(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=6400, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=400, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=1, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=1600, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, PinName0Unconfig=spi_mosi_i2c_scl_uart_rx, PinName1Unconfig=spi_miso_i2c_sda_uart_tx, RemoveI2cPins=false, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=false, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=true, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=true, ScbClkFreqDes=6400, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=8, ScbModeHw=0, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=0, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=1382.4, UartClockFromTerm=false, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=false, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=0, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=SCB_1, CY_INSTANCE_SHORT_NAME=SCB_1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=SCB_1, )
module SCB_P4_v1_20_4 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("4ee47aff-a351-4cef-924e-4fb02af36bdf/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("156250000"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_452;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__sda_net;
wire [0:0] tmpFB_0__sda_net;
wire [0:0] tmpINTERRUPT_0__sda_net;
electrical [0:0] tmpSIOVREF__sda_net;
cy_psoc3_pins_v1_10
#(.id("4ee47aff-a351-4cef-924e-4fb02af36bdf/5382e105-1382-4a2e-b9f4-3bb2feba71e0"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
sda
(.oe(tmpOE__sda_net),
.y({1'b0}),
.fb({tmpFB_0__sda_net[0:0]}),
.io({Net_581}),
.siovref(tmpSIOVREF__sda_net),
.interrupt({tmpINTERRUPT_0__sda_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__sda_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__scl_net;
wire [0:0] tmpFB_0__scl_net;
wire [0:0] tmpINTERRUPT_0__scl_net;
electrical [0:0] tmpSIOVREF__scl_net;
cy_psoc3_pins_v1_10
#(.id("4ee47aff-a351-4cef-924e-4fb02af36bdf/22863ebe-a37b-476f-b252-6e49a8c00b12"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
scl
(.oe(tmpOE__scl_net),
.y({1'b0}),
.fb({tmpFB_0__scl_net[0:0]}),
.io({Net_580}),
.siovref(tmpSIOVREF__scl_net),
.interrupt({tmpINTERRUPT_0__scl_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__scl_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
cy_isr_v1_0
#(.int_type(2'b10))
SCB_IRQ
(.int_signal(interrupt));
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 0;
endmodule
// top
module top ;
wire Net_21;
wire Net_20;
wire Net_19;
wire Net_27;
wire Net_3;
wire Net_2;
wire Net_1;
SCB_P4_v1_20_0 UART (
.sclk(Net_1),
.interrupt(Net_2),
.clock(1'b0));
CapSense_CSD_P4_v2_0_3 CapSense (
.sclk2(Net_27));
SCB_P4_v1_20_4 SCB_1 (
.sclk(Net_19),
.interrupt(Net_20),
.clock(1'b0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_BLACKBOX_V
`define SKY130_FD_SC_HS__FA_BLACKBOX_V
/**
* fa: Full adder.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__fa (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_BLACKBOX_V
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XPCIe
Create Date: 15/07/2011
Design Name: adder
*******************************************************************/
`timescale 1ns/1ns
module adder
(
input clk ,
input rst ,
input [31:0] ain ,
input [31:0] bin ,
output reg [31:0] result ,
output reg [31:0] statistic
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
reg [31:0] result_last;
//-------------------------------------------------------------------
// Main Computation
//-------------------------------------------------------------------
/* the result & result_last register */
always @(posedge clk or posedge rst) begin
if (rst) begin
result <= 32'h0;
result_last <= 32'h0;
end else begin
result <= ain + bin;
result_last <= result;
end
end
/* the statistic register */
always @(posedge clk or posedge rst) begin
if (rst) begin
statistic[31:16] <= 16'hc001;
statistic[15:0] <= 16'h0;
end else begin
if ( result != result_last ) begin
statistic[15:0] <= statistic[15:0] + 16'h1;
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n", $time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's instruction fetch ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PC, instruction fetch, interface to IC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_if(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_dat_i, icpu_ack_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
// Internal i/f
if_freeze, if_insn, if_pc, flushpipe,
if_stall, no_more_dslot, genpc_refetch, rfe,
except_itlbmiss, except_immufault, except_ibuserr
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Internal i/f
//
input if_freeze;
output [31:0] if_insn;
output [31:0] if_pc;
input flushpipe;
output if_stall;
input no_more_dslot;
output genpc_refetch;
input rfe;
output except_itlbmiss;
output except_immufault;
output except_ibuserr;
//
// Internal wires and regs
//
reg [31:0] insn_saved;
reg [31:0] addr_saved;
reg saved;
//
// IF stage insn
//
assign if_insn = icpu_err_i | no_more_dslot | rfe ? {`OR1200_OR32_NOP, 26'h041_0000} : saved ? insn_saved : icpu_ack_i ? icpu_dat_i : {`OR1200_OR32_NOP, 26'h061_0000};
assign if_pc = saved ? addr_saved : icpu_adr_i;
// assign if_stall = !icpu_err_i & !icpu_ack_i & !saved & !no_more_dslot;
assign if_stall = !icpu_err_i & !icpu_ack_i & !saved;
assign genpc_refetch = saved & icpu_ack_i;
assign except_itlbmiss = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_TE) & !no_more_dslot;
assign except_immufault = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_PE) & !no_more_dslot;
assign except_ibuserr = icpu_err_i & (icpu_tag_i == `OR1200_ITAG_BE) & !no_more_dslot;
//
// Flag for saved insn/address
//
always @(posedge clk or posedge rst)
if (rst)
saved <= #1 1'b0;
else if (flushpipe)
saved <= #1 1'b0;
else if (icpu_ack_i & if_freeze & !saved)
saved <= #1 1'b1;
else if (!if_freeze)
saved <= #1 1'b0;
//
// Store fetched instruction
//
always @(posedge clk or posedge rst)
if (rst)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (flushpipe)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
else if (icpu_ack_i & if_freeze & !saved)
insn_saved <= #1 icpu_dat_i;
else if (!if_freeze)
insn_saved <= #1 {`OR1200_OR32_NOP, 26'h041_0000};
//
// Store fetched instruction's address
//
always @(posedge clk or posedge rst)
if (rst)
addr_saved <= #1 32'h00000000;
else if (flushpipe)
addr_saved <= #1 32'h00000000;
else if (icpu_ack_i & if_freeze & !saved)
addr_saved <= #1 icpu_adr_i;
else if (!if_freeze)
addr_saved <= #1 icpu_adr_i;
endmodule
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
`include "hi_iso14443a.v"
`include "relay.v"
`include "relay_test.v"
`include "util.v"
`define SNIFFER 3'b000
`define TAGSIM_LISTEN 3'b001
`define TAGSIM_MOD 3'b010
`define READER_LISTEN 3'b011
`define READER_MOD 3'b100
`define FAKE_READER 3'b101
`define FAKE_TAG 3'b110
module fpga(
spck, miso, mosi, ncs,
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk, adc_noe,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg
);
input spck, mosi, ncs;
output miso;
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk, adc_noe;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
input dbg;
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg = 16'b0;
reg [7:0] divisor = 8'b0;
reg [7:0] conf_word = 8'b0;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
4'b0001: conf_word <= shift_reg[7:0]; // FPGA_CMD_SET_CONFREG
4'b0010: divisor <= shift_reg[7:0]; // FPGA_CMD_SET_DIVISOR
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
wire major_mode;
assign major_mode = conf_word[5];
// For the high-frequency simulated tag: what kind of modulation to use.
wire [2:0] hi_simulate_mod_type;
assign hi_simulate_mod_type = conf_word[2:0];
wire [2:0] relay_mod_type;
wire [2:0] mod_type;
wire hisn_ssp_dout;
wire relay_out;
wire relay_active = (hi_simulate_mod_type == `FAKE_READER || hi_simulate_mod_type == `FAKE_TAG || hi_simulate_mod_type == 3'b111);
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_iso14443a hisn(
pck0, ck_1356meg, ck_1356megb,
, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, hisn_ssp_dout, hisn_ssp_clk,
cross_hi, cross_lo,
,
mod_type
);
relay r(
ck_1356meg,
~relay_active,
dbg,
hi_simulate_mod_type,
relay_mod_type,
relay_out,
hisn_ssp_din,
relay_relay
);
relay_test rt(
pck0, ck_1356meg, ck_1356megb,
rt_ssp_frame, rt_ssp_din, ssp_dout, rt_ssp_clk,
dbg, rt_data_out,
hi_simulate_mod_type
);
mux2 mux_ssp_clk (major_mode, ssp_clk, hisn_ssp_clk, rt_ssp_clk);
mux2 mux_ssp_din (major_mode, ssp_din, hisn_ssp_din, rt_ssp_din);
mux2 mux_ssp_frame (major_mode, ssp_frame, hisn_ssp_frame, rt_ssp_frame);
mux2 mux_pwr_oe1 (major_mode, pwr_oe1, hisn_pwr_oe1, 1'b0);
mux2 mux_pwr_oe2 (major_mode, pwr_oe2, hisn_pwr_oe2, 1'b0);
mux2 mux_pwr_oe3 (major_mode, pwr_oe3, hisn_pwr_oe3, 1'b0);
mux2 mux_pwr_oe4 (major_mode, pwr_oe4, hisn_pwr_oe4, 1'b0);
mux2 mux_pwr_lo (major_mode, pwr_lo, relay_relay, rt_data_out);
mux2 mux_pwr_hi (major_mode, pwr_hi, hisn_pwr_hi, 1'b0);
mux2 mux_adc_clk (major_mode, adc_clk, hisn_adc_clk, 1'b0);
assign mod_type = relay_active ? relay_mod_type : hi_simulate_mod_type;
assign hisn_ssp_dout = relay_active ? relay_out : ssp_dout;
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
endmodule
|
module add_subZ0_add_r_inj (mult_out_r,out_inner_prod_r,un2_pre_out_10,un2_pre_out_9,un2_pre_out_7,un2_pre_out_6,un2_pre_out_5,un2_pre_out_4,un2_pre_out_3,un2_pre_out_2,un2_pre_out_1,acc_clear,un2_pre_out_s_11,N_26_i,N_20_i);
input [11:0] mult_out_r ;
input [11:0] out_inner_prod_r ;
output un2_pre_out_10 ;
output un2_pre_out_9 ;
output un2_pre_out_7 ;
output un2_pre_out_6 ;
output un2_pre_out_5 ;
output un2_pre_out_4 ;
output un2_pre_out_3 ;
output un2_pre_out_2 ;
output un2_pre_out_1 ;
input acc_clear ;
output un2_pre_out_s_11 ;
output N_26_i ;
output N_20_i ;
wire un2_pre_out_10 ;
wire un2_pre_out_9 ;
wire un2_pre_out_7 ;
wire un2_pre_out_6 ;
wire un2_pre_out_5 ;
wire un2_pre_out_4 ;
wire un2_pre_out_3 ;
wire un2_pre_out_2 ;
wire un2_pre_out_1 ;
wire acc_clear ;
wire un2_pre_out_s_11 ;
wire N_26_i ;
wire N_20_i ;
wire [8:0] un2_pre_out ;
wire VCC ;
wire un2_pre_out_axb_1 ;
wire un2_pre_out_axb_2 ;
wire un2_pre_out_axb_3 ;
wire un2_pre_out_axb_4 ;
wire un2_pre_out_axb_5 ;
wire un2_pre_out_axb_6 ;
wire un2_pre_out_axb_7 ;
wire un2_pre_out_axb_8 ;
wire un2_pre_out_axb_9 ;
wire un2_pre_out_axb_10 ;
wire un2_pre_out_axb_11 ;
wire un2_pre_out_cry_10 ;
wire un2_pre_out_cry_9 ;
wire un2_pre_out_cry_8 ;
wire un2_pre_out_cry_7 ;
wire un2_pre_out_cry_6 ;
wire un2_pre_out_cry_5 ;
wire un2_pre_out_cry_4 ;
wire un2_pre_out_cry_3 ;
wire un2_pre_out_cry_2 ;
wire un2_pre_out_cry_1 ;
wire un2_pre_out_cry_0 ;
wire GND ;
// instances
LUT2 un2_pre_out_axb_0(.I0(mult_out_r[0:0]),.I1(out_inner_prod_r[0:0]),.O(un2_pre_out[0:0]));
defparam un2_pre_out_axb_0.INIT=4'h6;
LUT2 un2_pre_out_axb_1_cZ(.I0(mult_out_r[1:1]),.I1(out_inner_prod_r[1:1]),.O(un2_pre_out_axb_1));
defparam un2_pre_out_axb_1_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_2_cZ(.I0(mult_out_r[2:2]),.I1(out_inner_prod_r[2:2]),.O(un2_pre_out_axb_2));
defparam un2_pre_out_axb_2_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_3_cZ(.I0(mult_out_r[3:3]),.I1(out_inner_prod_r[3:3]),.O(un2_pre_out_axb_3));
defparam un2_pre_out_axb_3_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_4_cZ(.I0(mult_out_r[4:4]),.I1(out_inner_prod_r[4:4]),.O(un2_pre_out_axb_4));
defparam un2_pre_out_axb_4_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_5_cZ(.I0(mult_out_r[5:5]),.I1(out_inner_prod_r[5:5]),.O(un2_pre_out_axb_5));
defparam un2_pre_out_axb_5_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_6_cZ(.I0(mult_out_r[6:6]),.I1(out_inner_prod_r[6:6]),.O(un2_pre_out_axb_6));
defparam un2_pre_out_axb_6_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_7_cZ(.I0(mult_out_r[7:7]),.I1(out_inner_prod_r[7:7]),.O(un2_pre_out_axb_7));
defparam un2_pre_out_axb_7_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_8_cZ(.I0(mult_out_r[8:8]),.I1(out_inner_prod_r[8:8]),.O(un2_pre_out_axb_8));
defparam un2_pre_out_axb_8_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_9_cZ(.I0(mult_out_r[9:9]),.I1(out_inner_prod_r[9:9]),.O(un2_pre_out_axb_9));
defparam un2_pre_out_axb_9_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_10_cZ(.I0(mult_out_r[10:10]),.I1(out_inner_prod_r[10:10]),.O(un2_pre_out_axb_10));
defparam un2_pre_out_axb_10_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_11_cZ(.I0(mult_out_r[11:11]),.I1(out_inner_prod_r[11:11]),.O(un2_pre_out_axb_11));
defparam un2_pre_out_axb_11_cZ.INIT=4'h6;
XORCY un2_pre_out_s_11_c(.LI(un2_pre_out_axb_11),.CI(un2_pre_out_cry_10),.O(un2_pre_out_s_11));
XORCY un2_pre_out_s_10(.LI(un2_pre_out_axb_10),.CI(un2_pre_out_cry_9),.O(un2_pre_out_10));
MUXCY_L un2_pre_out_cry_10_cZ(.DI(mult_out_r[10:10]),.CI(un2_pre_out_cry_9),.S(un2_pre_out_axb_10),.LO(un2_pre_out_cry_10));
XORCY un2_pre_out_s_9(.LI(un2_pre_out_axb_9),.CI(un2_pre_out_cry_8),.O(un2_pre_out_9));
MUXCY_L un2_pre_out_cry_9_cZ(.DI(mult_out_r[9:9]),.CI(un2_pre_out_cry_8),.S(un2_pre_out_axb_9),.LO(un2_pre_out_cry_9));
XORCY un2_pre_out_s_8(.LI(un2_pre_out_axb_8),.CI(un2_pre_out_cry_7),.O(un2_pre_out[8:8]));
MUXCY_L un2_pre_out_cry_8_cZ(.DI(mult_out_r[8:8]),.CI(un2_pre_out_cry_7),.S(un2_pre_out_axb_8),.LO(un2_pre_out_cry_8));
XORCY un2_pre_out_s_7(.LI(un2_pre_out_axb_7),.CI(un2_pre_out_cry_6),.O(un2_pre_out_7));
MUXCY_L un2_pre_out_cry_7_cZ(.DI(mult_out_r[7:7]),.CI(un2_pre_out_cry_6),.S(un2_pre_out_axb_7),.LO(un2_pre_out_cry_7));
XORCY un2_pre_out_s_6(.LI(un2_pre_out_axb_6),.CI(un2_pre_out_cry_5),.O(un2_pre_out_6));
MUXCY_L un2_pre_out_cry_6_cZ(.DI(mult_out_r[6:6]),.CI(un2_pre_out_cry_5),.S(un2_pre_out_axb_6),.LO(un2_pre_out_cry_6));
XORCY un2_pre_out_s_5(.LI(un2_pre_out_axb_5),.CI(un2_pre_out_cry_4),.O(un2_pre_out_5));
MUXCY_L un2_pre_out_cry_5_cZ(.DI(mult_out_r[5:5]),.CI(un2_pre_out_cry_4),.S(un2_pre_out_axb_5),.LO(un2_pre_out_cry_5));
XORCY un2_pre_out_s_4(.LI(un2_pre_out_axb_4),.CI(un2_pre_out_cry_3),.O(un2_pre_out_4));
MUXCY_L un2_pre_out_cry_4_cZ(.DI(mult_out_r[4:4]),.CI(un2_pre_out_cry_3),.S(un2_pre_out_axb_4),.LO(un2_pre_out_cry_4));
XORCY un2_pre_out_s_3(.LI(un2_pre_out_axb_3),.CI(un2_pre_out_cry_2),.O(un2_pre_out_3));
MUXCY_L un2_pre_out_cry_3_cZ(.DI(mult_out_r[3:3]),.CI(un2_pre_out_cry_2),.S(un2_pre_out_axb_3),.LO(un2_pre_out_cry_3));
XORCY un2_pre_out_s_2(.LI(un2_pre_out_axb_2),.CI(un2_pre_out_cry_1),.O(un2_pre_out_2));
MUXCY_L un2_pre_out_cry_2_cZ(.DI(mult_out_r[2:2]),.CI(un2_pre_out_cry_1),.S(un2_pre_out_axb_2),.LO(un2_pre_out_cry_2));
XORCY un2_pre_out_s_1(.LI(un2_pre_out_axb_1),.CI(un2_pre_out_cry_0),.O(un2_pre_out_1));
MUXCY_L un2_pre_out_cry_1_cZ(.DI(mult_out_r[1:1]),.CI(un2_pre_out_cry_0),.S(un2_pre_out_axb_1),.LO(un2_pre_out_cry_1));
MUXCY_L un2_pre_out_cry_0_cZ(.DI(mult_out_r[0:0]),.CI(GND),.S(un2_pre_out[0:0]),.LO(un2_pre_out_cry_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT4 un2_pre_out_s_8_RNIQ3111_o6(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out_s_11),.O(N_26_i));
defparam un2_pre_out_s_8_RNIQ3111_o6.INIT=16'h3220;
LUT5 un2_pre_out_s_8_RNIQ3111_o5(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[8:8]),.I4(un2_pre_out_s_11),.O(N_20_i));
defparam un2_pre_out_s_8_RNIQ3111_o5.INIT=32'h33011300;
endmodule
module add_subZ0_add_r_1_inj (mult_out_i,out_inner_prod_i,un2_pre_out_10,un2_pre_out_9,un2_pre_out_8,un2_pre_out_7,un2_pre_out_6,un2_pre_out_5,un2_pre_out_4,un2_pre_out_3,un2_pre_out_2,un2_pre_out_1,un2_pre_out_s_11_0);
input [11:0] mult_out_i ;
input [11:0] out_inner_prod_i ;
output un2_pre_out_10 ;
output un2_pre_out_9 ;
output un2_pre_out_8 ;
output un2_pre_out_7 ;
output un2_pre_out_6 ;
output un2_pre_out_5 ;
output un2_pre_out_4 ;
output un2_pre_out_3 ;
output un2_pre_out_2 ;
output un2_pre_out_1 ;
output un2_pre_out_s_11_0 ;
wire un2_pre_out_10 ;
wire un2_pre_out_9 ;
wire un2_pre_out_8 ;
wire un2_pre_out_7 ;
wire un2_pre_out_6 ;
wire un2_pre_out_5 ;
wire un2_pre_out_4 ;
wire un2_pre_out_3 ;
wire un2_pre_out_2 ;
wire un2_pre_out_1 ;
wire un2_pre_out_s_11_0 ;
wire un2_pre_out ;
wire un2_pre_out_axb_1 ;
wire un2_pre_out_axb_2 ;
wire un2_pre_out_axb_3 ;
wire un2_pre_out_axb_4 ;
wire un2_pre_out_axb_5 ;
wire un2_pre_out_axb_6 ;
wire un2_pre_out_axb_7 ;
wire un2_pre_out_axb_8 ;
wire un2_pre_out_axb_9 ;
wire un2_pre_out_axb_10 ;
wire un2_pre_out_axb_11 ;
wire un2_pre_out_cry_10 ;
wire un2_pre_out_cry_9 ;
wire un2_pre_out_cry_8 ;
wire un2_pre_out_cry_7 ;
wire un2_pre_out_cry_6 ;
wire un2_pre_out_cry_5 ;
wire un2_pre_out_cry_4 ;
wire un2_pre_out_cry_3 ;
wire un2_pre_out_cry_2 ;
wire un2_pre_out_cry_1 ;
wire un2_pre_out_cry_0 ;
wire GND ;
wire VCC ;
// instances
LUT2 un2_pre_out_axb_0(.I0(mult_out_i[0:0]),.I1(out_inner_prod_i[0:0]),.O(un2_pre_out));
defparam un2_pre_out_axb_0.INIT=4'h6;
LUT2 un2_pre_out_axb_1_cZ(.I0(mult_out_i[1:1]),.I1(out_inner_prod_i[1:1]),.O(un2_pre_out_axb_1));
defparam un2_pre_out_axb_1_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_2_cZ(.I0(mult_out_i[2:2]),.I1(out_inner_prod_i[2:2]),.O(un2_pre_out_axb_2));
defparam un2_pre_out_axb_2_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_3_cZ(.I0(mult_out_i[3:3]),.I1(out_inner_prod_i[3:3]),.O(un2_pre_out_axb_3));
defparam un2_pre_out_axb_3_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_4_cZ(.I0(mult_out_i[4:4]),.I1(out_inner_prod_i[4:4]),.O(un2_pre_out_axb_4));
defparam un2_pre_out_axb_4_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_5_cZ(.I0(mult_out_i[5:5]),.I1(out_inner_prod_i[5:5]),.O(un2_pre_out_axb_5));
defparam un2_pre_out_axb_5_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_6_cZ(.I0(mult_out_i[6:6]),.I1(out_inner_prod_i[6:6]),.O(un2_pre_out_axb_6));
defparam un2_pre_out_axb_6_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_7_cZ(.I0(mult_out_i[7:7]),.I1(out_inner_prod_i[7:7]),.O(un2_pre_out_axb_7));
defparam un2_pre_out_axb_7_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_8_cZ(.I0(mult_out_i[8:8]),.I1(out_inner_prod_i[8:8]),.O(un2_pre_out_axb_8));
defparam un2_pre_out_axb_8_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_9_cZ(.I0(mult_out_i[9:9]),.I1(out_inner_prod_i[9:9]),.O(un2_pre_out_axb_9));
defparam un2_pre_out_axb_9_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_10_cZ(.I0(mult_out_i[10:10]),.I1(out_inner_prod_i[10:10]),.O(un2_pre_out_axb_10));
defparam un2_pre_out_axb_10_cZ.INIT=4'h6;
LUT2 un2_pre_out_axb_11_cZ(.I0(mult_out_i[11:11]),.I1(out_inner_prod_i[11:11]),.O(un2_pre_out_axb_11));
defparam un2_pre_out_axb_11_cZ.INIT=4'h6;
XORCY un2_pre_out_s_11(.LI(un2_pre_out_axb_11),.CI(un2_pre_out_cry_10),.O(un2_pre_out_s_11_0));
XORCY un2_pre_out_s_10(.LI(un2_pre_out_axb_10),.CI(un2_pre_out_cry_9),.O(un2_pre_out_10));
MUXCY_L un2_pre_out_cry_10_cZ(.DI(mult_out_i[10:10]),.CI(un2_pre_out_cry_9),.S(un2_pre_out_axb_10),.LO(un2_pre_out_cry_10));
XORCY un2_pre_out_s_9(.LI(un2_pre_out_axb_9),.CI(un2_pre_out_cry_8),.O(un2_pre_out_9));
MUXCY_L un2_pre_out_cry_9_cZ(.DI(mult_out_i[9:9]),.CI(un2_pre_out_cry_8),.S(un2_pre_out_axb_9),.LO(un2_pre_out_cry_9));
XORCY un2_pre_out_s_8(.LI(un2_pre_out_axb_8),.CI(un2_pre_out_cry_7),.O(un2_pre_out_8));
MUXCY_L un2_pre_out_cry_8_cZ(.DI(mult_out_i[8:8]),.CI(un2_pre_out_cry_7),.S(un2_pre_out_axb_8),.LO(un2_pre_out_cry_8));
XORCY un2_pre_out_s_7(.LI(un2_pre_out_axb_7),.CI(un2_pre_out_cry_6),.O(un2_pre_out_7));
MUXCY_L un2_pre_out_cry_7_cZ(.DI(mult_out_i[7:7]),.CI(un2_pre_out_cry_6),.S(un2_pre_out_axb_7),.LO(un2_pre_out_cry_7));
XORCY un2_pre_out_s_6(.LI(un2_pre_out_axb_6),.CI(un2_pre_out_cry_5),.O(un2_pre_out_6));
MUXCY_L un2_pre_out_cry_6_cZ(.DI(mult_out_i[6:6]),.CI(un2_pre_out_cry_5),.S(un2_pre_out_axb_6),.LO(un2_pre_out_cry_6));
XORCY un2_pre_out_s_5(.LI(un2_pre_out_axb_5),.CI(un2_pre_out_cry_4),.O(un2_pre_out_5));
MUXCY_L un2_pre_out_cry_5_cZ(.DI(mult_out_i[5:5]),.CI(un2_pre_out_cry_4),.S(un2_pre_out_axb_5),.LO(un2_pre_out_cry_5));
XORCY un2_pre_out_s_4(.LI(un2_pre_out_axb_4),.CI(un2_pre_out_cry_3),.O(un2_pre_out_4));
MUXCY_L un2_pre_out_cry_4_cZ(.DI(mult_out_i[4:4]),.CI(un2_pre_out_cry_3),.S(un2_pre_out_axb_4),.LO(un2_pre_out_cry_4));
XORCY un2_pre_out_s_3(.LI(un2_pre_out_axb_3),.CI(un2_pre_out_cry_2),.O(un2_pre_out_3));
MUXCY_L un2_pre_out_cry_3_cZ(.DI(mult_out_i[3:3]),.CI(un2_pre_out_cry_2),.S(un2_pre_out_axb_3),.LO(un2_pre_out_cry_3));
XORCY un2_pre_out_s_2(.LI(un2_pre_out_axb_2),.CI(un2_pre_out_cry_1),.O(un2_pre_out_2));
MUXCY_L un2_pre_out_cry_2_cZ(.DI(mult_out_i[2:2]),.CI(un2_pre_out_cry_1),.S(un2_pre_out_axb_2),.LO(un2_pre_out_cry_2));
XORCY un2_pre_out_s_1(.LI(un2_pre_out_axb_1),.CI(un2_pre_out_cry_0),.O(un2_pre_out_1));
MUXCY_L un2_pre_out_cry_1_cZ(.DI(mult_out_i[1:1]),.CI(un2_pre_out_cry_0),.S(un2_pre_out_axb_1),.LO(un2_pre_out_cry_1));
MUXCY_L un2_pre_out_cry_0_cZ(.DI(mult_out_i[0:0]),.CI(GND),.S(un2_pre_out),.LO(un2_pre_out_cry_0));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
endmodule
module add_subZ1_inj (pre_out_r,in_a_r_reg,in_b_r_reg,mult2_out_0,P_uc_34_0,PATTERNDETECT_7,clk);
output [23:7] pre_out_r ;
input [11:0] in_a_r_reg ;
input [11:0] in_b_r_reg ;
input [23:0] mult2_out_0 ;
input [47:24] P_uc_34_0 ;
output PATTERNDETECT_7 ;
input clk ;
wire PATTERNDETECT_7 ;
wire clk ;
wire [29:0] ACOUT_7 ;
wire [17:0] BCOUT_7 ;
wire [3:0] CARRYOUT_7 ;
wire [6:0] un2_pre_out ;
wire [47:24] P_uc_7 ;
wire [47:0] PCOUT_7 ;
wire CARRYCASCOUT_7 ;
wire MULTSIGNOUT_7 ;
wire OVERFLOW_7 ;
wire PATTERNBDETECT_7 ;
wire UNDERFLOW_7 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc268(.ACOUT(ACOUT_7[29:0]),.BCOUT(BCOUT_7[17:0]),.CARRYCASCOUT(CARRYCASCOUT_7),.CARRYOUT(CARRYOUT_7[3:0]),.MULTSIGNOUT(MULTSIGNOUT_7),.OVERFLOW(OVERFLOW_7),.P({P_uc_7[47:24],pre_out_r[23:7],un2_pre_out[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_7),.PATTERNDETECT(PATTERNDETECT_7),.PCOUT(PCOUT_7[47:0]),.UNDERFLOW(UNDERFLOW_7),.A({in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(VCC),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_34_0[47:24],mult2_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc268.ACASCREG=0;
defparam desc268.ADREG=0;
defparam desc268.ALUMODEREG=0;
defparam desc268.AREG=0;
defparam desc268.AUTORESET_PATDET="NO_RESET";
defparam desc268.A_INPUT="DIRECT";
defparam desc268.BCASCREG=0;
defparam desc268.BREG=0;
defparam desc268.B_INPUT="DIRECT";
defparam desc268.CARRYINREG=0;
defparam desc268.CARRYINSELREG=0;
defparam desc268.CREG=1;
defparam desc268.DREG=0;
defparam desc268.INMODEREG=0;
defparam desc268.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc268.MREG=1;
defparam desc268.OPMODEREG=0;
defparam desc268.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc268.PREG=0;
defparam desc268.SEL_MASK="MASK";
defparam desc268.USE_DPORT="FALSE";
defparam desc268.USE_MULT="MULTIPLY";
defparam desc268.USE_PATTERN_DETECT="PATDET";
defparam desc268.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ1_1_inj (pre_out_i,vec_out_r_AQ_2,in_b_i_reg,mult4_out_0,P_uc_27_0,PATTERNDETECT_3,clk);
output [23:7] pre_out_i ;
input [11:0] vec_out_r_AQ_2 ;
input [11:0] in_b_i_reg ;
input [23:0] mult4_out_0 ;
input [47:24] P_uc_27_0 ;
output PATTERNDETECT_3 ;
input clk ;
wire PATTERNDETECT_3 ;
wire clk ;
wire [29:0] ACOUT_3 ;
wire [17:0] BCOUT_3 ;
wire [3:0] CARRYOUT_3 ;
wire [6:0] un2_pre_out ;
wire [47:24] P_uc_3 ;
wire [47:0] PCOUT_3 ;
wire CARRYCASCOUT_3 ;
wire MULTSIGNOUT_3 ;
wire OVERFLOW_3 ;
wire PATTERNBDETECT_3 ;
wire UNDERFLOW_3 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc480(.ACOUT(ACOUT_3[29:0]),.BCOUT(BCOUT_3[17:0]),.CARRYCASCOUT(CARRYCASCOUT_3),.CARRYOUT(CARRYOUT_3[3:0]),.MULTSIGNOUT(MULTSIGNOUT_3),.OVERFLOW(OVERFLOW_3),.P({P_uc_3[47:24],pre_out_i[23:7],un2_pre_out[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_3),.PATTERNDETECT(PATTERNDETECT_3),.PCOUT(PCOUT_3[47:0]),.UNDERFLOW(UNDERFLOW_3),.A({vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_27_0[47:24],mult4_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc480.ACASCREG=2;
defparam desc480.ADREG=0;
defparam desc480.ALUMODEREG=0;
defparam desc480.AREG=2;
defparam desc480.AUTORESET_PATDET="NO_RESET";
defparam desc480.A_INPUT="DIRECT";
defparam desc480.BCASCREG=1;
defparam desc480.BREG=1;
defparam desc480.B_INPUT="DIRECT";
defparam desc480.CARRYINREG=0;
defparam desc480.CARRYINSELREG=0;
defparam desc480.CREG=1;
defparam desc480.DREG=0;
defparam desc480.INMODEREG=0;
defparam desc480.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc480.MREG=0;
defparam desc480.OPMODEREG=0;
defparam desc480.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc480.PREG=0;
defparam desc480.SEL_MASK="MASK";
defparam desc480.USE_DPORT="FALSE";
defparam desc480.USE_MULT="MULTIPLY";
defparam desc480.USE_PATTERN_DETECT="PATDET";
defparam desc480.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ1_2_inj (pre_out_i,vec_out_r_AQ_1,in_b_i_reg,mult4_out_0,P_uc_23_0,PATTERNDETECT_1,clk);
output [23:7] pre_out_i ;
input [11:0] vec_out_r_AQ_1 ;
input [11:0] in_b_i_reg ;
input [23:0] mult4_out_0 ;
input [47:24] P_uc_23_0 ;
output PATTERNDETECT_1 ;
input clk ;
wire PATTERNDETECT_1 ;
wire clk ;
wire [29:0] ACOUT_1 ;
wire [17:0] BCOUT_1 ;
wire [3:0] CARRYOUT_1 ;
wire [6:0] un2_pre_out ;
wire [47:24] P_uc_1 ;
wire [47:0] PCOUT_1 ;
wire CARRYCASCOUT_1 ;
wire MULTSIGNOUT_1 ;
wire OVERFLOW_1 ;
wire PATTERNBDETECT_1 ;
wire UNDERFLOW_1 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc535(.ACOUT(ACOUT_1[29:0]),.BCOUT(BCOUT_1[17:0]),.CARRYCASCOUT(CARRYCASCOUT_1),.CARRYOUT(CARRYOUT_1[3:0]),.MULTSIGNOUT(MULTSIGNOUT_1),.OVERFLOW(OVERFLOW_1),.P({P_uc_1[47:24],pre_out_i[23:7],un2_pre_out[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_1),.PATTERNDETECT(PATTERNDETECT_1),.PCOUT(PCOUT_1[47:0]),.UNDERFLOW(UNDERFLOW_1),.A({vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_23_0[47:24],mult4_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc535.ACASCREG=2;
defparam desc535.ADREG=0;
defparam desc535.ALUMODEREG=0;
defparam desc535.AREG=2;
defparam desc535.AUTORESET_PATDET="NO_RESET";
defparam desc535.A_INPUT="DIRECT";
defparam desc535.BCASCREG=1;
defparam desc535.BREG=1;
defparam desc535.B_INPUT="DIRECT";
defparam desc535.CARRYINREG=0;
defparam desc535.CARRYINSELREG=0;
defparam desc535.CREG=1;
defparam desc535.DREG=0;
defparam desc535.INMODEREG=0;
defparam desc535.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc535.MREG=0;
defparam desc535.OPMODEREG=0;
defparam desc535.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc535.PREG=0;
defparam desc535.SEL_MASK="MASK";
defparam desc535.USE_DPORT="FALSE";
defparam desc535.USE_MULT="MULTIPLY";
defparam desc535.USE_PATTERN_DETECT="PATDET";
defparam desc535.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ1_3_inj (pre_out_i,vec_out_r_AQ_0,in_b_i_reg,mult4_out_0,P_uc_19_0,PATTERNDETECT,clk);
output [23:7] pre_out_i ;
input [11:0] vec_out_r_AQ_0 ;
input [11:0] in_b_i_reg ;
input [23:0] mult4_out_0 ;
input [47:24] P_uc_19_0 ;
output PATTERNDETECT ;
input clk ;
wire PATTERNDETECT ;
wire clk ;
wire [29:0] ACOUT ;
wire [17:0] BCOUT ;
wire [3:0] CARRYOUT ;
wire [6:0] un2_pre_out ;
wire [47:24] P_uc ;
wire [47:0] PCOUT ;
wire CARRYCASCOUT ;
wire MULTSIGNOUT ;
wire OVERFLOW ;
wire PATTERNBDETECT ;
wire UNDERFLOW ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc590(.ACOUT(ACOUT[29:0]),.BCOUT(BCOUT[17:0]),.CARRYCASCOUT(CARRYCASCOUT),.CARRYOUT(CARRYOUT[3:0]),.MULTSIGNOUT(MULTSIGNOUT),.OVERFLOW(OVERFLOW),.P({P_uc[47:24],pre_out_i[23:7],un2_pre_out[6:0]}),.PATTERNBDETECT(PATTERNBDETECT),.PATTERNDETECT(PATTERNDETECT),.PCOUT(PCOUT[47:0]),.UNDERFLOW(UNDERFLOW),.A({vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_19_0[47:24],mult4_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc590.ACASCREG=2;
defparam desc590.ADREG=0;
defparam desc590.ALUMODEREG=0;
defparam desc590.AREG=2;
defparam desc590.AUTORESET_PATDET="NO_RESET";
defparam desc590.A_INPUT="DIRECT";
defparam desc590.BCASCREG=1;
defparam desc590.BREG=1;
defparam desc590.B_INPUT="DIRECT";
defparam desc590.CARRYINREG=0;
defparam desc590.CARRYINSELREG=0;
defparam desc590.CREG=1;
defparam desc590.DREG=0;
defparam desc590.INMODEREG=0;
defparam desc590.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc590.MREG=0;
defparam desc590.OPMODEREG=0;
defparam desc590.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc590.PREG=0;
defparam desc590.SEL_MASK="MASK";
defparam desc590.USE_DPORT="FALSE";
defparam desc590.USE_MULT="MULTIPLY";
defparam desc590.USE_PATTERN_DETECT="PATDET";
defparam desc590.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ1_4_inj (pre_out_i,vec_out_r_AQ_3,in_b_i_reg,mult4_out_0,P_uc_31_0,PATTERNDETECT_5,clk);
output [23:7] pre_out_i ;
input [11:0] vec_out_r_AQ_3 ;
input [11:0] in_b_i_reg ;
input [23:0] mult4_out_0 ;
input [47:24] P_uc_31_0 ;
output PATTERNDETECT_5 ;
input clk ;
wire PATTERNDETECT_5 ;
wire clk ;
wire [29:0] ACOUT_5 ;
wire [17:0] BCOUT_5 ;
wire [3:0] CARRYOUT_5 ;
wire [6:0] un2_pre_out ;
wire [47:24] P_uc_5 ;
wire [47:0] PCOUT_5 ;
wire CARRYCASCOUT_5 ;
wire MULTSIGNOUT_5 ;
wire OVERFLOW_5 ;
wire PATTERNBDETECT_5 ;
wire UNDERFLOW_5 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc645(.ACOUT(ACOUT_5[29:0]),.BCOUT(BCOUT_5[17:0]),.CARRYCASCOUT(CARRYCASCOUT_5),.CARRYOUT(CARRYOUT_5[3:0]),.MULTSIGNOUT(MULTSIGNOUT_5),.OVERFLOW(OVERFLOW_5),.P({P_uc_5[47:24],pre_out_i[23:7],un2_pre_out[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_5),.PATTERNDETECT(PATTERNDETECT_5),.PCOUT(PCOUT_5[47:0]),.UNDERFLOW(UNDERFLOW_5),.A({vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_31_0[47:24],mult4_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc645.ACASCREG=2;
defparam desc645.ADREG=0;
defparam desc645.ALUMODEREG=0;
defparam desc645.AREG=2;
defparam desc645.AUTORESET_PATDET="NO_RESET";
defparam desc645.A_INPUT="DIRECT";
defparam desc645.BCASCREG=1;
defparam desc645.BREG=1;
defparam desc645.B_INPUT="DIRECT";
defparam desc645.CARRYINREG=0;
defparam desc645.CARRYINSELREG=0;
defparam desc645.CREG=1;
defparam desc645.DREG=0;
defparam desc645.INMODEREG=0;
defparam desc645.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc645.MREG=0;
defparam desc645.OPMODEREG=0;
defparam desc645.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc645.PREG=0;
defparam desc645.SEL_MASK="MASK";
defparam desc645.USE_DPORT="FALSE";
defparam desc645.USE_MULT="MULTIPLY";
defparam desc645.USE_PATTERN_DETECT="PATDET";
defparam desc645.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ2_inj (pre_out_i,in_a_i_reg,in_b_r_reg,mult3_out_0,P_uc_35_0,PATTERNDETECT_8,clk);
output [23:7] pre_out_i ;
input [11:0] in_a_i_reg ;
input [11:0] in_b_r_reg ;
input [23:0] mult3_out_0 ;
input [47:24] P_uc_35_0 ;
output PATTERNDETECT_8 ;
input clk ;
wire PATTERNDETECT_8 ;
wire clk ;
wire [29:0] ACOUT_8 ;
wire [17:0] BCOUT_8 ;
wire [3:0] CARRYOUT_8 ;
wire [6:0] output_Z ;
wire [47:24] P_uc_8 ;
wire [47:0] PCOUT_8 ;
wire CARRYCASCOUT_8 ;
wire MULTSIGNOUT_8 ;
wire OVERFLOW_8 ;
wire PATTERNBDETECT_8 ;
wire UNDERFLOW_8 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc269(.ACOUT(ACOUT_8[29:0]),.BCOUT(BCOUT_8[17:0]),.CARRYCASCOUT(CARRYCASCOUT_8),.CARRYOUT(CARRYOUT_8[3:0]),.MULTSIGNOUT(MULTSIGNOUT_8),.OVERFLOW(OVERFLOW_8),.P({P_uc_8[47:24],pre_out_i[23:7],output_Z[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_8),.PATTERNDETECT(PATTERNDETECT_8),.PCOUT(PCOUT_8[47:0]),.UNDERFLOW(UNDERFLOW_8),.A({in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,VCC,VCC}),.B({in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(VCC),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_35_0[47:24],mult3_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc269.ACASCREG=0;
defparam desc269.ADREG=0;
defparam desc269.ALUMODEREG=0;
defparam desc269.AREG=0;
defparam desc269.AUTORESET_PATDET="NO_RESET";
defparam desc269.A_INPUT="DIRECT";
defparam desc269.BCASCREG=0;
defparam desc269.BREG=0;
defparam desc269.B_INPUT="DIRECT";
defparam desc269.CARRYINREG=0;
defparam desc269.CARRYINSELREG=0;
defparam desc269.CREG=1;
defparam desc269.DREG=0;
defparam desc269.INMODEREG=0;
defparam desc269.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc269.MREG=1;
defparam desc269.OPMODEREG=0;
defparam desc269.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc269.PREG=0;
defparam desc269.SEL_MASK="MASK";
defparam desc269.USE_DPORT="FALSE";
defparam desc269.USE_MULT="MULTIPLY";
defparam desc269.USE_PATTERN_DETECT="PATDET";
defparam desc269.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ2_1_inj (pre_out_r,vec_out_i_AQ_2,in_b_i_reg,mult1_out_0,P_uc_24_0,PATTERNDETECT_4,clk);
output [23:7] pre_out_r ;
input [11:0] vec_out_i_AQ_2 ;
input [11:0] in_b_i_reg ;
input [23:0] mult1_out_0 ;
input [47:24] P_uc_24_0 ;
output PATTERNDETECT_4 ;
input clk ;
wire PATTERNDETECT_4 ;
wire clk ;
wire [29:0] ACOUT_4 ;
wire [17:0] BCOUT_4 ;
wire [3:0] CARRYOUT_4 ;
wire [6:0] output_Z ;
wire [47:24] P_uc_4 ;
wire [47:0] PCOUT_4 ;
wire CARRYCASCOUT_4 ;
wire MULTSIGNOUT_4 ;
wire OVERFLOW_4 ;
wire PATTERNBDETECT_4 ;
wire UNDERFLOW_4 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc479(.ACOUT(ACOUT_4[29:0]),.BCOUT(BCOUT_4[17:0]),.CARRYCASCOUT(CARRYCASCOUT_4),.CARRYOUT(CARRYOUT_4[3:0]),.MULTSIGNOUT(MULTSIGNOUT_4),.OVERFLOW(OVERFLOW_4),.P({P_uc_4[47:24],pre_out_r[23:7],output_Z[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_4),.PATTERNDETECT(PATTERNDETECT_4),.PCOUT(PCOUT_4[47:0]),.UNDERFLOW(UNDERFLOW_4),.A({vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,VCC,VCC}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_24_0[47:24],mult1_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc479.ACASCREG=2;
defparam desc479.ADREG=0;
defparam desc479.ALUMODEREG=0;
defparam desc479.AREG=2;
defparam desc479.AUTORESET_PATDET="NO_RESET";
defparam desc479.A_INPUT="DIRECT";
defparam desc479.BCASCREG=1;
defparam desc479.BREG=1;
defparam desc479.B_INPUT="DIRECT";
defparam desc479.CARRYINREG=0;
defparam desc479.CARRYINSELREG=0;
defparam desc479.CREG=1;
defparam desc479.DREG=0;
defparam desc479.INMODEREG=0;
defparam desc479.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc479.MREG=0;
defparam desc479.OPMODEREG=0;
defparam desc479.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc479.PREG=0;
defparam desc479.SEL_MASK="MASK";
defparam desc479.USE_DPORT="FALSE";
defparam desc479.USE_MULT="MULTIPLY";
defparam desc479.USE_PATTERN_DETECT="PATDET";
defparam desc479.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ2_2_inj (pre_out_r,vec_out_i_AQ_1,in_b_i_reg,mult1_out_0,P_uc_20_0,PATTERNDETECT_2,clk);
output [23:7] pre_out_r ;
input [11:0] vec_out_i_AQ_1 ;
input [11:0] in_b_i_reg ;
input [23:0] mult1_out_0 ;
input [47:24] P_uc_20_0 ;
output PATTERNDETECT_2 ;
input clk ;
wire PATTERNDETECT_2 ;
wire clk ;
wire [29:0] ACOUT_2 ;
wire [17:0] BCOUT_2 ;
wire [3:0] CARRYOUT_2 ;
wire [6:0] output_Z ;
wire [47:24] P_uc_2 ;
wire [47:0] PCOUT_2 ;
wire CARRYCASCOUT_2 ;
wire MULTSIGNOUT_2 ;
wire OVERFLOW_2 ;
wire PATTERNBDETECT_2 ;
wire UNDERFLOW_2 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc534(.ACOUT(ACOUT_2[29:0]),.BCOUT(BCOUT_2[17:0]),.CARRYCASCOUT(CARRYCASCOUT_2),.CARRYOUT(CARRYOUT_2[3:0]),.MULTSIGNOUT(MULTSIGNOUT_2),.OVERFLOW(OVERFLOW_2),.P({P_uc_2[47:24],pre_out_r[23:7],output_Z[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_2),.PATTERNDETECT(PATTERNDETECT_2),.PCOUT(PCOUT_2[47:0]),.UNDERFLOW(UNDERFLOW_2),.A({vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,VCC,VCC}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_20_0[47:24],mult1_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc534.ACASCREG=2;
defparam desc534.ADREG=0;
defparam desc534.ALUMODEREG=0;
defparam desc534.AREG=2;
defparam desc534.AUTORESET_PATDET="NO_RESET";
defparam desc534.A_INPUT="DIRECT";
defparam desc534.BCASCREG=1;
defparam desc534.BREG=1;
defparam desc534.B_INPUT="DIRECT";
defparam desc534.CARRYINREG=0;
defparam desc534.CARRYINSELREG=0;
defparam desc534.CREG=1;
defparam desc534.DREG=0;
defparam desc534.INMODEREG=0;
defparam desc534.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc534.MREG=0;
defparam desc534.OPMODEREG=0;
defparam desc534.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc534.PREG=0;
defparam desc534.SEL_MASK="MASK";
defparam desc534.USE_DPORT="FALSE";
defparam desc534.USE_MULT="MULTIPLY";
defparam desc534.USE_PATTERN_DETECT="PATDET";
defparam desc534.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ2_3_inj (pre_out_r,vec_out_i_AQ_0,in_b_i_reg,mult1_out_0,P_uc_16_0,PATTERNDETECT_0,clk);
output [23:7] pre_out_r ;
input [11:0] vec_out_i_AQ_0 ;
input [11:0] in_b_i_reg ;
input [23:0] mult1_out_0 ;
input [47:24] P_uc_16_0 ;
output PATTERNDETECT_0 ;
input clk ;
wire PATTERNDETECT_0 ;
wire clk ;
wire [29:0] ACOUT_0 ;
wire [17:0] BCOUT_0 ;
wire [3:0] CARRYOUT_0 ;
wire [6:0] output_Z ;
wire [47:24] P_uc_0 ;
wire [47:0] PCOUT_0 ;
wire CARRYCASCOUT_0 ;
wire MULTSIGNOUT_0 ;
wire OVERFLOW_0 ;
wire PATTERNBDETECT_0 ;
wire UNDERFLOW_0 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc589(.ACOUT(ACOUT_0[29:0]),.BCOUT(BCOUT_0[17:0]),.CARRYCASCOUT(CARRYCASCOUT_0),.CARRYOUT(CARRYOUT_0[3:0]),.MULTSIGNOUT(MULTSIGNOUT_0),.OVERFLOW(OVERFLOW_0),.P({P_uc_0[47:24],pre_out_r[23:7],output_Z[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_0),.PATTERNDETECT(PATTERNDETECT_0),.PCOUT(PCOUT_0[47:0]),.UNDERFLOW(UNDERFLOW_0),.A({vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,VCC,VCC}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_16_0[47:24],mult1_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc589.ACASCREG=2;
defparam desc589.ADREG=0;
defparam desc589.ALUMODEREG=0;
defparam desc589.AREG=2;
defparam desc589.AUTORESET_PATDET="NO_RESET";
defparam desc589.A_INPUT="DIRECT";
defparam desc589.BCASCREG=1;
defparam desc589.BREG=1;
defparam desc589.B_INPUT="DIRECT";
defparam desc589.CARRYINREG=0;
defparam desc589.CARRYINSELREG=0;
defparam desc589.CREG=1;
defparam desc589.DREG=0;
defparam desc589.INMODEREG=0;
defparam desc589.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc589.MREG=0;
defparam desc589.OPMODEREG=0;
defparam desc589.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc589.PREG=0;
defparam desc589.SEL_MASK="MASK";
defparam desc589.USE_DPORT="FALSE";
defparam desc589.USE_MULT="MULTIPLY";
defparam desc589.USE_PATTERN_DETECT="PATDET";
defparam desc589.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ2_4_inj (pre_out_r,vec_out_i_AQ_3,in_b_i_reg,mult1_out_0,P_uc_28_0,PATTERNDETECT_6,clk);
output [23:7] pre_out_r ;
input [11:0] vec_out_i_AQ_3 ;
input [11:0] in_b_i_reg ;
input [23:0] mult1_out_0 ;
input [47:24] P_uc_28_0 ;
output PATTERNDETECT_6 ;
input clk ;
wire PATTERNDETECT_6 ;
wire clk ;
wire [29:0] ACOUT_6 ;
wire [17:0] BCOUT_6 ;
wire [3:0] CARRYOUT_6 ;
wire [6:0] output_Z ;
wire [47:24] P_uc_6 ;
wire [47:0] PCOUT_6 ;
wire CARRYCASCOUT_6 ;
wire MULTSIGNOUT_6 ;
wire OVERFLOW_6 ;
wire PATTERNBDETECT_6 ;
wire UNDERFLOW_6 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc644(.ACOUT(ACOUT_6[29:0]),.BCOUT(BCOUT_6[17:0]),.CARRYCASCOUT(CARRYCASCOUT_6),.CARRYOUT(CARRYOUT_6[3:0]),.MULTSIGNOUT(MULTSIGNOUT_6),.OVERFLOW(OVERFLOW_6),.P({P_uc_6[47:24],pre_out_r[23:7],output_Z[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_6),.PATTERNDETECT(PATTERNDETECT_6),.PCOUT(PCOUT_6[47:0]),.UNDERFLOW(UNDERFLOW_6),.A({vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,VCC,VCC}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(VCC),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,VCC,GND,VCC,GND,VCC}),.PCIN({P_uc_28_0[47:24],mult1_out_0[23:0]}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc644.ACASCREG=2;
defparam desc644.ADREG=0;
defparam desc644.ALUMODEREG=0;
defparam desc644.AREG=2;
defparam desc644.AUTORESET_PATDET="NO_RESET";
defparam desc644.A_INPUT="DIRECT";
defparam desc644.BCASCREG=1;
defparam desc644.BREG=1;
defparam desc644.B_INPUT="DIRECT";
defparam desc644.CARRYINREG=0;
defparam desc644.CARRYINSELREG=0;
defparam desc644.CREG=1;
defparam desc644.DREG=0;
defparam desc644.INMODEREG=0;
defparam desc644.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc644.MREG=0;
defparam desc644.OPMODEREG=0;
defparam desc644.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc644.PREG=0;
defparam desc644.SEL_MASK="MASK";
defparam desc644.USE_DPORT="FALSE";
defparam desc644.USE_MULT="MULTIPLY";
defparam desc644.USE_PATTERN_DETECT="PATDET";
defparam desc644.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module add_subZ3_inj (pre_out_10,output_iv_0,output_iv_1,output_iv_9,output_iv_8,output_iv_6,output_iv_7,output_iv_2,output_iv_3,output_iv_4,out_r_vec_mult_0,in_a_r_reg_0,N_500);
output pre_out_10 ;
output output_iv_0 ;
output output_iv_1 ;
output output_iv_9 ;
output output_iv_8 ;
output output_iv_6 ;
output output_iv_7 ;
output output_iv_2 ;
output output_iv_3 ;
output output_iv_4 ;
input [11:0] out_r_vec_mult_0 ;
input [11:0] in_a_r_reg_0 ;
output N_500 ;
wire pre_out_10 ;
wire output_iv_0 ;
wire output_iv_1 ;
wire output_iv_9 ;
wire output_iv_8 ;
wire output_iv_6 ;
wire output_iv_7 ;
wire output_iv_2 ;
wire output_iv_3 ;
wire output_iv_4 ;
wire N_500 ;
wire [10:1] pre_out ;
wire pre_out_i ;
wire VCC ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
wire GND ;
// instances
LUT2 pre_out_axb_0(.I0(out_r_vec_mult_0[0:0]),.I1(in_a_r_reg_0[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_r_vec_mult_0[1:1]),.I1(in_a_r_reg_0[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_r_vec_mult_0[2:2]),.I1(in_a_r_reg_0[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_r_vec_mult_0[3:3]),.I1(in_a_r_reg_0[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_r_vec_mult_0[4:4]),.I1(in_a_r_reg_0[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_r_vec_mult_0[5:5]),.I1(in_a_r_reg_0[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_r_vec_mult_0[6:6]),.I1(in_a_r_reg_0[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_r_vec_mult_0[7:7]),.I1(in_a_r_reg_0[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_r_vec_mult_0[8:8]),.I1(in_a_r_reg_0[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_r_vec_mult_0[9:9]),.I1(in_a_r_reg_0[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_r_vec_mult_0[10:10]),.I1(in_a_r_reg_0[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT2 pre_out_axb_11_cZ(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out_10));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out[10:10]));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_r_reg_0[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out[9:9]));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_r_reg_0[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out[8:8]));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_r_reg_0[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out[7:7]));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_r_reg_0[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out[6:6]));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_r_reg_0[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out[5:5]));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_r_reg_0[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out[4:4]));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_r_reg_0[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out[3:3]));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_r_reg_0[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out[2:2]));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_r_reg_0[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out[1:1]));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_r_reg_0[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_r_reg_0[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT4 desc711(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[5:5]),.I3(pre_out_10),.O(output_iv_4));
defparam desc711.INIT=16'h0D4F;
LUT4 desc712(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[6:6]),.I3(pre_out_10),.O(N_500));
defparam desc712.INIT=16'h0D4F;
LUT4 desc713(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[3:3]),.I3(pre_out_10),.O(output_iv_2));
defparam desc713.INIT=16'h0D4F;
LUT4 desc714(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[4:4]),.I3(pre_out_10),.O(output_iv_3));
defparam desc714.INIT=16'h0D4F;
LUT4 desc715(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[7:7]),.I3(pre_out_10),.O(output_iv_6));
defparam desc715.INIT=16'h0D4F;
LUT4 desc716(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[8:8]),.I3(pre_out_10),.O(output_iv_7));
defparam desc716.INIT=16'h0D4F;
LUT4 desc717(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[10:10]),.I3(pre_out_10),.O(output_iv_9));
defparam desc717.INIT=16'h0D4F;
LUT4 desc718(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[9:9]),.I3(pre_out_10),.O(output_iv_8));
defparam desc718.INIT=16'h0D4F;
LUT4 desc719(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[1:1]),.I3(pre_out_10),.O(output_iv_0));
defparam desc719.INIT=16'h0D4F;
LUT4 desc720(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0[11:11]),.I2(pre_out[2:2]),.I3(pre_out_10),.O(output_iv_1));
defparam desc720.INIT=16'h0D4F;
endmodule
module add_subZ3_1_inj (pre_out_i_m_8,pre_out_i_m_4,pre_out_i_m_0,out_r_vec_mult_1,in_a_r_reg_1,pre_out_10,pre_out_9,pre_out_8,pre_out_6,pre_out_5,pre_out_4,pre_out_2,pre_out_1,pre_out_0,un5_output);
output pre_out_i_m_8 ;
output pre_out_i_m_4 ;
output pre_out_i_m_0 ;
input [11:0] out_r_vec_mult_1 ;
input [11:0] in_a_r_reg_1 ;
output pre_out_10 ;
output pre_out_9 ;
output pre_out_8 ;
output pre_out_6 ;
output pre_out_5 ;
output pre_out_4 ;
output pre_out_2 ;
output pre_out_1 ;
output pre_out_0 ;
output un5_output ;
wire pre_out_i_m_8 ;
wire pre_out_i_m_4 ;
wire pre_out_i_m_0 ;
wire pre_out_10 ;
wire pre_out_9 ;
wire pre_out_8 ;
wire pre_out_6 ;
wire pre_out_5 ;
wire pre_out_4 ;
wire pre_out_2 ;
wire pre_out_1 ;
wire pre_out_0 ;
wire un5_output ;
wire [8:4] pre_out ;
wire pre_out_i ;
wire VCC ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
wire GND ;
// instances
LUT2 pre_out_axb_0(.I0(out_r_vec_mult_1[0:0]),.I1(in_a_r_reg_1[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_r_vec_mult_1[1:1]),.I1(in_a_r_reg_1[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_r_vec_mult_1[2:2]),.I1(in_a_r_reg_1[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_r_vec_mult_1[3:3]),.I1(in_a_r_reg_1[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_r_vec_mult_1[4:4]),.I1(in_a_r_reg_1[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_r_vec_mult_1[5:5]),.I1(in_a_r_reg_1[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_r_vec_mult_1[6:6]),.I1(in_a_r_reg_1[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_r_vec_mult_1[7:7]),.I1(in_a_r_reg_1[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_r_vec_mult_1[8:8]),.I1(in_a_r_reg_1[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_r_vec_mult_1[9:9]),.I1(in_a_r_reg_1[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_r_vec_mult_1[10:10]),.I1(in_a_r_reg_1[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT2 pre_out_axb_11_cZ(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out_10));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out_9));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_r_reg_1[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out_8));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_r_reg_1[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out[8:8]));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_r_reg_1[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out_6));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_r_reg_1[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out_5));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_r_reg_1[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out_4));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_r_reg_1[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out[4:4]));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_r_reg_1[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out_2));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_r_reg_1[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out_1));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_r_reg_1[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out_0));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_r_reg_1[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_r_reg_1[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT3 desc721(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(pre_out_10),.O(un5_output));
defparam desc721.INIT=8'hFB;
LUT5 desc722(.I0(out_r_vec_mult_1[0:0]),.I1(in_a_r_reg_1[0:0]),.I2(out_r_vec_mult_1[11:11]),.I3(in_a_r_reg_1[11:11]),.I4(pre_out_10),.O(pre_out_i_m_0));
defparam desc722.INIT=32'h99099099;
LUT4 pre_out_s_4_RNIDBUP_o6(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(pre_out[8:8]),.I3(pre_out_10),.O(pre_out_i_m_8));
defparam pre_out_s_4_RNIDBUP_o6.INIT=16'h0D0B;
LUT4 pre_out_s_4_RNIDBUP_o5(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(pre_out[4:4]),.I3(pre_out_10),.O(pre_out_i_m_4));
defparam pre_out_s_4_RNIDBUP_o5.INIT=16'h0D0B;
endmodule
module add_subZ3_2_inj (out_r_vec_mult_2,in_a_r_reg_2,pre_out_i_m_6,pre_out_i_m_0,pre_out_10,pre_out_9,pre_out_8,pre_out_7,pre_out_6,pre_out_4,pre_out_3,pre_out_2,pre_out_1,pre_out_0,un5_output);
input [11:0] out_r_vec_mult_2 ;
input [11:0] in_a_r_reg_2 ;
output pre_out_i_m_6 ;
output pre_out_i_m_0 ;
output pre_out_10 ;
output pre_out_9 ;
output pre_out_8 ;
output pre_out_7 ;
output pre_out_6 ;
output pre_out_4 ;
output pre_out_3 ;
output pre_out_2 ;
output pre_out_1 ;
output pre_out_0 ;
output un5_output ;
wire pre_out_i_m_6 ;
wire pre_out_i_m_0 ;
wire pre_out_10 ;
wire pre_out_9 ;
wire pre_out_8 ;
wire pre_out_7 ;
wire pre_out_6 ;
wire pre_out_4 ;
wire pre_out_3 ;
wire pre_out_2 ;
wire pre_out_1 ;
wire pre_out_0 ;
wire un5_output ;
wire [6:6] pre_out ;
wire pre_out_i ;
wire GND ;
wire VCC ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
// instances
LUT2 pre_out_axb_0(.I0(out_r_vec_mult_2[0:0]),.I1(in_a_r_reg_2[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_r_vec_mult_2[1:1]),.I1(in_a_r_reg_2[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_r_vec_mult_2[2:2]),.I1(in_a_r_reg_2[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_r_vec_mult_2[3:3]),.I1(in_a_r_reg_2[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_r_vec_mult_2[4:4]),.I1(in_a_r_reg_2[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_r_vec_mult_2[5:5]),.I1(in_a_r_reg_2[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_r_vec_mult_2[6:6]),.I1(in_a_r_reg_2[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_r_vec_mult_2[7:7]),.I1(in_a_r_reg_2[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_r_vec_mult_2[8:8]),.I1(in_a_r_reg_2[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_r_vec_mult_2[9:9]),.I1(in_a_r_reg_2[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_r_vec_mult_2[10:10]),.I1(in_a_r_reg_2[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT5 pre_out_s_11_RNI16U11(.I0(out_r_vec_mult_2[0:0]),.I1(in_a_r_reg_2[0:0]),.I2(out_r_vec_mult_2[11:11]),.I3(in_a_r_reg_2[11:11]),.I4(pre_out_10),.O(pre_out_i_m_0));
defparam pre_out_s_11_RNI16U11.INIT=32'h99099099;
LUT2 pre_out_axb_11_cZ(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out_10));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out_9));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_r_reg_2[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out_8));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_r_reg_2[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out_7));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_r_reg_2[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out_6));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_r_reg_2[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out[6:6]));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_r_reg_2[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out_4));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_r_reg_2[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out_3));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_r_reg_2[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out_2));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_r_reg_2[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out_1));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_r_reg_2[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out_0));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_r_reg_2[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_r_reg_2[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
LUT4 pre_out_s_6_RNIRQ081_o6(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(pre_out[6:6]),.I3(pre_out_10),.O(pre_out_i_m_6));
defparam pre_out_s_6_RNIRQ081_o6.INIT=16'h0D0B;
LUT3 pre_out_s_6_RNIRQ081_o5(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(pre_out_10),.O(un5_output));
defparam pre_out_s_6_RNIRQ081_o5.INIT=8'hFB;
endmodule
module add_subZ3_3_inj (out_r_vec_mult_3,in_a_r_reg_3,pre_out_i_m,pre_out_10,pre_out_9,pre_out_8,pre_out_7,pre_out_6,pre_out_5,pre_out_4,pre_out_3,pre_out_2,pre_out_1,un5_output);
input [11:0] out_r_vec_mult_3 ;
input [11:0] in_a_r_reg_3 ;
output [1:0] pre_out_i_m ;
output pre_out_10 ;
output pre_out_9 ;
output pre_out_8 ;
output pre_out_7 ;
output pre_out_6 ;
output pre_out_5 ;
output pre_out_4 ;
output pre_out_3 ;
output pre_out_2 ;
output pre_out_1 ;
output un5_output ;
wire pre_out_10 ;
wire pre_out_9 ;
wire pre_out_8 ;
wire pre_out_7 ;
wire pre_out_6 ;
wire pre_out_5 ;
wire pre_out_4 ;
wire pre_out_3 ;
wire pre_out_2 ;
wire pre_out_1 ;
wire un5_output ;
wire [1:1] pre_out ;
wire pre_out_i ;
wire GND ;
wire VCC ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
// instances
LUT2 pre_out_axb_0(.I0(out_r_vec_mult_3[0:0]),.I1(in_a_r_reg_3[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_r_vec_mult_3[1:1]),.I1(in_a_r_reg_3[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_r_vec_mult_3[2:2]),.I1(in_a_r_reg_3[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_r_vec_mult_3[3:3]),.I1(in_a_r_reg_3[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_r_vec_mult_3[4:4]),.I1(in_a_r_reg_3[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_r_vec_mult_3[5:5]),.I1(in_a_r_reg_3[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_r_vec_mult_3[6:6]),.I1(in_a_r_reg_3[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_r_vec_mult_3[7:7]),.I1(in_a_r_reg_3[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_r_vec_mult_3[8:8]),.I1(in_a_r_reg_3[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_r_vec_mult_3[9:9]),.I1(in_a_r_reg_3[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_r_vec_mult_3[10:10]),.I1(in_a_r_reg_3[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT5 pre_out_s_11_RNI6TNU(.I0(out_r_vec_mult_3[0:0]),.I1(in_a_r_reg_3[0:0]),.I2(out_r_vec_mult_3[11:11]),.I3(in_a_r_reg_3[11:11]),.I4(pre_out_10),.O(pre_out_i_m[0:0]));
defparam pre_out_s_11_RNI6TNU.INIT=32'h99099099;
LUT2 pre_out_axb_11_cZ(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out_10));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out_9));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_r_reg_3[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out_8));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_r_reg_3[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out_7));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_r_reg_3[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out_6));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_r_reg_3[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out_5));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_r_reg_3[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out_4));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_r_reg_3[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out_3));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_r_reg_3[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out_2));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_r_reg_3[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out_1));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_r_reg_3[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out[1:1]));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_r_reg_3[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_r_reg_3[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
LUT4 pre_out_s_1_RNIQIL91_o6(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(pre_out[1:1]),.I3(pre_out_10),.O(pre_out_i_m[1:1]));
defparam pre_out_s_1_RNIQIL91_o6.INIT=16'h0D0B;
LUT3 pre_out_s_1_RNIQIL91_o5(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(pre_out_10),.O(un5_output));
defparam pre_out_s_1_RNIQIL91_o5.INIT=8'hFB;
endmodule
module add_subZ3_4_inj (pre_out_10,output_iv,out_i_vec_sub_0,out_i_vec_mult_0,in_a_i_reg_0);
output pre_out_10 ;
output [10:0] output_iv ;
output [11:11] out_i_vec_sub_0 ;
input [11:0] out_i_vec_mult_0 ;
input [11:0] in_a_i_reg_0 ;
wire pre_out_10 ;
wire [10:1] pre_out ;
wire pre_out_i ;
wire VCC ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
wire GND ;
// instances
LUT2 pre_out_axb_0(.I0(out_i_vec_mult_0[0:0]),.I1(in_a_i_reg_0[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_i_vec_mult_0[1:1]),.I1(in_a_i_reg_0[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_i_vec_mult_0[2:2]),.I1(in_a_i_reg_0[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_i_vec_mult_0[3:3]),.I1(in_a_i_reg_0[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_i_vec_mult_0[4:4]),.I1(in_a_i_reg_0[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_i_vec_mult_0[5:5]),.I1(in_a_i_reg_0[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_i_vec_mult_0[6:6]),.I1(in_a_i_reg_0[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_i_vec_mult_0[7:7]),.I1(in_a_i_reg_0[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_i_vec_mult_0[8:8]),.I1(in_a_i_reg_0[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_i_vec_mult_0[9:9]),.I1(in_a_i_reg_0[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_i_vec_mult_0[10:10]),.I1(in_a_i_reg_0[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT2 pre_out_axb_11_cZ(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out_10));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out[10:10]));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_i_reg_0[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out[9:9]));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_i_reg_0[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out[8:8]));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_i_reg_0[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out[7:7]));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_i_reg_0[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out[6:6]));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_i_reg_0[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out[5:5]));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_i_reg_0[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out[4:4]));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_i_reg_0[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out[3:3]));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_i_reg_0[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out[2:2]));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_i_reg_0[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out[1:1]));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_i_reg_0[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_i_reg_0[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT5 desc723(.I0(out_i_vec_mult_0[0:0]),.I1(in_a_i_reg_0[0:0]),.I2(out_i_vec_mult_0[11:11]),.I3(in_a_i_reg_0[11:11]),.I4(pre_out_10),.O(output_iv[0:0]));
defparam desc723.INIT=32'h99099F99;
LUT3 desc724(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out_10),.O(out_i_vec_sub_0[11:11]));
defparam desc724.INIT=8'hD4;
LUT4 desc725(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[2:2]),.I3(pre_out_10),.O(output_iv[2:2]));
defparam desc725.INIT=16'h0D4F;
LUT4 desc726(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[3:3]),.I3(pre_out_10),.O(output_iv[3:3]));
defparam desc726.INIT=16'h0D4F;
LUT4 desc727(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[4:4]),.I3(pre_out_10),.O(output_iv[4:4]));
defparam desc727.INIT=16'h0D4F;
LUT4 desc728(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[1:1]),.I3(pre_out_10),.O(output_iv[1:1]));
defparam desc728.INIT=16'h0D4F;
LUT4 desc729(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[10:10]),.I3(pre_out_10),.O(output_iv[10:10]));
defparam desc729.INIT=16'h0D4F;
LUT4 desc730(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[9:9]),.I3(pre_out_10),.O(output_iv[9:9]));
defparam desc730.INIT=16'h0D4F;
LUT4 desc731(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[5:5]),.I3(pre_out_10),.O(output_iv[5:5]));
defparam desc731.INIT=16'h0D4F;
LUT4 desc732(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[6:6]),.I3(pre_out_10),.O(output_iv[6:6]));
defparam desc732.INIT=16'h0D4F;
LUT4 desc733(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[8:8]),.I3(pre_out_10),.O(output_iv[8:8]));
defparam desc733.INIT=16'h0D4F;
LUT4 desc734(.I0(out_i_vec_mult_0[11:11]),.I1(in_a_i_reg_0[11:11]),.I2(pre_out[7:7]),.I3(pre_out_10),.O(output_iv[7:7]));
defparam desc734.INIT=16'h0D4F;
endmodule
module add_subZ3_5_inj (pre_out_i_m,out_i_vec_mult_1,in_a_i_reg_1,pre_out,un5_output);
output pre_out_i_m ;
input [11:0] out_i_vec_mult_1 ;
input [11:0] in_a_i_reg_1 ;
output [11:1] pre_out ;
output un5_output ;
wire un5_output ;
wire pre_out_i ;
wire VCC ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
wire GND ;
// instances
LUT2 pre_out_axb_0(.I0(out_i_vec_mult_1[0:0]),.I1(in_a_i_reg_1[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_i_vec_mult_1[1:1]),.I1(in_a_i_reg_1[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_i_vec_mult_1[2:2]),.I1(in_a_i_reg_1[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_i_vec_mult_1[3:3]),.I1(in_a_i_reg_1[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_i_vec_mult_1[4:4]),.I1(in_a_i_reg_1[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_i_vec_mult_1[5:5]),.I1(in_a_i_reg_1[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_i_vec_mult_1[6:6]),.I1(in_a_i_reg_1[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_i_vec_mult_1[7:7]),.I1(in_a_i_reg_1[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_i_vec_mult_1[8:8]),.I1(in_a_i_reg_1[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_i_vec_mult_1[9:9]),.I1(in_a_i_reg_1[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_i_vec_mult_1[10:10]),.I1(in_a_i_reg_1[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT2 pre_out_axb_11_cZ(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out[11:11]));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out[10:10]));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_i_reg_1[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out[9:9]));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_i_reg_1[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out[8:8]));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_i_reg_1[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out[7:7]));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_i_reg_1[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out[6:6]));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_i_reg_1[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out[5:5]));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_i_reg_1[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out[4:4]));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_i_reg_1[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out[3:3]));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_i_reg_1[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out[2:2]));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_i_reg_1[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out[1:1]));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_i_reg_1[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_i_reg_1[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT3 desc735(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(pre_out[11:11]),.O(un5_output));
defparam desc735.INIT=8'hFB;
LUT5 desc736(.I0(out_i_vec_mult_1[0:0]),.I1(in_a_i_reg_1[0:0]),.I2(out_i_vec_mult_1[11:11]),.I3(in_a_i_reg_1[11:11]),.I4(pre_out[11:11]),.O(pre_out_i_m));
defparam desc736.INIT=32'h99099099;
endmodule
module add_subZ3_6_inj (pre_out_i_m,out_i_vec_mult_2,in_a_i_reg_2,pre_out,un5_output);
output pre_out_i_m ;
input [11:0] out_i_vec_mult_2 ;
input [11:0] in_a_i_reg_2 ;
output [11:1] pre_out ;
output un5_output ;
wire un5_output ;
wire pre_out_i ;
wire VCC ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
wire GND ;
// instances
LUT2 pre_out_axb_0(.I0(out_i_vec_mult_2[0:0]),.I1(in_a_i_reg_2[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_i_vec_mult_2[1:1]),.I1(in_a_i_reg_2[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_i_vec_mult_2[2:2]),.I1(in_a_i_reg_2[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_i_vec_mult_2[3:3]),.I1(in_a_i_reg_2[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_i_vec_mult_2[4:4]),.I1(in_a_i_reg_2[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_i_vec_mult_2[5:5]),.I1(in_a_i_reg_2[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_i_vec_mult_2[6:6]),.I1(in_a_i_reg_2[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_i_vec_mult_2[7:7]),.I1(in_a_i_reg_2[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_i_vec_mult_2[8:8]),.I1(in_a_i_reg_2[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_i_vec_mult_2[9:9]),.I1(in_a_i_reg_2[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_i_vec_mult_2[10:10]),.I1(in_a_i_reg_2[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT2 pre_out_axb_11_cZ(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out[11:11]));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out[10:10]));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_i_reg_2[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out[9:9]));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_i_reg_2[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out[8:8]));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_i_reg_2[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out[7:7]));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_i_reg_2[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out[6:6]));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_i_reg_2[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out[5:5]));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_i_reg_2[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out[4:4]));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_i_reg_2[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out[3:3]));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_i_reg_2[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out[2:2]));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_i_reg_2[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out[1:1]));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_i_reg_2[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_i_reg_2[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT3 desc737(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(pre_out[11:11]),.O(un5_output));
defparam desc737.INIT=8'hFB;
LUT5 desc738(.I0(out_i_vec_mult_2[0:0]),.I1(in_a_i_reg_2[0:0]),.I2(out_i_vec_mult_2[11:11]),.I3(in_a_i_reg_2[11:11]),.I4(pre_out[11:11]),.O(pre_out_i_m));
defparam desc738.INIT=32'h99099099;
endmodule
module add_subZ3_7_inj (out_i_vec_mult_3,in_a_i_reg_3,pre_out_i_m_1,pre_out_i_m_5,pre_out_i_m_2,pre_out_i_m_10,pre_out_i_m_9,pre_out_i_m_6,pre_out_i_m_7,pre_out_i_m_3,pre_out_i_m_4,pre_out_i_m_0,pre_out_10,pre_out_7,un5_output);
input [11:0] out_i_vec_mult_3 ;
input [11:0] in_a_i_reg_3 ;
output pre_out_i_m_1 ;
output pre_out_i_m_5 ;
output pre_out_i_m_2 ;
output pre_out_i_m_10 ;
output pre_out_i_m_9 ;
output pre_out_i_m_6 ;
output pre_out_i_m_7 ;
output pre_out_i_m_3 ;
output pre_out_i_m_4 ;
output pre_out_i_m_0 ;
output pre_out_10 ;
output pre_out_7 ;
output un5_output ;
wire pre_out_i_m_1 ;
wire pre_out_i_m_5 ;
wire pre_out_i_m_2 ;
wire pre_out_i_m_10 ;
wire pre_out_i_m_9 ;
wire pre_out_i_m_6 ;
wire pre_out_i_m_7 ;
wire pre_out_i_m_3 ;
wire pre_out_i_m_4 ;
wire pre_out_i_m_0 ;
wire pre_out_10 ;
wire pre_out_7 ;
wire un5_output ;
wire [10:1] pre_out ;
wire pre_out_i ;
wire VCC ;
wire GND ;
wire pre_out_axb_1 ;
wire pre_out_axb_2 ;
wire pre_out_axb_3 ;
wire pre_out_axb_4 ;
wire pre_out_axb_5 ;
wire pre_out_axb_6 ;
wire pre_out_axb_7 ;
wire pre_out_axb_8 ;
wire pre_out_axb_9 ;
wire pre_out_axb_10 ;
wire pre_out_axb_11 ;
wire pre_out_cry_10 ;
wire pre_out_cry_9 ;
wire pre_out_cry_8 ;
wire pre_out_cry_7 ;
wire pre_out_cry_6 ;
wire pre_out_cry_5 ;
wire pre_out_cry_4 ;
wire pre_out_cry_3 ;
wire pre_out_cry_2 ;
wire pre_out_cry_1 ;
wire pre_out_cry_0 ;
// instances
LUT2 pre_out_axb_0(.I0(out_i_vec_mult_3[0:0]),.I1(in_a_i_reg_3[0:0]),.O(pre_out_i));
defparam pre_out_axb_0.INIT=4'h9;
LUT2 pre_out_axb_1_cZ(.I0(out_i_vec_mult_3[1:1]),.I1(in_a_i_reg_3[1:1]),.O(pre_out_axb_1));
defparam pre_out_axb_1_cZ.INIT=4'h9;
LUT2 pre_out_axb_2_cZ(.I0(out_i_vec_mult_3[2:2]),.I1(in_a_i_reg_3[2:2]),.O(pre_out_axb_2));
defparam pre_out_axb_2_cZ.INIT=4'h9;
LUT2 pre_out_axb_3_cZ(.I0(out_i_vec_mult_3[3:3]),.I1(in_a_i_reg_3[3:3]),.O(pre_out_axb_3));
defparam pre_out_axb_3_cZ.INIT=4'h9;
LUT2 pre_out_axb_4_cZ(.I0(out_i_vec_mult_3[4:4]),.I1(in_a_i_reg_3[4:4]),.O(pre_out_axb_4));
defparam pre_out_axb_4_cZ.INIT=4'h9;
LUT2 pre_out_axb_5_cZ(.I0(out_i_vec_mult_3[5:5]),.I1(in_a_i_reg_3[5:5]),.O(pre_out_axb_5));
defparam pre_out_axb_5_cZ.INIT=4'h9;
LUT2 pre_out_axb_6_cZ(.I0(out_i_vec_mult_3[6:6]),.I1(in_a_i_reg_3[6:6]),.O(pre_out_axb_6));
defparam pre_out_axb_6_cZ.INIT=4'h9;
LUT2 pre_out_axb_7_cZ(.I0(out_i_vec_mult_3[7:7]),.I1(in_a_i_reg_3[7:7]),.O(pre_out_axb_7));
defparam pre_out_axb_7_cZ.INIT=4'h9;
LUT2 pre_out_axb_8_cZ(.I0(out_i_vec_mult_3[8:8]),.I1(in_a_i_reg_3[8:8]),.O(pre_out_axb_8));
defparam pre_out_axb_8_cZ.INIT=4'h9;
LUT2 pre_out_axb_9_cZ(.I0(out_i_vec_mult_3[9:9]),.I1(in_a_i_reg_3[9:9]),.O(pre_out_axb_9));
defparam pre_out_axb_9_cZ.INIT=4'h9;
LUT2 pre_out_axb_10_cZ(.I0(out_i_vec_mult_3[10:10]),.I1(in_a_i_reg_3[10:10]),.O(pre_out_axb_10));
defparam pre_out_axb_10_cZ.INIT=4'h9;
LUT5 pre_out_s_11_RNIPS481(.I0(out_i_vec_mult_3[0:0]),.I1(in_a_i_reg_3[0:0]),.I2(out_i_vec_mult_3[11:11]),.I3(in_a_i_reg_3[11:11]),.I4(pre_out_10),.O(pre_out_i_m_0));
defparam pre_out_s_11_RNIPS481.INIT=32'h99099099;
LUT2 pre_out_axb_11_cZ(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.O(pre_out_axb_11));
defparam pre_out_axb_11_cZ.INIT=4'h9;
XORCY pre_out_s_11(.LI(pre_out_axb_11),.CI(pre_out_cry_10),.O(pre_out_10));
XORCY pre_out_s_10(.LI(pre_out_axb_10),.CI(pre_out_cry_9),.O(pre_out[10:10]));
MUXCY_L pre_out_cry_10_cZ(.DI(in_a_i_reg_3[10:10]),.CI(pre_out_cry_9),.S(pre_out_axb_10),.LO(pre_out_cry_10));
XORCY pre_out_s_9(.LI(pre_out_axb_9),.CI(pre_out_cry_8),.O(pre_out[9:9]));
MUXCY_L pre_out_cry_9_cZ(.DI(in_a_i_reg_3[9:9]),.CI(pre_out_cry_8),.S(pre_out_axb_9),.LO(pre_out_cry_9));
XORCY pre_out_s_8(.LI(pre_out_axb_8),.CI(pre_out_cry_7),.O(pre_out_7));
MUXCY_L pre_out_cry_8_cZ(.DI(in_a_i_reg_3[8:8]),.CI(pre_out_cry_7),.S(pre_out_axb_8),.LO(pre_out_cry_8));
XORCY pre_out_s_7(.LI(pre_out_axb_7),.CI(pre_out_cry_6),.O(pre_out[7:7]));
MUXCY_L pre_out_cry_7_cZ(.DI(in_a_i_reg_3[7:7]),.CI(pre_out_cry_6),.S(pre_out_axb_7),.LO(pre_out_cry_7));
XORCY pre_out_s_6(.LI(pre_out_axb_6),.CI(pre_out_cry_5),.O(pre_out[6:6]));
MUXCY_L pre_out_cry_6_cZ(.DI(in_a_i_reg_3[6:6]),.CI(pre_out_cry_5),.S(pre_out_axb_6),.LO(pre_out_cry_6));
XORCY pre_out_s_5(.LI(pre_out_axb_5),.CI(pre_out_cry_4),.O(pre_out[5:5]));
MUXCY_L pre_out_cry_5_cZ(.DI(in_a_i_reg_3[5:5]),.CI(pre_out_cry_4),.S(pre_out_axb_5),.LO(pre_out_cry_5));
XORCY pre_out_s_4(.LI(pre_out_axb_4),.CI(pre_out_cry_3),.O(pre_out[4:4]));
MUXCY_L pre_out_cry_4_cZ(.DI(in_a_i_reg_3[4:4]),.CI(pre_out_cry_3),.S(pre_out_axb_4),.LO(pre_out_cry_4));
XORCY pre_out_s_3(.LI(pre_out_axb_3),.CI(pre_out_cry_2),.O(pre_out[3:3]));
MUXCY_L pre_out_cry_3_cZ(.DI(in_a_i_reg_3[3:3]),.CI(pre_out_cry_2),.S(pre_out_axb_3),.LO(pre_out_cry_3));
XORCY pre_out_s_2(.LI(pre_out_axb_2),.CI(pre_out_cry_1),.O(pre_out[2:2]));
MUXCY_L pre_out_cry_2_cZ(.DI(in_a_i_reg_3[2:2]),.CI(pre_out_cry_1),.S(pre_out_axb_2),.LO(pre_out_cry_2));
XORCY pre_out_s_1(.LI(pre_out_axb_1),.CI(pre_out_cry_0),.O(pre_out[1:1]));
MUXCY_L pre_out_cry_1_cZ(.DI(in_a_i_reg_3[1:1]),.CI(pre_out_cry_0),.S(pre_out_axb_1),.LO(pre_out_cry_1));
MUXCY_L pre_out_cry_0_cZ(.DI(in_a_i_reg_3[0:0]),.CI(VCC),.S(pre_out_i),.LO(pre_out_cry_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT4 pre_out_s_3_RNI5JVQ1_o6(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[3:3]),.I3(pre_out_10),.O(pre_out_i_m_3));
defparam pre_out_s_3_RNI5JVQ1_o6.INIT=16'h0D0B;
LUT4 pre_out_s_3_RNI5JVQ1_o5(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[4:4]),.I3(pre_out_10),.O(pre_out_i_m_4));
defparam pre_out_s_3_RNI5JVQ1_o5.INIT=16'h0D0B;
LUT4 pre_out_s_6_RNIBJVQ1_o6(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[6:6]),.I3(pre_out_10),.O(pre_out_i_m_6));
defparam pre_out_s_6_RNIBJVQ1_o6.INIT=16'h0D0B;
LUT4 pre_out_s_6_RNIBJVQ1_o5(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[7:7]),.I3(pre_out_10),.O(pre_out_i_m_7));
defparam pre_out_s_6_RNIBJVQ1_o5.INIT=16'h0D0B;
LUT4 pre_out_s_9_RNIOUVQ1_o6(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[10:10]),.I3(pre_out_10),.O(pre_out_i_m_10));
defparam pre_out_s_9_RNIOUVQ1_o6.INIT=16'h0D0B;
LUT4 pre_out_s_9_RNIOUVQ1_o5(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[9:9]),.I3(pre_out_10),.O(pre_out_i_m_9));
defparam pre_out_s_9_RNIOUVQ1_o5.INIT=16'h0D0B;
LUT4 pre_out_s_2_RNINIFC1_o6(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[2:2]),.I3(pre_out_10),.O(pre_out_i_m_2));
defparam pre_out_s_2_RNINIFC1_o6.INIT=16'h0D0B;
LUT3 pre_out_s_2_RNINIFC1_o5(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out_10),.O(un5_output));
defparam pre_out_s_2_RNINIFC1_o5.INIT=8'hFB;
LUT4 pre_out_s_1_RNI4JVQ1_o6(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[1:1]),.I3(pre_out_10),.O(pre_out_i_m_1));
defparam pre_out_s_1_RNI4JVQ1_o6.INIT=16'h0D0B;
LUT4 pre_out_s_1_RNI4JVQ1_o5(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(pre_out[5:5]),.I3(pre_out_10),.O(pre_out_i_m_5));
defparam pre_out_s_1_RNI4JVQ1_o5.INIT=16'h0D0B;
endmodule
module complex_mult_pipe_prod_inj (mult_out_r,mult_out_i,in_a_r_reg,in_b_r_reg,in_a_i_reg,in_b_i_reg,clk);
output [11:0] mult_out_r ;
output [11:0] mult_out_i ;
input [11:0] in_a_r_reg ;
input [11:0] in_b_r_reg ;
input [11:0] in_a_i_reg ;
input [11:0] in_b_i_reg ;
input clk ;
wire clk ;
wire [23:7] pre_out_i ;
wire [23:7] pre_out_r ;
wire [23:23] mult2_out ;
wire [23:23] mult1_out ;
wire [23:23] mult3_out ;
wire [23:23] mult4_out ;
wire [11:11] pos_out_r ;
wire [11:11] pos_out_i ;
wire [10:0] un7_rnd_out_r ;
wire [10:0] pos_out_r_iv_i ;
wire [10:0] un5_rnd_out_i ;
wire [10:0] pos_out_i_iv_i ;
wire [23:0] mult2_out_0 ;
wire [47:24] P_uc_34_0 ;
wire [23:0] mult3_out_0 ;
wire [47:24] P_uc_35_0 ;
wire un5_rnd_out_i_axb_1 ;
wire un5_rnd_out_i_axb_2 ;
wire un5_rnd_out_i_axb_3 ;
wire un5_rnd_out_i_axb_4 ;
wire un5_rnd_out_i_axb_5 ;
wire un5_rnd_out_i_axb_6 ;
wire un5_rnd_out_i_axb_7 ;
wire un5_rnd_out_i_axb_8 ;
wire un5_rnd_out_i_axb_9 ;
wire un5_rnd_out_i_axb_10 ;
wire un5_rnd_out_i_axb_11 ;
wire un7_rnd_out_r_axb_1 ;
wire un7_rnd_out_r_axb_2 ;
wire un7_rnd_out_r_axb_3 ;
wire un7_rnd_out_r_axb_4 ;
wire un7_rnd_out_r_axb_5 ;
wire un7_rnd_out_r_axb_6 ;
wire un7_rnd_out_r_axb_7 ;
wire un7_rnd_out_r_axb_8 ;
wire un7_rnd_out_r_axb_9 ;
wire un7_rnd_out_r_axb_10 ;
wire un7_rnd_out_r_axb_11 ;
wire un7_rnd_out_r_axb_12 ;
wire un5_rnd_out_i_axb_12 ;
wire un4_rnd_sat_out_i_3 ;
wire un5_rnd_sat_out_r_3 ;
wire un1_pos_out_r_3 ;
wire un1_pos_out_i_3 ;
wire PATTERNDETECT_7 ;
wire un7_rnd_out_r_s_12 ;
wire PATTERNDETECT_8 ;
wire un5_rnd_out_i_s_12 ;
wire un7_rnd_out_r_cry_11 ;
wire un7_rnd_out_r_cry_10 ;
wire GND ;
wire un7_rnd_out_r_cry_9 ;
wire un7_rnd_out_r_cry_8 ;
wire un7_rnd_out_r_cry_7 ;
wire un7_rnd_out_r_cry_6 ;
wire un7_rnd_out_r_cry_5 ;
wire un7_rnd_out_r_cry_4 ;
wire un7_rnd_out_r_cry_3 ;
wire un7_rnd_out_r_cry_2 ;
wire un7_rnd_out_r_cry_1 ;
wire un5_rnd_out_i_cry_11 ;
wire un5_rnd_out_i_cry_10 ;
wire un5_rnd_out_i_cry_9 ;
wire un5_rnd_out_i_cry_8 ;
wire un5_rnd_out_i_cry_7 ;
wire un5_rnd_out_i_cry_6 ;
wire un5_rnd_out_i_cry_5 ;
wire un5_rnd_out_i_cry_4 ;
wire un5_rnd_out_i_cry_3 ;
wire un5_rnd_out_i_cry_2 ;
wire un5_rnd_out_i_cry_1 ;
wire VCC ;
// instances
LUT1 un5_rnd_out_i_axb_1_cZ(.I0(pre_out_i[8:8]),.O(un5_rnd_out_i_axb_1));
defparam un5_rnd_out_i_axb_1_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_2_cZ(.I0(pre_out_i[9:9]),.O(un5_rnd_out_i_axb_2));
defparam un5_rnd_out_i_axb_2_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_3_cZ(.I0(pre_out_i[10:10]),.O(un5_rnd_out_i_axb_3));
defparam un5_rnd_out_i_axb_3_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_4_cZ(.I0(pre_out_i[11:11]),.O(un5_rnd_out_i_axb_4));
defparam un5_rnd_out_i_axb_4_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_5_cZ(.I0(pre_out_i[12:12]),.O(un5_rnd_out_i_axb_5));
defparam un5_rnd_out_i_axb_5_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_6_cZ(.I0(pre_out_i[13:13]),.O(un5_rnd_out_i_axb_6));
defparam un5_rnd_out_i_axb_6_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_7_cZ(.I0(pre_out_i[14:14]),.O(un5_rnd_out_i_axb_7));
defparam un5_rnd_out_i_axb_7_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_8_cZ(.I0(pre_out_i[15:15]),.O(un5_rnd_out_i_axb_8));
defparam un5_rnd_out_i_axb_8_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_9_cZ(.I0(pre_out_i[16:16]),.O(un5_rnd_out_i_axb_9));
defparam un5_rnd_out_i_axb_9_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_10_cZ(.I0(pre_out_i[17:17]),.O(un5_rnd_out_i_axb_10));
defparam un5_rnd_out_i_axb_10_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_11_cZ(.I0(pre_out_i[18:18]),.O(un5_rnd_out_i_axb_11));
defparam un5_rnd_out_i_axb_11_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_1_cZ(.I0(pre_out_r[8:8]),.O(un7_rnd_out_r_axb_1));
defparam un7_rnd_out_r_axb_1_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_2_cZ(.I0(pre_out_r[9:9]),.O(un7_rnd_out_r_axb_2));
defparam un7_rnd_out_r_axb_2_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_3_cZ(.I0(pre_out_r[10:10]),.O(un7_rnd_out_r_axb_3));
defparam un7_rnd_out_r_axb_3_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_4_cZ(.I0(pre_out_r[11:11]),.O(un7_rnd_out_r_axb_4));
defparam un7_rnd_out_r_axb_4_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_5_cZ(.I0(pre_out_r[12:12]),.O(un7_rnd_out_r_axb_5));
defparam un7_rnd_out_r_axb_5_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_6_cZ(.I0(pre_out_r[13:13]),.O(un7_rnd_out_r_axb_6));
defparam un7_rnd_out_r_axb_6_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_7_cZ(.I0(pre_out_r[14:14]),.O(un7_rnd_out_r_axb_7));
defparam un7_rnd_out_r_axb_7_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_8_cZ(.I0(pre_out_r[15:15]),.O(un7_rnd_out_r_axb_8));
defparam un7_rnd_out_r_axb_8_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_9_cZ(.I0(pre_out_r[16:16]),.O(un7_rnd_out_r_axb_9));
defparam un7_rnd_out_r_axb_9_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_10_cZ(.I0(pre_out_r[17:17]),.O(un7_rnd_out_r_axb_10));
defparam un7_rnd_out_r_axb_10_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_11_cZ(.I0(pre_out_r[18:18]),.O(un7_rnd_out_r_axb_11));
defparam un7_rnd_out_r_axb_11_cZ.INIT=2'h2;
LUT1 un7_rnd_out_r_axb_12_cZ(.I0(pre_out_r[19:19]),.O(un7_rnd_out_r_axb_12));
defparam un7_rnd_out_r_axb_12_cZ.INIT=2'h2;
LUT1 un5_rnd_out_i_axb_12_cZ(.I0(pre_out_i[19:19]),.O(un5_rnd_out_i_axb_12));
defparam un5_rnd_out_i_axb_12_cZ.INIT=2'h2;
LUT4 un4_rnd_sat_out_i_3_cZ(.I0(pre_out_i[20:20]),.I1(pre_out_i[21:21]),.I2(pre_out_i[22:22]),.I3(pre_out_i[19:19]),.O(un4_rnd_sat_out_i_3));
defparam un4_rnd_sat_out_i_3_cZ.INIT=16'h8000;
LUT4 un5_rnd_sat_out_r_3_cZ(.I0(pre_out_r[20:20]),.I1(pre_out_r[21:21]),.I2(pre_out_r[22:22]),.I3(pre_out_r[19:19]),.O(un5_rnd_sat_out_r_3));
defparam un5_rnd_sat_out_r_3_cZ.INIT=16'h8000;
LUT3 un1_pos_out_r(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.O(un1_pos_out_r_3));
defparam un1_pos_out_r.INIT=8'h08;
LUT3 un1_pos_out_i(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.O(un1_pos_out_i_3));
defparam un1_pos_out_i.INIT=8'h02;
LUT6_L desc270(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r_s_12),.LO(pos_out_r[11:11]));
defparam desc270.INIT=64'hE7E0E7E00000E0E0;
LUT6_L desc271(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i_s_12),.LO(pos_out_i[11:11]));
defparam desc271.INIT=64'hBDB0BDB00000B0B0;
LUT6_L desc272(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(un7_rnd_out_r[0:0]),.I4(PATTERNDETECT_7),.I5(un5_rnd_sat_out_r_3),.LO(pos_out_r_iv_i[0:0]));
defparam desc272.INIT=64'hFF18FF1F1F181F1F;
LUT6_L desc273(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[1:1]),.LO(pos_out_r_iv_i[1:1]));
defparam desc273.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc274(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[2:2]),.LO(pos_out_r_iv_i[2:2]));
defparam desc274.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc275(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[3:3]),.LO(pos_out_r_iv_i[3:3]));
defparam desc275.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc276(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[4:4]),.LO(pos_out_r_iv_i[4:4]));
defparam desc276.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc277(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[5:5]),.LO(pos_out_r_iv_i[5:5]));
defparam desc277.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc278(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[6:6]),.LO(pos_out_r_iv_i[6:6]));
defparam desc278.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc279(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[7:7]),.LO(pos_out_r_iv_i[7:7]));
defparam desc279.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc280(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[8:8]),.LO(pos_out_r_iv_i[8:8]));
defparam desc280.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc281(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[9:9]),.LO(pos_out_r_iv_i[9:9]));
defparam desc281.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc282(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_7),.I4(un5_rnd_sat_out_r_3),.I5(un7_rnd_out_r[10:10]),.LO(pos_out_r_iv_i[10:10]));
defparam desc282.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc283(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(un5_rnd_out_i[0:0]),.I4(PATTERNDETECT_8),.I5(un4_rnd_sat_out_i_3),.LO(pos_out_i_iv_i[0:0]));
defparam desc283.INIT=64'hFF42FF4F4F424F4F;
LUT6_L desc284(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[1:1]),.LO(pos_out_i_iv_i[1:1]));
defparam desc284.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc285(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[2:2]),.LO(pos_out_i_iv_i[2:2]));
defparam desc285.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc286(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[3:3]),.LO(pos_out_i_iv_i[3:3]));
defparam desc286.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc287(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[4:4]),.LO(pos_out_i_iv_i[4:4]));
defparam desc287.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc288(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[5:5]),.LO(pos_out_i_iv_i[5:5]));
defparam desc288.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc289(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[6:6]),.LO(pos_out_i_iv_i[6:6]));
defparam desc289.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc290(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[7:7]),.LO(pos_out_i_iv_i[7:7]));
defparam desc290.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc291(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[8:8]),.LO(pos_out_i_iv_i[8:8]));
defparam desc291.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc292(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[9:9]),.LO(pos_out_i_iv_i[9:9]));
defparam desc292.INIT=64'hFFFF4F4F424F424F;
LUT6_L desc293(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_8),.I4(un4_rnd_sat_out_i_3),.I5(un5_rnd_out_i[10:10]),.LO(pos_out_i_iv_i[10:10]));
defparam desc293.INIT=64'hFFFF4F4F424F424F;
XORCY un7_rnd_out_r_s_12_cZ(.LI(un7_rnd_out_r_axb_12),.CI(un7_rnd_out_r_cry_11),.O(un7_rnd_out_r_s_12));
XORCY un7_rnd_out_r_s_11(.LI(un7_rnd_out_r_axb_11),.CI(un7_rnd_out_r_cry_10),.O(un7_rnd_out_r[10:10]));
MUXCY_L un7_rnd_out_r_cry_11_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_10),.S(un7_rnd_out_r_axb_11),.LO(un7_rnd_out_r_cry_11));
XORCY un7_rnd_out_r_s_10(.LI(un7_rnd_out_r_axb_10),.CI(un7_rnd_out_r_cry_9),.O(un7_rnd_out_r[9:9]));
MUXCY_L un7_rnd_out_r_cry_10_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_9),.S(un7_rnd_out_r_axb_10),.LO(un7_rnd_out_r_cry_10));
XORCY un7_rnd_out_r_s_9(.LI(un7_rnd_out_r_axb_9),.CI(un7_rnd_out_r_cry_8),.O(un7_rnd_out_r[8:8]));
MUXCY_L un7_rnd_out_r_cry_9_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_8),.S(un7_rnd_out_r_axb_9),.LO(un7_rnd_out_r_cry_9));
XORCY un7_rnd_out_r_s_8(.LI(un7_rnd_out_r_axb_8),.CI(un7_rnd_out_r_cry_7),.O(un7_rnd_out_r[7:7]));
MUXCY_L un7_rnd_out_r_cry_8_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_7),.S(un7_rnd_out_r_axb_8),.LO(un7_rnd_out_r_cry_8));
XORCY un7_rnd_out_r_s_7(.LI(un7_rnd_out_r_axb_7),.CI(un7_rnd_out_r_cry_6),.O(un7_rnd_out_r[6:6]));
MUXCY_L un7_rnd_out_r_cry_7_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_6),.S(un7_rnd_out_r_axb_7),.LO(un7_rnd_out_r_cry_7));
XORCY un7_rnd_out_r_s_6(.LI(un7_rnd_out_r_axb_6),.CI(un7_rnd_out_r_cry_5),.O(un7_rnd_out_r[5:5]));
MUXCY_L un7_rnd_out_r_cry_6_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_5),.S(un7_rnd_out_r_axb_6),.LO(un7_rnd_out_r_cry_6));
XORCY un7_rnd_out_r_s_5(.LI(un7_rnd_out_r_axb_5),.CI(un7_rnd_out_r_cry_4),.O(un7_rnd_out_r[4:4]));
MUXCY_L un7_rnd_out_r_cry_5_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_4),.S(un7_rnd_out_r_axb_5),.LO(un7_rnd_out_r_cry_5));
XORCY un7_rnd_out_r_s_4(.LI(un7_rnd_out_r_axb_4),.CI(un7_rnd_out_r_cry_3),.O(un7_rnd_out_r[3:3]));
MUXCY_L un7_rnd_out_r_cry_4_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_3),.S(un7_rnd_out_r_axb_4),.LO(un7_rnd_out_r_cry_4));
XORCY un7_rnd_out_r_s_3(.LI(un7_rnd_out_r_axb_3),.CI(un7_rnd_out_r_cry_2),.O(un7_rnd_out_r[2:2]));
MUXCY_L un7_rnd_out_r_cry_3_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_2),.S(un7_rnd_out_r_axb_3),.LO(un7_rnd_out_r_cry_3));
XORCY un7_rnd_out_r_s_2(.LI(un7_rnd_out_r_axb_2),.CI(un7_rnd_out_r_cry_1),.O(un7_rnd_out_r[1:1]));
MUXCY_L un7_rnd_out_r_cry_2_cZ(.DI(GND),.CI(un7_rnd_out_r_cry_1),.S(un7_rnd_out_r_axb_2),.LO(un7_rnd_out_r_cry_2));
XORCY un7_rnd_out_r_s_1(.LI(un7_rnd_out_r_axb_1),.CI(pre_out_r[7:7]),.O(un7_rnd_out_r[0:0]));
MUXCY_L un7_rnd_out_r_cry_1_cZ(.DI(GND),.CI(pre_out_r[7:7]),.S(un7_rnd_out_r_axb_1),.LO(un7_rnd_out_r_cry_1));
XORCY un5_rnd_out_i_s_12_cZ(.LI(un5_rnd_out_i_axb_12),.CI(un5_rnd_out_i_cry_11),.O(un5_rnd_out_i_s_12));
XORCY un5_rnd_out_i_s_11(.LI(un5_rnd_out_i_axb_11),.CI(un5_rnd_out_i_cry_10),.O(un5_rnd_out_i[10:10]));
MUXCY_L un5_rnd_out_i_cry_11_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_10),.S(un5_rnd_out_i_axb_11),.LO(un5_rnd_out_i_cry_11));
XORCY un5_rnd_out_i_s_10(.LI(un5_rnd_out_i_axb_10),.CI(un5_rnd_out_i_cry_9),.O(un5_rnd_out_i[9:9]));
MUXCY_L un5_rnd_out_i_cry_10_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_9),.S(un5_rnd_out_i_axb_10),.LO(un5_rnd_out_i_cry_10));
XORCY un5_rnd_out_i_s_9(.LI(un5_rnd_out_i_axb_9),.CI(un5_rnd_out_i_cry_8),.O(un5_rnd_out_i[8:8]));
MUXCY_L un5_rnd_out_i_cry_9_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_8),.S(un5_rnd_out_i_axb_9),.LO(un5_rnd_out_i_cry_9));
XORCY un5_rnd_out_i_s_8(.LI(un5_rnd_out_i_axb_8),.CI(un5_rnd_out_i_cry_7),.O(un5_rnd_out_i[7:7]));
MUXCY_L un5_rnd_out_i_cry_8_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_7),.S(un5_rnd_out_i_axb_8),.LO(un5_rnd_out_i_cry_8));
XORCY un5_rnd_out_i_s_7(.LI(un5_rnd_out_i_axb_7),.CI(un5_rnd_out_i_cry_6),.O(un5_rnd_out_i[6:6]));
MUXCY_L un5_rnd_out_i_cry_7_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_6),.S(un5_rnd_out_i_axb_7),.LO(un5_rnd_out_i_cry_7));
XORCY un5_rnd_out_i_s_6(.LI(un5_rnd_out_i_axb_6),.CI(un5_rnd_out_i_cry_5),.O(un5_rnd_out_i[5:5]));
MUXCY_L un5_rnd_out_i_cry_6_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_5),.S(un5_rnd_out_i_axb_6),.LO(un5_rnd_out_i_cry_6));
XORCY un5_rnd_out_i_s_5(.LI(un5_rnd_out_i_axb_5),.CI(un5_rnd_out_i_cry_4),.O(un5_rnd_out_i[4:4]));
MUXCY_L un5_rnd_out_i_cry_5_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_4),.S(un5_rnd_out_i_axb_5),.LO(un5_rnd_out_i_cry_5));
XORCY un5_rnd_out_i_s_4(.LI(un5_rnd_out_i_axb_4),.CI(un5_rnd_out_i_cry_3),.O(un5_rnd_out_i[3:3]));
MUXCY_L un5_rnd_out_i_cry_4_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_3),.S(un5_rnd_out_i_axb_4),.LO(un5_rnd_out_i_cry_4));
XORCY un5_rnd_out_i_s_3(.LI(un5_rnd_out_i_axb_3),.CI(un5_rnd_out_i_cry_2),.O(un5_rnd_out_i[2:2]));
MUXCY_L un5_rnd_out_i_cry_3_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_2),.S(un5_rnd_out_i_axb_3),.LO(un5_rnd_out_i_cry_3));
XORCY un5_rnd_out_i_s_2(.LI(un5_rnd_out_i_axb_2),.CI(un5_rnd_out_i_cry_1),.O(un5_rnd_out_i[1:1]));
MUXCY_L un5_rnd_out_i_cry_2_cZ(.DI(GND),.CI(un5_rnd_out_i_cry_1),.S(un5_rnd_out_i_axb_2),.LO(un5_rnd_out_i_cry_2));
XORCY un5_rnd_out_i_s_1(.LI(un5_rnd_out_i_axb_1),.CI(pre_out_i[7:7]),.O(un5_rnd_out_i[0:0]));
MUXCY_L un5_rnd_out_i_cry_1_cZ(.DI(GND),.CI(pre_out_i[7:7]),.S(un5_rnd_out_i_axb_1),.LO(un5_rnd_out_i_cry_1));
FDR desc294(.Q(mult_out_r[0:0]),.D(pos_out_r_iv_i[0:0]),.C(clk),.R(un1_pos_out_r_3));
FDR desc295(.Q(mult_out_r[1:1]),.D(pos_out_r_iv_i[1:1]),.C(clk),.R(un1_pos_out_r_3));
FDR desc296(.Q(mult_out_r[2:2]),.D(pos_out_r_iv_i[2:2]),.C(clk),.R(un1_pos_out_r_3));
FDR desc297(.Q(mult_out_r[3:3]),.D(pos_out_r_iv_i[3:3]),.C(clk),.R(un1_pos_out_r_3));
FDR desc298(.Q(mult_out_r[4:4]),.D(pos_out_r_iv_i[4:4]),.C(clk),.R(un1_pos_out_r_3));
FDR desc299(.Q(mult_out_r[5:5]),.D(pos_out_r_iv_i[5:5]),.C(clk),.R(un1_pos_out_r_3));
FDR desc300(.Q(mult_out_r[6:6]),.D(pos_out_r_iv_i[6:6]),.C(clk),.R(un1_pos_out_r_3));
FDR desc301(.Q(mult_out_r[7:7]),.D(pos_out_r_iv_i[7:7]),.C(clk),.R(un1_pos_out_r_3));
FDR desc302(.Q(mult_out_r[8:8]),.D(pos_out_r_iv_i[8:8]),.C(clk),.R(un1_pos_out_r_3));
FDR desc303(.Q(mult_out_r[9:9]),.D(pos_out_r_iv_i[9:9]),.C(clk),.R(un1_pos_out_r_3));
FDR desc304(.Q(mult_out_r[10:10]),.D(pos_out_r_iv_i[10:10]),.C(clk),.R(un1_pos_out_r_3));
FDS desc305(.Q(mult_out_r[11:11]),.D(pos_out_r[11:11]),.C(clk),.S(un1_pos_out_r_3));
FDR desc306(.Q(mult_out_i[0:0]),.D(pos_out_i_iv_i[0:0]),.C(clk),.R(un1_pos_out_i_3));
FDR desc307(.Q(mult_out_i[1:1]),.D(pos_out_i_iv_i[1:1]),.C(clk),.R(un1_pos_out_i_3));
FDR desc308(.Q(mult_out_i[2:2]),.D(pos_out_i_iv_i[2:2]),.C(clk),.R(un1_pos_out_i_3));
FDR desc309(.Q(mult_out_i[3:3]),.D(pos_out_i_iv_i[3:3]),.C(clk),.R(un1_pos_out_i_3));
FDR desc310(.Q(mult_out_i[4:4]),.D(pos_out_i_iv_i[4:4]),.C(clk),.R(un1_pos_out_i_3));
FDR desc311(.Q(mult_out_i[5:5]),.D(pos_out_i_iv_i[5:5]),.C(clk),.R(un1_pos_out_i_3));
FDR desc312(.Q(mult_out_i[6:6]),.D(pos_out_i_iv_i[6:6]),.C(clk),.R(un1_pos_out_i_3));
FDR desc313(.Q(mult_out_i[7:7]),.D(pos_out_i_iv_i[7:7]),.C(clk),.R(un1_pos_out_i_3));
FDR desc314(.Q(mult_out_i[8:8]),.D(pos_out_i_iv_i[8:8]),.C(clk),.R(un1_pos_out_i_3));
FDR desc315(.Q(mult_out_i[9:9]),.D(pos_out_i_iv_i[9:9]),.C(clk),.R(un1_pos_out_i_3));
FDR desc316(.Q(mult_out_i[10:10]),.D(pos_out_i_iv_i[10:10]),.C(clk),.R(un1_pos_out_i_3));
FDS desc317(.Q(mult_out_i[11:11]),.D(pos_out_i[11:11]),.C(clk),.S(un1_pos_out_i_3));
mult_pipe_inj mult1(.mult1_out(mult1_out[23:23]),.in_a_r_reg(in_a_r_reg[11:0]),.in_b_r_reg(in_b_r_reg[11:0]),.clk(clk));
mult_pipe_1_inj mult2(.mult2_out_23(mult2_out[23:23]),.mult2_out_0(mult2_out_0[23:0]),.P_uc_34_0(P_uc_34_0[47:24]),.in_a_i_reg(in_a_i_reg[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.clk(clk));
mult_pipe_2_inj mult3(.mult3_out_23(mult3_out[23:23]),.mult3_out_0(mult3_out_0[23:0]),.P_uc_35_0(P_uc_35_0[47:24]),.in_a_r_reg(in_a_r_reg[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.clk(clk));
mult_pipe_3_inj mult4(.mult4_out(mult4_out[23:23]),.in_a_i_reg(in_a_i_reg[11:0]),.in_b_r_reg(in_b_r_reg[11:0]),.clk(clk));
add_subZ1_inj add(.pre_out_r(pre_out_r[23:7]),.in_a_r_reg(in_a_r_reg[11:0]),.in_b_r_reg(in_b_r_reg[11:0]),.mult2_out_0(mult2_out_0[23:0]),.P_uc_34_0(P_uc_34_0[47:24]),.PATTERNDETECT_7(PATTERNDETECT_7),.clk(clk));
add_subZ2_inj sub(.pre_out_i(pre_out_i[23:7]),.in_a_i_reg(in_a_i_reg[11:0]),.in_b_r_reg(in_b_r_reg[11:0]),.mult3_out_0(mult3_out_0[23:0]),.P_uc_35_0(P_uc_35_0[47:24]),.PATTERNDETECT_8(PATTERNDETECT_8),.clk(clk));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
endmodule
module desc481_inj (out_i_vec_mult_2,out_r_vec_mult_2,out_inner_prod_r,vec_out_r_AQ_2,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,vec_out_i_AQ_2,out_inner_prod_i,in_b_i_reg,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output [11:0] out_i_vec_mult_2 ;
output [11:0] out_r_vec_mult_2 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_2 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input [11:0] vec_out_i_AQ_2 ;
input [11:0] out_inner_prod_i ;
input [11:0] in_b_i_reg ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [23:7] pre_out_r ;
wire [23:7] pre_out_i ;
wire [23:23] mult2_out ;
wire [23:23] mult1_out ;
wire [23:23] mult3_out ;
wire [23:23] mult4_out ;
wire [11:11] pos_out_r ;
wire [11:11] pos_out_i ;
wire [10:0] un1_rnd_out_i ;
wire [10:0] pos_out_i_iv_i ;
wire [10:0] un2_rnd_out_r ;
wire [10:0] pos_out_r_iv_i ;
wire [23:0] mult1_out_0 ;
wire [47:24] P_uc_24_0 ;
wire [23:0] mult4_out_0 ;
wire [47:24] P_uc_27_0 ;
wire un2_rnd_out_r_axb_1 ;
wire un2_rnd_out_r_axb_2 ;
wire un2_rnd_out_r_axb_3 ;
wire un2_rnd_out_r_axb_4 ;
wire un2_rnd_out_r_axb_5 ;
wire un2_rnd_out_r_axb_6 ;
wire un2_rnd_out_r_axb_7 ;
wire un2_rnd_out_r_axb_8 ;
wire un2_rnd_out_r_axb_9 ;
wire un2_rnd_out_r_axb_10 ;
wire un2_rnd_out_r_axb_11 ;
wire un1_rnd_out_i_axb_1 ;
wire un1_rnd_out_i_axb_2 ;
wire un1_rnd_out_i_axb_3 ;
wire un1_rnd_out_i_axb_4 ;
wire un1_rnd_out_i_axb_5 ;
wire un1_rnd_out_i_axb_6 ;
wire un1_rnd_out_i_axb_7 ;
wire un1_rnd_out_i_axb_8 ;
wire un1_rnd_out_i_axb_9 ;
wire un1_rnd_out_i_axb_10 ;
wire un1_rnd_out_i_axb_11 ;
wire un1_rnd_out_i_axb_12 ;
wire un2_rnd_out_r_axb_12 ;
wire un5_rnd_sat_out_r_3 ;
wire un4_rnd_sat_out_i_3 ;
wire un1_pos_out_r ;
wire un1_pos_out_i ;
wire PATTERNDETECT_4 ;
wire un2_rnd_out_r_s_12 ;
wire PATTERNDETECT_3 ;
wire un1_rnd_out_i_s_12 ;
wire un1_rnd_out_i_cry_11 ;
wire un1_rnd_out_i_cry_10 ;
wire GND ;
wire un1_rnd_out_i_cry_9 ;
wire un1_rnd_out_i_cry_8 ;
wire un1_rnd_out_i_cry_7 ;
wire un1_rnd_out_i_cry_6 ;
wire un1_rnd_out_i_cry_5 ;
wire un1_rnd_out_i_cry_4 ;
wire un1_rnd_out_i_cry_3 ;
wire un1_rnd_out_i_cry_2 ;
wire un1_rnd_out_i_cry_1 ;
wire un2_rnd_out_r_cry_11 ;
wire un2_rnd_out_r_cry_10 ;
wire un2_rnd_out_r_cry_9 ;
wire un2_rnd_out_r_cry_8 ;
wire un2_rnd_out_r_cry_7 ;
wire un2_rnd_out_r_cry_6 ;
wire un2_rnd_out_r_cry_5 ;
wire un2_rnd_out_r_cry_4 ;
wire un2_rnd_out_r_cry_3 ;
wire un2_rnd_out_r_cry_2 ;
wire un2_rnd_out_r_cry_1 ;
wire VCC ;
// instances
LUT1 un2_rnd_out_r_axb_1_cZ(.I0(pre_out_r[8:8]),.O(un2_rnd_out_r_axb_1));
defparam un2_rnd_out_r_axb_1_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_2_cZ(.I0(pre_out_r[9:9]),.O(un2_rnd_out_r_axb_2));
defparam un2_rnd_out_r_axb_2_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_3_cZ(.I0(pre_out_r[10:10]),.O(un2_rnd_out_r_axb_3));
defparam un2_rnd_out_r_axb_3_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_4_cZ(.I0(pre_out_r[11:11]),.O(un2_rnd_out_r_axb_4));
defparam un2_rnd_out_r_axb_4_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_5_cZ(.I0(pre_out_r[12:12]),.O(un2_rnd_out_r_axb_5));
defparam un2_rnd_out_r_axb_5_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_6_cZ(.I0(pre_out_r[13:13]),.O(un2_rnd_out_r_axb_6));
defparam un2_rnd_out_r_axb_6_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_7_cZ(.I0(pre_out_r[14:14]),.O(un2_rnd_out_r_axb_7));
defparam un2_rnd_out_r_axb_7_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_8_cZ(.I0(pre_out_r[15:15]),.O(un2_rnd_out_r_axb_8));
defparam un2_rnd_out_r_axb_8_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_9_cZ(.I0(pre_out_r[16:16]),.O(un2_rnd_out_r_axb_9));
defparam un2_rnd_out_r_axb_9_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_10_cZ(.I0(pre_out_r[17:17]),.O(un2_rnd_out_r_axb_10));
defparam un2_rnd_out_r_axb_10_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_11_cZ(.I0(pre_out_r[18:18]),.O(un2_rnd_out_r_axb_11));
defparam un2_rnd_out_r_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_1_cZ(.I0(pre_out_i[8:8]),.O(un1_rnd_out_i_axb_1));
defparam un1_rnd_out_i_axb_1_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_2_cZ(.I0(pre_out_i[9:9]),.O(un1_rnd_out_i_axb_2));
defparam un1_rnd_out_i_axb_2_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_3_cZ(.I0(pre_out_i[10:10]),.O(un1_rnd_out_i_axb_3));
defparam un1_rnd_out_i_axb_3_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_4_cZ(.I0(pre_out_i[11:11]),.O(un1_rnd_out_i_axb_4));
defparam un1_rnd_out_i_axb_4_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_5_cZ(.I0(pre_out_i[12:12]),.O(un1_rnd_out_i_axb_5));
defparam un1_rnd_out_i_axb_5_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_6_cZ(.I0(pre_out_i[13:13]),.O(un1_rnd_out_i_axb_6));
defparam un1_rnd_out_i_axb_6_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_7_cZ(.I0(pre_out_i[14:14]),.O(un1_rnd_out_i_axb_7));
defparam un1_rnd_out_i_axb_7_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_8_cZ(.I0(pre_out_i[15:15]),.O(un1_rnd_out_i_axb_8));
defparam un1_rnd_out_i_axb_8_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_9_cZ(.I0(pre_out_i[16:16]),.O(un1_rnd_out_i_axb_9));
defparam un1_rnd_out_i_axb_9_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_10_cZ(.I0(pre_out_i[17:17]),.O(un1_rnd_out_i_axb_10));
defparam un1_rnd_out_i_axb_10_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_11_cZ(.I0(pre_out_i[18:18]),.O(un1_rnd_out_i_axb_11));
defparam un1_rnd_out_i_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_12_cZ(.I0(pre_out_i[19:19]),.O(un1_rnd_out_i_axb_12));
defparam un1_rnd_out_i_axb_12_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_12_cZ(.I0(pre_out_r[19:19]),.O(un2_rnd_out_r_axb_12));
defparam un2_rnd_out_r_axb_12_cZ.INIT=2'h2;
LUT4 un5_rnd_sat_out_r_3_cZ(.I0(pre_out_r[20:20]),.I1(pre_out_r[21:21]),.I2(pre_out_r[22:22]),.I3(pre_out_r[19:19]),.O(un5_rnd_sat_out_r_3));
defparam un5_rnd_sat_out_r_3_cZ.INIT=16'h8000;
LUT4 un4_rnd_sat_out_i_3_cZ(.I0(pre_out_i[20:20]),.I1(pre_out_i[21:21]),.I2(pre_out_i[22:22]),.I3(pre_out_i[19:19]),.O(un4_rnd_sat_out_i_3));
defparam un4_rnd_sat_out_i_3_cZ.INIT=16'h8000;
LUT3 un1_pos_out_r_cZ(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.O(un1_pos_out_r));
defparam un1_pos_out_r_cZ.INIT=8'h04;
LUT3 un1_pos_out_i_cZ(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.O(un1_pos_out_i));
defparam un1_pos_out_i_cZ.INIT=8'h08;
LUT6_L desc482(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r_s_12),.LO(pos_out_r[11:11]));
defparam desc482.INIT=64'hDBD0DBD00000D0D0;
LUT6_L desc483(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i_s_12),.LO(pos_out_i[11:11]));
defparam desc483.INIT=64'hE7E0E7E00000E0E0;
LUT6_L desc484(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[10:10]),.LO(pos_out_i_iv_i[10:10]));
defparam desc484.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc485(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[9:9]),.LO(pos_out_i_iv_i[9:9]));
defparam desc485.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc486(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[8:8]),.LO(pos_out_i_iv_i[8:8]));
defparam desc486.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc487(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[7:7]),.LO(pos_out_i_iv_i[7:7]));
defparam desc487.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc488(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[6:6]),.LO(pos_out_i_iv_i[6:6]));
defparam desc488.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc489(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[5:5]),.LO(pos_out_i_iv_i[5:5]));
defparam desc489.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc490(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[4:4]),.LO(pos_out_i_iv_i[4:4]));
defparam desc490.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc491(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[3:3]),.LO(pos_out_i_iv_i[3:3]));
defparam desc491.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc492(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[2:2]),.LO(pos_out_i_iv_i[2:2]));
defparam desc492.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc493(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_3),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[1:1]),.LO(pos_out_i_iv_i[1:1]));
defparam desc493.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc494(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(un1_rnd_out_i[0:0]),.I4(PATTERNDETECT_3),.I5(un4_rnd_sat_out_i_3),.LO(pos_out_i_iv_i[0:0]));
defparam desc494.INIT=64'hFF18FF1F1F181F1F;
LUT6_L desc495(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[10:10]),.LO(pos_out_r_iv_i[10:10]));
defparam desc495.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc496(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[9:9]),.LO(pos_out_r_iv_i[9:9]));
defparam desc496.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc497(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[8:8]),.LO(pos_out_r_iv_i[8:8]));
defparam desc497.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc498(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[7:7]),.LO(pos_out_r_iv_i[7:7]));
defparam desc498.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc499(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[6:6]),.LO(pos_out_r_iv_i[6:6]));
defparam desc499.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc500(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[5:5]),.LO(pos_out_r_iv_i[5:5]));
defparam desc500.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc501(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[4:4]),.LO(pos_out_r_iv_i[4:4]));
defparam desc501.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc502(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[3:3]),.LO(pos_out_r_iv_i[3:3]));
defparam desc502.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc503(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[2:2]),.LO(pos_out_r_iv_i[2:2]));
defparam desc503.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc504(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_4),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[1:1]),.LO(pos_out_r_iv_i[1:1]));
defparam desc504.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc505(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(un2_rnd_out_r[0:0]),.I4(PATTERNDETECT_4),.I5(un5_rnd_sat_out_r_3),.LO(pos_out_r_iv_i[0:0]));
defparam desc505.INIT=64'hFF24FF2F2F242F2F;
XORCY un1_rnd_out_i_s_12_cZ(.LI(un1_rnd_out_i_axb_12),.CI(un1_rnd_out_i_cry_11),.O(un1_rnd_out_i_s_12));
XORCY un1_rnd_out_i_s_11(.LI(un1_rnd_out_i_axb_11),.CI(un1_rnd_out_i_cry_10),.O(un1_rnd_out_i[10:10]));
MUXCY_L un1_rnd_out_i_cry_11_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_10),.S(un1_rnd_out_i_axb_11),.LO(un1_rnd_out_i_cry_11));
XORCY un1_rnd_out_i_s_10(.LI(un1_rnd_out_i_axb_10),.CI(un1_rnd_out_i_cry_9),.O(un1_rnd_out_i[9:9]));
MUXCY_L un1_rnd_out_i_cry_10_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_9),.S(un1_rnd_out_i_axb_10),.LO(un1_rnd_out_i_cry_10));
XORCY un1_rnd_out_i_s_9(.LI(un1_rnd_out_i_axb_9),.CI(un1_rnd_out_i_cry_8),.O(un1_rnd_out_i[8:8]));
MUXCY_L un1_rnd_out_i_cry_9_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_8),.S(un1_rnd_out_i_axb_9),.LO(un1_rnd_out_i_cry_9));
XORCY un1_rnd_out_i_s_8(.LI(un1_rnd_out_i_axb_8),.CI(un1_rnd_out_i_cry_7),.O(un1_rnd_out_i[7:7]));
MUXCY_L un1_rnd_out_i_cry_8_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_7),.S(un1_rnd_out_i_axb_8),.LO(un1_rnd_out_i_cry_8));
XORCY un1_rnd_out_i_s_7(.LI(un1_rnd_out_i_axb_7),.CI(un1_rnd_out_i_cry_6),.O(un1_rnd_out_i[6:6]));
MUXCY_L un1_rnd_out_i_cry_7_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_6),.S(un1_rnd_out_i_axb_7),.LO(un1_rnd_out_i_cry_7));
XORCY un1_rnd_out_i_s_6(.LI(un1_rnd_out_i_axb_6),.CI(un1_rnd_out_i_cry_5),.O(un1_rnd_out_i[5:5]));
MUXCY_L un1_rnd_out_i_cry_6_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_5),.S(un1_rnd_out_i_axb_6),.LO(un1_rnd_out_i_cry_6));
XORCY un1_rnd_out_i_s_5(.LI(un1_rnd_out_i_axb_5),.CI(un1_rnd_out_i_cry_4),.O(un1_rnd_out_i[4:4]));
MUXCY_L un1_rnd_out_i_cry_5_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_4),.S(un1_rnd_out_i_axb_5),.LO(un1_rnd_out_i_cry_5));
XORCY un1_rnd_out_i_s_4(.LI(un1_rnd_out_i_axb_4),.CI(un1_rnd_out_i_cry_3),.O(un1_rnd_out_i[3:3]));
MUXCY_L un1_rnd_out_i_cry_4_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_3),.S(un1_rnd_out_i_axb_4),.LO(un1_rnd_out_i_cry_4));
XORCY un1_rnd_out_i_s_3(.LI(un1_rnd_out_i_axb_3),.CI(un1_rnd_out_i_cry_2),.O(un1_rnd_out_i[2:2]));
MUXCY_L un1_rnd_out_i_cry_3_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_2),.S(un1_rnd_out_i_axb_3),.LO(un1_rnd_out_i_cry_3));
XORCY un1_rnd_out_i_s_2(.LI(un1_rnd_out_i_axb_2),.CI(un1_rnd_out_i_cry_1),.O(un1_rnd_out_i[1:1]));
MUXCY_L un1_rnd_out_i_cry_2_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_1),.S(un1_rnd_out_i_axb_2),.LO(un1_rnd_out_i_cry_2));
XORCY un1_rnd_out_i_s_1(.LI(un1_rnd_out_i_axb_1),.CI(pre_out_i[7:7]),.O(un1_rnd_out_i[0:0]));
MUXCY_L un1_rnd_out_i_cry_1_cZ(.DI(GND),.CI(pre_out_i[7:7]),.S(un1_rnd_out_i_axb_1),.LO(un1_rnd_out_i_cry_1));
XORCY un2_rnd_out_r_s_12_cZ(.LI(un2_rnd_out_r_axb_12),.CI(un2_rnd_out_r_cry_11),.O(un2_rnd_out_r_s_12));
XORCY un2_rnd_out_r_s_11(.LI(un2_rnd_out_r_axb_11),.CI(un2_rnd_out_r_cry_10),.O(un2_rnd_out_r[10:10]));
MUXCY_L un2_rnd_out_r_cry_11_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_10),.S(un2_rnd_out_r_axb_11),.LO(un2_rnd_out_r_cry_11));
XORCY un2_rnd_out_r_s_10(.LI(un2_rnd_out_r_axb_10),.CI(un2_rnd_out_r_cry_9),.O(un2_rnd_out_r[9:9]));
MUXCY_L un2_rnd_out_r_cry_10_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_9),.S(un2_rnd_out_r_axb_10),.LO(un2_rnd_out_r_cry_10));
XORCY un2_rnd_out_r_s_9(.LI(un2_rnd_out_r_axb_9),.CI(un2_rnd_out_r_cry_8),.O(un2_rnd_out_r[8:8]));
MUXCY_L un2_rnd_out_r_cry_9_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_8),.S(un2_rnd_out_r_axb_9),.LO(un2_rnd_out_r_cry_9));
XORCY un2_rnd_out_r_s_8(.LI(un2_rnd_out_r_axb_8),.CI(un2_rnd_out_r_cry_7),.O(un2_rnd_out_r[7:7]));
MUXCY_L un2_rnd_out_r_cry_8_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_7),.S(un2_rnd_out_r_axb_8),.LO(un2_rnd_out_r_cry_8));
XORCY un2_rnd_out_r_s_7(.LI(un2_rnd_out_r_axb_7),.CI(un2_rnd_out_r_cry_6),.O(un2_rnd_out_r[6:6]));
MUXCY_L un2_rnd_out_r_cry_7_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_6),.S(un2_rnd_out_r_axb_7),.LO(un2_rnd_out_r_cry_7));
XORCY un2_rnd_out_r_s_6(.LI(un2_rnd_out_r_axb_6),.CI(un2_rnd_out_r_cry_5),.O(un2_rnd_out_r[5:5]));
MUXCY_L un2_rnd_out_r_cry_6_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_5),.S(un2_rnd_out_r_axb_6),.LO(un2_rnd_out_r_cry_6));
XORCY un2_rnd_out_r_s_5(.LI(un2_rnd_out_r_axb_5),.CI(un2_rnd_out_r_cry_4),.O(un2_rnd_out_r[4:4]));
MUXCY_L un2_rnd_out_r_cry_5_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_4),.S(un2_rnd_out_r_axb_5),.LO(un2_rnd_out_r_cry_5));
XORCY un2_rnd_out_r_s_4(.LI(un2_rnd_out_r_axb_4),.CI(un2_rnd_out_r_cry_3),.O(un2_rnd_out_r[3:3]));
MUXCY_L un2_rnd_out_r_cry_4_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_3),.S(un2_rnd_out_r_axb_4),.LO(un2_rnd_out_r_cry_4));
XORCY un2_rnd_out_r_s_3(.LI(un2_rnd_out_r_axb_3),.CI(un2_rnd_out_r_cry_2),.O(un2_rnd_out_r[2:2]));
MUXCY_L un2_rnd_out_r_cry_3_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_2),.S(un2_rnd_out_r_axb_3),.LO(un2_rnd_out_r_cry_3));
XORCY un2_rnd_out_r_s_2(.LI(un2_rnd_out_r_axb_2),.CI(un2_rnd_out_r_cry_1),.O(un2_rnd_out_r[1:1]));
MUXCY_L un2_rnd_out_r_cry_2_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_1),.S(un2_rnd_out_r_axb_2),.LO(un2_rnd_out_r_cry_2));
XORCY un2_rnd_out_r_s_1(.LI(un2_rnd_out_r_axb_1),.CI(pre_out_r[7:7]),.O(un2_rnd_out_r[0:0]));
MUXCY_L un2_rnd_out_r_cry_1_cZ(.DI(GND),.CI(pre_out_r[7:7]),.S(un2_rnd_out_r_axb_1),.LO(un2_rnd_out_r_cry_1));
FDS desc506(.Q(out_i_vec_mult_2[11:11]),.D(pos_out_i[11:11]),.C(clk),.S(un1_pos_out_i));
FDR desc507(.Q(out_i_vec_mult_2[10:10]),.D(pos_out_i_iv_i[10:10]),.C(clk),.R(un1_pos_out_i));
FDR desc508(.Q(out_i_vec_mult_2[9:9]),.D(pos_out_i_iv_i[9:9]),.C(clk),.R(un1_pos_out_i));
FDR desc509(.Q(out_i_vec_mult_2[8:8]),.D(pos_out_i_iv_i[8:8]),.C(clk),.R(un1_pos_out_i));
FDR desc510(.Q(out_i_vec_mult_2[7:7]),.D(pos_out_i_iv_i[7:7]),.C(clk),.R(un1_pos_out_i));
FDR desc511(.Q(out_i_vec_mult_2[6:6]),.D(pos_out_i_iv_i[6:6]),.C(clk),.R(un1_pos_out_i));
FDR desc512(.Q(out_i_vec_mult_2[5:5]),.D(pos_out_i_iv_i[5:5]),.C(clk),.R(un1_pos_out_i));
FDR desc513(.Q(out_i_vec_mult_2[4:4]),.D(pos_out_i_iv_i[4:4]),.C(clk),.R(un1_pos_out_i));
FDR desc514(.Q(out_i_vec_mult_2[3:3]),.D(pos_out_i_iv_i[3:3]),.C(clk),.R(un1_pos_out_i));
FDR desc515(.Q(out_i_vec_mult_2[2:2]),.D(pos_out_i_iv_i[2:2]),.C(clk),.R(un1_pos_out_i));
FDR desc516(.Q(out_i_vec_mult_2[1:1]),.D(pos_out_i_iv_i[1:1]),.C(clk),.R(un1_pos_out_i));
FDR desc517(.Q(out_i_vec_mult_2[0:0]),.D(pos_out_i_iv_i[0:0]),.C(clk),.R(un1_pos_out_i));
FDS desc518(.Q(out_r_vec_mult_2[11:11]),.D(pos_out_r[11:11]),.C(clk),.S(un1_pos_out_r));
FDR desc519(.Q(out_r_vec_mult_2[10:10]),.D(pos_out_r_iv_i[10:10]),.C(clk),.R(un1_pos_out_r));
FDR desc520(.Q(out_r_vec_mult_2[9:9]),.D(pos_out_r_iv_i[9:9]),.C(clk),.R(un1_pos_out_r));
FDR desc521(.Q(out_r_vec_mult_2[8:8]),.D(pos_out_r_iv_i[8:8]),.C(clk),.R(un1_pos_out_r));
FDR desc522(.Q(out_r_vec_mult_2[7:7]),.D(pos_out_r_iv_i[7:7]),.C(clk),.R(un1_pos_out_r));
FDR desc523(.Q(out_r_vec_mult_2[6:6]),.D(pos_out_r_iv_i[6:6]),.C(clk),.R(un1_pos_out_r));
FDR desc524(.Q(out_r_vec_mult_2[5:5]),.D(pos_out_r_iv_i[5:5]),.C(clk),.R(un1_pos_out_r));
FDR desc525(.Q(out_r_vec_mult_2[4:4]),.D(pos_out_r_iv_i[4:4]),.C(clk),.R(un1_pos_out_r));
FDR desc526(.Q(out_r_vec_mult_2[3:3]),.D(pos_out_r_iv_i[3:3]),.C(clk),.R(un1_pos_out_r));
FDR desc527(.Q(out_r_vec_mult_2[2:2]),.D(pos_out_r_iv_i[2:2]),.C(clk),.R(un1_pos_out_r));
FDR desc528(.Q(out_r_vec_mult_2[1:1]),.D(pos_out_r_iv_i[1:1]),.C(clk),.R(un1_pos_out_r));
FDR desc529(.Q(out_r_vec_mult_2[0:0]),.D(pos_out_r_iv_i[0:0]),.C(clk),.R(un1_pos_out_r));
mult_pipe_4_inj mult1(.mult1_out_23(mult1_out[23:23]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_24_0(P_uc_24_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_2(vec_out_r_AQ_2[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
mult_pipe_5_inj mult2(.mult2_out_23(mult2_out[23:23]),.vec_out_i_AQ_2(vec_out_i_AQ_2[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_6_inj mult3(.mult3_out_23(mult3_out[23:23]),.vec_out_r_AQ_2(vec_out_r_AQ_2[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_7_inj mult4(.mult4_out_23(mult4_out[23:23]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_27_0(P_uc_27_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_i_AQ_2(vec_out_i_AQ_2[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
add_subZ2_1_inj sub(.pre_out_r(pre_out_r[23:7]),.vec_out_i_AQ_2(vec_out_i_AQ_2[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_24_0(P_uc_24_0[47:24]),.PATTERNDETECT_4(PATTERNDETECT_4),.clk(clk));
add_subZ1_1_inj add(.pre_out_i(pre_out_i[23:7]),.vec_out_r_AQ_2(vec_out_r_AQ_2[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_27_0(P_uc_27_0[47:24]),.PATTERNDETECT_3(PATTERNDETECT_3),.clk(clk));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
endmodule
module desc536_inj (out_i_vec_mult_1,out_r_vec_mult_1,out_inner_prod_r,vec_out_r_AQ_1,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,vec_out_i_AQ_1,out_inner_prod_i,in_b_i_reg,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output [11:0] out_i_vec_mult_1 ;
output [11:0] out_r_vec_mult_1 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_1 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input [11:0] vec_out_i_AQ_1 ;
input [11:0] out_inner_prod_i ;
input [11:0] in_b_i_reg ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [23:7] pre_out_r ;
wire [23:7] pre_out_i ;
wire [23:23] mult2_out ;
wire [23:23] mult1_out ;
wire [23:23] mult3_out ;
wire [23:23] mult4_out ;
wire [11:11] pos_out_r ;
wire [11:11] pos_out_i ;
wire [10:0] un1_rnd_out_i ;
wire [10:0] pos_out_i_iv_i ;
wire [10:0] un2_rnd_out_r ;
wire [10:0] pos_out_r_iv_i ;
wire [23:0] mult1_out_0 ;
wire [47:24] P_uc_20_0 ;
wire [23:0] mult4_out_0 ;
wire [47:24] P_uc_23_0 ;
wire un2_rnd_out_r_axb_1 ;
wire un2_rnd_out_r_axb_2 ;
wire un2_rnd_out_r_axb_3 ;
wire un2_rnd_out_r_axb_4 ;
wire un2_rnd_out_r_axb_5 ;
wire un2_rnd_out_r_axb_6 ;
wire un2_rnd_out_r_axb_7 ;
wire un2_rnd_out_r_axb_8 ;
wire un2_rnd_out_r_axb_9 ;
wire un2_rnd_out_r_axb_10 ;
wire un2_rnd_out_r_axb_11 ;
wire un1_rnd_out_i_axb_1 ;
wire un1_rnd_out_i_axb_2 ;
wire un1_rnd_out_i_axb_3 ;
wire un1_rnd_out_i_axb_4 ;
wire un1_rnd_out_i_axb_5 ;
wire un1_rnd_out_i_axb_6 ;
wire un1_rnd_out_i_axb_7 ;
wire un1_rnd_out_i_axb_8 ;
wire un1_rnd_out_i_axb_9 ;
wire un1_rnd_out_i_axb_10 ;
wire un1_rnd_out_i_axb_11 ;
wire un1_rnd_out_i_axb_12 ;
wire un2_rnd_out_r_axb_12 ;
wire un4_rnd_sat_out_i_3 ;
wire un5_rnd_sat_out_r_3 ;
wire un1_pos_out_r_0 ;
wire un1_pos_out_i_0 ;
wire PATTERNDETECT_2 ;
wire un2_rnd_out_r_s_12_2 ;
wire PATTERNDETECT_1 ;
wire un1_rnd_out_i_s_12_2 ;
wire un1_rnd_out_i_cry_11 ;
wire un1_rnd_out_i_cry_10 ;
wire GND ;
wire un1_rnd_out_i_cry_9 ;
wire un1_rnd_out_i_cry_8 ;
wire un1_rnd_out_i_cry_7 ;
wire un1_rnd_out_i_cry_6 ;
wire un1_rnd_out_i_cry_5 ;
wire un1_rnd_out_i_cry_4 ;
wire un1_rnd_out_i_cry_3 ;
wire un1_rnd_out_i_cry_2 ;
wire un1_rnd_out_i_cry_1 ;
wire un2_rnd_out_r_cry_11 ;
wire un2_rnd_out_r_cry_10 ;
wire un2_rnd_out_r_cry_9 ;
wire un2_rnd_out_r_cry_8 ;
wire un2_rnd_out_r_cry_7 ;
wire un2_rnd_out_r_cry_6 ;
wire un2_rnd_out_r_cry_5 ;
wire un2_rnd_out_r_cry_4 ;
wire un2_rnd_out_r_cry_3 ;
wire un2_rnd_out_r_cry_2 ;
wire un2_rnd_out_r_cry_1 ;
wire VCC ;
// instances
LUT1 un2_rnd_out_r_axb_1_cZ(.I0(pre_out_r[8:8]),.O(un2_rnd_out_r_axb_1));
defparam un2_rnd_out_r_axb_1_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_2_cZ(.I0(pre_out_r[9:9]),.O(un2_rnd_out_r_axb_2));
defparam un2_rnd_out_r_axb_2_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_3_cZ(.I0(pre_out_r[10:10]),.O(un2_rnd_out_r_axb_3));
defparam un2_rnd_out_r_axb_3_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_4_cZ(.I0(pre_out_r[11:11]),.O(un2_rnd_out_r_axb_4));
defparam un2_rnd_out_r_axb_4_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_5_cZ(.I0(pre_out_r[12:12]),.O(un2_rnd_out_r_axb_5));
defparam un2_rnd_out_r_axb_5_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_6_cZ(.I0(pre_out_r[13:13]),.O(un2_rnd_out_r_axb_6));
defparam un2_rnd_out_r_axb_6_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_7_cZ(.I0(pre_out_r[14:14]),.O(un2_rnd_out_r_axb_7));
defparam un2_rnd_out_r_axb_7_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_8_cZ(.I0(pre_out_r[15:15]),.O(un2_rnd_out_r_axb_8));
defparam un2_rnd_out_r_axb_8_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_9_cZ(.I0(pre_out_r[16:16]),.O(un2_rnd_out_r_axb_9));
defparam un2_rnd_out_r_axb_9_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_10_cZ(.I0(pre_out_r[17:17]),.O(un2_rnd_out_r_axb_10));
defparam un2_rnd_out_r_axb_10_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_11_cZ(.I0(pre_out_r[18:18]),.O(un2_rnd_out_r_axb_11));
defparam un2_rnd_out_r_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_1_cZ(.I0(pre_out_i[8:8]),.O(un1_rnd_out_i_axb_1));
defparam un1_rnd_out_i_axb_1_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_2_cZ(.I0(pre_out_i[9:9]),.O(un1_rnd_out_i_axb_2));
defparam un1_rnd_out_i_axb_2_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_3_cZ(.I0(pre_out_i[10:10]),.O(un1_rnd_out_i_axb_3));
defparam un1_rnd_out_i_axb_3_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_4_cZ(.I0(pre_out_i[11:11]),.O(un1_rnd_out_i_axb_4));
defparam un1_rnd_out_i_axb_4_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_5_cZ(.I0(pre_out_i[12:12]),.O(un1_rnd_out_i_axb_5));
defparam un1_rnd_out_i_axb_5_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_6_cZ(.I0(pre_out_i[13:13]),.O(un1_rnd_out_i_axb_6));
defparam un1_rnd_out_i_axb_6_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_7_cZ(.I0(pre_out_i[14:14]),.O(un1_rnd_out_i_axb_7));
defparam un1_rnd_out_i_axb_7_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_8_cZ(.I0(pre_out_i[15:15]),.O(un1_rnd_out_i_axb_8));
defparam un1_rnd_out_i_axb_8_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_9_cZ(.I0(pre_out_i[16:16]),.O(un1_rnd_out_i_axb_9));
defparam un1_rnd_out_i_axb_9_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_10_cZ(.I0(pre_out_i[17:17]),.O(un1_rnd_out_i_axb_10));
defparam un1_rnd_out_i_axb_10_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_11_cZ(.I0(pre_out_i[18:18]),.O(un1_rnd_out_i_axb_11));
defparam un1_rnd_out_i_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_12_cZ(.I0(pre_out_i[19:19]),.O(un1_rnd_out_i_axb_12));
defparam un1_rnd_out_i_axb_12_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_12_cZ(.I0(pre_out_r[19:19]),.O(un2_rnd_out_r_axb_12));
defparam un2_rnd_out_r_axb_12_cZ.INIT=2'h2;
LUT4 un4_rnd_sat_out_i_3_cZ(.I0(pre_out_i[20:20]),.I1(pre_out_i[21:21]),.I2(pre_out_i[22:22]),.I3(pre_out_i[19:19]),.O(un4_rnd_sat_out_i_3));
defparam un4_rnd_sat_out_i_3_cZ.INIT=16'h8000;
LUT4 un5_rnd_sat_out_r_3_cZ(.I0(pre_out_r[20:20]),.I1(pre_out_r[21:21]),.I2(pre_out_r[22:22]),.I3(pre_out_r[19:19]),.O(un5_rnd_sat_out_r_3));
defparam un5_rnd_sat_out_r_3_cZ.INIT=16'h8000;
LUT3 un1_pos_out_r(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.O(un1_pos_out_r_0));
defparam un1_pos_out_r.INIT=8'h04;
LUT3 un1_pos_out_i(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.O(un1_pos_out_i_0));
defparam un1_pos_out_i.INIT=8'h08;
LUT6_L desc537(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r_s_12_2),.LO(pos_out_r[11:11]));
defparam desc537.INIT=64'hDBD0DBD00000D0D0;
LUT6_L desc538(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i_s_12_2),.LO(pos_out_i[11:11]));
defparam desc538.INIT=64'hE7E0E7E00000E0E0;
LUT6_L desc539(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[10:10]),.LO(pos_out_i_iv_i[10:10]));
defparam desc539.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc540(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[9:9]),.LO(pos_out_i_iv_i[9:9]));
defparam desc540.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc541(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[8:8]),.LO(pos_out_i_iv_i[8:8]));
defparam desc541.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc542(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[7:7]),.LO(pos_out_i_iv_i[7:7]));
defparam desc542.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc543(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[6:6]),.LO(pos_out_i_iv_i[6:6]));
defparam desc543.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc544(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[5:5]),.LO(pos_out_i_iv_i[5:5]));
defparam desc544.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc545(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[4:4]),.LO(pos_out_i_iv_i[4:4]));
defparam desc545.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc546(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[3:3]),.LO(pos_out_i_iv_i[3:3]));
defparam desc546.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc547(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[2:2]),.LO(pos_out_i_iv_i[2:2]));
defparam desc547.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc548(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_1),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[1:1]),.LO(pos_out_i_iv_i[1:1]));
defparam desc548.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc549(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(un1_rnd_out_i[0:0]),.I4(PATTERNDETECT_1),.I5(un4_rnd_sat_out_i_3),.LO(pos_out_i_iv_i[0:0]));
defparam desc549.INIT=64'hFF18FF1F1F181F1F;
LUT6_L desc550(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[10:10]),.LO(pos_out_r_iv_i[10:10]));
defparam desc550.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc551(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[9:9]),.LO(pos_out_r_iv_i[9:9]));
defparam desc551.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc552(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[8:8]),.LO(pos_out_r_iv_i[8:8]));
defparam desc552.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc553(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[7:7]),.LO(pos_out_r_iv_i[7:7]));
defparam desc553.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc554(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[6:6]),.LO(pos_out_r_iv_i[6:6]));
defparam desc554.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc555(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[5:5]),.LO(pos_out_r_iv_i[5:5]));
defparam desc555.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc556(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[4:4]),.LO(pos_out_r_iv_i[4:4]));
defparam desc556.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc557(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[3:3]),.LO(pos_out_r_iv_i[3:3]));
defparam desc557.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc558(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[2:2]),.LO(pos_out_r_iv_i[2:2]));
defparam desc558.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc559(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_2),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[1:1]),.LO(pos_out_r_iv_i[1:1]));
defparam desc559.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc560(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(un2_rnd_out_r[0:0]),.I4(PATTERNDETECT_2),.I5(un5_rnd_sat_out_r_3),.LO(pos_out_r_iv_i[0:0]));
defparam desc560.INIT=64'hFF24FF2F2F242F2F;
XORCY un1_rnd_out_i_s_12(.LI(un1_rnd_out_i_axb_12),.CI(un1_rnd_out_i_cry_11),.O(un1_rnd_out_i_s_12_2));
XORCY un1_rnd_out_i_s_11(.LI(un1_rnd_out_i_axb_11),.CI(un1_rnd_out_i_cry_10),.O(un1_rnd_out_i[10:10]));
MUXCY_L un1_rnd_out_i_cry_11_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_10),.S(un1_rnd_out_i_axb_11),.LO(un1_rnd_out_i_cry_11));
XORCY un1_rnd_out_i_s_10(.LI(un1_rnd_out_i_axb_10),.CI(un1_rnd_out_i_cry_9),.O(un1_rnd_out_i[9:9]));
MUXCY_L un1_rnd_out_i_cry_10_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_9),.S(un1_rnd_out_i_axb_10),.LO(un1_rnd_out_i_cry_10));
XORCY un1_rnd_out_i_s_9(.LI(un1_rnd_out_i_axb_9),.CI(un1_rnd_out_i_cry_8),.O(un1_rnd_out_i[8:8]));
MUXCY_L un1_rnd_out_i_cry_9_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_8),.S(un1_rnd_out_i_axb_9),.LO(un1_rnd_out_i_cry_9));
XORCY un1_rnd_out_i_s_8(.LI(un1_rnd_out_i_axb_8),.CI(un1_rnd_out_i_cry_7),.O(un1_rnd_out_i[7:7]));
MUXCY_L un1_rnd_out_i_cry_8_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_7),.S(un1_rnd_out_i_axb_8),.LO(un1_rnd_out_i_cry_8));
XORCY un1_rnd_out_i_s_7(.LI(un1_rnd_out_i_axb_7),.CI(un1_rnd_out_i_cry_6),.O(un1_rnd_out_i[6:6]));
MUXCY_L un1_rnd_out_i_cry_7_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_6),.S(un1_rnd_out_i_axb_7),.LO(un1_rnd_out_i_cry_7));
XORCY un1_rnd_out_i_s_6(.LI(un1_rnd_out_i_axb_6),.CI(un1_rnd_out_i_cry_5),.O(un1_rnd_out_i[5:5]));
MUXCY_L un1_rnd_out_i_cry_6_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_5),.S(un1_rnd_out_i_axb_6),.LO(un1_rnd_out_i_cry_6));
XORCY un1_rnd_out_i_s_5(.LI(un1_rnd_out_i_axb_5),.CI(un1_rnd_out_i_cry_4),.O(un1_rnd_out_i[4:4]));
MUXCY_L un1_rnd_out_i_cry_5_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_4),.S(un1_rnd_out_i_axb_5),.LO(un1_rnd_out_i_cry_5));
XORCY un1_rnd_out_i_s_4(.LI(un1_rnd_out_i_axb_4),.CI(un1_rnd_out_i_cry_3),.O(un1_rnd_out_i[3:3]));
MUXCY_L un1_rnd_out_i_cry_4_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_3),.S(un1_rnd_out_i_axb_4),.LO(un1_rnd_out_i_cry_4));
XORCY un1_rnd_out_i_s_3(.LI(un1_rnd_out_i_axb_3),.CI(un1_rnd_out_i_cry_2),.O(un1_rnd_out_i[2:2]));
MUXCY_L un1_rnd_out_i_cry_3_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_2),.S(un1_rnd_out_i_axb_3),.LO(un1_rnd_out_i_cry_3));
XORCY un1_rnd_out_i_s_2(.LI(un1_rnd_out_i_axb_2),.CI(un1_rnd_out_i_cry_1),.O(un1_rnd_out_i[1:1]));
MUXCY_L un1_rnd_out_i_cry_2_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_1),.S(un1_rnd_out_i_axb_2),.LO(un1_rnd_out_i_cry_2));
XORCY un1_rnd_out_i_s_1(.LI(un1_rnd_out_i_axb_1),.CI(pre_out_i[7:7]),.O(un1_rnd_out_i[0:0]));
MUXCY_L un1_rnd_out_i_cry_1_cZ(.DI(GND),.CI(pre_out_i[7:7]),.S(un1_rnd_out_i_axb_1),.LO(un1_rnd_out_i_cry_1));
XORCY un2_rnd_out_r_s_12(.LI(un2_rnd_out_r_axb_12),.CI(un2_rnd_out_r_cry_11),.O(un2_rnd_out_r_s_12_2));
XORCY un2_rnd_out_r_s_11(.LI(un2_rnd_out_r_axb_11),.CI(un2_rnd_out_r_cry_10),.O(un2_rnd_out_r[10:10]));
MUXCY_L un2_rnd_out_r_cry_11_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_10),.S(un2_rnd_out_r_axb_11),.LO(un2_rnd_out_r_cry_11));
XORCY un2_rnd_out_r_s_10(.LI(un2_rnd_out_r_axb_10),.CI(un2_rnd_out_r_cry_9),.O(un2_rnd_out_r[9:9]));
MUXCY_L un2_rnd_out_r_cry_10_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_9),.S(un2_rnd_out_r_axb_10),.LO(un2_rnd_out_r_cry_10));
XORCY un2_rnd_out_r_s_9(.LI(un2_rnd_out_r_axb_9),.CI(un2_rnd_out_r_cry_8),.O(un2_rnd_out_r[8:8]));
MUXCY_L un2_rnd_out_r_cry_9_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_8),.S(un2_rnd_out_r_axb_9),.LO(un2_rnd_out_r_cry_9));
XORCY un2_rnd_out_r_s_8(.LI(un2_rnd_out_r_axb_8),.CI(un2_rnd_out_r_cry_7),.O(un2_rnd_out_r[7:7]));
MUXCY_L un2_rnd_out_r_cry_8_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_7),.S(un2_rnd_out_r_axb_8),.LO(un2_rnd_out_r_cry_8));
XORCY un2_rnd_out_r_s_7(.LI(un2_rnd_out_r_axb_7),.CI(un2_rnd_out_r_cry_6),.O(un2_rnd_out_r[6:6]));
MUXCY_L un2_rnd_out_r_cry_7_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_6),.S(un2_rnd_out_r_axb_7),.LO(un2_rnd_out_r_cry_7));
XORCY un2_rnd_out_r_s_6(.LI(un2_rnd_out_r_axb_6),.CI(un2_rnd_out_r_cry_5),.O(un2_rnd_out_r[5:5]));
MUXCY_L un2_rnd_out_r_cry_6_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_5),.S(un2_rnd_out_r_axb_6),.LO(un2_rnd_out_r_cry_6));
XORCY un2_rnd_out_r_s_5(.LI(un2_rnd_out_r_axb_5),.CI(un2_rnd_out_r_cry_4),.O(un2_rnd_out_r[4:4]));
MUXCY_L un2_rnd_out_r_cry_5_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_4),.S(un2_rnd_out_r_axb_5),.LO(un2_rnd_out_r_cry_5));
XORCY un2_rnd_out_r_s_4(.LI(un2_rnd_out_r_axb_4),.CI(un2_rnd_out_r_cry_3),.O(un2_rnd_out_r[3:3]));
MUXCY_L un2_rnd_out_r_cry_4_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_3),.S(un2_rnd_out_r_axb_4),.LO(un2_rnd_out_r_cry_4));
XORCY un2_rnd_out_r_s_3(.LI(un2_rnd_out_r_axb_3),.CI(un2_rnd_out_r_cry_2),.O(un2_rnd_out_r[2:2]));
MUXCY_L un2_rnd_out_r_cry_3_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_2),.S(un2_rnd_out_r_axb_3),.LO(un2_rnd_out_r_cry_3));
XORCY un2_rnd_out_r_s_2(.LI(un2_rnd_out_r_axb_2),.CI(un2_rnd_out_r_cry_1),.O(un2_rnd_out_r[1:1]));
MUXCY_L un2_rnd_out_r_cry_2_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_1),.S(un2_rnd_out_r_axb_2),.LO(un2_rnd_out_r_cry_2));
XORCY un2_rnd_out_r_s_1(.LI(un2_rnd_out_r_axb_1),.CI(pre_out_r[7:7]),.O(un2_rnd_out_r[0:0]));
MUXCY_L un2_rnd_out_r_cry_1_cZ(.DI(GND),.CI(pre_out_r[7:7]),.S(un2_rnd_out_r_axb_1),.LO(un2_rnd_out_r_cry_1));
FDS desc561(.Q(out_i_vec_mult_1[11:11]),.D(pos_out_i[11:11]),.C(clk),.S(un1_pos_out_i_0));
FDR desc562(.Q(out_i_vec_mult_1[10:10]),.D(pos_out_i_iv_i[10:10]),.C(clk),.R(un1_pos_out_i_0));
FDR desc563(.Q(out_i_vec_mult_1[9:9]),.D(pos_out_i_iv_i[9:9]),.C(clk),.R(un1_pos_out_i_0));
FDR desc564(.Q(out_i_vec_mult_1[8:8]),.D(pos_out_i_iv_i[8:8]),.C(clk),.R(un1_pos_out_i_0));
FDR desc565(.Q(out_i_vec_mult_1[7:7]),.D(pos_out_i_iv_i[7:7]),.C(clk),.R(un1_pos_out_i_0));
FDR desc566(.Q(out_i_vec_mult_1[6:6]),.D(pos_out_i_iv_i[6:6]),.C(clk),.R(un1_pos_out_i_0));
FDR desc567(.Q(out_i_vec_mult_1[5:5]),.D(pos_out_i_iv_i[5:5]),.C(clk),.R(un1_pos_out_i_0));
FDR desc568(.Q(out_i_vec_mult_1[4:4]),.D(pos_out_i_iv_i[4:4]),.C(clk),.R(un1_pos_out_i_0));
FDR desc569(.Q(out_i_vec_mult_1[3:3]),.D(pos_out_i_iv_i[3:3]),.C(clk),.R(un1_pos_out_i_0));
FDR desc570(.Q(out_i_vec_mult_1[2:2]),.D(pos_out_i_iv_i[2:2]),.C(clk),.R(un1_pos_out_i_0));
FDR desc571(.Q(out_i_vec_mult_1[1:1]),.D(pos_out_i_iv_i[1:1]),.C(clk),.R(un1_pos_out_i_0));
FDR desc572(.Q(out_i_vec_mult_1[0:0]),.D(pos_out_i_iv_i[0:0]),.C(clk),.R(un1_pos_out_i_0));
FDS desc573(.Q(out_r_vec_mult_1[11:11]),.D(pos_out_r[11:11]),.C(clk),.S(un1_pos_out_r_0));
FDR desc574(.Q(out_r_vec_mult_1[10:10]),.D(pos_out_r_iv_i[10:10]),.C(clk),.R(un1_pos_out_r_0));
FDR desc575(.Q(out_r_vec_mult_1[9:9]),.D(pos_out_r_iv_i[9:9]),.C(clk),.R(un1_pos_out_r_0));
FDR desc576(.Q(out_r_vec_mult_1[8:8]),.D(pos_out_r_iv_i[8:8]),.C(clk),.R(un1_pos_out_r_0));
FDR desc577(.Q(out_r_vec_mult_1[7:7]),.D(pos_out_r_iv_i[7:7]),.C(clk),.R(un1_pos_out_r_0));
FDR desc578(.Q(out_r_vec_mult_1[6:6]),.D(pos_out_r_iv_i[6:6]),.C(clk),.R(un1_pos_out_r_0));
FDR desc579(.Q(out_r_vec_mult_1[5:5]),.D(pos_out_r_iv_i[5:5]),.C(clk),.R(un1_pos_out_r_0));
FDR desc580(.Q(out_r_vec_mult_1[4:4]),.D(pos_out_r_iv_i[4:4]),.C(clk),.R(un1_pos_out_r_0));
FDR desc581(.Q(out_r_vec_mult_1[3:3]),.D(pos_out_r_iv_i[3:3]),.C(clk),.R(un1_pos_out_r_0));
FDR desc582(.Q(out_r_vec_mult_1[2:2]),.D(pos_out_r_iv_i[2:2]),.C(clk),.R(un1_pos_out_r_0));
FDR desc583(.Q(out_r_vec_mult_1[1:1]),.D(pos_out_r_iv_i[1:1]),.C(clk),.R(un1_pos_out_r_0));
FDR desc584(.Q(out_r_vec_mult_1[0:0]),.D(pos_out_r_iv_i[0:0]),.C(clk),.R(un1_pos_out_r_0));
mult_pipe_8_inj mult1(.mult1_out_23(mult1_out[23:23]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_20_0(P_uc_20_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_1(vec_out_r_AQ_1[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
mult_pipe_9_inj mult2(.mult2_out_23(mult2_out[23:23]),.vec_out_i_AQ_1(vec_out_i_AQ_1[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_10_inj mult3(.mult3_out_23(mult3_out[23:23]),.vec_out_r_AQ_1(vec_out_r_AQ_1[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_11_inj mult4(.mult4_out_23(mult4_out[23:23]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_23_0(P_uc_23_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_i_AQ_1(vec_out_i_AQ_1[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
add_subZ2_2_inj sub(.pre_out_r(pre_out_r[23:7]),.vec_out_i_AQ_1(vec_out_i_AQ_1[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_20_0(P_uc_20_0[47:24]),.PATTERNDETECT_2(PATTERNDETECT_2),.clk(clk));
add_subZ1_2_inj add(.pre_out_i(pre_out_i[23:7]),.vec_out_r_AQ_1(vec_out_r_AQ_1[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_23_0(P_uc_23_0[47:24]),.PATTERNDETECT_1(PATTERNDETECT_1),.clk(clk));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
endmodule
module desc591_inj (out_i_vec_mult_0,out_r_vec_mult_0,out_inner_prod_r,vec_out_r_AQ_0,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,vec_out_i_AQ_0,out_inner_prod_i,in_b_i_reg,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output [11:0] out_i_vec_mult_0 ;
output [11:0] out_r_vec_mult_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_0 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input [11:0] vec_out_i_AQ_0 ;
input [11:0] out_inner_prod_i ;
input [11:0] in_b_i_reg ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [23:7] pre_out_r ;
wire [23:7] pre_out_i ;
wire [23:23] mult2_out ;
wire [23:23] mult1_out ;
wire [23:23] mult3_out ;
wire [23:23] mult4_out ;
wire [11:11] pos_out_r ;
wire [11:11] pos_out_i ;
wire [10:0] un1_rnd_out_i ;
wire [10:0] pos_out_i_iv_i ;
wire [10:0] un2_rnd_out_r ;
wire [10:0] pos_out_r_iv_i ;
wire [23:0] mult1_out_0 ;
wire [47:24] P_uc_16_0 ;
wire [23:0] mult4_out_0 ;
wire [47:24] P_uc_19_0 ;
wire un2_rnd_out_r_axb_1 ;
wire un2_rnd_out_r_axb_2 ;
wire un2_rnd_out_r_axb_3 ;
wire un2_rnd_out_r_axb_4 ;
wire un2_rnd_out_r_axb_5 ;
wire un2_rnd_out_r_axb_6 ;
wire un2_rnd_out_r_axb_7 ;
wire un2_rnd_out_r_axb_8 ;
wire un2_rnd_out_r_axb_9 ;
wire un2_rnd_out_r_axb_10 ;
wire un2_rnd_out_r_axb_11 ;
wire un1_rnd_out_i_axb_1 ;
wire un1_rnd_out_i_axb_2 ;
wire un1_rnd_out_i_axb_3 ;
wire un1_rnd_out_i_axb_4 ;
wire un1_rnd_out_i_axb_5 ;
wire un1_rnd_out_i_axb_6 ;
wire un1_rnd_out_i_axb_7 ;
wire un1_rnd_out_i_axb_8 ;
wire un1_rnd_out_i_axb_9 ;
wire un1_rnd_out_i_axb_10 ;
wire un1_rnd_out_i_axb_11 ;
wire un1_rnd_out_i_axb_12 ;
wire un2_rnd_out_r_axb_12 ;
wire un4_rnd_sat_out_i_3 ;
wire un5_rnd_sat_out_r_3 ;
wire un1_pos_out_r_1 ;
wire un1_pos_out_i_1 ;
wire PATTERNDETECT_0 ;
wire un2_rnd_out_r_s_12_0 ;
wire PATTERNDETECT ;
wire un1_rnd_out_i_s_12_0 ;
wire un1_rnd_out_i_cry_11 ;
wire un1_rnd_out_i_cry_10 ;
wire GND ;
wire un1_rnd_out_i_cry_9 ;
wire un1_rnd_out_i_cry_8 ;
wire un1_rnd_out_i_cry_7 ;
wire un1_rnd_out_i_cry_6 ;
wire un1_rnd_out_i_cry_5 ;
wire un1_rnd_out_i_cry_4 ;
wire un1_rnd_out_i_cry_3 ;
wire un1_rnd_out_i_cry_2 ;
wire un1_rnd_out_i_cry_1 ;
wire un2_rnd_out_r_cry_11 ;
wire un2_rnd_out_r_cry_10 ;
wire un2_rnd_out_r_cry_9 ;
wire un2_rnd_out_r_cry_8 ;
wire un2_rnd_out_r_cry_7 ;
wire un2_rnd_out_r_cry_6 ;
wire un2_rnd_out_r_cry_5 ;
wire un2_rnd_out_r_cry_4 ;
wire un2_rnd_out_r_cry_3 ;
wire un2_rnd_out_r_cry_2 ;
wire un2_rnd_out_r_cry_1 ;
wire VCC ;
// instances
LUT1 un2_rnd_out_r_axb_1_cZ(.I0(pre_out_r[8:8]),.O(un2_rnd_out_r_axb_1));
defparam un2_rnd_out_r_axb_1_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_2_cZ(.I0(pre_out_r[9:9]),.O(un2_rnd_out_r_axb_2));
defparam un2_rnd_out_r_axb_2_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_3_cZ(.I0(pre_out_r[10:10]),.O(un2_rnd_out_r_axb_3));
defparam un2_rnd_out_r_axb_3_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_4_cZ(.I0(pre_out_r[11:11]),.O(un2_rnd_out_r_axb_4));
defparam un2_rnd_out_r_axb_4_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_5_cZ(.I0(pre_out_r[12:12]),.O(un2_rnd_out_r_axb_5));
defparam un2_rnd_out_r_axb_5_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_6_cZ(.I0(pre_out_r[13:13]),.O(un2_rnd_out_r_axb_6));
defparam un2_rnd_out_r_axb_6_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_7_cZ(.I0(pre_out_r[14:14]),.O(un2_rnd_out_r_axb_7));
defparam un2_rnd_out_r_axb_7_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_8_cZ(.I0(pre_out_r[15:15]),.O(un2_rnd_out_r_axb_8));
defparam un2_rnd_out_r_axb_8_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_9_cZ(.I0(pre_out_r[16:16]),.O(un2_rnd_out_r_axb_9));
defparam un2_rnd_out_r_axb_9_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_10_cZ(.I0(pre_out_r[17:17]),.O(un2_rnd_out_r_axb_10));
defparam un2_rnd_out_r_axb_10_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_11_cZ(.I0(pre_out_r[18:18]),.O(un2_rnd_out_r_axb_11));
defparam un2_rnd_out_r_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_1_cZ(.I0(pre_out_i[8:8]),.O(un1_rnd_out_i_axb_1));
defparam un1_rnd_out_i_axb_1_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_2_cZ(.I0(pre_out_i[9:9]),.O(un1_rnd_out_i_axb_2));
defparam un1_rnd_out_i_axb_2_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_3_cZ(.I0(pre_out_i[10:10]),.O(un1_rnd_out_i_axb_3));
defparam un1_rnd_out_i_axb_3_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_4_cZ(.I0(pre_out_i[11:11]),.O(un1_rnd_out_i_axb_4));
defparam un1_rnd_out_i_axb_4_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_5_cZ(.I0(pre_out_i[12:12]),.O(un1_rnd_out_i_axb_5));
defparam un1_rnd_out_i_axb_5_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_6_cZ(.I0(pre_out_i[13:13]),.O(un1_rnd_out_i_axb_6));
defparam un1_rnd_out_i_axb_6_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_7_cZ(.I0(pre_out_i[14:14]),.O(un1_rnd_out_i_axb_7));
defparam un1_rnd_out_i_axb_7_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_8_cZ(.I0(pre_out_i[15:15]),.O(un1_rnd_out_i_axb_8));
defparam un1_rnd_out_i_axb_8_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_9_cZ(.I0(pre_out_i[16:16]),.O(un1_rnd_out_i_axb_9));
defparam un1_rnd_out_i_axb_9_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_10_cZ(.I0(pre_out_i[17:17]),.O(un1_rnd_out_i_axb_10));
defparam un1_rnd_out_i_axb_10_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_11_cZ(.I0(pre_out_i[18:18]),.O(un1_rnd_out_i_axb_11));
defparam un1_rnd_out_i_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_12_cZ(.I0(pre_out_i[19:19]),.O(un1_rnd_out_i_axb_12));
defparam un1_rnd_out_i_axb_12_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_12_cZ(.I0(pre_out_r[19:19]),.O(un2_rnd_out_r_axb_12));
defparam un2_rnd_out_r_axb_12_cZ.INIT=2'h2;
LUT4 un4_rnd_sat_out_i_3_cZ(.I0(pre_out_i[20:20]),.I1(pre_out_i[21:21]),.I2(pre_out_i[22:22]),.I3(pre_out_i[19:19]),.O(un4_rnd_sat_out_i_3));
defparam un4_rnd_sat_out_i_3_cZ.INIT=16'h8000;
LUT4 un5_rnd_sat_out_r_3_cZ(.I0(pre_out_r[20:20]),.I1(pre_out_r[21:21]),.I2(pre_out_r[22:22]),.I3(pre_out_r[19:19]),.O(un5_rnd_sat_out_r_3));
defparam un5_rnd_sat_out_r_3_cZ.INIT=16'h8000;
LUT3 un1_pos_out_r(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.O(un1_pos_out_r_1));
defparam un1_pos_out_r.INIT=8'h04;
LUT3 un1_pos_out_i(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.O(un1_pos_out_i_1));
defparam un1_pos_out_i.INIT=8'h08;
LUT6_L desc592(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r_s_12_0),.LO(pos_out_r[11:11]));
defparam desc592.INIT=64'hDBD0DBD00000D0D0;
LUT6_L desc593(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i_s_12_0),.LO(pos_out_i[11:11]));
defparam desc593.INIT=64'hE7E0E7E00000E0E0;
LUT6_L desc594(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[10:10]),.LO(pos_out_i_iv_i[10:10]));
defparam desc594.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc595(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[9:9]),.LO(pos_out_i_iv_i[9:9]));
defparam desc595.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc596(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[8:8]),.LO(pos_out_i_iv_i[8:8]));
defparam desc596.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc597(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[7:7]),.LO(pos_out_i_iv_i[7:7]));
defparam desc597.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc598(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[6:6]),.LO(pos_out_i_iv_i[6:6]));
defparam desc598.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc599(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[5:5]),.LO(pos_out_i_iv_i[5:5]));
defparam desc599.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc600(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[4:4]),.LO(pos_out_i_iv_i[4:4]));
defparam desc600.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc601(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[3:3]),.LO(pos_out_i_iv_i[3:3]));
defparam desc601.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc602(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[2:2]),.LO(pos_out_i_iv_i[2:2]));
defparam desc602.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc603(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[1:1]),.LO(pos_out_i_iv_i[1:1]));
defparam desc603.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc604(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(un1_rnd_out_i[0:0]),.I4(PATTERNDETECT),.I5(un4_rnd_sat_out_i_3),.LO(pos_out_i_iv_i[0:0]));
defparam desc604.INIT=64'hFF18FF1F1F181F1F;
LUT6_L desc605(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[10:10]),.LO(pos_out_r_iv_i[10:10]));
defparam desc605.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc606(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[9:9]),.LO(pos_out_r_iv_i[9:9]));
defparam desc606.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc607(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[8:8]),.LO(pos_out_r_iv_i[8:8]));
defparam desc607.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc608(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[7:7]),.LO(pos_out_r_iv_i[7:7]));
defparam desc608.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc609(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[6:6]),.LO(pos_out_r_iv_i[6:6]));
defparam desc609.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc610(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[5:5]),.LO(pos_out_r_iv_i[5:5]));
defparam desc610.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc611(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[4:4]),.LO(pos_out_r_iv_i[4:4]));
defparam desc611.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc612(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[3:3]),.LO(pos_out_r_iv_i[3:3]));
defparam desc612.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc613(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[2:2]),.LO(pos_out_r_iv_i[2:2]));
defparam desc613.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc614(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_0),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[1:1]),.LO(pos_out_r_iv_i[1:1]));
defparam desc614.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc615(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(un2_rnd_out_r[0:0]),.I4(PATTERNDETECT_0),.I5(un5_rnd_sat_out_r_3),.LO(pos_out_r_iv_i[0:0]));
defparam desc615.INIT=64'hFF24FF2F2F242F2F;
XORCY un1_rnd_out_i_s_12(.LI(un1_rnd_out_i_axb_12),.CI(un1_rnd_out_i_cry_11),.O(un1_rnd_out_i_s_12_0));
XORCY un1_rnd_out_i_s_11(.LI(un1_rnd_out_i_axb_11),.CI(un1_rnd_out_i_cry_10),.O(un1_rnd_out_i[10:10]));
MUXCY_L un1_rnd_out_i_cry_11_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_10),.S(un1_rnd_out_i_axb_11),.LO(un1_rnd_out_i_cry_11));
XORCY un1_rnd_out_i_s_10(.LI(un1_rnd_out_i_axb_10),.CI(un1_rnd_out_i_cry_9),.O(un1_rnd_out_i[9:9]));
MUXCY_L un1_rnd_out_i_cry_10_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_9),.S(un1_rnd_out_i_axb_10),.LO(un1_rnd_out_i_cry_10));
XORCY un1_rnd_out_i_s_9(.LI(un1_rnd_out_i_axb_9),.CI(un1_rnd_out_i_cry_8),.O(un1_rnd_out_i[8:8]));
MUXCY_L un1_rnd_out_i_cry_9_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_8),.S(un1_rnd_out_i_axb_9),.LO(un1_rnd_out_i_cry_9));
XORCY un1_rnd_out_i_s_8(.LI(un1_rnd_out_i_axb_8),.CI(un1_rnd_out_i_cry_7),.O(un1_rnd_out_i[7:7]));
MUXCY_L un1_rnd_out_i_cry_8_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_7),.S(un1_rnd_out_i_axb_8),.LO(un1_rnd_out_i_cry_8));
XORCY un1_rnd_out_i_s_7(.LI(un1_rnd_out_i_axb_7),.CI(un1_rnd_out_i_cry_6),.O(un1_rnd_out_i[6:6]));
MUXCY_L un1_rnd_out_i_cry_7_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_6),.S(un1_rnd_out_i_axb_7),.LO(un1_rnd_out_i_cry_7));
XORCY un1_rnd_out_i_s_6(.LI(un1_rnd_out_i_axb_6),.CI(un1_rnd_out_i_cry_5),.O(un1_rnd_out_i[5:5]));
MUXCY_L un1_rnd_out_i_cry_6_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_5),.S(un1_rnd_out_i_axb_6),.LO(un1_rnd_out_i_cry_6));
XORCY un1_rnd_out_i_s_5(.LI(un1_rnd_out_i_axb_5),.CI(un1_rnd_out_i_cry_4),.O(un1_rnd_out_i[4:4]));
MUXCY_L un1_rnd_out_i_cry_5_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_4),.S(un1_rnd_out_i_axb_5),.LO(un1_rnd_out_i_cry_5));
XORCY un1_rnd_out_i_s_4(.LI(un1_rnd_out_i_axb_4),.CI(un1_rnd_out_i_cry_3),.O(un1_rnd_out_i[3:3]));
MUXCY_L un1_rnd_out_i_cry_4_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_3),.S(un1_rnd_out_i_axb_4),.LO(un1_rnd_out_i_cry_4));
XORCY un1_rnd_out_i_s_3(.LI(un1_rnd_out_i_axb_3),.CI(un1_rnd_out_i_cry_2),.O(un1_rnd_out_i[2:2]));
MUXCY_L un1_rnd_out_i_cry_3_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_2),.S(un1_rnd_out_i_axb_3),.LO(un1_rnd_out_i_cry_3));
XORCY un1_rnd_out_i_s_2(.LI(un1_rnd_out_i_axb_2),.CI(un1_rnd_out_i_cry_1),.O(un1_rnd_out_i[1:1]));
MUXCY_L un1_rnd_out_i_cry_2_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_1),.S(un1_rnd_out_i_axb_2),.LO(un1_rnd_out_i_cry_2));
XORCY un1_rnd_out_i_s_1(.LI(un1_rnd_out_i_axb_1),.CI(pre_out_i[7:7]),.O(un1_rnd_out_i[0:0]));
MUXCY_L un1_rnd_out_i_cry_1_cZ(.DI(GND),.CI(pre_out_i[7:7]),.S(un1_rnd_out_i_axb_1),.LO(un1_rnd_out_i_cry_1));
XORCY un2_rnd_out_r_s_12(.LI(un2_rnd_out_r_axb_12),.CI(un2_rnd_out_r_cry_11),.O(un2_rnd_out_r_s_12_0));
XORCY un2_rnd_out_r_s_11(.LI(un2_rnd_out_r_axb_11),.CI(un2_rnd_out_r_cry_10),.O(un2_rnd_out_r[10:10]));
MUXCY_L un2_rnd_out_r_cry_11_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_10),.S(un2_rnd_out_r_axb_11),.LO(un2_rnd_out_r_cry_11));
XORCY un2_rnd_out_r_s_10(.LI(un2_rnd_out_r_axb_10),.CI(un2_rnd_out_r_cry_9),.O(un2_rnd_out_r[9:9]));
MUXCY_L un2_rnd_out_r_cry_10_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_9),.S(un2_rnd_out_r_axb_10),.LO(un2_rnd_out_r_cry_10));
XORCY un2_rnd_out_r_s_9(.LI(un2_rnd_out_r_axb_9),.CI(un2_rnd_out_r_cry_8),.O(un2_rnd_out_r[8:8]));
MUXCY_L un2_rnd_out_r_cry_9_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_8),.S(un2_rnd_out_r_axb_9),.LO(un2_rnd_out_r_cry_9));
XORCY un2_rnd_out_r_s_8(.LI(un2_rnd_out_r_axb_8),.CI(un2_rnd_out_r_cry_7),.O(un2_rnd_out_r[7:7]));
MUXCY_L un2_rnd_out_r_cry_8_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_7),.S(un2_rnd_out_r_axb_8),.LO(un2_rnd_out_r_cry_8));
XORCY un2_rnd_out_r_s_7(.LI(un2_rnd_out_r_axb_7),.CI(un2_rnd_out_r_cry_6),.O(un2_rnd_out_r[6:6]));
MUXCY_L un2_rnd_out_r_cry_7_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_6),.S(un2_rnd_out_r_axb_7),.LO(un2_rnd_out_r_cry_7));
XORCY un2_rnd_out_r_s_6(.LI(un2_rnd_out_r_axb_6),.CI(un2_rnd_out_r_cry_5),.O(un2_rnd_out_r[5:5]));
MUXCY_L un2_rnd_out_r_cry_6_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_5),.S(un2_rnd_out_r_axb_6),.LO(un2_rnd_out_r_cry_6));
XORCY un2_rnd_out_r_s_5(.LI(un2_rnd_out_r_axb_5),.CI(un2_rnd_out_r_cry_4),.O(un2_rnd_out_r[4:4]));
MUXCY_L un2_rnd_out_r_cry_5_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_4),.S(un2_rnd_out_r_axb_5),.LO(un2_rnd_out_r_cry_5));
XORCY un2_rnd_out_r_s_4(.LI(un2_rnd_out_r_axb_4),.CI(un2_rnd_out_r_cry_3),.O(un2_rnd_out_r[3:3]));
MUXCY_L un2_rnd_out_r_cry_4_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_3),.S(un2_rnd_out_r_axb_4),.LO(un2_rnd_out_r_cry_4));
XORCY un2_rnd_out_r_s_3(.LI(un2_rnd_out_r_axb_3),.CI(un2_rnd_out_r_cry_2),.O(un2_rnd_out_r[2:2]));
MUXCY_L un2_rnd_out_r_cry_3_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_2),.S(un2_rnd_out_r_axb_3),.LO(un2_rnd_out_r_cry_3));
XORCY un2_rnd_out_r_s_2(.LI(un2_rnd_out_r_axb_2),.CI(un2_rnd_out_r_cry_1),.O(un2_rnd_out_r[1:1]));
MUXCY_L un2_rnd_out_r_cry_2_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_1),.S(un2_rnd_out_r_axb_2),.LO(un2_rnd_out_r_cry_2));
XORCY un2_rnd_out_r_s_1(.LI(un2_rnd_out_r_axb_1),.CI(pre_out_r[7:7]),.O(un2_rnd_out_r[0:0]));
MUXCY_L un2_rnd_out_r_cry_1_cZ(.DI(GND),.CI(pre_out_r[7:7]),.S(un2_rnd_out_r_axb_1),.LO(un2_rnd_out_r_cry_1));
FDS desc616(.Q(out_i_vec_mult_0[11:11]),.D(pos_out_i[11:11]),.C(clk),.S(un1_pos_out_i_1));
FDR desc617(.Q(out_i_vec_mult_0[10:10]),.D(pos_out_i_iv_i[10:10]),.C(clk),.R(un1_pos_out_i_1));
FDR desc618(.Q(out_i_vec_mult_0[9:9]),.D(pos_out_i_iv_i[9:9]),.C(clk),.R(un1_pos_out_i_1));
FDR desc619(.Q(out_i_vec_mult_0[8:8]),.D(pos_out_i_iv_i[8:8]),.C(clk),.R(un1_pos_out_i_1));
FDR desc620(.Q(out_i_vec_mult_0[7:7]),.D(pos_out_i_iv_i[7:7]),.C(clk),.R(un1_pos_out_i_1));
FDR desc621(.Q(out_i_vec_mult_0[6:6]),.D(pos_out_i_iv_i[6:6]),.C(clk),.R(un1_pos_out_i_1));
FDR desc622(.Q(out_i_vec_mult_0[5:5]),.D(pos_out_i_iv_i[5:5]),.C(clk),.R(un1_pos_out_i_1));
FDR desc623(.Q(out_i_vec_mult_0[4:4]),.D(pos_out_i_iv_i[4:4]),.C(clk),.R(un1_pos_out_i_1));
FDR desc624(.Q(out_i_vec_mult_0[3:3]),.D(pos_out_i_iv_i[3:3]),.C(clk),.R(un1_pos_out_i_1));
FDR desc625(.Q(out_i_vec_mult_0[2:2]),.D(pos_out_i_iv_i[2:2]),.C(clk),.R(un1_pos_out_i_1));
FDR desc626(.Q(out_i_vec_mult_0[1:1]),.D(pos_out_i_iv_i[1:1]),.C(clk),.R(un1_pos_out_i_1));
FDR desc627(.Q(out_i_vec_mult_0[0:0]),.D(pos_out_i_iv_i[0:0]),.C(clk),.R(un1_pos_out_i_1));
FDS desc628(.Q(out_r_vec_mult_0[11:11]),.D(pos_out_r[11:11]),.C(clk),.S(un1_pos_out_r_1));
FDR desc629(.Q(out_r_vec_mult_0[10:10]),.D(pos_out_r_iv_i[10:10]),.C(clk),.R(un1_pos_out_r_1));
FDR desc630(.Q(out_r_vec_mult_0[9:9]),.D(pos_out_r_iv_i[9:9]),.C(clk),.R(un1_pos_out_r_1));
FDR desc631(.Q(out_r_vec_mult_0[8:8]),.D(pos_out_r_iv_i[8:8]),.C(clk),.R(un1_pos_out_r_1));
FDR desc632(.Q(out_r_vec_mult_0[7:7]),.D(pos_out_r_iv_i[7:7]),.C(clk),.R(un1_pos_out_r_1));
FDR desc633(.Q(out_r_vec_mult_0[6:6]),.D(pos_out_r_iv_i[6:6]),.C(clk),.R(un1_pos_out_r_1));
FDR desc634(.Q(out_r_vec_mult_0[5:5]),.D(pos_out_r_iv_i[5:5]),.C(clk),.R(un1_pos_out_r_1));
FDR desc635(.Q(out_r_vec_mult_0[4:4]),.D(pos_out_r_iv_i[4:4]),.C(clk),.R(un1_pos_out_r_1));
FDR desc636(.Q(out_r_vec_mult_0[3:3]),.D(pos_out_r_iv_i[3:3]),.C(clk),.R(un1_pos_out_r_1));
FDR desc637(.Q(out_r_vec_mult_0[2:2]),.D(pos_out_r_iv_i[2:2]),.C(clk),.R(un1_pos_out_r_1));
FDR desc638(.Q(out_r_vec_mult_0[1:1]),.D(pos_out_r_iv_i[1:1]),.C(clk),.R(un1_pos_out_r_1));
FDR desc639(.Q(out_r_vec_mult_0[0:0]),.D(pos_out_r_iv_i[0:0]),.C(clk),.R(un1_pos_out_r_1));
mult_pipe_12_inj mult1(.mult1_out_23(mult1_out[23:23]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_16_0(P_uc_16_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_0(vec_out_r_AQ_0[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
mult_pipe_13_inj mult2(.mult2_out_23(mult2_out[23:23]),.vec_out_i_AQ_0(vec_out_i_AQ_0[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_14_inj mult3(.mult3_out_23(mult3_out[23:23]),.vec_out_r_AQ_0(vec_out_r_AQ_0[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_15_inj mult4(.mult4_out_23(mult4_out[23:23]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_19_0(P_uc_19_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_i_AQ_0(vec_out_i_AQ_0[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
add_subZ2_3_inj sub(.pre_out_r(pre_out_r[23:7]),.vec_out_i_AQ_0(vec_out_i_AQ_0[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_16_0(P_uc_16_0[47:24]),.PATTERNDETECT_0(PATTERNDETECT_0),.clk(clk));
add_subZ1_3_inj add(.pre_out_i(pre_out_i[23:7]),.vec_out_r_AQ_0(vec_out_r_AQ_0[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_19_0(P_uc_19_0[47:24]),.PATTERNDETECT(PATTERNDETECT),.clk(clk));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
endmodule
module desc646_inj (out_i_vec_mult_3,out_r_vec_mult_3,out_inner_prod_r,vec_out_r_AQ_3,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,vec_out_i_AQ_3,out_inner_prod_i,in_b_i_reg,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output [11:0] out_i_vec_mult_3 ;
output [11:0] out_r_vec_mult_3 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_3 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input [11:0] vec_out_i_AQ_3 ;
input [11:0] out_inner_prod_i ;
input [11:0] in_b_i_reg ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [23:7] pre_out_r ;
wire [23:7] pre_out_i ;
wire [23:23] mult2_out ;
wire [23:23] mult1_out ;
wire [23:23] mult3_out ;
wire [23:23] mult4_out ;
wire [11:11] pos_out_r ;
wire [11:11] pos_out_i ;
wire [10:0] un1_rnd_out_i ;
wire [10:0] pos_out_i_iv_i ;
wire [10:0] un2_rnd_out_r ;
wire [10:0] pos_out_r_iv_i ;
wire [23:0] mult1_out_0 ;
wire [47:24] P_uc_28_0 ;
wire [23:0] mult4_out_0 ;
wire [47:24] P_uc_31_0 ;
wire un2_rnd_out_r_axb_1 ;
wire un2_rnd_out_r_axb_2 ;
wire un2_rnd_out_r_axb_3 ;
wire un2_rnd_out_r_axb_4 ;
wire un2_rnd_out_r_axb_5 ;
wire un2_rnd_out_r_axb_6 ;
wire un2_rnd_out_r_axb_7 ;
wire un2_rnd_out_r_axb_8 ;
wire un2_rnd_out_r_axb_9 ;
wire un2_rnd_out_r_axb_10 ;
wire un2_rnd_out_r_axb_11 ;
wire un1_rnd_out_i_axb_1 ;
wire un1_rnd_out_i_axb_2 ;
wire un1_rnd_out_i_axb_3 ;
wire un1_rnd_out_i_axb_4 ;
wire un1_rnd_out_i_axb_5 ;
wire un1_rnd_out_i_axb_6 ;
wire un1_rnd_out_i_axb_7 ;
wire un1_rnd_out_i_axb_8 ;
wire un1_rnd_out_i_axb_9 ;
wire un1_rnd_out_i_axb_10 ;
wire un1_rnd_out_i_axb_11 ;
wire un1_rnd_out_i_axb_12 ;
wire un2_rnd_out_r_axb_12 ;
wire un4_rnd_sat_out_i_3 ;
wire un5_rnd_sat_out_r_3 ;
wire un1_pos_out_r_2 ;
wire un1_pos_out_i_2 ;
wire PATTERNDETECT_6 ;
wire un2_rnd_out_r_s_12_1 ;
wire PATTERNDETECT_5 ;
wire un1_rnd_out_i_s_12_1 ;
wire un1_rnd_out_i_cry_11 ;
wire un1_rnd_out_i_cry_10 ;
wire GND ;
wire un1_rnd_out_i_cry_9 ;
wire un1_rnd_out_i_cry_8 ;
wire un1_rnd_out_i_cry_7 ;
wire un1_rnd_out_i_cry_6 ;
wire un1_rnd_out_i_cry_5 ;
wire un1_rnd_out_i_cry_4 ;
wire un1_rnd_out_i_cry_3 ;
wire un1_rnd_out_i_cry_2 ;
wire un1_rnd_out_i_cry_1 ;
wire un2_rnd_out_r_cry_11 ;
wire un2_rnd_out_r_cry_10 ;
wire un2_rnd_out_r_cry_9 ;
wire un2_rnd_out_r_cry_8 ;
wire un2_rnd_out_r_cry_7 ;
wire un2_rnd_out_r_cry_6 ;
wire un2_rnd_out_r_cry_5 ;
wire un2_rnd_out_r_cry_4 ;
wire un2_rnd_out_r_cry_3 ;
wire un2_rnd_out_r_cry_2 ;
wire un2_rnd_out_r_cry_1 ;
wire VCC ;
// instances
LUT1 un2_rnd_out_r_axb_1_cZ(.I0(pre_out_r[8:8]),.O(un2_rnd_out_r_axb_1));
defparam un2_rnd_out_r_axb_1_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_2_cZ(.I0(pre_out_r[9:9]),.O(un2_rnd_out_r_axb_2));
defparam un2_rnd_out_r_axb_2_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_3_cZ(.I0(pre_out_r[10:10]),.O(un2_rnd_out_r_axb_3));
defparam un2_rnd_out_r_axb_3_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_4_cZ(.I0(pre_out_r[11:11]),.O(un2_rnd_out_r_axb_4));
defparam un2_rnd_out_r_axb_4_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_5_cZ(.I0(pre_out_r[12:12]),.O(un2_rnd_out_r_axb_5));
defparam un2_rnd_out_r_axb_5_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_6_cZ(.I0(pre_out_r[13:13]),.O(un2_rnd_out_r_axb_6));
defparam un2_rnd_out_r_axb_6_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_7_cZ(.I0(pre_out_r[14:14]),.O(un2_rnd_out_r_axb_7));
defparam un2_rnd_out_r_axb_7_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_8_cZ(.I0(pre_out_r[15:15]),.O(un2_rnd_out_r_axb_8));
defparam un2_rnd_out_r_axb_8_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_9_cZ(.I0(pre_out_r[16:16]),.O(un2_rnd_out_r_axb_9));
defparam un2_rnd_out_r_axb_9_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_10_cZ(.I0(pre_out_r[17:17]),.O(un2_rnd_out_r_axb_10));
defparam un2_rnd_out_r_axb_10_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_11_cZ(.I0(pre_out_r[18:18]),.O(un2_rnd_out_r_axb_11));
defparam un2_rnd_out_r_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_1_cZ(.I0(pre_out_i[8:8]),.O(un1_rnd_out_i_axb_1));
defparam un1_rnd_out_i_axb_1_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_2_cZ(.I0(pre_out_i[9:9]),.O(un1_rnd_out_i_axb_2));
defparam un1_rnd_out_i_axb_2_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_3_cZ(.I0(pre_out_i[10:10]),.O(un1_rnd_out_i_axb_3));
defparam un1_rnd_out_i_axb_3_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_4_cZ(.I0(pre_out_i[11:11]),.O(un1_rnd_out_i_axb_4));
defparam un1_rnd_out_i_axb_4_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_5_cZ(.I0(pre_out_i[12:12]),.O(un1_rnd_out_i_axb_5));
defparam un1_rnd_out_i_axb_5_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_6_cZ(.I0(pre_out_i[13:13]),.O(un1_rnd_out_i_axb_6));
defparam un1_rnd_out_i_axb_6_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_7_cZ(.I0(pre_out_i[14:14]),.O(un1_rnd_out_i_axb_7));
defparam un1_rnd_out_i_axb_7_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_8_cZ(.I0(pre_out_i[15:15]),.O(un1_rnd_out_i_axb_8));
defparam un1_rnd_out_i_axb_8_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_9_cZ(.I0(pre_out_i[16:16]),.O(un1_rnd_out_i_axb_9));
defparam un1_rnd_out_i_axb_9_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_10_cZ(.I0(pre_out_i[17:17]),.O(un1_rnd_out_i_axb_10));
defparam un1_rnd_out_i_axb_10_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_11_cZ(.I0(pre_out_i[18:18]),.O(un1_rnd_out_i_axb_11));
defparam un1_rnd_out_i_axb_11_cZ.INIT=2'h2;
LUT1 un1_rnd_out_i_axb_12_cZ(.I0(pre_out_i[19:19]),.O(un1_rnd_out_i_axb_12));
defparam un1_rnd_out_i_axb_12_cZ.INIT=2'h2;
LUT1 un2_rnd_out_r_axb_12_cZ(.I0(pre_out_r[19:19]),.O(un2_rnd_out_r_axb_12));
defparam un2_rnd_out_r_axb_12_cZ.INIT=2'h2;
LUT4 un4_rnd_sat_out_i_3_cZ(.I0(pre_out_i[20:20]),.I1(pre_out_i[21:21]),.I2(pre_out_i[22:22]),.I3(pre_out_i[19:19]),.O(un4_rnd_sat_out_i_3));
defparam un4_rnd_sat_out_i_3_cZ.INIT=16'h8000;
LUT4 un5_rnd_sat_out_r_3_cZ(.I0(pre_out_r[20:20]),.I1(pre_out_r[21:21]),.I2(pre_out_r[22:22]),.I3(pre_out_r[19:19]),.O(un5_rnd_sat_out_r_3));
defparam un5_rnd_sat_out_r_3_cZ.INIT=16'h8000;
LUT3 un1_pos_out_r(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.O(un1_pos_out_r_2));
defparam un1_pos_out_r.INIT=8'h04;
LUT3 un1_pos_out_i(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.O(un1_pos_out_i_2));
defparam un1_pos_out_i.INIT=8'h08;
LUT6_L desc647(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r_s_12_1),.LO(pos_out_r[11:11]));
defparam desc647.INIT=64'hDBD0DBD00000D0D0;
LUT6_L desc648(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i_s_12_1),.LO(pos_out_i[11:11]));
defparam desc648.INIT=64'hE7E0E7E00000E0E0;
LUT6_L desc649(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[10:10]),.LO(pos_out_i_iv_i[10:10]));
defparam desc649.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc650(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[9:9]),.LO(pos_out_i_iv_i[9:9]));
defparam desc650.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc651(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[8:8]),.LO(pos_out_i_iv_i[8:8]));
defparam desc651.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc652(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[7:7]),.LO(pos_out_i_iv_i[7:7]));
defparam desc652.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc653(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[6:6]),.LO(pos_out_i_iv_i[6:6]));
defparam desc653.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc654(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[5:5]),.LO(pos_out_i_iv_i[5:5]));
defparam desc654.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc655(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[4:4]),.LO(pos_out_i_iv_i[4:4]));
defparam desc655.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc656(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[3:3]),.LO(pos_out_i_iv_i[3:3]));
defparam desc656.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc657(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[2:2]),.LO(pos_out_i_iv_i[2:2]));
defparam desc657.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc658(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(PATTERNDETECT_5),.I4(un4_rnd_sat_out_i_3),.I5(un1_rnd_out_i[1:1]),.LO(pos_out_i_iv_i[1:1]));
defparam desc658.INIT=64'hFFFF1F1F181F181F;
LUT6_L desc659(.I0(mult3_out[23:23]),.I1(mult4_out[23:23]),.I2(pre_out_i[23:23]),.I3(un1_rnd_out_i[0:0]),.I4(PATTERNDETECT_5),.I5(un4_rnd_sat_out_i_3),.LO(pos_out_i_iv_i[0:0]));
defparam desc659.INIT=64'hFF18FF1F1F181F1F;
LUT6_L desc660(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[10:10]),.LO(pos_out_r_iv_i[10:10]));
defparam desc660.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc661(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[9:9]),.LO(pos_out_r_iv_i[9:9]));
defparam desc661.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc662(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[8:8]),.LO(pos_out_r_iv_i[8:8]));
defparam desc662.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc663(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[7:7]),.LO(pos_out_r_iv_i[7:7]));
defparam desc663.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc664(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[6:6]),.LO(pos_out_r_iv_i[6:6]));
defparam desc664.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc665(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[5:5]),.LO(pos_out_r_iv_i[5:5]));
defparam desc665.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc666(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[4:4]),.LO(pos_out_r_iv_i[4:4]));
defparam desc666.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc667(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[3:3]),.LO(pos_out_r_iv_i[3:3]));
defparam desc667.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc668(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[2:2]),.LO(pos_out_r_iv_i[2:2]));
defparam desc668.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc669(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(PATTERNDETECT_6),.I4(un5_rnd_sat_out_r_3),.I5(un2_rnd_out_r[1:1]),.LO(pos_out_r_iv_i[1:1]));
defparam desc669.INIT=64'hFFFF2F2F242F242F;
LUT6_L desc670(.I0(mult2_out[23:23]),.I1(mult1_out[23:23]),.I2(pre_out_r[23:23]),.I3(un2_rnd_out_r[0:0]),.I4(PATTERNDETECT_6),.I5(un5_rnd_sat_out_r_3),.LO(pos_out_r_iv_i[0:0]));
defparam desc670.INIT=64'hFF24FF2F2F242F2F;
XORCY un1_rnd_out_i_s_12(.LI(un1_rnd_out_i_axb_12),.CI(un1_rnd_out_i_cry_11),.O(un1_rnd_out_i_s_12_1));
XORCY un1_rnd_out_i_s_11(.LI(un1_rnd_out_i_axb_11),.CI(un1_rnd_out_i_cry_10),.O(un1_rnd_out_i[10:10]));
MUXCY_L un1_rnd_out_i_cry_11_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_10),.S(un1_rnd_out_i_axb_11),.LO(un1_rnd_out_i_cry_11));
XORCY un1_rnd_out_i_s_10(.LI(un1_rnd_out_i_axb_10),.CI(un1_rnd_out_i_cry_9),.O(un1_rnd_out_i[9:9]));
MUXCY_L un1_rnd_out_i_cry_10_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_9),.S(un1_rnd_out_i_axb_10),.LO(un1_rnd_out_i_cry_10));
XORCY un1_rnd_out_i_s_9(.LI(un1_rnd_out_i_axb_9),.CI(un1_rnd_out_i_cry_8),.O(un1_rnd_out_i[8:8]));
MUXCY_L un1_rnd_out_i_cry_9_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_8),.S(un1_rnd_out_i_axb_9),.LO(un1_rnd_out_i_cry_9));
XORCY un1_rnd_out_i_s_8(.LI(un1_rnd_out_i_axb_8),.CI(un1_rnd_out_i_cry_7),.O(un1_rnd_out_i[7:7]));
MUXCY_L un1_rnd_out_i_cry_8_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_7),.S(un1_rnd_out_i_axb_8),.LO(un1_rnd_out_i_cry_8));
XORCY un1_rnd_out_i_s_7(.LI(un1_rnd_out_i_axb_7),.CI(un1_rnd_out_i_cry_6),.O(un1_rnd_out_i[6:6]));
MUXCY_L un1_rnd_out_i_cry_7_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_6),.S(un1_rnd_out_i_axb_7),.LO(un1_rnd_out_i_cry_7));
XORCY un1_rnd_out_i_s_6(.LI(un1_rnd_out_i_axb_6),.CI(un1_rnd_out_i_cry_5),.O(un1_rnd_out_i[5:5]));
MUXCY_L un1_rnd_out_i_cry_6_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_5),.S(un1_rnd_out_i_axb_6),.LO(un1_rnd_out_i_cry_6));
XORCY un1_rnd_out_i_s_5(.LI(un1_rnd_out_i_axb_5),.CI(un1_rnd_out_i_cry_4),.O(un1_rnd_out_i[4:4]));
MUXCY_L un1_rnd_out_i_cry_5_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_4),.S(un1_rnd_out_i_axb_5),.LO(un1_rnd_out_i_cry_5));
XORCY un1_rnd_out_i_s_4(.LI(un1_rnd_out_i_axb_4),.CI(un1_rnd_out_i_cry_3),.O(un1_rnd_out_i[3:3]));
MUXCY_L un1_rnd_out_i_cry_4_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_3),.S(un1_rnd_out_i_axb_4),.LO(un1_rnd_out_i_cry_4));
XORCY un1_rnd_out_i_s_3(.LI(un1_rnd_out_i_axb_3),.CI(un1_rnd_out_i_cry_2),.O(un1_rnd_out_i[2:2]));
MUXCY_L un1_rnd_out_i_cry_3_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_2),.S(un1_rnd_out_i_axb_3),.LO(un1_rnd_out_i_cry_3));
XORCY un1_rnd_out_i_s_2(.LI(un1_rnd_out_i_axb_2),.CI(un1_rnd_out_i_cry_1),.O(un1_rnd_out_i[1:1]));
MUXCY_L un1_rnd_out_i_cry_2_cZ(.DI(GND),.CI(un1_rnd_out_i_cry_1),.S(un1_rnd_out_i_axb_2),.LO(un1_rnd_out_i_cry_2));
XORCY un1_rnd_out_i_s_1(.LI(un1_rnd_out_i_axb_1),.CI(pre_out_i[7:7]),.O(un1_rnd_out_i[0:0]));
MUXCY_L un1_rnd_out_i_cry_1_cZ(.DI(GND),.CI(pre_out_i[7:7]),.S(un1_rnd_out_i_axb_1),.LO(un1_rnd_out_i_cry_1));
XORCY un2_rnd_out_r_s_12(.LI(un2_rnd_out_r_axb_12),.CI(un2_rnd_out_r_cry_11),.O(un2_rnd_out_r_s_12_1));
XORCY un2_rnd_out_r_s_11(.LI(un2_rnd_out_r_axb_11),.CI(un2_rnd_out_r_cry_10),.O(un2_rnd_out_r[10:10]));
MUXCY_L un2_rnd_out_r_cry_11_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_10),.S(un2_rnd_out_r_axb_11),.LO(un2_rnd_out_r_cry_11));
XORCY un2_rnd_out_r_s_10(.LI(un2_rnd_out_r_axb_10),.CI(un2_rnd_out_r_cry_9),.O(un2_rnd_out_r[9:9]));
MUXCY_L un2_rnd_out_r_cry_10_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_9),.S(un2_rnd_out_r_axb_10),.LO(un2_rnd_out_r_cry_10));
XORCY un2_rnd_out_r_s_9(.LI(un2_rnd_out_r_axb_9),.CI(un2_rnd_out_r_cry_8),.O(un2_rnd_out_r[8:8]));
MUXCY_L un2_rnd_out_r_cry_9_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_8),.S(un2_rnd_out_r_axb_9),.LO(un2_rnd_out_r_cry_9));
XORCY un2_rnd_out_r_s_8(.LI(un2_rnd_out_r_axb_8),.CI(un2_rnd_out_r_cry_7),.O(un2_rnd_out_r[7:7]));
MUXCY_L un2_rnd_out_r_cry_8_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_7),.S(un2_rnd_out_r_axb_8),.LO(un2_rnd_out_r_cry_8));
XORCY un2_rnd_out_r_s_7(.LI(un2_rnd_out_r_axb_7),.CI(un2_rnd_out_r_cry_6),.O(un2_rnd_out_r[6:6]));
MUXCY_L un2_rnd_out_r_cry_7_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_6),.S(un2_rnd_out_r_axb_7),.LO(un2_rnd_out_r_cry_7));
XORCY un2_rnd_out_r_s_6(.LI(un2_rnd_out_r_axb_6),.CI(un2_rnd_out_r_cry_5),.O(un2_rnd_out_r[5:5]));
MUXCY_L un2_rnd_out_r_cry_6_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_5),.S(un2_rnd_out_r_axb_6),.LO(un2_rnd_out_r_cry_6));
XORCY un2_rnd_out_r_s_5(.LI(un2_rnd_out_r_axb_5),.CI(un2_rnd_out_r_cry_4),.O(un2_rnd_out_r[4:4]));
MUXCY_L un2_rnd_out_r_cry_5_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_4),.S(un2_rnd_out_r_axb_5),.LO(un2_rnd_out_r_cry_5));
XORCY un2_rnd_out_r_s_4(.LI(un2_rnd_out_r_axb_4),.CI(un2_rnd_out_r_cry_3),.O(un2_rnd_out_r[3:3]));
MUXCY_L un2_rnd_out_r_cry_4_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_3),.S(un2_rnd_out_r_axb_4),.LO(un2_rnd_out_r_cry_4));
XORCY un2_rnd_out_r_s_3(.LI(un2_rnd_out_r_axb_3),.CI(un2_rnd_out_r_cry_2),.O(un2_rnd_out_r[2:2]));
MUXCY_L un2_rnd_out_r_cry_3_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_2),.S(un2_rnd_out_r_axb_3),.LO(un2_rnd_out_r_cry_3));
XORCY un2_rnd_out_r_s_2(.LI(un2_rnd_out_r_axb_2),.CI(un2_rnd_out_r_cry_1),.O(un2_rnd_out_r[1:1]));
MUXCY_L un2_rnd_out_r_cry_2_cZ(.DI(GND),.CI(un2_rnd_out_r_cry_1),.S(un2_rnd_out_r_axb_2),.LO(un2_rnd_out_r_cry_2));
XORCY un2_rnd_out_r_s_1(.LI(un2_rnd_out_r_axb_1),.CI(pre_out_r[7:7]),.O(un2_rnd_out_r[0:0]));
MUXCY_L un2_rnd_out_r_cry_1_cZ(.DI(GND),.CI(pre_out_r[7:7]),.S(un2_rnd_out_r_axb_1),.LO(un2_rnd_out_r_cry_1));
FDS desc671(.Q(out_i_vec_mult_3[11:11]),.D(pos_out_i[11:11]),.C(clk),.S(un1_pos_out_i_2));
FDR desc672(.Q(out_i_vec_mult_3[10:10]),.D(pos_out_i_iv_i[10:10]),.C(clk),.R(un1_pos_out_i_2));
FDR desc673(.Q(out_i_vec_mult_3[9:9]),.D(pos_out_i_iv_i[9:9]),.C(clk),.R(un1_pos_out_i_2));
FDR desc674(.Q(out_i_vec_mult_3[8:8]),.D(pos_out_i_iv_i[8:8]),.C(clk),.R(un1_pos_out_i_2));
FDR desc675(.Q(out_i_vec_mult_3[7:7]),.D(pos_out_i_iv_i[7:7]),.C(clk),.R(un1_pos_out_i_2));
FDR desc676(.Q(out_i_vec_mult_3[6:6]),.D(pos_out_i_iv_i[6:6]),.C(clk),.R(un1_pos_out_i_2));
FDR desc677(.Q(out_i_vec_mult_3[5:5]),.D(pos_out_i_iv_i[5:5]),.C(clk),.R(un1_pos_out_i_2));
FDR desc678(.Q(out_i_vec_mult_3[4:4]),.D(pos_out_i_iv_i[4:4]),.C(clk),.R(un1_pos_out_i_2));
FDR desc679(.Q(out_i_vec_mult_3[3:3]),.D(pos_out_i_iv_i[3:3]),.C(clk),.R(un1_pos_out_i_2));
FDR desc680(.Q(out_i_vec_mult_3[2:2]),.D(pos_out_i_iv_i[2:2]),.C(clk),.R(un1_pos_out_i_2));
FDR desc681(.Q(out_i_vec_mult_3[1:1]),.D(pos_out_i_iv_i[1:1]),.C(clk),.R(un1_pos_out_i_2));
FDR desc682(.Q(out_i_vec_mult_3[0:0]),.D(pos_out_i_iv_i[0:0]),.C(clk),.R(un1_pos_out_i_2));
FDS desc683(.Q(out_r_vec_mult_3[11:11]),.D(pos_out_r[11:11]),.C(clk),.S(un1_pos_out_r_2));
FDR desc684(.Q(out_r_vec_mult_3[10:10]),.D(pos_out_r_iv_i[10:10]),.C(clk),.R(un1_pos_out_r_2));
FDR desc685(.Q(out_r_vec_mult_3[9:9]),.D(pos_out_r_iv_i[9:9]),.C(clk),.R(un1_pos_out_r_2));
FDR desc686(.Q(out_r_vec_mult_3[8:8]),.D(pos_out_r_iv_i[8:8]),.C(clk),.R(un1_pos_out_r_2));
FDR desc687(.Q(out_r_vec_mult_3[7:7]),.D(pos_out_r_iv_i[7:7]),.C(clk),.R(un1_pos_out_r_2));
FDR desc688(.Q(out_r_vec_mult_3[6:6]),.D(pos_out_r_iv_i[6:6]),.C(clk),.R(un1_pos_out_r_2));
FDR desc689(.Q(out_r_vec_mult_3[5:5]),.D(pos_out_r_iv_i[5:5]),.C(clk),.R(un1_pos_out_r_2));
FDR desc690(.Q(out_r_vec_mult_3[4:4]),.D(pos_out_r_iv_i[4:4]),.C(clk),.R(un1_pos_out_r_2));
FDR desc691(.Q(out_r_vec_mult_3[3:3]),.D(pos_out_r_iv_i[3:3]),.C(clk),.R(un1_pos_out_r_2));
FDR desc692(.Q(out_r_vec_mult_3[2:2]),.D(pos_out_r_iv_i[2:2]),.C(clk),.R(un1_pos_out_r_2));
FDR desc693(.Q(out_r_vec_mult_3[1:1]),.D(pos_out_r_iv_i[1:1]),.C(clk),.R(un1_pos_out_r_2));
FDR desc694(.Q(out_r_vec_mult_3[0:0]),.D(pos_out_r_iv_i[0:0]),.C(clk),.R(un1_pos_out_r_2));
mult_pipe_16_inj mult1(.mult1_out_23(mult1_out[23:23]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_28_0(P_uc_28_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_3(vec_out_r_AQ_3[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
mult_pipe_17_inj mult2(.mult2_out_23(mult2_out[23:23]),.vec_out_i_AQ_3(vec_out_i_AQ_3[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_18_inj mult3(.mult3_out_23(mult3_out[23:23]),.vec_out_r_AQ_3(vec_out_r_AQ_3[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk));
mult_pipe_19_inj mult4(.mult4_out_23(mult4_out[23:23]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_31_0(P_uc_31_0[47:24]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_i_AQ_3(vec_out_i_AQ_3[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
add_subZ2_4_inj sub(.pre_out_r(pre_out_r[23:7]),.vec_out_i_AQ_3(vec_out_i_AQ_3[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult1_out_0(mult1_out_0[23:0]),.P_uc_28_0(P_uc_28_0[47:24]),.PATTERNDETECT_6(PATTERNDETECT_6),.clk(clk));
add_subZ1_4_inj add(.pre_out_i(pre_out_i[23:7]),.vec_out_r_AQ_3(vec_out_r_AQ_3[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.mult4_out_0(mult4_out_0[23:0]),.P_uc_31_0(P_uc_31_0[47:24]),.PATTERNDETECT_5(PATTERNDETECT_5),.clk(clk));
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
endmodule
module desc940_inj (un8_rnd_out_un0_P_9,un8_rnd_out_un0_P_10,un8_rnd_out_un0_P_11,un8_rnd_out_un0_P_12,un8_rnd_out_un0_P_13,un8_rnd_out_un0_P_14,un8_rnd_out_un0_P_15,un8_rnd_out_un0_P_16,un8_rnd_out_un0_P_17,un8_rnd_out_un0_P_18,un8_rnd_out_un0_P_19,mult1_out,mult2_out,pre_out_23,un2_output_3,PATTERNDETECT_15);
output un8_rnd_out_un0_P_9 ;
output un8_rnd_out_un0_P_10 ;
output un8_rnd_out_un0_P_11 ;
output un8_rnd_out_un0_P_12 ;
output un8_rnd_out_un0_P_13 ;
output un8_rnd_out_un0_P_14 ;
output un8_rnd_out_un0_P_15 ;
output un8_rnd_out_un0_P_16 ;
output un8_rnd_out_un0_P_17 ;
output un8_rnd_out_un0_P_18 ;
output un8_rnd_out_un0_P_19 ;
input [11:0] mult1_out ;
input [11:0] mult2_out ;
output pre_out_23 ;
output un2_output_3 ;
output PATTERNDETECT_15 ;
wire un8_rnd_out_un0_P_9 ;
wire un8_rnd_out_un0_P_10 ;
wire un8_rnd_out_un0_P_11 ;
wire un8_rnd_out_un0_P_12 ;
wire un8_rnd_out_un0_P_13 ;
wire un8_rnd_out_un0_P_14 ;
wire un8_rnd_out_un0_P_15 ;
wire un8_rnd_out_un0_P_16 ;
wire un8_rnd_out_un0_P_17 ;
wire un8_rnd_out_un0_P_18 ;
wire un8_rnd_out_un0_P_19 ;
wire pre_out_23 ;
wire un2_output_3 ;
wire PATTERNDETECT_15 ;
wire [22:0] pre_out ;
wire [29:0] ACOUT_11 ;
wire [17:0] BCOUT_11 ;
wire [3:0] CARRYOUT_11 ;
wire [8:0] un8_rnd_out_un0_P ;
wire [23:20] P_uc_1 ;
wire [47:24] P_uc_11 ;
wire [47:0] PCOUT_11 ;
wire [29:0] ACOUT_15 ;
wire [17:0] BCOUT_15 ;
wire [3:0] CARRYOUT_15 ;
wire [47:24] P_uc_15 ;
wire [47:0] PCOUT_15 ;
wire CARRYCASCOUT_11 ;
wire MULTSIGNOUT_11 ;
wire OVERFLOW_11 ;
wire PATTERNBDETECT_11 ;
wire PATTERNDETECT_11 ;
wire UNDERFLOW_11 ;
wire VCC ;
wire GND ;
wire CARRYCASCOUT_15 ;
wire MULTSIGNOUT_15 ;
wire OVERFLOW_15 ;
wire PATTERNBDETECT_15 ;
wire UNDERFLOW_15 ;
// instances
LUT4 desc941(.I0(pre_out[19:19]),.I1(pre_out[20:20]),.I2(pre_out[21:21]),.I3(pre_out[22:22]),.O(un2_output_3));
defparam desc941.INIT=16'h0001;
DSP48E1 desc942(.ACOUT(ACOUT_11[29:0]),.BCOUT(BCOUT_11[17:0]),.CARRYCASCOUT(CARRYCASCOUT_11),.CARRYOUT(CARRYOUT_11[3:0]),.MULTSIGNOUT(MULTSIGNOUT_11),.OVERFLOW(OVERFLOW_11),.P({P_uc_11[47:24],P_uc_1[23:20],un8_rnd_out_un0_P_19,un8_rnd_out_un0_P_18,un8_rnd_out_un0_P_17,un8_rnd_out_un0_P_16,un8_rnd_out_un0_P_15,un8_rnd_out_un0_P_14,un8_rnd_out_un0_P_13,un8_rnd_out_un0_P_12,un8_rnd_out_un0_P_11,un8_rnd_out_un0_P_10,un8_rnd_out_un0_P_9,un8_rnd_out_un0_P[8:0]}),.PATTERNBDETECT(PATTERNBDETECT_11),.PATTERNDETECT(PATTERNDETECT_11),.PCOUT(PCOUT_11[47:0]),.UNDERFLOW(UNDERFLOW_11),.A({mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,GND,GND,GND,GND,GND,GND,GND}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(GND),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,VCC,VCC,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc942.ACASCREG=0;
defparam desc942.ADREG=0;
defparam desc942.ALUMODEREG=0;
defparam desc942.AREG=0;
defparam desc942.AUTORESET_PATDET="NO_RESET";
defparam desc942.A_INPUT="DIRECT";
defparam desc942.BCASCREG=0;
defparam desc942.BREG=0;
defparam desc942.B_INPUT="DIRECT";
defparam desc942.CARRYINREG=0;
defparam desc942.CARRYINSELREG=0;
defparam desc942.CREG=0;
defparam desc942.DREG=0;
defparam desc942.INMODEREG=0;
defparam desc942.MREG=0;
defparam desc942.OPMODEREG=0;
defparam desc942.PREG=0;
defparam desc942.USE_DPORT="FALSE";
defparam desc942.USE_MULT="MULTIPLY";
defparam desc942.USE_SIMD="ONE48";
DSP48E1 desc943(.ACOUT(ACOUT_15[29:0]),.BCOUT(BCOUT_15[17:0]),.CARRYCASCOUT(CARRYCASCOUT_15),.CARRYOUT(CARRYOUT_15[3:0]),.MULTSIGNOUT(MULTSIGNOUT_15),.OVERFLOW(OVERFLOW_15),.P({P_uc_15[47:24],pre_out_23,pre_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_15),.PATTERNDETECT(PATTERNDETECT_15),.PCOUT(PCOUT_15[47:0]),.UNDERFLOW(UNDERFLOW_15),.A({mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:11],mult1_out[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:11],mult2_out[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(GND),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc943.ACASCREG=0;
defparam desc943.ADREG=0;
defparam desc943.ALUMODEREG=0;
defparam desc943.AREG=0;
defparam desc943.AUTORESET_PATDET="NO_RESET";
defparam desc943.A_INPUT="DIRECT";
defparam desc943.BCASCREG=0;
defparam desc943.BREG=0;
defparam desc943.B_INPUT="DIRECT";
defparam desc943.CARRYINREG=0;
defparam desc943.CARRYINSELREG=0;
defparam desc943.CREG=1;
defparam desc943.DREG=0;
defparam desc943.INMODEREG=0;
defparam desc943.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc943.MREG=0;
defparam desc943.OPMODEREG=0;
defparam desc943.PATTERN=48'b111111111111111111111111111111111111111111111111;
defparam desc943.PREG=0;
defparam desc943.SEL_MASK="MASK";
defparam desc943.USE_DPORT="FALSE";
defparam desc943.USE_MULT="MULTIPLY";
defparam desc943.USE_PATTERN_DETECT="PATDET";
defparam desc943.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module inner_prod_inj (out_inner_prod_i,out_inner_prod_r,in_a_inner_prod_sel,single_out_r_AQ_7,single_out_r_AQ_0,single_out_r_AQ_1,single_out_r_AQ_4,single_out_r_AQ_2,in_b_inner_prod_sel,vec_in_r_AQ_mux_0_6,vec_in_r_AQ_mux_0_7,vec_in_r_AQ_mux_0_0,vec_in_r_AQ_mux_0_9,vec_in_r_AQ_mux_0_1,vec_in_r_AQ_mux_0_8,vec_in_r_AQ_mux_0_4,vec_in_r_AQ_mux_0_3,vec_in_r_AQ_mux_0_2,vec_in_r_AQ_mux_0_10,vec_in_i_AQ_mux_0_7,vec_in_i_AQ_mux_0_1,vec_in_i_AQ_mux_0_0,vec_in_i_AQ_mux_0_6,vec_in_i_AQ_mux_0_8,vec_in_i_AQ_mux_0_10,vec_in_i_AQ_mux_0_5,vec_in_i_AQ_mux_0_9,vec_in_i_AQ_mux_0_4,vec_in_i_AQ_mux_0_11,single_out_i_AQ_1,single_out_i_AQ_0,single_out_i_AQ_8,single_out_i_AQ_10,single_out_i_AQ_9,single_out_i_AQ_4,single_out_i_AQ_11,output_iv,single_out_r_AQ2_4,single_out_r_AQ2_0,single_out_r_AQ2_1,single_out_r_AQ2_6,output_iv_0_4,output_iv_0_7,output_iv_0_0,output_iv_0_9,output_iv_0_1,output_iv_0_6,output_iv_0_3,output_iv_0_2,output_iv_0_8,out_r_vec_sub_0,out_i_vec_sub_0,single_out_i_AQ2_0,single_out_i_AQ2_5,single_out_i_AQ2_4,single_out_i_AQ2_1,single_out_i_AQ2_11,start_inner_prod,red_mat_reg,clk,rst,done_inner_prod,N_623,N_568,N_622,N_507,N_549,N_505,N_597,N_567,N_596,N_628,N_637,N_566,N_506,N_585,N_584,N_612,N_583,N_595,N_508,N_501,N_605,N_624,N_607,N_552,N_555,N_586,N_645,N_641,N_582,N_606,N_632,N_500,N_571,p_desc318_p_O_FDC,p_desc319_p_O_FDC,p_desc320_p_O_FDC,p_desc321_p_O_FDC,p_desc322_p_O_FDC,p_in_reg_enable_fsm_Z_p_O_FDC,p_done_Z_p_O_FDC,p_acc_enable_Z_p_O_FDC,p_desc325_p_O_FDC,p_desc326_p_O_FDC,p_desc327_p_O_FDC,p_desc328_p_O_FDC,p_desc329_p_O_FDC,p_desc330_p_O_FDC,p_desc331_p_O_FDC,p_desc332_p_O_FDC,p_desc333_p_O_FDC,p_desc334_p_O_FDC,p_desc335_p_O_FDC,p_desc336_p_O_FDC,p_desc337_p_O_FDC,p_desc338_p_O_FDC,p_desc339_p_O_FDC,p_desc340_p_O_FDC,p_desc341_p_O_FDC,p_desc342_p_O_FDC,p_desc343_p_O_FDC,p_desc344_p_O_FDC,p_desc345_p_O_FDC,p_desc346_p_O_FDC,p_desc347_p_O_FDC,p_desc348_p_O_FDC,p_desc349_p_O_FDC,p_desc350_p_O_FDC,p_desc375_p_O_FDC,p_desc376_p_O_FDC,p_desc377_p_O_FDC,p_desc378_p_O_FDC,p_desc379_p_O_FDC,p_desc380_p_O_FDC,p_desc381_p_O_FDC,p_desc382_p_O_FDC,p_desc383_p_O_FDC,p_desc384_p_O_FDC,p_desc385_p_O_FDC,p_desc386_p_O_FDC,p_desc387_p_O_FDC,p_desc388_p_O_FDC,p_desc389_p_O_FDC,p_desc390_p_O_FDC,p_desc391_p_O_FDC,p_desc392_p_O_FDC,p_desc393_p_O_FDC,p_desc394_p_O_FDC,p_desc395_p_O_FDC,p_desc396_p_O_FDC,p_desc397_p_O_FDC,p_desc398_p_O_FDC,p_acc_clear_Z_p_O_FDP,p_desc324_p_O_FDCE,p_desc351_p_O_FDCE,p_desc352_p_O_FDCE,p_desc353_p_O_FDCE,p_desc354_p_O_FDCE,p_desc355_p_O_FDCE,p_desc356_p_O_FDCE,p_desc357_p_O_FDCE,p_desc358_p_O_FDCE,p_desc359_p_O_FDCE,p_desc360_p_O_FDCE,p_desc361_p_O_FDCE,p_desc362_p_O_FDCE,p_desc363_p_O_FDCE,p_desc364_p_O_FDCE,p_desc365_p_O_FDCE,p_desc366_p_O_FDCE,p_desc367_p_O_FDCE,p_desc368_p_O_FDCE,p_desc369_p_O_FDCE,p_desc370_p_O_FDCE,p_desc371_p_O_FDCE,p_desc372_p_O_FDCE,p_desc373_p_O_FDCE,p_desc374_p_O_FDCE);
output [11:0] out_inner_prod_i ;
output [11:0] out_inner_prod_r ;
input in_a_inner_prod_sel ;
input single_out_r_AQ_7 ;
input single_out_r_AQ_0 ;
input single_out_r_AQ_1 ;
input single_out_r_AQ_4 ;
input single_out_r_AQ_2 ;
input in_b_inner_prod_sel ;
input vec_in_r_AQ_mux_0_6 ;
input vec_in_r_AQ_mux_0_7 ;
input vec_in_r_AQ_mux_0_0 ;
input vec_in_r_AQ_mux_0_9 ;
input vec_in_r_AQ_mux_0_1 ;
input vec_in_r_AQ_mux_0_8 ;
input vec_in_r_AQ_mux_0_4 ;
input vec_in_r_AQ_mux_0_3 ;
input vec_in_r_AQ_mux_0_2 ;
input vec_in_r_AQ_mux_0_10 ;
input vec_in_i_AQ_mux_0_7 ;
input vec_in_i_AQ_mux_0_1 ;
input vec_in_i_AQ_mux_0_0 ;
input vec_in_i_AQ_mux_0_6 ;
input vec_in_i_AQ_mux_0_8 ;
input vec_in_i_AQ_mux_0_10 ;
input vec_in_i_AQ_mux_0_5 ;
input vec_in_i_AQ_mux_0_9 ;
input vec_in_i_AQ_mux_0_4 ;
input vec_in_i_AQ_mux_0_11 ;
input single_out_i_AQ_1 ;
input single_out_i_AQ_0 ;
input single_out_i_AQ_8 ;
input single_out_i_AQ_10 ;
input single_out_i_AQ_9 ;
input single_out_i_AQ_4 ;
input single_out_i_AQ_11 ;
input [10:0] output_iv ;
input single_out_r_AQ2_4 ;
input single_out_r_AQ2_0 ;
input single_out_r_AQ2_1 ;
input single_out_r_AQ2_6 ;
input output_iv_0_4 ;
input output_iv_0_7 ;
input output_iv_0_0 ;
input output_iv_0_9 ;
input output_iv_0_1 ;
input output_iv_0_6 ;
input output_iv_0_3 ;
input output_iv_0_2 ;
input output_iv_0_8 ;
input [11:11] out_r_vec_sub_0 ;
input [11:11] out_i_vec_sub_0 ;
input single_out_i_AQ2_0 ;
input single_out_i_AQ2_5 ;
input single_out_i_AQ2_4 ;
input single_out_i_AQ2_1 ;
input single_out_i_AQ2_11 ;
input start_inner_prod ;
input red_mat_reg ;
input clk ;
input rst ;
output done_inner_prod ;
input N_623 ;
input N_568 ;
input N_622 ;
input N_507 ;
input N_549 ;
input N_505 ;
input N_597 ;
input N_567 ;
input N_596 ;
input N_628 ;
input N_637 ;
input N_566 ;
input N_506 ;
input N_585 ;
input N_584 ;
input N_612 ;
input N_583 ;
input N_595 ;
input N_508 ;
input N_501 ;
input N_605 ;
input N_624 ;
input N_607 ;
input N_552 ;
input N_555 ;
input N_586 ;
input N_645 ;
input N_641 ;
input N_582 ;
input N_606 ;
input N_632 ;
input N_500 ;
input N_571 ;
wire single_out_r_AQ_7 ;
wire single_out_r_AQ_0 ;
wire single_out_r_AQ_1 ;
wire single_out_r_AQ_4 ;
wire single_out_r_AQ_2 ;
wire vec_in_r_AQ_mux_0_6 ;
wire vec_in_r_AQ_mux_0_7 ;
wire vec_in_r_AQ_mux_0_0 ;
wire vec_in_r_AQ_mux_0_9 ;
wire vec_in_r_AQ_mux_0_1 ;
wire vec_in_r_AQ_mux_0_8 ;
wire vec_in_r_AQ_mux_0_4 ;
wire vec_in_r_AQ_mux_0_3 ;
wire vec_in_r_AQ_mux_0_2 ;
wire vec_in_r_AQ_mux_0_10 ;
wire vec_in_i_AQ_mux_0_7 ;
wire vec_in_i_AQ_mux_0_1 ;
wire vec_in_i_AQ_mux_0_0 ;
wire vec_in_i_AQ_mux_0_6 ;
wire vec_in_i_AQ_mux_0_8 ;
wire vec_in_i_AQ_mux_0_10 ;
wire vec_in_i_AQ_mux_0_5 ;
wire vec_in_i_AQ_mux_0_9 ;
wire vec_in_i_AQ_mux_0_4 ;
wire vec_in_i_AQ_mux_0_11 ;
wire single_out_i_AQ_1 ;
wire single_out_i_AQ_0 ;
wire single_out_i_AQ_8 ;
wire single_out_i_AQ_10 ;
wire single_out_i_AQ_9 ;
wire single_out_i_AQ_4 ;
wire single_out_i_AQ_11 ;
wire single_out_r_AQ2_4 ;
wire single_out_r_AQ2_0 ;
wire single_out_r_AQ2_1 ;
wire single_out_r_AQ2_6 ;
wire output_iv_0_4 ;
wire output_iv_0_7 ;
wire output_iv_0_0 ;
wire output_iv_0_9 ;
wire output_iv_0_1 ;
wire output_iv_0_6 ;
wire output_iv_0_3 ;
wire output_iv_0_2 ;
wire output_iv_0_8 ;
wire single_out_i_AQ2_0 ;
wire single_out_i_AQ2_5 ;
wire single_out_i_AQ2_4 ;
wire single_out_i_AQ2_1 ;
wire single_out_i_AQ2_11 ;
wire start_inner_prod ;
wire red_mat_reg ;
wire clk ;
wire rst ;
wire done_inner_prod ;
wire N_623 ;
wire N_568 ;
wire N_622 ;
wire N_507 ;
wire N_549 ;
wire N_505 ;
wire N_597 ;
wire N_567 ;
wire N_596 ;
wire N_628 ;
wire N_637 ;
wire N_566 ;
wire N_506 ;
wire N_585 ;
wire N_584 ;
wire N_612 ;
wire N_583 ;
wire N_595 ;
wire N_508 ;
wire N_501 ;
wire N_605 ;
wire N_624 ;
wire N_607 ;
wire N_552 ;
wire N_555 ;
wire N_586 ;
wire N_645 ;
wire N_641 ;
wire N_582 ;
wire N_606 ;
wire N_632 ;
wire N_500 ;
wire N_571 ;
wire [11:0] mult_out_i ;
wire [10:1] un2_pre_out ;
wire [11:0] acc_i_2 ;
wire [2:0] pipe_counter ;
wire [1:0] state ;
wire [2:0] in_counter ;
wire [2:1] pipe_counter_4_0_a2 ;
wire state_i_0 ;
wire [11:0] in_a_i_reg ;
wire [11:0] in_a_i_reg_2 ;
wire [11:0] in_a_r_reg ;
wire [8:1] in_a_r_reg_3 ;
wire [1:0] state_ns ;
wire [11:0] in_b_i_reg ;
wire [11:0] in_b_i_reg_2 ;
wire [11:0] in_b_r_reg ;
wire [11:1] in_b_r_reg_2 ;
wire [11:0] mult_out_r ;
wire [10:1] un2_pre_out_0 ;
wire acc_clear ;
wire un2_pre_out_s_11_0 ;
wire VCC ;
wire acc_enable ;
wire un1_state_4_0_0_lut6_2_O6 ;
wire acc_enable_0 ;
wire in_reg_enable_fsm_0_sqmuxa ;
wire un1_state_8_0_0_a2_lut6_2_O5 ;
wire un7_acc_enable_lut6_2_O6 ;
wire acc_clear_0 ;
wire in_counter_5_43_i_i_a2 ;
wire N_113_i_0 ;
wire in_reg_enable_fsm ;
wire in_reg_enable_fsm_0 ;
wire done ;
wire N_516_i_0 ;
wire N_518_i ;
wire N_519_i_0 ;
wire N_520_i ;
wire N_523_i ;
wire N_193_i ;
wire N_524_i ;
wire N_183_i ;
wire N_195_i ;
wire N_191_i ;
wire N_26_i ;
wire N_24_i ;
wire N_22_i ;
wire N_20_i ;
wire N_18_i ;
wire N_16_i ;
wire N_14_i ;
wire N_12_i ;
wire N_10_i ;
wire N_8_i ;
wire N_6_i ;
wire N_4_i ;
wire N_521_i ;
wire N_517_i_0 ;
wire N_522_i ;
wire N_185_i ;
wire un2_pre_out_s_11 ;
wire N_27 ;
wire N_26 ;
wire N_25 ;
wire GND ;
input p_desc318_p_O_FDC ;
input p_desc319_p_O_FDC ;
input p_desc320_p_O_FDC ;
input p_desc321_p_O_FDC ;
input p_desc322_p_O_FDC ;
input p_in_reg_enable_fsm_Z_p_O_FDC ;
input p_done_Z_p_O_FDC ;
input p_acc_enable_Z_p_O_FDC ;
input p_desc325_p_O_FDC ;
input p_desc326_p_O_FDC ;
input p_desc327_p_O_FDC ;
input p_desc328_p_O_FDC ;
input p_desc329_p_O_FDC ;
input p_desc330_p_O_FDC ;
input p_desc331_p_O_FDC ;
input p_desc332_p_O_FDC ;
input p_desc333_p_O_FDC ;
input p_desc334_p_O_FDC ;
input p_desc335_p_O_FDC ;
input p_desc336_p_O_FDC ;
input p_desc337_p_O_FDC ;
input p_desc338_p_O_FDC ;
input p_desc339_p_O_FDC ;
input p_desc340_p_O_FDC ;
input p_desc341_p_O_FDC ;
input p_desc342_p_O_FDC ;
input p_desc343_p_O_FDC ;
input p_desc344_p_O_FDC ;
input p_desc345_p_O_FDC ;
input p_desc346_p_O_FDC ;
input p_desc347_p_O_FDC ;
input p_desc348_p_O_FDC ;
input p_desc349_p_O_FDC ;
input p_desc350_p_O_FDC ;
input p_desc375_p_O_FDC ;
input p_desc376_p_O_FDC ;
input p_desc377_p_O_FDC ;
input p_desc378_p_O_FDC ;
input p_desc379_p_O_FDC ;
input p_desc380_p_O_FDC ;
input p_desc381_p_O_FDC ;
input p_desc382_p_O_FDC ;
input p_desc383_p_O_FDC ;
input p_desc384_p_O_FDC ;
input p_desc385_p_O_FDC ;
input p_desc386_p_O_FDC ;
input p_desc387_p_O_FDC ;
input p_desc388_p_O_FDC ;
input p_desc389_p_O_FDC ;
input p_desc390_p_O_FDC ;
input p_desc391_p_O_FDC ;
input p_desc392_p_O_FDC ;
input p_desc393_p_O_FDC ;
input p_desc394_p_O_FDC ;
input p_desc395_p_O_FDC ;
input p_desc396_p_O_FDC ;
input p_desc397_p_O_FDC ;
input p_desc398_p_O_FDC ;
input p_acc_clear_Z_p_O_FDP ;
input p_desc324_p_O_FDCE ;
input p_desc351_p_O_FDCE ;
input p_desc352_p_O_FDCE ;
input p_desc353_p_O_FDCE ;
input p_desc354_p_O_FDCE ;
input p_desc355_p_O_FDCE ;
input p_desc356_p_O_FDCE ;
input p_desc357_p_O_FDCE ;
input p_desc358_p_O_FDCE ;
input p_desc359_p_O_FDCE ;
input p_desc360_p_O_FDCE ;
input p_desc361_p_O_FDCE ;
input p_desc362_p_O_FDCE ;
input p_desc363_p_O_FDCE ;
input p_desc364_p_O_FDCE ;
input p_desc365_p_O_FDCE ;
input p_desc366_p_O_FDCE ;
input p_desc367_p_O_FDCE ;
input p_desc368_p_O_FDCE ;
input p_desc369_p_O_FDCE ;
input p_desc370_p_O_FDCE ;
input p_desc371_p_O_FDCE ;
input p_desc372_p_O_FDCE ;
input p_desc373_p_O_FDCE ;
input p_desc374_p_O_FDCE ;
// instances
p_O_FDC desc318(.Q(in_counter[2:2]),.D(in_counter_5_43_i_i_a2),.C(clk),.CLR(rst),.E(p_desc318_p_O_FDC));
p_O_FDC desc319(.Q(in_counter[1:1]),.D(N_113_i_0),.C(clk),.CLR(rst),.E(p_desc319_p_O_FDC));
p_O_FDC desc320(.Q(in_counter[0:0]),.D(state_i_0),.C(clk),.CLR(rst),.E(p_desc320_p_O_FDC));
p_O_FDC desc321(.Q(pipe_counter[2:2]),.D(pipe_counter_4_0_a2[2:2]),.C(clk),.CLR(rst),.E(p_desc321_p_O_FDC));
p_O_FDC desc322(.Q(pipe_counter[1:1]),.D(pipe_counter_4_0_a2[1:1]),.C(clk),.CLR(rst),.E(p_desc322_p_O_FDC));
LUT4 desc323(.I0(in_counter[0:0]),.I1(state[0:0]),.I2(in_counter[1:1]),.I3(un1_state_4_0_0_lut6_2_O6),.O(N_113_i_0));
defparam desc323.INIT=16'h88F0;
p_O_FDCE desc324(.Q(pipe_counter[0:0]),.D(in_reg_enable_fsm_0_sqmuxa),.C(clk),.CLR(rst),.CE(un1_state_8_0_0_a2_lut6_2_O5),.E(p_desc324_p_O_FDCE));
p_O_FDC in_reg_enable_fsm_Z(.Q(in_reg_enable_fsm),.D(in_reg_enable_fsm_0),.C(clk),.CLR(rst),.E(p_in_reg_enable_fsm_Z_p_O_FDC));
p_O_FDC done_Z(.Q(done_inner_prod),.D(done),.C(clk),.CLR(rst),.E(p_done_Z_p_O_FDC));
p_O_FDC acc_enable_Z(.Q(acc_enable),.D(acc_enable_0),.C(clk),.CLR(rst),.E(p_acc_enable_Z_p_O_FDC));
p_O_FDP acc_clear_Z(.Q(acc_clear),.D(acc_clear_0),.C(clk),.PRE(rst),.E(p_acc_clear_Z_p_O_FDP));
p_O_FDC desc325(.Q(in_a_i_reg[0:0]),.D(in_a_i_reg_2[0:0]),.C(clk),.CLR(rst),.E(p_desc325_p_O_FDC));
p_O_FDC desc326(.Q(in_a_i_reg[1:1]),.D(in_a_i_reg_2[1:1]),.C(clk),.CLR(rst),.E(p_desc326_p_O_FDC));
p_O_FDC desc327(.Q(in_a_i_reg[2:2]),.D(N_516_i_0),.C(clk),.CLR(rst),.E(p_desc327_p_O_FDC));
p_O_FDC desc328(.Q(in_a_i_reg[3:3]),.D(N_518_i),.C(clk),.CLR(rst),.E(p_desc328_p_O_FDC));
p_O_FDC desc329(.Q(in_a_i_reg[4:4]),.D(in_a_i_reg_2[4:4]),.C(clk),.CLR(rst),.E(p_desc329_p_O_FDC));
p_O_FDC desc330(.Q(in_a_i_reg[5:5]),.D(in_a_i_reg_2[5:5]),.C(clk),.CLR(rst),.E(p_desc330_p_O_FDC));
p_O_FDC desc331(.Q(in_a_i_reg[6:6]),.D(N_519_i_0),.C(clk),.CLR(rst),.E(p_desc331_p_O_FDC));
p_O_FDC desc332(.Q(in_a_i_reg[7:7]),.D(N_520_i),.C(clk),.CLR(rst),.E(p_desc332_p_O_FDC));
p_O_FDC desc333(.Q(in_a_i_reg[8:8]),.D(in_a_i_reg_2[8:8]),.C(clk),.CLR(rst),.E(p_desc333_p_O_FDC));
p_O_FDC desc334(.Q(in_a_i_reg[9:9]),.D(in_a_i_reg_2[9:9]),.C(clk),.CLR(rst),.E(p_desc334_p_O_FDC));
p_O_FDC desc335(.Q(in_a_i_reg[10:10]),.D(in_a_i_reg_2[10:10]),.C(clk),.CLR(rst),.E(p_desc335_p_O_FDC));
p_O_FDC desc336(.Q(in_a_i_reg[11:11]),.D(in_a_i_reg_2[11:11]),.C(clk),.CLR(rst),.E(p_desc336_p_O_FDC));
p_O_FDC desc337(.Q(in_a_r_reg[3:3]),.D(in_a_r_reg_3[3:3]),.C(clk),.CLR(rst),.E(p_desc337_p_O_FDC));
p_O_FDC desc338(.Q(in_a_r_reg[4:4]),.D(in_a_r_reg_3[4:4]),.C(clk),.CLR(rst),.E(p_desc338_p_O_FDC));
p_O_FDC desc339(.Q(in_a_r_reg[5:5]),.D(in_a_r_reg_3[5:5]),.C(clk),.CLR(rst),.E(p_desc339_p_O_FDC));
p_O_FDC desc340(.Q(in_a_r_reg[6:6]),.D(N_523_i),.C(clk),.CLR(rst),.E(p_desc340_p_O_FDC));
p_O_FDC desc341(.Q(in_a_r_reg[7:7]),.D(N_193_i),.C(clk),.CLR(rst),.E(p_desc341_p_O_FDC));
p_O_FDC desc342(.Q(in_a_r_reg[8:8]),.D(in_a_r_reg_3[8:8]),.C(clk),.CLR(rst),.E(p_desc342_p_O_FDC));
p_O_FDC desc343(.Q(in_a_r_reg[9:9]),.D(N_524_i),.C(clk),.CLR(rst),.E(p_desc343_p_O_FDC));
p_O_FDC desc344(.Q(in_a_r_reg[10:10]),.D(N_183_i),.C(clk),.CLR(rst),.E(p_desc344_p_O_FDC));
p_O_FDC desc345(.Q(in_a_r_reg[11:11]),.D(N_195_i),.C(clk),.CLR(rst),.E(p_desc345_p_O_FDC));
p_O_FDC desc346(.Q(in_a_r_reg[0:0]),.D(N_191_i),.C(clk),.CLR(rst),.E(p_desc346_p_O_FDC));
p_O_FDC desc347(.Q(in_a_r_reg[1:1]),.D(in_a_r_reg_3[1:1]),.C(clk),.CLR(rst),.E(p_desc347_p_O_FDC));
p_O_FDC desc348(.Q(in_a_r_reg[2:2]),.D(in_a_r_reg_3[2:2]),.C(clk),.CLR(rst),.E(p_desc348_p_O_FDC));
p_O_FDC desc349(.Q(state[0:0]),.D(state_ns[0:0]),.C(clk),.CLR(rst),.E(p_desc349_p_O_FDC));
p_O_FDC desc350(.Q(state[1:1]),.D(state_ns[1:1]),.C(clk),.CLR(rst),.E(p_desc350_p_O_FDC));
p_O_FDCE desc351(.Q(out_inner_prod_i[11:11]),.D(acc_i_2[11:11]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc351_p_O_FDCE));
p_O_FDCE desc352(.Q(out_inner_prod_i[10:10]),.D(acc_i_2[10:10]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc352_p_O_FDCE));
p_O_FDCE desc353(.Q(out_inner_prod_i[9:9]),.D(acc_i_2[9:9]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc353_p_O_FDCE));
p_O_FDCE desc354(.Q(out_inner_prod_i[8:8]),.D(acc_i_2[8:8]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc354_p_O_FDCE));
p_O_FDCE desc355(.Q(out_inner_prod_i[7:7]),.D(acc_i_2[7:7]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc355_p_O_FDCE));
p_O_FDCE desc356(.Q(out_inner_prod_i[6:6]),.D(acc_i_2[6:6]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc356_p_O_FDCE));
p_O_FDCE desc357(.Q(out_inner_prod_i[5:5]),.D(acc_i_2[5:5]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc357_p_O_FDCE));
p_O_FDCE desc358(.Q(out_inner_prod_i[4:4]),.D(acc_i_2[4:4]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc358_p_O_FDCE));
p_O_FDCE desc359(.Q(out_inner_prod_i[3:3]),.D(acc_i_2[3:3]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc359_p_O_FDCE));
p_O_FDCE desc360(.Q(out_inner_prod_i[2:2]),.D(acc_i_2[2:2]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc360_p_O_FDCE));
p_O_FDCE desc361(.Q(out_inner_prod_i[1:1]),.D(acc_i_2[1:1]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc361_p_O_FDCE));
p_O_FDCE desc362(.Q(out_inner_prod_i[0:0]),.D(acc_i_2[0:0]),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc362_p_O_FDCE));
p_O_FDCE desc363(.Q(out_inner_prod_r[11:11]),.D(N_26_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc363_p_O_FDCE));
p_O_FDCE desc364(.Q(out_inner_prod_r[10:10]),.D(N_24_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc364_p_O_FDCE));
p_O_FDCE desc365(.Q(out_inner_prod_r[9:9]),.D(N_22_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc365_p_O_FDCE));
p_O_FDCE desc366(.Q(out_inner_prod_r[8:8]),.D(N_20_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc366_p_O_FDCE));
p_O_FDCE desc367(.Q(out_inner_prod_r[7:7]),.D(N_18_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc367_p_O_FDCE));
p_O_FDCE desc368(.Q(out_inner_prod_r[6:6]),.D(N_16_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc368_p_O_FDCE));
p_O_FDCE desc369(.Q(out_inner_prod_r[5:5]),.D(N_14_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc369_p_O_FDCE));
p_O_FDCE desc370(.Q(out_inner_prod_r[4:4]),.D(N_12_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc370_p_O_FDCE));
p_O_FDCE desc371(.Q(out_inner_prod_r[3:3]),.D(N_10_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc371_p_O_FDCE));
p_O_FDCE desc372(.Q(out_inner_prod_r[2:2]),.D(N_8_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc372_p_O_FDCE));
p_O_FDCE desc373(.Q(out_inner_prod_r[1:1]),.D(N_6_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc373_p_O_FDCE));
p_O_FDCE desc374(.Q(out_inner_prod_r[0:0]),.D(N_4_i),.C(clk),.CLR(rst),.CE(un7_acc_enable_lut6_2_O6),.E(p_desc374_p_O_FDCE));
p_O_FDC desc375(.Q(in_b_i_reg[11:11]),.D(in_b_i_reg_2[11:11]),.C(clk),.CLR(rst),.E(p_desc375_p_O_FDC));
p_O_FDC desc376(.Q(in_b_i_reg[10:10]),.D(in_b_i_reg_2[10:10]),.C(clk),.CLR(rst),.E(p_desc376_p_O_FDC));
p_O_FDC desc377(.Q(in_b_i_reg[9:9]),.D(in_b_i_reg_2[9:9]),.C(clk),.CLR(rst),.E(p_desc377_p_O_FDC));
p_O_FDC desc378(.Q(in_b_i_reg[8:8]),.D(in_b_i_reg_2[8:8]),.C(clk),.CLR(rst),.E(p_desc378_p_O_FDC));
p_O_FDC desc379(.Q(in_b_i_reg[7:7]),.D(in_b_i_reg_2[7:7]),.C(clk),.CLR(rst),.E(p_desc379_p_O_FDC));
p_O_FDC desc380(.Q(in_b_i_reg[6:6]),.D(in_b_i_reg_2[6:6]),.C(clk),.CLR(rst),.E(p_desc380_p_O_FDC));
p_O_FDC desc381(.Q(in_b_i_reg[5:5]),.D(in_b_i_reg_2[5:5]),.C(clk),.CLR(rst),.E(p_desc381_p_O_FDC));
p_O_FDC desc382(.Q(in_b_i_reg[4:4]),.D(in_b_i_reg_2[4:4]),.C(clk),.CLR(rst),.E(p_desc382_p_O_FDC));
p_O_FDC desc383(.Q(in_b_i_reg[3:3]),.D(N_521_i),.C(clk),.CLR(rst),.E(p_desc383_p_O_FDC));
p_O_FDC desc384(.Q(in_b_i_reg[2:2]),.D(N_517_i_0),.C(clk),.CLR(rst),.E(p_desc384_p_O_FDC));
p_O_FDC desc385(.Q(in_b_i_reg[1:1]),.D(in_b_i_reg_2[1:1]),.C(clk),.CLR(rst),.E(p_desc385_p_O_FDC));
p_O_FDC desc386(.Q(in_b_i_reg[0:0]),.D(in_b_i_reg_2[0:0]),.C(clk),.CLR(rst),.E(p_desc386_p_O_FDC));
p_O_FDC desc387(.Q(in_b_r_reg[11:11]),.D(in_b_r_reg_2[11:11]),.C(clk),.CLR(rst),.E(p_desc387_p_O_FDC));
p_O_FDC desc388(.Q(in_b_r_reg[10:10]),.D(in_b_r_reg_2[10:10]),.C(clk),.CLR(rst),.E(p_desc388_p_O_FDC));
p_O_FDC desc389(.Q(in_b_r_reg[9:9]),.D(in_b_r_reg_2[9:9]),.C(clk),.CLR(rst),.E(p_desc389_p_O_FDC));
p_O_FDC desc390(.Q(in_b_r_reg[8:8]),.D(in_b_r_reg_2[8:8]),.C(clk),.CLR(rst),.E(p_desc390_p_O_FDC));
p_O_FDC desc391(.Q(in_b_r_reg[7:7]),.D(in_b_r_reg_2[7:7]),.C(clk),.CLR(rst),.E(p_desc391_p_O_FDC));
p_O_FDC desc392(.Q(in_b_r_reg[6:6]),.D(N_522_i),.C(clk),.CLR(rst),.E(p_desc392_p_O_FDC));
p_O_FDC desc393(.Q(in_b_r_reg[5:5]),.D(in_b_r_reg_2[5:5]),.C(clk),.CLR(rst),.E(p_desc393_p_O_FDC));
p_O_FDC desc394(.Q(in_b_r_reg[4:4]),.D(in_b_r_reg_2[4:4]),.C(clk),.CLR(rst),.E(p_desc394_p_O_FDC));
p_O_FDC desc395(.Q(in_b_r_reg[3:3]),.D(in_b_r_reg_2[3:3]),.C(clk),.CLR(rst),.E(p_desc395_p_O_FDC));
p_O_FDC desc396(.Q(in_b_r_reg[2:2]),.D(in_b_r_reg_2[2:2]),.C(clk),.CLR(rst),.E(p_desc396_p_O_FDC));
p_O_FDC desc397(.Q(in_b_r_reg[1:1]),.D(in_b_r_reg_2[1:1]),.C(clk),.CLR(rst),.E(p_desc397_p_O_FDC));
p_O_FDC desc398(.Q(in_b_r_reg[0:0]),.D(N_185_i),.C(clk),.CLR(rst),.E(p_desc398_p_O_FDC));
LUT5_L desc399(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_623),.I4(vec_in_r_AQ_mux_0_6),.LO(N_193_i));
defparam desc399.INIT=32'hFC54A800;
LUT5_L desc400(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_r_AQ_7),.I4(vec_in_r_AQ_mux_0_7),.LO(in_a_r_reg_3[8:8]));
defparam desc400.INIT=32'hFC54A800;
LUT5_L desc401(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_r_AQ_0),.I4(vec_in_r_AQ_mux_0_0),.LO(in_a_r_reg_3[1:1]));
defparam desc401.INIT=32'hFC54A800;
LUT5_L desc402(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_568),.I4(vec_in_i_AQ_mux_0_7),.LO(N_520_i));
defparam desc402.INIT=32'hFC54A800;
LUT5_L desc403(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_622),.I4(N_507),.LO(N_191_i));
defparam desc403.INIT=32'hFC54A800;
LUT5_L desc404(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_i_AQ_1),.I4(vec_in_i_AQ_mux_0_1),.LO(in_a_i_reg_2[1:1]));
defparam desc404.INIT=32'hFC54A800;
LUT5_L desc405(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_i_AQ_0),.I4(vec_in_i_AQ_mux_0_0),.LO(in_a_i_reg_2[0:0]));
defparam desc405.INIT=32'hFC54A800;
LUT5_L desc406(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_549),.I4(N_505),.LO(N_516_i_0));
defparam desc406.INIT=32'hFC54A800;
LUT5_L desc407(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_597),.I4(vec_in_r_AQ_mux_0_9),.LO(N_183_i));
defparam desc407.INIT=32'hFC54A800;
LUT5_L desc408(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_567),.I4(vec_in_i_AQ_mux_0_6),.LO(N_519_i_0));
defparam desc408.INIT=32'hFC54A800;
LUT5_L desc409(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_r_AQ_1),.I4(vec_in_r_AQ_mux_0_1),.LO(in_a_r_reg_3[2:2]));
defparam desc409.INIT=32'hFC54A800;
LUT5_L desc410(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_596),.I4(vec_in_r_AQ_mux_0_8),.LO(N_524_i));
defparam desc410.INIT=32'hFC54A800;
LUT5_L desc411(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_i_AQ_8),.I4(vec_in_i_AQ_mux_0_8),.LO(in_a_i_reg_2[8:8]));
defparam desc411.INIT=32'hFC54A800;
LUT5_L desc412(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_i_AQ_10),.I4(vec_in_i_AQ_mux_0_10),.LO(in_a_i_reg_2[10:10]));
defparam desc412.INIT=32'hFC54A800;
LUT5_L desc413(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_628),.I4(vec_in_i_AQ_mux_0_5),.LO(in_a_i_reg_2[5:5]));
defparam desc413.INIT=32'hFC54A800;
LUT5_L desc414(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_r_AQ_4),.I4(vec_in_r_AQ_mux_0_4),.LO(in_a_r_reg_3[5:5]));
defparam desc414.INIT=32'hFC54A800;
LUT5_L desc415(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_637),.I4(vec_in_r_AQ_mux_0_3),.LO(in_a_r_reg_3[4:4]));
defparam desc415.INIT=32'hFC54A800;
LUT5_L desc416(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_i_AQ_9),.I4(vec_in_i_AQ_mux_0_9),.LO(in_a_i_reg_2[9:9]));
defparam desc416.INIT=32'hFC54A800;
LUT5_L desc417(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_i_AQ_4),.I4(vec_in_i_AQ_mux_0_4),.LO(in_a_i_reg_2[4:4]));
defparam desc417.INIT=32'hFC54A800;
LUT5_L desc418(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(single_out_r_AQ_2),.I4(vec_in_r_AQ_mux_0_2),.LO(in_a_r_reg_3[3:3]));
defparam desc418.INIT=32'hFC54A800;
LUT5_L desc419(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_566),.I4(N_506),.LO(N_518_i));
defparam desc419.INIT=32'hFC54A800;
LUT5_L desc420(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[9:9]),.I4(N_585),.LO(in_b_i_reg_2[9:9]));
defparam desc420.INIT=32'hA8FC0054;
LUT5_L desc421(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[5:5]),.I4(single_out_r_AQ2_4),.LO(in_b_r_reg_2[5:5]));
defparam desc421.INIT=32'hA8FC0054;
LUT5_L desc422(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[7:7]),.I4(N_584),.LO(in_b_i_reg_2[7:7]));
defparam desc422.INIT=32'hA8FC0054;
LUT5_L desc423(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[8:8]),.I4(N_612),.LO(in_b_i_reg_2[8:8]));
defparam desc423.INIT=32'hA8FC0054;
LUT5_L desc424(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[6:6]),.I4(N_583),.LO(in_b_i_reg_2[6:6]));
defparam desc424.INIT=32'hA8FC0054;
LUT5_L desc425(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_595),.I4(N_508),.LO(N_523_i));
defparam desc425.INIT=32'hFC54A800;
LUT5_L desc426(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[1:1]),.I4(single_out_r_AQ2_0),.LO(in_b_r_reg_2[1:1]));
defparam desc426.INIT=32'hA8FC0054;
LUT5_L desc427(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[0:0]),.I4(single_out_i_AQ2_0),.LO(in_b_i_reg_2[0:0]));
defparam desc427.INIT=32'hA8FC0054;
LUT5_L desc428(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_4),.I4(single_out_i_AQ2_5),.LO(in_b_i_reg_2[5:5]));
defparam desc428.INIT=32'hA8FC0054;
LUT5_L desc429(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_501),.I4(N_605),.LO(N_185_i));
defparam desc429.INIT=32'hA8FC0054;
LUT5_L desc430(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(vec_in_r_AQ_mux_0_10),.I4(N_624),.LO(N_195_i));
defparam desc430.INIT=32'hFCA85400;
LUT5_L desc431(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[4:4]),.I4(single_out_i_AQ2_4),.LO(in_b_i_reg_2[4:4]));
defparam desc431.INIT=32'hA8FC0054;
LUT5_L desc432(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[10:10]),.I4(N_607),.LO(in_b_r_reg_2[10:10]));
defparam desc432.INIT=32'hA8FC0054;
LUT5_L desc433(.I0(in_a_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(vec_in_i_AQ_mux_0_11),.I4(single_out_i_AQ_11),.LO(in_a_i_reg_2[11:11]));
defparam desc433.INIT=32'hFCA85400;
LUT5_L desc434(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_7),.I4(N_552),.LO(in_b_r_reg_2[8:8]));
defparam desc434.INIT=32'hA8FC0054;
LUT5_L desc435(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[2:2]),.I4(N_555),.LO(N_517_i_0));
defparam desc435.INIT=32'hA8FC0054;
LUT5_L desc436(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_0),.I4(single_out_i_AQ2_1),.LO(in_b_i_reg_2[1:1]));
defparam desc436.INIT=32'hA8FC0054;
LUT5_L desc437(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_9),.I4(N_586),.LO(in_b_i_reg_2[10:10]));
defparam desc437.INIT=32'hA8FC0054;
LUT5_L desc438(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv[3:3]),.I4(N_645),.LO(in_b_r_reg_2[3:3]));
defparam desc438.INIT=32'hA8FC0054;
LUT5_L desc439(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_1),.I4(single_out_r_AQ2_1),.LO(in_b_r_reg_2[2:2]));
defparam desc439.INIT=32'hA8FC0054;
LUT5_L desc440(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_6),.I4(single_out_r_AQ2_6),.LO(in_b_r_reg_2[7:7]));
defparam desc440.INIT=32'hA8FC0054;
LUT5_L desc441(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_3),.I4(N_641),.LO(in_b_r_reg_2[4:4]));
defparam desc441.INIT=32'hA8FC0054;
LUT5_L desc442(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_2),.I4(N_582),.LO(N_521_i));
defparam desc442.INIT=32'hA8FC0054;
LUT5_L desc443(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(output_iv_0_8),.I4(N_606),.LO(in_b_r_reg_2[9:9]));
defparam desc443.INIT=32'hA8FC0054;
LUT5_L desc444(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(out_r_vec_sub_0[11:11]),.I4(N_632),.LO(in_b_r_reg_2[11:11]));
defparam desc444.INIT=32'hFCA85400;
LUT5_L desc445(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(out_i_vec_sub_0[11:11]),.I4(single_out_i_AQ2_11),.LO(in_b_i_reg_2[11:11]));
defparam desc445.INIT=32'hFCA85400;
LUT5_L desc446(.I0(in_b_inner_prod_sel),.I1(in_reg_enable_fsm),.I2(start_inner_prod),.I3(N_500),.I4(N_571),.LO(N_522_i));
defparam desc446.INIT=32'hA8FC0054;
LUT5_L desc447(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[7:7]),.I4(un2_pre_out_s_11),.LO(N_18_i));
defparam desc447.INIT=32'h33011300;
LUT5_L desc448(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[6:6]),.I4(un2_pre_out_s_11),.LO(N_16_i));
defparam desc448.INIT=32'h33011300;
LUT5_L desc449(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[5:5]),.I4(un2_pre_out_s_11),.LO(N_14_i));
defparam desc449.INIT=32'h33011300;
LUT5_L desc450(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[4:4]),.I4(un2_pre_out_s_11),.LO(N_12_i));
defparam desc450.INIT=32'h33011300;
LUT6_L desc451(.I0(mult_out_r[0:0]),.I1(mult_out_r[11:11]),.I2(out_inner_prod_r[0:0]),.I3(acc_clear),.I4(out_inner_prod_r[11:11]),.I5(un2_pre_out_s_11),.LO(N_4_i));
defparam desc451.INIT=64'h005A007B0012005A;
LUT5_L desc452(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[9:9]),.I4(un2_pre_out_s_11),.LO(N_22_i));
defparam desc452.INIT=32'h33011300;
LUT5_L desc453(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[3:3]),.I4(un2_pre_out_s_11),.LO(N_10_i));
defparam desc453.INIT=32'h33011300;
LUT5_L desc454(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[2:2]),.I4(un2_pre_out_s_11),.LO(N_8_i));
defparam desc454.INIT=32'h33011300;
LUT5_L desc455(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out[1:1]),.I4(un2_pre_out_s_11),.LO(N_6_i));
defparam desc455.INIT=32'h33011300;
LUT5_L desc456(.I0(mult_out_r[11:11]),.I1(acc_clear),.I2(out_inner_prod_r[11:11]),.I3(un2_pre_out_0[10:10]),.I4(un2_pre_out_s_11),.LO(N_24_i));
defparam desc456.INIT=32'h33011300;
LUT6_L desc457(.I0(mult_out_i[0:0]),.I1(out_inner_prod_i[0:0]),.I2(mult_out_i[11:11]),.I3(acc_clear),.I4(out_inner_prod_i[11:11]),.I5(un2_pre_out_s_11_0),.LO(acc_i_2[0:0]));
defparam desc457.INIT=64'h0066006F00060066;
LUT6_L desc458(.I0(pipe_counter[2:2]),.I1(in_counter[2:2]),.I2(in_counter[0:0]),.I3(state[1:1]),.I4(state[0:0]),.I5(red_mat_reg),.LO(state_ns[1:1]));
defparam desc458.INIT=64'hF0F05500CCCC5500;
LUT4_L done_e(.I0(pipe_counter[2:2]),.I1(state[1:1]),.I2(done_inner_prod),.I3(state[0:0]),.LO(done));
defparam done_e.INIT=16'hF0C8;
LUT6_L desc459(.I0(in_counter[2:2]),.I1(in_counter[0:0]),.I2(state[1:1]),.I3(state[0:0]),.I4(red_mat_reg),.I5(start_inner_prod),.LO(state_ns[0:0]));
defparam desc459.INIT=64'h330F550F33005500;
LUT5_L in_reg_enable_fsm_e(.I0(state[1:1]),.I1(state[0:0]),.I2(in_reg_enable_fsm),.I3(start_inner_prod),.I4(in_reg_enable_fsm_0_sqmuxa),.LO(in_reg_enable_fsm_0));
defparam in_reg_enable_fsm_e.INIT=32'h3333F1F0;
LUT5_L desc460(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out[8:8]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[8:8]));
defparam desc460.INIT=32'h33011300;
LUT5_L desc461(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[4:4]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[4:4]));
defparam desc461.INIT=32'h33011300;
LUT5_L desc462(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[7:7]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[7:7]));
defparam desc462.INIT=32'h33011300;
LUT5_L desc463(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[3:3]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[3:3]));
defparam desc463.INIT=32'h33011300;
LUT5_L desc464(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[5:5]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[5:5]));
defparam desc464.INIT=32'h33011300;
LUT5_L desc465(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[1:1]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[1:1]));
defparam desc465.INIT=32'h33011300;
LUT5_L desc466(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[2:2]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[2:2]));
defparam desc466.INIT=32'h33011300;
LUT5_L desc467(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[9:9]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[9:9]));
defparam desc467.INIT=32'h33011300;
LUT5_L desc468(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_0[6:6]),.I4(un2_pre_out_s_11_0),.LO(acc_i_2[6:6]));
defparam desc468.INIT=32'h33011300;
complex_mult_pipe_prod_inj cp_mult(.mult_out_r(mult_out_r[11:0]),.mult_out_i(mult_out_i[11:0]),.in_a_r_reg(in_a_r_reg[11:0]),.in_b_r_reg(in_b_r_reg[11:0]),.in_a_i_reg(in_a_i_reg[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.clk(clk));
add_subZ0_add_r_inj add_r(.mult_out_r(mult_out_r[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.un2_pre_out_10(un2_pre_out_0[10:10]),.un2_pre_out_9(un2_pre_out[9:9]),.un2_pre_out_7(un2_pre_out[7:7]),.un2_pre_out_6(un2_pre_out[6:6]),.un2_pre_out_5(un2_pre_out[5:5]),.un2_pre_out_4(un2_pre_out[4:4]),.un2_pre_out_3(un2_pre_out[3:3]),.un2_pre_out_2(un2_pre_out[2:2]),.un2_pre_out_1(un2_pre_out[1:1]),.acc_clear(acc_clear),.un2_pre_out_s_11(un2_pre_out_s_11),.N_26_i(N_26_i),.N_20_i(N_20_i));
add_subZ0_add_r_1_inj add_i(.mult_out_i(mult_out_i[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.un2_pre_out_10(un2_pre_out[10:10]),.un2_pre_out_9(un2_pre_out_0[9:9]),.un2_pre_out_8(un2_pre_out[8:8]),.un2_pre_out_7(un2_pre_out_0[7:7]),.un2_pre_out_6(un2_pre_out_0[6:6]),.un2_pre_out_5(un2_pre_out_0[5:5]),.un2_pre_out_4(un2_pre_out_0[4:4]),.un2_pre_out_3(un2_pre_out_0[3:3]),.un2_pre_out_2(un2_pre_out_0[2:2]),.un2_pre_out_1(un2_pre_out_0[1:1]),.un2_pre_out_s_11_0(un2_pre_out_s_11_0));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT4 desc469(.I0(in_counter[1:1]),.I1(in_counter[2:2]),.I2(state[0:0]),.I3(un1_state_4_0_0_lut6_2_O6),.O(in_counter_5_43_i_i_a2));
defparam desc469.INIT=16'hA0CC;
LUT3 desc470(.I0(in_counter[0:0]),.I1(state[0:0]),.I2(un1_state_4_0_0_lut6_2_O6),.O(state_i_0));
defparam desc470.INIT=8'h3A;
LUT4 desc471(.I0(pipe_counter[1:1]),.I1(pipe_counter[2:2]),.I2(state[0:0]),.I3(un1_state_8_0_0_a2_lut6_2_O5),.O(pipe_counter_4_0_a2[2:2]));
defparam desc471.INIT=16'h0ACC;
LUT4 desc472(.I0(pipe_counter[0:0]),.I1(pipe_counter[1:1]),.I2(state[0:0]),.I3(un1_state_8_0_0_a2_lut6_2_O5),.O(pipe_counter_4_0_a2[1:1]));
defparam desc472.INIT=16'h0ACC;
LUT2 un7_acc_enable_lut6_2_o6(.I0(acc_enable),.I1(acc_clear),.O(un7_acc_enable_lut6_2_O6));
defparam un7_acc_enable_lut6_2_o6.INIT=4'hE;
LUT4 un7_acc_enable_lut6_2_o5(.I0(state[1:1]),.I1(state[0:0]),.I2(acc_clear),.I3(start_inner_prod),.O(acc_clear_0));
defparam un7_acc_enable_lut6_2_o5.INIT=16'hB1A0;
LUT4 un1_state_8_0_0_a2_lut6_2_o6(.I0(in_counter[2:2]),.I1(in_counter[0:0]),.I2(state[0:0]),.I3(red_mat_reg),.O(in_reg_enable_fsm_0_sqmuxa));
defparam un1_state_8_0_0_a2_lut6_2_o6.INIT=16'hC0A0;
LUT5 un1_state_8_0_0_a2_lut6_2_o5(.I0(in_counter[2:2]),.I1(in_counter[0:0]),.I2(state[1:1]),.I3(state[0:0]),.I4(red_mat_reg),.O(un1_state_8_0_0_a2_lut6_2_O5));
defparam un1_state_8_0_0_a2_lut6_2_o5.INIT=32'hFCF0FAF0;
LUT3 un1_state_4_0_0_lut6_2_o6(.I0(state[1:1]),.I1(state[0:0]),.I2(start_inner_prod),.O(un1_state_4_0_0_lut6_2_O6));
defparam un1_state_4_0_0_lut6_2_o6.INIT=8'hDC;
LUT4 un1_state_4_0_0_lut6_2_o5(.I0(acc_enable),.I1(pipe_counter[2:2]),.I2(state[1:1]),.I3(state[0:0]),.O(acc_enable_0));
defparam un1_state_4_0_0_lut6_2_o5.INIT=16'hFF2A;
LUT4 desc473(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out_s_11_0),.O(acc_i_2[11:11]));
defparam desc473.INIT=16'h3220;
LUT5 desc474(.I0(mult_out_i[11:11]),.I1(acc_clear),.I2(out_inner_prod_i[11:11]),.I3(un2_pre_out[10:10]),.I4(un2_pre_out_s_11_0),.O(acc_i_2[10:10]));
defparam desc474.INIT=32'h33011300;
endmodule
module inv_sqrt_inj (out_inner_prod_r,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_8,out_inv_sqrt_7,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_11,out_inv_sqrt_0,done_inv_sqrt,clk,rst,start_inv_sqrt,N_434_i,N_431_i,N_428_i,N_425_i,p_output_reg_pipe_13_Z_p_O_FDshifterZ0_,p_output_reg_pipe_12_Z_p_O_FDshifterZ0_,p_output_reg_pipe_Z_p_O_FDshifterZ0_,p_desc951_p_O_FDE,p_desc952_p_O_FDE,p_desc953_p_O_FDE,p_desc954_p_O_FDE,p_desc955_p_O_FDE,p_desc956_p_O_FDE,p_desc957_p_O_FDE,p_desc958_p_O_FDE,p_desc959_p_O_FDE,p_desc960_p_O_FDE,p_desc961_p_O_FDE,p_desc962_p_O_FDE,p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_,p_output_reg_pipe_Z_p_O_FDRE,p_output_reg_pipe_3_Z_p_O_FDRE,p_output_reg_pipe_6_Z_p_O_FDRE,p_output_reg_pipe_9_Z_p_O_FDRE,p_output_reg_pipe_12_Z_p_O_FDRE,p_output_reg_pipe_15_Z_p_O_FDRE,p_output_reg_pipe_16_Z_p_O_FDRE,p_output_reg_pipe_17_Z_p_O_FDRE,p_output_reg_pipe_18_Z_p_O_FDRE,p_output_reg_pipe_21_Z_p_O_FDRE,p_done_Z_p_O_FDC,p_desc946_p_O_FDC,p_desc947_p_O_FDC,p_desc948_p_O_FDC,p_desc949_p_O_FDC,p_desc950_p_O_FDC);
input [11:0] out_inner_prod_r ;
output out_inv_sqrt_9 ;
output out_inv_sqrt_10 ;
output out_inv_sqrt_8 ;
output out_inv_sqrt_7 ;
output out_inv_sqrt_2 ;
output out_inv_sqrt_1 ;
output out_inv_sqrt_11 ;
output out_inv_sqrt_0 ;
output done_inv_sqrt ;
input clk ;
input rst ;
input start_inv_sqrt ;
output N_434_i ;
output N_431_i ;
output N_428_i ;
output N_425_i ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_11 ;
wire out_inv_sqrt_0 ;
wire done_inv_sqrt ;
wire clk ;
wire rst ;
wire start_inv_sqrt ;
wire N_434_i ;
wire N_431_i ;
wire N_428_i ;
wire N_425_i ;
wire [2:2] ret_val_m10 ;
wire [3:1] ret_val ;
wire [11:11] un1_poly_odd_s_lut6_2_O6 ;
wire [11:0] input_reg ;
wire [3:0] counter ;
wire state ;
wire [3:1] counter_4 ;
wire [11:0] un14_pos_outputf ;
wire [11:0] pre_outputf ;
wire [1:1] out_shift_amount ;
wire [6:5] un7_output_2_1 ;
wire [6:5] un11_output ;
wire [11:0] pre_output ;
wire [7:1] un26_output ;
wire [7:4] un1_input_shifted ;
wire state_i ;
wire [11:1] un14_pos_output ;
wire [9:9] un11_output_6_d_0 ;
wire [11:0] z_5 ;
wire [3:3] ret_val_m2 ;
wire [1:1] ret_val_d_a1 ;
wire [1:1] ret_val_d_a0 ;
wire [10:7] un1_poly_odd ;
wire [10:9] un7 ;
wire [6:2] input_shifted ;
wire ret_val_d_0 ;
wire [1:1] shift_amount_1 ;
wire [2:2] shift_amount_1_i ;
wire [11:11] z_5_i ;
wire [19:9] un8_rnd_out_un0_P ;
wire [23:23] pre_out ;
wire [14:14] un20_output_2 ;
wire [11:11] un1_poly_odd_d ;
wire [6:6] un26_output_0_iv_3 ;
wire [6:6] un26_output_0_iv_2_0 ;
wire [4:4] output_d ;
wire [6:6] un7_output_2_0_0 ;
wire [6:6] un1_poly_odd_i ;
wire [11:0] mult1_out ;
wire [11:0] mult2_out ;
wire N_454 ;
wire un3_shift_right_c2_0_0_a0_1 ;
wire un9_0_axb_8 ;
wire VCC ;
wire m9_a1_1 ;
wire GND ;
wire N_439 ;
wire done ;
wire output_reg_pipe_11 ;
wire N_419 ;
wire un3_shift_right ;
wire z_5_axb_5 ;
wire N_71 ;
wire N_50_i ;
wire output_reg_pipe_12_RNIPJ901_O6 ;
wire N_420 ;
wire output_reg_pipe_17 ;
wire z_axb_0_i ;
wire un9_0_s_2 ;
wire m9_0_0 ;
wire CO1 ;
wire N_62 ;
wire z_5_8_d ;
wire N_414 ;
wire N_417 ;
wire N_33 ;
wire N_31 ;
wire z_5_axb_10 ;
wire un1_apply_nrlt8_1 ;
wire SUM1_0_i_a2_a0_1 ;
wire SUM1_0_i_1_1 ;
wire ret_val_ss0 ;
wire N_458 ;
wire N_378 ;
wire N_13_0 ;
wire N_410 ;
wire N_413 ;
wire N_18_0 ;
wire z_5_axb_7 ;
wire N_80 ;
wire N_51 ;
wire z_5_axb_3 ;
wire N_65 ;
wire un9_0_o5_2 ;
wire N_72 ;
wire un9_0_axb_1 ;
wire un9_0_o5_1 ;
wire un9_0_cry_0_RNO ;
wire N_100_i ;
wire N_79 ;
wire N_50 ;
wire z_5_axb_2 ;
wire un9_0_axb_3 ;
wire un9_0_axb_2 ;
wire ret_val_sm0 ;
wire un4_overflow_2 ;
wire get_m8_0_o4_2 ;
wire N_441 ;
wire un3_shift_right_axb0_i ;
wire un9_0_cry_0_cy ;
wire ret_val_ss3 ;
wire un4_overflow_0 ;
wire PATTERNDETECT_15 ;
wire un2_output_3 ;
wire z_axb_10 ;
wire un1_apply_nrlt7 ;
wire z_axb_9 ;
wire z_axb_8 ;
wire z_axb_7 ;
wire z_axb_6 ;
wire z_axb_5 ;
wire z_axb_4 ;
wire z_axb_3 ;
wire z_axb_2 ;
wire z_axb_1 ;
wire z_axb_0 ;
wire N_45 ;
wire N_70 ;
wire N_73 ;
wire un20_output_0_0_a2_0_0_lut6_2_O5 ;
wire z_5_axb_8 ;
wire un9_0_axb_0 ;
wire N_56 ;
wire N_49 ;
wire z_5_axb_1 ;
wire N_33_0 ;
wire z_5_axb_4 ;
wire z_5_axb_6 ;
wire z_5_axb_9 ;
wire z_5_cry_10 ;
wire z_5_cry_9 ;
wire z_5_cry_8 ;
wire z_5_cry_7 ;
wire z_5_cry_6 ;
wire z_5_cry_5 ;
wire z_5_cry_4 ;
wire z_5_cry_3 ;
wire z_5_cry_2 ;
wire z_5_cry_1 ;
wire z_5_cry_0 ;
wire z_cry_10 ;
wire z_cry_9 ;
wire z_cry_8 ;
wire z_cry_7 ;
wire z_cry_6 ;
wire z_cry_5 ;
wire z_cry_4 ;
wire z_cry_3 ;
wire z_cry_2 ;
wire z_cry_1 ;
wire z_cry_0 ;
wire un9_0_cry_7 ;
wire un9_0_s_8 ;
wire un9_0_cry_6 ;
wire un9_0_s_7 ;
wire N_2502_i ;
wire un9_0_cry_5 ;
wire un9_0_s_6 ;
wire un9_0_cry_4 ;
wire un9_0_s_5 ;
wire un9_0_axb_4 ;
wire un9_0_cry_3 ;
wire un9_0_s_4 ;
wire un9_0_cry_2 ;
wire un9_0_s_3 ;
wire un9_0_cry_1 ;
wire un9_0_cry_0 ;
wire un9_0_s_1 ;
wire un9_0_s_0 ;
input p_output_reg_pipe_13_Z_p_O_FDshifterZ0_ ;
input p_output_reg_pipe_12_Z_p_O_FDshifterZ0_ ;
input p_output_reg_pipe_Z_p_O_FDshifterZ0_ ;
input p_desc951_p_O_FDE ;
input p_desc952_p_O_FDE ;
input p_desc953_p_O_FDE ;
input p_desc954_p_O_FDE ;
input p_desc955_p_O_FDE ;
input p_desc956_p_O_FDE ;
input p_desc957_p_O_FDE ;
input p_desc958_p_O_FDE ;
input p_desc959_p_O_FDE ;
input p_desc960_p_O_FDE ;
input p_desc961_p_O_FDE ;
input p_desc962_p_O_FDE ;
input p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_ ;
input p_output_reg_pipe_Z_p_O_FDRE ;
input p_output_reg_pipe_3_Z_p_O_FDRE ;
input p_output_reg_pipe_6_Z_p_O_FDRE ;
input p_output_reg_pipe_9_Z_p_O_FDRE ;
input p_output_reg_pipe_12_Z_p_O_FDRE ;
input p_output_reg_pipe_15_Z_p_O_FDRE ;
input p_output_reg_pipe_16_Z_p_O_FDRE ;
input p_output_reg_pipe_17_Z_p_O_FDRE ;
input p_output_reg_pipe_18_Z_p_O_FDRE ;
input p_output_reg_pipe_21_Z_p_O_FDRE ;
input p_done_Z_p_O_FDC ;
input p_desc946_p_O_FDC ;
input p_desc947_p_O_FDC ;
input p_desc948_p_O_FDC ;
input p_desc949_p_O_FDC ;
input p_desc950_p_O_FDC ;
// instances
LUT4 desc944(.I0(un3_shift_right),.I1(un7_output_2_1[5:5]),.I2(un11_output[5:5]),.I3(pre_output[6:6]),.O(z_5_axb_5));
defparam desc944.INIT=16'h27D8;
LUT4 desc945(.I0(N_71),.I1(un26_output[4:4]),.I2(un3_shift_right),.I3(un9_0_axb_8),.O(un1_input_shifted[7:7]));
defparam desc945.INIT=16'hFFAC;
p_O_FDC done_Z(.Q(done_inv_sqrt),.D(done),.C(clk),.CLR(rst),.E(p_done_Z_p_O_FDC));
p_O_FDC desc946(.Q(counter[0:0]),.D(state_i),.C(clk),.CLR(rst),.E(p_desc946_p_O_FDC));
p_O_FDC desc947(.Q(counter[1:1]),.D(counter_4[1:1]),.C(clk),.CLR(rst),.E(p_desc947_p_O_FDC));
p_O_FDC desc948(.Q(counter[2:2]),.D(counter_4[2:2]),.C(clk),.CLR(rst),.E(p_desc948_p_O_FDC));
p_O_FDC desc949(.Q(counter[3:3]),.D(counter_4[3:3]),.C(clk),.CLR(rst),.E(p_desc949_p_O_FDC));
p_O_FDC desc950(.Q(state),.D(N_50_i),.C(clk),.CLR(rst),.E(p_desc950_p_O_FDC));
p_O_FDE desc951(.Q(input_reg[11:11]),.D(out_inner_prod_r[11:11]),.C(clk),.CE(start_inv_sqrt),.E(p_desc951_p_O_FDE));
p_O_FDE desc952(.Q(input_reg[10:10]),.D(out_inner_prod_r[10:10]),.C(clk),.CE(start_inv_sqrt),.E(p_desc952_p_O_FDE));
p_O_FDE desc953(.Q(input_reg[9:9]),.D(out_inner_prod_r[9:9]),.C(clk),.CE(start_inv_sqrt),.E(p_desc953_p_O_FDE));
p_O_FDE desc954(.Q(input_reg[8:8]),.D(out_inner_prod_r[8:8]),.C(clk),.CE(start_inv_sqrt),.E(p_desc954_p_O_FDE));
p_O_FDE desc955(.Q(input_reg[7:7]),.D(out_inner_prod_r[7:7]),.C(clk),.CE(start_inv_sqrt),.E(p_desc955_p_O_FDE));
p_O_FDE desc956(.Q(input_reg[6:6]),.D(out_inner_prod_r[6:6]),.C(clk),.CE(start_inv_sqrt),.E(p_desc956_p_O_FDE));
p_O_FDE desc957(.Q(input_reg[5:5]),.D(out_inner_prod_r[5:5]),.C(clk),.CE(start_inv_sqrt),.E(p_desc957_p_O_FDE));
p_O_FDE desc958(.Q(input_reg[4:4]),.D(out_inner_prod_r[4:4]),.C(clk),.CE(start_inv_sqrt),.E(p_desc958_p_O_FDE));
p_O_FDE desc959(.Q(input_reg[3:3]),.D(out_inner_prod_r[3:3]),.C(clk),.CE(start_inv_sqrt),.E(p_desc959_p_O_FDE));
p_O_FDE desc960(.Q(input_reg[2:2]),.D(out_inner_prod_r[2:2]),.C(clk),.CE(start_inv_sqrt),.E(p_desc960_p_O_FDE));
p_O_FDE desc961(.Q(input_reg[1:1]),.D(out_inner_prod_r[1:1]),.C(clk),.CE(start_inv_sqrt),.E(p_desc961_p_O_FDE));
p_O_FDE desc962(.Q(input_reg[0:0]),.D(out_inner_prod_r[0:0]),.C(clk),.CE(start_inv_sqrt),.E(p_desc962_p_O_FDE));
p_O_FDRE output_reg_pipe_Z(.Q(pre_outputf[1:1]),.D(pre_output[1:1]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_Z_p_O_FDRE));
FDSE output_reg_pipe_1_Z(.Q(un14_pos_outputf[1:1]),.D(un14_pos_output[1:1]),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
p_O_FDRE output_reg_pipe_3_Z(.Q(pre_outputf[2:2]),.D(pre_output[2:2]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_3_Z_p_O_FDRE));
FDSE output_reg_pipe_4_Z(.Q(un14_pos_outputf[2:2]),.D(un14_pos_output[2:2]),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
p_O_FDRE output_reg_pipe_6_Z(.Q(pre_outputf[7:7]),.D(pre_output[7:7]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_6_Z_p_O_FDRE));
FDSE output_reg_pipe_7_Z(.Q(un14_pos_outputf[7:7]),.D(un14_pos_output[7:7]),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
p_O_FDRE output_reg_pipe_9_Z(.Q(pre_outputf[8:8]),.D(pre_output[8:8]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_9_Z_p_O_FDRE));
FDSE output_reg_pipe_10_Z(.Q(un14_pos_outputf[8:8]),.D(un14_pos_output[8:8]),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
FDSE output_reg_pipe_11_Z(.Q(output_reg_pipe_11),.D(N_420),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
p_O_FDRE output_reg_pipe_12_Z(.Q(pre_outputf[10:10]),.D(pre_output[10:10]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_12_Z_p_O_FDRE));
FDSE output_reg_pipe_13_Z(.Q(un14_pos_outputf[10:10]),.D(un14_pos_output[10:10]),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
p_O_FDRE output_reg_pipe_15_Z(.Q(pre_outputf[11:11]),.D(pre_output[11:11]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_15_Z_p_O_FDRE));
p_O_FDRE output_reg_pipe_16_Z(.Q(un14_pos_outputf[11:11]),.D(un14_pos_output[11:11]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_16_Z_p_O_FDRE));
p_O_FDRE output_reg_pipe_17_Z(.Q(output_reg_pipe_17),.D(N_420),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_17_Z_p_O_FDRE));
p_O_FDRE output_reg_pipe_18_Z(.Q(pre_outputf[0:0]),.D(pre_output[0:0]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_18_Z_p_O_FDRE));
FDSE output_reg_pipe_19_Z(.Q(un14_pos_outputf[0:0]),.D(z_axb_0_i),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
p_O_FDRE output_reg_pipe_21_Z(.Q(pre_outputf[9:9]),.D(pre_output[9:9]),.C(clk),.R(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt),.E(p_output_reg_pipe_21_Z_p_O_FDRE));
FDSE output_reg_pipe_22_Z(.Q(un14_pos_outputf[9:9]),.D(un14_pos_output[9:9]),.C(clk),.S(output_reg_pipe_12_RNIPJ901_O6),.CE(done_inv_sqrt));
LUT4 desc963(.I0(ret_val[3:3]),.I1(m9_a1_1),.I2(un9_0_s_2),.I3(m9_0_0),.O(pre_output[0:0]));
defparam desc963.INIT=16'h5540;
LUT5 desc964(.I0(ret_val[2:2]),.I1(ret_val[3:3]),.I2(CO1),.I3(un11_output_6_d_0[9:9]),.I4(N_62),.O(z_5_8_d));
defparam desc964.INIT=32'hFE24DA00;
LUT5 desc965(.I0(ret_val[3:3]),.I1(N_414),.I2(N_417),.I3(N_33),.I4(N_31),.O(z_5_axb_10));
defparam desc965.INIT=32'h0F0FF2F8;
LUT5 desc966(.I0(ret_val[3:3]),.I1(m9_a1_1),.I2(un9_0_s_2),.I3(m9_0_0),.I4(pre_output[1:1]),.O(z_5[0:0]));
defparam desc966.INIT=32'hAABF5540;
LUT4 desc967(.I0(un3_shift_right),.I1(un7_output_2_1[6:6]),.I2(un11_output[6:6]),.I3(pre_output[7:7]),.O(un1_apply_nrlt8_1));
defparam desc967.INIT=16'hD800;
LUT6 desc968(.I0(input_reg[3:3]),.I1(input_reg[4:4]),.I2(input_reg[5:5]),.I3(input_reg[6:6]),.I4(ret_val_m2[3:3]),.I5(N_454),.O(ret_val[3:3]));
defparam desc968.INIT=64'h0003000200000000;
LUT6 desc969(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(input_reg[10:10]),.I3(input_reg[11:11]),.I4(ret_val_m2[3:3]),.I5(SUM1_0_i_a2_a0_1),.O(SUM1_0_i_1_1));
defparam desc969.INIT=64'hFFF0FFF1FFF0FFF0;
LUT6 desc970(.I0(ret_val_ss0),.I1(ret_val_d_a1[1:1]),.I2(N_458),.I3(ret_val_d_a0[1:1]),.I4(N_454),.I5(un9_0_axb_8),.O(N_378));
defparam desc970.INIT=64'h5F5CFFCCA0A30033;
LUT6 desc971(.I0(ret_val_ss0),.I1(ret_val_d_a1[1:1]),.I2(N_458),.I3(ret_val_d_a0[1:1]),.I4(N_454),.I5(un9_0_axb_8),.O(CO1));
defparam desc971.INIT=64'h5F5CFFCC00000000;
LUT6 desc972(.I0(ret_val[3:3]),.I1(CO1),.I2(N_13_0),.I3(N_410),.I4(N_413),.I5(N_18_0),.O(z_5_axb_7));
defparam desc972.INIT=64'h08807FF77FF70880;
LUT6 desc973(.I0(ret_val[3:3]),.I1(CO1),.I2(un3_shift_right),.I3(N_80),.I4(N_51),.I5(pre_output[4:4]),.O(z_5_axb_3));
defparam desc973.INIT=64'h080FF8FFF7F00700;
LUT6 un9_0_o5_2_cZ(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_65),.I3(un26_output[7:7]),.I4(un1_input_shifted[5:5]),.I5(un1_poly_odd[9:9]),.O(un9_0_o5_2));
defparam un9_0_o5_2_cZ.INIT=64'hFFFF5D7F5D7F0000;
LUT6 un9_0_axb_1_cZ(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_72),.I3(un26_output[5:5]),.I4(un7[10:10]),.I5(un1_poly_odd[10:10]),.O(un9_0_axb_1));
defparam un9_0_axb_1_cZ.INIT=64'h5140AEBFAEBF5140;
LUT6 un9_0_o5_1_cZ(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_72),.I3(un26_output[5:5]),.I4(un7[10:10]),.I5(un1_poly_odd[10:10]),.O(un9_0_o5_1));
defparam un9_0_o5_1_cZ.INIT=64'hFFFF514051400000;
LUT4 un9_0_cry_0_RNO_cZ(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_72),.I3(un26_output[5:5]),.O(un9_0_cry_0_RNO));
defparam un9_0_cry_0_RNO_cZ.INIT=16'h082A;
LUT5 un9_0_cry_4_RNO(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_72),.I3(un26_output[5:5]),.I4(input_shifted[6:6]),.O(un1_poly_odd[7:7]));
defparam un9_0_cry_4_RNO.INIT=32'h0415AEBF;
LUT6 desc974(.I0(N_100_i),.I1(un3_shift_right),.I2(N_79),.I3(N_50),.I4(N_80),.I5(N_51),.O(z_5_axb_2));
defparam desc974.INIT=64'h02CE20ECCE02EC20;
LUT6 un9_0_axb_3_cZ(.I0(un9_0_axb_8),.I1(un1_input_shifted[4:4]),.I2(un7[9:9]),.I3(un1_poly_odd[8:8]),.I4(un1_input_shifted[5:5]),.I5(un1_poly_odd[9:9]),.O(un9_0_axb_3));
defparam un9_0_axb_3_cZ.INIT=64'h6699699669969966;
LUT6 un9_0_axb_2_cZ(.I0(un1_input_shifted[6:6]),.I1(un7[9:9]),.I2(un1_input_shifted[5:5]),.I3(un7[10:10]),.I4(un1_poly_odd[10:10]),.I5(un1_poly_odd[9:9]),.O(un9_0_axb_2));
defparam un9_0_axb_2_cZ.INIT=64'h3C6969C3C396963C;
LUT6 desc975(.I0(ret_val_sm0),.I1(un4_overflow_2),.I2(get_m8_0_o4_2),.I3(ret_val_ss0),.I4(N_441),.I5(ret_val_d_0),.O(un3_shift_right_axb0_i));
defparam desc975.INIT=64'h00000408FFFFF7FB;
MUXCY_L un9_0_cry_0_cy_cZ(.DI(GND),.CI(VCC),.S(un1_input_shifted[7:7]),.LO(un9_0_cry_0_cy));
LUT5 desc976(.I0(ret_val_ss0),.I1(ret_val_d_a1[1:1]),.I2(N_458),.I3(ret_val_d_a0[1:1]),.I4(N_454),.O(ret_val[1:1]));
defparam desc976.INIT=32'h5F5CFFCC;
LUT4 desc977(.I0(N_454),.I1(SUM1_0_i_1_1),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(shift_amount_1[1:1]));
defparam desc977.INIT=16'hCFEC;
LUT5 desc978(.I0(N_454),.I1(un3_shift_right_c2_0_0_a0_1),.I2(ret_val[2:2]),.I3(ret_val[1:1]),.I4(un9_0_axb_8),.O(shift_amount_1_i[2:2]));
defparam desc978.INIT=32'h0F7D7D7D;
LUT4 desc979(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_65),.I3(un26_output[7:7]),.O(un1_input_shifted[4:4]));
defparam desc979.INIT=16'hFBEA;
LUT4 desc980(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_65),.I3(un26_output[7:7]),.O(un7[9:9]));
defparam desc980.INIT=16'h5D7F;
LUT1_L desc981(.I0(z_5[11:11]),.LO(z_5_i[11:11]));
defparam desc981.INIT=2'h1;
LUT2 desc982(.I0(input_reg[1:1]),.I1(input_reg[2:2]),.O(ret_val_sm0));
defparam desc982.INIT=4'hE;
LUT2 desc983(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.O(un4_overflow_2));
defparam desc983.INIT=4'h1;
LUT1_L desc984(.I0(state),.LO(state_i));
defparam desc984.INIT=2'h1;
LUT3 desc985(.I0(un14_pos_outputf[11:11]),.I1(output_reg_pipe_17),.I2(pre_outputf[11:11]),.O(out_inv_sqrt_11));
defparam desc985.INIT=8'hB8;
LUT3 desc986(.I0(un14_pos_outputf[0:0]),.I1(pre_outputf[0:0]),.I2(output_reg_pipe_11),.O(out_inv_sqrt_0));
defparam desc986.INIT=8'hAC;
LUT4 desc987(.I0(input_reg[3:3]),.I1(input_reg[7:7]),.I2(input_reg[11:11]),.I3(input_reg[6:6]),.O(get_m8_0_o4_2));
defparam desc987.INIT=16'hFFFE;
LUT4 desc988(.I0(input_reg[3:3]),.I1(input_reg[4:4]),.I2(input_reg[5:5]),.I3(input_reg[6:6]),.O(N_458));
defparam desc988.INIT=16'h0001;
LUT3 desc989(.I0(input_reg[0:0]),.I1(input_reg[1:1]),.I2(input_reg[2:2]),.O(ret_val_m2[3:3]));
defparam desc989.INIT=8'hFE;
LUT4 desc990(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[10:10]),.I3(input_reg[11:11]),.O(ret_val_d_a1[1:1]));
defparam desc990.INIT=16'h000E;
LUT3 desc991(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[10:10]),.O(N_441));
defparam desc991.INIT=8'hFE;
LUT3_L desc992(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(input_reg[6:6]),.LO(ret_val_ss3));
defparam desc992.INIT=8'hF2;
LUT3 desc993(.I0(input_reg[0:0]),.I1(input_reg[1:1]),.I2(input_reg[2:2]),.O(ret_val_ss0));
defparam desc993.INIT=8'hF1;
LUT3_L desc994(.I0(counter[3:3]),.I1(state),.I2(start_inv_sqrt),.LO(N_50_i));
defparam desc994.INIT=8'h74;
LUT5_L desc995(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[3:3]),.I3(input_reg[7:7]),.I4(input_reg[6:6]),.LO(SUM1_0_i_a2_a0_1));
defparam desc995.INIT=32'h00000001;
LUT5 desc996(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[7:7]),.I3(input_reg[10:10]),.I4(input_reg[11:11]),.O(N_454));
defparam desc996.INIT=32'h00000001;
LUT6 desc997(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(input_reg[7:7]),.I3(input_reg[10:10]),.I4(input_reg[11:11]),.I5(input_reg[6:6]),.O(ret_val_d_a0[1:1]));
defparam desc997.INIT=64'h000000000000000E;
LUT6 desc998(.I0(input_reg[2:2]),.I1(input_reg[3:3]),.I2(input_reg[7:7]),.I3(input_reg[6:6]),.I4(N_439),.I5(un4_overflow_2),.O(un4_overflow_0));
defparam desc998.INIT=64'h0000000100000000;
LUT6 desc999(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[7:7]),.I3(input_reg[10:10]),.I4(input_reg[11:11]),.I5(ret_val_ss3),.O(ret_val_d_0));
defparam desc999.INIT=64'h0000FF450000FF44;
LUT6 desc1000(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(input_reg[7:7]),.I3(input_reg[11:11]),.I4(input_reg[6:6]),.I5(N_441),.O(ret_val[2:2]));
defparam desc1000.INIT=64'h0000000000FF00FE;
LUT6 desc1001(.I0(input_reg[3:3]),.I1(input_reg[7:7]),.I2(input_reg[6:6]),.I3(un4_overflow_2),.I4(ret_val_m2[3:3]),.I5(N_441),.O(un3_shift_right_c2_0_0_a0_1));
defparam desc1001.INIT=64'h00000F0000000D00;
LUT5_L desc1002(.I0(z_5[10:10]),.I1(un8_rnd_out_un0_P[19:19]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_10));
defparam desc1002.INIT=32'h99A995A5;
LUT6 desc1003(.I0(pre_output[0:0]),.I1(pre_output[1:1]),.I2(pre_output[2:2]),.I3(pre_output[4:4]),.I4(pre_output[3:3]),.I5(pre_output[5:5]),.O(un1_apply_nrlt7));
defparam desc1003.INIT=64'hFFFFFFFFFF00E000;
LUT6 desc1004(.I0(ret_val_sm0),.I1(un4_overflow_2),.I2(get_m8_0_o4_2),.I3(ret_val_ss0),.I4(N_441),.I5(ret_val_d_0),.O(un9_0_axb_8));
defparam desc1004.INIT=64'hFFFFFBF700000804;
LUT5_L desc1005(.I0(z_5[9:9]),.I1(un8_rnd_out_un0_P[18:18]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_9));
defparam desc1005.INIT=32'h99599A5A;
LUT5_L desc1006(.I0(z_5[8:8]),.I1(un8_rnd_out_un0_P[17:17]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_8));
defparam desc1006.INIT=32'h99599A5A;
LUT5_L desc1007(.I0(z_5[7:7]),.I1(un8_rnd_out_un0_P[16:16]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_7));
defparam desc1007.INIT=32'h99599A5A;
LUT5_L desc1008(.I0(z_5[6:6]),.I1(un8_rnd_out_un0_P[15:15]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_6));
defparam desc1008.INIT=32'h99599A5A;
LUT5_L desc1009(.I0(z_5[5:5]),.I1(un8_rnd_out_un0_P[14:14]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_5));
defparam desc1009.INIT=32'h99599A5A;
LUT5_L desc1010(.I0(z_5[4:4]),.I1(un8_rnd_out_un0_P[13:13]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_4));
defparam desc1010.INIT=32'h99599A5A;
LUT5_L desc1011(.I0(z_5[3:3]),.I1(un8_rnd_out_un0_P[12:12]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_3));
defparam desc1011.INIT=32'h99599A5A;
LUT5_L desc1012(.I0(z_5[2:2]),.I1(un8_rnd_out_un0_P[11:11]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_2));
defparam desc1012.INIT=32'h99599A5A;
LUT5_L desc1013(.I0(z_5[1:1]),.I1(un8_rnd_out_un0_P[10:10]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_1));
defparam desc1013.INIT=32'h99599A5A;
LUT5 desc1014(.I0(z_5[0:0]),.I1(un8_rnd_out_un0_P[9:9]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.O(z_axb_0));
defparam desc1014.INIT=32'h99599A5A;
LUT5_L desc1015(.I0(z_5[0:0]),.I1(un8_rnd_out_un0_P[9:9]),.I2(pre_out[23:23]),.I3(PATTERNDETECT_15),.I4(un2_output_3),.LO(z_axb_0_i));
defparam desc1015.INIT=32'h66A665A5;
LUT5 desc1016(.I0(ret_val_m10[2:2]),.I1(N_454),.I2(un3_shift_right_c2_0_0_a0_1),.I3(ret_val[1:1]),.I4(un9_0_axb_8),.O(un3_shift_right));
defparam desc1016.INIT=32'h00D1D1D1;
LUT6 desc1017(.I0(input_reg[2:2]),.I1(un9_0_axb_8),.I2(un20_output_2[14:14]),.I3(N_45),.I4(shift_amount_1[1:1]),.I5(input_shifted[2:2]),.O(un1_poly_odd_d[11:11]));
defparam desc1017.INIT=64'h03331313CFFFDFDF;
LUT5 desc1018(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(input_shifted[2:2]),.I3(N_70),.I4(un26_output[3:3]),.O(un1_poly_odd[10:10]));
defparam desc1018.INIT=32'h058D27AF;
LUT4 desc1019(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_72),.I3(un26_output[5:5]),.O(un1_input_shifted[6:6]));
defparam desc1019.INIT=16'h5140;
LUT6 desc1020(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_70),.I3(N_71),.I4(un26_output[4:4]),.I5(un26_output[3:3]),.O(un1_poly_odd[9:9]));
defparam desc1020.INIT=64'h048C26AE159D37BF;
LUT6 desc1021(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_71),.I3(un26_output[4:4]),.I4(N_72),.I5(un26_output[5:5]),.O(un1_poly_odd[8:8]));
defparam desc1021.INIT=64'h04158C9D2637AEBF;
LUT5 desc1022(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_73),.I3(un26_output_0_iv_3[6:6]),.I4(un26_output_0_iv_2_0[6:6]),.O(un1_input_shifted[5:5]));
defparam desc1022.INIT=32'h51515140;
LUT5 desc1023(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_73),.I3(un26_output_0_iv_3[6:6]),.I4(un26_output_0_iv_2_0[6:6]),.O(un7[10:10]));
defparam desc1023.INIT=32'h0808082A;
LUT5 desc1024(.I0(un20_output_0_0_a2_0_0_lut6_2_O5),.I1(un3_shift_right),.I2(un11_output_6_d_0[9:9]),.I3(N_62),.I4(pre_output[8:8]),.O(z_5_axb_8));
defparam desc1024.INIT=32'hCDEF3210;
LUT5 desc1025(.I0(un9_0_axb_8),.I1(un1_poly_odd_s_lut6_2_O6[11:11]),.I2(un26_output[1:1]),.I3(un1_poly_odd_d[11:11]),.I4(input_shifted[5:5]),.O(un9_0_axb_0));
defparam desc1025.INIT=32'h3F0C95A6;
LUT5 desc1026(.I0(un20_output_2[14:14]),.I1(un3_shift_right),.I2(N_56),.I3(N_49),.I4(pre_output[2:2]),.O(z_5_axb_1));
defparam desc1026.INIT=32'h13DFEC20;
LUT5 desc1027(.I0(N_419),.I1(un3_shift_right),.I2(N_33_0),.I3(output_d[4:4]),.I4(pre_output[5:5]),.O(z_5_axb_4));
defparam desc1027.INIT=32'h087FF780;
LUT5 desc1028(.I0(un3_shift_right),.I1(un7_output_2_0_0[6:6]),.I2(un7_output_2_1[6:6]),.I3(un11_output[6:6]),.I4(pre_output[7:7]),.O(z_5_axb_6));
defparam desc1028.INIT=32'h2A7FD580;
LUT5 desc1029(.I0(un20_output_0_0_a2_0_0_lut6_2_O5),.I1(un3_shift_right),.I2(un11_output_6_d_0[9:9]),.I3(N_62),.I4(pre_output[10:10]),.O(z_5_axb_9));
defparam desc1029.INIT=32'hCDEF3210;
XORCY desc1030(.LI(pre_output[11:11]),.CI(z_5_cry_10),.O(z_5[11:11]));
XORCY desc1031(.LI(z_5_axb_10),.CI(z_5_cry_9),.O(z_5[10:10]));
MUXCY_L desc1032(.DI(pre_output[10:10]),.CI(z_5_cry_9),.S(z_5_axb_10),.LO(z_5_cry_10));
XORCY desc1033(.LI(z_5_axb_9),.CI(z_5_cry_8),.O(z_5[9:9]));
MUXCY_L desc1034(.DI(z_5_8_d),.CI(z_5_cry_8),.S(z_5_axb_9),.LO(z_5_cry_9));
XORCY desc1035(.LI(z_5_axb_8),.CI(z_5_cry_7),.O(z_5[8:8]));
MUXCY_L desc1036(.DI(z_5_8_d),.CI(z_5_cry_7),.S(z_5_axb_8),.LO(z_5_cry_8));
XORCY desc1037(.LI(z_5_axb_7),.CI(z_5_cry_6),.O(z_5[7:7]));
MUXCY_L desc1038(.DI(pre_output[7:7]),.CI(z_5_cry_6),.S(z_5_axb_7),.LO(z_5_cry_7));
XORCY desc1039(.LI(z_5_axb_6),.CI(z_5_cry_5),.O(z_5[6:6]));
MUXCY_L desc1040(.DI(pre_output[6:6]),.CI(z_5_cry_5),.S(z_5_axb_6),.LO(z_5_cry_6));
XORCY desc1041(.LI(z_5_axb_5),.CI(z_5_cry_4),.O(z_5[5:5]));
MUXCY_L desc1042(.DI(pre_output[5:5]),.CI(z_5_cry_4),.S(z_5_axb_5),.LO(z_5_cry_5));
XORCY desc1043(.LI(z_5_axb_4),.CI(z_5_cry_3),.O(z_5[4:4]));
MUXCY_L desc1044(.DI(pre_output[4:4]),.CI(z_5_cry_3),.S(z_5_axb_4),.LO(z_5_cry_4));
XORCY desc1045(.LI(z_5_axb_3),.CI(z_5_cry_2),.O(z_5[3:3]));
MUXCY_L desc1046(.DI(pre_output[3:3]),.CI(z_5_cry_2),.S(z_5_axb_3),.LO(z_5_cry_3));
XORCY desc1047(.LI(z_5_axb_2),.CI(z_5_cry_1),.O(z_5[2:2]));
MUXCY_L desc1048(.DI(pre_output[2:2]),.CI(z_5_cry_1),.S(z_5_axb_2),.LO(z_5_cry_2));
XORCY desc1049(.LI(z_5_axb_1),.CI(z_5_cry_0),.O(z_5[1:1]));
MUXCY_L desc1050(.DI(pre_output[1:1]),.CI(z_5_cry_0),.S(z_5_axb_1),.LO(z_5_cry_1));
MUXCY_L desc1051(.DI(pre_output[0:0]),.CI(GND),.S(z_5[0:0]),.LO(z_5_cry_0));
XORCY desc1052(.LI(z_5_i[11:11]),.CI(z_cry_10),.O(un14_pos_output[11:11]));
XORCY desc1053(.LI(z_axb_10),.CI(z_cry_9),.O(un14_pos_output[10:10]));
MUXCY_L desc1054(.DI(z_5[10:10]),.CI(z_cry_9),.S(z_axb_10),.LO(z_cry_10));
XORCY desc1055(.LI(z_axb_9),.CI(z_cry_8),.O(un14_pos_output[9:9]));
MUXCY_L desc1056(.DI(z_5[9:9]),.CI(z_cry_8),.S(z_axb_9),.LO(z_cry_9));
XORCY desc1057(.LI(z_axb_8),.CI(z_cry_7),.O(un14_pos_output[8:8]));
MUXCY_L desc1058(.DI(z_5[8:8]),.CI(z_cry_7),.S(z_axb_8),.LO(z_cry_8));
XORCY desc1059(.LI(z_axb_7),.CI(z_cry_6),.O(un14_pos_output[7:7]));
MUXCY_L desc1060(.DI(z_5[7:7]),.CI(z_cry_6),.S(z_axb_7),.LO(z_cry_7));
XORCY desc1061(.LI(z_axb_6),.CI(z_cry_5),.O(un14_pos_output[6:6]));
MUXCY_L desc1062(.DI(z_5[6:6]),.CI(z_cry_5),.S(z_axb_6),.LO(z_cry_6));
XORCY desc1063(.LI(z_axb_5),.CI(z_cry_4),.O(un14_pos_output[5:5]));
MUXCY_L desc1064(.DI(z_5[5:5]),.CI(z_cry_4),.S(z_axb_5),.LO(z_cry_5));
XORCY desc1065(.LI(z_axb_4),.CI(z_cry_3),.O(un14_pos_output[4:4]));
MUXCY_L desc1066(.DI(z_5[4:4]),.CI(z_cry_3),.S(z_axb_4),.LO(z_cry_4));
XORCY desc1067(.LI(z_axb_3),.CI(z_cry_2),.O(un14_pos_output[3:3]));
MUXCY_L desc1068(.DI(z_5[3:3]),.CI(z_cry_2),.S(z_axb_3),.LO(z_cry_3));
XORCY desc1069(.LI(z_axb_2),.CI(z_cry_1),.O(un14_pos_output[2:2]));
MUXCY_L desc1070(.DI(z_5[2:2]),.CI(z_cry_1),.S(z_axb_2),.LO(z_cry_2));
XORCY desc1071(.LI(z_axb_1),.CI(z_cry_0),.O(un14_pos_output[1:1]));
MUXCY_L desc1072(.DI(z_5[1:1]),.CI(z_cry_0),.S(z_axb_1),.LO(z_cry_1));
MUXCY_L desc1073(.DI(z_5[0:0]),.CI(VCC),.S(z_axb_0),.LO(z_cry_0));
XORCY un9_0_s_8_cZ(.LI(un9_0_axb_8),.CI(un9_0_cry_7),.O(un9_0_s_8));
XORCY un9_0_s_7_cZ(.LI(un3_shift_right_axb0_i),.CI(un9_0_cry_6),.O(un9_0_s_7));
MUXCY_L un9_0_cry_7_cZ(.DI(VCC),.CI(un9_0_cry_6),.S(un3_shift_right_axb0_i),.LO(un9_0_cry_7));
XORCY un9_0_s_6_cZ(.LI(N_2502_i),.CI(un9_0_cry_5),.O(un9_0_s_6));
MUXCY_L un9_0_cry_6_cZ(.DI(VCC),.CI(un9_0_cry_5),.S(N_2502_i),.LO(un9_0_cry_6));
XORCY un9_0_s_5_cZ(.LI(un1_poly_odd_i[6:6]),.CI(un9_0_cry_4),.O(un9_0_s_5));
MUXCY_L un9_0_cry_5_cZ(.DI(VCC),.CI(un9_0_cry_4),.S(un1_poly_odd_i[6:6]),.LO(un9_0_cry_5));
XORCY un9_0_s_4_cZ(.LI(un9_0_axb_4),.CI(un9_0_cry_3),.O(un9_0_s_4));
MUXCY_L un9_0_cry_4_cZ(.DI(un1_poly_odd[7:7]),.CI(un9_0_cry_3),.S(un9_0_axb_4),.LO(un9_0_cry_4));
XORCY un9_0_s_3_cZ(.LI(un9_0_axb_3),.CI(un9_0_cry_2),.O(un9_0_s_3));
MUXCY_L un9_0_cry_3_cZ(.DI(un9_0_o5_2),.CI(un9_0_cry_2),.S(un9_0_axb_3),.LO(un9_0_cry_3));
XORCY un9_0_s_2_cZ(.LI(un9_0_axb_2),.CI(un9_0_cry_1),.O(un9_0_s_2));
MUXCY_L un9_0_cry_2_cZ(.DI(un9_0_o5_1),.CI(un9_0_cry_1),.S(un9_0_axb_2),.LO(un9_0_cry_2));
XORCY un9_0_s_1_cZ(.LI(un9_0_axb_1),.CI(un9_0_cry_0),.O(un9_0_s_1));
MUXCY_L un9_0_cry_1_cZ(.DI(GND),.CI(un9_0_cry_0),.S(un9_0_axb_1),.LO(un9_0_cry_1));
XORCY un9_0_s_0_cZ(.LI(un9_0_axb_0),.CI(un9_0_cry_0_cy),.O(un9_0_s_0));
MUXCY_L un9_0_cry_0_cZ(.DI(un9_0_cry_0_RNO),.CI(un9_0_cry_0_cy),.S(un9_0_axb_0),.LO(un9_0_cry_0));
shifterZ1_inj in_shift(.ret_val(ret_val[3:1]),.un20_output_2(un20_output_2[14:14]),.ret_val_m2(ret_val_m2[3:3]),.shift_amount_1(shift_amount_1[1:1]),.un26_output_0_iv_3(un26_output_0_iv_3[6:6]),.ret_val_d_a1(ret_val_d_a1[1:1]),.ret_val_d_a0(ret_val_d_a0[1:1]),.un26_output_6(un26_output[7:7]),.un26_output_2(un26_output[3:3]),.un26_output_4(un26_output[5:5]),.un26_output_3(un26_output[4:4]),.un26_output_0(un26_output[1:1]),.un1_poly_odd_i(un1_poly_odd_i[6:6]),.input_reg(input_reg[11:0]),.un26_output_0_iv_2_0_1(un26_output_0_iv_2_0[6:6]),.input_shifted_4(input_shifted[6:6]),.input_shifted_0(input_shifted[2:2]),.input_shifted_3(input_shifted[5:5]),.un1_input_shifted(un1_input_shifted[4:4]),.un1_poly_odd(un1_poly_odd[8:8]),.un9_0_axb_8(un9_0_axb_8),.un20_output_0_0_a2_0_0_lut6_2_O5(un20_output_0_0_a2_0_0_lut6_2_O5),.N_100_i(N_100_i),.N_65(N_65),.un3_shift_right(un3_shift_right),.N_2502_i(N_2502_i),.un4_overflow_2(un4_overflow_2),.N_454(N_454),.N_72(N_72),.ret_val_ss0(ret_val_ss0),.N_458(N_458),.N_45(N_45),.N_70(N_70),.N_73(N_73),.N_71(N_71),.N_441(N_441),.un9_0_axb_4(un9_0_axb_4));
shifterZ0_inj out_shift(.input_reg(input_reg[11:10]),.shift_amount_1(shift_amount_1[1:1]),.un14_pos_output(un14_pos_output[6:3]),.ret_val(ret_val[3:1]),.un11_output_6_d_0(un11_output_6_d_0[9:9]),.out_shift_amount(out_shift_amount[1:1]),.un7_output_2_0_0(un7_output_2_0_0[6:6]),.un7_output_2_1(un7_output_2_1[6:5]),.output_d(output_d[4:4]),.shift_amount_1_i(shift_amount_1_i[2:2]),.un11_output_1(un11_output[5:5]),.un11_output_2(un11_output[6:6]),.un20_output_2(un20_output_2[14:14]),.pre_output(pre_output[11:1]),.done_inv_sqrt(done_inv_sqrt),.un4_overflow_0(un4_overflow_0),.output_reg_pipe_12_RNIPJ901_O6(output_reg_pipe_12_RNIPJ901_O6),.un9_0_axb_8(un9_0_axb_8),.un9_0_s_6(un9_0_s_6),.un9_0_s_7(un9_0_s_7),.N_414(N_414),.N_33(N_33),.clk(clk),.N_420(N_420),.un3_shift_right(un3_shift_right),.N_410(N_410),.un9_0_s_5(un9_0_s_5),.un9_0_s_8(un9_0_s_8),.N_79(N_79),.N_50(N_50),.un9_0_s_4(un9_0_s_4),.un9_0_s_3(un9_0_s_3),.N_13_0(N_13_0),.N_100_i(N_100_i),.N_31(N_31),.N_18_0(N_18_0),.N_378(N_378),.N_33_0(N_33_0),.N_80(N_80),.N_51(N_51),.un9_0_s_0(un9_0_s_0),.un9_0_s_1(un9_0_s_1),.m9_0_0(m9_0_0),.N_417(N_417),.N_62(N_62),.N_454(N_454),.SUM1_0_i_1_1(SUM1_0_i_1_1),.N_56(N_56),.N_434_i(N_434_i),.N_431_i(N_431_i),.N_428_i(N_428_i),.N_425_i(N_425_i),.un9_0_s_2(un9_0_s_2),.N_419(N_419),.N_49(N_49),.N_413(N_413),.un20_output_0_0_a2_0_0_lut6_2_O5(un20_output_0_0_a2_0_0_lut6_2_O5),.un1_apply_nrlt8_1(un1_apply_nrlt8_1),.un1_apply_nrlt7(un1_apply_nrlt7),.p_output_reg_pipe_13_Z_p_O_FD(p_output_reg_pipe_13_Z_p_O_FDshifterZ0_),.p_output_reg_pipe_12_Z_p_O_FD(p_output_reg_pipe_12_Z_p_O_FDshifterZ0_),.p_output_reg_pipe_Z_p_O_FD(p_output_reg_pipe_Z_p_O_FDshifterZ0_),.p_output_reg_pipe_1_Z_p_O_FDE(p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_4_Z_p_O_FDE(p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_5_Z_p_O_FDE(p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_6_Z_p_O_FDE(p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_9_Z_p_O_FDE(p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_10_Z_p_O_FDE(p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_11_Z_p_O_FDE(p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_14_Z_p_O_FDE(p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_15_Z_p_O_FDE(p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_16_Z_p_O_FDE(p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_),.p_output_reg_pipe_19_Z_p_O_FDE(p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_));
multiplier_inj desc1074(.mult1_out(mult1_out[11:0]),.pre_output(pre_output[11:0]));
multiplier_1_inj desc1075(.mult2_out(mult2_out[11:0]),.pre_output(pre_output[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.start_inv_sqrt(start_inv_sqrt),.clk(clk));
desc940_inj desc1076(.un8_rnd_out_un0_P_9(un8_rnd_out_un0_P[9:9]),.un8_rnd_out_un0_P_10(un8_rnd_out_un0_P[10:10]),.un8_rnd_out_un0_P_11(un8_rnd_out_un0_P[11:11]),.un8_rnd_out_un0_P_12(un8_rnd_out_un0_P[12:12]),.un8_rnd_out_un0_P_13(un8_rnd_out_un0_P[13:13]),.un8_rnd_out_un0_P_14(un8_rnd_out_un0_P[14:14]),.un8_rnd_out_un0_P_15(un8_rnd_out_un0_P[15:15]),.un8_rnd_out_un0_P_16(un8_rnd_out_un0_P[16:16]),.un8_rnd_out_un0_P_17(un8_rnd_out_un0_P[17:17]),.un8_rnd_out_un0_P_18(un8_rnd_out_un0_P[18:18]),.un8_rnd_out_un0_P_19(un8_rnd_out_un0_P[19:19]),.mult1_out(mult1_out[11:0]),.mult2_out(mult2_out[11:0]),.pre_out_23(pre_out[23:23]),.un2_output_3(un2_output_3),.PATTERNDETECT_15(PATTERNDETECT_15));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT4 desc1077(.I0(N_454),.I1(ret_val[2:2]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(out_shift_amount[1:1]));
defparam desc1077.INIT=16'hC623;
LUT4 desc1078(.I0(N_454),.I1(ret_val[2:2]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(N_419));
defparam desc1078.INIT=16'h1DDC;
LUT2 desc1079(.I0(counter[1:1]),.I1(state),.O(counter_4[2:2]));
defparam desc1079.INIT=4'h8;
LUT2 desc1080(.I0(counter[2:2]),.I1(state),.O(counter_4[3:3]));
defparam desc1080.INIT=4'h8;
LUT3 desc1081(.I0(un14_pos_outputf[2:2]),.I1(pre_outputf[2:2]),.I2(output_reg_pipe_11),.O(out_inv_sqrt_2));
defparam desc1081.INIT=8'hAC;
LUT3 desc1082(.I0(un14_pos_outputf[1:1]),.I1(pre_outputf[1:1]),.I2(output_reg_pipe_11),.O(out_inv_sqrt_1));
defparam desc1082.INIT=8'hAC;
LUT3 desc1083(.I0(un14_pos_outputf[8:8]),.I1(pre_outputf[8:8]),.I2(output_reg_pipe_11),.O(out_inv_sqrt_8));
defparam desc1083.INIT=8'hAC;
LUT3 desc1084(.I0(un14_pos_outputf[7:7]),.I1(pre_outputf[7:7]),.I2(output_reg_pipe_11),.O(out_inv_sqrt_7));
defparam desc1084.INIT=8'hAC;
LUT3 desc1085(.I0(un14_pos_outputf[9:9]),.I1(pre_outputf[9:9]),.I2(output_reg_pipe_11),.O(out_inv_sqrt_9));
defparam desc1085.INIT=8'hAC;
LUT3 desc1086(.I0(un14_pos_outputf[10:10]),.I1(pre_outputf[10:10]),.I2(output_reg_pipe_11),.O(out_inv_sqrt_10));
defparam desc1086.INIT=8'hAC;
LUT3 done_e_lut6_2_o6(.I0(counter[3:3]),.I1(state),.I2(done_inv_sqrt),.O(done));
defparam done_e_lut6_2_o6.INIT=8'hC8;
LUT2 done_e_lut6_2_o5(.I0(counter[0:0]),.I1(state),.O(counter_4[1:1]));
defparam done_e_lut6_2_o5.INIT=4'h8;
LUT4 desc1087(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[10:10]),.I3(input_reg[11:11]),.O(ret_val_m10[2:2]));
defparam desc1087.INIT=16'h0001;
LUT2 desc1088(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.O(N_439));
defparam desc1088.INIT=4'hE;
LUT4 desc1089(.I0(ret_val_m10[2:2]),.I1(N_454),.I2(un3_shift_right_c2_0_0_a0_1),.I3(un9_0_axb_8),.O(un1_poly_odd_s_lut6_2_O6[11:11]));
defparam desc1089.INIT=16'h002E;
LUT5 desc1090(.I0(ret_val_m10[2:2]),.I1(N_454),.I2(un3_shift_right_c2_0_0_a0_1),.I3(ret_val[1:1]),.I4(un9_0_axb_8),.O(m9_a1_1));
defparam desc1090.INIT=32'h000000D1;
endmodule
module mat_regs_inj (col_sel_AQ2_mux_i_m3_lut6_2_O6,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ_int,w_col_sel_AQ_mux_i_m3_lut6_2_O6,w_col_sel_AQ_mux_i_m3_lut6_2_O5,vec_out_r_AQ_0,vec_in_r_AQ_mux_0_4,vec_in_r_AQ_mux_0_9,vec_in_r_AQ_mux_0_6,vec_in_r_AQ_mux_0_0,vec_in_r_AQ_mux_0_1,vec_in_r_AQ_mux_0_2,vec_in_r_AQ_mux_0_3,vec_in_r_AQ_mux_0_10,vec_in_r_AQ_mux_0_7,vec_in_r_AQ_mux_0_8,vec_out_r_AQ_3,vec_in_r_AQ_mux_3,out_Q_r,vec_out_r_AQ_2,vec_out_r_AQ_1,vec_in_r_AQ_mux_2,vec_in_r_AQ_mux_1,vec_out_i_AQ_0,vec_in_i_AQ_mux_0_5,vec_in_i_AQ_mux_0_10,vec_in_i_AQ_mux_0_7,vec_in_i_AQ_mux_0_0,vec_in_i_AQ_mux_0_1,vec_in_i_AQ_mux_0_4,vec_in_i_AQ_mux_0_6,vec_in_i_AQ_mux_0_11,vec_in_i_AQ_mux_0_8,vec_in_i_AQ_mux_0_9,vec_out_i_AQ_3,vec_in_i_AQ_mux_3,out_Q_i,vec_out_i_AQ_2,vec_out_i_AQ_1,vec_in_i_AQ_mux_2,vec_in_i_AQ_mux_1,row_sel_AQ,single_out_r_AQ2_1,single_out_r_AQ2_6,single_out_r_AQ2_4,single_out_r_AQ2_0,single_out_i_AQ2_1,single_out_i_AQ2_5,single_out_i_AQ2_4,single_out_i_AQ2_0,single_out_i_AQ2_11,single_out_i_AQ_1,single_out_i_AQ_0,single_out_i_AQ_8,single_out_i_AQ_10,single_out_i_AQ_11,single_out_i_AQ_9,single_out_i_AQ_4,single_out_r_AQ_4,single_out_r_AQ_2,single_out_r_AQ_7,single_out_r_AQ_1,single_out_r_AQ_0,clk,wr_en_AQ_mux_i_m3_lut6_2_O6,N_507,N_508,N_505,N_506,N_645,N_641,N_637,N_632,N_628,N_624,N_623,N_622,N_612,N_607,N_606,N_605,N_597,N_596,N_595,N_586,N_585,N_584,N_583,N_582,N_571,N_568,N_567,N_566,N_555,N_552,N_549);
input col_sel_AQ2_mux_i_m3_lut6_2_O6 ;
input col_sel_AQ2_mux_i_m3_lut6_2_O5 ;
input [1:0] col_sel_AQ_int ;
input w_col_sel_AQ_mux_i_m3_lut6_2_O6 ;
input w_col_sel_AQ_mux_i_m3_lut6_2_O5 ;
output [11:0] vec_out_r_AQ_0 ;
input vec_in_r_AQ_mux_0_4 ;
input vec_in_r_AQ_mux_0_9 ;
input vec_in_r_AQ_mux_0_6 ;
input vec_in_r_AQ_mux_0_0 ;
input vec_in_r_AQ_mux_0_1 ;
input vec_in_r_AQ_mux_0_2 ;
input vec_in_r_AQ_mux_0_3 ;
input vec_in_r_AQ_mux_0_10 ;
input vec_in_r_AQ_mux_0_7 ;
input vec_in_r_AQ_mux_0_8 ;
output [11:0] vec_out_r_AQ_3 ;
input [11:0] vec_in_r_AQ_mux_3 ;
output [47:0] out_Q_r ;
output [11:0] vec_out_r_AQ_2 ;
output [11:0] vec_out_r_AQ_1 ;
input [11:0] vec_in_r_AQ_mux_2 ;
input [11:0] vec_in_r_AQ_mux_1 ;
output [11:0] vec_out_i_AQ_0 ;
input vec_in_i_AQ_mux_0_5 ;
input vec_in_i_AQ_mux_0_10 ;
input vec_in_i_AQ_mux_0_7 ;
input vec_in_i_AQ_mux_0_0 ;
input vec_in_i_AQ_mux_0_1 ;
input vec_in_i_AQ_mux_0_4 ;
input vec_in_i_AQ_mux_0_6 ;
input vec_in_i_AQ_mux_0_11 ;
input vec_in_i_AQ_mux_0_8 ;
input vec_in_i_AQ_mux_0_9 ;
output [11:0] vec_out_i_AQ_3 ;
input [11:0] vec_in_i_AQ_mux_3 ;
output [47:0] out_Q_i ;
output [11:0] vec_out_i_AQ_2 ;
output [11:0] vec_out_i_AQ_1 ;
input [11:0] vec_in_i_AQ_mux_2 ;
input [11:0] vec_in_i_AQ_mux_1 ;
input [1:0] row_sel_AQ ;
output single_out_r_AQ2_1 ;
output single_out_r_AQ2_6 ;
output single_out_r_AQ2_4 ;
output single_out_r_AQ2_0 ;
output single_out_i_AQ2_1 ;
output single_out_i_AQ2_5 ;
output single_out_i_AQ2_4 ;
output single_out_i_AQ2_0 ;
output single_out_i_AQ2_11 ;
output single_out_i_AQ_1 ;
output single_out_i_AQ_0 ;
output single_out_i_AQ_8 ;
output single_out_i_AQ_10 ;
output single_out_i_AQ_11 ;
output single_out_i_AQ_9 ;
output single_out_i_AQ_4 ;
output single_out_r_AQ_4 ;
output single_out_r_AQ_2 ;
output single_out_r_AQ_7 ;
output single_out_r_AQ_1 ;
output single_out_r_AQ_0 ;
input clk ;
input wr_en_AQ_mux_i_m3_lut6_2_O6 ;
input N_507 ;
input N_508 ;
input N_505 ;
input N_506 ;
output N_645 ;
output N_641 ;
output N_637 ;
output N_632 ;
output N_628 ;
output N_624 ;
output N_623 ;
output N_622 ;
output N_612 ;
output N_607 ;
output N_606 ;
output N_605 ;
output N_597 ;
output N_596 ;
output N_595 ;
output N_586 ;
output N_585 ;
output N_584 ;
output N_583 ;
output N_582 ;
output N_571 ;
output N_568 ;
output N_567 ;
output N_566 ;
output N_555 ;
output N_552 ;
output N_549 ;
wire vec_in_r_AQ_mux_0_4 ;
wire vec_in_r_AQ_mux_0_9 ;
wire vec_in_r_AQ_mux_0_6 ;
wire vec_in_r_AQ_mux_0_0 ;
wire vec_in_r_AQ_mux_0_1 ;
wire vec_in_r_AQ_mux_0_2 ;
wire vec_in_r_AQ_mux_0_3 ;
wire vec_in_r_AQ_mux_0_10 ;
wire vec_in_r_AQ_mux_0_7 ;
wire vec_in_r_AQ_mux_0_8 ;
wire vec_in_i_AQ_mux_0_5 ;
wire vec_in_i_AQ_mux_0_10 ;
wire vec_in_i_AQ_mux_0_7 ;
wire vec_in_i_AQ_mux_0_0 ;
wire vec_in_i_AQ_mux_0_1 ;
wire vec_in_i_AQ_mux_0_4 ;
wire vec_in_i_AQ_mux_0_6 ;
wire vec_in_i_AQ_mux_0_11 ;
wire vec_in_i_AQ_mux_0_8 ;
wire vec_in_i_AQ_mux_0_9 ;
wire single_out_r_AQ2_1 ;
wire single_out_r_AQ2_6 ;
wire single_out_r_AQ2_4 ;
wire single_out_r_AQ2_0 ;
wire single_out_i_AQ2_1 ;
wire single_out_i_AQ2_5 ;
wire single_out_i_AQ2_4 ;
wire single_out_i_AQ2_0 ;
wire single_out_i_AQ2_11 ;
wire single_out_i_AQ_1 ;
wire single_out_i_AQ_0 ;
wire single_out_i_AQ_8 ;
wire single_out_i_AQ_10 ;
wire single_out_i_AQ_11 ;
wire single_out_i_AQ_9 ;
wire single_out_i_AQ_4 ;
wire single_out_r_AQ_4 ;
wire single_out_r_AQ_2 ;
wire single_out_r_AQ_7 ;
wire single_out_r_AQ_1 ;
wire single_out_r_AQ_0 ;
wire clk ;
wire wr_en_AQ_mux_i_m3_lut6_2_O6 ;
wire N_507 ;
wire N_508 ;
wire N_505 ;
wire N_506 ;
wire N_645 ;
wire N_641 ;
wire N_637 ;
wire N_632 ;
wire N_628 ;
wire N_624 ;
wire N_623 ;
wire N_622 ;
wire N_612 ;
wire N_607 ;
wire N_606 ;
wire N_605 ;
wire N_597 ;
wire N_596 ;
wire N_595 ;
wire N_586 ;
wire N_585 ;
wire N_584 ;
wire N_583 ;
wire N_582 ;
wire N_571 ;
wire N_568 ;
wire N_567 ;
wire N_566 ;
wire N_555 ;
wire N_552 ;
wire N_549 ;
wire [1:0] mat_r_1_I_47_DOC ;
wire [1:0] mat_r_1_I_47_DOD ;
wire [1:0] mat_r_1_I_45_DOC ;
wire [1:0] mat_r_1_I_45_DOD ;
wire [1:0] mat_r_1_I_43_DOC ;
wire [1:0] mat_r_1_I_43_DOD ;
wire [1:0] mat_r_1_I_41_DOC ;
wire [1:0] mat_r_1_I_41_DOD ;
wire [1:0] mat_r_1_I_39_DOC ;
wire [1:0] mat_r_1_I_39_DOD ;
wire [1:0] mat_r_1_I_37_DOC ;
wire [1:0] mat_r_1_I_37_DOD ;
wire [1:0] mat_r_1_I_35_DOC ;
wire [1:0] mat_r_1_I_35_DOD ;
wire [1:0] mat_r_1_I_33_DOC ;
wire [1:0] mat_r_1_I_33_DOD ;
wire [1:0] mat_r_1_I_31_DOC ;
wire [1:0] mat_r_1_I_31_DOD ;
wire [1:0] mat_r_1_I_29_DOC ;
wire [1:0] mat_r_1_I_29_DOD ;
wire [1:0] mat_r_1_I_27_DOC ;
wire [1:0] mat_r_1_I_27_DOD ;
wire [1:0] mat_r_1_I_25_DOC ;
wire [1:0] mat_r_1_I_25_DOD ;
wire [1:0] mat_r_1_I_23_DOC ;
wire [1:0] mat_r_1_I_23_DOD ;
wire [1:0] mat_r_1_I_21_DOC ;
wire [1:0] mat_r_1_I_21_DOD ;
wire [1:0] mat_r_1_I_19_DOC ;
wire [1:0] mat_r_1_I_19_DOD ;
wire [1:0] mat_r_1_I_17_DOC ;
wire [1:0] mat_r_1_I_17_DOD ;
wire [1:0] mat_r_1_I_15_DOC ;
wire [1:0] mat_r_1_I_15_DOD ;
wire [1:0] mat_r_1_I_13_DOC ;
wire [1:0] mat_r_1_I_13_DOD ;
wire [1:0] mat_r_1_I_11_DOC ;
wire [1:0] mat_r_1_I_11_DOD ;
wire [1:0] mat_r_1_I_9_DOC ;
wire [1:0] mat_r_1_I_9_DOD ;
wire [1:0] mat_r_1_I_7_DOC ;
wire [1:0] mat_r_1_I_7_DOD ;
wire [1:0] mat_r_1_I_5_DOC ;
wire [1:0] mat_r_1_I_5_DOD ;
wire [1:0] mat_r_1_I_3_DOC ;
wire [1:0] mat_r_1_I_3_DOD ;
wire [1:0] mat_r_1_I_1_DOC ;
wire [1:0] mat_r_1_I_1_DOD ;
wire [1:0] mat_i_1_I_47_DOC ;
wire [1:0] mat_i_1_I_47_DOD ;
wire [1:0] mat_i_1_I_45_DOC ;
wire [1:0] mat_i_1_I_45_DOD ;
wire [1:0] mat_i_1_I_43_DOC ;
wire [1:0] mat_i_1_I_43_DOD ;
wire [1:0] mat_i_1_I_41_DOC ;
wire [1:0] mat_i_1_I_41_DOD ;
wire [1:0] mat_i_1_I_39_DOC ;
wire [1:0] mat_i_1_I_39_DOD ;
wire [1:0] mat_i_1_I_37_DOC ;
wire [1:0] mat_i_1_I_37_DOD ;
wire [1:0] mat_i_1_I_35_DOC ;
wire [1:0] mat_i_1_I_35_DOD ;
wire [1:0] mat_i_1_I_33_DOC ;
wire [1:0] mat_i_1_I_33_DOD ;
wire [1:0] mat_i_1_I_31_DOC ;
wire [1:0] mat_i_1_I_31_DOD ;
wire [1:0] mat_i_1_I_29_DOC ;
wire [1:0] mat_i_1_I_29_DOD ;
wire [1:0] mat_i_1_I_27_DOC ;
wire [1:0] mat_i_1_I_27_DOD ;
wire [1:0] mat_i_1_I_25_DOC ;
wire [1:0] mat_i_1_I_25_DOD ;
wire [1:0] mat_i_1_I_23_DOC ;
wire [1:0] mat_i_1_I_23_DOD ;
wire [1:0] mat_i_1_I_21_DOC ;
wire [1:0] mat_i_1_I_21_DOD ;
wire [1:0] mat_i_1_I_19_DOC ;
wire [1:0] mat_i_1_I_19_DOD ;
wire [1:0] mat_i_1_I_17_DOC ;
wire [1:0] mat_i_1_I_17_DOD ;
wire [1:0] mat_i_1_I_15_DOC ;
wire [1:0] mat_i_1_I_15_DOD ;
wire [1:0] mat_i_1_I_13_DOC ;
wire [1:0] mat_i_1_I_13_DOD ;
wire [1:0] mat_i_1_I_11_DOC ;
wire [1:0] mat_i_1_I_11_DOD ;
wire [1:0] mat_i_1_I_9_DOC ;
wire [1:0] mat_i_1_I_9_DOD ;
wire [1:0] mat_i_1_I_7_DOC ;
wire [1:0] mat_i_1_I_7_DOD ;
wire [1:0] mat_i_1_I_5_DOC ;
wire [1:0] mat_i_1_I_5_DOD ;
wire [1:0] mat_i_1_I_3_DOC ;
wire [1:0] mat_i_1_I_3_DOD ;
wire [1:0] mat_i_1_I_1_DOC ;
wire [1:0] mat_i_1_I_1_DOD ;
wire GND ;
wire VCC ;
// instances
RAM32M mat_r_1_I_47(.DOA({out_Q_r[8:8],out_Q_r[5:5]}),.DOB({vec_out_r_AQ_3[8:8],vec_out_r_AQ_3[5:5]}),.DOC(mat_r_1_I_47_DOC[1:0]),.DOD(mat_r_1_I_47_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_3[8:8],vec_in_r_AQ_mux_3[5:5]}),.DIB({vec_in_r_AQ_mux_3[8:8],vec_in_r_AQ_mux_3[5:5]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_47.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_47.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_47.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_47.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_45(.DOA({out_Q_r[41:41],out_Q_r[19:19]}),.DOB({vec_out_r_AQ_0[5:5],vec_out_r_AQ_2[7:7]}),.DOC(mat_r_1_I_45_DOC[1:0]),.DOD(mat_r_1_I_45_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_0_4,vec_in_r_AQ_mux_2[7:7]}),.DIB({vec_in_r_AQ_mux_0_4,vec_in_r_AQ_mux_2[7:7]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_45.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_45.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_45.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_45.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_43(.DOA({out_Q_r[46:46],out_Q_r[2:2]}),.DOB({vec_out_r_AQ_0[10:10],vec_out_r_AQ_3[2:2]}),.DOC(mat_r_1_I_43_DOC[1:0]),.DOD(mat_r_1_I_43_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_0_9,vec_in_r_AQ_mux_3[2:2]}),.DIB({vec_in_r_AQ_mux_0_9,vec_in_r_AQ_mux_3[2:2]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_43.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_43.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_43.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_43.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_41(.DOA({out_Q_r[32:32],out_Q_r[20:20]}),.DOB({vec_out_r_AQ_1[8:8],vec_out_r_AQ_2[8:8]}),.DOC(mat_r_1_I_41_DOC[1:0]),.DOD(mat_r_1_I_41_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_1[8:8],vec_in_r_AQ_mux_2[8:8]}),.DIB({vec_in_r_AQ_mux_1[8:8],vec_in_r_AQ_mux_2[8:8]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_41.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_41.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_41.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_41.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_39(.DOA({out_Q_r[43:43],out_Q_r[21:21]}),.DOB({vec_out_r_AQ_0[7:7],vec_out_r_AQ_2[9:9]}),.DOC(mat_r_1_I_39_DOC[1:0]),.DOD(mat_r_1_I_39_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_0_6,vec_in_r_AQ_mux_2[9:9]}),.DIB({vec_in_r_AQ_mux_0_6,vec_in_r_AQ_mux_2[9:9]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_39.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_39.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_39.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_39.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_37(.DOA({out_Q_r[26:26],out_Q_r[35:35]}),.DOB({vec_out_r_AQ_1[2:2],vec_out_r_AQ_1[11:11]}),.DOC(mat_r_1_I_37_DOC[1:0]),.DOD(mat_r_1_I_37_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_1[2:2],vec_in_r_AQ_mux_1[11:11]}),.DIB({vec_in_r_AQ_mux_1[2:2],vec_in_r_AQ_mux_1[11:11]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_37.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_37.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_37.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_37.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_35(.DOA({out_Q_r[22:22],out_Q_r[18:18]}),.DOB({vec_out_r_AQ_2[10:10],vec_out_r_AQ_2[6:6]}),.DOC(mat_r_1_I_35_DOC[1:0]),.DOD(mat_r_1_I_35_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_2[10:10],vec_in_r_AQ_mux_2[6:6]}),.DIB({vec_in_r_AQ_mux_2[10:10],vec_in_r_AQ_mux_2[6:6]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_35.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_35.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_35.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_35.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_33(.DOA({out_Q_r[36:36],out_Q_r[23:23]}),.DOB({vec_out_r_AQ_0[0:0],vec_out_r_AQ_2[11:11]}),.DOC(mat_r_1_I_33_DOC[1:0]),.DOD(mat_r_1_I_33_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({N_507,vec_in_r_AQ_mux_2[11:11]}),.DIB({N_507,vec_in_r_AQ_mux_2[11:11]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_33.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_33.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_33.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_33.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_31(.DOA({out_Q_r[10:10],out_Q_r[37:37]}),.DOB({vec_out_r_AQ_3[10:10],vec_out_r_AQ_0[1:1]}),.DOC(mat_r_1_I_31_DOC[1:0]),.DOD(mat_r_1_I_31_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_3[10:10],vec_in_r_AQ_mux_0_0}),.DIB({vec_in_r_AQ_mux_3[10:10],vec_in_r_AQ_mux_0_0}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_31.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_31.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_31.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_31.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_29(.DOA({out_Q_r[24:24],out_Q_r[11:11]}),.DOB({vec_out_r_AQ_1[0:0],vec_out_r_AQ_3[11:11]}),.DOC(mat_r_1_I_29_DOC[1:0]),.DOD(mat_r_1_I_29_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_1[0:0],vec_in_r_AQ_mux_3[11:11]}),.DIB({vec_in_r_AQ_mux_1[0:0],vec_in_r_AQ_mux_3[11:11]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_29.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_29.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_29.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_29.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_27(.DOA({out_Q_r[38:38],out_Q_r[25:25]}),.DOB({vec_out_r_AQ_0[2:2],vec_out_r_AQ_1[1:1]}),.DOC(mat_r_1_I_27_DOC[1:0]),.DOD(mat_r_1_I_27_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_0_1,vec_in_r_AQ_mux_1[1:1]}),.DIB({vec_in_r_AQ_mux_0_1,vec_in_r_AQ_mux_1[1:1]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_27.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_27.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_27.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_27.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_25(.DOA({out_Q_r[12:12],out_Q_r[39:39]}),.DOB({vec_out_r_AQ_2[0:0],vec_out_r_AQ_0[3:3]}),.DOC(mat_r_1_I_25_DOC[1:0]),.DOD(mat_r_1_I_25_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_2[0:0],vec_in_r_AQ_mux_0_2}),.DIB({vec_in_r_AQ_mux_2[0:0],vec_in_r_AQ_mux_0_2}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_25.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_25.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_25.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_25.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_23(.DOA({out_Q_r[9:9],out_Q_r[13:13]}),.DOB({vec_out_r_AQ_3[9:9],vec_out_r_AQ_2[1:1]}),.DOC(mat_r_1_I_23_DOC[1:0]),.DOD(mat_r_1_I_23_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_3[9:9],vec_in_r_AQ_mux_2[1:1]}),.DIB({vec_in_r_AQ_mux_3[9:9],vec_in_r_AQ_mux_2[1:1]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_23.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_23.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_23.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_23.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_21(.DOA({out_Q_r[40:40],out_Q_r[27:27]}),.DOB({vec_out_r_AQ_0[4:4],vec_out_r_AQ_1[3:3]}),.DOC(mat_r_1_I_21_DOC[1:0]),.DOD(mat_r_1_I_21_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_0_3,vec_in_r_AQ_mux_1[3:3]}),.DIB({vec_in_r_AQ_mux_0_3,vec_in_r_AQ_mux_1[3:3]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_21.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_21.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_21.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_21.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_19(.DOA({out_Q_r[14:14],out_Q_r[0:0]}),.DOB({vec_out_r_AQ_2[2:2],vec_out_r_AQ_3[0:0]}),.DOC(mat_r_1_I_19_DOC[1:0]),.DOD(mat_r_1_I_19_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_2[2:2],vec_in_r_AQ_mux_3[0:0]}),.DIB({vec_in_r_AQ_mux_2[2:2],vec_in_r_AQ_mux_3[0:0]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_19.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_19.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_19.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_19.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_17(.DOA({out_Q_r[6:6],out_Q_r[34:34]}),.DOB({vec_out_r_AQ_3[6:6],vec_out_r_AQ_1[10:10]}),.DOC(mat_r_1_I_17_DOC[1:0]),.DOD(mat_r_1_I_17_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_3[6:6],vec_in_r_AQ_mux_1[10:10]}),.DIB({vec_in_r_AQ_mux_3[6:6],vec_in_r_AQ_mux_1[10:10]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_17.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_17.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_17.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_17.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_15(.DOA({out_Q_r[42:42],out_Q_r[1:1]}),.DOB({vec_out_r_AQ_0[6:6],vec_out_r_AQ_3[1:1]}),.DOC(mat_r_1_I_15_DOC[1:0]),.DOD(mat_r_1_I_15_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({N_508,vec_in_r_AQ_mux_3[1:1]}),.DIB({N_508,vec_in_r_AQ_mux_3[1:1]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_15.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_15.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_15.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_15.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_13(.DOA({out_Q_r[7:7],out_Q_r[47:47]}),.DOB({vec_out_r_AQ_3[7:7],vec_out_r_AQ_0[11:11]}),.DOC(mat_r_1_I_13_DOC[1:0]),.DOD(mat_r_1_I_13_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_3[7:7],vec_in_r_AQ_mux_0_10}),.DIB({vec_in_r_AQ_mux_3[7:7],vec_in_r_AQ_mux_0_10}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_13.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_13.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_13.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_13.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_11(.DOA({out_Q_r[30:30],out_Q_r[17:17]}),.DOB({vec_out_r_AQ_1[6:6],vec_out_r_AQ_2[5:5]}),.DOC(mat_r_1_I_11_DOC[1:0]),.DOD(mat_r_1_I_11_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_1[6:6],vec_in_r_AQ_mux_2[5:5]}),.DIB({vec_in_r_AQ_mux_1[6:6],vec_in_r_AQ_mux_2[5:5]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_11.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_11.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_11.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_11.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_9(.DOA({out_Q_r[44:44],out_Q_r[31:31]}),.DOB({vec_out_r_AQ_0[8:8],vec_out_r_AQ_1[7:7]}),.DOC(mat_r_1_I_9_DOC[1:0]),.DOD(mat_r_1_I_9_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_0_7,vec_in_r_AQ_mux_1[7:7]}),.DIB({vec_in_r_AQ_mux_0_7,vec_in_r_AQ_mux_1[7:7]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_9.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_9.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_9.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_9.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_7(.DOA({out_Q_r[3:3],out_Q_r[45:45]}),.DOB({vec_out_r_AQ_3[3:3],vec_out_r_AQ_0[9:9]}),.DOC(mat_r_1_I_7_DOC[1:0]),.DOD(mat_r_1_I_7_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_3[3:3],vec_in_r_AQ_mux_0_8}),.DIB({vec_in_r_AQ_mux_3[3:3],vec_in_r_AQ_mux_0_8}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_7.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_7.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_7.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_7.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_5(.DOA({out_Q_r[4:4],out_Q_r[28:28]}),.DOB({vec_out_r_AQ_3[4:4],vec_out_r_AQ_1[4:4]}),.DOC(mat_r_1_I_5_DOC[1:0]),.DOD(mat_r_1_I_5_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_3[4:4],vec_in_r_AQ_mux_1[4:4]}),.DIB({vec_in_r_AQ_mux_3[4:4],vec_in_r_AQ_mux_1[4:4]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_5.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_5.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_5.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_5.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_3(.DOA({out_Q_r[15:15],out_Q_r[33:33]}),.DOB({vec_out_r_AQ_2[3:3],vec_out_r_AQ_1[9:9]}),.DOC(mat_r_1_I_3_DOC[1:0]),.DOD(mat_r_1_I_3_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_2[3:3],vec_in_r_AQ_mux_1[9:9]}),.DIB({vec_in_r_AQ_mux_2[3:3],vec_in_r_AQ_mux_1[9:9]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_3.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_3.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_3.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_3.INIT_D=64'h0000000000000000;
RAM32M mat_r_1_I_1(.DOA({out_Q_r[29:29],out_Q_r[16:16]}),.DOB({vec_out_r_AQ_1[5:5],vec_out_r_AQ_2[4:4]}),.DOC(mat_r_1_I_1_DOC[1:0]),.DOD(mat_r_1_I_1_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_r_AQ_mux_1[5:5],vec_in_r_AQ_mux_2[4:4]}),.DIB({vec_in_r_AQ_mux_1[5:5],vec_in_r_AQ_mux_2[4:4]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_r_1_I_1.INIT_A=64'h0000000000000000;
defparam mat_r_1_I_1.INIT_B=64'h0000000000000000;
defparam mat_r_1_I_1.INIT_C=64'h0000000000000000;
defparam mat_r_1_I_1.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_47(.DOA({out_Q_i[8:8],out_Q_i[5:5]}),.DOB({vec_out_i_AQ_3[8:8],vec_out_i_AQ_3[5:5]}),.DOC(mat_i_1_I_47_DOC[1:0]),.DOD(mat_i_1_I_47_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_3[8:8],vec_in_i_AQ_mux_3[5:5]}),.DIB({vec_in_i_AQ_mux_3[8:8],vec_in_i_AQ_mux_3[5:5]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_47.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_47.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_47.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_47.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_45(.DOA({out_Q_i[41:41],out_Q_i[19:19]}),.DOB({vec_out_i_AQ_0[5:5],vec_out_i_AQ_2[7:7]}),.DOC(mat_i_1_I_45_DOC[1:0]),.DOD(mat_i_1_I_45_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_0_5,vec_in_i_AQ_mux_2[7:7]}),.DIB({vec_in_i_AQ_mux_0_5,vec_in_i_AQ_mux_2[7:7]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_45.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_45.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_45.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_45.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_43(.DOA({out_Q_i[46:46],out_Q_i[2:2]}),.DOB({vec_out_i_AQ_0[10:10],vec_out_i_AQ_3[2:2]}),.DOC(mat_i_1_I_43_DOC[1:0]),.DOD(mat_i_1_I_43_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_0_10,vec_in_i_AQ_mux_3[2:2]}),.DIB({vec_in_i_AQ_mux_0_10,vec_in_i_AQ_mux_3[2:2]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_43.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_43.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_43.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_43.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_41(.DOA({out_Q_i[32:32],out_Q_i[20:20]}),.DOB({vec_out_i_AQ_1[8:8],vec_out_i_AQ_2[8:8]}),.DOC(mat_i_1_I_41_DOC[1:0]),.DOD(mat_i_1_I_41_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_1[8:8],vec_in_i_AQ_mux_2[8:8]}),.DIB({vec_in_i_AQ_mux_1[8:8],vec_in_i_AQ_mux_2[8:8]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_41.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_41.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_41.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_41.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_39(.DOA({out_Q_i[43:43],out_Q_i[21:21]}),.DOB({vec_out_i_AQ_0[7:7],vec_out_i_AQ_2[9:9]}),.DOC(mat_i_1_I_39_DOC[1:0]),.DOD(mat_i_1_I_39_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_0_7,vec_in_i_AQ_mux_2[9:9]}),.DIB({vec_in_i_AQ_mux_0_7,vec_in_i_AQ_mux_2[9:9]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_39.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_39.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_39.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_39.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_37(.DOA({out_Q_i[26:26],out_Q_i[35:35]}),.DOB({vec_out_i_AQ_1[2:2],vec_out_i_AQ_1[11:11]}),.DOC(mat_i_1_I_37_DOC[1:0]),.DOD(mat_i_1_I_37_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_1[2:2],vec_in_i_AQ_mux_1[11:11]}),.DIB({vec_in_i_AQ_mux_1[2:2],vec_in_i_AQ_mux_1[11:11]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_37.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_37.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_37.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_37.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_35(.DOA({out_Q_i[22:22],out_Q_i[18:18]}),.DOB({vec_out_i_AQ_2[10:10],vec_out_i_AQ_2[6:6]}),.DOC(mat_i_1_I_35_DOC[1:0]),.DOD(mat_i_1_I_35_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_2[10:10],vec_in_i_AQ_mux_2[6:6]}),.DIB({vec_in_i_AQ_mux_2[10:10],vec_in_i_AQ_mux_2[6:6]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_35.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_35.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_35.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_35.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_33(.DOA({out_Q_i[36:36],out_Q_i[23:23]}),.DOB({vec_out_i_AQ_0[0:0],vec_out_i_AQ_2[11:11]}),.DOC(mat_i_1_I_33_DOC[1:0]),.DOD(mat_i_1_I_33_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_0_0,vec_in_i_AQ_mux_2[11:11]}),.DIB({vec_in_i_AQ_mux_0_0,vec_in_i_AQ_mux_2[11:11]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_33.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_33.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_33.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_33.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_31(.DOA({out_Q_i[10:10],out_Q_i[37:37]}),.DOB({vec_out_i_AQ_3[10:10],vec_out_i_AQ_0[1:1]}),.DOC(mat_i_1_I_31_DOC[1:0]),.DOD(mat_i_1_I_31_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_3[10:10],vec_in_i_AQ_mux_0_1}),.DIB({vec_in_i_AQ_mux_3[10:10],vec_in_i_AQ_mux_0_1}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_31.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_31.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_31.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_31.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_29(.DOA({out_Q_i[24:24],out_Q_i[11:11]}),.DOB({vec_out_i_AQ_1[0:0],vec_out_i_AQ_3[11:11]}),.DOC(mat_i_1_I_29_DOC[1:0]),.DOD(mat_i_1_I_29_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_1[0:0],vec_in_i_AQ_mux_3[11:11]}),.DIB({vec_in_i_AQ_mux_1[0:0],vec_in_i_AQ_mux_3[11:11]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_29.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_29.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_29.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_29.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_27(.DOA({out_Q_i[38:38],out_Q_i[25:25]}),.DOB({vec_out_i_AQ_0[2:2],vec_out_i_AQ_1[1:1]}),.DOC(mat_i_1_I_27_DOC[1:0]),.DOD(mat_i_1_I_27_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({N_505,vec_in_i_AQ_mux_1[1:1]}),.DIB({N_505,vec_in_i_AQ_mux_1[1:1]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_27.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_27.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_27.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_27.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_25(.DOA({out_Q_i[12:12],out_Q_i[39:39]}),.DOB({vec_out_i_AQ_2[0:0],vec_out_i_AQ_0[3:3]}),.DOC(mat_i_1_I_25_DOC[1:0]),.DOD(mat_i_1_I_25_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_2[0:0],N_506}),.DIB({vec_in_i_AQ_mux_2[0:0],N_506}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_25.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_25.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_25.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_25.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_23(.DOA({out_Q_i[9:9],out_Q_i[13:13]}),.DOB({vec_out_i_AQ_3[9:9],vec_out_i_AQ_2[1:1]}),.DOC(mat_i_1_I_23_DOC[1:0]),.DOD(mat_i_1_I_23_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_3[9:9],vec_in_i_AQ_mux_2[1:1]}),.DIB({vec_in_i_AQ_mux_3[9:9],vec_in_i_AQ_mux_2[1:1]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_23.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_23.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_23.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_23.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_21(.DOA({out_Q_i[40:40],out_Q_i[27:27]}),.DOB({vec_out_i_AQ_0[4:4],vec_out_i_AQ_1[3:3]}),.DOC(mat_i_1_I_21_DOC[1:0]),.DOD(mat_i_1_I_21_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_0_4,vec_in_i_AQ_mux_1[3:3]}),.DIB({vec_in_i_AQ_mux_0_4,vec_in_i_AQ_mux_1[3:3]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_21.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_21.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_21.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_21.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_19(.DOA({out_Q_i[14:14],out_Q_i[0:0]}),.DOB({vec_out_i_AQ_2[2:2],vec_out_i_AQ_3[0:0]}),.DOC(mat_i_1_I_19_DOC[1:0]),.DOD(mat_i_1_I_19_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_2[2:2],vec_in_i_AQ_mux_3[0:0]}),.DIB({vec_in_i_AQ_mux_2[2:2],vec_in_i_AQ_mux_3[0:0]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_19.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_19.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_19.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_19.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_17(.DOA({out_Q_i[6:6],out_Q_i[34:34]}),.DOB({vec_out_i_AQ_3[6:6],vec_out_i_AQ_1[10:10]}),.DOC(mat_i_1_I_17_DOC[1:0]),.DOD(mat_i_1_I_17_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_3[6:6],vec_in_i_AQ_mux_1[10:10]}),.DIB({vec_in_i_AQ_mux_3[6:6],vec_in_i_AQ_mux_1[10:10]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_17.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_17.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_17.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_17.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_15(.DOA({out_Q_i[42:42],out_Q_i[1:1]}),.DOB({vec_out_i_AQ_0[6:6],vec_out_i_AQ_3[1:1]}),.DOC(mat_i_1_I_15_DOC[1:0]),.DOD(mat_i_1_I_15_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_0_6,vec_in_i_AQ_mux_3[1:1]}),.DIB({vec_in_i_AQ_mux_0_6,vec_in_i_AQ_mux_3[1:1]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_15.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_15.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_15.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_15.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_13(.DOA({out_Q_i[7:7],out_Q_i[47:47]}),.DOB({vec_out_i_AQ_3[7:7],vec_out_i_AQ_0[11:11]}),.DOC(mat_i_1_I_13_DOC[1:0]),.DOD(mat_i_1_I_13_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_3[7:7],vec_in_i_AQ_mux_0_11}),.DIB({vec_in_i_AQ_mux_3[7:7],vec_in_i_AQ_mux_0_11}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_13.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_13.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_13.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_13.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_11(.DOA({out_Q_i[30:30],out_Q_i[17:17]}),.DOB({vec_out_i_AQ_1[6:6],vec_out_i_AQ_2[5:5]}),.DOC(mat_i_1_I_11_DOC[1:0]),.DOD(mat_i_1_I_11_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_1[6:6],vec_in_i_AQ_mux_2[5:5]}),.DIB({vec_in_i_AQ_mux_1[6:6],vec_in_i_AQ_mux_2[5:5]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_11.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_11.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_11.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_11.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_9(.DOA({out_Q_i[44:44],out_Q_i[31:31]}),.DOB({vec_out_i_AQ_0[8:8],vec_out_i_AQ_1[7:7]}),.DOC(mat_i_1_I_9_DOC[1:0]),.DOD(mat_i_1_I_9_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_0_8,vec_in_i_AQ_mux_1[7:7]}),.DIB({vec_in_i_AQ_mux_0_8,vec_in_i_AQ_mux_1[7:7]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_9.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_9.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_9.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_9.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_7(.DOA({out_Q_i[3:3],out_Q_i[45:45]}),.DOB({vec_out_i_AQ_3[3:3],vec_out_i_AQ_0[9:9]}),.DOC(mat_i_1_I_7_DOC[1:0]),.DOD(mat_i_1_I_7_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_3[3:3],vec_in_i_AQ_mux_0_9}),.DIB({vec_in_i_AQ_mux_3[3:3],vec_in_i_AQ_mux_0_9}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_7.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_7.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_7.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_7.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_5(.DOA({out_Q_i[4:4],out_Q_i[28:28]}),.DOB({vec_out_i_AQ_3[4:4],vec_out_i_AQ_1[4:4]}),.DOC(mat_i_1_I_5_DOC[1:0]),.DOD(mat_i_1_I_5_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_3[4:4],vec_in_i_AQ_mux_1[4:4]}),.DIB({vec_in_i_AQ_mux_3[4:4],vec_in_i_AQ_mux_1[4:4]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_5.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_5.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_5.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_5.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_3(.DOA({out_Q_i[15:15],out_Q_i[33:33]}),.DOB({vec_out_i_AQ_2[3:3],vec_out_i_AQ_1[9:9]}),.DOC(mat_i_1_I_3_DOC[1:0]),.DOD(mat_i_1_I_3_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_2[3:3],vec_in_i_AQ_mux_1[9:9]}),.DIB({vec_in_i_AQ_mux_2[3:3],vec_in_i_AQ_mux_1[9:9]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_3.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_3.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_3.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_3.INIT_D=64'h0000000000000000;
RAM32M mat_i_1_I_1(.DOA({out_Q_i[29:29],out_Q_i[16:16]}),.DOB({vec_out_i_AQ_1[5:5],vec_out_i_AQ_2[4:4]}),.DOC(mat_i_1_I_1_DOC[1:0]),.DOD(mat_i_1_I_1_DOD[1:0]),.ADDRA({GND,GND,GND,col_sel_AQ2_mux_i_m3_lut6_2_O5,col_sel_AQ2_mux_i_m3_lut6_2_O6}),.ADDRB({GND,GND,GND,col_sel_AQ_int[1:0]}),.ADDRC({GND,GND,GND,GND,GND}),.ADDRD({GND,GND,GND,w_col_sel_AQ_mux_i_m3_lut6_2_O5,w_col_sel_AQ_mux_i_m3_lut6_2_O6}),.DIA({vec_in_i_AQ_mux_1[5:5],vec_in_i_AQ_mux_2[4:4]}),.DIB({vec_in_i_AQ_mux_1[5:5],vec_in_i_AQ_mux_2[4:4]}),.DIC({GND,GND}),.DID({GND,GND}),.WCLK(clk),.WE(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam mat_i_1_I_1.INIT_A=64'h0000000000000000;
defparam mat_i_1_I_1.INIT_B=64'h0000000000000000;
defparam mat_i_1_I_1.INIT_C=64'h0000000000000000;
defparam mat_i_1_I_1.INIT_D=64'h0000000000000000;
LUT6 desc0(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[3:3]),.I3(out_Q_r[15:15]),.I4(out_Q_r[27:27]),.I5(out_Q_r[39:39]),.O(N_645));
defparam desc0.INIT=64'hF7D5B391E6C4A280;
LUT6 desc1(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[4:4]),.I3(out_Q_r[40:40]),.I4(out_Q_r[16:16]),.I5(out_Q_r[28:28]),.O(N_641));
defparam desc1.INIT=64'hF7E6D5C4B3A29180;
LUT6 desc2(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[4:4]),.I3(vec_out_r_AQ_3[4:4]),.I4(vec_out_r_AQ_1[4:4]),.I5(vec_out_r_AQ_2[4:4]),.O(N_637));
defparam desc2.INIT=64'hFE76BA32DC549810;
LUT6 desc3(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[11:11]),.I3(out_Q_r[23:23]),.I4(out_Q_r[35:35]),.I5(out_Q_r[47:47]),.O(N_632));
defparam desc3.INIT=64'hF7D5B391E6C4A280;
LUT6 desc4(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[5:5]),.I3(vec_out_i_AQ_1[5:5]),.I4(vec_out_i_AQ_2[5:5]),.I5(vec_out_i_AQ_3[5:5]),.O(N_628));
defparam desc4.INIT=64'hFEBADC9876325410;
LUT6 desc5(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[11:11]),.I3(vec_out_r_AQ_1[11:11]),.I4(vec_out_r_AQ_2[11:11]),.I5(vec_out_r_AQ_3[11:11]),.O(N_624));
defparam desc5.INIT=64'hFEBADC9876325410;
LUT6 desc6(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[7:7]),.I3(vec_out_r_AQ_3[7:7]),.I4(vec_out_r_AQ_1[7:7]),.I5(vec_out_r_AQ_2[7:7]),.O(N_623));
defparam desc6.INIT=64'hFE76BA32DC549810;
LUT6 desc7(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[0:0]),.I3(vec_out_r_AQ_1[0:0]),.I4(vec_out_r_AQ_2[0:0]),.I5(vec_out_r_AQ_3[0:0]),.O(N_622));
defparam desc7.INIT=64'hFEBADC9876325410;
LUT6 desc8(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[8:8]),.I3(out_Q_i[32:32]),.I4(out_Q_i[44:44]),.I5(out_Q_i[20:20]),.O(N_612));
defparam desc8.INIT=64'hF7B3E6A2D591C480;
LUT6 desc9(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[10:10]),.I3(out_Q_r[22:22]),.I4(out_Q_r[46:46]),.I5(out_Q_r[34:34]),.O(N_607));
defparam desc9.INIT=64'hF7D5E6C4B391A280;
LUT6 desc10(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[9:9]),.I3(out_Q_r[21:21]),.I4(out_Q_r[33:33]),.I5(out_Q_r[45:45]),.O(N_606));
defparam desc10.INIT=64'hF7D5B391E6C4A280;
LUT6 desc11(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[12:12]),.I3(out_Q_r[24:24]),.I4(out_Q_r[36:36]),.I5(out_Q_r[0:0]),.O(N_605));
defparam desc11.INIT=64'hFDB9ECA875316420;
LUT6 desc12(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[10:10]),.I3(vec_out_r_AQ_2[10:10]),.I4(vec_out_r_AQ_3[10:10]),.I5(vec_out_r_AQ_1[10:10]),.O(N_597));
defparam desc12.INIT=64'hFEDC7654BA983210;
LUT6 desc13(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_3[9:9]),.I3(vec_out_r_AQ_0[9:9]),.I4(vec_out_r_AQ_1[9:9]),.I5(vec_out_r_AQ_2[9:9]),.O(N_596));
defparam desc13.INIT=64'hF7E6B3A2D5C49180;
LUT6 desc14(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[6:6]),.I3(vec_out_r_AQ_1[6:6]),.I4(vec_out_r_AQ_3[6:6]),.I5(vec_out_r_AQ_2[6:6]),.O(N_595));
defparam desc14.INIT=64'hFEBA7632DC985410;
LUT6 desc15(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[10:10]),.I3(out_Q_i[22:22]),.I4(out_Q_i[46:46]),.I5(out_Q_i[34:34]),.O(N_586));
defparam desc15.INIT=64'hF7D5E6C4B391A280;
LUT6 desc16(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[9:9]),.I3(out_Q_i[21:21]),.I4(out_Q_i[33:33]),.I5(out_Q_i[45:45]),.O(N_585));
defparam desc16.INIT=64'hF7D5B391E6C4A280;
LUT6 desc17(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[7:7]),.I3(out_Q_i[43:43]),.I4(out_Q_i[19:19]),.I5(out_Q_i[31:31]),.O(N_584));
defparam desc17.INIT=64'hF7E6D5C4B3A29180;
LUT6 desc18(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[6:6]),.I3(out_Q_i[30:30]),.I4(out_Q_i[42:42]),.I5(out_Q_i[18:18]),.O(N_583));
defparam desc18.INIT=64'hF7B3E6A2D591C480;
LUT6 desc19(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[3:3]),.I3(out_Q_i[15:15]),.I4(out_Q_i[27:27]),.I5(out_Q_i[39:39]),.O(N_582));
defparam desc19.INIT=64'hF7D5B391E6C4A280;
LUT6 desc20(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[6:6]),.I3(out_Q_r[30:30]),.I4(out_Q_r[42:42]),.I5(out_Q_r[18:18]),.O(N_571));
defparam desc20.INIT=64'hF7B3E6A2D591C480;
LUT6 desc21(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[7:7]),.I3(vec_out_i_AQ_3[7:7]),.I4(vec_out_i_AQ_1[7:7]),.I5(vec_out_i_AQ_2[7:7]),.O(N_568));
defparam desc21.INIT=64'hFE76BA32DC549810;
LUT6 desc22(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[6:6]),.I3(vec_out_i_AQ_1[6:6]),.I4(vec_out_i_AQ_3[6:6]),.I5(vec_out_i_AQ_2[6:6]),.O(N_567));
defparam desc22.INIT=64'hFEBA7632DC985410;
LUT6 desc23(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_2[3:3]),.I3(vec_out_i_AQ_3[3:3]),.I4(vec_out_i_AQ_0[3:3]),.I5(vec_out_i_AQ_1[3:3]),.O(N_566));
defparam desc23.INIT=64'hFD75EC64B931A820;
LUT6 desc24(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[14:14]),.I3(out_Q_i[26:26]),.I4(out_Q_i[38:38]),.I5(out_Q_i[2:2]),.O(N_555));
defparam desc24.INIT=64'hFDB9ECA875316420;
LUT6 desc25(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[8:8]),.I3(out_Q_r[32:32]),.I4(out_Q_r[44:44]),.I5(out_Q_r[20:20]),.O(N_552));
defparam desc25.INIT=64'hF7B3E6A2D591C480;
LUT6 desc26(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[2:2]),.I3(vec_out_i_AQ_1[2:2]),.I4(vec_out_i_AQ_2[2:2]),.I5(vec_out_i_AQ_3[2:2]),.O(N_549));
defparam desc26.INIT=64'hFEBADC9876325410;
LUT6 desc27(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[14:14]),.I3(out_Q_r[26:26]),.I4(out_Q_r[38:38]),.I5(out_Q_r[2:2]),.O(single_out_r_AQ2_1));
defparam desc27.INIT=64'hFDB9ECA875316420;
LUT6 desc28(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[5:5]),.I3(vec_out_r_AQ_1[5:5]),.I4(vec_out_r_AQ_2[5:5]),.I5(vec_out_r_AQ_3[5:5]),.O(single_out_r_AQ_4));
defparam desc28.INIT=64'hFEBADC9876325410;
LUT6 desc29(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_2[3:3]),.I3(vec_out_r_AQ_3[3:3]),.I4(vec_out_r_AQ_0[3:3]),.I5(vec_out_r_AQ_1[3:3]),.O(single_out_r_AQ_2));
defparam desc29.INIT=64'hFD75EC64B931A820;
LUT6 desc30(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[1:1]),.I3(out_Q_i[13:13]),.I4(out_Q_i[25:25]),.I5(out_Q_i[37:37]),.O(single_out_i_AQ2_1));
defparam desc30.INIT=64'hF7D5B391E6C4A280;
LUT6 desc31(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[1:1]),.I3(vec_out_i_AQ_1[1:1]),.I4(vec_out_i_AQ_2[1:1]),.I5(vec_out_i_AQ_3[1:1]),.O(single_out_i_AQ_1));
defparam desc31.INIT=64'hFEBADC9876325410;
LUT6 desc32(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[29:29]),.I3(out_Q_i[41:41]),.I4(out_Q_i[5:5]),.I5(out_Q_i[17:17]),.O(single_out_i_AQ2_5));
defparam desc32.INIT=64'hFBEA7362D9C85140;
LUT6 desc33(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[7:7]),.I3(out_Q_r[43:43]),.I4(out_Q_r[19:19]),.I5(out_Q_r[31:31]),.O(single_out_r_AQ2_6));
defparam desc33.INIT=64'hF7E6D5C4B3A29180;
LUT6 desc34(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[0:0]),.I3(vec_out_i_AQ_1[0:0]),.I4(vec_out_i_AQ_2[0:0]),.I5(vec_out_i_AQ_3[0:0]),.O(single_out_i_AQ_0));
defparam desc34.INIT=64'hFEBADC9876325410;
LUT6 desc35(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[4:4]),.I3(out_Q_i[40:40]),.I4(out_Q_i[16:16]),.I5(out_Q_i[28:28]),.O(single_out_i_AQ2_4));
defparam desc35.INIT=64'hF7E6D5C4B3A29180;
LUT6 desc36(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[12:12]),.I3(out_Q_i[24:24]),.I4(out_Q_i[36:36]),.I5(out_Q_i[0:0]),.O(single_out_i_AQ2_0));
defparam desc36.INIT=64'hFDB9ECA875316420;
LUT6 desc37(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[29:29]),.I3(out_Q_r[41:41]),.I4(out_Q_r[5:5]),.I5(out_Q_r[17:17]),.O(single_out_r_AQ2_4));
defparam desc37.INIT=64'hFBEA7362D9C85140;
LUT6 desc38(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_r[1:1]),.I3(out_Q_r[13:13]),.I4(out_Q_r[25:25]),.I5(out_Q_r[37:37]),.O(single_out_r_AQ2_0));
defparam desc38.INIT=64'hF7D5B391E6C4A280;
LUT6 desc39(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[8:8]),.I3(vec_out_i_AQ_1[8:8]),.I4(vec_out_i_AQ_3[8:8]),.I5(vec_out_i_AQ_2[8:8]),.O(single_out_i_AQ_8));
defparam desc39.INIT=64'hFEBA7632DC985410;
LUT6 desc40(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[10:10]),.I3(vec_out_i_AQ_2[10:10]),.I4(vec_out_i_AQ_3[10:10]),.I5(vec_out_i_AQ_1[10:10]),.O(single_out_i_AQ_10));
defparam desc40.INIT=64'hFEDC7654BA983210;
LUT6 desc41(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(out_Q_i[11:11]),.I3(out_Q_i[23:23]),.I4(out_Q_i[35:35]),.I5(out_Q_i[47:47]),.O(single_out_i_AQ2_11));
defparam desc41.INIT=64'hF7D5B391E6C4A280;
LUT6 desc42(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[11:11]),.I3(vec_out_i_AQ_1[11:11]),.I4(vec_out_i_AQ_2[11:11]),.I5(vec_out_i_AQ_3[11:11]),.O(single_out_i_AQ_11));
defparam desc42.INIT=64'hFEBADC9876325410;
LUT6 desc43(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_3[9:9]),.I3(vec_out_i_AQ_0[9:9]),.I4(vec_out_i_AQ_1[9:9]),.I5(vec_out_i_AQ_2[9:9]),.O(single_out_i_AQ_9));
defparam desc43.INIT=64'hF7E6B3A2D5C49180;
LUT6 desc44(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_i_AQ_0[4:4]),.I3(vec_out_i_AQ_3[4:4]),.I4(vec_out_i_AQ_1[4:4]),.I5(vec_out_i_AQ_2[4:4]),.O(single_out_i_AQ_4));
defparam desc44.INIT=64'hFE76BA32DC549810;
LUT6 desc45(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[8:8]),.I3(vec_out_r_AQ_1[8:8]),.I4(vec_out_r_AQ_3[8:8]),.I5(vec_out_r_AQ_2[8:8]),.O(single_out_r_AQ_7));
defparam desc45.INIT=64'hFEBA7632DC985410;
LUT6 desc46(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[2:2]),.I3(vec_out_r_AQ_1[2:2]),.I4(vec_out_r_AQ_2[2:2]),.I5(vec_out_r_AQ_3[2:2]),.O(single_out_r_AQ_1));
defparam desc46.INIT=64'hFEBADC9876325410;
LUT6 desc47(.I0(row_sel_AQ[1:1]),.I1(row_sel_AQ[0:0]),.I2(vec_out_r_AQ_0[1:1]),.I3(vec_out_r_AQ_1[1:1]),.I4(vec_out_r_AQ_2[1:1]),.I5(vec_out_r_AQ_3[1:1]),.O(single_out_r_AQ_0));
defparam desc47.INIT=64'hFEBADC9876325410;
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
endmodule
module mult_pipe_inj (mult1_out,in_a_r_reg,in_b_r_reg,clk);
output [23:23] mult1_out ;
input [11:0] in_a_r_reg ;
input [11:0] in_b_r_reg ;
input clk ;
wire clk ;
wire [29:0] ACOUT_33 ;
wire [17:0] BCOUT_33 ;
wire [3:0] CARRYOUT_33 ;
wire [22:0] pre_out_P_0 ;
wire [47:24] P_uc_33 ;
wire [47:0] PCOUT_33 ;
wire CARRYCASCOUT_33 ;
wire MULTSIGNOUT_33 ;
wire OVERFLOW_33 ;
wire PATTERNBDETECT_33 ;
wire PATTERNDETECT_33 ;
wire UNDERFLOW_33 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc264(.ACOUT(ACOUT_33[29:0]),.BCOUT(BCOUT_33[17:0]),.CARRYCASCOUT(CARRYCASCOUT_33),.CARRYOUT(CARRYOUT_33[3:0]),.MULTSIGNOUT(MULTSIGNOUT_33),.OVERFLOW(OVERFLOW_33),.P({P_uc_33[47:24],mult1_out[23:23],pre_out_P_0[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_33),.PATTERNDETECT(PATTERNDETECT_33),.PCOUT(PCOUT_33[47:0]),.UNDERFLOW(UNDERFLOW_33),.A({in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(VCC),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc264.ACASCREG=0;
defparam desc264.ADREG=0;
defparam desc264.ALUMODEREG=0;
defparam desc264.AREG=0;
defparam desc264.AUTORESET_PATDET="NO_RESET";
defparam desc264.A_INPUT="DIRECT";
defparam desc264.BCASCREG=0;
defparam desc264.BREG=0;
defparam desc264.B_INPUT="DIRECT";
defparam desc264.CARRYINREG=0;
defparam desc264.CARRYINSELREG=0;
defparam desc264.CREG=1;
defparam desc264.DREG=0;
defparam desc264.INMODEREG=0;
defparam desc264.MREG=1;
defparam desc264.OPMODEREG=0;
defparam desc264.PREG=0;
defparam desc264.USE_DPORT="FALSE";
defparam desc264.USE_MULT="MULTIPLY";
defparam desc264.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_1_inj (mult2_out_23,mult2_out_0,P_uc_34_0,in_a_i_reg,in_b_i_reg,clk);
output mult2_out_23 ;
output [23:0] mult2_out_0 ;
output [47:24] P_uc_34_0 ;
input [11:0] in_a_i_reg ;
input [11:0] in_b_i_reg ;
input clk ;
wire mult2_out_23 ;
wire clk ;
wire [29:0] ACOUT_34 ;
wire [17:0] BCOUT_34 ;
wire [3:0] CARRYOUT_34 ;
wire [22:0] mult2_out ;
wire [47:24] P_uc_34 ;
wire CARRYCASCOUT_34 ;
wire MULTSIGNOUT_34 ;
wire OVERFLOW_34 ;
wire PATTERNBDETECT_34 ;
wire PATTERNDETECT_34 ;
wire UNDERFLOW_34 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc265(.ACOUT(ACOUT_34[29:0]),.BCOUT(BCOUT_34[17:0]),.CARRYCASCOUT(CARRYCASCOUT_34),.CARRYOUT(CARRYOUT_34[3:0]),.MULTSIGNOUT(MULTSIGNOUT_34),.OVERFLOW(OVERFLOW_34),.P({P_uc_34[47:24],mult2_out_23,mult2_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_34),.PATTERNDETECT(PATTERNDETECT_34),.PCOUT({P_uc_34_0[47:24],mult2_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_34),.A({in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc265.ACASCREG=0;
defparam desc265.ADREG=0;
defparam desc265.ALUMODEREG=0;
defparam desc265.AREG=0;
defparam desc265.AUTORESET_PATDET="NO_RESET";
defparam desc265.A_INPUT="DIRECT";
defparam desc265.BCASCREG=0;
defparam desc265.BREG=0;
defparam desc265.B_INPUT="DIRECT";
defparam desc265.CARRYINREG=0;
defparam desc265.CARRYINSELREG=0;
defparam desc265.CREG=1;
defparam desc265.DREG=0;
defparam desc265.INMODEREG=0;
defparam desc265.MREG=0;
defparam desc265.OPMODEREG=0;
defparam desc265.PREG=1;
defparam desc265.USE_DPORT="FALSE";
defparam desc265.USE_MULT="MULTIPLY";
defparam desc265.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_10_inj (mult3_out_23,vec_out_r_AQ_1,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult3_out_23 ;
input [11:0] vec_out_r_AQ_1 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult3_out_23 ;
wire clk ;
wire [29:0] ACOUT_22 ;
wire [17:0] BCOUT_22 ;
wire [3:0] CARRYOUT_22 ;
wire [22:0] mult3_out ;
wire [47:24] P_uc_22 ;
wire [47:0] PCOUT_22 ;
wire CARRYCASCOUT_22 ;
wire MULTSIGNOUT_22 ;
wire OVERFLOW_22 ;
wire PATTERNBDETECT_22 ;
wire PATTERNDETECT_22 ;
wire UNDERFLOW_22 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc532(.ACOUT(ACOUT_22[29:0]),.BCOUT(BCOUT_22[17:0]),.CARRYCASCOUT(CARRYCASCOUT_22),.CARRYOUT(CARRYOUT_22[3:0]),.MULTSIGNOUT(MULTSIGNOUT_22),.OVERFLOW(OVERFLOW_22),.P({P_uc_22[47:24],mult3_out_23,mult3_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_22),.PATTERNDETECT(PATTERNDETECT_22),.PCOUT(PCOUT_22[47:0]),.UNDERFLOW(UNDERFLOW_22),.A({vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc532.ACASCREG=1;
defparam desc532.ADREG=0;
defparam desc532.ALUMODEREG=0;
defparam desc532.AREG=1;
defparam desc532.AUTORESET_PATDET="NO_RESET";
defparam desc532.A_INPUT="DIRECT";
defparam desc532.BCASCREG=1;
defparam desc532.BREG=1;
defparam desc532.B_INPUT="DIRECT";
defparam desc532.CARRYINREG=0;
defparam desc532.CARRYINSELREG=0;
defparam desc532.CREG=1;
defparam desc532.DREG=0;
defparam desc532.INMODEREG=0;
defparam desc532.MREG=0;
defparam desc532.OPMODEREG=0;
defparam desc532.PREG=1;
defparam desc532.USE_DPORT="FALSE";
defparam desc532.USE_MULT="MULTIPLY";
defparam desc532.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_11_inj (mult4_out_23,mult4_out_0,P_uc_23_0,out_inner_prod_r,vec_out_i_AQ_1,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult4_out_23 ;
output [23:0] mult4_out_0 ;
output [47:24] P_uc_23_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_i_AQ_1 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult4_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_23 ;
wire [17:0] BCOUT_23 ;
wire [3:0] CARRYOUT_23 ;
wire [22:0] mult4_out ;
wire [47:24] P_uc_23 ;
wire CARRYCASCOUT_23 ;
wire MULTSIGNOUT_23 ;
wire OVERFLOW_23 ;
wire PATTERNBDETECT_23 ;
wire PATTERNDETECT_23 ;
wire UNDERFLOW_23 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc533(.ACOUT(ACOUT_23[29:0]),.BCOUT(BCOUT_23[17:0]),.CARRYCASCOUT(CARRYCASCOUT_23),.CARRYOUT(CARRYOUT_23[3:0]),.MULTSIGNOUT(MULTSIGNOUT_23),.OVERFLOW(OVERFLOW_23),.P({P_uc_23[47:24],mult4_out_23,mult4_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_23),.PATTERNDETECT(PATTERNDETECT_23),.PCOUT({P_uc_23_0[47:24],mult4_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_23),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc533.ACASCREG=1;
defparam desc533.ADREG=1;
defparam desc533.ALUMODEREG=0;
defparam desc533.AREG=1;
defparam desc533.AUTORESET_PATDET="NO_RESET";
defparam desc533.A_INPUT="DIRECT";
defparam desc533.BCASCREG=2;
defparam desc533.BREG=2;
defparam desc533.B_INPUT="DIRECT";
defparam desc533.CARRYINREG=0;
defparam desc533.CARRYINSELREG=0;
defparam desc533.CREG=1;
defparam desc533.DREG=1;
defparam desc533.INMODEREG=1;
defparam desc533.MREG=0;
defparam desc533.OPMODEREG=0;
defparam desc533.PREG=0;
defparam desc533.USE_DPORT="TRUE";
defparam desc533.USE_MULT="MULTIPLY";
defparam desc533.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_12_inj (mult1_out_23,mult1_out_0,P_uc_16_0,out_inner_prod_r,vec_out_r_AQ_0,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult1_out_23 ;
output [23:0] mult1_out_0 ;
output [47:24] P_uc_16_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_0 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult1_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_16 ;
wire [17:0] BCOUT_16 ;
wire [3:0] CARRYOUT_16 ;
wire [22:0] mult1_out ;
wire [47:24] P_uc_16 ;
wire CARRYCASCOUT_16 ;
wire MULTSIGNOUT_16 ;
wire OVERFLOW_16 ;
wire PATTERNBDETECT_16 ;
wire PATTERNDETECT_16 ;
wire UNDERFLOW_16 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc585(.ACOUT(ACOUT_16[29:0]),.BCOUT(BCOUT_16[17:0]),.CARRYCASCOUT(CARRYCASCOUT_16),.CARRYOUT(CARRYOUT_16[3:0]),.MULTSIGNOUT(MULTSIGNOUT_16),.OVERFLOW(OVERFLOW_16),.P({P_uc_16[47:24],mult1_out_23,mult1_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_16),.PATTERNDETECT(PATTERNDETECT_16),.PCOUT({P_uc_16_0[47:24],mult1_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_16),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc585.ACASCREG=1;
defparam desc585.ADREG=1;
defparam desc585.ALUMODEREG=0;
defparam desc585.AREG=1;
defparam desc585.AUTORESET_PATDET="NO_RESET";
defparam desc585.A_INPUT="DIRECT";
defparam desc585.BCASCREG=2;
defparam desc585.BREG=2;
defparam desc585.B_INPUT="DIRECT";
defparam desc585.CARRYINREG=0;
defparam desc585.CARRYINSELREG=0;
defparam desc585.CREG=1;
defparam desc585.DREG=1;
defparam desc585.INMODEREG=1;
defparam desc585.MREG=0;
defparam desc585.OPMODEREG=0;
defparam desc585.PREG=0;
defparam desc585.USE_DPORT="TRUE";
defparam desc585.USE_MULT="MULTIPLY";
defparam desc585.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_13_inj (mult2_out_23,vec_out_i_AQ_0,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult2_out_23 ;
input [11:0] vec_out_i_AQ_0 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult2_out_23 ;
wire clk ;
wire [29:0] ACOUT_17 ;
wire [17:0] BCOUT_17 ;
wire [3:0] CARRYOUT_17 ;
wire [22:0] mult2_out ;
wire [47:24] P_uc_17 ;
wire [47:0] PCOUT_17 ;
wire CARRYCASCOUT_17 ;
wire MULTSIGNOUT_17 ;
wire OVERFLOW_17 ;
wire PATTERNBDETECT_17 ;
wire PATTERNDETECT_17 ;
wire UNDERFLOW_17 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc586(.ACOUT(ACOUT_17[29:0]),.BCOUT(BCOUT_17[17:0]),.CARRYCASCOUT(CARRYCASCOUT_17),.CARRYOUT(CARRYOUT_17[3:0]),.MULTSIGNOUT(MULTSIGNOUT_17),.OVERFLOW(OVERFLOW_17),.P({P_uc_17[47:24],mult2_out_23,mult2_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_17),.PATTERNDETECT(PATTERNDETECT_17),.PCOUT(PCOUT_17[47:0]),.UNDERFLOW(UNDERFLOW_17),.A({vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc586.ACASCREG=1;
defparam desc586.ADREG=0;
defparam desc586.ALUMODEREG=0;
defparam desc586.AREG=1;
defparam desc586.AUTORESET_PATDET="NO_RESET";
defparam desc586.A_INPUT="DIRECT";
defparam desc586.BCASCREG=1;
defparam desc586.BREG=1;
defparam desc586.B_INPUT="DIRECT";
defparam desc586.CARRYINREG=0;
defparam desc586.CARRYINSELREG=0;
defparam desc586.CREG=1;
defparam desc586.DREG=0;
defparam desc586.INMODEREG=0;
defparam desc586.MREG=0;
defparam desc586.OPMODEREG=0;
defparam desc586.PREG=1;
defparam desc586.USE_DPORT="FALSE";
defparam desc586.USE_MULT="MULTIPLY";
defparam desc586.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_14_inj (mult3_out_23,vec_out_r_AQ_0,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult3_out_23 ;
input [11:0] vec_out_r_AQ_0 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult3_out_23 ;
wire clk ;
wire [29:0] ACOUT_18 ;
wire [17:0] BCOUT_18 ;
wire [3:0] CARRYOUT_18 ;
wire [22:0] mult3_out ;
wire [47:24] P_uc_18 ;
wire [47:0] PCOUT_18 ;
wire CARRYCASCOUT_18 ;
wire MULTSIGNOUT_18 ;
wire OVERFLOW_18 ;
wire PATTERNBDETECT_18 ;
wire PATTERNDETECT_18 ;
wire UNDERFLOW_18 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc587(.ACOUT(ACOUT_18[29:0]),.BCOUT(BCOUT_18[17:0]),.CARRYCASCOUT(CARRYCASCOUT_18),.CARRYOUT(CARRYOUT_18[3:0]),.MULTSIGNOUT(MULTSIGNOUT_18),.OVERFLOW(OVERFLOW_18),.P({P_uc_18[47:24],mult3_out_23,mult3_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_18),.PATTERNDETECT(PATTERNDETECT_18),.PCOUT(PCOUT_18[47:0]),.UNDERFLOW(UNDERFLOW_18),.A({vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:11],vec_out_r_AQ_0[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc587.ACASCREG=1;
defparam desc587.ADREG=0;
defparam desc587.ALUMODEREG=0;
defparam desc587.AREG=1;
defparam desc587.AUTORESET_PATDET="NO_RESET";
defparam desc587.A_INPUT="DIRECT";
defparam desc587.BCASCREG=1;
defparam desc587.BREG=1;
defparam desc587.B_INPUT="DIRECT";
defparam desc587.CARRYINREG=0;
defparam desc587.CARRYINSELREG=0;
defparam desc587.CREG=1;
defparam desc587.DREG=0;
defparam desc587.INMODEREG=0;
defparam desc587.MREG=0;
defparam desc587.OPMODEREG=0;
defparam desc587.PREG=1;
defparam desc587.USE_DPORT="FALSE";
defparam desc587.USE_MULT="MULTIPLY";
defparam desc587.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_15_inj (mult4_out_23,mult4_out_0,P_uc_19_0,out_inner_prod_r,vec_out_i_AQ_0,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult4_out_23 ;
output [23:0] mult4_out_0 ;
output [47:24] P_uc_19_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_i_AQ_0 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult4_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_19 ;
wire [17:0] BCOUT_19 ;
wire [3:0] CARRYOUT_19 ;
wire [22:0] mult4_out ;
wire [47:24] P_uc_19 ;
wire CARRYCASCOUT_19 ;
wire MULTSIGNOUT_19 ;
wire OVERFLOW_19 ;
wire PATTERNBDETECT_19 ;
wire PATTERNDETECT_19 ;
wire UNDERFLOW_19 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc588(.ACOUT(ACOUT_19[29:0]),.BCOUT(BCOUT_19[17:0]),.CARRYCASCOUT(CARRYCASCOUT_19),.CARRYOUT(CARRYOUT_19[3:0]),.MULTSIGNOUT(MULTSIGNOUT_19),.OVERFLOW(OVERFLOW_19),.P({P_uc_19[47:24],mult4_out_23,mult4_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_19),.PATTERNDETECT(PATTERNDETECT_19),.PCOUT({P_uc_19_0[47:24],mult4_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_19),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:11],vec_out_i_AQ_0[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc588.ACASCREG=1;
defparam desc588.ADREG=1;
defparam desc588.ALUMODEREG=0;
defparam desc588.AREG=1;
defparam desc588.AUTORESET_PATDET="NO_RESET";
defparam desc588.A_INPUT="DIRECT";
defparam desc588.BCASCREG=2;
defparam desc588.BREG=2;
defparam desc588.B_INPUT="DIRECT";
defparam desc588.CARRYINREG=0;
defparam desc588.CARRYINSELREG=0;
defparam desc588.CREG=1;
defparam desc588.DREG=1;
defparam desc588.INMODEREG=1;
defparam desc588.MREG=0;
defparam desc588.OPMODEREG=0;
defparam desc588.PREG=0;
defparam desc588.USE_DPORT="TRUE";
defparam desc588.USE_MULT="MULTIPLY";
defparam desc588.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_16_inj (mult1_out_23,mult1_out_0,P_uc_28_0,out_inner_prod_r,vec_out_r_AQ_3,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult1_out_23 ;
output [23:0] mult1_out_0 ;
output [47:24] P_uc_28_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_3 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult1_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_28 ;
wire [17:0] BCOUT_28 ;
wire [3:0] CARRYOUT_28 ;
wire [22:0] mult1_out ;
wire [47:24] P_uc_28 ;
wire CARRYCASCOUT_28 ;
wire MULTSIGNOUT_28 ;
wire OVERFLOW_28 ;
wire PATTERNBDETECT_28 ;
wire PATTERNDETECT_28 ;
wire UNDERFLOW_28 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc640(.ACOUT(ACOUT_28[29:0]),.BCOUT(BCOUT_28[17:0]),.CARRYCASCOUT(CARRYCASCOUT_28),.CARRYOUT(CARRYOUT_28[3:0]),.MULTSIGNOUT(MULTSIGNOUT_28),.OVERFLOW(OVERFLOW_28),.P({P_uc_28[47:24],mult1_out_23,mult1_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_28),.PATTERNDETECT(PATTERNDETECT_28),.PCOUT({P_uc_28_0[47:24],mult1_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_28),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc640.ACASCREG=1;
defparam desc640.ADREG=1;
defparam desc640.ALUMODEREG=0;
defparam desc640.AREG=1;
defparam desc640.AUTORESET_PATDET="NO_RESET";
defparam desc640.A_INPUT="DIRECT";
defparam desc640.BCASCREG=2;
defparam desc640.BREG=2;
defparam desc640.B_INPUT="DIRECT";
defparam desc640.CARRYINREG=0;
defparam desc640.CARRYINSELREG=0;
defparam desc640.CREG=1;
defparam desc640.DREG=1;
defparam desc640.INMODEREG=1;
defparam desc640.MREG=0;
defparam desc640.OPMODEREG=0;
defparam desc640.PREG=0;
defparam desc640.USE_DPORT="TRUE";
defparam desc640.USE_MULT="MULTIPLY";
defparam desc640.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_17_inj (mult2_out_23,vec_out_i_AQ_3,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult2_out_23 ;
input [11:0] vec_out_i_AQ_3 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult2_out_23 ;
wire clk ;
wire [29:0] ACOUT_29 ;
wire [17:0] BCOUT_29 ;
wire [3:0] CARRYOUT_29 ;
wire [22:0] mult2_out ;
wire [47:24] P_uc_29 ;
wire [47:0] PCOUT_29 ;
wire CARRYCASCOUT_29 ;
wire MULTSIGNOUT_29 ;
wire OVERFLOW_29 ;
wire PATTERNBDETECT_29 ;
wire PATTERNDETECT_29 ;
wire UNDERFLOW_29 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc641(.ACOUT(ACOUT_29[29:0]),.BCOUT(BCOUT_29[17:0]),.CARRYCASCOUT(CARRYCASCOUT_29),.CARRYOUT(CARRYOUT_29[3:0]),.MULTSIGNOUT(MULTSIGNOUT_29),.OVERFLOW(OVERFLOW_29),.P({P_uc_29[47:24],mult2_out_23,mult2_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_29),.PATTERNDETECT(PATTERNDETECT_29),.PCOUT(PCOUT_29[47:0]),.UNDERFLOW(UNDERFLOW_29),.A({vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc641.ACASCREG=1;
defparam desc641.ADREG=0;
defparam desc641.ALUMODEREG=0;
defparam desc641.AREG=1;
defparam desc641.AUTORESET_PATDET="NO_RESET";
defparam desc641.A_INPUT="DIRECT";
defparam desc641.BCASCREG=1;
defparam desc641.BREG=1;
defparam desc641.B_INPUT="DIRECT";
defparam desc641.CARRYINREG=0;
defparam desc641.CARRYINSELREG=0;
defparam desc641.CREG=1;
defparam desc641.DREG=0;
defparam desc641.INMODEREG=0;
defparam desc641.MREG=0;
defparam desc641.OPMODEREG=0;
defparam desc641.PREG=1;
defparam desc641.USE_DPORT="FALSE";
defparam desc641.USE_MULT="MULTIPLY";
defparam desc641.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_18_inj (mult3_out_23,vec_out_r_AQ_3,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult3_out_23 ;
input [11:0] vec_out_r_AQ_3 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult3_out_23 ;
wire clk ;
wire [29:0] ACOUT_30 ;
wire [17:0] BCOUT_30 ;
wire [3:0] CARRYOUT_30 ;
wire [22:0] mult3_out ;
wire [47:24] P_uc_30 ;
wire [47:0] PCOUT_30 ;
wire CARRYCASCOUT_30 ;
wire MULTSIGNOUT_30 ;
wire OVERFLOW_30 ;
wire PATTERNBDETECT_30 ;
wire PATTERNDETECT_30 ;
wire UNDERFLOW_30 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc642(.ACOUT(ACOUT_30[29:0]),.BCOUT(BCOUT_30[17:0]),.CARRYCASCOUT(CARRYCASCOUT_30),.CARRYOUT(CARRYOUT_30[3:0]),.MULTSIGNOUT(MULTSIGNOUT_30),.OVERFLOW(OVERFLOW_30),.P({P_uc_30[47:24],mult3_out_23,mult3_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_30),.PATTERNDETECT(PATTERNDETECT_30),.PCOUT(PCOUT_30[47:0]),.UNDERFLOW(UNDERFLOW_30),.A({vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:11],vec_out_r_AQ_3[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc642.ACASCREG=1;
defparam desc642.ADREG=0;
defparam desc642.ALUMODEREG=0;
defparam desc642.AREG=1;
defparam desc642.AUTORESET_PATDET="NO_RESET";
defparam desc642.A_INPUT="DIRECT";
defparam desc642.BCASCREG=1;
defparam desc642.BREG=1;
defparam desc642.B_INPUT="DIRECT";
defparam desc642.CARRYINREG=0;
defparam desc642.CARRYINSELREG=0;
defparam desc642.CREG=1;
defparam desc642.DREG=0;
defparam desc642.INMODEREG=0;
defparam desc642.MREG=0;
defparam desc642.OPMODEREG=0;
defparam desc642.PREG=1;
defparam desc642.USE_DPORT="FALSE";
defparam desc642.USE_MULT="MULTIPLY";
defparam desc642.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_19_inj (mult4_out_23,mult4_out_0,P_uc_31_0,out_inner_prod_r,vec_out_i_AQ_3,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult4_out_23 ;
output [23:0] mult4_out_0 ;
output [47:24] P_uc_31_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_i_AQ_3 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult4_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_31 ;
wire [17:0] BCOUT_31 ;
wire [3:0] CARRYOUT_31 ;
wire [22:0] mult4_out ;
wire [47:24] P_uc_31 ;
wire CARRYCASCOUT_31 ;
wire MULTSIGNOUT_31 ;
wire OVERFLOW_31 ;
wire PATTERNBDETECT_31 ;
wire PATTERNDETECT_31 ;
wire UNDERFLOW_31 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc643(.ACOUT(ACOUT_31[29:0]),.BCOUT(BCOUT_31[17:0]),.CARRYCASCOUT(CARRYCASCOUT_31),.CARRYOUT(CARRYOUT_31[3:0]),.MULTSIGNOUT(MULTSIGNOUT_31),.OVERFLOW(OVERFLOW_31),.P({P_uc_31[47:24],mult4_out_23,mult4_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_31),.PATTERNDETECT(PATTERNDETECT_31),.PCOUT({P_uc_31_0[47:24],mult4_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_31),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:11],vec_out_i_AQ_3[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc643.ACASCREG=1;
defparam desc643.ADREG=1;
defparam desc643.ALUMODEREG=0;
defparam desc643.AREG=1;
defparam desc643.AUTORESET_PATDET="NO_RESET";
defparam desc643.A_INPUT="DIRECT";
defparam desc643.BCASCREG=2;
defparam desc643.BREG=2;
defparam desc643.B_INPUT="DIRECT";
defparam desc643.CARRYINREG=0;
defparam desc643.CARRYINSELREG=0;
defparam desc643.CREG=1;
defparam desc643.DREG=1;
defparam desc643.INMODEREG=1;
defparam desc643.MREG=0;
defparam desc643.OPMODEREG=0;
defparam desc643.PREG=0;
defparam desc643.USE_DPORT="TRUE";
defparam desc643.USE_MULT="MULTIPLY";
defparam desc643.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_2_inj (mult3_out_23,mult3_out_0,P_uc_35_0,in_a_r_reg,in_b_i_reg,clk);
output mult3_out_23 ;
output [23:0] mult3_out_0 ;
output [47:24] P_uc_35_0 ;
input [11:0] in_a_r_reg ;
input [11:0] in_b_i_reg ;
input clk ;
wire mult3_out_23 ;
wire clk ;
wire [29:0] ACOUT_35 ;
wire [17:0] BCOUT_35 ;
wire [3:0] CARRYOUT_35 ;
wire [22:0] mult3_out ;
wire [47:24] P_uc_35 ;
wire CARRYCASCOUT_35 ;
wire MULTSIGNOUT_35 ;
wire OVERFLOW_35 ;
wire PATTERNBDETECT_35 ;
wire PATTERNDETECT_35 ;
wire UNDERFLOW_35 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc266(.ACOUT(ACOUT_35[29:0]),.BCOUT(BCOUT_35[17:0]),.CARRYCASCOUT(CARRYCASCOUT_35),.CARRYOUT(CARRYOUT_35[3:0]),.MULTSIGNOUT(MULTSIGNOUT_35),.OVERFLOW(OVERFLOW_35),.P({P_uc_35[47:24],mult3_out_23,mult3_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_35),.PATTERNDETECT(PATTERNDETECT_35),.PCOUT({P_uc_35_0[47:24],mult3_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_35),.A({in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:11],in_a_r_reg[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:11],in_b_i_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc266.ACASCREG=0;
defparam desc266.ADREG=0;
defparam desc266.ALUMODEREG=0;
defparam desc266.AREG=0;
defparam desc266.AUTORESET_PATDET="NO_RESET";
defparam desc266.A_INPUT="DIRECT";
defparam desc266.BCASCREG=0;
defparam desc266.BREG=0;
defparam desc266.B_INPUT="DIRECT";
defparam desc266.CARRYINREG=0;
defparam desc266.CARRYINSELREG=0;
defparam desc266.CREG=1;
defparam desc266.DREG=0;
defparam desc266.INMODEREG=0;
defparam desc266.MREG=0;
defparam desc266.OPMODEREG=0;
defparam desc266.PREG=1;
defparam desc266.USE_DPORT="FALSE";
defparam desc266.USE_MULT="MULTIPLY";
defparam desc266.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_3_inj (mult4_out,in_a_i_reg,in_b_r_reg,clk);
output [23:23] mult4_out ;
input [11:0] in_a_i_reg ;
input [11:0] in_b_r_reg ;
input clk ;
wire clk ;
wire [29:0] ACOUT_36 ;
wire [17:0] BCOUT_36 ;
wire [3:0] CARRYOUT_36 ;
wire [22:0] pre_out_P ;
wire [47:24] P_uc_36 ;
wire [47:0] PCOUT_36 ;
wire CARRYCASCOUT_36 ;
wire MULTSIGNOUT_36 ;
wire OVERFLOW_36 ;
wire PATTERNBDETECT_36 ;
wire PATTERNDETECT_36 ;
wire UNDERFLOW_36 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc267(.ACOUT(ACOUT_36[29:0]),.BCOUT(BCOUT_36[17:0]),.CARRYCASCOUT(CARRYCASCOUT_36),.CARRYOUT(CARRYOUT_36[3:0]),.MULTSIGNOUT(MULTSIGNOUT_36),.OVERFLOW(OVERFLOW_36),.P({P_uc_36[47:24],mult4_out[23:23],pre_out_P[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_36),.PATTERNDETECT(PATTERNDETECT_36),.PCOUT(PCOUT_36[47:0]),.UNDERFLOW(UNDERFLOW_36),.A({in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:11],in_a_i_reg[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:11],in_b_r_reg[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(VCC),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc267.ACASCREG=0;
defparam desc267.ADREG=0;
defparam desc267.ALUMODEREG=0;
defparam desc267.AREG=0;
defparam desc267.AUTORESET_PATDET="NO_RESET";
defparam desc267.A_INPUT="DIRECT";
defparam desc267.BCASCREG=0;
defparam desc267.BREG=0;
defparam desc267.B_INPUT="DIRECT";
defparam desc267.CARRYINREG=0;
defparam desc267.CARRYINSELREG=0;
defparam desc267.CREG=1;
defparam desc267.DREG=0;
defparam desc267.INMODEREG=0;
defparam desc267.MREG=1;
defparam desc267.OPMODEREG=0;
defparam desc267.PREG=0;
defparam desc267.USE_DPORT="FALSE";
defparam desc267.USE_MULT="MULTIPLY";
defparam desc267.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_4_inj (mult1_out_23,mult1_out_0,P_uc_24_0,out_inner_prod_r,vec_out_r_AQ_2,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult1_out_23 ;
output [23:0] mult1_out_0 ;
output [47:24] P_uc_24_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_2 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult1_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_24 ;
wire [17:0] BCOUT_24 ;
wire [3:0] CARRYOUT_24 ;
wire [22:0] mult1_out ;
wire [47:24] P_uc_24 ;
wire CARRYCASCOUT_24 ;
wire MULTSIGNOUT_24 ;
wire OVERFLOW_24 ;
wire PATTERNBDETECT_24 ;
wire PATTERNDETECT_24 ;
wire UNDERFLOW_24 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc475(.ACOUT(ACOUT_24[29:0]),.BCOUT(BCOUT_24[17:0]),.CARRYCASCOUT(CARRYCASCOUT_24),.CARRYOUT(CARRYOUT_24[3:0]),.MULTSIGNOUT(MULTSIGNOUT_24),.OVERFLOW(OVERFLOW_24),.P({P_uc_24[47:24],mult1_out_23,mult1_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_24),.PATTERNDETECT(PATTERNDETECT_24),.PCOUT({P_uc_24_0[47:24],mult1_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_24),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc475.ACASCREG=1;
defparam desc475.ADREG=1;
defparam desc475.ALUMODEREG=0;
defparam desc475.AREG=1;
defparam desc475.AUTORESET_PATDET="NO_RESET";
defparam desc475.A_INPUT="DIRECT";
defparam desc475.BCASCREG=2;
defparam desc475.BREG=2;
defparam desc475.B_INPUT="DIRECT";
defparam desc475.CARRYINREG=0;
defparam desc475.CARRYINSELREG=0;
defparam desc475.CREG=1;
defparam desc475.DREG=1;
defparam desc475.INMODEREG=1;
defparam desc475.MREG=0;
defparam desc475.OPMODEREG=0;
defparam desc475.PREG=0;
defparam desc475.USE_DPORT="TRUE";
defparam desc475.USE_MULT="MULTIPLY";
defparam desc475.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_5_inj (mult2_out_23,vec_out_i_AQ_2,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult2_out_23 ;
input [11:0] vec_out_i_AQ_2 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult2_out_23 ;
wire clk ;
wire [29:0] ACOUT_25 ;
wire [17:0] BCOUT_25 ;
wire [3:0] CARRYOUT_25 ;
wire [22:0] mult2_out ;
wire [47:24] P_uc_25 ;
wire [47:0] PCOUT_25 ;
wire CARRYCASCOUT_25 ;
wire MULTSIGNOUT_25 ;
wire OVERFLOW_25 ;
wire PATTERNBDETECT_25 ;
wire PATTERNDETECT_25 ;
wire UNDERFLOW_25 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc476(.ACOUT(ACOUT_25[29:0]),.BCOUT(BCOUT_25[17:0]),.CARRYCASCOUT(CARRYCASCOUT_25),.CARRYOUT(CARRYOUT_25[3:0]),.MULTSIGNOUT(MULTSIGNOUT_25),.OVERFLOW(OVERFLOW_25),.P({P_uc_25[47:24],mult2_out_23,mult2_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_25),.PATTERNDETECT(PATTERNDETECT_25),.PCOUT(PCOUT_25[47:0]),.UNDERFLOW(UNDERFLOW_25),.A({vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc476.ACASCREG=1;
defparam desc476.ADREG=0;
defparam desc476.ALUMODEREG=0;
defparam desc476.AREG=1;
defparam desc476.AUTORESET_PATDET="NO_RESET";
defparam desc476.A_INPUT="DIRECT";
defparam desc476.BCASCREG=1;
defparam desc476.BREG=1;
defparam desc476.B_INPUT="DIRECT";
defparam desc476.CARRYINREG=0;
defparam desc476.CARRYINSELREG=0;
defparam desc476.CREG=1;
defparam desc476.DREG=0;
defparam desc476.INMODEREG=0;
defparam desc476.MREG=0;
defparam desc476.OPMODEREG=0;
defparam desc476.PREG=1;
defparam desc476.USE_DPORT="FALSE";
defparam desc476.USE_MULT="MULTIPLY";
defparam desc476.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_6_inj (mult3_out_23,vec_out_r_AQ_2,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult3_out_23 ;
input [11:0] vec_out_r_AQ_2 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult3_out_23 ;
wire clk ;
wire [29:0] ACOUT_26 ;
wire [17:0] BCOUT_26 ;
wire [3:0] CARRYOUT_26 ;
wire [22:0] mult3_out ;
wire [47:24] P_uc_26 ;
wire [47:0] PCOUT_26 ;
wire CARRYCASCOUT_26 ;
wire MULTSIGNOUT_26 ;
wire OVERFLOW_26 ;
wire PATTERNBDETECT_26 ;
wire PATTERNDETECT_26 ;
wire UNDERFLOW_26 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc477(.ACOUT(ACOUT_26[29:0]),.BCOUT(BCOUT_26[17:0]),.CARRYCASCOUT(CARRYCASCOUT_26),.CARRYOUT(CARRYOUT_26[3:0]),.MULTSIGNOUT(MULTSIGNOUT_26),.OVERFLOW(OVERFLOW_26),.P({P_uc_26[47:24],mult3_out_23,mult3_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_26),.PATTERNDETECT(PATTERNDETECT_26),.PCOUT(PCOUT_26[47:0]),.UNDERFLOW(UNDERFLOW_26),.A({vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:11],vec_out_r_AQ_2[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc477.ACASCREG=1;
defparam desc477.ADREG=0;
defparam desc477.ALUMODEREG=0;
defparam desc477.AREG=1;
defparam desc477.AUTORESET_PATDET="NO_RESET";
defparam desc477.A_INPUT="DIRECT";
defparam desc477.BCASCREG=1;
defparam desc477.BREG=1;
defparam desc477.B_INPUT="DIRECT";
defparam desc477.CARRYINREG=0;
defparam desc477.CARRYINSELREG=0;
defparam desc477.CREG=1;
defparam desc477.DREG=0;
defparam desc477.INMODEREG=0;
defparam desc477.MREG=0;
defparam desc477.OPMODEREG=0;
defparam desc477.PREG=1;
defparam desc477.USE_DPORT="FALSE";
defparam desc477.USE_MULT="MULTIPLY";
defparam desc477.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_7_inj (mult4_out_23,mult4_out_0,P_uc_27_0,out_inner_prod_r,vec_out_i_AQ_2,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult4_out_23 ;
output [23:0] mult4_out_0 ;
output [47:24] P_uc_27_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_i_AQ_2 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult4_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_27 ;
wire [17:0] BCOUT_27 ;
wire [3:0] CARRYOUT_27 ;
wire [22:0] mult4_out ;
wire [47:24] P_uc_27 ;
wire CARRYCASCOUT_27 ;
wire MULTSIGNOUT_27 ;
wire OVERFLOW_27 ;
wire PATTERNBDETECT_27 ;
wire PATTERNDETECT_27 ;
wire UNDERFLOW_27 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc478(.ACOUT(ACOUT_27[29:0]),.BCOUT(BCOUT_27[17:0]),.CARRYCASCOUT(CARRYCASCOUT_27),.CARRYOUT(CARRYOUT_27[3:0]),.MULTSIGNOUT(MULTSIGNOUT_27),.OVERFLOW(OVERFLOW_27),.P({P_uc_27[47:24],mult4_out_23,mult4_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_27),.PATTERNDETECT(PATTERNDETECT_27),.PCOUT({P_uc_27_0[47:24],mult4_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_27),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:11],vec_out_i_AQ_2[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc478.ACASCREG=1;
defparam desc478.ADREG=1;
defparam desc478.ALUMODEREG=0;
defparam desc478.AREG=1;
defparam desc478.AUTORESET_PATDET="NO_RESET";
defparam desc478.A_INPUT="DIRECT";
defparam desc478.BCASCREG=2;
defparam desc478.BREG=2;
defparam desc478.B_INPUT="DIRECT";
defparam desc478.CARRYINREG=0;
defparam desc478.CARRYINSELREG=0;
defparam desc478.CREG=1;
defparam desc478.DREG=1;
defparam desc478.INMODEREG=1;
defparam desc478.MREG=0;
defparam desc478.OPMODEREG=0;
defparam desc478.PREG=0;
defparam desc478.USE_DPORT="TRUE";
defparam desc478.USE_MULT="MULTIPLY";
defparam desc478.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_8_inj (mult1_out_23,mult1_out_0,P_uc_20_0,out_inner_prod_r,vec_out_r_AQ_1,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,in_b_vec_mult_sel,clk,N_425_i,N_428_i,N_431_i,N_434_i);
output mult1_out_23 ;
output [23:0] mult1_out_0 ;
output [47:24] P_uc_20_0 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_1 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input in_b_vec_mult_sel ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire mult1_out_23 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [29:0] ACOUT_20 ;
wire [17:0] BCOUT_20 ;
wire [3:0] CARRYOUT_20 ;
wire [22:0] mult1_out ;
wire [47:24] P_uc_20 ;
wire CARRYCASCOUT_20 ;
wire MULTSIGNOUT_20 ;
wire OVERFLOW_20 ;
wire PATTERNBDETECT_20 ;
wire PATTERNDETECT_20 ;
wire UNDERFLOW_20 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc530(.ACOUT(ACOUT_20[29:0]),.BCOUT(BCOUT_20[17:0]),.CARRYCASCOUT(CARRYCASCOUT_20),.CARRYOUT(CARRYOUT_20[3:0]),.MULTSIGNOUT(MULTSIGNOUT_20),.OVERFLOW(OVERFLOW_20),.P({P_uc_20[47:24],mult1_out_23,mult1_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_20),.PATTERNDETECT(PATTERNDETECT_20),.PCOUT({P_uc_20_0[47:24],mult1_out_0[23:0]}),.UNDERFLOW(UNDERFLOW_20),.A({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:11],vec_out_r_AQ_1[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(VCC),.CEALUMODE(GND),.CEB1(VCC),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(VCC),.CEINMODE(VCC),.CEM(GND),.CEP(GND),.CLK(clk),.D({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.INMODE({GND,GND,in_b_vec_mult_sel,in_b_vec_mult_sel,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc530.ACASCREG=1;
defparam desc530.ADREG=1;
defparam desc530.ALUMODEREG=0;
defparam desc530.AREG=1;
defparam desc530.AUTORESET_PATDET="NO_RESET";
defparam desc530.A_INPUT="DIRECT";
defparam desc530.BCASCREG=2;
defparam desc530.BREG=2;
defparam desc530.B_INPUT="DIRECT";
defparam desc530.CARRYINREG=0;
defparam desc530.CARRYINSELREG=0;
defparam desc530.CREG=1;
defparam desc530.DREG=1;
defparam desc530.INMODEREG=1;
defparam desc530.MREG=0;
defparam desc530.OPMODEREG=0;
defparam desc530.PREG=0;
defparam desc530.USE_DPORT="TRUE";
defparam desc530.USE_MULT="MULTIPLY";
defparam desc530.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_pipe_9_inj (mult2_out_23,vec_out_i_AQ_1,out_inner_prod_i,in_b_vec_mult_sel,clk);
output mult2_out_23 ;
input [11:0] vec_out_i_AQ_1 ;
input [11:0] out_inner_prod_i ;
input in_b_vec_mult_sel ;
input clk ;
wire mult2_out_23 ;
wire clk ;
wire [29:0] ACOUT_21 ;
wire [17:0] BCOUT_21 ;
wire [3:0] CARRYOUT_21 ;
wire [22:0] mult2_out ;
wire [47:24] P_uc_21 ;
wire [47:0] PCOUT_21 ;
wire CARRYCASCOUT_21 ;
wire MULTSIGNOUT_21 ;
wire OVERFLOW_21 ;
wire PATTERNBDETECT_21 ;
wire PATTERNDETECT_21 ;
wire UNDERFLOW_21 ;
wire VCC ;
wire GND ;
// instances
DSP48E1 desc531(.ACOUT(ACOUT_21[29:0]),.BCOUT(BCOUT_21[17:0]),.CARRYCASCOUT(CARRYCASCOUT_21),.CARRYOUT(CARRYOUT_21[3:0]),.MULTSIGNOUT(MULTSIGNOUT_21),.OVERFLOW(OVERFLOW_21),.P({P_uc_21[47:24],mult2_out_23,mult2_out[22:0]}),.PATTERNBDETECT(PATTERNBDETECT_21),.PATTERNDETECT(PATTERNDETECT_21),.PCOUT(PCOUT_21[47:0]),.UNDERFLOW(UNDERFLOW_21),.A({vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:11],vec_out_i_AQ_1[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:11],out_inner_prod_i[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(VCC),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(in_b_vec_mult_sel),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc531.ACASCREG=1;
defparam desc531.ADREG=0;
defparam desc531.ALUMODEREG=0;
defparam desc531.AREG=1;
defparam desc531.AUTORESET_PATDET="NO_RESET";
defparam desc531.A_INPUT="DIRECT";
defparam desc531.BCASCREG=1;
defparam desc531.BREG=1;
defparam desc531.B_INPUT="DIRECT";
defparam desc531.CARRYINREG=0;
defparam desc531.CARRYINSELREG=0;
defparam desc531.CREG=1;
defparam desc531.DREG=0;
defparam desc531.INMODEREG=0;
defparam desc531.MREG=0;
defparam desc531.OPMODEREG=0;
defparam desc531.PREG=1;
defparam desc531.USE_DPORT="FALSE";
defparam desc531.USE_MULT="MULTIPLY";
defparam desc531.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module mult_with_reg_inj (un8_rnd_out,un8_rnd_out_P_19,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,out_inner_prod_r,pre_out_19,pre_out_20,pre_out_21,pre_out_22,pre_out_reg,N_425_i,N_428_i,N_431_i,N_434_i,N_512_i,clk,PATTERNDETECT_32);
output [10:0] un8_rnd_out ;
output un8_rnd_out_P_19 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input [11:0] out_inner_prod_r ;
output pre_out_19 ;
output pre_out_20 ;
output pre_out_21 ;
output pre_out_22 ;
output [23:23] pre_out_reg ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
input N_512_i ;
input clk ;
output PATTERNDETECT_32 ;
wire un8_rnd_out_P_19 ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire pre_out_19 ;
wire pre_out_20 ;
wire pre_out_21 ;
wire pre_out_22 ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire N_512_i ;
wire clk ;
wire PATTERNDETECT_32 ;
wire [29:0] ACOUT_12 ;
wire [17:0] BCOUT_12 ;
wire [3:0] CARRYOUT_12 ;
wire [6:0] un8_rnd_out_P ;
wire [23:20] P_uc_2 ;
wire [47:24] P_uc_12 ;
wire [47:0] PCOUT_12 ;
wire [29:0] ACOUT_32 ;
wire [17:0] BCOUT_32 ;
wire [3:0] CARRYOUT_32 ;
wire [18:0] pre_out ;
wire [47:24] P_uc_32 ;
wire [47:0] PCOUT_32 ;
wire CARRYCASCOUT_12 ;
wire MULTSIGNOUT_12 ;
wire OVERFLOW_12 ;
wire N_3 ;
wire PATTERNBDETECT_12 ;
wire PATTERNDETECT_12 ;
wire UNDERFLOW_12 ;
wire VCC ;
wire GND ;
wire CARRYCASCOUT_32 ;
wire MULTSIGNOUT_32 ;
wire OVERFLOW_32 ;
wire PATTERNBDETECT_32 ;
wire UNDERFLOW_32 ;
// instances
DSP48E1 desc843(.ACOUT(ACOUT_12[29:0]),.BCOUT(BCOUT_12[17:0]),.CARRYCASCOUT(CARRYCASCOUT_12),.CARRYOUT(CARRYOUT_12[3:0]),.MULTSIGNOUT(MULTSIGNOUT_12),.OVERFLOW(OVERFLOW_12),.P({P_uc_12[47:24],P_uc_2[23:20],un8_rnd_out_P_19,un8_rnd_out[10:0],N_3,un8_rnd_out_P[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_12),.PATTERNDETECT(PATTERNDETECT_12),.PCOUT(PCOUT_12[47:0]),.UNDERFLOW(UNDERFLOW_12),.A({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,GND,GND,GND,GND,GND,GND,GND}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(N_512_i),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,VCC,VCC,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc843.ACASCREG=2;
defparam desc843.ADREG=0;
defparam desc843.ALUMODEREG=0;
defparam desc843.AREG=2;
defparam desc843.AUTORESET_PATDET="NO_RESET";
defparam desc843.A_INPUT="DIRECT";
defparam desc843.BCASCREG=1;
defparam desc843.BREG=1;
defparam desc843.B_INPUT="DIRECT";
defparam desc843.CARRYINREG=0;
defparam desc843.CARRYINSELREG=0;
defparam desc843.CREG=0;
defparam desc843.DREG=0;
defparam desc843.INMODEREG=0;
defparam desc843.MREG=0;
defparam desc843.OPMODEREG=0;
defparam desc843.PREG=0;
defparam desc843.USE_DPORT="FALSE";
defparam desc843.USE_MULT="MULTIPLY";
defparam desc843.USE_SIMD="ONE48";
DSP48E1 desc844(.ACOUT(ACOUT_32[29:0]),.BCOUT(BCOUT_32[17:0]),.CARRYCASCOUT(CARRYCASCOUT_32),.CARRYOUT(CARRYOUT_32[3:0]),.MULTSIGNOUT(MULTSIGNOUT_32),.OVERFLOW(OVERFLOW_32),.P({P_uc_32[47:24],pre_out_reg[23:23],pre_out_22,pre_out_21,pre_out_20,pre_out_19,pre_out[18:0]}),.PATTERNBDETECT(PATTERNBDETECT_32),.PATTERNDETECT(PATTERNDETECT_32),.PCOUT(PCOUT_32[47:0]),.UNDERFLOW(UNDERFLOW_32),.A({out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_11,out_inv_sqrt_10,out_inv_sqrt_9,out_inv_sqrt_8,out_inv_sqrt_7,N_434_i,N_431_i,N_428_i,N_425_i,out_inv_sqrt_2,out_inv_sqrt_1,out_inv_sqrt_0}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(N_512_i),.CEA2(VCC),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(VCC),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc844.ACASCREG=2;
defparam desc844.ADREG=0;
defparam desc844.ALUMODEREG=0;
defparam desc844.AREG=2;
defparam desc844.AUTORESET_PATDET="NO_RESET";
defparam desc844.A_INPUT="DIRECT";
defparam desc844.BCASCREG=1;
defparam desc844.BREG=1;
defparam desc844.B_INPUT="DIRECT";
defparam desc844.CARRYINREG=0;
defparam desc844.CARRYINSELREG=0;
defparam desc844.CREG=1;
defparam desc844.DREG=0;
defparam desc844.INMODEREG=0;
defparam desc844.MASK=48'b111111111111111111111111011111111111111111111111;
defparam desc844.MREG=0;
defparam desc844.OPMODEREG=0;
defparam desc844.PATTERN=48'b111111111111111111111111111111111111111111111111;
defparam desc844.PREG=0;
defparam desc844.SEL_MASK="MASK";
defparam desc844.USE_DPORT="FALSE";
defparam desc844.USE_MULT="MULTIPLY";
defparam desc844.USE_PATTERN_DETECT="PATDET";
defparam desc844.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module multiplier_inj (mult1_out,pre_output);
output [11:0] mult1_out ;
input [11:0] pre_output ;
wire [23:0] pre_out ;
wire [18:8] un8_rnd_out_P ;
wire [19:19] un8_rnd_out_P_0 ;
wire [29:0] ACOUT_9 ;
wire [17:0] BCOUT_9 ;
wire [3:0] CARRYOUT_9 ;
wire [6:0] un8_rnd_out_P_1 ;
wire [23:20] P_uc ;
wire [47:24] P_uc_9 ;
wire [47:0] PCOUT_9 ;
wire [29:0] ACOUT_13 ;
wire [17:0] BCOUT_13 ;
wire [3:0] CARRYOUT_13 ;
wire [47:24] P_uc_13 ;
wire [47:0] PCOUT_13 ;
wire un5_output_3_0 ;
wire PATTERNDETECT_13 ;
wire CARRYCASCOUT_9 ;
wire MULTSIGNOUT_9 ;
wire OVERFLOW_9 ;
wire N_15 ;
wire PATTERNBDETECT_9 ;
wire PATTERNDETECT_9 ;
wire UNDERFLOW_9 ;
wire VCC ;
wire GND ;
wire CARRYCASCOUT_13 ;
wire MULTSIGNOUT_13 ;
wire OVERFLOW_13 ;
wire PATTERNBDETECT_13 ;
wire UNDERFLOW_13 ;
// instances
LUT2 desc910(.I0(pre_out[21:21]),.I1(pre_out[22:22]),.O(un5_output_3_0));
defparam desc910.INIT=4'h8;
LUT6 desc911(.I0(un8_rnd_out_P[8:8]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[0:0]));
defparam desc911.INIT=64'h80AA00AA80FF00FF;
LUT6 desc912(.I0(un8_rnd_out_P[9:9]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[1:1]));
defparam desc912.INIT=64'h80AA00AA80FF00FF;
LUT6 desc913(.I0(un8_rnd_out_P[10:10]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[2:2]));
defparam desc913.INIT=64'h80AA00AA80FF00FF;
LUT6 desc914(.I0(un8_rnd_out_P[11:11]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[3:3]));
defparam desc914.INIT=64'h80AA00AA80FF00FF;
LUT6 desc915(.I0(un8_rnd_out_P[12:12]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[4:4]));
defparam desc915.INIT=64'h80AA00AA80FF00FF;
LUT6 desc916(.I0(un8_rnd_out_P[13:13]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[5:5]));
defparam desc916.INIT=64'h80AA00AA80FF00FF;
LUT6 desc917(.I0(un8_rnd_out_P[14:14]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[6:6]));
defparam desc917.INIT=64'h80AA00AA80FF00FF;
LUT6 desc918(.I0(un8_rnd_out_P[15:15]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[7:7]));
defparam desc918.INIT=64'h80AA00AA80FF00FF;
LUT6 desc919(.I0(un8_rnd_out_P[16:16]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[8:8]));
defparam desc919.INIT=64'h80AA00AA80FF00FF;
LUT6 desc920(.I0(un8_rnd_out_P[17:17]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[9:9]));
defparam desc920.INIT=64'h80AA00AA80FF00FF;
LUT6 desc921(.I0(un8_rnd_out_P[18:18]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[10:10]));
defparam desc921.INIT=64'h80AA00AA80FF00FF;
LUT6 desc922(.I0(un8_rnd_out_P_0[19:19]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_13),.O(mult1_out[11:11]));
defparam desc922.INIT=64'hBFAAFFAABF00FF00;
DSP48E1 desc923(.ACOUT(ACOUT_9[29:0]),.BCOUT(BCOUT_9[17:0]),.CARRYCASCOUT(CARRYCASCOUT_9),.CARRYOUT(CARRYOUT_9[3:0]),.MULTSIGNOUT(MULTSIGNOUT_9),.OVERFLOW(OVERFLOW_9),.P({P_uc_9[47:24],P_uc[23:20],un8_rnd_out_P_0[19:19],un8_rnd_out_P[18:8],N_15,un8_rnd_out_P_1[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_9),.PATTERNDETECT(PATTERNDETECT_9),.PCOUT(PCOUT_9[47:0]),.UNDERFLOW(UNDERFLOW_9),.A({pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,GND,GND,GND,GND,GND,GND,GND}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(GND),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,VCC,VCC,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc923.ACASCREG=0;
defparam desc923.ADREG=0;
defparam desc923.ALUMODEREG=0;
defparam desc923.AREG=0;
defparam desc923.AUTORESET_PATDET="NO_RESET";
defparam desc923.A_INPUT="DIRECT";
defparam desc923.BCASCREG=0;
defparam desc923.BREG=0;
defparam desc923.B_INPUT="DIRECT";
defparam desc923.CARRYINREG=0;
defparam desc923.CARRYINSELREG=0;
defparam desc923.CREG=0;
defparam desc923.DREG=0;
defparam desc923.INMODEREG=0;
defparam desc923.MREG=0;
defparam desc923.OPMODEREG=0;
defparam desc923.PREG=0;
defparam desc923.USE_DPORT="FALSE";
defparam desc923.USE_MULT="MULTIPLY";
defparam desc923.USE_SIMD="ONE48";
DSP48E1 desc924(.ACOUT(ACOUT_13[29:0]),.BCOUT(BCOUT_13[17:0]),.CARRYCASCOUT(CARRYCASCOUT_13),.CARRYOUT(CARRYOUT_13[3:0]),.MULTSIGNOUT(MULTSIGNOUT_13),.OVERFLOW(OVERFLOW_13),.P({P_uc_13[47:24],pre_out[23:0]}),.PATTERNBDETECT(PATTERNBDETECT_13),.PATTERNDETECT(PATTERNDETECT_13),.PCOUT(PCOUT_13[47:0]),.UNDERFLOW(UNDERFLOW_13),.A({pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(GND),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(GND),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc924.ACASCREG=0;
defparam desc924.ADREG=0;
defparam desc924.ALUMODEREG=0;
defparam desc924.AREG=0;
defparam desc924.AUTORESET_PATDET="NO_RESET";
defparam desc924.A_INPUT="DIRECT";
defparam desc924.BCASCREG=0;
defparam desc924.BREG=0;
defparam desc924.B_INPUT="DIRECT";
defparam desc924.CARRYINREG=0;
defparam desc924.CARRYINSELREG=0;
defparam desc924.CREG=1;
defparam desc924.DREG=0;
defparam desc924.INMODEREG=0;
defparam desc924.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc924.MREG=0;
defparam desc924.OPMODEREG=0;
defparam desc924.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc924.PREG=0;
defparam desc924.SEL_MASK="MASK";
defparam desc924.USE_DPORT="FALSE";
defparam desc924.USE_MULT="MULTIPLY";
defparam desc924.USE_PATTERN_DETECT="PATDET";
defparam desc924.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module multiplier_1_inj (mult2_out,pre_output,out_inner_prod_r,start_inv_sqrt,clk);
output [11:0] mult2_out ;
input [11:0] pre_output ;
input [11:0] out_inner_prod_r ;
input start_inv_sqrt ;
input clk ;
wire start_inv_sqrt ;
wire clk ;
wire [23:0] pre_out ;
wire [18:0] un8_rnd_out_P_0 ;
wire [19:19] un8_rnd_out_P_1 ;
wire [29:0] ACOUT_10 ;
wire [17:0] BCOUT_10 ;
wire [3:0] CARRYOUT_10 ;
wire [23:20] P_uc_0 ;
wire [47:24] P_uc_10 ;
wire [47:0] PCOUT_10 ;
wire [29:0] ACOUT_14 ;
wire [17:0] BCOUT_14 ;
wire [3:0] CARRYOUT_14 ;
wire [47:24] P_uc_14 ;
wire [47:0] PCOUT_14 ;
wire un5_output_3_0 ;
wire PATTERNDETECT_14 ;
wire CARRYCASCOUT_10 ;
wire MULTSIGNOUT_10 ;
wire OVERFLOW_10 ;
wire N_3 ;
wire PATTERNBDETECT_10 ;
wire PATTERNDETECT_10 ;
wire UNDERFLOW_10 ;
wire VCC ;
wire GND ;
wire CARRYCASCOUT_14 ;
wire MULTSIGNOUT_14 ;
wire OVERFLOW_14 ;
wire PATTERNBDETECT_14 ;
wire UNDERFLOW_14 ;
// instances
LUT2 desc925(.I0(pre_out[21:21]),.I1(pre_out[22:22]),.O(un5_output_3_0));
defparam desc925.INIT=4'h8;
LUT6 desc926(.I0(un8_rnd_out_P_0[8:8]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[0:0]));
defparam desc926.INIT=64'h80AA00AA80FF00FF;
LUT6 desc927(.I0(un8_rnd_out_P_0[9:9]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[1:1]));
defparam desc927.INIT=64'h80AA00AA80FF00FF;
LUT6 desc928(.I0(un8_rnd_out_P_0[10:10]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[2:2]));
defparam desc928.INIT=64'h80AA00AA80FF00FF;
LUT6 desc929(.I0(un8_rnd_out_P_0[11:11]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[3:3]));
defparam desc929.INIT=64'h80AA00AA80FF00FF;
LUT6 desc930(.I0(un8_rnd_out_P_0[12:12]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[4:4]));
defparam desc930.INIT=64'h80AA00AA80FF00FF;
LUT6 desc931(.I0(un8_rnd_out_P_0[13:13]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[5:5]));
defparam desc931.INIT=64'h80AA00AA80FF00FF;
LUT6 desc932(.I0(un8_rnd_out_P_0[14:14]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[6:6]));
defparam desc932.INIT=64'h80AA00AA80FF00FF;
LUT6 desc933(.I0(un8_rnd_out_P_0[15:15]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[7:7]));
defparam desc933.INIT=64'h80AA00AA80FF00FF;
LUT6 desc934(.I0(un8_rnd_out_P_0[16:16]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[8:8]));
defparam desc934.INIT=64'h80AA00AA80FF00FF;
LUT6 desc935(.I0(un8_rnd_out_P_0[17:17]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[9:9]));
defparam desc935.INIT=64'h80AA00AA80FF00FF;
LUT6 desc936(.I0(un8_rnd_out_P_0[18:18]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[10:10]));
defparam desc936.INIT=64'h80AA00AA80FF00FF;
LUT6 desc937(.I0(un8_rnd_out_P_1[19:19]),.I1(pre_out[19:19]),.I2(pre_out[20:20]),.I3(pre_out[23:23]),.I4(un5_output_3_0),.I5(PATTERNDETECT_14),.O(mult2_out[11:11]));
defparam desc937.INIT=64'hBFAAFFAABF00FF00;
DSP48E1 desc938(.ACOUT(ACOUT_10[29:0]),.BCOUT(BCOUT_10[17:0]),.CARRYCASCOUT(CARRYCASCOUT_10),.CARRYOUT(CARRYOUT_10[3:0]),.MULTSIGNOUT(MULTSIGNOUT_10),.OVERFLOW(OVERFLOW_10),.P({P_uc_10[47:24],P_uc_0[23:20],un8_rnd_out_P_1[19:19],un8_rnd_out_P_0[18:8],N_3,un8_rnd_out_P_0[6:0]}),.PATTERNBDETECT(PATTERNBDETECT_10),.PATTERNDETECT(PATTERNDETECT_10),.PCOUT(PCOUT_10[47:0]),.UNDERFLOW(UNDERFLOW_10),.A({pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,VCC,GND,GND,GND,GND,GND,GND,GND}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(start_inv_sqrt),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,VCC,VCC,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc938.ACASCREG=0;
defparam desc938.ADREG=0;
defparam desc938.ALUMODEREG=0;
defparam desc938.AREG=0;
defparam desc938.AUTORESET_PATDET="NO_RESET";
defparam desc938.A_INPUT="DIRECT";
defparam desc938.BCASCREG=1;
defparam desc938.BREG=1;
defparam desc938.B_INPUT="DIRECT";
defparam desc938.CARRYINREG=0;
defparam desc938.CARRYINSELREG=0;
defparam desc938.CREG=0;
defparam desc938.DREG=0;
defparam desc938.INMODEREG=0;
defparam desc938.MREG=0;
defparam desc938.OPMODEREG=0;
defparam desc938.PREG=0;
defparam desc938.USE_DPORT="FALSE";
defparam desc938.USE_MULT="MULTIPLY";
defparam desc938.USE_SIMD="ONE48";
DSP48E1 desc939(.ACOUT(ACOUT_14[29:0]),.BCOUT(BCOUT_14[17:0]),.CARRYCASCOUT(CARRYCASCOUT_14),.CARRYOUT(CARRYOUT_14[3:0]),.MULTSIGNOUT(MULTSIGNOUT_14),.OVERFLOW(OVERFLOW_14),.P({P_uc_14[47:24],pre_out[23:0]}),.PATTERNBDETECT(PATTERNBDETECT_14),.PATTERNDETECT(PATTERNDETECT_14),.PCOUT(PCOUT_14[47:0]),.UNDERFLOW(UNDERFLOW_14),.A({pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:11],pre_output[11:0]}),.ACIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.ALUMODE({GND,GND,GND,GND}),.B({out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:11],out_inner_prod_r[11:0]}),.BCIN({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.C({VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC,VCC}),.CARRYCASCIN(GND),.CARRYIN(GND),.CARRYINSEL({GND,GND,GND}),.CEA1(GND),.CEA2(GND),.CEAD(GND),.CEALUMODE(GND),.CEB1(GND),.CEB2(start_inv_sqrt),.CEC(GND),.CECARRYIN(GND),.CECTRL(GND),.CED(GND),.CEINMODE(GND),.CEM(GND),.CEP(GND),.CLK(clk),.D({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.INMODE({GND,GND,GND,GND,GND}),.MULTSIGNIN(GND),.OPMODE({GND,GND,GND,GND,VCC,GND,VCC}),.PCIN({GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND,GND}),.RSTA(GND),.RSTALLCARRYIN(GND),.RSTALUMODE(GND),.RSTB(GND),.RSTC(GND),.RSTCTRL(GND),.RSTD(GND),.RSTINMODE(GND),.RSTM(GND),.RSTP(GND));
defparam desc939.ACASCREG=0;
defparam desc939.ADREG=0;
defparam desc939.ALUMODEREG=0;
defparam desc939.AREG=0;
defparam desc939.AUTORESET_PATDET="NO_RESET";
defparam desc939.A_INPUT="DIRECT";
defparam desc939.BCASCREG=1;
defparam desc939.BREG=1;
defparam desc939.B_INPUT="DIRECT";
defparam desc939.CARRYINREG=0;
defparam desc939.CARRYINSELREG=0;
defparam desc939.CREG=1;
defparam desc939.DREG=0;
defparam desc939.INMODEREG=0;
defparam desc939.MASK=48'b111111111111111111111111100001111111111111111111;
defparam desc939.MREG=0;
defparam desc939.OPMODEREG=0;
defparam desc939.PATTERN=48'b111111111111111111111111100001111111111111111111;
defparam desc939.PREG=0;
defparam desc939.SEL_MASK="MASK";
defparam desc939.USE_DPORT="FALSE";
defparam desc939.USE_MULT="MULTIPLY";
defparam desc939.USE_PATTERN_DETECT="PATDET";
defparam desc939.USE_SIMD="ONE48";
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module qr_decomp_inj (out_Q_r,out_Q_i,col_sel_R,out_R_i,out_R_r,col_sel_AQ,in_A_r,in_A_i,clk,rst,wr_A_QR,start_QR,done_QR,red_mat_reg_0,p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_,p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_,p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_,p_desc951_p_O_FDEinv_sqrt_,p_desc952_p_O_FDEinv_sqrt_,p_desc953_p_O_FDEinv_sqrt_,p_desc954_p_O_FDEinv_sqrt_,p_desc955_p_O_FDEinv_sqrt_,p_desc956_p_O_FDEinv_sqrt_,p_desc957_p_O_FDEinv_sqrt_,p_desc958_p_O_FDEinv_sqrt_,p_desc959_p_O_FDEinv_sqrt_,p_desc960_p_O_FDEinv_sqrt_,p_desc961_p_O_FDEinv_sqrt_,p_desc962_p_O_FDEinv_sqrt_,p_desc48_p_O_FDEr_mat_regs_,p_desc49_p_O_FDEr_mat_regs_,p_desc50_p_O_FDEr_mat_regs_,p_desc51_p_O_FDEr_mat_regs_,p_desc52_p_O_FDEr_mat_regs_,p_desc53_p_O_FDEr_mat_regs_,p_desc54_p_O_FDEr_mat_regs_,p_desc55_p_O_FDEr_mat_regs_,p_desc56_p_O_FDEr_mat_regs_,p_desc57_p_O_FDEr_mat_regs_,p_desc58_p_O_FDEr_mat_regs_,p_desc59_p_O_FDEr_mat_regs_,p_desc60_p_O_FDEr_mat_regs_,p_desc61_p_O_FDEr_mat_regs_,p_desc62_p_O_FDEr_mat_regs_,p_desc63_p_O_FDEr_mat_regs_,p_desc64_p_O_FDEr_mat_regs_,p_desc65_p_O_FDEr_mat_regs_,p_desc66_p_O_FDEr_mat_regs_,p_desc67_p_O_FDEr_mat_regs_,p_desc68_p_O_FDEr_mat_regs_,p_desc69_p_O_FDEr_mat_regs_,p_desc70_p_O_FDEr_mat_regs_,p_desc71_p_O_FDEr_mat_regs_,p_desc72_p_O_FDEr_mat_regs_,p_desc73_p_O_FDEr_mat_regs_,p_desc74_p_O_FDEr_mat_regs_,p_desc75_p_O_FDEr_mat_regs_,p_desc76_p_O_FDEr_mat_regs_,p_desc77_p_O_FDEr_mat_regs_,p_desc78_p_O_FDEr_mat_regs_,p_desc79_p_O_FDEr_mat_regs_,p_desc80_p_O_FDEr_mat_regs_,p_desc81_p_O_FDEr_mat_regs_,p_desc82_p_O_FDEr_mat_regs_,p_desc83_p_O_FDEr_mat_regs_,p_desc84_p_O_FDEr_mat_regs_,p_desc85_p_O_FDEr_mat_regs_,p_desc86_p_O_FDEr_mat_regs_,p_desc87_p_O_FDEr_mat_regs_,p_desc88_p_O_FDEr_mat_regs_,p_desc89_p_O_FDEr_mat_regs_,p_desc90_p_O_FDEr_mat_regs_,p_desc91_p_O_FDEr_mat_regs_,p_desc92_p_O_FDEr_mat_regs_,p_desc93_p_O_FDEr_mat_regs_,p_desc94_p_O_FDEr_mat_regs_,p_desc95_p_O_FDEr_mat_regs_,p_desc96_p_O_FDEr_mat_regs_,p_desc97_p_O_FDEr_mat_regs_,p_desc98_p_O_FDEr_mat_regs_,p_desc99_p_O_FDEr_mat_regs_,p_desc100_p_O_FDEr_mat_regs_,p_desc101_p_O_FDEr_mat_regs_,p_desc102_p_O_FDEr_mat_regs_,p_desc103_p_O_FDEr_mat_regs_,p_desc104_p_O_FDEr_mat_regs_,p_desc105_p_O_FDEr_mat_regs_,p_desc106_p_O_FDEr_mat_regs_,p_desc107_p_O_FDEr_mat_regs_,p_desc108_p_O_FDEr_mat_regs_,p_desc109_p_O_FDEr_mat_regs_,p_desc110_p_O_FDEr_mat_regs_,p_desc111_p_O_FDEr_mat_regs_,p_desc112_p_O_FDEr_mat_regs_,p_desc113_p_O_FDEr_mat_regs_,p_desc114_p_O_FDEr_mat_regs_,p_desc115_p_O_FDEr_mat_regs_,p_desc116_p_O_FDEr_mat_regs_,p_desc117_p_O_FDEr_mat_regs_,p_desc118_p_O_FDEr_mat_regs_,p_desc119_p_O_FDEr_mat_regs_,p_desc120_p_O_FDEr_mat_regs_,p_desc121_p_O_FDEr_mat_regs_,p_desc122_p_O_FDEr_mat_regs_,p_desc123_p_O_FDEr_mat_regs_,p_desc124_p_O_FDEr_mat_regs_,p_desc125_p_O_FDEr_mat_regs_,p_desc126_p_O_FDEr_mat_regs_,p_desc127_p_O_FDEr_mat_regs_,p_desc128_p_O_FDEr_mat_regs_,p_desc129_p_O_FDEr_mat_regs_,p_desc130_p_O_FDEr_mat_regs_,p_desc131_p_O_FDEr_mat_regs_,p_desc132_p_O_FDEr_mat_regs_,p_desc133_p_O_FDEr_mat_regs_,p_desc134_p_O_FDEr_mat_regs_,p_desc135_p_O_FDEr_mat_regs_,p_desc136_p_O_FDEr_mat_regs_,p_desc137_p_O_FDEr_mat_regs_,p_desc138_p_O_FDEr_mat_regs_,p_desc139_p_O_FDEr_mat_regs_,p_desc140_p_O_FDEr_mat_regs_,p_desc141_p_O_FDEr_mat_regs_,p_desc142_p_O_FDEr_mat_regs_,p_desc143_p_O_FDEr_mat_regs_,p_desc144_p_O_FDEr_mat_regs_,p_desc145_p_O_FDEr_mat_regs_,p_desc146_p_O_FDEr_mat_regs_,p_desc147_p_O_FDEr_mat_regs_,p_desc148_p_O_FDEr_mat_regs_,p_desc149_p_O_FDEr_mat_regs_,p_desc150_p_O_FDEr_mat_regs_,p_desc151_p_O_FDEr_mat_regs_,p_desc152_p_O_FDEr_mat_regs_,p_desc153_p_O_FDEr_mat_regs_,p_desc154_p_O_FDEr_mat_regs_,p_desc155_p_O_FDEr_mat_regs_,p_desc156_p_O_FDEr_mat_regs_,p_desc157_p_O_FDEr_mat_regs_,p_desc158_p_O_FDEr_mat_regs_,p_desc159_p_O_FDEr_mat_regs_,p_desc160_p_O_FDEr_mat_regs_,p_desc161_p_O_FDEr_mat_regs_,p_desc162_p_O_FDEr_mat_regs_,p_desc163_p_O_FDEr_mat_regs_,p_desc164_p_O_FDEr_mat_regs_,p_desc165_p_O_FDEr_mat_regs_,p_desc166_p_O_FDEr_mat_regs_,p_desc167_p_O_FDEr_mat_regs_,p_desc168_p_O_FDEr_mat_regs_,p_desc169_p_O_FDEr_mat_regs_,p_desc170_p_O_FDEr_mat_regs_,p_desc171_p_O_FDEr_mat_regs_,p_desc172_p_O_FDEr_mat_regs_,p_desc173_p_O_FDEr_mat_regs_,p_desc174_p_O_FDEr_mat_regs_,p_desc175_p_O_FDEr_mat_regs_,p_desc176_p_O_FDEr_mat_regs_,p_desc177_p_O_FDEr_mat_regs_,p_desc178_p_O_FDEr_mat_regs_,p_desc179_p_O_FDEr_mat_regs_,p_desc180_p_O_FDEr_mat_regs_,p_desc181_p_O_FDEr_mat_regs_,p_desc182_p_O_FDEr_mat_regs_,p_desc183_p_O_FDEr_mat_regs_,p_desc184_p_O_FDEr_mat_regs_,p_desc185_p_O_FDEr_mat_regs_,p_desc186_p_O_FDEr_mat_regs_,p_desc187_p_O_FDEr_mat_regs_,p_desc188_p_O_FDEr_mat_regs_,p_desc189_p_O_FDEr_mat_regs_,p_desc190_p_O_FDEr_mat_regs_,p_desc191_p_O_FDEr_mat_regs_,p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_,p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_,p_desc739_p_O_FDEvec_sub_,p_desc740_p_O_FDEvec_sub_,p_desc741_p_O_FDEvec_sub_,p_desc742_p_O_FDEvec_sub_,p_desc743_p_O_FDEvec_sub_,p_desc744_p_O_FDEvec_sub_,p_desc745_p_O_FDEvec_sub_,p_desc746_p_O_FDEvec_sub_,p_desc747_p_O_FDEvec_sub_,p_desc748_p_O_FDEvec_sub_,p_desc749_p_O_FDEvec_sub_,p_desc750_p_O_FDEvec_sub_,p_desc751_p_O_FDEvec_sub_,p_desc752_p_O_FDEvec_sub_,p_desc753_p_O_FDEvec_sub_,p_desc754_p_O_FDEvec_sub_,p_desc755_p_O_FDEvec_sub_,p_desc756_p_O_FDEvec_sub_,p_desc757_p_O_FDEvec_sub_,p_desc758_p_O_FDEvec_sub_,p_desc759_p_O_FDEvec_sub_,p_desc760_p_O_FDEvec_sub_,p_desc761_p_O_FDEvec_sub_,p_desc762_p_O_FDEvec_sub_,p_desc763_p_O_FDEvec_sub_,p_desc764_p_O_FDEvec_sub_,p_desc765_p_O_FDEvec_sub_,p_desc766_p_O_FDEvec_sub_,p_desc767_p_O_FDEvec_sub_,p_desc768_p_O_FDEvec_sub_,p_desc769_p_O_FDEvec_sub_,p_desc770_p_O_FDEvec_sub_,p_desc771_p_O_FDEvec_sub_,p_desc772_p_O_FDEvec_sub_,p_desc773_p_O_FDEvec_sub_,p_desc774_p_O_FDEvec_sub_,p_desc775_p_O_FDEvec_sub_,p_desc776_p_O_FDEvec_sub_,p_desc777_p_O_FDEvec_sub_,p_desc778_p_O_FDEvec_sub_,p_desc779_p_O_FDEvec_sub_,p_desc780_p_O_FDEvec_sub_,p_desc781_p_O_FDEvec_sub_,p_desc782_p_O_FDEvec_sub_,p_desc783_p_O_FDEvec_sub_,p_desc784_p_O_FDEvec_sub_,p_desc785_p_O_FDEvec_sub_,p_desc786_p_O_FDEvec_sub_,p_desc787_p_O_FDEvec_sub_,p_desc788_p_O_FDEvec_sub_,p_desc789_p_O_FDEvec_sub_,p_desc790_p_O_FDEvec_sub_,p_desc791_p_O_FDEvec_sub_,p_desc792_p_O_FDEvec_sub_,p_desc793_p_O_FDEvec_sub_,p_desc794_p_O_FDEvec_sub_,p_desc795_p_O_FDEvec_sub_,p_desc796_p_O_FDEvec_sub_,p_desc797_p_O_FDEvec_sub_,p_desc798_p_O_FDEvec_sub_,p_desc799_p_O_FDEvec_sub_,p_desc800_p_O_FDEvec_sub_,p_desc801_p_O_FDEvec_sub_,p_desc802_p_O_FDEvec_sub_,p_desc803_p_O_FDEvec_sub_,p_desc804_p_O_FDEvec_sub_,p_desc805_p_O_FDEvec_sub_,p_desc806_p_O_FDEvec_sub_,p_desc807_p_O_FDEvec_sub_,p_desc808_p_O_FDEvec_sub_,p_desc809_p_O_FDEvec_sub_,p_desc810_p_O_FDEvec_sub_,p_desc811_p_O_FDEvec_sub_,p_desc812_p_O_FDEvec_sub_,p_desc813_p_O_FDEvec_sub_,p_desc814_p_O_FDEvec_sub_,p_desc815_p_O_FDEvec_sub_,p_desc816_p_O_FDEvec_sub_,p_desc817_p_O_FDEvec_sub_,p_desc818_p_O_FDEvec_sub_,p_desc819_p_O_FDEvec_sub_,p_desc820_p_O_FDEvec_sub_,p_desc821_p_O_FDEvec_sub_,p_desc822_p_O_FDEvec_sub_,p_desc823_p_O_FDEvec_sub_,p_desc824_p_O_FDEvec_sub_,p_desc825_p_O_FDEvec_sub_,p_desc826_p_O_FDEvec_sub_,p_desc827_p_O_FDEvec_sub_,p_desc828_p_O_FDEvec_sub_,p_desc829_p_O_FDEvec_sub_,p_desc830_p_O_FDEvec_sub_,p_desc831_p_O_FDEvec_sub_,p_desc832_p_O_FDEvec_sub_,p_desc833_p_O_FDEvec_sub_,p_desc834_p_O_FDEvec_sub_,p_output_reg_pipe_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_,p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_,p_desc318_p_O_FDCinner_prod_,p_desc319_p_O_FDCinner_prod_,p_desc320_p_O_FDCinner_prod_,p_desc321_p_O_FDCinner_prod_,p_desc322_p_O_FDCinner_prod_,p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_,p_done_Z_p_O_FDCinner_prod_,p_acc_enable_Z_p_O_FDCinner_prod_,p_desc325_p_O_FDCinner_prod_,p_desc326_p_O_FDCinner_prod_,p_desc327_p_O_FDCinner_prod_,p_desc328_p_O_FDCinner_prod_,p_desc329_p_O_FDCinner_prod_,p_desc330_p_O_FDCinner_prod_,p_desc331_p_O_FDCinner_prod_,p_desc332_p_O_FDCinner_prod_,p_desc333_p_O_FDCinner_prod_,p_desc334_p_O_FDCinner_prod_,p_desc335_p_O_FDCinner_prod_,p_desc336_p_O_FDCinner_prod_,p_desc337_p_O_FDCinner_prod_,p_desc338_p_O_FDCinner_prod_,p_desc339_p_O_FDCinner_prod_,p_desc340_p_O_FDCinner_prod_,p_desc341_p_O_FDCinner_prod_,p_desc342_p_O_FDCinner_prod_,p_desc343_p_O_FDCinner_prod_,p_desc344_p_O_FDCinner_prod_,p_desc345_p_O_FDCinner_prod_,p_desc346_p_O_FDCinner_prod_,p_desc347_p_O_FDCinner_prod_,p_desc348_p_O_FDCinner_prod_,p_desc349_p_O_FDCinner_prod_,p_desc350_p_O_FDCinner_prod_,p_desc375_p_O_FDCinner_prod_,p_desc376_p_O_FDCinner_prod_,p_desc377_p_O_FDCinner_prod_,p_desc378_p_O_FDCinner_prod_,p_desc379_p_O_FDCinner_prod_,p_desc380_p_O_FDCinner_prod_,p_desc381_p_O_FDCinner_prod_,p_desc382_p_O_FDCinner_prod_,p_desc383_p_O_FDCinner_prod_,p_desc384_p_O_FDCinner_prod_,p_desc385_p_O_FDCinner_prod_,p_desc386_p_O_FDCinner_prod_,p_desc387_p_O_FDCinner_prod_,p_desc388_p_O_FDCinner_prod_,p_desc389_p_O_FDCinner_prod_,p_desc390_p_O_FDCinner_prod_,p_desc391_p_O_FDCinner_prod_,p_desc392_p_O_FDCinner_prod_,p_desc393_p_O_FDCinner_prod_,p_desc394_p_O_FDCinner_prod_,p_desc395_p_O_FDCinner_prod_,p_desc396_p_O_FDCinner_prod_,p_desc397_p_O_FDCinner_prod_,p_desc398_p_O_FDCinner_prod_,p_done_Z_p_O_FDCinv_sqrt_,p_desc946_p_O_FDCinv_sqrt_,p_desc947_p_O_FDCinv_sqrt_,p_desc948_p_O_FDCinv_sqrt_,p_desc949_p_O_FDCinv_sqrt_,p_desc950_p_O_FDCinv_sqrt_,p_desc1255_p_O_FDCqr_decomp_ctl_,p_desc1256_p_O_FDCqr_decomp_ctl_,p_desc1257_p_O_FDCqr_decomp_ctl_,p_desc1258_p_O_FDCqr_decomp_ctl_,p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_,p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_,p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_,p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_,p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_,p_desc1274_p_O_FDCqr_decomp_ctl_,p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_,p_done_Z_p_O_FDCqr_decomp_ctl_,p_desc1275_p_O_FDCqr_decomp_ctl_,p_desc1276_p_O_FDCqr_decomp_ctl_,p_desc1277_p_O_FDCqr_decomp_ctl_,p_desc1278_p_O_FDCqr_decomp_ctl_,p_desc1279_p_O_FDCqr_decomp_ctl_,p_desc1281_p_O_FDCqr_decomp_ctl_,p_desc1282_p_O_FDCqr_decomp_ctl_,p_desc1283_p_O_FDCqr_decomp_ctl_,p_desc1284_p_O_FDCqr_decomp_ctl_,p_desc1285_p_O_FDCqr_decomp_ctl_,p_desc1286_p_O_FDCqr_decomp_ctl_,p_desc1287_p_O_FDCqr_decomp_ctl_,p_desc1288_p_O_FDCqr_decomp_ctl_,p_acc_clear_Z_p_O_FDPinner_prod_,p_desc1265_p_O_FDPqr_decomp_ctl_,p_desc1268_p_O_FDPqr_decomp_ctl_,p_desc1280_p_O_FDPqr_decomp_ctl_,p_desc324_p_O_FDCEinner_prod_,p_desc351_p_O_FDCEinner_prod_,p_desc352_p_O_FDCEinner_prod_,p_desc353_p_O_FDCEinner_prod_,p_desc354_p_O_FDCEinner_prod_,p_desc355_p_O_FDCEinner_prod_,p_desc356_p_O_FDCEinner_prod_,p_desc357_p_O_FDCEinner_prod_,p_desc358_p_O_FDCEinner_prod_,p_desc359_p_O_FDCEinner_prod_,p_desc360_p_O_FDCEinner_prod_,p_desc361_p_O_FDCEinner_prod_,p_desc362_p_O_FDCEinner_prod_,p_desc363_p_O_FDCEinner_prod_,p_desc364_p_O_FDCEinner_prod_,p_desc365_p_O_FDCEinner_prod_,p_desc366_p_O_FDCEinner_prod_,p_desc367_p_O_FDCEinner_prod_,p_desc368_p_O_FDCEinner_prod_,p_desc369_p_O_FDCEinner_prod_,p_desc370_p_O_FDCEinner_prod_,p_desc371_p_O_FDCEinner_prod_,p_desc372_p_O_FDCEinner_prod_,p_desc373_p_O_FDCEinner_prod_,p_desc374_p_O_FDCEinner_prod_,p_desc1263_p_O_FDCEqr_decomp_ctl_,p_desc1264_p_O_FDCEqr_decomp_ctl_,p_desc1266_p_O_FDCEqr_decomp_ctl_,p_desc1267_p_O_FDCEqr_decomp_ctl_,p_desc1269_p_O_FDCEqr_decomp_ctl_,p_desc1270_p_O_FDCEqr_decomp_ctl_,p_desc1271_p_O_FDCEqr_decomp_ctl_,p_desc1272_p_O_FDCEqr_decomp_ctl_,p_desc1273_p_O_FDCEqr_decomp_ctl_);
output [47:0] out_Q_r ;
output [47:0] out_Q_i ;
input [1:0] col_sel_R ;
output [47:12] out_R_i ;
output [47:0] out_R_r ;
input [1:0] col_sel_AQ ;
input [47:0] in_A_r ;
input [47:0] in_A_i ;
input clk ;
input rst ;
input wr_A_QR ;
input start_QR ;
output done_QR ;
input red_mat_reg_0 ;
wire clk ;
wire rst ;
wire wr_A_QR ;
wire start_QR ;
wire done_QR ;
wire red_mat_reg_0 ;
wire col_sel_AQ2_mux_i_m3_lut6_2_O6 ;
wire col_sel_AQ2_mux_i_m3_lut6_2_O5 ;
wire [1:0] col_sel_AQ_int ;
wire w_col_sel_AQ_mux_i_m3_lut6_2_O6 ;
wire w_col_sel_AQ_mux_i_m3_lut6_2_O5 ;
wire [11:0] vec_out_r_AQ_0 ;
wire [11:1] vec_in_r_AQ_mux_0 ;
wire [11:0] vec_out_r_AQ_3 ;
wire [11:0] vec_in_r_AQ_mux_3 ;
wire [11:0] vec_out_r_AQ_2 ;
wire [11:0] vec_out_r_AQ_1 ;
wire [11:0] vec_in_r_AQ_mux_2 ;
wire [11:0] vec_in_r_AQ_mux_1 ;
wire [11:0] vec_out_i_AQ_0 ;
wire [11:0] vec_in_i_AQ_mux_0 ;
wire [11:0] vec_out_i_AQ_3 ;
wire [11:0] vec_in_i_AQ_mux_3 ;
wire [11:0] vec_out_i_AQ_2 ;
wire [11:0] vec_out_i_AQ_1 ;
wire [11:0] vec_in_i_AQ_mux_2 ;
wire [11:0] vec_in_i_AQ_mux_1 ;
wire [1:0] row_sel_AQ ;
wire [7:1] single_out_r_AQ2 ;
wire [11:0] single_out_i_AQ2 ;
wire [11:0] single_out_i_AQ ;
wire [8:1] single_out_r_AQ ;
wire [1:0] row_sel_R ;
wire col_sel_R_mux_i_m3_lut6_2_O6 ;
wire col_sel_R_mux_i_m3_lut6_2_O5 ;
wire [11:11] single_in_r_R_mux ;
wire wr_en_AQ_sel ;
wire [1:0] col_sel_R_int ;
wire [11:0] out_inner_prod_i ;
wire [11:0] out_inner_prod_r ;
wire in_a_inner_prod_sel ;
wire in_b_inner_prod_sel ;
wire [10:0] output_iv ;
wire [10:1] output_iv_0 ;
wire [11:11] out_r_vec_sub_0 ;
wire [11:11] out_i_vec_sub_0 ;
wire in_b_vec_mult_sel ;
wire [11:0] out_i_vec_mult_2 ;
wire [11:0] out_r_vec_mult_2 ;
wire [11:0] out_inv_sqrt ;
wire [11:0] out_i_vec_mult_1 ;
wire [11:0] out_r_vec_mult_1 ;
wire [11:0] out_i_vec_mult_0 ;
wire [11:0] out_r_vec_mult_0 ;
wire [11:0] out_i_vec_mult_3 ;
wire [11:0] out_r_vec_mult_3 ;
wire [11:11] in_a_r_reg_3 ;
wire [11:11] in_a_r_reg_2 ;
wire [11:11] in_a_r_reg_1 ;
wire [11:0] in_a_r_reg_0 ;
wire [11:11] in_a_i_reg_3 ;
wire [11:11] in_a_i_reg_2 ;
wire [11:11] in_a_i_reg_1 ;
wire [11:11] in_a_i_reg_0 ;
wire [22:1] pre_out ;
wire [10:0] pre_out_i_m ;
wire [11:1] pre_out_0 ;
wire [6:0] pre_out_i_m_0 ;
wire [11:1] pre_out_1 ;
wire [11:1] pre_out_2 ;
wire pre_out_i_m_1 ;
wire [11:2] pre_out_3 ;
wire [11:11] pre_out_4 ;
wire pre_out_i_m_2 ;
wire pre_out_i_m_3 ;
wire pre_out_i_m_4 ;
wire [11:11] pre_out_5 ;
wire [11:11] pre_out_6 ;
wire [10:0] un8_rnd_out ;
wire [19:19] un8_rnd_out_P ;
wire [23:23] pre_out_reg ;
wire single_in_R_sel ;
wire single_in_R_sel_0 ;
wire [1:0] w_col_sel_AQ_int ;
wire [1:0] col_sel_AQ2_int ;
wire [8:3] state ;
wire wr_en_AQ_sel_0 ;
wire [1:0] vec_in_AQ_sel ;
wire wr_en_AQ_mux_i_m3_lut6_2_O6 ;
wire N_507 ;
wire N_508 ;
wire N_505 ;
wire N_506 ;
wire N_645 ;
wire N_641 ;
wire N_637 ;
wire N_632 ;
wire N_628 ;
wire N_624 ;
wire N_623 ;
wire N_622 ;
wire N_612 ;
wire N_607 ;
wire N_606 ;
wire N_605 ;
wire N_597 ;
wire N_596 ;
wire N_595 ;
wire N_586 ;
wire N_585 ;
wire N_584 ;
wire N_583 ;
wire N_582 ;
wire N_571 ;
wire N_568 ;
wire N_567 ;
wire N_566 ;
wire N_555 ;
wire N_552 ;
wire N_549 ;
wire wr_en_R ;
wire N_28_i ;
wire N_30_i ;
wire N_32_i ;
wire N_34_i ;
wire N_383_i ;
wire N_384_i ;
wire N_385_i ;
wire N_386_i ;
wire N_387_i ;
wire N_388_i ;
wire N_389_i ;
wire N_390_i ;
wire N_391_i ;
wire N_392_i ;
wire N_393_i ;
wire N_394_i ;
wire N_395_i ;
wire N_396_i ;
wire N_397_i ;
wire N_398_i ;
wire N_399_i ;
wire N_400_i ;
wire N_401_i ;
wire start_inner_prod ;
wire red_mat_reg ;
wire done_inner_prod ;
wire N_501 ;
wire N_500 ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire w_in_a_vec_sub ;
wire un5_output ;
wire un5_output_0 ;
wire un5_output_1 ;
wire un5_output_2 ;
wire un5_output_3 ;
wire un5_output_4 ;
wire N_512_i ;
wire PATTERNDETECT_32 ;
wire done_inv_sqrt ;
wire start_inv_sqrt ;
wire wr_en_AQ_int ;
wire GND ;
wire VCC ;
input p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_ ;
input p_desc951_p_O_FDEinv_sqrt_ ;
input p_desc952_p_O_FDEinv_sqrt_ ;
input p_desc953_p_O_FDEinv_sqrt_ ;
input p_desc954_p_O_FDEinv_sqrt_ ;
input p_desc955_p_O_FDEinv_sqrt_ ;
input p_desc956_p_O_FDEinv_sqrt_ ;
input p_desc957_p_O_FDEinv_sqrt_ ;
input p_desc958_p_O_FDEinv_sqrt_ ;
input p_desc959_p_O_FDEinv_sqrt_ ;
input p_desc960_p_O_FDEinv_sqrt_ ;
input p_desc961_p_O_FDEinv_sqrt_ ;
input p_desc962_p_O_FDEinv_sqrt_ ;
input p_desc48_p_O_FDEr_mat_regs_ ;
input p_desc49_p_O_FDEr_mat_regs_ ;
input p_desc50_p_O_FDEr_mat_regs_ ;
input p_desc51_p_O_FDEr_mat_regs_ ;
input p_desc52_p_O_FDEr_mat_regs_ ;
input p_desc53_p_O_FDEr_mat_regs_ ;
input p_desc54_p_O_FDEr_mat_regs_ ;
input p_desc55_p_O_FDEr_mat_regs_ ;
input p_desc56_p_O_FDEr_mat_regs_ ;
input p_desc57_p_O_FDEr_mat_regs_ ;
input p_desc58_p_O_FDEr_mat_regs_ ;
input p_desc59_p_O_FDEr_mat_regs_ ;
input p_desc60_p_O_FDEr_mat_regs_ ;
input p_desc61_p_O_FDEr_mat_regs_ ;
input p_desc62_p_O_FDEr_mat_regs_ ;
input p_desc63_p_O_FDEr_mat_regs_ ;
input p_desc64_p_O_FDEr_mat_regs_ ;
input p_desc65_p_O_FDEr_mat_regs_ ;
input p_desc66_p_O_FDEr_mat_regs_ ;
input p_desc67_p_O_FDEr_mat_regs_ ;
input p_desc68_p_O_FDEr_mat_regs_ ;
input p_desc69_p_O_FDEr_mat_regs_ ;
input p_desc70_p_O_FDEr_mat_regs_ ;
input p_desc71_p_O_FDEr_mat_regs_ ;
input p_desc72_p_O_FDEr_mat_regs_ ;
input p_desc73_p_O_FDEr_mat_regs_ ;
input p_desc74_p_O_FDEr_mat_regs_ ;
input p_desc75_p_O_FDEr_mat_regs_ ;
input p_desc76_p_O_FDEr_mat_regs_ ;
input p_desc77_p_O_FDEr_mat_regs_ ;
input p_desc78_p_O_FDEr_mat_regs_ ;
input p_desc79_p_O_FDEr_mat_regs_ ;
input p_desc80_p_O_FDEr_mat_regs_ ;
input p_desc81_p_O_FDEr_mat_regs_ ;
input p_desc82_p_O_FDEr_mat_regs_ ;
input p_desc83_p_O_FDEr_mat_regs_ ;
input p_desc84_p_O_FDEr_mat_regs_ ;
input p_desc85_p_O_FDEr_mat_regs_ ;
input p_desc86_p_O_FDEr_mat_regs_ ;
input p_desc87_p_O_FDEr_mat_regs_ ;
input p_desc88_p_O_FDEr_mat_regs_ ;
input p_desc89_p_O_FDEr_mat_regs_ ;
input p_desc90_p_O_FDEr_mat_regs_ ;
input p_desc91_p_O_FDEr_mat_regs_ ;
input p_desc92_p_O_FDEr_mat_regs_ ;
input p_desc93_p_O_FDEr_mat_regs_ ;
input p_desc94_p_O_FDEr_mat_regs_ ;
input p_desc95_p_O_FDEr_mat_regs_ ;
input p_desc96_p_O_FDEr_mat_regs_ ;
input p_desc97_p_O_FDEr_mat_regs_ ;
input p_desc98_p_O_FDEr_mat_regs_ ;
input p_desc99_p_O_FDEr_mat_regs_ ;
input p_desc100_p_O_FDEr_mat_regs_ ;
input p_desc101_p_O_FDEr_mat_regs_ ;
input p_desc102_p_O_FDEr_mat_regs_ ;
input p_desc103_p_O_FDEr_mat_regs_ ;
input p_desc104_p_O_FDEr_mat_regs_ ;
input p_desc105_p_O_FDEr_mat_regs_ ;
input p_desc106_p_O_FDEr_mat_regs_ ;
input p_desc107_p_O_FDEr_mat_regs_ ;
input p_desc108_p_O_FDEr_mat_regs_ ;
input p_desc109_p_O_FDEr_mat_regs_ ;
input p_desc110_p_O_FDEr_mat_regs_ ;
input p_desc111_p_O_FDEr_mat_regs_ ;
input p_desc112_p_O_FDEr_mat_regs_ ;
input p_desc113_p_O_FDEr_mat_regs_ ;
input p_desc114_p_O_FDEr_mat_regs_ ;
input p_desc115_p_O_FDEr_mat_regs_ ;
input p_desc116_p_O_FDEr_mat_regs_ ;
input p_desc117_p_O_FDEr_mat_regs_ ;
input p_desc118_p_O_FDEr_mat_regs_ ;
input p_desc119_p_O_FDEr_mat_regs_ ;
input p_desc120_p_O_FDEr_mat_regs_ ;
input p_desc121_p_O_FDEr_mat_regs_ ;
input p_desc122_p_O_FDEr_mat_regs_ ;
input p_desc123_p_O_FDEr_mat_regs_ ;
input p_desc124_p_O_FDEr_mat_regs_ ;
input p_desc125_p_O_FDEr_mat_regs_ ;
input p_desc126_p_O_FDEr_mat_regs_ ;
input p_desc127_p_O_FDEr_mat_regs_ ;
input p_desc128_p_O_FDEr_mat_regs_ ;
input p_desc129_p_O_FDEr_mat_regs_ ;
input p_desc130_p_O_FDEr_mat_regs_ ;
input p_desc131_p_O_FDEr_mat_regs_ ;
input p_desc132_p_O_FDEr_mat_regs_ ;
input p_desc133_p_O_FDEr_mat_regs_ ;
input p_desc134_p_O_FDEr_mat_regs_ ;
input p_desc135_p_O_FDEr_mat_regs_ ;
input p_desc136_p_O_FDEr_mat_regs_ ;
input p_desc137_p_O_FDEr_mat_regs_ ;
input p_desc138_p_O_FDEr_mat_regs_ ;
input p_desc139_p_O_FDEr_mat_regs_ ;
input p_desc140_p_O_FDEr_mat_regs_ ;
input p_desc141_p_O_FDEr_mat_regs_ ;
input p_desc142_p_O_FDEr_mat_regs_ ;
input p_desc143_p_O_FDEr_mat_regs_ ;
input p_desc144_p_O_FDEr_mat_regs_ ;
input p_desc145_p_O_FDEr_mat_regs_ ;
input p_desc146_p_O_FDEr_mat_regs_ ;
input p_desc147_p_O_FDEr_mat_regs_ ;
input p_desc148_p_O_FDEr_mat_regs_ ;
input p_desc149_p_O_FDEr_mat_regs_ ;
input p_desc150_p_O_FDEr_mat_regs_ ;
input p_desc151_p_O_FDEr_mat_regs_ ;
input p_desc152_p_O_FDEr_mat_regs_ ;
input p_desc153_p_O_FDEr_mat_regs_ ;
input p_desc154_p_O_FDEr_mat_regs_ ;
input p_desc155_p_O_FDEr_mat_regs_ ;
input p_desc156_p_O_FDEr_mat_regs_ ;
input p_desc157_p_O_FDEr_mat_regs_ ;
input p_desc158_p_O_FDEr_mat_regs_ ;
input p_desc159_p_O_FDEr_mat_regs_ ;
input p_desc160_p_O_FDEr_mat_regs_ ;
input p_desc161_p_O_FDEr_mat_regs_ ;
input p_desc162_p_O_FDEr_mat_regs_ ;
input p_desc163_p_O_FDEr_mat_regs_ ;
input p_desc164_p_O_FDEr_mat_regs_ ;
input p_desc165_p_O_FDEr_mat_regs_ ;
input p_desc166_p_O_FDEr_mat_regs_ ;
input p_desc167_p_O_FDEr_mat_regs_ ;
input p_desc168_p_O_FDEr_mat_regs_ ;
input p_desc169_p_O_FDEr_mat_regs_ ;
input p_desc170_p_O_FDEr_mat_regs_ ;
input p_desc171_p_O_FDEr_mat_regs_ ;
input p_desc172_p_O_FDEr_mat_regs_ ;
input p_desc173_p_O_FDEr_mat_regs_ ;
input p_desc174_p_O_FDEr_mat_regs_ ;
input p_desc175_p_O_FDEr_mat_regs_ ;
input p_desc176_p_O_FDEr_mat_regs_ ;
input p_desc177_p_O_FDEr_mat_regs_ ;
input p_desc178_p_O_FDEr_mat_regs_ ;
input p_desc179_p_O_FDEr_mat_regs_ ;
input p_desc180_p_O_FDEr_mat_regs_ ;
input p_desc181_p_O_FDEr_mat_regs_ ;
input p_desc182_p_O_FDEr_mat_regs_ ;
input p_desc183_p_O_FDEr_mat_regs_ ;
input p_desc184_p_O_FDEr_mat_regs_ ;
input p_desc185_p_O_FDEr_mat_regs_ ;
input p_desc186_p_O_FDEr_mat_regs_ ;
input p_desc187_p_O_FDEr_mat_regs_ ;
input p_desc188_p_O_FDEr_mat_regs_ ;
input p_desc189_p_O_FDEr_mat_regs_ ;
input p_desc190_p_O_FDEr_mat_regs_ ;
input p_desc191_p_O_FDEr_mat_regs_ ;
input p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_ ;
input p_desc739_p_O_FDEvec_sub_ ;
input p_desc740_p_O_FDEvec_sub_ ;
input p_desc741_p_O_FDEvec_sub_ ;
input p_desc742_p_O_FDEvec_sub_ ;
input p_desc743_p_O_FDEvec_sub_ ;
input p_desc744_p_O_FDEvec_sub_ ;
input p_desc745_p_O_FDEvec_sub_ ;
input p_desc746_p_O_FDEvec_sub_ ;
input p_desc747_p_O_FDEvec_sub_ ;
input p_desc748_p_O_FDEvec_sub_ ;
input p_desc749_p_O_FDEvec_sub_ ;
input p_desc750_p_O_FDEvec_sub_ ;
input p_desc751_p_O_FDEvec_sub_ ;
input p_desc752_p_O_FDEvec_sub_ ;
input p_desc753_p_O_FDEvec_sub_ ;
input p_desc754_p_O_FDEvec_sub_ ;
input p_desc755_p_O_FDEvec_sub_ ;
input p_desc756_p_O_FDEvec_sub_ ;
input p_desc757_p_O_FDEvec_sub_ ;
input p_desc758_p_O_FDEvec_sub_ ;
input p_desc759_p_O_FDEvec_sub_ ;
input p_desc760_p_O_FDEvec_sub_ ;
input p_desc761_p_O_FDEvec_sub_ ;
input p_desc762_p_O_FDEvec_sub_ ;
input p_desc763_p_O_FDEvec_sub_ ;
input p_desc764_p_O_FDEvec_sub_ ;
input p_desc765_p_O_FDEvec_sub_ ;
input p_desc766_p_O_FDEvec_sub_ ;
input p_desc767_p_O_FDEvec_sub_ ;
input p_desc768_p_O_FDEvec_sub_ ;
input p_desc769_p_O_FDEvec_sub_ ;
input p_desc770_p_O_FDEvec_sub_ ;
input p_desc771_p_O_FDEvec_sub_ ;
input p_desc772_p_O_FDEvec_sub_ ;
input p_desc773_p_O_FDEvec_sub_ ;
input p_desc774_p_O_FDEvec_sub_ ;
input p_desc775_p_O_FDEvec_sub_ ;
input p_desc776_p_O_FDEvec_sub_ ;
input p_desc777_p_O_FDEvec_sub_ ;
input p_desc778_p_O_FDEvec_sub_ ;
input p_desc779_p_O_FDEvec_sub_ ;
input p_desc780_p_O_FDEvec_sub_ ;
input p_desc781_p_O_FDEvec_sub_ ;
input p_desc782_p_O_FDEvec_sub_ ;
input p_desc783_p_O_FDEvec_sub_ ;
input p_desc784_p_O_FDEvec_sub_ ;
input p_desc785_p_O_FDEvec_sub_ ;
input p_desc786_p_O_FDEvec_sub_ ;
input p_desc787_p_O_FDEvec_sub_ ;
input p_desc788_p_O_FDEvec_sub_ ;
input p_desc789_p_O_FDEvec_sub_ ;
input p_desc790_p_O_FDEvec_sub_ ;
input p_desc791_p_O_FDEvec_sub_ ;
input p_desc792_p_O_FDEvec_sub_ ;
input p_desc793_p_O_FDEvec_sub_ ;
input p_desc794_p_O_FDEvec_sub_ ;
input p_desc795_p_O_FDEvec_sub_ ;
input p_desc796_p_O_FDEvec_sub_ ;
input p_desc797_p_O_FDEvec_sub_ ;
input p_desc798_p_O_FDEvec_sub_ ;
input p_desc799_p_O_FDEvec_sub_ ;
input p_desc800_p_O_FDEvec_sub_ ;
input p_desc801_p_O_FDEvec_sub_ ;
input p_desc802_p_O_FDEvec_sub_ ;
input p_desc803_p_O_FDEvec_sub_ ;
input p_desc804_p_O_FDEvec_sub_ ;
input p_desc805_p_O_FDEvec_sub_ ;
input p_desc806_p_O_FDEvec_sub_ ;
input p_desc807_p_O_FDEvec_sub_ ;
input p_desc808_p_O_FDEvec_sub_ ;
input p_desc809_p_O_FDEvec_sub_ ;
input p_desc810_p_O_FDEvec_sub_ ;
input p_desc811_p_O_FDEvec_sub_ ;
input p_desc812_p_O_FDEvec_sub_ ;
input p_desc813_p_O_FDEvec_sub_ ;
input p_desc814_p_O_FDEvec_sub_ ;
input p_desc815_p_O_FDEvec_sub_ ;
input p_desc816_p_O_FDEvec_sub_ ;
input p_desc817_p_O_FDEvec_sub_ ;
input p_desc818_p_O_FDEvec_sub_ ;
input p_desc819_p_O_FDEvec_sub_ ;
input p_desc820_p_O_FDEvec_sub_ ;
input p_desc821_p_O_FDEvec_sub_ ;
input p_desc822_p_O_FDEvec_sub_ ;
input p_desc823_p_O_FDEvec_sub_ ;
input p_desc824_p_O_FDEvec_sub_ ;
input p_desc825_p_O_FDEvec_sub_ ;
input p_desc826_p_O_FDEvec_sub_ ;
input p_desc827_p_O_FDEvec_sub_ ;
input p_desc828_p_O_FDEvec_sub_ ;
input p_desc829_p_O_FDEvec_sub_ ;
input p_desc830_p_O_FDEvec_sub_ ;
input p_desc831_p_O_FDEvec_sub_ ;
input p_desc832_p_O_FDEvec_sub_ ;
input p_desc833_p_O_FDEvec_sub_ ;
input p_desc834_p_O_FDEvec_sub_ ;
input p_output_reg_pipe_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_ ;
input p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_ ;
input p_desc318_p_O_FDCinner_prod_ ;
input p_desc319_p_O_FDCinner_prod_ ;
input p_desc320_p_O_FDCinner_prod_ ;
input p_desc321_p_O_FDCinner_prod_ ;
input p_desc322_p_O_FDCinner_prod_ ;
input p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_ ;
input p_done_Z_p_O_FDCinner_prod_ ;
input p_acc_enable_Z_p_O_FDCinner_prod_ ;
input p_desc325_p_O_FDCinner_prod_ ;
input p_desc326_p_O_FDCinner_prod_ ;
input p_desc327_p_O_FDCinner_prod_ ;
input p_desc328_p_O_FDCinner_prod_ ;
input p_desc329_p_O_FDCinner_prod_ ;
input p_desc330_p_O_FDCinner_prod_ ;
input p_desc331_p_O_FDCinner_prod_ ;
input p_desc332_p_O_FDCinner_prod_ ;
input p_desc333_p_O_FDCinner_prod_ ;
input p_desc334_p_O_FDCinner_prod_ ;
input p_desc335_p_O_FDCinner_prod_ ;
input p_desc336_p_O_FDCinner_prod_ ;
input p_desc337_p_O_FDCinner_prod_ ;
input p_desc338_p_O_FDCinner_prod_ ;
input p_desc339_p_O_FDCinner_prod_ ;
input p_desc340_p_O_FDCinner_prod_ ;
input p_desc341_p_O_FDCinner_prod_ ;
input p_desc342_p_O_FDCinner_prod_ ;
input p_desc343_p_O_FDCinner_prod_ ;
input p_desc344_p_O_FDCinner_prod_ ;
input p_desc345_p_O_FDCinner_prod_ ;
input p_desc346_p_O_FDCinner_prod_ ;
input p_desc347_p_O_FDCinner_prod_ ;
input p_desc348_p_O_FDCinner_prod_ ;
input p_desc349_p_O_FDCinner_prod_ ;
input p_desc350_p_O_FDCinner_prod_ ;
input p_desc375_p_O_FDCinner_prod_ ;
input p_desc376_p_O_FDCinner_prod_ ;
input p_desc377_p_O_FDCinner_prod_ ;
input p_desc378_p_O_FDCinner_prod_ ;
input p_desc379_p_O_FDCinner_prod_ ;
input p_desc380_p_O_FDCinner_prod_ ;
input p_desc381_p_O_FDCinner_prod_ ;
input p_desc382_p_O_FDCinner_prod_ ;
input p_desc383_p_O_FDCinner_prod_ ;
input p_desc384_p_O_FDCinner_prod_ ;
input p_desc385_p_O_FDCinner_prod_ ;
input p_desc386_p_O_FDCinner_prod_ ;
input p_desc387_p_O_FDCinner_prod_ ;
input p_desc388_p_O_FDCinner_prod_ ;
input p_desc389_p_O_FDCinner_prod_ ;
input p_desc390_p_O_FDCinner_prod_ ;
input p_desc391_p_O_FDCinner_prod_ ;
input p_desc392_p_O_FDCinner_prod_ ;
input p_desc393_p_O_FDCinner_prod_ ;
input p_desc394_p_O_FDCinner_prod_ ;
input p_desc395_p_O_FDCinner_prod_ ;
input p_desc396_p_O_FDCinner_prod_ ;
input p_desc397_p_O_FDCinner_prod_ ;
input p_desc398_p_O_FDCinner_prod_ ;
input p_done_Z_p_O_FDCinv_sqrt_ ;
input p_desc946_p_O_FDCinv_sqrt_ ;
input p_desc947_p_O_FDCinv_sqrt_ ;
input p_desc948_p_O_FDCinv_sqrt_ ;
input p_desc949_p_O_FDCinv_sqrt_ ;
input p_desc950_p_O_FDCinv_sqrt_ ;
input p_desc1255_p_O_FDCqr_decomp_ctl_ ;
input p_desc1256_p_O_FDCqr_decomp_ctl_ ;
input p_desc1257_p_O_FDCqr_decomp_ctl_ ;
input p_desc1258_p_O_FDCqr_decomp_ctl_ ;
input p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_ ;
input p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_ ;
input p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_ ;
input p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_ ;
input p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_ ;
input p_desc1274_p_O_FDCqr_decomp_ctl_ ;
input p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_ ;
input p_done_Z_p_O_FDCqr_decomp_ctl_ ;
input p_desc1275_p_O_FDCqr_decomp_ctl_ ;
input p_desc1276_p_O_FDCqr_decomp_ctl_ ;
input p_desc1277_p_O_FDCqr_decomp_ctl_ ;
input p_desc1278_p_O_FDCqr_decomp_ctl_ ;
input p_desc1279_p_O_FDCqr_decomp_ctl_ ;
input p_desc1281_p_O_FDCqr_decomp_ctl_ ;
input p_desc1282_p_O_FDCqr_decomp_ctl_ ;
input p_desc1283_p_O_FDCqr_decomp_ctl_ ;
input p_desc1284_p_O_FDCqr_decomp_ctl_ ;
input p_desc1285_p_O_FDCqr_decomp_ctl_ ;
input p_desc1286_p_O_FDCqr_decomp_ctl_ ;
input p_desc1287_p_O_FDCqr_decomp_ctl_ ;
input p_desc1288_p_O_FDCqr_decomp_ctl_ ;
input p_acc_clear_Z_p_O_FDPinner_prod_ ;
input p_desc1265_p_O_FDPqr_decomp_ctl_ ;
input p_desc1268_p_O_FDPqr_decomp_ctl_ ;
input p_desc1280_p_O_FDPqr_decomp_ctl_ ;
input p_desc324_p_O_FDCEinner_prod_ ;
input p_desc351_p_O_FDCEinner_prod_ ;
input p_desc352_p_O_FDCEinner_prod_ ;
input p_desc353_p_O_FDCEinner_prod_ ;
input p_desc354_p_O_FDCEinner_prod_ ;
input p_desc355_p_O_FDCEinner_prod_ ;
input p_desc356_p_O_FDCEinner_prod_ ;
input p_desc357_p_O_FDCEinner_prod_ ;
input p_desc358_p_O_FDCEinner_prod_ ;
input p_desc359_p_O_FDCEinner_prod_ ;
input p_desc360_p_O_FDCEinner_prod_ ;
input p_desc361_p_O_FDCEinner_prod_ ;
input p_desc362_p_O_FDCEinner_prod_ ;
input p_desc363_p_O_FDCEinner_prod_ ;
input p_desc364_p_O_FDCEinner_prod_ ;
input p_desc365_p_O_FDCEinner_prod_ ;
input p_desc366_p_O_FDCEinner_prod_ ;
input p_desc367_p_O_FDCEinner_prod_ ;
input p_desc368_p_O_FDCEinner_prod_ ;
input p_desc369_p_O_FDCEinner_prod_ ;
input p_desc370_p_O_FDCEinner_prod_ ;
input p_desc371_p_O_FDCEinner_prod_ ;
input p_desc372_p_O_FDCEinner_prod_ ;
input p_desc373_p_O_FDCEinner_prod_ ;
input p_desc374_p_O_FDCEinner_prod_ ;
input p_desc1263_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1264_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1266_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1267_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1269_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1270_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1271_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1272_p_O_FDCEqr_decomp_ctl_ ;
input p_desc1273_p_O_FDCEqr_decomp_ctl_ ;
// instances
mat_regs_inj A_Q_mat(.col_sel_AQ2_mux_i_m3_lut6_2_O6(col_sel_AQ2_mux_i_m3_lut6_2_O6),.col_sel_AQ2_mux_i_m3_lut6_2_O5(col_sel_AQ2_mux_i_m3_lut6_2_O5),.col_sel_AQ_int(col_sel_AQ_int[1:0]),.w_col_sel_AQ_mux_i_m3_lut6_2_O6(w_col_sel_AQ_mux_i_m3_lut6_2_O6),.w_col_sel_AQ_mux_i_m3_lut6_2_O5(w_col_sel_AQ_mux_i_m3_lut6_2_O5),.vec_out_r_AQ_0(vec_out_r_AQ_0[11:0]),.vec_in_r_AQ_mux_0_4(vec_in_r_AQ_mux_0[5:5]),.vec_in_r_AQ_mux_0_9(vec_in_r_AQ_mux_0[10:10]),.vec_in_r_AQ_mux_0_6(vec_in_r_AQ_mux_0[7:7]),.vec_in_r_AQ_mux_0_0(vec_in_r_AQ_mux_0[1:1]),.vec_in_r_AQ_mux_0_1(vec_in_r_AQ_mux_0[2:2]),.vec_in_r_AQ_mux_0_2(vec_in_r_AQ_mux_0[3:3]),.vec_in_r_AQ_mux_0_3(vec_in_r_AQ_mux_0[4:4]),.vec_in_r_AQ_mux_0_10(vec_in_r_AQ_mux_0[11:11]),.vec_in_r_AQ_mux_0_7(vec_in_r_AQ_mux_0[8:8]),.vec_in_r_AQ_mux_0_8(vec_in_r_AQ_mux_0[9:9]),.vec_out_r_AQ_3(vec_out_r_AQ_3[11:0]),.vec_in_r_AQ_mux_3(vec_in_r_AQ_mux_3[11:0]),.out_Q_r(out_Q_r[47:0]),.vec_out_r_AQ_2(vec_out_r_AQ_2[11:0]),.vec_out_r_AQ_1(vec_out_r_AQ_1[11:0]),.vec_in_r_AQ_mux_2(vec_in_r_AQ_mux_2[11:0]),.vec_in_r_AQ_mux_1(vec_in_r_AQ_mux_1[11:0]),.vec_out_i_AQ_0(vec_out_i_AQ_0[11:0]),.vec_in_i_AQ_mux_0_5(vec_in_i_AQ_mux_0[5:5]),.vec_in_i_AQ_mux_0_10(vec_in_i_AQ_mux_0[10:10]),.vec_in_i_AQ_mux_0_7(vec_in_i_AQ_mux_0[7:7]),.vec_in_i_AQ_mux_0_0(vec_in_i_AQ_mux_0[0:0]),.vec_in_i_AQ_mux_0_1(vec_in_i_AQ_mux_0[1:1]),.vec_in_i_AQ_mux_0_4(vec_in_i_AQ_mux_0[4:4]),.vec_in_i_AQ_mux_0_6(vec_in_i_AQ_mux_0[6:6]),.vec_in_i_AQ_mux_0_11(vec_in_i_AQ_mux_0[11:11]),.vec_in_i_AQ_mux_0_8(vec_in_i_AQ_mux_0[8:8]),.vec_in_i_AQ_mux_0_9(vec_in_i_AQ_mux_0[9:9]),.vec_out_i_AQ_3(vec_out_i_AQ_3[11:0]),.vec_in_i_AQ_mux_3(vec_in_i_AQ_mux_3[11:0]),.out_Q_i(out_Q_i[47:0]),.vec_out_i_AQ_2(vec_out_i_AQ_2[11:0]),.vec_out_i_AQ_1(vec_out_i_AQ_1[11:0]),.vec_in_i_AQ_mux_2(vec_in_i_AQ_mux_2[11:0]),.vec_in_i_AQ_mux_1(vec_in_i_AQ_mux_1[11:0]),.row_sel_AQ(row_sel_AQ[1:0]),.single_out_r_AQ2_1(single_out_r_AQ2[2:2]),.single_out_r_AQ2_6(single_out_r_AQ2[7:7]),.single_out_r_AQ2_4(single_out_r_AQ2[5:5]),.single_out_r_AQ2_0(single_out_r_AQ2[1:1]),.single_out_i_AQ2_1(single_out_i_AQ2[1:1]),.single_out_i_AQ2_5(single_out_i_AQ2[5:5]),.single_out_i_AQ2_4(single_out_i_AQ2[4:4]),.single_out_i_AQ2_0(single_out_i_AQ2[0:0]),.single_out_i_AQ2_11(single_out_i_AQ2[11:11]),.single_out_i_AQ_1(single_out_i_AQ[1:1]),.single_out_i_AQ_0(single_out_i_AQ[0:0]),.single_out_i_AQ_8(single_out_i_AQ[8:8]),.single_out_i_AQ_10(single_out_i_AQ[10:10]),.single_out_i_AQ_11(single_out_i_AQ[11:11]),.single_out_i_AQ_9(single_out_i_AQ[9:9]),.single_out_i_AQ_4(single_out_i_AQ[4:4]),.single_out_r_AQ_4(single_out_r_AQ[5:5]),.single_out_r_AQ_2(single_out_r_AQ[3:3]),.single_out_r_AQ_7(single_out_r_AQ[8:8]),.single_out_r_AQ_1(single_out_r_AQ[2:2]),.single_out_r_AQ_0(single_out_r_AQ[1:1]),.clk(clk),.wr_en_AQ_mux_i_m3_lut6_2_O6(wr_en_AQ_mux_i_m3_lut6_2_O6),.N_507(N_507),.N_508(N_508),.N_505(N_505),.N_506(N_506),.N_645(N_645),.N_641(N_641),.N_637(N_637),.N_632(N_632),.N_628(N_628),.N_624(N_624),.N_623(N_623),.N_622(N_622),.N_612(N_612),.N_607(N_607),.N_606(N_606),.N_605(N_605),.N_597(N_597),.N_596(N_596),.N_595(N_595),.N_586(N_586),.N_585(N_585),.N_584(N_584),.N_583(N_583),.N_582(N_582),.N_571(N_571),.N_568(N_568),.N_567(N_567),.N_566(N_566),.N_555(N_555),.N_552(N_552),.N_549(N_549));
r_mat_regs_inj R_mat(.row_sel_R(row_sel_R[1:0]),.col_sel_R_mux_i_m3_lut6_2_O6(col_sel_R_mux_i_m3_lut6_2_O6),.col_sel_R_mux_i_m3_lut6_2_O5(col_sel_R_mux_i_m3_lut6_2_O5),.single_in_r_R_mux(single_in_r_R_mux[11:11]),.wr_en_AQ_sel(wr_en_AQ_sel),.col_sel_R(col_sel_R[1:0]),.col_sel_R_int(col_sel_R_int[1:0]),.out_R_i(out_R_i[47:12]),.out_R_r(out_R_r[47:0]),.wr_en_R(wr_en_R),.N_28_i(N_28_i),.clk(clk),.N_30_i(N_30_i),.N_32_i(N_32_i),.N_34_i(N_34_i),.N_383_i(N_383_i),.N_384_i(N_384_i),.N_385_i(N_385_i),.N_386_i(N_386_i),.N_387_i(N_387_i),.N_388_i(N_388_i),.N_389_i(N_389_i),.N_390_i(N_390_i),.N_391_i(N_391_i),.N_392_i(N_392_i),.N_393_i(N_393_i),.N_394_i(N_394_i),.N_395_i(N_395_i),.N_396_i(N_396_i),.N_397_i(N_397_i),.N_398_i(N_398_i),.N_399_i(N_399_i),.N_400_i(N_400_i),.N_401_i(N_401_i),.p_desc48_p_O_FDE(p_desc48_p_O_FDEr_mat_regs_),.p_desc49_p_O_FDE(p_desc49_p_O_FDEr_mat_regs_),.p_desc50_p_O_FDE(p_desc50_p_O_FDEr_mat_regs_),.p_desc51_p_O_FDE(p_desc51_p_O_FDEr_mat_regs_),.p_desc52_p_O_FDE(p_desc52_p_O_FDEr_mat_regs_),.p_desc53_p_O_FDE(p_desc53_p_O_FDEr_mat_regs_),.p_desc54_p_O_FDE(p_desc54_p_O_FDEr_mat_regs_),.p_desc55_p_O_FDE(p_desc55_p_O_FDEr_mat_regs_),.p_desc56_p_O_FDE(p_desc56_p_O_FDEr_mat_regs_),.p_desc57_p_O_FDE(p_desc57_p_O_FDEr_mat_regs_),.p_desc58_p_O_FDE(p_desc58_p_O_FDEr_mat_regs_),.p_desc59_p_O_FDE(p_desc59_p_O_FDEr_mat_regs_),.p_desc60_p_O_FDE(p_desc60_p_O_FDEr_mat_regs_),.p_desc61_p_O_FDE(p_desc61_p_O_FDEr_mat_regs_),.p_desc62_p_O_FDE(p_desc62_p_O_FDEr_mat_regs_),.p_desc63_p_O_FDE(p_desc63_p_O_FDEr_mat_regs_),.p_desc64_p_O_FDE(p_desc64_p_O_FDEr_mat_regs_),.p_desc65_p_O_FDE(p_desc65_p_O_FDEr_mat_regs_),.p_desc66_p_O_FDE(p_desc66_p_O_FDEr_mat_regs_),.p_desc67_p_O_FDE(p_desc67_p_O_FDEr_mat_regs_),.p_desc68_p_O_FDE(p_desc68_p_O_FDEr_mat_regs_),.p_desc69_p_O_FDE(p_desc69_p_O_FDEr_mat_regs_),.p_desc70_p_O_FDE(p_desc70_p_O_FDEr_mat_regs_),.p_desc71_p_O_FDE(p_desc71_p_O_FDEr_mat_regs_),.p_desc72_p_O_FDE(p_desc72_p_O_FDEr_mat_regs_),.p_desc73_p_O_FDE(p_desc73_p_O_FDEr_mat_regs_),.p_desc74_p_O_FDE(p_desc74_p_O_FDEr_mat_regs_),.p_desc75_p_O_FDE(p_desc75_p_O_FDEr_mat_regs_),.p_desc76_p_O_FDE(p_desc76_p_O_FDEr_mat_regs_),.p_desc77_p_O_FDE(p_desc77_p_O_FDEr_mat_regs_),.p_desc78_p_O_FDE(p_desc78_p_O_FDEr_mat_regs_),.p_desc79_p_O_FDE(p_desc79_p_O_FDEr_mat_regs_),.p_desc80_p_O_FDE(p_desc80_p_O_FDEr_mat_regs_),.p_desc81_p_O_FDE(p_desc81_p_O_FDEr_mat_regs_),.p_desc82_p_O_FDE(p_desc82_p_O_FDEr_mat_regs_),.p_desc83_p_O_FDE(p_desc83_p_O_FDEr_mat_regs_),.p_desc84_p_O_FDE(p_desc84_p_O_FDEr_mat_regs_),.p_desc85_p_O_FDE(p_desc85_p_O_FDEr_mat_regs_),.p_desc86_p_O_FDE(p_desc86_p_O_FDEr_mat_regs_),.p_desc87_p_O_FDE(p_desc87_p_O_FDEr_mat_regs_),.p_desc88_p_O_FDE(p_desc88_p_O_FDEr_mat_regs_),.p_desc89_p_O_FDE(p_desc89_p_O_FDEr_mat_regs_),.p_desc90_p_O_FDE(p_desc90_p_O_FDEr_mat_regs_),.p_desc91_p_O_FDE(p_desc91_p_O_FDEr_mat_regs_),.p_desc92_p_O_FDE(p_desc92_p_O_FDEr_mat_regs_),.p_desc93_p_O_FDE(p_desc93_p_O_FDEr_mat_regs_),.p_desc94_p_O_FDE(p_desc94_p_O_FDEr_mat_regs_),.p_desc95_p_O_FDE(p_desc95_p_O_FDEr_mat_regs_),.p_desc96_p_O_FDE(p_desc96_p_O_FDEr_mat_regs_),.p_desc97_p_O_FDE(p_desc97_p_O_FDEr_mat_regs_),.p_desc98_p_O_FDE(p_desc98_p_O_FDEr_mat_regs_),.p_desc99_p_O_FDE(p_desc99_p_O_FDEr_mat_regs_),.p_desc100_p_O_FDE(p_desc100_p_O_FDEr_mat_regs_),.p_desc101_p_O_FDE(p_desc101_p_O_FDEr_mat_regs_),.p_desc102_p_O_FDE(p_desc102_p_O_FDEr_mat_regs_),.p_desc103_p_O_FDE(p_desc103_p_O_FDEr_mat_regs_),.p_desc104_p_O_FDE(p_desc104_p_O_FDEr_mat_regs_),.p_desc105_p_O_FDE(p_desc105_p_O_FDEr_mat_regs_),.p_desc106_p_O_FDE(p_desc106_p_O_FDEr_mat_regs_),.p_desc107_p_O_FDE(p_desc107_p_O_FDEr_mat_regs_),.p_desc108_p_O_FDE(p_desc108_p_O_FDEr_mat_regs_),.p_desc109_p_O_FDE(p_desc109_p_O_FDEr_mat_regs_),.p_desc110_p_O_FDE(p_desc110_p_O_FDEr_mat_regs_),.p_desc111_p_O_FDE(p_desc111_p_O_FDEr_mat_regs_),.p_desc112_p_O_FDE(p_desc112_p_O_FDEr_mat_regs_),.p_desc113_p_O_FDE(p_desc113_p_O_FDEr_mat_regs_),.p_desc114_p_O_FDE(p_desc114_p_O_FDEr_mat_regs_),.p_desc115_p_O_FDE(p_desc115_p_O_FDEr_mat_regs_),.p_desc116_p_O_FDE(p_desc116_p_O_FDEr_mat_regs_),.p_desc117_p_O_FDE(p_desc117_p_O_FDEr_mat_regs_),.p_desc118_p_O_FDE(p_desc118_p_O_FDEr_mat_regs_),.p_desc119_p_O_FDE(p_desc119_p_O_FDEr_mat_regs_),.p_desc120_p_O_FDE(p_desc120_p_O_FDEr_mat_regs_),.p_desc121_p_O_FDE(p_desc121_p_O_FDEr_mat_regs_),.p_desc122_p_O_FDE(p_desc122_p_O_FDEr_mat_regs_),.p_desc123_p_O_FDE(p_desc123_p_O_FDEr_mat_regs_),.p_desc124_p_O_FDE(p_desc124_p_O_FDEr_mat_regs_),.p_desc125_p_O_FDE(p_desc125_p_O_FDEr_mat_regs_),.p_desc126_p_O_FDE(p_desc126_p_O_FDEr_mat_regs_),.p_desc127_p_O_FDE(p_desc127_p_O_FDEr_mat_regs_),.p_desc128_p_O_FDE(p_desc128_p_O_FDEr_mat_regs_),.p_desc129_p_O_FDE(p_desc129_p_O_FDEr_mat_regs_),.p_desc130_p_O_FDE(p_desc130_p_O_FDEr_mat_regs_),.p_desc131_p_O_FDE(p_desc131_p_O_FDEr_mat_regs_),.p_desc132_p_O_FDE(p_desc132_p_O_FDEr_mat_regs_),.p_desc133_p_O_FDE(p_desc133_p_O_FDEr_mat_regs_),.p_desc134_p_O_FDE(p_desc134_p_O_FDEr_mat_regs_),.p_desc135_p_O_FDE(p_desc135_p_O_FDEr_mat_regs_),.p_desc136_p_O_FDE(p_desc136_p_O_FDEr_mat_regs_),.p_desc137_p_O_FDE(p_desc137_p_O_FDEr_mat_regs_),.p_desc138_p_O_FDE(p_desc138_p_O_FDEr_mat_regs_),.p_desc139_p_O_FDE(p_desc139_p_O_FDEr_mat_regs_),.p_desc140_p_O_FDE(p_desc140_p_O_FDEr_mat_regs_),.p_desc141_p_O_FDE(p_desc141_p_O_FDEr_mat_regs_),.p_desc142_p_O_FDE(p_desc142_p_O_FDEr_mat_regs_),.p_desc143_p_O_FDE(p_desc143_p_O_FDEr_mat_regs_),.p_desc144_p_O_FDE(p_desc144_p_O_FDEr_mat_regs_),.p_desc145_p_O_FDE(p_desc145_p_O_FDEr_mat_regs_),.p_desc146_p_O_FDE(p_desc146_p_O_FDEr_mat_regs_),.p_desc147_p_O_FDE(p_desc147_p_O_FDEr_mat_regs_),.p_desc148_p_O_FDE(p_desc148_p_O_FDEr_mat_regs_),.p_desc149_p_O_FDE(p_desc149_p_O_FDEr_mat_regs_),.p_desc150_p_O_FDE(p_desc150_p_O_FDEr_mat_regs_),.p_desc151_p_O_FDE(p_desc151_p_O_FDEr_mat_regs_),.p_desc152_p_O_FDE(p_desc152_p_O_FDEr_mat_regs_),.p_desc153_p_O_FDE(p_desc153_p_O_FDEr_mat_regs_),.p_desc154_p_O_FDE(p_desc154_p_O_FDEr_mat_regs_),.p_desc155_p_O_FDE(p_desc155_p_O_FDEr_mat_regs_),.p_desc156_p_O_FDE(p_desc156_p_O_FDEr_mat_regs_),.p_desc157_p_O_FDE(p_desc157_p_O_FDEr_mat_regs_),.p_desc158_p_O_FDE(p_desc158_p_O_FDEr_mat_regs_),.p_desc159_p_O_FDE(p_desc159_p_O_FDEr_mat_regs_),.p_desc160_p_O_FDE(p_desc160_p_O_FDEr_mat_regs_),.p_desc161_p_O_FDE(p_desc161_p_O_FDEr_mat_regs_),.p_desc162_p_O_FDE(p_desc162_p_O_FDEr_mat_regs_),.p_desc163_p_O_FDE(p_desc163_p_O_FDEr_mat_regs_),.p_desc164_p_O_FDE(p_desc164_p_O_FDEr_mat_regs_),.p_desc165_p_O_FDE(p_desc165_p_O_FDEr_mat_regs_),.p_desc166_p_O_FDE(p_desc166_p_O_FDEr_mat_regs_),.p_desc167_p_O_FDE(p_desc167_p_O_FDEr_mat_regs_),.p_desc168_p_O_FDE(p_desc168_p_O_FDEr_mat_regs_),.p_desc169_p_O_FDE(p_desc169_p_O_FDEr_mat_regs_),.p_desc170_p_O_FDE(p_desc170_p_O_FDEr_mat_regs_),.p_desc171_p_O_FDE(p_desc171_p_O_FDEr_mat_regs_),.p_desc172_p_O_FDE(p_desc172_p_O_FDEr_mat_regs_),.p_desc173_p_O_FDE(p_desc173_p_O_FDEr_mat_regs_),.p_desc174_p_O_FDE(p_desc174_p_O_FDEr_mat_regs_),.p_desc175_p_O_FDE(p_desc175_p_O_FDEr_mat_regs_),.p_desc176_p_O_FDE(p_desc176_p_O_FDEr_mat_regs_),.p_desc177_p_O_FDE(p_desc177_p_O_FDEr_mat_regs_),.p_desc178_p_O_FDE(p_desc178_p_O_FDEr_mat_regs_),.p_desc179_p_O_FDE(p_desc179_p_O_FDEr_mat_regs_),.p_desc180_p_O_FDE(p_desc180_p_O_FDEr_mat_regs_),.p_desc181_p_O_FDE(p_desc181_p_O_FDEr_mat_regs_),.p_desc182_p_O_FDE(p_desc182_p_O_FDEr_mat_regs_),.p_desc183_p_O_FDE(p_desc183_p_O_FDEr_mat_regs_),.p_desc184_p_O_FDE(p_desc184_p_O_FDEr_mat_regs_),.p_desc185_p_O_FDE(p_desc185_p_O_FDEr_mat_regs_),.p_desc186_p_O_FDE(p_desc186_p_O_FDEr_mat_regs_),.p_desc187_p_O_FDE(p_desc187_p_O_FDEr_mat_regs_),.p_desc188_p_O_FDE(p_desc188_p_O_FDEr_mat_regs_),.p_desc189_p_O_FDE(p_desc189_p_O_FDEr_mat_regs_),.p_desc190_p_O_FDE(p_desc190_p_O_FDEr_mat_regs_),.p_desc191_p_O_FDE(p_desc191_p_O_FDEr_mat_regs_));
inner_prod_inj inner_prod_inst(.out_inner_prod_i(out_inner_prod_i[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.in_a_inner_prod_sel(in_a_inner_prod_sel),.single_out_r_AQ_7(single_out_r_AQ[8:8]),.single_out_r_AQ_0(single_out_r_AQ[1:1]),.single_out_r_AQ_1(single_out_r_AQ[2:2]),.single_out_r_AQ_4(single_out_r_AQ[5:5]),.single_out_r_AQ_2(single_out_r_AQ[3:3]),.in_b_inner_prod_sel(in_b_inner_prod_sel),.vec_in_r_AQ_mux_0_6(vec_in_r_AQ_mux_0[7:7]),.vec_in_r_AQ_mux_0_7(vec_in_r_AQ_mux_0[8:8]),.vec_in_r_AQ_mux_0_0(vec_in_r_AQ_mux_0[1:1]),.vec_in_r_AQ_mux_0_9(vec_in_r_AQ_mux_0[10:10]),.vec_in_r_AQ_mux_0_1(vec_in_r_AQ_mux_0[2:2]),.vec_in_r_AQ_mux_0_8(vec_in_r_AQ_mux_0[9:9]),.vec_in_r_AQ_mux_0_4(vec_in_r_AQ_mux_0[5:5]),.vec_in_r_AQ_mux_0_3(vec_in_r_AQ_mux_0[4:4]),.vec_in_r_AQ_mux_0_2(vec_in_r_AQ_mux_0[3:3]),.vec_in_r_AQ_mux_0_10(vec_in_r_AQ_mux_0[11:11]),.vec_in_i_AQ_mux_0_7(vec_in_i_AQ_mux_0[7:7]),.vec_in_i_AQ_mux_0_1(vec_in_i_AQ_mux_0[1:1]),.vec_in_i_AQ_mux_0_0(vec_in_i_AQ_mux_0[0:0]),.vec_in_i_AQ_mux_0_6(vec_in_i_AQ_mux_0[6:6]),.vec_in_i_AQ_mux_0_8(vec_in_i_AQ_mux_0[8:8]),.vec_in_i_AQ_mux_0_10(vec_in_i_AQ_mux_0[10:10]),.vec_in_i_AQ_mux_0_5(vec_in_i_AQ_mux_0[5:5]),.vec_in_i_AQ_mux_0_9(vec_in_i_AQ_mux_0[9:9]),.vec_in_i_AQ_mux_0_4(vec_in_i_AQ_mux_0[4:4]),.vec_in_i_AQ_mux_0_11(vec_in_i_AQ_mux_0[11:11]),.single_out_i_AQ_1(single_out_i_AQ[1:1]),.single_out_i_AQ_0(single_out_i_AQ[0:0]),.single_out_i_AQ_8(single_out_i_AQ[8:8]),.single_out_i_AQ_10(single_out_i_AQ[10:10]),.single_out_i_AQ_9(single_out_i_AQ[9:9]),.single_out_i_AQ_4(single_out_i_AQ[4:4]),.single_out_i_AQ_11(single_out_i_AQ[11:11]),.output_iv(output_iv[10:0]),.single_out_r_AQ2_4(single_out_r_AQ2[5:5]),.single_out_r_AQ2_0(single_out_r_AQ2[1:1]),.single_out_r_AQ2_1(single_out_r_AQ2[2:2]),.single_out_r_AQ2_6(single_out_r_AQ2[7:7]),.output_iv_0_4(output_iv_0[5:5]),.output_iv_0_7(output_iv_0[8:8]),.output_iv_0_0(output_iv_0[1:1]),.output_iv_0_9(output_iv_0[10:10]),.output_iv_0_1(output_iv_0[2:2]),.output_iv_0_6(output_iv_0[7:7]),.output_iv_0_3(output_iv_0[4:4]),.output_iv_0_2(output_iv_0[3:3]),.output_iv_0_8(output_iv_0[9:9]),.out_r_vec_sub_0(out_r_vec_sub_0[11:11]),.out_i_vec_sub_0(out_i_vec_sub_0[11:11]),.single_out_i_AQ2_0(single_out_i_AQ2[0:0]),.single_out_i_AQ2_5(single_out_i_AQ2[5:5]),.single_out_i_AQ2_4(single_out_i_AQ2[4:4]),.single_out_i_AQ2_1(single_out_i_AQ2[1:1]),.single_out_i_AQ2_11(single_out_i_AQ2[11:11]),.start_inner_prod(start_inner_prod),.red_mat_reg(red_mat_reg),.clk(clk),.rst(rst),.done_inner_prod(done_inner_prod),.N_623(N_623),.N_568(N_568),.N_622(N_622),.N_507(N_507),.N_549(N_549),.N_505(N_505),.N_597(N_597),.N_567(N_567),.N_596(N_596),.N_628(N_628),.N_637(N_637),.N_566(N_566),.N_506(N_506),.N_585(N_585),.N_584(N_584),.N_612(N_612),.N_583(N_583),.N_595(N_595),.N_508(N_508),.N_501(N_501),.N_605(N_605),.N_624(N_624),.N_607(N_607),.N_552(N_552),.N_555(N_555),.N_586(N_586),.N_645(N_645),.N_641(N_641),.N_582(N_582),.N_606(N_606),.N_632(N_632),.N_500(N_500),.N_571(N_571),.p_desc318_p_O_FDC(p_desc318_p_O_FDCinner_prod_),.p_desc319_p_O_FDC(p_desc319_p_O_FDCinner_prod_),.p_desc320_p_O_FDC(p_desc320_p_O_FDCinner_prod_),.p_desc321_p_O_FDC(p_desc321_p_O_FDCinner_prod_),.p_desc322_p_O_FDC(p_desc322_p_O_FDCinner_prod_),.p_in_reg_enable_fsm_Z_p_O_FDC(p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_),.p_done_Z_p_O_FDC(p_done_Z_p_O_FDCinner_prod_),.p_acc_enable_Z_p_O_FDC(p_acc_enable_Z_p_O_FDCinner_prod_),.p_desc325_p_O_FDC(p_desc325_p_O_FDCinner_prod_),.p_desc326_p_O_FDC(p_desc326_p_O_FDCinner_prod_),.p_desc327_p_O_FDC(p_desc327_p_O_FDCinner_prod_),.p_desc328_p_O_FDC(p_desc328_p_O_FDCinner_prod_),.p_desc329_p_O_FDC(p_desc329_p_O_FDCinner_prod_),.p_desc330_p_O_FDC(p_desc330_p_O_FDCinner_prod_),.p_desc331_p_O_FDC(p_desc331_p_O_FDCinner_prod_),.p_desc332_p_O_FDC(p_desc332_p_O_FDCinner_prod_),.p_desc333_p_O_FDC(p_desc333_p_O_FDCinner_prod_),.p_desc334_p_O_FDC(p_desc334_p_O_FDCinner_prod_),.p_desc335_p_O_FDC(p_desc335_p_O_FDCinner_prod_),.p_desc336_p_O_FDC(p_desc336_p_O_FDCinner_prod_),.p_desc337_p_O_FDC(p_desc337_p_O_FDCinner_prod_),.p_desc338_p_O_FDC(p_desc338_p_O_FDCinner_prod_),.p_desc339_p_O_FDC(p_desc339_p_O_FDCinner_prod_),.p_desc340_p_O_FDC(p_desc340_p_O_FDCinner_prod_),.p_desc341_p_O_FDC(p_desc341_p_O_FDCinner_prod_),.p_desc342_p_O_FDC(p_desc342_p_O_FDCinner_prod_),.p_desc343_p_O_FDC(p_desc343_p_O_FDCinner_prod_),.p_desc344_p_O_FDC(p_desc344_p_O_FDCinner_prod_),.p_desc345_p_O_FDC(p_desc345_p_O_FDCinner_prod_),.p_desc346_p_O_FDC(p_desc346_p_O_FDCinner_prod_),.p_desc347_p_O_FDC(p_desc347_p_O_FDCinner_prod_),.p_desc348_p_O_FDC(p_desc348_p_O_FDCinner_prod_),.p_desc349_p_O_FDC(p_desc349_p_O_FDCinner_prod_),.p_desc350_p_O_FDC(p_desc350_p_O_FDCinner_prod_),.p_desc375_p_O_FDC(p_desc375_p_O_FDCinner_prod_),.p_desc376_p_O_FDC(p_desc376_p_O_FDCinner_prod_),.p_desc377_p_O_FDC(p_desc377_p_O_FDCinner_prod_),.p_desc378_p_O_FDC(p_desc378_p_O_FDCinner_prod_),.p_desc379_p_O_FDC(p_desc379_p_O_FDCinner_prod_),.p_desc380_p_O_FDC(p_desc380_p_O_FDCinner_prod_),.p_desc381_p_O_FDC(p_desc381_p_O_FDCinner_prod_),.p_desc382_p_O_FDC(p_desc382_p_O_FDCinner_prod_),.p_desc383_p_O_FDC(p_desc383_p_O_FDCinner_prod_),.p_desc384_p_O_FDC(p_desc384_p_O_FDCinner_prod_),.p_desc385_p_O_FDC(p_desc385_p_O_FDCinner_prod_),.p_desc386_p_O_FDC(p_desc386_p_O_FDCinner_prod_),.p_desc387_p_O_FDC(p_desc387_p_O_FDCinner_prod_),.p_desc388_p_O_FDC(p_desc388_p_O_FDCinner_prod_),.p_desc389_p_O_FDC(p_desc389_p_O_FDCinner_prod_),.p_desc390_p_O_FDC(p_desc390_p_O_FDCinner_prod_),.p_desc391_p_O_FDC(p_desc391_p_O_FDCinner_prod_),.p_desc392_p_O_FDC(p_desc392_p_O_FDCinner_prod_),.p_desc393_p_O_FDC(p_desc393_p_O_FDCinner_prod_),.p_desc394_p_O_FDC(p_desc394_p_O_FDCinner_prod_),.p_desc395_p_O_FDC(p_desc395_p_O_FDCinner_prod_),.p_desc396_p_O_FDC(p_desc396_p_O_FDCinner_prod_),.p_desc397_p_O_FDC(p_desc397_p_O_FDCinner_prod_),.p_desc398_p_O_FDC(p_desc398_p_O_FDCinner_prod_),.p_acc_clear_Z_p_O_FDP(p_acc_clear_Z_p_O_FDPinner_prod_),.p_desc324_p_O_FDCE(p_desc324_p_O_FDCEinner_prod_),.p_desc351_p_O_FDCE(p_desc351_p_O_FDCEinner_prod_),.p_desc352_p_O_FDCE(p_desc352_p_O_FDCEinner_prod_),.p_desc353_p_O_FDCE(p_desc353_p_O_FDCEinner_prod_),.p_desc354_p_O_FDCE(p_desc354_p_O_FDCEinner_prod_),.p_desc355_p_O_FDCE(p_desc355_p_O_FDCEinner_prod_),.p_desc356_p_O_FDCE(p_desc356_p_O_FDCEinner_prod_),.p_desc357_p_O_FDCE(p_desc357_p_O_FDCEinner_prod_),.p_desc358_p_O_FDCE(p_desc358_p_O_FDCEinner_prod_),.p_desc359_p_O_FDCE(p_desc359_p_O_FDCEinner_prod_),.p_desc360_p_O_FDCE(p_desc360_p_O_FDCEinner_prod_),.p_desc361_p_O_FDCE(p_desc361_p_O_FDCEinner_prod_),.p_desc362_p_O_FDCE(p_desc362_p_O_FDCEinner_prod_),.p_desc363_p_O_FDCE(p_desc363_p_O_FDCEinner_prod_),.p_desc364_p_O_FDCE(p_desc364_p_O_FDCEinner_prod_),.p_desc365_p_O_FDCE(p_desc365_p_O_FDCEinner_prod_),.p_desc366_p_O_FDCE(p_desc366_p_O_FDCEinner_prod_),.p_desc367_p_O_FDCE(p_desc367_p_O_FDCEinner_prod_),.p_desc368_p_O_FDCE(p_desc368_p_O_FDCEinner_prod_),.p_desc369_p_O_FDCE(p_desc369_p_O_FDCEinner_prod_),.p_desc370_p_O_FDCE(p_desc370_p_O_FDCEinner_prod_),.p_desc371_p_O_FDCE(p_desc371_p_O_FDCEinner_prod_),.p_desc372_p_O_FDCE(p_desc372_p_O_FDCEinner_prod_),.p_desc373_p_O_FDCE(p_desc373_p_O_FDCEinner_prod_),.p_desc374_p_O_FDCE(p_desc374_p_O_FDCEinner_prod_));
vec_mult_inj vec_mult_inst(.in_b_vec_mult_sel(in_b_vec_mult_sel),.out_inner_prod_i(out_inner_prod_i[11:0]),.out_i_vec_mult_2(out_i_vec_mult_2[11:0]),.out_r_vec_mult_2(out_r_vec_mult_2[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_2(vec_out_r_AQ_2[11:0]),.out_inv_sqrt_0(out_inv_sqrt[0:0]),.out_inv_sqrt_1(out_inv_sqrt[1:1]),.out_inv_sqrt_2(out_inv_sqrt[2:2]),.out_inv_sqrt_7(out_inv_sqrt[7:7]),.out_inv_sqrt_8(out_inv_sqrt[8:8]),.out_inv_sqrt_9(out_inv_sqrt[9:9]),.out_inv_sqrt_10(out_inv_sqrt[10:10]),.out_inv_sqrt_11(out_inv_sqrt[11:11]),.vec_out_i_AQ_2(vec_out_i_AQ_2[11:0]),.out_i_vec_mult_1(out_i_vec_mult_1[11:0]),.out_r_vec_mult_1(out_r_vec_mult_1[11:0]),.vec_out_r_AQ_1(vec_out_r_AQ_1[11:0]),.vec_out_i_AQ_1(vec_out_i_AQ_1[11:0]),.out_i_vec_mult_0(out_i_vec_mult_0[11:0]),.out_r_vec_mult_0(out_r_vec_mult_0[11:0]),.vec_out_r_AQ_0(vec_out_r_AQ_0[11:0]),.vec_out_i_AQ_0(vec_out_i_AQ_0[11:0]),.out_i_vec_mult_3(out_i_vec_mult_3[11:0]),.out_r_vec_mult_3(out_r_vec_mult_3[11:0]),.vec_out_r_AQ_3(vec_out_r_AQ_3[11:0]),.vec_out_i_AQ_3(vec_out_i_AQ_3[11:0]),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
vec_sub_inj vec_sub_inst(.in_a_r_reg_3_11(in_a_r_reg_3[11:11]),.in_a_r_reg_2_11(in_a_r_reg_2[11:11]),.in_a_r_reg_1_11(in_a_r_reg_1[11:11]),.in_a_r_reg_0_0(in_a_r_reg_0[0:0]),.in_a_r_reg_0_11(in_a_r_reg_0[11:11]),.out_Q_r(out_Q_r[47:0]),.in_a_i_reg_3_11(in_a_i_reg_3[11:11]),.in_a_i_reg_2_11(in_a_i_reg_2[11:11]),.in_a_i_reg_1_11(in_a_i_reg_1[11:11]),.in_a_i_reg_0_11(in_a_i_reg_0[11:11]),.out_Q_i(out_Q_i[47:0]),.out_r_vec_mult_0(out_r_vec_mult_0[11:0]),.out_r_vec_mult_1(out_r_vec_mult_1[11:0]),.out_r_vec_mult_2(out_r_vec_mult_2[11:0]),.pre_out(pre_out[11:1]),.out_r_vec_mult_3(out_r_vec_mult_3[11:0]),.pre_out_i_m_1(pre_out_i_m[0:0]),.pre_out_0(pre_out_0[11:1]),.output_iv({output_iv[10:10],output_iv_0[9:7],output_iv[6:5],output_iv_0[4:4],output_iv[3:3],output_iv_0[2:2],output_iv[1:0]}),.output_iv_0_0(output_iv_0[1:1]),.output_iv_0_1(output_iv[2:2]),.output_iv_0_2(output_iv_0[3:3]),.output_iv_0_3(output_iv[4:4]),.output_iv_0_4(output_iv_0[5:5]),.output_iv_0_6(output_iv[7:7]),.output_iv_0_7(output_iv[8:8]),.output_iv_0_8(output_iv[9:9]),.output_iv_0_9(output_iv_0[10:10]),.out_i_vec_sub_0(out_i_vec_sub_0[11:11]),.out_i_vec_mult_0(out_i_vec_mult_0[11:0]),.pre_out_i_m_2(pre_out_i_m_0[0:0]),.out_i_vec_mult_1(out_i_vec_mult_1[11:0]),.pre_out_1(pre_out_1[11:1]),.pre_out_4(pre_out_2[11:11]),.pre_out_i_m_3(pre_out_i_m_1),.out_i_vec_mult_2(out_i_vec_mult_2[11:0]),.pre_out_2({pre_out_3[11:11],pre_out_2[10:1]}),.pre_out_5(pre_out_4[11:11]),.out_i_vec_mult_3(out_i_vec_mult_3[11:0]),.pre_out_i_m({pre_out_i_m[10:1],pre_out_i_m_2}),.pre_out_i_m_0_0(pre_out_i_m_3),.pre_out_i_m_0_1(pre_out_i_m_0[1:1]),.pre_out_i_m_0_6(pre_out_i_m_0[6:6]),.pre_out_i_m_0_4(pre_out_i_m_0[4:4]),.pre_out_i_m_4(pre_out_i_m_4),.pre_out_6(pre_out_5[11:11]),.pre_out_3_9(pre_out_6[11:11]),.pre_out_3_0(pre_out_3[2:2]),.pre_out_3_1(pre_out_3[3:3]),.pre_out_3_3(pre_out_3[5:5]),.pre_out_3_5(pre_out_3[7:7]),.pre_out_3_7(pre_out_3[9:9]),.pre_out_3_8(pre_out_3[10:10]),.pre_out_3_6(pre_out_3[8:8]),.clk(clk),.w_in_a_vec_sub(w_in_a_vec_sub),.N_500(N_500),.un5_output(un5_output),.un5_output_0(un5_output_0),.un5_output_1(un5_output_1),.un5_output_2(un5_output_2),.un5_output_3(un5_output_3),.un5_output_4(un5_output_4),.p_desc739_p_O_FDE(p_desc739_p_O_FDEvec_sub_),.p_desc740_p_O_FDE(p_desc740_p_O_FDEvec_sub_),.p_desc741_p_O_FDE(p_desc741_p_O_FDEvec_sub_),.p_desc742_p_O_FDE(p_desc742_p_O_FDEvec_sub_),.p_desc743_p_O_FDE(p_desc743_p_O_FDEvec_sub_),.p_desc744_p_O_FDE(p_desc744_p_O_FDEvec_sub_),.p_desc745_p_O_FDE(p_desc745_p_O_FDEvec_sub_),.p_desc746_p_O_FDE(p_desc746_p_O_FDEvec_sub_),.p_desc747_p_O_FDE(p_desc747_p_O_FDEvec_sub_),.p_desc748_p_O_FDE(p_desc748_p_O_FDEvec_sub_),.p_desc749_p_O_FDE(p_desc749_p_O_FDEvec_sub_),.p_desc750_p_O_FDE(p_desc750_p_O_FDEvec_sub_),.p_desc751_p_O_FDE(p_desc751_p_O_FDEvec_sub_),.p_desc752_p_O_FDE(p_desc752_p_O_FDEvec_sub_),.p_desc753_p_O_FDE(p_desc753_p_O_FDEvec_sub_),.p_desc754_p_O_FDE(p_desc754_p_O_FDEvec_sub_),.p_desc755_p_O_FDE(p_desc755_p_O_FDEvec_sub_),.p_desc756_p_O_FDE(p_desc756_p_O_FDEvec_sub_),.p_desc757_p_O_FDE(p_desc757_p_O_FDEvec_sub_),.p_desc758_p_O_FDE(p_desc758_p_O_FDEvec_sub_),.p_desc759_p_O_FDE(p_desc759_p_O_FDEvec_sub_),.p_desc760_p_O_FDE(p_desc760_p_O_FDEvec_sub_),.p_desc761_p_O_FDE(p_desc761_p_O_FDEvec_sub_),.p_desc762_p_O_FDE(p_desc762_p_O_FDEvec_sub_),.p_desc763_p_O_FDE(p_desc763_p_O_FDEvec_sub_),.p_desc764_p_O_FDE(p_desc764_p_O_FDEvec_sub_),.p_desc765_p_O_FDE(p_desc765_p_O_FDEvec_sub_),.p_desc766_p_O_FDE(p_desc766_p_O_FDEvec_sub_),.p_desc767_p_O_FDE(p_desc767_p_O_FDEvec_sub_),.p_desc768_p_O_FDE(p_desc768_p_O_FDEvec_sub_),.p_desc769_p_O_FDE(p_desc769_p_O_FDEvec_sub_),.p_desc770_p_O_FDE(p_desc770_p_O_FDEvec_sub_),.p_desc771_p_O_FDE(p_desc771_p_O_FDEvec_sub_),.p_desc772_p_O_FDE(p_desc772_p_O_FDEvec_sub_),.p_desc773_p_O_FDE(p_desc773_p_O_FDEvec_sub_),.p_desc774_p_O_FDE(p_desc774_p_O_FDEvec_sub_),.p_desc775_p_O_FDE(p_desc775_p_O_FDEvec_sub_),.p_desc776_p_O_FDE(p_desc776_p_O_FDEvec_sub_),.p_desc777_p_O_FDE(p_desc777_p_O_FDEvec_sub_),.p_desc778_p_O_FDE(p_desc778_p_O_FDEvec_sub_),.p_desc779_p_O_FDE(p_desc779_p_O_FDEvec_sub_),.p_desc780_p_O_FDE(p_desc780_p_O_FDEvec_sub_),.p_desc781_p_O_FDE(p_desc781_p_O_FDEvec_sub_),.p_desc782_p_O_FDE(p_desc782_p_O_FDEvec_sub_),.p_desc783_p_O_FDE(p_desc783_p_O_FDEvec_sub_),.p_desc784_p_O_FDE(p_desc784_p_O_FDEvec_sub_),.p_desc785_p_O_FDE(p_desc785_p_O_FDEvec_sub_),.p_desc786_p_O_FDE(p_desc786_p_O_FDEvec_sub_),.p_desc787_p_O_FDE(p_desc787_p_O_FDEvec_sub_),.p_desc788_p_O_FDE(p_desc788_p_O_FDEvec_sub_),.p_desc789_p_O_FDE(p_desc789_p_O_FDEvec_sub_),.p_desc790_p_O_FDE(p_desc790_p_O_FDEvec_sub_),.p_desc791_p_O_FDE(p_desc791_p_O_FDEvec_sub_),.p_desc792_p_O_FDE(p_desc792_p_O_FDEvec_sub_),.p_desc793_p_O_FDE(p_desc793_p_O_FDEvec_sub_),.p_desc794_p_O_FDE(p_desc794_p_O_FDEvec_sub_),.p_desc795_p_O_FDE(p_desc795_p_O_FDEvec_sub_),.p_desc796_p_O_FDE(p_desc796_p_O_FDEvec_sub_),.p_desc797_p_O_FDE(p_desc797_p_O_FDEvec_sub_),.p_desc798_p_O_FDE(p_desc798_p_O_FDEvec_sub_),.p_desc799_p_O_FDE(p_desc799_p_O_FDEvec_sub_),.p_desc800_p_O_FDE(p_desc800_p_O_FDEvec_sub_),.p_desc801_p_O_FDE(p_desc801_p_O_FDEvec_sub_),.p_desc802_p_O_FDE(p_desc802_p_O_FDEvec_sub_),.p_desc803_p_O_FDE(p_desc803_p_O_FDEvec_sub_),.p_desc804_p_O_FDE(p_desc804_p_O_FDEvec_sub_),.p_desc805_p_O_FDE(p_desc805_p_O_FDEvec_sub_),.p_desc806_p_O_FDE(p_desc806_p_O_FDEvec_sub_),.p_desc807_p_O_FDE(p_desc807_p_O_FDEvec_sub_),.p_desc808_p_O_FDE(p_desc808_p_O_FDEvec_sub_),.p_desc809_p_O_FDE(p_desc809_p_O_FDEvec_sub_),.p_desc810_p_O_FDE(p_desc810_p_O_FDEvec_sub_),.p_desc811_p_O_FDE(p_desc811_p_O_FDEvec_sub_),.p_desc812_p_O_FDE(p_desc812_p_O_FDEvec_sub_),.p_desc813_p_O_FDE(p_desc813_p_O_FDEvec_sub_),.p_desc814_p_O_FDE(p_desc814_p_O_FDEvec_sub_),.p_desc815_p_O_FDE(p_desc815_p_O_FDEvec_sub_),.p_desc816_p_O_FDE(p_desc816_p_O_FDEvec_sub_),.p_desc817_p_O_FDE(p_desc817_p_O_FDEvec_sub_),.p_desc818_p_O_FDE(p_desc818_p_O_FDEvec_sub_),.p_desc819_p_O_FDE(p_desc819_p_O_FDEvec_sub_),.p_desc820_p_O_FDE(p_desc820_p_O_FDEvec_sub_),.p_desc821_p_O_FDE(p_desc821_p_O_FDEvec_sub_),.p_desc822_p_O_FDE(p_desc822_p_O_FDEvec_sub_),.p_desc823_p_O_FDE(p_desc823_p_O_FDEvec_sub_),.p_desc824_p_O_FDE(p_desc824_p_O_FDEvec_sub_),.p_desc825_p_O_FDE(p_desc825_p_O_FDEvec_sub_),.p_desc826_p_O_FDE(p_desc826_p_O_FDEvec_sub_),.p_desc827_p_O_FDE(p_desc827_p_O_FDEvec_sub_),.p_desc828_p_O_FDE(p_desc828_p_O_FDEvec_sub_),.p_desc829_p_O_FDE(p_desc829_p_O_FDEvec_sub_),.p_desc830_p_O_FDE(p_desc830_p_O_FDEvec_sub_),.p_desc831_p_O_FDE(p_desc831_p_O_FDEvec_sub_),.p_desc832_p_O_FDE(p_desc832_p_O_FDEvec_sub_),.p_desc833_p_O_FDE(p_desc833_p_O_FDEvec_sub_),.p_desc834_p_O_FDE(p_desc834_p_O_FDEvec_sub_));
mult_with_reg_inj r_mult(.un8_rnd_out(un8_rnd_out[10:0]),.un8_rnd_out_P_19(un8_rnd_out_P[19:19]),.out_inv_sqrt_0(out_inv_sqrt[0:0]),.out_inv_sqrt_1(out_inv_sqrt[1:1]),.out_inv_sqrt_2(out_inv_sqrt[2:2]),.out_inv_sqrt_7(out_inv_sqrt[7:7]),.out_inv_sqrt_8(out_inv_sqrt[8:8]),.out_inv_sqrt_9(out_inv_sqrt[9:9]),.out_inv_sqrt_10(out_inv_sqrt[10:10]),.out_inv_sqrt_11(out_inv_sqrt[11:11]),.out_inner_prod_r(out_inner_prod_r[11:0]),.pre_out_19(pre_out[19:19]),.pre_out_20(pre_out[20:20]),.pre_out_21(pre_out[21:21]),.pre_out_22(pre_out[22:22]),.pre_out_reg(pre_out_reg[23:23]),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i),.N_512_i(N_512_i),.clk(clk),.PATTERNDETECT_32(PATTERNDETECT_32));
inv_sqrt_inj inv_sqrt_inst(.out_inner_prod_r(out_inner_prod_r[11:0]),.out_inv_sqrt_9(out_inv_sqrt[9:9]),.out_inv_sqrt_10(out_inv_sqrt[10:10]),.out_inv_sqrt_8(out_inv_sqrt[8:8]),.out_inv_sqrt_7(out_inv_sqrt[7:7]),.out_inv_sqrt_2(out_inv_sqrt[2:2]),.out_inv_sqrt_1(out_inv_sqrt[1:1]),.out_inv_sqrt_11(out_inv_sqrt[11:11]),.out_inv_sqrt_0(out_inv_sqrt[0:0]),.done_inv_sqrt(done_inv_sqrt),.clk(clk),.rst(rst),.start_inv_sqrt(start_inv_sqrt),.N_434_i(N_434_i),.N_431_i(N_431_i),.N_428_i(N_428_i),.N_425_i(N_425_i),.p_output_reg_pipe_13_Z_p_O_FDshifterZ0_(p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_),.p_output_reg_pipe_12_Z_p_O_FDshifterZ0_(p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_),.p_output_reg_pipe_Z_p_O_FDshifterZ0_(p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_),.p_desc951_p_O_FDE(p_desc951_p_O_FDEinv_sqrt_),.p_desc952_p_O_FDE(p_desc952_p_O_FDEinv_sqrt_),.p_desc953_p_O_FDE(p_desc953_p_O_FDEinv_sqrt_),.p_desc954_p_O_FDE(p_desc954_p_O_FDEinv_sqrt_),.p_desc955_p_O_FDE(p_desc955_p_O_FDEinv_sqrt_),.p_desc956_p_O_FDE(p_desc956_p_O_FDEinv_sqrt_),.p_desc957_p_O_FDE(p_desc957_p_O_FDEinv_sqrt_),.p_desc958_p_O_FDE(p_desc958_p_O_FDEinv_sqrt_),.p_desc959_p_O_FDE(p_desc959_p_O_FDEinv_sqrt_),.p_desc960_p_O_FDE(p_desc960_p_O_FDEinv_sqrt_),.p_desc961_p_O_FDE(p_desc961_p_O_FDEinv_sqrt_),.p_desc962_p_O_FDE(p_desc962_p_O_FDEinv_sqrt_),.p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_(p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_),.p_output_reg_pipe_Z_p_O_FDRE(p_output_reg_pipe_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_3_Z_p_O_FDRE(p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_6_Z_p_O_FDRE(p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_9_Z_p_O_FDRE(p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_12_Z_p_O_FDRE(p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_15_Z_p_O_FDRE(p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_16_Z_p_O_FDRE(p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_17_Z_p_O_FDRE(p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_18_Z_p_O_FDRE(p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_),.p_output_reg_pipe_21_Z_p_O_FDRE(p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_),.p_done_Z_p_O_FDC(p_done_Z_p_O_FDCinv_sqrt_),.p_desc946_p_O_FDC(p_desc946_p_O_FDCinv_sqrt_),.p_desc947_p_O_FDC(p_desc947_p_O_FDCinv_sqrt_),.p_desc948_p_O_FDC(p_desc948_p_O_FDCinv_sqrt_),.p_desc949_p_O_FDC(p_desc949_p_O_FDCinv_sqrt_),.p_desc950_p_O_FDC(p_desc950_p_O_FDCinv_sqrt_));
qr_decomp_ctl_mux_inj muxes(.single_in_R_sel(single_in_R_sel),.single_in_R_sel_0(single_in_R_sel_0),.w_col_sel_AQ_int(w_col_sel_AQ_int[1:0]),.col_sel_AQ(col_sel_AQ[1:0]),.wr_en_AQ_sel(wr_en_AQ_sel),.w_col_sel_AQ_mux_i_m3_lut6_2_O6(w_col_sel_AQ_mux_i_m3_lut6_2_O6),.w_col_sel_AQ_mux_i_m3_lut6_2_O5(w_col_sel_AQ_mux_i_m3_lut6_2_O5),.col_sel_AQ2_int(col_sel_AQ2_int[1:0]),.col_sel_AQ2_mux_i_m3_lut6_2_O6(col_sel_AQ2_mux_i_m3_lut6_2_O6),.col_sel_AQ2_mux_i_m3_lut6_2_O5(col_sel_AQ2_mux_i_m3_lut6_2_O5),.state_0(state[3:3]),.state_2(state[5:5]),.state_5(state[8:8]),.wr_en_AQ_sel_0(wr_en_AQ_sel_0),.col_sel_R(col_sel_R[1:0]),.col_sel_R_int(col_sel_R_int[1:0]),.col_sel_R_mux_i_m3_lut6_2_O6(col_sel_R_mux_i_m3_lut6_2_O6),.col_sel_R_mux_i_m3_lut6_2_O5(col_sel_R_mux_i_m3_lut6_2_O5),.in_a_r_reg_0_0(in_a_r_reg_0[0:0]),.in_a_r_reg_0_11(in_a_r_reg_0[11:11]),.out_r_vec_sub_0(out_r_vec_sub_0[11:11]),.in_a_i_reg_1(in_a_i_reg_1[11:11]),.vec_in_AQ_sel(vec_in_AQ_sel[1:0]),.in_a_r_reg_3(in_a_r_reg_3[11:11]),.in_a_i_reg_0(in_a_i_reg_0[11:11]),.in_a_i_reg_3(in_a_i_reg_3[11:11]),.in_a_r_reg_1(in_a_r_reg_1[11:11]),.pre_out_4(pre_out_0[11:11]),.pre_out_0({pre_out_2[11:11],pre_out_1[10:9],pre_out_0[8:8],pre_out_1[7:7],pre_out_0[6:6],pre_out_1[5:5],pre_out_0[4:4],pre_out_1[3:2],pre_out[1:1]}),.in_a_r_reg_2(in_a_r_reg_2[11:11]),.pre_out_5(pre_out_1[11:11]),.pre_out_1({pre_out_3[11:11],pre_out[10:9],pre_out_3[8:8],pre_out[7:2],pre_out_0[1:1]}),.in_a_i_reg_2(in_a_i_reg_2[11:11]),.pre_out_6(pre_out_4[11:11]),.pre_out_3_9(pre_out_5[11:11]),.pre_out_3_1(pre_out_3[3:3]),.pre_out_3_7(pre_out_3[9:9]),.pre_out_3_3(pre_out_3[5:5]),.pre_out_3_8(pre_out_3[10:10]),.pre_out_3_5(pre_out_3[7:7]),.pre_out_3_6(pre_out_2[8:8]),.pre_out_3_0(pre_out_3[2:2]),.pre_out_2({pre_out_6[11:11],pre_out_0[10:9],pre_out[8:8],pre_out_0[7:7],pre_out_2[6:6],pre_out_0[5:5],pre_out_2[4:4],pre_out_0[3:2],pre_out_2[1:1]}),.out_inner_prod_i(out_inner_prod_i[11:0]),.pre_out_10(pre_out[11:11]),.pre_out_9(pre_out_2[10:10]),.pre_out_0_d0(pre_out_1[1:1]),.pre_out_1_d0(pre_out_2[2:2]),.pre_out_3_d0(pre_out_1[4:4]),.pre_out_6_d0(pre_out_2[7:7]),.pre_out_7(pre_out_1[8:8]),.pre_out_8(pre_out_2[9:9]),.pre_out_5_d0(pre_out_1[6:6]),.pre_out_4_d0(pre_out_2[5:5]),.pre_out_2_d0(pre_out_2[3:3]),.pre_out_18(pre_out[19:19]),.pre_out_19(pre_out[20:20]),.pre_out_20(pre_out[21:21]),.pre_out_21(pre_out[22:22]),.pre_out_reg(pre_out_reg[23:23]),.out_r_vec_mult_2(out_r_vec_mult_2[11:0]),.vec_in_r_AQ_mux_2(vec_in_r_AQ_mux_2[11:0]),.out_r_vec_mult_1(out_r_vec_mult_1[11:0]),.vec_in_r_AQ_mux_1(vec_in_r_AQ_mux_1[11:0]),.pre_out_i_m({pre_out_i_m[10:2],pre_out_i_m_0[1:1],pre_out_i_m_3}),.out_i_vec_mult_3(out_i_vec_mult_3[11:0]),.pre_out_i_m_1(pre_out_i_m_4),.vec_in_i_AQ_mux_3(vec_in_i_AQ_mux_3[11:0]),.output_iv({output_iv[10:10],output_iv_0[9:9],output_iv[8:8],output_iv_0[7:7],output_iv[6:5],output_iv_0[4:3],output_iv[2:2],output_iv_0[1:1],output_iv[0:0]}),.out_i_vec_mult_0(out_i_vec_mult_0[11:0]),.vec_in_i_AQ_mux_0_11(vec_in_i_AQ_mux_0[11:11]),.vec_in_i_AQ_mux_0_1(vec_in_i_AQ_mux_0[1:1]),.vec_in_i_AQ_mux_0_5(vec_in_i_AQ_mux_0[5:5]),.vec_in_i_AQ_mux_0_0(vec_in_i_AQ_mux_0[0:0]),.vec_in_i_AQ_mux_0_8(vec_in_i_AQ_mux_0[8:8]),.vec_in_i_AQ_mux_0_10(vec_in_i_AQ_mux_0[10:10]),.vec_in_i_AQ_mux_0_7(vec_in_i_AQ_mux_0[7:7]),.vec_in_i_AQ_mux_0_6(vec_in_i_AQ_mux_0[6:6]),.vec_in_i_AQ_mux_0_9(vec_in_i_AQ_mux_0[9:9]),.vec_in_i_AQ_mux_0_4(vec_in_i_AQ_mux_0[4:4]),.out_r_vec_mult_0(out_r_vec_mult_0[11:0]),.output_iv_0_2(output_iv[3:3]),.output_iv_0_4(output_iv_0[5:5]),.output_iv_0_1(output_iv_0[2:2]),.output_iv_0_0(output_iv[1:1]),.output_iv_0_9(output_iv_0[10:10]),.output_iv_0_6(output_iv[7:7]),.output_iv_0_8(output_iv[9:9]),.output_iv_0_3(output_iv[4:4]),.output_iv_0_7(output_iv_0[8:8]),.vec_in_r_AQ_mux_0_10(vec_in_r_AQ_mux_0[11:11]),.vec_in_r_AQ_mux_0_2(vec_in_r_AQ_mux_0[3:3]),.vec_in_r_AQ_mux_0_4(vec_in_r_AQ_mux_0[5:5]),.vec_in_r_AQ_mux_0_3(vec_in_r_AQ_mux_0[4:4]),.vec_in_r_AQ_mux_0_6(vec_in_r_AQ_mux_0[7:7]),.vec_in_r_AQ_mux_0_1(vec_in_r_AQ_mux_0[2:2]),.vec_in_r_AQ_mux_0_9(vec_in_r_AQ_mux_0[10:10]),.vec_in_r_AQ_mux_0_8(vec_in_r_AQ_mux_0[9:9]),.vec_in_r_AQ_mux_0_0(vec_in_r_AQ_mux_0[1:1]),.vec_in_r_AQ_mux_0_7(vec_in_r_AQ_mux_0[8:8]),.pre_out_i_m_0_0(pre_out_i_m_2),.pre_out_i_m_0_6(pre_out_i_m_0[6:6]),.pre_out_i_m_0_4(pre_out_i_m_0[4:4]),.pre_out_i_m_0_1(pre_out_i_m[1:1]),.in_A_r(in_A_r[47:0]),.out_r_vec_mult_3(out_r_vec_mult_3[11:0]),.pre_out_i_m_2(pre_out_i_m[0:0]),.vec_in_r_AQ_mux_3(vec_in_r_AQ_mux_3[11:0]),.out_i_vec_mult_2(out_i_vec_mult_2[11:0]),.pre_out_i_m_3(pre_out_i_m_1),.vec_in_i_AQ_mux_2(vec_in_i_AQ_mux_2[11:0]),.in_A_i(in_A_i[47:0]),.out_i_vec_mult_1(out_i_vec_mult_1[11:0]),.pre_out_i_m_4(pre_out_i_m_0[0:0]),.vec_in_i_AQ_mux_1(vec_in_i_AQ_mux_1[11:0]),.un8_rnd_out_P(un8_rnd_out_P[19:19]),.single_in_r_R_mux(single_in_r_R_mux[11:11]),.out_inner_prod_r(out_inner_prod_r[11:0]),.un8_rnd_out(un8_rnd_out[10:0]),.N_390_i(N_390_i),.N_393_i(N_393_i),.done_inv_sqrt(done_inv_sqrt),.N_391_i(N_391_i),.N_394_i(N_394_i),.N_396_i(N_396_i),.N_395_i(N_395_i),.N_397_i(N_397_i),.N_398_i(N_398_i),.N_400_i(N_400_i),.N_399_i(N_399_i),.N_401_i(N_401_i),.wr_en_AQ_int(wr_en_AQ_int),.wr_A_QR(wr_A_QR),.start_QR(start_QR),.wr_en_AQ_mux_i_m3_lut6_2_O6(wr_en_AQ_mux_i_m3_lut6_2_O6),.N_501(N_501),.N_392_i(N_392_i),.PATTERNDETECT_32(PATTERNDETECT_32),.N_500(N_500),.N_508(N_508),.N_507(N_507),.N_506(N_506),.N_505(N_505),.un5_output(un5_output_0),.un5_output_0(un5_output),.un5_output_1(un5_output_4),.un5_output_2(un5_output_1),.un5_output_3(un5_output_3),.un5_output_4(un5_output_2),.N_389_i(N_389_i),.N_388_i(N_388_i),.N_387_i(N_387_i),.N_386_i(N_386_i),.N_385_i(N_385_i),.N_384_i(N_384_i),.N_383_i(N_383_i),.N_34_i(N_34_i),.N_32_i(N_32_i),.N_30_i(N_30_i),.N_28_i(N_28_i));
qr_decomp_ctl_inj the_ctl(.col_sel_AQ_int(col_sel_AQ_int[1:0]),.col_sel_AQ2_int(col_sel_AQ2_int[1:0]),.row_sel_AQ(row_sel_AQ[1:0]),.state_5(state[5:5]),.state_8(state[8:8]),.state_3(state[3:3]),.in_b_inner_prod_sel(in_b_inner_prod_sel),.w_col_sel_AQ_int(w_col_sel_AQ_int[1:0]),.col_sel_R_int(col_sel_R_int[1:0]),.row_sel_R(row_sel_R[1:0]),.in_a_inner_prod_sel(in_a_inner_prod_sel),.vec_in_AQ_sel(vec_in_AQ_sel[1:0]),.single_in_R_sel(single_in_R_sel),.single_in_R_sel_0(single_in_R_sel_0),.wr_en_AQ_sel(wr_en_AQ_sel),.wr_en_AQ_sel_0(wr_en_AQ_sel_0),.in_b_vec_mult_sel(in_b_vec_mult_sel),.red_mat_reg(red_mat_reg),.rst(rst),.done_inv_sqrt(done_inv_sqrt),.N_512_i(N_512_i),.done_inner_prod(done_inner_prod),.start_inv_sqrt(start_inv_sqrt),.clk(clk),.start_inner_prod(start_inner_prod),.wr_en_AQ_int(wr_en_AQ_int),.wr_en_R(wr_en_R),.w_in_a_vec_sub(w_in_a_vec_sub),.done_QR(done_QR),.start_QR(start_QR),.red_mat_reg_0(red_mat_reg_0),.p_desc1255_p_O_FDC(p_desc1255_p_O_FDCqr_decomp_ctl_),.p_desc1256_p_O_FDC(p_desc1256_p_O_FDCqr_decomp_ctl_),.p_desc1257_p_O_FDC(p_desc1257_p_O_FDCqr_decomp_ctl_),.p_desc1258_p_O_FDC(p_desc1258_p_O_FDCqr_decomp_ctl_),.p_start_inner_prod_Z_p_O_FDC(p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_),.p_wr_en_AQ_int_Z_p_O_FDC(p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_),.p_wr_en_R_Z_p_O_FDC(p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_),.p_w_in_a_vec_sub_Z_p_O_FDC(p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_),.p_start_inv_sqrt_Z_p_O_FDC(p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_),.p_desc1274_p_O_FDC(p_desc1274_p_O_FDCqr_decomp_ctl_),.p_pre_red_mat_reg_Z_p_O_FDC(p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_),.p_done_Z_p_O_FDC(p_done_Z_p_O_FDCqr_decomp_ctl_),.p_desc1275_p_O_FDC(p_desc1275_p_O_FDCqr_decomp_ctl_),.p_desc1276_p_O_FDC(p_desc1276_p_O_FDCqr_decomp_ctl_),.p_desc1277_p_O_FDC(p_desc1277_p_O_FDCqr_decomp_ctl_),.p_desc1278_p_O_FDC(p_desc1278_p_O_FDCqr_decomp_ctl_),.p_desc1279_p_O_FDC(p_desc1279_p_O_FDCqr_decomp_ctl_),.p_desc1281_p_O_FDC(p_desc1281_p_O_FDCqr_decomp_ctl_),.p_desc1282_p_O_FDC(p_desc1282_p_O_FDCqr_decomp_ctl_),.p_desc1283_p_O_FDC(p_desc1283_p_O_FDCqr_decomp_ctl_),.p_desc1284_p_O_FDC(p_desc1284_p_O_FDCqr_decomp_ctl_),.p_desc1285_p_O_FDC(p_desc1285_p_O_FDCqr_decomp_ctl_),.p_desc1286_p_O_FDC(p_desc1286_p_O_FDCqr_decomp_ctl_),.p_desc1287_p_O_FDC(p_desc1287_p_O_FDCqr_decomp_ctl_),.p_desc1288_p_O_FDC(p_desc1288_p_O_FDCqr_decomp_ctl_),.p_desc1265_p_O_FDP(p_desc1265_p_O_FDPqr_decomp_ctl_),.p_desc1268_p_O_FDP(p_desc1268_p_O_FDPqr_decomp_ctl_),.p_desc1280_p_O_FDP(p_desc1280_p_O_FDPqr_decomp_ctl_),.p_desc1263_p_O_FDCE(p_desc1263_p_O_FDCEqr_decomp_ctl_),.p_desc1264_p_O_FDCE(p_desc1264_p_O_FDCEqr_decomp_ctl_),.p_desc1266_p_O_FDCE(p_desc1266_p_O_FDCEqr_decomp_ctl_),.p_desc1267_p_O_FDCE(p_desc1267_p_O_FDCEqr_decomp_ctl_),.p_desc1269_p_O_FDCE(p_desc1269_p_O_FDCEqr_decomp_ctl_),.p_desc1270_p_O_FDCE(p_desc1270_p_O_FDCEqr_decomp_ctl_),.p_desc1271_p_O_FDCE(p_desc1271_p_O_FDCEqr_decomp_ctl_),.p_desc1272_p_O_FDCE(p_desc1272_p_O_FDCEqr_decomp_ctl_),.p_desc1273_p_O_FDCE(p_desc1273_p_O_FDCEqr_decomp_ctl_));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module qr_decomp_ctl_inj (col_sel_AQ_int,col_sel_AQ2_int,row_sel_AQ,state_5,state_8,state_3,in_b_inner_prod_sel,w_col_sel_AQ_int,col_sel_R_int,row_sel_R,in_a_inner_prod_sel,vec_in_AQ_sel,single_in_R_sel,single_in_R_sel_0,wr_en_AQ_sel,wr_en_AQ_sel_0,in_b_vec_mult_sel,red_mat_reg,rst,done_inv_sqrt,N_512_i,done_inner_prod,start_inv_sqrt,clk,start_inner_prod,wr_en_AQ_int,wr_en_R,w_in_a_vec_sub,done_QR,start_QR,red_mat_reg_0,p_desc1255_p_O_FDC,p_desc1256_p_O_FDC,p_desc1257_p_O_FDC,p_desc1258_p_O_FDC,p_start_inner_prod_Z_p_O_FDC,p_wr_en_AQ_int_Z_p_O_FDC,p_wr_en_R_Z_p_O_FDC,p_w_in_a_vec_sub_Z_p_O_FDC,p_start_inv_sqrt_Z_p_O_FDC,p_desc1274_p_O_FDC,p_pre_red_mat_reg_Z_p_O_FDC,p_done_Z_p_O_FDC,p_desc1275_p_O_FDC,p_desc1276_p_O_FDC,p_desc1277_p_O_FDC,p_desc1278_p_O_FDC,p_desc1279_p_O_FDC,p_desc1281_p_O_FDC,p_desc1282_p_O_FDC,p_desc1283_p_O_FDC,p_desc1284_p_O_FDC,p_desc1285_p_O_FDC,p_desc1286_p_O_FDC,p_desc1287_p_O_FDC,p_desc1288_p_O_FDC,p_desc1265_p_O_FDP,p_desc1268_p_O_FDP,p_desc1280_p_O_FDP,p_desc1263_p_O_FDCE,p_desc1264_p_O_FDCE,p_desc1266_p_O_FDCE,p_desc1267_p_O_FDCE,p_desc1269_p_O_FDCE,p_desc1270_p_O_FDCE,p_desc1271_p_O_FDCE,p_desc1272_p_O_FDCE,p_desc1273_p_O_FDCE);
output [1:0] col_sel_AQ_int ;
output [1:0] col_sel_AQ2_int ;
output [1:0] row_sel_AQ ;
output state_5 ;
output state_8 ;
output state_3 ;
output in_b_inner_prod_sel ;
output [1:0] w_col_sel_AQ_int ;
output [1:0] col_sel_R_int ;
output [1:0] row_sel_R ;
output in_a_inner_prod_sel ;
output [1:0] vec_in_AQ_sel ;
output single_in_R_sel ;
input single_in_R_sel_0 ;
output wr_en_AQ_sel ;
input wr_en_AQ_sel_0 ;
output in_b_vec_mult_sel ;
output red_mat_reg ;
input rst ;
input done_inv_sqrt ;
output N_512_i ;
input done_inner_prod ;
output start_inv_sqrt ;
input clk ;
output start_inner_prod ;
output wr_en_AQ_int ;
output wr_en_R ;
output w_in_a_vec_sub ;
output done_QR ;
input start_QR ;
input red_mat_reg_0 ;
wire state_5 ;
wire state_8 ;
wire state_3 ;
wire red_mat_reg ;
wire rst ;
wire done_inv_sqrt ;
wire N_512_i ;
wire done_inner_prod ;
wire start_inv_sqrt ;
wire clk ;
wire start_inner_prod ;
wire wr_en_AQ_int ;
wire wr_en_R ;
wire w_in_a_vec_sub ;
wire done_QR ;
wire start_QR ;
wire red_mat_reg_0 ;
wire [7:0] state ;
wire [2:0] mult_counter ;
wire [5:5] state_ns_2_tz ;
wire [7:1] state_ns ;
wire in_b_inner_prod_sel_0 ;
wire [1:0] w_col_sel_AQ_int_4_i_m2_i_m3 ;
wire [1:0] col_sel_R_int_4_i_m2_i_m3 ;
wire in_a_inner_prod_sel_0 ;
wire [1:1] j_RNO ;
wire VCC ;
wire N_676 ;
wire N_210_i ;
wire N_526 ;
wire row_sel_R_0_sqmuxa ;
wire row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_O5 ;
wire N_662 ;
wire N_201_2 ;
wire N_706 ;
wire N_686 ;
wire N_495 ;
wire N_503 ;
wire N_652 ;
wire un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_O6 ;
wire un1_state_10_0_o6_0_o2_lut6_2_O6 ;
wire N_653 ;
wire start_inv_sqrt_0 ;
wire un1_state_23_0_0_o2_lut6_2_O6 ;
wire N_513_i ;
wire N_218_i ;
wire un1_state_33_0_0 ;
wire N_220_i ;
wire start_inner_prod_0 ;
wire wr_en_AQ_int_0 ;
wire un1_state_29_0_0 ;
wire N_514_i ;
wire wr_en_R_0 ;
wire w_in_a_vec_sub_0 ;
wire pre_red_mat_reg ;
wire done ;
wire N_214_i ;
wire N_216_i ;
wire N_231_i ;
wire N_201_i ;
wire N_196_3 ;
wire N_106_1 ;
wire N_527 ;
wire N_106_2 ;
wire N_123 ;
wire N_122 ;
wire N_121 ;
wire N_120 ;
wire N_119 ;
wire N_118 ;
wire N_117 ;
wire N_116 ;
wire N_115 ;
wire GND ;
input p_desc1255_p_O_FDC ;
input p_desc1256_p_O_FDC ;
input p_desc1257_p_O_FDC ;
input p_desc1258_p_O_FDC ;
input p_start_inner_prod_Z_p_O_FDC ;
input p_wr_en_AQ_int_Z_p_O_FDC ;
input p_wr_en_R_Z_p_O_FDC ;
input p_w_in_a_vec_sub_Z_p_O_FDC ;
input p_start_inv_sqrt_Z_p_O_FDC ;
input p_desc1274_p_O_FDC ;
input p_pre_red_mat_reg_Z_p_O_FDC ;
input p_done_Z_p_O_FDC ;
input p_desc1275_p_O_FDC ;
input p_desc1276_p_O_FDC ;
input p_desc1277_p_O_FDC ;
input p_desc1278_p_O_FDC ;
input p_desc1279_p_O_FDC ;
input p_desc1281_p_O_FDC ;
input p_desc1282_p_O_FDC ;
input p_desc1283_p_O_FDC ;
input p_desc1284_p_O_FDC ;
input p_desc1285_p_O_FDC ;
input p_desc1286_p_O_FDC ;
input p_desc1287_p_O_FDC ;
input p_desc1288_p_O_FDC ;
input p_desc1265_p_O_FDP ;
input p_desc1268_p_O_FDP ;
input p_desc1280_p_O_FDP ;
input p_desc1263_p_O_FDCE ;
input p_desc1264_p_O_FDCE ;
input p_desc1266_p_O_FDCE ;
input p_desc1267_p_O_FDCE ;
input p_desc1269_p_O_FDCE ;
input p_desc1270_p_O_FDCE ;
input p_desc1271_p_O_FDCE ;
input p_desc1272_p_O_FDCE ;
input p_desc1273_p_O_FDCE ;
// instances
p_O_FDC desc1255(.Q(w_col_sel_AQ_int[1:1]),.D(w_col_sel_AQ_int_4_i_m2_i_m3[1:1]),.C(clk),.CLR(rst),.E(p_desc1255_p_O_FDC));
p_O_FDC desc1256(.Q(w_col_sel_AQ_int[0:0]),.D(w_col_sel_AQ_int_4_i_m2_i_m3[0:0]),.C(clk),.CLR(rst),.E(p_desc1256_p_O_FDC));
p_O_FDC desc1257(.Q(col_sel_R_int[1:1]),.D(col_sel_R_int_4_i_m2_i_m3[1:1]),.C(clk),.CLR(rst),.E(p_desc1257_p_O_FDC));
p_O_FDC desc1258(.Q(col_sel_R_int[0:0]),.D(col_sel_R_int_4_i_m2_i_m3[0:0]),.C(clk),.CLR(rst),.E(p_desc1258_p_O_FDC));
LUT5 desc1259(.I0(col_sel_AQ2_int[0:0]),.I1(state[7:7]),.I2(col_sel_AQ_int[0:0]),.I3(w_col_sel_AQ_int[0:0]),.I4(un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_O6),.O(w_col_sel_AQ_int_4_i_m2_i_m3[0:0]));
defparam desc1259.INIT=32'hE2E2FF00;
LUT5 desc1260(.I0(col_sel_AQ2_int[1:1]),.I1(state[7:7]),.I2(col_sel_AQ_int[1:1]),.I3(w_col_sel_AQ_int[1:1]),.I4(un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_O6),.O(w_col_sel_AQ_int_4_i_m2_i_m3[1:1]));
defparam desc1260.INIT=32'hE2E2FF00;
LUT5 desc1261(.I0(col_sel_AQ2_int[0:0]),.I1(state_5),.I2(col_sel_AQ_int[0:0]),.I3(col_sel_R_int[0:0]),.I4(un1_state_23_0_0_o2_lut6_2_O6),.O(col_sel_R_int_4_i_m2_i_m3[0:0]));
defparam desc1261.INIT=32'hE2E2FF00;
LUT5 desc1262(.I0(col_sel_AQ2_int[1:1]),.I1(state_5),.I2(col_sel_AQ_int[1:1]),.I3(col_sel_R_int[1:1]),.I4(un1_state_23_0_0_o2_lut6_2_O6),.O(col_sel_R_int_4_i_m2_i_m3[1:1]));
defparam desc1262.INIT=32'hE2E2FF00;
p_O_FDCE desc1263(.Q(row_sel_R[0:0]),.D(col_sel_AQ_int[0:0]),.C(clk),.CLR(rst),.CE(row_sel_R_0_sqmuxa),.E(p_desc1263_p_O_FDCE));
p_O_FDCE desc1264(.Q(row_sel_R[1:1]),.D(col_sel_AQ_int[1:1]),.C(clk),.CLR(rst),.CE(row_sel_R_0_sqmuxa),.E(p_desc1264_p_O_FDCE));
p_O_FDP desc1265(.Q(in_b_inner_prod_sel),.D(in_b_inner_prod_sel_0),.C(clk),.PRE(rst),.E(p_desc1265_p_O_FDP));
p_O_FDCE desc1266(.Q(row_sel_AQ[0:0]),.D(N_218_i),.C(clk),.CLR(rst),.CE(un1_state_33_0_0),.E(p_desc1266_p_O_FDCE));
p_O_FDCE desc1267(.Q(row_sel_AQ[1:1]),.D(N_220_i),.C(clk),.CLR(rst),.CE(un1_state_33_0_0),.E(p_desc1267_p_O_FDCE));
p_O_FDC start_inner_prod_Z(.Q(start_inner_prod),.D(start_inner_prod_0),.C(clk),.CLR(rst),.E(p_start_inner_prod_Z_p_O_FDC));
p_O_FDP desc1268(.Q(in_a_inner_prod_sel),.D(in_a_inner_prod_sel_0),.C(clk),.PRE(rst),.E(p_desc1268_p_O_FDP));
p_O_FDC wr_en_AQ_int_Z(.Q(wr_en_AQ_int),.D(wr_en_AQ_int_0),.C(clk),.CLR(rst),.E(p_wr_en_AQ_int_Z_p_O_FDC));
p_O_FDCE desc1269(.Q(mult_counter[0:0]),.D(un1_state_23_0_0_o2_lut6_2_O6),.C(clk),.CLR(rst),.CE(un1_state_29_0_0),.E(p_desc1269_p_O_FDCE));
p_O_FDCE desc1270(.Q(mult_counter[1:1]),.D(N_513_i),.C(clk),.CLR(rst),.CE(un1_state_29_0_0),.E(p_desc1270_p_O_FDCE));
p_O_FDCE desc1271(.Q(mult_counter[2:2]),.D(N_514_i),.C(clk),.CLR(rst),.CE(un1_state_29_0_0),.E(p_desc1271_p_O_FDCE));
p_O_FDC wr_en_R_Z(.Q(wr_en_R),.D(wr_en_R_0),.C(clk),.CLR(rst),.E(p_wr_en_R_Z_p_O_FDC));
p_O_FDCE desc1272(.Q(vec_in_AQ_sel[0:0]),.D(state_5),.C(clk),.CLR(rst),.CE(row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_O5),.E(p_desc1272_p_O_FDCE));
p_O_FDCE desc1273(.Q(vec_in_AQ_sel[1:1]),.D(state[2:2]),.C(clk),.CLR(rst),.CE(row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_O5),.E(p_desc1273_p_O_FDCE));
p_O_FDC w_in_a_vec_sub_Z(.Q(w_in_a_vec_sub),.D(w_in_a_vec_sub_0),.C(clk),.CLR(rst),.E(p_w_in_a_vec_sub_Z_p_O_FDC));
p_O_FDC start_inv_sqrt_Z(.Q(start_inv_sqrt),.D(start_inv_sqrt_0),.C(clk),.CLR(rst),.E(p_start_inv_sqrt_Z_p_O_FDC));
p_O_FDC desc1274(.Q(single_in_R_sel),.D(single_in_R_sel_0),.C(clk),.CLR(rst),.E(p_desc1274_p_O_FDC));
p_O_FDC pre_red_mat_reg_Z(.Q(red_mat_reg),.D(pre_red_mat_reg),.C(clk),.CLR(rst),.E(p_pre_red_mat_reg_Z_p_O_FDC));
p_O_FDC done_Z(.Q(done_QR),.D(done),.C(clk),.CLR(rst),.E(p_done_Z_p_O_FDC));
p_O_FDC desc1275(.Q(wr_en_AQ_sel),.D(wr_en_AQ_sel_0),.C(clk),.CLR(rst),.E(p_desc1275_p_O_FDC));
p_O_FDC desc1276(.Q(col_sel_AQ_int[0:0]),.D(N_214_i),.C(clk),.CLR(rst),.E(p_desc1276_p_O_FDC));
p_O_FDC desc1277(.Q(col_sel_AQ_int[1:1]),.D(N_216_i),.C(clk),.CLR(rst),.E(p_desc1277_p_O_FDC));
p_O_FDC desc1278(.Q(col_sel_AQ2_int[0:0]),.D(N_231_i),.C(clk),.CLR(rst),.E(p_desc1278_p_O_FDC));
p_O_FDC desc1279(.Q(col_sel_AQ2_int[1:1]),.D(j_RNO[1:1]),.C(clk),.CLR(rst),.E(p_desc1279_p_O_FDC));
p_O_FDP desc1280(.Q(state_8),.D(N_201_i),.C(clk),.PRE(rst),.E(p_desc1280_p_O_FDP));
p_O_FDC desc1281(.Q(state[7:7]),.D(state_ns[1:1]),.C(clk),.CLR(rst),.E(p_desc1281_p_O_FDC));
p_O_FDC desc1282(.Q(state[6:6]),.D(state_ns[2:2]),.C(clk),.CLR(rst),.E(p_desc1282_p_O_FDC));
p_O_FDC desc1283(.Q(state_5),.D(state_ns[3:3]),.C(clk),.CLR(rst),.E(p_desc1283_p_O_FDC));
p_O_FDC desc1284(.Q(state[4:4]),.D(state_ns[4:4]),.C(clk),.CLR(rst),.E(p_desc1284_p_O_FDC));
p_O_FDC desc1285(.Q(state_3),.D(state_ns[5:5]),.C(clk),.CLR(rst),.E(p_desc1285_p_O_FDC));
p_O_FDC desc1286(.Q(state[2:2]),.D(state_ns[6:6]),.C(clk),.CLR(rst),.E(p_desc1286_p_O_FDC));
p_O_FDC desc1287(.Q(state[1:1]),.D(state_ns[7:7]),.C(clk),.CLR(rst),.E(p_desc1287_p_O_FDC));
p_O_FDC desc1288(.Q(state[0:0]),.D(N_210_i),.C(clk),.CLR(rst),.E(p_desc1288_p_O_FDC));
FDPE desc1289(.Q(in_b_vec_mult_sel),.D(row_sel_R_0_sqmuxa),.C(clk),.PRE(rst),.CE(un1_state_23_0_0_o2_lut6_2_O6));
LUT6 un1_state_29_0_0_cZ(.I0(done_inner_prod),.I1(state[1:1]),.I2(state[2:2]),.I3(state[4:4]),.I4(state_5),.I5(done_inv_sqrt),.O(un1_state_29_0_0));
defparam un1_state_29_0_0_cZ.INIT=64'hFFFFFFECFFECFFEC;
LUT5_L desc1290(.I0(mult_counter[1:1]),.I1(done_inner_prod),.I2(state[2:2]),.I3(state_5),.I4(done_inv_sqrt),.LO(N_514_i));
defparam desc1290.INIT=32'h002A2A2A;
LUT6_L desc1291(.I0(state_3),.I1(state[1:1]),.I2(mult_counter[2:2]),.I3(state_ns_2_tz[5:5]),.I4(N_526),.I5(N_676),.LO(state_ns[5:5]));
defparam desc1291.INIT=64'hFFFFFFFFEAAAC000;
LUT6_L desc1292(.I0(start_QR),.I1(state[1:1]),.I2(mult_counter[2:2]),.I3(state_8),.I4(row_sel_AQ[0:0]),.I5(N_676),.LO(N_218_i));
defparam desc1292.INIT=64'h000000000000153F;
LUT6_L desc1293(.I0(state_3),.I1(state[7:7]),.I2(state_8),.I3(in_a_inner_prod_sel),.I4(N_676),.I5(N_652),.LO(in_a_inner_prod_sel_0));
defparam desc1293.INIT=64'hFEFEFEFEFEFEFFEE;
LUT6 un1_state_33_0_0_cZ(.I0(state_3),.I1(start_QR),.I2(state[7:7]),.I3(state_8),.I4(N_706),.I5(N_676),.O(un1_state_33_0_0));
defparam un1_state_33_0_0_cZ.INIT=64'hFFFFFFFFFFFFFEFA;
LUT6_L un1_state_28_i_0_3(.I0(state[7:7]),.I1(done_inner_prod),.I2(state[2:2]),.I3(state_5),.I4(state_8),.I5(N_662),.LO(N_196_3));
defparam un1_state_28_i_0_3.INIT=64'hFFFFFFFFFFFFFFBA;
LUT6_L desc1294(.I0(state[6:6]),.I1(state[7:7]),.I2(done_inner_prod),.I3(red_mat_reg),.I4(row_sel_AQ[1:1]),.I5(row_sel_AQ[0:0]),.LO(state_ns[2:2]));
defparam desc1294.INIT=64'hCECECE0A0A0A0A0A;
LUT6_L desc1295(.I0(state_3),.I1(done_inner_prod),.I2(state[2:2]),.I3(red_mat_reg),.I4(row_sel_AQ[1:1]),.I5(row_sel_AQ[0:0]),.LO(state_ns[6:6]));
defparam desc1295.INIT=64'hBABABA3030303030;
LUT6 desc1296(.I0(col_sel_AQ2_int[0:0]),.I1(state[1:1]),.I2(state[4:4]),.I3(mult_counter[2:2]),.I4(col_sel_AQ_int[1:1]),.I5(col_sel_AQ_int[0:0]),.O(N_106_1));
defparam desc1296.INIT=64'h00008800F8000000;
LUT4_L w_in_a_vec_sub_e(.I0(done_inner_prod),.I1(state[1:1]),.I2(state[2:2]),.I3(w_in_a_vec_sub),.LO(w_in_a_vec_sub_0));
defparam w_in_a_vec_sub_e.INIT=16'hB3A0;
LUT6_L desc1297(.I0(col_sel_AQ2_int[1:1]),.I1(red_mat_reg),.I2(mult_counter[2:2]),.I3(state_8),.I4(col_sel_AQ_int[0:0]),.I5(N_495),.LO(N_214_i));
defparam desc1297.INIT=64'h00FF0000001F00E0;
LUT4_L desc1298(.I0(state[6:6]),.I1(done_inner_prod),.I2(state_5),.I3(done_inv_sqrt),.LO(state_ns[3:3]));
defparam desc1298.INIT=16'h88F8;
LUT4_L pre_red_mat_reg_e(.I0(red_mat_reg_0),.I1(start_QR),.I2(red_mat_reg),.I3(state_8),.LO(pre_red_mat_reg));
defparam pre_red_mat_reg_e.INIT=16'hB8F0;
LUT3_L done_e(.I0(done_QR),.I1(state[0:0]),.I2(state_8),.LO(done));
defparam done_e.INIT=8'hCE;
LUT6 un1_state_1_sqmuxa_3_0_o2_0(.I0(col_sel_AQ2_int[1:1]),.I1(red_mat_reg),.I2(mult_counter[2:2]),.I3(state_8),.I4(col_sel_AQ_int[1:1]),.I5(N_495),.O(N_652));
defparam un1_state_1_sqmuxa_3_0_o2_0.INIT=64'hFF00FF00FFE0FFC0;
LUT6 desc1299(.I0(col_sel_AQ2_int[1:1]),.I1(state[4:4]),.I2(red_mat_reg),.I3(col_sel_AQ_int[1:1]),.I4(col_sel_AQ_int[0:0]),.I5(N_495),.O(N_527));
defparam desc1299.INIT=64'h000C0000050D0505;
LUT5_L desc1300(.I0(start_QR),.I1(state[7:7]),.I2(state_8),.I3(N_526),.I4(N_503),.LO(state_ns[1:1]));
defparam desc1300.INIT=32'hECA0FFFF;
LUT6_L desc1301(.I0(state[0:0]),.I1(state[6:6]),.I2(start_QR),.I3(state[2:2]),.I4(state_5),.I5(N_201_2),.LO(N_201_i));
defparam desc1301.INIT=64'h0000000000000023;
LUT6_L wr_en_AQ_int_e(.I0(wr_en_AQ_int),.I1(state[6:6]),.I2(state[2:2]),.I3(mult_counter[2:2]),.I4(un1_state_10_0_o6_0_o2_lut6_2_O6),.I5(N_653),.LO(wr_en_AQ_int_0));
defparam wr_en_AQ_int_e.INIT=64'hAAAAAAAAABAAA8A8;
LUT5_L wr_en_R_e(.I0(state[6:6]),.I1(wr_en_R),.I2(state[2:2]),.I3(state[4:4]),.I4(N_196_3),.LO(wr_en_R_0));
defparam wr_en_R_e.INIT=32'hCCCCDDD8;
LUT6_L desc1302(.I0(col_sel_AQ2_int[1:1]),.I1(state[1:1]),.I2(mult_counter[2:2]),.I3(state_8),.I4(col_sel_AQ_int[0:0]),.I5(N_527),.LO(N_106_2));
defparam desc1302.INIT=64'hF0FAF0FA002A000A;
LUT4_L desc1303(.I0(state_8),.I1(col_sel_AQ_int[1:1]),.I2(col_sel_AQ_int[0:0]),.I3(N_503),.LO(N_216_i));
defparam desc1303.INIT=16'h4414;
LUT6_L desc1304(.I0(start_QR),.I1(state_8),.I2(row_sel_AQ[1:1]),.I3(row_sel_AQ[0:0]),.I4(N_706),.I5(N_676),.LO(N_220_i));
defparam desc1304.INIT=64'h0000000000000770;
LUT6_L start_inner_prod_e(.I0(start_QR),.I1(state_8),.I2(start_inner_prod),.I3(un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_O6),.I4(N_706),.I5(N_676),.LO(start_inner_prod_0));
defparam start_inner_prod_e.INIT=64'hFFFFFFFFFFFF88B8;
LUT6_L desc1305(.I0(col_sel_AQ2_int[1:1]),.I1(state[4:4]),.I2(state_8),.I3(N_495),.I4(N_106_1),.I5(N_106_2),.LO(j_RNO[1:1]));
defparam desc1305.INIT=64'hFFFFFFFFFFFF0200;
LUT6_L desc1306(.I0(mult_counter[2:2]),.I1(state_8),.I2(col_sel_AQ_int[0:0]),.I3(N_495),.I4(N_686),.I5(N_527),.LO(N_231_i));
defparam desc1306.INIT=64'h0000111100003313;
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT4 un1_state_23_0_0_o2_lut6_2_o6(.I0(done_inner_prod),.I1(state[2:2]),.I2(state_5),.I3(done_inv_sqrt),.O(un1_state_23_0_0_o2_lut6_2_O6));
defparam un1_state_23_0_0_o2_lut6_2_o6.INIT=16'hF888;
LUT5 un1_state_23_0_0_o2_lut6_2_o5(.I0(mult_counter[0:0]),.I1(done_inner_prod),.I2(state[2:2]),.I3(state_5),.I4(done_inv_sqrt),.O(N_513_i));
defparam un1_state_23_0_0_o2_lut6_2_o5.INIT=32'h002A2A2A;
LUT2 un1_state_25_0_0_o2_lut6_2_o6(.I0(state_5),.I1(state_8),.O(N_653));
defparam un1_state_25_0_0_o2_lut6_2_o6.INIT=4'hE;
LUT5 un1_state_25_0_0_o2_lut6_2_o5(.I0(state[6:6]),.I1(done_inner_prod),.I2(state_5),.I3(start_inv_sqrt),.I4(state_8),.O(start_inv_sqrt_0));
defparam un1_state_25_0_0_o2_lut6_2_o5.INIT=32'hAAAAAFA8;
LUT2 un1_state_10_0_o6_0_o2_lut6_2_o6(.I0(state[1:1]),.I1(state[4:4]),.O(un1_state_10_0_o6_0_o2_lut6_2_O6));
defparam un1_state_10_0_o6_0_o2_lut6_2_o6.INIT=4'hE;
LUT4 un1_state_10_0_o6_0_o2_lut6_2_o5(.I0(state[1:1]),.I1(done_inner_prod),.I2(state[2:2]),.I3(mult_counter[2:2]),.O(state_ns[7:7]));
defparam un1_state_10_0_o6_0_o2_lut6_2_o5.INIT=16'hC0EA;
LUT2 un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_o6(.I0(state_3),.I1(state[7:7]),.O(un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_O6));
defparam un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_o6.INIT=4'hE;
LUT5 un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_o5(.I0(state_3),.I1(state[7:7]),.I2(state_8),.I3(in_b_inner_prod_sel),.I4(N_652),.O(in_b_inner_prod_sel_0));
defparam un1_state_1_sqmuxa_3_0_o6_0_o2_lut6_2_o5.INIT=32'hFEFEFFEE;
LUT2 desc1307(.I0(col_sel_AQ2_int[0:0]),.I1(state[1:1]),.O(N_495));
defparam desc1307.INIT=4'h7;
LUT5 desc1308(.I0(col_sel_AQ2_int[0:0]),.I1(col_sel_AQ2_int[1:1]),.I2(state[1:1]),.I3(red_mat_reg),.I4(mult_counter[2:2]),.O(N_503));
defparam desc1308.INIT=32'h5F7FFFFF;
LUT2 un1_state_1_sqmuxa_4_0_0_a3_lut6_2_o6(.I0(state[1:1]),.I1(mult_counter[2:2]),.O(N_706));
defparam un1_state_1_sqmuxa_4_0_0_a3_lut6_2_o6.INIT=4'h8;
LUT5 un1_state_1_sqmuxa_4_0_0_a3_lut6_2_o5(.I0(col_sel_AQ2_int[0:0]),.I1(state[1:1]),.I2(state[4:4]),.I3(mult_counter[2:2]),.I4(col_sel_AQ_int[0:0]),.O(N_686));
defparam un1_state_1_sqmuxa_4_0_0_a3_lut6_2_o5.INIT=32'h11550155;
LUT2 desc1309(.I0(state[4:4]),.I1(mult_counter[2:2]),.O(N_662));
defparam desc1309.INIT=4'h2;
LUT4 desc1310(.I0(state_3),.I1(state[7:7]),.I2(state[4:4]),.I3(state[1:1]),.O(N_201_2));
defparam desc1310.INIT=16'hFFFE;
LUT2 row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_o6(.I0(state_5),.I1(done_inv_sqrt),.O(row_sel_R_0_sqmuxa));
defparam row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_o6.INIT=4'h8;
LUT5 row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_o5(.I0(done_inner_prod),.I1(state[2:2]),.I2(state_5),.I3(state_8),.I4(done_inv_sqrt),.O(row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_O5));
defparam row_sel_R_0_sqmuxa_0_a6_0_a2_lut6_2_o5.INIT=32'hFFF8FF88;
LUT2 desc1311(.I0(rst),.I1(state[4:4]),.O(N_512_i));
defparam desc1311.INIT=4'h4;
LUT4 desc1312(.I0(state[4:4]),.I1(mult_counter[2:2]),.I2(state_5),.I3(done_inv_sqrt),.O(state_ns[4:4]));
defparam desc1312.INIT=16'hF222;
LUT3 desc1313(.I0(red_mat_reg),.I1(row_sel_AQ[1:1]),.I2(row_sel_AQ[0:0]),.O(N_526));
defparam desc1313.INIT=8'h1F;
LUT3 desc1314(.I0(col_sel_AQ2_int[0:0]),.I1(col_sel_AQ2_int[1:1]),.I2(red_mat_reg),.O(state_ns_2_tz[5:5]));
defparam desc1314.INIT=8'h57;
LUT5 desc1315(.I0(state[4:4]),.I1(red_mat_reg),.I2(mult_counter[2:2]),.I3(col_sel_AQ_int[1:1]),.I4(col_sel_AQ_int[0:0]),.O(N_676));
defparam desc1315.INIT=32'h0020A0A0;
LUT5 desc1316(.I0(state[4:4]),.I1(red_mat_reg),.I2(mult_counter[2:2]),.I3(col_sel_AQ_int[1:1]),.I4(col_sel_AQ_int[0:0]),.O(N_210_i));
defparam desc1316.INIT=32'hA0800000;
endmodule
module qr_decomp_ctl_mux_inj (single_in_R_sel,single_in_R_sel_0,w_col_sel_AQ_int,col_sel_AQ,wr_en_AQ_sel,w_col_sel_AQ_mux_i_m3_lut6_2_O6,w_col_sel_AQ_mux_i_m3_lut6_2_O5,col_sel_AQ2_int,col_sel_AQ2_mux_i_m3_lut6_2_O6,col_sel_AQ2_mux_i_m3_lut6_2_O5,state_0,state_2,state_5,wr_en_AQ_sel_0,col_sel_R,col_sel_R_int,col_sel_R_mux_i_m3_lut6_2_O6,col_sel_R_mux_i_m3_lut6_2_O5,in_a_r_reg_0_0,in_a_r_reg_0_11,out_r_vec_sub_0,in_a_i_reg_1,vec_in_AQ_sel,in_a_r_reg_3,in_a_i_reg_0,in_a_i_reg_3,in_a_r_reg_1,pre_out_4,pre_out_0,in_a_r_reg_2,pre_out_5,pre_out_1,in_a_i_reg_2,pre_out_6,pre_out_3_9,pre_out_3_1,pre_out_3_7,pre_out_3_3,pre_out_3_8,pre_out_3_5,pre_out_3_6,pre_out_3_0,pre_out_2,out_inner_prod_i,pre_out_10,pre_out_9,pre_out_0_d0,pre_out_1_d0,pre_out_3_d0,pre_out_6_d0,pre_out_7,pre_out_8,pre_out_5_d0,pre_out_4_d0,pre_out_2_d0,pre_out_18,pre_out_19,pre_out_20,pre_out_21,pre_out_reg,out_r_vec_mult_2,vec_in_r_AQ_mux_2,out_r_vec_mult_1,vec_in_r_AQ_mux_1,pre_out_i_m,out_i_vec_mult_3,pre_out_i_m_1,vec_in_i_AQ_mux_3,output_iv,out_i_vec_mult_0,vec_in_i_AQ_mux_0_11,vec_in_i_AQ_mux_0_1,vec_in_i_AQ_mux_0_5,vec_in_i_AQ_mux_0_0,vec_in_i_AQ_mux_0_8,vec_in_i_AQ_mux_0_10,vec_in_i_AQ_mux_0_7,vec_in_i_AQ_mux_0_6,vec_in_i_AQ_mux_0_9,vec_in_i_AQ_mux_0_4,out_r_vec_mult_0,output_iv_0_2,output_iv_0_4,output_iv_0_1,output_iv_0_0,output_iv_0_9,output_iv_0_6,output_iv_0_8,output_iv_0_3,output_iv_0_7,vec_in_r_AQ_mux_0_10,vec_in_r_AQ_mux_0_2,vec_in_r_AQ_mux_0_4,vec_in_r_AQ_mux_0_3,vec_in_r_AQ_mux_0_6,vec_in_r_AQ_mux_0_1,vec_in_r_AQ_mux_0_9,vec_in_r_AQ_mux_0_8,vec_in_r_AQ_mux_0_0,vec_in_r_AQ_mux_0_7,pre_out_i_m_0_0,pre_out_i_m_0_6,pre_out_i_m_0_4,pre_out_i_m_0_1,in_A_r,out_r_vec_mult_3,pre_out_i_m_2,vec_in_r_AQ_mux_3,out_i_vec_mult_2,pre_out_i_m_3,vec_in_i_AQ_mux_2,in_A_i,out_i_vec_mult_1,pre_out_i_m_4,vec_in_i_AQ_mux_1,un8_rnd_out_P,single_in_r_R_mux,out_inner_prod_r,un8_rnd_out,N_390_i,N_393_i,done_inv_sqrt,N_391_i,N_394_i,N_396_i,N_395_i,N_397_i,N_398_i,N_400_i,N_399_i,N_401_i,wr_en_AQ_int,wr_A_QR,start_QR,wr_en_AQ_mux_i_m3_lut6_2_O6,N_501,N_392_i,PATTERNDETECT_32,N_500,N_508,N_507,N_506,N_505,un5_output,un5_output_0,un5_output_1,un5_output_2,un5_output_3,un5_output_4,N_389_i,N_388_i,N_387_i,N_386_i,N_385_i,N_384_i,N_383_i,N_34_i,N_32_i,N_30_i,N_28_i);
input single_in_R_sel ;
output single_in_R_sel_0 ;
input [1:0] w_col_sel_AQ_int ;
input [1:0] col_sel_AQ ;
input wr_en_AQ_sel ;
output w_col_sel_AQ_mux_i_m3_lut6_2_O6 ;
output w_col_sel_AQ_mux_i_m3_lut6_2_O5 ;
input [1:0] col_sel_AQ2_int ;
output col_sel_AQ2_mux_i_m3_lut6_2_O6 ;
output col_sel_AQ2_mux_i_m3_lut6_2_O5 ;
input state_0 ;
input state_2 ;
input state_5 ;
output wr_en_AQ_sel_0 ;
input [1:0] col_sel_R ;
input [1:0] col_sel_R_int ;
output col_sel_R_mux_i_m3_lut6_2_O6 ;
output col_sel_R_mux_i_m3_lut6_2_O5 ;
input in_a_r_reg_0_0 ;
input in_a_r_reg_0_11 ;
output [11:11] out_r_vec_sub_0 ;
input [11:11] in_a_i_reg_1 ;
input [1:0] vec_in_AQ_sel ;
input [11:11] in_a_r_reg_3 ;
input [11:11] in_a_i_reg_0 ;
input [11:11] in_a_i_reg_3 ;
input [11:11] in_a_r_reg_1 ;
input [11:11] pre_out_4 ;
input [11:1] pre_out_0 ;
input [11:11] in_a_r_reg_2 ;
input [11:11] pre_out_5 ;
input [11:1] pre_out_1 ;
input [11:11] in_a_i_reg_2 ;
input [11:11] pre_out_6 ;
input pre_out_3_9 ;
input pre_out_3_1 ;
input pre_out_3_7 ;
input pre_out_3_3 ;
input pre_out_3_8 ;
input pre_out_3_5 ;
input pre_out_3_6 ;
input pre_out_3_0 ;
input [11:1] pre_out_2 ;
input [11:0] out_inner_prod_i ;
input pre_out_10 ;
input pre_out_9 ;
input pre_out_0_d0 ;
input pre_out_1_d0 ;
input pre_out_3_d0 ;
input pre_out_6_d0 ;
input pre_out_7 ;
input pre_out_8 ;
input pre_out_5_d0 ;
input pre_out_4_d0 ;
input pre_out_2_d0 ;
input pre_out_18 ;
input pre_out_19 ;
input pre_out_20 ;
input pre_out_21 ;
input [23:23] pre_out_reg ;
input [11:0] out_r_vec_mult_2 ;
output [11:0] vec_in_r_AQ_mux_2 ;
input [11:0] out_r_vec_mult_1 ;
output [11:0] vec_in_r_AQ_mux_1 ;
input [10:0] pre_out_i_m ;
input [11:0] out_i_vec_mult_3 ;
input pre_out_i_m_1 ;
output [11:0] vec_in_i_AQ_mux_3 ;
input [10:0] output_iv ;
input [11:0] out_i_vec_mult_0 ;
output vec_in_i_AQ_mux_0_11 ;
output vec_in_i_AQ_mux_0_1 ;
output vec_in_i_AQ_mux_0_5 ;
output vec_in_i_AQ_mux_0_0 ;
output vec_in_i_AQ_mux_0_8 ;
output vec_in_i_AQ_mux_0_10 ;
output vec_in_i_AQ_mux_0_7 ;
output vec_in_i_AQ_mux_0_6 ;
output vec_in_i_AQ_mux_0_9 ;
output vec_in_i_AQ_mux_0_4 ;
input [11:0] out_r_vec_mult_0 ;
input output_iv_0_2 ;
input output_iv_0_4 ;
input output_iv_0_1 ;
input output_iv_0_0 ;
input output_iv_0_9 ;
input output_iv_0_6 ;
input output_iv_0_8 ;
input output_iv_0_3 ;
input output_iv_0_7 ;
output vec_in_r_AQ_mux_0_10 ;
output vec_in_r_AQ_mux_0_2 ;
output vec_in_r_AQ_mux_0_4 ;
output vec_in_r_AQ_mux_0_3 ;
output vec_in_r_AQ_mux_0_6 ;
output vec_in_r_AQ_mux_0_1 ;
output vec_in_r_AQ_mux_0_9 ;
output vec_in_r_AQ_mux_0_8 ;
output vec_in_r_AQ_mux_0_0 ;
output vec_in_r_AQ_mux_0_7 ;
input pre_out_i_m_0_0 ;
input pre_out_i_m_0_6 ;
input pre_out_i_m_0_4 ;
input pre_out_i_m_0_1 ;
input [47:0] in_A_r ;
input [11:0] out_r_vec_mult_3 ;
input pre_out_i_m_2 ;
output [11:0] vec_in_r_AQ_mux_3 ;
input [11:0] out_i_vec_mult_2 ;
input pre_out_i_m_3 ;
output [11:0] vec_in_i_AQ_mux_2 ;
input [47:0] in_A_i ;
input [11:0] out_i_vec_mult_1 ;
input pre_out_i_m_4 ;
output [11:0] vec_in_i_AQ_mux_1 ;
input [19:19] un8_rnd_out_P ;
output [11:11] single_in_r_R_mux ;
input [11:0] out_inner_prod_r ;
input [10:0] un8_rnd_out ;
output N_390_i ;
output N_393_i ;
input done_inv_sqrt ;
output N_391_i ;
output N_394_i ;
output N_396_i ;
output N_395_i ;
output N_397_i ;
output N_398_i ;
output N_400_i ;
output N_399_i ;
output N_401_i ;
input wr_en_AQ_int ;
input wr_A_QR ;
input start_QR ;
output wr_en_AQ_mux_i_m3_lut6_2_O6 ;
output N_501 ;
output N_392_i ;
input PATTERNDETECT_32 ;
input N_500 ;
output N_508 ;
output N_507 ;
output N_506 ;
output N_505 ;
input un5_output ;
input un5_output_0 ;
input un5_output_1 ;
input un5_output_2 ;
input un5_output_3 ;
input un5_output_4 ;
output N_389_i ;
output N_388_i ;
output N_387_i ;
output N_386_i ;
output N_385_i ;
output N_384_i ;
output N_383_i ;
output N_34_i ;
output N_32_i ;
output N_30_i ;
output N_28_i ;
wire state_0 ;
wire state_2 ;
wire state_5 ;
wire in_a_r_reg_0_0 ;
wire in_a_r_reg_0_11 ;
wire pre_out_3_9 ;
wire pre_out_3_1 ;
wire pre_out_3_7 ;
wire pre_out_3_3 ;
wire pre_out_3_8 ;
wire pre_out_3_5 ;
wire pre_out_3_6 ;
wire pre_out_3_0 ;
wire pre_out_10 ;
wire pre_out_9 ;
wire pre_out_0_d0 ;
wire pre_out_1_d0 ;
wire pre_out_3_d0 ;
wire pre_out_6_d0 ;
wire pre_out_7 ;
wire pre_out_8 ;
wire pre_out_5_d0 ;
wire pre_out_4_d0 ;
wire pre_out_2_d0 ;
wire pre_out_18 ;
wire pre_out_19 ;
wire pre_out_20 ;
wire pre_out_21 ;
wire vec_in_i_AQ_mux_0_11 ;
wire vec_in_i_AQ_mux_0_1 ;
wire vec_in_i_AQ_mux_0_5 ;
wire vec_in_i_AQ_mux_0_0 ;
wire vec_in_i_AQ_mux_0_8 ;
wire vec_in_i_AQ_mux_0_10 ;
wire vec_in_i_AQ_mux_0_7 ;
wire vec_in_i_AQ_mux_0_6 ;
wire vec_in_i_AQ_mux_0_9 ;
wire vec_in_i_AQ_mux_0_4 ;
wire output_iv_0_2 ;
wire output_iv_0_4 ;
wire output_iv_0_1 ;
wire output_iv_0_0 ;
wire output_iv_0_9 ;
wire output_iv_0_6 ;
wire output_iv_0_8 ;
wire output_iv_0_3 ;
wire output_iv_0_7 ;
wire vec_in_r_AQ_mux_0_10 ;
wire vec_in_r_AQ_mux_0_2 ;
wire vec_in_r_AQ_mux_0_4 ;
wire vec_in_r_AQ_mux_0_3 ;
wire vec_in_r_AQ_mux_0_6 ;
wire vec_in_r_AQ_mux_0_1 ;
wire vec_in_r_AQ_mux_0_9 ;
wire vec_in_r_AQ_mux_0_8 ;
wire vec_in_r_AQ_mux_0_0 ;
wire vec_in_r_AQ_mux_0_7 ;
wire pre_out_i_m_0_0 ;
wire pre_out_i_m_0_6 ;
wire pre_out_i_m_0_4 ;
wire pre_out_i_m_0_1 ;
wire N_390_i ;
wire N_393_i ;
wire done_inv_sqrt ;
wire N_391_i ;
wire N_394_i ;
wire N_396_i ;
wire N_395_i ;
wire N_397_i ;
wire N_398_i ;
wire N_400_i ;
wire N_399_i ;
wire N_401_i ;
wire wr_en_AQ_int ;
wire wr_A_QR ;
wire start_QR ;
wire wr_en_AQ_mux_i_m3_lut6_2_O6 ;
wire N_501 ;
wire N_392_i ;
wire PATTERNDETECT_32 ;
wire N_500 ;
wire N_508 ;
wire N_507 ;
wire N_506 ;
wire N_505 ;
wire un5_output ;
wire un5_output_0 ;
wire un5_output_1 ;
wire un5_output_2 ;
wire un5_output_3 ;
wire un5_output_4 ;
wire N_389_i ;
wire N_388_i ;
wire N_387_i ;
wire N_386_i ;
wire N_385_i ;
wire N_384_i ;
wire N_383_i ;
wire N_34_i ;
wire N_32_i ;
wire N_30_i ;
wire N_28_i ;
wire GND ;
wire VCC ;
wire N_161 ;
wire N_162 ;
wire N_163 ;
wire N_164 ;
wire N_165 ;
wire N_148 ;
wire N_166 ;
wire N_167 ;
wire N_168 ;
wire N_169 ;
wire N_149 ;
wire N_150 ;
wire N_151 ;
wire N_152 ;
wire N_153 ;
wire N_154 ;
wire N_155 ;
wire N_143 ;
wire N_156 ;
wire N_157 ;
wire N_37 ;
wire N_38 ;
wire N_39 ;
wire N_40 ;
wire N_41 ;
wire N_50 ;
wire N_60 ;
wire N_66 ;
wire N_61 ;
wire N_62 ;
wire N_64 ;
wire N_65 ;
wire N_68 ;
wire N_69 ;
wire N_48 ;
wire N_49 ;
wire N_51 ;
wire N_52 ;
wire N_54 ;
wire N_55 ;
wire N_56 ;
wire N_57 ;
wire N_42 ;
wire N_43 ;
wire N_44 ;
wire N_45 ;
wire N_160 ;
wire N_95 ;
wire N_122 ;
// instances
LUT6 desc1091(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_169),.I4(pre_out_9),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[10:10]));
defparam desc1091.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1092(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_160),.I4(pre_out_0_d0),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[1:1]));
defparam desc1092.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1093(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_161),.I4(pre_out_1_d0),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[2:2]));
defparam desc1093.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1094(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_163),.I4(pre_out_3_d0),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[4:4]));
defparam desc1094.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1095(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_166),.I4(pre_out_6_d0),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[7:7]));
defparam desc1095.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1096(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_167),.I4(pre_out_7),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[8:8]));
defparam desc1096.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1097(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_168),.I4(pre_out_8),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[9:9]));
defparam desc1097.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1098(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_165),.I4(pre_out_5_d0),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[6:6]));
defparam desc1098.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1099(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_164),.I4(pre_out_4_d0),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[5:5]));
defparam desc1099.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1100(.I0(out_i_vec_mult_1[11:11]),.I1(in_a_i_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_162),.I4(pre_out_2_d0),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[3:3]));
defparam desc1100.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1101(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_41),.I4(pre_out_0[6:6]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[6:6]));
defparam desc1101.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1102(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_44),.I4(pre_out_0[9:9]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[9:9]));
defparam desc1102.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1103(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_37),.I4(pre_out_0[2:2]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[2:2]));
defparam desc1103.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1104(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_39),.I4(pre_out_0[4:4]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[4:4]));
defparam desc1104.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1105(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_40),.I4(pre_out_0[5:5]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[5:5]));
defparam desc1105.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1106(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_45),.I4(pre_out_0[10:10]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[10:10]));
defparam desc1106.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1107(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_38),.I4(pre_out_0[3:3]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[3:3]));
defparam desc1107.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1108(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_42),.I4(pre_out_0[7:7]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[7:7]));
defparam desc1108.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1109(.I0(out_r_vec_mult_3[11:11]),.I1(in_a_r_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_43),.I4(pre_out_0[8:8]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[8:8]));
defparam desc1109.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1110(.I0(in_A_i[47:47]),.I1(out_i_vec_mult_0[11:11]),.I2(in_a_i_reg_0[11:11]),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_2[11:11]),.O(vec_in_i_AQ_mux_0_11));
defparam desc1110.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1111(.I0(in_A_r[47:47]),.I1(out_r_vec_mult_0[11:11]),.I2(in_a_r_reg_0_11),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_10),.O(vec_in_r_AQ_mux_0_10));
defparam desc1111.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1112(.I0(out_i_vec_mult_3[11:11]),.I1(in_a_i_reg_3[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_143),.I4(pre_out_1[8:8]),.I5(pre_out_3_9),.O(vec_in_i_AQ_mux_3[8:8]));
defparam desc1112.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1113(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_62),.I4(pre_out_1[3:3]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[3:3]));
defparam desc1113.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1114(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_65),.I4(pre_out_1[6:6]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[6:6]));
defparam desc1114.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1115(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_64),.I4(pre_out_1[5:5]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[5:5]));
defparam desc1115.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1116(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_69),.I4(pre_out_1[10:10]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[10:10]));
defparam desc1116.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1117(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_60),.I4(pre_out_0[1:1]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[1:1]));
defparam desc1117.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1118(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_68),.I4(pre_out_1[9:9]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[9:9]));
defparam desc1118.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1119(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_61),.I4(pre_out_1[2:2]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[2:2]));
defparam desc1119.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1120(.I0(out_r_vec_mult_1[11:11]),.I1(in_a_r_reg_1[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_66),.I4(pre_out_1[7:7]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[7:7]));
defparam desc1120.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1121(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_51),.I4(pre_out_1[4:4]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[4:4]));
defparam desc1121.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1122(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_55),.I4(pre_out_2[8:8]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[8:8]));
defparam desc1122.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1123(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_54),.I4(pre_out_2[7:7]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[7:7]));
defparam desc1123.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1124(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_48),.I4(pre_out_1[1:1]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[1:1]));
defparam desc1124.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1125(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_50),.I4(pre_out_2[3:3]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[3:3]));
defparam desc1125.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1126(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_57),.I4(pre_out_2[10:10]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[10:10]));
defparam desc1126.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1127(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_52),.I4(pre_out_2[5:5]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[5:5]));
defparam desc1127.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1128(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_49),.I4(pre_out_2[2:2]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[2:2]));
defparam desc1128.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1129(.I0(out_r_vec_mult_2[11:11]),.I1(in_a_r_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_56),.I4(pre_out_2[9:9]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[9:9]));
defparam desc1129.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1130(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_150),.I4(pre_out_3_1),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[3:3]));
defparam desc1130.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1131(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_156),.I4(pre_out_3_7),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[9:9]));
defparam desc1131.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1132(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_152),.I4(pre_out_3_3),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[5:5]));
defparam desc1132.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1133(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_157),.I4(pre_out_3_8),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[10:10]));
defparam desc1133.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1134(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_151),.I4(pre_out_2[4:4]),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[4:4]));
defparam desc1134.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1135(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_154),.I4(pre_out_3_5),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[7:7]));
defparam desc1135.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1136(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_155),.I4(pre_out_3_6),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[8:8]));
defparam desc1136.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1137(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_149),.I4(pre_out_3_0),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[2:2]));
defparam desc1137.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1138(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_153),.I4(pre_out_2[6:6]),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[6:6]));
defparam desc1138.INIT=64'hFFF02F20BFB00F00;
LUT6 desc1139(.I0(out_i_vec_mult_2[11:11]),.I1(in_a_i_reg_2[11:11]),.I2(vec_in_AQ_sel[1:1]),.I3(N_148),.I4(pre_out_2[1:1]),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[1:1]));
defparam desc1139.INIT=64'hFFF02F20BFB00F00;
LUT3 desc1140(.I0(in_A_i[25:25]),.I1(out_i_vec_mult_1[1:1]),.I2(vec_in_AQ_sel[0:0]),.O(N_160));
defparam desc1140.INIT=8'hCA;
LUT2 N_392_i_c(.I0(out_inner_prod_i[2:2]),.I1(single_in_R_sel),.O(N_392_i));
defparam N_392_i_c.INIT=4'h8;
LUT6 single_in_r_R_mux_i_a3_a(.I0(single_in_R_sel),.I1(pre_out_18),.I2(pre_out_19),.I3(pre_out_20),.I4(pre_out_21),.I5(PATTERNDETECT_32),.O(N_95));
defparam single_in_r_R_mux_i_a3_a.INIT=64'h1555555500000000;
LUT6 desc1141(.I0(single_in_R_sel),.I1(pre_out_reg[23:23]),.I2(pre_out_18),.I3(pre_out_19),.I4(pre_out_20),.I5(pre_out_21),.O(N_122));
defparam desc1141.INIT=64'h4444444444444445;
LUT5 desc1142(.I0(in_A_r[42:42]),.I1(out_r_vec_mult_0[6:6]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(N_500),.O(N_508));
defparam desc1142.INIT=32'h00CAFFCA;
LUT5 desc1143(.I0(in_A_r[36:36]),.I1(out_r_vec_mult_0[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(N_501),.O(N_507));
defparam desc1143.INIT=32'h00CAFFCA;
LUT5 desc1144(.I0(in_A_i[39:39]),.I1(out_i_vec_mult_0[3:3]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[3:3]),.O(N_506));
defparam desc1144.INIT=32'h00CAFFCA;
LUT5 desc1145(.I0(in_A_i[38:38]),.I1(out_i_vec_mult_0[2:2]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[2:2]),.O(N_505));
defparam desc1145.INIT=32'h00CAFFCA;
LUT5 desc1146(.I0(in_A_r[39:39]),.I1(out_r_vec_mult_0[3:3]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_2),.O(vec_in_r_AQ_mux_0_2));
defparam desc1146.INIT=32'h00CAFFCA;
LUT6 desc1147(.I0(in_A_r[11:11]),.I1(out_r_vec_mult_3[11:11]),.I2(in_a_r_reg_3[11:11]),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_1[11:11]),.O(vec_in_r_AQ_mux_3[11:11]));
defparam desc1147.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1148(.I0(in_A_r[23:23]),.I1(out_r_vec_mult_2[11:11]),.I2(in_a_r_reg_2[11:11]),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_5[11:11]),.O(vec_in_r_AQ_mux_2[11:11]));
defparam desc1148.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1149(.I0(in_A_r[18:18]),.I1(out_r_vec_mult_2[6:6]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[6:6]),.I5(un5_output),.O(vec_in_r_AQ_mux_2[6:6]));
defparam desc1149.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1150(.I0(in_A_r[12:12]),.I1(out_r_vec_mult_2[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[0:0]),.I5(un5_output),.O(vec_in_r_AQ_mux_2[0:0]));
defparam desc1150.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1151(.I0(in_A_r[35:35]),.I1(out_r_vec_mult_1[11:11]),.I2(in_a_r_reg_1[11:11]),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_4[11:11]),.O(vec_in_r_AQ_mux_1[11:11]));
defparam desc1151.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1152(.I0(in_A_r[32:32]),.I1(out_r_vec_mult_1[8:8]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[8:8]),.I5(un5_output_0),.O(vec_in_r_AQ_mux_1[8:8]));
defparam desc1152.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1153(.I0(in_A_r[28:28]),.I1(out_r_vec_mult_1[4:4]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[4:4]),.I5(un5_output_0),.O(vec_in_r_AQ_mux_1[4:4]));
defparam desc1153.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1154(.I0(in_A_r[24:24]),.I1(out_r_vec_mult_1[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m_0_0),.I5(un5_output_0),.O(vec_in_r_AQ_mux_1[0:0]));
defparam desc1154.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1155(.I0(in_A_i[11:11]),.I1(out_i_vec_mult_3[11:11]),.I2(in_a_i_reg_3[11:11]),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_3_9),.O(vec_in_i_AQ_mux_3[11:11]));
defparam desc1155.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1156(.I0(in_A_i[10:10]),.I1(out_i_vec_mult_3[10:10]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[10:10]),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[10:10]));
defparam desc1156.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1157(.I0(in_A_i[9:9]),.I1(out_i_vec_mult_3[9:9]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[9:9]),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[9:9]));
defparam desc1157.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1158(.I0(in_A_i[7:7]),.I1(out_i_vec_mult_3[7:7]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[7:7]),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[7:7]));
defparam desc1158.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1159(.I0(in_A_i[6:6]),.I1(out_i_vec_mult_3[6:6]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m_0_6),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[6:6]));
defparam desc1159.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1160(.I0(in_A_i[5:5]),.I1(out_i_vec_mult_3[5:5]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[5:5]),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[5:5]));
defparam desc1160.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1161(.I0(in_A_i[4:4]),.I1(out_i_vec_mult_3[4:4]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m_0_4),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[4:4]));
defparam desc1161.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1162(.I0(in_A_i[3:3]),.I1(out_i_vec_mult_3[3:3]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[3:3]),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[3:3]));
defparam desc1162.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1163(.I0(in_A_i[2:2]),.I1(out_i_vec_mult_3[2:2]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[2:2]),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[2:2]));
defparam desc1163.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1164(.I0(in_A_i[1:1]),.I1(out_i_vec_mult_3[1:1]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m[1:1]),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[1:1]));
defparam desc1164.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1165(.I0(in_A_i[0:0]),.I1(out_i_vec_mult_3[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m_1),.I5(un5_output_1),.O(vec_in_i_AQ_mux_3[0:0]));
defparam desc1165.INIT=64'h00CAFFCA00CA00CA;
LUT5 desc1166(.I0(in_A_i[37:37]),.I1(out_i_vec_mult_0[1:1]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[1:1]),.O(vec_in_i_AQ_mux_0_1));
defparam desc1166.INIT=32'h00CAFFCA;
LUT5 desc1167(.I0(in_A_r[41:41]),.I1(out_r_vec_mult_0[5:5]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[5:5]),.O(vec_in_r_AQ_mux_0_4));
defparam desc1167.INIT=32'h00CAFFCA;
LUT5 desc1168(.I0(in_A_r[40:40]),.I1(out_r_vec_mult_0[4:4]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[4:4]),.O(vec_in_r_AQ_mux_0_3));
defparam desc1168.INIT=32'h00CAFFCA;
LUT5 desc1169(.I0(in_A_i[41:41]),.I1(out_i_vec_mult_0[5:5]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_4),.O(vec_in_i_AQ_mux_0_5));
defparam desc1169.INIT=32'h00CAFFCA;
LUT5 desc1170(.I0(in_A_i[36:36]),.I1(out_i_vec_mult_0[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[0:0]),.O(vec_in_i_AQ_mux_0_0));
defparam desc1170.INIT=32'h00CAFFCA;
LUT5 desc1171(.I0(in_A_r[43:43]),.I1(out_r_vec_mult_0[7:7]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[7:7]),.O(vec_in_r_AQ_mux_0_6));
defparam desc1171.INIT=32'h00CAFFCA;
LUT5 desc1172(.I0(in_A_r[38:38]),.I1(out_r_vec_mult_0[2:2]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_1),.O(vec_in_r_AQ_mux_0_1));
defparam desc1172.INIT=32'h00CAFFCA;
LUT5 desc1173(.I0(in_A_i[44:44]),.I1(out_i_vec_mult_0[8:8]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[8:8]),.O(vec_in_i_AQ_mux_0_8));
defparam desc1173.INIT=32'h00CAFFCA;
LUT5 desc1174(.I0(in_A_r[46:46]),.I1(out_r_vec_mult_0[10:10]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[10:10]),.O(vec_in_r_AQ_mux_0_9));
defparam desc1174.INIT=32'h00CAFFCA;
LUT5 desc1175(.I0(in_A_r[45:45]),.I1(out_r_vec_mult_0[9:9]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[9:9]),.O(vec_in_r_AQ_mux_0_8));
defparam desc1175.INIT=32'h00CAFFCA;
LUT5 desc1176(.I0(in_A_r[37:37]),.I1(out_r_vec_mult_0[1:1]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_0),.O(vec_in_r_AQ_mux_0_0));
defparam desc1176.INIT=32'h00CAFFCA;
LUT5 desc1177(.I0(in_A_i[46:46]),.I1(out_i_vec_mult_0[10:10]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_9),.O(vec_in_i_AQ_mux_0_10));
defparam desc1177.INIT=32'h00CAFFCA;
LUT5 desc1178(.I0(in_A_i[43:43]),.I1(out_i_vec_mult_0[7:7]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_6),.O(vec_in_i_AQ_mux_0_7));
defparam desc1178.INIT=32'h00CAFFCA;
LUT5 desc1179(.I0(in_A_i[42:42]),.I1(out_i_vec_mult_0[6:6]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv[6:6]),.O(vec_in_i_AQ_mux_0_6));
defparam desc1179.INIT=32'h00CAFFCA;
LUT5 desc1180(.I0(in_A_i[45:45]),.I1(out_i_vec_mult_0[9:9]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_8),.O(vec_in_i_AQ_mux_0_9));
defparam desc1180.INIT=32'h00CAFFCA;
LUT5 desc1181(.I0(in_A_i[40:40]),.I1(out_i_vec_mult_0[4:4]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_3),.O(vec_in_i_AQ_mux_0_4));
defparam desc1181.INIT=32'h00CAFFCA;
LUT5 desc1182(.I0(in_A_r[44:44]),.I1(out_r_vec_mult_0[8:8]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(output_iv_0_7),.O(vec_in_r_AQ_mux_0_7));
defparam desc1182.INIT=32'h00CAFFCA;
LUT6 desc1183(.I0(in_A_r[1:1]),.I1(out_r_vec_mult_3[1:1]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m_0_1),.I5(un5_output_2),.O(vec_in_r_AQ_mux_3[1:1]));
defparam desc1183.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1184(.I0(in_A_r[0:0]),.I1(out_r_vec_mult_3[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(pre_out_i_m_2),.I5(un5_output_2),.O(vec_in_r_AQ_mux_3[0:0]));
defparam desc1184.INIT=64'h00CAFFCA00CA00CA;
LUT6 desc1185(.I0(in_A_i[23:23]),.I1(out_i_vec_mult_2[11:11]),.I2(in_a_i_reg_2[11:11]),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_6[11:11]),.O(vec_in_i_AQ_mux_2[11:11]));
defparam desc1185.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1186(.I0(in_A_i[12:12]),.I1(out_i_vec_mult_2[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(un5_output_3),.I5(pre_out_i_m_3),.O(vec_in_i_AQ_mux_2[0:0]));
defparam desc1186.INIT=64'h00CA00CAFFCA00CA;
LUT6 desc1187(.I0(in_A_i[35:35]),.I1(out_i_vec_mult_1[11:11]),.I2(in_a_i_reg_1[11:11]),.I3(vec_in_AQ_sel[0:0]),.I4(vec_in_AQ_sel[1:1]),.I5(pre_out_0[11:11]),.O(vec_in_i_AQ_mux_1[11:11]));
defparam desc1187.INIT=64'hF3F3CCAA3030CCAA;
LUT6 desc1188(.I0(in_A_i[24:24]),.I1(out_i_vec_mult_1[0:0]),.I2(vec_in_AQ_sel[0:0]),.I3(vec_in_AQ_sel[1:1]),.I4(un5_output_4),.I5(pre_out_i_m_4),.O(vec_in_i_AQ_mux_1[0:0]));
defparam desc1188.INIT=64'h00CA00CAFFCA00CA;
LUT5 desc1189(.I0(single_in_R_sel),.I1(out_inner_prod_r[11:11]),.I2(un8_rnd_out_P[19:19]),.I3(N_122),.I4(N_95),.O(single_in_r_R_mux[11:11]));
defparam desc1189.INIT=32'hFFFFF888;
LUT5 desc1190(.I0(out_inner_prod_r[10:10]),.I1(single_in_R_sel),.I2(un8_rnd_out[10:10]),.I3(N_122),.I4(N_95),.O(N_389_i));
defparam desc1190.INIT=32'h0000B0BB;
LUT5 desc1191(.I0(out_inner_prod_r[9:9]),.I1(single_in_R_sel),.I2(un8_rnd_out[9:9]),.I3(N_122),.I4(N_95),.O(N_388_i));
defparam desc1191.INIT=32'h0000B0BB;
LUT5 desc1192(.I0(out_inner_prod_r[8:8]),.I1(single_in_R_sel),.I2(un8_rnd_out[8:8]),.I3(N_122),.I4(N_95),.O(N_387_i));
defparam desc1192.INIT=32'h0000B0BB;
LUT5 desc1193(.I0(out_inner_prod_r[7:7]),.I1(single_in_R_sel),.I2(un8_rnd_out[7:7]),.I3(N_122),.I4(N_95),.O(N_386_i));
defparam desc1193.INIT=32'h0000B0BB;
LUT5 desc1194(.I0(out_inner_prod_r[6:6]),.I1(single_in_R_sel),.I2(un8_rnd_out[6:6]),.I3(N_122),.I4(N_95),.O(N_385_i));
defparam desc1194.INIT=32'h0000B0BB;
LUT5 desc1195(.I0(out_inner_prod_r[5:5]),.I1(single_in_R_sel),.I2(un8_rnd_out[5:5]),.I3(N_122),.I4(N_95),.O(N_384_i));
defparam desc1195.INIT=32'h0000B0BB;
LUT5 desc1196(.I0(out_inner_prod_r[4:4]),.I1(single_in_R_sel),.I2(un8_rnd_out[4:4]),.I3(N_122),.I4(N_95),.O(N_383_i));
defparam desc1196.INIT=32'h0000B0BB;
LUT5 desc1197(.I0(out_inner_prod_r[3:3]),.I1(single_in_R_sel),.I2(un8_rnd_out[3:3]),.I3(N_122),.I4(N_95),.O(N_34_i));
defparam desc1197.INIT=32'h0000B0BB;
LUT5 desc1198(.I0(out_inner_prod_r[2:2]),.I1(single_in_R_sel),.I2(un8_rnd_out[2:2]),.I3(N_122),.I4(N_95),.O(N_32_i));
defparam desc1198.INIT=32'h0000B0BB;
LUT5 desc1199(.I0(out_inner_prod_r[1:1]),.I1(single_in_R_sel),.I2(un8_rnd_out[1:1]),.I3(N_122),.I4(N_95),.O(N_30_i));
defparam desc1199.INIT=32'h0000B0BB;
LUT5 desc1200(.I0(out_inner_prod_r[0:0]),.I1(single_in_R_sel),.I2(un8_rnd_out[0:0]),.I3(N_122),.I4(N_95),.O(N_28_i));
defparam desc1200.INIT=32'h0000B0BB;
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
LUT5 desc1201(.I0(out_r_vec_mult_0[0:0]),.I1(in_a_r_reg_0_0),.I2(out_r_vec_mult_0[11:11]),.I3(in_a_r_reg_0_11),.I4(pre_out_10),.O(N_501));
defparam desc1201.INIT=32'h99099F99;
LUT3 desc1202(.I0(out_r_vec_mult_0[11:11]),.I1(in_a_r_reg_0_11),.I2(pre_out_10),.O(out_r_vec_sub_0[11:11]));
defparam desc1202.INIT=8'hD4;
LUT3 desc1203(.I0(col_sel_R_int[0:0]),.I1(col_sel_R[0:0]),.I2(wr_en_AQ_sel),.O(col_sel_R_mux_i_m3_lut6_2_O6));
defparam desc1203.INIT=8'hAC;
LUT3 desc1204(.I0(col_sel_R[1:1]),.I1(col_sel_R_int[1:1]),.I2(wr_en_AQ_sel),.O(col_sel_R_mux_i_m3_lut6_2_O5));
defparam desc1204.INIT=8'hCA;
LUT3 wr_en_AQ_mux_i_m3_lut6_2_o6(.I0(wr_en_AQ_int),.I1(wr_A_QR),.I2(wr_en_AQ_sel),.O(wr_en_AQ_mux_i_m3_lut6_2_O6));
defparam wr_en_AQ_mux_i_m3_lut6_2_o6.INIT=8'hAC;
LUT3 wr_en_AQ_mux_i_m3_lut6_2_o5(.I0(start_QR),.I1(state_5),.I2(wr_en_AQ_sel),.O(wr_en_AQ_sel_0));
defparam wr_en_AQ_mux_i_m3_lut6_2_o5.INIT=8'hB8;
LUT3 desc1205(.I0(col_sel_AQ[0:0]),.I1(col_sel_AQ2_int[0:0]),.I2(wr_en_AQ_sel),.O(col_sel_AQ2_mux_i_m3_lut6_2_O6));
defparam desc1205.INIT=8'hCA;
LUT3 desc1206(.I0(col_sel_AQ[1:1]),.I1(col_sel_AQ2_int[1:1]),.I2(wr_en_AQ_sel),.O(col_sel_AQ2_mux_i_m3_lut6_2_O5));
defparam desc1206.INIT=8'hCA;
LUT3 desc1207(.I0(w_col_sel_AQ_int[0:0]),.I1(col_sel_AQ[0:0]),.I2(wr_en_AQ_sel),.O(w_col_sel_AQ_mux_i_m3_lut6_2_O6));
defparam desc1207.INIT=8'hAC;
LUT3 desc1208(.I0(w_col_sel_AQ_int[1:1]),.I1(col_sel_AQ[1:1]),.I2(wr_en_AQ_sel),.O(w_col_sel_AQ_mux_i_m3_lut6_2_O5));
defparam desc1208.INIT=8'hAC;
LUT3 desc1209(.I0(in_A_r[9:9]),.I1(out_r_vec_mult_3[9:9]),.I2(vec_in_AQ_sel[0:0]),.O(N_44));
defparam desc1209.INIT=8'hCA;
LUT3 desc1210(.I0(in_A_r[10:10]),.I1(out_r_vec_mult_3[10:10]),.I2(vec_in_AQ_sel[0:0]),.O(N_45));
defparam desc1210.INIT=8'hCA;
LUT3 desc1211(.I0(in_A_r[7:7]),.I1(out_r_vec_mult_3[7:7]),.I2(vec_in_AQ_sel[0:0]),.O(N_42));
defparam desc1211.INIT=8'hCA;
LUT3 desc1212(.I0(in_A_r[8:8]),.I1(out_r_vec_mult_3[8:8]),.I2(vec_in_AQ_sel[0:0]),.O(N_43));
defparam desc1212.INIT=8'hCA;
LUT3 desc1213(.I0(in_A_r[21:21]),.I1(out_r_vec_mult_2[9:9]),.I2(vec_in_AQ_sel[0:0]),.O(N_56));
defparam desc1213.INIT=8'hCA;
LUT3 desc1214(.I0(in_A_r[22:22]),.I1(out_r_vec_mult_2[10:10]),.I2(vec_in_AQ_sel[0:0]),.O(N_57));
defparam desc1214.INIT=8'hCA;
LUT3 desc1215(.I0(in_A_r[19:19]),.I1(out_r_vec_mult_2[7:7]),.I2(vec_in_AQ_sel[0:0]),.O(N_54));
defparam desc1215.INIT=8'hCA;
LUT3 desc1216(.I0(in_A_r[20:20]),.I1(out_r_vec_mult_2[8:8]),.I2(vec_in_AQ_sel[0:0]),.O(N_55));
defparam desc1216.INIT=8'hCA;
LUT3 desc1217(.I0(in_A_r[16:16]),.I1(out_r_vec_mult_2[4:4]),.I2(vec_in_AQ_sel[0:0]),.O(N_51));
defparam desc1217.INIT=8'hCA;
LUT3 desc1218(.I0(in_A_r[17:17]),.I1(out_r_vec_mult_2[5:5]),.I2(vec_in_AQ_sel[0:0]),.O(N_52));
defparam desc1218.INIT=8'hCA;
LUT3 desc1219(.I0(in_A_r[13:13]),.I1(out_r_vec_mult_2[1:1]),.I2(vec_in_AQ_sel[0:0]),.O(N_48));
defparam desc1219.INIT=8'hCA;
LUT3 desc1220(.I0(in_A_r[14:14]),.I1(out_r_vec_mult_2[2:2]),.I2(vec_in_AQ_sel[0:0]),.O(N_49));
defparam desc1220.INIT=8'hCA;
LUT3 desc1221(.I0(in_A_r[33:33]),.I1(out_r_vec_mult_1[9:9]),.I2(vec_in_AQ_sel[0:0]),.O(N_68));
defparam desc1221.INIT=8'hCA;
LUT3 desc1222(.I0(in_A_r[34:34]),.I1(out_r_vec_mult_1[10:10]),.I2(vec_in_AQ_sel[0:0]),.O(N_69));
defparam desc1222.INIT=8'hCA;
LUT3 desc1223(.I0(in_A_r[29:29]),.I1(out_r_vec_mult_1[5:5]),.I2(vec_in_AQ_sel[0:0]),.O(N_64));
defparam desc1223.INIT=8'hCA;
LUT3 desc1224(.I0(in_A_r[30:30]),.I1(out_r_vec_mult_1[6:6]),.I2(vec_in_AQ_sel[0:0]),.O(N_65));
defparam desc1224.INIT=8'hCA;
LUT3 desc1225(.I0(in_A_r[26:26]),.I1(out_r_vec_mult_1[2:2]),.I2(vec_in_AQ_sel[0:0]),.O(N_61));
defparam desc1225.INIT=8'hCA;
LUT3 desc1226(.I0(in_A_r[27:27]),.I1(out_r_vec_mult_1[3:3]),.I2(vec_in_AQ_sel[0:0]),.O(N_62));
defparam desc1226.INIT=8'hCA;
LUT3 desc1227(.I0(in_A_r[25:25]),.I1(out_r_vec_mult_1[1:1]),.I2(vec_in_AQ_sel[0:0]),.O(N_60));
defparam desc1227.INIT=8'hCA;
LUT3 desc1228(.I0(in_A_r[31:31]),.I1(out_r_vec_mult_1[7:7]),.I2(vec_in_AQ_sel[0:0]),.O(N_66));
defparam desc1228.INIT=8'hCA;
LUT3 desc1229(.I0(in_A_r[6:6]),.I1(out_r_vec_mult_3[6:6]),.I2(vec_in_AQ_sel[0:0]),.O(N_41));
defparam desc1229.INIT=8'hCA;
LUT3 desc1230(.I0(in_A_r[15:15]),.I1(out_r_vec_mult_2[3:3]),.I2(vec_in_AQ_sel[0:0]),.O(N_50));
defparam desc1230.INIT=8'hCA;
LUT3 desc1231(.I0(in_A_r[4:4]),.I1(out_r_vec_mult_3[4:4]),.I2(vec_in_AQ_sel[0:0]),.O(N_39));
defparam desc1231.INIT=8'hCA;
LUT3 desc1232(.I0(in_A_r[5:5]),.I1(out_r_vec_mult_3[5:5]),.I2(vec_in_AQ_sel[0:0]),.O(N_40));
defparam desc1232.INIT=8'hCA;
LUT3 desc1233(.I0(in_A_r[2:2]),.I1(out_r_vec_mult_3[2:2]),.I2(vec_in_AQ_sel[0:0]),.O(N_37));
defparam desc1233.INIT=8'hCA;
LUT3 desc1234(.I0(in_A_r[3:3]),.I1(out_r_vec_mult_3[3:3]),.I2(vec_in_AQ_sel[0:0]),.O(N_38));
defparam desc1234.INIT=8'hCA;
LUT3 desc1235(.I0(in_A_i[21:21]),.I1(out_i_vec_mult_2[9:9]),.I2(vec_in_AQ_sel[0:0]),.O(N_156));
defparam desc1235.INIT=8'hCA;
LUT3 desc1236(.I0(in_A_i[22:22]),.I1(out_i_vec_mult_2[10:10]),.I2(vec_in_AQ_sel[0:0]),.O(N_157));
defparam desc1236.INIT=8'hCA;
LUT3 desc1237(.I0(in_A_i[20:20]),.I1(out_i_vec_mult_2[8:8]),.I2(vec_in_AQ_sel[0:0]),.O(N_155));
defparam desc1237.INIT=8'hCA;
LUT3 desc1238(.I0(in_A_i[8:8]),.I1(out_i_vec_mult_3[8:8]),.I2(vec_in_AQ_sel[0:0]),.O(N_143));
defparam desc1238.INIT=8'hCA;
LUT3 desc1239(.I0(in_A_i[18:18]),.I1(out_i_vec_mult_2[6:6]),.I2(vec_in_AQ_sel[0:0]),.O(N_153));
defparam desc1239.INIT=8'hCA;
LUT3 desc1240(.I0(in_A_i[19:19]),.I1(out_i_vec_mult_2[7:7]),.I2(vec_in_AQ_sel[0:0]),.O(N_154));
defparam desc1240.INIT=8'hCA;
LUT3 desc1241(.I0(in_A_i[16:16]),.I1(out_i_vec_mult_2[4:4]),.I2(vec_in_AQ_sel[0:0]),.O(N_151));
defparam desc1241.INIT=8'hCA;
LUT3 desc1242(.I0(in_A_i[17:17]),.I1(out_i_vec_mult_2[5:5]),.I2(vec_in_AQ_sel[0:0]),.O(N_152));
defparam desc1242.INIT=8'hCA;
LUT3 desc1243(.I0(in_A_i[14:14]),.I1(out_i_vec_mult_2[2:2]),.I2(vec_in_AQ_sel[0:0]),.O(N_149));
defparam desc1243.INIT=8'hCA;
LUT3 desc1244(.I0(in_A_i[15:15]),.I1(out_i_vec_mult_2[3:3]),.I2(vec_in_AQ_sel[0:0]),.O(N_150));
defparam desc1244.INIT=8'hCA;
LUT3 desc1245(.I0(in_A_i[33:33]),.I1(out_i_vec_mult_1[9:9]),.I2(vec_in_AQ_sel[0:0]),.O(N_168));
defparam desc1245.INIT=8'hCA;
LUT3 desc1246(.I0(in_A_i[34:34]),.I1(out_i_vec_mult_1[10:10]),.I2(vec_in_AQ_sel[0:0]),.O(N_169));
defparam desc1246.INIT=8'hCA;
LUT3 desc1247(.I0(in_A_i[31:31]),.I1(out_i_vec_mult_1[7:7]),.I2(vec_in_AQ_sel[0:0]),.O(N_166));
defparam desc1247.INIT=8'hCA;
LUT3 desc1248(.I0(in_A_i[32:32]),.I1(out_i_vec_mult_1[8:8]),.I2(vec_in_AQ_sel[0:0]),.O(N_167));
defparam desc1248.INIT=8'hCA;
LUT3 desc1249(.I0(in_A_i[30:30]),.I1(out_i_vec_mult_1[6:6]),.I2(vec_in_AQ_sel[0:0]),.O(N_165));
defparam desc1249.INIT=8'hCA;
LUT3 desc1250(.I0(in_A_i[13:13]),.I1(out_i_vec_mult_2[1:1]),.I2(vec_in_AQ_sel[0:0]),.O(N_148));
defparam desc1250.INIT=8'hCA;
LUT3 desc1251(.I0(in_A_i[28:28]),.I1(out_i_vec_mult_1[4:4]),.I2(vec_in_AQ_sel[0:0]),.O(N_163));
defparam desc1251.INIT=8'hCA;
LUT3 desc1252(.I0(in_A_i[29:29]),.I1(out_i_vec_mult_1[5:5]),.I2(vec_in_AQ_sel[0:0]),.O(N_164));
defparam desc1252.INIT=8'hCA;
LUT3 desc1253(.I0(in_A_i[26:26]),.I1(out_i_vec_mult_1[2:2]),.I2(vec_in_AQ_sel[0:0]),.O(N_161));
defparam desc1253.INIT=8'hCA;
LUT3 desc1254(.I0(in_A_i[27:27]),.I1(out_i_vec_mult_1[3:3]),.I2(vec_in_AQ_sel[0:0]),.O(N_162));
defparam desc1254.INIT=8'hCA;
LUT2 N_399_i_lut6_2_o6(.I0(out_inner_prod_i[9:9]),.I1(single_in_R_sel),.O(N_399_i));
defparam N_399_i_lut6_2_o6.INIT=4'h8;
LUT2 N_399_i_lut6_2_o5(.I0(single_in_R_sel),.I1(out_inner_prod_i[11:11]),.O(N_401_i));
defparam N_399_i_lut6_2_o5.INIT=4'h8;
LUT2 N_398_i_lut6_2_o6(.I0(out_inner_prod_i[8:8]),.I1(single_in_R_sel),.O(N_398_i));
defparam N_398_i_lut6_2_o6.INIT=4'h8;
LUT2 N_398_i_lut6_2_o5(.I0(out_inner_prod_i[10:10]),.I1(single_in_R_sel),.O(N_400_i));
defparam N_398_i_lut6_2_o5.INIT=4'h8;
LUT2 N_395_i_lut6_2_o6(.I0(out_inner_prod_i[5:5]),.I1(single_in_R_sel),.O(N_395_i));
defparam N_395_i_lut6_2_o6.INIT=4'h8;
LUT2 N_395_i_lut6_2_o5(.I0(out_inner_prod_i[7:7]),.I1(single_in_R_sel),.O(N_397_i));
defparam N_395_i_lut6_2_o5.INIT=4'h8;
LUT2 N_394_i_lut6_2_o6(.I0(out_inner_prod_i[4:4]),.I1(single_in_R_sel),.O(N_394_i));
defparam N_394_i_lut6_2_o6.INIT=4'h8;
LUT2 N_394_i_lut6_2_o5(.I0(out_inner_prod_i[6:6]),.I1(single_in_R_sel),.O(N_396_i));
defparam N_394_i_lut6_2_o5.INIT=4'h8;
LUT2 N_391_i_lut6_2_o6(.I0(out_inner_prod_i[1:1]),.I1(single_in_R_sel),.O(N_391_i));
defparam N_391_i_lut6_2_o6.INIT=4'h8;
LUT4 N_391_i_lut6_2_o5(.I0(state_0),.I1(state_2),.I2(single_in_R_sel),.I3(done_inv_sqrt),.O(single_in_R_sel_0));
defparam N_391_i_lut6_2_o5.INIT=16'hBAFA;
LUT2 N_390_i_lut6_2_o6(.I0(out_inner_prod_i[0:0]),.I1(single_in_R_sel),.O(N_390_i));
defparam N_390_i_lut6_2_o6.INIT=4'h8;
LUT2 N_390_i_lut6_2_o5(.I0(out_inner_prod_i[3:3]),.I1(single_in_R_sel),.O(N_393_i));
defparam N_390_i_lut6_2_o5.INIT=4'h8;
endmodule
module qr_wrapper_inj (out_Q_r,out_Q_i,out_R_i,out_R_r,in_A_r,in_A_i,clk,rst,valid_out,ready,request_out,start,reduced_matrix,p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_,p_desc951_p_O_FDEinv_sqrt_qr_decomp_,p_desc952_p_O_FDEinv_sqrt_qr_decomp_,p_desc953_p_O_FDEinv_sqrt_qr_decomp_,p_desc954_p_O_FDEinv_sqrt_qr_decomp_,p_desc955_p_O_FDEinv_sqrt_qr_decomp_,p_desc956_p_O_FDEinv_sqrt_qr_decomp_,p_desc957_p_O_FDEinv_sqrt_qr_decomp_,p_desc958_p_O_FDEinv_sqrt_qr_decomp_,p_desc959_p_O_FDEinv_sqrt_qr_decomp_,p_desc960_p_O_FDEinv_sqrt_qr_decomp_,p_desc961_p_O_FDEinv_sqrt_qr_decomp_,p_desc962_p_O_FDEinv_sqrt_qr_decomp_,p_desc48_p_O_FDEr_mat_regs_qr_decomp_,p_desc49_p_O_FDEr_mat_regs_qr_decomp_,p_desc50_p_O_FDEr_mat_regs_qr_decomp_,p_desc51_p_O_FDEr_mat_regs_qr_decomp_,p_desc52_p_O_FDEr_mat_regs_qr_decomp_,p_desc53_p_O_FDEr_mat_regs_qr_decomp_,p_desc54_p_O_FDEr_mat_regs_qr_decomp_,p_desc55_p_O_FDEr_mat_regs_qr_decomp_,p_desc56_p_O_FDEr_mat_regs_qr_decomp_,p_desc57_p_O_FDEr_mat_regs_qr_decomp_,p_desc58_p_O_FDEr_mat_regs_qr_decomp_,p_desc59_p_O_FDEr_mat_regs_qr_decomp_,p_desc60_p_O_FDEr_mat_regs_qr_decomp_,p_desc61_p_O_FDEr_mat_regs_qr_decomp_,p_desc62_p_O_FDEr_mat_regs_qr_decomp_,p_desc63_p_O_FDEr_mat_regs_qr_decomp_,p_desc64_p_O_FDEr_mat_regs_qr_decomp_,p_desc65_p_O_FDEr_mat_regs_qr_decomp_,p_desc66_p_O_FDEr_mat_regs_qr_decomp_,p_desc67_p_O_FDEr_mat_regs_qr_decomp_,p_desc68_p_O_FDEr_mat_regs_qr_decomp_,p_desc69_p_O_FDEr_mat_regs_qr_decomp_,p_desc70_p_O_FDEr_mat_regs_qr_decomp_,p_desc71_p_O_FDEr_mat_regs_qr_decomp_,p_desc72_p_O_FDEr_mat_regs_qr_decomp_,p_desc73_p_O_FDEr_mat_regs_qr_decomp_,p_desc74_p_O_FDEr_mat_regs_qr_decomp_,p_desc75_p_O_FDEr_mat_regs_qr_decomp_,p_desc76_p_O_FDEr_mat_regs_qr_decomp_,p_desc77_p_O_FDEr_mat_regs_qr_decomp_,p_desc78_p_O_FDEr_mat_regs_qr_decomp_,p_desc79_p_O_FDEr_mat_regs_qr_decomp_,p_desc80_p_O_FDEr_mat_regs_qr_decomp_,p_desc81_p_O_FDEr_mat_regs_qr_decomp_,p_desc82_p_O_FDEr_mat_regs_qr_decomp_,p_desc83_p_O_FDEr_mat_regs_qr_decomp_,p_desc84_p_O_FDEr_mat_regs_qr_decomp_,p_desc85_p_O_FDEr_mat_regs_qr_decomp_,p_desc86_p_O_FDEr_mat_regs_qr_decomp_,p_desc87_p_O_FDEr_mat_regs_qr_decomp_,p_desc88_p_O_FDEr_mat_regs_qr_decomp_,p_desc89_p_O_FDEr_mat_regs_qr_decomp_,p_desc90_p_O_FDEr_mat_regs_qr_decomp_,p_desc91_p_O_FDEr_mat_regs_qr_decomp_,p_desc92_p_O_FDEr_mat_regs_qr_decomp_,p_desc93_p_O_FDEr_mat_regs_qr_decomp_,p_desc94_p_O_FDEr_mat_regs_qr_decomp_,p_desc95_p_O_FDEr_mat_regs_qr_decomp_,p_desc96_p_O_FDEr_mat_regs_qr_decomp_,p_desc97_p_O_FDEr_mat_regs_qr_decomp_,p_desc98_p_O_FDEr_mat_regs_qr_decomp_,p_desc99_p_O_FDEr_mat_regs_qr_decomp_,p_desc100_p_O_FDEr_mat_regs_qr_decomp_,p_desc101_p_O_FDEr_mat_regs_qr_decomp_,p_desc102_p_O_FDEr_mat_regs_qr_decomp_,p_desc103_p_O_FDEr_mat_regs_qr_decomp_,p_desc104_p_O_FDEr_mat_regs_qr_decomp_,p_desc105_p_O_FDEr_mat_regs_qr_decomp_,p_desc106_p_O_FDEr_mat_regs_qr_decomp_,p_desc107_p_O_FDEr_mat_regs_qr_decomp_,p_desc108_p_O_FDEr_mat_regs_qr_decomp_,p_desc109_p_O_FDEr_mat_regs_qr_decomp_,p_desc110_p_O_FDEr_mat_regs_qr_decomp_,p_desc111_p_O_FDEr_mat_regs_qr_decomp_,p_desc112_p_O_FDEr_mat_regs_qr_decomp_,p_desc113_p_O_FDEr_mat_regs_qr_decomp_,p_desc114_p_O_FDEr_mat_regs_qr_decomp_,p_desc115_p_O_FDEr_mat_regs_qr_decomp_,p_desc116_p_O_FDEr_mat_regs_qr_decomp_,p_desc117_p_O_FDEr_mat_regs_qr_decomp_,p_desc118_p_O_FDEr_mat_regs_qr_decomp_,p_desc119_p_O_FDEr_mat_regs_qr_decomp_,p_desc120_p_O_FDEr_mat_regs_qr_decomp_,p_desc121_p_O_FDEr_mat_regs_qr_decomp_,p_desc122_p_O_FDEr_mat_regs_qr_decomp_,p_desc123_p_O_FDEr_mat_regs_qr_decomp_,p_desc124_p_O_FDEr_mat_regs_qr_decomp_,p_desc125_p_O_FDEr_mat_regs_qr_decomp_,p_desc126_p_O_FDEr_mat_regs_qr_decomp_,p_desc127_p_O_FDEr_mat_regs_qr_decomp_,p_desc128_p_O_FDEr_mat_regs_qr_decomp_,p_desc129_p_O_FDEr_mat_regs_qr_decomp_,p_desc130_p_O_FDEr_mat_regs_qr_decomp_,p_desc131_p_O_FDEr_mat_regs_qr_decomp_,p_desc132_p_O_FDEr_mat_regs_qr_decomp_,p_desc133_p_O_FDEr_mat_regs_qr_decomp_,p_desc134_p_O_FDEr_mat_regs_qr_decomp_,p_desc135_p_O_FDEr_mat_regs_qr_decomp_,p_desc136_p_O_FDEr_mat_regs_qr_decomp_,p_desc137_p_O_FDEr_mat_regs_qr_decomp_,p_desc138_p_O_FDEr_mat_regs_qr_decomp_,p_desc139_p_O_FDEr_mat_regs_qr_decomp_,p_desc140_p_O_FDEr_mat_regs_qr_decomp_,p_desc141_p_O_FDEr_mat_regs_qr_decomp_,p_desc142_p_O_FDEr_mat_regs_qr_decomp_,p_desc143_p_O_FDEr_mat_regs_qr_decomp_,p_desc144_p_O_FDEr_mat_regs_qr_decomp_,p_desc145_p_O_FDEr_mat_regs_qr_decomp_,p_desc146_p_O_FDEr_mat_regs_qr_decomp_,p_desc147_p_O_FDEr_mat_regs_qr_decomp_,p_desc148_p_O_FDEr_mat_regs_qr_decomp_,p_desc149_p_O_FDEr_mat_regs_qr_decomp_,p_desc150_p_O_FDEr_mat_regs_qr_decomp_,p_desc151_p_O_FDEr_mat_regs_qr_decomp_,p_desc152_p_O_FDEr_mat_regs_qr_decomp_,p_desc153_p_O_FDEr_mat_regs_qr_decomp_,p_desc154_p_O_FDEr_mat_regs_qr_decomp_,p_desc155_p_O_FDEr_mat_regs_qr_decomp_,p_desc156_p_O_FDEr_mat_regs_qr_decomp_,p_desc157_p_O_FDEr_mat_regs_qr_decomp_,p_desc158_p_O_FDEr_mat_regs_qr_decomp_,p_desc159_p_O_FDEr_mat_regs_qr_decomp_,p_desc160_p_O_FDEr_mat_regs_qr_decomp_,p_desc161_p_O_FDEr_mat_regs_qr_decomp_,p_desc162_p_O_FDEr_mat_regs_qr_decomp_,p_desc163_p_O_FDEr_mat_regs_qr_decomp_,p_desc164_p_O_FDEr_mat_regs_qr_decomp_,p_desc165_p_O_FDEr_mat_regs_qr_decomp_,p_desc166_p_O_FDEr_mat_regs_qr_decomp_,p_desc167_p_O_FDEr_mat_regs_qr_decomp_,p_desc168_p_O_FDEr_mat_regs_qr_decomp_,p_desc169_p_O_FDEr_mat_regs_qr_decomp_,p_desc170_p_O_FDEr_mat_regs_qr_decomp_,p_desc171_p_O_FDEr_mat_regs_qr_decomp_,p_desc172_p_O_FDEr_mat_regs_qr_decomp_,p_desc173_p_O_FDEr_mat_regs_qr_decomp_,p_desc174_p_O_FDEr_mat_regs_qr_decomp_,p_desc175_p_O_FDEr_mat_regs_qr_decomp_,p_desc176_p_O_FDEr_mat_regs_qr_decomp_,p_desc177_p_O_FDEr_mat_regs_qr_decomp_,p_desc178_p_O_FDEr_mat_regs_qr_decomp_,p_desc179_p_O_FDEr_mat_regs_qr_decomp_,p_desc180_p_O_FDEr_mat_regs_qr_decomp_,p_desc181_p_O_FDEr_mat_regs_qr_decomp_,p_desc182_p_O_FDEr_mat_regs_qr_decomp_,p_desc183_p_O_FDEr_mat_regs_qr_decomp_,p_desc184_p_O_FDEr_mat_regs_qr_decomp_,p_desc185_p_O_FDEr_mat_regs_qr_decomp_,p_desc186_p_O_FDEr_mat_regs_qr_decomp_,p_desc187_p_O_FDEr_mat_regs_qr_decomp_,p_desc188_p_O_FDEr_mat_regs_qr_decomp_,p_desc189_p_O_FDEr_mat_regs_qr_decomp_,p_desc190_p_O_FDEr_mat_regs_qr_decomp_,p_desc191_p_O_FDEr_mat_regs_qr_decomp_,p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_,p_desc739_p_O_FDEvec_sub_qr_decomp_,p_desc740_p_O_FDEvec_sub_qr_decomp_,p_desc741_p_O_FDEvec_sub_qr_decomp_,p_desc742_p_O_FDEvec_sub_qr_decomp_,p_desc743_p_O_FDEvec_sub_qr_decomp_,p_desc744_p_O_FDEvec_sub_qr_decomp_,p_desc745_p_O_FDEvec_sub_qr_decomp_,p_desc746_p_O_FDEvec_sub_qr_decomp_,p_desc747_p_O_FDEvec_sub_qr_decomp_,p_desc748_p_O_FDEvec_sub_qr_decomp_,p_desc749_p_O_FDEvec_sub_qr_decomp_,p_desc750_p_O_FDEvec_sub_qr_decomp_,p_desc751_p_O_FDEvec_sub_qr_decomp_,p_desc752_p_O_FDEvec_sub_qr_decomp_,p_desc753_p_O_FDEvec_sub_qr_decomp_,p_desc754_p_O_FDEvec_sub_qr_decomp_,p_desc755_p_O_FDEvec_sub_qr_decomp_,p_desc756_p_O_FDEvec_sub_qr_decomp_,p_desc757_p_O_FDEvec_sub_qr_decomp_,p_desc758_p_O_FDEvec_sub_qr_decomp_,p_desc759_p_O_FDEvec_sub_qr_decomp_,p_desc760_p_O_FDEvec_sub_qr_decomp_,p_desc761_p_O_FDEvec_sub_qr_decomp_,p_desc762_p_O_FDEvec_sub_qr_decomp_,p_desc763_p_O_FDEvec_sub_qr_decomp_,p_desc764_p_O_FDEvec_sub_qr_decomp_,p_desc765_p_O_FDEvec_sub_qr_decomp_,p_desc766_p_O_FDEvec_sub_qr_decomp_,p_desc767_p_O_FDEvec_sub_qr_decomp_,p_desc768_p_O_FDEvec_sub_qr_decomp_,p_desc769_p_O_FDEvec_sub_qr_decomp_,p_desc770_p_O_FDEvec_sub_qr_decomp_,p_desc771_p_O_FDEvec_sub_qr_decomp_,p_desc772_p_O_FDEvec_sub_qr_decomp_,p_desc773_p_O_FDEvec_sub_qr_decomp_,p_desc774_p_O_FDEvec_sub_qr_decomp_,p_desc775_p_O_FDEvec_sub_qr_decomp_,p_desc776_p_O_FDEvec_sub_qr_decomp_,p_desc777_p_O_FDEvec_sub_qr_decomp_,p_desc778_p_O_FDEvec_sub_qr_decomp_,p_desc779_p_O_FDEvec_sub_qr_decomp_,p_desc780_p_O_FDEvec_sub_qr_decomp_,p_desc781_p_O_FDEvec_sub_qr_decomp_,p_desc782_p_O_FDEvec_sub_qr_decomp_,p_desc783_p_O_FDEvec_sub_qr_decomp_,p_desc784_p_O_FDEvec_sub_qr_decomp_,p_desc785_p_O_FDEvec_sub_qr_decomp_,p_desc786_p_O_FDEvec_sub_qr_decomp_,p_desc787_p_O_FDEvec_sub_qr_decomp_,p_desc788_p_O_FDEvec_sub_qr_decomp_,p_desc789_p_O_FDEvec_sub_qr_decomp_,p_desc790_p_O_FDEvec_sub_qr_decomp_,p_desc791_p_O_FDEvec_sub_qr_decomp_,p_desc792_p_O_FDEvec_sub_qr_decomp_,p_desc793_p_O_FDEvec_sub_qr_decomp_,p_desc794_p_O_FDEvec_sub_qr_decomp_,p_desc795_p_O_FDEvec_sub_qr_decomp_,p_desc796_p_O_FDEvec_sub_qr_decomp_,p_desc797_p_O_FDEvec_sub_qr_decomp_,p_desc798_p_O_FDEvec_sub_qr_decomp_,p_desc799_p_O_FDEvec_sub_qr_decomp_,p_desc800_p_O_FDEvec_sub_qr_decomp_,p_desc801_p_O_FDEvec_sub_qr_decomp_,p_desc802_p_O_FDEvec_sub_qr_decomp_,p_desc803_p_O_FDEvec_sub_qr_decomp_,p_desc804_p_O_FDEvec_sub_qr_decomp_,p_desc805_p_O_FDEvec_sub_qr_decomp_,p_desc806_p_O_FDEvec_sub_qr_decomp_,p_desc807_p_O_FDEvec_sub_qr_decomp_,p_desc808_p_O_FDEvec_sub_qr_decomp_,p_desc809_p_O_FDEvec_sub_qr_decomp_,p_desc810_p_O_FDEvec_sub_qr_decomp_,p_desc811_p_O_FDEvec_sub_qr_decomp_,p_desc812_p_O_FDEvec_sub_qr_decomp_,p_desc813_p_O_FDEvec_sub_qr_decomp_,p_desc814_p_O_FDEvec_sub_qr_decomp_,p_desc815_p_O_FDEvec_sub_qr_decomp_,p_desc816_p_O_FDEvec_sub_qr_decomp_,p_desc817_p_O_FDEvec_sub_qr_decomp_,p_desc818_p_O_FDEvec_sub_qr_decomp_,p_desc819_p_O_FDEvec_sub_qr_decomp_,p_desc820_p_O_FDEvec_sub_qr_decomp_,p_desc821_p_O_FDEvec_sub_qr_decomp_,p_desc822_p_O_FDEvec_sub_qr_decomp_,p_desc823_p_O_FDEvec_sub_qr_decomp_,p_desc824_p_O_FDEvec_sub_qr_decomp_,p_desc825_p_O_FDEvec_sub_qr_decomp_,p_desc826_p_O_FDEvec_sub_qr_decomp_,p_desc827_p_O_FDEvec_sub_qr_decomp_,p_desc828_p_O_FDEvec_sub_qr_decomp_,p_desc829_p_O_FDEvec_sub_qr_decomp_,p_desc830_p_O_FDEvec_sub_qr_decomp_,p_desc831_p_O_FDEvec_sub_qr_decomp_,p_desc832_p_O_FDEvec_sub_qr_decomp_,p_desc833_p_O_FDEvec_sub_qr_decomp_,p_desc834_p_O_FDEvec_sub_qr_decomp_,p_output_reg_pipe_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_qr_decomp_,p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_qr_decomp_,p_desc318_p_O_FDCinner_prod_qr_decomp_,p_desc319_p_O_FDCinner_prod_qr_decomp_,p_desc320_p_O_FDCinner_prod_qr_decomp_,p_desc321_p_O_FDCinner_prod_qr_decomp_,p_desc322_p_O_FDCinner_prod_qr_decomp_,p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_qr_decomp_,p_done_Z_p_O_FDCinner_prod_qr_decomp_,p_acc_enable_Z_p_O_FDCinner_prod_qr_decomp_,p_desc325_p_O_FDCinner_prod_qr_decomp_,p_desc326_p_O_FDCinner_prod_qr_decomp_,p_desc327_p_O_FDCinner_prod_qr_decomp_,p_desc328_p_O_FDCinner_prod_qr_decomp_,p_desc329_p_O_FDCinner_prod_qr_decomp_,p_desc330_p_O_FDCinner_prod_qr_decomp_,p_desc331_p_O_FDCinner_prod_qr_decomp_,p_desc332_p_O_FDCinner_prod_qr_decomp_,p_desc333_p_O_FDCinner_prod_qr_decomp_,p_desc334_p_O_FDCinner_prod_qr_decomp_,p_desc335_p_O_FDCinner_prod_qr_decomp_,p_desc336_p_O_FDCinner_prod_qr_decomp_,p_desc337_p_O_FDCinner_prod_qr_decomp_,p_desc338_p_O_FDCinner_prod_qr_decomp_,p_desc339_p_O_FDCinner_prod_qr_decomp_,p_desc340_p_O_FDCinner_prod_qr_decomp_,p_desc341_p_O_FDCinner_prod_qr_decomp_,p_desc342_p_O_FDCinner_prod_qr_decomp_,p_desc343_p_O_FDCinner_prod_qr_decomp_,p_desc344_p_O_FDCinner_prod_qr_decomp_,p_desc345_p_O_FDCinner_prod_qr_decomp_,p_desc346_p_O_FDCinner_prod_qr_decomp_,p_desc347_p_O_FDCinner_prod_qr_decomp_,p_desc348_p_O_FDCinner_prod_qr_decomp_,p_desc349_p_O_FDCinner_prod_qr_decomp_,p_desc350_p_O_FDCinner_prod_qr_decomp_,p_desc375_p_O_FDCinner_prod_qr_decomp_,p_desc376_p_O_FDCinner_prod_qr_decomp_,p_desc377_p_O_FDCinner_prod_qr_decomp_,p_desc378_p_O_FDCinner_prod_qr_decomp_,p_desc379_p_O_FDCinner_prod_qr_decomp_,p_desc380_p_O_FDCinner_prod_qr_decomp_,p_desc381_p_O_FDCinner_prod_qr_decomp_,p_desc382_p_O_FDCinner_prod_qr_decomp_,p_desc383_p_O_FDCinner_prod_qr_decomp_,p_desc384_p_O_FDCinner_prod_qr_decomp_,p_desc385_p_O_FDCinner_prod_qr_decomp_,p_desc386_p_O_FDCinner_prod_qr_decomp_,p_desc387_p_O_FDCinner_prod_qr_decomp_,p_desc388_p_O_FDCinner_prod_qr_decomp_,p_desc389_p_O_FDCinner_prod_qr_decomp_,p_desc390_p_O_FDCinner_prod_qr_decomp_,p_desc391_p_O_FDCinner_prod_qr_decomp_,p_desc392_p_O_FDCinner_prod_qr_decomp_,p_desc393_p_O_FDCinner_prod_qr_decomp_,p_desc394_p_O_FDCinner_prod_qr_decomp_,p_desc395_p_O_FDCinner_prod_qr_decomp_,p_desc396_p_O_FDCinner_prod_qr_decomp_,p_desc397_p_O_FDCinner_prod_qr_decomp_,p_desc398_p_O_FDCinner_prod_qr_decomp_,p_done_Z_p_O_FDCinv_sqrt_qr_decomp_,p_desc946_p_O_FDCinv_sqrt_qr_decomp_,p_desc947_p_O_FDCinv_sqrt_qr_decomp_,p_desc948_p_O_FDCinv_sqrt_qr_decomp_,p_desc949_p_O_FDCinv_sqrt_qr_decomp_,p_desc950_p_O_FDCinv_sqrt_qr_decomp_,p_desc1255_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1256_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1257_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1258_p_O_FDCqr_decomp_ctl_qr_decomp_,p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_qr_decomp_,p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_qr_decomp_,p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_qr_decomp_,p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_qr_decomp_,p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1274_p_O_FDCqr_decomp_ctl_qr_decomp_,p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_qr_decomp_,p_done_Z_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1275_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1276_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1277_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1278_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1279_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1281_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1282_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1283_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1284_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1285_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1286_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1287_p_O_FDCqr_decomp_ctl_qr_decomp_,p_desc1288_p_O_FDCqr_decomp_ctl_qr_decomp_,p_start_QR_Z_p_O_FDC,p_wr_A_QR_Z_p_O_FDC,p_valid_out_Z_p_O_FDC,p_ready_Z_p_O_FDC,p_red_mat_reg_Z_p_O_FDC,p_desc1317_p_O_FDC,p_desc1318_p_O_FDC,p_desc1319_p_O_FDC,p_desc1320_p_O_FDC,p_desc1321_p_O_FDC,p_desc1322_p_O_FDC,p_acc_clear_Z_p_O_FDPinner_prod_qr_decomp_,p_desc1265_p_O_FDPqr_decomp_ctl_qr_decomp_,p_desc1268_p_O_FDPqr_decomp_ctl_qr_decomp_,p_desc1280_p_O_FDPqr_decomp_ctl_qr_decomp_,p_desc324_p_O_FDCEinner_prod_qr_decomp_,p_desc351_p_O_FDCEinner_prod_qr_decomp_,p_desc352_p_O_FDCEinner_prod_qr_decomp_,p_desc353_p_O_FDCEinner_prod_qr_decomp_,p_desc354_p_O_FDCEinner_prod_qr_decomp_,p_desc355_p_O_FDCEinner_prod_qr_decomp_,p_desc356_p_O_FDCEinner_prod_qr_decomp_,p_desc357_p_O_FDCEinner_prod_qr_decomp_,p_desc358_p_O_FDCEinner_prod_qr_decomp_,p_desc359_p_O_FDCEinner_prod_qr_decomp_,p_desc360_p_O_FDCEinner_prod_qr_decomp_,p_desc361_p_O_FDCEinner_prod_qr_decomp_,p_desc362_p_O_FDCEinner_prod_qr_decomp_,p_desc363_p_O_FDCEinner_prod_qr_decomp_,p_desc364_p_O_FDCEinner_prod_qr_decomp_,p_desc365_p_O_FDCEinner_prod_qr_decomp_,p_desc366_p_O_FDCEinner_prod_qr_decomp_,p_desc367_p_O_FDCEinner_prod_qr_decomp_,p_desc368_p_O_FDCEinner_prod_qr_decomp_,p_desc369_p_O_FDCEinner_prod_qr_decomp_,p_desc370_p_O_FDCEinner_prod_qr_decomp_,p_desc371_p_O_FDCEinner_prod_qr_decomp_,p_desc372_p_O_FDCEinner_prod_qr_decomp_,p_desc373_p_O_FDCEinner_prod_qr_decomp_,p_desc374_p_O_FDCEinner_prod_qr_decomp_,p_desc1263_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1264_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1266_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1267_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1269_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1270_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1271_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1272_p_O_FDCEqr_decomp_ctl_qr_decomp_,p_desc1273_p_O_FDCEqr_decomp_ctl_qr_decomp_);
output [47:0] out_Q_r ;
output [47:0] out_Q_i ;
output [47:12] out_R_i ;
output [47:0] out_R_r ;
input [47:0] in_A_r ;
input [47:0] in_A_i ;
input clk ;
input rst ;
output valid_out ;
output ready ;
input request_out ;
input start ;
input reduced_matrix ;
wire clk ;
wire rst ;
wire valid_out ;
wire ready ;
wire request_out ;
wire start ;
wire reduced_matrix ;
wire [1:0] col_sel_AQ ;
wire [1:0] col_sel_AQ_4 ;
wire [1:0] col_sel_R ;
wire [1:0] state ;
wire [1:0] state_ns ;
wire start_QR ;
wire start_QR_0 ;
wire wr_A_QR ;
wire wr_A_QR_0 ;
wire valid_out_0 ;
wire ready_0 ;
wire red_mat_reg ;
wire red_mat_reg_0 ;
wire N_14_i ;
wire N_16_i ;
wire N_26 ;
wire done_QR ;
wire N_50 ;
wire N_49 ;
wire N_48 ;
wire N_47 ;
wire GND ;
wire VCC ;
input p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_ ;
input p_desc951_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc952_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc953_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc954_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc955_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc956_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc957_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc958_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc959_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc960_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc961_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc962_p_O_FDEinv_sqrt_qr_decomp_ ;
input p_desc48_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc49_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc50_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc51_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc52_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc53_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc54_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc55_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc56_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc57_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc58_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc59_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc60_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc61_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc62_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc63_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc64_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc65_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc66_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc67_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc68_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc69_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc70_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc71_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc72_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc73_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc74_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc75_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc76_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc77_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc78_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc79_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc80_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc81_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc82_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc83_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc84_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc85_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc86_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc87_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc88_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc89_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc90_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc91_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc92_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc93_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc94_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc95_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc96_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc97_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc98_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc99_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc100_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc101_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc102_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc103_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc104_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc105_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc106_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc107_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc108_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc109_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc110_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc111_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc112_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc113_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc114_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc115_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc116_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc117_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc118_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc119_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc120_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc121_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc122_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc123_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc124_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc125_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc126_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc127_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc128_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc129_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc130_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc131_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc132_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc133_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc134_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc135_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc136_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc137_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc138_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc139_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc140_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc141_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc142_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc143_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc144_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc145_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc146_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc147_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc148_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc149_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc150_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc151_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc152_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc153_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc154_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc155_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc156_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc157_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc158_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc159_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc160_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc161_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc162_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc163_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc164_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc165_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc166_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc167_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc168_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc169_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc170_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc171_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc172_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc173_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc174_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc175_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc176_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc177_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc178_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc179_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc180_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc181_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc182_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc183_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc184_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc185_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc186_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc187_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc188_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc189_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc190_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_desc191_p_O_FDEr_mat_regs_qr_decomp_ ;
input p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_ ;
input p_desc739_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc740_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc741_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc742_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc743_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc744_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc745_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc746_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc747_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc748_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc749_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc750_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc751_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc752_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc753_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc754_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc755_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc756_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc757_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc758_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc759_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc760_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc761_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc762_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc763_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc764_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc765_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc766_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc767_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc768_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc769_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc770_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc771_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc772_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc773_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc774_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc775_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc776_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc777_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc778_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc779_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc780_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc781_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc782_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc783_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc784_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc785_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc786_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc787_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc788_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc789_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc790_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc791_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc792_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc793_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc794_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc795_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc796_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc797_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc798_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc799_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc800_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc801_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc802_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc803_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc804_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc805_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc806_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc807_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc808_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc809_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc810_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc811_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc812_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc813_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc814_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc815_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc816_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc817_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc818_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc819_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc820_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc821_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc822_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc823_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc824_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc825_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc826_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc827_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc828_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc829_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc830_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc831_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc832_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc833_p_O_FDEvec_sub_qr_decomp_ ;
input p_desc834_p_O_FDEvec_sub_qr_decomp_ ;
input p_output_reg_pipe_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_qr_decomp_ ;
input p_desc318_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc319_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc320_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc321_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc322_p_O_FDCinner_prod_qr_decomp_ ;
input p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_qr_decomp_ ;
input p_done_Z_p_O_FDCinner_prod_qr_decomp_ ;
input p_acc_enable_Z_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc325_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc326_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc327_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc328_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc329_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc330_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc331_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc332_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc333_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc334_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc335_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc336_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc337_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc338_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc339_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc340_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc341_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc342_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc343_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc344_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc345_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc346_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc347_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc348_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc349_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc350_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc375_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc376_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc377_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc378_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc379_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc380_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc381_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc382_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc383_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc384_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc385_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc386_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc387_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc388_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc389_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc390_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc391_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc392_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc393_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc394_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc395_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc396_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc397_p_O_FDCinner_prod_qr_decomp_ ;
input p_desc398_p_O_FDCinner_prod_qr_decomp_ ;
input p_done_Z_p_O_FDCinv_sqrt_qr_decomp_ ;
input p_desc946_p_O_FDCinv_sqrt_qr_decomp_ ;
input p_desc947_p_O_FDCinv_sqrt_qr_decomp_ ;
input p_desc948_p_O_FDCinv_sqrt_qr_decomp_ ;
input p_desc949_p_O_FDCinv_sqrt_qr_decomp_ ;
input p_desc950_p_O_FDCinv_sqrt_qr_decomp_ ;
input p_desc1255_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1256_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1257_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1258_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1274_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_done_Z_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1275_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1276_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1277_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1278_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1279_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1281_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1282_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1283_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1284_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1285_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1286_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1287_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_desc1288_p_O_FDCqr_decomp_ctl_qr_decomp_ ;
input p_start_QR_Z_p_O_FDC ;
input p_wr_A_QR_Z_p_O_FDC ;
input p_valid_out_Z_p_O_FDC ;
input p_ready_Z_p_O_FDC ;
input p_red_mat_reg_Z_p_O_FDC ;
input p_desc1317_p_O_FDC ;
input p_desc1318_p_O_FDC ;
input p_desc1319_p_O_FDC ;
input p_desc1320_p_O_FDC ;
input p_desc1321_p_O_FDC ;
input p_desc1322_p_O_FDC ;
input p_acc_clear_Z_p_O_FDPinner_prod_qr_decomp_ ;
input p_desc1265_p_O_FDPqr_decomp_ctl_qr_decomp_ ;
input p_desc1268_p_O_FDPqr_decomp_ctl_qr_decomp_ ;
input p_desc1280_p_O_FDPqr_decomp_ctl_qr_decomp_ ;
input p_desc324_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc351_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc352_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc353_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc354_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc355_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc356_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc357_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc358_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc359_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc360_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc361_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc362_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc363_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc364_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc365_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc366_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc367_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc368_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc369_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc370_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc371_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc372_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc373_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc374_p_O_FDCEinner_prod_qr_decomp_ ;
input p_desc1263_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1264_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1266_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1267_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1269_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1270_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1271_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1272_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
input p_desc1273_p_O_FDCEqr_decomp_ctl_qr_decomp_ ;
// instances
p_O_FDC start_QR_Z(.Q(start_QR),.D(start_QR_0),.C(clk),.CLR(rst),.E(p_start_QR_Z_p_O_FDC));
p_O_FDC wr_A_QR_Z(.Q(wr_A_QR),.D(wr_A_QR_0),.C(clk),.CLR(rst),.E(p_wr_A_QR_Z_p_O_FDC));
p_O_FDC valid_out_Z(.Q(valid_out),.D(valid_out_0),.C(clk),.CLR(rst),.E(p_valid_out_Z_p_O_FDC));
p_O_FDC ready_Z(.Q(ready),.D(ready_0),.C(clk),.CLR(rst),.E(p_ready_Z_p_O_FDC));
p_O_FDC red_mat_reg_Z(.Q(red_mat_reg),.D(red_mat_reg_0),.C(clk),.CLR(rst),.E(p_red_mat_reg_Z_p_O_FDC));
p_O_FDC desc1317(.Q(col_sel_AQ[1:1]),.D(col_sel_AQ_4[1:1]),.C(clk),.CLR(rst),.E(p_desc1317_p_O_FDC));
p_O_FDC desc1318(.Q(col_sel_R[0:0]),.D(N_14_i),.C(clk),.CLR(rst),.E(p_desc1318_p_O_FDC));
p_O_FDC desc1319(.Q(col_sel_R[1:1]),.D(N_16_i),.C(clk),.CLR(rst),.E(p_desc1319_p_O_FDC));
p_O_FDC desc1320(.Q(col_sel_AQ[0:0]),.D(col_sel_AQ_4[0:0]),.C(clk),.CLR(rst),.E(p_desc1320_p_O_FDC));
p_O_FDC desc1321(.Q(state[0:0]),.D(state_ns[0:0]),.C(clk),.CLR(rst),.E(p_desc1321_p_O_FDC));
p_O_FDC desc1322(.Q(state[1:1]),.D(state_ns[1:1]),.C(clk),.CLR(rst),.E(p_desc1322_p_O_FDC));
LUT6_L desc1323(.I0(request_out),.I1(start),.I2(col_sel_AQ[1:1]),.I3(col_sel_AQ[0:0]),.I4(state[0:0]),.I5(state[1:1]),.LO(col_sel_AQ_4[1:1]));
defparam desc1323.INIT=64'h0FF0F0F00FF01010;
LUT6_L start_QR_e(.I0(red_mat_reg),.I1(col_sel_AQ[1:1]),.I2(col_sel_AQ[0:0]),.I3(start_QR),.I4(state[0:0]),.I5(state[1:1]),.LO(start_QR_0));
defparam start_QR_e.INIT=64'hFF000000FFE0FF00;
LUT3 desc1324(.I0(red_mat_reg),.I1(col_sel_AQ[1:1]),.I2(col_sel_AQ[0:0]),.O(N_26));
defparam desc1324.INIT=8'h1F;
LUT5_L ready_e(.I0(request_out),.I1(start),.I2(ready),.I3(state[0:0]),.I4(state[1:1]),.LO(ready_0));
defparam ready_e.INIT=32'hF0F0F011;
LUT5_L red_mat_reg_e(.I0(reduced_matrix),.I1(start),.I2(red_mat_reg),.I3(state[0:0]),.I4(state[1:1]),.LO(red_mat_reg_0));
defparam red_mat_reg_e.INIT=32'hF0F0F0B8;
LUT5_L desc1325(.I0(request_out),.I1(start),.I2(state[0:0]),.I3(state[1:1]),.I4(N_26),.LO(state_ns[0:0]));
defparam desc1325.INIT=32'hF0FE000E;
LUT5_L desc1326(.I0(request_out),.I1(start),.I2(col_sel_AQ[0:0]),.I3(state[0:0]),.I4(state[1:1]),.LO(col_sel_AQ_4[0:0]));
defparam desc1326.INIT=32'h0FF00F10;
LUT6_L desc1327(.I0(request_out),.I1(start),.I2(state[0:0]),.I3(state[1:1]),.I4(col_sel_R[0:0]),.I5(col_sel_R[1:1]),.LO(N_16_i));
defparam desc1327.INIT=64'h0FFDFFFDF0000000;
LUT5_L desc1328(.I0(request_out),.I1(start),.I2(state[0:0]),.I3(state[1:1]),.I4(col_sel_R[0:0]),.LO(N_14_i));
defparam desc1328.INIT=32'h0FFDF000;
LUT6_L valid_out_e(.I0(request_out),.I1(start),.I2(valid_out),.I3(state[0:0]),.I4(state[1:1]),.I5(N_26),.LO(valid_out_0));
defparam valid_out_e.INIT=64'hF0F0F0F200F0F0F2;
LUT6_L desc1329(.I0(request_out),.I1(start),.I2(done_QR),.I3(state[0:0]),.I4(state[1:1]),.I5(N_26),.LO(state_ns[1:1]));
defparam desc1329.INIT=64'hFF0F0022000FFF22;
LUT5_L wr_A_QR_e(.I0(start),.I1(wr_A_QR),.I2(state[0:0]),.I3(state[1:1]),.I4(N_26),.LO(wr_A_QR_0));
defparam wr_A_QR_e.INIT=32'hCCCECC0E;
qr_decomp_inj qr_decomp_inst(.out_Q_r(out_Q_r[47:0]),.out_Q_i(out_Q_i[47:0]),.col_sel_R(col_sel_R[1:0]),.out_R_i(out_R_i[47:12]),.out_R_r(out_R_r[47:0]),.col_sel_AQ(col_sel_AQ[1:0]),.in_A_r(in_A_r[47:0]),.in_A_i(in_A_i[47:0]),.clk(clk),.rst(rst),.wr_A_QR(wr_A_QR),.start_QR(start_QR),.done_QR(done_QR),.red_mat_reg_0(red_mat_reg),.p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_(p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_(p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_(p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_),.p_desc951_p_O_FDEinv_sqrt_(p_desc951_p_O_FDEinv_sqrt_qr_decomp_),.p_desc952_p_O_FDEinv_sqrt_(p_desc952_p_O_FDEinv_sqrt_qr_decomp_),.p_desc953_p_O_FDEinv_sqrt_(p_desc953_p_O_FDEinv_sqrt_qr_decomp_),.p_desc954_p_O_FDEinv_sqrt_(p_desc954_p_O_FDEinv_sqrt_qr_decomp_),.p_desc955_p_O_FDEinv_sqrt_(p_desc955_p_O_FDEinv_sqrt_qr_decomp_),.p_desc956_p_O_FDEinv_sqrt_(p_desc956_p_O_FDEinv_sqrt_qr_decomp_),.p_desc957_p_O_FDEinv_sqrt_(p_desc957_p_O_FDEinv_sqrt_qr_decomp_),.p_desc958_p_O_FDEinv_sqrt_(p_desc958_p_O_FDEinv_sqrt_qr_decomp_),.p_desc959_p_O_FDEinv_sqrt_(p_desc959_p_O_FDEinv_sqrt_qr_decomp_),.p_desc960_p_O_FDEinv_sqrt_(p_desc960_p_O_FDEinv_sqrt_qr_decomp_),.p_desc961_p_O_FDEinv_sqrt_(p_desc961_p_O_FDEinv_sqrt_qr_decomp_),.p_desc962_p_O_FDEinv_sqrt_(p_desc962_p_O_FDEinv_sqrt_qr_decomp_),.p_desc48_p_O_FDEr_mat_regs_(p_desc48_p_O_FDEr_mat_regs_qr_decomp_),.p_desc49_p_O_FDEr_mat_regs_(p_desc49_p_O_FDEr_mat_regs_qr_decomp_),.p_desc50_p_O_FDEr_mat_regs_(p_desc50_p_O_FDEr_mat_regs_qr_decomp_),.p_desc51_p_O_FDEr_mat_regs_(p_desc51_p_O_FDEr_mat_regs_qr_decomp_),.p_desc52_p_O_FDEr_mat_regs_(p_desc52_p_O_FDEr_mat_regs_qr_decomp_),.p_desc53_p_O_FDEr_mat_regs_(p_desc53_p_O_FDEr_mat_regs_qr_decomp_),.p_desc54_p_O_FDEr_mat_regs_(p_desc54_p_O_FDEr_mat_regs_qr_decomp_),.p_desc55_p_O_FDEr_mat_regs_(p_desc55_p_O_FDEr_mat_regs_qr_decomp_),.p_desc56_p_O_FDEr_mat_regs_(p_desc56_p_O_FDEr_mat_regs_qr_decomp_),.p_desc57_p_O_FDEr_mat_regs_(p_desc57_p_O_FDEr_mat_regs_qr_decomp_),.p_desc58_p_O_FDEr_mat_regs_(p_desc58_p_O_FDEr_mat_regs_qr_decomp_),.p_desc59_p_O_FDEr_mat_regs_(p_desc59_p_O_FDEr_mat_regs_qr_decomp_),.p_desc60_p_O_FDEr_mat_regs_(p_desc60_p_O_FDEr_mat_regs_qr_decomp_),.p_desc61_p_O_FDEr_mat_regs_(p_desc61_p_O_FDEr_mat_regs_qr_decomp_),.p_desc62_p_O_FDEr_mat_regs_(p_desc62_p_O_FDEr_mat_regs_qr_decomp_),.p_desc63_p_O_FDEr_mat_regs_(p_desc63_p_O_FDEr_mat_regs_qr_decomp_),.p_desc64_p_O_FDEr_mat_regs_(p_desc64_p_O_FDEr_mat_regs_qr_decomp_),.p_desc65_p_O_FDEr_mat_regs_(p_desc65_p_O_FDEr_mat_regs_qr_decomp_),.p_desc66_p_O_FDEr_mat_regs_(p_desc66_p_O_FDEr_mat_regs_qr_decomp_),.p_desc67_p_O_FDEr_mat_regs_(p_desc67_p_O_FDEr_mat_regs_qr_decomp_),.p_desc68_p_O_FDEr_mat_regs_(p_desc68_p_O_FDEr_mat_regs_qr_decomp_),.p_desc69_p_O_FDEr_mat_regs_(p_desc69_p_O_FDEr_mat_regs_qr_decomp_),.p_desc70_p_O_FDEr_mat_regs_(p_desc70_p_O_FDEr_mat_regs_qr_decomp_),.p_desc71_p_O_FDEr_mat_regs_(p_desc71_p_O_FDEr_mat_regs_qr_decomp_),.p_desc72_p_O_FDEr_mat_regs_(p_desc72_p_O_FDEr_mat_regs_qr_decomp_),.p_desc73_p_O_FDEr_mat_regs_(p_desc73_p_O_FDEr_mat_regs_qr_decomp_),.p_desc74_p_O_FDEr_mat_regs_(p_desc74_p_O_FDEr_mat_regs_qr_decomp_),.p_desc75_p_O_FDEr_mat_regs_(p_desc75_p_O_FDEr_mat_regs_qr_decomp_),.p_desc76_p_O_FDEr_mat_regs_(p_desc76_p_O_FDEr_mat_regs_qr_decomp_),.p_desc77_p_O_FDEr_mat_regs_(p_desc77_p_O_FDEr_mat_regs_qr_decomp_),.p_desc78_p_O_FDEr_mat_regs_(p_desc78_p_O_FDEr_mat_regs_qr_decomp_),.p_desc79_p_O_FDEr_mat_regs_(p_desc79_p_O_FDEr_mat_regs_qr_decomp_),.p_desc80_p_O_FDEr_mat_regs_(p_desc80_p_O_FDEr_mat_regs_qr_decomp_),.p_desc81_p_O_FDEr_mat_regs_(p_desc81_p_O_FDEr_mat_regs_qr_decomp_),.p_desc82_p_O_FDEr_mat_regs_(p_desc82_p_O_FDEr_mat_regs_qr_decomp_),.p_desc83_p_O_FDEr_mat_regs_(p_desc83_p_O_FDEr_mat_regs_qr_decomp_),.p_desc84_p_O_FDEr_mat_regs_(p_desc84_p_O_FDEr_mat_regs_qr_decomp_),.p_desc85_p_O_FDEr_mat_regs_(p_desc85_p_O_FDEr_mat_regs_qr_decomp_),.p_desc86_p_O_FDEr_mat_regs_(p_desc86_p_O_FDEr_mat_regs_qr_decomp_),.p_desc87_p_O_FDEr_mat_regs_(p_desc87_p_O_FDEr_mat_regs_qr_decomp_),.p_desc88_p_O_FDEr_mat_regs_(p_desc88_p_O_FDEr_mat_regs_qr_decomp_),.p_desc89_p_O_FDEr_mat_regs_(p_desc89_p_O_FDEr_mat_regs_qr_decomp_),.p_desc90_p_O_FDEr_mat_regs_(p_desc90_p_O_FDEr_mat_regs_qr_decomp_),.p_desc91_p_O_FDEr_mat_regs_(p_desc91_p_O_FDEr_mat_regs_qr_decomp_),.p_desc92_p_O_FDEr_mat_regs_(p_desc92_p_O_FDEr_mat_regs_qr_decomp_),.p_desc93_p_O_FDEr_mat_regs_(p_desc93_p_O_FDEr_mat_regs_qr_decomp_),.p_desc94_p_O_FDEr_mat_regs_(p_desc94_p_O_FDEr_mat_regs_qr_decomp_),.p_desc95_p_O_FDEr_mat_regs_(p_desc95_p_O_FDEr_mat_regs_qr_decomp_),.p_desc96_p_O_FDEr_mat_regs_(p_desc96_p_O_FDEr_mat_regs_qr_decomp_),.p_desc97_p_O_FDEr_mat_regs_(p_desc97_p_O_FDEr_mat_regs_qr_decomp_),.p_desc98_p_O_FDEr_mat_regs_(p_desc98_p_O_FDEr_mat_regs_qr_decomp_),.p_desc99_p_O_FDEr_mat_regs_(p_desc99_p_O_FDEr_mat_regs_qr_decomp_),.p_desc100_p_O_FDEr_mat_regs_(p_desc100_p_O_FDEr_mat_regs_qr_decomp_),.p_desc101_p_O_FDEr_mat_regs_(p_desc101_p_O_FDEr_mat_regs_qr_decomp_),.p_desc102_p_O_FDEr_mat_regs_(p_desc102_p_O_FDEr_mat_regs_qr_decomp_),.p_desc103_p_O_FDEr_mat_regs_(p_desc103_p_O_FDEr_mat_regs_qr_decomp_),.p_desc104_p_O_FDEr_mat_regs_(p_desc104_p_O_FDEr_mat_regs_qr_decomp_),.p_desc105_p_O_FDEr_mat_regs_(p_desc105_p_O_FDEr_mat_regs_qr_decomp_),.p_desc106_p_O_FDEr_mat_regs_(p_desc106_p_O_FDEr_mat_regs_qr_decomp_),.p_desc107_p_O_FDEr_mat_regs_(p_desc107_p_O_FDEr_mat_regs_qr_decomp_),.p_desc108_p_O_FDEr_mat_regs_(p_desc108_p_O_FDEr_mat_regs_qr_decomp_),.p_desc109_p_O_FDEr_mat_regs_(p_desc109_p_O_FDEr_mat_regs_qr_decomp_),.p_desc110_p_O_FDEr_mat_regs_(p_desc110_p_O_FDEr_mat_regs_qr_decomp_),.p_desc111_p_O_FDEr_mat_regs_(p_desc111_p_O_FDEr_mat_regs_qr_decomp_),.p_desc112_p_O_FDEr_mat_regs_(p_desc112_p_O_FDEr_mat_regs_qr_decomp_),.p_desc113_p_O_FDEr_mat_regs_(p_desc113_p_O_FDEr_mat_regs_qr_decomp_),.p_desc114_p_O_FDEr_mat_regs_(p_desc114_p_O_FDEr_mat_regs_qr_decomp_),.p_desc115_p_O_FDEr_mat_regs_(p_desc115_p_O_FDEr_mat_regs_qr_decomp_),.p_desc116_p_O_FDEr_mat_regs_(p_desc116_p_O_FDEr_mat_regs_qr_decomp_),.p_desc117_p_O_FDEr_mat_regs_(p_desc117_p_O_FDEr_mat_regs_qr_decomp_),.p_desc118_p_O_FDEr_mat_regs_(p_desc118_p_O_FDEr_mat_regs_qr_decomp_),.p_desc119_p_O_FDEr_mat_regs_(p_desc119_p_O_FDEr_mat_regs_qr_decomp_),.p_desc120_p_O_FDEr_mat_regs_(p_desc120_p_O_FDEr_mat_regs_qr_decomp_),.p_desc121_p_O_FDEr_mat_regs_(p_desc121_p_O_FDEr_mat_regs_qr_decomp_),.p_desc122_p_O_FDEr_mat_regs_(p_desc122_p_O_FDEr_mat_regs_qr_decomp_),.p_desc123_p_O_FDEr_mat_regs_(p_desc123_p_O_FDEr_mat_regs_qr_decomp_),.p_desc124_p_O_FDEr_mat_regs_(p_desc124_p_O_FDEr_mat_regs_qr_decomp_),.p_desc125_p_O_FDEr_mat_regs_(p_desc125_p_O_FDEr_mat_regs_qr_decomp_),.p_desc126_p_O_FDEr_mat_regs_(p_desc126_p_O_FDEr_mat_regs_qr_decomp_),.p_desc127_p_O_FDEr_mat_regs_(p_desc127_p_O_FDEr_mat_regs_qr_decomp_),.p_desc128_p_O_FDEr_mat_regs_(p_desc128_p_O_FDEr_mat_regs_qr_decomp_),.p_desc129_p_O_FDEr_mat_regs_(p_desc129_p_O_FDEr_mat_regs_qr_decomp_),.p_desc130_p_O_FDEr_mat_regs_(p_desc130_p_O_FDEr_mat_regs_qr_decomp_),.p_desc131_p_O_FDEr_mat_regs_(p_desc131_p_O_FDEr_mat_regs_qr_decomp_),.p_desc132_p_O_FDEr_mat_regs_(p_desc132_p_O_FDEr_mat_regs_qr_decomp_),.p_desc133_p_O_FDEr_mat_regs_(p_desc133_p_O_FDEr_mat_regs_qr_decomp_),.p_desc134_p_O_FDEr_mat_regs_(p_desc134_p_O_FDEr_mat_regs_qr_decomp_),.p_desc135_p_O_FDEr_mat_regs_(p_desc135_p_O_FDEr_mat_regs_qr_decomp_),.p_desc136_p_O_FDEr_mat_regs_(p_desc136_p_O_FDEr_mat_regs_qr_decomp_),.p_desc137_p_O_FDEr_mat_regs_(p_desc137_p_O_FDEr_mat_regs_qr_decomp_),.p_desc138_p_O_FDEr_mat_regs_(p_desc138_p_O_FDEr_mat_regs_qr_decomp_),.p_desc139_p_O_FDEr_mat_regs_(p_desc139_p_O_FDEr_mat_regs_qr_decomp_),.p_desc140_p_O_FDEr_mat_regs_(p_desc140_p_O_FDEr_mat_regs_qr_decomp_),.p_desc141_p_O_FDEr_mat_regs_(p_desc141_p_O_FDEr_mat_regs_qr_decomp_),.p_desc142_p_O_FDEr_mat_regs_(p_desc142_p_O_FDEr_mat_regs_qr_decomp_),.p_desc143_p_O_FDEr_mat_regs_(p_desc143_p_O_FDEr_mat_regs_qr_decomp_),.p_desc144_p_O_FDEr_mat_regs_(p_desc144_p_O_FDEr_mat_regs_qr_decomp_),.p_desc145_p_O_FDEr_mat_regs_(p_desc145_p_O_FDEr_mat_regs_qr_decomp_),.p_desc146_p_O_FDEr_mat_regs_(p_desc146_p_O_FDEr_mat_regs_qr_decomp_),.p_desc147_p_O_FDEr_mat_regs_(p_desc147_p_O_FDEr_mat_regs_qr_decomp_),.p_desc148_p_O_FDEr_mat_regs_(p_desc148_p_O_FDEr_mat_regs_qr_decomp_),.p_desc149_p_O_FDEr_mat_regs_(p_desc149_p_O_FDEr_mat_regs_qr_decomp_),.p_desc150_p_O_FDEr_mat_regs_(p_desc150_p_O_FDEr_mat_regs_qr_decomp_),.p_desc151_p_O_FDEr_mat_regs_(p_desc151_p_O_FDEr_mat_regs_qr_decomp_),.p_desc152_p_O_FDEr_mat_regs_(p_desc152_p_O_FDEr_mat_regs_qr_decomp_),.p_desc153_p_O_FDEr_mat_regs_(p_desc153_p_O_FDEr_mat_regs_qr_decomp_),.p_desc154_p_O_FDEr_mat_regs_(p_desc154_p_O_FDEr_mat_regs_qr_decomp_),.p_desc155_p_O_FDEr_mat_regs_(p_desc155_p_O_FDEr_mat_regs_qr_decomp_),.p_desc156_p_O_FDEr_mat_regs_(p_desc156_p_O_FDEr_mat_regs_qr_decomp_),.p_desc157_p_O_FDEr_mat_regs_(p_desc157_p_O_FDEr_mat_regs_qr_decomp_),.p_desc158_p_O_FDEr_mat_regs_(p_desc158_p_O_FDEr_mat_regs_qr_decomp_),.p_desc159_p_O_FDEr_mat_regs_(p_desc159_p_O_FDEr_mat_regs_qr_decomp_),.p_desc160_p_O_FDEr_mat_regs_(p_desc160_p_O_FDEr_mat_regs_qr_decomp_),.p_desc161_p_O_FDEr_mat_regs_(p_desc161_p_O_FDEr_mat_regs_qr_decomp_),.p_desc162_p_O_FDEr_mat_regs_(p_desc162_p_O_FDEr_mat_regs_qr_decomp_),.p_desc163_p_O_FDEr_mat_regs_(p_desc163_p_O_FDEr_mat_regs_qr_decomp_),.p_desc164_p_O_FDEr_mat_regs_(p_desc164_p_O_FDEr_mat_regs_qr_decomp_),.p_desc165_p_O_FDEr_mat_regs_(p_desc165_p_O_FDEr_mat_regs_qr_decomp_),.p_desc166_p_O_FDEr_mat_regs_(p_desc166_p_O_FDEr_mat_regs_qr_decomp_),.p_desc167_p_O_FDEr_mat_regs_(p_desc167_p_O_FDEr_mat_regs_qr_decomp_),.p_desc168_p_O_FDEr_mat_regs_(p_desc168_p_O_FDEr_mat_regs_qr_decomp_),.p_desc169_p_O_FDEr_mat_regs_(p_desc169_p_O_FDEr_mat_regs_qr_decomp_),.p_desc170_p_O_FDEr_mat_regs_(p_desc170_p_O_FDEr_mat_regs_qr_decomp_),.p_desc171_p_O_FDEr_mat_regs_(p_desc171_p_O_FDEr_mat_regs_qr_decomp_),.p_desc172_p_O_FDEr_mat_regs_(p_desc172_p_O_FDEr_mat_regs_qr_decomp_),.p_desc173_p_O_FDEr_mat_regs_(p_desc173_p_O_FDEr_mat_regs_qr_decomp_),.p_desc174_p_O_FDEr_mat_regs_(p_desc174_p_O_FDEr_mat_regs_qr_decomp_),.p_desc175_p_O_FDEr_mat_regs_(p_desc175_p_O_FDEr_mat_regs_qr_decomp_),.p_desc176_p_O_FDEr_mat_regs_(p_desc176_p_O_FDEr_mat_regs_qr_decomp_),.p_desc177_p_O_FDEr_mat_regs_(p_desc177_p_O_FDEr_mat_regs_qr_decomp_),.p_desc178_p_O_FDEr_mat_regs_(p_desc178_p_O_FDEr_mat_regs_qr_decomp_),.p_desc179_p_O_FDEr_mat_regs_(p_desc179_p_O_FDEr_mat_regs_qr_decomp_),.p_desc180_p_O_FDEr_mat_regs_(p_desc180_p_O_FDEr_mat_regs_qr_decomp_),.p_desc181_p_O_FDEr_mat_regs_(p_desc181_p_O_FDEr_mat_regs_qr_decomp_),.p_desc182_p_O_FDEr_mat_regs_(p_desc182_p_O_FDEr_mat_regs_qr_decomp_),.p_desc183_p_O_FDEr_mat_regs_(p_desc183_p_O_FDEr_mat_regs_qr_decomp_),.p_desc184_p_O_FDEr_mat_regs_(p_desc184_p_O_FDEr_mat_regs_qr_decomp_),.p_desc185_p_O_FDEr_mat_regs_(p_desc185_p_O_FDEr_mat_regs_qr_decomp_),.p_desc186_p_O_FDEr_mat_regs_(p_desc186_p_O_FDEr_mat_regs_qr_decomp_),.p_desc187_p_O_FDEr_mat_regs_(p_desc187_p_O_FDEr_mat_regs_qr_decomp_),.p_desc188_p_O_FDEr_mat_regs_(p_desc188_p_O_FDEr_mat_regs_qr_decomp_),.p_desc189_p_O_FDEr_mat_regs_(p_desc189_p_O_FDEr_mat_regs_qr_decomp_),.p_desc190_p_O_FDEr_mat_regs_(p_desc190_p_O_FDEr_mat_regs_qr_decomp_),.p_desc191_p_O_FDEr_mat_regs_(p_desc191_p_O_FDEr_mat_regs_qr_decomp_),.p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_(p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_),.p_desc739_p_O_FDEvec_sub_(p_desc739_p_O_FDEvec_sub_qr_decomp_),.p_desc740_p_O_FDEvec_sub_(p_desc740_p_O_FDEvec_sub_qr_decomp_),.p_desc741_p_O_FDEvec_sub_(p_desc741_p_O_FDEvec_sub_qr_decomp_),.p_desc742_p_O_FDEvec_sub_(p_desc742_p_O_FDEvec_sub_qr_decomp_),.p_desc743_p_O_FDEvec_sub_(p_desc743_p_O_FDEvec_sub_qr_decomp_),.p_desc744_p_O_FDEvec_sub_(p_desc744_p_O_FDEvec_sub_qr_decomp_),.p_desc745_p_O_FDEvec_sub_(p_desc745_p_O_FDEvec_sub_qr_decomp_),.p_desc746_p_O_FDEvec_sub_(p_desc746_p_O_FDEvec_sub_qr_decomp_),.p_desc747_p_O_FDEvec_sub_(p_desc747_p_O_FDEvec_sub_qr_decomp_),.p_desc748_p_O_FDEvec_sub_(p_desc748_p_O_FDEvec_sub_qr_decomp_),.p_desc749_p_O_FDEvec_sub_(p_desc749_p_O_FDEvec_sub_qr_decomp_),.p_desc750_p_O_FDEvec_sub_(p_desc750_p_O_FDEvec_sub_qr_decomp_),.p_desc751_p_O_FDEvec_sub_(p_desc751_p_O_FDEvec_sub_qr_decomp_),.p_desc752_p_O_FDEvec_sub_(p_desc752_p_O_FDEvec_sub_qr_decomp_),.p_desc753_p_O_FDEvec_sub_(p_desc753_p_O_FDEvec_sub_qr_decomp_),.p_desc754_p_O_FDEvec_sub_(p_desc754_p_O_FDEvec_sub_qr_decomp_),.p_desc755_p_O_FDEvec_sub_(p_desc755_p_O_FDEvec_sub_qr_decomp_),.p_desc756_p_O_FDEvec_sub_(p_desc756_p_O_FDEvec_sub_qr_decomp_),.p_desc757_p_O_FDEvec_sub_(p_desc757_p_O_FDEvec_sub_qr_decomp_),.p_desc758_p_O_FDEvec_sub_(p_desc758_p_O_FDEvec_sub_qr_decomp_),.p_desc759_p_O_FDEvec_sub_(p_desc759_p_O_FDEvec_sub_qr_decomp_),.p_desc760_p_O_FDEvec_sub_(p_desc760_p_O_FDEvec_sub_qr_decomp_),.p_desc761_p_O_FDEvec_sub_(p_desc761_p_O_FDEvec_sub_qr_decomp_),.p_desc762_p_O_FDEvec_sub_(p_desc762_p_O_FDEvec_sub_qr_decomp_),.p_desc763_p_O_FDEvec_sub_(p_desc763_p_O_FDEvec_sub_qr_decomp_),.p_desc764_p_O_FDEvec_sub_(p_desc764_p_O_FDEvec_sub_qr_decomp_),.p_desc765_p_O_FDEvec_sub_(p_desc765_p_O_FDEvec_sub_qr_decomp_),.p_desc766_p_O_FDEvec_sub_(p_desc766_p_O_FDEvec_sub_qr_decomp_),.p_desc767_p_O_FDEvec_sub_(p_desc767_p_O_FDEvec_sub_qr_decomp_),.p_desc768_p_O_FDEvec_sub_(p_desc768_p_O_FDEvec_sub_qr_decomp_),.p_desc769_p_O_FDEvec_sub_(p_desc769_p_O_FDEvec_sub_qr_decomp_),.p_desc770_p_O_FDEvec_sub_(p_desc770_p_O_FDEvec_sub_qr_decomp_),.p_desc771_p_O_FDEvec_sub_(p_desc771_p_O_FDEvec_sub_qr_decomp_),.p_desc772_p_O_FDEvec_sub_(p_desc772_p_O_FDEvec_sub_qr_decomp_),.p_desc773_p_O_FDEvec_sub_(p_desc773_p_O_FDEvec_sub_qr_decomp_),.p_desc774_p_O_FDEvec_sub_(p_desc774_p_O_FDEvec_sub_qr_decomp_),.p_desc775_p_O_FDEvec_sub_(p_desc775_p_O_FDEvec_sub_qr_decomp_),.p_desc776_p_O_FDEvec_sub_(p_desc776_p_O_FDEvec_sub_qr_decomp_),.p_desc777_p_O_FDEvec_sub_(p_desc777_p_O_FDEvec_sub_qr_decomp_),.p_desc778_p_O_FDEvec_sub_(p_desc778_p_O_FDEvec_sub_qr_decomp_),.p_desc779_p_O_FDEvec_sub_(p_desc779_p_O_FDEvec_sub_qr_decomp_),.p_desc780_p_O_FDEvec_sub_(p_desc780_p_O_FDEvec_sub_qr_decomp_),.p_desc781_p_O_FDEvec_sub_(p_desc781_p_O_FDEvec_sub_qr_decomp_),.p_desc782_p_O_FDEvec_sub_(p_desc782_p_O_FDEvec_sub_qr_decomp_),.p_desc783_p_O_FDEvec_sub_(p_desc783_p_O_FDEvec_sub_qr_decomp_),.p_desc784_p_O_FDEvec_sub_(p_desc784_p_O_FDEvec_sub_qr_decomp_),.p_desc785_p_O_FDEvec_sub_(p_desc785_p_O_FDEvec_sub_qr_decomp_),.p_desc786_p_O_FDEvec_sub_(p_desc786_p_O_FDEvec_sub_qr_decomp_),.p_desc787_p_O_FDEvec_sub_(p_desc787_p_O_FDEvec_sub_qr_decomp_),.p_desc788_p_O_FDEvec_sub_(p_desc788_p_O_FDEvec_sub_qr_decomp_),.p_desc789_p_O_FDEvec_sub_(p_desc789_p_O_FDEvec_sub_qr_decomp_),.p_desc790_p_O_FDEvec_sub_(p_desc790_p_O_FDEvec_sub_qr_decomp_),.p_desc791_p_O_FDEvec_sub_(p_desc791_p_O_FDEvec_sub_qr_decomp_),.p_desc792_p_O_FDEvec_sub_(p_desc792_p_O_FDEvec_sub_qr_decomp_),.p_desc793_p_O_FDEvec_sub_(p_desc793_p_O_FDEvec_sub_qr_decomp_),.p_desc794_p_O_FDEvec_sub_(p_desc794_p_O_FDEvec_sub_qr_decomp_),.p_desc795_p_O_FDEvec_sub_(p_desc795_p_O_FDEvec_sub_qr_decomp_),.p_desc796_p_O_FDEvec_sub_(p_desc796_p_O_FDEvec_sub_qr_decomp_),.p_desc797_p_O_FDEvec_sub_(p_desc797_p_O_FDEvec_sub_qr_decomp_),.p_desc798_p_O_FDEvec_sub_(p_desc798_p_O_FDEvec_sub_qr_decomp_),.p_desc799_p_O_FDEvec_sub_(p_desc799_p_O_FDEvec_sub_qr_decomp_),.p_desc800_p_O_FDEvec_sub_(p_desc800_p_O_FDEvec_sub_qr_decomp_),.p_desc801_p_O_FDEvec_sub_(p_desc801_p_O_FDEvec_sub_qr_decomp_),.p_desc802_p_O_FDEvec_sub_(p_desc802_p_O_FDEvec_sub_qr_decomp_),.p_desc803_p_O_FDEvec_sub_(p_desc803_p_O_FDEvec_sub_qr_decomp_),.p_desc804_p_O_FDEvec_sub_(p_desc804_p_O_FDEvec_sub_qr_decomp_),.p_desc805_p_O_FDEvec_sub_(p_desc805_p_O_FDEvec_sub_qr_decomp_),.p_desc806_p_O_FDEvec_sub_(p_desc806_p_O_FDEvec_sub_qr_decomp_),.p_desc807_p_O_FDEvec_sub_(p_desc807_p_O_FDEvec_sub_qr_decomp_),.p_desc808_p_O_FDEvec_sub_(p_desc808_p_O_FDEvec_sub_qr_decomp_),.p_desc809_p_O_FDEvec_sub_(p_desc809_p_O_FDEvec_sub_qr_decomp_),.p_desc810_p_O_FDEvec_sub_(p_desc810_p_O_FDEvec_sub_qr_decomp_),.p_desc811_p_O_FDEvec_sub_(p_desc811_p_O_FDEvec_sub_qr_decomp_),.p_desc812_p_O_FDEvec_sub_(p_desc812_p_O_FDEvec_sub_qr_decomp_),.p_desc813_p_O_FDEvec_sub_(p_desc813_p_O_FDEvec_sub_qr_decomp_),.p_desc814_p_O_FDEvec_sub_(p_desc814_p_O_FDEvec_sub_qr_decomp_),.p_desc815_p_O_FDEvec_sub_(p_desc815_p_O_FDEvec_sub_qr_decomp_),.p_desc816_p_O_FDEvec_sub_(p_desc816_p_O_FDEvec_sub_qr_decomp_),.p_desc817_p_O_FDEvec_sub_(p_desc817_p_O_FDEvec_sub_qr_decomp_),.p_desc818_p_O_FDEvec_sub_(p_desc818_p_O_FDEvec_sub_qr_decomp_),.p_desc819_p_O_FDEvec_sub_(p_desc819_p_O_FDEvec_sub_qr_decomp_),.p_desc820_p_O_FDEvec_sub_(p_desc820_p_O_FDEvec_sub_qr_decomp_),.p_desc821_p_O_FDEvec_sub_(p_desc821_p_O_FDEvec_sub_qr_decomp_),.p_desc822_p_O_FDEvec_sub_(p_desc822_p_O_FDEvec_sub_qr_decomp_),.p_desc823_p_O_FDEvec_sub_(p_desc823_p_O_FDEvec_sub_qr_decomp_),.p_desc824_p_O_FDEvec_sub_(p_desc824_p_O_FDEvec_sub_qr_decomp_),.p_desc825_p_O_FDEvec_sub_(p_desc825_p_O_FDEvec_sub_qr_decomp_),.p_desc826_p_O_FDEvec_sub_(p_desc826_p_O_FDEvec_sub_qr_decomp_),.p_desc827_p_O_FDEvec_sub_(p_desc827_p_O_FDEvec_sub_qr_decomp_),.p_desc828_p_O_FDEvec_sub_(p_desc828_p_O_FDEvec_sub_qr_decomp_),.p_desc829_p_O_FDEvec_sub_(p_desc829_p_O_FDEvec_sub_qr_decomp_),.p_desc830_p_O_FDEvec_sub_(p_desc830_p_O_FDEvec_sub_qr_decomp_),.p_desc831_p_O_FDEvec_sub_(p_desc831_p_O_FDEvec_sub_qr_decomp_),.p_desc832_p_O_FDEvec_sub_(p_desc832_p_O_FDEvec_sub_qr_decomp_),.p_desc833_p_O_FDEvec_sub_(p_desc833_p_O_FDEvec_sub_qr_decomp_),.p_desc834_p_O_FDEvec_sub_(p_desc834_p_O_FDEvec_sub_qr_decomp_),.p_output_reg_pipe_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_(p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_qr_decomp_),.p_desc318_p_O_FDCinner_prod_(p_desc318_p_O_FDCinner_prod_qr_decomp_),.p_desc319_p_O_FDCinner_prod_(p_desc319_p_O_FDCinner_prod_qr_decomp_),.p_desc320_p_O_FDCinner_prod_(p_desc320_p_O_FDCinner_prod_qr_decomp_),.p_desc321_p_O_FDCinner_prod_(p_desc321_p_O_FDCinner_prod_qr_decomp_),.p_desc322_p_O_FDCinner_prod_(p_desc322_p_O_FDCinner_prod_qr_decomp_),.p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_(p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_qr_decomp_),.p_done_Z_p_O_FDCinner_prod_(p_done_Z_p_O_FDCinner_prod_qr_decomp_),.p_acc_enable_Z_p_O_FDCinner_prod_(p_acc_enable_Z_p_O_FDCinner_prod_qr_decomp_),.p_desc325_p_O_FDCinner_prod_(p_desc325_p_O_FDCinner_prod_qr_decomp_),.p_desc326_p_O_FDCinner_prod_(p_desc326_p_O_FDCinner_prod_qr_decomp_),.p_desc327_p_O_FDCinner_prod_(p_desc327_p_O_FDCinner_prod_qr_decomp_),.p_desc328_p_O_FDCinner_prod_(p_desc328_p_O_FDCinner_prod_qr_decomp_),.p_desc329_p_O_FDCinner_prod_(p_desc329_p_O_FDCinner_prod_qr_decomp_),.p_desc330_p_O_FDCinner_prod_(p_desc330_p_O_FDCinner_prod_qr_decomp_),.p_desc331_p_O_FDCinner_prod_(p_desc331_p_O_FDCinner_prod_qr_decomp_),.p_desc332_p_O_FDCinner_prod_(p_desc332_p_O_FDCinner_prod_qr_decomp_),.p_desc333_p_O_FDCinner_prod_(p_desc333_p_O_FDCinner_prod_qr_decomp_),.p_desc334_p_O_FDCinner_prod_(p_desc334_p_O_FDCinner_prod_qr_decomp_),.p_desc335_p_O_FDCinner_prod_(p_desc335_p_O_FDCinner_prod_qr_decomp_),.p_desc336_p_O_FDCinner_prod_(p_desc336_p_O_FDCinner_prod_qr_decomp_),.p_desc337_p_O_FDCinner_prod_(p_desc337_p_O_FDCinner_prod_qr_decomp_),.p_desc338_p_O_FDCinner_prod_(p_desc338_p_O_FDCinner_prod_qr_decomp_),.p_desc339_p_O_FDCinner_prod_(p_desc339_p_O_FDCinner_prod_qr_decomp_),.p_desc340_p_O_FDCinner_prod_(p_desc340_p_O_FDCinner_prod_qr_decomp_),.p_desc341_p_O_FDCinner_prod_(p_desc341_p_O_FDCinner_prod_qr_decomp_),.p_desc342_p_O_FDCinner_prod_(p_desc342_p_O_FDCinner_prod_qr_decomp_),.p_desc343_p_O_FDCinner_prod_(p_desc343_p_O_FDCinner_prod_qr_decomp_),.p_desc344_p_O_FDCinner_prod_(p_desc344_p_O_FDCinner_prod_qr_decomp_),.p_desc345_p_O_FDCinner_prod_(p_desc345_p_O_FDCinner_prod_qr_decomp_),.p_desc346_p_O_FDCinner_prod_(p_desc346_p_O_FDCinner_prod_qr_decomp_),.p_desc347_p_O_FDCinner_prod_(p_desc347_p_O_FDCinner_prod_qr_decomp_),.p_desc348_p_O_FDCinner_prod_(p_desc348_p_O_FDCinner_prod_qr_decomp_),.p_desc349_p_O_FDCinner_prod_(p_desc349_p_O_FDCinner_prod_qr_decomp_),.p_desc350_p_O_FDCinner_prod_(p_desc350_p_O_FDCinner_prod_qr_decomp_),.p_desc375_p_O_FDCinner_prod_(p_desc375_p_O_FDCinner_prod_qr_decomp_),.p_desc376_p_O_FDCinner_prod_(p_desc376_p_O_FDCinner_prod_qr_decomp_),.p_desc377_p_O_FDCinner_prod_(p_desc377_p_O_FDCinner_prod_qr_decomp_),.p_desc378_p_O_FDCinner_prod_(p_desc378_p_O_FDCinner_prod_qr_decomp_),.p_desc379_p_O_FDCinner_prod_(p_desc379_p_O_FDCinner_prod_qr_decomp_),.p_desc380_p_O_FDCinner_prod_(p_desc380_p_O_FDCinner_prod_qr_decomp_),.p_desc381_p_O_FDCinner_prod_(p_desc381_p_O_FDCinner_prod_qr_decomp_),.p_desc382_p_O_FDCinner_prod_(p_desc382_p_O_FDCinner_prod_qr_decomp_),.p_desc383_p_O_FDCinner_prod_(p_desc383_p_O_FDCinner_prod_qr_decomp_),.p_desc384_p_O_FDCinner_prod_(p_desc384_p_O_FDCinner_prod_qr_decomp_),.p_desc385_p_O_FDCinner_prod_(p_desc385_p_O_FDCinner_prod_qr_decomp_),.p_desc386_p_O_FDCinner_prod_(p_desc386_p_O_FDCinner_prod_qr_decomp_),.p_desc387_p_O_FDCinner_prod_(p_desc387_p_O_FDCinner_prod_qr_decomp_),.p_desc388_p_O_FDCinner_prod_(p_desc388_p_O_FDCinner_prod_qr_decomp_),.p_desc389_p_O_FDCinner_prod_(p_desc389_p_O_FDCinner_prod_qr_decomp_),.p_desc390_p_O_FDCinner_prod_(p_desc390_p_O_FDCinner_prod_qr_decomp_),.p_desc391_p_O_FDCinner_prod_(p_desc391_p_O_FDCinner_prod_qr_decomp_),.p_desc392_p_O_FDCinner_prod_(p_desc392_p_O_FDCinner_prod_qr_decomp_),.p_desc393_p_O_FDCinner_prod_(p_desc393_p_O_FDCinner_prod_qr_decomp_),.p_desc394_p_O_FDCinner_prod_(p_desc394_p_O_FDCinner_prod_qr_decomp_),.p_desc395_p_O_FDCinner_prod_(p_desc395_p_O_FDCinner_prod_qr_decomp_),.p_desc396_p_O_FDCinner_prod_(p_desc396_p_O_FDCinner_prod_qr_decomp_),.p_desc397_p_O_FDCinner_prod_(p_desc397_p_O_FDCinner_prod_qr_decomp_),.p_desc398_p_O_FDCinner_prod_(p_desc398_p_O_FDCinner_prod_qr_decomp_),.p_done_Z_p_O_FDCinv_sqrt_(p_done_Z_p_O_FDCinv_sqrt_qr_decomp_),.p_desc946_p_O_FDCinv_sqrt_(p_desc946_p_O_FDCinv_sqrt_qr_decomp_),.p_desc947_p_O_FDCinv_sqrt_(p_desc947_p_O_FDCinv_sqrt_qr_decomp_),.p_desc948_p_O_FDCinv_sqrt_(p_desc948_p_O_FDCinv_sqrt_qr_decomp_),.p_desc949_p_O_FDCinv_sqrt_(p_desc949_p_O_FDCinv_sqrt_qr_decomp_),.p_desc950_p_O_FDCinv_sqrt_(p_desc950_p_O_FDCinv_sqrt_qr_decomp_),.p_desc1255_p_O_FDCqr_decomp_ctl_(p_desc1255_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1256_p_O_FDCqr_decomp_ctl_(p_desc1256_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1257_p_O_FDCqr_decomp_ctl_(p_desc1257_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1258_p_O_FDCqr_decomp_ctl_(p_desc1258_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_(p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_(p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_(p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_(p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_(p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1274_p_O_FDCqr_decomp_ctl_(p_desc1274_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_(p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_done_Z_p_O_FDCqr_decomp_ctl_(p_done_Z_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1275_p_O_FDCqr_decomp_ctl_(p_desc1275_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1276_p_O_FDCqr_decomp_ctl_(p_desc1276_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1277_p_O_FDCqr_decomp_ctl_(p_desc1277_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1278_p_O_FDCqr_decomp_ctl_(p_desc1278_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1279_p_O_FDCqr_decomp_ctl_(p_desc1279_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1281_p_O_FDCqr_decomp_ctl_(p_desc1281_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1282_p_O_FDCqr_decomp_ctl_(p_desc1282_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1283_p_O_FDCqr_decomp_ctl_(p_desc1283_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1284_p_O_FDCqr_decomp_ctl_(p_desc1284_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1285_p_O_FDCqr_decomp_ctl_(p_desc1285_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1286_p_O_FDCqr_decomp_ctl_(p_desc1286_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1287_p_O_FDCqr_decomp_ctl_(p_desc1287_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_desc1288_p_O_FDCqr_decomp_ctl_(p_desc1288_p_O_FDCqr_decomp_ctl_qr_decomp_),.p_acc_clear_Z_p_O_FDPinner_prod_(p_acc_clear_Z_p_O_FDPinner_prod_qr_decomp_),.p_desc1265_p_O_FDPqr_decomp_ctl_(p_desc1265_p_O_FDPqr_decomp_ctl_qr_decomp_),.p_desc1268_p_O_FDPqr_decomp_ctl_(p_desc1268_p_O_FDPqr_decomp_ctl_qr_decomp_),.p_desc1280_p_O_FDPqr_decomp_ctl_(p_desc1280_p_O_FDPqr_decomp_ctl_qr_decomp_),.p_desc324_p_O_FDCEinner_prod_(p_desc324_p_O_FDCEinner_prod_qr_decomp_),.p_desc351_p_O_FDCEinner_prod_(p_desc351_p_O_FDCEinner_prod_qr_decomp_),.p_desc352_p_O_FDCEinner_prod_(p_desc352_p_O_FDCEinner_prod_qr_decomp_),.p_desc353_p_O_FDCEinner_prod_(p_desc353_p_O_FDCEinner_prod_qr_decomp_),.p_desc354_p_O_FDCEinner_prod_(p_desc354_p_O_FDCEinner_prod_qr_decomp_),.p_desc355_p_O_FDCEinner_prod_(p_desc355_p_O_FDCEinner_prod_qr_decomp_),.p_desc356_p_O_FDCEinner_prod_(p_desc356_p_O_FDCEinner_prod_qr_decomp_),.p_desc357_p_O_FDCEinner_prod_(p_desc357_p_O_FDCEinner_prod_qr_decomp_),.p_desc358_p_O_FDCEinner_prod_(p_desc358_p_O_FDCEinner_prod_qr_decomp_),.p_desc359_p_O_FDCEinner_prod_(p_desc359_p_O_FDCEinner_prod_qr_decomp_),.p_desc360_p_O_FDCEinner_prod_(p_desc360_p_O_FDCEinner_prod_qr_decomp_),.p_desc361_p_O_FDCEinner_prod_(p_desc361_p_O_FDCEinner_prod_qr_decomp_),.p_desc362_p_O_FDCEinner_prod_(p_desc362_p_O_FDCEinner_prod_qr_decomp_),.p_desc363_p_O_FDCEinner_prod_(p_desc363_p_O_FDCEinner_prod_qr_decomp_),.p_desc364_p_O_FDCEinner_prod_(p_desc364_p_O_FDCEinner_prod_qr_decomp_),.p_desc365_p_O_FDCEinner_prod_(p_desc365_p_O_FDCEinner_prod_qr_decomp_),.p_desc366_p_O_FDCEinner_prod_(p_desc366_p_O_FDCEinner_prod_qr_decomp_),.p_desc367_p_O_FDCEinner_prod_(p_desc367_p_O_FDCEinner_prod_qr_decomp_),.p_desc368_p_O_FDCEinner_prod_(p_desc368_p_O_FDCEinner_prod_qr_decomp_),.p_desc369_p_O_FDCEinner_prod_(p_desc369_p_O_FDCEinner_prod_qr_decomp_),.p_desc370_p_O_FDCEinner_prod_(p_desc370_p_O_FDCEinner_prod_qr_decomp_),.p_desc371_p_O_FDCEinner_prod_(p_desc371_p_O_FDCEinner_prod_qr_decomp_),.p_desc372_p_O_FDCEinner_prod_(p_desc372_p_O_FDCEinner_prod_qr_decomp_),.p_desc373_p_O_FDCEinner_prod_(p_desc373_p_O_FDCEinner_prod_qr_decomp_),.p_desc374_p_O_FDCEinner_prod_(p_desc374_p_O_FDCEinner_prod_qr_decomp_),.p_desc1263_p_O_FDCEqr_decomp_ctl_(p_desc1263_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1264_p_O_FDCEqr_decomp_ctl_(p_desc1264_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1266_p_O_FDCEqr_decomp_ctl_(p_desc1266_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1267_p_O_FDCEqr_decomp_ctl_(p_desc1267_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1269_p_O_FDCEqr_decomp_ctl_(p_desc1269_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1270_p_O_FDCEqr_decomp_ctl_(p_desc1270_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1271_p_O_FDCEqr_decomp_ctl_(p_desc1271_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1272_p_O_FDCEqr_decomp_ctl_(p_desc1272_p_O_FDCEqr_decomp_ctl_qr_decomp_),.p_desc1273_p_O_FDCEqr_decomp_ctl_(p_desc1273_p_O_FDCEqr_decomp_ctl_qr_decomp_));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module qr_wrapper_wrapper_inj (clk,rst,reduced_matrix,start,request_out,valid_out,ready,in_A_r,in_A_i,sigma_in,out_Q_r,out_Q_i,out_R_r,out_R_i,permut,p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_desc951_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc952_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc953_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc954_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc955_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc956_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc957_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc958_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc959_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc960_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc961_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc962_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_,p_desc48_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc49_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc50_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc51_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc52_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc53_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc54_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc55_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc56_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc57_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc58_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc59_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc60_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc61_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc62_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc63_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc64_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc65_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc66_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc67_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc68_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc69_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc70_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc71_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc72_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc73_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc74_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc75_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc76_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc77_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc78_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc79_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc80_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc81_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc82_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc83_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc84_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc85_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc86_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc87_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc88_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc89_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc90_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc91_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc92_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc93_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc94_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc95_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc96_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc97_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc98_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc99_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc100_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc101_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc102_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc103_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc104_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc105_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc106_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc107_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc108_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc109_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc110_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc111_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc112_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc113_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc114_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc115_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc116_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc117_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc118_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc119_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc120_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc121_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc122_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc123_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc124_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc125_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc126_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc127_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc128_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc129_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc130_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc131_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc132_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc133_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc134_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc135_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc136_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc137_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc138_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc139_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc140_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc141_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc142_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc143_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc144_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc145_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc146_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc147_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc148_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc149_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc150_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc151_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc152_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc153_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc154_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc155_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc156_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc157_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc158_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc159_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc160_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc161_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc162_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc163_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc164_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc165_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc166_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc167_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc168_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc169_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc170_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc171_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc172_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc173_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc174_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc175_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc176_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc177_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc178_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc179_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc180_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc181_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc182_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc183_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc184_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc185_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc186_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc187_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc188_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc189_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc190_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_desc191_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_,p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_,p_desc739_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc740_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc741_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc742_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc743_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc744_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc745_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc746_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc747_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc748_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc749_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc750_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc751_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc752_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc753_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc754_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc755_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc756_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc757_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc758_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc759_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc760_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc761_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc762_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc763_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc764_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc765_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc766_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc767_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc768_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc769_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc770_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc771_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc772_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc773_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc774_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc775_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc776_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc777_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc778_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc779_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc780_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc781_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc782_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc783_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc784_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc785_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc786_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc787_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc788_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc789_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc790_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc791_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc792_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc793_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc794_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc795_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc796_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc797_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc798_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc799_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc800_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc801_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc802_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc803_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc804_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc805_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc806_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc807_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc808_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc809_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc810_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc811_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc812_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc813_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc814_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc815_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc816_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc817_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc818_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc819_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc820_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc821_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc822_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc823_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc824_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc825_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc826_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc827_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc828_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc829_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc830_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc831_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc832_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc833_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_desc834_p_O_FDEvec_sub_qr_decomp_qr_wrapper_,p_output_reg_pipe_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_,p_desc318_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc319_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc320_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc321_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc322_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_done_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_acc_enable_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc325_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc326_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc327_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc328_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc329_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc330_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc331_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc332_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc333_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc334_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc335_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc336_p_O_FDCinner_prod_qr_decomp_qr_wrapper_,p_desc337_p_O_FDCinner_prod_qr_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_decomp_qr_wrapper_,p_desc368_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_,p_desc369_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_,p_desc370_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_,p_desc371_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_,p_desc372_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_,p_desc373_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_,p_desc374_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_,p_desc1263_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1264_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1266_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1267_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1269_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1270_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1271_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1272_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_,p_desc1273_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_);
input clk ;
input rst ;
input reduced_matrix ;
input start ;
input request_out ;
output valid_out ;
output ready ;
input [47:0] in_A_r ;
input [47:0] in_A_i ;
input [11:0] sigma_in ;
output [47:0] out_Q_r ;
output [47:0] out_Q_i ;
output [47:0] out_R_r ;
output [47:0] out_R_i ;
output [7:0] permut ;
wire clk ;
wire rst ;
wire reduced_matrix ;
wire start ;
wire request_out ;
wire valid_out ;
wire ready ;
wire VCC ;
wire GND ;
input p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc951_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc952_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc953_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc954_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc955_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc956_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc957_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc958_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc959_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc960_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc961_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc962_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc48_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc49_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc50_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc51_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc52_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc53_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc54_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc55_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc56_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc57_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc58_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc59_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc60_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc61_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc62_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc63_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc64_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc65_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc66_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc67_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc68_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc69_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc70_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc71_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc72_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc73_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc74_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc75_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc76_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc77_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc78_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc79_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc80_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc81_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc82_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc83_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc84_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc85_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc86_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc87_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc88_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc89_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc90_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc91_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc92_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc93_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc94_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc95_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc96_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc97_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc98_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc99_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc100_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc101_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc102_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc103_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc104_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc105_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc106_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc107_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc108_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc109_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc110_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc111_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc112_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc113_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc114_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc115_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc116_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc117_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc118_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc119_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc120_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc121_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc122_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc123_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc124_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc125_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc126_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc127_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc128_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc129_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc130_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc131_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc132_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc133_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc134_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc135_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc136_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc137_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc138_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc139_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc140_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc141_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc142_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc143_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc144_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc145_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc146_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc147_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc148_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc149_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc150_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc151_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc152_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc153_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc154_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc155_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc156_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc157_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc158_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc159_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc160_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc161_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc162_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc163_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc164_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc165_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc166_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc167_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc168_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc169_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc170_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc171_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc172_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc173_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc174_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc175_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc176_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc177_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc178_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc179_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc180_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc181_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc182_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc183_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc184_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc185_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc186_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc187_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc188_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc189_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc190_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_desc191_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc739_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc740_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc741_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc742_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc743_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc744_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc745_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc746_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc747_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc748_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc749_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc750_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc751_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc752_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc753_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc754_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc755_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc756_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc757_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc758_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc759_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc760_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc761_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc762_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc763_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc764_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc765_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc766_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc767_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc768_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc769_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc770_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc771_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc772_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc773_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc774_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc775_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc776_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc777_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc778_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc779_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc780_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc781_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc782_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc783_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc784_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc785_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc786_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc787_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc788_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc789_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc790_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc791_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc792_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc793_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc794_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc795_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc796_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc797_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc798_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc799_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc800_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc801_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc802_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc803_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc804_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc805_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc806_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc807_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc808_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc809_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc810_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc811_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc812_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc813_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc814_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc815_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc816_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc817_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc818_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc819_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc820_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc821_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc822_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc823_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc824_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc825_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc826_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc827_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc828_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc829_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc830_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc831_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc832_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc833_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_desc834_p_O_FDEvec_sub_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc318_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc319_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc320_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc321_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc322_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_done_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_acc_enable_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc325_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc326_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc327_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc328_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc329_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc330_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc331_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc332_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc333_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc334_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc335_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc336_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc337_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc338_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc339_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc340_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc341_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc342_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc343_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc344_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc345_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc346_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc347_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc348_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc349_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc350_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc375_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc376_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc377_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc378_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc379_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc380_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc381_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc382_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc383_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc384_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc385_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc386_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc387_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc388_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc389_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc390_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc391_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc392_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc393_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc394_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc395_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc396_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc397_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc398_p_O_FDCinner_prod_qr_decomp_qr_wrapper_ ;
input p_done_Z_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc946_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc947_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc948_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc949_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc950_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_ ;
input p_desc1255_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1256_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1257_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1258_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1274_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_done_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1275_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1276_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1277_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1278_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1279_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1281_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1282_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1283_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1284_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1285_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1286_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1287_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1288_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_start_QR_Z_p_O_FDCqr_wrapper_ ;
input p_wr_A_QR_Z_p_O_FDCqr_wrapper_ ;
input p_valid_out_Z_p_O_FDCqr_wrapper_ ;
input p_ready_Z_p_O_FDCqr_wrapper_ ;
input p_red_mat_reg_Z_p_O_FDCqr_wrapper_ ;
input p_desc1317_p_O_FDCqr_wrapper_ ;
input p_desc1318_p_O_FDCqr_wrapper_ ;
input p_desc1319_p_O_FDCqr_wrapper_ ;
input p_desc1320_p_O_FDCqr_wrapper_ ;
input p_desc1321_p_O_FDCqr_wrapper_ ;
input p_desc1322_p_O_FDCqr_wrapper_ ;
input p_acc_clear_Z_p_O_FDPinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc1265_p_O_FDPqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1268_p_O_FDPqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1280_p_O_FDPqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc324_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc351_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc352_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc353_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc354_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc355_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc356_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc357_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc358_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc359_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc360_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc361_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc362_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc363_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc364_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc365_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc366_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc367_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc368_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc369_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc370_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc371_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc372_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc373_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc374_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_ ;
input p_desc1263_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1264_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1266_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1267_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1269_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1270_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1271_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1272_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
input p_desc1273_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_ ;
// instances
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
qr_wrapper_inj qr_wrapper_inst(.out_Q_r(out_Q_r[47:0]),.out_Q_i(out_Q_i[47:0]),.out_R_i(out_R_i[47:12]),.out_R_r(out_R_r[47:0]),.in_A_r(in_A_r[47:0]),.in_A_i(in_A_i[47:0]),.clk(clk),.rst(rst),.valid_out(valid_out),.ready(ready),.request_out(request_out),.start(start),.reduced_matrix(reduced_matrix),.p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_13_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_12_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_Z_p_O_FDshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_desc951_p_O_FDEinv_sqrt_qr_decomp_(p_desc951_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc952_p_O_FDEinv_sqrt_qr_decomp_(p_desc952_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc953_p_O_FDEinv_sqrt_qr_decomp_(p_desc953_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc954_p_O_FDEinv_sqrt_qr_decomp_(p_desc954_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc955_p_O_FDEinv_sqrt_qr_decomp_(p_desc955_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc956_p_O_FDEinv_sqrt_qr_decomp_(p_desc956_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc957_p_O_FDEinv_sqrt_qr_decomp_(p_desc957_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc958_p_O_FDEinv_sqrt_qr_decomp_(p_desc958_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc959_p_O_FDEinv_sqrt_qr_decomp_(p_desc959_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc960_p_O_FDEinv_sqrt_qr_decomp_(p_desc960_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc961_p_O_FDEinv_sqrt_qr_decomp_(p_desc961_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc962_p_O_FDEinv_sqrt_qr_decomp_(p_desc962_p_O_FDEinv_sqrt_qr_decomp_qr_wrapper_),.p_desc48_p_O_FDEr_mat_regs_qr_decomp_(p_desc48_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc49_p_O_FDEr_mat_regs_qr_decomp_(p_desc49_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc50_p_O_FDEr_mat_regs_qr_decomp_(p_desc50_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc51_p_O_FDEr_mat_regs_qr_decomp_(p_desc51_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc52_p_O_FDEr_mat_regs_qr_decomp_(p_desc52_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc53_p_O_FDEr_mat_regs_qr_decomp_(p_desc53_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc54_p_O_FDEr_mat_regs_qr_decomp_(p_desc54_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc55_p_O_FDEr_mat_regs_qr_decomp_(p_desc55_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc56_p_O_FDEr_mat_regs_qr_decomp_(p_desc56_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc57_p_O_FDEr_mat_regs_qr_decomp_(p_desc57_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc58_p_O_FDEr_mat_regs_qr_decomp_(p_desc58_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc59_p_O_FDEr_mat_regs_qr_decomp_(p_desc59_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc60_p_O_FDEr_mat_regs_qr_decomp_(p_desc60_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc61_p_O_FDEr_mat_regs_qr_decomp_(p_desc61_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc62_p_O_FDEr_mat_regs_qr_decomp_(p_desc62_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc63_p_O_FDEr_mat_regs_qr_decomp_(p_desc63_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc64_p_O_FDEr_mat_regs_qr_decomp_(p_desc64_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc65_p_O_FDEr_mat_regs_qr_decomp_(p_desc65_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc66_p_O_FDEr_mat_regs_qr_decomp_(p_desc66_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc67_p_O_FDEr_mat_regs_qr_decomp_(p_desc67_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc68_p_O_FDEr_mat_regs_qr_decomp_(p_desc68_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc69_p_O_FDEr_mat_regs_qr_decomp_(p_desc69_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc70_p_O_FDEr_mat_regs_qr_decomp_(p_desc70_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc71_p_O_FDEr_mat_regs_qr_decomp_(p_desc71_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc72_p_O_FDEr_mat_regs_qr_decomp_(p_desc72_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc73_p_O_FDEr_mat_regs_qr_decomp_(p_desc73_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc74_p_O_FDEr_mat_regs_qr_decomp_(p_desc74_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc75_p_O_FDEr_mat_regs_qr_decomp_(p_desc75_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc76_p_O_FDEr_mat_regs_qr_decomp_(p_desc76_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc77_p_O_FDEr_mat_regs_qr_decomp_(p_desc77_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc78_p_O_FDEr_mat_regs_qr_decomp_(p_desc78_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc79_p_O_FDEr_mat_regs_qr_decomp_(p_desc79_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc80_p_O_FDEr_mat_regs_qr_decomp_(p_desc80_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc81_p_O_FDEr_mat_regs_qr_decomp_(p_desc81_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc82_p_O_FDEr_mat_regs_qr_decomp_(p_desc82_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc83_p_O_FDEr_mat_regs_qr_decomp_(p_desc83_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc84_p_O_FDEr_mat_regs_qr_decomp_(p_desc84_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc85_p_O_FDEr_mat_regs_qr_decomp_(p_desc85_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc86_p_O_FDEr_mat_regs_qr_decomp_(p_desc86_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc87_p_O_FDEr_mat_regs_qr_decomp_(p_desc87_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc88_p_O_FDEr_mat_regs_qr_decomp_(p_desc88_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc89_p_O_FDEr_mat_regs_qr_decomp_(p_desc89_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc90_p_O_FDEr_mat_regs_qr_decomp_(p_desc90_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc91_p_O_FDEr_mat_regs_qr_decomp_(p_desc91_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc92_p_O_FDEr_mat_regs_qr_decomp_(p_desc92_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc93_p_O_FDEr_mat_regs_qr_decomp_(p_desc93_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc94_p_O_FDEr_mat_regs_qr_decomp_(p_desc94_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc95_p_O_FDEr_mat_regs_qr_decomp_(p_desc95_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc96_p_O_FDEr_mat_regs_qr_decomp_(p_desc96_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc97_p_O_FDEr_mat_regs_qr_decomp_(p_desc97_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc98_p_O_FDEr_mat_regs_qr_decomp_(p_desc98_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc99_p_O_FDEr_mat_regs_qr_decomp_(p_desc99_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc100_p_O_FDEr_mat_regs_qr_decomp_(p_desc100_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc101_p_O_FDEr_mat_regs_qr_decomp_(p_desc101_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc102_p_O_FDEr_mat_regs_qr_decomp_(p_desc102_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc103_p_O_FDEr_mat_regs_qr_decomp_(p_desc103_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc104_p_O_FDEr_mat_regs_qr_decomp_(p_desc104_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc105_p_O_FDEr_mat_regs_qr_decomp_(p_desc105_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc106_p_O_FDEr_mat_regs_qr_decomp_(p_desc106_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc107_p_O_FDEr_mat_regs_qr_decomp_(p_desc107_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc108_p_O_FDEr_mat_regs_qr_decomp_(p_desc108_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc109_p_O_FDEr_mat_regs_qr_decomp_(p_desc109_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc110_p_O_FDEr_mat_regs_qr_decomp_(p_desc110_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc111_p_O_FDEr_mat_regs_qr_decomp_(p_desc111_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc112_p_O_FDEr_mat_regs_qr_decomp_(p_desc112_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc113_p_O_FDEr_mat_regs_qr_decomp_(p_desc113_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc114_p_O_FDEr_mat_regs_qr_decomp_(p_desc114_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc115_p_O_FDEr_mat_regs_qr_decomp_(p_desc115_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc116_p_O_FDEr_mat_regs_qr_decomp_(p_desc116_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc117_p_O_FDEr_mat_regs_qr_decomp_(p_desc117_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc118_p_O_FDEr_mat_regs_qr_decomp_(p_desc118_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc119_p_O_FDEr_mat_regs_qr_decomp_(p_desc119_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc120_p_O_FDEr_mat_regs_qr_decomp_(p_desc120_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc121_p_O_FDEr_mat_regs_qr_decomp_(p_desc121_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc122_p_O_FDEr_mat_regs_qr_decomp_(p_desc122_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc123_p_O_FDEr_mat_regs_qr_decomp_(p_desc123_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc124_p_O_FDEr_mat_regs_qr_decomp_(p_desc124_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc125_p_O_FDEr_mat_regs_qr_decomp_(p_desc125_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc126_p_O_FDEr_mat_regs_qr_decomp_(p_desc126_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc127_p_O_FDEr_mat_regs_qr_decomp_(p_desc127_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc128_p_O_FDEr_mat_regs_qr_decomp_(p_desc128_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc129_p_O_FDEr_mat_regs_qr_decomp_(p_desc129_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc130_p_O_FDEr_mat_regs_qr_decomp_(p_desc130_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc131_p_O_FDEr_mat_regs_qr_decomp_(p_desc131_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc132_p_O_FDEr_mat_regs_qr_decomp_(p_desc132_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc133_p_O_FDEr_mat_regs_qr_decomp_(p_desc133_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc134_p_O_FDEr_mat_regs_qr_decomp_(p_desc134_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc135_p_O_FDEr_mat_regs_qr_decomp_(p_desc135_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc136_p_O_FDEr_mat_regs_qr_decomp_(p_desc136_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc137_p_O_FDEr_mat_regs_qr_decomp_(p_desc137_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc138_p_O_FDEr_mat_regs_qr_decomp_(p_desc138_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc139_p_O_FDEr_mat_regs_qr_decomp_(p_desc139_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc140_p_O_FDEr_mat_regs_qr_decomp_(p_desc140_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc141_p_O_FDEr_mat_regs_qr_decomp_(p_desc141_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc142_p_O_FDEr_mat_regs_qr_decomp_(p_desc142_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc143_p_O_FDEr_mat_regs_qr_decomp_(p_desc143_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc144_p_O_FDEr_mat_regs_qr_decomp_(p_desc144_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc145_p_O_FDEr_mat_regs_qr_decomp_(p_desc145_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc146_p_O_FDEr_mat_regs_qr_decomp_(p_desc146_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc147_p_O_FDEr_mat_regs_qr_decomp_(p_desc147_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc148_p_O_FDEr_mat_regs_qr_decomp_(p_desc148_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc149_p_O_FDEr_mat_regs_qr_decomp_(p_desc149_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc150_p_O_FDEr_mat_regs_qr_decomp_(p_desc150_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc151_p_O_FDEr_mat_regs_qr_decomp_(p_desc151_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc152_p_O_FDEr_mat_regs_qr_decomp_(p_desc152_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc153_p_O_FDEr_mat_regs_qr_decomp_(p_desc153_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc154_p_O_FDEr_mat_regs_qr_decomp_(p_desc154_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc155_p_O_FDEr_mat_regs_qr_decomp_(p_desc155_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc156_p_O_FDEr_mat_regs_qr_decomp_(p_desc156_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc157_p_O_FDEr_mat_regs_qr_decomp_(p_desc157_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc158_p_O_FDEr_mat_regs_qr_decomp_(p_desc158_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc159_p_O_FDEr_mat_regs_qr_decomp_(p_desc159_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc160_p_O_FDEr_mat_regs_qr_decomp_(p_desc160_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc161_p_O_FDEr_mat_regs_qr_decomp_(p_desc161_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc162_p_O_FDEr_mat_regs_qr_decomp_(p_desc162_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc163_p_O_FDEr_mat_regs_qr_decomp_(p_desc163_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc164_p_O_FDEr_mat_regs_qr_decomp_(p_desc164_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc165_p_O_FDEr_mat_regs_qr_decomp_(p_desc165_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc166_p_O_FDEr_mat_regs_qr_decomp_(p_desc166_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc167_p_O_FDEr_mat_regs_qr_decomp_(p_desc167_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc168_p_O_FDEr_mat_regs_qr_decomp_(p_desc168_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc169_p_O_FDEr_mat_regs_qr_decomp_(p_desc169_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc170_p_O_FDEr_mat_regs_qr_decomp_(p_desc170_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc171_p_O_FDEr_mat_regs_qr_decomp_(p_desc171_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc172_p_O_FDEr_mat_regs_qr_decomp_(p_desc172_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc173_p_O_FDEr_mat_regs_qr_decomp_(p_desc173_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc174_p_O_FDEr_mat_regs_qr_decomp_(p_desc174_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc175_p_O_FDEr_mat_regs_qr_decomp_(p_desc175_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc176_p_O_FDEr_mat_regs_qr_decomp_(p_desc176_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc177_p_O_FDEr_mat_regs_qr_decomp_(p_desc177_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc178_p_O_FDEr_mat_regs_qr_decomp_(p_desc178_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc179_p_O_FDEr_mat_regs_qr_decomp_(p_desc179_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc180_p_O_FDEr_mat_regs_qr_decomp_(p_desc180_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc181_p_O_FDEr_mat_regs_qr_decomp_(p_desc181_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc182_p_O_FDEr_mat_regs_qr_decomp_(p_desc182_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc183_p_O_FDEr_mat_regs_qr_decomp_(p_desc183_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc184_p_O_FDEr_mat_regs_qr_decomp_(p_desc184_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc185_p_O_FDEr_mat_regs_qr_decomp_(p_desc185_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc186_p_O_FDEr_mat_regs_qr_decomp_(p_desc186_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc187_p_O_FDEr_mat_regs_qr_decomp_(p_desc187_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc188_p_O_FDEr_mat_regs_qr_decomp_(p_desc188_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc189_p_O_FDEr_mat_regs_qr_decomp_(p_desc189_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc190_p_O_FDEr_mat_regs_qr_decomp_(p_desc190_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_desc191_p_O_FDEr_mat_regs_qr_decomp_(p_desc191_p_O_FDEr_mat_regs_qr_decomp_qr_wrapper_),.p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_1_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_4_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_5_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_6_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_9_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_10_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_11_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_14_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_15_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_16_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_(p_output_reg_pipe_19_Z_p_O_FDEshifterZ0_inv_sqrt_qr_decomp_qr_wrapper_),.p_desc739_p_O_FDEvec_sub_qr_decomp_(p_desc739_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc740_p_O_FDEvec_sub_qr_decomp_(p_desc740_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc741_p_O_FDEvec_sub_qr_decomp_(p_desc741_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc742_p_O_FDEvec_sub_qr_decomp_(p_desc742_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc743_p_O_FDEvec_sub_qr_decomp_(p_desc743_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc744_p_O_FDEvec_sub_qr_decomp_(p_desc744_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc745_p_O_FDEvec_sub_qr_decomp_(p_desc745_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc746_p_O_FDEvec_sub_qr_decomp_(p_desc746_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc747_p_O_FDEvec_sub_qr_decomp_(p_desc747_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc748_p_O_FDEvec_sub_qr_decomp_(p_desc748_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc749_p_O_FDEvec_sub_qr_decomp_(p_desc749_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc750_p_O_FDEvec_sub_qr_decomp_(p_desc750_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc751_p_O_FDEvec_sub_qr_decomp_(p_desc751_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc752_p_O_FDEvec_sub_qr_decomp_(p_desc752_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc753_p_O_FDEvec_sub_qr_decomp_(p_desc753_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc754_p_O_FDEvec_sub_qr_decomp_(p_desc754_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc755_p_O_FDEvec_sub_qr_decomp_(p_desc755_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc756_p_O_FDEvec_sub_qr_decomp_(p_desc756_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc757_p_O_FDEvec_sub_qr_decomp_(p_desc757_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc758_p_O_FDEvec_sub_qr_decomp_(p_desc758_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc759_p_O_FDEvec_sub_qr_decomp_(p_desc759_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc760_p_O_FDEvec_sub_qr_decomp_(p_desc760_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc761_p_O_FDEvec_sub_qr_decomp_(p_desc761_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc762_p_O_FDEvec_sub_qr_decomp_(p_desc762_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc763_p_O_FDEvec_sub_qr_decomp_(p_desc763_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc764_p_O_FDEvec_sub_qr_decomp_(p_desc764_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc765_p_O_FDEvec_sub_qr_decomp_(p_desc765_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc766_p_O_FDEvec_sub_qr_decomp_(p_desc766_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc767_p_O_FDEvec_sub_qr_decomp_(p_desc767_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc768_p_O_FDEvec_sub_qr_decomp_(p_desc768_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc769_p_O_FDEvec_sub_qr_decomp_(p_desc769_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc770_p_O_FDEvec_sub_qr_decomp_(p_desc770_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc771_p_O_FDEvec_sub_qr_decomp_(p_desc771_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc772_p_O_FDEvec_sub_qr_decomp_(p_desc772_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc773_p_O_FDEvec_sub_qr_decomp_(p_desc773_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc774_p_O_FDEvec_sub_qr_decomp_(p_desc774_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc775_p_O_FDEvec_sub_qr_decomp_(p_desc775_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc776_p_O_FDEvec_sub_qr_decomp_(p_desc776_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc777_p_O_FDEvec_sub_qr_decomp_(p_desc777_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc778_p_O_FDEvec_sub_qr_decomp_(p_desc778_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc779_p_O_FDEvec_sub_qr_decomp_(p_desc779_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc780_p_O_FDEvec_sub_qr_decomp_(p_desc780_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc781_p_O_FDEvec_sub_qr_decomp_(p_desc781_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc782_p_O_FDEvec_sub_qr_decomp_(p_desc782_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc783_p_O_FDEvec_sub_qr_decomp_(p_desc783_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc784_p_O_FDEvec_sub_qr_decomp_(p_desc784_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc785_p_O_FDEvec_sub_qr_decomp_(p_desc785_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc786_p_O_FDEvec_sub_qr_decomp_(p_desc786_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc787_p_O_FDEvec_sub_qr_decomp_(p_desc787_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc788_p_O_FDEvec_sub_qr_decomp_(p_desc788_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc789_p_O_FDEvec_sub_qr_decomp_(p_desc789_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc790_p_O_FDEvec_sub_qr_decomp_(p_desc790_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc791_p_O_FDEvec_sub_qr_decomp_(p_desc791_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc792_p_O_FDEvec_sub_qr_decomp_(p_desc792_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc793_p_O_FDEvec_sub_qr_decomp_(p_desc793_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc794_p_O_FDEvec_sub_qr_decomp_(p_desc794_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc795_p_O_FDEvec_sub_qr_decomp_(p_desc795_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc796_p_O_FDEvec_sub_qr_decomp_(p_desc796_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc797_p_O_FDEvec_sub_qr_decomp_(p_desc797_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc798_p_O_FDEvec_sub_qr_decomp_(p_desc798_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc799_p_O_FDEvec_sub_qr_decomp_(p_desc799_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc800_p_O_FDEvec_sub_qr_decomp_(p_desc800_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc801_p_O_FDEvec_sub_qr_decomp_(p_desc801_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc802_p_O_FDEvec_sub_qr_decomp_(p_desc802_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc803_p_O_FDEvec_sub_qr_decomp_(p_desc803_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc804_p_O_FDEvec_sub_qr_decomp_(p_desc804_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc805_p_O_FDEvec_sub_qr_decomp_(p_desc805_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc806_p_O_FDEvec_sub_qr_decomp_(p_desc806_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc807_p_O_FDEvec_sub_qr_decomp_(p_desc807_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc808_p_O_FDEvec_sub_qr_decomp_(p_desc808_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc809_p_O_FDEvec_sub_qr_decomp_(p_desc809_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc810_p_O_FDEvec_sub_qr_decomp_(p_desc810_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc811_p_O_FDEvec_sub_qr_decomp_(p_desc811_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc812_p_O_FDEvec_sub_qr_decomp_(p_desc812_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc813_p_O_FDEvec_sub_qr_decomp_(p_desc813_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc814_p_O_FDEvec_sub_qr_decomp_(p_desc814_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc815_p_O_FDEvec_sub_qr_decomp_(p_desc815_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc816_p_O_FDEvec_sub_qr_decomp_(p_desc816_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc817_p_O_FDEvec_sub_qr_decomp_(p_desc817_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc818_p_O_FDEvec_sub_qr_decomp_(p_desc818_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc819_p_O_FDEvec_sub_qr_decomp_(p_desc819_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc820_p_O_FDEvec_sub_qr_decomp_(p_desc820_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc821_p_O_FDEvec_sub_qr_decomp_(p_desc821_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc822_p_O_FDEvec_sub_qr_decomp_(p_desc822_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc823_p_O_FDEvec_sub_qr_decomp_(p_desc823_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc824_p_O_FDEvec_sub_qr_decomp_(p_desc824_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc825_p_O_FDEvec_sub_qr_decomp_(p_desc825_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc826_p_O_FDEvec_sub_qr_decomp_(p_desc826_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc827_p_O_FDEvec_sub_qr_decomp_(p_desc827_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc828_p_O_FDEvec_sub_qr_decomp_(p_desc828_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc829_p_O_FDEvec_sub_qr_decomp_(p_desc829_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc830_p_O_FDEvec_sub_qr_decomp_(p_desc830_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc831_p_O_FDEvec_sub_qr_decomp_(p_desc831_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc832_p_O_FDEvec_sub_qr_decomp_(p_desc832_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc833_p_O_FDEvec_sub_qr_decomp_(p_desc833_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_desc834_p_O_FDEvec_sub_qr_decomp_(p_desc834_p_O_FDEvec_sub_qr_decomp_qr_wrapper_),.p_output_reg_pipe_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_3_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_6_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_9_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_12_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_15_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_16_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_17_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_18_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_qr_decomp_(p_output_reg_pipe_21_Z_p_O_FDREinv_sqrt_qr_decomp_qr_wrapper_),.p_desc318_p_O_FDCinner_prod_qr_decomp_(p_desc318_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc319_p_O_FDCinner_prod_qr_decomp_(p_desc319_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc320_p_O_FDCinner_prod_qr_decomp_(p_desc320_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc321_p_O_FDCinner_prod_qr_decomp_(p_desc321_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc322_p_O_FDCinner_prod_qr_decomp_(p_desc322_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_qr_decomp_(p_in_reg_enable_fsm_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_done_Z_p_O_FDCinner_prod_qr_decomp_(p_done_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_acc_enable_Z_p_O_FDCinner_prod_qr_decomp_(p_acc_enable_Z_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc325_p_O_FDCinner_prod_qr_decomp_(p_desc325_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc326_p_O_FDCinner_prod_qr_decomp_(p_desc326_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc327_p_O_FDCinner_prod_qr_decomp_(p_desc327_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc328_p_O_FDCinner_prod_qr_decomp_(p_desc328_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc329_p_O_FDCinner_prod_qr_decomp_(p_desc329_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc330_p_O_FDCinner_prod_qr_decomp_(p_desc330_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc331_p_O_FDCinner_prod_qr_decomp_(p_desc331_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc332_p_O_FDCinner_prod_qr_decomp_(p_desc332_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc333_p_O_FDCinner_prod_qr_decomp_(p_desc333_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc334_p_O_FDCinner_prod_qr_decomp_(p_desc334_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc335_p_O_FDCinner_prod_qr_decomp_(p_desc335_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc336_p_O_FDCinner_prod_qr_decomp_(p_desc336_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc337_p_O_FDCinner_prod_qr_decomp_(p_desc337_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc338_p_O_FDCinner_prod_qr_decomp_(p_desc338_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc339_p_O_FDCinner_prod_qr_decomp_(p_desc339_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc340_p_O_FDCinner_prod_qr_decomp_(p_desc340_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc341_p_O_FDCinner_prod_qr_decomp_(p_desc341_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc342_p_O_FDCinner_prod_qr_decomp_(p_desc342_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc343_p_O_FDCinner_prod_qr_decomp_(p_desc343_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc344_p_O_FDCinner_prod_qr_decomp_(p_desc344_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc345_p_O_FDCinner_prod_qr_decomp_(p_desc345_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc346_p_O_FDCinner_prod_qr_decomp_(p_desc346_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc347_p_O_FDCinner_prod_qr_decomp_(p_desc347_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc348_p_O_FDCinner_prod_qr_decomp_(p_desc348_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc349_p_O_FDCinner_prod_qr_decomp_(p_desc349_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc350_p_O_FDCinner_prod_qr_decomp_(p_desc350_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc375_p_O_FDCinner_prod_qr_decomp_(p_desc375_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc376_p_O_FDCinner_prod_qr_decomp_(p_desc376_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc377_p_O_FDCinner_prod_qr_decomp_(p_desc377_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc378_p_O_FDCinner_prod_qr_decomp_(p_desc378_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc379_p_O_FDCinner_prod_qr_decomp_(p_desc379_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc380_p_O_FDCinner_prod_qr_decomp_(p_desc380_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc381_p_O_FDCinner_prod_qr_decomp_(p_desc381_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc382_p_O_FDCinner_prod_qr_decomp_(p_desc382_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc383_p_O_FDCinner_prod_qr_decomp_(p_desc383_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc384_p_O_FDCinner_prod_qr_decomp_(p_desc384_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc385_p_O_FDCinner_prod_qr_decomp_(p_desc385_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc386_p_O_FDCinner_prod_qr_decomp_(p_desc386_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc387_p_O_FDCinner_prod_qr_decomp_(p_desc387_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc388_p_O_FDCinner_prod_qr_decomp_(p_desc388_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc389_p_O_FDCinner_prod_qr_decomp_(p_desc389_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc390_p_O_FDCinner_prod_qr_decomp_(p_desc390_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc391_p_O_FDCinner_prod_qr_decomp_(p_desc391_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc392_p_O_FDCinner_prod_qr_decomp_(p_desc392_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc393_p_O_FDCinner_prod_qr_decomp_(p_desc393_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc394_p_O_FDCinner_prod_qr_decomp_(p_desc394_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc395_p_O_FDCinner_prod_qr_decomp_(p_desc395_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc396_p_O_FDCinner_prod_qr_decomp_(p_desc396_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc397_p_O_FDCinner_prod_qr_decomp_(p_desc397_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_desc398_p_O_FDCinner_prod_qr_decomp_(p_desc398_p_O_FDCinner_prod_qr_decomp_qr_wrapper_),.p_done_Z_p_O_FDCinv_sqrt_qr_decomp_(p_done_Z_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_),.p_desc946_p_O_FDCinv_sqrt_qr_decomp_(p_desc946_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_),.p_desc947_p_O_FDCinv_sqrt_qr_decomp_(p_desc947_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_),.p_desc948_p_O_FDCinv_sqrt_qr_decomp_(p_desc948_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_),.p_desc949_p_O_FDCinv_sqrt_qr_decomp_(p_desc949_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_),.p_desc950_p_O_FDCinv_sqrt_qr_decomp_(p_desc950_p_O_FDCinv_sqrt_qr_decomp_qr_wrapper_),.p_desc1255_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1255_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1256_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1256_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1257_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1257_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1258_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1258_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_qr_decomp_(p_start_inner_prod_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_qr_decomp_(p_wr_en_AQ_int_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_qr_decomp_(p_wr_en_R_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_qr_decomp_(p_w_in_a_vec_sub_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_qr_decomp_(p_start_inv_sqrt_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1274_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1274_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_qr_decomp_(p_pre_red_mat_reg_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_done_Z_p_O_FDCqr_decomp_ctl_qr_decomp_(p_done_Z_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1275_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1275_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1276_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1276_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1277_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1277_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1278_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1278_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1279_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1279_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1281_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1281_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1282_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1282_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1283_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1283_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1284_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1284_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1285_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1285_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1286_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1286_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1287_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1287_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1288_p_O_FDCqr_decomp_ctl_qr_decomp_(p_desc1288_p_O_FDCqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_start_QR_Z_p_O_FDC(p_start_QR_Z_p_O_FDCqr_wrapper_),.p_wr_A_QR_Z_p_O_FDC(p_wr_A_QR_Z_p_O_FDCqr_wrapper_),.p_valid_out_Z_p_O_FDC(p_valid_out_Z_p_O_FDCqr_wrapper_),.p_ready_Z_p_O_FDC(p_ready_Z_p_O_FDCqr_wrapper_),.p_red_mat_reg_Z_p_O_FDC(p_red_mat_reg_Z_p_O_FDCqr_wrapper_),.p_desc1317_p_O_FDC(p_desc1317_p_O_FDCqr_wrapper_),.p_desc1318_p_O_FDC(p_desc1318_p_O_FDCqr_wrapper_),.p_desc1319_p_O_FDC(p_desc1319_p_O_FDCqr_wrapper_),.p_desc1320_p_O_FDC(p_desc1320_p_O_FDCqr_wrapper_),.p_desc1321_p_O_FDC(p_desc1321_p_O_FDCqr_wrapper_),.p_desc1322_p_O_FDC(p_desc1322_p_O_FDCqr_wrapper_),.p_acc_clear_Z_p_O_FDPinner_prod_qr_decomp_(p_acc_clear_Z_p_O_FDPinner_prod_qr_decomp_qr_wrapper_),.p_desc1265_p_O_FDPqr_decomp_ctl_qr_decomp_(p_desc1265_p_O_FDPqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1268_p_O_FDPqr_decomp_ctl_qr_decomp_(p_desc1268_p_O_FDPqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1280_p_O_FDPqr_decomp_ctl_qr_decomp_(p_desc1280_p_O_FDPqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc324_p_O_FDCEinner_prod_qr_decomp_(p_desc324_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc351_p_O_FDCEinner_prod_qr_decomp_(p_desc351_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc352_p_O_FDCEinner_prod_qr_decomp_(p_desc352_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc353_p_O_FDCEinner_prod_qr_decomp_(p_desc353_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc354_p_O_FDCEinner_prod_qr_decomp_(p_desc354_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc355_p_O_FDCEinner_prod_qr_decomp_(p_desc355_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc356_p_O_FDCEinner_prod_qr_decomp_(p_desc356_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc357_p_O_FDCEinner_prod_qr_decomp_(p_desc357_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc358_p_O_FDCEinner_prod_qr_decomp_(p_desc358_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc359_p_O_FDCEinner_prod_qr_decomp_(p_desc359_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc360_p_O_FDCEinner_prod_qr_decomp_(p_desc360_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc361_p_O_FDCEinner_prod_qr_decomp_(p_desc361_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc362_p_O_FDCEinner_prod_qr_decomp_(p_desc362_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc363_p_O_FDCEinner_prod_qr_decomp_(p_desc363_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc364_p_O_FDCEinner_prod_qr_decomp_(p_desc364_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc365_p_O_FDCEinner_prod_qr_decomp_(p_desc365_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc366_p_O_FDCEinner_prod_qr_decomp_(p_desc366_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc367_p_O_FDCEinner_prod_qr_decomp_(p_desc367_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc368_p_O_FDCEinner_prod_qr_decomp_(p_desc368_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc369_p_O_FDCEinner_prod_qr_decomp_(p_desc369_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc370_p_O_FDCEinner_prod_qr_decomp_(p_desc370_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc371_p_O_FDCEinner_prod_qr_decomp_(p_desc371_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc372_p_O_FDCEinner_prod_qr_decomp_(p_desc372_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc373_p_O_FDCEinner_prod_qr_decomp_(p_desc373_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc374_p_O_FDCEinner_prod_qr_decomp_(p_desc374_p_O_FDCEinner_prod_qr_decomp_qr_wrapper_),.p_desc1263_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1263_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1264_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1264_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1266_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1266_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1267_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1267_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1269_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1269_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1270_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1270_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1271_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1271_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1272_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1272_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_),.p_desc1273_p_O_FDCEqr_decomp_ctl_qr_decomp_(p_desc1273_p_O_FDCEqr_decomp_ctl_qr_decomp_qr_wrapper_));
assign out_R_i[0:0]=GND;
assign out_R_i[1:1]=GND;
assign out_R_i[2:2]=GND;
assign out_R_i[3:3]=GND;
assign out_R_i[4:4]=GND;
assign out_R_i[5:5]=GND;
assign out_R_i[6:6]=GND;
assign out_R_i[7:7]=GND;
assign out_R_i[8:8]=GND;
assign out_R_i[9:9]=GND;
assign out_R_i[10:10]=GND;
assign out_R_i[11:11]=GND;
assign permut[0:0]=GND;
assign permut[1:1]=GND;
assign permut[2:2]=GND;
assign permut[3:3]=GND;
assign permut[4:4]=GND;
assign permut[5:5]=GND;
assign permut[6:6]=GND;
assign permut[7:7]=GND;
endmodule
module r_mat_regs_inj (row_sel_R,col_sel_R_mux_i_m3_lut6_2_O6,col_sel_R_mux_i_m3_lut6_2_O5,single_in_r_R_mux,wr_en_AQ_sel,col_sel_R,col_sel_R_int,out_R_i,out_R_r,wr_en_R,N_28_i,clk,N_30_i,N_32_i,N_34_i,N_383_i,N_384_i,N_385_i,N_386_i,N_387_i,N_388_i,N_389_i,N_390_i,N_391_i,N_392_i,N_393_i,N_394_i,N_395_i,N_396_i,N_397_i,N_398_i,N_399_i,N_400_i,N_401_i,p_desc48_p_O_FDE,p_desc49_p_O_FDE,p_desc50_p_O_FDE,p_desc51_p_O_FDE,p_desc52_p_O_FDE,p_desc53_p_O_FDE,p_desc54_p_O_FDE,p_desc55_p_O_FDE,p_desc56_p_O_FDE,p_desc57_p_O_FDE,p_desc58_p_O_FDE,p_desc59_p_O_FDE,p_desc60_p_O_FDE,p_desc61_p_O_FDE,p_desc62_p_O_FDE,p_desc63_p_O_FDE,p_desc64_p_O_FDE,p_desc65_p_O_FDE,p_desc66_p_O_FDE,p_desc67_p_O_FDE,p_desc68_p_O_FDE,p_desc69_p_O_FDE,p_desc70_p_O_FDE,p_desc71_p_O_FDE,p_desc72_p_O_FDE,p_desc73_p_O_FDE,p_desc74_p_O_FDE,p_desc75_p_O_FDE,p_desc76_p_O_FDE,p_desc77_p_O_FDE,p_desc78_p_O_FDE,p_desc79_p_O_FDE,p_desc80_p_O_FDE,p_desc81_p_O_FDE,p_desc82_p_O_FDE,p_desc83_p_O_FDE,p_desc84_p_O_FDE,p_desc85_p_O_FDE,p_desc86_p_O_FDE,p_desc87_p_O_FDE,p_desc88_p_O_FDE,p_desc89_p_O_FDE,p_desc90_p_O_FDE,p_desc91_p_O_FDE,p_desc92_p_O_FDE,p_desc93_p_O_FDE,p_desc94_p_O_FDE,p_desc95_p_O_FDE,p_desc96_p_O_FDE,p_desc97_p_O_FDE,p_desc98_p_O_FDE,p_desc99_p_O_FDE,p_desc100_p_O_FDE,p_desc101_p_O_FDE,p_desc102_p_O_FDE,p_desc103_p_O_FDE,p_desc104_p_O_FDE,p_desc105_p_O_FDE,p_desc106_p_O_FDE,p_desc107_p_O_FDE,p_desc108_p_O_FDE,p_desc109_p_O_FDE,p_desc110_p_O_FDE,p_desc111_p_O_FDE,p_desc112_p_O_FDE,p_desc113_p_O_FDE,p_desc114_p_O_FDE,p_desc115_p_O_FDE,p_desc116_p_O_FDE,p_desc117_p_O_FDE,p_desc118_p_O_FDE,p_desc119_p_O_FDE,p_desc120_p_O_FDE,p_desc121_p_O_FDE,p_desc122_p_O_FDE,p_desc123_p_O_FDE,p_desc124_p_O_FDE,p_desc125_p_O_FDE,p_desc126_p_O_FDE,p_desc127_p_O_FDE,p_desc128_p_O_FDE,p_desc129_p_O_FDE,p_desc130_p_O_FDE,p_desc131_p_O_FDE,p_desc132_p_O_FDE,p_desc133_p_O_FDE,p_desc134_p_O_FDE,p_desc135_p_O_FDE,p_desc136_p_O_FDE,p_desc137_p_O_FDE,p_desc138_p_O_FDE,p_desc139_p_O_FDE,p_desc140_p_O_FDE,p_desc141_p_O_FDE,p_desc142_p_O_FDE,p_desc143_p_O_FDE,p_desc144_p_O_FDE,p_desc145_p_O_FDE,p_desc146_p_O_FDE,p_desc147_p_O_FDE,p_desc148_p_O_FDE,p_desc149_p_O_FDE,p_desc150_p_O_FDE,p_desc151_p_O_FDE,p_desc152_p_O_FDE,p_desc153_p_O_FDE,p_desc154_p_O_FDE,p_desc155_p_O_FDE,p_desc156_p_O_FDE,p_desc157_p_O_FDE,p_desc158_p_O_FDE,p_desc159_p_O_FDE,p_desc160_p_O_FDE,p_desc161_p_O_FDE,p_desc162_p_O_FDE,p_desc163_p_O_FDE,p_desc164_p_O_FDE,p_desc165_p_O_FDE,p_desc166_p_O_FDE,p_desc167_p_O_FDE,p_desc168_p_O_FDE,p_desc169_p_O_FDE,p_desc170_p_O_FDE,p_desc171_p_O_FDE,p_desc172_p_O_FDE,p_desc173_p_O_FDE,p_desc174_p_O_FDE,p_desc175_p_O_FDE,p_desc176_p_O_FDE,p_desc177_p_O_FDE,p_desc178_p_O_FDE,p_desc179_p_O_FDE,p_desc180_p_O_FDE,p_desc181_p_O_FDE,p_desc182_p_O_FDE,p_desc183_p_O_FDE,p_desc184_p_O_FDE,p_desc185_p_O_FDE,p_desc186_p_O_FDE,p_desc187_p_O_FDE,p_desc188_p_O_FDE,p_desc189_p_O_FDE,p_desc190_p_O_FDE,p_desc191_p_O_FDE);
input [1:0] row_sel_R ;
input col_sel_R_mux_i_m3_lut6_2_O6 ;
input col_sel_R_mux_i_m3_lut6_2_O5 ;
input [11:11] single_in_r_R_mux ;
input wr_en_AQ_sel ;
input [1:0] col_sel_R ;
input [1:0] col_sel_R_int ;
output [47:12] out_R_i ;
output [47:0] out_R_r ;
input wr_en_R ;
input N_28_i ;
input clk ;
input N_30_i ;
input N_32_i ;
input N_34_i ;
input N_383_i ;
input N_384_i ;
input N_385_i ;
input N_386_i ;
input N_387_i ;
input N_388_i ;
input N_389_i ;
input N_390_i ;
input N_391_i ;
input N_392_i ;
input N_393_i ;
input N_394_i ;
input N_395_i ;
input N_396_i ;
input N_397_i ;
input N_398_i ;
input N_399_i ;
input N_400_i ;
input N_401_i ;
wire wr_en_R ;
wire N_28_i ;
wire clk ;
wire N_30_i ;
wire N_32_i ;
wire N_34_i ;
wire N_383_i ;
wire N_384_i ;
wire N_385_i ;
wire N_386_i ;
wire N_387_i ;
wire N_388_i ;
wire N_389_i ;
wire N_390_i ;
wire N_391_i ;
wire N_392_i ;
wire N_393_i ;
wire N_394_i ;
wire N_395_i ;
wire N_396_i ;
wire N_397_i ;
wire N_398_i ;
wire N_399_i ;
wire N_400_i ;
wire N_401_i ;
wire [11:0] mat_r_reg_3_3 ;
wire [11:0] mat_r_reg_3_2 ;
wire [11:0] mat_r_reg_3_1 ;
wire [11:0] mat_r_reg_2_2 ;
wire [11:0] mat_r_reg_2_1 ;
wire [11:0] mat_r_reg_1_1 ;
wire [11:0] mat_i_reg_3_2 ;
wire [11:0] mat_i_reg_3_1 ;
wire [11:0] mat_i_reg_3_0 ;
wire [11:0] mat_i_reg_2_1 ;
wire [11:0] mat_i_reg_2_0 ;
wire [11:0] mat_i_reg_1_0 ;
wire VCC ;
wire mat_i_reg_1_0_1_sqmuxa ;
wire mat_i_reg_3_0_1_sqmuxa ;
wire mat_r_reg_1_1_1_sqmuxa ;
wire mat_i_reg_3_1_1_sqmuxa ;
wire mat_i_reg_2_0_1_sqmuxa ;
wire mat_i_reg_3_2_1_sqmuxa ;
wire mat_r_reg_2_2_1_sqmuxa ;
wire mat_r_reg_3_3_1_sqmuxa ;
wire mat_i_reg_2_1_1_sqmuxa ;
wire mat_i_reg_2_1_1_sqmuxa_lut6_2_O5 ;
wire GND ;
input p_desc48_p_O_FDE ;
input p_desc49_p_O_FDE ;
input p_desc50_p_O_FDE ;
input p_desc51_p_O_FDE ;
input p_desc52_p_O_FDE ;
input p_desc53_p_O_FDE ;
input p_desc54_p_O_FDE ;
input p_desc55_p_O_FDE ;
input p_desc56_p_O_FDE ;
input p_desc57_p_O_FDE ;
input p_desc58_p_O_FDE ;
input p_desc59_p_O_FDE ;
input p_desc60_p_O_FDE ;
input p_desc61_p_O_FDE ;
input p_desc62_p_O_FDE ;
input p_desc63_p_O_FDE ;
input p_desc64_p_O_FDE ;
input p_desc65_p_O_FDE ;
input p_desc66_p_O_FDE ;
input p_desc67_p_O_FDE ;
input p_desc68_p_O_FDE ;
input p_desc69_p_O_FDE ;
input p_desc70_p_O_FDE ;
input p_desc71_p_O_FDE ;
input p_desc72_p_O_FDE ;
input p_desc73_p_O_FDE ;
input p_desc74_p_O_FDE ;
input p_desc75_p_O_FDE ;
input p_desc76_p_O_FDE ;
input p_desc77_p_O_FDE ;
input p_desc78_p_O_FDE ;
input p_desc79_p_O_FDE ;
input p_desc80_p_O_FDE ;
input p_desc81_p_O_FDE ;
input p_desc82_p_O_FDE ;
input p_desc83_p_O_FDE ;
input p_desc84_p_O_FDE ;
input p_desc85_p_O_FDE ;
input p_desc86_p_O_FDE ;
input p_desc87_p_O_FDE ;
input p_desc88_p_O_FDE ;
input p_desc89_p_O_FDE ;
input p_desc90_p_O_FDE ;
input p_desc91_p_O_FDE ;
input p_desc92_p_O_FDE ;
input p_desc93_p_O_FDE ;
input p_desc94_p_O_FDE ;
input p_desc95_p_O_FDE ;
input p_desc96_p_O_FDE ;
input p_desc97_p_O_FDE ;
input p_desc98_p_O_FDE ;
input p_desc99_p_O_FDE ;
input p_desc100_p_O_FDE ;
input p_desc101_p_O_FDE ;
input p_desc102_p_O_FDE ;
input p_desc103_p_O_FDE ;
input p_desc104_p_O_FDE ;
input p_desc105_p_O_FDE ;
input p_desc106_p_O_FDE ;
input p_desc107_p_O_FDE ;
input p_desc108_p_O_FDE ;
input p_desc109_p_O_FDE ;
input p_desc110_p_O_FDE ;
input p_desc111_p_O_FDE ;
input p_desc112_p_O_FDE ;
input p_desc113_p_O_FDE ;
input p_desc114_p_O_FDE ;
input p_desc115_p_O_FDE ;
input p_desc116_p_O_FDE ;
input p_desc117_p_O_FDE ;
input p_desc118_p_O_FDE ;
input p_desc119_p_O_FDE ;
input p_desc120_p_O_FDE ;
input p_desc121_p_O_FDE ;
input p_desc122_p_O_FDE ;
input p_desc123_p_O_FDE ;
input p_desc124_p_O_FDE ;
input p_desc125_p_O_FDE ;
input p_desc126_p_O_FDE ;
input p_desc127_p_O_FDE ;
input p_desc128_p_O_FDE ;
input p_desc129_p_O_FDE ;
input p_desc130_p_O_FDE ;
input p_desc131_p_O_FDE ;
input p_desc132_p_O_FDE ;
input p_desc133_p_O_FDE ;
input p_desc134_p_O_FDE ;
input p_desc135_p_O_FDE ;
input p_desc136_p_O_FDE ;
input p_desc137_p_O_FDE ;
input p_desc138_p_O_FDE ;
input p_desc139_p_O_FDE ;
input p_desc140_p_O_FDE ;
input p_desc141_p_O_FDE ;
input p_desc142_p_O_FDE ;
input p_desc143_p_O_FDE ;
input p_desc144_p_O_FDE ;
input p_desc145_p_O_FDE ;
input p_desc146_p_O_FDE ;
input p_desc147_p_O_FDE ;
input p_desc148_p_O_FDE ;
input p_desc149_p_O_FDE ;
input p_desc150_p_O_FDE ;
input p_desc151_p_O_FDE ;
input p_desc152_p_O_FDE ;
input p_desc153_p_O_FDE ;
input p_desc154_p_O_FDE ;
input p_desc155_p_O_FDE ;
input p_desc156_p_O_FDE ;
input p_desc157_p_O_FDE ;
input p_desc158_p_O_FDE ;
input p_desc159_p_O_FDE ;
input p_desc160_p_O_FDE ;
input p_desc161_p_O_FDE ;
input p_desc162_p_O_FDE ;
input p_desc163_p_O_FDE ;
input p_desc164_p_O_FDE ;
input p_desc165_p_O_FDE ;
input p_desc166_p_O_FDE ;
input p_desc167_p_O_FDE ;
input p_desc168_p_O_FDE ;
input p_desc169_p_O_FDE ;
input p_desc170_p_O_FDE ;
input p_desc171_p_O_FDE ;
input p_desc172_p_O_FDE ;
input p_desc173_p_O_FDE ;
input p_desc174_p_O_FDE ;
input p_desc175_p_O_FDE ;
input p_desc176_p_O_FDE ;
input p_desc177_p_O_FDE ;
input p_desc178_p_O_FDE ;
input p_desc179_p_O_FDE ;
input p_desc180_p_O_FDE ;
input p_desc181_p_O_FDE ;
input p_desc182_p_O_FDE ;
input p_desc183_p_O_FDE ;
input p_desc184_p_O_FDE ;
input p_desc185_p_O_FDE ;
input p_desc186_p_O_FDE ;
input p_desc187_p_O_FDE ;
input p_desc188_p_O_FDE ;
input p_desc189_p_O_FDE ;
input p_desc190_p_O_FDE ;
input p_desc191_p_O_FDE ;
// instances
p_O_FDE desc48(.Q(mat_r_reg_3_3[0:0]),.D(N_28_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc48_p_O_FDE));
p_O_FDE desc49(.Q(mat_r_reg_3_3[1:1]),.D(N_30_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc49_p_O_FDE));
p_O_FDE desc50(.Q(mat_r_reg_3_3[2:2]),.D(N_32_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc50_p_O_FDE));
p_O_FDE desc51(.Q(mat_r_reg_3_3[3:3]),.D(N_34_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc51_p_O_FDE));
p_O_FDE desc52(.Q(mat_r_reg_3_3[4:4]),.D(N_383_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc52_p_O_FDE));
p_O_FDE desc53(.Q(mat_r_reg_3_3[5:5]),.D(N_384_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc53_p_O_FDE));
p_O_FDE desc54(.Q(mat_r_reg_3_3[6:6]),.D(N_385_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc54_p_O_FDE));
p_O_FDE desc55(.Q(mat_r_reg_3_3[7:7]),.D(N_386_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc55_p_O_FDE));
p_O_FDE desc56(.Q(mat_r_reg_3_3[8:8]),.D(N_387_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc56_p_O_FDE));
p_O_FDE desc57(.Q(mat_r_reg_3_3[9:9]),.D(N_388_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc57_p_O_FDE));
p_O_FDE desc58(.Q(mat_r_reg_3_3[10:10]),.D(N_389_i),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc58_p_O_FDE));
p_O_FDE desc59(.Q(mat_r_reg_3_3[11:11]),.D(single_in_r_R_mux[11:11]),.C(clk),.CE(mat_r_reg_3_3_1_sqmuxa),.E(p_desc59_p_O_FDE));
p_O_FDE desc60(.Q(mat_r_reg_3_2[0:0]),.D(N_28_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc60_p_O_FDE));
p_O_FDE desc61(.Q(mat_r_reg_3_2[1:1]),.D(N_30_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc61_p_O_FDE));
p_O_FDE desc62(.Q(mat_r_reg_3_2[2:2]),.D(N_32_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc62_p_O_FDE));
p_O_FDE desc63(.Q(mat_r_reg_3_2[3:3]),.D(N_34_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc63_p_O_FDE));
p_O_FDE desc64(.Q(mat_r_reg_3_2[4:4]),.D(N_383_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc64_p_O_FDE));
p_O_FDE desc65(.Q(mat_r_reg_3_2[5:5]),.D(N_384_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc65_p_O_FDE));
p_O_FDE desc66(.Q(mat_r_reg_3_2[6:6]),.D(N_385_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc66_p_O_FDE));
p_O_FDE desc67(.Q(mat_r_reg_3_2[7:7]),.D(N_386_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc67_p_O_FDE));
p_O_FDE desc68(.Q(mat_r_reg_3_2[8:8]),.D(N_387_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc68_p_O_FDE));
p_O_FDE desc69(.Q(mat_r_reg_3_2[9:9]),.D(N_388_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc69_p_O_FDE));
p_O_FDE desc70(.Q(mat_r_reg_3_2[10:10]),.D(N_389_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc70_p_O_FDE));
p_O_FDE desc71(.Q(mat_r_reg_3_2[11:11]),.D(single_in_r_R_mux[11:11]),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc71_p_O_FDE));
p_O_FDE desc72(.Q(mat_r_reg_3_1[0:0]),.D(N_28_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc72_p_O_FDE));
p_O_FDE desc73(.Q(mat_r_reg_3_1[1:1]),.D(N_30_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc73_p_O_FDE));
p_O_FDE desc74(.Q(mat_r_reg_3_1[2:2]),.D(N_32_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc74_p_O_FDE));
p_O_FDE desc75(.Q(mat_r_reg_3_1[3:3]),.D(N_34_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc75_p_O_FDE));
p_O_FDE desc76(.Q(mat_r_reg_3_1[4:4]),.D(N_383_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc76_p_O_FDE));
p_O_FDE desc77(.Q(mat_r_reg_3_1[5:5]),.D(N_384_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc77_p_O_FDE));
p_O_FDE desc78(.Q(mat_r_reg_3_1[6:6]),.D(N_385_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc78_p_O_FDE));
p_O_FDE desc79(.Q(mat_r_reg_3_1[7:7]),.D(N_386_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc79_p_O_FDE));
p_O_FDE desc80(.Q(mat_r_reg_3_1[8:8]),.D(N_387_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc80_p_O_FDE));
p_O_FDE desc81(.Q(mat_r_reg_3_1[9:9]),.D(N_388_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc81_p_O_FDE));
p_O_FDE desc82(.Q(mat_r_reg_3_1[10:10]),.D(N_389_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc82_p_O_FDE));
p_O_FDE desc83(.Q(mat_r_reg_3_1[11:11]),.D(single_in_r_R_mux[11:11]),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc83_p_O_FDE));
p_O_FDE desc84(.Q(mat_r_reg_2_2[0:0]),.D(N_28_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc84_p_O_FDE));
p_O_FDE desc85(.Q(mat_r_reg_2_2[1:1]),.D(N_30_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc85_p_O_FDE));
p_O_FDE desc86(.Q(mat_r_reg_2_2[2:2]),.D(N_32_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc86_p_O_FDE));
p_O_FDE desc87(.Q(mat_r_reg_2_2[3:3]),.D(N_34_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc87_p_O_FDE));
p_O_FDE desc88(.Q(mat_r_reg_2_2[4:4]),.D(N_383_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc88_p_O_FDE));
p_O_FDE desc89(.Q(mat_r_reg_2_2[5:5]),.D(N_384_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc89_p_O_FDE));
p_O_FDE desc90(.Q(mat_r_reg_2_2[6:6]),.D(N_385_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc90_p_O_FDE));
p_O_FDE desc91(.Q(mat_r_reg_2_2[7:7]),.D(N_386_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc91_p_O_FDE));
p_O_FDE desc92(.Q(mat_r_reg_2_2[8:8]),.D(N_387_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc92_p_O_FDE));
p_O_FDE desc93(.Q(mat_r_reg_2_2[9:9]),.D(N_388_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc93_p_O_FDE));
p_O_FDE desc94(.Q(mat_r_reg_2_2[10:10]),.D(N_389_i),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc94_p_O_FDE));
p_O_FDE desc95(.Q(mat_r_reg_2_2[11:11]),.D(single_in_r_R_mux[11:11]),.C(clk),.CE(mat_r_reg_2_2_1_sqmuxa),.E(p_desc95_p_O_FDE));
p_O_FDE desc96(.Q(mat_r_reg_2_1[0:0]),.D(N_28_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc96_p_O_FDE));
p_O_FDE desc97(.Q(mat_r_reg_2_1[1:1]),.D(N_30_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc97_p_O_FDE));
p_O_FDE desc98(.Q(mat_r_reg_2_1[2:2]),.D(N_32_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc98_p_O_FDE));
p_O_FDE desc99(.Q(mat_r_reg_2_1[3:3]),.D(N_34_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc99_p_O_FDE));
p_O_FDE desc100(.Q(mat_r_reg_2_1[4:4]),.D(N_383_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc100_p_O_FDE));
p_O_FDE desc101(.Q(mat_r_reg_2_1[5:5]),.D(N_384_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc101_p_O_FDE));
p_O_FDE desc102(.Q(mat_r_reg_2_1[6:6]),.D(N_385_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc102_p_O_FDE));
p_O_FDE desc103(.Q(mat_r_reg_2_1[7:7]),.D(N_386_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc103_p_O_FDE));
p_O_FDE desc104(.Q(mat_r_reg_2_1[8:8]),.D(N_387_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc104_p_O_FDE));
p_O_FDE desc105(.Q(mat_r_reg_2_1[9:9]),.D(N_388_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc105_p_O_FDE));
p_O_FDE desc106(.Q(mat_r_reg_2_1[10:10]),.D(N_389_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc106_p_O_FDE));
p_O_FDE desc107(.Q(mat_r_reg_2_1[11:11]),.D(single_in_r_R_mux[11:11]),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc107_p_O_FDE));
p_O_FDE desc108(.Q(mat_r_reg_1_1[0:0]),.D(N_28_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc108_p_O_FDE));
p_O_FDE desc109(.Q(mat_r_reg_1_1[1:1]),.D(N_30_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc109_p_O_FDE));
p_O_FDE desc110(.Q(mat_r_reg_1_1[2:2]),.D(N_32_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc110_p_O_FDE));
p_O_FDE desc111(.Q(mat_r_reg_1_1[3:3]),.D(N_34_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc111_p_O_FDE));
p_O_FDE desc112(.Q(mat_r_reg_1_1[4:4]),.D(N_383_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc112_p_O_FDE));
p_O_FDE desc113(.Q(mat_r_reg_1_1[5:5]),.D(N_384_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc113_p_O_FDE));
p_O_FDE desc114(.Q(mat_r_reg_1_1[6:6]),.D(N_385_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc114_p_O_FDE));
p_O_FDE desc115(.Q(mat_r_reg_1_1[7:7]),.D(N_386_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc115_p_O_FDE));
p_O_FDE desc116(.Q(mat_r_reg_1_1[8:8]),.D(N_387_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc116_p_O_FDE));
p_O_FDE desc117(.Q(mat_r_reg_1_1[9:9]),.D(N_388_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc117_p_O_FDE));
p_O_FDE desc118(.Q(mat_r_reg_1_1[10:10]),.D(N_389_i),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc118_p_O_FDE));
p_O_FDE desc119(.Q(mat_r_reg_1_1[11:11]),.D(single_in_r_R_mux[11:11]),.C(clk),.CE(mat_r_reg_1_1_1_sqmuxa),.E(p_desc119_p_O_FDE));
p_O_FDE desc120(.Q(mat_i_reg_3_2[0:0]),.D(N_390_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc120_p_O_FDE));
p_O_FDE desc121(.Q(mat_i_reg_3_2[1:1]),.D(N_391_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc121_p_O_FDE));
p_O_FDE desc122(.Q(mat_i_reg_3_2[2:2]),.D(N_392_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc122_p_O_FDE));
p_O_FDE desc123(.Q(mat_i_reg_3_2[3:3]),.D(N_393_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc123_p_O_FDE));
p_O_FDE desc124(.Q(mat_i_reg_3_2[4:4]),.D(N_394_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc124_p_O_FDE));
p_O_FDE desc125(.Q(mat_i_reg_3_2[5:5]),.D(N_395_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc125_p_O_FDE));
p_O_FDE desc126(.Q(mat_i_reg_3_2[6:6]),.D(N_396_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc126_p_O_FDE));
p_O_FDE desc127(.Q(mat_i_reg_3_2[7:7]),.D(N_397_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc127_p_O_FDE));
p_O_FDE desc128(.Q(mat_i_reg_3_2[8:8]),.D(N_398_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc128_p_O_FDE));
p_O_FDE desc129(.Q(mat_i_reg_3_2[9:9]),.D(N_399_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc129_p_O_FDE));
p_O_FDE desc130(.Q(mat_i_reg_3_2[10:10]),.D(N_400_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc130_p_O_FDE));
p_O_FDE desc131(.Q(mat_i_reg_3_2[11:11]),.D(N_401_i),.C(clk),.CE(mat_i_reg_3_2_1_sqmuxa),.E(p_desc131_p_O_FDE));
p_O_FDE desc132(.Q(mat_i_reg_3_1[0:0]),.D(N_390_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc132_p_O_FDE));
p_O_FDE desc133(.Q(mat_i_reg_3_1[1:1]),.D(N_391_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc133_p_O_FDE));
p_O_FDE desc134(.Q(mat_i_reg_3_1[2:2]),.D(N_392_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc134_p_O_FDE));
p_O_FDE desc135(.Q(mat_i_reg_3_1[3:3]),.D(N_393_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc135_p_O_FDE));
p_O_FDE desc136(.Q(mat_i_reg_3_1[4:4]),.D(N_394_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc136_p_O_FDE));
p_O_FDE desc137(.Q(mat_i_reg_3_1[5:5]),.D(N_395_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc137_p_O_FDE));
p_O_FDE desc138(.Q(mat_i_reg_3_1[6:6]),.D(N_396_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc138_p_O_FDE));
p_O_FDE desc139(.Q(mat_i_reg_3_1[7:7]),.D(N_397_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc139_p_O_FDE));
p_O_FDE desc140(.Q(mat_i_reg_3_1[8:8]),.D(N_398_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc140_p_O_FDE));
p_O_FDE desc141(.Q(mat_i_reg_3_1[9:9]),.D(N_399_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc141_p_O_FDE));
p_O_FDE desc142(.Q(mat_i_reg_3_1[10:10]),.D(N_400_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc142_p_O_FDE));
p_O_FDE desc143(.Q(mat_i_reg_3_1[11:11]),.D(N_401_i),.C(clk),.CE(mat_i_reg_3_1_1_sqmuxa),.E(p_desc143_p_O_FDE));
p_O_FDE desc144(.Q(mat_i_reg_3_0[0:0]),.D(N_390_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc144_p_O_FDE));
p_O_FDE desc145(.Q(mat_i_reg_3_0[1:1]),.D(N_391_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc145_p_O_FDE));
p_O_FDE desc146(.Q(mat_i_reg_3_0[2:2]),.D(N_392_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc146_p_O_FDE));
p_O_FDE desc147(.Q(mat_i_reg_3_0[3:3]),.D(N_393_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc147_p_O_FDE));
p_O_FDE desc148(.Q(mat_i_reg_3_0[4:4]),.D(N_394_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc148_p_O_FDE));
p_O_FDE desc149(.Q(mat_i_reg_3_0[5:5]),.D(N_395_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc149_p_O_FDE));
p_O_FDE desc150(.Q(mat_i_reg_3_0[6:6]),.D(N_396_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc150_p_O_FDE));
p_O_FDE desc151(.Q(mat_i_reg_3_0[7:7]),.D(N_397_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc151_p_O_FDE));
p_O_FDE desc152(.Q(mat_i_reg_3_0[8:8]),.D(N_398_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc152_p_O_FDE));
p_O_FDE desc153(.Q(mat_i_reg_3_0[9:9]),.D(N_399_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc153_p_O_FDE));
p_O_FDE desc154(.Q(mat_i_reg_3_0[10:10]),.D(N_400_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc154_p_O_FDE));
p_O_FDE desc155(.Q(mat_i_reg_3_0[11:11]),.D(N_401_i),.C(clk),.CE(mat_i_reg_3_0_1_sqmuxa),.E(p_desc155_p_O_FDE));
p_O_FDE desc156(.Q(mat_i_reg_2_1[0:0]),.D(N_390_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc156_p_O_FDE));
p_O_FDE desc157(.Q(mat_i_reg_2_1[1:1]),.D(N_391_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc157_p_O_FDE));
p_O_FDE desc158(.Q(mat_i_reg_2_1[2:2]),.D(N_392_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc158_p_O_FDE));
p_O_FDE desc159(.Q(mat_i_reg_2_1[3:3]),.D(N_393_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc159_p_O_FDE));
p_O_FDE desc160(.Q(mat_i_reg_2_1[4:4]),.D(N_394_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc160_p_O_FDE));
p_O_FDE desc161(.Q(mat_i_reg_2_1[5:5]),.D(N_395_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc161_p_O_FDE));
p_O_FDE desc162(.Q(mat_i_reg_2_1[6:6]),.D(N_396_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc162_p_O_FDE));
p_O_FDE desc163(.Q(mat_i_reg_2_1[7:7]),.D(N_397_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc163_p_O_FDE));
p_O_FDE desc164(.Q(mat_i_reg_2_1[8:8]),.D(N_398_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc164_p_O_FDE));
p_O_FDE desc165(.Q(mat_i_reg_2_1[9:9]),.D(N_399_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc165_p_O_FDE));
p_O_FDE desc166(.Q(mat_i_reg_2_1[10:10]),.D(N_400_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc166_p_O_FDE));
p_O_FDE desc167(.Q(mat_i_reg_2_1[11:11]),.D(N_401_i),.C(clk),.CE(mat_i_reg_2_1_1_sqmuxa),.E(p_desc167_p_O_FDE));
p_O_FDE desc168(.Q(mat_i_reg_2_0[0:0]),.D(N_390_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc168_p_O_FDE));
p_O_FDE desc169(.Q(mat_i_reg_2_0[1:1]),.D(N_391_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc169_p_O_FDE));
p_O_FDE desc170(.Q(mat_i_reg_2_0[2:2]),.D(N_392_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc170_p_O_FDE));
p_O_FDE desc171(.Q(mat_i_reg_2_0[3:3]),.D(N_393_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc171_p_O_FDE));
p_O_FDE desc172(.Q(mat_i_reg_2_0[4:4]),.D(N_394_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc172_p_O_FDE));
p_O_FDE desc173(.Q(mat_i_reg_2_0[5:5]),.D(N_395_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc173_p_O_FDE));
p_O_FDE desc174(.Q(mat_i_reg_2_0[6:6]),.D(N_396_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc174_p_O_FDE));
p_O_FDE desc175(.Q(mat_i_reg_2_0[7:7]),.D(N_397_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc175_p_O_FDE));
p_O_FDE desc176(.Q(mat_i_reg_2_0[8:8]),.D(N_398_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc176_p_O_FDE));
p_O_FDE desc177(.Q(mat_i_reg_2_0[9:9]),.D(N_399_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc177_p_O_FDE));
p_O_FDE desc178(.Q(mat_i_reg_2_0[10:10]),.D(N_400_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc178_p_O_FDE));
p_O_FDE desc179(.Q(mat_i_reg_2_0[11:11]),.D(N_401_i),.C(clk),.CE(mat_i_reg_2_0_1_sqmuxa),.E(p_desc179_p_O_FDE));
p_O_FDE desc180(.Q(mat_i_reg_1_0[0:0]),.D(N_390_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc180_p_O_FDE));
p_O_FDE desc181(.Q(mat_i_reg_1_0[1:1]),.D(N_391_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc181_p_O_FDE));
p_O_FDE desc182(.Q(mat_i_reg_1_0[2:2]),.D(N_392_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc182_p_O_FDE));
p_O_FDE desc183(.Q(mat_i_reg_1_0[3:3]),.D(N_393_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc183_p_O_FDE));
p_O_FDE desc184(.Q(mat_i_reg_1_0[4:4]),.D(N_394_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc184_p_O_FDE));
p_O_FDE desc185(.Q(mat_i_reg_1_0[5:5]),.D(N_395_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc185_p_O_FDE));
p_O_FDE desc186(.Q(mat_i_reg_1_0[6:6]),.D(N_396_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc186_p_O_FDE));
p_O_FDE desc187(.Q(mat_i_reg_1_0[7:7]),.D(N_397_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc187_p_O_FDE));
p_O_FDE desc188(.Q(mat_i_reg_1_0[8:8]),.D(N_398_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc188_p_O_FDE));
p_O_FDE desc189(.Q(mat_i_reg_1_0[9:9]),.D(N_399_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc189_p_O_FDE));
p_O_FDE desc190(.Q(mat_i_reg_1_0[10:10]),.D(N_400_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc190_p_O_FDE));
p_O_FDE desc191(.Q(mat_i_reg_1_0[11:11]),.D(N_401_i),.C(clk),.CE(mat_i_reg_1_0_1_sqmuxa),.E(p_desc191_p_O_FDE));
LUT6 desc192(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[0:0]),.I3(mat_r_reg_3_2[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[12:12]));
defparam desc192.INIT=64'hFC300000A820A820;
LUT6 desc193(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[11:11]),.I3(mat_i_reg_3_1[11:11]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[35:35]));
defparam desc193.INIT=64'hFC300000A820A820;
LUT6 desc194(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[10:10]),.I3(mat_i_reg_3_1[10:10]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[34:34]));
defparam desc194.INIT=64'hFC300000A820A820;
LUT6 desc195(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[9:9]),.I3(mat_i_reg_3_1[9:9]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[33:33]));
defparam desc195.INIT=64'hFC300000A820A820;
LUT6 desc196(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[6:6]),.I3(mat_i_reg_3_1[6:6]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[30:30]));
defparam desc196.INIT=64'hFC300000A820A820;
LUT6 desc197(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[5:5]),.I3(mat_i_reg_3_1[5:5]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[29:29]));
defparam desc197.INIT=64'hFC300000A820A820;
LUT6 desc198(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[4:4]),.I3(mat_i_reg_3_1[4:4]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[28:28]));
defparam desc198.INIT=64'hFC300000A820A820;
LUT6 desc199(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[3:3]),.I3(mat_i_reg_3_1[3:3]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[27:27]));
defparam desc199.INIT=64'hFC300000A820A820;
LUT6 desc200(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[2:2]),.I3(mat_i_reg_3_1[2:2]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[26:26]));
defparam desc200.INIT=64'hFC300000A820A820;
LUT6 desc201(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[1:1]),.I3(mat_i_reg_3_1[1:1]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[25:25]));
defparam desc201.INIT=64'hFC300000A820A820;
LUT6 desc202(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[0:0]),.I3(mat_i_reg_3_1[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[24:24]));
defparam desc202.INIT=64'hFC300000A820A820;
LUT6 desc203(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[1:1]),.I3(mat_r_reg_3_2[1:1]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[13:13]));
defparam desc203.INIT=64'hFC300000A820A820;
LUT6 desc204(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[3:3]),.I3(mat_r_reg_3_2[3:3]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[15:15]));
defparam desc204.INIT=64'hFC300000A820A820;
LUT6 desc205(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[2:2]),.I3(mat_r_reg_3_2[2:2]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[14:14]));
defparam desc205.INIT=64'hFC300000A820A820;
LUT6 desc206(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[5:5]),.I3(mat_r_reg_3_2[5:5]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[17:17]));
defparam desc206.INIT=64'hFC300000A820A820;
LUT6 desc207(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[7:7]),.I3(mat_r_reg_3_2[7:7]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[19:19]));
defparam desc207.INIT=64'hFC300000A820A820;
LUT6 desc208(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[6:6]),.I3(mat_r_reg_3_2[6:6]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[18:18]));
defparam desc208.INIT=64'hFC300000A820A820;
LUT6 desc209(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[9:9]),.I3(mat_r_reg_3_2[9:9]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[21:21]));
defparam desc209.INIT=64'hFC300000A820A820;
LUT6 desc210(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[8:8]),.I3(mat_r_reg_3_2[8:8]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[20:20]));
defparam desc210.INIT=64'hFC300000A820A820;
LUT6 desc211(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[11:11]),.I3(mat_r_reg_3_2[11:11]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[23:23]));
defparam desc211.INIT=64'hFC300000A820A820;
LUT6 desc212(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[10:10]),.I3(mat_r_reg_3_2[10:10]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[22:22]));
defparam desc212.INIT=64'hFC300000A820A820;
LUT6 desc213(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[7:7]),.I3(mat_i_reg_3_1[7:7]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[31:31]));
defparam desc213.INIT=64'hFC300000A820A820;
LUT6 desc214(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_r_reg_2_2[4:4]),.I3(mat_r_reg_3_2[4:4]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[16:16]));
defparam desc214.INIT=64'hFC300000A820A820;
LUT6 desc215(.I0(col_sel_R[1:1]),.I1(col_sel_R_mux_i_m3_lut6_2_O6),.I2(mat_i_reg_2_1[8:8]),.I3(mat_i_reg_3_1[8:8]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[32:32]));
defparam desc215.INIT=64'hFC300000A820A820;
LUT6 desc216(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[4:4]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[4:4]));
defparam desc216.INIT=64'hF000000080808080;
LUT6 desc217(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[3:3]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[3:3]));
defparam desc217.INIT=64'hF000000080808080;
LUT6 desc218(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[1:1]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[1:1]));
defparam desc218.INIT=64'hF000000080808080;
LUT6 desc219(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[0:0]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[0:0]));
defparam desc219.INIT=64'hF000000080808080;
LUT6 desc220(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[11:11]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[23:23]));
defparam desc220.INIT=64'hF000000080808080;
LUT6 desc221(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[10:10]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[22:22]));
defparam desc221.INIT=64'hF000000080808080;
LUT6 desc222(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[9:9]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[21:21]));
defparam desc222.INIT=64'hF000000080808080;
LUT6 desc223(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[8:8]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[8:8]));
defparam desc223.INIT=64'hF000000080808080;
LUT6 desc224(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[10:10]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[10:10]));
defparam desc224.INIT=64'hF000000080808080;
LUT6 desc225(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[9:9]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[9:9]));
defparam desc225.INIT=64'hF000000080808080;
LUT6 desc226(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[7:7]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[7:7]));
defparam desc226.INIT=64'hF000000080808080;
LUT6 desc227(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[6:6]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[6:6]));
defparam desc227.INIT=64'hF000000080808080;
LUT6 desc228(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[5:5]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[5:5]));
defparam desc228.INIT=64'hF000000080808080;
LUT6 desc229(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[2:2]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[14:14]));
defparam desc229.INIT=64'hF000000080808080;
LUT6 desc230(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[2:2]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[2:2]));
defparam desc230.INIT=64'hF000000080808080;
LUT6 desc231(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[8:8]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[20:20]));
defparam desc231.INIT=64'hF000000080808080;
LUT6 desc232(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[7:7]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[19:19]));
defparam desc232.INIT=64'hF000000080808080;
LUT6 desc233(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[6:6]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[18:18]));
defparam desc233.INIT=64'hF000000080808080;
LUT6 desc234(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[5:5]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[17:17]));
defparam desc234.INIT=64'hF000000080808080;
LUT6 desc235(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[4:4]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[16:16]));
defparam desc235.INIT=64'hF000000080808080;
LUT6 desc236(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[3:3]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[15:15]));
defparam desc236.INIT=64'hF000000080808080;
LUT6 desc237(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[1:1]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[13:13]));
defparam desc237.INIT=64'hF000000080808080;
LUT6 desc238(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_i_reg_3_2[0:0]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_i[12:12]));
defparam desc238.INIT=64'hF000000080808080;
LUT6 desc239(.I0(col_sel_R[0:0]),.I1(col_sel_R[1:1]),.I2(mat_r_reg_3_3[11:11]),.I3(col_sel_R_int[0:0]),.I4(col_sel_R_int[1:1]),.I5(wr_en_AQ_sel),.O(out_R_r[11:11]));
defparam desc239.INIT=64'hF000000080808080;
LUT5 desc240(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[2:2]),.I3(mat_i_reg_2_0[2:2]),.I4(mat_i_reg_3_0[2:2]),.O(out_R_i[38:38]));
defparam desc240.INIT=32'hECA86420;
LUT5 desc241(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[1:1]),.I3(mat_i_reg_2_0[1:1]),.I4(mat_i_reg_3_0[1:1]),.O(out_R_i[37:37]));
defparam desc241.INIT=32'hECA86420;
LUT5 desc242(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[4:4]),.I3(mat_i_reg_2_0[4:4]),.I4(mat_i_reg_3_0[4:4]),.O(out_R_i[40:40]));
defparam desc242.INIT=32'hECA86420;
LUT5 desc243(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[3:3]),.I3(mat_i_reg_2_0[3:3]),.I4(mat_i_reg_3_0[3:3]),.O(out_R_i[39:39]));
defparam desc243.INIT=32'hECA86420;
LUT5 desc244(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[6:6]),.I3(mat_i_reg_2_0[6:6]),.I4(mat_i_reg_3_0[6:6]),.O(out_R_i[42:42]));
defparam desc244.INIT=32'hECA86420;
LUT5 desc245(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[5:5]),.I3(mat_i_reg_2_0[5:5]),.I4(mat_i_reg_3_0[5:5]),.O(out_R_i[41:41]));
defparam desc245.INIT=32'hECA86420;
LUT5 desc246(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[8:8]),.I3(mat_i_reg_2_0[8:8]),.I4(mat_i_reg_3_0[8:8]),.O(out_R_i[44:44]));
defparam desc246.INIT=32'hECA86420;
LUT5 desc247(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[7:7]),.I3(mat_i_reg_2_0[7:7]),.I4(mat_i_reg_3_0[7:7]),.O(out_R_i[43:43]));
defparam desc247.INIT=32'hECA86420;
LUT5 desc248(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[10:10]),.I3(mat_i_reg_2_0[10:10]),.I4(mat_i_reg_3_0[10:10]),.O(out_R_i[46:46]));
defparam desc248.INIT=32'hECA86420;
LUT5 desc249(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[9:9]),.I3(mat_i_reg_2_0[9:9]),.I4(mat_i_reg_3_0[9:9]),.O(out_R_i[45:45]));
defparam desc249.INIT=32'hECA86420;
LUT5 desc250(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[11:11]),.I3(mat_i_reg_2_0[11:11]),.I4(mat_i_reg_3_0[11:11]),.O(out_R_i[47:47]));
defparam desc250.INIT=32'hECA86420;
LUT5 desc251(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[11:11]),.I3(mat_r_reg_2_1[11:11]),.I4(mat_r_reg_3_1[11:11]),.O(out_R_r[35:35]));
defparam desc251.INIT=32'hECA86420;
LUT5 desc252(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[8:8]),.I3(mat_r_reg_2_1[8:8]),.I4(mat_r_reg_3_1[8:8]),.O(out_R_r[32:32]));
defparam desc252.INIT=32'hECA86420;
LUT5 desc253(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[9:9]),.I3(mat_r_reg_2_1[9:9]),.I4(mat_r_reg_3_1[9:9]),.O(out_R_r[33:33]));
defparam desc253.INIT=32'hECA86420;
LUT5 desc254(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[10:10]),.I3(mat_r_reg_2_1[10:10]),.I4(mat_r_reg_3_1[10:10]),.O(out_R_r[34:34]));
defparam desc254.INIT=32'hECA86420;
LUT5 desc255(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[5:5]),.I3(mat_r_reg_2_1[5:5]),.I4(mat_r_reg_3_1[5:5]),.O(out_R_r[29:29]));
defparam desc255.INIT=32'hECA86420;
LUT5 desc256(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[6:6]),.I3(mat_r_reg_2_1[6:6]),.I4(mat_r_reg_3_1[6:6]),.O(out_R_r[30:30]));
defparam desc256.INIT=32'hECA86420;
LUT5 desc257(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[7:7]),.I3(mat_r_reg_2_1[7:7]),.I4(mat_r_reg_3_1[7:7]),.O(out_R_r[31:31]));
defparam desc257.INIT=32'hECA86420;
LUT5 desc258(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[2:2]),.I3(mat_r_reg_2_1[2:2]),.I4(mat_r_reg_3_1[2:2]),.O(out_R_r[26:26]));
defparam desc258.INIT=32'hECA86420;
LUT5 desc259(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[3:3]),.I3(mat_r_reg_2_1[3:3]),.I4(mat_r_reg_3_1[3:3]),.O(out_R_r[27:27]));
defparam desc259.INIT=32'hECA86420;
LUT5 desc260(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[4:4]),.I3(mat_r_reg_2_1[4:4]),.I4(mat_r_reg_3_1[4:4]),.O(out_R_r[28:28]));
defparam desc260.INIT=32'hECA86420;
LUT5 desc261(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_i_reg_1_0[0:0]),.I3(mat_i_reg_2_0[0:0]),.I4(mat_i_reg_3_0[0:0]),.O(out_R_i[36:36]));
defparam desc261.INIT=32'hECA86420;
LUT5 desc262(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[0:0]),.I3(mat_r_reg_2_1[0:0]),.I4(mat_r_reg_3_1[0:0]),.O(out_R_r[24:24]));
defparam desc262.INIT=32'hECA86420;
LUT5 desc263(.I0(col_sel_R_mux_i_m3_lut6_2_O6),.I1(col_sel_R_mux_i_m3_lut6_2_O5),.I2(mat_r_reg_1_1[1:1]),.I3(mat_r_reg_2_1[1:1]),.I4(mat_r_reg_3_1[1:1]),.O(out_R_r[25:25]));
defparam desc263.INIT=32'hECA86420;
RAM32X1S mat_r_reg_0_mat_r_reg_0_11_0(.O(out_R_r[47:47]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(single_in_r_R_mux[11:11]),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_10_0(.O(out_R_r[46:46]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_389_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_9_0(.O(out_R_r[45:45]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_388_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_8_0(.O(out_R_r[44:44]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_387_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_7_0(.O(out_R_r[43:43]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_386_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_6_0(.O(out_R_r[42:42]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_385_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_5_0(.O(out_R_r[41:41]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_384_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_4_0(.O(out_R_r[40:40]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_383_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_3_0(.O(out_R_r[39:39]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_34_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_2_0(.O(out_R_r[38:38]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_32_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_1_0(.O(out_R_r[37:37]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_30_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
RAM32X1S mat_r_reg_0_mat_r_reg_0_0_0(.O(out_R_r[36:36]),.A0(col_sel_R_mux_i_m3_lut6_2_O6),.A1(col_sel_R_mux_i_m3_lut6_2_O5),.A2(GND),.A3(GND),.A4(GND),.D(N_28_i),.WCLK(clk),.WE(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT5 mat_i_reg_2_1_1_sqmuxa_lut6_2_o6(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_i_reg_2_1_1_sqmuxa));
defparam mat_i_reg_2_1_1_sqmuxa_lut6_2_o6.INIT=32'h00200000;
LUT3 mat_i_reg_2_1_1_sqmuxa_lut6_2_o5(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.O(mat_i_reg_2_1_1_sqmuxa_lut6_2_O5));
defparam mat_i_reg_2_1_1_sqmuxa_lut6_2_o5.INIT=8'h10;
LUT5 mat_r_reg_2_2_1_sqmuxa_lut6_2_o6(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_r_reg_2_2_1_sqmuxa));
defparam mat_r_reg_2_2_1_sqmuxa_lut6_2_o6.INIT=32'h00400000;
LUT5 mat_r_reg_2_2_1_sqmuxa_lut6_2_o5(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_r_reg_3_3_1_sqmuxa));
defparam mat_r_reg_2_2_1_sqmuxa_lut6_2_o5.INIT=32'h80000000;
LUT5 mat_i_reg_2_0_1_sqmuxa_lut6_2_o6(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_i_reg_2_0_1_sqmuxa));
defparam mat_i_reg_2_0_1_sqmuxa_lut6_2_o6.INIT=32'h00100000;
LUT5 mat_i_reg_2_0_1_sqmuxa_lut6_2_o5(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_i_reg_3_2_1_sqmuxa));
defparam mat_i_reg_2_0_1_sqmuxa_lut6_2_o5.INIT=32'h40000000;
LUT5 mat_r_reg_1_1_1_sqmuxa_lut6_2_o6(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_r_reg_1_1_1_sqmuxa));
defparam mat_r_reg_1_1_1_sqmuxa_lut6_2_o6.INIT=32'h00002000;
LUT5 mat_r_reg_1_1_1_sqmuxa_lut6_2_o5(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_i_reg_3_1_1_sqmuxa));
defparam mat_r_reg_1_1_1_sqmuxa_lut6_2_o5.INIT=32'h20000000;
LUT5 mat_i_reg_1_0_1_sqmuxa_lut6_2_o6(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_i_reg_1_0_1_sqmuxa));
defparam mat_i_reg_1_0_1_sqmuxa_lut6_2_o6.INIT=32'h00001000;
LUT5 mat_i_reg_1_0_1_sqmuxa_lut6_2_o5(.I0(row_sel_R[0:0]),.I1(row_sel_R[1:1]),.I2(wr_en_R),.I3(col_sel_R_mux_i_m3_lut6_2_O6),.I4(col_sel_R_mux_i_m3_lut6_2_O5),.O(mat_i_reg_3_0_1_sqmuxa));
defparam mat_i_reg_1_0_1_sqmuxa_lut6_2_o5.INIT=32'h10000000;
endmodule
module shifterZ0_inj (input_reg,shift_amount_1,un14_pos_output,ret_val,un11_output_6_d_0,out_shift_amount,un7_output_2_0_0,un7_output_2_1,output_d,shift_amount_1_i,un11_output_1,un11_output_2,un20_output_2,pre_output,done_inv_sqrt,un4_overflow_0,output_reg_pipe_12_RNIPJ901_O6,un9_0_axb_8,un9_0_s_6,un9_0_s_7,N_414,N_33,clk,N_420,un3_shift_right,N_410,un9_0_s_5,un9_0_s_8,N_79,N_50,un9_0_s_4,un9_0_s_3,N_13_0,N_100_i,N_31,N_18_0,N_378,N_33_0,N_80,N_51,un9_0_s_0,un9_0_s_1,m9_0_0,N_417,N_62,N_454,SUM1_0_i_1_1,N_56,N_434_i,N_431_i,N_428_i,N_425_i,un9_0_s_2,N_419,N_49,N_413,un20_output_0_0_a2_0_0_lut6_2_O5,un1_apply_nrlt8_1,un1_apply_nrlt7,p_output_reg_pipe_13_Z_p_O_FD,p_output_reg_pipe_12_Z_p_O_FD,p_output_reg_pipe_Z_p_O_FD,p_output_reg_pipe_1_Z_p_O_FDE,p_output_reg_pipe_4_Z_p_O_FDE,p_output_reg_pipe_5_Z_p_O_FDE,p_output_reg_pipe_6_Z_p_O_FDE,p_output_reg_pipe_9_Z_p_O_FDE,p_output_reg_pipe_10_Z_p_O_FDE,p_output_reg_pipe_11_Z_p_O_FDE,p_output_reg_pipe_14_Z_p_O_FDE,p_output_reg_pipe_15_Z_p_O_FDE,p_output_reg_pipe_16_Z_p_O_FDE,p_output_reg_pipe_19_Z_p_O_FDE);
input [11:10] input_reg ;
input [1:1] shift_amount_1 ;
input [6:3] un14_pos_output ;
input [3:1] ret_val ;
output [9:9] un11_output_6_d_0 ;
input [1:1] out_shift_amount ;
output [6:6] un7_output_2_0_0 ;
output [6:5] un7_output_2_1 ;
output [4:4] output_d ;
input [2:2] shift_amount_1_i ;
output un11_output_1 ;
output un11_output_2 ;
input [14:14] un20_output_2 ;
output [11:1] pre_output ;
input done_inv_sqrt ;
input un4_overflow_0 ;
output output_reg_pipe_12_RNIPJ901_O6 ;
input un9_0_axb_8 ;
input un9_0_s_6 ;
input un9_0_s_7 ;
output N_414 ;
output N_33 ;
input clk ;
output N_420 ;
input un3_shift_right ;
output N_410 ;
input un9_0_s_5 ;
input un9_0_s_8 ;
output N_79 ;
output N_50 ;
input un9_0_s_4 ;
input un9_0_s_3 ;
output N_13_0 ;
input N_100_i ;
output N_31 ;
output N_18_0 ;
input N_378 ;
output N_33_0 ;
output N_80 ;
output N_51 ;
input un9_0_s_0 ;
input un9_0_s_1 ;
output m9_0_0 ;
output N_417 ;
output N_62 ;
input N_454 ;
input SUM1_0_i_1_1 ;
output N_56 ;
output N_434_i ;
output N_431_i ;
output N_428_i ;
output N_425_i ;
input un9_0_s_2 ;
input N_419 ;
output N_49 ;
output N_413 ;
input un20_output_0_0_a2_0_0_lut6_2_O5 ;
input un1_apply_nrlt8_1 ;
input un1_apply_nrlt7 ;
wire un11_output_1 ;
wire un11_output_2 ;
wire done_inv_sqrt ;
wire un4_overflow_0 ;
wire output_reg_pipe_12_RNIPJ901_O6 ;
wire un9_0_axb_8 ;
wire un9_0_s_6 ;
wire un9_0_s_7 ;
wire N_414 ;
wire N_33 ;
wire clk ;
wire N_420 ;
wire un3_shift_right ;
wire N_410 ;
wire un9_0_s_5 ;
wire un9_0_s_8 ;
wire N_79 ;
wire N_50 ;
wire un9_0_s_4 ;
wire un9_0_s_3 ;
wire N_13_0 ;
wire N_100_i ;
wire N_31 ;
wire N_18_0 ;
wire N_378 ;
wire N_33_0 ;
wire N_80 ;
wire N_51 ;
wire un9_0_s_0 ;
wire un9_0_s_1 ;
wire m9_0_0 ;
wire N_417 ;
wire N_62 ;
wire N_454 ;
wire SUM1_0_i_1_1 ;
wire N_56 ;
wire N_434_i ;
wire N_431_i ;
wire N_428_i ;
wire N_425_i ;
wire un9_0_s_2 ;
wire N_419 ;
wire N_49 ;
wire N_413 ;
wire un20_output_0_0_a2_0_0_lut6_2_O5 ;
wire un1_apply_nrlt8_1 ;
wire un1_apply_nrlt7 ;
wire [6:3] un14_pos_outputf ;
wire [6:3] pre_outputf ;
wire [4:4] un11_output ;
wire [6:4] un11_output_1_Z ;
wire un4_overflow_if ;
wire VCC ;
wire un4_overflow_i_0 ;
wire output_reg_pipe_13 ;
wire m41 ;
wire output_reg_pipe ;
wire m44 ;
wire output_reg_pipe_5 ;
wire N_427 ;
wire output_reg_pipe_10 ;
wire N_430 ;
wire output_reg_pipe_15 ;
wire N_433 ;
wire m25_0_1 ;
wire m25_0_0 ;
wire m17_0_2 ;
wire GND ;
input p_output_reg_pipe_13_Z_p_O_FD ;
input p_output_reg_pipe_12_Z_p_O_FD ;
input p_output_reg_pipe_Z_p_O_FD ;
input p_output_reg_pipe_1_Z_p_O_FDE ;
input p_output_reg_pipe_4_Z_p_O_FDE ;
input p_output_reg_pipe_5_Z_p_O_FDE ;
input p_output_reg_pipe_6_Z_p_O_FDE ;
input p_output_reg_pipe_9_Z_p_O_FDE ;
input p_output_reg_pipe_10_Z_p_O_FDE ;
input p_output_reg_pipe_11_Z_p_O_FDE ;
input p_output_reg_pipe_14_Z_p_O_FDE ;
input p_output_reg_pipe_15_Z_p_O_FDE ;
input p_output_reg_pipe_16_Z_p_O_FDE ;
input p_output_reg_pipe_19_Z_p_O_FDE ;
// instances
p_O_FD output_reg_pipe_13_Z(.Q(output_reg_pipe_13),.D(m41),.C(clk),.E(p_output_reg_pipe_13_Z_p_O_FD));
p_O_FD output_reg_pipe_12_Z(.Q(un4_overflow_if),.D(un4_overflow_i_0),.C(clk),.E(p_output_reg_pipe_12_Z_p_O_FD));
p_O_FD output_reg_pipe_Z(.Q(output_reg_pipe),.D(m44),.C(clk),.E(p_output_reg_pipe_Z_p_O_FD));
LUT5 output_reg_pipe_RNO(.I0(un4_overflow_0),.I1(pre_output[3:3]),.I2(N_420),.I3(output_reg_pipe),.I4(done_inv_sqrt),.O(m44));
defparam output_reg_pipe_RNO.INIT=32'h0101FF00;
LUT6 output_reg_pipe_13_RNO(.I0(input_reg[10:10]),.I1(input_reg[11:11]),.I2(un4_overflow_0),.I3(N_420),.I4(output_reg_pipe_13),.I5(done_inv_sqrt),.O(m41));
defparam output_reg_pipe_13_RNO.INIT=64'hEF00EF00FFFF0000;
p_O_FDE output_reg_pipe_1_Z(.Q(un14_pos_outputf[3:3]),.D(un14_pos_output[3:3]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_1_Z_p_O_FDE));
p_O_FDE output_reg_pipe_4_Z(.Q(pre_outputf[3:3]),.D(pre_output[3:3]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_4_Z_p_O_FDE));
p_O_FDE output_reg_pipe_5_Z(.Q(output_reg_pipe_5),.D(N_427),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_5_Z_p_O_FDE));
p_O_FDE output_reg_pipe_6_Z(.Q(un14_pos_outputf[4:4]),.D(un14_pos_output[4:4]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_6_Z_p_O_FDE));
p_O_FDE output_reg_pipe_9_Z(.Q(pre_outputf[4:4]),.D(pre_output[4:4]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_9_Z_p_O_FDE));
p_O_FDE output_reg_pipe_10_Z(.Q(output_reg_pipe_10),.D(N_430),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_10_Z_p_O_FDE));
p_O_FDE output_reg_pipe_11_Z(.Q(un14_pos_outputf[5:5]),.D(un14_pos_output[5:5]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_11_Z_p_O_FDE));
p_O_FDE output_reg_pipe_14_Z(.Q(pre_outputf[5:5]),.D(pre_output[5:5]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_14_Z_p_O_FDE));
p_O_FDE output_reg_pipe_15_Z(.Q(output_reg_pipe_15),.D(N_433),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_15_Z_p_O_FDE));
p_O_FDE output_reg_pipe_16_Z(.Q(un14_pos_outputf[6:6]),.D(un14_pos_output[6:6]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_16_Z_p_O_FDE));
p_O_FDE output_reg_pipe_19_Z(.Q(pre_outputf[6:6]),.D(pre_output[6:6]),.C(clk),.CE(done_inv_sqrt),.E(p_output_reg_pipe_19_Z_p_O_FDE));
LUT3 desc883(.I0(un3_shift_right),.I1(un7_output_2_1[5:5]),.I2(un11_output_1),.O(pre_output[5:5]));
defparam desc883.INIT=8'hD8;
LUT4 m26(.I0(ret_val[3:3]),.I1(N_410),.I2(m25_0_1),.I3(m25_0_0),.O(pre_output[8:8]));
defparam m26.INIT=16'hFFD8;
LUT5 desc884(.I0(ret_val[3:3]),.I1(ret_val[1:1]),.I2(shift_amount_1[1:1]),.I3(un9_0_s_5),.I4(un9_0_s_8),.O(un11_output_6_d_0[9:9]));
defparam desc884.INIT=32'hF8F00800;
LUT5 desc885(.I0(ret_val[3:3]),.I1(ret_val[1:1]),.I2(un3_shift_right),.I3(N_79),.I4(N_50),.O(pre_output[2:2]));
defparam desc885.INIT=32'hFFF00700;
LUT4 m19(.I0(ret_val[2:2]),.I1(un9_0_axb_8),.I2(shift_amount_1[1:1]),.I3(un9_0_s_4),.O(N_410));
defparam m19.INIT=16'h0600;
LUT4 m12(.I0(ret_val[2:2]),.I1(un9_0_axb_8),.I2(shift_amount_1[1:1]),.I3(un9_0_s_3),.O(N_13_0));
defparam m12.INIT=16'h0600;
LUT3 m31(.I0(N_100_i),.I1(un9_0_s_6),.I2(N_31),.O(pre_output[10:10]));
defparam m31.INIT=8'hE4;
LUT3 m18(.I0(N_100_i),.I1(un9_0_s_3),.I2(N_18_0),.O(pre_output[7:7]));
defparam m18.INIT=8'hE4;
LUT5 desc886(.I0(N_378),.I1(un3_shift_right),.I2(un9_0_s_6),.I3(N_33_0),.I4(un11_output[4:4]),.O(pre_output[4:4]));
defparam desc886.INIT=32'hF733CC80;
LUT5 desc887(.I0(ret_val[3:3]),.I1(ret_val[1:1]),.I2(un9_0_axb_8),.I3(out_shift_amount[1:1]),.I4(un9_0_s_8),.O(un7_output_2_0_0[6:6]));
defparam desc887.INIT=32'h437F007F;
LUT6 desc888(.I0(ret_val[3:3]),.I1(ret_val[1:1]),.I2(un9_0_axb_8),.I3(un3_shift_right),.I4(N_80),.I5(N_51),.O(pre_output[3:3]));
defparam desc888.INIT=64'hFF7FFF00007F0000;
LUT6 m25_0_1_cZ(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(out_shift_amount[1:1]),.I3(un3_shift_right),.I4(un9_0_s_8),.I5(un9_0_s_7),.O(m25_0_1));
defparam m25_0_1_cZ.INIT=64'h090F000609090000;
LUT6 m30(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(out_shift_amount[1:1]),.I3(un3_shift_right),.I4(un9_0_s_8),.I5(un9_0_s_7),.O(N_31));
defparam m30.INIT=64'h00F0006000900000;
LUT5 desc889(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(out_shift_amount[1:1]),.I3(un9_0_s_6),.I4(un9_0_s_7),.O(un7_output_2_1[5:5]));
defparam desc889.INIT=32'hFF990F09;
LUT5 desc890(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(out_shift_amount[1:1]),.I3(un9_0_s_6),.I4(un9_0_s_7),.O(un7_output_2_1[6:6]));
defparam desc890.INIT=32'hFFF69990;
LUT6 m25_0_0_cZ(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(out_shift_amount[1:1]),.I3(un3_shift_right),.I4(un9_0_s_5),.I5(un9_0_s_6),.O(m25_0_0));
defparam m25_0_0_cZ.INIT=64'h00F0009000600000;
LUT5 desc891(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(un3_shift_right),.I3(un9_0_s_6),.I4(un11_output[4:4]),.O(output_d[4:4]));
defparam desc891.INIT=32'h9F0F9000;
LUT6 m9_0_0_c(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(out_shift_amount[1:1]),.I3(un3_shift_right),.I4(un9_0_s_0),.I5(un9_0_s_1),.O(m9_0_0));
defparam m9_0_0_c.INIT=64'h0F09060009090000;
LUT4 m33(.I0(ret_val[2:2]),.I1(shift_amount_1[1:1]),.I2(un3_shift_right),.I3(un9_0_s_8),.O(N_417));
defparam m33.INIT=16'h0400;
LUT4 desc892(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(un9_0_s_6),.I3(un9_0_s_7),.O(N_62));
defparam desc892.INIT=16'hF960;
LUT6 desc893(.I0(N_454),.I1(SUM1_0_i_1_1),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.I4(un9_0_s_0),.I5(un9_0_s_1),.O(N_56));
defparam desc893.INIT=64'hFFFF3013CFEC0000;
LUT4 desc894(.I0(ret_val[1:1]),.I1(un9_0_axb_8),.I2(un9_0_s_4),.I3(un9_0_s_5),.O(N_33_0));
defparam desc894.INIT=16'hF690;
LUT5 output_reg_pipe_15_RNIJLNH1(.I0(un14_pos_outputf[6:6]),.I1(output_reg_pipe_15),.I2(pre_outputf[6:6]),.I3(un4_overflow_if),.I4(output_reg_pipe_13),.O(N_434_i));
defparam output_reg_pipe_15_RNIJLNH1.INIT=32'h22277277;
LUT5 output_reg_pipe_10_RNI4LNH1(.I0(un14_pos_outputf[5:5]),.I1(output_reg_pipe_10),.I2(pre_outputf[5:5]),.I3(un4_overflow_if),.I4(output_reg_pipe_13),.O(N_431_i));
defparam output_reg_pipe_10_RNI4LNH1.INIT=32'h22277277;
LUT5 output_reg_pipe_5_RNI0B2S(.I0(un14_pos_outputf[4:4]),.I1(output_reg_pipe_5),.I2(pre_outputf[4:4]),.I3(un4_overflow_if),.I4(output_reg_pipe_13),.O(N_428_i));
defparam output_reg_pipe_5_RNI0B2S.INIT=32'h22277277;
LUT5 output_reg_pipe_1_RNI23E61(.I0(un14_pos_outputf[3:3]),.I1(output_reg_pipe),.I2(pre_outputf[3:3]),.I3(un4_overflow_if),.I4(output_reg_pipe_13),.O(N_425_i));
defparam output_reg_pipe_1_RNI23E61.INIT=32'h22277277;
LUT5 desc895(.I0(shift_amount_1_i[2:2]),.I1(shift_amount_1[1:1]),.I2(un9_0_s_0),.I3(un9_0_s_1),.I4(un9_0_s_2),.O(N_79));
defparam desc895.INIT=32'hBA329810;
LUT5 desc896(.I0(shift_amount_1_i[2:2]),.I1(shift_amount_1[1:1]),.I2(un9_0_s_2),.I3(N_56),.I4(un9_0_s_3),.O(N_80));
defparam desc896.INIT=32'hF7A2D580;
LUT6_L desc897(.I0(shift_amount_1_i[2:2]),.I1(N_100_i),.I2(shift_amount_1[1:1]),.I3(un9_0_s_1),.I4(un9_0_s_2),.I5(un9_0_s_3),.LO(un11_output_1_Z[5:5]));
defparam desc897.INIT=64'h4644060442400200;
LUT6_L desc898(.I0(shift_amount_1_i[2:2]),.I1(N_100_i),.I2(shift_amount_1[1:1]),.I3(un9_0_s_0),.I4(un9_0_s_1),.I5(un9_0_s_2),.LO(un11_output_1_Z[4:4]));
defparam desc898.INIT=64'h4644060442400200;
LUT6 desc899(.I0(N_419),.I1(N_378),.I2(N_100_i),.I3(un9_0_s_1),.I4(un9_0_s_2),.I5(un9_0_s_3),.O(N_49));
defparam desc899.INIT=64'hEA62C840AA228800;
LUT6 desc900(.I0(N_419),.I1(N_378),.I2(N_100_i),.I3(un9_0_s_2),.I4(un9_0_s_3),.I5(un9_0_s_4),.O(N_50));
defparam desc900.INIT=64'hEA62C840AA228800;
LUT6_L desc901(.I0(N_378),.I1(N_100_i),.I2(out_shift_amount[1:1]),.I3(un9_0_s_2),.I4(un9_0_s_3),.I5(un9_0_s_4),.LO(un11_output_1_Z[6:6]));
defparam desc901.INIT=64'hC2C0828042400200;
LUT6_L m17_0_2_cZ(.I0(N_378),.I1(out_shift_amount[1:1]),.I2(un3_shift_right),.I3(un9_0_s_4),.I4(un9_0_s_5),.I5(un9_0_s_8),.LO(m17_0_2));
defparam m17_0_2_cZ.INIT=64'h1C1814100C080400;
LUT6 m25_0(.I0(N_378),.I1(out_shift_amount[1:1]),.I2(un3_shift_right),.I3(un9_0_s_8),.I4(un9_0_s_7),.I5(m25_0_0),.O(N_413));
defparam m25_0.INIT=64'hFFFFFFFF23012200;
LUT6 desc902(.I0(shift_amount_1_i[2:2]),.I1(N_378),.I2(N_100_i),.I3(un9_0_s_4),.I4(un9_0_s_5),.I5(un11_output_1_Z[5:5]),.O(un11_output_1));
defparam desc902.INIT=64'hFFFFFFFFA0802000;
LUT6 desc903(.I0(shift_amount_1_i[2:2]),.I1(N_378),.I2(N_100_i),.I3(un9_0_s_3),.I4(un9_0_s_4),.I5(un11_output_1_Z[4:4]),.O(un11_output[4:4]));
defparam desc903.INIT=64'hFFFFFFFFA0802000;
LUT6 desc904(.I0(un20_output_0_0_a2_0_0_lut6_2_O5),.I1(N_378),.I2(un3_shift_right),.I3(un9_0_s_6),.I4(un9_0_s_7),.I5(un11_output_6_d_0[9:9]),.O(pre_output[9:9]));
defparam desc904.INIT=64'h0F0D07050A080200;
LUT6 m34(.I0(N_100_i),.I1(out_shift_amount[1:1]),.I2(shift_amount_1[1:1]),.I3(un3_shift_right),.I4(un9_0_s_8),.I5(un9_0_s_7),.O(pre_output[11:11]));
defparam m34.INIT=64'h0081000100800000;
LUT6 desc905(.I0(N_378),.I1(N_100_i),.I2(out_shift_amount[1:1]),.I3(un9_0_s_3),.I4(un9_0_s_4),.I5(un9_0_s_5),.O(N_51));
defparam desc905.INIT=64'h8C8488800C040800;
LUT6 m17_0(.I0(N_378),.I1(out_shift_amount[1:1]),.I2(un3_shift_right),.I3(un9_0_s_6),.I4(un9_0_s_7),.I5(m17_0_2),.O(N_18_0));
defparam m17_0.INIT=64'hFFFFFFFF23220100;
LUT6 desc906(.I0(N_378),.I1(N_100_i),.I2(out_shift_amount[1:1]),.I3(un9_0_s_5),.I4(un9_0_s_6),.I5(un11_output_1_Z[6:6]),.O(un11_output_2));
defparam desc906.INIT=64'hFFFFFFFF0C080400;
LUT6 desc907(.I0(pre_output[11:11]),.I1(pre_output[10:10]),.I2(pre_output[9:9]),.I3(pre_output[8:8]),.I4(un1_apply_nrlt8_1),.I5(un1_apply_nrlt7),.O(N_420));
defparam desc907.INIT=64'h0101011101110111;
LUT5_L output_reg_pipe_5_RNO(.I0(input_reg[10:10]),.I1(input_reg[11:11]),.I2(un4_overflow_0),.I3(pre_output[4:4]),.I4(N_420),.LO(N_427));
defparam output_reg_pipe_5_RNO.INIT=32'h000000EF;
LUT5_L output_reg_pipe_10_RNO(.I0(input_reg[10:10]),.I1(input_reg[11:11]),.I2(un4_overflow_0),.I3(pre_output[5:5]),.I4(N_420),.LO(N_430));
defparam output_reg_pipe_10_RNO.INIT=32'h000000EF;
LUT5_L output_reg_pipe_15_RNO(.I0(input_reg[10:10]),.I1(input_reg[11:11]),.I2(un4_overflow_0),.I3(pre_output[6:6]),.I4(N_420),.LO(N_433));
defparam output_reg_pipe_15_RNO.INIT=32'h000000EF;
LUT4 desc908(.I0(un20_output_2[14:14]),.I1(un3_shift_right),.I2(N_56),.I3(N_49),.O(pre_output[1:1]));
defparam desc908.INIT=16'hEC20;
LUT4 desc909(.I0(un3_shift_right),.I1(un7_output_2_0_0[6:6]),.I2(un7_output_2_1[6:6]),.I3(un11_output_2),.O(pre_output[6:6]));
defparam desc909.INIT=16'hD580;
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
LUT4 m27_lut6_2_o6(.I0(ret_val[2:2]),.I1(un9_0_axb_8),.I2(shift_amount_1[1:1]),.I3(un9_0_s_6),.O(N_414));
defparam m27_lut6_2_o6.INIT=16'h0600;
LUT4 m27_lut6_2_o5(.I0(ret_val[2:2]),.I1(un9_0_axb_8),.I2(shift_amount_1[1:1]),.I3(un9_0_s_7),.O(N_33));
defparam m27_lut6_2_o5.INIT=16'h0600;
LUT4 output_reg_pipe_12_RNIPJ901_o6(.I0(input_reg[10:10]),.I1(input_reg[11:11]),.I2(done_inv_sqrt),.I3(un4_overflow_0),.O(output_reg_pipe_12_RNIPJ901_O6));
defparam output_reg_pipe_12_RNIPJ901_o6.INIT=16'h1000;
LUT5 output_reg_pipe_12_RNIPJ901_o5(.I0(un4_overflow_if),.I1(input_reg[10:10]),.I2(input_reg[11:11]),.I3(done_inv_sqrt),.I4(un4_overflow_0),.O(un4_overflow_i_0));
defparam output_reg_pipe_12_RNIPJ901_o5.INIT=32'hFCAAFFAA;
endmodule
module shifterZ1_inj (ret_val,un20_output_2,ret_val_m2,shift_amount_1,un26_output_0_iv_3,ret_val_d_a1,ret_val_d_a0,un26_output_6,un26_output_2,un26_output_4,un26_output_3,un26_output_0,un1_poly_odd_i,input_reg,un26_output_0_iv_2_0_1,input_shifted_4,input_shifted_0,input_shifted_3,un1_input_shifted,un1_poly_odd,un9_0_axb_8,un20_output_0_0_a2_0_0_lut6_2_O5,N_100_i,N_65,un3_shift_right,N_2502_i,un4_overflow_2,N_454,N_72,ret_val_ss0,N_458,N_45,N_70,N_73,N_71,N_441,un9_0_axb_4);
input [3:1] ret_val ;
output [14:14] un20_output_2 ;
input [3:3] ret_val_m2 ;
input [1:1] shift_amount_1 ;
output [6:6] un26_output_0_iv_3 ;
input [1:1] ret_val_d_a1 ;
input [1:1] ret_val_d_a0 ;
output un26_output_6 ;
output un26_output_2 ;
output un26_output_4 ;
output un26_output_3 ;
output un26_output_0 ;
output [6:6] un1_poly_odd_i ;
input [11:0] input_reg ;
output un26_output_0_iv_2_0_1 ;
output input_shifted_4 ;
output input_shifted_0 ;
output input_shifted_3 ;
input [4:4] un1_input_shifted ;
input [8:8] un1_poly_odd ;
input un9_0_axb_8 ;
output un20_output_0_0_a2_0_0_lut6_2_O5 ;
output N_100_i ;
output N_65 ;
input un3_shift_right ;
output N_2502_i ;
input un4_overflow_2 ;
input N_454 ;
output N_72 ;
input ret_val_ss0 ;
input N_458 ;
output N_45 ;
output N_70 ;
output N_73 ;
output N_71 ;
input N_441 ;
output un9_0_axb_4 ;
wire un26_output_6 ;
wire un26_output_2 ;
wire un26_output_4 ;
wire un26_output_3 ;
wire un26_output_0 ;
wire un26_output_0_iv_2_0_1 ;
wire input_shifted_4 ;
wire input_shifted_0 ;
wire input_shifted_3 ;
wire un9_0_axb_8 ;
wire un20_output_0_0_a2_0_0_lut6_2_O5 ;
wire N_100_i ;
wire N_65 ;
wire un3_shift_right ;
wire N_2502_i ;
wire un4_overflow_2 ;
wire N_454 ;
wire N_72 ;
wire ret_val_ss0 ;
wire N_458 ;
wire N_45 ;
wire N_70 ;
wire N_73 ;
wire N_71 ;
wire N_441 ;
wire un9_0_axb_4 ;
wire [4:4] input_m_s ;
wire [5:5] un26_output_0_iv_2_0 ;
wire [3:3] input_m_0 ;
wire [2:2] output_a1_0 ;
wire [3:3] un26_output_0_iv_0 ;
wire [4:4] un26_output_0_iv_2_a0 ;
wire [1:0] input_m_4 ;
wire input_m_2 ;
wire [2:2] input_m_3 ;
wire [7:7] un26_output_0_iv_0_a2_xx ;
wire [7:7] un26_output_0_iv_0_a2_yy ;
wire input_m_4_a0_0 ;
wire [2:2] output_0_2 ;
wire GND ;
wire VCC ;
wire un20_output_0_0_a2_0_0 ;
wire N_47 ;
wire un20_output_0_2_a0_0 ;
wire un20_output_3_0_0_a2_s ;
wire un26_m3_i_0 ;
wire N_46 ;
wire N_443 ;
wire N_445 ;
// instances
LUT4 desc845(.I0(N_65),.I1(un26_output_6),.I2(un3_shift_right),.I3(un9_0_axb_8),.O(N_2502_i));
defparam desc845.INIT=16'h00AC;
LUT4 un20_output_0(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(un20_output_0_2_a0_0),.I3(ret_val[3:3]),.O(un20_output_2[14:14]));
defparam un20_output_0.INIT=16'h00DF;
LUT5 un20_output_1_0_0_a2_0(.I0(input_reg[3:3]),.I1(un4_overflow_2),.I2(ret_val_m2[3:3]),.I3(N_454),.I4(un9_0_axb_8),.O(un20_output_3_0_0_a2_s));
defparam un20_output_1_0_0_a2_0.INIT=32'h000037FF;
LUT5 desc846(.I0(input_reg[3:3]),.I1(input_reg[6:6]),.I2(un9_0_axb_8),.I3(input_m_s[4:4]),.I4(shift_amount_1[1:1]),.O(un26_output_0_iv_3[6:6]));
defparam desc846.INIT=32'hFF0ACCC0;
LUT3 desc847(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(un9_0_axb_8),.O(un26_output_0_iv_2_0[5:5]));
defparam desc847.INIT=8'hCA;
LUT4 desc848(.I0(input_reg[3:3]),.I1(ret_val[2:2]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(input_m_0[3:3]));
defparam desc848.INIT=16'h2A00;
LUT5 desc849(.I0(input_reg[8:8]),.I1(input_reg[7:7]),.I2(un9_0_axb_8),.I3(N_47),.I4(shift_amount_1[1:1]),.O(N_72));
defparam desc849.INIT=32'hCACAFF00;
LUT6 desc850(.I0(input_reg[2:2]),.I1(ret_val_ss0),.I2(ret_val_d_a1[1:1]),.I3(N_458),.I4(ret_val_d_a0[1:1]),.I5(N_454),.O(output_a1_0[2:2]));
defparam desc850.INIT=64'h1155115055555050;
LUT6 desc851(.I0(input_reg[2:2]),.I1(un9_0_axb_8),.I2(un20_output_2[14:14]),.I3(input_m_0[3:3]),.I4(shift_amount_1[1:1]),.I5(un26_output_0_iv_0[3:3]),.O(un26_output_2));
defparam desc851.INIT=64'hFFFFFFFF0000FF20;
LUT6 desc852(.I0(input_reg[2:2]),.I1(un9_0_axb_8),.I2(un26_output_0_iv_2_0[5:5]),.I3(un26_m3_i_0),.I4(input_m_0[3:3]),.I5(shift_amount_1[1:1]),.O(un26_output_4));
defparam desc852.INIT=64'hFFFFFF22FFF0FFF0;
LUT6 desc853(.I0(input_reg[3:3]),.I1(un9_0_axb_8),.I2(un20_output_2[14:14]),.I3(input_m_s[4:4]),.I4(un26_output_0_iv_2_a0[4:4]),.I5(shift_amount_1[1:1]),.O(un26_output_3));
defparam desc853.INIT=64'h0000FFFFFF20FF2F;
LUT6 desc854(.I0(input_reg[5:5]),.I1(input_reg[6:6]),.I2(un9_0_axb_8),.I3(un20_output_2[14:14]),.I4(N_45),.I5(shift_amount_1[1:1]),.O(N_70));
defparam desc854.INIT=64'hAC00AC00FF000000;
LUT6 desc855(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[7:7]),.I3(input_reg[6:6]),.I4(un9_0_axb_8),.I5(shift_amount_1[1:1]),.O(N_73));
defparam desc855.INIT=64'hCCCCAAAAFF00F0F0;
LUT6 desc856(.I0(input_reg[7:7]),.I1(input_reg[6:6]),.I2(un9_0_axb_8),.I3(un20_output_2[14:14]),.I4(N_46),.I5(shift_amount_1[1:1]),.O(N_71));
defparam desc856.INIT=64'hCACACACAFF000000;
LUT4 desc857(.I0(input_reg[1:1]),.I1(ret_val[3:3]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(input_m_4[1:1]));
defparam desc857.INIT=16'h0008;
LUT4 desc858(.I0(input_reg[4:4]),.I1(ret_val[2:2]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(input_m_s[4:4]));
defparam desc858.INIT=16'h2A00;
LUT4_L desc859(.I0(input_reg[0:0]),.I1(ret_val[2:2]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.LO(input_m_2));
defparam desc859.INIT=16'h8000;
LUT4 desc860(.I0(input_reg[2:2]),.I1(ret_val[2:2]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(input_m_3[2:2]));
defparam desc860.INIT=16'h8000;
LUT5_L desc861(.I0(input_reg[0:0]),.I1(input_reg[1:1]),.I2(un9_0_axb_8),.I3(un20_output_2[14:14]),.I4(shift_amount_1[1:1]),.LO(un26_output_0_iv_0[3:3]));
defparam desc861.INIT=32'hCA000000;
LUT5 desc862(.I0(input_reg[1:1]),.I1(input_reg[2:2]),.I2(un9_0_axb_8),.I3(un20_output_2[14:14]),.I4(input_m_2),.O(un26_output_0_iv_2_a0[4:4]));
defparam desc862.INIT=32'h000035FF;
LUT5 desc863(.I0(input_reg[0:0]),.I1(input_reg[1:1]),.I2(un9_0_axb_8),.I3(un20_output_0_0_a2_0_0),.I4(shift_amount_1[1:1]),.O(un26_output_0));
defparam desc863.INIT=32'h0000CA00;
LUT5 desc864(.I0(N_443),.I1(N_445),.I2(un26_output_0_iv_0_a2_xx[7:7]),.I3(un26_output_0_iv_0_a2_yy[7:7]),.I4(shift_amount_1[1:1]),.O(un26_output_6));
defparam desc864.INIT=32'hFFAAFCFC;
LUT5 desc865(.I0(un9_0_axb_8),.I1(un3_shift_right),.I2(N_65),.I3(un26_output_6),.I4(input_shifted_4),.O(un1_poly_odd_i[6:6]));
defparam desc865.INIT=32'hF7D5A280;
LUT3 desc866(.I0(input_reg[3:3]),.I1(input_reg[4:4]),.I2(un9_0_axb_8),.O(N_45));
defparam desc866.INIT=8'hAC;
LUT3 desc867(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(un9_0_axb_8),.O(N_46));
defparam desc867.INIT=8'hAC;
LUT3 desc868(.I0(input_reg[7:7]),.I1(input_reg[6:6]),.I2(un9_0_axb_8),.O(N_445));
defparam desc868.INIT=8'hAC;
LUT3 desc869(.I0(input_reg[4:4]),.I1(input_reg[5:5]),.I2(un9_0_axb_8),.O(N_443));
defparam desc869.INIT=8'hCA;
LUT6 un20_output_0_2_a0_0_0(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[7:7]),.I3(input_reg[10:10]),.I4(input_reg[11:11]),.I5(input_reg[6:6]),.O(un20_output_0_2_a0_0));
defparam un20_output_0_2_a0_0_0.INIT=64'h0000000000000001;
LUT6 desc870(.I0(input_reg[0:0]),.I1(input_reg[7:7]),.I2(input_reg[11:11]),.I3(input_reg[6:6]),.I4(un4_overflow_2),.I5(N_441),.O(input_m_4_a0_0));
defparam desc870.INIT=64'hAAAAAAAAA0A2A0A0;
LUT4 desc871(.I0(input_m_4_a0_0),.I1(ret_val[3:3]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(input_m_4[0:0]));
defparam desc871.INIT=16'h0800;
LUT6 desc872(.I0(input_reg[0:0]),.I1(input_reg[1:1]),.I2(ret_val[2:2]),.I3(output_a1_0[2:2]),.I4(ret_val[3:3]),.I5(un9_0_axb_8),.O(output_0_2[2:2]));
defparam desc872.INIT=64'h000000AF0000CFCF;
LUT6 un26_m3_i_0_cZ(.I0(input_reg[0:0]),.I1(input_reg[1:1]),.I2(ret_val[2:2]),.I3(ret_val[3:3]),.I4(ret_val[1:1]),.I5(un9_0_axb_8),.O(un26_m3_i_0));
defparam un26_m3_i_0_cZ.INIT=64'h00C0000000000A00;
LUT6 desc873(.I0(input_reg[0:0]),.I1(input_reg[1:1]),.I2(ret_val[2:2]),.I3(ret_val[3:3]),.I4(ret_val[1:1]),.I5(un9_0_axb_8),.O(un26_output_0_iv_0_a2_yy[7:7]));
defparam desc873.INIT=64'h00C00C000A000A00;
LUT6 desc874(.I0(input_reg[2:2]),.I1(input_reg[3:3]),.I2(ret_val[2:2]),.I3(ret_val[3:3]),.I4(ret_val[1:1]),.I5(un9_0_axb_8),.O(un26_output_0_iv_0_a2_xx[7:7]));
defparam desc874.INIT=64'h00C00C000A000A00;
LUT6 desc875(.I0(input_reg[9:9]),.I1(input_reg[8:8]),.I2(input_reg[7:7]),.I3(input_reg[10:10]),.I4(un9_0_axb_8),.I5(shift_amount_1[1:1]),.O(N_65));
defparam desc875.INIT=64'hAAAAFF00F0F0CCCC;
LUT6 desc876(.I0(input_reg[3:3]),.I1(ret_val[2:2]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.I4(output_0_2[2:2]),.I5(N_46),.O(input_shifted_0));
defparam desc876.INIT=64'h3F2F00003C2C0000;
LUT6 desc877(.I0(input_reg[5:5]),.I1(un20_output_3_0_0_a2_s),.I2(input_m_3[2:2]),.I3(input_m_4[0:0]),.I4(input_m_4[1:1]),.I5(shift_amount_1[1:1]),.O(un26_output_0_iv_2_0_1));
defparam desc877.INIT=64'hFFFFFFF0FFFFFFF8;
LUT3 desc878(.I0(un3_shift_right),.I1(N_72),.I2(un26_output_4),.O(input_shifted_3));
defparam desc878.INIT=8'hD8;
LUT4 desc879(.I0(un3_shift_right),.I1(N_73),.I2(un26_output_0_iv_3[6:6]),.I3(un26_output_0_iv_2_0_1),.O(input_shifted_4));
defparam desc879.INIT=16'hDDD8;
LUT5 desc880(.I0(un9_0_axb_8),.I1(input_shifted_3),.I2(un1_input_shifted[4:4]),.I3(un1_poly_odd[8:8]),.I4(input_shifted_4),.O(un9_0_axb_4));
defparam desc880.INIT=32'hEBB1411B;
GND GND_cZ(.G(GND));
VCC VCC_cZ(.P(VCC));
LUT3 desc881(.I0(input_reg[5:5]),.I1(input_reg[6:6]),.I2(un9_0_axb_8),.O(N_47));
defparam desc881.INIT=8'hAC;
LUT3 desc882(.I0(ret_val[3:3]),.I1(ret_val[1:1]),.I2(un9_0_axb_8),.O(N_100_i));
defparam desc882.INIT=8'h7F;
LUT3 un20_output_0_0_a2_0_0_lut6_2_o6(.I0(ret_val[2:2]),.I1(ret_val[3:3]),.I2(ret_val[1:1]),.O(un20_output_0_0_a2_0_0));
defparam un20_output_0_0_a2_0_0_lut6_2_o6.INIT=8'h13;
LUT4 un20_output_0_0_a2_0_0_lut6_2_o5(.I0(ret_val[2:2]),.I1(ret_val[3:3]),.I2(ret_val[1:1]),.I3(un9_0_axb_8),.O(un20_output_0_0_a2_0_0_lut6_2_O5));
defparam un20_output_0_0_a2_0_0_lut6_2_o5.INIT=16'h2444;
endmodule
module vec_mult_inj (in_b_vec_mult_sel,out_inner_prod_i,out_i_vec_mult_2,out_r_vec_mult_2,out_inner_prod_r,vec_out_r_AQ_2,out_inv_sqrt_0,out_inv_sqrt_1,out_inv_sqrt_2,out_inv_sqrt_7,out_inv_sqrt_8,out_inv_sqrt_9,out_inv_sqrt_10,out_inv_sqrt_11,vec_out_i_AQ_2,out_i_vec_mult_1,out_r_vec_mult_1,vec_out_r_AQ_1,vec_out_i_AQ_1,out_i_vec_mult_0,out_r_vec_mult_0,vec_out_r_AQ_0,vec_out_i_AQ_0,out_i_vec_mult_3,out_r_vec_mult_3,vec_out_r_AQ_3,vec_out_i_AQ_3,clk,N_425_i,N_428_i,N_431_i,N_434_i);
input in_b_vec_mult_sel ;
input [11:0] out_inner_prod_i ;
output [11:0] out_i_vec_mult_2 ;
output [11:0] out_r_vec_mult_2 ;
input [11:0] out_inner_prod_r ;
input [11:0] vec_out_r_AQ_2 ;
input out_inv_sqrt_0 ;
input out_inv_sqrt_1 ;
input out_inv_sqrt_2 ;
input out_inv_sqrt_7 ;
input out_inv_sqrt_8 ;
input out_inv_sqrt_9 ;
input out_inv_sqrt_10 ;
input out_inv_sqrt_11 ;
input [11:0] vec_out_i_AQ_2 ;
output [11:0] out_i_vec_mult_1 ;
output [11:0] out_r_vec_mult_1 ;
input [11:0] vec_out_r_AQ_1 ;
input [11:0] vec_out_i_AQ_1 ;
output [11:0] out_i_vec_mult_0 ;
output [11:0] out_r_vec_mult_0 ;
input [11:0] vec_out_r_AQ_0 ;
input [11:0] vec_out_i_AQ_0 ;
output [11:0] out_i_vec_mult_3 ;
output [11:0] out_r_vec_mult_3 ;
input [11:0] vec_out_r_AQ_3 ;
input [11:0] vec_out_i_AQ_3 ;
input clk ;
input N_425_i ;
input N_428_i ;
input N_431_i ;
input N_434_i ;
wire out_inv_sqrt_0 ;
wire out_inv_sqrt_1 ;
wire out_inv_sqrt_2 ;
wire out_inv_sqrt_7 ;
wire out_inv_sqrt_8 ;
wire out_inv_sqrt_9 ;
wire out_inv_sqrt_10 ;
wire out_inv_sqrt_11 ;
wire clk ;
wire N_425_i ;
wire N_428_i ;
wire N_431_i ;
wire N_434_i ;
wire [11:0] in_b_i_reg ;
wire GND ;
wire VCC ;
// instances
FDR desc695(.Q(in_b_i_reg[11:11]),.D(out_inner_prod_i[11:11]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc696(.Q(in_b_i_reg[10:10]),.D(out_inner_prod_i[10:10]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc697(.Q(in_b_i_reg[9:9]),.D(out_inner_prod_i[9:9]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc698(.Q(in_b_i_reg[8:8]),.D(out_inner_prod_i[8:8]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc699(.Q(in_b_i_reg[7:7]),.D(out_inner_prod_i[7:7]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc700(.Q(in_b_i_reg[6:6]),.D(out_inner_prod_i[6:6]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc701(.Q(in_b_i_reg[5:5]),.D(out_inner_prod_i[5:5]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc702(.Q(in_b_i_reg[4:4]),.D(out_inner_prod_i[4:4]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc703(.Q(in_b_i_reg[3:3]),.D(out_inner_prod_i[3:3]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc704(.Q(in_b_i_reg[2:2]),.D(out_inner_prod_i[2:2]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc705(.Q(in_b_i_reg[1:1]),.D(out_inner_prod_i[1:1]),.C(clk),.R(in_b_vec_mult_sel));
FDR desc706(.Q(in_b_i_reg[0:0]),.D(out_inner_prod_i[0:0]),.C(clk),.R(in_b_vec_mult_sel));
desc481_inj desc707(.out_i_vec_mult_2(out_i_vec_mult_2[11:0]),.out_r_vec_mult_2(out_r_vec_mult_2[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_2(vec_out_r_AQ_2[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.vec_out_i_AQ_2(vec_out_i_AQ_2[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
desc536_inj desc708(.out_i_vec_mult_1(out_i_vec_mult_1[11:0]),.out_r_vec_mult_1(out_r_vec_mult_1[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_1(vec_out_r_AQ_1[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.vec_out_i_AQ_1(vec_out_i_AQ_1[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
desc591_inj desc709(.out_i_vec_mult_0(out_i_vec_mult_0[11:0]),.out_r_vec_mult_0(out_r_vec_mult_0[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_0(vec_out_r_AQ_0[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.vec_out_i_AQ_0(vec_out_i_AQ_0[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
desc646_inj desc710(.out_i_vec_mult_3(out_i_vec_mult_3[11:0]),.out_r_vec_mult_3(out_r_vec_mult_3[11:0]),.out_inner_prod_r(out_inner_prod_r[11:0]),.vec_out_r_AQ_3(vec_out_r_AQ_3[11:0]),.out_inv_sqrt_0(out_inv_sqrt_0),.out_inv_sqrt_1(out_inv_sqrt_1),.out_inv_sqrt_2(out_inv_sqrt_2),.out_inv_sqrt_7(out_inv_sqrt_7),.out_inv_sqrt_8(out_inv_sqrt_8),.out_inv_sqrt_9(out_inv_sqrt_9),.out_inv_sqrt_10(out_inv_sqrt_10),.out_inv_sqrt_11(out_inv_sqrt_11),.in_b_vec_mult_sel(in_b_vec_mult_sel),.vec_out_i_AQ_3(vec_out_i_AQ_3[11:0]),.out_inner_prod_i(out_inner_prod_i[11:0]),.in_b_i_reg(in_b_i_reg[11:0]),.clk(clk),.N_425_i(N_425_i),.N_428_i(N_428_i),.N_431_i(N_431_i),.N_434_i(N_434_i));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
module vec_sub_inj (in_a_r_reg_3_11,in_a_r_reg_2_11,in_a_r_reg_1_11,in_a_r_reg_0_0,in_a_r_reg_0_11,out_Q_r,in_a_i_reg_3_11,in_a_i_reg_2_11,in_a_i_reg_1_11,in_a_i_reg_0_11,out_Q_i,out_r_vec_mult_0,out_r_vec_mult_1,out_r_vec_mult_2,pre_out,out_r_vec_mult_3,pre_out_i_m_1,pre_out_0,output_iv,output_iv_0_0,output_iv_0_1,output_iv_0_2,output_iv_0_3,output_iv_0_4,output_iv_0_6,output_iv_0_7,output_iv_0_8,output_iv_0_9,out_i_vec_sub_0,out_i_vec_mult_0,pre_out_i_m_2,out_i_vec_mult_1,pre_out_1,pre_out_4,pre_out_i_m_3,out_i_vec_mult_2,pre_out_2,pre_out_5,out_i_vec_mult_3,pre_out_i_m,pre_out_i_m_0_0,pre_out_i_m_0_1,pre_out_i_m_0_6,pre_out_i_m_0_4,pre_out_i_m_4,pre_out_6,pre_out_3_9,pre_out_3_0,pre_out_3_1,pre_out_3_3,pre_out_3_5,pre_out_3_7,pre_out_3_8,pre_out_3_6,clk,w_in_a_vec_sub,N_500,un5_output,un5_output_0,un5_output_1,un5_output_2,un5_output_3,un5_output_4,p_desc739_p_O_FDE,p_desc740_p_O_FDE,p_desc741_p_O_FDE,p_desc742_p_O_FDE,p_desc743_p_O_FDE,p_desc744_p_O_FDE,p_desc745_p_O_FDE,p_desc746_p_O_FDE,p_desc747_p_O_FDE,p_desc748_p_O_FDE,p_desc749_p_O_FDE,p_desc750_p_O_FDE,p_desc751_p_O_FDE,p_desc752_p_O_FDE,p_desc753_p_O_FDE,p_desc754_p_O_FDE,p_desc755_p_O_FDE,p_desc756_p_O_FDE,p_desc757_p_O_FDE,p_desc758_p_O_FDE,p_desc759_p_O_FDE,p_desc760_p_O_FDE,p_desc761_p_O_FDE,p_desc762_p_O_FDE,p_desc763_p_O_FDE,p_desc764_p_O_FDE,p_desc765_p_O_FDE,p_desc766_p_O_FDE,p_desc767_p_O_FDE,p_desc768_p_O_FDE,p_desc769_p_O_FDE,p_desc770_p_O_FDE,p_desc771_p_O_FDE,p_desc772_p_O_FDE,p_desc773_p_O_FDE,p_desc774_p_O_FDE,p_desc775_p_O_FDE,p_desc776_p_O_FDE,p_desc777_p_O_FDE,p_desc778_p_O_FDE,p_desc779_p_O_FDE,p_desc780_p_O_FDE,p_desc781_p_O_FDE,p_desc782_p_O_FDE,p_desc783_p_O_FDE,p_desc784_p_O_FDE,p_desc785_p_O_FDE,p_desc786_p_O_FDE,p_desc787_p_O_FDE,p_desc788_p_O_FDE,p_desc789_p_O_FDE,p_desc790_p_O_FDE,p_desc791_p_O_FDE,p_desc792_p_O_FDE,p_desc793_p_O_FDE,p_desc794_p_O_FDE,p_desc795_p_O_FDE,p_desc796_p_O_FDE,p_desc797_p_O_FDE,p_desc798_p_O_FDE,p_desc799_p_O_FDE,p_desc800_p_O_FDE,p_desc801_p_O_FDE,p_desc802_p_O_FDE,p_desc803_p_O_FDE,p_desc804_p_O_FDE,p_desc805_p_O_FDE,p_desc806_p_O_FDE,p_desc807_p_O_FDE,p_desc808_p_O_FDE,p_desc809_p_O_FDE,p_desc810_p_O_FDE,p_desc811_p_O_FDE,p_desc812_p_O_FDE,p_desc813_p_O_FDE,p_desc814_p_O_FDE,p_desc815_p_O_FDE,p_desc816_p_O_FDE,p_desc817_p_O_FDE,p_desc818_p_O_FDE,p_desc819_p_O_FDE,p_desc820_p_O_FDE,p_desc821_p_O_FDE,p_desc822_p_O_FDE,p_desc823_p_O_FDE,p_desc824_p_O_FDE,p_desc825_p_O_FDE,p_desc826_p_O_FDE,p_desc827_p_O_FDE,p_desc828_p_O_FDE,p_desc829_p_O_FDE,p_desc830_p_O_FDE,p_desc831_p_O_FDE,p_desc832_p_O_FDE,p_desc833_p_O_FDE,p_desc834_p_O_FDE);
output in_a_r_reg_3_11 ;
output in_a_r_reg_2_11 ;
output in_a_r_reg_1_11 ;
output in_a_r_reg_0_0 ;
output in_a_r_reg_0_11 ;
input [47:0] out_Q_r ;
output in_a_i_reg_3_11 ;
output in_a_i_reg_2_11 ;
output in_a_i_reg_1_11 ;
output in_a_i_reg_0_11 ;
input [47:0] out_Q_i ;
input [11:0] out_r_vec_mult_0 ;
input [11:0] out_r_vec_mult_1 ;
input [11:0] out_r_vec_mult_2 ;
output [11:1] pre_out ;
input [11:0] out_r_vec_mult_3 ;
output pre_out_i_m_1 ;
output [11:1] pre_out_0 ;
output [10:0] output_iv ;
output output_iv_0_0 ;
output output_iv_0_1 ;
output output_iv_0_2 ;
output output_iv_0_3 ;
output output_iv_0_4 ;
output output_iv_0_6 ;
output output_iv_0_7 ;
output output_iv_0_8 ;
output output_iv_0_9 ;
output [11:11] out_i_vec_sub_0 ;
input [11:0] out_i_vec_mult_0 ;
output pre_out_i_m_2 ;
input [11:0] out_i_vec_mult_1 ;
output [11:1] pre_out_1 ;
output [11:11] pre_out_4 ;
output pre_out_i_m_3 ;
input [11:0] out_i_vec_mult_2 ;
output [11:1] pre_out_2 ;
output [11:11] pre_out_5 ;
input [11:0] out_i_vec_mult_3 ;
output [10:0] pre_out_i_m ;
output pre_out_i_m_0_0 ;
output pre_out_i_m_0_1 ;
output pre_out_i_m_0_6 ;
output pre_out_i_m_0_4 ;
output pre_out_i_m_4 ;
output [11:11] pre_out_6 ;
output pre_out_3_9 ;
output pre_out_3_0 ;
output pre_out_3_1 ;
output pre_out_3_3 ;
output pre_out_3_5 ;
output pre_out_3_7 ;
output pre_out_3_8 ;
output pre_out_3_6 ;
input clk ;
input w_in_a_vec_sub ;
output N_500 ;
output un5_output ;
output un5_output_0 ;
output un5_output_1 ;
output un5_output_2 ;
output un5_output_3 ;
output un5_output_4 ;
wire in_a_r_reg_3_11 ;
wire in_a_r_reg_2_11 ;
wire in_a_r_reg_1_11 ;
wire in_a_r_reg_0_0 ;
wire in_a_r_reg_0_11 ;
wire in_a_i_reg_3_11 ;
wire in_a_i_reg_2_11 ;
wire in_a_i_reg_1_11 ;
wire in_a_i_reg_0_11 ;
wire output_iv_0_0 ;
wire output_iv_0_1 ;
wire output_iv_0_2 ;
wire output_iv_0_3 ;
wire output_iv_0_4 ;
wire output_iv_0_6 ;
wire output_iv_0_7 ;
wire output_iv_0_8 ;
wire output_iv_0_9 ;
wire pre_out_i_m_0_0 ;
wire pre_out_i_m_0_1 ;
wire pre_out_i_m_0_6 ;
wire pre_out_i_m_0_4 ;
wire pre_out_3_9 ;
wire pre_out_3_0 ;
wire pre_out_3_1 ;
wire pre_out_3_3 ;
wire pre_out_3_5 ;
wire pre_out_3_7 ;
wire pre_out_3_8 ;
wire pre_out_3_6 ;
wire clk ;
wire w_in_a_vec_sub ;
wire N_500 ;
wire un5_output ;
wire un5_output_0 ;
wire un5_output_1 ;
wire un5_output_2 ;
wire un5_output_3 ;
wire un5_output_4 ;
wire [10:0] in_a_r_reg_3 ;
wire [10:0] in_a_r_reg_2 ;
wire [10:0] in_a_r_reg_1 ;
wire [10:1] in_a_r_reg_0 ;
wire [10:0] in_a_i_reg_3 ;
wire [10:0] in_a_i_reg_2 ;
wire [10:0] in_a_i_reg_1 ;
wire [10:0] in_a_i_reg_0 ;
wire GND ;
wire VCC ;
input p_desc739_p_O_FDE ;
input p_desc740_p_O_FDE ;
input p_desc741_p_O_FDE ;
input p_desc742_p_O_FDE ;
input p_desc743_p_O_FDE ;
input p_desc744_p_O_FDE ;
input p_desc745_p_O_FDE ;
input p_desc746_p_O_FDE ;
input p_desc747_p_O_FDE ;
input p_desc748_p_O_FDE ;
input p_desc749_p_O_FDE ;
input p_desc750_p_O_FDE ;
input p_desc751_p_O_FDE ;
input p_desc752_p_O_FDE ;
input p_desc753_p_O_FDE ;
input p_desc754_p_O_FDE ;
input p_desc755_p_O_FDE ;
input p_desc756_p_O_FDE ;
input p_desc757_p_O_FDE ;
input p_desc758_p_O_FDE ;
input p_desc759_p_O_FDE ;
input p_desc760_p_O_FDE ;
input p_desc761_p_O_FDE ;
input p_desc762_p_O_FDE ;
input p_desc763_p_O_FDE ;
input p_desc764_p_O_FDE ;
input p_desc765_p_O_FDE ;
input p_desc766_p_O_FDE ;
input p_desc767_p_O_FDE ;
input p_desc768_p_O_FDE ;
input p_desc769_p_O_FDE ;
input p_desc770_p_O_FDE ;
input p_desc771_p_O_FDE ;
input p_desc772_p_O_FDE ;
input p_desc773_p_O_FDE ;
input p_desc774_p_O_FDE ;
input p_desc775_p_O_FDE ;
input p_desc776_p_O_FDE ;
input p_desc777_p_O_FDE ;
input p_desc778_p_O_FDE ;
input p_desc779_p_O_FDE ;
input p_desc780_p_O_FDE ;
input p_desc781_p_O_FDE ;
input p_desc782_p_O_FDE ;
input p_desc783_p_O_FDE ;
input p_desc784_p_O_FDE ;
input p_desc785_p_O_FDE ;
input p_desc786_p_O_FDE ;
input p_desc787_p_O_FDE ;
input p_desc788_p_O_FDE ;
input p_desc789_p_O_FDE ;
input p_desc790_p_O_FDE ;
input p_desc791_p_O_FDE ;
input p_desc792_p_O_FDE ;
input p_desc793_p_O_FDE ;
input p_desc794_p_O_FDE ;
input p_desc795_p_O_FDE ;
input p_desc796_p_O_FDE ;
input p_desc797_p_O_FDE ;
input p_desc798_p_O_FDE ;
input p_desc799_p_O_FDE ;
input p_desc800_p_O_FDE ;
input p_desc801_p_O_FDE ;
input p_desc802_p_O_FDE ;
input p_desc803_p_O_FDE ;
input p_desc804_p_O_FDE ;
input p_desc805_p_O_FDE ;
input p_desc806_p_O_FDE ;
input p_desc807_p_O_FDE ;
input p_desc808_p_O_FDE ;
input p_desc809_p_O_FDE ;
input p_desc810_p_O_FDE ;
input p_desc811_p_O_FDE ;
input p_desc812_p_O_FDE ;
input p_desc813_p_O_FDE ;
input p_desc814_p_O_FDE ;
input p_desc815_p_O_FDE ;
input p_desc816_p_O_FDE ;
input p_desc817_p_O_FDE ;
input p_desc818_p_O_FDE ;
input p_desc819_p_O_FDE ;
input p_desc820_p_O_FDE ;
input p_desc821_p_O_FDE ;
input p_desc822_p_O_FDE ;
input p_desc823_p_O_FDE ;
input p_desc824_p_O_FDE ;
input p_desc825_p_O_FDE ;
input p_desc826_p_O_FDE ;
input p_desc827_p_O_FDE ;
input p_desc828_p_O_FDE ;
input p_desc829_p_O_FDE ;
input p_desc830_p_O_FDE ;
input p_desc831_p_O_FDE ;
input p_desc832_p_O_FDE ;
input p_desc833_p_O_FDE ;
input p_desc834_p_O_FDE ;
// instances
p_O_FDE desc739(.Q(in_a_r_reg_3[0:0]),.D(out_Q_r[0:0]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc739_p_O_FDE));
p_O_FDE desc740(.Q(in_a_r_reg_3[1:1]),.D(out_Q_r[1:1]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc740_p_O_FDE));
p_O_FDE desc741(.Q(in_a_r_reg_3[2:2]),.D(out_Q_r[2:2]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc741_p_O_FDE));
p_O_FDE desc742(.Q(in_a_r_reg_3[3:3]),.D(out_Q_r[3:3]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc742_p_O_FDE));
p_O_FDE desc743(.Q(in_a_r_reg_3[4:4]),.D(out_Q_r[4:4]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc743_p_O_FDE));
p_O_FDE desc744(.Q(in_a_r_reg_3[5:5]),.D(out_Q_r[5:5]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc744_p_O_FDE));
p_O_FDE desc745(.Q(in_a_r_reg_3[6:6]),.D(out_Q_r[6:6]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc745_p_O_FDE));
p_O_FDE desc746(.Q(in_a_r_reg_3[7:7]),.D(out_Q_r[7:7]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc746_p_O_FDE));
p_O_FDE desc747(.Q(in_a_r_reg_3[8:8]),.D(out_Q_r[8:8]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc747_p_O_FDE));
p_O_FDE desc748(.Q(in_a_r_reg_3[9:9]),.D(out_Q_r[9:9]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc748_p_O_FDE));
p_O_FDE desc749(.Q(in_a_r_reg_3[10:10]),.D(out_Q_r[10:10]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc749_p_O_FDE));
p_O_FDE desc750(.Q(in_a_r_reg_3_11),.D(out_Q_r[11:11]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc750_p_O_FDE));
p_O_FDE desc751(.Q(in_a_r_reg_2[0:0]),.D(out_Q_r[12:12]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc751_p_O_FDE));
p_O_FDE desc752(.Q(in_a_r_reg_2[1:1]),.D(out_Q_r[13:13]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc752_p_O_FDE));
p_O_FDE desc753(.Q(in_a_r_reg_2[2:2]),.D(out_Q_r[14:14]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc753_p_O_FDE));
p_O_FDE desc754(.Q(in_a_r_reg_2[3:3]),.D(out_Q_r[15:15]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc754_p_O_FDE));
p_O_FDE desc755(.Q(in_a_r_reg_2[4:4]),.D(out_Q_r[16:16]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc755_p_O_FDE));
p_O_FDE desc756(.Q(in_a_r_reg_2[5:5]),.D(out_Q_r[17:17]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc756_p_O_FDE));
p_O_FDE desc757(.Q(in_a_r_reg_2[6:6]),.D(out_Q_r[18:18]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc757_p_O_FDE));
p_O_FDE desc758(.Q(in_a_r_reg_2[7:7]),.D(out_Q_r[19:19]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc758_p_O_FDE));
p_O_FDE desc759(.Q(in_a_r_reg_2[8:8]),.D(out_Q_r[20:20]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc759_p_O_FDE));
p_O_FDE desc760(.Q(in_a_r_reg_2[9:9]),.D(out_Q_r[21:21]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc760_p_O_FDE));
p_O_FDE desc761(.Q(in_a_r_reg_2[10:10]),.D(out_Q_r[22:22]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc761_p_O_FDE));
p_O_FDE desc762(.Q(in_a_r_reg_2_11),.D(out_Q_r[23:23]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc762_p_O_FDE));
p_O_FDE desc763(.Q(in_a_r_reg_1[0:0]),.D(out_Q_r[24:24]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc763_p_O_FDE));
p_O_FDE desc764(.Q(in_a_r_reg_1[1:1]),.D(out_Q_r[25:25]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc764_p_O_FDE));
p_O_FDE desc765(.Q(in_a_r_reg_1[2:2]),.D(out_Q_r[26:26]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc765_p_O_FDE));
p_O_FDE desc766(.Q(in_a_r_reg_1[3:3]),.D(out_Q_r[27:27]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc766_p_O_FDE));
p_O_FDE desc767(.Q(in_a_r_reg_1[4:4]),.D(out_Q_r[28:28]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc767_p_O_FDE));
p_O_FDE desc768(.Q(in_a_r_reg_1[5:5]),.D(out_Q_r[29:29]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc768_p_O_FDE));
p_O_FDE desc769(.Q(in_a_r_reg_1[6:6]),.D(out_Q_r[30:30]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc769_p_O_FDE));
p_O_FDE desc770(.Q(in_a_r_reg_1[7:7]),.D(out_Q_r[31:31]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc770_p_O_FDE));
p_O_FDE desc771(.Q(in_a_r_reg_1[8:8]),.D(out_Q_r[32:32]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc771_p_O_FDE));
p_O_FDE desc772(.Q(in_a_r_reg_1[9:9]),.D(out_Q_r[33:33]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc772_p_O_FDE));
p_O_FDE desc773(.Q(in_a_r_reg_1[10:10]),.D(out_Q_r[34:34]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc773_p_O_FDE));
p_O_FDE desc774(.Q(in_a_r_reg_1_11),.D(out_Q_r[35:35]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc774_p_O_FDE));
p_O_FDE desc775(.Q(in_a_r_reg_0_0),.D(out_Q_r[36:36]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc775_p_O_FDE));
p_O_FDE desc776(.Q(in_a_r_reg_0[1:1]),.D(out_Q_r[37:37]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc776_p_O_FDE));
p_O_FDE desc777(.Q(in_a_r_reg_0[2:2]),.D(out_Q_r[38:38]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc777_p_O_FDE));
p_O_FDE desc778(.Q(in_a_r_reg_0[3:3]),.D(out_Q_r[39:39]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc778_p_O_FDE));
p_O_FDE desc779(.Q(in_a_r_reg_0[4:4]),.D(out_Q_r[40:40]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc779_p_O_FDE));
p_O_FDE desc780(.Q(in_a_r_reg_0[5:5]),.D(out_Q_r[41:41]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc780_p_O_FDE));
p_O_FDE desc781(.Q(in_a_r_reg_0[6:6]),.D(out_Q_r[42:42]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc781_p_O_FDE));
p_O_FDE desc782(.Q(in_a_r_reg_0[7:7]),.D(out_Q_r[43:43]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc782_p_O_FDE));
p_O_FDE desc783(.Q(in_a_r_reg_0[8:8]),.D(out_Q_r[44:44]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc783_p_O_FDE));
p_O_FDE desc784(.Q(in_a_r_reg_0[9:9]),.D(out_Q_r[45:45]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc784_p_O_FDE));
p_O_FDE desc785(.Q(in_a_r_reg_0[10:10]),.D(out_Q_r[46:46]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc785_p_O_FDE));
p_O_FDE desc786(.Q(in_a_r_reg_0_11),.D(out_Q_r[47:47]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc786_p_O_FDE));
p_O_FDE desc787(.Q(in_a_i_reg_3[0:0]),.D(out_Q_i[0:0]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc787_p_O_FDE));
p_O_FDE desc788(.Q(in_a_i_reg_3[1:1]),.D(out_Q_i[1:1]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc788_p_O_FDE));
p_O_FDE desc789(.Q(in_a_i_reg_3[2:2]),.D(out_Q_i[2:2]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc789_p_O_FDE));
p_O_FDE desc790(.Q(in_a_i_reg_3[3:3]),.D(out_Q_i[3:3]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc790_p_O_FDE));
p_O_FDE desc791(.Q(in_a_i_reg_3[4:4]),.D(out_Q_i[4:4]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc791_p_O_FDE));
p_O_FDE desc792(.Q(in_a_i_reg_3[5:5]),.D(out_Q_i[5:5]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc792_p_O_FDE));
p_O_FDE desc793(.Q(in_a_i_reg_3[6:6]),.D(out_Q_i[6:6]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc793_p_O_FDE));
p_O_FDE desc794(.Q(in_a_i_reg_3[7:7]),.D(out_Q_i[7:7]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc794_p_O_FDE));
p_O_FDE desc795(.Q(in_a_i_reg_3[8:8]),.D(out_Q_i[8:8]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc795_p_O_FDE));
p_O_FDE desc796(.Q(in_a_i_reg_3[9:9]),.D(out_Q_i[9:9]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc796_p_O_FDE));
p_O_FDE desc797(.Q(in_a_i_reg_3[10:10]),.D(out_Q_i[10:10]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc797_p_O_FDE));
p_O_FDE desc798(.Q(in_a_i_reg_3_11),.D(out_Q_i[11:11]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc798_p_O_FDE));
p_O_FDE desc799(.Q(in_a_i_reg_2[0:0]),.D(out_Q_i[12:12]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc799_p_O_FDE));
p_O_FDE desc800(.Q(in_a_i_reg_2[1:1]),.D(out_Q_i[13:13]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc800_p_O_FDE));
p_O_FDE desc801(.Q(in_a_i_reg_2[2:2]),.D(out_Q_i[14:14]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc801_p_O_FDE));
p_O_FDE desc802(.Q(in_a_i_reg_2[3:3]),.D(out_Q_i[15:15]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc802_p_O_FDE));
p_O_FDE desc803(.Q(in_a_i_reg_2[4:4]),.D(out_Q_i[16:16]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc803_p_O_FDE));
p_O_FDE desc804(.Q(in_a_i_reg_2[5:5]),.D(out_Q_i[17:17]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc804_p_O_FDE));
p_O_FDE desc805(.Q(in_a_i_reg_2[6:6]),.D(out_Q_i[18:18]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc805_p_O_FDE));
p_O_FDE desc806(.Q(in_a_i_reg_2[7:7]),.D(out_Q_i[19:19]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc806_p_O_FDE));
p_O_FDE desc807(.Q(in_a_i_reg_2[8:8]),.D(out_Q_i[20:20]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc807_p_O_FDE));
p_O_FDE desc808(.Q(in_a_i_reg_2[9:9]),.D(out_Q_i[21:21]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc808_p_O_FDE));
p_O_FDE desc809(.Q(in_a_i_reg_2[10:10]),.D(out_Q_i[22:22]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc809_p_O_FDE));
p_O_FDE desc810(.Q(in_a_i_reg_2_11),.D(out_Q_i[23:23]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc810_p_O_FDE));
p_O_FDE desc811(.Q(in_a_i_reg_1[0:0]),.D(out_Q_i[24:24]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc811_p_O_FDE));
p_O_FDE desc812(.Q(in_a_i_reg_1[1:1]),.D(out_Q_i[25:25]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc812_p_O_FDE));
p_O_FDE desc813(.Q(in_a_i_reg_1[2:2]),.D(out_Q_i[26:26]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc813_p_O_FDE));
p_O_FDE desc814(.Q(in_a_i_reg_1[3:3]),.D(out_Q_i[27:27]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc814_p_O_FDE));
p_O_FDE desc815(.Q(in_a_i_reg_1[4:4]),.D(out_Q_i[28:28]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc815_p_O_FDE));
p_O_FDE desc816(.Q(in_a_i_reg_1[5:5]),.D(out_Q_i[29:29]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc816_p_O_FDE));
p_O_FDE desc817(.Q(in_a_i_reg_1[6:6]),.D(out_Q_i[30:30]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc817_p_O_FDE));
p_O_FDE desc818(.Q(in_a_i_reg_1[7:7]),.D(out_Q_i[31:31]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc818_p_O_FDE));
p_O_FDE desc819(.Q(in_a_i_reg_1[8:8]),.D(out_Q_i[32:32]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc819_p_O_FDE));
p_O_FDE desc820(.Q(in_a_i_reg_1[9:9]),.D(out_Q_i[33:33]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc820_p_O_FDE));
p_O_FDE desc821(.Q(in_a_i_reg_1[10:10]),.D(out_Q_i[34:34]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc821_p_O_FDE));
p_O_FDE desc822(.Q(in_a_i_reg_1_11),.D(out_Q_i[35:35]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc822_p_O_FDE));
p_O_FDE desc823(.Q(in_a_i_reg_0[0:0]),.D(out_Q_i[36:36]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc823_p_O_FDE));
p_O_FDE desc824(.Q(in_a_i_reg_0[1:1]),.D(out_Q_i[37:37]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc824_p_O_FDE));
p_O_FDE desc825(.Q(in_a_i_reg_0[2:2]),.D(out_Q_i[38:38]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc825_p_O_FDE));
p_O_FDE desc826(.Q(in_a_i_reg_0[3:3]),.D(out_Q_i[39:39]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc826_p_O_FDE));
p_O_FDE desc827(.Q(in_a_i_reg_0[4:4]),.D(out_Q_i[40:40]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc827_p_O_FDE));
p_O_FDE desc828(.Q(in_a_i_reg_0[5:5]),.D(out_Q_i[41:41]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc828_p_O_FDE));
p_O_FDE desc829(.Q(in_a_i_reg_0[6:6]),.D(out_Q_i[42:42]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc829_p_O_FDE));
p_O_FDE desc830(.Q(in_a_i_reg_0[7:7]),.D(out_Q_i[43:43]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc830_p_O_FDE));
p_O_FDE desc831(.Q(in_a_i_reg_0[8:8]),.D(out_Q_i[44:44]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc831_p_O_FDE));
p_O_FDE desc832(.Q(in_a_i_reg_0[9:9]),.D(out_Q_i[45:45]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc832_p_O_FDE));
p_O_FDE desc833(.Q(in_a_i_reg_0[10:10]),.D(out_Q_i[46:46]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc833_p_O_FDE));
p_O_FDE desc834(.Q(in_a_i_reg_0_11),.D(out_Q_i[47:47]),.C(clk),.CE(w_in_a_vec_sub),.E(p_desc834_p_O_FDE));
add_subZ3_inj desc835(.pre_out_10(pre_out[11:11]),.output_iv_0(output_iv[1:1]),.output_iv_1(output_iv[2:2]),.output_iv_9(output_iv[10:10]),.output_iv_8(output_iv[9:9]),.output_iv_6(output_iv[7:7]),.output_iv_7(output_iv[8:8]),.output_iv_2(output_iv[3:3]),.output_iv_3(output_iv[4:4]),.output_iv_4(output_iv[5:5]),.out_r_vec_mult_0(out_r_vec_mult_0[11:0]),.in_a_r_reg_0({in_a_r_reg_0_11,in_a_r_reg_0[10:1],in_a_r_reg_0_0}),.N_500(N_500));
add_subZ3_1_inj desc836(.pre_out_i_m_8(pre_out_i_m[8:8]),.pre_out_i_m_4(pre_out_i_m[4:4]),.pre_out_i_m_0(pre_out_i_m[0:0]),.out_r_vec_mult_1(out_r_vec_mult_1[11:0]),.in_a_r_reg_1({in_a_r_reg_1_11,in_a_r_reg_1[10:0]}),.pre_out_10(pre_out_0[11:11]),.pre_out_9(pre_out[10:10]),.pre_out_8(pre_out[9:9]),.pre_out_6(pre_out[7:7]),.pre_out_5(pre_out[6:6]),.pre_out_4(pre_out[5:5]),.pre_out_2(pre_out[3:3]),.pre_out_1(pre_out[2:2]),.pre_out_0(pre_out[1:1]),.un5_output(un5_output));
add_subZ3_2_inj desc837(.out_r_vec_mult_2(out_r_vec_mult_2[11:0]),.in_a_r_reg_2({in_a_r_reg_2_11,in_a_r_reg_2[10:0]}),.pre_out_i_m_6(pre_out_i_m[6:6]),.pre_out_i_m_0(pre_out_i_m_0_0),.pre_out_10(pre_out_1[11:11]),.pre_out_9(pre_out_0[10:10]),.pre_out_8(pre_out_0[9:9]),.pre_out_7(pre_out[8:8]),.pre_out_6(pre_out_0[7:7]),.pre_out_4(pre_out_0[5:5]),.pre_out_3(pre_out[4:4]),.pre_out_2(pre_out_0[3:3]),.pre_out_1(pre_out_0[2:2]),.pre_out_0(pre_out_0[1:1]),.un5_output(un5_output_0));
add_subZ3_3_inj desc838(.out_r_vec_mult_3(out_r_vec_mult_3[11:0]),.in_a_r_reg_3({in_a_r_reg_3_11,in_a_r_reg_3[10:0]}),.pre_out_i_m({pre_out_i_m[1:1],pre_out_i_m_1}),.pre_out_10(pre_out_2[11:11]),.pre_out_9(pre_out_1[10:10]),.pre_out_8(pre_out_1[9:9]),.pre_out_7(pre_out_0[8:8]),.pre_out_6(pre_out_1[7:7]),.pre_out_5(pre_out_0[6:6]),.pre_out_4(pre_out_1[5:5]),.pre_out_3(pre_out_0[4:4]),.pre_out_2(pre_out_1[3:3]),.pre_out_1(pre_out_1[2:2]),.un5_output(un5_output_1));
add_subZ3_4_inj desc839(.pre_out_10(pre_out_3_9),.output_iv({output_iv_0_9,output_iv_0_8,output_iv_0_7,output_iv_0_6,output_iv[6:6],output_iv_0_4,output_iv_0_3,output_iv_0_2,output_iv_0_1,output_iv_0_0,output_iv[0:0]}),.out_i_vec_sub_0(out_i_vec_sub_0[11:11]),.out_i_vec_mult_0(out_i_vec_mult_0[11:0]),.in_a_i_reg_0({in_a_i_reg_0_11,in_a_i_reg_0[10:0]}));
add_subZ3_5_inj desc840(.pre_out_i_m(pre_out_i_m_2),.out_i_vec_mult_1(out_i_vec_mult_1[11:0]),.in_a_i_reg_1({in_a_i_reg_1_11,in_a_i_reg_1[10:0]}),.pre_out({pre_out_4[11:11],pre_out_2[10:9],pre_out_1[8:8],pre_out_2[7:7],pre_out_1[6:6],pre_out_2[5:5],pre_out_1[4:4],pre_out_2[3:2],pre_out_1[1:1]}),.un5_output(un5_output_2));
add_subZ3_6_inj desc841(.pre_out_i_m(pre_out_i_m_3),.out_i_vec_mult_2(out_i_vec_mult_2[11:0]),.in_a_i_reg_2({in_a_i_reg_2_11,in_a_i_reg_2[10:0]}),.pre_out({pre_out_5[11:11],pre_out_3_8,pre_out_3_7,pre_out_2[8:8],pre_out_3_5,pre_out_2[6:6],pre_out_3_3,pre_out_2[4:4],pre_out_3_1,pre_out_3_0,pre_out_2[1:1]}),.un5_output(un5_output_3));
add_subZ3_7_inj desc842(.out_i_vec_mult_3(out_i_vec_mult_3[11:0]),.in_a_i_reg_3({in_a_i_reg_3_11,in_a_i_reg_3[10:0]}),.pre_out_i_m_1(pre_out_i_m_0_1),.pre_out_i_m_5(pre_out_i_m[5:5]),.pre_out_i_m_2(pre_out_i_m[2:2]),.pre_out_i_m_10(pre_out_i_m[10:10]),.pre_out_i_m_9(pre_out_i_m[9:9]),.pre_out_i_m_6(pre_out_i_m_0_6),.pre_out_i_m_7(pre_out_i_m[7:7]),.pre_out_i_m_3(pre_out_i_m[3:3]),.pre_out_i_m_4(pre_out_i_m_0_4),.pre_out_i_m_0(pre_out_i_m_4),.pre_out_10(pre_out_6[11:11]),.pre_out_7(pre_out_3_6),.un5_output(un5_output_4));
VCC VCC_cZ(.P(VCC));
GND GND_cZ(.G(GND));
endmodule
|
`timescale 1ns / 1ps
/*
**
** This file is accompanied by the document
** "METU CENG232 FPGA Board User Manual"
**
** v1.0, 07-April-2012
**
** www.ceng.metu.edu.tr
*/
module Board232 (
input mclk,
input [3:0] btn,
input [7:0] sw,
output [7:0] led,
output reg [6:0] seg,
output reg [3:0] an,
output dp,
output [2:1] OutBlue,
output [2:0] OutGreen,
output [2:0] OutRed,
output HS,
output VS
);
// 7-segments, individual segments and dot
// set to 0 to enable, 1 to disable a segment
assign dp = 1'b1;
// 7-segments, enable bits
// set to 0 to enable, 1 to disable a display
// LEDs
assign led[7] = btn[3]; // Show Clock at leftmost LED
assign led[6] = 1'b0;
wire [7:0] lab3_credit;
BasicVendingMachine BVM(
sw[2:0], // input [2:0] KeyPad
sw[7:6], // input [1:0] Mode
btn[3], // input CLK
btn[0], // input RESET
lab3_credit, // output reg [7:0] Credit,
led[5:0] // output reg [5:0] Coins
);
//-----------------------------------------------------------------------------------------------
//-----------------------------------------------------------------------------------------------
// Rest of the file handles displaying of lab3_credit onto 7-segment displays
//
reg [18:0] sevenseg_refresh_counter;
initial sevenseg_refresh_counter<= 0;
always @(posedge mclk) sevenseg_refresh_counter = sevenseg_refresh_counter+1;
wire [3:0] lab3_credit_ones;
wire [3:0] lab3_credit_tens;
wire [3:0] lab3_credit_hundreds;
binary_to_BCD b2bcd(lab3_credit, lab3_credit_ones, lab3_credit_tens, lab3_credit_hundreds);
reg [3:0] tmp_digit;
always @(sevenseg_refresh_counter[18:17])
begin
case (sevenseg_refresh_counter[18:17])
2'b00:
begin
an = 4'b1110;
tmp_digit = lab3_credit_ones;
end
2'b01:
begin
an = 4'b1101;
tmp_digit = lab3_credit_tens;
end
2'b10:
begin
an = 4'b1011;
tmp_digit = lab3_credit_hundreds;
end
default:
begin
an = 4'b0111;
tmp_digit = 0;
end
endcase
case (tmp_digit)
4'd0: seg <= ~7'h3F;
4'd1: seg <= ~7'h06;
4'd2: seg <= ~7'h5B;
4'd3: seg <= ~7'h4F;
4'd4: seg <= ~7'h66;
4'd5: seg <= ~7'h6D;
4'd6: seg <= ~7'h7D;
4'd7: seg <= ~7'h07;
4'd8: seg <= ~7'h7F;
4'd9: seg <= ~7'h6F;
default: seg <= ~7'b1111000;
endcase
end
// VGA
assign OutBlue = 0;
assign OutGreen = 0;
assign OutRed = 0;
assign HS = 0;
assign VS = 0;
endmodule
module binary_to_BCD(A,ONES,TENS,HUNDREDS);
input [7:0] A;
output [3:0] ONES, TENS, HUNDREDS;
wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,A[7:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};
binary_to_BCD_add3 m1(d1,c1);
binary_to_BCD_add3 m2(d2,c2);
binary_to_BCD_add3 m3(d3,c3);
binary_to_BCD_add3 m4(d4,c4);
binary_to_BCD_add3 m5(d5,c5);
binary_to_BCD_add3 m6(d6,c6);
binary_to_BCD_add3 m7(d7,c7);
assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};
assign HUNDREDS = {0,0,c6[3],c7[3]};
endmodule
module binary_to_BCD_add3(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @ (in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_monitor_128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Detects transaction open/close events from the stream
// of data from the tx_port_channel_gate. Filters out events and passes data
// onto the tx_port_buffer.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTMON128_NEXT 6'b00_0001
`define S_TXPORTMON128_EVT_2 6'b00_0010
`define S_TXPORTMON128_TXN 6'b00_0100
`define S_TXPORTMON128_READ 6'b00_1000
`define S_TXPORTMON128_END_0 6'b01_0000
`define S_TXPORTMON128_END_1 6'b10_0000
`timescale 1ns/1ns
module tx_port_monitor_128 #(
parameter C_DATA_WIDTH = 9'd128,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_THRESH = (C_FIFO_DEPTH - 4),
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1),
parameter C_VALID_HIST = 1
)
(
input RST,
input CLK,
input [C_DATA_WIDTH:0] EVT_DATA, // Event data from tx_port_channel_gate
input EVT_DATA_EMPTY, // Event data FIFO is empty
output EVT_DATA_RD_EN, // Event data FIFO read enable
output [C_DATA_WIDTH-1:0] WR_DATA, // Output data
output WR_EN, // Write enable for output data
input [C_FIFO_DEPTH_WIDTH-1:0] WR_COUNT, // Output FIFO count
output TXN, // Transaction parameters are valid
input ACK, // Transaction parameter read, continue
output LAST, // Channel last write
output [31:0] LEN, // Channel write length (in 32 bit words)
output [30:0] OFF, // Channel write offset
output [31:0] WORDS_RECVD, // Count of data words received in transaction
output DONE, // Transaction is closed
input TX_ERR // Transaction encountered an error
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [5:0] rState=`S_TXPORTMON128_NEXT, _rState=`S_TXPORTMON128_NEXT;
reg rRead=0, _rRead=0;
reg [C_VALID_HIST-1:0] rDataValid={C_VALID_HIST{1'd0}}, _rDataValid={C_VALID_HIST{1'd0}};
reg rEvent=0, _rEvent=0;
reg [63:0] rReadData=64'd0, _rReadData=64'd0;
reg [31:0] rWordsRecvd=0, _rWordsRecvd=0;
reg [31:0] rWordsRecvdAdv=0, _rWordsRecvdAdv=0;
reg rAlmostAllRecvd=0, _rAlmostAllRecvd=0;
reg rAlmostFull=0, _rAlmostFull=0;
reg rLenEQ0Hi=0, _rLenEQ0Hi=0;
reg rLenEQ0Lo=0, _rLenEQ0Lo=0;
reg rLenLE4Lo=0, _rLenLE4Lo=0;
reg rTxErr=0, _rTxErr=0;
wire wEventData = (rDataValid[0] & EVT_DATA[C_DATA_WIDTH]);
wire wPayloadData = (rDataValid[0] & !EVT_DATA[C_DATA_WIDTH] & rState[3]); // S_TXPORTMON128_READ
wire wAllWordsRecvd = ((rAlmostAllRecvd | (rLenEQ0Hi & rLenLE4Lo)) & wPayloadData);
assign EVT_DATA_RD_EN = rRead;
assign WR_DATA = EVT_DATA[C_DATA_WIDTH-1:0];
assign WR_EN = wPayloadData; // S_TXPORTMON128_READ
assign TXN = rState[2]; // S_TXPORTMON128_TXN
assign LAST = rReadData[0];
assign OFF = rReadData[31:1];
assign LEN = rReadData[63:32];
assign WORDS_RECVD = rWordsRecvd;
assign DONE = !rState[3]; // !S_TXPORTMON128_READ
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxErr <= #1 (RST ? 1'd0 : _rTxErr);
end
always @ (*) begin
_rTxErr = TX_ERR;
end
// Transaction monitoring FSM.
always @ (posedge CLK) begin
rState <= #1 (RST ? `S_TXPORTMON128_NEXT : _rState);
end
always @ (*) begin
_rState = rState;
case (rState)
`S_TXPORTMON128_NEXT: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_EVT_2;
end
`S_TXPORTMON128_EVT_2: begin // Read, wait for start of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_TXN;
end
`S_TXPORTMON128_TXN: begin // Don't read, wait until transaction has been acknowledged
if (ACK)
_rState = ((rLenEQ0Hi && rLenEQ0Lo) ? `S_TXPORTMON128_END_0 : `S_TXPORTMON128_READ);
end
`S_TXPORTMON128_READ: begin // Continue reading, wait for end of transaction event or all expected data
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
else if (wAllWordsRecvd | rTxErr)
_rState = `S_TXPORTMON128_END_0;
end
`S_TXPORTMON128_END_0: begin // Continue reading, wait for first end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_END_1;
end
`S_TXPORTMON128_END_1: begin // Continue reading, wait for second end of transaction event
if (rEvent)
_rState = `S_TXPORTMON128_NEXT;
end
default: begin
_rState = `S_TXPORTMON128_NEXT;
end
endcase
end
// Manage reading from the FIFO and tracking amounts read.
always @ (posedge CLK) begin
rRead <= #1 (RST ? 1'd0 : _rRead);
rDataValid <= #1 (RST ? {C_VALID_HIST{1'd0}} : _rDataValid);
rEvent <= #1 (RST ? 1'd0 : _rEvent);
rReadData <= #1 _rReadData;
rWordsRecvd <= #1 _rWordsRecvd;
rWordsRecvdAdv <= #1 _rWordsRecvdAdv;
rAlmostAllRecvd <= #1 _rAlmostAllRecvd;
rAlmostFull <= #1 _rAlmostFull;
rLenEQ0Hi <= #1 _rLenEQ0Hi;
rLenEQ0Lo <= #1 _rLenEQ0Lo;
rLenLE4Lo <= #1 _rLenLE4Lo;
end
always @ (*) begin
// Don't get to the full point in the output FIFO
_rAlmostFull = (WR_COUNT >= C_FIFO_DEPTH_THRESH);
// Track read history so we know when data is valid
_rDataValid = ((rDataValid<<1) | (rRead & !EVT_DATA_EMPTY));
// Read until we get a (valid) event
_rRead = (!rState[2] & !(rState[1] & rEvent) & !wEventData & !rAlmostFull); // !S_TXPORTMON128_TXN
// Track detected events
_rEvent = wEventData;
// Save event data when valid
if (wEventData)
_rReadData = EVT_DATA[63:0];
else
_rReadData = rReadData;
// If LEN == 0, we don't want to send any data to the output
_rLenEQ0Hi = (LEN[31:16] == 16'd0);
_rLenEQ0Lo = (LEN[15:0] == 16'd0);
// If LEN <= 4, we want to trigger the almost all received flag
_rLenLE4Lo = (LEN[15:0] <= 16'd4);
// Count received non-event data
_rWordsRecvd = (ACK ? 0 : rWordsRecvd + (wPayloadData<<2));
_rWordsRecvdAdv = (ACK ? 2*(C_DATA_WIDTH/32) : rWordsRecvdAdv + (wPayloadData<<2));
_rAlmostAllRecvd = ((rWordsRecvdAdv >= LEN) && wPayloadData);
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({TXN, wPayloadData, wEventData, rState}),
.DATA({201'd0,
rWordsRecvd, // 32
WR_COUNT, // 10
wPayloadData, // 1
EVT_DATA_RD_EN, // 1
RST, // 1
rTxErr, // 1
wEventData, // 1
rReadData, // 64
OFF, // 31
LEN, // 32
LAST, // 1
TXN, // 1
EVT_DATA_EMPTY, // 1
EVT_DATA, // 129
rState}) // 5
);
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX2I_2_V
`define SKY130_FD_SC_HD__MUX2I_2_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_2 (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__mux2i_2 (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX2I_2_V
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rxr_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The RXR Engine (Classic) takes a single stream of TLP
// packets and provides the request packets on the RXR Interface.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "tlp.vh"
module rxr_engine_classic
#(parameter C_VENDOR = "ALTERA",
parameter C_PCI_DATA_WIDTH = 128,
parameter C_RX_PIPELINE_DEPTH=10)
(// Interface: Clocks
input CLK,
// Interface: Resets
input RST_BUS, // Replacement for generic RST_IN
input RST_LOGIC, // Addition for RIFFA_RST
output DONE_RXR_RST,
// Interface: RX Classic
input [C_PCI_DATA_WIDTH-1:0] RX_TLP,
input RX_TLP_VALID,
input RX_TLP_START_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_START_OFFSET,
input RX_TLP_END_FLAG,
input [`SIG_OFFSET_W-1:0] RX_TLP_END_OFFSET,
input [`SIG_BARDECODE_W-1:0] RX_TLP_BAR_DECODE,
// Interface: RXR
output [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
output RXR_DATA_VALID,
output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
output RXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
output RXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
output [`SIG_FBE_W-1:0] RXR_META_FDWBE,
output [`SIG_LBE_W-1:0] RXR_META_LDWBE,
output [`SIG_TC_W-1:0] RXR_META_TC,
output [`SIG_ATTR_W-1:0] RXR_META_ATTR,
output [`SIG_TAG_W-1:0] RXR_META_TAG,
output [`SIG_TYPE_W-1:0] RXR_META_TYPE,
output [`SIG_ADDR_W-1:0] RXR_META_ADDR,
output [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
output [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
output [`SIG_LEN_W-1:0] RXR_META_LENGTH,
output RXR_META_EP,
// Interface: RX Shift Register
input [(C_RX_PIPELINE_DEPTH+1)*C_PCI_DATA_WIDTH-1:0] RX_SR_DATA,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_EOP,
input [(C_RX_PIPELINE_DEPTH+1)*`SIG_OFFSET_W-1:0] RX_SR_END_OFFSET,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_SOP,
input [C_RX_PIPELINE_DEPTH:0] RX_SR_VALID
);
/*AUTOWIRE*/
///*AUTOOUTPUT*/
// End of automatics
localparam C_RX_BE_W = (`SIG_FBE_W+`SIG_LBE_W);
localparam C_RX_INPUT_STAGES = 1;
localparam C_RX_OUTPUT_STAGES = 1; // Must always be at least one
localparam C_RX_COMPUTATION_STAGES = 1;
localparam C_TOTAL_STAGES = C_RX_COMPUTATION_STAGES + C_RX_OUTPUT_STAGES + C_RX_INPUT_STAGES;
// Cycle index in the SOP register when enable is raised
// Computation can begin when the last DW of the header is recieved.
localparam C_RX_COMPUTATION_CYCLE = C_RX_COMPUTATION_STAGES + (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
// The computation cycle must be at least one cycle before the address is enabled
localparam C_RX_DATA_CYCLE = C_RX_COMPUTATION_CYCLE;
localparam C_RX_ADDRDW0_CYCLE = (`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW1_CYCLE = (`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW0_CYCLE = (`TLP_REQMETADW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_METADW1_CYCLE = (`TLP_REQMETADW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES;
localparam C_RX_ADDRDW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH);
localparam C_RX_ADDRDW1_RESET_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +
C_PCI_DATA_WIDTH*(C_RX_ADDRDW1_CYCLE - C_RX_METADW0_CYCLE) +
`TLP_4DWHBIT_I;
localparam C_RX_METADW0_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW0_I%C_PCI_DATA_WIDTH);
localparam C_RX_METADW1_INDEX = C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES + (`TLP_REQMETADW1_I%C_PCI_DATA_WIDTH);
localparam C_OFFSET_WIDTH = clog2s(C_PCI_DATA_WIDTH/32);
localparam C_MAX_ABLANK_WIDTH = 32;
localparam C_MAX_START_OFFSET = (`TLP_MAXHDR_W + C_MAX_ABLANK_WIDTH)/32;
localparam C_STD_START_DELAY = (64/C_PCI_DATA_WIDTH);
wire [63:0] wAddrFmt;
wire [63:0] wMetadata;
wire [`TLP_TYPE_W-1:0] wType;
wire [`TLP_LEN_W-1:0] wLength;
wire wAddrDW0Bit2;
wire wAddrDW1Bit2;
wire wAddrHiReset;
wire [31:0] wAddrMux[(`TLP_REQADDR_W / 32)-1:0];
wire [63:0] wAddr;
wire w4DWH;
wire wHasPayload;
wire [2:0] wHdrLength;
wire [2:0] wHdrLengthM1;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wEndMask;
wire _wEndFlag;
wire wEndFlag;
wire [C_OFFSET_WIDTH-1:0] wEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wStartMask;
wire [3:0] wStartFlags;
wire wStartFlag;
wire _wStartFlag;
wire [clog2s(C_MAX_START_OFFSET)-1:0] wStartOffset;
wire wInsertBlank;
wire wRotateAddressField;
wire [C_PCI_DATA_WIDTH-1:0] wRxrData;
wire [`SIG_ADDR_W-1:0] wRxrMetaAddr;
wire [63:0] wRxrMetadata;
wire wRxrDataValid;
wire wRxrDataReady; // Pinned High
wire wRxrDataEndFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataEndOffset;
wire [(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataWordEnable;
wire wRxrDataStartFlag;
wire [C_OFFSET_WIDTH-1:0] wRxrDataStartOffset;
wire [C_RX_PIPELINE_DEPTH:0] wRxSrSop;
reg rValid,_rValid;
reg rRST;
assign DONE_RXR_RST = ~rRST;
assign wAddrHiReset = ~RX_SR_DATA[C_RX_ADDRDW1_RESET_INDEX];
// Select Addr[31:0] from one of the two possible locations in the TLP based
// on header length (1 bit)
assign wRotateAddressField = w4DWH;
assign wAddrFmt = {wAddrMux[~wRotateAddressField],wAddrMux[wRotateAddressField]};
assign wAddrMux[0] = wAddr[31:0];
assign wAddrMux[1] = wAddr[63:32];
// Calculate the header length (start offset), and header length minus 1 (end offset)
assign wHdrLength = {w4DWH,~w4DWH,~w4DWH};
assign wHdrLengthM1 = {1'b0,1'b1,w4DWH};
// Determine if the TLP has an inserted blank before the payload
assign wInsertBlank = ((w4DWH & wAddrDW1Bit2) | (~w4DWH & ~wAddrDW0Bit2)) & (C_VENDOR == "ALTERA");
assign wStartOffset = (wHdrLength + {2'd0,wInsertBlank}); // Start offset in dwords
assign wEndOffset = wHdrLengthM1 + wInsertBlank + wLength;//RX_SR_END_OFFSET[(C_TOTAL_STAGES-1)*`SIG_OFFSET_W +: C_OFFSET_WIDTH];
// Inputs
// Technically an input, but the trellis protocol specifies it must be held high at all times
assign wRxrDataReady = 1;
// Outputs
assign RXR_DATA = RX_SR_DATA[(C_TOTAL_STAGES)*C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
assign RXR_DATA_VALID = wRxrDataValid;
assign RXR_DATA_END_FLAG = wRxrDataEndFlag;
assign RXR_DATA_END_OFFSET = wRxrDataEndOffset;
assign RXR_DATA_START_FLAG = wRxrDataStartFlag;
assign RXR_DATA_START_OFFSET = wRxrDataStartOffset;
assign RXR_META_BAR_DECODED = 0;
assign RXR_META_LENGTH = wRxrMetadata[`TLP_LEN_R];
assign RXR_META_TC = wRxrMetadata[`TLP_TC_R];
assign RXR_META_ATTR = {wRxrMetadata[`TLP_ATTR1_R], wRxrMetadata[`TLP_ATTR0_R]};
assign RXR_META_TYPE = tlp_to_trellis_type({wRxrMetadata[`TLP_FMT_R],wRxrMetadata[`TLP_TYPE_R]});
assign RXR_META_ADDR = wRxrMetaAddr;
assign RXR_META_REQUESTER_ID = wRxrMetadata[`TLP_REQREQID_R];
assign RXR_META_TAG = wRxrMetadata[`TLP_REQTAG_R];
assign RXR_META_FDWBE = wRxrMetadata[`TLP_REQFBE_R];
assign RXR_META_LDWBE = wRxrMetadata[`TLP_REQLBE_R];
assign RXR_META_EP = wRxrMetadata[`TLP_EP_R];
assign _wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES];
assign wEndFlag = RX_SR_EOP[C_RX_INPUT_STAGES+1];
assign _wStartFlag = wStartFlags != 0;
generate
if(C_PCI_DATA_WIDTH == 32) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 3] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 2] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if(C_PCI_DATA_WIDTH == 64) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 2] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Any remaining cases
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~wMetadata[`TLP_4DWHBIT_I]; // 3DWH, No Blank
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES + 1] & ~wMetadata[`TLP_PAYBIT_I]; // No Payload
end else if (C_PCI_DATA_WIDTH == 128) begin
assign wStartFlags[3] = 0;
assign wStartFlags[2] = wRxSrSop[C_RX_INPUT_STAGES + 1] & wMetadata[`TLP_PAYBIT_I] & ~rValid; // Is this correct?
if(C_VENDOR == "ALTERA") begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I] & RX_SR_DATA[C_RX_ADDRDW0_INDEX + 2]; // 3DWH, No Blank
end else begin
assign wStartFlags[1] = wRxSrSop[C_RX_INPUT_STAGES] & RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_4DWHBIT_I];
end
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES] & ~RX_SR_DATA[C_RX_METADW0_INDEX + `TLP_PAYBIT_I]; // No Payload
end else begin // 256
assign wStartFlags[3] = 0;
assign wStartFlags[2] = 0;
assign wStartFlags[1] = 0;
assign wStartFlags[0] = wRxSrSop[C_RX_INPUT_STAGES];
end // else: !if(C_PCI_DATA_WIDTH == 128)
endgenerate
always @(*) begin
_rValid = rValid;
if(_wStartFlag) begin
_rValid = 1'b1;
end else if (wEndFlag) begin
_rValid = 1'b0;
end
end
always @(posedge CLK) begin
if(rRST) begin
rValid <= 1'b0;
end else begin
rValid <= _rValid;
end
end
always @(posedge CLK) begin
rRST <= RST_BUS | RST_LOGIC;
end
assign wStartMask = {C_PCI_DATA_WIDTH/32{1'b1}} << ({C_OFFSET_WIDTH{wStartFlag}}& wStartOffset[C_OFFSET_WIDTH-1:0]);
offset_to_mask
#(// Parameters
.C_MASK_SWAP (0),
.C_MASK_WIDTH (C_PCI_DATA_WIDTH/32)
/*AUTOINSTPARAM*/)
o2m_ef
(
// Outputs
.MASK (wEndMask),
// Inputs
.OFFSET_ENABLE (wEndFlag),
.OFFSET (wEndOffset[C_OFFSET_WIDTH-1:0])
/*AUTOINST*/);
generate
if(C_RX_OUTPUT_STAGES == 0) begin
assign RXR_DATA_WORD_ENABLE = {wEndMask & wStartMask} & {C_PCI_DATA_WIDTH/32{~rValid | ~wMetadata[`TLP_PAYBIT_I]}};
end else begin
register
#(
// Parameters
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
dw_enable
(// Outputs
.RD_DATA (wRxrDataWordEnable),
// Inputs
.RST_IN (~rValid | ~wMetadata[`TLP_PAYBIT_I]),
.WR_DATA (wEndMask & wStartMask),
.WR_EN (1),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(
// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES-1),
.C_WIDTH (C_PCI_DATA_WIDTH/32),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
dw_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA (RXR_DATA_WORD_ENABLE),
.RD_DATA_VALID (),
// Inputs
.WR_DATA (wRxrDataWordEnable),
.WR_DATA_VALID (1),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
end
endgenerate
register
#(
// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_DW0_register
(
// Outputs
.RD_DATA (wMetadata[31:0]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_METADW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW0_CYCLE]),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
meta_DW1_register
(// Outputs
.RD_DATA (wMetadata[63:32]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_METADW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_METADW1_CYCLE]),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW0_register
(// Outputs
.RD_DATA (wAddr[31:0]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_ADDRDW0_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW0_CYCLE]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (32),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW1_register
(// Outputs
.RD_DATA (wAddr[63:32]),
// Inputs
.WR_DATA (RX_SR_DATA[C_RX_ADDRDW1_INDEX +: 32]),
.WR_EN (wRxSrSop[C_RX_ADDRDW1_CYCLE]),
.RST_IN (wAddrHiReset & wRxSrSop[C_RX_ADDRDW1_CYCLE]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (2),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_4DWH_register
(// Outputs
.RD_DATA ({wHasPayload,w4DWH}),
// Inputs
.WR_DATA (RX_SR_DATA[`TLP_FMT_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES +: 2]),
.WR_EN (wRxSrSop[`TLP_4DWHBIT_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_TYPE_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_type_register
(// Outputs
.RD_DATA (wType),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_TYPE_I/* + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES*/) +: `TLP_TYPE_W]),
.WR_EN (wRxSrSop[`TLP_TYPE_I/C_PCI_DATA_WIDTH/* + C_RX_INPUT_STAGES*/]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (`TLP_LEN_W),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
metadata_length_register
(// Outputs
.RD_DATA (wLength),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_LEN_I + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES) +: `TLP_LEN_W]),
.WR_EN (wRxSrSop[`TLP_LEN_I/C_PCI_DATA_WIDTH + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW0_bit_2_register
(// Outputs
.RD_DATA (wAddrDW0Bit2),
// Inputs
.RST_IN (0),
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW0_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
.WR_EN (wRxSrSop[(`TLP_REQADDRDW0_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
addr_DW1_bit_2_register
(// Outputs
.RD_DATA (wAddrDW1Bit2),
// Inputs
.WR_DATA (RX_SR_DATA[(`TLP_REQADDRDW1_I%C_PCI_DATA_WIDTH) + 2 + C_PCI_DATA_WIDTH*C_RX_INPUT_STAGES]),
.WR_EN (wRxSrSop[(`TLP_REQADDRDW1_I/C_PCI_DATA_WIDTH) + C_RX_INPUT_STAGES]),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
register
#(// Parameters
.C_WIDTH (1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
start_flag_register
(// Outputs
.RD_DATA (wStartFlag),
// Inputs
.WR_DATA (_wStartFlag),
.WR_EN (1),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
pipeline
#(// Parameters
.C_DEPTH (C_RX_OUTPUT_STAGES),
.C_WIDTH (`TLP_MAXHDR_W + 2*(1 + C_OFFSET_WIDTH)),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_pipeline
(// Outputs
.WR_DATA_READY (), // Pinned to 1
.RD_DATA ({wRxrMetadata,wRxrMetaAddr,wRxrDataStartFlag,wRxrDataStartOffset,wRxrDataEndFlag,wRxrDataEndOffset}),
.RD_DATA_VALID (wRxrDataValid),
// Inputs
.WR_DATA ({wMetadata, wAddrFmt, wStartFlag,wStartOffset[C_OFFSET_WIDTH-1:0],wEndFlag,wEndOffset[C_OFFSET_WIDTH-1:0]}),
.WR_DATA_VALID (rValid & RX_SR_VALID[C_TOTAL_STAGES-C_RX_OUTPUT_STAGES]),
.RD_DATA_READY (1'b1),
.RST_IN (rRST),
/*AUTOINST*/
// Inputs
.CLK (CLK));
// Start Flag Shift Register. Data enables are derived from the
// taps on this shift register.
shiftreg
#(// Parameters
.C_DEPTH (C_RX_PIPELINE_DEPTH),
.C_WIDTH (1'b1),
.C_VALUE (0)
/*AUTOINSTPARAM*/)
sop_shiftreg_inst
(// Outputs
.RD_DATA (wRxSrSop),
// Inputs
.WR_DATA (RX_TLP_START_FLAG & RX_TLP_VALID & (RX_SR_DATA[`TLP_TYPE_R] == `TLP_TYPE_REQ)),
.RST_IN (0),
/*AUTOINST*/
// Inputs
.CLK (CLK));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common")
// End:
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History:
// 2010/01/09/ Corrected dfifo_has_enough_room threshold logic.
// It has to set higher in Read Only port.
//*****************************************************************************
`timescale 1ps/1ps
module read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input cmd_valid_i,
input data_valid_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input user_bl_cnt_is_1,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
input gen_rdy_i,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output [6:0] rd_buff_avail_o,
input rd_mdata_fifo_empty,
output rd_mdata_en
);
reg empty_r;
reg rd_first_data;
wire full;
wire empty;
wire wr_en;
reg rd_en;
reg data_valid_r;
reg user_bl_cnt_not_1;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en;
assign rd_buff_avail_o = buf_avail_r;
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room & wait_done;
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin // prbs_blen from cmd_gen is random, it can be two 64 in consecutive
// the logic here to prevent cmd_gen send any further read command if
// any large bl command has been sent.
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 62 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
assign wr_en = cmd_valid_i & !full & dfifo_has_enough_room_d1 & wait_done;
always @ (posedge clk_i)
data_valid_r <= #TCQ data_valid_i;
always @ (posedge clk_i)
begin
if (data_valid_i && user_bl_cnt_is_1) // current count is 1 and data_is_valie, then next cycle is not 1
user_bl_cnt_not_1 <= #TCQ 1'b1;
else
user_bl_cnt_not_1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1) begin
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
// MCB FIFO size is 64.
// buf_available is calculated by:
// FIFO DEPTH - ( Write Poitner - Read Pointer)
buf_avail_r <= #TCQ 64 - (rd_data_counts_asked - rd_data_received_counts);
always @(gen_rdy_i, empty,empty_r,rd_mdata_fifo_empty,rd_first_data ,data_valid_i,data_valid_r,user_bl_cnt_not_1)
begin
if (FAMILY == "SPARTAN6")
rd_en = gen_rdy_i & !empty;
else
if ( MEM_BURST_LEN == 4)
rd_en = (~empty & empty_r & ~rd_first_data) | (~rd_mdata_fifo_empty & ~empty ) | (user_bl_cnt_not_1 & data_valid_i);
else
rd_en = (data_valid_i & ~data_valid_r) | (user_bl_cnt_not_1 & data_valid_i);
end
always @ (posedge clk_i)
empty_r <= #TCQ empty;
always @ (posedge clk_i)
begin
if (rst_i)
rd_first_data <= #TCQ 1'b0;
else if (~empty && empty_r)
rd_first_data <= #TCQ 1'b1;
end
assign gen_valid_o = !empty;
afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Dispatcher State Machine
// File : der_smdisp.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_smdisp
(
input de_clk,
input de_rstn,
input en_3d,
input cmdrdy,
input sup_done,
input abort_cmd,
input dex_busy,
input [3:0] opc_1,
input [3:0] opc_15,
input [3:0] opc_2,
input pc_last, // Last push from the pixel cache.
input cmd_done_3d,
output reg go_sup,
output reg load_15, // Transfer parameters from L1 to L1.5
output reg load_actvn, // Transfer parameters from L1.5 to L2 or L1 to L2.
output reg load_actv_3d, // Transfer parameters from L1.5 to L2, in 3D engine.
output reg goline,
output reg goblt,
output reg pal_load,
output reg tc_inv_cmd,
output reg cmdack,
output reg cmdcpyclr,
output reg busy_3d,
output reg abort_cmd_flag
);
//////////////////////////////////////////////////////////////////
// DISPATCHER STATE MACHINE
// DEFINE PARAMETERS
//
reg abort_cmd_ack;
reg sup_done_flag;
reg sup_done_ack;
reg goline_ii;
reg goblt_ii;
reg goline_i;
reg goblt_i;
reg dex_3d_busy;
reg sup_busy;
`ifdef RTL_ENUM
enum {
IDLE =3'b000,
DECODE =3'b001,
DECODE2 =3'b010,
WAIT_SUP =3'b011,
DECODE3 =3'b100,
WAIT_3D =3'b101,
BUSY =3'b110,
NOOP_ST =3'b111
} d_cs;
`else
parameter
IDLE =3'b000,
DECODE =3'b001,
DECODE2 =3'b010,
WAIT_SUP =3'b011,
DECODE3 =3'b100,
WAIT_3D =3'b101,
BUSY =3'b110,
NOOP_ST =3'b111;
reg [2:0] d_cs;
`endif
parameter
NOOP = 4'h0,
BLT = 4'h1,
LINE = 4'h2,
ELINE = 4'h3,
P_LINE = 4'h5,
RXFER = 4'h6,
WXFER = 4'h7,
LINE_3D = 4'h8,
TRIAN_3D = 4'h9,
LD_TEX = 4'hA,
LD_TPAL = 4'hB,
busy_0 = 3'b001,
busy_15 = 3'b010,
busy_2 = 3'b100;
// Delay goblt and goline for data delay.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
goblt_ii <= 1'b0;
goline_ii <= 1'b0;
goblt <= 1'b0;
goline <= 1'b0;
end
else begin
goblt <= goblt_ii;
goblt_ii <= goblt_i;
goline <= goline_ii;
goline_ii <= goline_i;
end
end
// Capture abort and sup_done.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
abort_cmd_flag <= 1'b0;
sup_done_flag <= 1'b0;
dex_3d_busy <= 1'b0;
busy_3d <= 1'b0;
end
else begin
if(abort_cmd) abort_cmd_flag <= 1'b1;
else if(abort_cmd_ack) abort_cmd_flag <= 1'b0;
if(sup_done) sup_done_flag <= 1'b1;
else if(sup_done_ack) sup_done_flag <= 1'b0;
if(load_actv_3d) dex_3d_busy <= 1'b1;
// else if(cmd_done_3d) dex_3d_busy <= 1'b0;
else if(pc_last) dex_3d_busy <= 1'b0;
if(d_cs == IDLE) busy_3d <= 1'b0;
else if(load_actv_3d) busy_3d <= 1'b1;
end
end
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
go_sup <= 1'b0;
sup_busy <= 1'b0;
load_15 <= 1'b0;
cmdack <= 1'b0;
load_actvn <= 1'b1;
load_actv_3d <= 1'b0;
cmdcpyclr <= 1'b0;
goline_i <= 1'b0;
goblt_i <= 1'b0;
pal_load <= 1'b0;
tc_inv_cmd <= 1'b0;
abort_cmd_ack <= 1'b0;
sup_done_ack <= 1'b0;
d_cs <= IDLE;
end
else begin
go_sup <= 1'b0;
load_15 <= 1'b0;
cmdack <= 1'b0;
load_actvn <= 1'b1;
load_actv_3d <= 1'b0;
cmdcpyclr <= 1'b0;
goline_i <= 1'b0;
goblt_i <= 1'b0;
pal_load <= 1'b0;
tc_inv_cmd <= 1'b0;
abort_cmd_ack <= 1'b0;
sup_done_ack <= 1'b0;
case(d_cs)
// No commands in pipe.
// Wait for command ready.
IDLE: if(!cmdrdy)d_cs <= IDLE;
// NOOP, or obsolete RXFER, WXFER.
else if((opc_1==NOOP) || (opc_1==RXFER) || (opc_1==WXFER)) begin
cmdack <= 1'b1; // Free Level 1.
d_cs <= NOOP_ST; // Kill one cycle.
end
// 3D Command, load L15, and start setup engine.
else if(((opc_1==TRIAN_3D) || (opc_1==LINE_3D)) & en_3d & !sup_busy) begin
go_sup <= 1'b1; // Start setup.
load_15 <= 1'b1; // Load Level 15.
cmdack <= 1'b1; // Free Level 1.
sup_busy <= 1'b1;
d_cs <= WAIT_SUP; // Go wait for setup.
end
// 2D Command.
else begin
if(opc_1 == BLT) begin goblt_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == LINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == ELINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if(opc_1 == P_LINE) begin goline_i <= 1'b1; cmdack <= 1'b1; end
if((opc_1 == LD_TEX) & en_3d) cmdack <= 1'b1;
if((opc_1 == LD_TPAL) & en_3d) cmdack <= 1'b1;
if(en_3d) begin // if 3D Core, L15 is included.
load_15 <= 1'b1;
d_cs <= DECODE;
end else begin // else just L2 is included.
load_actvn <= 1'b1;
d_cs <= DECODE2;
end
end
DECODE: begin // Not a 3D command transfer 1.5 to 2.0
d_cs <= DECODE2;
load_actvn <= 1'b0;
end
DECODE2: d_cs <= BUSY;
WAIT_SUP: begin // Wait for setup, no 3D in progress.
if(abort_cmd_flag && !dex_3d_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
abort_cmd_ack <= 1'b1;
sup_busy <= 1'b0;
end
// SUP done no 3D in progress.
else if(sup_done_flag && !dex_3d_busy) begin
d_cs <= DECODE3;
load_actvn <= 1'b0;
load_actv_3d <= 1'b1;
sup_done_ack <= 1'b1;
sup_busy <= 1'b0;
end
else d_cs <= WAIT_SUP;
end
DECODE3: d_cs <= WAIT_3D;
WAIT_3D: begin // 3D in progress, another setup can be started.
if(!dex_3d_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
end
else if(!cmdrdy || sup_busy)d_cs <= WAIT_3D;
// if another 3D command start setup.
else if((opc_1==TRIAN_3D) || (opc_1==LINE_3D) ) begin
go_sup <= 1'b1; // Start setup.
load_15 <= 1'b1; // Load Level 15.
cmdack <= 1'b1; // Free Level 1.
sup_busy <= 1'b1;
d_cs <= WAIT_SUP; // Go wait for setup.
end
else d_cs <= WAIT_3D;
end
BUSY: begin
if(opc_2 == LD_TEX && !dex_3d_busy) begin // texture load command done
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
tc_inv_cmd <= 1'b1;
end
else if(opc_2==LD_TPAL && !dex_3d_busy) begin // palette load command done.
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
pal_load <= 1'b1;
end
else if(opc_2==LD_TEX && dex_3d_busy)d_cs <= BUSY;
else if(opc_2==LD_TPAL && dex_3d_busy)d_cs <= BUSY;
else if((opc_2== NOOP) || !dex_busy) begin
d_cs <= IDLE;
cmdcpyclr <= 1'b1;
end
else d_cs <= BUSY;
end
NOOP_ST: d_cs <= IDLE;
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_TB_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_TB_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkinvkapwr.v"
module top();
// Inputs are registered
reg A;
reg KAPWR;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
KAPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 KAPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 KAPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 KAPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 KAPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 KAPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_clkinvkapwr dut (.A(A), .KAPWR(KAPWR), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Tue Apr 18 23:18:55 2017
// Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// X:/final_project_sim/lzw/lzw.srcs/sources_1/ip/bram_1024_0/bram_1024_0_sim_netlist.v
// Design : bram_1024_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bram_1024_0,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bram_1024_0
(clka,
ena,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [9:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [19:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [19:0]douta;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [19:0]NLW_U0_doutb_UNCONNECTED;
wire [9:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [9:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [19:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "10" *)
(* C_ADDRB_WIDTH = "10" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bram_1024_0.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_0.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *)
(* C_READ_DEPTH_B = "1024" *)
(* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *)
(* C_WRITE_DEPTH_B = "1024" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "20" *)
(* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
bram_1024_0_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[19:0]),
.eccpipece(1'b0),
.ena(ena),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[9:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[9:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[19:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bram_1024_0_blk_mem_gen_generic_cstr
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bram_1024_0_blk_mem_gen_prim_width
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bram_1024_0_blk_mem_gen_prim_wrapper_init
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000001D0000001900000015000000110000000D000000090000000500000001),
.INIT_01(256'h0000011D0000011900000115000001110000010D000001090000010500000101),
.INIT_02(256'h0000021D0000021900000215000002110000020D000002090000020500000201),
.INIT_03(256'h0000031D0000031900000315000003110000030D000003090000030500000301),
.INIT_04(256'h0000041D0000041900000415000004110000040D000004090000040500000401),
.INIT_05(256'h0000051D0000051900000515000005110000050D000005090000050500000501),
.INIT_06(256'h0000061D0000061900000615000006110000060D000006090000060500000601),
.INIT_07(256'h0000071D0000071900000715000007110000070D000007090000070500000701),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,dina[19:15],1'b0,1'b0,1'b0,dina[14:10],1'b0,1'b0,1'b0,dina[9:5],1'b0,1'b0,1'b0,dina[4:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_21 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_22 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_23 ,douta[19:15],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_29 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_30 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_31 ,douta[14:10],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_39 ,douta[9:5],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_47 ,douta[4:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_85 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_86 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(ena),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(ena),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bram_1024_0_blk_mem_gen_top
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "10" *) (* C_ADDRB_WIDTH = "10" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.74095 mW" *)
(* C_FAMILY = "zynq" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bram_1024_0.mem" *)
(* C_INIT_FILE_NAME = "bram_1024_0.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1024" *) (* C_READ_DEPTH_B = "1024" *) (* C_READ_WIDTH_A = "20" *)
(* C_READ_WIDTH_B = "20" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1024" *) (* C_WRITE_DEPTH_B = "1024" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "20" *) (* C_WRITE_WIDTH_B = "20" *)
(* C_XDEVICEFAMILY = "zynq" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bram_1024_0_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [9:0]addra;
input [19:0]dina;
output [19:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [9:0]addrb;
input [19:0]dinb;
output [19:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [9:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [19:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [19:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [9:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[19] = \<const0> ;
assign doutb[18] = \<const0> ;
assign doutb[17] = \<const0> ;
assign doutb[16] = \<const0> ;
assign doutb[15] = \<const0> ;
assign doutb[14] = \<const0> ;
assign doutb[13] = \<const0> ;
assign doutb[12] = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bram_1024_0_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bram_1024_0_blk_mem_gen_v8_3_5_synth
(douta,
clka,
ena,
addra,
dina,
wea);
output [19:0]douta;
input clka;
input ena;
input [9:0]addra;
input [19:0]dina;
input [0:0]wea;
wire [9:0]addra;
wire clka;
wire [19:0]dina;
wire [19:0]douta;
wire ena;
wire [0:0]wea;
bram_1024_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.ena(ena),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*!
memfifo -- implementation of EZ-USB slave FIFO's (input and output) a FIFO using the DDR3 SDRAM for ZTEX USB-FPGA Modules 2.13
Copyright (C) 2009-2014 ZTEX GmbH.
http://www.ztex.de
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License version 3 as
published by the Free Software Foundation.
This program is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, see http://www.gnu.org/licenses/.
!*/
/*
Implements the EZ-USB Slave FIFO interface for both
directions. It also includes an scheduler (required if both
directions are used at the same time) and short packets (PKTEND).
*/
module ezusb_io #(
parameter OUTEP = 2, // EP for FPGA -> EZ-USB transfers
parameter INEP = 6 // EP for EZ-USB -> FPGA transfers
) (
output ifclk,
input reset, // asynchronous reset input
output reset_out, // synchronous reset output
// pins
input ifclk_in,
inout [15:0] fd,
output reg SLWR, PKTEND,
output SLRD, SLOE,
output [1:0] FIFOADDR,
input EMPTY_FLAG, FULL_FLAG,
// signals for FPGA -> EZ-USB transfer
input [15:0] DI, // data written to EZ-USB
input DI_valid, // 1 indicates data valid; DI and DI_valid must be hold if DI_ready is 0
output DI_ready, // 1 if new data are accepted
input DI_enable, // setting to 0 disables FPGA -> EZ-USB transfers
input [15:0] pktend_timeout, // timeout in multiples of 65536 clocks before a short packet committed
// setting to 0 disables this feature
// signals for EZ-USB -> FPGA transfer
output reg [15:0] DO, // data read from EZ-USB
output reg DO_valid, // 1 indicated valid data
input DO_ready, // setting to 1 enables writing new data to DO in next clock; DO and DO_valid are hold if DO_ready is 0
// set to 0 to disable data reads
// debug output
output [3:0] status
);
wire ifclk_inbuf, ifclk_fbin, ifclk_fbout, ifclk_out, locked;
IBUFG ifclkin_buf (
.I(ifclk_in),
.O(ifclk_inbuf)
);
BUFG ifclk_fb_buf (
.I(ifclk_fbout),
.O(ifclk_fbin)
);
BUFG ifclk_out_buf (
.I(ifclk_out),
.O(ifclk)
);
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(20.0),
.CLKFBOUT_PHASE(0.0),
.CLKIN1_PERIOD(0.0),
.CLKOUT0_DIVIDE_F(20.0),
.CLKOUT1_DIVIDE(1),
.CLKOUT2_DIVIDE(1),
.CLKOUT3_DIVIDE(1),
.CLKOUT4_DIVIDE(1),
.CLKOUT5_DIVIDE(1),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_PHASE(0.0),
.CLKOUT4_CASCADE("FALSE"),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.0),
.STARTUP_WAIT("FALSE")
) isclk_mmcm_inst (
.CLKOUT0(ifclk_out),
.CLKFBOUT(ifclk_fbout),
.CLKIN1(ifclk_inbuf),
.PWRDWN(1'b0),
.RST(reset),
.CLKFBIN(ifclk_fbin),
.LOCKED(locked)
);
reg reset_ifclk = 1;
reg if_out, if_in;
reg [4:0] if_out_buf;
reg [15:0] fd_buf;
reg resend;
reg SLRD_buf, pktend_req, pktend_en;
reg [31:0] pktend_cnt;
// FPGA <-> EZ-USB signals
assign SLOE = if_out;
// assign FIFOADDR[0] = 1'b0;
// assign FIFOADDR[1] = !if_out;
assign FIFOADDR = if_out ? OUTEP/2-1 : INEP/2-1;
assign fd = if_out ? fd_buf : {16{1'bz}};
assign SLRD = SLRD_buf || !DO_ready;
assign status = { !SLRD_buf, !SLWR, resend, if_out };
assign DI_ready = !reset_ifclk && FULL_FLAG && if_out & if_out_buf[4] && !resend;
assign reset_out = reset || reset_ifclk;
always @ (posedge ifclk)
begin
reset_ifclk <= reset || !locked;
// FPGA -> EZ-USB
if ( reset_ifclk )
begin
SLWR <= 1'b1;
if_out <= DI_enable; // direction of EZ-USB interface: 1 means FPGA writes / EZ_USB reads
resend <= 1'b0;
SLRD_buf <= 1'b1;
if_out_buf = {5{!DI_enable}};
end else if ( FULL_FLAG && if_out && if_out_buf[4] && ( resend || DI_valid) ) // FPGA -> EZ-USB
begin
SLWR <= 1'b0;
SLRD_buf <= 1'b1;
resend <= 1'b0;
if ( !resend ) fd_buf <= DI;
end else if ( EMPTY_FLAG && !if_out && !if_out_buf[4] && DO_ready ) // EZ-USB -> FPGA
begin
SLWR <= 1'b1;
DO <= fd;
SLRD_buf <= 1'b0;
end else if (if_out == if_out_buf[4])
begin
if ( !SLWR && !FULL_FLAG ) resend <= 1'b1; // FLAGS are received two clocks after data. If FULL_FLAG was asserted last data was ignored and has to be re-sent.
SLRD_buf <= 1'b1;
SLWR <= 1'b1;
if_out <= DI_enable && (!DO_ready || !EMPTY_FLAG);
end
if_out_buf <= { if_out_buf[3:0], if_out };
if ( DO_ready ) DO_valid <= !if_out && !if_out_buf[4] && EMPTY_FLAG && !SLRD_buf; // assertion of SLRD_buf takes two clocks to take effect
// PKTEND processing
if ( reset_ifclk || DI_valid )
begin
pktend_req <= 1'b0;
pktend_en <= !reset_ifclk;
pktend_cnt <= 32'd0;
PKTEND <= 1'b1;
end else
begin
pktend_req <= pktend_req || ( pktend_en && (pktend_timeout != 16'd0) && (pktend_timeout == pktend_cnt[31:16]) );
pktend_cnt <= pktend_cnt + 1;
if ( pktend_req && if_out && if_out_buf[4] )
begin
PKTEND <= 1'b0;
pktend_req <= 1'b0;
pktend_en <= 1'b0;
end else
begin
PKTEND <= 1'b1;
pktend_req <= pktend_req || ( pktend_en && (pktend_timeout != 16'd0) && (pktend_timeout == pktend_cnt[31:16]) );
end
end
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 13.1
// \ \ Application : xaw2verilog
// / / Filename : main_pll.v
// /___/ /\ Timestamp : 06/03/2011 01:58:13
// \ \ / \
// \___\/\___\
//
//Command: xaw2verilog -st /home/teknohog/dcm2/ipcore_dir/./main_pll.xaw /home/teknohog/dcm2/ipcore_dir/./main_pll
//Design Name: main_pll
//Device: xc3s500e-4fg320
//
// Module main_pll
// Generated by Xilinx Architecture Wizard
// Written for synthesis tool: XST
`timescale 1ns / 1ps
module dyn_pll # (parameter SPEED_MHZ = 25 )
(CLKIN_IN,
CLKFX1_OUT,
CLKFX2_OUT,
CLKDV_OUT,
DCM_SP_LOCKED_OUT,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_progdone,
dcm_locked,
dcm_status);
input CLKIN_IN;
wire CLKIN_IBUFG_OUT;
wire CLK0_OUT;
output CLKFX1_OUT;
output CLKFX2_OUT;
output CLKDV_OUT;
output DCM_SP_LOCKED_OUT;
input dcm_progclk;
input dcm_progdata;
input dcm_progen;
input dcm_reset;
output dcm_progdone;
output dcm_locked;
output [2:1] dcm_status;
wire CLKFB_IN;
wire CLKIN_IBUFG;
wire CLK0_BUF;
wire CLKFX1_BUF;
wire CLKFX2_BUF;
wire CLKDV_BUF;
wire GND_BIT;
wire dcm_progclk_buf;
assign GND_BIT = 0;
assign CLKIN_IBUFG_OUT = CLKIN_IBUFG;
assign CLK0_OUT = CLKFB_IN;
IBUFG CLKIN_IBUFG_INST (.I(CLKIN_IN),
.O(CLKIN_IBUFG));
BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
.O(CLKFB_IN));
BUFG CLKFX1_BUFG_INST (.I(CLKFX1_BUF),
.O(CLKFX1_OUT));
BUFG CLKFX2_BUFG_INST (.I(CLKFX2_BUF),
.O(CLKFX2_OUT));
BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
.O(CLKDV_OUT));
BUFG DCMPROGCLK_BUFG_INST (.I(dcm_progclk),
.O(dcm_progclk_buf));
// 100 MHZ osc gives fixed 50MHz CLKFX1, 12.5MHZ CLKDV
DCM_SP #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(8.0), .CLKFX_DIVIDE(8),
.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"),
.CLKIN_PERIOD(10.000), .CLKOUT_PHASE_SHIFT("NONE"),
.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("LOW"),
.DLL_FREQUENCY_MODE("LOW"), .DUTY_CYCLE_CORRECTION("TRUE"),
.FACTORY_JF(16'hC080), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE") )
DCM_SP_INST (.CLKFB(CLKFB_IN),
.CLKIN(CLKIN_IBUFG),
.DSSEN(GND_BIT),
.PSCLK(GND_BIT),
.PSEN(GND_BIT),
.PSINCDEC(GND_BIT),
.RST(GND_BIT),
.CLKDV(CLKDV_BUF),
.CLKFX(CLKFX1_BUF),
.CLKFX180(),
.CLK0(CLK0_BUF),
.CLK2X(),
.CLK2X180(),
.CLK90(),
.CLK180(),
.CLK270(),
.LOCKED(DCM_SP_LOCKED_OUT),
.PSDONE(),
.STATUS());
DCM_CLKGEN #(
.CLKFX_DIVIDE(100), // 100Mhz osc so gives steps of 1MHz
.CLKFX_MULTIPLY(SPEED_MHZ),
.CLKFXDV_DIVIDE(2), // Unused
.CLKIN_PERIOD(10.0),
.CLKFX_MD_MAX(0.000),
.SPREAD_SPECTRUM("NONE"),
.STARTUP_WAIT("FALSE")
)
DCM_CLKGEN_INST (
.CLKIN(CLKIN_IBUFG),
.CLKFX(CLKFX2_BUF),
.FREEZEDCM(1'b0),
.PROGCLK(dcm_progclk_buf),
.PROGDATA(dcm_progdata),
.PROGEN(dcm_progen),
.PROGDONE(dcm_progdone),
.LOCKED(dcm_locked),
.STATUS(dcm_status),
.RST(dcm_reset)
);
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 200MHz
* Reset: Push button, active high
*/
input wire sys_clk_p,
input wire sys_clk_n,
input wire reset,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire ledu,
output wire ledl,
output wire ledd,
output wire ledr,
output wire ledc,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T SGMII
*/
input wire phy_sgmii_rx_p,
input wire phy_sgmii_rx_n,
output wire phy_sgmii_tx_p,
output wire phy_sgmii_tx_n,
input wire phy_sgmii_clk_p,
input wire phy_sgmii_clk_n,
output wire phy_reset_n,
/*
* Silicon Labs CP2103 USB UART
*/
output wire uart_rxd,
input wire uart_txd,
input wire uart_rts,
output wire uart_cts
);
// Clock and reset
wire sys_clk_ibufg;
// Internal 125 MHz clock
wire clk_125mhz_mmcm_out;
wire clk_125mhz_int;
wire rst_125mhz_int;
wire mmcm_rst = reset;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFGDS
clk_ibufgds_inst(
.I(sys_clk_p),
.IB(sys_clk_n),
.O(sys_clk_ibufg)
);
// MMCM instance
// 200 MHz in, 125 MHz out
// PFD range: 10 MHz to 450 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCM_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(5),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.100),
.CLKIN1_PERIOD(5.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(sys_clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_125mhz_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_125mhz_bufg_inst (
.I(clk_125mhz_mmcm_out),
.O(clk_125mhz_int)
);
sync_reset #(
.N(4)
)
sync_reset_125mhz_inst (
.clk(clk_125mhz_int),
.rst(~mmcm_locked),
.out(rst_125mhz_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
wire ledu_int;
wire ledl_int;
wire ledd_int;
wire ledr_int;
wire ledc_int;
wire [7:0] led_int;
wire uart_rxd_int;
wire uart_txd_int;
wire uart_rts_int;
wire uart_cts_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_125mhz_int),
.rst(rst_125mhz_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(2),
.N(2)
)
sync_signal_inst (
.clk(clk_125mhz_int),
.in({uart_txd,
uart_rts}),
.out({uart_txd_int,
uart_rts_int})
);
assign ledu = ledu_int;
assign ledl = ledl_int;
assign ledd = ledd_int;
assign ledr = ledr_int;
assign ledc = ledc_int;
//assign led = led_int;
assign uart_rxd = uart_rxd_int;
assign uart_cts = uart_cts_int;
// SGMII interface to PHY
wire phy_gmii_clk_int;
wire phy_gmii_rst_int;
wire phy_gmii_clk_en_int;
wire [7:0] phy_gmii_txd_int;
wire phy_gmii_tx_en_int;
wire phy_gmii_tx_er_int;
wire [7:0] phy_gmii_rxd_int;
wire phy_gmii_rx_dv_int;
wire phy_gmii_rx_er_int;
wire phy_sgmii_mgtrefclk;
wire phy_sgmii_txoutclk;
wire phy_sgmii_userclk2;
IBUFDS_GTXE1
phy_sgmii_ibufds_mgtrefclk (
.CEB (1'b0),
.I (phy_sgmii_clk_p),
.IB (phy_sgmii_clk_n),
.O (phy_sgmii_mgtrefclk),
.ODIV2 ()
);
BUFG
phy_sgmii_bufg_userclk2 (
.I (phy_sgmii_txoutclk),
.O (phy_sgmii_userclk2)
);
assign phy_gmii_clk_int = phy_sgmii_userclk2;
sync_reset #(
.N(4)
)
sync_reset_pcspma_inst (
.clk(phy_gmii_clk_int),
.rst(rst_125mhz_int),
.out(phy_gmii_rst_int)
);
wire [15:0] pcspma_status_vector;
wire pcspma_status_link_status = pcspma_status_vector[0];
wire pcspma_status_link_synchronization = pcspma_status_vector[1];
wire pcspma_status_rudi_c = pcspma_status_vector[2];
wire pcspma_status_rudi_i = pcspma_status_vector[3];
wire pcspma_status_rudi_invalid = pcspma_status_vector[4];
wire pcspma_status_rxdisperr = pcspma_status_vector[5];
wire pcspma_status_rxnotintable = pcspma_status_vector[6];
wire pcspma_status_phy_link_status = pcspma_status_vector[7];
wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8];
wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10];
wire pcspma_status_duplex = pcspma_status_vector[12];
wire pcspma_status_remote_fault = pcspma_status_vector[13];
wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14];
wire [4:0] pcspma_config_vector;
assign pcspma_config_vector[4] = 1'b1; // autonegotiation enable
assign pcspma_config_vector[3] = 1'b0; // isolate
assign pcspma_config_vector[2] = 1'b0; // power down
assign pcspma_config_vector[1] = 1'b0; // loopback enable
assign pcspma_config_vector[0] = 1'b0; // unidirectional enable
wire [15:0] pcspma_an_config_vector;
assign pcspma_an_config_vector[15] = 1'b1; // SGMII link status
assign pcspma_an_config_vector[14] = 1'b1; // SGMII Acknowledge
assign pcspma_an_config_vector[13:12] = 2'b01; // full duplex
assign pcspma_an_config_vector[11:10] = 2'b10; // SGMII speed
assign pcspma_an_config_vector[9] = 1'b0; // reserved
assign pcspma_an_config_vector[8:7] = 2'b00; // pause frames - SGMII reserved
assign pcspma_an_config_vector[6] = 1'b0; // reserved
assign pcspma_an_config_vector[5] = 1'b0; // full duplex - SGMII reserved
assign pcspma_an_config_vector[4:1] = 4'b0000; // reserved
assign pcspma_an_config_vector[0] = 1'b1; // SGMII
gig_eth_pcs_pma_v11_5_block
eth_pcspma (
// Transceiver Interface
.mgtrefclk (phy_sgmii_mgtrefclk),
.gtx_reset_clk (clk_125mhz_int),
.txp (phy_sgmii_tx_p),
.txn (phy_sgmii_tx_n),
.rxp (phy_sgmii_rx_p),
.rxn (phy_sgmii_rx_n),
.txoutclk (phy_sgmii_txoutclk),
.userclk2 (phy_sgmii_userclk2),
.pma_reset (rst_125mhz_int),
// GMII Interface
.sgmii_clk_r (),
.sgmii_clk_f (),
.sgmii_clk_en (phy_gmii_clk_en_int),
.gmii_txd (phy_gmii_txd_int),
.gmii_tx_en (phy_gmii_tx_en_int),
.gmii_tx_er (phy_gmii_tx_er_int),
.gmii_rxd (phy_gmii_rxd_int),
.gmii_rx_dv (phy_gmii_rx_dv_int),
.gmii_rx_er (phy_gmii_rx_er_int),
.gmii_isolate (),
// Management: Alternative to MDIO Interface
.configuration_vector (pcspma_config_vector),
.an_interrupt (),
.an_adv_config_vector (pcspma_an_config_vector),
.an_restart_config (1'b0),
.link_timer_value (9'd50),
// Speed Control
.speed_is_10_100 (pcspma_status_speed != 2'b10),
.speed_is_100 (pcspma_status_speed == 2'b01),
// General IO's
.status_vector (pcspma_status_vector),
.reset (rst_125mhz_int),
.signal_detect (1'b1)
);
// SGMII interface debug:
// SW1:1 (sw[0]) off for payload byte, on for status vector
// SW1:2 (sw[1]) off for LSB of status vector, on for MSB
assign led = sw[7] ? (sw[6] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int;
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk_125mhz(clk_125mhz_int),
.rst_125mhz(rst_125mhz_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.ledu(ledu_int),
.ledl(ledl_int),
.ledd(ledd_int),
.ledr(ledr_int),
.ledc(ledc_int),
.led(led_int),
/*
* Ethernet: 1000BASE-T SGMII
*/
.phy_gmii_clk(phy_gmii_clk_int),
.phy_gmii_rst(phy_gmii_rst_int),
.phy_gmii_clk_en(phy_gmii_clk_en_int),
.phy_gmii_rxd(phy_gmii_rxd_int),
.phy_gmii_rx_dv(phy_gmii_rx_dv_int),
.phy_gmii_rx_er(phy_gmii_rx_er_int),
.phy_gmii_txd(phy_gmii_txd_int),
.phy_gmii_tx_en(phy_gmii_tx_en_int),
.phy_gmii_tx_er(phy_gmii_tx_er_int),
.phy_reset_n(phy_reset_n),
/*
* UART: 115200 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd_int),
.uart_rts(uart_rts_int),
.uart_cts(uart_cts_int)
);
endmodule
`resetall
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/********
* This module captures the relative frequency with which each bit in 'value'
* toggles. This can be useful for detecting address patterns for example.
*
* Eg. (in hex)
* Linear: 1ff ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Linear predicated: 1ff ff 80 40 00 00 00 20 10 8 4 2 1 0 0 0 ...
* Strided: 00 00 ff 80 40 20 10 08 04 02 1 0 0 0 ...
* Random: ff ff ff ff ff ff ff ff ff ...
*
* The counters that track the toggle rates automatically get divided by 2 once
* any of their values comes close to overflowing. Hence the toggle rates are
* relative, and comparable only within a single module instance.
*
* The last counter (count[WIDTH]) is a saturating counter storing the number of
* times a scaledown was performed. If you assume the relative rates don't
* change between scaledowns, this can be used to approximate absolute toggle
* rates (which can be compared against rates from another instance).
*****************/
module acl_toggle_detect
#(
parameter WIDTH=13, // Width of input signal in bits
parameter COUNTERWIDTH=10 // in bits, MUST be greater than 3
)
(
input logic clk,
input logic resetn,
input logic valid,
input logic [WIDTH-1:0] value,
output logic [COUNTERWIDTH-1:0] count[WIDTH+1]
);
/******************
* LOCAL PARAMETERS
*******************/
/******************
* SIGNALS
*******************/
logic [WIDTH-1:0] last_value;
logic [WIDTH-1:0] bits_toggled;
logic scaledown;
/******************
* ARCHITECTURE
*******************/
always@(posedge clk or negedge resetn)
if (!resetn)
last_value<={WIDTH{1'b0}};
else if (valid)
last_value<=value;
// Compute which bits toggled via XOR
always@(posedge clk or negedge resetn)
if (!resetn)
bits_toggled<={WIDTH{1'b0}};
else if (valid)
bits_toggled<=value^last_value;
else
bits_toggled<={WIDTH{1'b0}};
// Create one counter for each bit in value. Increment the respective
// counter if that bit toggled.
genvar i;
generate
for (i = 0; i < WIDTH; i = i + 1)
begin:counters
always@(posedge clk or negedge resetn)
if (!resetn)
count[i] <= {COUNTERWIDTH{1'b0}};
else if (bits_toggled[i] && scaledown)
count[i] <= (count[i] + 2'b1) >> 1;
else if (bits_toggled[i])
count[i] <= count[i] + 2'b1;
else if (scaledown)
count[i] <= count[i] >> 1;
end
endgenerate
// Count total number of times scaled down - saturating counter
// This can be used to approximate absolute toggle rates
always@(posedge clk or negedge resetn)
if (!resetn)
count[WIDTH] <= 1'b0;
else if (scaledown && count[WIDTH]!={COUNTERWIDTH{1'b1}})
count[WIDTH] <= count[WIDTH] + 2'b1;
// If any counter value's top 3 bits are 1s, scale down all counter values
integer j;
always@(posedge clk or negedge resetn)
if (!resetn)
scaledown <= 1'b0;
else if (scaledown)
scaledown <= 1'b0;
else
for (j = 0; j < WIDTH; j = j + 1)
if (&count[j][COUNTERWIDTH-1:COUNTERWIDTH-3])
scaledown <= 1'b1;
endmodule
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_tx # (
parameter C_SIM_CPLL_CAL_BYPASS = 1'b1,
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter C_FREERUN_FREQUENCY = 100,
parameter REVISION = 2,
parameter C_PCIE_ENABLE = "FALSE",
parameter C_PCIE_CORECLK_FREQ = 250
)(
// control signals
input wire [17:0] TXOUTCLK_PERIOD_IN,
input wire [15:0] WAIT_DEASSERT_CPLLPD_IN,
input wire [17:0] CNT_TOL_IN,
input wire [15:0] FREQ_COUNT_WINDOW_IN,
// User Interface
input wire RESET_IN,
input wire CLK_IN,
input wire [1:0] USER_TXPLLCLKSEL,
input wire USER_TXPROGDIVRESET_IN,
output reg USER_TXPRGDIVRESETDONE_OUT,
input wire [2:0] USER_TXOUTCLKSEL_IN,
input wire USER_TXOUTCLK_BUFG_CE_IN,
input wire USER_TXOUTCLK_BUFG_CLR_IN,
output reg USER_CPLLLOCK_OUT,
// Debug Interface
output wire CPLL_CAL_FAIL,
output wire CPLL_CAL_DONE,
output wire [15:0] DEBUG_OUT,
output wire [17:0] CAL_FREQ_CNT,
input [3:0] REPEAT_RESET_LIMIT,
// GT Interface
input wire GTYE4_TXOUTCLK_IN,
input wire GTYE4_CPLLLOCK_IN,
output wire GTYE4_CPLLRESET_OUT,
output wire GTYE4_CPLLPD_OUT,
output reg GTYE4_TXPROGDIVRESET_OUT,
output reg [2:0] GTYE4_TXOUTCLKSEL_OUT,
input wire GTYE4_TXPRGDIVRESETDONE_IN,
output wire [9:0] GTYE4_CHANNEL_DRPADDR_OUT,
output wire [15:0] GTYE4_CHANNEL_DRPDI_OUT,
output wire GTYE4_CHANNEL_DRPEN_OUT,
output wire GTYE4_CHANNEL_DRPWE_OUT,
input wire GTYE4_CHANNEL_DRPRDY_IN,
input wire [15:0] GTYE4_CHANNEL_DRPDO_IN,
output wire DONE
);
//DRP FSM
localparam DRP_WAIT = 0;
localparam DRP_READ = 1;
localparam DRP_READ_ACK = 2;
localparam DRP_MODIFY = 3;
localparam DRP_WRITE = 4;
localparam DRP_WRITE_ACK = 5;
localparam DRP_DONE = 6;
localparam RESET = 0;
localparam READ_X0E1 = 1;
localparam CHECK_X0E1_STATUS = 2;
localparam READ_PROGCLK_SEL = 3;
localparam SAVE_PROGCLK_SEL = 4;
localparam READ_X079 = 5;
localparam CHECK_X079_STATUS = 6;
localparam READ_PROGDIV_CFG = 7;
localparam SAVE_PROGDIV_CFG = 8;
localparam READ_X0E1_BEFORE_PROGCLK_SEL_MOD = 9;
localparam MODIFY_PROGCLK_SEL = 10;
localparam MODIFY_PROGDIV = 11;
localparam MODIFY_TXOUTCLK_SEL = 12;
localparam ASSERT_CPLLPD = 13;
localparam DEASSERT_CPLLPD = 14;
localparam ASSERT_CPLLRESET = 15;
localparam DEASSERT_CPLLRESET = 16;
localparam WAIT_GTCPLLLOCK = 17;
localparam ASSERT_PROGDIVRESET = 18;
localparam WAIT_PRGDIVRESETDONE = 19;
localparam CHECK_FREQ = 20;
localparam RESTORE_READ_X0E1 = 21;
localparam RESTORE_READ_X079 = 22;
localparam RESTORE_PROGDIV = 23;
localparam RESTORE_PROGCLK_SEL = 24;
localparam CLEAR_FLAG_x0E1 = 25;
localparam CLEAR_FLAG_x079 = 26;
localparam WAIT_GTCPLLLOCK2 = 27;
localparam ASSERT_PROGDIVRESET2 = 28;
localparam WAIT_PRGDIVRESETDONE2= 29;
localparam CAL_FAIL = 30;
localparam CAL_DONE = 31;
reg [31:0] cpll_cal_state = 31'd0;
wire [4:0] cpll_cal_state_bin;
reg [6:0] drp_state = 7'd1;
wire drp_done;
reg [9:0] daddr = 10'd0;
reg [15:0] di = 16'd0;
wire drdy;
wire [15:0] dout;
reg den = 1'b0;
reg dwe = 1'b0;
reg wr = 1'b0;
reg rd = 1'b0;
reg [15:0] di_msk;
reg [15:0] mask;
reg [24:0] wait_ctr;
reg [3:0] repeat_ctr;
reg [15:0] progclk_sel_store = 16'd0;
reg [15:0] progdiv_cfg_store = 16'd0;
reg fboost_store = 1'b0;
reg mask_user_in = 1'b0;
reg cpllreset_int = 1'b0;
reg cpllpd_int = 1'b0;
reg txprogdivreset_int = 1'b0;
reg [2:0] txoutclksel_int = 3'b000;
reg cal_fail_store = 1'b0;
reg [15:0] x0e1_store = 16'd0;
reg status_store = 1'b0;
wire den_i;
wire dwe_i;
//All these need to be based on CLK_IN frequency (free_run)
localparam [24:0] SYNTH_WAIT_ASSERT_CPLLRESET = (1000 * C_FREERUN_FREQUENCY); // 1 ms
localparam [24:0] SYNTH_WAIT_CPLLLOCK = (1000 * C_FREERUN_FREQUENCY); // 1 ms
localparam [24:0] SYNTH_WAIT_DEASSERT_CPLLRESET = (100 * C_FREERUN_FREQUENCY); // 100 us
localparam [24:0] SIM_WAIT_ASSERT_CPLLRESET = SYNTH_WAIT_ASSERT_CPLLRESET/10;
localparam [24:0] SIM_WAIT_CPLLLOCK = SYNTH_WAIT_CPLLLOCK/10;
localparam [24:0] SIM_WAIT_DEASSERT_CPLLRESET = SYNTH_WAIT_DEASSERT_CPLLRESET/10;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [4:0] WAIT_WIDTH_PROGDIVRESET = 5'd25; // >= 100 ns
localparam [24:0] WAIT_ASSERT_CPLLRESET =
//pragma translate_off
(SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_ASSERT_CPLLRESET :
//pragma translate_on
SYNTH_WAIT_ASSERT_CPLLRESET;
localparam [4:0] WAIT_ASSERT_CPLLPD = 5'd25; // >= 100 ns
localparam [24:0] WAIT_DEASSERT_CPLLRESET =
//pragma translate_off
(SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_DEASSERT_CPLLRESET :
//pragma translate_on
SYNTH_WAIT_DEASSERT_CPLLRESET;
localparam [24:0] WAIT_CPLLLOCK =
//pragma translate_off
(SIM_RESET_SPEEDUP_REG == "TRUE") ? SIM_WAIT_CPLLLOCK :
//pragma translate_on
SYNTH_WAIT_CPLLLOCK;
localparam [1:0] MOD_PROGCLK_SEL = 2'b10;
localparam [15:0] MOD_PROGDIV_CFG = 16'hE062; //divider 20
localparam [2:0] MOD_TXOUTCLK_SEL = 3'b101;
localparam [9:0] ADDR_TX_PROGCLK_SEL = 10'h00C;
localparam [9:0] ADDR_TX_PROGDIV_CFG = 10'h057; //GTY /GTH addresses are different (003E in GTH; 0057 in GTY)
localparam [9:0] ADDR_X0E1 = 10'h0E1;
localparam [9:0] ADDR_X079 = 10'h079;
// Drive TXOUTCLK with BUFG_GT-buffered source clock, divider = 1
wire txoutclkmon;
//assign txoutclkmon = GTYE4_TXOUTCLK_IN;
BUFG_GT bufg_gt_txoutclkmon_inst (
.CE (USER_TXOUTCLK_BUFG_CE_IN),
.CEMASK (1'b1),
.CLR (USER_TXOUTCLK_BUFG_CLR_IN),
.CLRMASK (1'b1),
.DIV (3'b000),
.I (GTYE4_TXOUTCLK_IN),
.O (txoutclkmon)
);
wire gtye4_cplllock_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_cplllock_inst (
.clk_in (CLK_IN),
.i_in (GTYE4_CPLLLOCK_IN),
.o_out (gtye4_cplllock_sync)
);
wire user_txprogdivreset_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txprogdivreset_inst (
.clk_in (CLK_IN),
.i_in (USER_TXPROGDIVRESET_IN),
.o_out (user_txprogdivreset_sync)
);
wire gtye4_txprgdivresetdone_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txprgdivresetdone_inst (
.clk_in (CLK_IN),
.i_in (GTYE4_TXPRGDIVRESETDONE_IN),
.o_out (gtye4_txprgdivresetdone_sync)
);
wire [2:0] user_txoutclksel_sync;
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txoutclksel_inst0 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[0]),
.o_out (user_txoutclksel_sync[0])
);
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txoutclksel_inst1 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[1]),
.o_out (user_txoutclksel_sync[1])
);
gtwizard_ultrascale_v1_7_1_bit_synchronizer bit_synchronizer_txoutclksel_inst2 (
.clk_in (CLK_IN),
.i_in (USER_TXOUTCLKSEL_IN[2]),
.o_out (user_txoutclksel_sync[2])
);
assign GTYE4_CPLLRESET_OUT = cpllreset_int;
assign GTYE4_CPLLPD_OUT = cpllpd_int;
always @(posedge CLK_IN) begin
if (mask_user_in | cpll_cal_state[CAL_FAIL] | cpll_cal_state[RESET] | RESET_IN)
USER_CPLLLOCK_OUT <= 1'b0;
else
USER_CPLLLOCK_OUT <= gtye4_cplllock_sync;
end
generate if (C_PCIE_ENABLE)
begin : pcie_txoutclksel
always @(*) begin
GTYE4_TXOUTCLKSEL_OUT <= mask_user_in ? txoutclksel_int : USER_TXOUTCLKSEL_IN;
GTYE4_TXPROGDIVRESET_OUT <= mask_user_in ? txprogdivreset_int : USER_TXPROGDIVRESET_IN;
end
end
else begin : non_pcie_txoutclksel
always @(posedge CLK_IN) begin
if (mask_user_in)
GTYE4_TXPROGDIVRESET_OUT <= txprogdivreset_int;
else
GTYE4_TXPROGDIVRESET_OUT <= user_txprogdivreset_sync;
end
always @(posedge CLK_IN) begin
if (mask_user_in)
GTYE4_TXOUTCLKSEL_OUT <= txoutclksel_int;
else
GTYE4_TXOUTCLKSEL_OUT <= user_txoutclksel_sync;
end
end
endgenerate
always @(posedge CLK_IN) begin
if (mask_user_in)
USER_TXPRGDIVRESETDONE_OUT <= 1'b0;
else
USER_TXPRGDIVRESETDONE_OUT <= gtye4_txprgdivresetdone_sync;
end
// frequency counter for txoutclk
wire [17:0] txoutclk_freq_cnt;
reg freq_counter_rst = 1'b1;
wire freq_cnt_done;
gtwizard_ultrascale_v1_7_1_gtye4_cpll_cal_freq_counter U_TXOUTCLK_FREQ_COUNTER
(
.freq_cnt_o(txoutclk_freq_cnt),
.done_o(freq_cnt_done),
.rst_i(freq_counter_rst),
.test_term_cnt_i(FREQ_COUNT_WINDOW_IN),
.ref_clk_i(CLK_IN),
.test_clk_i(txoutclkmon)
);
//Debug signals
assign DEBUG_OUT = {cpllreset_int,cpllpd_int,gtye4_cplllock_sync,1'b0,freq_cnt_done,freq_counter_rst,mask_user_in,cpll_cal_state_bin,repeat_ctr};
assign CPLL_CAL_FAIL = cpll_cal_state[CAL_FAIL];
assign CPLL_CAL_DONE = cpll_cal_state[CAL_DONE];
assign CAL_FREQ_CNT = txoutclk_freq_cnt;
assign DONE = cpll_cal_state[CAL_DONE] | cpll_cal_state[RESET];
//pragma translate_off
generate if (C_SIM_CPLL_CAL_BYPASS == 1'b1)
begin: gen_sim_cpll_cal_bypass_gtye4
//CPLL CAL FSM for simulation
always @(posedge CLK_IN) begin
if (RESET_IN) begin
cpll_cal_state <= 0;
cpll_cal_state[RESET] <= 1'b1;
cpllreset_int <= 1'b0;
cpllpd_int <= 1'b0;
txprogdivreset_int <= 1'b0;
mask_user_in <= 1'b0;
wr <= 1'b0;
rd <= 1'b0;
end
else begin
cpll_cal_state <= 0;
case(1'b1) // synthesis parallel_case full_case
cpll_cal_state[RESET]:
begin
wait_ctr <= 25'd0;
repeat_ctr <= 4'd0;
mask_user_in <= 1'b1;
di_msk <= 16'b0000_0000_0000_0000;
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[READ_X0E1]:
begin
mask_user_in <= 1'b1;
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
end
else
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[CHECK_X0E1_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X079] <= 1'b1;
else
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
cpll_cal_state[READ_PROGCLK_SEL]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X079] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= {1'b1,progclk_sel_store[14:0]};
end
cpll_cal_state[READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
end
else begin
cpll_cal_state[READ_X079] <= 1'b1;
end
end
cpll_cal_state[CHECK_X079_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
else
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
cpll_cal_state[READ_PROGDIV_CFG]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= {1'b1,dout[14:0]};
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGDIV_CFG]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
di_msk <= progdiv_cfg_store;
end
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
x0e1_store <= dout;
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
end
cpll_cal_state[MODIFY_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
end
cpll_cal_state[MODIFY_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
wait_ctr <= 25'd0;
end
di_msk<= MOD_PROGDIV_CFG;
end
cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
begin
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
end
cpll_cal_state[ASSERT_CPLLRESET]:
begin
cpllreset_int <= 1'b1;
freq_counter_rst <= 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
wait_ctr <= 25'd0;
end
cpll_cal_state[DEASSERT_CPLLRESET]:
begin
if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
end
else begin
cpllreset_int <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
wait_ctr <= 16'd0;
end
end
cpll_cal_state[WAIT_GTCPLLLOCK]:
begin
if(!gtye4_cplllock_sync) begin
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
end
end
cpll_cal_state[RESTORE_READ_X0E1]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
end
end
cpll_cal_state[RESTORE_READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= dout;
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end
end
cpll_cal_state[RESTORE_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
end
cpll_cal_state[RESTORE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]};
end
cpll_cal_state[CLEAR_FLAG_x0E1]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[CLEAR_FLAG_x079]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[WAIT_GTCPLLLOCK2]:
begin
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
if(!gtye4_cplllock_sync)
cal_fail_store <= 1'b1;
else
cal_fail_store <= cal_fail_store;
end
cpll_cal_state[ASSERT_PROGDIVRESET2]:
begin
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
wait_ctr <= wait_ctr + 1'b1;
txprogdivreset_int <= 1'b1;
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
end
else begin
txprogdivreset_int <= 1'b0;
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
begin
if (gtye4_txprgdivresetdone_sync) begin
if (cal_fail_store)
cpll_cal_state[CAL_FAIL] <= 1'b1;
else
cpll_cal_state[CAL_DONE] <= 1'b1;
end
else begin
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
end
end
cpll_cal_state[CAL_FAIL]:
begin
cpll_cal_state[CAL_FAIL] <= 1'b1;
mask_user_in <= 1'b0;
end
cpll_cal_state[CAL_DONE]:
begin
cpll_cal_state[CAL_DONE] <= 1'b1;
mask_user_in <= 1'b0;
end
endcase
end
end // always block
end
else
begin: gen_cpll_cal_gtye4
//pragma translate_on
//CPLL CAL FSM
always @(posedge CLK_IN) begin
if (RESET_IN) begin
cpll_cal_state <= 0;
cpll_cal_state[RESET] <= 1'b1;
cpllreset_int <= 1'b0;
cpllpd_int <= 1'b0;
txprogdivreset_int <= 1'b0;
mask_user_in <= 1'b0;
wr <= 1'b0;
rd <= 1'b0;
end
else begin
cpll_cal_state <= 0;
case(1'b1) // synthesis parallel_case full_case
cpll_cal_state[RESET]:
begin
wait_ctr <= 25'd0;
repeat_ctr <= 4'd0;
mask_user_in <= 1'b1;
di_msk <= 16'b0000_0000_0000_0000;
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[READ_X0E1]:
begin
mask_user_in <= 1'b1;
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X0E1_STATUS] <= 1'b1;
end
else
cpll_cal_state[READ_X0E1] <= 1'b1;
end
cpll_cal_state[CHECK_X0E1_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X079] <= 1'b1;
else
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
cpll_cal_state[READ_PROGCLK_SEL]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGCLK_SEL] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X079] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= {1'b1,progclk_sel_store[14:0]};
end
cpll_cal_state[READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
status_store <= dout[15];
cpll_cal_state[CHECK_X079_STATUS] <= 1'b1;
end
else begin
cpll_cal_state[READ_X079] <= 1'b1;
end
end
cpll_cal_state[CHECK_X079_STATUS]:
begin
if (status_store)
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
else
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
cpll_cal_state[READ_PROGDIV_CFG]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= {1'b1,dout[14:0]};
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
else begin
cpll_cal_state[READ_PROGDIV_CFG] <= 1'b1;
end
end
cpll_cal_state[SAVE_PROGDIV_CFG]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
else begin
cpll_cal_state[SAVE_PROGDIV_CFG] <= 1'b1;
end
di_msk <= progdiv_cfg_store;
end
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
x0e1_store <= dout;
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD] <= 1'b1;
end
end
cpll_cal_state[MODIFY_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGCLK_SEL] <= 1'b1;
end
di_msk<= {1'b0,x0e1_store[14:12],MOD_PROGCLK_SEL,x0e1_store[9:0]};
end
cpll_cal_state[MODIFY_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[MODIFY_TXOUTCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[MODIFY_PROGDIV] <= 1'b1;
wait_ctr <= 25'd0;
end
di_msk<= MOD_PROGDIV_CFG;
end
cpll_cal_state[MODIFY_TXOUTCLK_SEL]:
begin
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
end
cpll_cal_state[ASSERT_CPLLPD]:
begin
if (wait_ctr < WAIT_ASSERT_CPLLPD) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
end
else begin
cpllpd_int <= 1'b1;
cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[DEASSERT_CPLLPD]:
begin
if (wait_ctr < SYNTH_WAIT_DEASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[DEASSERT_CPLLPD] <= 1'b1;
end
else begin
cpllpd_int <= 1'b0;
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
wait_ctr <= 16'd0;
freq_counter_rst <= 1'b1;
end
end
cpll_cal_state[ASSERT_CPLLRESET]:
begin
if (wait_ctr < WAIT_ASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[ASSERT_CPLLRESET] <= 1'b1;
end
else begin
cpllreset_int <= 1'b1;
freq_counter_rst <= 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[DEASSERT_CPLLRESET]:
begin
if (wait_ctr < WAIT_DEASSERT_CPLLRESET) begin
wait_ctr <= wait_ctr + 1'b1;
cpll_cal_state[DEASSERT_CPLLRESET] <= 1'b1;
end
else begin
cpllreset_int <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
wait_ctr <= 16'd0;
end
end
cpll_cal_state[WAIT_GTCPLLLOCK]:
begin
if(wait_ctr < WAIT_CPLLLOCK) begin
cpll_cal_state[WAIT_GTCPLLLOCK] <= 1'b1;
wait_ctr <= wait_ctr + 1'b1;
end
else begin
cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
wait_ctr <= 16'd0;
end
end
cpll_cal_state[ASSERT_PROGDIVRESET]:
begin
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
wait_ctr <= wait_ctr + 1'b1;
txprogdivreset_int <= 1'b1;
cpll_cal_state[ASSERT_PROGDIVRESET] <= 1'b1;
end
else begin
txprogdivreset_int <= 1'b0;
cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[WAIT_PRGDIVRESETDONE]:
begin
if (gtye4_txprgdivresetdone_sync) begin
cpll_cal_state[CHECK_FREQ] <= 1'b1;
freq_counter_rst <= 1'b0;
end
else begin
cpll_cal_state[WAIT_PRGDIVRESETDONE] <= 1'b1;
end
end
cpll_cal_state[CHECK_FREQ]:
begin
if(freq_cnt_done) begin
if ((txoutclk_freq_cnt >= (TXOUTCLK_PERIOD_IN - CNT_TOL_IN)) & (txoutclk_freq_cnt <= (TXOUTCLK_PERIOD_IN + CNT_TOL_IN))) begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
cal_fail_store <= 1'b0;
end
else begin
if (repeat_ctr < REPEAT_RESET_LIMIT) begin
cpll_cal_state[ASSERT_CPLLPD] <= 1'b1;
repeat_ctr <= repeat_ctr + 1'b1;
end
else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
cal_fail_store <= 1'b1;
end
end
end
else
cpll_cal_state[CHECK_FREQ] <= 1'b1;
end
cpll_cal_state[RESTORE_READ_X0E1]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progclk_sel_store <= dout;
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X0E1] <= 1'b1;
end
end
cpll_cal_state[RESTORE_READ_X079]:
begin
rd <= 1'b1;
if (drp_done) begin
rd <= 1'b0;
progdiv_cfg_store <= dout;
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end else begin
cpll_cal_state[RESTORE_READ_X079] <= 1'b1;
end
end
cpll_cal_state[RESTORE_PROGDIV]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGDIV] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? ((USER_TXPLLCLKSEL == 2'b11)? 16'hE078 : ((C_PCIE_CORECLK_FREQ == 250) ? 16'hE060 : 16'hE078)) : progdiv_cfg_store;
end
cpll_cal_state[RESTORE_PROGCLK_SEL]:
begin
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
else begin
cpll_cal_state[RESTORE_PROGCLK_SEL] <= 1'b1;
end
di_msk <= (C_PCIE_ENABLE) ? {1'b0,progclk_sel_store[14:12],2'b10,progclk_sel_store[9:0]} : {1'b0,progclk_sel_store[14:0]};
end
cpll_cal_state[CLEAR_FLAG_x0E1]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x0E1] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[CLEAR_FLAG_x079]:
begin
//set [15] to 0
wr <= 1'b1;
if (drp_done) begin
wr <= 1'b0;
cpll_cal_state[WAIT_GTCPLLLOCK2] <= 1'b1;
end
else begin
cpll_cal_state[CLEAR_FLAG_x079] <= 1'b1;
end
// clear
di_msk <= 16'h0000;
end
cpll_cal_state[WAIT_GTCPLLLOCK2]:
begin
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
if(!gtye4_cplllock_sync)
cal_fail_store <= 1'b1;
else
cal_fail_store <= cal_fail_store;
end
cpll_cal_state[ASSERT_PROGDIVRESET2]:
begin
if (wait_ctr < WAIT_WIDTH_PROGDIVRESET) begin
wait_ctr <= wait_ctr + 1'b1;
txprogdivreset_int <= 1'b1;
cpll_cal_state[ASSERT_PROGDIVRESET2] <= 1'b1;
end
else begin
txprogdivreset_int <= 1'b0;
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
wait_ctr <= 25'd0;
end
end
cpll_cal_state[WAIT_PRGDIVRESETDONE2]:
begin
if (gtye4_txprgdivresetdone_sync) begin
if (cal_fail_store)
cpll_cal_state[CAL_FAIL] <= 1'b1;
else
cpll_cal_state[CAL_DONE] <= 1'b1;
end
else begin
cpll_cal_state[WAIT_PRGDIVRESETDONE2] <= 1'b1;
end
end
cpll_cal_state[CAL_FAIL]:
begin
cpll_cal_state[CAL_FAIL] <= 1'b1;
mask_user_in <= 1'b0;
end
cpll_cal_state[CAL_DONE]:
begin
cpll_cal_state[CAL_DONE] <= 1'b1;
mask_user_in <= 1'b0;
end
endcase
end
end // always block
//pragma translate_off
end
endgenerate
//pragma translate_on
always @(posedge CLK_IN) begin
if (cpll_cal_state[RESET])
txoutclksel_int <= 3'b0;
else if (cpll_cal_state[MODIFY_TXOUTCLK_SEL])
txoutclksel_int <= MOD_TXOUTCLK_SEL;
end
always @(posedge CLK_IN) begin
if (cpll_cal_state[RESET]) begin
daddr <= 10'h000;
mask <= 16'b1111_1111_1111_1111;
end
else if (cpll_cal_state[READ_X0E1] | cpll_cal_state[SAVE_PROGCLK_SEL] | cpll_cal_state[RESTORE_READ_X0E1] | cpll_cal_state[CLEAR_FLAG_x0E1] | cpll_cal_state[READ_X0E1_BEFORE_PROGCLK_SEL_MOD]) begin
daddr <= ADDR_X0E1;
end
else if (cpll_cal_state[READ_X079] | cpll_cal_state[SAVE_PROGDIV_CFG] | cpll_cal_state[RESTORE_READ_X079] | cpll_cal_state[CLEAR_FLAG_x079]) begin
daddr <= ADDR_X079;
end
else if (cpll_cal_state[READ_PROGCLK_SEL] | cpll_cal_state[MODIFY_PROGCLK_SEL] | cpll_cal_state[RESTORE_PROGCLK_SEL]) begin
daddr <= ADDR_TX_PROGCLK_SEL;
end
else if (cpll_cal_state[READ_PROGDIV_CFG] | cpll_cal_state[MODIFY_PROGDIV] | cpll_cal_state[RESTORE_PROGDIV]) begin
daddr <= ADDR_TX_PROGDIV_CFG;
end
end
assign drp_done = drp_state[DRP_DONE];
assign GTYE4_CHANNEL_DRPEN_OUT = den;
assign GTYE4_CHANNEL_DRPWE_OUT = dwe;
assign GTYE4_CHANNEL_DRPADDR_OUT = daddr;
assign GTYE4_CHANNEL_DRPDI_OUT = di;
assign drdy = GTYE4_CHANNEL_DRPRDY_IN;
assign dout = GTYE4_CHANNEL_DRPDO_IN;
always @(posedge CLK_IN or posedge RESET_IN) begin
if (RESET_IN) begin
den <= 1'b0;
dwe <= 1'b0;
di <= 16'h0000;
drp_state <= 0;
drp_state[DRP_WAIT] <= 1'b1;
end
else begin
drp_state <= 0;
case (1'b1) // synthesis parallel_case full_case
drp_state[DRP_WAIT]:
begin
if (rd) drp_state[DRP_READ] <= 1'b1;
else if (wr) drp_state[DRP_WRITE] <= 1'b1;
else drp_state[DRP_WAIT] <= 1'b1;
end
drp_state[DRP_READ]:
begin
den <= 1'b1;
drp_state[DRP_READ_ACK] <= 1'b1;
end
drp_state[DRP_READ_ACK]:
begin
den <= 1'b0;
if (drdy == 1'b1) begin
if (rd) drp_state[DRP_DONE] <= 1'b1;
else drp_state[DRP_MODIFY] <= 1'b1;
end
else drp_state[DRP_READ_ACK] <= 1'b1;
end
drp_state[DRP_MODIFY]:
begin
drp_state[DRP_WRITE] <= 1'b1;
end
drp_state[DRP_WRITE]:
begin
den <= 1'b1;
dwe <= 1'b1;
di <= di_msk;
drp_state[DRP_WRITE_ACK] <= 1'b1;
end
drp_state[DRP_WRITE_ACK]:
begin
den <= 1'b0;
dwe <= 1'b0;
if (drdy == 1'b1) drp_state[DRP_DONE] <= 1'b1;
else drp_state[DRP_WRITE_ACK] <= 1'b1;
end
drp_state[DRP_DONE]:
begin
drp_state[DRP_WAIT] <= 1'b1;
end
endcase
end
end
//debug logic - convert one hot state to binary
genvar i,j;
generate
for (j=0; j<5; j=j+1)
begin : jl
wire [32-1:0] tmp_mask;
for (i=0; i<32; i=i+1)
begin : il
assign tmp_mask[i] = i[j];
end
assign cpll_cal_state_bin[j] = |(tmp_mask & cpll_cal_state);
end
endgenerate
endmodule //CPLL_CAL
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_M_V
`define SKY130_FD_SC_LP__NAND3B_M_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_m (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_m (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_M_V
|
//*****************************************************************************
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// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v2_3_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_double_ll (
clock,
resetn,
dataa,
datab,
result,
enable);
input enable;
input clock, resetn;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
// Latency 10
acl_fp_custom_add_core_double core(
.clock(clock),
.resetn(resetn),
.dataa(dataa),
.datab(datab),
.result(result),
.valid_in(),
.valid_out(),
.stall_in(),
.stall_out(),
.enable(enable));
defparam core.HIGH_CAPACITY = 0;
defparam core.FLUSH_DENORMS = 0;
defparam core.HIGH_LATENCY = 0;
defparam core.ROUNDING_MODE = 0;
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// Behavioral model for the register file
module RegFileWW (rd1data,rd2data,wrdata,rd1addr,rd2addr,wraddr,
rd1en,rd2en,wren,wrbyteen,clk);
// Definitions for the constants the advanced register file
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Output signals...
/**
* Output data that's read from the 2 ports of the advanced
* register file: data from Port 1 and Port 2
*
* Stay at high impedance state if no read operation is performed
*/
output [127:0] rd1data,rd2data;
// ===============================================================
// Input signals
// Input data coming into the write port of the register file
input [0:127] wrdata;
// Clock signal to facilitate state transitions
input clk;
// Write enable signal to facilitate writing signals; active-high
input wren;
// Read enable signals for two read ports; active-high
input rd1en, rd2en;
/**
* Addresses for write and read operations
*
* wraddr must have valid output data at positive edge of the
* clock when wren is set to logic HIGH
*
* rd?addr should contain valid value when rd?en = HIGH
*/
input [4:0] wraddr, rd1addr, rd2addr;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [127:0] rd1data,rd2data; // Output signals
/**
* (32 word) depth and (128 bits per word) width
*/
reg [127:0] reg_file [31:0]; // Store the data here
reg [127:0] ones; // 128-bit ones
reg [127:0] result; // ones & operand
reg [7:0] operand; // Write data to operate with
// ===============================================================
always @(posedge clk)
begin
ones=128'd0;
ones=ones-1'd1;
if(wren)
begin
if(wrbyteen==16'h1)
begin
operand=wrdata[0:7];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3)
begin
operand=wrdata[8:15];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7)
begin
operand=wrdata[16:23];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hf)
begin
operand=wrdata[24:31];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1f)
begin
operand=wrdata[32:39];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3f)
begin
operand=wrdata[40:47];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7f)
begin
operand=wrdata[48:55];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hff)
begin
operand=wrdata[56:63];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1ff)
begin
operand=wrdata[64:71];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3ff)
begin
operand=wrdata[72:79];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7ff)
begin
operand=wrdata[80:87];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hfff)
begin
operand=wrdata[88:95];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h1fff)
begin
operand=wrdata[96:103];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h3fff)
begin
operand=wrdata[104:111];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'h7fff)
begin
operand=wrdata[112:119];
result = ones & operand;
reg_file[wraddr] <= result;
end
else if(wrbyteen==16'hffff)
begin
operand=wrdata[120:127];
result = ones & operand;
reg_file[wraddr] <= result;
end
end
//if(rd1en && !((rd1addr==5'bxxxxx) || (rd1addr==5'bzzzzz)))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd1en)
begin
rd1data<=reg_file[rd1addr];
end
else
begin
rd1data<=128'b0;
end
//if(rd2en && (rd2addr!=5'bx) && (rd2addr!=5'bz))
/**
* Assume that no hardware errors will occur such that
* the values of the buses or signals will never be at the
* value X or Z.
*
* This can be ensured if the logic block is reset before
* usage.
*/
if(rd2en)
begin
rd2data<=reg_file[rd2addr];
end
else
begin
rd2data<=128'b0;
end
end
endmodule
|
/***********************************************************************************************************************
* Copyright (C) 2017 Andrew Zonenberg and contributors *
* *
* This program is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General *
* Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) *
* any later version. *
* *
* This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied *
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for *
* more details. *
* *
* You should have received a copy of the GNU Lesser General Public License along with this program; if not, you may *
* find one here: *
* https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt *
* or you may search the http://www.gnu.org website for the version 2.1 license, or you may write to the Free Software *
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA *
**********************************************************************************************************************/
`default_nettype none
/**
INPUTS:
FIXME
OUTPUTS:
FIXME
TEST PROCEDURE:
FIXME
*/
module DCMP(muxsel, greater, equal, count_overflow);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// I/O declarations
(* LOC = "P20 P19" *)
input wire[1:0] muxsel;
(* LOC = "P18" *)
output wire greater;
(* LOC = "P17" *)
output wire equal;
(* LOC = "P16" *)
output wire count_overflow;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// System reset stuff
//Power-on reset
wire por_done;
GP_POR #(
.POR_TIME(500)
) por (
.RST_DONE(por_done)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// RC oscillator clock
wire clk_2mhz;
GP_RCOSC #(
.PWRDN_EN(0),
.AUTO_PWRDN(0),
.OSC_FREQ("2M"),
.HARDIP_DIV(1),
.FABRIC_DIV(1)
) rcosc (
.PWRDN(1'b0),
.CLKOUT_HARDIP(clk_2mhz),
.CLKOUT_FABRIC()
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Buffer the RC oscillator clock
//This drives the MuxedClockBuffer for the ADC/DCMP
wire clk_2mhz_buf;
GP_CLKBUF clkbuf (
.IN(clk_2mhz),
.OUT(clk_2mhz_buf));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// A counter driving the input of the DCMP/PWM
localparam COUNT_MAX = 255;
//Explicitly instantiated counter b/c we don't yet have inference support when using POUT
wire[7:0] count_pout;
GP_COUNT8 #(
.CLKIN_DIVIDE(1),
.COUNT_TO(COUNT_MAX),
.RESET_MODE("RISING")
) cnt (
.CLK(clk_2mhz),
.RST(1'b0),
.OUT(count_overflow),
.POUT(count_pout)
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reference inputs to the DCMP
wire[7:0] ref0;
wire[7:0] ref1;
wire[7:0] ref2;
wire[7:0] ref3;
GP_DCMPREF #(.REF_VAL(8'h80)) rs0(.OUT(ref0));
GP_DCMPREF #(.REF_VAL(8'h40)) rs1(.OUT(ref1));
GP_DCMPREF #(.REF_VAL(8'hc0)) rs2(.OUT(ref2));
GP_DCMPREF #(.REF_VAL(8'hf0)) rs3(.OUT(ref3));
wire[7:0] muxouta;
wire[7:0] muxoutb;
GP_DCMPMUX mux(
.SEL(muxsel),
.OUTA(muxouta),
.OUTB(muxoutb),
.IN0(ref0),
.IN1(ref1),
.IN2(ref2),
.IN3(ref3));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The DCMP itself
GP_DCMP #(
.GREATER_OR_EQUAL(1'b0),
.CLK_EDGE("RISING"),
.PWRDN_SYNC(1'b1)
) dcmp(
.INP(muxouta),
.INN(count_pout),
.CLK(clk_2mhz_buf),
.PWRDN(1'b0),
.GREATER(greater),
.EQUAL(equal)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug749
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
genvar g;
for (g=1; g<3; ++g) begin : gblk
sub2 #(.IN(g)) u ();
//sub #(.IN(g)) u2 ();
end
sub1 #(.IN(0)) u ();
always @ (posedge clk) begin
if (t.u.IN != 0) $stop;
if (t.u.FLAVOR != 1) $stop;
//if (t.u2.IN != 0) $stop; // This should be not found
if (t.gblk[1].u.IN != 1) $stop;
if (t.gblk[2].u.IN != 2) $stop;
if (t.gblk[1].u.FLAVOR != 2) $stop;
if (t.gblk[2].u.FLAVOR != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub1 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 1;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
module sub2 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 2;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_SC_deviders_s_lfs_XOR.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_SC_serial_lfs_XOR_***
// File Name: d_SC_deviders_s_lfs_XOR.v
//
// Version: v1.0.1-256B_T14
//
// Description: Serial linear feedback shift XOR for data area
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.1
// - minor modification for releasing
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_SC_parameters.vh"
`timescale 1ns / 1ps
module d_SC_serial_lfs_XOR_001(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1001100100001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_003(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1111010111001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_005(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000010100011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_007(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000010100101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_009(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1101110001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_011(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011100010101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_013(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1010101001011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_015(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000011001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_017(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011111000001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_019(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1110010111011;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_021(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1000000110101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_023(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1100111001001;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_025(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1100100101101;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
module d_SC_serial_lfs_XOR_027(i_message, i_cur_remainder, o_nxt_remainder);
parameter [0:12] MIN_POLY = 13'b1011101001111;
input wire i_message;
input wire [`D_SC_GF_ORDER-1:0] i_cur_remainder;
output wire [`D_SC_GF_ORDER-1:0] o_nxt_remainder;
wire w_FB_term;
assign w_FB_term = i_cur_remainder[`D_SC_GF_ORDER-1];
assign o_nxt_remainder[0] = i_message ^ w_FB_term;
genvar i;
generate
for (i=1; i<`D_SC_GF_ORDER; i=i+1)
begin: linear_function
if (MIN_POLY[i] == 1)
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1] ^ w_FB_term;
end
else
begin
assign o_nxt_remainder[i] = i_cur_remainder[i-1];
end
end
endgenerate
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Serial Control Bus from Cypress chip
module serial_io
( input master_clk,
input serial_clock,
input serial_data_in,
input enable,
input reset,
inout wire serial_data_out,
output reg [6:0] serial_addr,
output reg [31:0] serial_data,
output wire serial_strobe,
input wire [31:0] readback_0,
input wire [31:0] readback_1,
input wire [31:0] readback_2,
input wire [31:0] readback_3,
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
input wire [31:0] readback_7
);
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
assign serial_data_out = is_read ? serial_data[31] : 1'bz;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
ser_ctr <= #1 8'd0;
else if(~enable)
ser_ctr <= #1 8'd0;
else if(ser_ctr == 39)
ser_ctr <= #1 8'd0;
else
ser_ctr <= #1 ser_ctr + 8'd1;
always @(posedge serial_clock, posedge reset, negedge enable)
if(reset)
is_read <= #1 1'b0;
else if(~enable)
is_read <= #1 1'b0;
else if((ser_ctr == 7)&&(serial_addr[6]==1))
is_read <= #1 1'b1;
always @(posedge serial_clock, posedge reset)
if(reset)
begin
serial_addr <= #1 7'b0;
serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else if(~enable)
begin
//serial_addr <= #1 7'b0;
//serial_data <= #1 32'b0;
write_done <= #1 1'b0;
end
else
begin
if(~is_read && (ser_ctr == 39))
write_done <= #1 1'b1;
else
write_done <= #1 1'b0;
if(is_read & (ser_ctr==8))
case (serial_addr)
7'd1: serial_data <= #1 readback_0;
7'd2: serial_data <= #1 readback_1;
7'd3: serial_data <= #1 readback_2;
7'd4: serial_data <= #1 readback_3;
7'd5: serial_data <= #1 readback_4;
7'd6: serial_data <= #1 readback_5;
7'd7: serial_data <= #1 readback_6;
7'd8: serial_data <= #1 readback_7;
default: serial_data <= #1 32'd0;
endcase // case(serial_addr)
else if(ser_ctr >= 8)
serial_data <= #1 {serial_data[30:0],serial_data_in};
else if(ser_ctr < 8)
serial_addr <= #1 {serial_addr[5:0],serial_data_in};
end // else: !if(~enable)
reg enable_d1, enable_d2;
always @(posedge master_clk)
begin
enable_d1 <= #1 enable;
enable_d2 <= #1 enable_d1;
end
assign serial_strobe = enable_d2 & ~enable_d1;
endmodule // serial_io
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AxiLite Slave Conversion
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axilite_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_axilite_conv #
(
parameter C_FAMILY = "virtex6",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [3-1:0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER, // Constant =0
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [3-1:0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST, // Constant =1
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER, // Constant =0
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
wire s_awvalid_i;
wire s_arvalid_i;
wire [C_AXI_ADDR_WIDTH-1:0] m_axaddr;
// Arbiter
reg read_active;
reg write_active;
reg busy;
wire read_req;
wire write_req;
wire read_complete;
wire write_complete;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ~ARESETN};
end
assign s_awvalid_i = S_AXI_AWVALID & (C_AXI_SUPPORTS_WRITE != 0);
assign s_arvalid_i = S_AXI_ARVALID & (C_AXI_SUPPORTS_READ != 0);
assign read_req = s_arvalid_i & ~busy & ~|areset_d & ~write_active;
assign write_req = s_awvalid_i & ~busy & ~|areset_d & ((~read_active & ~s_arvalid_i) | write_active);
assign read_complete = M_AXI_RVALID & S_AXI_RREADY;
assign write_complete = M_AXI_BVALID & S_AXI_BREADY;
always @(posedge ACLK) begin : arbiter_read_ff
if (|areset_d)
read_active <= 1'b0;
else if (read_complete)
read_active <= 1'b0;
else if (read_req)
read_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_write_ff
if (|areset_d)
write_active <= 1'b0;
else if (write_complete)
write_active <= 1'b0;
else if (write_req)
write_active <= 1'b1;
end
always @(posedge ACLK) begin : arbiter_busy_ff
if (|areset_d)
busy <= 1'b0;
else if (read_complete | write_complete)
busy <= 1'b0;
else if ((write_req & M_AXI_AWREADY) | (read_req & M_AXI_ARREADY))
busy <= 1'b1;
end
assign M_AXI_ARVALID = read_req;
assign S_AXI_ARREADY = M_AXI_ARREADY & read_req;
assign M_AXI_AWVALID = write_req;
assign S_AXI_AWREADY = M_AXI_AWREADY & write_req;
assign M_AXI_RREADY = S_AXI_RREADY & read_active;
assign S_AXI_RVALID = M_AXI_RVALID & read_active;
assign M_AXI_BREADY = S_AXI_BREADY & write_active;
assign S_AXI_BVALID = M_AXI_BVALID & write_active;
// Address multiplexer
assign m_axaddr = (read_req | (C_AXI_SUPPORTS_WRITE == 0)) ? S_AXI_ARADDR : S_AXI_AWADDR;
// Id multiplexer and flip-flop
reg [C_AXI_ID_WIDTH-1:0] s_axid;
always @(posedge ACLK) begin : axid
if (read_req) s_axid <= S_AXI_ARID;
else if (write_req) s_axid <= S_AXI_AWID;
end
assign S_AXI_BID = s_axid;
assign S_AXI_RID = s_axid;
assign M_AXI_AWADDR = m_axaddr;
assign M_AXI_ARADDR = m_axaddr;
// Feed-through signals
assign S_AXI_WREADY = M_AXI_WREADY & ~|areset_d;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_WVALID = S_AXI_WVALID & ~|areset_d;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_ARPROT = S_AXI_ARPROT;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
// lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
// RFID Reader for testing epc class 1 gen 2 tags.
// rigidly assume clock = 7.812mhz. (this makes our divide ratios work out nicely)
// for an 8mhz crystal, we are off by about 2%
`timescale 1ns/1ns
module rfid_reader (
// basic setup connections
reset, clk, tag_backscatter, reader_modulation
);
input reset, clk, tag_backscatter;
output reader_modulation;
// Packets (valid tx_cmd values)
parameter QUERYREP = 0;
parameter ACK = 1;
parameter QUERY = 2;
parameter QUERYADJ = 3;
parameter SELECT = 4;
parameter NACK = 5;
parameter REQRN = 6;
parameter READ = 7;
parameter WRITE = 8;
parameter KILL = 9;
parameter LOCK = 10;
parameter ACCESS = 11;
parameter BLOCKWRITE = 12;
parameter BLOCKERASE = 13;
// Query parameters
parameter DR = 1'd0; // 0 = 8, 1 = 64/3
parameter M = 2'd0; // 0 to 3
parameter TREXT = 1'd0; // 0 or 1
parameter SEL = 2'd0; // 0 or 1
parameter SESSION = 2'd0; // 0 or 1
parameter TARGET = 1'd0; // 0 or 1
parameter Q = 4'd2; // 0 to 15
// TX Timing info
parameter DELIM = 16'd15000; // delimiter = 15us
parameter PW = 16'd1000; //
parameter TARI = 16'd6250; //
parameter RTCAL = 16'd18750; // 2.5*TARI<RTCAL<3*TARI
parameter TRCAL = 16'd25000; // >RTCAL
wire [2:0] miller;
assign miller = M;
wire trext;
assign trext = TREXT;
wire divide_ratio;
assign divide_ratio = DR;
wire [15:0] tari_ns;
assign tari_ns = TARI;
wire [15:0] trcal_ns;
assign trcal_ns = TRCAL;
wire [2:0] q_adj;
assign q_adj = 0;
wire [3:0] slot_q;
assign slot_q = Q;
wire [1:0] session;
assign session = SESSION;
wire [1:0] select;
assign select = SEL;
wire target;
assign target = TARGET;
reg [3:0] send_packet_type;
reg start_tx;
reg [15:0] tx_handle;
wire [15:0] rx_handle;
wire reader_done, rx_timeout, rx_packet_complete, reader_running;
rfid_reader_packet_rxtx UREADER (
// basic setup connections
reset, clk, tag_backscatter, reader_modulation,
// modulation settings
miller, trext, divide_ratio, tari_ns, trcal_ns,
// tag state settings
slot_q, q_adj, session, target, select,
// command to send, posedge send trigger
send_packet_type, start_tx, reader_done, rx_timeout, rx_packet_complete, reader_running,
// tx payload info
tx_handle,
// rx payload info
rx_handle
);
// divide time periods by 128 ns via shift right 7 to get clock cycles
parameter CLK_EXP = 7;
wire [15:0] startup_counts;
assign startup_counts = 16'd50000 >> CLK_EXP;
reg [5:0] reader_state;
parameter STATE_INIT = 0;
parameter STATE_QUERY = 1;
parameter STATE_QUERYREP = 2;
parameter STATE_ACK = 3;
parameter STATE_REQRN = 4;
parameter STATE_READ = 5;
parameter STATE_REQMASK = 6;
parameter STATE_WRITE = 7;
reg started;
reg [15:0] counter;
always @ (posedge clk or posedge reset) begin
if (reset) begin
reader_state <= 0;
started <= 0;
tx_handle <= 0;
start_tx <= 0;
counter <= 0;
send_packet_type <= 0;
end else begin
case(reader_state)
STATE_INIT: begin
if (!started) begin
counter <= 0;
started <= 1;
end else begin
if (counter >= startup_counts) begin
reader_state <= STATE_QUERY;
started <= 0;
end else begin
counter <= counter + 1;
end
end
end
STATE_QUERY: begin
send_packet_type <= QUERY;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_ACK;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERYREP;
started <= 0;
end
end
STATE_QUERYREP: begin
send_packet_type <= QUERYREP;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_ACK;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERYREP;
started <= 0;
end
end
STATE_ACK: begin
send_packet_type <= ACK;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_REQRN;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERY;
started <= 0;
end
end
STATE_REQRN: begin
send_packet_type <= REQRN;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_READ;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERY;
started <= 0;
end
end
STATE_READ: begin
send_packet_type <= READ;
if (!started && reader_running) begin
start_tx <= 0;
started <= 1;
end else if (!started && !reader_running) begin
start_tx <= 1;
end else if (started && reader_done && rx_packet_complete) begin
tx_handle <= rx_handle;
reader_state <= STATE_QUERY;
started <= 0;
end else if (started && reader_done && !rx_packet_complete) begin
reader_state <= STATE_QUERY;
started <= 0;
end
end
default: begin
reader_state <= 0;
end
endcase
end
end
endmodule
|
`timescale 1ns/1ps
module test;
reg pass;
reg c1reg,c2reg;
wire rla, rlc, rlo;
wire rha, rhc, rho;
wire c1 = c1reg;
wire c2 = c2reg;
// Pull the pins opposite to the arm.
pulldown pd1 (rla);
pullup (weak1) pu1 (rlc,rlo);
pulldown (weak0) pd2 (rhc,rho);
pullup pu2 (rha);
SPDT_RELAY rl (.COIL1(c1), .COIL2(c2), .ARM(rla), .NC(rlc), .NO(rlo));
SPDT_RELAY rh (.COIL1(c1), .COIL2(c2), .ARM(rha), .NC(rhc), .NO(rho));
initial begin
pass = 1'b1;
// Test both coil terminals low.
c1reg = 0;
c2reg = 0;
#10;
if (rla !== 1'b0 || rlo !== 1'b1 || rlc !== 1'b0) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b0 || rhc !== 1'b1) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
// Test c1 low and c2 high.
c2reg = 1;
#10;
if (rla !== 1'b0 || rlo !== 1'b0 || rlc !== 1'b1) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b1 || rhc !== 1'b0) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
// Test both coil terminal high.
c1reg = 1;
#10;
if (rla !== 1'b0 || rlo !== 1'b1 || rlc !== 1'b0) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b0 || rhc !== 1'b1) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
// Test c1 high and c2 low.
c2reg = 0;
#10;
if (rla !== 1'b0 || rlo !== 1'b0 || rlc !== 1'b1) begin
$display("Failed R1 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rla, rlc, rlo);
pass = 1'b0;
end
if (rha !== 1'b1 || rho !== 1'b1 || rhc !== 1'b0) begin
$display("Failed R2 coil (%b-%b), arm=%b, NC=%b, NO=%b",
c1, c2, rha, rhc, rho);
pass = 1'b0;
end
if (pass) $display ("PASSED");
$finish;
end
endmodule
module SPDT_RELAY (COIL1, COIL2, ARM, NC, NO);
inout COIL1, COIL2, ARM, NC, NO;
wire coil = ((COIL1===1'b1) && (COIL2===1'b0)) ||
((COIL1===1'b0) && (COIL2===1'b1));
wire #1 dly_coil = coil;
wire coil_on = coil & dly_coil;
wire coil_off = !coil & !dly_coil;
tranif1 t1 (ARM,NC,coil_off);
tranif1 t2 (ARM,NO,coil_on);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_TB_V
`define SKY130_FD_SC_MS__CLKBUF_TB_V
/**
* clkbuf: Clock tree buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ms__clkbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_TB_V
|
// Check behaviour with out-of-range and undefined array indices
// on LHS of procedural continuous (reg) assignment.
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
module top;
reg [1:0] array1[2:1];
reg [1:0] array2[1:0];
reg [1:0] var1;
`ifndef VLOG95
real array3[2:1];
real array4[1:0];
real var2;
`endif
reg failed;
initial begin
failed = 0;
array1[1] = 2'd0;
array1[2] = 2'd0;
array2[0] = 2'd0;
array2[1] = 2'd0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array1[0] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[0];
`endif
/* This is not supported at present
assign array1[1] = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd1) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[1];
assign array1[2] = var1;
var1 = 2'd1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd1)) failed = 1;
var1 = 2'd2;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd2)) failed = 1;
deassign array1[2];
*/
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array1[3] = var1;
#1 $display("array = %h %h", array1[2], array1[1]);
if ((array1[1] !== 2'd0) || (array1[2] !== 2'd0)) failed = 1;
deassign array1[3];
assign array2['bx] = 2'd1;
#1 $display("array = %h %h", array2[1], array2[0]);
if ((array2[0] !== 2'd0) || (array2[1] !== 2'd0)) failed = 1;
deassign array2['bx];
`endif
`ifndef VLOG95
array3[1] = 0.0;
array3[2] = 0.0;
array4[0] = 0.0;
array4[1] = 0.0;
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array3[0] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[0];
`endif
/* This is not supported at present
assign array3[1] = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 1.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[1];
assign array3[2] = var2;
var2 = 1.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 1.0)) failed = 1;
var2 = 2.0;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 2.0)) failed = 1;
deassign array3[2];
*/
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
assign array3[3] = var2;
#1 $display("array = %0g %0g", array3[2], array3[1]);
if ((array3[1] != 0.0) || (array3[2] != 0.0)) failed = 1;
deassign array3[3];
assign array4['bx] = 1.0;
#1 $display("array = %0g %0g", array4[1], array4[0]);
if ((array4[0] != 0.0) || (array4[1] != 0.0)) failed = 1;
deassign array4['bx];
`endif
`endif
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR2_BLACKBOX_V
`define SKY130_FD_SC_HD__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR2_BLACKBOX_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
//
// bug354
typedef logic [5:0] data_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire rst;
data_t iii_in = crc[5:0];
data_t jjj_in = crc[11:6];
data_t iii_out;
data_t jjj_out;
logic [1:0] ctl0 = crc[63:62];
aaa aaa (.*);
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<10) begin
sum <= 64'h0;
rst <= 1'b1;
end
else if (cyc<90) begin
rst <= 1'b0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module bbb
(
output data_t ggg_out[1:0],
input data_t ggg_in [1:0],
input [1:0] [1:0] ctl,
input logic clk,
input logic rst
);
genvar i;
generate
for (i=0; i<2; i++) begin: PPP
always_ff @(posedge clk) begin
if (rst) begin
ggg_out[i] <= 6'b0;
end
else begin
if (ctl[i][0]) begin
if (ctl[i][1]) begin
ggg_out[i] <= ~ggg_in[i];
end else begin
ggg_out[i] <= ggg_in[i];
end
end
end
end
end
endgenerate
endmodule
module aaa
(
input data_t iii_in,
input data_t jjj_in,
input [1:0] ctl0,
output data_t iii_out,
output data_t jjj_out,
input logic clk,
input logic rst
);
// Below is a bug; {} concat isn't used to make arrays
bbb bbb (
.ggg_in ({jjj_in, iii_in}),
.ggg_out ({jjj_out, iii_out}),
.ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}),
.*);
endmodule
|
module timer(
input CLK,
input switch_up,
input switch_dn,
input switch_cancel,
input switch_start_stop,
output [7:0] SEG,
output [3:0] DIGIT,
output BUZZER
);
wire s_up, s_dn, s_cancel, s_start_stop;
debouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_up (s_up));
debouncer d2(.CLK (CLK), .switch_input (switch_dn), .trans_up (s_dn));
debouncer d3(.CLK (CLK), .switch_input (switch_cancel), .trans_up (s_cancel));
debouncer d4(.CLK (CLK), .switch_input (switch_start_stop), .trans_up (s_start_stop));
reg alarm_on = 0;
alarm a(.CLK (CLK), .BUZZER (BUZZER), .enable (alarm_on));
reg [3:0] secs = 0;
reg [3:0] ten_secs = 0;
reg [3:0] mins = 1;
reg [3:0] mins_stored;
reg [3:0] unused_digit = 4'd10; // digits above 9 not displayed
reg [25:0] prescaler = 0;
display_7_seg display(.CLK (CLK),
.units (secs), .tens (ten_secs), .hundreds (mins), .thousands (unused_digit),
.SEG (SEG), .DIGIT (DIGIT));
// States
localparam SETTING = 0, RUNNING = 1, BEEPING = 2;
reg [1:0] state = SETTING;
always @(posedge CLK)
begin
case (state)
SETTING : begin
handle_settings();
if (s_start_stop)
begin
mins_stored <= mins;
state <= RUNNING;
end
end
RUNNING : begin
decrement_time();
if (s_start_stop)
begin
state <= SETTING;
end
if (s_cancel)
begin
reset_time();
state <= SETTING;
end
if ((secs == 0) & (ten_secs == 0) & (mins == 0))
begin
alarm_on <= 1;
state <= BEEPING;
end
end
BEEPING : begin
if (s_cancel)
begin
alarm_on <= 0;
state <= SETTING;
reset_time();
end
end
endcase
end
task handle_settings;
begin
if (s_up)
begin
mins <= mins + 1;
if (mins == 9)
begin
mins <= 1;
end
end
if (s_dn)
begin
mins <= mins - 1;
if (mins == 1)
begin
mins <= 9;
end
end
end
endtask
task decrement_time;
begin
prescaler <= prescaler + 1;
if (prescaler == 26'd31999999) // 32 MHz to 1Hz
begin
prescaler <= 0;
secs <= secs - 1;
if (secs < 1)
begin
secs <= 9;
ten_secs <= ten_secs - 1;
if (ten_secs < 1)
begin
ten_secs <= 5;
mins <= mins - 1;
end
end
end
end
endtask
task reset_time;
begin
secs <= 0;
ten_secs <= 0;
mins <= mins_stored;
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41OI_BLACKBOX_V
`define SKY130_FD_SC_HD__A41OI_BLACKBOX_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a41oi (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41OI_BLACKBOX_V
|
//-------------------------
//-------------------------
`include "sd_defines.v"
`define BUFFER_OFFSET 2
module sd_data_phy(
input sd_clk,
input rst,
output reg DAT_oe_o,
output reg[3:0] DAT_dat_o,
input [3:0] DAT_dat_i,
output [1:0] sd_adr_o,
input [7:0] sd_dat_i,
output reg [7:0] sd_dat_o,
output reg sd_we_o,
output reg sd_re_o,
input [3:4] fifo_full,
input [3:4] fifo_empty,
input [1:0] start_dat,
input fifo_acces
);
reg [5:0] in_buff_ptr_read;
reg [5:0] out_buff_ptr_read;
reg crc_ok;
reg [3:0] last_din_read;
reg [7:0] tmp_crc_token ;
reg[2:0] crc_read_count;
//CRC16
reg [3:0] crc_in_write;
reg crc_en_write;
reg crc_rst_write;
wire [15:0] crc_out_write [3:0];
reg [3:0] crc_in_read;
reg crc_en_read;
reg crc_rst_read;
wire [15:0] crc_out_read [3:0];
reg[7:0] next_out;
reg data_read_index;
reg [10:0] transf_cnt_write;
reg [10:0] transf_cnt_read;
parameter SIZE = 6;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 6'b000001;
parameter WRITE_DAT = 6'b000010;
parameter READ_CRC = 6'b000100;
parameter WRITE_CRC = 6'b001000;
parameter READ_WAIT = 6'b010000;
parameter READ_DAT = 6'b100000;
reg in_dat_buffer_empty;
reg [2:0] crc_status_token;
reg busy_int;
reg add_token;
genvar i;
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_write
CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]);
end
endgenerate
generate
for(i=0; i<4; i=i+1) begin:CRC_16_gen_read
CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]);
end
endgenerate
reg q_start_bit;
always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty )
begin : FSM_COMBO
next_state = 0;
case(state)
IDLE: begin
if (start_dat == 2'b01)
next_state=WRITE_DAT;
else if (start_dat == 2'b10)
next_state=READ_WAIT;
else
next_state=IDLE;
end
WRITE_DAT: begin
if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET)
next_state= READ_CRC;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=WRITE_DAT;
end
READ_WAIT: begin
if (DAT_dat_i[0]== 0 )
next_state= READ_DAT;
else
next_state=READ_WAIT;
end
READ_CRC: begin
if ( (crc_read_count == 3'b111) &&(busy_int ==1) )
next_state= WRITE_CRC;
else
next_state=READ_CRC;
end
WRITE_CRC: begin
next_state= IDLE;
end
READ_DAT: begin
if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty)) //Startbit consumed...
next_state= IDLE;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=READ_DAT;
end
endcase
end
always @ (posedge sd_clk or posedge rst )
begin
if (rst ) begin
q_start_bit<=1;
end
else begin
q_start_bit <= DAT_dat_i[0];
end
end
//----------------Seq logic------------
always @ (posedge sd_clk or posedge rst )
begin : FSM_SEQ
if (rst ) begin
state <= #1 IDLE;
end
else begin
state <= #1 next_state;
end
end
reg [4:0] crc_cnt_write;
reg [4:0]crc_cnt_read;
reg [3:0] last_din;
reg [2:0] crc_s ;
reg [7:0] write_buf_0,write_buf_1, sd_data_out;
reg out_buff_ptr,in_buff_ptr;
reg data_send_index;
reg [1:0] sd_adr_o_read;
reg [1:0] sd_adr_o_write;
reg read_byte_cnt;
assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
//assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write;
reg [3:0] in_dat_buffer [63:0];
always @ (negedge sd_clk or posedge rst )
begin
if (rst) begin
DAT_oe_o<=0;
crc_en_write<=0;
crc_rst_write<=1;
transf_cnt_write<=0;
crc_cnt_write<=15;
crc_status_token<=7;
data_send_index<=0;
out_buff_ptr<=0;
in_buff_ptr<=0;
read_byte_cnt<=0;
write_buf_0<=0;
write_buf_1<=0;
sd_re_o<=0;
sd_data_out<=0;
sd_adr_o_write<=0;
crc_in_write<=0;
DAT_dat_o<=0;
last_din<=0;
end
else begin
case(state)
IDLE: begin
DAT_oe_o<=0;
crc_en_write<=0;
crc_rst_write<=1;
crc_cnt_write<=16;
read_byte_cnt<=0;
crc_status_token<=7;
data_send_index<=0;
out_buff_ptr<=0;
in_buff_ptr<=0;
sd_re_o<=0;
transf_cnt_write<=0;
end
WRITE_DAT: begin
transf_cnt_write<=transf_cnt_write+1;
if ( (in_buff_ptr != out_buff_ptr) || (transf_cnt_write<2) ) begin
read_byte_cnt<=read_byte_cnt+1;
sd_re_o<=0;
case (read_byte_cnt)
0:begin
sd_adr_o_write <=2;
sd_re_o<=1;
end
1:begin
if (!in_buff_ptr)
write_buf_0<=sd_dat_i;
else
write_buf_1 <=sd_dat_i;
in_buff_ptr<=in_buff_ptr+1;
end
endcase
end
if (!out_buff_ptr)
sd_data_out<=write_buf_0;
else
sd_data_out<=write_buf_1;
if (transf_cnt_write==1+`BUFFER_OFFSET) begin
crc_rst_write<=0;
crc_en_write<=1;
last_din <=write_buf_0[3:0];
DAT_oe_o<=1;
DAT_dat_o<=0;
crc_in_write<= write_buf_0[3:0];
data_send_index<=1;
out_buff_ptr<=out_buff_ptr+1;
end
else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin
DAT_oe_o<=1;
case (data_send_index)
0:begin
last_din <=sd_data_out[3:0];
crc_in_write <=sd_data_out[3:0];
out_buff_ptr<=out_buff_ptr+1;
end
1:begin
last_din <=sd_data_out[7:4];
crc_in_write <=sd_data_out[7:4];
end
endcase
data_send_index<=data_send_index+1;
DAT_dat_o<= last_din;
if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin
crc_en_write<=0;
end
end
else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin
crc_en_write<=0;
crc_cnt_write<=crc_cnt_write-1;
DAT_oe_o<=1;
DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1];
DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1];
DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1];
DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1];
end
else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin
DAT_oe_o<=1;
DAT_dat_o<=4'b1111;
end
else if (transf_cnt_write !=0) begin
DAT_oe_o<=0;
end
end
endcase
end
end
always @ (posedge sd_clk or posedge rst )
begin
if (rst) begin
add_token<=0;
sd_adr_o_read<=0;
crc_read_count<=0;
sd_we_o<=0;
tmp_crc_token<=0;
crc_rst_read<=0;
crc_en_read<=0;
in_buff_ptr_read<=0;
out_buff_ptr_read<=0;
crc_cnt_read<=0;
transf_cnt_read<=0;
data_read_index<=0;
in_dat_buffer_empty<=0;
next_out<=0;
busy_int<=0;
sd_dat_o<=0;
end
else begin
case(state)
IDLE: begin
add_token<=0;
crc_read_count<=0;
sd_we_o<=0;
tmp_crc_token<=0;
crc_rst_read<=1;
crc_en_read<=0;
in_buff_ptr_read<=0;
out_buff_ptr_read<=0;
crc_cnt_read<=15;
transf_cnt_read<=0;
data_read_index<=0;
in_dat_buffer_empty<=0;
end
READ_DAT: begin
add_token<=1;
crc_rst_read<=0;
crc_en_read<=1;
if (fifo_acces) begin
if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin
data_read_index<=~data_read_index;
case(data_read_index)
0: begin
sd_adr_o_read<=3;
sd_we_o<=0;
next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ];
next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ];
end
1: begin
out_buff_ptr_read<=out_buff_ptr_read+2;
sd_dat_o<=next_out;
sd_we_o<=1;
end
endcase
end
else
in_dat_buffer_empty<=1;
end
if (transf_cnt_read<`BIT_BLOCK_REC) begin
in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i;
crc_in_read<=DAT_dat_i;
crc_ok<=1;
transf_cnt_read<=transf_cnt_read+1;
in_buff_ptr_read<=in_buff_ptr_read+1;
end
else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
transf_cnt_read<=transf_cnt_read+1;
crc_en_read<=0;
last_din_read <=DAT_dat_i;
if (transf_cnt_read> `BIT_BLOCK_REC) begin
crc_cnt_read <=crc_cnt_read-1;
if (crc_out_read[0][crc_cnt_read] != last_din[0])
crc_ok<=0;
if (crc_out_read[1][crc_cnt_read] != last_din[1])
crc_ok<=0;
if (crc_out_read[2][crc_cnt_read] != last_din[2])
crc_ok<=0;
if (crc_out_read[3][crc_cnt_read] != last_din[3])
crc_ok<=0;
if (crc_cnt_read==0) begin
//in_dat_buffer[in_buff_ptr_read] <= {7'b0,crc_ok}
end
end
end
end
READ_CRC: begin
if (crc_read_count<3'b111) begin
crc_read_count<=crc_read_count+1;
tmp_crc_token[crc_read_count] <= DAT_dat_i[0];
end
busy_int <=DAT_dat_i[0];
end
WRITE_CRC: begin
add_token<=1;
sd_adr_o_read<=3;
sd_we_o<=1;
sd_dat_o<=tmp_crc_token;
end
endcase
end
end
//Sync
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 18 23:18:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/ZyboIP/examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ip/system_xlconstant_0_0/system_xlconstant_0_0_sim_netlist.v
// Design : system_xlconstant_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module system_xlconstant_0_0
(dout);
output [0:0]dout;
wire \<const1> ;
assign dout[0] = \<const1> ;
VCC VCC
(.P(\<const1> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_MUX_2TO1_SYMBOL_V
`define SKY130_FD_SC_HDLL__UDP_MUX_2TO1_SYMBOL_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_MUX_2TO1_SYMBOL_V
|
`timescale 1 ns / 1 ps
`include "audio_to_AXI_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module audio_to_AXI_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFSBP_PP_SYMBOL_V
|
`ifdef __ICARUS__
`include "../source/register.v"
`include "../source/alu.v"
`include "../source/cpuController.v"
`endif
module rcpu ( // RCPU
input wire rst, // Reset
input wire clk, // Clock
input wire irq, // Interrupt request
output wire turnOffIRQ, // Interrupt acknowledgement signal
input wire memReady, // Is memory ready
input wire[N-1:0] intAddr, // Interrupt address
input wire[M-1:0] intData, // Interrupt data
input wire[M-1:0] page, // High 16 bits for addressed mode
output reg[N-1:0] memAddr, // Memory address
input wire[M-1:0] memReadIn, // Readed from memory
output reg[M-1:0] memWrite, // For writing to memory
output wire memRE, // Enable reading from memory
output wire memWE, // Enable writing to memory
output wire[1:0] inMask,
output wire[1:0] outMask,
// For debugging only
output wire[M-1:0] A,
output wire[M-1:0] B,
output wire[M-1:0] C,
output wire[N-1:0] PC,
output wire[M-1:0] FP,
output wire[M-1:0] SP,
output wire[5:0] state,
output wire[3:0] F
);
`include "constants"
parameter M = 16; // Data bus width
parameter N = 32; // Address bus width
wire[M-1:0] memRead;
wire stall = !memReady && memRE;
// Registers
//wire[M-1:0] A;
//wire[M-1:0] B;
//wire[M-1:0] C;
//wire[N-1:0] PC; // Program counter
//wire[M-1:0] SP; // Stack pointer
//wire[M-1:0] FP; // Frame pointer
// Enable write signals
wire enA;
wire enB;
wire enC;
wire enPC;
wire enSP;
wire enFP;
wire[1:0] sourcePC;
wire sourceFP;
wire[M-1:0] inR = aluY; // Input to ABC registers
reg[N-1:0] inPC; // Input to program counter
always @ ( * ) begin
inPC = {aluYHigh, aluY};
if (sourcePC == 2'b01)
inPC = {PC[31:16], memRead};
else if (sourcePC == 2'b10)
inPC = {memRead, PC[15:0]};
else if (sourcePC == 2'b11)
inPC = {PC[31:17], aluB, 1'b0};
end
wire[M-1:0] opcode; // Instruction register
wire enIR;
wire[M-1:0] value1; // Internal registers
wire enV1;
wire[M-1:0] value2;
wire enV2;
wire[M-1:0] res;
wire enR;
// Flag register
//wire[3:0] F;
wire enF;
wire[3:0] inFFromAlu;
reg[3:0] inF;
// Flags
wire c = F[3]; // Carry
wire n = F[2]; // Negative
wire z = F[1]; // Zero
wire v = F[0]; // Overflow
wire[M-1:0] aluY; // ALU output
wire[M-1:0] aluYHigh; // ALU output high bits
wire[1:0] sourceF;
wire[3:0] altF;
wire isMul;
wire initSPFP;
wire writeToSP = (memAddr == 32'hFFFF100F) && memWE;
wire[M-1:0] inSP = initSPFP? 16'hFFFE:
writeToSP? memWrite:
aluY;
// Registers logic
register #(M) rIR (clk, memRead, opcode, enIR && !stall, rst, 2'b11, 2'b11);
register #(M) rV1 (clk, memRead, value1, enV1 && !stall, rst, 2'b11, 2'b11);
register #(M) rV2 (clk, memRead, value2, enV2 && !stall, rst, 2'b11, 2'b11);
register #(M) rR (clk, aluY, res, enR && !stall, rst, 2'b11, 2'b11);
register #(M) rA (clk, isMul? yhigh : inR, A, enA && !stall, rst, inMask, outMask);
register #(M) rB (clk, inR, B, enB && !stall, rst, inMask, outMask);
register #(M) rC (clk, inR, C, enC && !stall, rst, inMask, outMask);
register #(N) rPC (clk, inPC, PC, enPC && !stall, rst, 2'b11, 2'b11);
register #(M) rSP (clk, inSP, SP, (enSP || writeToSP) && !stall, rst, 2'b11, 2'b11);
register #(M) rFP (clk, initSPFP? 16'hFFFE: sourceFP? memRead: aluY, FP, enFP && !stall, rst, 2'b11, 2'b11);
register #(4) rF (clk, inF, F, enF && !stall, rst, 2'b11, 2'b11);
assign memRead = memAddr == 32'hFFFF100F ? SP : memReadIn;
// ALU inputs
reg[M-1:0] aluA;
reg[M-1:0] aluAHigh;
reg[M-1:0] aluB;
wire[3:0] aluFunc; // ALU function control bus
wire[M-1:0] aluOutA; // ALU output to A register
wire[3:0] aluASource; // Source of ALU input A
wire[3:0] aluBSource; // Source of ALU input B
reg use32bit; // ALU size control bit
alu alu1 ( // ALU logic
.a (aluA),
.ahigh (aluAHigh),
.b (aluB),
.y (aluY),
.yhigh (aluYHigh),
.func (aluFunc),
.use32bit (use32bit),
.co (inFFromAlu[3]), // Carry flag out
.negative (inFFromAlu[2]),
.zero (inFFromAlu[1]),
.overflow (inFFromAlu[0]),
.ci (c) // Carry flag in
);
wire[2:0] memAddrSource;
wire[3:0] writeDataSource;
wire readStack;
cpuController cpuCTRL ( // CPU control unit (FSM)
// Inputs
.clk (clk),
.stall(stall),
.rst (rst),
.opcode (enIR? memRead : opcode), // Current instruction
.flags (F),
.irq (irq),
// Outputs
.enPC (enPC),
.aluFunc (aluFunc),
.aluA (aluASource),
.aluB (aluBSource),
.enA (enA),
.enB (enB),
.enC (enC),
.saveOpcode (enIR),
.saveMem1 (enV1),
.saveMem2 (enV2),
.memAddr (memAddrSource), // Source of memory read/write address
.we (memWE), // Enable write to memory
.re (memRE), // Enable read from memory
.writeDataSource (writeDataSource), // Source of memory write data
.saveResult (enR), //Enable write to ALU result register
.enF (enF),
.sourceF (sourceF),
.sourceFP (sourceFP),
.enFP (enFP),
.sourcePC (sourcePC),
.inF (altF), // Input to flag register
.enSP (enSP),
.state (state),
.turnOffIRQ (turnOffIRQ),
.readStack (readStack),
.isMul (isMul),
.initSPFP (initSPFP),
.inMask (inMask),
.outMask (outMask)
);
always @ ( * ) begin // ALU input A logic
aluA = 0; // If none, equals 0
use32bit = 0;
aluAHigh = 0;
case (aluASource)
ALU1_FROM_0: aluA = 0;
ALU1_FROM_A: aluA = A;
ALU1_FROM_B: aluA = B;
ALU1_FROM_C: aluA = C;
ALU1_FROM_PC: begin {aluAHigh, aluA} = PC; use32bit = 1; end
ALU1_FROM_MEM: aluA = value1;
ALU1_FROM_HIMEM: begin {aluAHigh, aluA} = {value2, value1};
use32bit = 1;
end
ALU1_FROM_SP: aluA = SP;
ALU1_FROM_XX: aluA = opcode[6:0];
ALU1_FROM_INTADDR: begin {aluAHigh, aluA} = intAddr; use32bit = 1; end
ALU1_FROM_DIRECTREAD: aluA = memRead;
default: aluA = 0;
endcase
end
always @ ( * ) begin // ALU input B logic
aluB = 0; // If none, equals 0
case (aluBSource)
ALU2_FROM_0: aluB = 0;
ALU2_FROM_A: aluB = A;
ALU2_FROM_B: aluB = B;
ALU2_FROM_C: aluB = C;
// From instruction itself
ALU2_FROM_OP: aluB = {{9{opcode[7]}}, opcode[6:0]};
// Adress from J Type instruction
ALU2_FROM_ADDR: aluB = {{3{opcode[12]}}, opcode[11:0], 1'b0}; // From instruction itself
ALU2_FROM_FADDR: aluB = {{8{opcode[7]}}, opcode[6:0], 1'b0};
ALU2_FROM_2: aluB = 2;
ALU2_FROM_FP: aluB = FP;
ALU2_FROM_MEM: aluB = value1;
default: aluB = 0;
endcase
end
always @ ( * ) begin // Flag register logic
case (sourceF)
FLAG_FROM_ALU: inF = inFFromAlu;
FLAG_FROM_ALU_OUT: inF = aluY[3:0];
FLAG_FROM_8BIT: inF = {1'b0, aluY[7], aluY[7:0] == 8'h00, 1'b0};
default: inF = inFFromAlu;
endcase
end
always @ ( * ) begin // Memory address logic
case (memAddrSource)
READ_FROM_PC: memAddr = PC;
READ_FROM_A: memAddr = {page, A};
READ_FROM_ALU: memAddr = readStack? {16'hD000, aluY} : {aluYHigh, aluY};
READ_FROM_SP: memAddr = {16'hD000, SP};
READ_FROM_FASTMEM: memAddr = {25'h1FFFE20, opcode[6:0]};
default: memAddr = PC;
endcase
end
always @ ( * ) begin // Memory write data logic
memWrite = aluY;
case (writeDataSource)
WRITE_FROM_ALU: memWrite = aluY;
WRITE_FROM_RES: memWrite = res;
WRITE_FROM_PC1: memWrite = PC[15:0];
WRITE_FROM_PC2: memWrite = PC[31:16];
WRITE_FROM_FP: memWrite = FP;
WRITE_FROM_A: memWrite = A;
WRITE_FROM_B: memWrite = B;
WRITE_FROM_C: memWrite = C;
WRITE_FROM_INTDATA: memWrite = intData;
WRITE_FROM_F: memWrite = F;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O2BB2AI_PP_SYMBOL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2bb2ai (
//# {{data|Data Signals}}
input A1_N,
input A2_N,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_PP_SYMBOL_V
|
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//
// FRAME GEN
//
//
//
// Description: This module is a pattern generator to test the Aurora
// designs in hardware. It generates data and passes it
// through the Aurora channel. If connected to a framing
// interface, it generates frames of varying size and
// separation. LFSR is used to generate the pseudo-random
// data and lower bits of LFSR are connected to REM bus
`timescale 1 ns / 1 ps
`define DLY #1
module aur1_FRAME_GEN
(
// User Interface
TX_D,
TX_SRC_RDY_N,
TX_DST_RDY_N,
// System Interface
USER_CLK,
RESET,
CHANNEL_UP
);
//*****************************Parameter Declarations****************************
//***********************************Port Declarations*******************************
// User Interface
output [0:63] TX_D;
output TX_SRC_RDY_N;
input TX_DST_RDY_N;
// System Interface
input USER_CLK;
input RESET;
input CHANNEL_UP;
//***************************External Register Declarations***************************
reg TX_SRC_RDY_N;
//***************************Internal Register Declarations***************************
reg [0:15] data_lfsr_r;
wire reset_c;
//*********************************Main Body of Code**********************************
//Generate RESET signal when Aurora channel is not ready
assign reset_c = RESET || !CHANNEL_UP;
//______________________________ Transmit Data __________________________________
//Transmit data when TX_DST_RDY_N is asserted.
//Random data is generated using XNOR feedback LFSR
//TX_SRC_RDY_N is asserted on every cycle with data
always @(posedge USER_CLK)
if(reset_c)
begin
data_lfsr_r <= `DLY 16'hABCD; //random seed value
TX_SRC_RDY_N <= `DLY 1'b1;
end
else if(!TX_DST_RDY_N)
begin
data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]},
data_lfsr_r[0:14]};
TX_SRC_RDY_N <= `DLY 1'b0;
end
//Connect TX_D to the DATA LFSR register
assign TX_D = {4{data_lfsr_r}};
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_aa
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_aa.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_aa.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_aa
//
// No user `defines in this module
module ent_aa
//
// Generated Module inst_aa
//
(
port_aa_1, // Use internally test1
port_aa_2, // Use internally test2, no port generated
port_aa_3, // Interhierachy link, will create p_mix_sig_3_go
port_aa_4, // Interhierachy link, will create p_mix_sig_4_gi
port_aa_5, // Bus, single bits go to outside
port_aa_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// Generated Module Inputs:
input port_aa_4;
// Generated Module Outputs:
output port_aa_1;
output port_aa_2;
output port_aa_3;
output [3:0] port_aa_5;
output [3:0] port_aa_6;
output [5:0] sig_07;
output [8:2] sig_08;
output [4:0] sig_13;
output [6:0] sig_14;
// Generated Wires:
wire port_aa_1;
wire port_aa_2;
wire port_aa_3;
wire port_aa_4;
wire [3:0] port_aa_5;
wire [3:0] port_aa_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire [6:0] sig_14;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_aa
//
//
//!End of Module/s
// --------------------------------------------------------------
|