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module main_pll (inclk0, c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
// synopsys translate_off
.fref (),
.icdrclk (),
// synopsys translate_on
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 5,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=main_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
|
/**
* Copyright 2014 Kevin Townsend
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns/1ps
module std_fifo_tb;
reg rst, clk;
reg push, pop;
reg [7:0] d;
wire [7:0] q;
wire full, empty;
wire [3:0] count;
wire almost_empty;
wire almost_full;
std_fifo dut(
rst,
clk,
push,
pop,
d,
q,
full,
empty,
count,
almost_empty,
almost_full);
integer i;
initial begin
$display("starting testbench");
rst = 1;
push = 0; pop = 0;
d = 0;
#101 rst = 0;
$display("time: %d", $time);
#10 if(empty != 1) begin
$display("test1:failed");
end else begin
$display("test1:passed");
end
#10 push <=1;
d <= 1;
if(empty == 0)
$display("test2:failed");
if(full == 1)
$display("test2:failed full high");
for(i = 2; i < 64; i = i + 1) begin
#10 push <=1;
d <= i;
if(empty == 1) begin
$display("test3:failed empty high, round %d", i);
end
if(full == 1)
$display("test3:failed full high");
end
#10 push <= 1;
d <= 64;
if(empty == 1)
$display("error");
if(full == 1)
$display("error");
#10 if(full == 1)
$display("test4:passed");
else
$display("test4:error");
push <= 0;
pop <= 1;
for(i = 1; i < 65; i = i + 1) begin
#10 if(q != i) begin
$display("ERROR:");
end
end
pop <= 0;
#10
if(empty != 1)
$display("ERROR:");
else
$display("test5:passed");
if(full != 0)
$display("ERROR:");
#100 $finish;
//TODO: check empty
end
initial begin
clk = 1;
forever #5 clk=~clk;
end
initial
$monitor("At time %t, value ", $time);
endmodule
|
`timescale 1 ns / 1 ps
module axis_trigger #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter AXIS_TDATA_SIGNED = "FALSE"
)
(
// System signals
input wire aclk,
input wire pol_data,
input wire [AXIS_TDATA_WIDTH-1:0] msk_data,
input wire [AXIS_TDATA_WIDTH-1:0] lvl_data,
output wire trg_flag,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid
);
reg [1:0] int_comp_reg;
wire int_comp_wire;
generate
if(AXIS_TDATA_SIGNED == "TRUE")
begin : SIGNED
assign int_comp_wire = $signed(s_axis_tdata & msk_data) >= $signed(lvl_data);
end
else
begin : UNSIGNED
assign int_comp_wire = (s_axis_tdata & msk_data) >= lvl_data;
end
endgenerate
always @(posedge aclk)
begin
if(s_axis_tvalid)
begin
int_comp_reg <= {int_comp_reg[0], int_comp_wire};
end
end
assign s_axis_tready = 1'b1;
assign trg_flag = s_axis_tvalid & (pol_data ^ int_comp_reg[0]) & (pol_data ^ ~int_comp_reg[1]);
endmodule
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_acos_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_arccos_s5 inst (
.en (enable),
.areset(1'b0),
.clk(clock),
.a(dataa),
.q(sub_wire0));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V
/**
* srdlrtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_s.v"
`celldefine
module sky130_fd_sc_lp__srdlrtp (
Q ,
RESET_B,
D ,
GATE ,
SLEEP_B
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
input SLEEP_B;
// Local signals
wire buf_Q;
wire RESET;
wire kapwr;
wire vgnd ;
wire vpwr ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_lp__udp_dlatch$PR_pp$PKG$s `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET, SLEEP_B, kapwr, vgnd, vpwr);
bufif1 bufif10 (Q , buf_Q, vpwr );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLRTP_FUNCTIONAL_V |
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// When read and write with the same address, the behavior depends on which
// clock arrives first, and the read/write clock MUST be separated at least
// twrcc, otherwise will incur indeterminate result.
//
// See "TSN45GS2PRF: TSMC 45nm (=N40G) General Purpose Superb Two-Port
// Register File Compiler Databook"
//
`define bsg_mem_1r1w_sync_macro_rf(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_2rf_lg``lgEls``_w``bits``_m``mux``_bit mem \
( \
.AA ( w_addr_i ) \
,.D ( w_data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_v_i ) \
,.CLKW ( clk_i ) \
\
,.AB ( r_addr_i ) \
,.REB ( ~r_v_i ) \
,.CLKR ( clk_i ) \
,.Q ( r_data_o ) \
\
,.RDELAY ( 2'b00 ) \
,.WDELAY ( 2'b00 ) \
); \
end
module bsg_mem_1r1w_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
)
( input clk_i
, input reset_i
, input w_v_i
, input [width_p-1:0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_sync_macro_rf(256,128,8,1) else
`bsg_mem_1r1w_sync_macro_rf(64,88,6,1) else
bsg_mem_1r1w_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p (els_p )
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
//synopsys translate_off
/*
always_ff @(negedge clk_i)
begin
if (reset_i!==1'b1 & (r_v_i | w_v_i))
$display("@@ w=%b w_addr=%x w_data=%x w_mask=%x r=%b r_addr=%x (%m)",w_v_i,w_addr_i,w_data_i,w_mask_i,r_v_i,r_addr_i);
end
*/
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else
begin
$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x)",reset_i, w_addr_i,w_data_i,w_mask_i);
//$finish();
end
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p, harden_p);
assert ( read_write_same_addr_p == 0) else begin
$error("## The hard memory do not support read write the same address. (%m)");
$finish;
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_mask_write_bit)
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_cntrl.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Structural block instantiating the three sub blocks that make up
// a bank machine.
`timescale 1ps/1ps
module mig_7series_v4_0_bank_cntrl #
(
parameter TCQ = 100,
parameter ADDR_CMD_MODE = "1T",
parameter BANK_WIDTH = 3,
parameter BM_CNT_WIDTH = 2,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter ECC = "OFF",
parameter ID = 4,
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2,
parameter nOP_WAIT = 0,
parameter nRAS_CLKS = 10,
parameter nRCD = 5,
parameter nRTP = 4,
parameter nRP = 10,
parameter nWTP_CLKS = 5,
parameter ORDERING = "NORM",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter RAS_TIMER_WIDTH = 5,
parameter ROW_WIDTH = 16,
parameter STARVE_LIMIT = 2
)
(/*AUTOARG*/
// Outputs
wr_this_rank_r, start_rcd, start_pre_wait, rts_row, rts_col, rts_pre, rtc,
row_cmd_wr, row_addr, req_size_r, req_row_r, req_ras,
req_periodic_rd_r, req_cas, req_bank_r, rd_this_rank_r,
rb_hit_busy_ns, ras_timer_ns, rank_busy_r, ordered_r,
ordered_issued, op_exit_req, end_rtp, demand_priority,
demand_act_priority, col_rdy_wr, col_addr, act_this_rank_r, idle_ns,
req_wr_r, rd_wr_r, bm_end, idle_r, head_r, req_rank_r,
rb_hit_busy_r, passing_open_bank, maint_hit, req_data_buf_addr_r,
// Inputs
was_wr, was_priority, use_addr, start_rcd_in,
size, sent_row, sent_col, sending_row, sending_pre, sending_col, rst, row,
req_rank_r_in, rd_rmw, rd_data_addr, rb_hit_busy_ns_in,
rb_hit_busy_cnt, ras_timer_ns_in, rank, periodic_rd_rank_r,
periodic_rd_insert, periodic_rd_ack_r, passing_open_bank_in,
order_cnt, op_exit_grant, maint_zq_r, maint_sre_r, maint_req_r, maint_rank_r,
maint_idle, low_idle_cnt_r, rnk_config_valid_r, inhbt_rd, inhbt_wr,
rnk_config_strobe, rnk_config, inhbt_act_faw_r, idle_cnt, hi_priority,
dq_busy_data, phy_rddata_valid, demand_priority_in, demand_act_priority_in,
data_buf_addr, col, cmd, clk, bm_end_in, bank, adv_order_q,
accept_req, accept_internal_r, rnk_config_kill_rts_col, phy_mc_ctl_full,
phy_mc_cmd_full, phy_mc_data_full
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_internal_r; // To bank_queue0 of bank_queue.v
input accept_req; // To bank_queue0 of bank_queue.v
input adv_order_q; // To bank_queue0 of bank_queue.v
input [BANK_WIDTH-1:0] bank; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] bm_end_in; // To bank_queue0 of bank_queue.v
input clk; // To bank_compare0 of bank_compare.v, ...
input [2:0] cmd; // To bank_compare0 of bank_compare.v
input [COL_WIDTH-1:0] col; // To bank_compare0 of bank_compare.v
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;// To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] demand_act_priority_in;// To bank_state0 of bank_state.v
input [(nBANK_MACHS*2)-1:0] demand_priority_in;// To bank_state0 of bank_state.v
input phy_rddata_valid; // To bank_state0 of bank_state.v
input dq_busy_data; // To bank_state0 of bank_state.v
input hi_priority; // To bank_compare0 of bank_compare.v
input [BM_CNT_WIDTH-1:0] idle_cnt; // To bank_queue0 of bank_queue.v
input [RANKS-1:0] inhbt_act_faw_r; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_rd; // To bank_state0 of bank_state.v
input [RANKS-1:0] inhbt_wr; // To bank_state0 of bank_state.v
input [RANK_WIDTH-1:0]rnk_config; // To bank_state0 of bank_state.v
input rnk_config_strobe; // To bank_state0 of bank_state.v
input rnk_config_kill_rts_col;// To bank_state0 of bank_state.v
input rnk_config_valid_r; // To bank_state0 of bank_state.v
input low_idle_cnt_r; // To bank_state0 of bank_state.v
input maint_idle; // To bank_queue0 of bank_queue.v
input [RANK_WIDTH-1:0] maint_rank_r; // To bank_compare0 of bank_compare.v
input maint_req_r; // To bank_queue0 of bank_queue.v
input maint_zq_r; // To bank_compare0 of bank_compare.v
input maint_sre_r; // To bank_compare0 of bank_compare.v
input op_exit_grant; // To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] order_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;// To bank_queue0 of bank_queue.v
input periodic_rd_ack_r; // To bank_queue0 of bank_queue.v
input periodic_rd_insert; // To bank_compare0 of bank_compare.v
input [RANK_WIDTH-1:0] periodic_rd_rank_r; // To bank_compare0 of bank_compare.v
input phy_mc_ctl_full;
input phy_mc_cmd_full;
input phy_mc_data_full;
input [RANK_WIDTH-1:0] rank; // To bank_compare0 of bank_compare.v
input [(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0] ras_timer_ns_in;// To bank_state0 of bank_state.v
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt; // To bank_queue0 of bank_queue.v
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;// To bank_queue0 of bank_queue.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To bank_state0 of bank_state.v
input rd_rmw; // To bank_state0 of bank_state.v
input [(RANK_WIDTH*nBANK_MACHS*2)-1:0] req_rank_r_in;// To bank_state0 of bank_state.v
input [ROW_WIDTH-1:0] row; // To bank_compare0 of bank_compare.v
input rst; // To bank_state0 of bank_state.v, ...
input sending_col; // To bank_compare0 of bank_compare.v, ...
input sending_row; // To bank_state0 of bank_state.v
input sending_pre;
input sent_col; // To bank_state0 of bank_state.v
input sent_row; // To bank_state0 of bank_state.v
input size; // To bank_compare0 of bank_compare.v
input [(nBANK_MACHS*2)-1:0] start_rcd_in; // To bank_state0 of bank_state.v
input use_addr; // To bank_queue0 of bank_queue.v
input was_priority; // To bank_queue0 of bank_queue.v
input was_wr; // To bank_queue0 of bank_queue.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [RANKS-1:0] act_this_rank_r; // From bank_state0 of bank_state.v
output [ROW_WIDTH-1:0] col_addr; // From bank_compare0 of bank_compare.v
output col_rdy_wr; // From bank_state0 of bank_state.v
output demand_act_priority; // From bank_state0 of bank_state.v
output demand_priority; // From bank_state0 of bank_state.v
output end_rtp; // From bank_state0 of bank_state.v
output op_exit_req; // From bank_state0 of bank_state.v
output ordered_issued; // From bank_queue0 of bank_queue.v
output ordered_r; // From bank_queue0 of bank_queue.v
output [RANKS-1:0] rank_busy_r; // From bank_compare0 of bank_compare.v
output [RAS_TIMER_WIDTH-1:0] ras_timer_ns; // From bank_state0 of bank_state.v
output rb_hit_busy_ns; // From bank_compare0 of bank_compare.v
output [RANKS-1:0] rd_this_rank_r; // From bank_state0 of bank_state.v
output [BANK_WIDTH-1:0] req_bank_r; // From bank_compare0 of bank_compare.v
output req_cas; // From bank_compare0 of bank_compare.v
output req_periodic_rd_r; // From bank_compare0 of bank_compare.v
output req_ras; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] req_row_r; // From bank_compare0 of bank_compare.v
output req_size_r; // From bank_compare0 of bank_compare.v
output [ROW_WIDTH-1:0] row_addr; // From bank_compare0 of bank_compare.v
output row_cmd_wr; // From bank_compare0 of bank_compare.v
output rtc; // From bank_state0 of bank_state.v
output rts_col; // From bank_state0 of bank_state.v
output rts_row; // From bank_state0 of bank_state.v
output rts_pre;
output start_pre_wait; // From bank_state0 of bank_state.v
output start_rcd; // From bank_state0 of bank_state.v
output [RANKS-1:0] wr_this_rank_r; // From bank_state0 of bank_state.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire act_wait_r; // From bank_state0 of bank_state.v
wire allow_auto_pre; // From bank_state0 of bank_state.v
wire auto_pre_r; // From bank_queue0 of bank_queue.v
wire bank_wait_in_progress; // From bank_state0 of bank_state.v
wire order_q_zero; // From bank_queue0 of bank_queue.v
wire pass_open_bank_ns; // From bank_queue0 of bank_queue.v
wire pass_open_bank_r; // From bank_queue0 of bank_queue.v
wire pre_wait_r; // From bank_state0 of bank_state.v
wire precharge_bm_end; // From bank_state0 of bank_state.v
wire q_has_priority; // From bank_queue0 of bank_queue.v
wire q_has_rd; // From bank_queue0 of bank_queue.v
wire [nBANK_MACHS*2-1:0] rb_hit_busies_r; // From bank_queue0 of bank_queue.v
wire rcv_open_bank; // From bank_queue0 of bank_queue.v
wire rd_half_rmw; // From bank_state0 of bank_state.v
wire req_priority_r; // From bank_compare0 of bank_compare.v
wire row_hit_r; // From bank_compare0 of bank_compare.v
wire tail_r; // From bank_queue0 of bank_queue.v
wire wait_for_maint_r; // From bank_queue0 of bank_queue.v
// End of automatics
output idle_ns;
output req_wr_r;
output rd_wr_r;
output bm_end;
output idle_r;
output head_r;
output [RANK_WIDTH-1:0] req_rank_r;
output rb_hit_busy_r;
output passing_open_bank;
output maint_hit;
output [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
mig_7series_v4_0_bank_compare #
(/*AUTOINSTPARAM*/
// Parameters
.BANK_WIDTH (BANK_WIDTH),
.TCQ (TCQ),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH))
bank_compare0
(/*AUTOINST*/
// Outputs
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.req_periodic_rd_r (req_periodic_rd_r),
.req_size_r (req_size_r),
.rd_wr_r (rd_wr_r),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_bank_r (req_bank_r[BANK_WIDTH-1:0]),
.req_row_r (req_row_r[ROW_WIDTH-1:0]),
.req_wr_r (req_wr_r),
.req_priority_r (req_priority_r),
.rb_hit_busy_r (rb_hit_busy_r),
.rb_hit_busy_ns (rb_hit_busy_ns),
.row_hit_r (row_hit_r),
.maint_hit (maint_hit),
.col_addr (col_addr[ROW_WIDTH-1:0]),
.req_ras (req_ras),
.req_cas (req_cas),
.row_cmd_wr (row_cmd_wr),
.row_addr (row_addr[ROW_WIDTH-1:0]),
.rank_busy_r (rank_busy_r[RANKS-1:0]),
// Inputs
.clk (clk),
.idle_ns (idle_ns),
.idle_r (idle_r),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.periodic_rd_insert (periodic_rd_insert),
.size (size),
.cmd (cmd[2:0]),
.sending_col (sending_col),
.rank (rank[RANK_WIDTH-1:0]),
.periodic_rd_rank_r (periodic_rd_rank_r[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.hi_priority (hi_priority),
.maint_rank_r (maint_rank_r[RANK_WIDTH-1:0]),
.maint_zq_r (maint_zq_r),
.maint_sre_r (maint_sre_r),
.auto_pre_r (auto_pre_r),
.rd_half_rmw (rd_half_rmw),
.act_wait_r (act_wait_r));
mig_7series_v4_0_bank_state #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.ECC (ECC),
.ID (ID),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nOP_WAIT (nOP_WAIT),
.nRAS_CLKS (nRAS_CLKS),
.nRP (nRP),
.nRTP (nRTP),
.nRCD (nRCD),
.nWTP_CLKS (nWTP_CLKS),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.RAS_TIMER_WIDTH (RAS_TIMER_WIDTH),
.STARVE_LIMIT (STARVE_LIMIT))
bank_state0
(/*AUTOINST*/
// Outputs
.start_rcd (start_rcd),
.act_wait_r (act_wait_r),
.rd_half_rmw (rd_half_rmw),
.ras_timer_ns (ras_timer_ns[RAS_TIMER_WIDTH-1:0]),
.end_rtp (end_rtp),
.bank_wait_in_progress (bank_wait_in_progress),
.start_pre_wait (start_pre_wait),
.op_exit_req (op_exit_req),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.precharge_bm_end (precharge_bm_end),
.demand_act_priority (demand_act_priority),
.rts_row (rts_row),
.rts_pre (rts_pre),
.act_this_rank_r (act_this_rank_r[RANKS-1:0]),
.demand_priority (demand_priority),
.col_rdy_wr (col_rdy_wr),
.rts_col (rts_col),
.wr_this_rank_r (wr_this_rank_r[RANKS-1:0]),
.rd_this_rank_r (rd_this_rank_r[RANKS-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.bm_end (bm_end),
.pass_open_bank_r (pass_open_bank_r),
.sending_row (sending_row),
.sending_pre (sending_pre),
.rcv_open_bank (rcv_open_bank),
.sending_col (sending_col),
.rd_wr_r (rd_wr_r),
.req_wr_r (req_wr_r),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.req_data_buf_addr_r (req_data_buf_addr_r[DATA_BUF_ADDR_WIDTH-1:0]),
.phy_rddata_valid (phy_rddata_valid),
.rd_rmw (rd_rmw),
.ras_timer_ns_in (ras_timer_ns_in[(2*(RAS_TIMER_WIDTH*nBANK_MACHS))-1:0]),
.rb_hit_busies_r (rb_hit_busies_r[(nBANK_MACHS*2)-1:0]),
.idle_r (idle_r),
.passing_open_bank (passing_open_bank),
.low_idle_cnt_r (low_idle_cnt_r),
.op_exit_grant (op_exit_grant),
.tail_r (tail_r),
.auto_pre_r (auto_pre_r),
.pass_open_bank_ns (pass_open_bank_ns),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_data_full (phy_mc_data_full),
.rnk_config (rnk_config[RANK_WIDTH-1:0]),
.rnk_config_strobe (rnk_config_strobe),
.rnk_config_kill_rts_col (rnk_config_kill_rts_col),
.rnk_config_valid_r (rnk_config_valid_r),
.rtc (rtc),
.req_rank_r (req_rank_r[RANK_WIDTH-1:0]),
.req_rank_r_in (req_rank_r_in[(RANK_WIDTH*nBANK_MACHS*2)-1:0]),
.start_rcd_in (start_rcd_in[(nBANK_MACHS*2)-1:0]),
.inhbt_act_faw_r (inhbt_act_faw_r[RANKS-1:0]),
.wait_for_maint_r (wait_for_maint_r),
.head_r (head_r),
.sent_row (sent_row),
.demand_act_priority_in (demand_act_priority_in[(nBANK_MACHS*2)-1:0]),
.order_q_zero (order_q_zero),
.sent_col (sent_col),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.req_priority_r (req_priority_r),
.idle_ns (idle_ns),
.demand_priority_in (demand_priority_in[(nBANK_MACHS*2)-1:0]),
.inhbt_rd (inhbt_rd[RANKS-1:0]),
.inhbt_wr (inhbt_wr[RANKS-1:0]),
.dq_busy_data (dq_busy_data));
mig_7series_v4_0_bank_queue #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.ORDERING (ORDERING),
.ID (ID))
bank_queue0
(/*AUTOINST*/
// Outputs
.head_r (head_r),
.tail_r (tail_r),
.idle_ns (idle_ns),
.idle_r (idle_r),
.pass_open_bank_ns (pass_open_bank_ns),
.pass_open_bank_r (pass_open_bank_r),
.auto_pre_r (auto_pre_r),
.bm_end (bm_end),
.passing_open_bank (passing_open_bank),
.ordered_issued (ordered_issued),
.ordered_r (ordered_r),
.order_q_zero (order_q_zero),
.rcv_open_bank (rcv_open_bank),
.rb_hit_busies_r (rb_hit_busies_r[nBANK_MACHS*2-1:0]),
.q_has_rd (q_has_rd),
.q_has_priority (q_has_priority),
.wait_for_maint_r (wait_for_maint_r),
// Inputs
.clk (clk),
.rst (rst),
.accept_internal_r (accept_internal_r),
.use_addr (use_addr),
.periodic_rd_ack_r (periodic_rd_ack_r),
.bm_end_in (bm_end_in[(nBANK_MACHS*2)-1:0]),
.idle_cnt (idle_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_cnt (rb_hit_busy_cnt[BM_CNT_WIDTH-1:0]),
.accept_req (accept_req),
.rb_hit_busy_r (rb_hit_busy_r),
.maint_idle (maint_idle),
.maint_hit (maint_hit),
.row_hit_r (row_hit_r),
.pre_wait_r (pre_wait_r),
.allow_auto_pre (allow_auto_pre),
.sending_col (sending_col),
.req_wr_r (req_wr_r),
.rd_wr_r (rd_wr_r),
.bank_wait_in_progress (bank_wait_in_progress),
.precharge_bm_end (precharge_bm_end),
.adv_order_q (adv_order_q),
.order_cnt (order_cnt[BM_CNT_WIDTH-1:0]),
.rb_hit_busy_ns_in (rb_hit_busy_ns_in[(nBANK_MACHS*2)-1:0]),
.passing_open_bank_in (passing_open_bank_in[(nBANK_MACHS*2)-1:0]),
.was_wr (was_wr),
.maint_req_r (maint_req_r),
.was_priority (was_priority));
endmodule // bank_cntrl
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:34:23 02/11/2015
// Design Name: aes_sbox
// Project Name: crypto_aes
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: aes_sbox
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module aes_sbox_tb;
// Inputs
reg [7:0] U;
reg dec;
// Outputs
wire [7:0] S;
reg [8:0] i;
reg [8 * 256 - 1:0] test_data;
wire [7:0] test_val;
// Instantiate the Unit Under Test (UUT)
aes_sbox uut (
.U(U),
.dec(dec),
.S(S)
);
initial begin
// Initialize Inputs
U = 0;
dec = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
test_data = {
8'h63, 8'h7c, 8'h77, 8'h7b, 8'hf2, 8'h6b, 8'h6f, 8'hc5,
8'h30, 8'h01, 8'h67, 8'h2b, 8'hfe, 8'hd7, 8'hab, 8'h76,
8'hca, 8'h82, 8'hc9, 8'h7d, 8'hfa, 8'h59, 8'h47, 8'hf0,
8'had, 8'hd4, 8'ha2, 8'haf, 8'h9c, 8'ha4, 8'h72, 8'hc0,
8'hb7, 8'hfd, 8'h93, 8'h26, 8'h36, 8'h3f, 8'hf7, 8'hcc,
8'h34, 8'ha5, 8'he5, 8'hf1, 8'h71, 8'hd8, 8'h31, 8'h15,
8'h04, 8'hc7, 8'h23, 8'hc3, 8'h18, 8'h96, 8'h05, 8'h9a,
8'h07, 8'h12, 8'h80, 8'he2, 8'heb, 8'h27, 8'hb2, 8'h75,
8'h09, 8'h83, 8'h2c, 8'h1a, 8'h1b, 8'h6e, 8'h5a, 8'ha0,
8'h52, 8'h3b, 8'hd6, 8'hb3, 8'h29, 8'he3, 8'h2f, 8'h84,
8'h53, 8'hd1, 8'h00, 8'hed, 8'h20, 8'hfc, 8'hb1, 8'h5b,
8'h6a, 8'hcb, 8'hbe, 8'h39, 8'h4a, 8'h4c, 8'h58, 8'hcf,
8'hd0, 8'hef, 8'haa, 8'hfb, 8'h43, 8'h4d, 8'h33, 8'h85,
8'h45, 8'hf9, 8'h02, 8'h7f, 8'h50, 8'h3c, 8'h9f, 8'ha8,
8'h51, 8'ha3, 8'h40, 8'h8f, 8'h92, 8'h9d, 8'h38, 8'hf5,
8'hbc, 8'hb6, 8'hda, 8'h21, 8'h10, 8'hff, 8'hf3, 8'hd2,
8'hcd, 8'h0c, 8'h13, 8'hec, 8'h5f, 8'h97, 8'h44, 8'h17,
8'hc4, 8'ha7, 8'h7e, 8'h3d, 8'h64, 8'h5d, 8'h19, 8'h73,
8'h60, 8'h81, 8'h4f, 8'hdc, 8'h22, 8'h2a, 8'h90, 8'h88,
8'h46, 8'hee, 8'hb8, 8'h14, 8'hde, 8'h5e, 8'h0b, 8'hdb,
8'he0, 8'h32, 8'h3a, 8'h0a, 8'h49, 8'h06, 8'h24, 8'h5c,
8'hc2, 8'hd3, 8'hac, 8'h62, 8'h91, 8'h95, 8'he4, 8'h79,
8'he7, 8'hc8, 8'h37, 8'h6d, 8'h8d, 8'hd5, 8'h4e, 8'ha9,
8'h6c, 8'h56, 8'hf4, 8'hea, 8'h65, 8'h7a, 8'hae, 8'h08,
8'hba, 8'h78, 8'h25, 8'h2e, 8'h1c, 8'ha6, 8'hb4, 8'hc6,
8'he8, 8'hdd, 8'h74, 8'h1f, 8'h4b, 8'hbd, 8'h8b, 8'h8a,
8'h70, 8'h3e, 8'hb5, 8'h66, 8'h48, 8'h03, 8'hf6, 8'h0e,
8'h61, 8'h35, 8'h57, 8'hb9, 8'h86, 8'hc1, 8'h1d, 8'h9e,
8'he1, 8'hf8, 8'h98, 8'h11, 8'h69, 8'hd9, 8'h8e, 8'h94,
8'h9b, 8'h1e, 8'h87, 8'he9, 8'hce, 8'h55, 8'h28, 8'hdf,
8'h8c, 8'ha1, 8'h89, 8'h0d, 8'hbf, 8'he6, 8'h42, 8'h68,
8'h41, 8'h99, 8'h2d, 8'h0f, 8'hb0, 8'h54, 8'hbb, 8'h16
};
#1;
for(i = 0; i < 256; i = i + 1)
begin
U = i[7:0];
dec = 0;
#1;
if(test_val != S)
begin
$display("AES sbox forward mismatch at %d", i);
$stop;
end
U = S;
dec = 1;
#1;
if(S != i[7:0])
begin
$display("AES sbox reverse mismatch at %d", i);
$stop;
end
test_data = test_data << 8;
end
$display("AES sbox pass");
$finish;
end
assign test_val = test_data[8 * 256 - 1:8 * 256 - 8];
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %ALTECC%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altecc_encoder
// ============================================================
// File Name: alt_mem_ddrx_ecc_encoder_64.v
// Megafunction Name(s):
// altecc_encoder
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altecc_encoder device_family="Stratix III" lpm_pipeline=0 width_codeword=72 width_dataword=64 data q
//VERSION_BEGIN 10.0SP1 cbx_altecc_encoder 2010:08:18:21:16:35:SJ cbx_mgl 2010:08:18:21:20:44:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
) /* synthesis synthesis_clearbox=1 */;
input clk;
input reset_n;
input [63:0] data;
output [71:0] q;
wire [63:0] data_wire;
wire [34:0] parity_01_wire;
wire [17:0] parity_02_wire;
wire [8:0] parity_03_wire;
wire [3:0] parity_04_wire;
wire [1:0] parity_05_wire;
wire [30:0] parity_06_wire;
wire [6:0] parity_07_wire;
wire [70:0] parity_final;
wire [70:0] parity_final_wire;
reg [70:0] parity_final_reg;
wire [70:0] q_wire;
reg [70:0] q_reg;
assign
data_wire = data,
parity_01_wire = {
(data_wire[63] ^ parity_01_wire[33]),
(data_wire[61] ^ parity_01_wire[32]),
(data_wire[59] ^ parity_01_wire[31]),
(data_wire[57] ^ parity_01_wire[30]),
(data_wire[56] ^ parity_01_wire[29]),
(data_wire[54] ^ parity_01_wire[28]),
(data_wire[52] ^ parity_01_wire[27]),
(data_wire[50] ^ parity_01_wire[26]),
(data_wire[48] ^ parity_01_wire[25]),
(data_wire[46] ^ parity_01_wire[24]),
(data_wire[44] ^ parity_01_wire[23]),
(data_wire[42] ^ parity_01_wire[22]),
(data_wire[40] ^ parity_01_wire[21]),
(data_wire[38] ^ parity_01_wire[20]),
(data_wire[36] ^ parity_01_wire[19]),
(data_wire[34] ^ parity_01_wire[18]),
(data_wire[32] ^ parity_01_wire[17]),
(data_wire[30] ^ parity_01_wire[16]),
(data_wire[28] ^ parity_01_wire[15]),
(data_wire[26] ^ parity_01_wire[14]),
(data_wire[25] ^ parity_01_wire[13]),
(data_wire[23] ^ parity_01_wire[12]),
(data_wire[21] ^ parity_01_wire[11]),
(data_wire[19] ^ parity_01_wire[10]),
(data_wire[17] ^ parity_01_wire[9]),
(data_wire[15] ^ parity_01_wire[8]),
(data_wire[13] ^ parity_01_wire[7]),
(data_wire[11] ^ parity_01_wire[6]),
(data_wire[10] ^ parity_01_wire[5]),
(data_wire[8] ^ parity_01_wire[4]),
(data_wire[6] ^ parity_01_wire[3]),
(data_wire[4] ^ parity_01_wire[2]),
(data_wire[3] ^ parity_01_wire[1]),
(data_wire[1] ^ parity_01_wire[0]),
data_wire[0]
},
parity_02_wire = {
((data_wire[62] ^ data_wire[63]) ^ parity_02_wire[16]),
((data_wire[58] ^ data_wire[59]) ^ parity_02_wire[15]),
((data_wire[55] ^ data_wire[56]) ^ parity_02_wire[14]),
((data_wire[51] ^ data_wire[52]) ^ parity_02_wire[13]),
((data_wire[47] ^ data_wire[48]) ^ parity_02_wire[12]),
((data_wire[43] ^ data_wire[44]) ^ parity_02_wire[11]),
((data_wire[39] ^ data_wire[40]) ^ parity_02_wire[10]),
((data_wire[35] ^ data_wire[36]) ^ parity_02_wire[9]),
((data_wire[31] ^ data_wire[32]) ^ parity_02_wire[8]),
((data_wire[27] ^ data_wire[28]) ^ parity_02_wire[7]),
((data_wire[24] ^ data_wire[25]) ^ parity_02_wire[6]),
((data_wire[20] ^ data_wire[21]) ^ parity_02_wire[5]),
((data_wire[16] ^ data_wire[17]) ^ parity_02_wire[4]),
((data_wire[12] ^ data_wire[13]) ^ parity_02_wire[3]),
((data_wire[9] ^ data_wire[10]) ^ parity_02_wire[2]),
((data_wire[5] ^ data_wire[6]) ^ parity_02_wire[1]),
((data_wire[2] ^ data_wire[3]) ^ parity_02_wire[0]),
data_wire[0]
},
parity_03_wire = {
((((data_wire[60] ^ data_wire[61]) ^ data_wire[62]) ^ data_wire[63]) ^ parity_03_wire[7]),
((((data_wire[53] ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_03_wire[6]),
((((data_wire[45] ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ parity_03_wire[5]),
((((data_wire[37] ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_03_wire[4]),
((((data_wire[29] ^ data_wire[30]) ^ data_wire[31]) ^ data_wire[32]) ^ parity_03_wire[3]),
((((data_wire[22] ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_03_wire[2]),
((((data_wire[14] ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ parity_03_wire[1]),
((((data_wire[7] ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10]) ^ parity_03_wire[0]),
((data_wire[1] ^ data_wire[2]) ^ data_wire[3])
},
parity_04_wire = {
((((((((data_wire[49] ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_04_wire[2]),
((((((((data_wire[33] ^ data_wire[34]) ^ data_wire[35]) ^ data_wire[36]) ^ data_wire[37]) ^ data_wire[38]) ^ data_wire[39]) ^ data_wire[40]) ^ parity_04_wire[1]),
((((((((data_wire[18] ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25]) ^ parity_04_wire[0]),
((((((data_wire[4] ^ data_wire[5]) ^ data_wire[6]) ^ data_wire[7]) ^ data_wire[8]) ^ data_wire[9]) ^ data_wire[10])
},
parity_05_wire = {
((((((((((((((((data_wire[41] ^ data_wire[42]) ^ data_wire[43]) ^ data_wire[44]) ^ data_wire[45]) ^ data_wire[46]) ^ data_wire[47]) ^ data_wire[48]) ^ data_wire[49]) ^ data_wire[50]) ^ data_wire[51]) ^ data_wire[52]) ^ data_wire[53]) ^ data_wire[54]) ^ data_wire[55]) ^ data_wire[56]) ^ parity_05_wire[0]),
((((((((((((((data_wire[11] ^ data_wire[12]) ^ data_wire[13]) ^ data_wire[14]) ^ data_wire[15]) ^ data_wire[16]) ^ data_wire[17]) ^ data_wire[18]) ^ data_wire[19]) ^ data_wire[20]) ^ data_wire[21]) ^ data_wire[22]) ^ data_wire[23]) ^ data_wire[24]) ^ data_wire[25])
},
parity_06_wire = {
(data_wire[56] ^ parity_06_wire[29]),
(data_wire[55] ^ parity_06_wire[28]),
(data_wire[54] ^ parity_06_wire[27]),
(data_wire[53] ^ parity_06_wire[26]),
(data_wire[52] ^ parity_06_wire[25]),
(data_wire[51] ^ parity_06_wire[24]),
(data_wire[50] ^ parity_06_wire[23]),
(data_wire[49] ^ parity_06_wire[22]),
(data_wire[48] ^ parity_06_wire[21]),
(data_wire[47] ^ parity_06_wire[20]),
(data_wire[46] ^ parity_06_wire[19]),
(data_wire[45] ^ parity_06_wire[18]),
(data_wire[44] ^ parity_06_wire[17]),
(data_wire[43] ^ parity_06_wire[16]),
(data_wire[42] ^ parity_06_wire[15]),
(data_wire[41] ^ parity_06_wire[14]),
(data_wire[40] ^ parity_06_wire[13]),
(data_wire[39] ^ parity_06_wire[12]),
(data_wire[38] ^ parity_06_wire[11]),
(data_wire[37] ^ parity_06_wire[10]),
(data_wire[36] ^ parity_06_wire[9]),
(data_wire[35] ^ parity_06_wire[8]),
(data_wire[34] ^ parity_06_wire[7]),
(data_wire[33] ^ parity_06_wire[6]),
(data_wire[32] ^ parity_06_wire[5]),
(data_wire[31] ^ parity_06_wire[4]),
(data_wire[30] ^ parity_06_wire[3]),
(data_wire[29] ^ parity_06_wire[2]),
(data_wire[28] ^ parity_06_wire[1]),
(data_wire[27] ^ parity_06_wire[0]),
data_wire[26]
},
parity_07_wire = {
(data_wire[63] ^ parity_07_wire[5]),
(data_wire[62] ^ parity_07_wire[4]),
(data_wire[61] ^ parity_07_wire[3]),
(data_wire[60] ^ parity_07_wire[2]),
(data_wire[59] ^ parity_07_wire[1]),
(data_wire[58] ^ parity_07_wire[0]),
data_wire[57]
},
parity_final_wire = {
(q_wire[70] ^ parity_final_wire[69]),
(q_wire[69] ^ parity_final_wire[68]),
(q_wire[68] ^ parity_final_wire[67]),
(q_wire[67] ^ parity_final_wire[66]),
(q_wire[66] ^ parity_final_wire[65]),
(q_wire[65] ^ parity_final_wire[64]),
(q_wire[64] ^ parity_final_wire[63]),
(q_wire[63] ^ parity_final_wire[62]),
(q_wire[62] ^ parity_final_wire[61]),
(q_wire[61] ^ parity_final_wire[60]),
(q_wire[60] ^ parity_final_wire[59]),
(q_wire[59] ^ parity_final_wire[58]),
(q_wire[58] ^ parity_final_wire[57]),
(q_wire[57] ^ parity_final_wire[56]),
(q_wire[56] ^ parity_final_wire[55]),
(q_wire[55] ^ parity_final_wire[54]),
(q_wire[54] ^ parity_final_wire[53]),
(q_wire[53] ^ parity_final_wire[52]),
(q_wire[52] ^ parity_final_wire[51]),
(q_wire[51] ^ parity_final_wire[50]),
(q_wire[50] ^ parity_final_wire[49]),
(q_wire[49] ^ parity_final_wire[48]),
(q_wire[48] ^ parity_final_wire[47]),
(q_wire[47] ^ parity_final_wire[46]),
(q_wire[46] ^ parity_final_wire[45]),
(q_wire[45] ^ parity_final_wire[44]),
(q_wire[44] ^ parity_final_wire[43]),
(q_wire[43] ^ parity_final_wire[42]),
(q_wire[42] ^ parity_final_wire[41]),
(q_wire[41] ^ parity_final_wire[40]),
(q_wire[40] ^ parity_final_wire[39]),
(q_wire[39] ^ parity_final_wire[38]),
(q_wire[38] ^ parity_final_wire[37]),
(q_wire[37] ^ parity_final_wire[36]),
(q_wire[36] ^ parity_final_wire[35]),
(q_wire[35] ^ parity_final_wire[34]),
(q_wire[34] ^ parity_final_wire[33]),
(q_wire[33] ^ parity_final_wire[32]),
(q_wire[32] ^ parity_final_wire[31]),
(q_wire[31] ^ parity_final_wire[30]),
(q_wire[30] ^ parity_final_wire[29]),
(q_wire[29] ^ parity_final_wire[28]),
(q_wire[28] ^ parity_final_wire[27]),
(q_wire[27] ^ parity_final_wire[26]),
(q_wire[26] ^ parity_final_wire[25]),
(q_wire[25] ^ parity_final_wire[24]),
(q_wire[24] ^ parity_final_wire[23]),
(q_wire[23] ^ parity_final_wire[22]),
(q_wire[22] ^ parity_final_wire[21]),
(q_wire[21] ^ parity_final_wire[20]),
(q_wire[20] ^ parity_final_wire[19]),
(q_wire[19] ^ parity_final_wire[18]),
(q_wire[18] ^ parity_final_wire[17]),
(q_wire[17] ^ parity_final_wire[16]),
(q_wire[16] ^ parity_final_wire[15]),
(q_wire[15] ^ parity_final_wire[14]),
(q_wire[14] ^ parity_final_wire[13]),
(q_wire[13] ^ parity_final_wire[12]),
(q_wire[12] ^ parity_final_wire[11]),
(q_wire[11] ^ parity_final_wire[10]),
(q_wire[10] ^ parity_final_wire[9]),
(q_wire[9] ^ parity_final_wire[8]),
(q_wire[8] ^ parity_final_wire[7]),
(q_wire[7] ^ parity_final_wire[6]),
(q_wire[6] ^ parity_final_wire[5]),
(q_wire[5] ^ parity_final_wire[4]),
(q_wire[4] ^ parity_final_wire[3]),
(q_wire[3] ^ parity_final_wire[2]),
(q_wire[2] ^ parity_final_wire[1]),
(q_wire[1] ^ parity_final_wire[0]),
q_wire[0]
},
parity_final = {
(q_reg[70] ^ parity_final[69]),
(q_reg[69] ^ parity_final[68]),
(q_reg[68] ^ parity_final[67]),
(q_reg[67] ^ parity_final[66]),
(q_reg[66] ^ parity_final[65]),
(q_reg[65] ^ parity_final[64]),
parity_final_reg [64 : 0]
},
q = {parity_final[70], q_reg},
q_wire = {parity_07_wire[6], parity_06_wire[30], parity_05_wire[1], parity_04_wire[3], parity_03_wire[8], parity_02_wire[17], parity_01_wire[34], data_wire};
generate
if (CFG_ECC_ENC_REG)
begin
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
q_reg <= 0;
parity_final_reg <= 0;
end
else
begin
q_reg <= q_wire;
parity_final_reg <= parity_final_wire;
end
end
end
else
begin
always @ (*)
begin
q_reg = q_wire;
parity_final_reg = parity_final_wire;
end
end
endgenerate
endmodule //alt_mem_ddrx_ecc_encoder_64_altecc_encoder
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_mem_ddrx_ecc_encoder_64 #
( parameter
CFG_ECC_ENC_REG = 0
)
(
clk,
reset_n,
data,
q
)/* synthesis synthesis_clearbox = 1 */;
input clk;
input reset_n;
input [63:0] data;
output [71:0] q;
wire [71:0] sub_wire0;
wire [71:0] q = sub_wire0[71:0];
alt_mem_ddrx_ecc_encoder_64_altecc_encoder #
(
.CFG_ECC_ENC_REG (CFG_ECC_ENC_REG)
)
alt_mem_ddrx_ecc_encoder_64_altecc_encoder_component
(
.clk (clk),
.reset_n (reset_n),
.data (data),
.q (sub_wire0)
);
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: lpm_pipeline NUMERIC "0"
// Retrieval info: CONSTANT: width_codeword NUMERIC "72"
// Retrieval info: CONSTANT: width_dataword NUMERIC "64"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: q 0 0 72 0 OUTPUT NODEFVAL "q[71..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: q 0 0 72 0 @q 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_32_syn.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_mem_ddrx_ecc_encoder_64_syn.v TRUE
|
module queue_param_1r_1w(
in_wr_en,
in_wr_addr,
in_wr_data,
in_rd_addr,
out_rd_data,
clk,
rst
);
parameter BITS = 2;
parameter SIZE = 4;
parameter WIDTH = 32;
input in_wr_en;
input [BITS - 1:0] in_wr_addr;
input [WIDTH - 1:0] in_wr_data;
input [BITS - 1:0] in_rd_addr;
output [WIDTH - 1:0] out_rd_data;
input clk;
input rst;
wire [(SIZE * WIDTH) - 1:0] word_out;
wire [SIZE - 1:0] wr_word_select;
wire [SIZE - 1:0] wr_en_word;
mux_param #(.BITS(BITS), .SIZE(SIZE), .WIDTH(WIDTH)) mux_rd_port (.out(out_rd_data), .in(word_out), .select(in_rd_addr));
decoder_param #(.BITS(BITS), .SIZE(SIZE)) decoder_wr_port (.out(wr_word_select), .in(in_wr_addr));
assign wr_en_word = {SIZE{in_wr_en}} & wr_word_select;
reg_param #(.WIDTH(WIDTH)) word[SIZE - 1:0] (.out(word_out), .in(in_wr_data), .wr_en(wr_en_word), .clk(clk), .rst(rst));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Todd Strader.
function integer get_baz(input integer bar);
get_baz = bar;
$fatal(2, "boom");
endfunction
module foo #(parameter BAR = 0);
localparam integer BAZ = get_baz(BAR);
endmodule
module foo2 #(parameter QUX = 0);
genvar x;
generate
for (x = 0; x < 2; x++) begin: foo2_loop
foo #(.BAR (QUX + x)) foo_in_foo2_inst();
end
endgenerate
endmodule
module t;
genvar i, j;
generate
for (i = 0; i < 2; i++) begin: genloop
foo #(.BAR (i)) foo_inst();
end
for (i = 2; i < 4; i++) begin: gen_l1
for (j = 0; j < 2; j++) begin: gen_l2
foo #(.BAR (i + j*2)) foo_inst2();
end
end
if (1 == 1) begin: cond_true
foo #(.BAR (6)) foo_inst3();
end
if (1 == 1) begin // unnamed
foo #(.BAR (7)) foo_inst4();
end
for (i = 8; i < 12; i = i + 2) begin: nested_loop
foo2 #(.QUX (i)) foo2_inst();
end
endgenerate
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "clk_gen.v"
//BASIL includes
`include "utils/bus_to_ip.v"
`include "gpio/gpio.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "sram_fifo/sram_fifo_core.v"
`include "sram_fifo/sram_fifo.v"
`include "fei4_rx/fei4_rx_core.v"
`include "fei4_rx/receiver_logic.v"
`include "fei4_rx/sync_master.v"
`include "fei4_rx/rec_sync.v"
`include "fei4_rx/decode_8b10b.v"
`include "fei4_rx/fei4_rx.v"
`include "utils/flag_domain_crossing.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/CG_MOD_pos.v"
`include "utils/clock_divider.v"
`include "utils/fx2_to_bus.v"
`include "utils/reset_gen.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "tdc_s3/tdc_s3.v"
`include "tdc_s3/tdc_s3_core.v"
`include "utils/3_stage_synchronizer.v"
`include "rrp_arbiter/rrp_arbiter.v"
`include "utils/ddr_des.v"
`ifdef COCOTB_SIM //for simulation
`include "utils/IDDR_sim.v"
`include "utils/ODDR_sim.v"
`include "utils/BUFG_sim.v"
`include "utils/DCM_sim.v"
`include "utils/clock_multiplier.v"
`include "utils/RAMB16_S1_S9_sim.v"
`else
`include "utils/IDDR_s3.v"
`include "utils/ODDR_s3.v"
`endif
module fe65p2_mio (
input wire FCLK_IN, // 48MHz
//full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
//high speed
inout wire [7:0] FDATA,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
//SRAM
output wire [19:0] SRAM_A,
inout wire [15:0] SRAM_IO,
output wire SRAM_BHE_B,
output wire SRAM_BLE_B,
output wire SRAM_CE1_B,
output wire SRAM_OE_B,
output wire SRAM_WE_B,
input wire [2:0] LEMO_RX,
output wire [2:0] LEMO_TX,
inout wire SDA,
inout wire SCL,
output wire [4:0] LED,
output wire [1:0] DUT_RESET,
output wire DUT_CLK_BX,
output wire DUT_TRIGGER,
output wire DUT_INJ,
output wire DUT_CLK_CNFG,
output wire DUT_EN_PIX_SR_CNFG,
output wire DUT_LD_CNFG,
output wire DUT_SI_CNFG,
input wire DUT_SO_CNFG,
input wire DUT_HIT_OR,
output wire DUT_PIX_D_CONF,
output wire DUT_CLK_DATA,
input wire DUT_OUT_DATA
);
// MODULE ADREESSES //
localparam GPIO_BASEADDR = 16'h0000;
localparam GPIO_HIGHADDR = 16'h1000-1;
localparam SPI_BASEADDR = 16'h1000; //0x1000
localparam SPI_HIGHADDR = 16'h2000-1; //0x300f
localparam FAST_SR_AQ_BASEADDR = 16'h2000;
localparam FAST_SR_AQ_HIGHADDR = 16'h3000-1;
localparam PULSE_TRIGGER_BASEADDR = 16'h3000;
localparam PULSE_TRIGGER_HIGHADDR = 16'h4000-1;
localparam PULSE_INJ_BASEADDR = 16'h4000;
localparam PULSE_INJ_HIGHADDR = 16'h5000-1;
localparam PULSE_TESTHIT_BASEADDR = 16'h5000;
localparam PULSE_TESTHIT_HIGHADDR = 16'h6000-1;
localparam FERX_BASEADDR = 16'h6000;
localparam FERX_HIGHADDR = 16'h7000-1;
localparam FIFO_BASEADDR = 16'h8000;
localparam FIFO_HIGHADDR = 16'h9000-1;
localparam TDC_BASEADDR = 16'h9000;
localparam TDC_HIGHADDR = 16'ha000-1;
// ------- RESRT/CLOCK ------- //
(* KEEP = "{TRUE}" *)
wire CLK320;
(* KEEP = "{TRUE}" *)
wire CLK160;
(* KEEP = "{TRUE}" *)
wire CLK40;
(* KEEP = "{TRUE}" *)
wire CLK16;
(* KEEP = "{TRUE}" *)
wire BUS_CLK;
(* KEEP = "{TRUE}" *)
wire CLK8;
(* KEEP = "{TRUE}" *)
wire CLK1;
clock_divider #(
.DIVISOR(8)
) i_clock_divisor_1MHz (
.CLK(CLK8),
.RESET(1'b0),
.CE(),
.CLOCK(CLK1)
);
wire CLK_LOCKED;
clk_gen iclk_gen(
.CLKIN(FCLK_IN),
.BUS_CLK(BUS_CLK),
.U1_CLK8(CLK8),
.U2_CLK40(CLK40),
.U2_CLK16(CLK16),
.U2_CLK160(CLK160),
.U2_CLK320(CLK320),
.U2_LOCKED(CLK_LOCKED)
);
wire BUS_RST;
reset_gen ireset_gen(.CLK(BUS_CLK), .RST(BUS_RST));
// ------- BUS SYGNALING ------- //
wire [15:0] BUS_ADD;
wire BUS_RD, BUS_WR;
fx2_to_bus i_fx2_to_bus (
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.BUS_CLK(BUS_CLK),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
// ------- MODULES ------- //
wire [7:0] GPIO_OUT;
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(GPIO_OUT)
);
wire DISABLE_LD, LD;
assign #1000 DUT_RESET = GPIO_OUT[1:0];
ODDR clk_bx_gate(.D1(GPIO_OUT[2]), .D2(1'b0), .C(CLK40), .CE(1'b1), .R(1'b0), .S(1'b0), .Q(DUT_CLK_BX) );
ODDR clk_out_gate(.D1(GPIO_OUT[6]), .D2(1'b0), .C(CLK160), .CE(1'b1), .R(1'b0), .S(1'b0), .Q(DUT_CLK_DATA) );
// ODDR clk_data_gate(.D1(1'b1), .D2(1'b0), .C(CLK160), .CE(1'b1), .R(1'b0), .S(1'b0), .Q(LEMO_TX[0]) );
// ODDR clk_pollo_gate(.D1(1'b1), .D2(1'b0), .C(CLK40), .CE(1'b1), .R(1'b0), .S(1'b0), .Q(LEMO_TX[1]) );
// ODDR clk_cane_gate(.D1(1'b1), .D2(1'b0), .C(CLK8), .CE(1'b1), .R(1'b0), .S(1'b0), .Q(LEMO_TX[2]) );
assign DUT_PIX_D_CONF = GPIO_OUT[3];
wire GATE_EN_PIX_SR_CNFG;
assign GATE_EN_PIX_SR_CNFG = GPIO_OUT[4];
assign DISABLE_LD = GPIO_OUT[5];
assign LD = GPIO_OUT[7];
wire SCLK, SDI, SDO, SEN, SLD;
spi
#(
.BASEADDR(SPI_BASEADDR),
.HIGHADDR(SPI_HIGHADDR),
.MEM_BYTES(512)
) i_spi
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(CLK8),
.SCLK(SCLK),
.SDI(SDI),
.SDO(SDO),
.SEN(SEN),
.SLD(SLD)
);
reg [2:0] delay_cnt;
always@(posedge CLK1)
if(BUS_RST)
delay_cnt <= 0;
else if(SEN)
delay_cnt <= 3'b111;
else if(delay_cnt != 0)
delay_cnt <= delay_cnt - 1;
wire TESTHIT;
assign SDO = DUT_SO_CNFG;
assign DUT_SI_CNFG = SDI;
assign DUT_CLK_CNFG = SCLK; //~
assign DUT_EN_PIX_SR_CNFG = /*(SEN| (|delay_cnt) ) &*/ GATE_EN_PIX_SR_CNFG;
assign DUT_LD_CNFG = (SLD & !DISABLE_LD) | TESTHIT | LD;
pulse_gen
#(
.BASEADDR(PULSE_INJ_BASEADDR),
.HIGHADDR(PULSE_INJ_HIGHADDR)
) i_pulse_gen_inj
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(~CLK40),
.EXT_START(SLD),
.PULSE(DUT_INJ) //DUT_INJ
);
pulse_gen
#(
.BASEADDR(PULSE_TESTHIT_BASEADDR),
.HIGHADDR(PULSE_TESTHIT_HIGHADDR)
) i_pulse_gen_testhit
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(~CLK40),
.EXT_START(SLD),
.PULSE(TESTHIT)
);
pulse_gen
#(
.BASEADDR(PULSE_TRIGGER_BASEADDR),
.HIGHADDR(PULSE_TRIGGER_HIGHADDR)
) i_pulse_gen_trigger
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(~CLK40),
.EXT_START(TESTHIT | DUT_INJ),
.PULSE(DUT_TRIGGER)
);
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
wire FE_FIFO_READ;
wire FE_FIFO_EMPTY;
wire [31:0] FE_FIFO_DATA;
wire TDC_FIFO_READ;
wire TDC_FIFO_EMPTY;
wire [31:0] TDC_FIFO_DATA;
rrp_arbiter
#(
.WIDTH(2)
) i_rrp_arbiter
(
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ({~FE_FIFO_EMPTY, ~TDC_FIFO_EMPTY}),
.HOLD_REQ({2'b0}),
.DATA_IN({FE_FIFO_DATA, TDC_FIFO_DATA}),
.READ_GRANT({FE_FIFO_READ, TDC_FIFO_READ}),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
wire RX_READY, RX_8B10B_DECODER_ERR, RX_FIFO_OVERFLOW_ERR, RX_FIFO_FULL;
fei4_rx #(
.BASEADDR(FERX_BASEADDR),
.HIGHADDR(FERX_HIGHADDR),
.DSIZE(10),
.DATA_IDENTIFIER(0)
) i_fei4_rx (
.RX_CLK(CLK160), //CLK160
.RX_CLK2X(CLK320), //CLK320
.DATA_CLK(CLK16), //CLK16
.RX_DATA(DUT_OUT_DATA),
.RX_READY(RX_READY),
.RX_8B10B_DECODER_ERR(RX_8B10B_DECODER_ERR),
.RX_FIFO_OVERFLOW_ERR(RX_FIFO_OVERFLOW_ERR),
.FIFO_READ(FE_FIFO_READ),
.FIFO_EMPTY(FE_FIFO_EMPTY),
.FIFO_DATA(FE_FIFO_DATA),
.RX_FIFO_FULL(RX_FIFO_FULL),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR)
);
tdc_s3 #(
.BASEADDR(TDC_BASEADDR),
.HIGHADDR(TDC_HIGHADDR),
.CLKDV(4),
.DATA_IDENTIFIER(4'b0100),
.FAST_TDC(1),
.FAST_TRIGGER(1)
) i_tdc (
.CLK320(CLK320),
.CLK160(CLK160),
.DV_CLK(CLK40),
.TDC_IN(DUT_HIT_OR),
.TDC_OUT(LEMO_TX[0]),
.TRIG_IN(LEMO_RX[0]),
.TRIG_OUT(),
.FIFO_READ(TDC_FIFO_READ),
.FIFO_EMPTY(TDC_FIFO_EMPTY),
.FIFO_DATA(TDC_FIFO_DATA),
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.ARM_TDC(1'b0),
.EXT_EN(1'b0),
.TIMESTAMP(16'b0)
);
assign LEMO_TX[1] = DUT_INJ;
assign LEMO_TX[2] = 1'b0;
// assign TDC_FIFO_EMPTY = 1;
wire USB_READ;
assign USB_READ = FREAD & FSTROBE;
wire FIFO_FULL;
sram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.USB_READ(USB_READ),
.USB_DATA(FDATA),
.FIFO_READ_NEXT_OUT(ARB_READY_OUT),
.FIFO_EMPTY_IN(!ARB_WRITE_OUT),
.FIFO_DATA(ARB_DATA_OUT),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(FIFO_FULL),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
assign SDA = 1'bz;
assign SCL = 1'bz;
wire CLK_3HZ;
clock_divider #(
.DIVISOR(13333333)
) i_clock_divisor_40MHz_to_3Hz (
.CLK(CLK40),
.RESET(1'b0),
.CE(),
.CLOCK(CLK_3HZ)
);
wire CLK_1HZ;
clock_divider #(
.DIVISOR(40000000)
) i_clock_divisor_40MHz_to_1Hz (
.CLK(CLK40),
.RESET(1'b0),
.CE(),
.CLOCK(CLK_1HZ)
);
assign LED[2:0] = 3'b000;
assign LED[3] = RX_READY & ((RX_8B10B_DECODER_ERR? CLK_3HZ : CLK_1HZ) | RX_FIFO_OVERFLOW_ERR | RX_FIFO_FULL);
assign LED[4] = (CLK_1HZ | FIFO_FULL) & CLK_LOCKED;
/*
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(CLK80),
.TRIG0({DUT_HIT_OR, DUT_SO_CNFG , DUT_OUT_DATA}) //
);
*/
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
//-----------------------------------------------------
// Design Name : hw3_t
// File Name : hw3_t.v
// Function : This program will test datapath.v
// Coder : hydai
//-----------------------------------------------------
`timescale 1 ns/1 ps
`define TESTSIZE 44
`define STRINGIFY(x) `"x`"
`define PATTERN pattern1.dat
`define GOLDEN golden1.dat
`define SNAPSHOT dump1.dat
`define CLOCK_CYCLE 10
`define HALF_CYCLE 5
module hw3_t ;
reg [57:0] test_vector [`TESTSIZE-1:0];
reg [291:0] test_response [`TESTSIZE-1:0];
reg [25:0] control;
reg [15:0] constant;
reg [15:0] data;
reg clk, rst_n;
reg V, C, N, Z;
wire [15:0] R0;
wire [15:0] R1;
wire [15:0] R2;
wire [15:0] R3;
wire [15:0] R4;
wire [15:0] R5;
wire [15:0] R6;
wire [15:0] R7;
wire [15:0] R8;
wire [15:0] R9;
wire [15:0] R10;
wire [15:0] R11;
wire [15:0] R12;
wire [15:0] R13;
wire [15:0] R14;
wire [15:0] R15;
wire [15:0] BUSA;
wire [15:0] BUSB;
reg [291:0] snapshot;
integer error, snapshotPT, descPT, i;
reg cmp;
datapath golden(
V, C, N, Z,
R0, R1, R2, R3, R4, R5, R6, R7,
R8, R9, R10, R11, R12, R13, R14, R15,
BUSA, BUSB,
control,
constant,
data,
clk,
rst_n
);
initial begin
`ifdef NETLIST
$sdf_annotate("datapath_syn.sdf", golden);
$fsdbDumpfile("datapath_syn.fsdb");
`else
$fsdbDumpfile("datapath.fsdb");
`endif
$fsdbDumpvars;
end
always begin
#`CLOCK_CYCLE clk = ~clk;
end
task simulation;
input [57:0] instr;
begin
#(`HALF_CYCLE) assign {control, constant, data} = instr;
#(`HALF_CYCLE)
#(`CLOCK_CYCLE)
$display("");
end
endtask
initial begin
$fsdbDumpfile("hw3_t.fsdb");
$fsdbDumpvars;
end
initial begin
#0 clk = 0; rst_n = 0; constant = 0; control = 0; data = 0;
#20 rst_n = 1;
$readmemb(`STRINGIFY(`PATTERN), test_vector);
$readmemb(`STRINGIFY(`GOLDEN), test_response);
snapshotPT = $fopen(`STRINGIFY(`SNAPSHOT));
$display("File dump handle in %h", snapshotPT);
error = 0;
for (i = 0; i < `TESTSIZE; i++) begin
simulation(test_vector[i]);
descPT = snapshotPT;
assign snapshot = {V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB};
$fdisplay(descPT, "%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b_%b", V, C, N, Z, R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, BUSA, BUSB);
cmp = (snapshot == test_response[i])?1:0;
if (cmp == 0) begin
$display("Error in line %d", i);
error++;
end
end
#10
if (error == 0) begin
$display("PASS");
end else begin
$display("NOT PASS");
end
$fclose(snapshotPT);
$finish;
end
endmodule // End of Module hw3_t
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_incr_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_incr_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
reg [11:0] axaddr_incr;
reg [8:0] axlen_cnt;
reg next_pending_r;
wire [3:0] axsize_shift;
wire [11:0] axsize_mask;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// calculate cmd_byte_addr
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_incr[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_incr[11:0];
end
endgenerate
assign axsize_shift = (1 << axsize[1:0]);
assign axsize_mask = ~(axsize_shift - 1'b1);
// Incremented version of axaddr
always @(posedge clk) begin
if (sel_first) begin
if(~next) begin
axaddr_incr <= axaddr[11:0] & axsize_mask;
end else begin
axaddr_incr <= (axaddr[11:0] & axsize_mask) + axsize_shift;
end
end else if (next) begin
axaddr_incr <= axaddr_incr + axsize_shift;
end
end
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen;
next_pending_r <= (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= ((axlen_cnt - 1) >= 1);
end else begin
axlen_cnt <= 9'd0;
next_pending_r <= 1'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = (axlen >= 1);
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = ((axlen_cnt - 1) >= 1);
end else begin
next_pending = 1'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
endmodule
`default_nettype wire
|
/*
* Wishbone Compatible RS232 core
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module serial (
// Wishbone slave interface
input wb_clk_i, // Clock Input
input wb_rst_i, // Reset Input
input [15:0] wb_dat_i, // Command to send to mouse
output [15:0] wb_dat_o, // Received data
input wb_cyc_i, // Cycle
input wb_stb_i, // Strobe
input [ 1:0] wb_adr_i, // Wishbone address lines
input [ 1:0] wb_sel_i, // Wishbone Select lines
input wb_we_i, // Write enable
output reg wb_ack_o, // Normal bus termination
output wb_tgc_o, // Interrupt request
output rs232_tx, // RS232 output
input rs232_rx // RS232 input
);
// --------------------------------------------------------------------
// This section is a simple WB interface
// --------------------------------------------------------------------
reg [7:0] dat_o;
wire [7:0] dat_i;
wire [2:0] UART_Addr;
wire wb_ack_i;
wire wr_command;
wire rd_command;
// Unused output
wire rxd_endofpacket;
// --------------------------------------------------------------------
// Wires for Interrupt Enable Register (IER)
// --------------------------------------------------------------------
wire EDAI;
wire ETXH;
//wire ERLS = ier[2]; // Enable Receive Line Status Interrupt
wire EMSI;
wire [7:0] INTE;
// --------------------------------------------------------------------
// Wires for Interrupt Identification Register (IIR)
// --------------------------------------------------------------------
reg IPEN; // 0 if intereupt pending
reg IPEND; // Interupt pending
reg [1:0] INTID; // Interrupt ID Bits
wire [7:0] ISTAT;
// --------------------------------------------------------------------
// Wires for Line Status Register (LSR)
// --------------------------------------------------------------------
wire TSRE;
wire PE;
wire BI;
wire FE;
wire OR;
reg rx_rden; // Receive data enable
reg DR; // Data Ready
reg THRE; // Transmitter Holding Register Empty
wire [7:0] LSTAT;
// --------------------------------------------------------------------
// Wires for Modem Control Register (MCR)
// --------------------------------------------------------------------
wire DTR;
wire RTS;
wire OUT1;
wire OUT2;
wire LOOP;
wire [7:0] MCON;
// --------------------------------------------------------------------
// Wires for Modem Status Register (MSR)
// --------------------------------------------------------------------
wire RLSD;
wire RI;
wire DSR;
wire CTS;
wire DRLSD;
wire TERI;
wire DDSR;
wire DCTS;
wire [7:0] MSTAT;
// --------------------------------------------------------------------
// Wires for Line Control Register (LCRR)
// --------------------------------------------------------------------
wire [7:0] LCON;
wire dlab;
// --------------------------------------------------------------------
// 8250A Registers
// --------------------------------------------------------------------
wire [7:0] output_data; // Wired to receiver
reg [7:0] input_data; // Transmit register
reg [3:0] ier; // Interrupt enable register
reg [7:0] lcr; // Line Control register
reg [7:0] mcr; // Modem Control register
reg [7:0] dll; // Data latch register low
reg [7:0] dlh; // Data latch register high
// --------------------------------------------------------------------
// Instantiate the UART
// --------------------------------------------------------------------
//reg rx_read; // Signal to read next byte in the buffer
wire rx_drdy; // Indicates new data has come in
wire rx_idle; // Indicates Receiver is idle
wire rx_over; // Indicates buffer over run error
reg tx_send; // Signal to send data
wire to_error; // Indicates a transmit error occured
wire tx_done;
wire tx_busy; // Signal transmitter is busy
// --------------------------------------------------------------------
// Baud Clock Generator
// --------------------------------------------------------------------
wire [18:0] Baudiv;
wire Baud1Tick;
wire Baud8Tick;
reg [18:0] BaudAcc1;
reg [15:0] BaudAcc8;
wire [18:0] BaudInc;
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if (wb_rst_i) wb_ack_o <= 1'b0;
else wb_ack_o <= wb_ack_i & ~wb_ack_o; // one clock delay on acknowledge output
end
// --------------------------------------------------------------------
// This section is a simple 8250 Emulator that front ends the UART
// --------------------------------------------------------------------
// --------------------------------------------------------------------
// Register addresses and defaults
// --------------------------------------------------------------------
`define UART_RG_TR 3'h0 // RW - Transmit / Receive register
`define UART_RG_IE 3'h1 // RW - Interrupt enable
`define UART_RG_II 3'h2 // R - Interrupt identification (no fifo on 8250)
`define UART_RG_LC 3'h3 // RW - Line Control
`define UART_RG_MC 3'h4 // W - Modem control
`define UART_RG_LS 3'h5 // R - Line status
`define UART_RG_MS 3'h6 // R - Modem status
`define UART_RG_SR 3'h7 // RW - Scratch register
`define UART_DL_LSB 8'h60 // Divisor latch least significant byte, hard coded to 9600 baud
`define UART_DL_MSB 8'h00 // Divisor latch most significant byte
`define UART_IE_DEF 8'h00 // Interupt Enable default
`define UART_LC_DEF 8'h03 // Line Control default
`define UART_MC_DEF 8'h00 // Line Control default
// --------------------------------------------------------------------
// UART Interrupt Behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
IPEN <= 1'b1; // Interupt Enable default
IPEND <= 1'b0; // Interupt pending
INTID <= 2'b00; // Interupt ID
end
else begin
if(DR & EDAI) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b10; // Set Interupt ID
end
if(THRE & ETXH) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b01; // Set Interupt ID
end
if((CTS | DSR | RI |RLSD) && EMSI) begin // If enabled
IPEN <= 1'b0; // Set latch (inverted)
IPEND <= 1'b1; // Indicates an Interupt is pending
INTID <= 2'b00; // Interupt ID
end
if(rd_command) // If a read was requested
case(UART_Addr) // Determine which register was read
`UART_RG_TR: IPEN <= 1'b1; // Resets interupt flag
`UART_RG_II: IPEN <= 1'b1; // Resets interupt flag
`UART_RG_MS: IPEN <= 1'b1; // Resets interupt flag
default: ; // Do nothing if anything else
endcase // End of case
if(wr_command) // If a write was requested
case(UART_Addr) // Determine which register was writen to
`UART_RG_TR: IPEN <= 1'b1; // Resets interupt flag;
default: ; // Do nothing if anything else
endcase // End of case
if(IPEN & IPEND) begin
INTID <= 2'b00; // user has cleared the Interupt
IPEND <= 1'b0; // Interupt pending
end
end
end // Synchrounous always
// --------------------------------------------------------------------
// UART Line Status Behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
// rx_read <= 1'b0; // Singal to get the data out of the buffer
rx_rden <= 1'b1; // Singal to get the data out of the buffer
DR <= 1'b0; // Indicates data is waiting to be read
THRE <= 1'b0; // Transmitter holding register is empty
end
else begin
if(rx_drdy) begin // If enabled
DR <= 1'b1; // Indicates data is waiting to be read
if(rx_rden) /*rx_read <= 1'b1*/; // If reading enabled, request another byte
else begin // of data out of the buffer, else..
//rx_read <= 1'b0; // on next clock, do not request anymore
rx_rden <= 1'b0; // block your fifo from reading
end // until ready
end
if(tx_done) begin // If enabled
THRE <= 1'b1; // Transmitter holding register is empty
end
if(IPEN && IPEND) begin // If the user has cleared the and there is not one pending
rx_rden <= 1'b1; // User has digested that byte, now enable reading some more
DR <= 1'b0; // interrupt, then clear
THRE <= 1'b0; // the flags in the Line status register
end
end
end
// --------------------------------------------------------------------
// UART Register behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
dat_o <= 8'h00; // Default value
end
else
if(rd_command) begin
case(UART_Addr) // Determine which register was read
`UART_RG_TR: dat_o <= dlab ? dll : output_data;
`UART_RG_IE: dat_o <= dlab ? dlh : INTE;
`UART_RG_II: dat_o <= ISTAT; // Interupt ID
`UART_RG_LC: dat_o <= LCON; // Line control
`UART_RG_MC: dat_o <= MCON; // Modem Control Register
`UART_RG_LS: dat_o <= LSTAT; // Line status
`UART_RG_MS: dat_o <= MSTAT; // Modem Status
`UART_RG_SR: dat_o <= 8'h00; // No Scratch register
default: dat_o <= 8'h00; // Default
endcase // End of case
end
end // Synchrounous always
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) begin
dll <= `UART_DL_LSB; // Set default to 9600 baud
dlh <= `UART_DL_MSB; // Set default to 9600 baud
ier <= 4'h01; // Interupt Enable default
lcr <= 8'h03; // Default value
mcr <= 8'h00; // Default value
end
else if(wr_command) begin // If a write was requested
case(UART_Addr) // Determine which register was writen to
`UART_RG_TR: if(dlab) dll <= dat_i; else input_data <= dat_i;
`UART_RG_IE: if(dlab) dlh <= dat_i; else ier <= dat_i[3:0];
`UART_RG_II: ; // Read only register
`UART_RG_LC: lcr <= dat_i; // Line Control
`UART_RG_MC: mcr <= dat_i; // Modem Control Register
`UART_RG_LS: ; // Read only register
`UART_RG_MS: ; // Read only register
`UART_RG_SR: ; // No scratch register
default: ; // Default
endcase // End of case
end
end // Synchrounous always
// --------------------------------------------------------------------
// Transmit behavior
// --------------------------------------------------------------------
always @(posedge wb_clk_i or posedge wb_rst_i) begin // Synchrounous
if(wb_rst_i) tx_send <= 1'b0; // Default value
else tx_send <= (wr_command && (UART_Addr == `UART_RG_TR) && !dlab);
end // Synchrounous always
serial_arx arx (
.clk (wb_clk_i),
.baud8tick (Baud8Tick),
.rxd (rs232_rx),
.rxd_data_ready (rx_drdy),
.rxd_data (output_data),
.rxd_endofpacket (rxd_endofpacket),
.rxd_idle (rx_idle)
);
serial_atx atx (
.clk (wb_clk_i),
.baud1tick (Baud1Tick),
.txd (rs232_tx),
.txd_start (tx_send),
.txd_data (input_data),
.txd_busy (tx_busy)
);
// --------------------------------------------------------------------
// 1.8432Mhz Baud Clock Generator:
// This module generates the standard 1.8432Mhz Baud Clock. Using this clock
// The Baud Rate Generator below can then derive all the standard
// Bauds. Make the accumulator 1 more bit for carry out than what is
// Needed. Example: Main Clock = 12.5Mhz = 12,500,000 Hence
// 1024/151 = 6.78, => 12,500,000 / 6.78 = 1,843,261.72 , .003% error, Good !
// so the accumulator should be 11 bits (log2(1024) +1
//
// --------------------------------------------------------------------
// Baud Rate Generator:
// Once we have our little 1.8432Mhz Baud Clock, deriving the bauds is
// simple simon. Just divide by 16 to get the 1x baud for transmitting
// and divide by 2 to get the 8x oversampling clock for receiving.
//
// Baud Clock = 1.8432Mhz
// Divisor = 16
//
// Baud Divsr %Error
// ------ ----- -----
// 50 2304 0.000%
// 75 1536 0.000%
// 110 1047 0.026%
// 150 768 0.000%
// 300 384 0.000%
// 600 192 0.000%
// 1200 96 0.000%
// 2400 48 0.000%
// 4800 24 0.000%
// 7200 16 0.000%
// 9600 12 0.000%
// 14400 8 0.000%
// 19200 6 0.000%
// 28800 4 0.000%
// 38400 3 0.000%
// 57600 2 0.000%
// 115200 1 0.000%
//
// --------------------------------------------------------------------
always @(posedge wb_clk_i)
BaudAcc1 <= {1'b0, BaudAcc1[17:0]} + BaudInc;
always @(posedge wb_clk_i)
BaudAcc8 <= {1'b0, BaudAcc8[14:0]} + BaudInc[15:0];
// Combinatorial logic
assign dat_i = wb_sel_i[0] ? wb_dat_i[7:0] : wb_dat_i[15:8]; // 8 to 16 bit WB
assign wb_dat_o = wb_sel_i[0] ? {8'h00, dat_o} : {dat_o, 8'h00}; // 8 to 16 bit WB
assign UART_Addr = {wb_adr_i, wb_sel_i[1]}; // Computer UART Address
assign wb_ack_i = wb_stb_i & wb_cyc_i; // Immediate ack
assign wr_command = wb_ack_i & wb_we_i; // WISHBONE write access, Singal to send
assign rd_command = wb_ack_i & ~wb_we_i; // WISHBONE write access, Singal to send
assign wb_tgc_o = ~IPEN; // If ==0 - new data has been received
assign EDAI = ier[0]; // Enable Data Available Interrupt
assign ETXH = ier[1]; // Enable Tx Holding Register Empty Interrupt
assign EMSI = ier[3]; // Enable Modem Status Interrupt
assign INTE = {4'b0000, ier};
assign ISTAT = { 5'b0000_0,INTID,IPEN};
assign TSRE = tx_done; // Tx Shift Register Empty
assign PE = 1'b0; // Parity Error
assign BI = 1'b0; // Break Interrupt, hard coded off
assign FE = to_error; // Framing Error, hard coded off
assign OR = rx_over; // Overrun Error, hard coded off
assign LSTAT = {1'b0,TSRE,THRE,BI,FE,PE,OR,DR};
assign DTR = mcr[0];
assign RTS = mcr[1];
assign OUT1 = mcr[2];
assign OUT2 = mcr[3];
assign LOOP = mcr[4];
assign MCON = {3'b000, mcr[4:0]};
assign RLSD = LOOP ? OUT2 : 1'b0; // Received Line Signal Detect
assign RI = LOOP ? OUT1 : 1'b1; // Ring Indicator
assign DSR = LOOP ? DTR : 1'b0; // Data Set Ready
assign CTS = LOOP ? RTS : 1'b0; // Clear To Send
assign DRLSD = 1'b0; // Delta Rx Line Signal Detect
assign TERI = 1'b0; // Trailing Edge Ring Indicator
assign DDSR = 1'b0; // Delta Data Set Ready
assign DCTS = 1'b0; // Delta Clear to Send
assign MSTAT = {RLSD,RI,DSR,CTS,DCTS,DDSR,TERI,DRLSD};
assign LCON = lcr; // Data Latch Address Bit
assign dlab = lcr[7]; // Data Latch Address Bit
assign tx_done = ~tx_busy; // Signal command finished sending
assign rx_over = 1'b0;
assign to_error = 1'b0;
assign Baudiv = {3'b000,dlh,dll};
assign Baud1Tick = BaudAcc1[18];
assign BaudInc = 19'd2416/Baudiv;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: syncff.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A back to back FF design to mitigate metastable issues
// when crossing clock domains.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module syncff
(
input CLK,
input IN_ASYNC,
output OUT_SYNC
);
wire wSyncFFQ;
ff
syncFF
(
.CLK(CLK),
.D(IN_ASYNC),
.Q(wSyncFFQ)
);
ff metaFF (
.CLK(CLK),
.D(wSyncFFQ),
.Q(OUT_SYNC)
);
endmodule
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
// Test array variables inside a constant function
module constfunc14();
function [7:0] concat1(input [7:0] value);
reg [3:0] tmp[1:2];
begin
{tmp[1], tmp[2]} = {value[3:0], value[7:4]};
{concat1[3:0], concat1[7:4]} = {tmp[2], tmp[1]};
end
endfunction
function [7:0] concat2(input [7:0] value);
reg [3:0] tmp[1:2];
begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{tmp[1], tmp[3]} = {value[3:0], value[7:4]};
{concat2[3:0], concat2[7:4]} = {tmp[3], tmp[1]};
`else
{tmp[1]} = {value[3:0]};
{concat2[3:0], concat2[7:4]} = {4'bxxxx, tmp[1]};
`endif
end
endfunction
function [7:0] concat3(input [7:0] value);
reg [3:0] tmp[1:2];
begin
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
{tmp['bx], tmp[1]} = {value[3:0], value[7:4]};
{concat3[3:0], concat3[7:4]} = {tmp['bx], tmp[1]};
`else
{tmp[1]} = {value[7:4]};
{concat3[3:0], concat3[7:4]} = {4'bxxxx, tmp[1]};
`endif
end
endfunction
localparam res1 = concat1(8'ha5);
localparam res2 = concat2(8'ha5);
localparam res3 = concat2(8'ha5);
reg failed = 0;
initial begin
$display("%h", res1); if (res1 !== 8'h5a) failed = 1;
$display("%h", res2); if (res2 !== 8'h5x) failed = 1;
$display("%h", res3); if (res3 !== 8'h5x) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
module dummy;
parameter [TSTBITS-1:0] // synopsys enum tstate_info
TIDLE = 3'b000,
TCN1 = 3'b001,
TCN2 = TCN1+1, // must be numbered consecutively
TCN3 = TCN2+1,
TCN4 = TCN3+1,
TCN5 = TCN4+1,
IOCLR = TCN5+1,
TUNU1 = 3'b111;
// state and output logic
always @ (`ifdef SIMFSM
ireset or
`endif
/*AUTOSENSE*/fooc2_qual or foocr_we or ioclrinst or tstate) begin
ioclrtmout = 1'b0;
case (tstate)
TIDLE: begin
if (foocr_we)
ntstate = TCN1;
else
ntstate = TIDLE;
end
TCN1,TCN2,TCN3,TCN4,TCN5: begin
if (ioclrinst | fooc2_qual)
ntstate = TIDLE;
else
ntstate = tstate + 1;
end
IOCLR: begin
ntstate = TIDLE;
ioclrtmout = 1'b1;
end
TUNU1: begin
ntstate = TIDLE;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unused state at %t",$time);
`endif
end
default: begin
ntstate = 'bx;
ioclrtmout = 1'bx;
`ifdef SIMFSM
if (~ireset)
$display("ERROR: entered unknown state at %t",$time);
`endif
end
endcase // case(tstate)
end // always @ (...
endmodule // dummy
|
module sgpr(
lsu_source1_addr,
lsu_source2_addr,
lsu_dest_addr,
lsu_dest_data,
lsu_dest_wr_en,
lsu_instr_done_wfid,
lsu_instr_done,
lsu_source1_rd_en,
lsu_source2_rd_en,
simd0_rd_addr,
simd0_rd_en,
simd1_rd_addr,
simd1_rd_en,
simd2_rd_addr,
simd2_rd_en,
simd3_rd_addr,
simd3_rd_en,
simd0_wr_addr,
simd0_wr_en,
simd0_wr_data,
simd1_wr_addr,
simd1_wr_en,
simd1_wr_data,
simd2_wr_addr,
simd2_wr_en,
simd2_wr_data,
simd3_wr_addr,
simd3_wr_en,
simd3_wr_data,
simd0_wr_mask,
simd1_wr_mask,
simd2_wr_mask,
simd3_wr_mask,
simf0_rd_addr,
simf0_rd_en,
simf1_rd_addr,
simf1_rd_en,
simf2_rd_addr,
simf2_rd_en,
simf3_rd_addr,
simf3_rd_en,
simf0_wr_addr,
simf0_wr_en,
simf0_wr_data,
simf1_wr_addr,
simf1_wr_en,
simf1_wr_data,
simf2_wr_addr,
simf2_wr_en,
simf2_wr_data,
simf3_wr_addr,
simf3_wr_en,
simf3_wr_data,
simf0_wr_mask,
simf1_wr_mask,
simf2_wr_mask,
simf3_wr_mask,
salu_dest_data,
salu_dest_addr,
salu_dest_wr_en,
salu_source2_addr,
salu_source1_addr,
salu_instr_done_wfid,
salu_instr_done,
salu_source1_rd_en,
salu_source2_rd_en,
rfa_select_fu,
lsu_source1_data,
lsu_source2_data,
simd_rd_data,
simf_rd_data,
salu_source2_data,
salu_source1_data,
issue_alu_wr_done_wfid,
issue_alu_wr_done,
issue_alu_dest_reg_addr,
issue_alu_dest_reg_valid,
issue_lsu_instr_done_wfid,
issue_lsu_instr_done,
issue_lsu_dest_reg_addr,
issue_lsu_dest_reg_valid,
issue_valu_dest_reg_valid,
issue_valu_dest_addr,
clk,
`ifdef FPGA
clk_double,
`endif
rst
);
input clk;
`ifdef FPGA
input clk_double;
`endif
input rst;
input salu_source1_rd_en,
salu_source2_rd_en,
lsu_source1_rd_en,
lsu_source2_rd_en;
input lsu_instr_done, simd0_rd_en, simd1_rd_en, simd2_rd_en,
simd3_rd_en, simd0_wr_en, simd1_wr_en, simd2_wr_en, simd3_wr_en, simf0_rd_en,
simf1_rd_en, simf2_rd_en, simf3_rd_en, simf0_wr_en, simf1_wr_en, simf2_wr_en,
simf3_wr_en, salu_instr_done;
input [1:0] salu_dest_wr_en;
input [3:0] lsu_dest_wr_en;
input [5:0] lsu_instr_done_wfid, salu_instr_done_wfid;
input [8:0] lsu_source1_addr, lsu_source2_addr, lsu_dest_addr, simd0_rd_addr,
simd1_rd_addr, simd2_rd_addr, simd3_rd_addr, simd0_wr_addr, simd1_wr_addr,
simd2_wr_addr, simd3_wr_addr, simf0_rd_addr, simf1_rd_addr, simf2_rd_addr,
simf3_rd_addr, simf0_wr_addr, simf1_wr_addr, simf2_wr_addr, simf3_wr_addr,
salu_dest_addr, salu_source2_addr, salu_source1_addr;
input [15:0] rfa_select_fu;
input [127:0] lsu_dest_data;
input [63:0] simd0_wr_data, simd1_wr_data, simd2_wr_data, simd3_wr_data,
simf0_wr_data, simf1_wr_data, simf2_wr_data, simf3_wr_data,
salu_dest_data,
simd0_wr_mask, simd1_wr_mask, simd2_wr_mask, simd3_wr_mask,
simf0_wr_mask, simf1_wr_mask, simf2_wr_mask, simf3_wr_mask;
output issue_alu_wr_done, issue_lsu_instr_done, issue_valu_dest_reg_valid;
output [3:0] issue_lsu_dest_reg_valid;
output [1:0] issue_alu_dest_reg_valid;
output [5:0] issue_alu_wr_done_wfid, issue_lsu_instr_done_wfid;
output [8:0] issue_alu_dest_reg_addr, issue_lsu_dest_reg_addr, issue_valu_dest_addr;
output [31:0] lsu_source2_data, simd_rd_data, simf_rd_data;
output [63:0] salu_source2_data, salu_source1_data;
output [127:0] lsu_source1_data;
///////////////////////////////
//Your code goes here - beware: script does not recognize changes
// into files. It ovewrites everithing without mercy. Save your work before running the script
///////////////////////////////
wire dummy;
assign dummy = rst;
wire [31:0] simx_rd_data;
wire [8:0] simx_muxed_rd_addr;
wire [31:0] simx_muxed_rd_data;
wire simx_muxed_rd_en;
wire [3:0] simxlsu_muxed_wr_en;
wire [8:0] simxlsu_muxed_wr_addr;
wire [127:0] simxlsu_muxed_wr_data;
wire [63:0] simx_rd_old_data;
wire [127:0] simxlsu_wr_merged_data;
wire [127:0] simxlsu_muxed_wr_mask;
wire [3:0] simxlsu_muxed_wr_en_i;
wire [8:0] simxlsu_muxed_wr_addr_i;
wire [127:0] simxlsu_muxed_wr_data_i;
wire [127:0] simxlsu_muxed_wr_mask_i;
wire [8:0] final_port0_addr;
wire [8:0] final_port1_addr;
wire [127:0] final_port0_data;
wire [63:0] final_port1_data;
wire [127:0] port0_distribute_data;
wire [127:0] port1_distribute_data;
wire [127:0] simd0_wr_data_i, simd1_wr_data_i, simd2_wr_data_i, simd3_wr_data_i,
simf0_wr_data_i, simf1_wr_data_i, simf2_wr_data_i, simf3_wr_data_i;
wire [127:0] simd0_wr_mask_i, simd1_wr_mask_i, simd2_wr_mask_i, simd3_wr_mask_i,
simf0_wr_mask_i, simf1_wr_mask_i, simf2_wr_mask_i, simf3_wr_mask_i;
wire [3:0] simd0_wr_en_i, simd1_wr_en_i, simd2_wr_en_i, simd3_wr_en_i,
simf0_wr_en_i, simf1_wr_en_i, simf2_wr_en_i, simf3_wr_en_i;
assign simd0_wr_data_i = {simd0_wr_data, simd0_wr_data};
assign simd1_wr_data_i = {simd1_wr_data, simd1_wr_data};
assign simd2_wr_data_i = {simd2_wr_data, simd2_wr_data};
assign simd3_wr_data_i = {simd3_wr_data, simd3_wr_data};
assign simf0_wr_data_i = {simf0_wr_data, simf0_wr_data};
assign simf1_wr_data_i = {simf1_wr_data, simf1_wr_data};
assign simf2_wr_data_i = {simf2_wr_data, simf2_wr_data};
assign simf3_wr_data_i = {simf3_wr_data, simf3_wr_data};
assign simd0_wr_mask_i = {simd0_wr_mask, simd0_wr_mask};
assign simd1_wr_mask_i = {simd1_wr_mask, simd1_wr_mask};
assign simd2_wr_mask_i = {simd2_wr_mask, simd2_wr_mask};
assign simd3_wr_mask_i = {simd3_wr_mask, simd3_wr_mask};
assign simf0_wr_mask_i = {simf0_wr_mask, simf0_wr_mask};
assign simf1_wr_mask_i = {simf1_wr_mask, simf1_wr_mask};
assign simf2_wr_mask_i = {simf2_wr_mask, simf2_wr_mask};
assign simf3_wr_mask_i = {simf3_wr_mask, simf3_wr_mask};
assign simd0_wr_en_i = {4{simd0_wr_en}} & 4'b0011;
assign simd1_wr_en_i = {4{simd1_wr_en}} & 4'b0011;
assign simd2_wr_en_i = {4{simd2_wr_en}} & 4'b0011;
assign simd3_wr_en_i = {4{simd3_wr_en}} & 4'b0011;
assign simf0_wr_en_i = {4{simf0_wr_en}} & 4'b0011;
assign simf1_wr_en_i = {4{simf1_wr_en}} & 4'b0011;
assign simf2_wr_en_i = {4{simf2_wr_en}} & 4'b0011;
assign simf3_wr_en_i = {4{simf3_wr_en}} & 4'b0011;
assign issue_alu_wr_done_wfid = salu_instr_done_wfid;
assign issue_alu_wr_done = salu_instr_done;
assign issue_alu_dest_reg_addr = salu_dest_addr;
assign issue_alu_dest_reg_valid = salu_dest_wr_en;
assign issue_lsu_instr_done_wfid = lsu_instr_done_wfid;
assign issue_lsu_instr_done = lsu_instr_done;
assign issue_lsu_dest_reg_addr = lsu_dest_addr;
assign issue_lsu_dest_reg_valid = lsu_dest_wr_en;
//For writes from simx, read the old value using a ead port and modify only
//the bits specified by the wr mask
assign simxlsu_wr_merged_data = (simxlsu_muxed_wr_data_i &
simxlsu_muxed_wr_mask_i) |
({2{simx_rd_old_data}} &
(~simxlsu_muxed_wr_mask_i));
dff wr0_delay_flop[4+9+128+128-1:0]
(.q({simxlsu_muxed_wr_en_i, simxlsu_muxed_wr_addr_i,
simxlsu_muxed_wr_data_i,simxlsu_muxed_wr_mask_i}),
.d({simxlsu_muxed_wr_en, simxlsu_muxed_wr_addr,
simxlsu_muxed_wr_data,simxlsu_muxed_wr_mask}),
.clk(clk),
.rst(rst));
reg_512x32b_3r_2w sgpr_reg_file
(
.rd0_addr(final_port0_addr),
.rd0_data(final_port0_data),
.rd1_addr(final_port1_addr),
.rd1_data(final_port1_data),
.rd2_addr(simxlsu_muxed_wr_addr),
.rd2_data(simx_rd_old_data),
.wr0_en(simxlsu_muxed_wr_en_i),
.wr0_addr(simxlsu_muxed_wr_addr_i),
.wr0_data(simxlsu_wr_merged_data),
.wr1_en(salu_dest_wr_en),
.wr1_addr(salu_dest_addr),
.wr1_data(salu_dest_data),
.clk(clk)
`ifdef FPGA
,.clk_double(clk_double)
`endif
);
sgpr_simx_rd_port_mux simx_rd_port_mux
(
.port0_rd_en(simd0_rd_en),
.port0_rd_addr(simd0_rd_addr),
.port1_rd_en(simd1_rd_en),
.port1_rd_addr(simd1_rd_addr),
.port2_rd_en(simd2_rd_en),
.port2_rd_addr(simd2_rd_addr),
.port3_rd_en(simd3_rd_en),
.port3_rd_addr(simd3_rd_addr),
.port4_rd_en(simf0_rd_en),
.port4_rd_addr(simf0_rd_addr),
.port5_rd_en(simf1_rd_en),
.port5_rd_addr(simf1_rd_addr),
.port6_rd_en(simf2_rd_en),
.port6_rd_addr(simf2_rd_addr),
.port7_rd_en(simf3_rd_en),
.port7_rd_addr(simf3_rd_addr),
.port_rd_data(simx_rd_data),
.rd_addr(simx_muxed_rd_addr),
.rd_data(simx_muxed_rd_data),
.rd_en(simx_muxed_rd_en)
);
assign simd_rd_data = simx_rd_data;
assign simf_rd_data = simx_rd_data;
sgpr_3to1_rd_port_mux rd_port0_mux
(
.port0_rd_en(lsu_source1_rd_en),
.port0_rd_addr(lsu_source1_addr),
.port1_rd_en(1'b0),
.port1_rd_addr(9'b0),
.port2_rd_en(salu_source1_rd_en),
.port2_rd_addr(salu_source1_addr),
.port_rd_data(port0_distribute_data),
.rd_addr(final_port0_addr),
.rd_data(final_port0_data)
);
assign lsu_source1_data = port0_distribute_data;
assign salu_source1_data = port0_distribute_data[63:0];
sgpr_3to1_rd_port_mux rd_port1_mux
(
.port0_rd_en(lsu_source2_rd_en),
.port0_rd_addr(lsu_source2_addr),
.port1_rd_en(simx_muxed_rd_en),
.port1_rd_addr(simx_muxed_rd_addr),
.port2_rd_en(salu_source2_rd_en),
.port2_rd_addr(salu_source2_addr),
.port_rd_data(port1_distribute_data),
.rd_addr(final_port1_addr),
.rd_data({64'b0,final_port1_data})
);
assign lsu_source2_data = port1_distribute_data[31:0];
assign simx_muxed_rd_data = port1_distribute_data[31:0];
assign salu_source2_data = port1_distribute_data[63:0];
///////////////////////////////////////////
sgpr_simxlsu_wr_port_mux simx_wr_port_mux
(
.wr_port_select(rfa_select_fu),
.port0_wr_en(simd0_wr_en_i),
.port0_wr_addr(simd0_wr_addr),
.port0_wr_data(simd0_wr_data_i),
.port0_wr_mask(simd0_wr_mask_i),
.port1_wr_en(simd1_wr_en_i),
.port1_wr_addr(simd1_wr_addr),
.port1_wr_data(simd1_wr_data_i),
.port1_wr_mask(simd1_wr_mask_i),
.port2_wr_en(simd2_wr_en_i),
.port2_wr_addr(simd2_wr_addr),
.port2_wr_data(simd2_wr_data_i),
.port2_wr_mask(simd2_wr_mask_i),
.port3_wr_en(simd3_wr_en_i),
.port3_wr_addr(simd3_wr_addr),
.port3_wr_data(simd3_wr_data_i),
.port3_wr_mask(simd3_wr_mask_i),
.port4_wr_en(simf0_wr_en_i),
.port4_wr_addr(simf0_wr_addr),
.port4_wr_data(simf0_wr_data_i),
.port4_wr_mask(simf0_wr_mask_i),
.port5_wr_en(simf1_wr_en_i),
.port5_wr_addr(simf1_wr_addr),
.port5_wr_data(simf1_wr_data_i),
.port5_wr_mask(simf1_wr_mask_i),
.port6_wr_en(simf2_wr_en_i),
.port6_wr_addr(simf2_wr_addr),
.port6_wr_data(simf2_wr_data_i),
.port6_wr_mask(simf2_wr_mask_i),
.port7_wr_en(simf3_wr_en_i),
.port7_wr_addr(simf3_wr_addr),
.port7_wr_data(simf3_wr_data_i),
.port7_wr_mask(simf3_wr_mask_i),
.port8_wr_en(lsu_dest_wr_en),
.port8_wr_addr(lsu_dest_addr),
.port8_wr_data(lsu_dest_data),
.port8_wr_mask({128{1'b1}}),
.muxed_port_wr_en(simxlsu_muxed_wr_en),
.muxed_port_wr_addr(simxlsu_muxed_wr_addr),
.muxed_port_wr_data(simxlsu_muxed_wr_data),
.muxed_port_wr_mask(simxlsu_muxed_wr_mask)
);
assign issue_valu_dest_reg_valid = (|simxlsu_muxed_wr_en) & (~|lsu_dest_wr_en);
assign issue_valu_dest_addr = simxlsu_muxed_wr_addr;
endmodule
|
// trigger_delay.v
`timescale 1 ns / 1 ps
module trigger_delay #(parameter N=3)
(
input clk,
input sync,
input reset,
input [7:0]delay,
input trg_in,
input [(N-1):0]data_in,
output reg trg_out,
output reg [(N-1):0]data_out
);
// time stamp counter
reg [7:0]t;
always @(posedge clk or posedge reset)
begin
if (reset) t <= 0;
else if (sync) t <= t + 8'd1;
end
wire empty;
wire [7:0]tq;
wire [(N-1):0]dout;
wire write = trg_in && sync;
wire hit = tq == (t - delay);
wire read = hit && sync;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
trg_out <= 0;
data_out <= 0;
end
else if (sync)
begin
if (!empty)
begin
trg_out <= hit;
data_out <= dout;
end
else
begin
trg_out <= 0;
data_out <= 0;
end
end
end
scfifo
#(
.add_ram_output_register("OFF"),
.intended_device_family("Cyclone III"),
.lpm_numwords(256),
.lpm_showahead("ON"),
.lpm_type("scfifo"),
.lpm_width(N+8),
.lpm_widthu(8),
.overflow_checking("ON"),
.underflow_checking("ON"),
.use_eab("ON")
) fifo
(
.aclr (reset),
.clock (clk),
.data ({data_in, t}),
.rdreq (read),
.wrreq (write),
.empty (empty),
.q ({dout, tq}),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ()
);
endmodule
|
// -- (c) Copyright 2011-2014 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: axi_crossbar.v
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_axi_crossbar # (
parameter C_FAMILY = "rtl",
// FPGA Base Family. Current version: virtex6 or spartan6.
parameter integer C_NUM_SLAVE_SLOTS = 1,
// Number of Slave Interface (SI) slots for connecting
// to master IP. Range: 1-16.
parameter integer C_NUM_MASTER_SLOTS = 2,
// Number of Master Interface (MI) slots for connecting
// to slave IP. Range: 1-16.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of ID signals propagated by the Interconnect.
// Width of ID signals produced on all MI slots.
// Range: 1-32.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr for all SI/MI slots.
// Range: 1-64.
parameter integer C_AXI_DATA_WIDTH = 32,
// Data width of the internal interconnect write and read
// data paths.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_PROTOCOL = 0,
// 0 = "AXI4",
// 1 = "AXI3",
// 2 = "AXI4LITE"
// Propagate WID only when C_AXI_PROTOCOL = 1.
parameter integer C_NUM_ADDR_RANGES = 1,
// Number of BASE/HIGH_ADDR pairs per MI slot.
// Range: 1-16.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] C_M_AXI_BASE_ADDR = 128'h00000000001000000000000000000000,
// Base address of each range of each MI slot.
// For unused ranges, set C_M_AXI_BASE_ADDR[mm*aa*64 +: C_AXI_ADDR_WIDTH] = {C_AXI_ADDR_WIDTH{1'b1}}.
// (Bit positions above C_AXI_ADDR_WIDTH are ignored.)
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit64}}.
parameter [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*32-1:0] C_M_AXI_ADDR_WIDTH = 64'H0000000c0000000c,
// Number of low-order address bits that are used to select locations within each address range of each MI slot.
// The High address of each range is derived as BASE_ADDR + 2**C_M_AXI_ADDR_WIDTH -1.
// For used address ranges, C_M_AXI_ADDR_WIDTH must be > 0.
// For unused ranges, set C_M_AXI_ADDR_WIDTH to 32'h00000000.
// Format: C_NUM_MASTER_SLOTS{C_NUM_ADDR_RANGES{Bit32}}.
// Range: 0 - C_AXI_ADDR_WIDTH.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_BASE_ID = 32'h00000000,
// Base ID of each SI slot.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 to 2**C_AXI_ID_WIDTH-1.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_THREAD_ID_WIDTH = 32'h00000000,
// Number of low-order ID bits a connected master may vary to select a transaction thread.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0 - C_AXI_ID_WIDTH.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
// 1 = Propagate all USER signals, 0 = Dont propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of BUSER signals for all SI slots and MI slots.
// Range: 1-1024.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway write connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_CONNECTIVITY = 64'hFFFFFFFFFFFFFFFF,
// Multi-pathway read connectivity from each SI slot (N) to each
// MI slot (M):
// 0 = no pathway required; 1 = pathway required. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
parameter integer C_R_REGISTER = 0,
// Insert register slice on R channel in the crossbar. (Valid only for SASD)
// Range: Reg-slice type (0-8).
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_SINGLE_THREAD = 32'h00000000,
// 0 = Implement separate command queues per ID thread.
// 1 = Force corresponding SI slot to be single-threaded. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0, 1
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_WRITE_ACCEPTANCE = 32'H00000002,
// Maximum number of active write transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_READ_ACCEPTANCE = 32'H00000002,
// Maximum number of active read transactions that each SI
// slot can accept. (Valid only for SAMD)
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_WRITE_ISSUING = 64'H0000000400000004,
// Maximum number of data-active write transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_READ_ISSUING = 64'H0000000400000004,
// Maximum number of active read transactions that
// each MI slot can generate at any one time. (Valid only for SAMD)
// Format: C_NUM_MASTER_SLOTS{Bit32};
// Range: 1-32.
parameter [C_NUM_SLAVE_SLOTS*32-1:0] C_S_AXI_ARB_PRIORITY = 32'h00000000,
// Arbitration priority among each SI slot.
// Higher values indicate higher priority.
// Format: C_NUM_SLAVE_SLOTS{Bit32};
// Range: 0-15.
parameter [C_NUM_MASTER_SLOTS*32-1:0] C_M_AXI_SECURE = 32'h00000000,
// Indicates whether each MI slot connects to a secure slave
// (allows only TrustZone secure access).
// Format: C_NUM_MASTER_SLOTS{Bit32}.
// Range: 0, 1
parameter integer C_CONNECTIVITY_MODE = 1
// 0 = Shared-Address Shared-Data (SASD).
// 1 = Shared-Address Multi-Data (SAMD).
// Default 1 (on) for simulation; default 0 (off) for implementation.
)
(
// Global Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_awburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_awprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_awqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wlast,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_bresp,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arsize,
input wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_arburst,
input wire [C_NUM_SLAVE_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arcache,
input wire [C_NUM_SLAVE_SLOTS*3-1:0] s_axi_arprot,
// input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arregion,
input wire [C_NUM_SLAVE_SLOTS*4-1:0] s_axi_arqos,
input wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arvalid,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [C_NUM_SLAVE_SLOTS*2-1:0] s_axi_rresp,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rlast,
output wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rvalid,
input wire [C_NUM_SLAVE_SLOTS-1:0] s_axi_rready,
// Master Interface Write Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_awburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_awprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_awqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_awready,
// Master Interface Write Data Ports
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wlast,
output wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_wready,
// Master Interface Write Response Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_bresp,
input wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_bready,
// Master Interface Read Address Port
output wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arsize,
output wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_arburst,
output wire [C_NUM_MASTER_SLOTS*((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arcache,
output wire [C_NUM_MASTER_SLOTS*3-1:0] m_axi_arprot,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arregion,
output wire [C_NUM_MASTER_SLOTS*4-1:0] m_axi_arqos,
output wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arvalid,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_arready,
// Master Interface Read Data Ports
input wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [C_NUM_MASTER_SLOTS*2-1:0] m_axi_rresp,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rlast,
input wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rvalid,
output wire [C_NUM_MASTER_SLOTS-1:0] m_axi_rready
);
localparam [64:0] P_ONES = {65{1'b1}};
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_BASE_ID = f_base_id(0);
localparam [C_NUM_SLAVE_SLOTS*64-1:0] P_S_AXI_HIGH_ID = f_high_id(0);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam [2:0] P_AXILITE_SIZE = 3'b010;
localparam [1:0] P_INCR = 2'b01;
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_WRITE = f_m_supports_write(0);
localparam [C_NUM_MASTER_SLOTS-1:0] P_M_AXI_SUPPORTS_READ = f_m_supports_read(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_WRITE = f_s_supports_write(0);
localparam [C_NUM_SLAVE_SLOTS-1:0] P_S_AXI_SUPPORTS_READ = f_s_supports_read(0);
localparam integer C_DEBUG = 1;
localparam integer P_RANGE_CHECK = 1;
// 1 (non-zero) = Detect and issue DECERR on the following conditions:
// a. address range mismatch (no valid MI slot)
// b. Burst or >32-bit transfer to AxiLite slave
// c. TrustZone access violation
// d. R/W direction unsupported by target
// 0 = Pass all transactions (no DECERR):
// a. Omit DECERR detection and response logic
// b. Omit address decoder and propagate s_axi_a*REGION to m_axi_a*REGION
// when C_NUM_MASTER_SLOTS=1 and C_NUM_ADDR_RANGES=1.
// c. Unpredictable target MI-slot if address mismatch and >1 MI-slot
// d. Transaction corruption if any burst or >32-bit transfer to AxiLite slave
// Illegal combination: P_RANGE_CHECK = 0 && C_M_AXI_SECURE != 0.
localparam integer P_ADDR_DECODE = ((P_RANGE_CHECK == 1) || (C_NUM_MASTER_SLOTS > 1) || (C_NUM_ADDR_RANGES > 1)) ? 1 : 0; // Always 1
localparam [C_NUM_MASTER_SLOTS*32-1:0] P_M_AXI_ERR_MODE = {C_NUM_MASTER_SLOTS{32'h00000000}};
// Transaction error detection (per MI-slot)
// 0 = None; 1 = AXI4Lite burst violation
// Format: C_NUM_MASTER_SLOTS{Bit32};
localparam integer P_LEN = (C_AXI_PROTOCOL == P_AXI3) ? 4 : 8;
localparam integer P_LOCK = (C_AXI_PROTOCOL == P_AXI3) ? 2 : 1;
localparam P_FAMILY = ((C_FAMILY == "virtex7") || (C_FAMILY == "kintex7") || (C_FAMILY == "artix7") || (C_FAMILY == "zynq")) ? C_FAMILY : "rtl";
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// Widths of all write issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_write_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_WRITE_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_write_issue_width_vec = result;
end
endfunction
// Widths of all read issuance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [(C_NUM_MASTER_SLOTS+1)*32-1:0] f_read_issue_width_vec
(input null_arg);
integer mi;
reg [(C_NUM_MASTER_SLOTS+1)*32-1:0] result;
begin
result = 0;
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result[mi*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_M_AXI_READ_ISSUING[mi*32+:32]);
end
result[C_NUM_MASTER_SLOTS*32+:32] = 32'h0;
f_read_issue_width_vec = result;
end
endfunction
// Widths of all write acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_write_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_WRITE_ACCEPTANCE[si*32+:32]);
end
f_write_accept_width_vec = result;
end
endfunction
// Widths of all read acceptance counters implemented in axi_crossbar_v2_1_crossbar (before counter carry-out bit)
function [C_NUM_SLAVE_SLOTS*32-1:0] f_read_accept_width_vec
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*32-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*32+:32] = (C_AXI_PROTOCOL == P_AXILITE) ? 32'h0 : f_ceil_log2(C_S_AXI_READ_ACCEPTANCE[si*32+:32]);
end
f_read_accept_width_vec = result;
end
endfunction
// Convert C_S_AXI_BASE_ID vector from Bit32 to Bit64 format
function [C_NUM_SLAVE_SLOTS*64-1:0] f_base_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH];
end
f_base_id = result;
end
endfunction
// Construct P_S_HIGH_ID vector
function [C_NUM_SLAVE_SLOTS*64-1:0] f_high_id
(input null_arg);
integer si;
reg [C_NUM_SLAVE_SLOTS*64-1:0] result;
begin
result = 0;
for (si=0; si<C_NUM_SLAVE_SLOTS; si=si+1) begin
result[si*64+:C_AXI_ID_WIDTH] = (C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
f_high_id = result;
end
endfunction
// Construct P_M_HIGH_ADDR vector
function [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] f_high_addr
(input null_arg);
integer ar;
reg [C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64-1:0] result;
begin
result = {C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES*64{1'b0}};
for (ar=0; ar<C_NUM_MASTER_SLOTS*C_NUM_ADDR_RANGES; ar=ar+1) begin
result[ar*64+:C_AXI_ADDR_WIDTH] = (C_M_AXI_ADDR_WIDTH[ar*32+:32] == 0) ? 64'h00000000_00000000 :
({1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:31]} >= C_AXI_ADDR_WIDTH) ? {C_AXI_ADDR_WIDTH{1'b1}} :
(C_M_AXI_BASE_ADDR[ar*64+:C_AXI_ADDR_WIDTH] | ~(P_ONES << {1'b0, C_M_AXI_ADDR_WIDTH[ar*32+:7]}));
end
f_high_addr = result;
end
endfunction
// Generate a mask of valid ID bits for a given SI slot.
function [C_AXI_ID_WIDTH-1:0] f_thread_id_mask
(input integer si);
begin
f_thread_id_mask =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? {C_AXI_ID_WIDTH{1'b0}} :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? {C_AXI_ID_WIDTH{1'b1}} :
({C_AXI_ID_WIDTH{1'b0}} | ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]}));
end
endfunction
// Isolate thread bits of input S_ID and add to BASE_ID to form MI-side ID value
// only for end-point SI-slots
function [C_AXI_ID_WIDTH-1:0] f_extend_ID (
input [C_AXI_ID_WIDTH-1:0] s_id,
input integer si
);
begin
f_extend_ID =
(C_S_AXI_THREAD_ID_WIDTH[si*32+:32] == 0) ? C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] :
({1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:31]} >= C_AXI_ID_WIDTH) ? s_id :
(C_S_AXI_BASE_ID[si*32+:C_AXI_ID_WIDTH] | (s_id & ~(P_ONES << {1'b0, C_S_AXI_THREAD_ID_WIDTH[si*32+:6]})));
end
endfunction
// Bit vector of SI slots with at least one write connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_write
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_write = result;
end
endfunction
// Bit vector of SI slots with at least one read connection.
function [C_NUM_SLAVE_SLOTS-1:0] f_s_supports_read
(input null_arg);
integer mi;
reg [C_NUM_SLAVE_SLOTS-1:0] result;
begin
result = {C_NUM_SLAVE_SLOTS{1'b0}};
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
result = result | C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS];
end
f_s_supports_read = result;
end
endfunction
// Bit vector of MI slots with at least one write connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_write
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_write[mi] = (|C_M_AXI_WRITE_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
// Bit vector of MI slots with at least one read connection.
function [C_NUM_MASTER_SLOTS-1:0] f_m_supports_read
(input null_arg);
integer mi;
begin
for (mi=0; mi<C_NUM_MASTER_SLOTS; mi=mi+1) begin
f_m_supports_read[mi] = (|C_M_AXI_READ_CONNECTIVITY[mi*32+:C_NUM_SLAVE_SLOTS]);
end
end
endfunction
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_awid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_awaddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_awlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_awlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_awprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_awqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH-1:0] si_cb_awuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_awready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_wid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_wdata ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH/8-1:0] si_cb_wstrb ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH-1:0] si_cb_wuser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_wready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_bid ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_bresp ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH-1:0] si_cb_buser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_bready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_arid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH-1:0] si_cb_araddr ;
wire [C_NUM_SLAVE_SLOTS*8-1:0] si_cb_arlen ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arsize ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arburst ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_arlock ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arcache ;
wire [C_NUM_SLAVE_SLOTS*3-1:0] si_cb_arprot ;
// wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arregion ;
wire [C_NUM_SLAVE_SLOTS*4-1:0] si_cb_arqos ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH-1:0] si_cb_aruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_arready ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH-1:0] si_cb_rid ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_DATA_WIDTH-1:0] si_cb_rdata ;
wire [C_NUM_SLAVE_SLOTS*2-1:0] si_cb_rresp ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rlast ;
wire [C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH-1:0] si_cb_ruser ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rvalid ;
wire [C_NUM_SLAVE_SLOTS-1:0] si_cb_rready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_awid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_awaddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_awlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_awlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_awprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_awqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH-1:0] cb_mi_awuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_awready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_wid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_wdata ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH/8-1:0] cb_mi_wstrb ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH-1:0] cb_mi_wuser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_wready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_bid ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_bresp ;
wire [C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH-1:0] cb_mi_buser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_bready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_arid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH-1:0] cb_mi_araddr ;
wire [C_NUM_MASTER_SLOTS*8-1:0] cb_mi_arlen ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arsize ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arburst ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_arlock ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arcache ;
wire [C_NUM_MASTER_SLOTS*3-1:0] cb_mi_arprot ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arregion ;
wire [C_NUM_MASTER_SLOTS*4-1:0] cb_mi_arqos ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH-1:0] cb_mi_aruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_arready ;
wire [C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH-1:0] cb_mi_rid ;
wire [C_NUM_MASTER_SLOTS*C_AXI_DATA_WIDTH-1:0] cb_mi_rdata ;
wire [C_NUM_MASTER_SLOTS*2-1:0] cb_mi_rresp ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rlast ;
wire [C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH-1:0] cb_mi_ruser ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rvalid ;
wire [C_NUM_MASTER_SLOTS-1:0] cb_mi_rready ;
genvar slot;
generate
for (slot=0;slot<C_NUM_SLAVE_SLOTS;slot=slot+1) begin : gen_si_tieoff
assign si_cb_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_awlen[slot*8+:8] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_awsize[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_awburst[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst[slot*2+:2] : P_INCR ;
assign si_cb_awlock[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_awlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_awcache[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache[slot*4+:4] : 0 ;
assign si_cb_awprot[slot*3+:3] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awprot[slot*3+:3] : 0 ;
assign si_cb_awqos[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos[slot*4+:4] : 0 ;
// assign si_cb_awregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion[slot*4+:4] : 0 ;
assign si_cb_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign si_cb_awvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_awvalid[slot*1+:1] : 0 ;
assign si_cb_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI3) ) ? (s_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign si_cb_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign si_cb_wlast[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast[slot*1+:1] : 1'b1 ;
assign si_cb_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign si_cb_wvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_wvalid[slot*1+:1] : 0 ;
assign si_cb_bready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? s_axi_bready[slot*1+:1] : 0 ;
assign si_cb_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (s_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign si_cb_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign si_cb_arlen[slot*8+:8] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arlen[slot*P_LEN+:P_LEN] : 0 ;
assign si_cb_arsize[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize[slot*3+:3] : P_AXILITE_SIZE ;
assign si_cb_arburst[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst[slot*2+:2] : P_INCR ;
assign si_cb_arlock[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? {1'b0, s_axi_arlock[slot*P_LOCK+:1]} : 0 ;
assign si_cb_arcache[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache[slot*4+:4] : 0 ;
assign si_cb_arprot[slot*3+:3] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arprot[slot*3+:3] : 0 ;
assign si_cb_arqos[slot*4+:4] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos[slot*4+:4] : 0 ;
// assign si_cb_arregion[slot*4+:4] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion[slot*4+:4] : 0 ;
assign si_cb_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign si_cb_arvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_arvalid[slot*1+:1] : 0 ;
assign si_cb_rready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? s_axi_rready[slot*1+:1] : 0 ;
assign s_axi_awready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_awready[slot*1+:1] : 0 ;
assign s_axi_wready[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_wready[slot*1+:1] : 0 ;
assign s_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_bresp[slot*2+:2] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bresp[slot*2+:2] : 0 ;
assign s_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_S_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign s_axi_bvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_WRITE[slot] ) ? si_cb_bvalid[slot*1+:1] : 0 ;
assign s_axi_arready[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_arready[slot*1+:1] : 0 ;
assign s_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? (si_cb_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] & f_thread_id_mask(slot)) : 0 ;
assign s_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign s_axi_rresp[slot*2+:2] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rresp[slot*2+:2] : 0 ;
assign s_axi_rlast[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cb_rlast[slot*1+:1] : 0 ;
assign s_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_S_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cb_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign s_axi_rvalid[slot*1+:1] = (P_S_AXI_SUPPORTS_READ[slot] ) ? si_cb_rvalid[slot*1+:1] : 0 ;
end // gen_si_tieoff
for (slot=0;slot<C_NUM_MASTER_SLOTS;slot=slot+1) begin : gen_mi_tieoff
assign m_axi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awaddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_awlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_WRITE[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_awlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_awlen[slot*8+:4] : 0 ;
assign m_axi_awsize[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awsize[slot*3+:3] : 0 ;
assign m_axi_awburst[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awburst[slot*2+:2] : 0 ;
assign m_axi_awlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awlock[slot*2+:1] : 0 ;
assign m_axi_awcache[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awcache[slot*4+:4] : 0 ;
assign m_axi_awprot[slot*3+:3] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awprot[slot*3+:3] : 0 ;
assign m_axi_awregion[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_awregion[slot*4+:4] : 0 ;
assign m_axi_awqos[slot*4+:4] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_awqos[slot*4+:4] : 0 ;
assign m_axi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_awuser[slot*C_AXI_AWUSER_WIDTH+:C_AXI_AWUSER_WIDTH] : 0 ;
assign m_axi_awvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_awvalid[slot*1+:1] : 0 ;
assign m_axi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign m_axi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wstrb[slot*C_AXI_DATA_WIDTH/8+:C_AXI_DATA_WIDTH/8] : 0 ;
assign m_axi_wlast[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_wlast[slot*1+:1] : 0 ;
assign m_axi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_wuser[slot*C_AXI_WUSER_WIDTH+:C_AXI_WUSER_WIDTH] : 0 ;
assign m_axi_wvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_wvalid[slot*1+:1] : 0 ;
assign m_axi_bready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? cb_mi_bready[slot*1+:1] : 0 ;
assign m_axi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign m_axi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_araddr[slot*C_AXI_ADDR_WIDTH+:C_AXI_ADDR_WIDTH] : 0 ;
assign m_axi_arlen[slot*P_LEN+:P_LEN] = (~P_M_AXI_SUPPORTS_READ[slot]) ? 0 : (C_AXI_PROTOCOL==P_AXI4 ) ? cb_mi_arlen[slot*8+:8] : (C_AXI_PROTOCOL==P_AXI3) ? cb_mi_arlen[slot*8+:4] : 0 ;
assign m_axi_arsize[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arsize[slot*3+:3] : 0 ;
assign m_axi_arburst[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arburst[slot*2+:2] : 0 ;
assign m_axi_arlock[slot*P_LOCK+:P_LOCK] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arlock[slot*2+:1] : 0 ;
assign m_axi_arcache[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arcache[slot*4+:4] : 0 ;
assign m_axi_arprot[slot*3+:3] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arprot[slot*3+:3] : 0 ;
assign m_axi_arregion[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL==P_AXI4) ) ? cb_mi_arregion[slot*4+:4] : 0 ;
assign m_axi_arqos[slot*4+:4] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cb_mi_arqos[slot*4+:4] : 0 ;
assign m_axi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cb_mi_aruser[slot*C_AXI_ARUSER_WIDTH+:C_AXI_ARUSER_WIDTH] : 0 ;
assign m_axi_arvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_arvalid[slot*1+:1] : 0 ;
assign m_axi_rready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? cb_mi_rready[slot*1+:1] : 0 ;
assign cb_mi_awready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_awready[slot*1+:1] : 0 ;
assign cb_mi_wready[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_wready[slot*1+:1] : 0 ;
assign cb_mi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_bresp[slot*2+:2] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bresp[slot*2+:2] : 0 ;
assign cb_mi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] = (P_M_AXI_SUPPORTS_WRITE[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser[slot*C_AXI_BUSER_WIDTH+:C_AXI_BUSER_WIDTH] : 0 ;
assign cb_mi_bvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_WRITE[slot] ) ? m_axi_bvalid[slot*1+:1] : 0 ;
assign cb_mi_arready[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_arready[slot*1+:1] : 0 ;
assign cb_mi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid[slot*C_AXI_ID_WIDTH+:C_AXI_ID_WIDTH] : 0 ;
assign cb_mi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rdata[slot*C_AXI_DATA_WIDTH+:C_AXI_DATA_WIDTH] : 0 ;
assign cb_mi_rresp[slot*2+:2] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rresp[slot*2+:2] : 0 ;
assign cb_mi_rlast[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast[slot*1+:1] : 1'b1 ;
assign cb_mi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] = (P_M_AXI_SUPPORTS_READ[slot] && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser[slot*C_AXI_RUSER_WIDTH+:C_AXI_RUSER_WIDTH] : 0 ;
assign cb_mi_rvalid[slot*1+:1] = (P_M_AXI_SUPPORTS_READ[slot] ) ? m_axi_rvalid[slot*1+:1] : 0 ;
end // gen_mi_tieoff
if ((C_CONNECTIVITY_MODE==0) || (C_AXI_PROTOCOL==P_AXILITE)) begin : gen_sasd
axi_crossbar_v2_1_crossbar_sasd #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_R_REGISTER (C_R_REGISTER),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_sasd_0
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end else begin : gen_samd
axi_crossbar_v2_1_crossbar #
(
.C_FAMILY (P_FAMILY),
.C_NUM_SLAVE_SLOTS (C_NUM_SLAVE_SLOTS),
.C_NUM_MASTER_SLOTS (C_NUM_MASTER_SLOTS),
.C_NUM_ADDR_RANGES (C_NUM_ADDR_RANGES),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_S_AXI_THREAD_ID_WIDTH (C_S_AXI_THREAD_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_M_AXI_BASE_ADDR (C_M_AXI_BASE_ADDR),
.C_M_AXI_HIGH_ADDR (f_high_addr(0)),
.C_S_AXI_BASE_ID (P_S_AXI_BASE_ID),
.C_S_AXI_HIGH_ID (P_S_AXI_HIGH_ID),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_ARUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_S_AXI_SUPPORTS_WRITE (P_S_AXI_SUPPORTS_WRITE),
.C_S_AXI_SUPPORTS_READ (P_S_AXI_SUPPORTS_READ),
.C_M_AXI_SUPPORTS_WRITE (P_M_AXI_SUPPORTS_WRITE),
.C_M_AXI_SUPPORTS_READ (P_M_AXI_SUPPORTS_READ),
.C_M_AXI_WRITE_CONNECTIVITY (C_M_AXI_WRITE_CONNECTIVITY),
.C_M_AXI_READ_CONNECTIVITY (C_M_AXI_READ_CONNECTIVITY),
.C_S_AXI_SINGLE_THREAD (C_S_AXI_SINGLE_THREAD),
.C_S_AXI_WRITE_ACCEPTANCE (C_S_AXI_WRITE_ACCEPTANCE),
.C_S_AXI_READ_ACCEPTANCE (C_S_AXI_READ_ACCEPTANCE),
.C_M_AXI_WRITE_ISSUING (C_M_AXI_WRITE_ISSUING),
.C_M_AXI_READ_ISSUING (C_M_AXI_READ_ISSUING),
.C_S_AXI_ARB_PRIORITY (C_S_AXI_ARB_PRIORITY),
.C_M_AXI_SECURE (C_M_AXI_SECURE),
.C_RANGE_CHECK (P_RANGE_CHECK),
.C_ADDR_DECODE (P_ADDR_DECODE),
.C_W_ISSUE_WIDTH (f_write_issue_width_vec(0) ),
.C_R_ISSUE_WIDTH (f_read_issue_width_vec(0) ),
.C_W_ACCEPT_WIDTH (f_write_accept_width_vec(0)),
.C_R_ACCEPT_WIDTH (f_read_accept_width_vec(0)),
.C_M_AXI_ERR_MODE (P_M_AXI_ERR_MODE),
.C_DEBUG (C_DEBUG)
)
crossbar_samd
(
.ACLK (aclk),
.ARESETN (aresetn),
.S_AXI_AWID (si_cb_awid ),
.S_AXI_AWADDR (si_cb_awaddr ),
.S_AXI_AWLEN (si_cb_awlen ),
.S_AXI_AWSIZE (si_cb_awsize ),
.S_AXI_AWBURST (si_cb_awburst ),
.S_AXI_AWLOCK (si_cb_awlock ),
.S_AXI_AWCACHE (si_cb_awcache ),
.S_AXI_AWPROT (si_cb_awprot ),
// .S_AXI_AWREGION (si_cb_awregion ),
.S_AXI_AWQOS (si_cb_awqos ),
.S_AXI_AWUSER (si_cb_awuser ),
.S_AXI_AWVALID (si_cb_awvalid ),
.S_AXI_AWREADY (si_cb_awready ),
.S_AXI_WID (si_cb_wid ),
.S_AXI_WDATA (si_cb_wdata ),
.S_AXI_WSTRB (si_cb_wstrb ),
.S_AXI_WLAST (si_cb_wlast ),
.S_AXI_WUSER (si_cb_wuser ),
.S_AXI_WVALID (si_cb_wvalid ),
.S_AXI_WREADY (si_cb_wready ),
.S_AXI_BID (si_cb_bid ),
.S_AXI_BRESP (si_cb_bresp ),
.S_AXI_BUSER (si_cb_buser ),
.S_AXI_BVALID (si_cb_bvalid ),
.S_AXI_BREADY (si_cb_bready ),
.S_AXI_ARID (si_cb_arid ),
.S_AXI_ARADDR (si_cb_araddr ),
.S_AXI_ARLEN (si_cb_arlen ),
.S_AXI_ARSIZE (si_cb_arsize ),
.S_AXI_ARBURST (si_cb_arburst ),
.S_AXI_ARLOCK (si_cb_arlock ),
.S_AXI_ARCACHE (si_cb_arcache ),
.S_AXI_ARPROT (si_cb_arprot ),
// .S_AXI_ARREGION (si_cb_arregion ),
.S_AXI_ARQOS (si_cb_arqos ),
.S_AXI_ARUSER (si_cb_aruser ),
.S_AXI_ARVALID (si_cb_arvalid ),
.S_AXI_ARREADY (si_cb_arready ),
.S_AXI_RID (si_cb_rid ),
.S_AXI_RDATA (si_cb_rdata ),
.S_AXI_RRESP (si_cb_rresp ),
.S_AXI_RLAST (si_cb_rlast ),
.S_AXI_RUSER (si_cb_ruser ),
.S_AXI_RVALID (si_cb_rvalid ),
.S_AXI_RREADY (si_cb_rready ),
.M_AXI_AWID (cb_mi_awid ),
.M_AXI_AWADDR (cb_mi_awaddr ),
.M_AXI_AWLEN (cb_mi_awlen ),
.M_AXI_AWSIZE (cb_mi_awsize ),
.M_AXI_AWBURST (cb_mi_awburst ),
.M_AXI_AWLOCK (cb_mi_awlock ),
.M_AXI_AWCACHE (cb_mi_awcache ),
.M_AXI_AWPROT (cb_mi_awprot ),
.M_AXI_AWREGION (cb_mi_awregion ),
.M_AXI_AWQOS (cb_mi_awqos ),
.M_AXI_AWUSER (cb_mi_awuser ),
.M_AXI_AWVALID (cb_mi_awvalid ),
.M_AXI_AWREADY (cb_mi_awready ),
.M_AXI_WID (cb_mi_wid ),
.M_AXI_WDATA (cb_mi_wdata ),
.M_AXI_WSTRB (cb_mi_wstrb ),
.M_AXI_WLAST (cb_mi_wlast ),
.M_AXI_WUSER (cb_mi_wuser ),
.M_AXI_WVALID (cb_mi_wvalid ),
.M_AXI_WREADY (cb_mi_wready ),
.M_AXI_BID (cb_mi_bid ),
.M_AXI_BRESP (cb_mi_bresp ),
.M_AXI_BUSER (cb_mi_buser ),
.M_AXI_BVALID (cb_mi_bvalid ),
.M_AXI_BREADY (cb_mi_bready ),
.M_AXI_ARID (cb_mi_arid ),
.M_AXI_ARADDR (cb_mi_araddr ),
.M_AXI_ARLEN (cb_mi_arlen ),
.M_AXI_ARSIZE (cb_mi_arsize ),
.M_AXI_ARBURST (cb_mi_arburst ),
.M_AXI_ARLOCK (cb_mi_arlock ),
.M_AXI_ARCACHE (cb_mi_arcache ),
.M_AXI_ARPROT (cb_mi_arprot ),
.M_AXI_ARREGION (cb_mi_arregion ),
.M_AXI_ARQOS (cb_mi_arqos ),
.M_AXI_ARUSER (cb_mi_aruser ),
.M_AXI_ARVALID (cb_mi_arvalid ),
.M_AXI_ARREADY (cb_mi_arready ),
.M_AXI_RID (cb_mi_rid ),
.M_AXI_RDATA (cb_mi_rdata ),
.M_AXI_RRESP (cb_mi_rresp ),
.M_AXI_RLAST (cb_mi_rlast ),
.M_AXI_RUSER (cb_mi_ruser ),
.M_AXI_RVALID (cb_mi_rvalid ),
.M_AXI_RREADY (cb_mi_rready )
);
end // gen_samd
// end // gen_crossbar
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: This is a generic n-deep SRL instantiation
// Verilog-standard: Verilog 2001
// $Revision:
// $Date:
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_ndeep_srl #
(
parameter C_FAMILY = "none", // FPGA Family
parameter C_A_WIDTH = 1 // Address Width (>= 1)
)
(
input wire CLK, // Clock
input wire [C_A_WIDTH-1:0] A, // Address
input wire CE, // Clock Enable
input wire D, // Input Data
output wire Q // Output Data
);
localparam P_SRLASIZE = 5;
localparam P_NUMSRLS = (C_A_WIDTH>P_SRLASIZE) ? (2**(C_A_WIDTH-P_SRLASIZE)) : 1;
wire [P_NUMSRLS:0] d_i;
wire [P_NUMSRLS-1:0] q_i;
wire [(C_A_WIDTH>P_SRLASIZE) ? (C_A_WIDTH-1) : (P_SRLASIZE-1) : 0] a_i;
genvar i;
// Instantiate SRLs in carry chain format
assign d_i[0] = D;
assign a_i = A;
generate
for (i=0;i<P_NUMSRLS;i=i+1) begin : gen_srls
SRLC32E
srl_inst
(
.CLK (CLK),
.A (a_i[P_SRLASIZE-1:0]),
.CE (CE),
.D (d_i[i]),
.Q (q_i[i]),
.Q31 (d_i[i+1])
);
end
endgenerate
// Instantiate MUX
generate
if (C_A_WIDTH>P_SRLASIZE) begin : gen_srl_mux
generic_baseblocks_v2_1_nto1_mux #
(
.C_RATIO (2**(C_A_WIDTH-P_SRLASIZE)),
.C_SEL_WIDTH (C_A_WIDTH-P_SRLASIZE),
.C_DATAOUT_WIDTH (1),
.C_ONEHOT (0)
)
srl_q_mux_inst
(
.SEL_ONEHOT ({2**(C_A_WIDTH-P_SRLASIZE){1'b0}}),
.SEL (a_i[C_A_WIDTH-1:P_SRLASIZE]),
.IN (q_i),
.OUT (Q)
);
end else begin : gen_no_srl_mux
assign Q = q_i[0];
end
endgenerate
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en, sr_req, app_sr_active, ref_req, app_ref_ack,
zq_req, app_zq_ack,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en, app_sr_req, sr_active, app_ref_req, ref_ack,
app_zq_req, zq_ack
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
input app_sr_req;
output wire sr_req;
assign sr_req = app_sr_req;
input sr_active;
output wire app_sr_active;
assign app_sr_active = sr_active;
input app_ref_req;
output wire ref_req;
assign ref_req = app_ref_req;
input ref_ack;
output wire app_ref_ack;
assign app_ref_ack = ref_ack;
input app_zq_req;
output wire zq_req;
assign zq_req = app_zq_req;
input zq_ack;
output wire app_zq_ack;
assign app_zq_ack = zq_ack;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
mig_7series_v2_3_ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
mig_7series_v2_3_ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
mig_7series_v2_3_ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple[3:0]),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:27:32 06/14/2012
// Design Name:
// Module Name: reorder_queue_output
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Outputs stored TLPs in increasing tag order.
//
// Dependencies:
// reorder_queue.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "trellis.vh"
module reorder_queue_output #(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_TAG_DW_COUNT_WIDTH = 8, // Width of max count DWs per packet
parameter C_DATA_ADDR_STRIDE_WIDTH = 5, // Width of max num stored data addr positions per tag
parameter C_DATA_ADDR_WIDTH = 10, // Width of stored data address
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_WORD_WIDTH = clog2s(C_PCI_DATA_WORD),
parameter C_PCI_DATA_COUNT_WIDTH = clog2s(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH
)
(
input CLK, // Clock
input RST, // Synchronous reset
output [C_DATA_ADDR_WIDTH-1:0] DATA_ADDR, // Address of stored packet data
input [C_PCI_DATA_WIDTH-1:0] DATA, // Stored packet data
input [C_NUM_TAGS-1:0] TAG_FINISHED, // Bitmap of finished tags
output [C_NUM_TAGS-1:0] TAG_CLEAR, // Bitmap of tags to clear
output [C_TAG_WIDTH-1:0] TAG, // Tag for which to retrieve packet data
input [5:0] TAG_MAPPED, // Mapped tag (i.e. internal tag)
input [C_TAG_DW_COUNT_WIDTH-1:0] PKT_WORDS, // Total count of packet payload in DWs
input PKT_WORDS_LTE1, // True if total count of packet payload is <= 4 DWs
input PKT_WORDS_LTE2, // True if total count of packet payload is <= 8 DWs
input PKT_DONE, // Packet done flag
input PKT_ERR, // Packet error flag
output [C_PCI_DATA_WIDTH-1:0] ENG_DATA, // Engine data
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
output [C_NUM_CHNL-1:0] MAIN_DONE, // Main data complete
output [C_NUM_CHNL-1:0] MAIN_ERR, // Main data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
output [C_NUM_CHNL-1:0] SG_RX_DONE, // Scatter gather for RX data complete
output [C_NUM_CHNL-1:0] SG_RX_ERR, // Scatter gather for RX data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
output [C_NUM_CHNL-1:0] SG_TX_DONE, // Scatter gather for TX data complete
output [C_NUM_CHNL-1:0] SG_TX_ERR // Scatter gather for TX data completed with error
);
reg [1:0] rState=0;
reg [C_DATA_ADDR_WIDTH-1:0] rDataAddr=0;
reg [C_PCI_DATA_WIDTH-1:0] rData=0;
reg rTagFinished=0;
reg [C_NUM_TAGS-1:0] rClear=0;
reg [C_TAG_WIDTH-1:0] rTag=0;
reg [C_TAG_WIDTH-1:0] rTagCurr=0;
wire [C_TAG_WIDTH-1:0] wTagNext = rTag + 1'd1;
reg [5:0] rShift;
reg rDone=0;
reg rDoneLast=0;
reg rErr=0;
reg rErrLast=0;
reg [C_PCI_DATA_COUNT_WIDTH-1:0] rDE=0;
reg [C_TAG_DW_COUNT_WIDTH-1:0] rWords=0;
reg rLTE2Pkts=0;
reg [C_PCI_DATA_WIDTH-1:0] rDataOut={C_PCI_DATA_WIDTH{1'b0}};
reg [(3*16*C_PCI_DATA_COUNT_WIDTH)-1:0] rDEOut={3*16*C_PCI_DATA_COUNT_WIDTH{1'd0}};
reg [(3*16)-1:0] rDoneOut={3*16{1'd0}};
reg [(3*16)-1:0] rErrOut={3*16{1'd0}};
assign DATA_ADDR = rDataAddr;
assign TAG = rTag;
assign TAG_CLEAR = rClear;
assign ENG_DATA = rDataOut;
assign MAIN_DATA_EN = rDEOut[(0*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign MAIN_DONE = rDoneOut[(0*16) +:C_NUM_CHNL];
assign MAIN_ERR = rErrOut[(0*16) +:C_NUM_CHNL];
assign SG_RX_DATA_EN = rDEOut[(1*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign SG_RX_DONE = rDoneOut[(1*16) +:C_NUM_CHNL];
assign SG_RX_ERR = rErrOut[(1*16) +:C_NUM_CHNL];
assign SG_TX_DATA_EN = rDEOut[(2*16*C_PCI_DATA_COUNT_WIDTH) +:(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)];
assign SG_TX_DONE = rDoneOut[(2*16) +:C_NUM_CHNL];
assign SG_TX_ERR = rErrOut[(2*16) +:C_NUM_CHNL];
// Output completed data in increasing tag order, avoid stalls if possible
always @ (posedge CLK) begin
if (RST) begin
rState <= #1 0;
rTag <= #1 0;
rDataAddr <= #1 0;
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 0;
rClear <= #1 0;
rTagFinished <= #1 0;
rShift <= 0; // Added
end
else begin
rTagFinished <= #1 TAG_FINISHED[rTag];
case (rState)
2'd0: begin // Request initial data and final info, output nothing
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 0;
rClear <= #1 0;
if (rTagFinished) begin
rTag <= #1 wTagNext;
rTagCurr <= #1 rTag;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd2;
end
else begin
rState <= #1 2'd0;
end
end
2'd1: begin // Request initial data and final info, output last data
rDone <= #1 rDoneLast;
rErr <= #1 rErrLast;
rDE <= #1 rWords[C_PCI_DATA_COUNT_WIDTH-1:0];
rClear <= #1 1<<rTagCurr; // Clear the tag
if (rTagFinished) begin
rTag <= #1 wTagNext;
rTagCurr <= #1 rTag;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd2;
end
else begin
rState <= #1 2'd0;
end
end
2'd2: begin // Initial data now available, output data
rShift <= #1 TAG_MAPPED;
rDoneLast <= #1 PKT_DONE;
rErrLast <= #1 PKT_ERR;
rWords <= #1 PKT_WORDS - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rLTE2Pkts <= #1 (PKT_WORDS <= (C_PCI_DATA_WORD*3));
if (PKT_WORDS_LTE1) begin // Guessed wrong, no addl data, need to reset
rDone <= #1 PKT_DONE;
rErr <= #1 PKT_ERR;
rDE <= #1 PKT_WORDS[C_PCI_DATA_COUNT_WIDTH-1:0];
rClear <= #1 1<<rTagCurr; // Clear the tag
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd0;
end
else if (PKT_WORDS_LTE2) begin // Guessed right, end of data, output last and continue
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rClear <= #1 0;
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd1;
end
else begin // Guessed right, more data, output it and continue
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rClear <= #1 0;
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd3;
end
end
2'd3: begin // Next data now available, output data
rDone <= #1 0;
rErr <= #1 0;
rDE <= #1 C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rWords <= #1 rWords - C_PCI_DATA_WORD[C_PCI_DATA_WORD_WIDTH:0];
rLTE2Pkts <= #1 (rWords <= (C_PCI_DATA_WORD*3));
if (rLTE2Pkts) begin // End of data, output last and continue
rDataAddr <= #1 rTag<<C_DATA_ADDR_STRIDE_WIDTH; // rTag is already on the next
rState <= #1 2'd1;
end
else begin // More data, output it and continue
rDataAddr <= #1 rDataAddr + 1'd1;
rState <= #1 2'd3;
end
end
endcase
end
end
// Output the data
always @ (posedge CLK) begin
rData <= #1 DATA;
rDataOut <= #1 rData;
if (RST) begin
rDEOut <= #1 0;
rDoneOut <= #1 0;
rErrOut <= #1 0;
end
else begin
rDEOut <= #1 rDE<<(C_PCI_DATA_COUNT_WIDTH*rShift);
rDoneOut <= #1 (rDone | rErr)<<rShift;
rErrOut <= #1 rErr<<rShift;
end
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(DVI_CLK),
.CONTROL(wControl0),
.TRIG0({wFifoFull, wFifoEmpty, rState, rPrevDVI_VS, DVI_DE, DVI_HS, DVI_VS}),
.DATA({457'd0,
rCount, // 21
rFrameCount, // 21
wCapture, // 1
RD_EN, // 1
RD_EMPTY, // 1
EOF, // 1
wPackerFull, // 1
wFifoFull, // 1
wFifoEmpty, // 1
rState, // 2
rPrevDVI_VS, // 1
DVI_DE, // 1
DVI_HS, // 1
DVI_VS}) // 1
);
*/
endmodule
|
// zhiyang ong
// andrew mattheisen
// The next line is only used for module synthesis
//`include "~/ee577b/syn/src/control.h"
module control(instr,
aluop, ww,
memEn, memWrEn, maddr, wbyteen,
regop, rrdaddra, rrdaddrb, rwraddrd,
reginmuxop,
aluinmuxop,
immediate);
// INPUTS
input [0:31] instr;
// OUTPUTS
output [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
output [0:2] regop;
output [0:1] ww;
output [0:20] maddr;
output memEn, memWrEn;
output reginmuxop, aluinmuxop;
output [0:15] wbyteen;
output [0:127] immediate;
// REGISTERS
reg [0:4] aluop, rrdaddra, rrdaddrb, rwraddrd;
reg [0:2] ppp, regop;
reg [0:1] ww, memop;
reg [0:20] maddr;
reg memEn, memWrEn;
reg reginmuxop, aluinmuxop;
reg [0:15] wbyteen;
reg [0:127] immediate;
// PARAMETERS
parameter zero = 1'b0;
parameter one = 1'b1;
always @ (ppp or ww or instr) // determine wbyteen
begin
if (instr[5]== 1'b1)
begin
wbyteen=16'b1111111111111111;
end
else if (ppp == `aa)
wbyteen=16'b1111111111111111;
else if (ppp == `uu)
wbyteen=16'b1111111100000000;
else if (ppp == `dd)
wbyteen=16'b0000000011111111;
else if (ppp == `ee)
begin
if (ww==`w8)
wbyteen=16'b1010101010101010;
else if (ww==`w16)
wbyteen=16'b1100110011001100;
else if (ww==`w32)
wbyteen=16'b1111000011110000;
else // default
wbyteen=16'b0;
end
else if (ppp == `oo)
begin
if (ww==`w8)
wbyteen=16'b0101010101010101;
else if (ww==`w16)
wbyteen=16'b0011001100110011;
else if (ww==`w32)
wbyteen=16'b0000111100001111;
else // default
wbyteen=16'b0;
end
else if (ppp == `mm)
begin
if (ww==`w8)
wbyteen=16'b1000000000000000;
else if (ww==`w16)
wbyteen=16'b1100000000000000;
else if (ww==`w32)
wbyteen=16'b1111000000000000;
else // default
wbyteen=16'b0;
end
else if (ppp == `ll)
begin
if (ww==`w8)
wbyteen=16'b0000000000000001;
else if (ww==`w16)
wbyteen=16'b0000000000000011;
else if (ww==`w32)
wbyteen=16'b0000000000001111;
else // default
wbyteen=16'b0;
end
else // default
wbyteen=16'b0;
end //always @ (ppp or ww)
always @ (instr)
begin
immediate={instr[16:20], {123{zero}}};
ppp=instr[21:23];
ww=instr[24:25];
maddr=instr[11:31];
rwraddrd=instr[6:10];
if (instr[2] == 1'b1) // => instr is wmv
begin
aluop=instr[26:31]; // alu control
regop=`rd1wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=one; // mux control
reginmuxop=zero;
end // if (instr[2] == 1'b1)
else if (instr[3] == 1'b1) // must examine bits 0-5
begin
if ({instr[26:28], instr[31]} == 4'b0101) // immediate shift
begin
aluop=instr[26:31]; // alu control
regop=`rd1wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=one; // mux control
reginmuxop=zero;
end
else if (instr[26:31]==6'b001000) // instr is wnot
begin
aluop=instr[26:31]; // alu control
regop=`rd1wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=one; // mux control
reginmuxop=zero;
end
else // all other commands
begin
aluop=instr[26:31]; // alu control
regop=`rd2wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop; // mem control
memEn=zero;
memWrEn=zero;
aluinmuxop=zero; // mux control
reginmuxop=zero;
end
end // else if (instr[3] == 1'b1)
else if (instr[4]==1'b1) // => instr is wst
begin
aluop=`alunop; // alu control
regop=`rd2wr0; // reg control
rrdaddra=instr[6:10]; // note this is special
rrdaddrb=instr[6:10]; // note this is special
//memop=`memwst; // mem control
memEn=one;
memWrEn=one;
aluinmuxop=zero; // mux control
reginmuxop=zero;
end // else if (instr[4]==1'b1)
else if (instr[5]==1'b1) // => instr is wld
begin
aluop=`alunop; // alu control
regop=`rd0wr1; // reg control
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memwld; // mem control
memEn=one;
memWrEn=zero;
aluinmuxop=zero; // mux control
reginmuxop=one;
end // else if (instr[5]==1'b1)
else // => instr is NOP
begin
aluop=`alunop;
regop=`regnop;
rrdaddra=instr[11:15];
rrdaddrb=instr[16:20];
//memop=`memnop;
memEn=zero;
memWrEn=zero;
reginmuxop=zero;
aluinmuxop=zero;
end // else
end // always @ (instr)
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_req # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_read_req_size,
output pcie_rx_cmd_rd_en,
input [33:0] pcie_rx_cmd_rd_data,
input pcie_rx_cmd_empty_n,
output pcie_tag_alloc,
output [7:0] pcie_alloc_tag,
output [9:4] pcie_tag_alloc_len,
input pcie_tag_full_n,
input pcie_rx_fifo_full_n,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack
);
localparam LP_PCIE_TAG_PREFIX = 4'b0001;
localparam LP_PCIE_MRD_DELAY = 8;
localparam S_IDLE = 9'b000000001;
localparam S_PCIE_RX_CMD_0 = 9'b000000010;
localparam S_PCIE_RX_CMD_1 = 9'b000000100;
localparam S_PCIE_CHK_NUM_MRD = 9'b000001000;
localparam S_PCIE_MRD_REQ = 9'b000010000;
localparam S_PCIE_MRD_ACK = 9'b000100000;
localparam S_PCIE_MRD_DONE = 9'b001000000;
localparam S_PCIE_MRD_DELAY = 9'b010000000;
localparam S_PCIE_MRD_NEXT = 9'b100000000;
reg [8:0] cur_state;
reg [8:0] next_state;
reg [2:0] r_pcie_max_read_req_size;
reg r_pcie_rx_cmd_rd_en;
reg [12:2] r_pcie_rx_len;
reg [9:2] r_pcie_rx_cur_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_pcie_addr;
reg [3:0] r_pcie_rx_tag;
reg r_pcie_rx_tag_update;
reg [5:0] r_pcie_mrd_delay;
reg r_pcie_tag_alloc;
reg r_tx_dma_mrd_req;
assign pcie_rx_cmd_rd_en = r_pcie_rx_cmd_rd_en;
assign pcie_tag_alloc = r_pcie_tag_alloc;
assign pcie_alloc_tag = {LP_PCIE_TAG_PREFIX, r_pcie_rx_tag};
assign pcie_tag_alloc_len = r_pcie_rx_cur_len[9:4];
assign tx_dma_mrd_req = r_tx_dma_mrd_req;
assign tx_dma_mrd_tag = {LP_PCIE_TAG_PREFIX, r_pcie_rx_tag};
assign tx_dma_mrd_len = {2'b0, r_pcie_rx_cur_len};
assign tx_dma_mrd_addr = r_pcie_addr;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_rx_cmd_empty_n == 1)
next_state <= S_PCIE_RX_CMD_0;
else
next_state <= S_IDLE;
end
S_PCIE_RX_CMD_0: begin
next_state <= S_PCIE_RX_CMD_1;
end
S_PCIE_RX_CMD_1: begin
next_state <= S_PCIE_CHK_NUM_MRD;
end
S_PCIE_CHK_NUM_MRD: begin
if(pcie_rx_fifo_full_n == 1 && pcie_tag_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_PCIE_CHK_NUM_MRD;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_dma_mrd_req_ack == 1)
next_state <= S_PCIE_MRD_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_DONE: begin
next_state <= S_PCIE_MRD_DELAY;
end
S_PCIE_MRD_DELAY: begin
if(r_pcie_mrd_delay == 0)
next_state <= S_PCIE_MRD_NEXT;
else
next_state <= S_PCIE_MRD_DELAY;
end
S_PCIE_MRD_NEXT: begin
if(r_pcie_rx_len == 0)
next_state <= S_IDLE;
else
next_state <= S_PCIE_CHK_NUM_MRD;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_rx_tag <= 0;
end
else begin
if(r_pcie_rx_tag_update == 1)
r_pcie_rx_tag <= r_pcie_rx_tag + 1;
end
end
always @ (posedge pcie_user_clk)
begin
r_pcie_max_read_req_size <= pcie_max_read_req_size;
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_PCIE_RX_CMD_0: begin
r_pcie_rx_len <= {pcie_rx_cmd_rd_data[10:2], 2'b0};
end
S_PCIE_RX_CMD_1: begin
case(r_pcie_max_read_req_size)
3'b010: begin
if(r_pcie_rx_len[8:7] == 0 && r_pcie_rx_len[6:2] == 0)
r_pcie_rx_cur_len[9:7] <= 3'b100;
else
r_pcie_rx_cur_len[9:7] <= {1'b0, r_pcie_rx_len[8:7]};
end
3'b001: begin
if(r_pcie_rx_len[7] == 0 && r_pcie_rx_len[6:2] == 0)
r_pcie_rx_cur_len[9:7] <= 3'b010;
else
r_pcie_rx_cur_len[9:7] <= {2'b0, r_pcie_rx_len[7]};
end
default: begin
if(r_pcie_rx_len[6:2] == 0)
r_pcie_rx_cur_len[9:7] <= 3'b001;
else
r_pcie_rx_cur_len[9:7] <= 3'b000;
end
endcase
r_pcie_rx_cur_len[6:2] <= r_pcie_rx_len[6:2];
r_pcie_addr <= {pcie_rx_cmd_rd_data[33:2], 2'b0};
end
S_PCIE_CHK_NUM_MRD: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_DONE: begin
r_pcie_addr <= r_pcie_addr + r_pcie_rx_cur_len;
r_pcie_rx_len <= r_pcie_rx_len - r_pcie_rx_cur_len;
case(r_pcie_max_read_req_size)
3'b010: r_pcie_rx_cur_len <= 8'h80;
3'b001: r_pcie_rx_cur_len <= 8'h40;
default: r_pcie_rx_cur_len <= 8'h20;
endcase
r_pcie_mrd_delay <= LP_PCIE_MRD_DELAY;
end
S_PCIE_MRD_DELAY: begin
r_pcie_mrd_delay <= r_pcie_mrd_delay - 1'b1;
end
S_PCIE_MRD_NEXT: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_RX_CMD_0: begin
r_pcie_rx_cmd_rd_en <= 1;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_RX_CMD_1: begin
r_pcie_rx_cmd_rd_en <= 1;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_CHK_NUM_MRD: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 1;
r_tx_dma_mrd_req <= 1;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_DONE: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 1;
end
S_PCIE_MRD_DELAY: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
S_PCIE_MRD_NEXT: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
default: begin
r_pcie_rx_cmd_rd_en <= 0;
r_pcie_tag_alloc <= 0;
r_tx_dma_mrd_req <= 0;
r_pcie_rx_tag_update <= 0;
end
endcase
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_efuse_reg.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_efuse_reg
// Description: Shift register to hold fuse value from efuse unit.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_efuse_reg (/*AUTOARG*/
// Outputs
fuse_reg,
// Inputs
arst_l, fuse_clk, data_in, shift_en
);
// synopsys template
parameter REG_WIDTH = `IOB_FUSE_WIDTH;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input arst_l;
input fuse_clk;
input data_in;
input shift_en;
output [REG_WIDTH-1:0] fuse_reg;
wire [REG_WIDTH-1:0] fuse_reg_next;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// The MSB is shifted out first
assign fuse_reg_next = shift_en ? {fuse_reg[REG_WIDTH-2:0],data_in} :
fuse_reg;
dffsl_async_ns #(REG_WIDTH) fuse_reg_ff (.din(fuse_reg_next),
.set_l(arst_l),
.clk(fuse_clk),
.q(fuse_reg));
endmodule // iobdg_efuse_reg
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
`include "qlf_k6n10f/cells_sim.v"
module tb();
// Clock
reg clk;
initial clk <= 1'b0;
always #0.5 clk <= ~clk;
// Reset
reg rst;
initial begin
rst <= 1'b0;
#1 rst <= 1'b1;
#2 rst <= 1'b0;
end
// Input data / reference
reg signed [19:0] A;
reg signed [17:0] B;
reg signed [37:0] C;
// Shift data change half a clock cycle
// to make registered inputs apparent
initial begin
forever begin
A = $random;
B = $random;
C <= A * B;
#1.5;
end
end
// UUT
wire signed [37:0] Z;
dsp_t1_sim # (
) uut (
.a_i (A),
.b_i (B),
.unsigned_a_i (1'h0),
.unsigned_b_i (1'h0),
.feedback_i (3'h0),
.register_inputs_i (1'h1),
.output_select_i (3'h0),
.clock_i (clk),
.z_o (Z)
);
// Error detection
reg [37:0] r_C;
initial r_C <= 0;
always @(posedge clk)
r_C <= C;
wire error = (Z !== r_C);
// Error counting
integer error_count;
initial error_count <= 0;
always @(posedge clk) begin
if (error) error_count <= error_count + 1;
end
// Simulation control / data dump
initial begin
$dumpfile(`VCD_FILE);
$dumpvars(0, tb);
#100 $finish_and_return( (error_count == 0) ? 0 : -1 );
end
endmodule
|
Require Import List.
Require Import Arith.
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import InfSeqExt.infseq.
Import ListNotations.
Module Type DynamicSystem.
Parameter addr : Type. (* must be finite, decidable *)
Parameter client_addr : addr -> Prop.
Parameter client_addr_dec : forall a : addr, {client_addr a} + {~ client_addr a}.
Parameter addr_eq_dec : forall x y : addr, {x = y} + {x <> y}.
Parameter payload : Type. (* must be serializable *)
Parameter payload_eq_dec : forall x y : payload, {x = y} + {x <> y}.
Parameter client_payload : payload -> Prop. (* holds for payloads that clients can send *)
Parameter client_payload_dec : forall p : payload, {client_payload p} + {~ client_payload p}.
Parameter data : Type.
Parameter timeout : Type.
Parameter timeout_eq_dec : forall x y : timeout, {x = y} + {x <> y}.
Parameter label : Type.
Parameter label_eq_dec : forall x y : label, {x = y} + {x <> y}.
Parameter start_handler : addr -> list addr -> data * list (addr * payload) * list timeout.
Definition res := (data * list (addr * payload) * list timeout * list timeout)%type.
Parameter recv_handler : addr -> addr -> data -> payload -> res.
Parameter timeout_handler : addr -> data -> timeout -> res.
Parameter recv_handler_l : addr -> addr -> data -> payload -> (res * label).
Parameter timeout_handler_l : addr -> data -> timeout -> (res * label).
Parameter label_input : addr -> addr -> payload -> label.
Parameter label_output : addr -> addr -> payload -> label.
Parameter recv_handler_labeling :
forall src dst st p r,
(recv_handler src dst st p = r ->
exists l,
recv_handler_l src dst st p = (r, l)) /\
(forall l,
recv_handler_l src dst st p = (r, l) ->
recv_handler src dst st p = r).
Parameter timeout_handler_labeling :
forall h st t r,
(timeout_handler h st t = r ->
exists l,
timeout_handler_l h st t = (r, l)) /\
(forall l,
timeout_handler_l h st t = (r, l) ->
timeout_handler h st t = r).
End DynamicSystem.
Module Type ConstrainedDynamicSystem.
Include DynamicSystem.
(* msgs *)
Definition msg : Type := (addr * (addr * payload))%type.
Inductive event : Type :=
| e_send : msg -> event
| e_recv : msg -> event
| e_timeout : addr -> timeout -> event
| e_fail : addr -> event.
Record global_state :=
{ nodes : list addr;
failed_nodes : list addr;
timeouts : addr -> list timeout;
sigma : addr -> option data;
msgs : list msg;
trace : list event
}.
Parameter timeout_constraint : global_state -> addr -> timeout -> Prop.
(* failure_constraint is parametrized over an initial state, the
address of the failing node, and what the state would be after
the failure. *)
Parameter failure_constraint : global_state -> addr -> global_state -> Prop.
Parameter start_constraint : global_state -> addr -> Prop.
End ConstrainedDynamicSystem.
Module DynamicSemantics (S : ConstrainedDynamicSystem).
Include S.
Definition msg_eq_dec :
forall x y : msg, {x = y} + {x <> y}.
Proof.
repeat decide equality;
auto using addr_eq_dec, payload_eq_dec.
Defined.
Definition send (a : addr) (p : addr * payload) : msg :=
(a, p).
Definition update_msgs (gst : global_state) (ms : list msg) : global_state :=
{| nodes := nodes gst;
failed_nodes := failed_nodes gst;
timeouts := timeouts gst;
sigma := sigma gst;
msgs := ms;
trace := trace gst
|}.
Definition fail_node (gst : global_state) (h : addr) : global_state :=
{| nodes := nodes gst;
failed_nodes := h :: failed_nodes gst;
timeouts := timeouts gst;
sigma := sigma gst;
msgs := msgs gst;
trace := trace gst
|}.
Definition apply_handler_result (h : addr) (r : res) (es : list event) (gst : global_state) : global_state :=
let '(st, ms, nts, cts) := r in
let sends := map (send h) ms in
let ts' := nts ++ remove_all timeout_eq_dec cts (timeouts gst h) in
{| nodes := nodes gst;
failed_nodes := failed_nodes gst;
timeouts := update addr_eq_dec (timeouts gst) h ts';
sigma := update addr_eq_dec (sigma gst) h (Some st);
msgs := sends ++ msgs gst;
trace := trace gst ++ es
|}.
Lemma apply_handler_result_nodes :
forall h r e gst,
nodes (apply_handler_result h r e gst) = nodes gst.
Proof using.
unfold apply_handler_result.
intros.
now repeat break_let.
Qed.
Definition update_for_start
(gst : global_state) (h : addr)
(res : data * list (addr * payload) * list timeout) : global_state :=
let '(st, ms, newts) := res in
let sends := map (send h) ms in
{| nodes := h :: nodes gst;
failed_nodes := failed_nodes gst;
timeouts := update addr_eq_dec (timeouts gst) h newts;
sigma := update addr_eq_dec (sigma gst) h (Some st);
msgs := sends ++ msgs gst;
trace := trace gst ++ (map e_send sends)
|}.
Lemma update_for_start_nodes :
forall gst gst' h res,
update_for_start gst h res = gst' ->
h :: nodes gst = nodes gst'.
Proof using.
unfold update_for_start.
intros.
repeat break_let.
now repeat find_reverse_rewrite.
Qed.
Lemma update_for_start_nodes_eq :
forall gst h res,
nodes (update_for_start gst h res) = h :: nodes gst.
Proof using.
unfold update_for_start.
intros.
now repeat break_let.
Qed.
Lemma update_for_start_sigma_h_exists :
forall gst h res,
exists st,
sigma (update_for_start gst h res) h = Some st.
Proof using.
unfold update_for_start.
intros.
repeat break_let.
simpl.
eexists; eauto using update_eq.
Qed.
Lemma update_for_start_sigma_h_n :
forall gst h n res st,
h <> n ->
sigma gst n = Some st ->
sigma (update_for_start gst h res) n = Some st.
Proof using.
unfold update_for_start.
intros.
repeat break_let.
simpl.
now rewrite update_diff.
Qed.
Definition live_with_state (gst : global_state) (h : addr) (st : data) :=
In h (nodes gst) /\
~ In h (failed_nodes gst) /\
sigma gst h = Some st.
Definition update_msgs_and_trace (gst : global_state) (ms : list msg) (e : event) : global_state :=
{| nodes := nodes gst;
failed_nodes := failed_nodes gst;
timeouts := timeouts gst;
sigma := sigma gst;
msgs := ms;
trace := trace gst ++ [e] |}.
Inductive step_dynamic : global_state -> global_state -> Prop :=
| Start :
forall h gst gst' k,
~ In h (nodes gst) ->
~ client_addr h ->
start_constraint gst h ->
(* hypotheses on the list of known nodes *)
In k (nodes gst) ->
~ In k (failed_nodes gst) ->
gst' = update_for_start gst h (start_handler h (k :: nil)) ->
step_dynamic gst gst'
| Fail :
forall h gst gst',
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
gst' = fail_node gst h ->
failure_constraint gst h gst' ->
step_dynamic gst gst'
| Timeout :
forall gst gst' h st t st' ms newts clearedts,
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some st ->
In t (timeouts gst h) ->
timeout_handler h st t = (st', ms, newts, clearedts) ->
gst' = (apply_handler_result
h
(st', ms, newts, t :: clearedts)
[e_timeout h t]
gst) ->
timeout_constraint gst h t ->
step_dynamic gst gst'
| Deliver_node :
forall gst gst' m h d xs ys ms st newts clearedts,
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some d ->
recv_handler (fst m) h d (snd (snd m)) = (st, ms, newts, clearedts) ->
gst' = apply_handler_result
h
(st, ms, newts, clearedts)
[e_recv m]
(update_msgs gst (xs ++ ys)) ->
step_dynamic gst gst'
| Input :
forall gst gst' h i to m,
client_addr h ->
client_payload i ->
m = send h (to, i) ->
gst' = update_msgs_and_trace gst (m :: msgs gst) (e_send m) ->
step_dynamic gst gst'
| Deliver_client :
forall gst gst' h xs m ys,
client_addr h ->
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
gst' = update_msgs_and_trace gst (xs ++ ys) (e_recv m) ->
step_dynamic gst gst'.
Inductive labeled_step_dynamic : global_state -> label -> global_state -> Prop :=
| LTimeout :
forall gst gst' h st t lb st' ms newts clearedts,
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some st ->
In t (timeouts gst h) ->
timeout_handler_l h st t = (st', ms, newts, clearedts, lb) ->
gst' = (apply_handler_result
h
(st', ms, newts, t :: clearedts)
[e_timeout h t]
gst) ->
timeout_constraint gst h t ->
labeled_step_dynamic gst lb gst'
| LDeliver_node :
forall gst gst' m h d xs ys ms lb st newts clearedts,
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
In h (nodes gst) ->
~ In h (failed_nodes gst) ->
sigma gst h = Some d ->
recv_handler_l (fst m) h d (snd (snd m)) = (st, ms, newts, clearedts, lb) ->
gst' = apply_handler_result
h
(st, ms, newts, clearedts)
[e_recv m]
(update_msgs gst (xs ++ ys)) ->
labeled_step_dynamic gst lb gst'
| LInput :
forall gst gst' h i to m l,
client_addr h ->
client_payload i ->
m = send h (to, i) ->
l = label_input h to i ->
gst' = update_msgs_and_trace gst (m :: msgs gst) (e_send m) ->
labeled_step_dynamic gst l gst'
| LDeliver_client :
forall gst gst' h xs m ys l,
client_addr h ->
msgs gst = xs ++ m :: ys ->
h = fst (snd m) ->
l = label_output (fst m) h (snd (snd m)) ->
gst' = update_msgs_and_trace gst (xs ++ ys) (e_recv m) ->
labeled_step_dynamic gst l gst'.
Record occurrence := { occ_gst : global_state ; occ_label : label }.
Definition enabled (l : label) (gst : global_state) : Prop :=
exists gst', labeled_step_dynamic gst l gst'.
Definition l_enabled (l : label) (occ : occurrence) : Prop :=
enabled l (occ_gst occ).
Definition occurred (l : label) (occ :occurrence) : Prop := l = occ_label occ.
Definition inf_enabled (l : label) (s : infseq occurrence) : Prop :=
inf_often (now (l_enabled l)) s.
Definition cont_enabled (l : label) (s : infseq occurrence) : Prop :=
continuously (now (l_enabled l)) s.
Definition inf_occurred (l : label) (s : infseq occurrence) : Prop :=
inf_often (now (occurred l)) s.
Definition strong_local_fairness (s : infseq occurrence) : Prop :=
forall l : label, inf_enabled l s -> inf_occurred l s.
Definition weak_local_fairness (s : infseq occurrence) : Prop :=
forall l : label, cont_enabled l s -> inf_occurred l s.
Lemma strong_local_fairness_invar :
forall e s, strong_local_fairness (Cons e s) -> strong_local_fairness s.
Proof using.
unfold strong_local_fairness. unfold inf_enabled, inf_occurred, inf_often.
intros e s fair a alev.
assert (alevt_es: always (eventually (now (l_enabled a))) (Cons e s)).
constructor.
constructor 2. destruct alev; assumption.
simpl. assumption.
clear alev. generalize (fair a alevt_es); clear fair alevt_es.
intro fair; case (always_Cons fair); trivial.
Qed.
Lemma weak_local_fairness_invar :
forall e s, weak_local_fairness (Cons e s) -> weak_local_fairness s.
Proof using.
unfold weak_local_fairness. unfold cont_enabled, inf_occurred, continuously, inf_often.
intros e s fair l eval.
assert (eval_es: eventually (always (now (l_enabled l))) (Cons e s)).
apply E_next. assumption.
apply fair in eval_es.
apply always_invar in eval_es.
assumption.
Qed.
Lemma strong_local_fairness_weak :
forall s, strong_local_fairness s -> weak_local_fairness s.
Proof using.
intros [e s].
unfold strong_local_fairness, weak_local_fairness, inf_enabled, cont_enabled.
intros H_str l H_cont.
apply H_str.
apply continuously_inf_often.
assumption.
Qed.
CoInductive lb_execution : infseq occurrence -> Prop :=
Cons_lb_exec : forall (o o' : occurrence) (s : infseq occurrence),
labeled_step_dynamic (occ_gst o) (occ_label o) (occ_gst o') ->
lb_execution (Cons o' s) ->
lb_execution (Cons o (Cons o' s)).
Lemma lb_execution_invar :
forall x s, lb_execution (Cons x s) -> lb_execution s.
Proof using.
intros x s e. change (lb_execution (tl (Cons x s))).
destruct e; simpl. assumption.
Qed.
Lemma labeled_step_is_unlabeled_step :
forall gst l gst',
labeled_step_dynamic gst l gst' ->
step_dynamic gst gst'.
Proof using.
intuition.
match goal with
| H: labeled_step_dynamic _ _ _ |- _ =>
invc H
end.
- find_apply_lem_hyp timeout_handler_labeling.
eapply Timeout; eauto.
- find_apply_lem_hyp recv_handler_labeling.
eapply Deliver_node; eauto.
- eapply Input; eauto.
- eapply Deliver_client; eauto.
Qed.
Inductive churn_between (gst gst' : global_state) : Prop :=
| fail_churn : failed_nodes gst <> failed_nodes gst' -> churn_between gst gst'
| join_churn : nodes gst <> nodes gst' -> churn_between gst gst'.
Ltac invc_lstep :=
match goal with
| H: labeled_step_dynamic _ _ _ |- _ =>
invc H
end.
Lemma labeled_step_dynamic_preserves_nodes :
forall gst l gst',
labeled_step_dynamic gst l gst' ->
nodes gst = nodes gst'.
Proof.
intros.
inv_prop labeled_step_dynamic;
simpl; reflexivity.
Qed.
Lemma labeled_step_dynamic_preserves_failed_nodes :
forall gst l gst',
labeled_step_dynamic gst l gst' ->
failed_nodes gst = failed_nodes gst'.
Proof.
intros.
inv_prop labeled_step_dynamic;
simpl; reflexivity.
Qed.
Lemma labeled_step_dynamic_is_step_dynamic_without_churn :
forall gst gst',
step_dynamic gst gst' ->
((exists l, labeled_step_dynamic gst l gst') /\ ~ churn_between gst gst') \/
((~ exists l, labeled_step_dynamic gst l gst') /\ churn_between gst gst').
Proof using.
intuition.
match goal with
| H: step_dynamic _ _ |- _ =>
invc H
end.
- right.
split.
* intuition.
break_exists.
invc_lstep;
find_apply_lem_hyp update_for_start_nodes;
try find_rewrite_lem apply_handler_result_nodes;
eapply list_neq_cons; eauto.
* apply join_churn.
rewrite update_for_start_nodes_eq.
eauto using list_neq_cons.
- right.
unfold fail_node.
split.
* intuition.
break_exists.
invc_lstep;
unfold apply_handler_result, update_msgs_and_trace in *;
find_inversion;
eapply list_neq_cons; eauto.
* eauto using fail_churn, list_neq_cons.
- left.
split.
* find_apply_lem_hyp timeout_handler_labeling.
break_exists_exists.
eauto using LTimeout.
* intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
- left.
split.
* find_apply_lem_hyp recv_handler_labeling.
break_exists_exists.
eauto using LDeliver_node.
* intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
- left. split.
+ eauto using labeled_step_dynamic.
+ intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
- left. split.
+ eauto using labeled_step_dynamic.
+ intuition.
match goal with
| H: churn_between _ _ |- _ =>
inversion H; eauto
end.
Qed.
Ltac break_step :=
match goal with
| [ H : step_dynamic _ _ |- _ ] =>
induction H
end; subst.
(* Predicates on global states *)
Definition gpred : Type := global_state -> Prop.
Definition gpred_and (P Q : global_state -> Prop) (gst : global_state) : Prop :=
P gst /\ Q gst.
Definition lift_gpred_to_occ (P : global_state -> Prop) (o : occurrence) : Prop :=
P (occ_gst o).
Definition lift_gpred_to_ex (P : global_state -> Prop) : infseq.infseq occurrence -> Prop :=
infseq.now (lift_gpred_to_occ P).
End DynamicSemantics.
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_load (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* This tests the latching of an output that isn't really an output,
* but an intermediate symbol that is only used in some clauses.
*/
module main;
reg [15:0] out, a;
reg [7:0] b;
reg cy;
reg with_carry;
(* ivl_combinational *)
always @(with_carry, a, b, cy)
if (with_carry) begin
{cy, out[7:0]} = {1'b0, a[7:0]} + {1'b0, b[7:0]};
out[15:8] = a[15:8] + {7'b0, cy};
end else begin
out = a + {8'h00, b};
end
(* ivl_synthesis_off *)
initial begin
a = 16'h00fe;
b = 8'h00;
with_carry = 0;
#1 if (out !== 16'h00fe) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
with_carry = 1;
#1 if (out !== 16'h00fe) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
b = 2;
#1 if (out !== 16'h0100) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
with_carry = 0;
#1 if (out !== 16'h0100) begin
$display("FAILED -- a=%h, b=%h, out=%h", a, b, out);
$finish;
end
$display("PASSED");
end
endmodule // main
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module Muliti_cycle_Cpu( clk,
reset,
MIO_ready,
pc_out, //TEST
Inst, //TEST
mem_w,
Addr_out,
data_out,
data_in,
breq_o,
CPU_MIO,
state,
Ireq,
Iack,
Enable_i
);
input clk,reset,MIO_ready,Ireq,Enable_i;
output [31:0] pc_out;
output [31:0] Inst;
output mem_w, breq_o, CPU_MIO,Iack;
output [31:0] Addr_out;
output [31:0] data_out;
output [4:0] state;
input [31:0] data_in;
wire [31:0] Inst,Addr_out,PC_Current,pc_out,data_in,data_out;
wire [15:0] imm;
wire [4:0] state;
wire [2:0] ALU_operation,MemtoReg,PCSource;
wire [1:0] RegDst,ALUSrcB,IntCause;
wire breq_o,CPU_MIO,MemRead,MemWrite,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq,CauseWrite,EPCWrite,Co0Write;
wire reset,MIO_ready, mem_w,zero,overflow,Ireq,Iack,Enable_i;
// assign rst=reset;
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++=
ctrl x_ctrl(.clk(clk),
.reset(reset),
.Inst_in(Inst),
.zero(zero),
.overflow(overflow),
.MIO_ready(MIO_ready),
.MemRead(MemRead),
.MemWrite(MemWrite),
.ALU_operation(ALU_operation),
.state_out(state),
.CPU_MIO(CPU_MIO),
.IorD(IorD),
.IRWrite(IRWrite),
.RegDst(RegDst),
.RegWrite(RegWrite),
.MemtoReg(MemtoReg),
.ALUSrcA(ALUSrcA),
.ALUSrcB(ALUSrcB),
.PCSource(PCSource),
.PCWrite(PCWrite),
.PCWriteCond(PCWriteCond),
.Beq(Beq),
.CauseWrite(CauseWrite),
.IntCause(IntCause),
.EPCWrite(EPCWrite),
.Co0Write(Co0Write),
.Ireq(Ireq),
.Iack(Iack),
.Enable_i(Enable_i)
);
data_path x_datapath(.clk(clk),
.reset(reset),
.MIO_ready(MIO_ready),
.IorD(IorD),
.IRWrite(IRWrite),
.RegDst(RegDst),
.RegWrite(RegWrite),
.MemtoReg(MemtoReg),
.ALUSrcA(ALUSrcA),
.ALUSrcB(ALUSrcB),
.PCSource(PCSource),
.PCWrite(PCWrite),
.PCWriteCond(PCWriteCond),
.Beq(Beq),
.ALU_operation(ALU_operation),
.PC_Current(PC_Current),
.data2CPU(data_in),
.Inst_R(Inst),
.data_out(data_out),
.M_addr(Addr_out),
.zero(zero),
.overflow(overflow),
.CauseWrite(CauseWrite),
.IntCause(IntCause),
.EPCWrite(EPCWrite),
.Co0Write(Co0Write)
);
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++==
assign mem_w=MemWrite&&(~MemRead);
assign breq_o=MemRead|MemWrite;
assign pc_out=PC_Current;
endmodule
|
//
// TV80 8-Bit Microprocessor Core
// Based on the VHDL T80 core by Daniel Wallner ([email protected])
//
// Copyright (c) 2004 Guy Hutchison ([email protected])
//
// Permission is hereby granted, free of charge, to any person obtaining a
// copy of this software and associated documentation files (the "Software"),
// to deal in the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included
// in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
module tv80_alu (/*AUTOARG*/
// Outputs
Q, F_Out,
// Inputs
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
);
parameter Mode = 3;
parameter Flag_C = 0;
parameter Flag_N = 1;
parameter Flag_P = 2;
parameter Flag_X = 3;
parameter Flag_H = 4;
parameter Flag_Y = 5;
parameter Flag_Z = 6;
parameter Flag_S = 7;
input Arith16;
input Z16;
input [3:0] ALU_Op ;
input [5:0] IR;
input [1:0] ISet;
input [7:0] BusA;
input [7:0] BusB;
input [7:0] F_In;
output [7:0] Q;
output [7:0] F_Out;
reg [7:0] Q;
reg [7:0] F_Out;
function [4:0] AddSub4;
input [3:0] A;
input [3:0] B;
input Sub;
input Carry_In;
begin
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
function [3:0] AddSub3;
input [2:0] A;
input [2:0] B;
input Sub;
input Carry_In;
begin
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
function [1:0] AddSub1;
input A;
input B;
input Sub;
input Carry_In;
begin
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + Carry_In;
end
endfunction // AddSub4
// AddSub variables (temporary signals)
reg UseCarry;
reg Carry7_v;
reg OverFlow_v;
reg HalfCarry_v;
reg Carry_v;
reg [7:0] Q_v;
reg [7:0] BitMask;
always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
begin
case (IR[5:3])
3'b000 : BitMask = 8'b00000001;
3'b001 : BitMask = 8'b00000010;
3'b010 : BitMask = 8'b00000100;
3'b011 : BitMask = 8'b00001000;
3'b100 : BitMask = 8'b00010000;
3'b101 : BitMask = 8'b00100000;
3'b110 : BitMask = 8'b01000000;
default: BitMask = 8'b10000000;
endcase // case(IR[5:3])
UseCarry = ~ ALU_Op[2] && ALU_Op[0];
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
OverFlow_v = Carry_v ^ Carry7_v;
end // always @ *
reg [7:0] Q_t;
reg [8:0] DAA_Q;
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
or Carry_v or F_In or HalfCarry_v or IR or ISet
or OverFlow_v or Q_v or Z16)
begin
Q_t = 8'hxx;
DAA_Q = {9{1'bx}};
F_Out = F_In;
case (ALU_Op)
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
begin
F_Out[Flag_N] = 1'b0;
F_Out[Flag_C] = 1'b0;
case (ALU_Op[2:0])
3'b000, 3'b001 : // ADD, ADC
begin
Q_t = Q_v;
F_Out[Flag_C] = Carry_v;
F_Out[Flag_H] = HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
begin
Q_t = Q_v;
F_Out[Flag_N] = 1'b1;
F_Out[Flag_C] = ~ Carry_v;
F_Out[Flag_H] = ~ HalfCarry_v;
F_Out[Flag_P] = OverFlow_v;
end
3'b100 : // AND
begin
Q_t[7:0] = BusA & BusB;
F_Out[Flag_H] = 1'b1;
end
3'b101 : // XOR
begin
Q_t[7:0] = BusA ^ BusB;
F_Out[Flag_H] = 1'b0;
end
default : // OR 3'b110
begin
Q_t[7:0] = BusA | BusB;
F_Out[Flag_H] = 1'b0;
end
endcase // case(ALU_OP[2:0])
if (ALU_Op[2:0] == 3'b111 )
begin // CP
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
else
begin
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
end
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
if (Z16 == 1'b1 )
begin
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
end
end
else
begin
F_Out[Flag_Z] = 1'b0;
end // else: !if(Q_t[7:0] == 8'b00000000 )
F_Out[Flag_S] = Q_t[7];
case (ALU_Op[2:0])
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
;
default :
F_Out[Flag_P] = ~(^Q_t);
endcase // case(ALU_Op[2:0])
if (Arith16 == 1'b1 )
begin
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
F_Out[Flag_P] = F_In[Flag_P];
end
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
4'b1100 :
begin
// DAA
F_Out[Flag_H] = F_In[Flag_H];
F_Out[Flag_C] = F_In[Flag_C];
DAA_Q[7:0] = BusA;
DAA_Q[8] = 1'b0;
if (F_In[Flag_N] == 1'b0 )
begin
// After addition
// Alow > 9 || H == 1
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if ((DAA_Q[3:0] > 9) )
begin
F_Out[Flag_H] = 1'b1;
end
else
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q = DAA_Q + 6;
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
// new Ahigh > 9 || C == 1
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q + 96; // 0x60
end
end
else
begin
// After subtraction
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
begin
if (DAA_Q[3:0] > 5 )
begin
F_Out[Flag_H] = 1'b0;
end
DAA_Q[7:0] = DAA_Q[7:0] - 6;
end
if (BusA > 153 || F_In[Flag_C] == 1'b1 )
begin
DAA_Q = DAA_Q - 352; // 0x160
end
end // else: !if(F_In[Flag_N] == 1'b0 )
F_Out[Flag_X] = DAA_Q[3];
F_Out[Flag_Y] = DAA_Q[5];
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
Q_t = DAA_Q[7:0];
if (DAA_Q[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = DAA_Q[7];
F_Out[Flag_P] = ~ (^DAA_Q);
end // case: 4'b1100
4'b1101, 4'b1110 :
begin
// RLD, RRD
Q_t[7:4] = BusA[7:4];
if (ALU_Op[0] == 1'b1 )
begin
Q_t[3:0] = BusB[7:4];
end
else
begin
Q_t[3:0] = BusB[3:0];
end
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_S] = Q_t[7];
F_Out[Flag_P] = ~(^Q_t);
end // case: when 4'b1101, 4'b1110
4'b1001 :
begin
// BIT
Q_t[7:0] = BusB & BitMask;
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
F_Out[Flag_P] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
F_Out[Flag_P] = 1'b0;
end
F_Out[Flag_H] = 1'b1;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = 1'b0;
F_Out[Flag_Y] = 1'b0;
if (IR[2:0] != 3'b110 )
begin
F_Out[Flag_X] = BusB[3];
F_Out[Flag_Y] = BusB[5];
end
end // case: when 4'b1001
4'b1010 :
// SET
Q_t[7:0] = BusB | BitMask;
4'b1011 :
// RES
Q_t[7:0] = BusB & ~ BitMask;
4'b1000 :
begin
// ROT
case (IR[5:3])
3'b000 : // RLC
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = BusA[7];
F_Out[Flag_C] = BusA[7];
end
3'b010 : // RL
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = F_In[Flag_C];
F_Out[Flag_C] = BusA[7];
end
3'b001 : // RRC
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[0];
F_Out[Flag_C] = BusA[0];
end
3'b011 : // RR
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = F_In[Flag_C];
F_Out[Flag_C] = BusA[0];
end
3'b100 : // SLA
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b0;
F_Out[Flag_C] = BusA[7];
end
3'b110 : // SLL (Undocumented) / SWAP
begin
if (Mode == 3 )
begin
Q_t[7:4] = BusA[3:0];
Q_t[3:0] = BusA[7:4];
F_Out[Flag_C] = 1'b0;
end
else
begin
Q_t[7:1] = BusA[6:0];
Q_t[0] = 1'b1;
F_Out[Flag_C] = BusA[7];
end // else: !if(Mode == 3 )
end // case: 3'b110
3'b101 : // SRA
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = BusA[7];
F_Out[Flag_C] = BusA[0];
end
default : // SRL
begin
Q_t[6:0] = BusA[7:1];
Q_t[7] = 1'b0;
F_Out[Flag_C] = BusA[0];
end
endcase // case(IR[5:3])
F_Out[Flag_H] = 1'b0;
F_Out[Flag_N] = 1'b0;
F_Out[Flag_X] = Q_t[3];
F_Out[Flag_Y] = Q_t[5];
F_Out[Flag_S] = Q_t[7];
if (Q_t[7:0] == 8'b00000000 )
begin
F_Out[Flag_Z] = 1'b1;
end
else
begin
F_Out[Flag_Z] = 1'b0;
end
F_Out[Flag_P] = ~(^Q_t);
if (ISet == 2'b00 )
begin
F_Out[Flag_P] = F_In[Flag_P];
F_Out[Flag_S] = F_In[Flag_S];
F_Out[Flag_Z] = F_In[Flag_Z];
end
end // case: 4'b1000
default :
;
endcase // case(ALU_Op)
Q = Q_t;
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
endmodule // T80_ALU
|
//==============================================================================
// File: $URL: svn+ssh://[email protected]/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/HardRegister.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2005-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//------------------------------------------------------------------------------
// Module: HardRegister
// Desc: A register which should not be removed by synthesis
// Author: <a href="http://www.gdgib.com/">Greg Gibeling</a>
// Version: $Revision: 26904 $
//------------------------------------------------------------------------------
module HardRegister(Clock, Reset, Set, Enable, In, Out) /* synthesis syn_hier = "hard" */;
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Width = 32,
Initial = {Width{1'bx}},
AsyncReset = 0,
AsyncSet = 0,
ResetValue = {Width{1'b0}},
SetValue = {Width{1'b1}};
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Inputs & Outputs
//--------------------------------------------------------------------------
input Clock, Enable, Reset, Set;
input [Width-1:0] In;
output reg [Width-1:0] Out = Initial /* synthesis syn_keep = 1 */;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Behavioral Register
//--------------------------------------------------------------------------
generate if (AsyncReset) begin:AR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Reset or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock or posedge Reset) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end else begin:SR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end endgenerate
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfrbp (
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFRBP_BLACKBOX_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txethmac.v ////
/// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8 2003/01/30 13:33:24 mohor
// When padding was enabled and crc disabled, frame was not ended correctly.
//
// Revision 1.7 2002/02/26 16:24:01 mohor
// RetryCntLatched was unused and removed from design
//
// Revision 1.6 2002/02/22 12:56:35 mohor
// Retry is not activated when a Tx Underrun occured
//
// Revision 1.5 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:08 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:58 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, DeferIndication, StatePreamble, StateData
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxEndFrm; // Transmit packet end frame
input TxUnderRun; // Transmit packet under-run
input [7:0] TxData; // Transmit packet data byte
input CarrierSense; // Carrier sense (synchronized)
input Collision; // Collision (synchronized)
input Pad; // Pad enable (from register)
input CrcEn; // Crc enable (from register)
input FullD; // Full duplex (from register)
input HugEn; // Huge packets enable (from register)
input DlyCrcEn; // Delayed Crc enabled (from register)
input [15:0] MinFL; // Minimum frame length (from register)
input [15:0] MaxFL; // Maximum frame length (from register)
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid; // Valid collision window (from register)
input [3:0] MaxRet; // Maximum retry number (from register)
input NoBckof; // No backoff (from register)
input ExDfrEn; // Excessive defferal enable (from register)
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxRetry; // Transmit packet retry (to RISC)
output TxAbort; // Transmit packet abort (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output DeferIndication;
output StatePreamble;
output [1:0] StateData;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxRetry;
reg TxAbort;
reg TxUsedData;
reg WillTransmit;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
wire StartFCS;
wire StartJam;
wire StartDefer;
wire StartBackoff;
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePAD;
wire StateFCS;
wire StateJam;
wire StateJam_q;
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire UnderRun;
wire TooBig;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq15;
wire NibbleMinFl;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire MaxFrame;
wire RetryMax;
wire RandomEq0;
wire RandomEqByteCnt;
wire PacketFinished_d;
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign StateSFD = StatePreamble & NibCntEq15;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StopExcessiveDeferOccured <= 1'b0;
else
begin
if(~TxStartFrm)
StopExcessiveDeferOccured <= 1'b0;
else
if(ExcessiveDeferOccured)
StopExcessiveDeferOccured <= 1'b1;
end
end
// Collision Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ColWindow <= 1'b1;
else
begin
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
ColWindow <= 1'b0;
else
if(StateIdle | StateIPG)
ColWindow <= 1'b1;
end
end
// Start Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StatusLatch <= 1'b0;
else
begin
if(~TxStartFrm)
StatusLatch <= 1'b0;
else
if(ExcessiveDeferOccured | StateIdle)
StatusLatch <= 1'b1;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= 1'b0;
else
TxUsedData <= |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxDone <= 1'b0;
else
if(StartTxDone)
TxDone <= 1'b1;
end
end
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRetry <= 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxRetry <= 1'b0;
else
if(StartTxRetry)
TxRetry <= 1'b1;
end
end
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxAbort <= 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
TxAbort <= 1'b0;
else
if(StartTxAbort)
TxAbort <= 1'b1;
end
end
// Retry counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCnt[3:0] <= 4'h0;
else
begin
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
RetryCnt[3:0] <= 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= RetryCnt[3:0] + 1;
end
end
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
Crc or NibCntEq15)
begin
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateFCS)
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
else
if(StateJam)
MTxD_d[3:0] = 4'h9; // Jam pattern
else
if(StatePreamble)
if(NibCntEq15)
MTxD_d[3:0] = 4'hd; // SFD
else
MTxD_d[3:0] = 4'h5; // Preamble
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= 1'b0;
else
MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= 4'h0;
else
MTxD[3:0] <= MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= 1'b0;
else
MTxErr <= TooBig | UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= 1'b0;
else
WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= 1'b0;
PacketFinished_q <= 1'b0;
end
else
begin
PacketFinished <= PacketFinished_d;
PacketFinished_q <= PacketFinished;
end
end
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
.DlyCrcCnt(DlyCrcCnt)
);
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateFCS;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Depth 2 FIFO
module FIFO2(CLK,
RST_N,
D_IN,
ENQ,
FULL_N,
D_OUT,
DEQ,
EMPTY_N,
CLR);
parameter width = 1;
parameter guarded = 1;
input CLK ;
input RST_N ;
input [width - 1 : 0] D_IN;
input ENQ;
input DEQ;
input CLR ;
output FULL_N;
output EMPTY_N;
output [width - 1 : 0] D_OUT;
reg full_reg;
reg empty_reg;
reg [width - 1 : 0] data0_reg;
reg [width - 1 : 0] data1_reg;
assign FULL_N = full_reg ;
assign EMPTY_N = empty_reg ;
assign D_OUT = data0_reg ;
// Optimize the loading logic since state encoding is not power of 2!
wire d0di = (ENQ && ! empty_reg ) || ( ENQ && DEQ && full_reg ) ;
wire d0d1 = DEQ && ! full_reg ;
wire d0h = ((! DEQ) && (! ENQ )) || (!DEQ && empty_reg ) || ( ! ENQ &&full_reg) ;
wire d1di = ENQ & empty_reg ;
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial
begin
data0_reg = {((width + 1)/2) {2'b10}} ;
data1_reg = {((width + 1)/2) {2'b10}} ;
empty_reg = 1'b0;
full_reg = 1'b1;
end // initial begin
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
always@(posedge CLK /* or negedge RST_N */)
begin
if (!RST_N)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (RST_N == 0)
else
begin
if (CLR)
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b0;
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
end // if (CLR)
else if ( ENQ && ! DEQ ) // just enq
begin
empty_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
full_reg <= `BSV_ASSIGNMENT_DELAY ! empty_reg ;
end
else if ( DEQ && ! ENQ )
begin
full_reg <= `BSV_ASSIGNMENT_DELAY 1'b1;
empty_reg <= `BSV_ASSIGNMENT_DELAY ! full_reg;
end // if ( DEQ && ! ENQ )
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
always@(posedge CLK /* or negedge RST_N */ )
begin
// Following section initializes the data registers which
// may be desired only in some situations.
// Uncomment to initialize array
/*
if (!RST_N)
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
data1_reg <= `BSV_ASSIGNMENT_DELAY {width {1'b0}} ;
end
else
*/
begin
data0_reg <= `BSV_ASSIGNMENT_DELAY
{width{d0di}} & D_IN | {width{d0d1}} & data1_reg | {width{d0h}} & data0_reg ;
data1_reg <= `BSV_ASSIGNMENT_DELAY
d1di ? D_IN : data1_reg ;
end // else: !if(RST_N == 0)
end // always@ (posedge CLK or negedge RST_N)
// synopsys translate_off
always@(posedge CLK)
begin: error_checks
reg deqerror, enqerror ;
deqerror = 0;
enqerror = 0;
if ( RST_N )
begin
if ( ! empty_reg && DEQ )
begin
deqerror = 1;
$display( "Warning: FIFO2: %m -- Dequeuing from empty fifo" ) ;
end
if ( ! full_reg && ENQ && (!DEQ || guarded) )
begin
enqerror = 1;
$display( "Warning: FIFO2: %m -- Enqueuing to a full fifo" ) ;
end
end
end // always@ (posedge CLK)
// synopsys translate_on
endmodule
|
// megafunction wizard: %ALTFP_COMPARE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_compare
// ============================================================
// File Name: acl_fp_cmp.v
// Megafunction Name(s):
// altfp_compare
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_compare CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=3 WIDTH_EXP=8 WIDTH_MAN=23 aeb agb ageb alb aleb aneb clk_en clock dataa datab unordered
//VERSION_BEGIN 10.0SP1 cbx_altfp_compare 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_compare 4 reg 25
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_cmp_altfp_compare_6me
(
aeb,
agb,
ageb,
alb,
aleb,
aneb,
clk_en,
clock,
dataa,
datab,
unordered) ;
output aeb;
output agb;
output ageb;
output alb;
output aleb;
output aneb;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output unordered;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg aligned_dataa_sign_adjusted_w_dffe2;
reg aligned_dataa_sign_dffe1;
reg aligned_datab_sign_adjusted_w_dffe2;
reg aligned_datab_sign_dffe1;
reg both_inputs_zero_dffe2;
reg exp_a_all_one_w_dffe1;
reg exp_a_not_zero_w_dffe1;
reg exp_aeb_w_dffe2;
reg exp_agb_w_dffe2;
reg exp_b_all_one_w_dffe1;
reg exp_b_not_zero_w_dffe1;
reg flip_outputs_dffe2;
reg input_dataa_nan_dffe2;
reg input_datab_nan_dffe2;
reg [1:0] man_a_not_zero_w_dffe1;
reg [1:0] man_b_not_zero_w_dffe1;
reg out_aeb_w_dffe3;
reg out_agb_w_dffe3;
reg out_ageb_w_dffe3;
reg out_alb_w_dffe3;
reg out_aleb_w_dffe3;
reg out_aneb_w_dffe3;
reg out_unordered_w_dffe3;
wire wire_cmpr1_aeb;
wire wire_cmpr1_agb;
wire wire_cmpr2_aeb;
wire wire_cmpr2_agb;
wire wire_cmpr3_aeb;
wire wire_cmpr3_agb;
wire wire_cmpr4_aeb;
wire wire_cmpr4_agb;
wire aclr;
wire aligned_dataa_sign_adjusted_dffe2_wi;
wire aligned_dataa_sign_adjusted_dffe2_wo;
wire aligned_dataa_sign_adjusted_w;
wire aligned_dataa_sign_dffe1_wi;
wire aligned_dataa_sign_dffe1_wo;
wire aligned_dataa_sign_w;
wire [30:0] aligned_dataa_w;
wire aligned_datab_sign_adjusted_dffe2_wi;
wire aligned_datab_sign_adjusted_dffe2_wo;
wire aligned_datab_sign_adjusted_w;
wire aligned_datab_sign_dffe1_wi;
wire aligned_datab_sign_dffe1_wo;
wire aligned_datab_sign_w;
wire [30:0] aligned_datab_w;
wire both_inputs_zero;
wire both_inputs_zero_dffe2_wi;
wire both_inputs_zero_dffe2_wo;
wire exp_a_all_one_dffe1_wi;
wire exp_a_all_one_dffe1_wo;
wire [7:0] exp_a_all_one_w;
wire exp_a_not_zero_dffe1_wi;
wire exp_a_not_zero_dffe1_wo;
wire [7:0] exp_a_not_zero_w;
wire [3:0] exp_aeb;
wire [3:0] exp_aeb_tmp_w;
wire exp_aeb_w;
wire exp_aeb_w_dffe2_wi;
wire exp_aeb_w_dffe2_wo;
wire [3:0] exp_agb;
wire [3:0] exp_agb_tmp_w;
wire exp_agb_w;
wire exp_agb_w_dffe2_wi;
wire exp_agb_w_dffe2_wo;
wire exp_b_all_one_dffe1_wi;
wire exp_b_all_one_dffe1_wo;
wire [7:0] exp_b_all_one_w;
wire exp_b_not_zero_dffe1_wi;
wire exp_b_not_zero_dffe1_wo;
wire [7:0] exp_b_not_zero_w;
wire [2:0] exp_eq_grp;
wire [3:0] exp_eq_gt_grp;
wire flip_outputs_dffe2_wi;
wire flip_outputs_dffe2_wo;
wire flip_outputs_w;
wire input_dataa_nan_dffe2_wi;
wire input_dataa_nan_dffe2_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_w;
wire input_datab_nan_dffe2_wi;
wire input_datab_nan_dffe2_wo;
wire input_datab_nan_w;
wire input_datab_zero_w;
wire [1:0] man_a_not_zero_dffe1_wi;
wire [1:0] man_a_not_zero_dffe1_wo;
wire [1:0] man_a_not_zero_merge_w;
wire [22:0] man_a_not_zero_w;
wire [1:0] man_b_not_zero_dffe1_wi;
wire [1:0] man_b_not_zero_dffe1_wo;
wire [1:0] man_b_not_zero_merge_w;
wire [22:0] man_b_not_zero_w;
wire out_aeb_dffe3_wi;
wire out_aeb_dffe3_wo;
wire out_aeb_w;
wire out_agb_dffe3_wi;
wire out_agb_dffe3_wo;
wire out_agb_w;
wire out_ageb_dffe3_wi;
wire out_ageb_dffe3_wo;
wire out_ageb_w;
wire out_alb_dffe3_wi;
wire out_alb_dffe3_wo;
wire out_alb_w;
wire out_aleb_dffe3_wi;
wire out_aleb_dffe3_wo;
wire out_aleb_w;
wire out_aneb_dffe3_wi;
wire out_aneb_dffe3_wo;
wire out_aneb_w;
wire out_unordered_dffe3_wi;
wire out_unordered_dffe3_wo;
wire out_unordered_w;
// synopsys translate_off
initial
aligned_dataa_sign_adjusted_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_adjusted_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_adjusted_w_dffe2 <= aligned_dataa_sign_adjusted_dffe2_wi;
// synopsys translate_off
initial
aligned_dataa_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_dataa_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) aligned_dataa_sign_dffe1 <= aligned_dataa_sign_dffe1_wi;
// synopsys translate_off
initial
aligned_datab_sign_adjusted_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_adjusted_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_adjusted_w_dffe2 <= aligned_datab_sign_adjusted_dffe2_wi;
// synopsys translate_off
initial
aligned_datab_sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) aligned_datab_sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) aligned_datab_sign_dffe1 <= aligned_datab_sign_dffe1_wi;
// synopsys translate_off
initial
both_inputs_zero_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) both_inputs_zero_dffe2 <= 1'b0;
else if (clk_en == 1'b1) both_inputs_zero_dffe2 <= both_inputs_zero_dffe2_wi;
// synopsys translate_off
initial
exp_a_all_one_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_a_all_one_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_a_all_one_w_dffe1 <= exp_a_all_one_dffe1_wi;
// synopsys translate_off
initial
exp_a_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_a_not_zero_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_a_not_zero_w_dffe1 <= exp_a_not_zero_dffe1_wi;
// synopsys translate_off
initial
exp_aeb_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_aeb_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) exp_aeb_w_dffe2 <= exp_aeb_w_dffe2_wi;
// synopsys translate_off
initial
exp_agb_w_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_agb_w_dffe2 <= 1'b0;
else if (clk_en == 1'b1) exp_agb_w_dffe2 <= exp_agb_w_dffe2_wi;
// synopsys translate_off
initial
exp_b_all_one_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_b_all_one_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_b_all_one_w_dffe1 <= exp_b_all_one_dffe1_wi;
// synopsys translate_off
initial
exp_b_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_b_not_zero_w_dffe1 <= 1'b0;
else if (clk_en == 1'b1) exp_b_not_zero_w_dffe1 <= exp_b_not_zero_dffe1_wi;
// synopsys translate_off
initial
flip_outputs_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) flip_outputs_dffe2 <= 1'b0;
else if (clk_en == 1'b1) flip_outputs_dffe2 <= flip_outputs_dffe2_wi;
// synopsys translate_off
initial
input_dataa_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_dataa_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_dataa_nan_dffe2 <= input_dataa_nan_dffe2_wi;
// synopsys translate_off
initial
input_datab_nan_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_datab_nan_dffe2 <= 1'b0;
else if (clk_en == 1'b1) input_datab_nan_dffe2 <= input_datab_nan_dffe2_wi;
// synopsys translate_off
initial
man_a_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_a_not_zero_w_dffe1 <= 2'b0;
else if (clk_en == 1'b1) man_a_not_zero_w_dffe1 <= man_a_not_zero_dffe1_wi;
// synopsys translate_off
initial
man_b_not_zero_w_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_b_not_zero_w_dffe1 <= 2'b0;
else if (clk_en == 1'b1) man_b_not_zero_w_dffe1 <= man_b_not_zero_dffe1_wi;
// synopsys translate_off
initial
out_aeb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aeb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aeb_w_dffe3 <= out_aeb_dffe3_wi;
// synopsys translate_off
initial
out_agb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_agb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_agb_w_dffe3 <= out_agb_dffe3_wi;
// synopsys translate_off
initial
out_ageb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_ageb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_ageb_w_dffe3 <= out_ageb_dffe3_wi;
// synopsys translate_off
initial
out_alb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_alb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_alb_w_dffe3 <= out_alb_dffe3_wi;
// synopsys translate_off
initial
out_aleb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aleb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aleb_w_dffe3 <= out_aleb_dffe3_wi;
// synopsys translate_off
initial
out_aneb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aneb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aneb_w_dffe3 <= out_aneb_dffe3_wi;
// synopsys translate_off
initial
out_unordered_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_unordered_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_unordered_w_dffe3 <= out_unordered_dffe3_wi;
lpm_compare cmpr1
(
.aclr(aclr),
.aeb(wire_cmpr1_aeb),
.agb(wire_cmpr1_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[30:23]),
.datab(aligned_datab_w[30:23]));
defparam
cmpr1.lpm_pipeline = 1,
cmpr1.lpm_representation = "UNSIGNED",
cmpr1.lpm_width = 8,
cmpr1.lpm_type = "lpm_compare";
lpm_compare cmpr2
(
.aclr(aclr),
.aeb(wire_cmpr2_aeb),
.agb(wire_cmpr2_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[22:15]),
.datab(aligned_datab_w[22:15]));
defparam
cmpr2.lpm_pipeline = 1,
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 8,
cmpr2.lpm_type = "lpm_compare";
lpm_compare cmpr3
(
.aclr(aclr),
.aeb(wire_cmpr3_aeb),
.agb(wire_cmpr3_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[14:7]),
.datab(aligned_datab_w[14:7]));
defparam
cmpr3.lpm_pipeline = 1,
cmpr3.lpm_representation = "UNSIGNED",
cmpr3.lpm_width = 8,
cmpr3.lpm_type = "lpm_compare";
lpm_compare cmpr4
(
.aclr(aclr),
.aeb(wire_cmpr4_aeb),
.agb(wire_cmpr4_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.clken(clk_en),
.clock(clock),
.dataa(aligned_dataa_w[6:0]),
.datab(aligned_datab_w[6:0]));
defparam
cmpr4.lpm_pipeline = 1,
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 7,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
aeb = out_aeb_dffe3_wo,
agb = out_agb_dffe3_wo,
ageb = out_ageb_dffe3_wo,
alb = out_alb_dffe3_wo,
aleb = out_aleb_dffe3_wo,
aligned_dataa_sign_adjusted_dffe2_wi = aligned_dataa_sign_adjusted_w,
aligned_dataa_sign_adjusted_dffe2_wo = aligned_dataa_sign_adjusted_w_dffe2,
aligned_dataa_sign_adjusted_w = (aligned_dataa_sign_dffe1_wo & (~ input_dataa_zero_w)),
aligned_dataa_sign_dffe1_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe1_wo = aligned_dataa_sign_dffe1,
aligned_dataa_sign_w = dataa[31],
aligned_dataa_w = {dataa[30:0]},
aligned_datab_sign_adjusted_dffe2_wi = aligned_datab_sign_adjusted_w,
aligned_datab_sign_adjusted_dffe2_wo = aligned_datab_sign_adjusted_w_dffe2,
aligned_datab_sign_adjusted_w = (aligned_datab_sign_dffe1_wo & (~ input_datab_zero_w)),
aligned_datab_sign_dffe1_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe1_wo = aligned_datab_sign_dffe1,
aligned_datab_sign_w = datab[31],
aligned_datab_w = {datab[30:0]},
aneb = out_aneb_dffe3_wo,
both_inputs_zero = (input_dataa_zero_w & input_datab_zero_w),
both_inputs_zero_dffe2_wi = both_inputs_zero,
both_inputs_zero_dffe2_wo = both_inputs_zero_dffe2,
exp_a_all_one_dffe1_wi = exp_a_all_one_w[7],
exp_a_all_one_dffe1_wo = exp_a_all_one_w_dffe1,
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_dffe1_wi = exp_a_not_zero_w[7],
exp_a_not_zero_dffe1_wo = exp_a_not_zero_w_dffe1,
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_aeb = {wire_cmpr4_aeb, wire_cmpr3_aeb, wire_cmpr2_aeb, wire_cmpr1_aeb},
exp_aeb_tmp_w = {(exp_aeb[3] & exp_aeb_tmp_w[2]), (exp_aeb[2] & exp_aeb_tmp_w[1]), (exp_aeb[1] & exp_aeb_tmp_w[0]), exp_aeb[0]},
exp_aeb_w = exp_aeb_tmp_w[3],
exp_aeb_w_dffe2_wi = exp_aeb_w,
exp_aeb_w_dffe2_wo = exp_aeb_w_dffe2,
exp_agb = {wire_cmpr4_agb, wire_cmpr3_agb, wire_cmpr2_agb, wire_cmpr1_agb},
exp_agb_tmp_w = {(exp_agb_tmp_w[2] | exp_eq_gt_grp[3]), (exp_agb_tmp_w[1] | exp_eq_gt_grp[2]), (exp_agb_tmp_w[0] | exp_eq_gt_grp[1]), exp_eq_gt_grp[0]},
exp_agb_w = exp_agb_tmp_w[3],
exp_agb_w_dffe2_wi = exp_agb_w,
exp_agb_w_dffe2_wo = exp_agb_w_dffe2,
exp_b_all_one_dffe1_wi = exp_b_all_one_w[7],
exp_b_all_one_dffe1_wo = exp_b_all_one_w_dffe1,
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_dffe1_wi = exp_b_not_zero_w[7],
exp_b_not_zero_dffe1_wo = exp_b_not_zero_w_dffe1,
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_eq_grp = {(exp_eq_grp[1] & exp_aeb[2]), (exp_eq_grp[0] & exp_aeb[1]), exp_aeb[0]},
exp_eq_gt_grp = {(exp_eq_grp[2] & exp_agb[3]), (exp_eq_grp[1] & exp_agb[2]), (exp_eq_grp[0] & exp_agb[1]), exp_agb[0]},
flip_outputs_dffe2_wi = flip_outputs_w,
flip_outputs_dffe2_wo = flip_outputs_dffe2,
flip_outputs_w = (aligned_dataa_sign_adjusted_w & aligned_datab_sign_adjusted_w),
input_dataa_nan_dffe2_wi = input_dataa_nan_w,
input_dataa_nan_dffe2_wo = input_dataa_nan_dffe2,
input_dataa_nan_w = (exp_a_all_one_dffe1_wo & man_a_not_zero_merge_w[1]),
input_dataa_zero_w = (~ exp_a_not_zero_dffe1_wo),
input_datab_nan_dffe2_wi = input_datab_nan_w,
input_datab_nan_dffe2_wo = input_datab_nan_dffe2,
input_datab_nan_w = (exp_b_all_one_dffe1_wo & man_b_not_zero_merge_w[1]),
input_datab_zero_w = (~ exp_b_not_zero_dffe1_wo),
man_a_not_zero_dffe1_wi = {man_a_not_zero_w[22], man_a_not_zero_w[11]},
man_a_not_zero_dffe1_wo = man_a_not_zero_w_dffe1,
man_a_not_zero_merge_w = {(man_a_not_zero_dffe1_wo[1] | man_a_not_zero_merge_w[0]), man_a_not_zero_dffe1_wo[0]},
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), dataa[12], (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_not_zero_dffe1_wi = {man_b_not_zero_w[22], man_b_not_zero_w[11]},
man_b_not_zero_dffe1_wo = man_b_not_zero_w_dffe1,
man_b_not_zero_merge_w = {(man_b_not_zero_dffe1_wo[1] | man_b_not_zero_merge_w[0]), man_b_not_zero_dffe1_wo[0]},
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), datab[12], (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
out_aeb_dffe3_wi = out_aeb_w,
out_aeb_dffe3_wo = out_aeb_w_dffe3,
out_aeb_w = ((((~ (aligned_dataa_sign_adjusted_dffe2_wo ^ aligned_datab_sign_adjusted_dffe2_wo)) & exp_aeb_w_dffe2_wo) | both_inputs_zero_dffe2_wo) & (~ out_unordered_w)),
out_agb_dffe3_wi = out_agb_w,
out_agb_dffe3_wo = out_agb_w_dffe3,
out_agb_w = (((((~ aligned_dataa_sign_adjusted_dffe2_wo) & aligned_datab_sign_adjusted_dffe2_wo) | ((exp_agb_w_dffe2_wo & (~ aligned_dataa_sign_adjusted_dffe2_wo)) & (~ both_inputs_zero_dffe2_wo))) | ((flip_outputs_dffe2_wo & (~ exp_agb_w_dffe2_wo)) & (~ out_aeb_w))) & (~ out_unordered_w)),
out_ageb_dffe3_wi = out_ageb_w,
out_ageb_dffe3_wo = out_ageb_w_dffe3,
out_ageb_w = ((out_agb_w | out_aeb_w) & (~ out_unordered_w)),
out_alb_dffe3_wi = out_alb_w,
out_alb_dffe3_wo = out_alb_w_dffe3,
out_alb_w = (((~ out_agb_w) & (~ out_aeb_w)) & (~ out_unordered_w)),
out_aleb_dffe3_wi = out_aleb_w,
out_aleb_dffe3_wo = out_aleb_w_dffe3,
out_aleb_w = ((out_alb_w | out_aeb_w) & (~ out_unordered_w)),
out_aneb_dffe3_wi = out_aneb_w,
out_aneb_dffe3_wo = out_aneb_w_dffe3,
out_aneb_w = ((~ out_aeb_w) & (~ out_unordered_w)),
out_unordered_dffe3_wi = out_unordered_w,
out_unordered_dffe3_wo = out_unordered_w_dffe3,
out_unordered_w = (input_dataa_nan_dffe2_wo | input_datab_nan_dffe2_wo),
unordered = out_unordered_dffe3_wo;
endmodule //acl_fp_cmp_altfp_compare_6me
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_cmp (
enable,
clock,
dataa,
datab,
result);
parameter COMPARISON_MODE = 0;
parameter UNORDERED_MODE = 0;
// The meaning of mode is:
// 0 -> ==
// 1 -> !=
// 2 -> >=
// 3 -> >
// 4 -> <=
// 5 -> <
input enable;
input clock;
input [31:0] dataa;
input [31:0] datab;
output reg result;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire sub_wire6;
wire aeb = sub_wire0;
wire aleb = sub_wire1;
wire unordered = sub_wire2;
wire ageb = sub_wire3;
wire alb = sub_wire4;
wire agb = sub_wire5;
wire aneb = sub_wire6;
acl_fp_cmp_altfp_compare_6me acl_fp_cmp_altfp_compare_6me_component (
.clk_en (enable),
.clock (clock),
.datab (datab),
.dataa (dataa),
.aeb (sub_wire0),
.aleb (sub_wire1),
.unordered (sub_wire2),
.ageb (sub_wire3),
.alb (sub_wire4),
.agb (sub_wire5),
.aneb (sub_wire6));
always@(*)
begin
case(COMPARISON_MODE)
1: result = (UNORDERED_MODE == 0) ? (aneb & ~unordered) : (aneb | unordered);
2: result = (UNORDERED_MODE == 0) ? (ageb & ~unordered) : (ageb | unordered);
3: result = (UNORDERED_MODE == 0) ? (agb & ~unordered) : (agb | unordered);
4: result = (UNORDERED_MODE == 0) ? (aleb & ~unordered) : (aleb | unordered);
5: result = (UNORDERED_MODE == 0) ? (alb & ~unordered) : (alb | unordered);
6: result = (UNORDERED_MODE == 0) ? (~unordered) : unordered;
default:
// default is the same as COMPARISON_MODE=0 and performs equality checking.
begin
result = (UNORDERED_MODE == 0) ? (aeb & ~unordered) : (aeb | unordered);
end
endcase
end
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "3"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
// Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
// Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
// Retrieval info: USED_PORT: aneb 0 0 0 0 OUTPUT NODEFVAL "aneb"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: unordered 0 0 0 0 OUTPUT NODEFVAL "unordered"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
// Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
// Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
// Retrieval info: CONNECT: aneb 0 0 0 0 @aneb 0 0 0 0
// Retrieval info: CONNECT: unordered 0 0 0 0 @unordered 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_cmp_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
// file: clk_wiz_v3_3_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module clk_wiz_v3_3_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 40.000*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
reg RESET = 0;
wire LOCKED;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "reset";
RESET = 1;
#(PER1*6);
RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_3_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.RESET (RESET),
.LOCKED (LOCKED));
endmodule
|
Require Import Coq.Lists.List.
Require Import Coq.omega.Omega.
Require Import Coq.Arith.Peano_dec.
Require Import Coq.Classes.Morphisms.
Require Import Crypto.Tactics.VerdiTactics.
Require Import Coq.Numbers.Natural.Peano.NPeano.
Require Import Crypto.Util.NatUtil.
Require Export Crypto.Util.FixCoqMistakes.
Create HintDb distr_length discriminated.
Create HintDb simpl_set_nth discriminated.
Create HintDb simpl_update_nth discriminated.
Create HintDb simpl_nth_default discriminated.
Create HintDb simpl_nth_error discriminated.
Create HintDb simpl_firstn discriminated.
Create HintDb simpl_skipn discriminated.
Create HintDb simpl_fold_right discriminated.
Create HintDb simpl_sum_firstn discriminated.
Create HintDb pull_nth_error discriminated.
Create HintDb push_nth_error discriminated.
Create HintDb pull_nth_default discriminated.
Create HintDb push_nth_default discriminated.
Create HintDb pull_firstn discriminated.
Create HintDb push_firstn discriminated.
Create HintDb pull_skipn discriminated.
Create HintDb push_skipn discriminated.
Create HintDb pull_update_nth discriminated.
Create HintDb push_update_nth discriminated.
Create HintDb znonzero discriminated.
Hint Extern 1 => progress autorewrite with distr_length in * : distr_length.
Ltac distr_length := autorewrite with distr_length in *;
try solve [simpl in *; omega].
Module Export List.
Local Set Implicit Arguments.
Import ListNotations.
(** From the 8.6 Standard Library *)
Section Elts.
Variable A : Type.
(** Results about [nth_error] *)
Lemma nth_error_In l n (x : A) : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
End Elts.
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Lemma map_cons (x:A)(l:list A) : map f (x::l) = (f x) :: (map f l).
Proof.
reflexivity.
Qed.
End Map.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len; simpl; intros.
- rewrite <- plus_n_O. split;[easy|].
intros (H,H'). apply (Lt.lt_irrefl _ (Lt.le_lt_trans _ _ _ H H')).
- rewrite IHlen, <- plus_n_Sm; simpl; split.
* intros [H|H]; subst; intuition auto with arith.
* intros (H,H'). destruct (Lt.le_lt_or_eq _ _ H); intuition.
Qed.
Section Facts.
Variable A : Type.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l=[].
Proof.
split; [now destruct l | now intros ->].
Qed.
End Facts.
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
End Repeat.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (_,_) H).
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
induction l; simpl; intros; auto.
destruct p; destruct a; destruct (split l); simpl in *.
destruct H.
injection H; auto.
right; apply (IHl (_,_) H).
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
induction l.
destruct n; destruct d; simpl; auto.
destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
induction l; simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
induction l; simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
let (l1,l2) := split l in combine l1 l2 = l.
Proof.
induction l.
simpl; auto.
destruct a; simpl.
destruct (split l); simpl in *.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
induction l, l'; simpl; trivial; try discriminate.
now intros [= ->%IHl].
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto; intros.
contradiction.
destruct H.
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
induction l.
simpl; intros; contradiction.
destruct l'; simpl; auto; intros.
destruct H.
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
induction l.
simpl; auto.
destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
induction l; destruct l'; intros; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
induction l;
[ simpl; tauto
| simpl; intros; apply in_or_app; destruct H;
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
split; [ | intros; apply in_prod; intuition ].
induction l; simpl; intros.
intuition.
destruct (in_app_or _ _ _ H); clear H.
destruct (in_map_iff (fun y : B => (a, y)) l' (x,y)) as (H1,_).
destruct (H1 H0) as (z,(H2,H3)); clear H0 H1.
injection H2 as -> ->; intuition.
intuition.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
induction l; simpl; auto.
intros.
rewrite app_length.
rewrite map_length.
auto.
Qed.
End ListPairs.
Section Cutting.
Variable A : Type.
Local Notation firstn := (@firstn A).
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. apply Peano.le_S_n in H. f_equal. apply iHk, H.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | destruct l as [|x xs]; simpl].
- auto with arith.
- apply le_n_S, iHk.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. induction l as [|x xs Hrec].
- simpl. intros n H. apply le_n_0_eq in H. rewrite <- H. now simpl.
- destruct n.
* now simpl.
* simpl. intro H. apply le_S_n in H. now rewrite (Hrec n H).
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* unfold List.firstn at 2, length. now rewrite 2!app_nil_l, <- minus_n_O.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold List.firstn at 2. rewrite <- plus_n_O, app_nil_r.
rewrite firstn_app. rewrite <- minus_diag_reverse.
unfold List.firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. auto with arith.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
auto with arith.
rewrite H0, firstn_all2; [reflexivity | auto with arith].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- destruct i.
* intro. now simpl.
* destruct j.
+ now simpl.
+ simpl. f_equal. apply Hl.
Qed.
End Cutting.
End List.
Hint Rewrite
@app_length
@rev_length
@map_length
@seq_length
@fold_left_length
@split_length_l
@split_length_r
@firstn_length
@combine_length
@prod_length
: distr_length.
Hint Rewrite @firstn_skipn : simpl_firstn.
Hint Rewrite @firstn_skipn : simpl_skipn.
Hint Rewrite @firstn_nil @firstn_cons @List.firstn_all @firstn_O @firstn_app_2 @List.firstn_firstn : push_firstn.
Hint Rewrite @firstn_nil @firstn_cons @List.firstn_all @firstn_O @firstn_app_2 @List.firstn_firstn : simpl_firstn.
Hint Rewrite @firstn_app : push_firstn.
Hint Rewrite <- @firstn_cons @firstn_app @List.firstn_firstn : pull_firstn.
Hint Rewrite @firstn_all2 @removelast_firstn @firstn_removelast using omega : push_firstn.
Hint Rewrite @firstn_all2 @removelast_firstn @firstn_removelast using omega : simpl_firstn.
Local Arguments value / _ _.
Local Arguments error / _.
Definition sum_firstn l n := fold_right Z.add 0%Z (firstn n l).
Fixpoint map2 {A B C} (f : A -> B -> C) (la : list A) (lb : list B) : list C :=
match la with
| nil => nil
| a :: la' => match lb with
| nil => nil
| b :: lb' => f a b :: map2 f la' lb'
end
end.
(* xs[n] := f xs[n] *)
Fixpoint update_nth {T} n f (xs:list T) {struct n} :=
match n with
| O => match xs with
| nil => nil
| x'::xs' => f x'::xs'
end
| S n' => match xs with
| nil => nil
| x'::xs' => x'::update_nth n' f xs'
end
end.
(* xs[n] := x *)
Definition set_nth {T} n x (xs:list T)
:= update_nth n (fun _ => x) xs.
Definition splice_nth {T} n (x:T) xs := firstn n xs ++ x :: skipn (S n) xs.
Hint Unfold splice_nth.
Ltac boring :=
simpl; intuition auto with zarith datatypes;
repeat match goal with
| [ H : _ |- _ ] => rewrite H; clear H
| [ |- appcontext[match ?pf with end] ] => solve [ case pf ]
| _ => progress autounfold in *
| _ => progress autorewrite with core
| _ => progress simpl in *
| _ => progress intuition auto with zarith datatypes
end; eauto.
Ltac boring_list :=
repeat match goal with
| _ => progress boring
| _ => progress autorewrite with distr_length simpl_nth_default simpl_update_nth simpl_set_nth simpl_nth_error in *
end.
Lemma nth_default_cons : forall {T} (x u0 : T) us, nth_default x (u0 :: us) 0 = u0.
Proof. auto. Qed.
Hint Rewrite @nth_default_cons : simpl_nth_default.
Hint Rewrite @nth_default_cons : push_nth_default.
Lemma nth_default_cons_S : forall {A} us (u0 : A) n d,
nth_default d (u0 :: us) (S n) = nth_default d us n.
Proof. boring. Qed.
Hint Rewrite @nth_default_cons_S : simpl_nth_default.
Hint Rewrite @nth_default_cons_S : push_nth_default.
Lemma nth_default_nil : forall {T} n (d : T), nth_default d nil n = d.
Proof. induction n; boring. Qed.
Hint Rewrite @nth_default_nil : simpl_nth_default.
Hint Rewrite @nth_default_nil : push_nth_default.
Lemma nth_error_nil_error : forall {A} n, nth_error (@nil A) n = None.
Proof. induction n; boring. Qed.
Hint Rewrite @nth_error_nil_error : simpl_nth_error.
Ltac nth_tac' :=
intros; simpl in *; unfold error,value in *; repeat progress (match goal with
| [ |- context[nth_error nil ?n] ] => rewrite nth_error_nil_error
| [ H: ?x = Some _ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ H: ?x = None _ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ |- context[match ?x with Some _ => ?a | None => ?a end ] ] => destruct x
| [ |- context[match nth_error ?xs ?i with Some _ => _ | None => _ end ] ] => case_eq (nth_error xs i); intros
| [ |- context[(if lt_dec ?a ?b then _ else _) = _] ] => destruct (lt_dec a b)
| [ |- context[_ = (if lt_dec ?a ?b then _ else _)] ] => destruct (lt_dec a b)
| [ H: context[(if lt_dec ?a ?b then _ else _) = _] |- _ ] => destruct (lt_dec a b)
| [ H: context[_ = (if lt_dec ?a ?b then _ else _)] |- _ ] => destruct (lt_dec a b)
| [ H: _ /\ _ |- _ ] => destruct H
| [ H: Some _ = Some _ |- _ ] => injection H; clear H; intros; subst
| [ H: None = Some _ |- _ ] => inversion H
| [ H: Some _ = None |- _ ] => inversion H
| [ |- Some _ = Some _ ] => apply f_equal
end); eauto; try (autorewrite with list in *); try omega; eauto.
Lemma nth_error_map : forall A B (f:A->B) i xs y,
nth_error (map f xs) i = Some y ->
exists x, nth_error xs i = Some x /\ f x = y.
Proof.
induction i; destruct xs; nth_tac'.
Qed.
Lemma nth_error_seq : forall i start len,
nth_error (seq start len) i =
if lt_dec i len
then Some (start + i)
else None.
induction i; destruct len; nth_tac'; erewrite IHi; nth_tac'.
Qed.
Lemma nth_error_error_length : forall A i (xs:list A), nth_error xs i = None ->
i >= length xs.
Proof.
induction i; destruct xs; nth_tac'; try specialize (IHi _ H); omega.
Qed.
Lemma nth_error_value_length : forall A i (xs:list A) x, nth_error xs i = Some x ->
i < length xs.
Proof.
induction i; destruct xs; nth_tac'; try specialize (IHi _ _ H); omega.
Qed.
Lemma nth_error_length_error : forall A i (xs:list A),
i >= length xs ->
nth_error xs i = None.
Proof.
induction i; destruct xs; nth_tac'; rewrite IHi by omega; auto.
Qed.
Hint Resolve nth_error_length_error.
Hint Rewrite @nth_error_length_error using omega : simpl_nth_error.
Lemma map_nth_default : forall (A B : Type) (f : A -> B) n x y l,
(n < length l) -> nth_default y (map f l) n = f (nth_default x l n).
Proof.
intros.
unfold nth_default.
erewrite map_nth_error.
reflexivity.
nth_tac'.
pose proof (nth_error_error_length A n l H0).
omega.
Qed.
Lemma map_nil : forall A B (f : A -> B), map f nil = nil.
Proof. reflexivity. Qed.
(* Note: this is a duplicate of a lemma that exists in 8.5, included for
8.4 support *)
Lemma In_nth : forall {A} (x : A) d xs, In x xs ->
exists i, i < length xs /\ nth i xs d = x.
Proof.
induction xs; intros;
match goal with H : In _ _ |- _ => simpl in H; destruct H end.
+ subst. exists 0. simpl; split; auto || omega.
+ destruct IHxs as [i [ ]]; auto.
exists (S i).
split; auto; simpl; try omega.
Qed.
Hint Rewrite @map_nth_default using omega : push_nth_default.
Ltac nth_tac :=
repeat progress (try nth_tac'; try (match goal with
| [ H: nth_error (map _ _) _ = Some _ |- _ ] => destruct (nth_error_map _ _ _ _ _ _ H); clear H
| [ H: nth_error (seq _ _) _ = Some _ |- _ ] => rewrite nth_error_seq in H
| [H: nth_error _ _ = None |- _ ] => specialize (nth_error_error_length _ _ _ H); intro; clear H
end)).
Lemma app_cons_app_app : forall T xs (y:T) ys, xs ++ y :: ys = (xs ++ (y::nil)) ++ ys.
Proof. induction xs; boring. Qed.
Lemma unfold_set_nth {T} n x
: forall xs,
@set_nth T n x xs
= match n with
| O => match xs with
| nil => nil
| x'::xs' => x::xs'
end
| S n' => match xs with
| nil => nil
| x'::xs' => x'::set_nth n' x xs'
end
end.
Proof.
induction n; destruct xs; reflexivity.
Qed.
Lemma simpl_set_nth_0 {T} x
: forall xs,
@set_nth T 0 x xs
= match xs with
| nil => nil
| x'::xs' => x::xs'
end.
Proof. intro; rewrite unfold_set_nth; reflexivity. Qed.
Lemma simpl_set_nth_S {T} x n
: forall xs,
@set_nth T (S n) x xs
= match xs with
| nil => nil
| x'::xs' => x'::set_nth n x xs'
end.
Proof. intro; rewrite unfold_set_nth; reflexivity. Qed.
Hint Rewrite @simpl_set_nth_S @simpl_set_nth_0 : simpl_set_nth.
Lemma update_nth_ext {T} f g n
: forall xs, (forall x, nth_error xs n = Some x -> f x = g x)
-> @update_nth T n f xs = @update_nth T n g xs.
Proof.
induction n; destruct xs; simpl; intros H;
try rewrite IHn; try rewrite H;
try congruence; trivial.
Qed.
Global Instance update_nth_Proper {T}
: Proper (eq ==> pointwise_relation _ eq ==> eq ==> eq) (@update_nth T).
Proof. repeat intro; subst; apply update_nth_ext; trivial. Qed.
Lemma update_nth_id_eq_specific {T} f n
: forall (xs : list T) (H : forall x, nth_error xs n = Some x -> f x = x),
update_nth n f xs = xs.
Proof.
induction n; destruct xs; simpl; intros;
try rewrite IHn; try rewrite H; unfold value in *;
try congruence; assumption.
Qed.
Hint Rewrite @update_nth_id_eq_specific using congruence : simpl_update_nth.
Lemma update_nth_id_eq : forall {T} f (H : forall x, f x = x) n (xs : list T),
update_nth n f xs = xs.
Proof. intros; apply update_nth_id_eq_specific; trivial. Qed.
Hint Rewrite @update_nth_id_eq using congruence : simpl_update_nth.
Lemma update_nth_id : forall {T} n (xs : list T),
update_nth n (fun x => x) xs = xs.
Proof. intros; apply update_nth_id_eq; trivial. Qed.
Hint Rewrite @update_nth_id : simpl_update_nth.
Lemma nth_update_nth : forall m {T} (xs:list T) (n:nat) (f:T -> T),
nth_error (update_nth m f xs) n =
if eq_nat_dec n m
then option_map f (nth_error xs n)
else nth_error xs n.
Proof.
induction m.
{ destruct n, xs; auto. }
{ destruct xs, n; intros; simpl; auto;
[ | rewrite IHm ]; clear IHm;
edestruct eq_nat_dec; reflexivity. }
Qed.
Hint Rewrite @nth_update_nth : push_nth_error.
Hint Rewrite <- @nth_update_nth : pull_nth_error.
Lemma length_update_nth : forall {T} i f (xs:list T), length (update_nth i f xs) = length xs.
Proof.
induction i, xs; boring.
Qed.
Hint Rewrite @length_update_nth : distr_length.
(** TODO: this is in the stdlib in 8.5; remove this when we move to 8.5-only *)
Lemma nth_error_None : forall (A : Type) (l : list A) (n : nat), nth_error l n = None <-> length l <= n.
Proof.
intros A l n.
destruct (le_lt_dec (length l) n) as [H|H];
split; intro H';
try omega;
try (apply nth_error_length_error in H; tauto);
try (apply nth_error_error_length in H'; omega).
Qed.
(** TODO: this is in the stdlib in 8.5; remove this when we move to 8.5-only *)
Lemma nth_error_Some : forall (A : Type) (l : list A) (n : nat), nth_error l n <> None <-> n < length l.
Proof. intros; rewrite nth_error_None; split; omega. Qed.
Lemma nth_set_nth : forall m {T} (xs:list T) (n:nat) x,
nth_error (set_nth m x xs) n =
if eq_nat_dec n m
then (if lt_dec n (length xs) then Some x else None)
else nth_error xs n.
Proof.
intros; unfold set_nth; rewrite nth_update_nth.
destruct (nth_error xs n) eqn:?, (lt_dec n (length xs)) as [p|p];
rewrite <- nth_error_Some in p;
solve [ reflexivity
| exfalso; apply p; congruence ].
Qed.
Hint Rewrite @nth_set_nth : push_nth_error.
Lemma length_set_nth : forall {T} i x (xs:list T), length (set_nth i x xs) = length xs.
Proof. intros; apply length_update_nth. Qed.
Hint Rewrite @length_set_nth : distr_length.
Lemma nth_error_length_exists_value : forall {A} (i : nat) (xs : list A),
(i < length xs)%nat -> exists x, nth_error xs i = Some x.
Proof.
induction i, xs; boring; try omega.
Qed.
Lemma nth_error_length_not_error : forall {A} (i : nat) (xs : list A),
nth_error xs i = None -> (i < length xs)%nat -> False.
Proof.
intros.
destruct (nth_error_length_exists_value i xs); intuition; congruence.
Qed.
Lemma nth_error_value_eq_nth_default : forall {T} i (x : T) xs,
nth_error xs i = Some x -> forall d, nth_default d xs i = x.
Proof.
unfold nth_default; boring.
Qed.
Hint Rewrite @nth_error_value_eq_nth_default using eassumption : simpl_nth_default.
Lemma skipn0 : forall {T} (xs:list T), skipn 0 xs = xs.
Proof. auto. Qed.
Lemma destruct_repeat : forall {A} xs y, (forall x : A, In x xs -> x = y) ->
xs = nil \/ exists xs', xs = y :: xs' /\ (forall x : A, In x xs' -> x = y).
Proof.
destruct xs; intros; try tauto.
right.
exists xs; split.
+ f_equal; auto using in_eq.
+ intros; auto using in_cons.
Qed.
Lemma splice_nth_equiv_update_nth : forall {T} n f d (xs:list T),
splice_nth n (f (nth_default d xs n)) xs =
if lt_dec n (length xs)
then update_nth n f xs
else xs ++ (f d)::nil.
Proof.
induction n, xs; boring_list.
do 2 break_if; auto; omega.
Qed.
Lemma splice_nth_equiv_update_nth_update : forall {T} n f d (xs:list T),
n < length xs ->
splice_nth n (f (nth_default d xs n)) xs = update_nth n f xs.
Proof.
intros.
rewrite splice_nth_equiv_update_nth.
break_if; auto; omega.
Qed.
Lemma splice_nth_equiv_update_nth_snoc : forall {T} n f d (xs:list T),
n >= length xs ->
splice_nth n (f (nth_default d xs n)) xs = xs ++ (f d)::nil.
Proof.
intros.
rewrite splice_nth_equiv_update_nth.
break_if; auto; omega.
Qed.
Definition IMPOSSIBLE {T} : list T. exact nil. Qed.
Ltac remove_nth_error :=
repeat match goal with
| _ => exfalso; solve [ eauto using @nth_error_length_not_error ]
| [ |- context[match nth_error ?ls ?n with _ => _ end] ]
=> destruct (nth_error ls n) eqn:?
end.
Lemma update_nth_equiv_splice_nth: forall {T} n f (xs:list T),
update_nth n f xs =
if lt_dec n (length xs)
then match nth_error xs n with
| Some v => splice_nth n (f v) xs
| None => IMPOSSIBLE
end
else xs.
Proof.
induction n; destruct xs; intros;
autorewrite with simpl_update_nth simpl_nth_default in *; simpl in *;
try (erewrite IHn; clear IHn); auto.
repeat break_match; remove_nth_error; try reflexivity; try omega.
Qed.
Lemma splice_nth_equiv_set_nth : forall {T} n x (xs:list T),
splice_nth n x xs =
if lt_dec n (length xs)
then set_nth n x xs
else xs ++ x::nil.
Proof. intros; rewrite splice_nth_equiv_update_nth with (f := fun _ => x); auto. Qed.
Lemma splice_nth_equiv_set_nth_set : forall {T} n x (xs:list T),
n < length xs ->
splice_nth n x xs = set_nth n x xs.
Proof. intros; rewrite splice_nth_equiv_update_nth_update with (f := fun _ => x); auto. Qed.
Lemma splice_nth_equiv_set_nth_snoc : forall {T} n x (xs:list T),
n >= length xs ->
splice_nth n x xs = xs ++ x::nil.
Proof. intros; rewrite splice_nth_equiv_update_nth_snoc with (f := fun _ => x); auto. Qed.
Lemma set_nth_equiv_splice_nth: forall {T} n x (xs:list T),
set_nth n x xs =
if lt_dec n (length xs)
then splice_nth n x xs
else xs.
Proof.
intros; unfold set_nth; rewrite update_nth_equiv_splice_nth with (f := fun _ => x); auto.
repeat break_match; remove_nth_error; trivial.
Qed.
Lemma combine_update_nth : forall {A B} n f g (xs:list A) (ys:list B),
combine (update_nth n f xs) (update_nth n g ys) =
update_nth n (fun xy => (f (fst xy), g (snd xy))) (combine xs ys).
Proof.
induction n; destruct xs, ys; simpl; try rewrite IHn; reflexivity.
Qed.
(* grumble, grumble, [rewrite] is bad at inferring the identity function, and constant functions *)
Ltac rewrite_rev_combine_update_nth :=
let lem := match goal with
| [ |- appcontext[update_nth ?n (fun xy => (@?f xy, @?g xy)) (combine ?xs ?ys)] ]
=> let f := match (eval cbv [fst] in (fun y x => f (x, y))) with
| fun _ => ?f => f
end in
let g := match (eval cbv [snd] in (fun x y => g (x, y))) with
| fun _ => ?g => g
end in
constr:(@combine_update_nth _ _ n f g xs ys)
end in
rewrite <- lem.
Lemma combine_update_nth_l : forall {A B} n (f : A -> A) xs (ys:list B),
combine (update_nth n f xs) ys =
update_nth n (fun xy => (f (fst xy), snd xy)) (combine xs ys).
Proof.
intros ??? f xs ys.
etransitivity; [ | apply combine_update_nth with (g := fun x => x) ].
rewrite update_nth_id; reflexivity.
Qed.
Lemma combine_update_nth_r : forall {A B} n (g : B -> B) (xs:list A) (ys:list B),
combine xs (update_nth n g ys) =
update_nth n (fun xy => (fst xy, g (snd xy))) (combine xs ys).
Proof.
intros ??? g xs ys.
etransitivity; [ | apply combine_update_nth with (f := fun x => x) ].
rewrite update_nth_id; reflexivity.
Qed.
Lemma combine_set_nth : forall {A B} n (x:A) xs (ys:list B),
combine (set_nth n x xs) ys =
match nth_error ys n with
| None => combine xs ys
| Some y => set_nth n (x,y) (combine xs ys)
end.
Proof.
intros; unfold set_nth; rewrite combine_update_nth_l.
nth_tac;
[ repeat rewrite_rev_combine_update_nth; apply f_equal2
| assert (nth_error (combine xs ys) n = None)
by (apply nth_error_None; rewrite combine_length; omega * ) ];
autorewrite with simpl_update_nth; reflexivity.
Qed.
Lemma nth_error_value_In : forall {T} n xs (x:T),
nth_error xs n = Some x -> In x xs.
Proof.
induction n; destruct xs; nth_tac.
Qed.
Lemma In_nth_error_value : forall {T} xs (x:T),
In x xs -> exists n, nth_error xs n = Some x.
Proof.
induction xs; nth_tac; break_or_hyp.
- exists 0; reflexivity.
- edestruct IHxs; eauto. exists (S x0). eauto.
Qed.
Lemma nth_value_index : forall {T} i xs (x:T),
nth_error xs i = Some x -> In i (seq 0 (length xs)).
Proof.
induction i; destruct xs; nth_tac; right.
rewrite <- seq_shift; apply in_map; eapply IHi; eauto.
Qed.
Lemma nth_error_app : forall {T} n (xs ys:list T), nth_error (xs ++ ys) n =
if lt_dec n (length xs)
then nth_error xs n
else nth_error ys (n - length xs).
Proof.
induction n; destruct xs; nth_tac;
rewrite IHn; destruct (lt_dec n (length xs)); trivial; omega.
Qed.
Lemma nth_default_app : forall {T} n x (xs ys:list T), nth_default x (xs ++ ys) n =
if lt_dec n (length xs)
then nth_default x xs n
else nth_default x ys (n - length xs).
Proof.
intros.
unfold nth_default.
rewrite nth_error_app.
destruct (lt_dec n (length xs)); auto.
Qed.
Hint Rewrite @nth_default_app : push_nth_default.
Lemma combine_truncate_r : forall {A B} (xs : list A) (ys : list B),
combine xs ys = combine xs (firstn (length xs) ys).
Proof.
induction xs; destruct ys; boring.
Qed.
Lemma combine_truncate_l : forall {A B} (xs : list A) (ys : list B),
combine xs ys = combine (firstn (length ys) xs) ys.
Proof.
induction xs; destruct ys; boring.
Qed.
Lemma combine_app_samelength : forall {A B} (xs xs':list A) (ys ys':list B),
length xs = length ys ->
combine (xs ++ xs') (ys ++ ys') = combine xs ys ++ combine xs' ys'.
Proof.
induction xs, xs', ys, ys'; boring; omega.
Qed.
Lemma skipn_nil : forall {A} n, skipn n nil = @nil A.
Proof. destruct n; auto. Qed.
Hint Rewrite @skipn_nil : simpl_skipn.
Hint Rewrite @skipn_nil : push_skipn.
Lemma skipn_0 : forall {A} xs, @skipn A 0 xs = xs.
Proof. reflexivity. Qed.
Hint Rewrite @skipn_0 : simpl_skipn.
Hint Rewrite @skipn_0 : push_skipn.
Lemma skipn_cons_S : forall {A} n x xs, @skipn A (S n) (x::xs) = @skipn A n xs.
Proof. reflexivity. Qed.
Hint Rewrite @skipn_cons_S : simpl_skipn.
Hint Rewrite @skipn_cons_S : push_skipn.
Lemma skipn_app : forall {A} n (xs ys : list A),
skipn n (xs ++ ys) = skipn n xs ++ skipn (n - length xs) ys.
Proof.
induction n, xs, ys; boring.
Qed.
Hint Rewrite @skipn_app : push_skipn.
Lemma firstn_app_inleft : forall {A} n (xs ys : list A), (n <= length xs)%nat ->
firstn n (xs ++ ys) = firstn n xs.
Proof.
induction n, xs, ys; boring; try omega.
Qed.
Hint Rewrite @firstn_app_inleft using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_app_inleft using solve [ distr_length ] : push_firstn.
Lemma skipn_app_inleft : forall {A} n (xs ys : list A), (n <= length xs)%nat ->
skipn n (xs ++ ys) = skipn n xs ++ ys.
Proof.
induction n, xs, ys; boring; try omega.
Qed.
Hint Rewrite @skipn_app_inleft using solve [ distr_length ] : push_skipn.
Lemma firstn_map : forall {A B} (f : A -> B) n (xs : list A), firstn n (map f xs) = map f (firstn n xs).
Proof. induction n, xs; boring. Qed.
Hint Rewrite @firstn_map : push_firstn.
Hint Rewrite <- @firstn_map : pull_firstn.
Lemma skipn_map : forall {A B} (f : A -> B) n (xs : list A), skipn n (map f xs) = map f (skipn n xs).
Proof. induction n, xs; boring. Qed.
Hint Rewrite @skipn_map : push_skipn.
Hint Rewrite <- @skipn_map : pull_skipn.
Lemma firstn_all : forall {A} n (xs:list A), n = length xs -> firstn n xs = xs.
Proof.
induction n, xs; boring; omega.
Qed.
Hint Rewrite @firstn_all using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_all using solve [ distr_length ] : push_firstn.
Lemma skipn_all : forall {T} n (xs:list T),
(n >= length xs)%nat ->
skipn n xs = nil.
Proof.
induction n, xs; boring; omega.
Qed.
Hint Rewrite @skipn_all using solve [ distr_length ] : simpl_skipn.
Hint Rewrite @skipn_all using solve [ distr_length ] : push_skipn.
Lemma firstn_app_sharp : forall {A} n (l l': list A),
length l = n ->
firstn n (l ++ l') = l.
Proof.
intros.
rewrite firstn_app_inleft; auto using firstn_all; omega.
Qed.
Hint Rewrite @firstn_app_sharp using solve [ distr_length ] : simpl_firstn.
Hint Rewrite @firstn_app_sharp using solve [ distr_length ] : push_firstn.
Lemma skipn_app_sharp : forall {A} n (l l': list A),
length l = n ->
skipn n (l ++ l') = l'.
Proof.
intros.
rewrite skipn_app_inleft; try rewrite skipn_all; auto; omega.
Qed.
Hint Rewrite @skipn_app_sharp using solve [ distr_length ] : simpl_skipn.
Hint Rewrite @skipn_app_sharp using solve [ distr_length ] : push_skipn.
Lemma skipn_length : forall {A} n (xs : list A),
length (skipn n xs) = (length xs - n)%nat.
Proof.
induction n, xs; boring.
Qed.
Hint Rewrite @skipn_length : distr_length.
Lemma fold_right_cons : forall {A B} (f:B->A->A) a b bs,
fold_right f a (b::bs) = f b (fold_right f a bs).
Proof.
reflexivity.
Qed.
Hint Rewrite @fold_right_cons : simpl_fold_right.
Lemma length_cons : forall {T} (x:T) xs, length (x::xs) = S (length xs).
reflexivity.
Qed.
Hint Rewrite @length_cons : distr_length.
Lemma cons_length : forall A (xs : list A) a, length (a :: xs) = S (length xs).
Proof.
auto.
Qed.
Lemma length0_nil : forall {A} (xs : list A), length xs = 0%nat -> xs = nil.
Proof.
induction xs; boring; discriminate.
Qed.
Lemma length_snoc : forall {T} xs (x:T),
length xs = pred (length (xs++x::nil)).
Proof.
boring; simpl_list; boring.
Qed.
Lemma firstn_combine : forall {A B} n (xs:list A) (ys:list B),
firstn n (combine xs ys) = combine (firstn n xs) (firstn n ys).
Proof.
induction n, xs, ys; boring.
Qed.
Hint Rewrite @firstn_combine : push_firstn.
Hint Rewrite <- @firstn_combine : pull_firstn.
Lemma combine_nil_r : forall {A B} (xs:list A),
combine xs (@nil B) = nil.
Proof.
induction xs; boring.
Qed.
Lemma skipn_combine : forall {A B} n (xs:list A) (ys:list B),
skipn n (combine xs ys) = combine (skipn n xs) (skipn n ys).
Proof.
induction n, xs, ys; boring.
rewrite combine_nil_r; reflexivity.
Qed.
Hint Rewrite @skipn_combine : push_skipn.
Hint Rewrite <- @skipn_combine : pull_skipn.
Lemma break_list_last: forall {T} (xs:list T),
xs = nil \/ exists xs' y, xs = xs' ++ y :: nil.
Proof.
destruct xs using rev_ind; auto.
right; do 2 eexists; auto.
Qed.
Lemma break_list_first: forall {T} (xs:list T),
xs = nil \/ exists x xs', xs = x :: xs'.
Proof.
destruct xs; auto.
right; do 2 eexists; auto.
Qed.
Lemma list012 : forall {T} (xs:list T),
xs = nil
\/ (exists x, xs = x::nil)
\/ (exists x xs' y, xs = x::xs'++y::nil).
Proof.
destruct xs; auto.
right.
destruct xs using rev_ind. {
left; eexists; auto.
} {
right; repeat eexists; auto.
}
Qed.
Lemma nil_length0 : forall {T}, length (@nil T) = 0%nat.
Proof.
auto.
Qed.
Hint Rewrite @nil_length0 : distr_length.
Lemma nth_error_Some_nth_default : forall {T} i x (l : list T), (i < length l)%nat ->
nth_error l i = Some (nth_default x l i).
Proof.
intros ? ? ? ? i_lt_length.
destruct (nth_error_length_exists_value _ _ i_lt_length) as [k nth_err_k].
unfold nth_default.
rewrite nth_err_k.
reflexivity.
Qed.
Lemma update_nth_cons : forall {T} f (u0 : T) us, update_nth 0 f (u0 :: us) = (f u0) :: us.
Proof. reflexivity. Qed.
Hint Rewrite @update_nth_cons : simpl_update_nth.
Lemma set_nth_cons : forall {T} (x u0 : T) us, set_nth 0 x (u0 :: us) = x :: us.
Proof. intros; apply update_nth_cons. Qed.
Hint Rewrite @set_nth_cons : simpl_set_nth.
Lemma cons_update_nth : forall {T} n f (y : T) us,
y :: update_nth n f us = update_nth (S n) f (y :: us).
Proof.
induction n; boring.
Qed.
Hint Rewrite <- @cons_update_nth : simpl_update_nth.
Lemma update_nth_nil : forall {T} n f, update_nth n f (@nil T) = @nil T.
Proof.
induction n; boring.
Qed.
Hint Rewrite @update_nth_nil : simpl_update_nth.
Lemma cons_set_nth : forall {T} n (x y : T) us,
y :: set_nth n x us = set_nth (S n) x (y :: us).
Proof. intros; apply cons_update_nth. Qed.
Hint Rewrite <- @cons_set_nth : simpl_set_nth.
Lemma set_nth_nil : forall {T} n (x : T), set_nth n x nil = nil.
Proof. intros; apply update_nth_nil. Qed.
Hint Rewrite @set_nth_nil : simpl_set_nth.
Lemma skipn_nth_default : forall {T} n us (d : T), (n < length us)%nat ->
skipn n us = nth_default d us n :: skipn (S n) us.
Proof.
induction n; destruct us; intros; nth_tac.
rewrite (IHn us d) at 1 by omega.
nth_tac.
Qed.
Lemma nth_default_out_of_bounds : forall {T} n us (d : T), (n >= length us)%nat ->
nth_default d us n = d.
Proof.
induction n; unfold nth_default; nth_tac; destruct us; nth_tac.
assert (n >= length us)%nat by omega.
pose proof (nth_error_length_error _ n us H1).
rewrite H0 in H2.
congruence.
Qed.
Hint Rewrite @nth_default_out_of_bounds using omega : simpl_nth_default.
Ltac nth_error_inbounds :=
match goal with
| [ |- context[match nth_error ?xs ?i with Some _ => _ | None => _ end ] ] =>
case_eq (nth_error xs i);
match goal with
| [ |- forall _, nth_error xs i = Some _ -> _ ] =>
let x := fresh "x" in
let H := fresh "H" in
intros x H;
repeat progress erewrite H;
repeat progress erewrite (nth_error_value_eq_nth_default i xs x); auto
| [ |- nth_error xs i = None -> _ ] =>
let H := fresh "H" in
intros H;
destruct (nth_error_length_not_error _ _ H);
try solve [distr_length]
end;
idtac
end.
Ltac set_nth_inbounds :=
match goal with
| [ |- context[set_nth ?i ?x ?xs] ] =>
rewrite (set_nth_equiv_splice_nth i x xs);
destruct (lt_dec i (length xs));
match goal with
| [ H : ~ (i < (length xs))%nat |- _ ] => destruct H
| [ H : (i < (length xs))%nat |- _ ] => try solve [distr_length]
end
end.
Ltac update_nth_inbounds :=
match goal with
| [ |- context[update_nth ?i ?f ?xs] ] =>
rewrite (update_nth_equiv_splice_nth i f xs);
destruct (lt_dec i (length xs));
match goal with
| [ H : ~ (i < (length xs))%nat |- _ ] => destruct H
| [ H : (i < (length xs))%nat |- _ ] => remove_nth_error; try solve [distr_length]
end
end.
Ltac nth_inbounds := nth_error_inbounds || set_nth_inbounds || update_nth_inbounds.
Definition nth_dep {A} (ls : list A) (n : nat) (pf : n < length ls) : A.
Proof.
refine (match nth_error ls n as v return nth_error ls n = v -> A with
| Some v => fun _ => v
| None => fun bad => match _ : False with end
end eq_refl).
apply (proj1 (@nth_error_None _ _ _)) in bad; instantiate; generalize dependent (length ls); clear.
abstract (intros; omega).
Defined.
Lemma nth_error_nth_dep {A} ls n pf : nth_error ls n = Some (@nth_dep A ls n pf).
Proof.
unfold nth_dep.
generalize dependent (@nth_error_None A ls n).
edestruct nth_error; boring.
Qed.
Lemma nth_default_nth_dep {A} d ls n pf : nth_default d ls n = @nth_dep A ls n pf.
Proof.
unfold nth_dep.
generalize dependent (@nth_error_None A ls n).
destruct (nth_error ls n) eqn:?; boring.
erewrite nth_error_value_eq_nth_default by eassumption; reflexivity.
Qed.
Lemma nth_default_in_bounds : forall {T} (d' d : T) n us, (n < length us)%nat ->
nth_default d us n = nth_default d' us n.
Proof.
intros; erewrite !nth_default_nth_dep; reflexivity.
Grab Existential Variables.
assumption.
Qed.
Hint Resolve @nth_default_in_bounds : simpl_nth_default.
Lemma cons_eq_head : forall {T} (x y:T) xs ys, x::xs = y::ys -> x=y.
Proof.
intros; solve_by_inversion.
Qed.
Lemma cons_eq_tail : forall {T} (x y:T) xs ys, x::xs = y::ys -> xs=ys.
Proof.
intros; solve_by_inversion.
Qed.
Lemma map_nth_default_always {A B} (f : A -> B) (n : nat) (x : A) (l : list A)
: nth_default (f x) (map f l) n = f (nth_default x l n).
Proof.
revert n; induction l; simpl; intro n; destruct n; [ try reflexivity.. ].
nth_tac.
Qed.
Hint Rewrite @map_nth_default_always : push_nth_default.
Lemma fold_right_and_True_forall_In_iff : forall {T} (l : list T) (P : T -> Prop),
(forall x, In x l -> P x) <-> fold_right and True (map P l).
Proof.
induction l; intros; simpl; try tauto.
rewrite <- IHl.
intuition (subst; auto).
Qed.
Lemma fold_right_invariant : forall {A} P (f: A -> A -> A) l x,
P x -> (forall y, In y l -> forall z, P z -> P (f y z)) ->
P (fold_right f x l).
Proof.
induction l; intros ? ? step; auto.
simpl.
apply step; try apply in_eq.
apply IHl; auto.
intros y in_y_l.
apply (in_cons a) in in_y_l.
auto.
Qed.
Lemma In_firstn : forall {T} n l (x : T), In x (firstn n l) -> In x l.
Proof.
induction n; destruct l; boring.
Qed.
Lemma In_skipn : forall {T} n l (x : T), In x (skipn n l) -> In x l.
Proof.
induction n; destruct l; boring.
Qed.
Lemma firstn_firstn : forall {A} m n (l : list A), (n <= m)%nat ->
firstn n (firstn m l) = firstn n l.
Proof.
induction m; destruct n; intros; try omega; auto.
destruct l; auto.
simpl.
f_equal.
apply IHm; omega.
Qed.
Hint Rewrite @firstn_firstn using omega : push_firstn.
Lemma firstn_succ : forall {A} (d : A) n l, (n < length l)%nat ->
firstn (S n) l = (firstn n l) ++ nth_default d l n :: nil.
Proof.
induction n; destruct l; rewrite ?(@nil_length0 A); intros; try omega.
+ rewrite nth_default_cons; auto.
+ simpl.
rewrite nth_default_cons_S.
rewrite <-IHn by (rewrite cons_length in *; omega).
reflexivity.
Qed.
Lemma update_nth_out_of_bounds : forall {A} n f xs, n >= length xs -> @update_nth A n f xs = xs.
Proof.
induction n; destruct xs; simpl; try congruence; try omega; intros.
rewrite IHn by omega; reflexivity.
Qed.
Hint Rewrite @update_nth_out_of_bounds using omega : simpl_update_nth.
Lemma update_nth_nth_default_full : forall {A} (d:A) n f l i,
nth_default d (update_nth n f l) i =
if lt_dec i (length l) then
if (eq_nat_dec i n) then f (nth_default d l i)
else nth_default d l i
else d.
Proof.
induction n; (destruct l; simpl in *; [ intros; destruct i; simpl; try reflexivity; omega | ]);
intros; repeat break_if; subst; try destruct i;
repeat first [ progress break_if
| progress subst
| progress boring
| progress autorewrite with simpl_nth_default
| omega ].
Qed.
Hint Rewrite @update_nth_nth_default_full : push_nth_default.
Lemma update_nth_nth_default : forall {A} (d:A) n f l i, (0 <= i < length l)%nat ->
nth_default d (update_nth n f l) i =
if (eq_nat_dec i n) then f (nth_default d l i) else nth_default d l i.
Proof. intros; rewrite update_nth_nth_default_full; repeat break_if; boring. Qed.
Hint Rewrite @update_nth_nth_default using (omega || distr_length; omega) : push_nth_default.
Lemma set_nth_nth_default_full : forall {A} (d:A) n v l i,
nth_default d (set_nth n v l) i =
if lt_dec i (length l) then
if (eq_nat_dec i n) then v
else nth_default d l i
else d.
Proof. intros; apply update_nth_nth_default_full; assumption. Qed.
Hint Rewrite @set_nth_nth_default_full : push_nth_default.
Lemma set_nth_nth_default : forall {A} (d:A) n x l i, (0 <= i < length l)%nat ->
nth_default d (set_nth n x l) i =
if (eq_nat_dec i n) then x else nth_default d l i.
Proof. intros; apply update_nth_nth_default; assumption. Qed.
Hint Rewrite @set_nth_nth_default using (omega || distr_length; omega) : push_nth_default.
Lemma nth_default_preserves_properties : forall {A} (P : A -> Prop) l n d,
(forall x, In x l -> P x) -> P d -> P (nth_default d l n).
Proof.
intros; rewrite nth_default_eq.
destruct (nth_in_or_default n l d); auto.
congruence.
Qed.
Lemma nth_default_preserves_properties_length_dep :
forall {A} (P : A -> Prop) l n d,
(forall x, In x l -> n < (length l) -> P x) -> ((~ n < length l) -> P d) -> P (nth_default d l n).
Proof.
intros.
destruct (lt_dec n (length l)).
+ rewrite nth_default_eq; auto using nth_In.
+ rewrite nth_default_out_of_bounds by omega.
auto.
Qed.
Lemma nth_error_first : forall {T} (a b : T) l,
nth_error (a :: l) 0 = Some b -> a = b.
Proof.
intros; simpl in *.
unfold value in *.
congruence.
Qed.
Lemma nth_error_exists_first : forall {T} l (x : T) (H : nth_error l 0 = Some x),
exists l', l = x :: l'.
Proof.
induction l; try discriminate; eexists.
apply nth_error_first in H.
subst; eauto.
Qed.
Lemma list_elementwise_eq : forall {T} (l1 l2 : list T),
(forall i, nth_error l1 i = nth_error l2 i) -> l1 = l2.
Proof.
induction l1, l2; intros; try reflexivity;
pose proof (H 0%nat) as Hfirst; simpl in Hfirst; inversion Hfirst.
f_equal.
apply IHl1.
intros i; specialize (H (S i)).
boring.
Qed.
Lemma sum_firstn_all_succ : forall n l, (length l <= n)%nat ->
sum_firstn l (S n) = sum_firstn l n.
Proof.
unfold sum_firstn; intros.
autorewrite with push_firstn; reflexivity.
Qed.
Hint Rewrite @sum_firstn_all_succ using omega : simpl_sum_firstn.
Lemma sum_firstn_all : forall n l, (length l <= n)%nat ->
sum_firstn l n = sum_firstn l (length l).
Proof.
unfold sum_firstn; intros.
autorewrite with push_firstn; reflexivity.
Qed.
Hint Rewrite @sum_firstn_all using omega : simpl_sum_firstn.
Lemma sum_firstn_succ_default : forall l i,
sum_firstn l (S i) = (nth_default 0 l i + sum_firstn l i)%Z.
Proof.
unfold sum_firstn; induction l, i;
intros; autorewrite with simpl_nth_default simpl_firstn simpl_fold_right in *;
try reflexivity.
rewrite IHl; omega.
Qed.
Hint Rewrite @sum_firstn_succ_default : simpl_sum_firstn.
Lemma sum_firstn_0 : forall xs,
sum_firstn xs 0 = 0%Z.
Proof.
destruct xs; reflexivity.
Qed.
Hint Rewrite @sum_firstn_0 : simpl_sum_firstn.
Lemma sum_firstn_succ : forall l i x,
nth_error l i = Some x ->
sum_firstn l (S i) = (x + sum_firstn l i)%Z.
Proof.
intros; rewrite sum_firstn_succ_default.
erewrite nth_error_value_eq_nth_default by eassumption; reflexivity.
Qed.
Hint Rewrite @sum_firstn_succ using congruence : simpl_sum_firstn.
Lemma sum_firstn_succ_cons : forall x xs i,
sum_firstn (x :: xs) (S i) = (x + sum_firstn xs i)%Z.
Proof.
unfold sum_firstn; simpl; reflexivity.
Qed.
Hint Rewrite @sum_firstn_succ_cons : simpl_sum_firstn.
Lemma sum_firstn_nil : forall i,
sum_firstn nil i = 0%Z.
Proof. destruct i; reflexivity. Qed.
Hint Rewrite @sum_firstn_nil : simpl_sum_firstn.
Lemma sum_firstn_succ_default_rev : forall l i,
sum_firstn l i = (sum_firstn l (S i) - nth_default 0 l i)%Z.
Proof.
intros; rewrite sum_firstn_succ_default; omega.
Qed.
Lemma sum_firstn_succ_rev : forall l i x,
nth_error l i = Some x ->
sum_firstn l i = (sum_firstn l (S i) - x)%Z.
Proof.
intros; erewrite sum_firstn_succ by eassumption; omega.
Qed.
Lemma sum_firstn_nonnegative : forall n l, (forall x, In x l -> 0 <= x)%Z
-> (0 <= sum_firstn l n)%Z.
Proof.
induction n as [|n IHn]; destruct l as [|? l]; autorewrite with simpl_sum_firstn; simpl; try omega.
{ specialize (IHn l).
destruct n; simpl; autorewrite with simpl_sum_firstn simpl_nth_default in *;
intuition auto with zarith. }
Qed.
Hint Resolve sum_firstn_nonnegative : znonzero.
Lemma sum_firstn_app : forall xs ys n,
sum_firstn (xs ++ ys) n = (sum_firstn xs n + sum_firstn ys (n - length xs))%Z.
Proof.
induction xs; simpl.
{ intros ys n; autorewrite with simpl_sum_firstn; simpl.
f_equal; omega. }
{ intros ys [|n]; autorewrite with simpl_sum_firstn; simpl; [ reflexivity | ].
rewrite IHxs; omega. }
Qed.
Lemma sum_firstn_app_sum : forall xs ys n,
sum_firstn (xs ++ ys) (length xs + n) = (sum_firstn xs (length xs) + sum_firstn ys n)%Z.
Proof.
intros; rewrite sum_firstn_app; autorewrite with simpl_sum_firstn.
do 2 f_equal; omega.
Qed.
Hint Rewrite @sum_firstn_app_sum : simpl_sum_firstn.
Lemma nth_error_skipn : forall {A} n (l : list A) m,
nth_error (skipn n l) m = nth_error l (n + m).
Proof.
induction n; destruct l; boring.
apply nth_error_nil_error.
Qed.
Hint Rewrite @nth_error_skipn : push_nth_error.
Lemma nth_default_skipn : forall {A} (l : list A) d n m, nth_default d (skipn n l) m = nth_default d l (n + m).
Proof.
cbv [nth_default]; intros.
rewrite nth_error_skipn.
reflexivity.
Qed.
Hint Rewrite @nth_default_skipn : push_nth_default.
Lemma sum_firstn_skipn : forall l n m, sum_firstn l (n + m) = (sum_firstn l n + sum_firstn (skipn n l) m)%Z.
Proof.
induction m; intros.
+ rewrite sum_firstn_0. autorewrite with natsimplify. omega.
+ rewrite <-plus_n_Sm, !sum_firstn_succ_default.
rewrite nth_default_skipn.
omega.
Qed.
Lemma sum_firstn_prefix_le' : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(sum_firstn l n <= sum_firstn l (n + m))%Z.
Proof.
intros.
rewrite sum_firstn_skipn.
pose proof (sum_firstn_nonnegative m (skipn n l)) as Hskipn_nonneg.
match type of Hskipn_nonneg with
?P -> _ => assert P as Q; [ | specialize (Hskipn_nonneg Q); omega ] end.
intros x HIn_skipn.
apply In_skipn in HIn_skipn.
auto.
Qed.
Lemma sum_firstn_prefix_le : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(n <= m)%nat ->
(sum_firstn l n <= sum_firstn l m)%Z.
Proof.
intros.
replace m with (n + (m - n))%nat by omega.
auto using sum_firstn_prefix_le'.
Qed.
Lemma sum_firstn_pos_lt_succ : forall l n m, (forall x, In x l -> (0 <= x)%Z) ->
(n < length l)%nat ->
(sum_firstn l n < sum_firstn l (S m))%Z ->
(n <= m)%nat.
Proof.
intros.
destruct (le_dec n m); auto.
replace n with (m + (n - m))%nat in H1 by omega.
rewrite sum_firstn_skipn in H1.
rewrite sum_firstn_succ_default in *.
match goal with H : (?a + ?b < ?c + ?a)%Z |- _ => assert (b < c)%Z by omega end.
destruct (lt_dec m (length l)). {
rewrite skipn_nth_default with (d := 0%Z) in H2 by assumption.
replace (n - m)%nat with (S (n - S m))%nat in H2 by omega.
rewrite sum_firstn_succ_cons in H2.
pose proof (sum_firstn_nonnegative (n - S m) (skipn (S m) l)).
match type of H3 with
?P -> _ => assert P as Q; [ | specialize (H3 Q); omega ] end.
intros ? A.
apply In_skipn in A.
apply H in A.
omega.
} {
rewrite skipn_all, nth_default_out_of_bounds in H2 by omega.
rewrite sum_firstn_nil in H2; omega.
}
Qed.
Definition NotSum {T} (xs : list T) (v : nat) := True.
Ltac NotSum :=
lazymatch goal with
| [ |- NotSum ?xs (length ?xs + _)%nat ] => fail
| [ |- NotSum _ _ ] => exact I
end.
Lemma sum_firstn_app_hint : forall xs ys n, NotSum xs n ->
sum_firstn (xs ++ ys) n = (sum_firstn xs n + sum_firstn ys (n - length xs))%Z.
Proof. auto using sum_firstn_app. Qed.
Hint Rewrite sum_firstn_app_hint using solve [ NotSum ] : simpl_sum_firstn.
Lemma nth_default_map2 : forall {A B C} (f : A -> B -> C) ls1 ls2 i d d1 d2,
nth_default d (map2 f ls1 ls2) i =
if lt_dec i (min (length ls1) (length ls2))
then f (nth_default d1 ls1 i) (nth_default d2 ls2 i)
else d.
Proof.
induction ls1, ls2.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ cbv [map2 length min].
intros.
break_if; try omega.
apply nth_default_nil.
+ simpl.
destruct i.
- intros. rewrite !nth_default_cons.
break_if; auto; omega.
- intros. rewrite !nth_default_cons_S.
rewrite IHls1 with (d1 := d1) (d2 := d2).
repeat break_if; auto; omega.
Qed.
Lemma map2_cons : forall A B C (f : A -> B -> C) ls1 ls2 a b,
map2 f (a :: ls1) (b :: ls2) = f a b :: map2 f ls1 ls2.
Proof.
reflexivity.
Qed.
Lemma map2_nil_l : forall A B C (f : A -> B -> C) ls2,
map2 f nil ls2 = nil.
Proof.
reflexivity.
Qed.
Lemma map2_nil_r : forall A B C (f : A -> B -> C) ls1,
map2 f ls1 nil = nil.
Proof.
destruct ls1; reflexivity.
Qed.
Local Hint Resolve map2_nil_r map2_nil_l.
Opaque map2.
Lemma map2_length : forall A B C (f : A -> B -> C) ls1 ls2,
length (map2 f ls1 ls2) = min (length ls1) (length ls2).
Proof.
induction ls1, ls2; intros; try solve [cbv; auto].
rewrite map2_cons, !length_cons, IHls1.
auto.
Qed.
Ltac simpl_list_lengths := repeat match goal with
| H : appcontext[length (@nil ?A)] |- _ => rewrite (@nil_length0 A) in H
| H : appcontext[length (_ :: _)] |- _ => rewrite length_cons in H
| |- appcontext[length (@nil ?A)] => rewrite (@nil_length0 A)
| |- appcontext[length (_ :: _)] => rewrite length_cons
end.
Lemma map2_app : forall A B C (f : A -> B -> C) ls1 ls2 ls1' ls2',
(length ls1 = length ls2) ->
map2 f (ls1 ++ ls1') (ls2 ++ ls2') = map2 f ls1 ls2 ++ map2 f ls1' ls2'.
Proof.
induction ls1, ls2; intros; rewrite ?map2_nil_r, ?app_nil_l; try congruence;
simpl_list_lengths; try omega.
rewrite <-!app_comm_cons, !map2_cons.
rewrite IHls1; auto.
Qed.
Lemma firstn_update_nth {A}
: forall f m n (xs : list A), firstn m (update_nth n f xs) = update_nth n f (firstn m xs).
Proof.
induction m; destruct n, xs;
autorewrite with simpl_firstn simpl_update_nth;
congruence.
Qed.
Hint Rewrite @firstn_update_nth : push_firstn.
Hint Rewrite @firstn_update_nth : pull_update_nth.
Hint Rewrite <- @firstn_update_nth : pull_firstn.
Hint Rewrite <- @firstn_update_nth : push_update_nth.
Require Import Coq.Lists.SetoidList.
Global Instance Proper_nth_default : forall A eq,
Proper (eq==>eqlistA eq==>Logic.eq==>eq) (nth_default (A:=A)).
Proof.
do 5 intro; subst; induction 1.
+ repeat intro; rewrite !nth_default_nil; assumption.
+ repeat intro; subst; destruct y0; rewrite ?nth_default_cons, ?nth_default_cons_S; auto.
Qed.
Lemma fold_right_andb_true_map_iff A (ls : list A) f
: List.fold_right andb true (List.map f ls) = true <-> forall i, List.In i ls -> f i = true.
Proof.
induction ls; simpl; [ | rewrite Bool.andb_true_iff, IHls ]; try tauto.
intuition (congruence || eauto).
Qed.
Lemma Forall2_forall_iff : forall {A} R (xs ys : list A) d, length xs = length ys ->
(Forall2 R xs ys <-> (forall i, (i < length xs)%nat -> R (nth_default d xs i) (nth_default d ys i))).
Proof.
split; intros.
+ revert xs ys H H0 H1.
induction i; intros; destruct H0; distr_length; autorewrite with push_nth_default; auto.
eapply IHi; auto. omega.
+ revert xs ys H H0; induction xs; intros; destruct ys; distr_length; econstructor.
- specialize (H0 0%nat).
autorewrite with push_nth_default in *; auto.
apply H0; omega.
- apply IHxs; try omega.
intros.
specialize (H0 (S i)).
autorewrite with push_nth_default in *; auto.
apply H0; omega.
Qed.
Lemma nth_default_firstn : forall {A} (d : A) l i n,
nth_default d (firstn n l) i = if le_dec n (length l)
then if lt_dec i n then nth_default d l i else d
else nth_default d l i.
Proof.
induction n; intros; break_if; autorewrite with push_nth_default; auto; try omega.
+ rewrite (firstn_succ d) by omega.
autorewrite with push_nth_default; repeat (break_if; distr_length);
rewrite Min.min_l in * by omega; try omega.
- apply IHn; omega.
- replace i with n in * by omega.
rewrite Nat.sub_diag.
autorewrite with push_nth_default; auto.
- rewrite nth_default_out_of_bounds; distr_length; auto.
+ rewrite firstn_all2 by omega.
auto.
Qed.
Hint Rewrite @nth_default_firstn : push_nth_default.
Lemma nth_error_repeat {T} x n i v : nth_error (@repeat T x n) i = Some v -> v = x.
Proof.
revert n x v; induction i as [|i IHi]; destruct n; simpl in *; eauto; congruence.
Qed.
Hint Rewrite repeat_length : distr_length.
Lemma repeat_spec_iff : forall {A} (ls : list A) x n,
(length ls = n /\ forall y, In y ls -> y = x) <-> ls = repeat x n.
Proof.
split; [ revert A ls x n | intro; subst; eauto using repeat_length, repeat_spec ].
induction ls, n; simpl; intros; intuition try congruence.
f_equal; auto.
Qed.
Lemma repeat_spec_eq : forall {A} (ls : list A) x n,
length ls = n
-> (forall y, In y ls -> y = x)
-> ls = repeat x n.
Proof.
intros; apply repeat_spec_iff; auto.
Qed.
Lemma tl_repeat {A} x n : tl (@repeat A x n) = repeat x (pred n).
Proof. destruct n; reflexivity. Qed.
Lemma firstn_repeat : forall {A} x n k, firstn k (@repeat A x n) = repeat x (min k n).
Proof. induction n, k; boring. Qed.
Hint Rewrite @firstn_repeat : push_firstn.
Lemma skipn_repeat : forall {A} x n k, skipn k (@repeat A x n) = repeat x (n - k).
Proof. induction n, k; boring. Qed.
Hint Rewrite @skipn_repeat : push_skipn.
|
module autoinst_precomment (
why,
/*AUTOARG*/
// Inputs
nnnot
);
input why;
input nnnot;
autoinst_wildcard_sub sub0
(
.sd_ras_ (foobar_ras_),
//.sd0_dqm7_l (dontdome),
/*AUTOINST*/
// Inouts
.sd0_dqm7_l (sd0_dqm7_l),
.sd0_dqm6_l (sd0_dqm6_l),
.sd0_dqm5_l (sd0_dqm5_l),
.sd0_dqm4_l (sd0_dqm4_l),
.sd0_dqm3_l (sd0_dqm3_l),
.sd0_dqm2_l (sd0_dqm2_l),
.sd0_dqm1_l (sd0_dqm1_l),
.sd0_dqm0_l (sd0_dqm0_l),
.sd0_ba1 (sd0_ba1),
.sd0_ba0 (sd0_ba0),
.sd0_adrs11 (sd0_adrs11),
.sd0_adrs10 (sd0_adrs10),
.sd0_adrs9 (sd0_adrs9),
.sd0_adrs8 (sd0_adrs8),
.sd0_adrs7 (sd0_adrs7),
.sd0_adrs6 (sd0_adrs6),
.sd0_adrs5 (sd0_adrs5),
.sd0_adrs4 (sd0_adrs4),
.sd0_adrs3 (sd0_adrs3),
.sd0_adrs2 (sd0_adrs2),
.sd0_adrs1 (sd0_adrs1),
.sd0_adrs0 (sd0_adrs0),
.sd0_clk (sd0_clk));
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocmc.v
*
* Date : 2012-11
*
* Description : Controller for OCM model
*
*****************************************************************************/
module processing_system7_bfm_v2_0_ocmc(
rstn,
sw_clk,
/* Goes to port 0 of OCM */
ocm_wr_ack_port0,
ocm_wr_dv_port0,
ocm_rd_req_port0,
ocm_rd_dv_port0,
ocm_wr_addr_port0,
ocm_wr_data_port0,
ocm_wr_bytes_port0,
ocm_rd_addr_port0,
ocm_rd_data_port0,
ocm_rd_bytes_port0,
ocm_wr_qos_port0,
ocm_rd_qos_port0,
/* Goes to port 1 of OCM */
ocm_wr_ack_port1,
ocm_wr_dv_port1,
ocm_rd_req_port1,
ocm_rd_dv_port1,
ocm_wr_addr_port1,
ocm_wr_data_port1,
ocm_wr_bytes_port1,
ocm_rd_addr_port1,
ocm_rd_data_port1,
ocm_rd_bytes_port1,
ocm_wr_qos_port1,
ocm_rd_qos_port1
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ocm_wr_ack_port0;
input ocm_wr_dv_port0;
input ocm_rd_req_port0;
output ocm_rd_dv_port0;
input[addr_width-1:0] ocm_wr_addr_port0;
input[max_burst_bits-1:0] ocm_wr_data_port0;
input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
input[addr_width-1:0] ocm_rd_addr_port0;
output[max_burst_bits-1:0] ocm_rd_data_port0;
input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
input [axi_qos_width-1:0] ocm_wr_qos_port0;
input [axi_qos_width-1:0] ocm_rd_qos_port0;
output ocm_wr_ack_port1;
input ocm_wr_dv_port1;
input ocm_rd_req_port1;
output ocm_rd_dv_port1;
input[addr_width-1:0] ocm_wr_addr_port1;
input[max_burst_bits-1:0] ocm_wr_data_port1;
input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bits-1:0] ocm_rd_data_port1;
input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
input[axi_qos_width-1:0] ocm_wr_qos_port1;
input[axi_qos_width-1:0] ocm_rd_qos_port1;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr ocm_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_port0),
.qos2(ocm_wr_qos_port1),
.prt_dv1(ocm_wr_dv_port0),
.prt_dv2(ocm_wr_dv_port1),
.prt_data1(ocm_wr_data_port0),
.prt_data2(ocm_wr_data_port1),
.prt_addr1(ocm_wr_addr_port0),
.prt_addr2(ocm_wr_addr_port1),
.prt_bytes1(ocm_wr_bytes_port0),
.prt_bytes2(ocm_wr_bytes_port1),
.prt_ack1(ocm_wr_ack_port0),
.prt_ack2(ocm_wr_ack_port1),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ocm_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_port0),
.qos2(ocm_rd_qos_port1),
.prt_req1(ocm_rd_req_port0),
.prt_req2(ocm_rd_req_port1),
.prt_data1(ocm_rd_data_port0),
.prt_data2(ocm_rd_data_port1),
.prt_addr1(ocm_rd_addr_port0),
.prt_addr2(ocm_rd_addr_port1),
.prt_bytes1(ocm_rd_bytes_port0),
.prt_bytes2(ocm_rd_bytes_port1),
.prt_dv1(ocm_rd_dv_port0),
.prt_dv2(ocm_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_ocm_mem ocm();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ocm.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ocm.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sin (
enable,
clock,
dataa,
resetn,
result);
input enable;
input clock;
input resetn;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_sin fpc_sin(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(sub_wire0[31]),
.exponentout(sub_wire0[30:23]),
.mantissaout(sub_wire0[22:0])
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN & ~I;
end else begin : USE_FPGA
wire I_n;
assign I_n = ~I;
AND2B1L and2b1l_inst
(
.O(O),
.DI(CIN),
.SRI(I_n)
);
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2A_BEHAVIORAL_V |
/* salsa_slowsixteen.v
*
* Copyright (c) 2013 kramble
* Derived from scrypt.c Copyright 2009 Colin Percival, 2011 ArtForz
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
module salsa (clk, B, Bx, Bo, X0out, Xaddr);
// Latency 16 clock cycles, approx 20nS propagation delay (SLOW!)
input clk;
// input feedback;
input [511:0]B;
input [511:0]Bx;
// output reg [511:0]Bo; // Output is registered
output [511:0]Bo; // Output is async
output [511:0]X0out; // Becomes new X0
output [9:0] Xaddr;
wire [9:0] xa1, xa2, xa3, xa4, ya1, ya2, ya3, ya4;
reg [511:0]x1d1, x1d1a;
reg [511:0]x1d2, x1d2a;
reg [511:0]x1d3, x1d3a;
reg [511:0]x1d4, x1d4a;
reg [511:0]Xod1, Xod1a;
reg [511:0]Xod2, Xod2a;
reg [511:0]Xod3, Xod3a;
reg [511:0]Xod4, X0out;
reg [511:0]xxd1, xxd1a;
reg [511:0]xxd2, xxd2a;
reg [511:0]xxd3, xxd3a;
reg [511:0]xxd4, xxd4a;
reg [511:0]yyd1, yyd1a;
reg [511:0]yyd2, yyd2a;
reg [511:0]yyd3, yyd3a;
reg [511:0]yyd4, yyd4a;
wire [511:0]xx; // Initial xor
wire [511:0]x1; // Salasa core outputs
wire [511:0]x2;
wire [511:0]x3;
wire [511:0]xr;
wire [511:0]Xo;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsax1 (clk, xx, x1, xa1);
salsa_core salsax2 (clk, x1, x2, xa2);
salsa_core salsax3 (clk, x2, x3, xa3);
salsa_core salsax4 (clk, x3, xr, xa4);
wire [511:0]yy; // Initial xor
wire [511:0]y1; // Salasa core outputs
wire [511:0]y2;
wire [511:0]y3;
wire [511:0]yr;
// Four salsa iterations. NB use registered salsa_core so 4 clock cycles.
salsa_core salsay1 (clk, yy, y1, ya1);
salsa_core salsay2 (clk, y1, y2, ya2);
salsa_core salsay3 (clk, y2, y3, ya3);
salsa_core salsay4 (clk, y3, yr, ya4);
assign Xaddr = yyd4[9:0] + ya4;
genvar i;
generate
for (i = 0; i < 16; i = i + 1) begin : XX
// Initial XOR. NB this adds to the propagation delay of the first salsa, may want register it.
assign xx[`IDX(i)] = B[`IDX(i)] ^ Bx[`IDX(i)];
assign Xo[`IDX(i)] = xxd4a[`IDX(i)] + xr[`IDX(i)];
assign yy[`IDX(i)] = x1d4a[`IDX(i)] ^ Xo[`IDX(i)];
assign Bo[`IDX(i)] = yyd4a[`IDX(i)] + yr[`IDX(i)]; // Async output
end
endgenerate
always @ (posedge clk)
begin
x1d1 <= Bx;
x1d1a <= x1d1;
x1d2 <= x1d1a;
x1d2a <= x1d2;
x1d3 <= x1d2a;
x1d3a <= x1d3;
x1d4 <= x1d3a;
x1d4a <= x1d4;
Xod1 <= Xo;
Xod1a <= Xod1;
Xod2 <= Xod1a;
Xod2a <= Xod2;
Xod3 <= Xod2a;
Xod3a <= Xod3;
Xod4 <= Xod3a;
X0out <= Xod4; // We output this to become new X0
xxd1 <= xx;
xxd1a <= xxd1;
xxd2 <= xxd1a;
xxd2a <= xxd2;
xxd3 <= xxd2a;
xxd3a <= xxd3;
xxd4 <= xxd3a;
xxd4a <= xxd4;
yyd1 <= yy;
yyd1a <= yyd1;
yyd2 <= yyd1a;
yyd2a <= yyd2;
yyd3 <= yyd2a;
yyd3a <= yyd3;
yyd4 <= yyd3a;
yyd4a <= yyd4;
end
endmodule
module salsa_core (clk, xx, out, Xaddr);
input clk;
input [511:0]xx;
output reg [511:0]out; // Output is registered
output [9:0] Xaddr; // Address output unregistered
// This is clunky due to my lack of verilog skills but it works so elegance can come later
wire [31:0]c00; // Column results
wire [31:0]c01;
wire [31:0]c02;
wire [31:0]c03;
wire [31:0]c04;
wire [31:0]c05;
wire [31:0]c06;
wire [31:0]c07;
wire [31:0]c08;
wire [31:0]c09;
wire [31:0]c10;
wire [31:0]c11;
wire [31:0]c12;
wire [31:0]c13;
wire [31:0]c14;
wire [31:0]c15;
wire [31:0]r00; // Row results
wire [31:0]r01;
wire [31:0]r02;
wire [31:0]r03;
wire [31:0]r04;
wire [31:0]r05;
wire [31:0]r06;
wire [31:0]r07;
wire [31:0]r08;
wire [31:0]r09;
wire [31:0]r10;
wire [31:0]r11;
wire [31:0]r12;
wire [31:0]r13;
wire [31:0]r14;
wire [31:0]r15;
wire [31:0]c00s; // Column sums
wire [31:0]c01s;
wire [31:0]c02s;
wire [31:0]c03s;
wire [31:0]c04s;
wire [31:0]c05s;
wire [31:0]c06s;
wire [31:0]c07s;
wire [31:0]c08s;
wire [31:0]c09s;
wire [31:0]c10s;
wire [31:0]c11s;
wire [31:0]c12s;
wire [31:0]c13s;
wire [31:0]c14s;
wire [31:0]c15s;
wire [31:0]r00s; // Row sums
wire [31:0]r01s;
wire [31:0]r02s;
wire [31:0]r03s;
wire [31:0]r04s;
wire [31:0]r05s;
wire [31:0]r06s;
wire [31:0]r07s;
wire [31:0]r08s;
wire [31:0]r09s;
wire [31:0]r10s;
wire [31:0]r11s;
wire [31:0]r12s;
wire [31:0]r13s;
wire [31:0]r14s;
wire [31:0]r15s;
reg [31:0]c00d; // Column results registered
reg [31:0]c01d;
reg [31:0]c02d;
reg [31:0]c03d;
reg [31:0]c04d;
reg [31:0]c05d;
reg [31:0]c06d;
reg [31:0]c07d;
reg [31:0]c08d;
reg [31:0]c09d;
reg [31:0]c10d;
reg [31:0]c11d;
reg [31:0]c12d;
reg [31:0]c13d;
reg [31:0]c14d;
reg [31:0]c15d;
/* From scrypt.c
#define R(a,b) (((a) << (b)) | ((a) >> (32 - (b))))
for (i = 0; i < 8; i += 2) {
// Operate on columns
x04 ^= R(x00+x12, 7); x09 ^= R(x05+x01, 7); x14 ^= R(x10+x06, 7); x03 ^= R(x15+x11, 7);
x08 ^= R(x04+x00, 9); x13 ^= R(x09+x05, 9); x02 ^= R(x14+x10, 9); x07 ^= R(x03+x15, 9);
x12 ^= R(x08+x04,13); x01 ^= R(x13+x09,13); x06 ^= R(x02+x14,13); x11 ^= R(x07+x03,13);
x00 ^= R(x12+x08,18); x05 ^= R(x01+x13,18); x10 ^= R(x06+x02,18); x15 ^= R(x11+x07,18);
// Operate on rows
x01 ^= R(x00+x03, 7); x06 ^= R(x05+x04, 7); x11 ^= R(x10+x09, 7); x12 ^= R(x15+x14, 7);
x02 ^= R(x01+x00, 9); x07 ^= R(x06+x05, 9); x08 ^= R(x11+x10, 9); x13 ^= R(x12+x15, 9);
x03 ^= R(x02+x01,13); x04 ^= R(x07+x06,13); x09 ^= R(x08+x11,13); x14 ^= R(x13+x12,13);
x00 ^= R(x03+x02,18); x05 ^= R(x04+x07,18); x10 ^= R(x09+x08,18); x15 ^= R(x14+x13,18);
}
*/
// cols
assign c04s = xx[`IDX(0)] + xx[`IDX(12)];
assign c04 = xx[`IDX(4)] ^ { c04s[24:0], c04s[31:25] };
assign c09s = xx[`IDX(5)] + xx[`IDX(1)];
assign c09 = xx[`IDX(9)] ^ { c09s[24:0], c09s[31:25] };
assign c14s = xx[`IDX(10)] + xx[`IDX(6)];
assign c14 = xx[`IDX(14)] ^ { c14s[24:0], c14s[31:25] };
assign c03s = xx[`IDX(15)] + xx[`IDX(11)];
assign c03 = xx[`IDX(03)] ^ { c03s[24:0], c03s[31:25] };
assign c08s = c04 + xx[`IDX(0)];
assign c08 = xx[`IDX(8)] ^ { c08s[22:0], c08s[31:23] };
assign c13s = c09 + xx[`IDX(5)];
assign c13 = xx[`IDX(13)] ^ { c13s[22:0], c13s[31:23] };
assign c02s = c14 + xx[`IDX(10)];
assign c02 = xx[`IDX(2)] ^ { c02s[22:0], c02s[31:23] };
assign c07s = c03 + xx[`IDX(15)];
assign c07 = xx[`IDX(7)] ^ { c07s[22:0], c07s[31:23] };
assign c12s = c08 + c04;
assign c12 = xx[`IDX(12)] ^ { c12s[18:0], c12s[31:19] };
assign c01s = c13 + c09;
assign c01 = xx[`IDX(1)] ^ { c01s[18:0], c01s[31:19] };
assign c06s = c02 + c14;
assign c06 = xx[`IDX(6)] ^ { c06s[18:0], c06s[31:19] };
assign c11s = c07 + c03;
assign c11 = xx[`IDX(11)] ^ { c11s[18:0], c11s[31:19] };
assign c00s = c12 + c08;
assign c00 = xx[`IDX(0)] ^ { c00s[13:0], c00s[31:14] };
assign c05s = c01 + c13;
assign c05 = xx[`IDX(5)] ^ { c05s[13:0], c05s[31:14] };
assign c10s = c06 + c02;
assign c10 = xx[`IDX(10)] ^ { c10s[13:0], c10s[31:14] };
assign c15s = c11 + c07;
assign c15 = xx[`IDX(15)] ^ { c15s[13:0], c15s[31:14] };
// rows
assign r01s = c00d + c03d;
assign r01 = c01d ^ { r01s[24:0], r01s[31:25] };
assign r06s = c05d + c04d;
assign r06 = c06d ^ { r06s[24:0], r06s[31:25] };
assign r11s = c10d + c09d;
assign r11 = c11d ^ { r11s[24:0], r11s[31:25] };
assign r12s = c15d + c14d;
assign r12 = c12d ^ { r12s[24:0], r12s[31:25] };
assign r02s = r01 + c00d;
assign r02 = c02d ^ { r02s[22:0], r02s[31:23] };
assign r07s = r06 + c05d;
assign r07 = c07d ^ { r07s[22:0], r07s[31:23] };
assign r08s = r11 + c10d;
assign r08 = c08d ^ { r08s[22:0], r08s[31:23] };
assign r13s = r12 + c15d;
assign r13 = c13d ^ { r13s[22:0], r13s[31:23] };
assign r03s = r02 + r01;
assign r03 = c03d ^ { r03s[18:0], r03s[31:19] };
assign r04s = r07 + r06;
assign r04 = c04d ^ { r04s[18:0], r04s[31:19] };
assign r09s = r08 + r11;
assign r09 = c09d ^ { r09s[18:0], r09s[31:19] };
assign r14s = r13 + r12;
assign r14 = c14d ^ { r14s[18:0], r14s[31:19] };
assign r00s = r03 + r02;
assign r00 = c00d ^ { r00s[13:0], r00s[31:14] };
assign r05s = r04 + r07;
assign r05 = c05d ^ { r05s[13:0], r05s[31:14] };
assign r10s = r09 + r08;
assign r10 = c10d ^ { r10s[13:0], r10s[31:14] };
assign r15s = r14 + r13;
assign r15 = c15d ^ { r15s[13:0], r15s[31:14] };
wire [511:0]xo; // Rename row results
assign xo = { r15, r14, r13, r12, r11, r10, r09, r08, r07, r06, r05, r04, r03, r02, r01, r00 };
assign Xaddr = xo[9:0]; // Unregistered output
always @ (posedge clk)
begin
c00d <= c00;
c01d <= c01;
c02d <= c02;
c03d <= c03;
c04d <= c04;
c05d <= c05;
c06d <= c06;
c07d <= c07;
c08d <= c08;
c09d <= c09;
c10d <= c10;
c11d <= c11;
c12d <= c12;
c13d <= c13;
c14d <= c14;
c15d <= c15;
out <= xo; // Registered output
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Posted Packet Builder module. This module takes the
// length info from the Posted Packet Slicer, and requests a tag from
// the Tag Generator and uses that info to build a posted memory write header
// which it writes into a FIFO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module posted_pkt_builder(
input clk,
input rst,
input [15:0] req_id, //from pcie block
//to/from posted_pkt_slicer
input posted_fifo_full,
input go,
output reg ack,
input [63:0] dmawad,
input [9:0] length,
//to posted_pkt_header_fifo
output reg [63:0] header_data_out,
output reg header_data_wren
);
//State machine states
localparam IDLE = 4'h0;
localparam HEAD1 = 4'h1;
localparam HEAD2 = 4'h2;
localparam WAIT_FOR_GO_DEASSERT = 4'h3;
//parameters used to define fixed header fields
localparam rsvd = 1'b0; //reserved and unused header fields to zero
localparam MWr = 5'b00000; //format for memory write header
localparam TC = 3'b000; //traffic class 0
localparam TD = 1'b0; //digest bit always 0
localparam EP = 1'b0; //poisoned bit always 0
localparam ATTR = 2'b00; //no snoop or relaxed-ordering
localparam LastBE = 4'b1111; //LastBE is always asserted since all transfers
//are on 128B boundaries and are always at least
//128B long
localparam FirstBE = 4'b1111;//FirstBE is always asserted since all transfers
//are on 128B boundaries
wire [1:0] fmt;
reg [3:0] state;
reg [63:0] dmawad_reg;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
//if the upper DWord of the destination address is zero
//than make the format of the packet header 3DW; otherwise 4DW
assign fmt[1:0] = (dmawad_reg[63:32] == 0) ? 2'b10 : 2'b11;
//if the posted_pkt_slicer asserts "go" then register the dma write params
always@(posedge clk)begin
if(rst_reg)begin
dmawad_reg[63:0] <= 0;
end else if(go)begin
dmawad_reg <= dmawad;
end
end
// State machine
// Builds headers for posted memory writes
// Writes them into a FIFO
always @ (posedge clk) begin
if (rst_reg) begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end else begin
case (state)
IDLE : begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
if(go & ~posted_fifo_full) // Jiansong: prevent p_hdr_fifo overflow
state<= HEAD1;
else
state<= IDLE;
end
HEAD1 : begin
//write the first 64-bits of a posted header into the
//posted fifo
header_data_out <= {rsvd,fmt[1:0],MWr,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
TD,EP,ATTR,rsvd,rsvd,length[9:0],req_id[15:0],
8'b00000000 ,LastBE,FirstBE};
ack <= 0;
header_data_wren <= 1'b1;
state <= HEAD2;
end
HEAD2 : begin
//write the next 32 or 64 bits of a posted header to the
//posted header fifo (32 if 3DW - 64 if 4DW header)
header_data_out <= (fmt[0]==1'b1)
? {dmawad_reg[63:2],2'b00}
: {dmawad_reg[31:2], 2'b00, dmawad_reg[63:32]};
header_data_wren <= 1'b1;
ack <= 1'b1; //acknowledge to the posted_packet_slicer that
//the packet has been queued up for transmission
state <= WAIT_FOR_GO_DEASSERT;
end
WAIT_FOR_GO_DEASSERT: begin
//ack causes "go" to deassert but we need to give the
//posted_pkt_slicer a chance to deassert "go" before returning
//to IDLE
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end
default : begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_8_V
`define SKY130_FD_SC_HVL__BUF_8_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__buf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_8_V
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** Base-2 Logarithm *)
Require Import NZAxioms NZMulOrder NZPow.
(** Interface of a log2 function, then its specification on naturals *)
Module Type Log2 (Import A : Typ).
Parameter Inline log2 : t -> t.
End Log2.
Module Type NZLog2Spec (A : NZOrdAxiomsSig')(B : Pow' A)(C : Log2 A).
Import A B C.
Axiom log2_spec : forall a, 0<a -> 2^(log2 a) <= a < 2^(S (log2 a)).
Axiom log2_nonpos : forall a, a<=0 -> log2 a == 0.
End NZLog2Spec.
Module Type NZLog2 (A : NZOrdAxiomsSig)(B : Pow A) := Log2 A <+ NZLog2Spec A B.
(** Derived properties of logarithm *)
Module Type NZLog2Prop
(Import A : NZOrdAxiomsSig')
(Import B : NZPow' A)
(Import C : NZLog2 A B)
(Import D : NZMulOrderProp A)
(Import E : NZPowProp A B D).
(** log2 is always non-negative *)
Lemma log2_nonneg : forall a, 0 <= log2 a.
Proof.
intros a. destruct (le_gt_cases a 0) as [Ha|Ha].
now rewrite log2_nonpos.
destruct (log2_spec a Ha) as (_,LT).
apply lt_succ_r, (pow_gt_1 2). order'.
rewrite <- le_succ_l, <- one_succ in Ha. order.
Qed.
(** A tactic for proving positivity and non-negativity *)
Ltac order_pos :=
((apply add_pos_pos || apply add_nonneg_nonneg ||
apply mul_pos_pos || apply mul_nonneg_nonneg ||
apply pow_nonneg || apply pow_pos_nonneg ||
apply log2_nonneg || apply (le_le_succ_r 0));
order_pos) (* in case of success of an apply, we recurse *)
|| order'. (* otherwise *)
(** The spec of log2 indeed determines it *)
Lemma log2_unique : forall a b, 0<=b -> 2^b<=a<2^(S b) -> log2 a == b.
Proof.
intros a b Hb (LEb,LTb).
assert (Ha : 0 < a).
apply lt_le_trans with (2^b); trivial.
apply pow_pos_nonneg; order'.
assert (Hc := log2_nonneg a).
destruct (log2_spec a Ha) as (LEc,LTc).
assert (log2 a <= b).
apply lt_succ_r, (pow_lt_mono_r_iff 2); try order'.
now apply le_le_succ_r.
assert (b <= log2 a).
apply lt_succ_r, (pow_lt_mono_r_iff 2); try order'.
now apply le_le_succ_r.
order.
Qed.
(** Hence log2 is a morphism. *)
Instance log2_wd : Proper (eq==>eq) log2.
Proof.
intros x x' Hx.
destruct (le_gt_cases x 0).
rewrite 2 log2_nonpos; trivial. reflexivity. now rewrite <- Hx.
apply log2_unique. apply log2_nonneg.
rewrite Hx in *. now apply log2_spec.
Qed.
(** An alternate specification *)
Lemma log2_spec_alt : forall a, 0<a -> exists r,
a == 2^(log2 a) + r /\ 0 <= r < 2^(log2 a).
Proof.
intros a Ha.
destruct (log2_spec _ Ha) as (LE,LT).
destruct (le_exists_sub _ _ LE) as (r & Hr & Hr').
exists r.
split. now rewrite add_comm.
split. trivial.
apply (add_lt_mono_r _ _ (2^log2 a)).
rewrite <- Hr. generalize LT.
rewrite pow_succ_r by order_pos.
rewrite two_succ at 1. now nzsimpl.
Qed.
Lemma log2_unique' : forall a b c, 0<=b -> 0<=c<2^b ->
a == 2^b + c -> log2 a == b.
Proof.
intros a b c Hb (Hc,H) EQ.
apply log2_unique. trivial.
rewrite EQ.
split.
rewrite <- add_0_r at 1. now apply add_le_mono_l.
rewrite pow_succ_r by order.
rewrite two_succ at 2. nzsimpl. now apply add_lt_mono_l.
Qed.
(** log2 is exact on powers of 2 *)
Lemma log2_pow2 : forall a, 0<=a -> log2 (2^a) == a.
Proof.
intros a Ha.
apply log2_unique' with 0; trivial.
split; order_pos. now nzsimpl.
Qed.
(** log2 and predecessors of powers of 2 *)
Lemma log2_pred_pow2 : forall a, 0<a -> log2 (P (2^a)) == P a.
Proof.
intros a Ha.
assert (Ha' : S (P a) == a) by (now rewrite lt_succ_pred with 0).
apply log2_unique.
apply lt_succ_r; order.
rewrite <-le_succ_l, <-lt_succ_r, Ha'.
rewrite lt_succ_pred with 0.
split; try easy. apply pow_lt_mono_r_iff; try order'.
rewrite succ_lt_mono, Ha'. apply lt_succ_diag_r.
apply pow_pos_nonneg; order'.
Qed.
(** log2 and basic constants *)
Lemma log2_1 : log2 1 == 0.
Proof.
rewrite <- (pow_0_r 2). now apply log2_pow2.
Qed.
Lemma log2_2 : log2 2 == 1.
Proof.
rewrite <- (pow_1_r 2). apply log2_pow2; order'.
Qed.
(** log2 n is strictly positive for 1<n *)
Lemma log2_pos : forall a, 1<a -> 0 < log2 a.
Proof.
intros a Ha.
assert (Ha' : 0 < a) by order'.
assert (H := log2_nonneg a). le_elim H; trivial.
generalize (log2_spec a Ha'). rewrite <- H in *. nzsimpl; try order.
intros (_,H'). rewrite two_succ in H'. apply lt_succ_r in H'; order.
Qed.
(** Said otherwise, log2 is null only below 1 *)
Lemma log2_null : forall a, log2 a == 0 <-> a <= 1.
Proof.
intros a. split; intros H.
destruct (le_gt_cases a 1) as [Ha|Ha]; trivial.
generalize (log2_pos a Ha); order.
le_elim H.
apply log2_nonpos. apply lt_succ_r. now rewrite <- one_succ.
rewrite H. apply log2_1.
Qed.
(** log2 is a monotone function (but not a strict one) *)
Lemma log2_le_mono : forall a b, a<=b -> log2 a <= log2 b.
Proof.
intros a b H.
destruct (le_gt_cases a 0) as [Ha|Ha].
rewrite log2_nonpos; order_pos.
assert (Hb : 0 < b) by order.
destruct (log2_spec a Ha) as (LEa,_).
destruct (log2_spec b Hb) as (_,LTb).
apply lt_succ_r, (pow_lt_mono_r_iff 2); order_pos.
Qed.
(** No reverse result for <=, consider for instance log2 3 <= log2 2 *)
Lemma log2_lt_cancel : forall a b, log2 a < log2 b -> a < b.
Proof.
intros a b H.
destruct (le_gt_cases b 0) as [Hb|Hb].
rewrite (log2_nonpos b) in H; trivial.
generalize (log2_nonneg a); order.
destruct (le_gt_cases a 0) as [Ha|Ha]. order.
destruct (log2_spec a Ha) as (_,LTa).
destruct (log2_spec b Hb) as (LEb,_).
apply le_succ_l in H.
apply (pow_le_mono_r_iff 2) in H; order_pos.
Qed.
(** When left side is a power of 2, we have an equivalence for <= *)
Lemma log2_le_pow2 : forall a b, 0<a -> (2^b<=a <-> b <= log2 a).
Proof.
intros a b Ha.
split; intros H.
destruct (lt_ge_cases b 0) as [Hb|Hb].
generalize (log2_nonneg a); order.
rewrite <- (log2_pow2 b); trivial. now apply log2_le_mono.
transitivity (2^(log2 a)).
apply pow_le_mono_r; order'.
now destruct (log2_spec a Ha).
Qed.
(** When right side is a square, we have an equivalence for < *)
Lemma log2_lt_pow2 : forall a b, 0<a -> (a<2^b <-> log2 a < b).
Proof.
intros a b Ha.
split; intros H.
destruct (lt_ge_cases b 0) as [Hb|Hb].
rewrite pow_neg_r in H; order.
apply (pow_lt_mono_r_iff 2); try order_pos.
apply le_lt_trans with a; trivial.
now destruct (log2_spec a Ha).
destruct (lt_ge_cases b 0) as [Hb|Hb].
generalize (log2_nonneg a); order.
apply log2_lt_cancel; try order.
now rewrite log2_pow2.
Qed.
(** Comparing log2 and identity *)
Lemma log2_lt_lin : forall a, 0<a -> log2 a < a.
Proof.
intros a Ha.
apply (pow_lt_mono_r_iff 2); try order_pos.
apply le_lt_trans with a.
now destruct (log2_spec a Ha).
apply pow_gt_lin_r; order'.
Qed.
Lemma log2_le_lin : forall a, 0<=a -> log2 a <= a.
Proof.
intros a Ha.
le_elim Ha.
now apply lt_le_incl, log2_lt_lin.
rewrite <- Ha, log2_nonpos; order.
Qed.
(** Log2 and multiplication. *)
(** Due to rounding error, we don't have the usual
[log2 (a*b) = log2 a + log2 b] but we may be off by 1 at most *)
Lemma log2_mul_below : forall a b, 0<a -> 0<b ->
log2 a + log2 b <= log2 (a*b).
Proof.
intros a b Ha Hb.
apply log2_le_pow2; try order_pos.
rewrite pow_add_r by order_pos.
apply mul_le_mono_nonneg; try apply log2_spec; order_pos.
Qed.
Lemma log2_mul_above : forall a b, 0<=a -> 0<=b ->
log2 (a*b) <= log2 a + log2 b + 1.
Proof.
intros a b Ha Hb.
le_elim Ha.
le_elim Hb.
apply lt_succ_r.
rewrite add_1_r, <- add_succ_r, <- add_succ_l.
apply log2_lt_pow2; try order_pos.
rewrite pow_add_r by order_pos.
apply mul_lt_mono_nonneg; try order; now apply log2_spec.
rewrite <- Hb. nzsimpl. rewrite log2_nonpos; order_pos.
rewrite <- Ha. nzsimpl. rewrite log2_nonpos; order_pos.
Qed.
(** And we can't find better approximations in general.
- The lower bound is exact for powers of 2.
- Concerning the upper bound, for any c>1, take a=b=2^c-1,
then log2 (a*b) = c+c -1 while (log2 a) = (log2 b) = c-1
*)
(** At least, we get back the usual equation when we multiply by 2 (or 2^k) *)
Lemma log2_mul_pow2 : forall a b, 0<a -> 0<=b -> log2 (a*2^b) == b + log2 a.
Proof.
intros a b Ha Hb.
apply log2_unique; try order_pos. split.
rewrite pow_add_r, mul_comm; try order_pos.
apply mul_le_mono_nonneg_r. order_pos. now apply log2_spec.
rewrite <-add_succ_r, pow_add_r, mul_comm; try order_pos.
apply mul_lt_mono_pos_l. order_pos. now apply log2_spec.
Qed.
Lemma log2_double : forall a, 0<a -> log2 (2*a) == S (log2 a).
Proof.
intros a Ha. generalize (log2_mul_pow2 a 1 Ha le_0_1). now nzsimpl'.
Qed.
(** Two numbers with same log2 cannot be far away. *)
Lemma log2_same : forall a b, 0<a -> 0<b -> log2 a == log2 b -> a < 2*b.
Proof.
intros a b Ha Hb H.
apply log2_lt_cancel. rewrite log2_double, H by trivial.
apply lt_succ_diag_r.
Qed.
(** Log2 and successor :
- the log2 function climbs by at most 1 at a time
- otherwise it stays at the same value
- the +1 steps occur for powers of two
*)
Lemma log2_succ_le : forall a, log2 (S a) <= S (log2 a).
Proof.
intros a.
destruct (lt_trichotomy 0 a) as [LT|[EQ|LT]].
apply (pow_le_mono_r_iff 2); try order_pos.
transitivity (S a).
apply log2_spec.
apply lt_succ_r; order.
now apply le_succ_l, log2_spec.
rewrite <- EQ, <- one_succ, log2_1; order_pos.
rewrite 2 log2_nonpos. order_pos. order'. now rewrite le_succ_l.
Qed.
Lemma log2_succ_or : forall a,
log2 (S a) == S (log2 a) \/ log2 (S a) == log2 a.
Proof.
intros.
destruct (le_gt_cases (log2 (S a)) (log2 a)) as [H|H].
right. generalize (log2_le_mono _ _ (le_succ_diag_r a)); order.
left. apply le_succ_l in H. generalize (log2_succ_le a); order.
Qed.
Lemma log2_eq_succ_is_pow2 : forall a,
log2 (S a) == S (log2 a) -> exists b, S a == 2^b.
Proof.
intros a H.
destruct (le_gt_cases a 0) as [Ha|Ha].
rewrite 2 (proj2 (log2_null _)) in H. generalize (lt_succ_diag_r 0); order.
order'. apply le_succ_l. order'.
assert (Ha' : 0 < S a) by (apply lt_succ_r; order).
exists (log2 (S a)).
generalize (proj1 (log2_spec (S a) Ha')) (proj2 (log2_spec a Ha)).
rewrite <- le_succ_l, <- H. order.
Qed.
Lemma log2_eq_succ_iff_pow2 : forall a, 0<a ->
(log2 (S a) == S (log2 a) <-> exists b, S a == 2^b).
Proof.
intros a Ha.
split. apply log2_eq_succ_is_pow2.
intros (b,Hb).
assert (Hb' : 0 < b).
apply (pow_gt_1 2); try order'; now rewrite <- Hb, one_succ, <- succ_lt_mono.
rewrite Hb, log2_pow2; try order'.
setoid_replace a with (P (2^b)). rewrite log2_pred_pow2; trivial.
symmetry; now apply lt_succ_pred with 0.
apply succ_inj. rewrite Hb. symmetry. apply lt_succ_pred with 0.
rewrite <- Hb, lt_succ_r; order.
Qed.
Lemma log2_succ_double : forall a, 0<a -> log2 (2*a+1) == S (log2 a).
Proof.
intros a Ha.
rewrite add_1_r.
destruct (log2_succ_or (2*a)) as [H|H]; [exfalso|now rewrite H, log2_double].
apply log2_eq_succ_is_pow2 in H. destruct H as (b,H).
destruct (lt_trichotomy b 0) as [LT|[EQ|LT]].
rewrite pow_neg_r in H; trivial.
apply (mul_pos_pos 2), succ_lt_mono in Ha; try order'.
rewrite <- one_succ in Ha. order'.
rewrite EQ, pow_0_r in H.
apply (mul_pos_pos 2), succ_lt_mono in Ha; try order'.
rewrite <- one_succ in Ha. order'.
assert (EQ:=lt_succ_pred 0 b LT).
rewrite <- EQ, pow_succ_r in H; [|now rewrite <- lt_succ_r, EQ].
destruct (lt_ge_cases a (2^(P b))) as [LT'|LE'].
generalize (mul_2_mono_l _ _ LT'). rewrite add_1_l. order.
rewrite (mul_le_mono_pos_l _ _ 2) in LE'; try order'.
rewrite <- H in LE'. apply le_succ_l in LE'. order.
Qed.
(** Log2 and addition *)
Lemma log2_add_le : forall a b, a~=1 -> b~=1 -> log2 (a+b) <= log2 a + log2 b.
Proof.
intros a b Ha Hb.
destruct (lt_trichotomy a 1) as [Ha'|[Ha'|Ha']]; [|order|].
rewrite one_succ, lt_succ_r in Ha'.
rewrite (log2_nonpos a); trivial. nzsimpl. apply log2_le_mono.
rewrite <- (add_0_l b) at 2. now apply add_le_mono.
destruct (lt_trichotomy b 1) as [Hb'|[Hb'|Hb']]; [|order|].
rewrite one_succ, lt_succ_r in Hb'.
rewrite (log2_nonpos b); trivial. nzsimpl. apply log2_le_mono.
rewrite <- (add_0_r a) at 2. now apply add_le_mono.
clear Ha Hb.
apply lt_succ_r.
apply log2_lt_pow2; try order_pos.
rewrite pow_succ_r by order_pos.
rewrite two_succ, one_succ at 1. nzsimpl.
apply add_lt_mono.
apply lt_le_trans with (2^(S (log2 a))). apply log2_spec; order'.
apply pow_le_mono_r. order'. rewrite <- add_1_r. apply add_le_mono_l.
rewrite one_succ; now apply le_succ_l, log2_pos.
apply lt_le_trans with (2^(S (log2 b))). apply log2_spec; order'.
apply pow_le_mono_r. order'. rewrite <- add_1_l. apply add_le_mono_r.
rewrite one_succ; now apply le_succ_l, log2_pos.
Qed.
(** The sum of two log2 is less than twice the log2 of the sum.
The large inequality is obvious thanks to monotonicity.
The strict one requires some more work. This is almost
a convexity inequality for points [2a], [2b] and their middle [a+b] :
ideally, we would have [2*log(a+b) >= log(2a)+log(2b) = 2+log a+log b].
Here, we cannot do better: consider for instance a=2 b=4, then 1+2<2*2
*)
Lemma add_log2_lt : forall a b, 0<a -> 0<b ->
log2 a + log2 b < 2 * log2 (a+b).
Proof.
intros a b Ha Hb. nzsimpl'.
assert (H : log2 a <= log2 (a+b)).
apply log2_le_mono. rewrite <- (add_0_r a) at 1. apply add_le_mono; order.
assert (H' : log2 b <= log2 (a+b)).
apply log2_le_mono. rewrite <- (add_0_l b) at 1. apply add_le_mono; order.
le_elim H.
apply lt_le_trans with (log2 (a+b) + log2 b).
now apply add_lt_mono_r. now apply add_le_mono_l.
rewrite <- H at 1. apply add_lt_mono_l.
le_elim H'; trivial.
symmetry in H. apply log2_same in H; try order_pos.
symmetry in H'. apply log2_same in H'; try order_pos.
revert H H'. nzsimpl'. rewrite <- add_lt_mono_l, <- add_lt_mono_r; order.
Qed.
End NZLog2Prop.
Module NZLog2UpProp
(Import A : NZDecOrdAxiomsSig')
(Import B : NZPow' A)
(Import C : NZLog2 A B)
(Import D : NZMulOrderProp A)
(Import E : NZPowProp A B D)
(Import F : NZLog2Prop A B C D E).
(** * [log2_up] : a binary logarithm that rounds up instead of down *)
(** For once, we define instead of axiomatizing, thanks to log2 *)
Definition log2_up a :=
match compare 1 a with
| Lt => S (log2 (P a))
| _ => 0
end.
Lemma log2_up_eqn0 : forall a, a<=1 -> log2_up a == 0.
Proof.
intros a Ha. unfold log2_up. case compare_spec; try order.
Qed.
Lemma log2_up_eqn : forall a, 1<a -> log2_up a == S (log2 (P a)).
Proof.
intros a Ha. unfold log2_up. case compare_spec; try order.
Qed.
Lemma log2_up_spec : forall a, 1<a ->
2^(P (log2_up a)) < a <= 2^(log2_up a).
Proof.
intros a Ha.
rewrite log2_up_eqn; trivial.
rewrite pred_succ.
rewrite <- (lt_succ_pred 1 a Ha) at 2 3.
rewrite lt_succ_r, le_succ_l.
apply log2_spec.
apply succ_lt_mono. now rewrite (lt_succ_pred 1 a Ha), <- one_succ.
Qed.
Lemma log2_up_nonpos : forall a, a<=0 -> log2_up a == 0.
Proof.
intros. apply log2_up_eqn0. order'.
Qed.
Instance log2_up_wd : Proper (eq==>eq) log2_up.
Proof.
assert (Proper (eq==>eq==>Logic.eq) compare).
repeat red; intros; do 2 case compare_spec; trivial; order.
intros a a' Ha. unfold log2_up. rewrite Ha at 1.
case compare; now rewrite ?Ha.
Qed.
(** [log2_up] is always non-negative *)
Lemma log2_up_nonneg : forall a, 0 <= log2_up a.
Proof.
intros a. unfold log2_up. case compare_spec; try order.
intros. apply le_le_succ_r, log2_nonneg.
Qed.
(** The spec of [log2_up] indeed determines it *)
Lemma log2_up_unique : forall a b, 0<b -> 2^(P b)<a<=2^b -> log2_up a == b.
Proof.
intros a b Hb (LEb,LTb).
assert (Ha : 1 < a).
apply le_lt_trans with (2^(P b)); trivial.
rewrite one_succ. apply le_succ_l.
apply pow_pos_nonneg. order'. apply lt_succ_r.
now rewrite (lt_succ_pred 0 b Hb).
assert (Hc := log2_up_nonneg a).
destruct (log2_up_spec a Ha) as (LTc,LEc).
assert (b <= log2_up a).
apply lt_succ_r. rewrite <- (lt_succ_pred 0 b Hb).
rewrite <- succ_lt_mono.
apply (pow_lt_mono_r_iff 2); try order'.
assert (Hc' : 0 < log2_up a) by order.
assert (log2_up a <= b).
apply lt_succ_r. rewrite <- (lt_succ_pred 0 _ Hc').
rewrite <- succ_lt_mono.
apply (pow_lt_mono_r_iff 2); try order'.
order.
Qed.
(** [log2_up] is exact on powers of 2 *)
Lemma log2_up_pow2 : forall a, 0<=a -> log2_up (2^a) == a.
Proof.
intros a Ha.
le_elim Ha.
apply log2_up_unique; trivial.
split; try order.
apply pow_lt_mono_r; try order'.
rewrite <- (lt_succ_pred 0 a Ha) at 2.
now apply lt_succ_r.
now rewrite <- Ha, pow_0_r, log2_up_eqn0.
Qed.
(** [log2_up] and successors of powers of 2 *)
Lemma log2_up_succ_pow2 : forall a, 0<=a -> log2_up (S (2^a)) == S a.
Proof.
intros a Ha.
rewrite log2_up_eqn, pred_succ, log2_pow2; try easy.
rewrite one_succ, <- succ_lt_mono. apply pow_pos_nonneg; order'.
Qed.
(** Basic constants *)
Lemma log2_up_1 : log2_up 1 == 0.
Proof.
now apply log2_up_eqn0.
Qed.
Lemma log2_up_2 : log2_up 2 == 1.
Proof.
rewrite <- (pow_1_r 2). apply log2_up_pow2; order'.
Qed.
(** Links between log2 and [log2_up] *)
Lemma le_log2_log2_up : forall a, log2 a <= log2_up a.
Proof.
intros a. unfold log2_up. case compare_spec; intros H.
rewrite <- H, log2_1. order.
rewrite <- (lt_succ_pred 1 a H) at 1. apply log2_succ_le.
rewrite log2_nonpos. order. now rewrite <-lt_succ_r, <-one_succ.
Qed.
Lemma le_log2_up_succ_log2 : forall a, log2_up a <= S (log2 a).
Proof.
intros a. unfold log2_up. case compare_spec; intros H; try order_pos.
rewrite <- succ_le_mono. apply log2_le_mono.
rewrite <- (lt_succ_pred 1 a H) at 2. apply le_succ_diag_r.
Qed.
Lemma log2_log2_up_spec : forall a, 0<a ->
2^log2 a <= a <= 2^log2_up a.
Proof.
intros a H. split.
now apply log2_spec.
rewrite <-le_succ_l, <-one_succ in H. le_elim H.
now apply log2_up_spec.
now rewrite <-H, log2_up_1, pow_0_r.
Qed.
Lemma log2_log2_up_exact :
forall a, 0<a -> (log2 a == log2_up a <-> exists b, a == 2^b).
Proof.
intros a Ha.
split. intros. exists (log2 a).
generalize (log2_log2_up_spec a Ha). rewrite <-H.
destruct 1; order.
intros (b,Hb). rewrite Hb.
destruct (le_gt_cases 0 b).
now rewrite log2_pow2, log2_up_pow2.
rewrite pow_neg_r; trivial. now rewrite log2_nonpos, log2_up_nonpos.
Qed.
(** [log2_up] n is strictly positive for 1<n *)
Lemma log2_up_pos : forall a, 1<a -> 0 < log2_up a.
Proof.
intros. rewrite log2_up_eqn; trivial. apply lt_succ_r; order_pos.
Qed.
(** Said otherwise, [log2_up] is null only below 1 *)
Lemma log2_up_null : forall a, log2_up a == 0 <-> a <= 1.
Proof.
intros a. split; intros H.
destruct (le_gt_cases a 1) as [Ha|Ha]; trivial.
generalize (log2_up_pos a Ha); order.
now apply log2_up_eqn0.
Qed.
(** [log2_up] is a monotone function (but not a strict one) *)
Lemma log2_up_le_mono : forall a b, a<=b -> log2_up a <= log2_up b.
Proof.
intros a b H.
destruct (le_gt_cases a 1) as [Ha|Ha].
rewrite log2_up_eqn0; trivial. apply log2_up_nonneg.
rewrite 2 log2_up_eqn; try order.
rewrite <- succ_le_mono. apply log2_le_mono, succ_le_mono.
rewrite 2 lt_succ_pred with 1; order.
Qed.
(** No reverse result for <=, consider for instance log2_up 4 <= log2_up 3 *)
Lemma log2_up_lt_cancel : forall a b, log2_up a < log2_up b -> a < b.
Proof.
intros a b H.
destruct (le_gt_cases b 1) as [Hb|Hb].
rewrite (log2_up_eqn0 b) in H; trivial.
generalize (log2_up_nonneg a); order.
destruct (le_gt_cases a 1) as [Ha|Ha]. order.
rewrite 2 log2_up_eqn in H; try order.
rewrite <- succ_lt_mono in H. apply log2_lt_cancel, succ_lt_mono in H.
rewrite 2 lt_succ_pred with 1 in H; order.
Qed.
(** When left side is a power of 2, we have an equivalence for < *)
Lemma log2_up_lt_pow2 : forall a b, 0<a -> (2^b<a <-> b < log2_up a).
Proof.
intros a b Ha.
split; intros H.
destruct (lt_ge_cases b 0) as [Hb|Hb].
generalize (log2_up_nonneg a); order.
apply (pow_lt_mono_r_iff 2). order'. apply log2_up_nonneg.
apply lt_le_trans with a; trivial.
apply (log2_up_spec a).
apply le_lt_trans with (2^b); trivial.
rewrite one_succ, le_succ_l. apply pow_pos_nonneg; order'.
destruct (lt_ge_cases b 0) as [Hb|Hb].
now rewrite pow_neg_r.
rewrite <- (log2_up_pow2 b) in H; trivial. now apply log2_up_lt_cancel.
Qed.
(** When right side is a square, we have an equivalence for <= *)
Lemma log2_up_le_pow2 : forall a b, 0<a -> (a<=2^b <-> log2_up a <= b).
Proof.
intros a b Ha.
split; intros H.
destruct (lt_ge_cases b 0) as [Hb|Hb].
rewrite pow_neg_r in H; order.
rewrite <- (log2_up_pow2 b); trivial. now apply log2_up_le_mono.
transitivity (2^(log2_up a)).
now apply log2_log2_up_spec.
apply pow_le_mono_r; order'.
Qed.
(** Comparing [log2_up] and identity *)
Lemma log2_up_lt_lin : forall a, 0<a -> log2_up a < a.
Proof.
intros a Ha.
assert (H : S (P a) == a) by (now apply lt_succ_pred with 0).
rewrite <- H at 2. apply lt_succ_r. apply log2_up_le_pow2; trivial.
rewrite <- H at 1. apply le_succ_l.
apply pow_gt_lin_r. order'. apply lt_succ_r; order.
Qed.
Lemma log2_up_le_lin : forall a, 0<=a -> log2_up a <= a.
Proof.
intros a Ha.
le_elim Ha.
now apply lt_le_incl, log2_up_lt_lin.
rewrite <- Ha, log2_up_nonpos; order.
Qed.
(** [log2_up] and multiplication. *)
(** Due to rounding error, we don't have the usual
[log2_up (a*b) = log2_up a + log2_up b] but we may be off by 1 at most *)
Lemma log2_up_mul_above : forall a b, 0<=a -> 0<=b ->
log2_up (a*b) <= log2_up a + log2_up b.
Proof.
intros a b Ha Hb.
assert (Ha':=log2_up_nonneg a).
assert (Hb':=log2_up_nonneg b).
le_elim Ha.
le_elim Hb.
apply log2_up_le_pow2; try order_pos.
rewrite pow_add_r; trivial.
apply mul_le_mono_nonneg; try apply log2_log2_up_spec; order'.
rewrite <- Hb. nzsimpl. rewrite log2_up_nonpos; order_pos.
rewrite <- Ha. nzsimpl. rewrite log2_up_nonpos; order_pos.
Qed.
Lemma log2_up_mul_below : forall a b, 0<a -> 0<b ->
log2_up a + log2_up b <= S (log2_up (a*b)).
Proof.
intros a b Ha Hb.
rewrite <-le_succ_l, <-one_succ in Ha. le_elim Ha.
rewrite <-le_succ_l, <-one_succ in Hb. le_elim Hb.
assert (Ha' : 0 < log2_up a) by (apply log2_up_pos; trivial).
assert (Hb' : 0 < log2_up b) by (apply log2_up_pos; trivial).
rewrite <- (lt_succ_pred 0 (log2_up a)); trivial.
rewrite <- (lt_succ_pred 0 (log2_up b)); trivial.
nzsimpl. rewrite <- succ_le_mono, le_succ_l.
apply (pow_lt_mono_r_iff 2). order'. apply log2_up_nonneg.
rewrite pow_add_r; try (apply lt_succ_r; rewrite (lt_succ_pred 0); trivial).
apply lt_le_trans with (a*b).
apply mul_lt_mono_nonneg; try order_pos; try now apply log2_up_spec.
apply log2_up_spec.
setoid_replace 1 with (1*1) by now nzsimpl.
apply mul_lt_mono_nonneg; order'.
rewrite <- Hb, log2_up_1; nzsimpl. apply le_succ_diag_r.
rewrite <- Ha, log2_up_1; nzsimpl. apply le_succ_diag_r.
Qed.
(** And we can't find better approximations in general.
- The upper bound is exact for powers of 2.
- Concerning the lower bound, for any c>1, take a=b=2^c+1,
then [log2_up (a*b) = c+c +1] while [(log2_up a) = (log2_up b) = c+1]
*)
(** At least, we get back the usual equation when we multiply by 2 (or 2^k) *)
Lemma log2_up_mul_pow2 : forall a b, 0<a -> 0<=b ->
log2_up (a*2^b) == b + log2_up a.
Proof.
intros a b Ha Hb.
rewrite <- le_succ_l, <- one_succ in Ha; le_elim Ha.
apply log2_up_unique. apply add_nonneg_pos; trivial. now apply log2_up_pos.
split.
assert (EQ := lt_succ_pred 0 _ (log2_up_pos _ Ha)).
rewrite <- EQ. nzsimpl. rewrite pow_add_r, mul_comm; trivial.
apply mul_lt_mono_pos_r. order_pos. now apply log2_up_spec.
rewrite <- lt_succ_r, EQ. now apply log2_up_pos.
rewrite pow_add_r, mul_comm; trivial.
apply mul_le_mono_nonneg_l. order_pos. now apply log2_up_spec.
apply log2_up_nonneg.
now rewrite <- Ha, mul_1_l, log2_up_1, add_0_r, log2_up_pow2.
Qed.
Lemma log2_up_double : forall a, 0<a -> log2_up (2*a) == S (log2_up a).
Proof.
intros a Ha. generalize (log2_up_mul_pow2 a 1 Ha le_0_1). now nzsimpl'.
Qed.
(** Two numbers with same [log2_up] cannot be far away. *)
Lemma log2_up_same : forall a b, 0<a -> 0<b -> log2_up a == log2_up b -> a < 2*b.
Proof.
intros a b Ha Hb H.
apply log2_up_lt_cancel. rewrite log2_up_double, H by trivial.
apply lt_succ_diag_r.
Qed.
(** [log2_up] and successor :
- the [log2_up] function climbs by at most 1 at a time
- otherwise it stays at the same value
- the +1 steps occur after powers of two
*)
Lemma log2_up_succ_le : forall a, log2_up (S a) <= S (log2_up a).
Proof.
intros a.
destruct (lt_trichotomy 1 a) as [LT|[EQ|LT]].
rewrite 2 log2_up_eqn; trivial.
rewrite pred_succ, <- succ_le_mono. rewrite <-(lt_succ_pred 1 a LT) at 1.
apply log2_succ_le.
apply lt_succ_r; order.
rewrite <- EQ, <- two_succ, log2_up_1, log2_up_2. now nzsimpl'.
rewrite 2 log2_up_eqn0. order_pos. order'. now rewrite le_succ_l.
Qed.
Lemma log2_up_succ_or : forall a,
log2_up (S a) == S (log2_up a) \/ log2_up (S a) == log2_up a.
Proof.
intros.
destruct (le_gt_cases (log2_up (S a)) (log2_up a)).
right. generalize (log2_up_le_mono _ _ (le_succ_diag_r a)); order.
left. apply le_succ_l in H. generalize (log2_up_succ_le a); order.
Qed.
Lemma log2_up_eq_succ_is_pow2 : forall a,
log2_up (S a) == S (log2_up a) -> exists b, a == 2^b.
Proof.
intros a H.
destruct (le_gt_cases a 0) as [Ha|Ha].
rewrite 2 (proj2 (log2_up_null _)) in H. generalize (lt_succ_diag_r 0); order.
order'. apply le_succ_l. order'.
assert (Ha' : 1 < S a) by (now rewrite one_succ, <- succ_lt_mono).
exists (log2_up a).
generalize (proj1 (log2_up_spec (S a) Ha')) (proj2 (log2_log2_up_spec a Ha)).
rewrite H, pred_succ, lt_succ_r. order.
Qed.
Lemma log2_up_eq_succ_iff_pow2 : forall a, 0<a ->
(log2_up (S a) == S (log2_up a) <-> exists b, a == 2^b).
Proof.
intros a Ha.
split. apply log2_up_eq_succ_is_pow2.
intros (b,Hb).
destruct (lt_ge_cases b 0) as [Hb'|Hb'].
rewrite pow_neg_r in Hb; order.
rewrite Hb, log2_up_pow2; try order'.
now rewrite log2_up_succ_pow2.
Qed.
Lemma log2_up_succ_double : forall a, 0<a ->
log2_up (2*a+1) == 2 + log2 a.
Proof.
intros a Ha.
rewrite log2_up_eqn. rewrite add_1_r, pred_succ, log2_double; now nzsimpl'.
apply le_lt_trans with (0+1). now nzsimpl'.
apply add_lt_mono_r. order_pos.
Qed.
(** [log2_up] and addition *)
Lemma log2_up_add_le : forall a b, a~=1 -> b~=1 ->
log2_up (a+b) <= log2_up a + log2_up b.
Proof.
intros a b Ha Hb.
destruct (lt_trichotomy a 1) as [Ha'|[Ha'|Ha']]; [|order|].
rewrite (log2_up_eqn0 a) by order. nzsimpl. apply log2_up_le_mono.
rewrite one_succ, lt_succ_r in Ha'.
rewrite <- (add_0_l b) at 2. now apply add_le_mono.
destruct (lt_trichotomy b 1) as [Hb'|[Hb'|Hb']]; [|order|].
rewrite (log2_up_eqn0 b) by order. nzsimpl. apply log2_up_le_mono.
rewrite one_succ, lt_succ_r in Hb'.
rewrite <- (add_0_r a) at 2. now apply add_le_mono.
clear Ha Hb.
transitivity (log2_up (a*b)).
now apply log2_up_le_mono, add_le_mul.
apply log2_up_mul_above; order'.
Qed.
(** The sum of two [log2_up] is less than twice the [log2_up] of the sum.
The large inequality is obvious thanks to monotonicity.
The strict one requires some more work. This is almost
a convexity inequality for points [2a], [2b] and their middle [a+b] :
ideally, we would have [2*log(a+b) >= log(2a)+log(2b) = 2+log a+log b].
Here, we cannot do better: consider for instance a=3 b=5, then 2+3<2*3
*)
Lemma add_log2_up_lt : forall a b, 0<a -> 0<b ->
log2_up a + log2_up b < 2 * log2_up (a+b).
Proof.
intros a b Ha Hb. nzsimpl'.
assert (H : log2_up a <= log2_up (a+b)).
apply log2_up_le_mono. rewrite <- (add_0_r a) at 1. apply add_le_mono; order.
assert (H' : log2_up b <= log2_up (a+b)).
apply log2_up_le_mono. rewrite <- (add_0_l b) at 1. apply add_le_mono; order.
le_elim H.
apply lt_le_trans with (log2_up (a+b) + log2_up b).
now apply add_lt_mono_r. now apply add_le_mono_l.
rewrite <- H at 1. apply add_lt_mono_l.
le_elim H'. trivial.
symmetry in H. apply log2_up_same in H; try order_pos.
symmetry in H'. apply log2_up_same in H'; try order_pos.
revert H H'. nzsimpl'. rewrite <- add_lt_mono_l, <- add_lt_mono_r; order.
Qed.
End NZLog2UpProp.
|
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// decerr_slave
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_decerr_slave #
(
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_RESP = 2'b11,
parameter integer C_IGNORE_ID = 0
)
(
input wire ACLK,
input wire ARESETN,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_AWID,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_BID,
output wire [1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [(C_AXI_ID_WIDTH-1):0] S_AXI_ARID,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] S_AXI_ARLEN,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [(C_AXI_ID_WIDTH-1):0] S_AXI_RID,
output wire [(C_AXI_DATA_WIDTH-1):0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
reg s_axi_awready_i;
reg s_axi_wready_i;
reg s_axi_bvalid_i;
reg s_axi_arready_i;
reg s_axi_rvalid_i;
localparam P_WRITE_IDLE = 2'b00;
localparam P_WRITE_DATA = 2'b01;
localparam P_WRITE_RESP = 2'b10;
localparam P_READ_IDLE = 2'b00;
localparam P_READ_START = 2'b01;
localparam P_READ_DATA = 2'b10;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
assign S_AXI_BRESP = C_RESP;
assign S_AXI_RRESP = C_RESP;
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_AWREADY = s_axi_awready_i;
assign S_AXI_WREADY = s_axi_wready_i;
assign S_AXI_BVALID = s_axi_bvalid_i;
assign S_AXI_ARREADY = s_axi_arready_i;
assign S_AXI_RVALID = s_axi_rvalid_i;
generate
if (C_AXI_PROTOCOL == P_AXILITE) begin : gen_axilite
reg s_axi_rvalid_en;
assign S_AXI_RLAST = 1'b1;
assign S_AXI_BID = 0;
assign S_AXI_RID = 0;
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
end else begin
if (s_axi_bvalid_i) begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
end
end else if (S_AXI_WVALID & s_axi_wready_i) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
end else if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b1;
end else begin
s_axi_awready_i <= 1'b1;
end
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rvalid_en <= 1'b0;
end else begin
if (s_axi_rvalid_i) begin
if (S_AXI_RREADY) begin
s_axi_rvalid_i <= 1'b0;
s_axi_arready_i <= 1'b1;
end
end else if (s_axi_rvalid_en) begin
s_axi_rvalid_en <= 1'b0;
s_axi_rvalid_i <= 1'b1;
end else if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
s_axi_rvalid_en <= 1'b1;
end else begin
s_axi_arready_i <= 1'b1;
end
end
end
end else begin : gen_axi
reg s_axi_rlast_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_bid_i;
reg [(C_AXI_ID_WIDTH-1):0] s_axi_rid_i;
reg [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] read_cnt;
reg [1:0] write_cs;
reg [1:0] read_cs;
assign S_AXI_RLAST = s_axi_rlast_i;
assign S_AXI_BID = C_IGNORE_ID ? 0 : s_axi_bid_i;
assign S_AXI_RID = C_IGNORE_ID ? 0 : s_axi_rid_i;
always @(posedge ACLK) begin
if (~ARESETN) begin
write_cs <= P_WRITE_IDLE;
s_axi_awready_i <= 1'b0;
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b0;
s_axi_bid_i <= 0;
end else begin
case (write_cs)
P_WRITE_IDLE:
begin
if (S_AXI_AWVALID & s_axi_awready_i) begin
s_axi_awready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_bid_i <= S_AXI_AWID;
s_axi_wready_i <= 1'b1;
write_cs <= P_WRITE_DATA;
end else begin
s_axi_awready_i <= 1'b1;
end
end
P_WRITE_DATA:
begin
if (S_AXI_WVALID & S_AXI_WLAST) begin
s_axi_wready_i <= 1'b0;
s_axi_bvalid_i <= 1'b1;
write_cs <= P_WRITE_RESP;
end
end
P_WRITE_RESP:
begin
if (S_AXI_BREADY) begin
s_axi_bvalid_i <= 1'b0;
s_axi_awready_i <= 1'b1;
write_cs <= P_WRITE_IDLE;
end
end
endcase
end
end
always @(posedge ACLK) begin
if (~ARESETN) begin
read_cs <= P_READ_IDLE;
s_axi_arready_i <= 1'b0;
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_rid_i <= 0;
read_cnt <= 0;
end else begin
case (read_cs)
P_READ_IDLE:
begin
if (S_AXI_ARVALID & s_axi_arready_i) begin
s_axi_arready_i <= 1'b0;
if (C_IGNORE_ID == 0) s_axi_rid_i <= S_AXI_ARID;
read_cnt <= S_AXI_ARLEN;
s_axi_rlast_i <= (S_AXI_ARLEN == 0);
read_cs <= P_READ_START;
end else begin
s_axi_arready_i <= 1'b1;
end
end
P_READ_START:
begin
s_axi_rvalid_i <= 1'b1;
read_cs <= P_READ_DATA;
end
P_READ_DATA:
begin
if (S_AXI_RREADY) begin
if (read_cnt == 0) begin
s_axi_rvalid_i <= 1'b0;
s_axi_rlast_i <= 1'b0;
s_axi_arready_i <= 1'b1;
read_cs <= P_READ_IDLE;
end else begin
if (read_cnt == 1) begin
s_axi_rlast_i <= 1'b1;
end
read_cnt <= read_cnt - 1;
end
end
end
endcase
end
end
end
endgenerate
endmodule
`default_nettype wire
|
(** * Extraction: Extracting ML from Coq *)
(** * Basic Extraction *)
(** In its simplest form, program extraction from Coq is completely straightforward. *)
(** First we say what language we want to extract into. Options are OCaml (the
most mature), Haskell (which mostly works), and Scheme (a bit out
of date). *)
Extraction Language Ocaml.
(** Now we load up the Coq environment with some definitions, either
directly or by importing them from other modules. *)
Require Import SfLib.
Require Import ImpCEvalFun.
(** Finally, we tell Coq the name of a definition to extract and the
name of a file to put the extracted code into. *)
Extraction "imp1.ml" ceval_step.
(** When Coq processes this command, it generates a file [imp1.ml]
containing an extracted version of [ceval_step], together with
everything that it recursively depends on. Have a look at this
file now. *)
(* ############################################################## *)
(** * Controlling Extraction of Specific Types *)
(** We can tell Coq to extract certain [Inductive] definitions to
specific OCaml types. For each one, we must say
- how the Coq type itself should be represented in OCaml, and
- how each constructor should be translated. *)
Extract Inductive bool => "bool" [ "true" "false" ].
(** Also, for non-enumeration types (where the constructors take
arguments), we give an OCaml expression that can be used as a
"recursor" over elements of the type. (Think Church numerals.) *)
Extract Inductive nat => "int"
[ "0" "(fun x -> x + 1)" ]
"(fun zero succ n ->
if n=0 then zero () else succ (n-1))".
(** We can also extract defined constants to specific OCaml terms or
operators. *)
Extract Constant plus => "( + )".
Extract Constant mult => "( * )".
Extract Constant beq_nat => "( = )".
(** Important: It is entirely _your responsibility_ to make sure that
the translations you're proving make sense. For example, it might
be tempting to include this one
Extract Constant minus => "( - )".
but doing so could lead to serious confusion! (Why?)
*)
Extraction "imp2.ml" ceval_step.
(** Have a look at the file [imp2.ml]. Notice how the fundamental
definitions have changed from [imp1.ml]. *)
(* ############################################################## *)
(** * A Complete Example *)
(** To use our extracted evaluator to run Imp programs, all we need to
add is a tiny driver program that calls the evaluator and somehow
prints out the result.
For simplicity, we'll print results by dumping out the first four
memory locations in the final state.
Also, to make it easier to type in examples, let's extract a
parser from the [ImpParser] Coq module. To do this, we need a few
more declarations to set up the right correspondence between Coq
strings and lists of OCaml characters. *)
Require Import Ascii String.
Extract Inductive ascii => char
[
"(* If this appears, you're using Ascii internals. Please don't *) (fun (b0,b1,b2,b3,b4,b5,b6,b7) -> let f b i = if b then 1 lsl i else 0 in Char.chr (f b0 0 + f b1 1 + f b2 2 + f b3 3 + f b4 4 + f b5 5 + f b6 6 + f b7 7))"
]
"(* If this appears, you're using Ascii internals. Please don't *) (fun f c -> let n = Char.code c in let h i = (n land (1 lsl i)) <> 0 in f (h 0) (h 1) (h 2) (h 3) (h 4) (h 5) (h 6) (h 7))".
Extract Constant zero => "'\000'".
Extract Constant one => "'\001'".
Extract Constant shift =>
"fun b c -> Char.chr (((Char.code c) lsl 1) land 255 + if b then 1 else 0)".
Extract Inlined Constant ascii_dec => "(=)".
(** We also need one more variant of booleans. *)
Extract Inductive sumbool => "bool" ["true" "false"].
(** The extraction is the same as always. *)
Require Import Imp.
Require Import ImpParser.
Extraction "imp.ml" empty_state ceval_step parse.
(** Now let's run our generated Imp evaluator. First, have a look at
[impdriver.ml]. (This was written by hand, not extracted.)
Next, compile the driver together with the extracted code and
execute it, as follows.
<<
ocamlc -w -20 -w -26 -o impdriver imp.mli imp.ml impdriver.ml
./impdriver
>>
(The [-w] flags to [ocamlc] are just there to suppress a few
spurious warnings.) *)
(* ############################################################## *)
(** * Discussion *)
(** Since we've proved that the [ceval_step] function behaves the same
as the [ceval] relation in an appropriate sense, the extracted
program can be viewed as a _certified_ Imp interpreter. (Of
course, the parser is not certified in any interesting sense,
since we didn't prove anything about it.) *)
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
module fake_nonburstboundary #
(
parameter WIDTH_D = 256,
parameter S_WIDTH_A = 26,
parameter M_WIDTH_A = S_WIDTH_A+$clog2(WIDTH_D/8),
parameter BURSTCOUNT_WIDTH = 6,
parameter BYTEENABLE_WIDTH = WIDTH_D,
parameter MAX_PENDING_READS = 64
)
(
input clk,
input resetn,
// Slave port
input [S_WIDTH_A-1:0] slave_address, // Word address
input [WIDTH_D-1:0] slave_writedata,
input slave_read,
input slave_write,
input [BURSTCOUNT_WIDTH-1:0] slave_burstcount,
input [BYTEENABLE_WIDTH-1:0] slave_byteenable,
output slave_waitrequest,
output [WIDTH_D-1:0] slave_readdata,
output slave_readdatavalid,
output [M_WIDTH_A-1:0] master_address, // Byte address
output [WIDTH_D-1:0] master_writedata,
output master_read,
output master_write,
output [BURSTCOUNT_WIDTH-1:0] master_burstcount,
output [BYTEENABLE_WIDTH-1:0] master_byteenable,
input master_waitrequest,
input [WIDTH_D-1:0] master_readdata,
input master_readdatavalid
);
assign master_read = slave_read;
assign master_write = slave_write;
assign master_writedata = slave_writedata;
assign master_burstcount = slave_burstcount;
assign master_address = {slave_address,{$clog2(WIDTH_D/8){1'b0}}}; //byteaddr
assign master_byteenable = slave_byteenable;
assign slave_waitrequest = master_waitrequest;
assign slave_readdatavalid = master_readdatavalid;
assign slave_readdata = master_readdata;
endmodule
|
/*****************************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/byte_group_io.v#4 $
// $Author: $
// $DateTime: $
// $Change: $
// Description:
// This verilog file is a paramertizable I/O termination for
// the single byte lane.
// to create a N byte-lane wide phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
//////////////////////////////////////////////////////////////////
*****************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_byte_group_io #(
// bit lane existance
parameter BITLANES = 12'b1111_1111_1111,
parameter BITLANES_OUTONLY = 12'b0000_0000_0000,
parameter PO_DATA_CTL = "FALSE",
parameter OSERDES_DATA_RATE = "DDR",
parameter OSERDES_DATA_WIDTH = 4,
parameter IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter IDELAYE2_IDELAY_VALUE = 00,
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter real TCK = 2500.0,
// local usage only, don't pass down
parameter BUS_WIDTH = 12,
parameter SYNTHESIS = "FALSE"
)
(
input [9:0] mem_dq_in,
output [BUS_WIDTH-1:0] mem_dq_out,
output [BUS_WIDTH-1:0] mem_dq_ts,
input mem_dqs_in,
output mem_dqs_out,
output mem_dqs_ts,
output [(4*10)-1:0] iserdes_dout, // 2 extra 12-bit lanes not used
output dqs_to_phaser,
input iserdes_clk,
input iserdes_clkb,
input iserdes_clkdiv,
input phy_clk,
input rst,
input oserdes_rst,
input iserdes_rst,
input [1:0] oserdes_dqs,
input [1:0] oserdes_dqsts,
input [(4*BUS_WIDTH)-1:0] oserdes_dq,
input [1:0] oserdes_dqts,
input oserdes_clk,
input oserdes_clk_delayed,
input oserdes_clkdiv,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input idelayctrl_refclk,
input [29:0] fine_delay ,
input fine_delay_sel
);
/// INSTANCES
localparam ISERDES_DQ_DATA_RATE = "DDR";
localparam ISERDES_DQ_DATA_WIDTH = 4;
localparam ISERDES_DQ_DYN_CLKDIV_INV_EN = "FALSE";
localparam ISERDES_DQ_DYN_CLK_INV_EN = "FALSE";
localparam ISERDES_DQ_INIT_Q1 = 1'b0;
localparam ISERDES_DQ_INIT_Q2 = 1'b0;
localparam ISERDES_DQ_INIT_Q3 = 1'b0;
localparam ISERDES_DQ_INIT_Q4 = 1'b0;
localparam ISERDES_DQ_INTERFACE_TYPE = "MEMORY_DDR3";
localparam ISERDES_NUM_CE = 2;
localparam ISERDES_DQ_IOBDELAY = "IFD";
localparam ISERDES_DQ_OFB_USED = "FALSE";
localparam ISERDES_DQ_SERDES_MODE = "MASTER";
localparam ISERDES_DQ_SRVAL_Q1 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q2 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q3 = 1'b0;
localparam ISERDES_DQ_SRVAL_Q4 = 1'b0;
localparam IDELAY_FINEDELAY_USE = (TCK > 1500) ? "FALSE" : "TRUE";
wire [BUS_WIDTH-1:0] data_in_dly;
wire [BUS_WIDTH-1:0] oserdes_dq_buf;
wire [BUS_WIDTH-1:0] oserdes_dqts_buf;
wire oserdes_dqs_buf;
wire oserdes_dqsts_buf;
wire [9:0] data_in;
wire tbyte_out;
reg [29:0] fine_delay_r;
assign mem_dq_out = oserdes_dq_buf;
assign mem_dq_ts = oserdes_dqts_buf;
assign data_in = mem_dq_in;
assign mem_dqs_out = oserdes_dqs_buf;
assign mem_dqs_ts = oserdes_dqsts_buf;
assign dqs_to_phaser = mem_dqs_in;
reg iserdes_clk_d;
always @(*)
iserdes_clk_d = iserdes_clk;
reg idelay_ld_rst;
reg rst_r1;
reg rst_r2;
reg rst_r3;
reg rst_r4;
always @(posedge phy_clk) begin
rst_r1 <= #1 rst;
rst_r2 <= #1 rst_r1;
rst_r3 <= #1 rst_r2;
rst_r4 <= #1 rst_r3;
end
always @(posedge phy_clk) begin
if (rst)
idelay_ld_rst <= #1 1'b1;
else if (rst_r4)
idelay_ld_rst <= #1 1'b0;
end
always @ (posedge phy_clk) begin
if(rst)
fine_delay_r <= #1 1'b0;
else if(fine_delay_sel)
fine_delay_r <= #1 fine_delay;
end
genvar i;
generate
for ( i = 0; i != 10 && PO_DATA_CTL == "TRUE" ; i=i+1) begin : input_
if ( BITLANES[i] && !BITLANES_OUTONLY[i]) begin : iserdes_dq_
ISERDESE2 #(
.DATA_RATE ( ISERDES_DQ_DATA_RATE),
.DATA_WIDTH ( ISERDES_DQ_DATA_WIDTH),
.DYN_CLKDIV_INV_EN ( ISERDES_DQ_DYN_CLKDIV_INV_EN),
.DYN_CLK_INV_EN ( ISERDES_DQ_DYN_CLK_INV_EN),
.INIT_Q1 ( ISERDES_DQ_INIT_Q1),
.INIT_Q2 ( ISERDES_DQ_INIT_Q2),
.INIT_Q3 ( ISERDES_DQ_INIT_Q3),
.INIT_Q4 ( ISERDES_DQ_INIT_Q4),
.INTERFACE_TYPE ( ISERDES_DQ_INTERFACE_TYPE),
.NUM_CE ( ISERDES_NUM_CE),
.IOBDELAY ( ISERDES_DQ_IOBDELAY),
.OFB_USED ( ISERDES_DQ_OFB_USED),
.SERDES_MODE ( ISERDES_DQ_SERDES_MODE),
.SRVAL_Q1 ( ISERDES_DQ_SRVAL_Q1),
.SRVAL_Q2 ( ISERDES_DQ_SRVAL_Q2),
.SRVAL_Q3 ( ISERDES_DQ_SRVAL_Q3),
.SRVAL_Q4 ( ISERDES_DQ_SRVAL_Q4)
)
iserdesdq
(
.O (),
.Q1 (iserdes_dout[4*i + 3]),
.Q2 (iserdes_dout[4*i + 2]),
.Q3 (iserdes_dout[4*i + 1]),
.Q4 (iserdes_dout[4*i + 0]),
.Q5 (),
.Q6 (),
.Q7 (),
.Q8 (),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.BITSLIP (1'b0),
.CE1 (1'b1),
.CE2 (1'b1),
.CLK (iserdes_clk_d),
.CLKB (!iserdes_clk_d),
.CLKDIVP (iserdes_clkdiv),
.CLKDIV (),
.DDLY (data_in_dly[i]),
.D (data_in[i]), // dedicated route to iob for debugging
// or as needed, select with IOBDELAY
.DYNCLKDIVSEL (1'b0),
.DYNCLKSEL (1'b0),
// NOTE: OCLK is not used in this design, but is required to meet
// a design rule check in map and bitgen. Do not disconnect it.
.OCLK (oserdes_clk),
.OCLKB (),
.OFB (),
.RST (1'b0),
// .RST (iserdes_rst),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0)
);
localparam IDELAYE2_CINVCTRL_SEL = "FALSE";
localparam IDELAYE2_DELAY_SRC = "IDATAIN";
localparam IDELAYE2_HIGH_PERFORMANCE_MODE = "TRUE";
localparam IDELAYE2_PIPE_SEL = "FALSE";
localparam IDELAYE2_ODELAY_TYPE = "FIXED";
localparam IDELAYE2_REFCLK_FREQUENCY = ((FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) && TCK <= 1500) ? 400.0 :
(FPGA_SPEED_GRADE == 1 && TCK <= 1500) ? 300.0 : 200.0;
localparam IDELAYE2_SIGNAL_PATTERN = "DATA";
localparam IDELAYE2_FINEDELAY_IN = "ADD_DLY";
if(IDELAY_FINEDELAY_USE == "TRUE") begin: idelay_finedelay_dq
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYE2_FINEDELAY #(
.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
.DELAY_SRC ( IDELAYE2_DELAY_SRC),
.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
.PIPE_SEL ( IDELAYE2_PIPE_SEL),
.FINEDELAY ( IDELAYE2_FINEDELAY_IN),
.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
)
idelaye2
(
.CNTVALUEOUT (),
.DATAOUT (data_in_dly[i]),
.C (phy_clk), // automatically wired by ISE
.CE (idelay_ce),
.CINVCTRL (),
.CNTVALUEIN (5'b00000),
.DATAIN (1'b0),
.IDATAIN (data_in[i]),
.IFDLY (fine_delay_r[i*3+:3]),
.INC (idelay_inc),
.LD (idelay_ld | idelay_ld_rst),
.LDPIPEEN (1'b0),
.REGRST (rst)
);
end else begin : idelay_dq
(* IODELAY_GROUP = IODELAY_GRP *)
IDELAYE2 #(
.CINVCTRL_SEL ( IDELAYE2_CINVCTRL_SEL),
.DELAY_SRC ( IDELAYE2_DELAY_SRC),
.HIGH_PERFORMANCE_MODE ( IDELAYE2_HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ( IDELAYE2_IDELAY_TYPE),
.IDELAY_VALUE ( IDELAYE2_IDELAY_VALUE),
.PIPE_SEL ( IDELAYE2_PIPE_SEL),
.REFCLK_FREQUENCY ( IDELAYE2_REFCLK_FREQUENCY ),
.SIGNAL_PATTERN ( IDELAYE2_SIGNAL_PATTERN)
)
idelaye2
(
.CNTVALUEOUT (),
.DATAOUT (data_in_dly[i]),
.C (phy_clk), // automatically wired by ISE
.CE (idelay_ce),
.CINVCTRL (),
.CNTVALUEIN (5'b00000),
.DATAIN (1'b0),
.IDATAIN (data_in[i]),
.INC (idelay_inc),
.LD (idelay_ld | idelay_ld_rst),
.LDPIPEEN (1'b0),
.REGRST (rst)
);
end
end // iserdes_dq
else begin
assign iserdes_dout[4*i + 3] = 0;
assign iserdes_dout[4*i + 2] = 0;
assign iserdes_dout[4*i + 1] = 0;
assign iserdes_dout[4*i + 0] = 0;
end
end // input_
endgenerate // iserdes_dq_
localparam OSERDES_DQ_DATA_RATE_OQ = OSERDES_DATA_RATE;
localparam OSERDES_DQ_DATA_RATE_TQ = OSERDES_DQ_DATA_RATE_OQ;
localparam OSERDES_DQ_DATA_WIDTH = OSERDES_DATA_WIDTH;
localparam OSERDES_DQ_INIT_OQ = 1'b1;
localparam OSERDES_DQ_INIT_TQ = 1'b1;
localparam OSERDES_DQ_INTERFACE_TYPE = "DEFAULT";
localparam OSERDES_DQ_ODELAY_USED = 0;
localparam OSERDES_DQ_SERDES_MODE = "MASTER";
localparam OSERDES_DQ_SRVAL_OQ = 1'b1;
localparam OSERDES_DQ_SRVAL_TQ = 1'b1;
// note: obuf used in control path case, no ts input so width irrelevant
localparam OSERDES_DQ_TRISTATE_WIDTH = (OSERDES_DQ_DATA_RATE_OQ == "DDR") ? 4 : 1;
localparam OSERDES_DQS_DATA_RATE_OQ = "DDR";
localparam OSERDES_DQS_DATA_RATE_TQ = "DDR";
localparam OSERDES_DQS_TRISTATE_WIDTH = 4; // this is always ddr
localparam OSERDES_DQS_DATA_WIDTH = 4;
localparam ODDR_CLK_EDGE = "SAME_EDGE";
localparam OSERDES_TBYTE_CTL = "TRUE";
generate
localparam NUM_BITLANES = PO_DATA_CTL == "TRUE" ? 10 : BUS_WIDTH;
if ( PO_DATA_CTL == "TRUE" ) begin : slave_ts
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL ("TRUE"),
.TBYTE_SRC ("TRUE")
)
oserdes_slave_ts
(
.OFB (),
.OQ (),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (),
.D2 (),
.D3 (),
.D4 (),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (oserdes_dqts[0]),
.T2 (oserdes_dqts[0]),
.T3 (oserdes_dqts[1]),
.T4 (oserdes_dqts[1]),
.TCE (1'b1),
.TBYTEOUT (tbyte_out),
.TBYTEIN (tbyte_out)
);
end // slave_ts
for (i = 0; i != NUM_BITLANES; i=i+1) begin : output_
if ( BITLANES[i]) begin : oserdes_dq_
if ( PO_DATA_CTL == "TRUE" ) begin : ddr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (OSERDES_DQ_INIT_OQ),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (OSERDES_DQ_SRVAL_OQ),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH),
.TBYTE_CTL (OSERDES_TBYTE_CTL),
.TBYTE_SRC ("FALSE")
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (),
.TFB (),
.TQ (oserdes_dqts_buf[i]),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (/*oserdes_dqts[0]*/),
.T2 (/*oserdes_dqts[0]*/),
.T3 (/*oserdes_dqts[1]*/),
.T4 (/*oserdes_dqts[1]*/),
.TCE (1'b1),
.TBYTEIN (tbyte_out)
);
end
else begin : sdr
OSERDESE2 #(
.DATA_RATE_OQ (OSERDES_DQ_DATA_RATE_OQ),
.DATA_RATE_TQ (OSERDES_DQ_DATA_RATE_TQ),
.DATA_WIDTH (OSERDES_DQ_DATA_WIDTH),
.INIT_OQ (1'b0 /*OSERDES_DQ_INIT_OQ*/),
.INIT_TQ (OSERDES_DQ_INIT_TQ),
.SERDES_MODE (OSERDES_DQ_SERDES_MODE),
.SRVAL_OQ (1'b0 /*OSERDES_DQ_SRVAL_OQ*/),
.SRVAL_TQ (OSERDES_DQ_SRVAL_TQ),
.TRISTATE_WIDTH (OSERDES_DQ_TRISTATE_WIDTH)
)
oserdes_dq_i
(
.OFB (),
.OQ (oserdes_dq_buf[i]),
.SHIFTOUT1 (), // not extended
.SHIFTOUT2 (), // not extended
.TBYTEOUT (),
.TFB (),
.TQ (),
.CLK (oserdes_clk),
.CLKDIV (oserdes_clkdiv),
.D1 (oserdes_dq[4 * i + 0]),
.D2 (oserdes_dq[4 * i + 1]),
.D3 (oserdes_dq[4 * i + 2]),
.D4 (oserdes_dq[4 * i + 3]),
.D5 (),
.D6 (),
.D7 (),
.D8 (),
.OCE (1'b1),
.RST (oserdes_rst),
.SHIFTIN1 (), // not extended
.SHIFTIN2 (), // not extended
.T1 (),
.T2 (),
.T3 (),
.T4 (),
.TCE (1'b1),
.TBYTEIN ()
);
end // ddr
end // oserdes_dq_
end // output_
endgenerate
generate
if ( PO_DATA_CTL == "TRUE" ) begin : dqs_gen
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqs
(
.Q (oserdes_dqs_buf),
.D1 (oserdes_dqs[0]),
.D2 (oserdes_dqs[1]),
.C (oserdes_clk_delayed),
.R (1'b0),
.S (),
.CE (1'b1)
);
ODDR
#(.DDR_CLK_EDGE (ODDR_CLK_EDGE))
oddr_dqsts
( .Q (oserdes_dqsts_buf),
.D1 (oserdes_dqsts[0]),
.D2 (oserdes_dqsts[0]),
.C (oserdes_clk_delayed),
.R (),
.S (1'b0),
.CE (1'b1)
);
end // sdr rate
else begin:null_dqs
end
endgenerate
endmodule // byte_group_io
|
`timescale 1 ns / 1 ps
module axis_red_pitaya_adc #
(
parameter integer ADC_DATA_WIDTH = 14,
parameter integer AXIS_TDATA_WIDTH = 32
)
(
// System signals
output wire adc_clk,
// ADC signals
output wire adc_csn,
input wire adc_clk_p,
input wire adc_clk_n,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_a,
input wire [ADC_DATA_WIDTH-1:0] adc_dat_b,
// Master side
output wire m_axis_tvalid,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata
);
localparam PADDING_WIDTH = AXIS_TDATA_WIDTH/2 - ADC_DATA_WIDTH;
reg [ADC_DATA_WIDTH-1:0] int_dat_a_reg;
reg [ADC_DATA_WIDTH-1:0] int_dat_b_reg;
wire int_clk;
IBUFGDS adc_clk_inst (.I(adc_clk_p), .IB(adc_clk_n), .O(int_clk));
always @(posedge int_clk)
begin
int_dat_a_reg <= adc_dat_a;
int_dat_b_reg <= adc_dat_b;
end
assign adc_clk = int_clk;
assign adc_csn = 1'b1;
assign m_axis_tvalid = 1'b1;
assign m_axis_tdata = {
{(PADDING_WIDTH+1){int_dat_b_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_b_reg[ADC_DATA_WIDTH-2:0],
{(PADDING_WIDTH+1){int_dat_a_reg[ADC_DATA_WIDTH-1]}}, ~int_dat_a_reg[ADC_DATA_WIDTH-2:0]};
endmodule
|
// $Id: whr_la_routing_logic.v 1922 2010-04-15 03:47:49Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// lookahead routing logic for wormhole router
module whr_la_routing_logic
(clk, reset, router_address, route_op, route_info, la_route_info);
`include "c_functions.v"
`include "c_constants.v"
// number of routers in each dimension
parameter num_routers_per_dim = 4;
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// number of dimensions in network
parameter num_dimensions = 2;
// width required to select individual router in network
localparam router_addr_width = num_dimensions * dim_addr_width;
// number of nodes per router (a.k.a. consentration factor)
parameter num_nodes_per_router = 1;
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width of global addresses
localparam addr_width = router_addr_width + node_addr_width;
// connectivity within each dimension
parameter connectivity = `CONNECTIVITY_LINE;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select an individual port
localparam port_idx_width = clogb(num_ports);
// width required for lookahead routing information
localparam la_route_info_width = port_idx_width;
// select routing function type
parameter routing_type = `ROUTING_TYPE_DOR;
// select order of dimension traversal
parameter dim_order = `DIM_ORDER_ASCENDING;
// total number of bits required for storing routing information
localparam route_info_width = addr_width;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// current router's address
input [0:router_addr_width-1] router_address;
// port on which the packet will leave the current router
input [0:num_ports-1] route_op;
// routing data
input [0:route_info_width-1] route_info;
// lookahead routing information for next router
output [0:la_route_info_width-1] la_route_info;
wire [0:la_route_info_width-1] la_route_info;
// address of destination router
wire [0:router_addr_width-1] dest_router_address;
assign dest_router_address = route_info[0:router_addr_width-1];
// address of the downstream router
wire [0:router_addr_width-1] next_router_address;
wire [0:num_dimensions-1] dim_addr_match;
wire [0:num_ports-1] next_route_op;
generate
case(routing_type)
`ROUTING_TYPE_DOR:
begin
genvar dim;
for(dim = 0; dim < num_dimensions; dim = dim + 1)
begin:dims
wire [0:dim_addr_width-1] dest_dim_addr;
assign dest_dim_addr
= dest_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] curr_dim_addr;
assign curr_dim_addr
= router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1];
wire [0:dim_addr_width-1] next_dim_addr;
assign dim_addr_match[dim] = (next_dim_addr == dest_dim_addr);
wire dim_sel;
case(dim_order)
`DIM_ORDER_ASCENDING:
begin
if(dim == 0)
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = &dim_addr_match[0:dim-1] &
~dim_addr_match[dim];
end
`DIM_ORDER_DESCENDING:
begin
if(dim == (num_dimensions - 1))
assign dim_sel = ~dim_addr_match[dim];
else
assign dim_sel = ~dim_addr_match[dim] &
dim_addr_match[(dim+1):
(num_dimensions-1)];
end
endcase
wire [0:num_neighbors_per_dim-1] port_dec;
assign next_router_address[dim*dim_addr_width:
(dim+1)*dim_addr_width-1]
= next_dim_addr;
case(connectivity)
`CONNECTIVITY_LINE, `CONNECTIVITY_RING:
begin
wire route_down;
assign route_down
= route_op[dim*num_neighbors_per_dim];
wire route_up;
assign route_up
= route_op[dim*num_neighbors_per_dim+1];
// Assemble a delta value for the address segment
// corresponding to the current dimension; the delta
// can have the values -1 (i.e., all ones in two's
// complement), 0 or 1
wire [0:dim_addr_width-1] addr_delta;
if(dim_addr_width > 1)
assign addr_delta[0:dim_addr_width-2]
= {(dim_addr_width-1){route_down}};
assign addr_delta[dim_addr_width-1]
= route_down | route_up;
assign next_dim_addr = curr_dim_addr + addr_delta;
case(connectivity)
`CONNECTIVITY_LINE:
begin
assign port_dec
= {dest_dim_addr < next_dim_addr,
dest_dim_addr > next_dim_addr};
end
`CONNECTIVITY_RING:
begin
// FIXME: add implementation here!
// synopsys translate_off
initial
begin
$display({"ERROR: The lookahead routing ",
"logic module %m does not yet ",
"support ring connectivity ",
"within each dimension."});
$stop;
end
// synopsys translate_on
end
endcase
end
`CONNECTIVITY_FULL:
begin
wire route_dest;
assign route_dest
= |route_op[dim*num_neighbors_per_dim:
(dim+1)*num_neighbors_per_dim-1];
assign next_dim_addr
= route_dest ? dest_dim_addr : curr_dim_addr;
wire [0:num_routers_per_dim-1] dest_dim_addr_dec;
c_decoder
#(.num_ports(num_routers_per_dim))
dest_dim_addr_dec_dec
(.data_in(dest_dim_addr),
.data_out(dest_dim_addr_dec));
wire [0:(2*num_routers_per_dim-1)-1]
dest_dim_addr_dec_repl;
assign dest_dim_addr_dec_repl
= {dest_dim_addr_dec,
dest_dim_addr_dec[0:(num_routers_per_dim-1)-1]};
assign port_dec
= dest_dim_addr_dec_repl[(next_dim_addr+1) +:
num_neighbors_per_dim];
end
endcase
assign next_route_op[dim*num_neighbors_per_dim:
(dim+1)*num_neighbors_per_dim-1]
= port_dec & {num_neighbors_per_dim{dim_sel}};
end
end
endcase
wire eject;
assign eject = &dim_addr_match;
if(num_nodes_per_router > 1)
begin
wire [0:node_addr_width-1] dest_node_address;
assign dest_node_address
= route_info[route_info_width-node_addr_width:route_info_width-1];
wire [0:num_nodes_per_router-1] node_sel;
c_decoder
#(.num_ports(num_nodes_per_router))
node_sel_dec
(.data_in(dest_node_address),
.data_out(node_sel));
assign next_route_op[num_ports-num_nodes_per_router:num_ports-1]
= node_sel & {num_nodes_per_router{eject}};
end
else
assign next_route_op[num_ports-1] = eject;
endgenerate
wire [0:port_idx_width-1] next_route_port;
c_encoder
#(.num_ports(num_ports))
next_route_port_enc
(.data_in(next_route_op),
.data_out(next_route_port));
assign la_route_info[0:port_idx_width-1] = next_route_port;
endmodule
|
//////////////////////////////////////////////////////////
// Copyright (c) 2006 Rice University //
// All Rights Reserved //
// This code is covered by the Rice-WARP license //
// See http://warp.rice.edu/license/ for details //
//////////////////////////////////////////////////////////
module radio_bridge
(
converter_clock_in,
converter_clock_out,
user_RSSI_ADC_clk,
radio_RSSI_ADC_clk,
user_RSSI_ADC_D,
user_EEPROM_IO_T,
user_EEPROM_IO_O,
user_EEPROM_IO_I,
user_TxModelStart,
radio_EEPROM_IO,
radio_DAC_I,
radio_DAC_Q,
radio_ADC_I,
radio_ADC_Q,
user_DAC_I,
user_DAC_Q,
user_ADC_I,
user_ADC_Q,
radio_B,
user_Tx_gain,
user_RxBB_gain,
user_RxRF_gain,
user_SHDN_external,
user_RxEn_external,
user_TxEn_external,
user_RxHP_external,
controller_logic_clk,
controller_spi_clk,
controller_spi_data,
controller_radio_cs,
controller_dac_cs,
controller_SHDN,
controller_TxEn,
controller_RxEn,
controller_RxHP,
controller_24PA,
controller_5PA,
controller_ANTSW,
controller_LED,
controller_RX_ADC_DCS,
controller_RX_ADC_DFS,
controller_RX_ADC_PWDNA,
controller_RX_ADC_PWDNB,
controller_DIPSW,
controller_RSSI_ADC_CLAMP,
controller_RSSI_ADC_HIZ,
controller_RSSI_ADC_SLEEP,
controller_RSSI_ADC_D,
controller_TxStart,
controller_LD,
controller_RX_ADC_OTRA,
controller_RX_ADC_OTRB,
controller_RSSI_ADC_OTR,
controller_DAC_PLL_LOCK,
controller_DAC_RESET,
controller_SHDN_external,
controller_RxEn_external,
controller_TxEn_external,
controller_RxHP_external,
dac_spi_data,
dac_spi_cs,
dac_spi_clk,
radio_spi_clk,
radio_spi_data,
radio_spi_cs,
radio_SHDN,
radio_TxEn,
radio_RxEn,
radio_RxHP,
radio_24PA,
radio_5PA,
radio_ANTSW,
radio_LED,
radio_RX_ADC_DCS,
radio_RX_ADC_DFS,
radio_RX_ADC_PWDNA,
radio_RX_ADC_PWDNB,
radio_DIPSW,
radio_RSSI_ADC_CLAMP,
radio_RSSI_ADC_HIZ,
radio_RSSI_ADC_SLEEP,
radio_RSSI_ADC_D,
radio_LD,
radio_RX_ADC_OTRA,
radio_RX_ADC_OTRB,
radio_RSSI_ADC_OTR,
radio_DAC_PLL_LOCK,
radio_DAC_RESET
);
//Parameter to choose which set of rate change filters to use
// Default is 4 (40MHz converter clock, 10MHz actual bandwidth)
// Value of 1 bypasses filters altogether; this is the original radio_bridge mode
// May add support for rate change = 2 in the future (requires new filter core)
// 16-bit datatype to play nice with BSB parameterization
//parameter rate_change = 16'h0004;
parameter C_FAMILY = "virtex2p";
/**********************/
/* Clock & Data Ports */
/**********************/
input converter_clock_in;
output converter_clock_out;
input user_RSSI_ADC_clk;
output radio_RSSI_ADC_clk;
output [0:9] user_RSSI_ADC_D;
input user_EEPROM_IO_T;
input user_EEPROM_IO_O;
output user_EEPROM_IO_I;
output user_TxModelStart;
output [0:15] radio_DAC_I;
output [0:15] radio_DAC_Q;
input [0:13] radio_ADC_I;
input [0:13] radio_ADC_Q;
input [0:15] user_DAC_I;
input [0:15] user_DAC_Q;
output [0:13] user_ADC_I;
output [0:13] user_ADC_Q;
input [0:1] user_RxRF_gain;
input [0:4] user_RxBB_gain;
input [0:5] user_Tx_gain;
/* radio_B is a 7-bit bus */
/* In Rx mode, radio_B[0:1] = RF gain, radio_B[2:6] = baseband gain */
/* In Tx mode, radio_B[1:6] = gain, radio_B[0] is unused */
output [0:6] radio_B;
input user_SHDN_external;
input user_RxEn_external;
input user_TxEn_external;
input user_RxHP_external;
/*******************************************/
/* Radio Controller <-> Radio Bridge Ports */
/*******************************************/
input controller_logic_clk;
input controller_spi_clk;
input controller_spi_data;
input controller_radio_cs;
input controller_dac_cs;
input controller_SHDN;
input controller_TxEn;
input controller_RxEn;
input controller_RxHP;
input controller_24PA;
input controller_5PA;
input [0:1] controller_ANTSW;
input [0:2] controller_LED;
input controller_RX_ADC_DCS;
input controller_RX_ADC_DFS;
input controller_RX_ADC_PWDNA;
input controller_RX_ADC_PWDNB;
input controller_RSSI_ADC_CLAMP;
input controller_RSSI_ADC_HIZ;
input controller_RSSI_ADC_SLEEP;
input controller_DAC_RESET;
input controller_TxStart;
output [0:3] controller_DIPSW;
output [0:9] controller_RSSI_ADC_D;
output controller_LD;
output controller_RX_ADC_OTRA;
output controller_RX_ADC_OTRB;
output controller_RSSI_ADC_OTR;
output controller_DAC_PLL_LOCK;
output controller_SHDN_external;
output controller_RxEn_external;
output controller_TxEn_external;
output controller_RxHP_external;
/**************************************/
/* Radio Bridge <-> Radio Board Ports */
/**************************************/
output dac_spi_data;
output dac_spi_cs;
output dac_spi_clk;
output radio_spi_clk;
output radio_spi_data;
output radio_spi_cs;
output radio_SHDN;
output radio_TxEn;
output radio_RxEn;
output radio_RxHP;
output radio_24PA;
output radio_5PA;
output [0:1] radio_ANTSW;
output [0:2] radio_LED;
output radio_RX_ADC_DCS;
output radio_RX_ADC_DFS;
output radio_RX_ADC_PWDNA;
output radio_RX_ADC_PWDNB;
output radio_RSSI_ADC_CLAMP;
output radio_RSSI_ADC_HIZ;
output radio_RSSI_ADC_SLEEP;
output radio_DAC_RESET;
input [0:9] radio_RSSI_ADC_D;
input radio_LD;
input radio_RX_ADC_OTRA;
input radio_RX_ADC_OTRB;
input radio_RSSI_ADC_OTR;
input radio_DAC_PLL_LOCK;
input [0:3] radio_DIPSW;
inout radio_EEPROM_IO;
//All the outputs will be registered using IOB registers
reg radio_RSSI_ADC_clk;
reg [0:9] user_RSSI_ADC_D;
reg [0:15] radio_DAC_I;
reg [0:15] radio_DAC_Q;
reg [0:13] user_ADC_I;
reg [0:13] user_ADC_Q;
reg [0:13] radio_ADC_I_nReg;
reg [0:13] radio_ADC_Q_nReg;
reg [0:6] radio_B;
reg [0:3] controller_DIPSW;
reg [0:9] controller_RSSI_ADC_D;
reg controller_LD;
reg controller_RX_ADC_OTRA;
reg controller_RX_ADC_OTRB;
reg controller_RSSI_ADC_OTR;
reg controller_DAC_PLL_LOCK;
reg dac_spi_data;
reg dac_spi_cs;
reg dac_spi_clk;
reg radio_spi_clk;
reg radio_spi_data;
reg radio_spi_cs;
reg radio_SHDN;
reg radio_TxEn;
reg radio_RxEn;
reg radio_RxHP;
reg radio_24PA;
reg radio_5PA;
reg [0:1] radio_ANTSW;
reg [0:2] radio_LED;
reg radio_RX_ADC_DCS;
reg radio_RX_ADC_DFS;
reg radio_RX_ADC_PWDNA;
reg radio_RX_ADC_PWDNB;
reg radio_RSSI_ADC_CLAMP;
reg radio_RSSI_ADC_HIZ;
reg radio_RSSI_ADC_SLEEP;
reg radio_DAC_RESET;
//Drive the clock out to the ADC/DACs
//synthesis attribute IOB of converter_clock_out IS true;
OFDDRRSE OFDDRRSE_inst (
.Q(converter_clock_out), // Data output (connect directly to top-level port)
.C0(converter_clock_in), // 0 degree clock input
.C1(~converter_clock_in), // 180 degree clock input
.CE(1'b1), // Clock enable input
.D0(1'b1), // Posedge data input
.D1(1'b0), // Negedge data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous preset input
);
//Pass the Tx start signal through to the user port
// This is an internal signal, so it won't be registered here
assign user_TxModelStart = controller_TxStart;
// Pass user_external signals to the controller
assign controller_SHDN_external = user_SHDN_external;
assign controller_RxEn_external = user_RxEn_external;
assign controller_TxEn_external = user_TxEn_external;
assign controller_RxHP_external = user_RxHP_external;
//Make the gain mux default to the Tx settings, unless Rx is active
//The Tx gain needs to be zero when TxEn is raised
//The radio controller outputs zero for TxGain by default
wire [0:6] radio_B_preReg;
assign radio_B_preReg = radio_RxEn ? {user_RxRF_gain, user_RxBB_gain} : {1'b0, user_Tx_gain};
/********************************************/
/* Instantiate the IOBUF for EEPROM Devices */
/********************************************/
IOBUF xIOBUF(
.T(user_EEPROM_IO_T),
.I(user_EEPROM_IO_O),
.O(user_EEPROM_IO_I),
.IO(radio_EEPROM_IO)
);
//Capture the incoming ADC signals on the negative
// edge of the converter clock
//synthesis attribute IOB of radio_ADC_I_nReg IS true;
//synthesis attribute IOB of radio_ADC_Q_nReg IS true;
always @( negedge converter_clock_in )
begin
radio_ADC_I_nReg <= radio_ADC_I;
radio_ADC_Q_nReg <= radio_ADC_Q;
end
always @( posedge converter_clock_in )
begin
/*******************************************/
/* PHY Cores <-> Radio Board */
/*******************************************/
radio_B <= radio_B_preReg;
radio_RSSI_ADC_clk <= user_RSSI_ADC_clk;
user_ADC_I <= radio_ADC_I_nReg;
user_ADC_Q <= radio_ADC_Q_nReg;
radio_DAC_I <= user_DAC_I;
radio_DAC_Q <= user_DAC_Q;
end
//Use the clock provied by the radio_controller to register its I/O
// This will be a copy of the PLB clock for the controller's bus
// It may be different than the converter clock (probably faster, but usually still synchronous)
always @( posedge controller_logic_clk )
begin
/*******************************************/
/* Radio Controller -> Radio Board Drivers */
/*******************************************/
dac_spi_clk <= controller_spi_clk;
dac_spi_data <= controller_spi_data;
dac_spi_cs <= controller_dac_cs;
radio_spi_clk <= controller_spi_clk;
radio_spi_data <= controller_spi_data;
radio_spi_cs <= controller_radio_cs;
radio_SHDN <= controller_SHDN;
radio_TxEn <= controller_TxEn;
radio_RxEn <= controller_RxEn;
radio_RxHP <= controller_RxHP;
radio_24PA <= controller_24PA;
radio_5PA <= controller_5PA;
radio_ANTSW <= controller_ANTSW;
radio_LED <= controller_LED;
radio_RX_ADC_DCS <= controller_RX_ADC_DCS;
radio_RX_ADC_DFS <= controller_RX_ADC_DFS;
radio_RX_ADC_PWDNA <= controller_RX_ADC_PWDNA;
radio_RX_ADC_PWDNB <= controller_RX_ADC_PWDNB;
radio_RSSI_ADC_CLAMP <= controller_RSSI_ADC_CLAMP;
radio_RSSI_ADC_HIZ <= controller_RSSI_ADC_HIZ;
radio_RSSI_ADC_SLEEP <= controller_RSSI_ADC_SLEEP;
/*******************************************/
/* Radio Board -> Radio Controller Drivers */
/*******************************************/
controller_DIPSW <= radio_DIPSW;
controller_LD <= radio_LD;
controller_RX_ADC_OTRA <= radio_RX_ADC_OTRA;
controller_RX_ADC_OTRB <= radio_RX_ADC_OTRB;
controller_RSSI_ADC_OTR <= radio_RSSI_ADC_OTR;
controller_DAC_PLL_LOCK <= radio_DAC_PLL_LOCK;
radio_DAC_RESET <= controller_DAC_RESET;
end
//Delay the user's RSSI clk input by 1 cycle
reg user_RSSI_ADC_clk_d1;
always @( posedge controller_logic_clk )
begin
user_RSSI_ADC_clk_d1 <= user_RSSI_ADC_clk;
end
//Only update the RSSI input regisers on the rising edge
// of the user-supplied RSSI clk; we'll assume the RSSI clk is
// synchronous with the bus clock for the radio controller's PLB
always @( posedge controller_logic_clk )
begin
if(user_RSSI_ADC_clk & ~user_RSSI_ADC_clk_d1)
begin
controller_RSSI_ADC_D <= radio_RSSI_ADC_D;
user_RSSI_ADC_D <= radio_RSSI_ADC_D;
end
end
//Use XST attributes to force the registers for these signals into the IOBs
//synthesis attribute IOB of radio_RSSI_ADC_clk IS true;
//synthesis attribute IOB of user_RSSI_ADC_D IS true;
//synthesis attribute IOB of radio_DAC_I IS true;
//synthesis attribute IOB of radio_DAC_Q IS true;
//synthesis attribute IOB of radio_B IS true;
//synthesis attribute IOB of controller_DIPSW IS true;
//synthesis attribute IOB of controller_RSSI_ADC_D IS true;
//synthesis attribute IOB of controller_LD IS true;
//synthesis attribute IOB of controller_RX_ADC_OTRA IS true;
//synthesis attribute IOB of controller_RX_ADC_OTRB IS true;
//synthesis attribute IOB of controller_RSSI_ADC_OTR IS true;
//synthesis attribute IOB of controller_DAC_PLL_LOCK IS true;
//synthesis attribute IOB of dac_spi_data IS true;
//synthesis attribute IOB of dac_spi_cs IS true;
//synthesis attribute IOB of dac_spi_clk IS true;
//synthesis attribute IOB of radio_spi_clk IS true;
//synthesis attribute IOB of radio_spi_data IS true;
//synthesis attribute IOB of radio_spi_cs IS true;
//synthesis attribute IOB of radio_SHDN IS true;
//synthesis attribute IOB of radio_TxEn IS true;
//synthesis attribute IOB of radio_RxEn IS true;
//synthesis attribute IOB of radio_RxHP IS true;
//synthesis attribute IOB of radio_24PA IS true;
//synthesis attribute IOB of radio_5PA IS true;
//synthesis attribute IOB of radio_ANTSW IS true;
//synthesis attribute IOB of radio_LED IS true;
//synthesis attribute IOB of radio_RX_ADC_DCS IS true;
//synthesis attribute IOB of radio_RX_ADC_DFS IS true;
//synthesis attribute IOB of radio_RX_ADC_PWDNA IS true;
//synthesis attribute IOB of radio_RX_ADC_PWDNB IS true;
//synthesis attribute IOB of radio_RSSI_ADC_CLAMP IS true;
//synthesis attribute IOB of radio_RSSI_ADC_HIZ IS true;
//synthesis attribute IOB of radio_RSSI_ADC_SLEEP IS true;
//synthesis attribute IOB of radio_DAC_RESET IS true;
endmodule
//Empty module declaration for filter NGC netlist
// See mdlsrc folder for source System Generator model
module radio_bridge_ratechangefilter_4x_2ch_cw (
clk,
ce,
decfiltbypass,
interpfiltbypass,
interp_en,
rx_i,
rx_i_fullrate,
rx_q,
rx_q_fullrate,
tx_i,
tx_i_fullrate,
tx_q,
tx_q_fullrate
);
input clk;
input ce;
input decfiltbypass;
input interpfiltbypass;
input interp_en;
input [13:0] rx_i_fullrate;
input [13:0] rx_q_fullrate;
input [15:0] tx_i;
input [15:0] tx_q;
output [13:0] rx_i;
output [13:0] rx_q;
output [15:0] tx_i_fullrate;
output [15:0] tx_q_fullrate;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O221AI_BEHAVIORAL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
// Local signals
wire B2 or0_out ;
wire B2 or1_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
nand nand0 (nand0_out_Y , or1_out, or0_out, C1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_BEHAVIORAL_V |
/****************************************************************************************
*
* File Name: ddr2.v
* Version: 5.20
* Model: BUS Functional
*
* Dependencies: ddr2_parameters.vh
*
* Description: Micron SDRAM DDR2 (Double Data Rate 2)
*
* Limitation: - doesn't check for average refresh timings
* - positive ck and ck_n edges are used to form internal clock
* - positive dqs and dqs_n edges are used to latch data
* - test mode is not modeled
*
* Note: - Set simulator resolution to "ps" accuracy
* - Set Debug = 0 to disable $display messages
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
* Rev Author Date Changes
* ---------------------------------------------------------------------------------------
* 1.00 JMK 07/29/03 Initial Release
* 1.10 JMK 08/09/03 Timing Parameter updates to tIS, tIH, tDS, tDH
* 2.20 JMK 08/07/03 General cleanup
* 2.30 JMK 11/26/03 Added CL_MIN, CL_MAX, wl_min and wl_max parameters.
* Added AL_MIN and AL_MAX parameters.
* Removed support for OCD.
* 2.40 JMK 01/15/04 Removed verilog 2001 constructs.
* 2.50 JMK 01/29/04 Removed tRP checks during Precharge command.
* 2.60 JMK 04/20/04 Fixed tWTR check.
* 2.70 JMK 04/30/04 Added tRFC maximum check.
* Combined Self Refresh and Power Down always blocks.
* Added Reset Function (CKE LOW Anytime).
* 2.80 JMK 08/19/04 Precharge is treated as NOP when bank is not active.
* Added checks for tRAS, tWR, tRTP to any bank during Pre-All.
* tRFC maximum violation will only display one time.
* 2.90 JMK 11/05/04 Fixed DQS checking during write.
* Fixed false tRFC max assertion during power up and self ref.
* Added warning for 200us CKE low time during initialization.
* Added -3, -3E, and -37V speed grades to ddr2_parameters.v
* 3.00 JMK 04/22/05 Removed ODT off requirement during power down.
* Added tAOND, tAOFD, tANPD, tAXPD, tAONPD, and tAOFPD parameters.
* Added ODT status messages.
* Updated the initialization sequence.
* Disable ODT and CLK pins during self refresh.
* Disable cmd and addr pins during power down and self refresh.
* 3.10 JMK 06/07/05 Disable trpa checking if the part does not have 8 banks.
* Changed tAXPD message from error to a warning.
* Added tDSS checking.
* Removed tDQSL checking during tWPRE and tWPST.
* Fixed a burst order error during writes.
* Renamed parameters file with .vh extension.
* 3.20 JMK 07/18/05 Removed 14 tCK requirement from LMR to READ.
* 3.30 JMK 08/03/05 Added check for interrupting a burst with auto precharge.
* 4.00 JMK 11/21/05 Parameter names all UPPERCASE, signal names all lowercase.
* Clock jitter can be tolerated within specification range.
* Clock frequency is sampled from the CK pin.
* Scaleable up to 64 DQ and 16 DQS bits.
* Read data can be randomly skewed using RANDOM_OUT_DELAY.
* Parameterized read and write DQS, and read DQ.
* Initialization can be bypassed using initialize task.
* 4.10 JMK 11/30/05 Fixed compile errors when `MAX_MEM was defined.
* 4.20 JMK 12/09/05 Fixed memory addressing error when `MAX_MEM was defined.
* 4.30 JMK 02/15/06 Added dummy write to initialization sequence.
* Removed tWPST maximum checking.
* Rising dqs_n edge latches data when enabled in EMR.
* Fixed a sign error in the tJIT(cc) calculation.
* 4.40 JMK 02/16/06 Fixed dummy write when`MAX_MEM was defined.
* 4.50 JMK 02/27/06 Fixed extra tDQSS assertions.
* Fixed tRCD and tWTR checking.
* Errors entering Power Down or Self Refresh will cause reset.
* Ignore dqs_n when disabled in EMR.
* 5.00 JMK 04/24/06 Test stimulus now included from external file (subtest.vh)
* Fixed tRFC max assertion during self refresh.
* Fixed tANPD checking during Power Down.
* Removed dummy write from initialization sequence.
* 5.01 JMK 04/28/06 Fixed Auto Precharge to Load Mode, Refresh and Self Refresh.
* Removed Auto Precharge error message during Power Down Enter.
* 5.10 JMK 07/26/06 Created internal clock using ck and ck_n.
* RDQS can only be enabled in EMR for x8 configurations.
* CAS latency is checked vs frequency when DLL locks.
* tMOD changed from tCK units to ns units.
* Added 50 Ohm setting for Rtt in EMR.
* Improved checking of DQS during writes.
* 5.20 JMK 10/02/06 Fixed DQS checking for interrupting write to write and x16.
****************************************************************************************/
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
module ddr2 (
ck,
ck_n,
cke,
cs_n,
ras_n,
cas_n,
we_n,
dm_rdqs,
ba,
addr,
dq,
dqs,
dqs_n,
rdqs_n,
odt
);
// `include "ddr2_parameters.vh"
/****************************************************************************************
*
* Disclaimer This software code and all associated documentation, comments or other
* of Warranty: information (collectively "Software") is provided "AS IS" without
* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGES. Because some jurisdictions prohibit the exclusion or
* limitation of liability for consequential or incidental damages, the
* above limitation may not apply to you.
*
* Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
// Timing parameters based on Speed Grade
// SYMBOL UNITS DESCRIPTION
// ------ ----- -----------
`ifdef sg25E
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
parameter TQHS = 300; // tQHS ps Data hold skew factor
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12000; // tRCD ps Active to Read/Write command time
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TRP = 12500; // tRP ps Precharge command period
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `ifdef sg25
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_DUTY = 100; // tJIT(duty) ps Half Period Jitter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 150; // tERR(nper) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 175; // tERR(nper) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 200; // tERR(nper) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 200; // tERR(nper) ps Accumulated Error (5-cycle)
parameter TERR_N1PER = 300; // tERR(nper) ps Accumulated Error (6-10-cycle)
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
parameter TQHS = 300; // tQHS ps Data hold skew factor
parameter TAC = 400; // tAC ps DQ output access time from CK/CK#
parameter TDS = 50; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 125; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSCK = 350; // tDQSCK ps DQS output access time from CK/CK#
parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TWTR = 10000; // tWTR ps Write to Read command delay
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXARDS = 8; // tXARDS tCK Exit low power active power down to a read command
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg3E
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
parameter TQHS = 340; // tQHS ps Data hold skew factor
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRC = 54000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 12000; // tRCD ps Active to Read/Write command time
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TRP = 12000; // tRP ps Precharge command period
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
parameter CL_TIME = 12000; // CL ps Minimum CAS Latency
`else `ifdef sg3
parameter TCK_MIN = 3000; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
parameter TQHS = 340; // tQHS ps Data hold skew factor
parameter TAC = 450; // tAC ps DQ output access time from CK/CK#
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 175; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK#
parameter TDQSQ = 240; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TWPRE = 0.35; // tWPRE tCK DQS Write Preamble
parameter TIS = 200; // tIS ps Input Setup Time
parameter TIH = 275; // tIH ps Input Hold Time
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXARDS = 7; // tXARDS tCK Exit low power active power down to a read command
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `ifdef sg37E
parameter TCK_MIN = 3750; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
parameter TJIT_DUTY = 125; // tJIT(duty) ps Half Period Jitter
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
parameter TQHS = 400; // tQHS ps Data hold skew factor
parameter TAC = 500; // tAC ps DQ output access time from CK/CK#
parameter TDS = 100; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 225; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSCK = 450; // tDQSCK ps DQS output access time from CK/CK#
parameter TDQSQ = 300; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TWPRE = 0.25; // tWPRE tCK DQS Write Preamble
parameter TIS = 250; // tIS ps Input Setup Time
parameter TIH = 375; // tIH ps Input Hold Time
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TWTR = 7500; // tWTR ps Write to Read command delay
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`else `define sg5E
parameter TCK_MIN = 5000; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 125; // tJIT(per) ps Period JItter
parameter TJIT_DUTY = 150; // tJIT(duty) ps Half Period Jitter
parameter TJIT_CC = 250; // tJIT(cc) ps Cycle to Cycle jitter
parameter TERR_2PER = 175; // tERR(nper) ps Accumulated Error (2-cycle)
parameter TERR_3PER = 225; // tERR(nper) ps Accumulated Error (3-cycle)
parameter TERR_4PER = 250; // tERR(nper) ps Accumulated Error (4-cycle)
parameter TERR_5PER = 250; // tERR(nper) ps Accumulated Error (5-cycle)
parameter TERR_N1PER = 350; // tERR(nper) ps Accumulated Error (6-10-cycle)
parameter TERR_N2PER = 450; // tERR(nper) ps Accumulated Error (11-50-cycle)
parameter TQHS = 450; // tQHS ps Data hold skew factor
parameter TAC = 600; // tAC ps DQ output access time from CK/CK#
parameter TDS = 150; // tDS ps DQ and DM input setup time relative to DQS
parameter TDH = 275; // tDH ps DQ and DM input hold time relative to DQS
parameter TDQSCK = 500; // tDQSCK ps DQS output access time from CK/CK#
parameter TDQSQ = 350; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
parameter TWPRE = 0.25; // tWPRE tCK DQS Write Preamble
parameter TIS = 350; // tIS ps Input Setup Time
parameter TIH = 475; // tIH ps Input Hold Time
parameter TRC = 55000; // tRC ps Active to Active/Auto Refresh command time
parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
parameter TWTR = 10000; // tWTR ps Write to Read command delay
parameter TRP = 15000; // tRP ps Precharge command period
parameter TXARDS = 6; // tXARDS tCK Exit low power active power down to a read command
parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
`endif `endif `endif `endif `endif
// Timing Parameters
// Mode Register
parameter AL_MIN = 0; // AL tCK Minimum Additive Latency
parameter AL_MAX = 5; // AL tCK Maximum Additive Latency
parameter CL_MIN = 3; // CL tCK Minimum CAS Latency
parameter CL_MAX = 6; // CL tCK Maximum CAS Latency
parameter WR_MIN = 2; // WR tCK Minimum Write Recovery
parameter WR_MAX = 6; // WR tCK Maximum Write Recovery
parameter BL_MIN = 4; // BL tCK Minimum Burst Length
parameter BL_MAX = 8; // BL tCK Minimum Burst Length
// Clock
parameter TCK_MAX = 8000; // tCK ps Maximum Clock Cycle Time
parameter TCH_MIN = 0.48; // tCH tCK Minimum Clock High-Level Pulse Width
parameter TCH_MAX = 0.52; // tCH tCK Maximum Clock High-Level Pulse Width
parameter TCL_MIN = 0.48; // tCL tCK Minimum Clock Low-Level Pulse Width
parameter TCL_MAX = 0.52; // tCL tCK Maximum Clock Low-Level Pulse Width
// Data
parameter TLZ = TAC; // tLZ ps Data-out low-impedance window from CK/CK#
parameter THZ = TAC; // tHZ ps Data-out high impedance window from CK/CK#
parameter TDIPW = 0.35; // tDIPW tCK DQ and DM input Pulse Width
// Data Strobe
parameter TDQSH = 0.35; // tDQSH tCK DQS input High Pulse Width
parameter TDQSL = 0.35; // tDQSL tCK DQS input Low Pulse Width
parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
parameter TWPST = 0.40; // tWPST tCK DQS Write Postamble
parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
// Command and Address
parameter TIPW = 0.6; // tIPW tCK Control and Address input Pulse Width
parameter TCCD = 2; // tCCD tCK Cas to Cas command delay
parameter TRAS_MIN = 40000; // tRAS ps Minimum Active to Precharge command time
parameter TRAS_MAX =70000000; // tRAS ps Maximum Active to Precharge command time
parameter TRTP = 7500; // tRTP ps Read to Precharge command delay
parameter TWR = 15000; // tWR ps Write recovery time
parameter TMRD = 2; // tMRD tCK Load Mode Register command cycle time
parameter TDLLK = 200; // tDLLK tCK DLL locking time
// Refresh
parameter TRFC_MIN = 75000; // tRFC ps Refresh to Refresh Command interval minimum value
parameter TRFC_MAX =70000000; // tRFC ps Refresh to Refresh Command Interval maximum value
// Self Refresh
parameter TXSNR = TRFC_MIN + 10000; // tXSNR ps Exit self refesh to a non-read command
parameter TXSRD = 200; // tXSRD tCK Exit self refresh to a read command
parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit.
// ODT
parameter TAOND = 2; // tAOND tCK ODT turn-on delay
parameter TAOFD = 2.5; // tAOFD tCK ODT turn-off delay
parameter TAONPD = 2000; // tAONPD ps ODT turn-on (precharge power-down mode)
parameter TAOFPD = 2000; // tAOFPD ps ODT turn-off (precharge power-down mode)
parameter TANPD = 3; // tANPD tCK ODT to power-down entry latency
parameter TAXPD = 8; // tAXPD tCK ODT power-down exit latency
parameter TMOD = 12000; // tMOD ps ODT enable in EMR to ODT pin transition
// Power Down
parameter TXARD = 2; // tXARD tCK Exit active power down to a read command
parameter TXP = 2; // tXP tCK Exit power down to a non-read command
parameter TCKE = 3; // tCKE tCK CKE minimum high or low pulse width
// Size Parameters based on Part Width
`ifdef x4
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 13; // MAX Address Bits
parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW Four access window time for the number of activates in an 8 bank device
`else `ifdef x8
parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 13; // MAX Address Bits
parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used
parameter TRRD = 7500; // tRRD Active bank a to Active bank b command time
parameter TFAW = 37500; // tFAW Four access window time for the number of activates in an 8 bank device
`else `define x16
parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used
parameter ADDR_BITS = 13; // MAX Address Bits
parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used
parameter COL_BITS = 9; // Set this parameter to control how many Column bits are used
parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used
parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used
parameter TRRD = 10000; // tRRD Active bank a to Active bank b command time
parameter TFAW = 50000; // tFAW Four access window time for the number of activates in an 8 bank device
`endif `endif
// Size Parameters
parameter BA_BITS = 2; // Set this parmaeter to control how many Bank Address bits are used
parameter MEM_BITS = 10; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024.
parameter AP = 10; // the address bit that controls auto-precharge and precharge-all
parameter BL_BITS = 3; // the number of bits required to count to MAX_BL
parameter BO_BITS = 2; // the number of Burst Order Bits
// Simulation parameters
parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors
parameter DEBUG = 0; // Turn on Debug messages
parameter BUS_DELAY = 0; // delay in nanoseconds
parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads
parameter RANDOM_SEED = 711689044; //seed value for random generator.
parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe
parameter RDQSEN_PST = 1; // DQS driving time after last read strobe
parameter RDQS_PRE = 2; // DQS low time prior to first read strobe
parameter RDQS_PST = 1; // DQS low time after last valid read strobe
parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data
parameter RDQEN_PST = 0; // DQ/DM driving time after last read data
parameter WDQS_PRE = 1; // DQS half clock periods prior to first write strobe
parameter WDQS_PST = 1; // DQS half clock periods after last valid write strobe
// text macros
`define DQ_PER_DQS DQ_BITS/DQS_BITS
`define BANKS (1<<BA_BITS)
`define MAX_BITS (BA_BITS+ROW_BITS+COL_BITS-BL_BITS)
`define MAX_SIZE (1<<(BA_BITS+ROW_BITS+COL_BITS-BL_BITS))
`define MEM_SIZE (1<<MEM_BITS)
`define MAX_PIPE 2*(AL_MAX + CL_MAX)
// Declare Ports
input ck;
input ck_n;
input cke;
input cs_n;
input ras_n;
input cas_n;
input we_n;
inout [DM_BITS-1:0] dm_rdqs;
input [BA_BITS-1:0] ba;
input [ADDR_BITS-1:0] addr;
inout [DQ_BITS-1:0] dq;
inout [DQS_BITS-1:0] dqs;
inout [DQS_BITS-1:0] dqs_n;
output [DQS_BITS-1:0] rdqs_n;
input odt;
// clock jitter
real tck_avg;
time tck_sample [TDLLK-1:0];
time tch_sample [TDLLK-1:0];
time tcl_sample [TDLLK-1:0];
time tck_i;
time tch_i;
time tcl_i;
real tch_avg;
real tcl_avg;
time tm_ck_pos;
time tm_ck_neg;
real tjit_per_rtime;
integer tjit_cc_time;
real terr_nper_rtime;
// clock skew
real out_delay;
integer dqsck [DQS_BITS-1:0];
integer dqsck_min;
integer dqsck_max;
integer dqsq_min;
integer dqsq_max;
integer seed;
// Mode Registers
reg burst_order;
reg [BL_BITS:0] burst_length;
integer cas_latency;
integer additive_latency;
reg dll_reset;
reg dll_locked;
reg dll_en;
integer write_recovery;
reg low_power;
reg [1:0] odt_rtt;
reg odt_en;
reg [2:0] ocd;
reg dqs_n_en;
reg rdqs_en;
reg out_en;
integer read_latency;
integer write_latency;
// cmd encoding
parameter
LOAD_MODE = 4'b0000,
REFRESH = 4'b0001,
PRECHARGE = 4'b0010,
ACTIVATE = 4'b0011,
WRITE = 4'b0100,
READ = 4'b0101,
NOP = 4'b0111,
PWR_DOWN = 4'b1000,
SELF_REF = 4'b1001
;
reg [8*9-1:0] cmd_string [9:0];
initial begin
cmd_string[LOAD_MODE] = "Load Mode";
cmd_string[REFRESH ] = "Refresh ";
cmd_string[PRECHARGE] = "Precharge";
cmd_string[ACTIVATE ] = "Activate ";
cmd_string[WRITE ] = "Write ";
cmd_string[READ ] = "Read ";
cmd_string[NOP ] = "No Op ";
cmd_string[PWR_DOWN ] = "Pwr Down ";
cmd_string[SELF_REF ] = "Self Ref ";
end
// command state
reg [`BANKS-1:0] active_bank;
reg [`BANKS-1:0] auto_precharge_bank;
reg [`BANKS-1:0] write_precharge_bank;
reg [`BANKS-1:0] read_precharge_bank;
reg [ROW_BITS-1:0] active_row [`BANKS-1:0];
reg in_power_down;
reg in_self_refresh;
reg precharge_all;
reg [3:0] init_mode_reg;
reg init_done;
integer init_step;
reg er_trfc_max;
reg odt_state;
reg prev_odt;
// cmd timers/counters
integer ref_cntr;
integer ck_cntr;
integer ck_load_mode;
integer ck_write;
integer ck_read;
integer ck_power_down;
integer ck_slow_exit_pd;
integer ck_self_refresh;
integer ck_cke;
integer ck_odt;
integer ck_dll_reset;
integer ck_bank_write [`BANKS-1:0];
integer ck_bank_read [`BANKS-1:0];
time tm_refresh;
time tm_precharge;
time tm_activate;
time tm_write_end;
time tm_self_refresh;
time tm_odt_en;
time tm_bank_precharge [`BANKS-1:0];
time tm_bank_activate [`BANKS-1:0];
time tm_bank_write_end [`BANKS-1:0];
time tm_bank_read_end [`BANKS-1:0];
// pipelines
reg [`MAX_PIPE:0] al_pipeline;
reg [`MAX_PIPE:0] wr_pipeline;
reg [`MAX_PIPE:0] rd_pipeline;
reg [`MAX_PIPE:0] odt_pipeline;
reg [BA_BITS-1:0] ba_pipeline [`MAX_PIPE:0];
reg [ROW_BITS-1:0] row_pipeline [`MAX_PIPE:0];
reg [COL_BITS-1:0] col_pipeline [`MAX_PIPE:0];
reg prev_cke;
// data state
reg [BL_MAX*DQ_BITS-1:0] memory_data;
reg [BL_MAX*DQ_BITS-1:0] bit_mask;
reg [BL_BITS-1:0] burst_position;
reg [BL_BITS:0] burst_cntr;
reg [DQ_BITS-1:0] dq_temp;
reg [31:0] check_write_postamble;
reg [31:0] check_write_preamble;
reg [31:0] check_write_dqs_high;
reg [31:0] check_write_dqs_low;
reg [15:0] check_dm_tdipw;
reg [63:0] check_dq_tdipw;
// data timers/counters
time tm_cke;
time tm_odt;
time tm_tdqss;
time tm_dm [15:0];
time tm_dqs [15:0];
time tm_dqs_pos [31:0];
time tm_dqss_pos [31:0];
time tm_dqs_neg [31:0];
time tm_dq [63:0];
time tm_cmd_addr [22:0];
reg [8*7-1:0] cmd_addr_string [22:0];
initial begin
cmd_addr_string[ 0] = "CS_N ";
cmd_addr_string[ 1] = "RAS_N ";
cmd_addr_string[ 2] = "CAS_N ";
cmd_addr_string[ 3] = "WE_N ";
cmd_addr_string[ 4] = "BA 0 ";
cmd_addr_string[ 5] = "BA 1 ";
cmd_addr_string[ 6] = "BA 2 ";
cmd_addr_string[ 7] = "ADDR 0";
cmd_addr_string[ 8] = "ADDR 1";
cmd_addr_string[ 9] = "ADDR 2";
cmd_addr_string[10] = "ADDR 3";
cmd_addr_string[11] = "ADDR 4";
cmd_addr_string[12] = "ADDR 5";
cmd_addr_string[13] = "ADDR 6";
cmd_addr_string[14] = "ADDR 7";
cmd_addr_string[15] = "ADDR 8";
cmd_addr_string[16] = "ADDR 9";
cmd_addr_string[17] = "ADDR 10";
cmd_addr_string[18] = "ADDR 11";
cmd_addr_string[19] = "ADDR 12";
cmd_addr_string[20] = "ADDR 13";
cmd_addr_string[21] = "ADDR 14";
cmd_addr_string[22] = "ADDR 15";
end
reg [8*5-1:0] dqs_string [1:0];
initial begin
dqs_string[0] = "DQS ";
dqs_string[1] = "DQS_N";
end
// Memory Storage
`ifdef MAX_MEM
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MAX_SIZE-1];
`else
reg [BL_MAX*DQ_BITS-1:0] memory [0:`MEM_SIZE-1];
reg [`MAX_BITS-1:0] address [0:`MEM_SIZE-1];
reg [MEM_BITS:0] memory_index;
reg [MEM_BITS:0] memory_used;
`endif
// receive
reg ck_in;
reg ck_n_in;
reg cke_in;
reg cs_n_in;
reg ras_n_in;
reg cas_n_in;
reg we_n_in;
reg [15:0] dm_in;
reg [2:0] ba_in;
reg [15:0] addr_in;
reg [63:0] dq_in;
reg [31:0] dqs_in;
reg odt_in;
reg [15:0] dm_in_pos;
reg [15:0] dm_in_neg;
reg [63:0] dq_in_pos;
reg [63:0] dq_in_neg;
reg dq_in_valid;
reg dqs_in_valid;
integer wdqs_cntr;
integer wdq_cntr;
integer wdqs_pos_cntr [31:0];
reg b2b_write;
reg [31:0] prev_dqs_in;
reg diff_ck;
always @(ck ) ck_in <= #BUS_DELAY ck;
always @(ck_n ) ck_n_in <= #BUS_DELAY ck_n;
always @(cke ) cke_in <= #BUS_DELAY cke;
always @(cs_n ) cs_n_in <= #BUS_DELAY cs_n;
always @(ras_n ) ras_n_in <= #BUS_DELAY ras_n;
always @(cas_n ) cas_n_in <= #BUS_DELAY cas_n;
always @(we_n ) we_n_in <= #BUS_DELAY we_n;
always @(dm_rdqs) dm_in <= #BUS_DELAY dm_rdqs;
always @(ba ) ba_in <= #BUS_DELAY ba;
always @(addr ) addr_in <= #BUS_DELAY addr;
always @(dq ) dq_in <= #BUS_DELAY dq;
always @(dqs or dqs_n) dqs_in <= #BUS_DELAY (dqs_n<<16) | dqs;
always @(odt ) odt_in <= #BUS_DELAY odt;
// create internal clock
always @(posedge ck_in) diff_ck <= ck_in;
always @(posedge ck_n_in) diff_ck <= ~ck_n_in;
wire [15:0] dqs_even = dqs_in[15:0];
wire [15:0] dqs_odd = dqs_n_en ? dqs_in[31:16] : ~dqs_in[15:0];
wire [3:0] cmd_n_in = !cs_n_in ? {ras_n_in, cas_n_in, we_n_in} : NOP; //deselect = nop
// transmit
reg dqs_out_en;
reg [DQS_BITS-1:0] dqs_out_en_dly;
reg dqs_out;
reg [DQS_BITS-1:0] dqs_out_dly;
reg dq_out_en;
reg [DQ_BITS-1:0] dq_out_en_dly;
reg [DQ_BITS-1:0] dq_out;
reg [DQ_BITS-1:0] dq_out_dly;
integer rdqsen_cntr;
integer rdqs_cntr;
integer rdqen_cntr;
integer rdq_cntr;
bufif1 buf_dqs [DQS_BITS-1:0] (dqs, dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}});
bufif1 buf_dm [DM_BITS-1:0] (dm_rdqs, dqs_out_dly, dqs_out_en_dly & {DM_BITS {out_en}} & {DM_BITS{rdqs_en}});
bufif1 buf_dqs_n [DQS_BITS-1:0] (dqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}});
bufif1 buf_rdqs_n [DQS_BITS-1:0] (rdqs_n, ~dqs_out_dly, dqs_out_en_dly & {DQS_BITS{out_en}} & {DQS_BITS{dqs_n_en}} & {DQS_BITS{rdqs_en}});
bufif1 buf_dq [DQ_BITS-1:0] (dq, dq_out_dly, dq_out_en_dly & {DQ_BITS {out_en}});
initial begin
if (BL_MAX < 2)
$display("%m ERROR: BL_MAX parameter must be >= 2. \nBL_MAX = %d", BL_MAX);
if ((1<<BO_BITS) > BL_MAX)
$display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter.");
$timeformat (-12, 1, " ps", 1);
reset_task;
seed = RANDOM_SEED;
ck_cntr = 0;
end
// calculate the absolute value of a real number
function real abs_value;
input arg;
real arg;
begin
if (arg < 0.0)
abs_value = -1.0 * arg;
else
abs_value = arg;
end
endfunction
`ifdef MAX_MEM
`else
function get_index;
input [`MAX_BITS-1:0] addr;
begin : index
get_index = 0;
for (memory_index=0; memory_index<memory_used; memory_index=memory_index+1) begin
if (address[memory_index] == addr) begin
get_index = 1;
disable index;
end
end
end
endfunction
`endif
task memory_write;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
input [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
memory[addr] = data;
`else
if (get_index(addr)) begin
address[memory_index] = addr;
memory[memory_index] = data;
end else if (memory_used == `MEM_SIZE) begin
$display ("%m: at time %t ERROR: Memory overflow. Write to Address %h with Data %h will be lost.\nYou must increase the MEM_BITS parameter or define MAX_MEM.", $time, addr, data);
if (STOP_ON_ERROR) $stop(0);
end else begin
address[memory_used] = addr;
memory[memory_used] = data;
memory_used = memory_used + 1;
end
`endif
end
endtask
task memory_read;
input [BA_BITS-1:0] bank;
input [ROW_BITS-1:0] row;
input [COL_BITS-1:0] col;
output [BL_MAX*DQ_BITS-1:0] data;
reg [`MAX_BITS-1:0] addr;
begin
// chop off the lowest address bits
addr = {bank, row, col}/BL_MAX;
`ifdef MAX_MEM
data = memory[addr];
`else
if (get_index(addr)) begin
data = memory[memory_index];
end else begin
data = {BL_MAX*DQ_BITS{1'bx}};
end
`endif
end
endtask
// Before this task runs, the model must be in a valid state for precharge power down.
// After this task runs, NOP commands must be issued until tRFC has been met
task initialize;
input [ADDR_BITS-1:0] mode_reg0;
input [ADDR_BITS-1:0] mode_reg1;
input [ADDR_BITS-1:0] mode_reg2;
input [ADDR_BITS-1:0] mode_reg3;
begin
if (DEBUG) $display ("%m: at time %t INFO: Performing Initialization Sequence", $time);
cmd_task(1, NOP, 'bx, 'bx);
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, LOAD_MODE, 3, mode_reg3);
cmd_task(1, LOAD_MODE, 2, mode_reg2);
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(1, LOAD_MODE, 0, mode_reg0 | 'h100); // DLL Reset
cmd_task(1, PRECHARGE, 'bx, 1<<AP); // Precharege ALL
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, REFRESH, 'bx, 'bx);
cmd_task(1, LOAD_MODE, 0, mode_reg0);
cmd_task(1, LOAD_MODE, 1, mode_reg1 | 'h380); // OCD Default
cmd_task(1, LOAD_MODE, 1, mode_reg1);
cmd_task(0, NOP, 'bx, 'bx);
end
endtask
task reset_task;
integer i;
begin
// disable inputs
dq_in_valid = 0;
dqs_in_valid <= 0;
wdqs_cntr = 0;
wdq_cntr = 0;
for (i=0; i<32; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
b2b_write <= 0;
// disable outputs
out_en = 0;
dqs_n_en = 0;
rdqs_en = 0;
dq_out_en = 0;
rdq_cntr = 0;
dqs_out_en = 0;
rdqs_cntr = 0;
// disable ODT
odt_en = 0;
odt_state = 0;
// reset bank state
active_bank = {`BANKS{1'b1}};
auto_precharge_bank = 0;
read_precharge_bank = 0;
write_precharge_bank = 0;
// require initialization sequence
init_done = 0;
init_step = 0;
init_mode_reg = 0;
// reset DLL
dll_en = 0;
dll_reset = 0;
dll_locked = 0;
ocd = 0;
// exit power down and self refresh
in_power_down = 0;
in_self_refresh = 0;
// clear pipelines
al_pipeline = 0;
wr_pipeline = 0;
rd_pipeline = 0;
odt_pipeline = 0;
// clear memory
`ifdef MAX_MEM
for (i=0; i<=`MAX_SIZE; i=i+1) begin //erase memory ... one address at a time
memory[i] <= 'bx;
end
`else
memory_used <= 0; //erase memory
`endif
end
endtask
task chk_err;
input samebank;
input [BA_BITS-1:0] bank;
input [3:0] fromcmd;
input [3:0] cmd;
reg err;
begin
// all matching case expressions will be evaluated
casex ({samebank, fromcmd, cmd})
{1'b0, LOAD_MODE, 4'b0xxx } : begin if (ck_cntr - ck_load_mode < TMRD) $display ("%m: at time %t ERROR: tMRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, LOAD_MODE, 4'b100x } : begin if (ck_cntr - ck_load_mode < TMRD) begin $display ("%m: at time %t INFO: Load Mode to Reset condition.", $time); init_done = 0; end end
{1'b0, REFRESH , 4'b0xxx } : begin if ($time - tm_refresh < TRFC_MIN) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); end
{1'b0, REFRESH , PWR_DOWN } : ; // 1 tCK
{1'b0, REFRESH , SELF_REF } : begin if ($time - tm_refresh < TRFC_MIN) begin $display ("%m: at time %t INFO: Refresh to Reset condition", $time); init_done = 0; end end
{1'b0, PRECHARGE, 4'b000x } : begin if ($time - tm_precharge < TRP) $display ("%m: at time %t ERROR: tRP violation during %s", $time, cmd_string[cmd]); end
{1'b1, PRECHARGE, PRECHARGE} : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, PRECHARGE, ACTIVATE } : begin if ($time - tm_bank_precharge[bank] < TRP) $display ("%m: at time %t ERROR: tRP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, PRECHARGE, PWR_DOWN } : ; //1 tCK, can be concurrent with auto precharge
{1'b0, PRECHARGE, SELF_REF } : begin if ($time - tm_precharge < TRP) begin $display ("%m: at time %t INFO: Precharge to Reset condition", $time); init_done = 0; end end
{1'b0, ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end
{1'b1, ACTIVATE , PRECHARGE} : begin if ($time - tm_bank_activate[bank] > TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank);
if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end
{1'b0, ACTIVATE , ACTIVATE } : begin if ($time - tm_activate < TRRD) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b1, ACTIVATE , 4'b010x } : ; // tRCD is checked outside this task
{1'b1, ACTIVATE , PWR_DOWN } : ; // 1 tCK
{1'b1, WRITE , PRECHARGE} : begin if ((ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2) || ($time - tm_bank_write_end[bank] < TWR)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , READ } : begin if ((ck_load_mode < ck_write) && (ck_cntr - ck_write < write_latency + burst_length/2 + 2 - additive_latency)) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, WRITE , PWR_DOWN } : begin if ((ck_load_mode < ck_write) && ((ck_cntr - ck_write < write_latency + burst_length/2 + 2) || ($time - tm_write_end < TWTR))) begin $display ("%m: at time %t INFO: Write to Reset condition", $time); init_done = 0; end end
{1'b1, READ , PRECHARGE} : begin if ((ck_cntr - ck_bank_read[bank] < additive_latency + burst_length/2) || ($time - tm_bank_read_end[bank] < TRTP)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , WRITE } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1 - write_latency)) $display ("%m: at time %t ERROR: tRTW violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end
{1'b0, READ , PWR_DOWN } : begin if ((ck_load_mode < ck_read) && (ck_cntr - ck_read < read_latency + burst_length/2 + 1)) begin $display ("%m: at time %t INFO: Read to Reset condition", $time); init_done = 0; end end
{1'b0, PWR_DOWN , 4'b00xx } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , WRITE } : begin if (ck_cntr - ck_power_down < TXP) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end
{1'b0, PWR_DOWN , READ } : begin if (ck_cntr - ck_slow_exit_pd < TXARDS - additive_latency) $display ("%m: at time %t ERROR: tXARDS violation during %s", $time, cmd_string[cmd]);
else if (ck_cntr - ck_power_down < TXARD) $display ("%m: at time %t ERROR: tXARD violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , 4'b00xx } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , WRITE } : begin if ($time - tm_self_refresh < TXSNR) $display ("%m: at time %t ERROR: tXSNR violation during %s", $time, cmd_string[cmd]); end
{1'b0, SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSRD) $display ("%m: at time %t ERROR: tXSRD violation during %s", $time, cmd_string[cmd]); end
{1'b0, 4'b100x , 4'b100x } : begin if (ck_cntr - ck_cke < TCKE) begin $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); init_done = 0; end end
endcase
end
endtask
task cmd_task;
input cke;
input [2:0] cmd;
input [BA_BITS-1:0] bank;
input [ADDR_BITS-1:0] addr;
reg [`BANKS:0] i;
integer j;
reg [`BANKS:0] tfaw_cntr;
reg [COL_BITS-1:0] col;
begin
if ((cmd < NOP) && (cmd != PRECHARGE)) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, cmd);
chk_err(1'b1, bank, j, cmd);
end
chk_err(1'b0, bank, PWR_DOWN, cmd);
chk_err(1'b0, bank, SELF_REF, cmd);
end
// tRFC max check
if (!er_trfc_max && !in_self_refresh) begin
if ($time - tm_refresh > TRFC_MAX) begin
$display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]);
er_trfc_max = 1;
end
end
if (cke) begin
case (cmd)
LOAD_MODE : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank);
case (bank)
0 : begin
// Burst Length
burst_length = 1<<addr[2:0];
if ((burst_length >= BL_MIN) && (burst_length <= BL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, burst_length);
end
// Burst Order
burst_order = addr[3];
if (!burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank);
end else if (burst_order) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order);
end
// CAS Latency
cas_latency = addr[6:4];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency);
end
// Test Mode
if (!addr[7]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Test Mode = Normal", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Test Mode = %d", $time, cmd_string[cmd], bank, addr[7]);
end
// DLL Reset
dll_reset = addr[8];
if (!dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank);
end else if (dll_reset) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank);
dll_locked = 0;
ck_dll_reset <= ck_cntr;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset);
end
// Write Recovery
write_recovery = addr[11:9] + 1;
if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery);
end
// Power Down Mode
low_power = addr[12];
if (!low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Fast Exit", $time, cmd_string[cmd], bank);
end else if (low_power) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = Slow Exit", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power);
end
end
1 : begin
// DLL Enable
dll_en = !addr[0];
if (!dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dll_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en);
end
// Output Drive Strength
if (!addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Full", $time, cmd_string[cmd], bank);
end else if (addr[1]) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = Reduced", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, addr[1]);
end
// ODT Rtt
odt_rtt = {addr[6], addr[2]};
if (odt_rtt == 2'b00) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank);
odt_en = 0;
end else if (odt_rtt == 2'b01) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 75 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b10) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 150 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else if (odt_rtt == 2'b11) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = 50 Ohm", $time, cmd_string[cmd], bank);
odt_en = 1;
tm_odt_en <= $time;
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt);
odt_en = 0;
end
// Additive Latency
additive_latency = addr[5:3];
read_latency = cas_latency + additive_latency;
write_latency = read_latency - 1;
if ((additive_latency >= AL_MIN) && (additive_latency <= AL_MAX)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, additive_latency);
end
// OCD Program
ocd = addr[9:7];
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Exit", $time, cmd_string[cmd], bank);
end else if (ocd == 3'b111) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d OCD Program = OCD Default", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal OCD Program = %b", $time, cmd_string[cmd], bank, ocd);
end
// DQS_N Enable
dqs_n_en = !addr[10];
if (!dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (dqs_n_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d DQS_N Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal DQS_N Enable = %d", $time, cmd_string[cmd], bank, dqs_n_en);
end
// RDQS Enable
rdqs_en = addr[11];
if (!rdqs_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (rdqs_en) begin
`ifdef x8
if (DEBUG) $display ("%m: at time %t INFO: %s %d RDQS Enable = Enabled", $time, cmd_string[cmd], bank);
`else
$display ("%m: at time %t WARNING: %s %d Illegal RDQS Enable. RDQS only exists on a x8 part", $time, cmd_string[cmd], bank);
rdqs_en = 0;
`endif
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal RDQS Enable = %d", $time, cmd_string[cmd], bank, rdqs_en);
end
// Output Enable
out_en = !addr[12];
if (!out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Disabled", $time, cmd_string[cmd], bank);
end else if (out_en) begin
if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Enable = Enabled", $time, cmd_string[cmd], bank);
end else begin
$display ("%m: at time %t ERROR: %s %d Illegal Output Enable = %d", $time, cmd_string[cmd], bank, out_en);
end
end
2, 3 : begin
if (addr !== 0) begin
$display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bits must be programmed to zero", $time, cmd_string[cmd], bank);
end
end
endcase
init_mode_reg[bank] = 1;
ck_load_mode <= ck_cntr;
end
end
REFRESH : begin
if (|active_bank) begin
$display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]);
er_trfc_max = 0;
ref_cntr = ref_cntr + 1;
tm_refresh <= $time;
end
end
PRECHARGE : begin
// tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
// the number of banks already open or closed.
if (addr[AP] && (`BANKS == 8)) begin
if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]);
precharge_all = 1'b1;
end
// PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state),
// or if the previously open row is already in the process of precharging
if (|active_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
if (active_bank[i]) begin
if (addr[AP] || (i == bank)) begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, i, j, cmd);
chk_err(1'b1, i, j, cmd);
end
chk_err(1'b0, i, PWR_DOWN, cmd);
chk_err(1'b0, i, SELF_REF, cmd);
if (auto_precharge_bank[i]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i);
active_bank[i] = 1'b0;
tm_bank_precharge[i] <= $time;
tm_precharge <= $time;
end
end
end
end
end
end
ACTIVATE : begin
if (`BANKS == 8) begin
tfaw_cntr = 0;
for (i=0; i<`BANKS; i=i+1) begin
if ($time - tm_bank_activate[i] < TFAW) begin
tfaw_cntr = tfaw_cntr + 1;
end
end
if (tfaw_cntr > 3) begin
$display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank);
end
end
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr >= 1<<ROW_BITS) begin
$display ("%m: at time %t WARNING: row = %h does not exist. Maximum row = %h", $time, addr, (1<<ROW_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d row %h", $time, cmd_string[cmd], bank, addr);
active_bank[bank] = 1'b1;
active_row[bank] = addr;
tm_bank_activate[bank] <= $time;
tm_activate <= $time;
end
end
WRITE : begin
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_write < burst_length/2) && (ck_cntr - ck_write)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
write_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
wr_pipeline[2*write_latency + 1] = 1;
ba_pipeline[2*write_latency + 1] = bank;
row_pipeline[2*write_latency + 1] = active_row[bank];
col_pipeline[2*write_latency + 1] = col;
ck_bank_write[bank] <= ck_cntr;
ck_write <= ck_cntr;
end
end
READ : begin
if (!dll_locked)
$display ("%m: at time %t WARNING: %s prior to DLL locked. Failing to wait for synchronization to occur may result in a violation of the tAC or tDQSCK parameters.", $time, cmd_string[cmd]);
if (!init_done) begin
$display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else if (!active_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Bank %d must be Activated.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if (auto_precharge_bank[bank]) begin
$display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], bank);
if (STOP_ON_ERROR) $stop(0);
end else if ((ck_cntr - ck_read < burst_length/2) && (ck_cntr - ck_read)%2) begin
$display ("%m: at time %t ERROR: %s Failure. Illegal burst interruption.", $time, cmd_string[cmd]);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (addr[AP]) begin
auto_precharge_bank[bank] = 1'b1;
read_precharge_bank[bank] = 1'b1;
end
col = ((addr>>1) & -1*(1<<AP)) | (addr & {AP{1'b1}});
if (col >= 1<<COL_BITS) begin
$display ("%m: at time %t WARNING: col = %h does not exist. Maximum col = %h", $time, col, (1<<COL_BITS)-1);
end
if (DEBUG) $display ("%m: at time %t INFO: %s bank %d col %h, auto precharge %d", $time, cmd_string[cmd], bank, col, addr[AP]);
rd_pipeline[2*read_latency - 1] = 1;
ba_pipeline[2*read_latency - 1] = bank;
row_pipeline[2*read_latency - 1] = active_row[bank];
col_pipeline[2*read_latency - 1] = col;
ck_bank_read[bank] <= ck_cntr;
ck_read <= ck_cntr;
end
end
NOP: begin
if (in_power_down) begin
if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time);
in_power_down = 0;
if (|active_bank & low_power) begin // slow exit active power down
ck_slow_exit_pd <= ck_cntr;
end
ck_power_down <= ck_cntr;
end
if (in_self_refresh) begin
if ($time - tm_cke < TISXR)
$display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time);
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time);
in_self_refresh = 0;
ck_dll_reset <= ck_cntr;
ck_self_refresh <= ck_cntr;
tm_self_refresh <= $time;
tm_refresh <= $time;
end
end
endcase
if ((prev_cke !== 1) && (cmd !== NOP)) begin
$display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time);
end
if (!init_done) begin
case (init_step)
0 : begin
if ($time < 200000000)
$display ("%m at time %t WARNING: 200 us is required before CKE goes active.", $time);
// if (cmd_chk + 200000000 > $time)
// $display("%m: at time %t WARNING: NOP or DESELECT is required for 200 us before CKE is brought high", $time);
init_step = init_step + 1;
end
1 : if (dll_en) init_step = init_step + 1;
2 : begin
if (&init_mode_reg && dll_reset) begin
active_bank = {`BANKS{1'b1}}; // require Precharge All or bank Precharges
ref_cntr = 0; // require refresh
init_step = init_step + 1;
end
end
3 : if (ref_cntr == 2) begin
init_step = init_step + 1;
end
4 : if (!dll_reset) init_step = init_step + 1;
5 : if (ocd == 3'b111) init_step = init_step + 1;
6 : begin
if (ocd == 3'b000) begin
if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time);
init_done = 1;
end
end
endcase
end
end else if (prev_cke) begin
if ((!init_done) && (init_step > 1)) begin
$display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end
case (cmd)
REFRESH : begin
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, SELF_REF);
end
chk_err(1'b0, bank, PWR_DOWN, SELF_REF);
chk_err(1'b0, bank, SELF_REF, SELF_REF);
if (|active_bank) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (odt_en && odt_state) begin
$display ("%m: at time %t ERROR: ODT must be off prior to entering Self Refresh", $time);
if (STOP_ON_ERROR) $stop(0);
init_done = 0;
end else if (!init_done) begin
$display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time);
in_self_refresh = 1;
dll_locked = 0;
end
end
NOP : begin
// entering slow_exit or precharge power down and tANPD has not been satisfied
if ((low_power || (active_bank == 0)) && (ck_cntr - ck_odt < TANPD))
$display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]);
for (j=0; j<NOP; j=j+1) begin
chk_err(1'b0, bank, j, PWR_DOWN);
end
chk_err(1'b0, bank, PWR_DOWN, PWR_DOWN);
chk_err(1'b0, bank, SELF_REF, PWR_DOWN);
if (!init_done) begin
$display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time);
if (STOP_ON_ERROR) $stop(0);
end else begin
if (DEBUG) begin
if (|active_bank) begin
$display ("%m: at time %t INFO: Active Power Down Enter", $time);
end else begin
$display ("%m: at time %t INFO: Precharge Power Down Enter", $time);
end
end
in_power_down = 1;
end
end
default : begin
$display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time);
init_done = 0;
end
endcase
if (!init_done) begin
if (DEBUG) $display ("%m: at time %t INFO: Reset has occurred.", $time);
reset_task;
end
end
prev_cke = cke;
end
endtask
task data_task;
reg [BA_BITS-1:0] bank;
reg [ROW_BITS-1:0] row;
reg [COL_BITS-1:0] col;
integer i;
integer j;
begin
if (diff_ck) begin
for (i=0; i<32; i=i+1) begin
if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg)))
$display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
if (check_write_dqs_high[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16);
end
check_write_dqs_high <= 0;
end else begin
for (i=0; i<32; i=i+1) begin
if (dll_locked && dq_in_valid) begin
tm_tdqss = abs_value($itor(tm_ck_pos) - tm_dqss_pos[i]);
if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg))
$display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if (check_write_dqs_low[i])
$display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16);
end
check_write_preamble <= 0;
check_write_postamble <= 0;
check_write_dqs_low <= 0;
end
if (wr_pipeline[0] || rd_pipeline[0]) begin
bank = ba_pipeline[0];
row = row_pipeline[0];
col = col_pipeline[0];
burst_cntr = 0;
memory_read(bank, row, col, memory_data);
end
// burst counter
if (burst_cntr < burst_length) begin
burst_position = col ^ burst_cntr;
if (!burst_order) begin
burst_position[BO_BITS-1:0] = col + burst_cntr;
end
burst_cntr = burst_cntr + 1;
end
// write dqs counter
if (wr_pipeline[WDQS_PRE + 1]) begin
wdqs_cntr = WDQS_PRE + burst_length + WDQS_PST - 1;
end
// write dqs
if ((wdqs_cntr == burst_length + WDQS_PST) && (wdq_cntr == 0)) begin //write preamble
check_write_preamble <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 1) begin // write data
if ((wdqs_cntr - WDQS_PST)%2) begin
check_write_dqs_high <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}};
end else begin
check_write_dqs_low <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}};
end
end
if (wdqs_cntr == WDQS_PST) begin // write postamble
check_write_postamble <= ({DQS_BITS{dqs_n_en}}<<16) | {DQS_BITS{1'b1}};
end
if (wdqs_cntr > 0) begin
wdqs_cntr = wdqs_cntr - 1;
end
// write dq
if (dq_in_valid) begin // write data
bit_mask = 0;
if (diff_ck) begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_neg[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_neg<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end else begin
for (i=0; i<DM_BITS; i=i+1) begin
bit_mask = bit_mask | ({`DQ_PER_DQS{~dm_in_pos[i]}}<<(burst_position*DQ_BITS + i*`DQ_PER_DQS));
end
memory_data = (dq_in_pos<<(burst_position*DQ_BITS) & bit_mask) | (memory_data & ~bit_mask);
end
dq_temp = memory_data>>(burst_position*DQ_BITS);
if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
if (burst_cntr%BL_MIN == 0) begin
memory_write(bank, row, col, memory_data);
end
end
if (wr_pipeline[1]) begin
wdq_cntr = burst_length;
end
if (wdq_cntr > 0) begin
wdq_cntr = wdq_cntr - 1;
dq_in_valid = 1'b1;
end else begin
dq_in_valid = 1'b0;
dqs_in_valid <= 1'b0;
for (i=0; i<32; i=i+1) begin
wdqs_pos_cntr[i] <= 0;
end
end
if (wr_pipeline[0]) begin
b2b_write <= 1'b0;
end
if (wr_pipeline[2]) begin
if (dqs_in_valid) begin
b2b_write <= 1'b1;
end
dqs_in_valid <= 1'b1;
end
// read dqs enable counter
if (rd_pipeline[RDQSEN_PRE]) begin
rdqsen_cntr = RDQSEN_PRE + burst_length + RDQSEN_PST - 1;
end
if (rdqsen_cntr > 0) begin
rdqsen_cntr = rdqsen_cntr - 1;
dqs_out_en = 1'b1;
end else begin
dqs_out_en = 1'b0;
end
// read dqs counter
if (rd_pipeline[RDQS_PRE]) begin
rdqs_cntr = RDQS_PRE + burst_length + RDQS_PST - 1;
end
// read dqs
if ((rdqs_cntr >= burst_length + RDQS_PST) && (rdq_cntr == 0)) begin //read preamble
dqs_out = 1'b0;
end else if (rdqs_cntr > RDQS_PST) begin // read data
dqs_out = rdqs_cntr - RDQS_PST;
end else if (rdqs_cntr > 0) begin // read postamble
dqs_out = 1'b0;
end else begin
dqs_out = 1'b1;
end
if (rdqs_cntr > 0) begin
rdqs_cntr = rdqs_cntr - 1;
end
// read dq enable counter
if (rd_pipeline[RDQEN_PRE]) begin
rdqen_cntr = RDQEN_PRE + burst_length + RDQEN_PST;
end
if (rdqen_cntr > 0) begin
rdqen_cntr = rdqen_cntr - 1;
dq_out_en = 1'b1;
end else begin
dq_out_en = 1'b0;
end
// read dq
if (rd_pipeline[0]) begin
rdq_cntr = burst_length;
end
if (rdq_cntr > 0) begin // read data
dq_temp = memory_data>>(burst_position*DQ_BITS);
dq_out = dq_temp;
if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp);
rdq_cntr = rdq_cntr - 1;
end else begin
dq_out = {DQ_BITS{1'b1}};
end
// delay signals prior to output
if (RANDOM_OUT_DELAY && (dqs_out_en || |dqs_out_en_dly || dq_out_en || |dq_out_en_dly)) begin
for (i=0; i<DQS_BITS; i=i+1) begin
// DQSCK requirements
// 1.) less than tDQSCK
// 2.) greater than -tDQSCK
// 3.) cannot change more than tQHS + tDQSQ from previous DQS edge
dqsck_max = TDQSCK;
if (dqsck_max > dqsck[i] + TQHS + TDQSQ) begin
dqsck_max = dqsck[i] + TQHS + TDQSQ;
end
dqsck_min = -1*TDQSCK;
if (dqsck_min < dqsck[i] - TQHS - TDQSQ) begin
dqsck_min = dqsck[i] - TQHS - TDQSQ;
end
// DQSQ requirements
// 1.) less than tAC - DQSCK
// 2.) less than tDQSQ
// 3.) greater than -tAC
// 4.) greater than tQH from previous DQS edge
dqsq_min = -1*TAC;
if (dqsq_min < dqsck[i] - TQHS) begin
dqsq_min = dqsck[i] - TQHS;
end
if (dqsck_min == dqsck_max) begin
dqsck[i] = dqsck_min;
end else begin
dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max);
end
dqsq_max = TAC;
if (dqsq_max > TDQSQ + dqsck[i]) begin
dqsq_max = TDQSQ + dqsck[i];
end
dqs_out_en_dly[i] <= #(tck_avg/2 + ($random % TAC)) dqs_out_en;
dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out;
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2 + ($random % TAC)) dq_out_en;
if (dqsq_min == dqsq_max) begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j];
end else begin
dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j];
end
end
end
end else begin
out_delay = tck_avg/2;
dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}};
dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }};
dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }};
dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }};
end
end
endtask
always @(diff_ck) begin : main
integer i;
if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1))
$display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time);
data_task;
if (diff_ck) begin
// check setup of command signals
if ($time > TIS) begin
if ($time - tm_cke < TIS)
$display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time);
if (cke_in) begin
for (i=0; i<22; i=i+1) begin
if ($time - tm_cmd_addr[i] < TIS)
$display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time);
end
end
end
// update current state
if (!dll_locked && !in_self_refresh && (ck_cntr - ck_dll_reset == TDLLK)) begin
// check CL value against the clock frequency
if (cas_latency*tck_avg < CL_TIME)
$display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg);
// check WR value against the clock frequency
if (write_recovery*tck_avg < TWR)
$display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg);
dll_locked = 1;
end
if (precharge_all) begin
for (i=0; i<`BANKS; i=i+1) begin
tm_bank_precharge[i] = $time;
end
precharge_all = 1'b0;
tm_precharge = $time;
end
if (|auto_precharge_bank) begin
for (i=0; i<`BANKS; i=i+1) begin
// Write with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command
if (write_precharge_bank[i]) begin
if ($time - tm_bank_activate[i] >= TRAS_MIN) begin
if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
write_precharge_bank[i] = 0;
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
end
end
// Read with Auto Precharge Calculation
// 1. Meet minimum tRAS requirement
// 2. Additive Latency plus BL/2 cycles after Read command
// 3. tRTP after the last 4-bit prefetch
if (read_precharge_bank[i]) begin
if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + burst_length/2)) begin
read_precharge_bank[i] = 0;
// In case the internal precharge is pushed out by tRTP, tRP starts at the point where
// the internal precharge happens (not at the next rising clock edge after this event).
if ($time - tm_bank_read_end[i] < TRTP) begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i);
active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0;
tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i);
active_bank[i] = 0;
auto_precharge_bank[i] = 0;
tm_bank_precharge[i] = $time;
tm_precharge = $time;
end
end
end
end
end
// respond to incoming command
if (cke_in ^ prev_cke) begin
ck_cke <= ck_cntr;
end
cmd_task(cke_in, cmd_n_in, ba_in, addr_in);
if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin
al_pipeline[2*additive_latency] = 1'b1;
end
if (al_pipeline[0]) begin
// check tRCD after additive latency
if ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD) begin
if (rd_pipeline[2*cas_latency - 1]) begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]);
end else begin
$display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]);
end
end
// check tWTR after additive latency
if (rd_pipeline[2*cas_latency - 1]) begin
if ($time - tm_write_end < TWTR)
$display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]);
end
end
if (rd_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]) begin
tm_bank_read_end[ba_pipeline[2*(cas_latency - burst_length/2 + 2) - 1]] <= $time;
end
for (i=0; i<`BANKS; i=i+1) begin
if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin
tm_bank_write_end[i] <= $time;
tm_write_end <= $time;
end
end
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
tjit_cc_time = $time - tm_ck_pos - tck_i;
tck_i = $time - tm_ck_pos;
tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tck_avg = tck_avg + tck_i/$itor(TDLLK);
tck_sample[ck_cntr%TDLLK] = tck_i;
tjit_per_rtime = tck_i - tck_avg;
if (dll_locked) begin
// check accumulated error
terr_nper_rtime = 0;
for (i=0; i<50; i=i+1) begin
terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg;
terr_nper_rtime = abs_value(terr_nper_rtime);
case (i)
0 :;
1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER);
2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER);
3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER);
4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER);
5,6,7,8,9 : if (terr_nper_rtime - TERR_N1PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n1per) violation by %f ps.", $time, terr_nper_rtime - TERR_N1PER);
default : if (terr_nper_rtime - TERR_N2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(n2per) violation by %f ps.", $time, terr_nper_rtime - TERR_N2PER);
endcase
end
// check tCK min/max/jitter
if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0)
$display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER);
if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0)
$display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC);
if (TCK_MIN - tck_avg >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg);
if (tck_avg - TCK_MAX >= 1.0)
$display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX);
if (tm_ck_pos + TCK_MIN - TJIT_PER > $time)
$display ("%m: at time %t ERROR: tCK(abs) minimum violation by %t", $time, tm_ck_pos + TCK_MIN - TJIT_PER - $time);
if (tm_ck_pos + TCK_MAX + TJIT_PER < $time)
$display ("%m: at time %t ERROR: tCK(abs) maximum violation by %t", $time, $time - tm_ck_pos - TCK_MAX - TJIT_PER);
// check tCL
if (tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, tm_ck_neg + TCL_MIN*tck_avg - TJIT_DUTY - $time);
if (tm_ck_neg + TCL_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCL(abs) maximum violation on CLK by %t", $time, $time - tm_ck_neg - TCL_MAX*tck_avg - TJIT_DUTY);
if (tcl_avg < TCL_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_MIN*tck_avg - tcl_avg);
if (tcl_avg > TCL_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_MAX*tck_avg);
end
// calculate the tch avg jitter
tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tch_avg = tch_avg + tch_i/$itor(TDLLK);
tch_sample[ck_cntr%TDLLK] = tch_i;
// update timers/counters
tcl_i <= $time - tm_ck_neg;
end
prev_odt <= odt_in;
// update timers/counters
ck_cntr <= ck_cntr + 1;
tm_ck_pos <= $time;
end else begin
// clk pin is disabled during self refresh
if (!in_self_refresh) begin
if (dll_locked) begin
if (tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY > $time)
$display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, tm_ck_pos + TCH_MIN*tck_avg - TJIT_DUTY + $time);
if (tm_ck_pos + TCH_MAX*tck_avg + TJIT_DUTY < $time)
$display ("%m: at time %t ERROR: tCH(abs) maximum violation on CLK by %t", $time, $time - tm_ck_pos - TCH_MAX*tck_avg - TJIT_DUTY);
if (tch_avg < TCH_MIN*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_MIN*tck_avg - tch_avg);
if (tch_avg > TCH_MAX*tck_avg)
$display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_MAX*tck_avg);
end
// calculate the tcl avg jitter
tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK);
tcl_avg = tcl_avg + tcl_i/$itor(TDLLK);
tcl_sample[ck_cntr%TDLLK] = tcl_i;
// update timers/counters
tch_i <= $time - tm_ck_pos;
end
tm_ck_neg <= $time;
end
// on die termination
if (odt_en) begin
// clk pin is disabled during self refresh
if (!in_self_refresh && diff_ck) begin
if ($time - tm_odt < TIS) begin
$display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time);
end
if (prev_odt ^ odt_in) begin
if (!dll_locked)
$display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time);
if (odt_in && ($time - tm_odt_en < TMOD))
$display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time);
if ($time - tm_self_refresh < TXSNR)
$display ("%m: at time %t ERROR: tXSNR violation during ODT transition", $time);
if (in_self_refresh)
$display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time);
// async ODT mode applies:
// 1.) during active power down with slow exit
// 2.) during precharge power down
// 3.) if tANPD has not been satisfied
// 4.) until tAXPD has been satisfied
if ((in_power_down && (low_power || (active_bank == 0))) || (ck_cntr - ck_slow_exit_pd < TAXPD)) begin
if (ck_cntr - ck_slow_exit_pd < TAXPD)
$display ("%m: at time %t WARNING: tAXPD violation during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time);
if (odt_in) begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAONPD, 1'b1);
odt_state <= #(TAONPD) 1'b1;
end else begin
if (DEBUG) $display ("%m: at time %t INFO: Async On Die Termination = %d", $time + TAOFPD, 1'b0);
odt_state <= #(TAOFPD) 1'b0;
end
// sync ODT mode applies:
// 1.) during normal operation
// 2.) during active power down with fast exit
end else begin
if (odt_in) begin
i = TAOND*2;
odt_pipeline[i] = 1'b1;
end else begin
i = TAOFD*2;
odt_pipeline[i] = 1'b1;
end
end
ck_odt <= ck_cntr;
end
end
if (odt_pipeline[0]) begin
odt_state = ~odt_state;
if (DEBUG) $display ("%m: at time %t INFO: Sync On Die Termination = %d", $time, odt_state);
end
end
// shift pipelines
if (|wr_pipeline || |rd_pipeline || |al_pipeline) begin
al_pipeline = al_pipeline>>1;
wr_pipeline = wr_pipeline>>1;
rd_pipeline = rd_pipeline>>1;
for (i=0; i<`MAX_PIPE; i=i+1) begin
ba_pipeline[i] = ba_pipeline[i+1];
row_pipeline[i] = row_pipeline[i+1];
col_pipeline[i] = col_pipeline[i+1];
end
end
if (|odt_pipeline) begin
odt_pipeline = odt_pipeline>>1;
end
end
// receiver(s)
task dqs_even_receiver;
input [3:0] i;
reg [DQ_BITS-1:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_even[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_pos[i] = 1'b0;
end else begin
dm_in_pos[i] = dm_in[i];
end
dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask);
end
end
endtask
always @(posedge dqs_even[ 0]) dqs_even_receiver( 0);
always @(posedge dqs_even[ 1]) dqs_even_receiver( 1);
always @(posedge dqs_even[ 2]) dqs_even_receiver( 2);
always @(posedge dqs_even[ 3]) dqs_even_receiver( 3);
always @(posedge dqs_even[ 4]) dqs_even_receiver( 4);
always @(posedge dqs_even[ 5]) dqs_even_receiver( 5);
always @(posedge dqs_even[ 6]) dqs_even_receiver( 6);
always @(posedge dqs_even[ 7]) dqs_even_receiver( 7);
always @(posedge dqs_even[ 8]) dqs_even_receiver( 8);
always @(posedge dqs_even[ 9]) dqs_even_receiver( 9);
always @(posedge dqs_even[10]) dqs_even_receiver(10);
always @(posedge dqs_even[11]) dqs_even_receiver(11);
always @(posedge dqs_even[12]) dqs_even_receiver(12);
always @(posedge dqs_even[13]) dqs_even_receiver(13);
always @(posedge dqs_even[14]) dqs_even_receiver(14);
always @(posedge dqs_even[15]) dqs_even_receiver(15);
task dqs_odd_receiver;
input [3:0] i;
reg [DQ_BITS-1:0] bit_mask;
begin
bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS);
if (dqs_odd[i]) begin
if (rdqs_en) begin // rdqs disables dm
dm_in_neg[i] = 1'b0;
end else begin
dm_in_neg[i] = dm_in[i];
end
dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask);
end
end
endtask
always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0);
always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1);
always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2);
always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3);
always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4);
always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5);
always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6);
always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7);
always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8);
always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9);
always @(posedge dqs_odd[10]) dqs_odd_receiver(10);
always @(posedge dqs_odd[11]) dqs_odd_receiver(11);
always @(posedge dqs_odd[12]) dqs_odd_receiver(12);
always @(posedge dqs_odd[13]) dqs_odd_receiver(13);
always @(posedge dqs_odd[14]) dqs_odd_receiver(14);
always @(posedge dqs_odd[15]) dqs_odd_receiver(15);
// Processes to check hold and pulse width of control signals
always @(cke_in) begin
if ($time > TIH) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time);
end
if (dll_locked && ($time - tm_cke < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW*tck_avg - $time);
tm_cke = $time;
end
always @(odt_in) begin
if (odt_en && !in_self_refresh) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_odt < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW*tck_avg - $time);
end
tm_odt = $time;
end
task cmd_addr_timing_check;
input i;
reg [4:0] i;
begin
if (prev_cke) begin
if ($time - tm_ck_pos < TIH)
$display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time);
if (dll_locked && ($time - tm_cmd_addr[i] < $rtoi(TIPW*tck_avg)))
$display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW*tck_avg - $time);
end
tm_cmd_addr[i] = $time;
end
endtask
always @(cs_n_in ) cmd_addr_timing_check( 0);
always @(ras_n_in ) cmd_addr_timing_check( 1);
always @(cas_n_in ) cmd_addr_timing_check( 2);
always @(we_n_in ) cmd_addr_timing_check( 3);
always @(ba_in [ 0]) cmd_addr_timing_check( 4);
always @(ba_in [ 1]) cmd_addr_timing_check( 5);
always @(ba_in [ 2]) cmd_addr_timing_check( 6);
always @(addr_in[ 0]) cmd_addr_timing_check( 7);
always @(addr_in[ 1]) cmd_addr_timing_check( 8);
always @(addr_in[ 2]) cmd_addr_timing_check( 9);
always @(addr_in[ 3]) cmd_addr_timing_check(10);
always @(addr_in[ 4]) cmd_addr_timing_check(11);
always @(addr_in[ 5]) cmd_addr_timing_check(12);
always @(addr_in[ 6]) cmd_addr_timing_check(13);
always @(addr_in[ 7]) cmd_addr_timing_check(14);
always @(addr_in[ 8]) cmd_addr_timing_check(15);
always @(addr_in[ 9]) cmd_addr_timing_check(16);
always @(addr_in[10]) cmd_addr_timing_check(17);
always @(addr_in[11]) cmd_addr_timing_check(18);
always @(addr_in[12]) cmd_addr_timing_check(19);
always @(addr_in[13]) cmd_addr_timing_check(20);
always @(addr_in[14]) cmd_addr_timing_check(21);
always @(addr_in[15]) cmd_addr_timing_check(22);
// Processes to check setup and hold of data signals
task dm_timing_check;
input i;
reg [3:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time);
if (check_dm_tdipw[i]) begin
if (dll_locked && ($time - tm_dm[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW*tck_avg - $time);
end
end
check_dm_tdipw[i] <= 1'b0;
tm_dm[i] = $time;
end
endtask
always @(dm_in[ 0]) dm_timing_check( 0);
always @(dm_in[ 1]) dm_timing_check( 1);
always @(dm_in[ 2]) dm_timing_check( 2);
always @(dm_in[ 3]) dm_timing_check( 3);
always @(dm_in[ 4]) dm_timing_check( 4);
always @(dm_in[ 5]) dm_timing_check( 5);
always @(dm_in[ 6]) dm_timing_check( 6);
always @(dm_in[ 7]) dm_timing_check( 7);
always @(dm_in[ 8]) dm_timing_check( 8);
always @(dm_in[ 9]) dm_timing_check( 9);
always @(dm_in[10]) dm_timing_check(10);
always @(dm_in[11]) dm_timing_check(11);
always @(dm_in[12]) dm_timing_check(12);
always @(dm_in[13]) dm_timing_check(13);
always @(dm_in[14]) dm_timing_check(14);
always @(dm_in[15]) dm_timing_check(15);
task dq_timing_check;
input i;
reg [5:0] i;
begin
if (dqs_in_valid) begin
if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH)
$display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time);
if (check_dq_tdipw[i]) begin
if (dll_locked && ($time - tm_dq[i] < $rtoi(TDIPW*tck_avg)))
$display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW*tck_avg - $time);
end
end
check_dq_tdipw[i] <= 1'b0;
tm_dq[i] = $time;
end
endtask
always @(dq_in[ 0]) dq_timing_check( 0);
always @(dq_in[ 1]) dq_timing_check( 1);
always @(dq_in[ 2]) dq_timing_check( 2);
always @(dq_in[ 3]) dq_timing_check( 3);
always @(dq_in[ 4]) dq_timing_check( 4);
always @(dq_in[ 5]) dq_timing_check( 5);
always @(dq_in[ 6]) dq_timing_check( 6);
always @(dq_in[ 7]) dq_timing_check( 7);
always @(dq_in[ 8]) dq_timing_check( 8);
always @(dq_in[ 9]) dq_timing_check( 9);
always @(dq_in[10]) dq_timing_check(10);
always @(dq_in[11]) dq_timing_check(11);
always @(dq_in[12]) dq_timing_check(12);
always @(dq_in[13]) dq_timing_check(13);
always @(dq_in[14]) dq_timing_check(14);
always @(dq_in[15]) dq_timing_check(15);
always @(dq_in[16]) dq_timing_check(16);
always @(dq_in[17]) dq_timing_check(17);
always @(dq_in[18]) dq_timing_check(18);
always @(dq_in[19]) dq_timing_check(19);
always @(dq_in[20]) dq_timing_check(20);
always @(dq_in[21]) dq_timing_check(21);
always @(dq_in[22]) dq_timing_check(22);
always @(dq_in[23]) dq_timing_check(23);
always @(dq_in[24]) dq_timing_check(24);
always @(dq_in[25]) dq_timing_check(25);
always @(dq_in[26]) dq_timing_check(26);
always @(dq_in[27]) dq_timing_check(27);
always @(dq_in[28]) dq_timing_check(28);
always @(dq_in[29]) dq_timing_check(29);
always @(dq_in[30]) dq_timing_check(30);
always @(dq_in[31]) dq_timing_check(31);
always @(dq_in[32]) dq_timing_check(32);
always @(dq_in[33]) dq_timing_check(33);
always @(dq_in[34]) dq_timing_check(34);
always @(dq_in[35]) dq_timing_check(35);
always @(dq_in[36]) dq_timing_check(36);
always @(dq_in[37]) dq_timing_check(37);
always @(dq_in[38]) dq_timing_check(38);
always @(dq_in[39]) dq_timing_check(39);
always @(dq_in[40]) dq_timing_check(40);
always @(dq_in[41]) dq_timing_check(41);
always @(dq_in[42]) dq_timing_check(42);
always @(dq_in[43]) dq_timing_check(43);
always @(dq_in[44]) dq_timing_check(44);
always @(dq_in[45]) dq_timing_check(45);
always @(dq_in[46]) dq_timing_check(46);
always @(dq_in[47]) dq_timing_check(47);
always @(dq_in[48]) dq_timing_check(48);
always @(dq_in[49]) dq_timing_check(49);
always @(dq_in[50]) dq_timing_check(50);
always @(dq_in[51]) dq_timing_check(51);
always @(dq_in[52]) dq_timing_check(52);
always @(dq_in[53]) dq_timing_check(53);
always @(dq_in[54]) dq_timing_check(54);
always @(dq_in[55]) dq_timing_check(55);
always @(dq_in[56]) dq_timing_check(56);
always @(dq_in[57]) dq_timing_check(57);
always @(dq_in[58]) dq_timing_check(58);
always @(dq_in[59]) dq_timing_check(59);
always @(dq_in[60]) dq_timing_check(60);
always @(dq_in[61]) dq_timing_check(61);
always @(dq_in[62]) dq_timing_check(62);
always @(dq_in[63]) dq_timing_check(63);
task dqs_pos_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && ((wdqs_pos_cntr[i] < burst_length/2) || b2b_write) && (dqs_n_en || i<16)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if (check_write_preamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPRE*tck_avg))
$display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16);
end else if (check_write_postamble[i]) begin
if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg))
$display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16);
end else begin
if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg))
$display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
if ($time - tm_dm[i] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
if ((wdqs_pos_cntr[i] < burst_length/2) && !b2b_write) begin
wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1;
end else begin
wdqs_pos_cntr[i] <= 1;
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_preamble[i] <= 1'b0;
check_write_postamble[i] <= 1'b0;
check_write_dqs_low[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqss_pos[i] <= $time;
tm_dqs_pos[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0);
always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1);
always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2);
always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3);
always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4);
always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5);
always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6);
always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7);
always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8);
always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9);
always @(posedge dqs_in[10]) dqs_pos_timing_check(10);
always @(posedge dqs_in[11]) dqs_pos_timing_check(11);
always @(posedge dqs_in[12]) dqs_pos_timing_check(12);
always @(posedge dqs_in[13]) dqs_pos_timing_check(13);
always @(posedge dqs_in[14]) dqs_pos_timing_check(14);
always @(posedge dqs_in[15]) dqs_pos_timing_check(15);
always @(negedge dqs_in[16]) dqs_pos_timing_check(16);
always @(negedge dqs_in[17]) dqs_pos_timing_check(17);
always @(negedge dqs_in[18]) dqs_pos_timing_check(18);
always @(negedge dqs_in[19]) dqs_pos_timing_check(19);
always @(negedge dqs_in[20]) dqs_pos_timing_check(20);
always @(negedge dqs_in[21]) dqs_pos_timing_check(21);
always @(negedge dqs_in[22]) dqs_pos_timing_check(22);
always @(negedge dqs_in[23]) dqs_pos_timing_check(23);
always @(negedge dqs_in[24]) dqs_pos_timing_check(24);
always @(negedge dqs_in[25]) dqs_pos_timing_check(25);
always @(negedge dqs_in[26]) dqs_pos_timing_check(26);
always @(negedge dqs_in[27]) dqs_pos_timing_check(27);
always @(negedge dqs_in[28]) dqs_pos_timing_check(28);
always @(negedge dqs_in[29]) dqs_pos_timing_check(29);
always @(negedge dqs_in[30]) dqs_pos_timing_check(30);
always @(negedge dqs_in[31]) dqs_pos_timing_check(31);
task dqs_neg_timing_check;
input i;
reg [4:0] i;
reg [3:0] j;
begin
if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && (dqs_n_en || i < 16)) begin
if (dqs_in[i] ^ prev_dqs_in[i]) begin
if (dll_locked) begin
if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg))
$display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg))
$display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16);
end
if ($time - tm_dm[i] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i] + TDS - $time);
if (!dq_out_en) begin
for (j=0; j<`DQ_PER_DQS; j=j+1) begin
if ($time - tm_dq[i*`DQ_PER_DQS+j] < TDS)
$display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[i*`DQ_PER_DQS+j] + TDS - $time);
check_dq_tdipw[i*`DQ_PER_DQS+j] <= 1'b1;
end
end
check_dm_tdipw[i%16] <= 1'b1;
check_write_dqs_high[i] <= 1'b0;
tm_dqs[i%16] <= $time;
end else begin
$display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16);
end
end
tm_dqs_neg[i] = $time;
prev_dqs_in[i] <= dqs_in[i];
end
endtask
always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0);
always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1);
always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2);
always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3);
always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4);
always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5);
always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6);
always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7);
always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8);
always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9);
always @(negedge dqs_in[10]) dqs_neg_timing_check(10);
always @(negedge dqs_in[11]) dqs_neg_timing_check(11);
always @(negedge dqs_in[12]) dqs_neg_timing_check(12);
always @(negedge dqs_in[13]) dqs_neg_timing_check(13);
always @(negedge dqs_in[14]) dqs_neg_timing_check(14);
always @(negedge dqs_in[15]) dqs_neg_timing_check(15);
always @(posedge dqs_in[16]) dqs_neg_timing_check(16);
always @(posedge dqs_in[17]) dqs_neg_timing_check(17);
always @(posedge dqs_in[18]) dqs_neg_timing_check(18);
always @(posedge dqs_in[19]) dqs_neg_timing_check(19);
always @(posedge dqs_in[20]) dqs_neg_timing_check(20);
always @(posedge dqs_in[21]) dqs_neg_timing_check(21);
always @(posedge dqs_in[22]) dqs_neg_timing_check(22);
always @(posedge dqs_in[23]) dqs_neg_timing_check(23);
always @(posedge dqs_in[24]) dqs_neg_timing_check(24);
always @(posedge dqs_in[25]) dqs_neg_timing_check(25);
always @(posedge dqs_in[26]) dqs_neg_timing_check(26);
always @(posedge dqs_in[27]) dqs_neg_timing_check(27);
always @(posedge dqs_in[28]) dqs_neg_timing_check(28);
always @(posedge dqs_in[29]) dqs_neg_timing_check(29);
always @(posedge dqs_in[30]) dqs_neg_timing_check(30);
always @(posedge dqs_in[31]) dqs_neg_timing_check(31);
endmodule
|
// Copyright (c) 2000 Steve Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: First test for Procedural continuous assignment
module test;
//
// Define a procedural assignment based mux.
//
reg [1:0] sel;
reg [1:0] out, a,b,c,d;
reg error;
always @ (sel)
case (sel)
2'b00: assign out = a;
2'b01: assign out = b;
2'b10: assign out = c;
2'b11: assign out = d;
endcase
initial
begin
error = 0;
#1 ;
sel = 0;
a = 0;
#1;
if(out !== 2'b00)
begin
$display("FAILED - Procedural assignment out != 0 (1)");
error =1;
end
#1;
a = 1;
#1;
if(out !== 2'b01)
begin
$display("FAILED - Procedural assignment out != 1 (2)");
error =1;
end
if(error == 0)
$display("PASSED");
end
endmodule
|
module system (
input clk100,
output led1,
output led2,
output led3,
output led4,
input sw1_1,
input sw1_2,
input sw2_1,
input sw2_2,
input sw3,
input sw4,
output RAMWE_b,
output RAMOE_b,
output RAMCS_b,
output [17:0] ADR,
inout [15:0] DAT,
input rxd,
output txd);
// CLKSPEED is the main clock speed
parameter CLKSPEED = 50000000;
// BAUD is the desired serial baud rate
parameter BAUD = 115200;
// RAMSIZE is the size of the RAM address bus
parameter RAMSIZE = 12;
// CPU signals
wire clk;
wire [31:0] cpu_din;
wire [31:0] cpu_dout;
wire [31:0] ram_dout;
wire [31:0] ext_dout;
wire [15:0] uart_dout;
wire [19:0] address;
wire rnw;
wire vpa;
wire vda;
wire vio;
wire ramclken; // clken signal for a internal ram access
wire extclken; // clken signal for a external ram access
reg ramclken_old = 0;
wire cpuclken;
reg sw4_sync;
reg reset_b;
// Map the RAM everywhere in IO space (for performance)
wire uart_cs_b = !(vio);
// Map the RAM at both the bottom of memory (uart_cs_b takes priority)
wire ram_cs_b = !((vpa || vda) && (address[19:8] < 12'h00E));
// wire ram_cs_b = !((vpa || vda) && (|address[19:RAMSIZE] == 1'b0));
// Everywhere else is external RAM
wire ext_cs_b = !((vpa || vda) && (address[19:8] >= 12'h00E));
// wire ext_cs_b = !((vpa || vda) && (|address[19:RAMSIZE] == 1'b1));
// External RAM signals
wire [15:0] ext_data_in;
wire [15:0] ext_data_out;
wire ext_data_oe;
`ifdef simulate
assign ext_data_in = DAT;
assign DAT = ext_data_oe ? ext_data_out : 16'hZZZZ;
`else
SB_IO #(
.PIN_TYPE(6'b 1010_01),
) sram_data_pins [15:0] (
.PACKAGE_PIN(DAT),
.OUTPUT_ENABLE(ext_data_oe),
.D_OUT_0(ext_data_out),
.D_IN_0(ext_data_in),
);
`endif
// Data Multiplexor
assign cpu_din = uart_cs_b ? (ram_cs_b ? ext_dout : ram_dout) : {16'b0, uart_dout};
reg [1:0] clkdiv = 2'b00;
always @(posedge clk100)
begin
clkdiv <= clkdiv + 1;
end
assign clk = clkdiv[0];
// Reset generation
reg [9:0] pwr_up_reset_counter = 0; // hold reset low for ~1000 cycles
wire pwr_up_reset_b = &pwr_up_reset_counter;
always @(posedge clk)
begin
ramclken_old <= ramclken;
if (!pwr_up_reset_b)
pwr_up_reset_counter <= pwr_up_reset_counter + 1;
sw4_sync <= sw4;
reset_b <= sw4_sync & pwr_up_reset_b;
end
assign ramclken = !ramclken_old | ram_cs_b;
assign cpuclken = !reset_b | (ext_cs_b ? ramclken : extclken);
assign led1 = 0; // blue
assign led2 = 1; // green
assign led3 = !rxd; // yellow
assign led4 = !txd; // red
// The CPU
opc7cpu CPU
(
.din(cpu_din),
.clk(clk),
.reset_b(reset_b),
.int_b(2'b11),
.clken(cpuclken),
.vpa(vpa),
.vda(vda),
.vio(vio),
.dout(cpu_dout),
.address(address),
.rnw(rnw)
);
memory_controller #
(
.DSIZE(32),
.ASIZE(20)
)
MEMC
(
.clock (clk),
.reset_b (reset_b),
.ext_cs_b (ext_cs_b),
.cpu_rnw (rnw),
.cpu_clken (extclken),
.cpu_addr (address),
.cpu_dout (cpu_dout),
.ext_dout (ext_dout),
.ram_cs_b (RAMCS_b),
.ram_oe_b (RAMOE_b),
.ram_we_b (RAMWE_b),
.ram_data_in (ext_data_in),
.ram_data_out (ext_data_out),
.ram_data_oe (ext_data_oe),
.ram_addr (ADR)
);
// A block RAM - clocked off negative edge to mask output register
ram RAM
(
.din(cpu_dout),
.dout(ram_dout),
.address(address[RAMSIZE-1:0]),
.rnw(rnw),
.clk(clk),
.cs_b(ram_cs_b)
);
// A simple 115200 baud UART
uart #(CLKSPEED, BAUD) UART
(
.din(cpu_dout[15:0]),
.dout(uart_dout),
.a0(address[0]),
.rnw(rnw),
.clk(clk),
.reset_b(reset_b),
.cs_b(uart_cs_b),
.rxd(rxd),
.txd(txd)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_4_V
`define SKY130_FD_SC_LP__OR4BB_4_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4bb_4 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or4bb_4 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_4_V
|
//altera_mult_add ADDNSUB_MULTIPLIER_PIPELINE_ACLR1="ACLR0" ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1="CLOCK0" ADDNSUB_MULTIPLIER_REGISTER1="UNREGISTERED" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEDICATED_MULTIPLIER_CIRCUITRY="YES" DEVICE_FAMILY="Cyclone V" DSP_BLOCK_BALANCING="Auto" INPUT_REGISTER_A0="UNREGISTERED" INPUT_REGISTER_B0="UNREGISTERED" INPUT_SOURCE_A0="DATAA" INPUT_SOURCE_B0="DATAB" MULTIPLIER1_DIRECTION="ADD" MULTIPLIER_ACLR0="ACLR0" MULTIPLIER_REGISTER0="CLOCK0" NUMBER_OF_MULTIPLIERS=1 OUTPUT_REGISTER="UNREGISTERED" port_addnsub1="PORT_UNUSED" port_addnsub3="PORT_UNUSED" REPRESENTATION_A="UNSIGNED" REPRESENTATION_B="UNSIGNED" SELECTED_DEVICE_FAMILY="CYCLONEV" SIGNED_PIPELINE_ACLR_A="ACLR0" SIGNED_PIPELINE_ACLR_B="ACLR0" SIGNED_PIPELINE_REGISTER_A="CLOCK0" SIGNED_PIPELINE_REGISTER_B="CLOCK0" SIGNED_REGISTER_A="UNREGISTERED" SIGNED_REGISTER_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_RESULT=32 aclr0 clock0 dataa datab ena0 result
//VERSION_BEGIN 16.0 cbx_altera_mult_add 2016:04:20:18:35:29:SJ cbx_altera_mult_add_rtl 2016:04:20:18:35:29:SJ cbx_mgl 2016:04:20:19:36:45:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = altera_mult_add_rtl 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altera_mult_add_37p2
(
aclr0,
clock0,
dataa,
datab,
ena0,
result) /* synthesis synthesis_clearbox=1 */;
input aclr0;
input clock0;
input [15:0] dataa;
input [15:0] datab;
input ena0;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr0;
tri1 clock0;
tri0 [15:0] dataa;
tri0 [15:0] datab;
tri1 ena0;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] wire_altera_mult_add_rtl1_result;
altera_mult_add_rtl altera_mult_add_rtl1
(
.aclr0(aclr0),
.chainout_sat_overflow(),
.clock0(clock0),
.dataa(dataa),
.datab(datab),
.ena0(ena0),
.mult0_is_saturated(),
.mult1_is_saturated(),
.mult2_is_saturated(),
.mult3_is_saturated(),
.overflow(),
.result(wire_altera_mult_add_rtl1_result),
.scanouta(),
.scanoutb(),
.accum_sload(1'b0),
.aclr1(1'b0),
.aclr2(1'b0),
.aclr3(1'b0),
.addnsub1(1'b1),
.addnsub1_round(1'b0),
.addnsub3(1'b1),
.addnsub3_round(1'b0),
.chainin({1{1'b0}}),
.chainout_round(1'b0),
.chainout_saturate(1'b0),
.clock1(1'b1),
.clock2(1'b1),
.clock3(1'b1),
.coefsel0({3{1'b0}}),
.coefsel1({3{1'b0}}),
.coefsel2({3{1'b0}}),
.coefsel3({3{1'b0}}),
.datac({22{1'b0}}),
.ena1(1'b1),
.ena2(1'b1),
.ena3(1'b1),
.mult01_round(1'b0),
.mult01_saturation(1'b0),
.mult23_round(1'b0),
.mult23_saturation(1'b0),
.negate(1'b0),
.output_round(1'b0),
.output_saturate(1'b0),
.rotate(1'b0),
.scanina({16{1'b0}}),
.scaninb({16{1'b0}}),
.sclr0(1'b0),
.sclr1(1'b0),
.sclr2(1'b0),
.sclr3(1'b0),
.shift_right(1'b0),
.signa(1'b0),
.signb(1'b0),
.sload_accum(1'b0),
.sourcea({1{1'b0}}),
.sourceb({1{1'b0}}),
.zero_chainout(1'b0),
.zero_loopback(1'b0)
);
defparam
altera_mult_add_rtl1.accum_direction = "ADD",
altera_mult_add_rtl1.accum_sload_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_aclr = "NONE",
altera_mult_add_rtl1.accum_sload_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_latency_sclr = "NONE",
altera_mult_add_rtl1.accum_sload_register = "UNREGISTERED",
altera_mult_add_rtl1.accum_sload_sclr = "NONE",
altera_mult_add_rtl1.accumulator = "NO",
altera_mult_add_rtl1.adder1_rounding = "NO",
altera_mult_add_rtl1.adder3_rounding = "NO",
altera_mult_add_rtl1.addnsub1_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_pipeline_sclr = "NONE",
altera_mult_add_rtl1.addnsub1_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub1_round_sclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_pipeline_sclr = "NONE",
altera_mult_add_rtl1.addnsub3_round_register = "UNREGISTERED",
altera_mult_add_rtl1.addnsub3_round_sclr = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_aclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_latency_clock3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_latency_sclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_latency_sclr3 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.addnsub_multiplier_sclr1 = "NONE",
altera_mult_add_rtl1.addnsub_multiplier_sclr3 = "NONE",
altera_mult_add_rtl1.chainout_aclr = "NONE",
altera_mult_add_rtl1.chainout_adder = "NO",
altera_mult_add_rtl1.chainout_adder_direction = "ADD",
altera_mult_add_rtl1.chainout_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_output_sclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_pipeline_sclr = "NONE",
altera_mult_add_rtl1.chainout_round_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_round_sclr = "NONE",
altera_mult_add_rtl1.chainout_rounding = "NO",
altera_mult_add_rtl1.chainout_saturate_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_output_sclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_pipeline_sclr = "NONE",
altera_mult_add_rtl1.chainout_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.chainout_saturate_sclr = "NONE",
altera_mult_add_rtl1.chainout_saturation = "NO",
altera_mult_add_rtl1.chainout_sclr = "NONE",
altera_mult_add_rtl1.coef0_0 = 0,
altera_mult_add_rtl1.coef0_1 = 0,
altera_mult_add_rtl1.coef0_2 = 0,
altera_mult_add_rtl1.coef0_3 = 0,
altera_mult_add_rtl1.coef0_4 = 0,
altera_mult_add_rtl1.coef0_5 = 0,
altera_mult_add_rtl1.coef0_6 = 0,
altera_mult_add_rtl1.coef0_7 = 0,
altera_mult_add_rtl1.coef1_0 = 0,
altera_mult_add_rtl1.coef1_1 = 0,
altera_mult_add_rtl1.coef1_2 = 0,
altera_mult_add_rtl1.coef1_3 = 0,
altera_mult_add_rtl1.coef1_4 = 0,
altera_mult_add_rtl1.coef1_5 = 0,
altera_mult_add_rtl1.coef1_6 = 0,
altera_mult_add_rtl1.coef1_7 = 0,
altera_mult_add_rtl1.coef2_0 = 0,
altera_mult_add_rtl1.coef2_1 = 0,
altera_mult_add_rtl1.coef2_2 = 0,
altera_mult_add_rtl1.coef2_3 = 0,
altera_mult_add_rtl1.coef2_4 = 0,
altera_mult_add_rtl1.coef2_5 = 0,
altera_mult_add_rtl1.coef2_6 = 0,
altera_mult_add_rtl1.coef2_7 = 0,
altera_mult_add_rtl1.coef3_0 = 0,
altera_mult_add_rtl1.coef3_1 = 0,
altera_mult_add_rtl1.coef3_2 = 0,
altera_mult_add_rtl1.coef3_3 = 0,
altera_mult_add_rtl1.coef3_4 = 0,
altera_mult_add_rtl1.coef3_5 = 0,
altera_mult_add_rtl1.coef3_6 = 0,
altera_mult_add_rtl1.coef3_7 = 0,
altera_mult_add_rtl1.coefsel0_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel0_latency_sclr = "NONE",
altera_mult_add_rtl1.coefsel0_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel0_sclr = "NONE",
altera_mult_add_rtl1.coefsel1_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_latency_sclr = "NONE",
altera_mult_add_rtl1.coefsel1_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel1_sclr = "NONE",
altera_mult_add_rtl1.coefsel2_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_latency_sclr = "NONE",
altera_mult_add_rtl1.coefsel2_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel2_sclr = "NONE",
altera_mult_add_rtl1.coefsel3_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_aclr = "NONE",
altera_mult_add_rtl1.coefsel3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_latency_sclr = "NONE",
altera_mult_add_rtl1.coefsel3_register = "UNREGISTERED",
altera_mult_add_rtl1.coefsel3_sclr = "NONE",
altera_mult_add_rtl1.dedicated_multiplier_circuitry = "YES",
altera_mult_add_rtl1.double_accum = "NO",
altera_mult_add_rtl1.dsp_block_balancing = "Auto",
altera_mult_add_rtl1.extra_latency = 0,
altera_mult_add_rtl1.input_a0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a0_latency_sclr = "NONE",
altera_mult_add_rtl1.input_a1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a1_latency_sclr = "NONE",
altera_mult_add_rtl1.input_a2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a2_latency_sclr = "NONE",
altera_mult_add_rtl1.input_a3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_a3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_a3_latency_sclr = "NONE",
altera_mult_add_rtl1.input_aclr_a0 = "NONE",
altera_mult_add_rtl1.input_aclr_a1 = "NONE",
altera_mult_add_rtl1.input_aclr_a2 = "NONE",
altera_mult_add_rtl1.input_aclr_a3 = "NONE",
altera_mult_add_rtl1.input_aclr_b0 = "NONE",
altera_mult_add_rtl1.input_aclr_b1 = "NONE",
altera_mult_add_rtl1.input_aclr_b2 = "NONE",
altera_mult_add_rtl1.input_aclr_b3 = "NONE",
altera_mult_add_rtl1.input_aclr_c0 = "NONE",
altera_mult_add_rtl1.input_aclr_c1 = "NONE",
altera_mult_add_rtl1.input_aclr_c2 = "NONE",
altera_mult_add_rtl1.input_aclr_c3 = "NONE",
altera_mult_add_rtl1.input_b0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b0_latency_sclr = "NONE",
altera_mult_add_rtl1.input_b1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b1_latency_sclr = "NONE",
altera_mult_add_rtl1.input_b2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b2_latency_sclr = "NONE",
altera_mult_add_rtl1.input_b3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_b3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_b3_latency_sclr = "NONE",
altera_mult_add_rtl1.input_c0_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c0_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c0_latency_sclr = "NONE",
altera_mult_add_rtl1.input_c1_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c1_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c1_latency_sclr = "NONE",
altera_mult_add_rtl1.input_c2_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c2_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c2_latency_sclr = "NONE",
altera_mult_add_rtl1.input_c3_latency_aclr = "NONE",
altera_mult_add_rtl1.input_c3_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.input_c3_latency_sclr = "NONE",
altera_mult_add_rtl1.input_register_a0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_a3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_b3 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c0 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c1 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c2 = "UNREGISTERED",
altera_mult_add_rtl1.input_register_c3 = "UNREGISTERED",
altera_mult_add_rtl1.input_sclr_a0 = "NONE",
altera_mult_add_rtl1.input_sclr_a1 = "NONE",
altera_mult_add_rtl1.input_sclr_a2 = "NONE",
altera_mult_add_rtl1.input_sclr_a3 = "NONE",
altera_mult_add_rtl1.input_sclr_b0 = "NONE",
altera_mult_add_rtl1.input_sclr_b1 = "NONE",
altera_mult_add_rtl1.input_sclr_b2 = "NONE",
altera_mult_add_rtl1.input_sclr_b3 = "NONE",
altera_mult_add_rtl1.input_sclr_c0 = "NONE",
altera_mult_add_rtl1.input_sclr_c1 = "NONE",
altera_mult_add_rtl1.input_sclr_c2 = "NONE",
altera_mult_add_rtl1.input_sclr_c3 = "NONE",
altera_mult_add_rtl1.input_source_a0 = "DATAA",
altera_mult_add_rtl1.input_source_a1 = "DATAA",
altera_mult_add_rtl1.input_source_a2 = "DATAA",
altera_mult_add_rtl1.input_source_a3 = "DATAA",
altera_mult_add_rtl1.input_source_b0 = "DATAB",
altera_mult_add_rtl1.input_source_b1 = "DATAB",
altera_mult_add_rtl1.input_source_b2 = "DATAB",
altera_mult_add_rtl1.input_source_b3 = "DATAB",
altera_mult_add_rtl1.latency = 0,
altera_mult_add_rtl1.loadconst_control_aclr = "NONE",
altera_mult_add_rtl1.loadconst_control_register = "UNREGISTERED",
altera_mult_add_rtl1.loadconst_control_sclr = "NONE",
altera_mult_add_rtl1.loadconst_value = 64,
altera_mult_add_rtl1.mult01_round_aclr = "NONE",
altera_mult_add_rtl1.mult01_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_round_sclr = "NONE",
altera_mult_add_rtl1.mult01_saturation_aclr = "ACLR0",
altera_mult_add_rtl1.mult01_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult01_saturation_sclr = "ACLR0",
altera_mult_add_rtl1.mult23_round_aclr = "NONE",
altera_mult_add_rtl1.mult23_round_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_round_sclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_aclr = "NONE",
altera_mult_add_rtl1.mult23_saturation_register = "UNREGISTERED",
altera_mult_add_rtl1.mult23_saturation_sclr = "NONE",
altera_mult_add_rtl1.multiplier01_rounding = "NO",
altera_mult_add_rtl1.multiplier01_saturation = "NO",
altera_mult_add_rtl1.multiplier1_direction = "ADD",
altera_mult_add_rtl1.multiplier23_rounding = "NO",
altera_mult_add_rtl1.multiplier23_saturation = "NO",
altera_mult_add_rtl1.multiplier3_direction = "ADD",
altera_mult_add_rtl1.multiplier_aclr0 = "ACLR0",
altera_mult_add_rtl1.multiplier_aclr1 = "NONE",
altera_mult_add_rtl1.multiplier_aclr2 = "NONE",
altera_mult_add_rtl1.multiplier_aclr3 = "NONE",
altera_mult_add_rtl1.multiplier_register0 = "CLOCK0",
altera_mult_add_rtl1.multiplier_register1 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register2 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_register3 = "UNREGISTERED",
altera_mult_add_rtl1.multiplier_sclr0 = "NONE",
altera_mult_add_rtl1.multiplier_sclr1 = "NONE",
altera_mult_add_rtl1.multiplier_sclr2 = "NONE",
altera_mult_add_rtl1.multiplier_sclr3 = "NONE",
altera_mult_add_rtl1.negate_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_aclr = "NONE",
altera_mult_add_rtl1.negate_latency_clock = "UNREGISTERED",
altera_mult_add_rtl1.negate_latency_sclr = "NONE",
altera_mult_add_rtl1.negate_register = "UNREGISTERED",
altera_mult_add_rtl1.negate_sclr = "NONE",
altera_mult_add_rtl1.number_of_multipliers = 1,
altera_mult_add_rtl1.output_aclr = "NONE",
altera_mult_add_rtl1.output_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_round_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_pipeline_sclr = "NONE",
altera_mult_add_rtl1.output_round_register = "UNREGISTERED",
altera_mult_add_rtl1.output_round_sclr = "NONE",
altera_mult_add_rtl1.output_round_type = "NEAREST_INTEGER",
altera_mult_add_rtl1.output_rounding = "NO",
altera_mult_add_rtl1.output_saturate_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.output_saturate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_pipeline_sclr = "NONE",
altera_mult_add_rtl1.output_saturate_register = "UNREGISTERED",
altera_mult_add_rtl1.output_saturate_sclr = "NONE",
altera_mult_add_rtl1.output_saturate_type = "ASYMMETRIC",
altera_mult_add_rtl1.output_saturation = "NO",
altera_mult_add_rtl1.output_sclr = "NONE",
altera_mult_add_rtl1.port_addnsub1 = "PORT_UNUSED",
altera_mult_add_rtl1.port_addnsub3 = "PORT_UNUSED",
altera_mult_add_rtl1.port_chainout_sat_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_negate = "PORT_UNUSED",
altera_mult_add_rtl1.port_output_is_overflow = "PORT_UNUSED",
altera_mult_add_rtl1.port_signa = "PORT_UNUSED",
altera_mult_add_rtl1.port_signb = "PORT_UNUSED",
altera_mult_add_rtl1.preadder_direction_0 = "ADD",
altera_mult_add_rtl1.preadder_direction_1 = "ADD",
altera_mult_add_rtl1.preadder_direction_2 = "ADD",
altera_mult_add_rtl1.preadder_direction_3 = "ADD",
altera_mult_add_rtl1.preadder_mode = "SIMPLE",
altera_mult_add_rtl1.representation_a = "UNSIGNED",
altera_mult_add_rtl1.representation_b = "UNSIGNED",
altera_mult_add_rtl1.rotate_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_aclr = "NONE",
altera_mult_add_rtl1.rotate_output_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_output_sclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_aclr = "NONE",
altera_mult_add_rtl1.rotate_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_pipeline_sclr = "NONE",
altera_mult_add_rtl1.rotate_register = "UNREGISTERED",
altera_mult_add_rtl1.rotate_sclr = "NONE",
altera_mult_add_rtl1.scanouta_aclr = "NONE",
altera_mult_add_rtl1.scanouta_register = "UNREGISTERED",
altera_mult_add_rtl1.scanouta_sclr = "NONE",
altera_mult_add_rtl1.selected_device_family = "Cyclone V",
altera_mult_add_rtl1.shift_mode = "NO",
altera_mult_add_rtl1.shift_right_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_aclr = "NONE",
altera_mult_add_rtl1.shift_right_output_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_output_sclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_aclr = "NONE",
altera_mult_add_rtl1.shift_right_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_pipeline_sclr = "NONE",
altera_mult_add_rtl1.shift_right_register = "UNREGISTERED",
altera_mult_add_rtl1.shift_right_sclr = "NONE",
altera_mult_add_rtl1.signed_aclr_a = "NONE",
altera_mult_add_rtl1.signed_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_a = "NONE",
altera_mult_add_rtl1.signed_latency_aclr_b = "NONE",
altera_mult_add_rtl1.signed_latency_clock_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_latency_clock_b = "UNREGISTERED",
altera_mult_add_rtl1.signed_latency_sclr_a = "NONE",
altera_mult_add_rtl1.signed_latency_sclr_b = "NONE",
altera_mult_add_rtl1.signed_register_a = "UNREGISTERED",
altera_mult_add_rtl1.signed_register_b = "UNREGISTERED",
altera_mult_add_rtl1.signed_sclr_a = "NONE",
altera_mult_add_rtl1.signed_sclr_b = "NONE",
altera_mult_add_rtl1.systolic_aclr1 = "NONE",
altera_mult_add_rtl1.systolic_aclr3 = "NONE",
altera_mult_add_rtl1.systolic_delay1 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_delay3 = "UNREGISTERED",
altera_mult_add_rtl1.systolic_sclr1 = "NONE",
altera_mult_add_rtl1.systolic_sclr3 = "NONE",
altera_mult_add_rtl1.use_sload_accum_port = "NO",
altera_mult_add_rtl1.use_subnadd = "NO",
altera_mult_add_rtl1.width_a = 16,
altera_mult_add_rtl1.width_b = 16,
altera_mult_add_rtl1.width_c = 22,
altera_mult_add_rtl1.width_chainin = 1,
altera_mult_add_rtl1.width_coef = 18,
altera_mult_add_rtl1.width_msb = 17,
altera_mult_add_rtl1.width_result = 32,
altera_mult_add_rtl1.width_saturate_sign = 1,
altera_mult_add_rtl1.zero_chainout_output_aclr = "NONE",
altera_mult_add_rtl1.zero_chainout_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_chainout_output_sclr = "NONE",
altera_mult_add_rtl1.zero_loopback_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_output_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_output_sclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_aclr = "NONE",
altera_mult_add_rtl1.zero_loopback_pipeline_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_pipeline_sclr = "NONE",
altera_mult_add_rtl1.zero_loopback_register = "UNREGISTERED",
altera_mult_add_rtl1.zero_loopback_sclr = "NONE",
altera_mult_add_rtl1.lpm_type = "altera_mult_add_rtl";
assign
result = wire_altera_mult_add_rtl1_result;
endmodule //altera_mult_add_37p2
//VALID FILE
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: ccnu
// Engineer: Poyi Xiong
//
// Create Date: 01/12/2017 12:00:21 PM
// Design Name:
// Module Name: Clock_SR_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Clock_SR_tb #(parameter WIDTH=170, CNT_WIDTH=8)();
reg clk;
reg rst;
reg start;
reg [CNT_WIDTH-1:0] count;
wire clk_sr;
Clock_SR #(.WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH))
DUT1(
.clk(clk),
.rst(rst),
.start(start),
.count(count),
.clk_sr(clk_sr)
);
initial begin
$dumpfile("Clock_SR.dump");
$dumpvars(0, Clock_SR);
end
initial begin
clk=0;
forever #50 clk=~clk;
end
initial begin
rst=1'b1;
#200 rst=1'b0;
end
initial begin
count=8'b0;
#50 count=8'b0;
forever #100 count=count+1'b1;
end
initial begin
start=1'b0;
#250 start=1'b1;
#100 start=1'b0;
#17600 start=1'b1;
#100 start=1'b0;
end
endmodule
|
`timescale 1us/100ns
module framing_crc(
output reg [7:0] dout,
output next_indicator,
input [7:0] din,
input indicator,
input clk,
input reset_n
);
localparam CRC_INIT = 16'hffff;
localparam WAITING = 0,
SHR = 1,
PHR_PSDU = 2,
FCS = 3;
reg [1:0] state, next_state;
reg [6:0] count, next_count;
reg [15:0] crc, next_crc;
wire crc_in = din[(count[2:0])-:1] ^ crc[0];
always @(*) begin
case (state)
WAITING: begin
if (indicator)
next_state = SHR;
else
next_state = WAITING;
next_count = 0;
next_crc = CRC_INIT;
end
SHR: begin
if (count < 79) begin
next_state = SHR;
next_count = count + 1;
end else begin
next_state = PHR_PSDU;
next_count = 0;
end
next_crc = CRC_INIT;
end
PHR_PSDU: begin
next_state = (indicator ? FCS : PHR_PSDU);
next_count = (count == 7 ? 0 : count + 1);
next_crc = {crc_in,
crc[15:12],
crc[11] ^ crc_in,
crc[10:5],
crc[4] ^ crc_in,
crc[3:1]};
end
FCS: begin
if (count < 15) begin
next_state = FCS;
next_count = count + 1;
next_crc = crc;
end else begin
next_state = WAITING;
next_count = 0;
next_crc = CRC_INIT;
end
end
default: begin
next_state = WAITING;
next_count = 0;
next_crc = CRC_INIT;
end
endcase
end
// Update states.
always @(posedge clk or negedge reset_n) begin
if (~reset_n) begin
state <= WAITING;
count <= 0;
crc <= CRC_INIT;
end else begin
state <= next_state;
count <= next_count;
crc <= next_crc;
end
end
always @(*) begin
case (state)
SHR:
if (count < 64)
dout = 8'haa;
else if (count < 72)
dout = 8'h98;
else
dout = 8'hf3;
PHR_PSDU:
dout = din;
FCS:
dout = ~(count < 8 ? crc[7:0] : crc[15:8]);
default:
dout = 0;
endcase
end
assign next_indicator = (state == WAITING && indicator ||
state == FCS && count == 15);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR4BB_PP_BLACKBOX_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_SYMBOL_V
`define SKY130_FD_SC_LP__AND3_SYMBOL_V
/**
* and3: 3-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2009 www.xilinx.com
//
// XAPP xyz
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : dvi_encoder.v
//
// Description : dvi_encoder
//
// Date - revision : April 2009 - 1.0.0
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors makeand you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specificallydisclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does notwarrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designswill be
// uninterrupted or error free, or that defects in theDesigns
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results ofthe
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or forany
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on anytheory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure ofthe
// essential purpose of any limited remedies herein.
//
// Copyright © 2009 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 1ps
module dvi_encoder_top (
input wire pclk, // pixel clock
input wire pclkx2, // pixel clock x2
input wire pclkx10, // pixel clock x2
input wire serdesstrobe, // OSERDES2 serdesstrobe
input wire rstin, // reset
input wire [7:0] blue_din, // Blue data in
input wire [7:0] green_din, // Green data in
input wire [7:0] red_din, // Red data in
input wire hsync, // hsync data
input wire vsync, // vsync data
input wire de, // data enable
output wire [3:0] TMDS,
output wire [3:0] TMDSB);
wire [9:0] red ;
wire [9:0] green ;
wire [9:0] blue ;
wire [4:0] tmds_data0, tmds_data1, tmds_data2;
wire [2:0] tmdsint;
//
// Forward TMDS Clock Using OSERDES2 block
//
reg [4:0] tmdsclkint = 5'b00000;
reg toggle = 1'b0;
always @ (posedge pclkx2 or posedge rstin) begin
if (rstin)
toggle <= 1'b0;
else
toggle <= ~toggle;
end
always @ (posedge pclkx2) begin
if (toggle)
tmdsclkint <= 5'b11111;
else
tmdsclkint <= 5'b00000;
end
wire tmdsclk;
serdes_n_to_1 #(
.SF (5))
clkout (
.iob_data_out (tmdsclk),
.ioclk (pclkx10),
.serdesstrobe (serdesstrobe),
.gclk (pclkx2),
.reset (rstin),
.datain (tmdsclkint));
OBUFDS TMDS3 (.I(tmdsclk), .O(TMDS[3]), .OB(TMDSB[3])) ;// clock
//
// Forward TMDS Data: 3 channels
//
serdes_n_to_1 #(.SF(5)) oserdes0 (
.ioclk(pclkx10),
.serdesstrobe(serdesstrobe),
.reset(rstin),
.gclk(pclkx2),
.datain(tmds_data0),
.iob_data_out(tmdsint[0])) ;
serdes_n_to_1 #(.SF(5)) oserdes1 (
.ioclk(pclkx10),
.serdesstrobe(serdesstrobe),
.reset(rstin),
.gclk(pclkx2),
.datain(tmds_data1),
.iob_data_out(tmdsint[1])) ;
serdes_n_to_1 #(.SF(5)) oserdes2 (
.ioclk(pclkx10),
.serdesstrobe(serdesstrobe),
.reset(rstin),
.gclk(pclkx2),
.datain(tmds_data2),
.iob_data_out(tmdsint[2])) ;
OBUFDS TMDS0 (.I(tmdsint[0]), .O(TMDS[0]), .OB(TMDSB[0])) ;
OBUFDS TMDS1 (.I(tmdsint[1]), .O(TMDS[1]), .OB(TMDSB[1])) ;
OBUFDS TMDS2 (.I(tmdsint[2]), .O(TMDS[2]), .OB(TMDSB[2])) ;
encode encb (
.clkin (pclk),
.rstin (rstin),
.din (blue_din),
.c0 (hsync),
.c1 (vsync),
.de (de),
.dout (blue)) ;
encode encg (
.clkin (pclk),
.rstin (rstin),
.din (green_din),
.c0 (1'b0),
.c1 (1'b0),
.de (de),
.dout (green)) ;
encode encr (
.clkin (pclk),
.rstin (rstin),
.din (red_din),
.c0 (1'b0),
.c1 (1'b0),
.de (de),
.dout (red)) ;
wire [29:0] s_data = {red[9:5], green[9:5], blue[9:5],
red[4:0], green[4:0], blue[4:0]};
convert_30to15_fifo pixel2x (
.rst (rstin),
.clk (pclk),
.clkx2 (pclkx2),
.datain (s_data),
.dataout ({tmds_data2, tmds_data1, tmds_data0}));
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
*
* ExampleBlackParrotSystem.v
*
*/
`include "bsg_noc_links.vh"
module ExampleBlackParrotSystem
import bp_common_pkg::*;
import bp_be_pkg::*;
import bp_me_pkg::*;
import bsg_noc_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_unicore_no_l2_cfg// e_bp_softcore_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_core_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p)
`declare_bp_bedrock_mem_if_widths(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, cce)
// Tracing parameters
, parameter calc_trace_p = 0
, parameter cce_trace_p = 0
, parameter cmt_trace_p = 0
, parameter dram_trace_p = 0
, parameter npc_trace_p = 0
, parameter icache_trace_p = 0
, parameter dcache_trace_p = 0
, parameter vm_trace_p = 0
, parameter core_profile_p = 0
, parameter preload_mem_p = 0
, parameter load_nbf_p = 0
, parameter skip_init_p = 0
, parameter cosim_p = 0
, parameter cosim_cfg_file_p = "prog.cfg"
, parameter cosim_instr_p = 0
, parameter warmup_instr_p = 0
, parameter mem_zero_p = 1
, parameter mem_file_p = "prog.mem"
, parameter mem_cap_in_bytes_p = 2**28
, parameter [paddr_width_p-1:0] mem_offset_p = dram_base_addr_gp
// Number of elements in the fake BlackParrot memory
/*, parameter use_max_latency_p = 0
, parameter use_random_latency_p = 0
, parameter use_dramsim2_latency_p = 0
, parameter max_latency_p = 15
, parameter dram_clock_period_in_ps_p = `BP_SIM_CLK_PERIOD
, parameter dram_cfg_p = "dram_ch.ini"
, parameter dram_sys_cfg_p = "dram_sys.ini"
, parameter dram_capacity_p = 16384
*/
)
(input clk_i
, input reset_i
//Wishbone interface
, input [63:0] wbm_dat_i
, output [63:0] wbm_dat_o
, input wbm_ack_i
, input wbm_err_i
, input wbm_rty_i
, output [36:0] wbm_adr_o //TODO parametrize this
, output wbm_stb_o
, output wbm_cyc_o
, output [7:0] wbm_sel_o
, output wbm_we_o
, output [2:0] wbm_cti_o //TODO:
, output [1:0] wbm_bte_o
// , input [3:0] interrupts
);
`declare_bp_bedrock_mem_if(paddr_width_p, cce_block_width_p, lce_id_width_p, lce_assoc_p, cce)
initial begin
if (num_core_p > 1) begin
assert (cosim_p == 0) else $error("cosim_p not supported for num_core_p > 1");
end
end
logic [num_core_p-1:0] program_finish_lo;
logic cosim_finish_lo;
bp_bedrock_cce_mem_msg_s proc_mem_cmd_lo;
logic proc_mem_cmd_v_lo, proc_mem_cmd_ready_li;
bp_bedrock_cce_mem_msg_s proc_mem_resp_li;
logic proc_mem_resp_v_li, proc_mem_resp_yumi_lo;
bp_bedrock_cce_mem_msg_s proc_io_cmd_lo;
logic proc_io_cmd_v_lo, proc_io_cmd_ready_li;
bp_bedrock_cce_mem_msg_s proc_io_resp_li;
logic proc_io_resp_v_li, proc_io_resp_yumi_lo;
bp_bedrock_cce_mem_msg_s io_cmd_lo;
logic io_cmd_v_lo, io_cmd_ready_li;
bp_bedrock_cce_mem_msg_s io_resp_li;
logic io_resp_v_li, io_resp_yumi_lo;
bp_bedrock_cce_mem_msg_s nbf_cmd_lo;
logic nbf_cmd_v_lo, nbf_cmd_yumi_li;
bp_bedrock_cce_mem_msg_s nbf_resp_li;
logic nbf_resp_v_li, nbf_resp_ready_lo;
bp_bedrock_cce_mem_msg_s cfg_cmd_lo;
logic cfg_cmd_v_lo, cfg_cmd_yumi_li;
bp_bedrock_cce_mem_msg_s cfg_resp_li;
logic cfg_resp_v_li, cfg_resp_ready_lo;
bp_bedrock_cce_mem_msg_s load_cmd_lo;
logic load_cmd_v_lo, load_cmd_yumi_li;
bp_bedrock_cce_mem_msg_s load_resp_li;
logic load_resp_v_li, load_resp_ready_lo;
bp_unicore_lite
#(.bp_params_p(bp_params_p))
softcore
(.clk_i(clk_i)
,.reset_i(reset_i)
,.io_cmd_o(proc_io_cmd_lo)
,.io_cmd_v_o(proc_io_cmd_v_lo)
,.io_cmd_ready_and_i(proc_io_cmd_ready_li)
,.io_resp_i(proc_io_resp_li)
,.io_resp_v_i(proc_io_resp_v_li)
,.io_resp_yumi_o(proc_io_resp_yumi_lo)
,.io_cmd_i(load_cmd_lo)
,.io_cmd_v_i(load_cmd_v_lo)
,.io_cmd_yumi_o(load_cmd_yumi_li)
,.io_resp_o(load_resp_li)
,.io_resp_v_o(load_resp_v_li)
,.io_resp_ready_and_i(load_resp_ready_lo)
,.mem_cmd_o(proc_mem_cmd_lo)
,.mem_cmd_v_o(proc_mem_cmd_v_lo)
,.mem_cmd_ready_and_i(proc_mem_cmd_ready_li)
,.mem_resp_i(proc_mem_resp_li)
,.mem_resp_v_i(proc_mem_resp_v_li)
,.mem_resp_yumi_o(proc_mem_resp_yumi_lo)
);
bp2wb_convertor
#(.bp_params_p(bp_params_p))
bp2wb
(.clk_i(clk_i)
,.reset_i(reset_i)
,.mem_cmd_i(proc_mem_cmd_lo)
,.mem_cmd_v_i(proc_mem_cmd_ready_li & proc_mem_cmd_v_lo)
,.mem_cmd_ready_o(proc_mem_cmd_ready_li)
,.mem_resp_o(proc_mem_resp_li)
,.mem_resp_v_o(proc_mem_resp_v_li)
,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
,.dat_i(wbm_dat_i)
,.dat_o(wbm_dat_o)
,.ack_i(wbm_ack_i)
,.adr_o(wbm_adr_o)
,.stb_o(wbm_stb_o)
,.cyc_o(wbm_cyc_o)
,.sel_o(wbm_sel_o )
,.we_o(wbm_we_o)
,.cti_o(wbm_cti_o)
,.bte_o(wbm_bte_o )
// ,.rty_i(wbm_rty_i)
,.err_i(wbm_err_i)
);
assign proc_io_cmd_ready_li = 1;//TODO: make sure this is necessary
logic nbf_done_lo, cfg_done_lo;
if (load_nbf_p)
begin : nbf
bp_nonsynth_nbf_loader
#(.bp_params_p(bp_params_p))
nbf_loader
(.clk_i(clk_i)
,.reset_i(reset_i | ~cfg_done_lo)
,.lce_id_i(lce_id_width_p'('b10))
,.io_cmd_o(nbf_cmd_lo)
,.io_cmd_v_o(nbf_cmd_v_lo)
,.io_cmd_yumi_i(nbf_cmd_yumi_li)
,.io_resp_i(nbf_resp_li)
,.io_resp_v_i(nbf_resp_v_li)
,.io_resp_ready_and_o(nbf_resp_ready_lo)
,.done_o(nbf_done_lo)
);
end
else
begin : no_nbf
assign nbf_resp_ready_lo = 1'b1;
assign nbf_cmd_v_lo = '0;
assign nbf_cmd_lo = '0;
assign nbf_done_lo = 1'b1;
end
localparam cce_instr_ram_addr_width_lp = `BSG_SAFE_CLOG2(num_cce_instr_ram_els_p);
bp_cce_mmio_cfg_loader
#(.bp_params_p(bp_params_p)
,.inst_width_p($bits(bp_cce_inst_s))
,.inst_ram_addr_width_p(cce_instr_ram_addr_width_lp)
,.inst_ram_els_p(num_cce_instr_ram_els_p)
,.skip_ram_init_p(skip_init_p)
,.clear_freeze_p(!load_nbf_p)
,.cce_ucode_filename_p("/tmp/cce_ucode.mem")
)
cfg_loader
(.clk_i(clk_i)
,.reset_i(reset_i)
,.lce_id_i(lce_id_width_p'('b10))
,.io_cmd_o(cfg_cmd_lo)
,.io_cmd_v_o(cfg_cmd_v_lo)
,.io_cmd_yumi_i(cfg_cmd_yumi_li)
,.io_resp_i(cfg_resp_li)
,.io_resp_v_i(cfg_resp_v_li)
,.io_resp_ready_o(cfg_resp_ready_lo)
,.done_o(cfg_done_lo)
);
// CFG and NBF are mutex, so we can just use fixed arbitration here
always_comb
if (~cfg_done_lo)
begin
load_cmd_lo = cfg_cmd_lo;
load_cmd_v_lo = cfg_cmd_v_lo;
nbf_cmd_yumi_li = '0;
cfg_cmd_yumi_li = load_cmd_yumi_li;
load_resp_ready_lo = cfg_resp_ready_lo;
nbf_resp_li = '0;
nbf_resp_v_li = '0;
cfg_resp_li = load_resp_li;
cfg_resp_v_li = load_resp_v_li;
end
else
begin
load_cmd_lo = nbf_cmd_lo;
load_cmd_v_lo = nbf_cmd_v_lo;
nbf_cmd_yumi_li = load_cmd_yumi_li;
cfg_cmd_yumi_li = '0;
load_resp_ready_lo = nbf_resp_ready_lo;
nbf_resp_li = load_resp_li;
nbf_resp_v_li = load_resp_v_li;
cfg_resp_li = '0;
cfg_resp_v_li = '0;
end
/*bp_nonsynth_host
#(.bp_params_p(bp_params_p))
host
(.clk_i(clk_i)
,.reset_i(reset_i)
,.io_cmd_i(proc_io_cmd_lo)
,.io_cmd_v_i(proc_io_cmd_v_lo & proc_io_cmd_ready_li)
,.io_cmd_ready_o(proc_io_cmd_ready_li)
,.io_resp_o(proc_io_resp_li)
,.io_resp_v_o(proc_io_resp_v_li)
,.io_resp_yumi_i(proc_io_resp_yumi_lo)
,.program_finish_o(program_finish_lo)
);
*/
/*bind bp_be_top
bp_nonsynth_commit_tracer
#(.bp_params_p(bp_params_p))
commit_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.cmt_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i('0)
,.decode_i(be_calculator.reservation_n.decode)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.commit_pc_i(be_calculator.commit_pkt.pc)
,.commit_instr_i(be_calculator.commit_pkt.instr)
,.rd_w_v_i(be_checker.scheduler.wb_pkt.rd_w_v)
,.rd_addr_i(be_checker.scheduler.wb_pkt.rd_addr)
,.rd_data_i(be_checker.scheduler.wb_pkt.rd_data)
);*/
/* if (num_core_p == 1)
begin : cosim
bind bp_be_top
bp_nonsynth_cosim
#(.bp_params_p(bp_params_p))
cosim
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.en_i(ExampleBlackParrotSystem.cosim_p == 1)
,.cosim_instr_i(ExampleBlackParrotSystem.cosim_instr_p)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
// Want to pass config file as a parameter, but cannot in Verilator 4.025
// Parameter-resolved constants must not use dotted references
,.config_file_i(ExampleBlackParrotSystem.cosim_cfg_file_p)
,.decode_i(be_calculator.reservation_n.decode)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.commit_pc_i(be_calculator.commit_pkt.pc)
,.commit_instr_i(be_calculator.commit_pkt.instr)
,.rd_w_v_i(be_checker.scheduler.wb_pkt.rd_w_v)
,.rd_addr_i(be_checker.scheduler.wb_pkt.rd_addr)
,.rd_data_i(be_checker.scheduler.wb_pkt.rd_data)
,.interrupt_v_i(be_mem.csr.trap_pkt_cast_o._interrupt)
,.cause_i(be_mem.csr.trap_pkt_cast_o.cause)
,.finish_o(ExampleBlackParrotSystem.cosim_finish_lo)
);
end
else
begin : no_cosim*/
assign cosim_finish_lo = '0;
// end
/*bind bp_be_top
bp_be_nonsynth_perf
#(.bp_params_p(bp_params_p))
perf
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.warmup_instr_i(ExampleBlackParrotSystem.warmup_instr_p)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.commit_v_i(be_calculator.commit_pkt.instret)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo | ExampleBlackParrotSystem.cosim_finish_lo)
);
*/
/* bind bp_be_top
bp_nonsynth_watchdog
#(.bp_params_p(bp_params_p)
,.timeout_cycles_p(100000)
,.heartbeat_instr_p(100000)
)
watchdog
(.clk_i(clk_i)
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.npc_i(be_checker.director.npc_r)
,.instret_i(be_calculator.commit_pkt.instret)
);
*/
/* bind bp_be_director
bp_be_nonsynth_npc_tracer
#(.bp_params_p(bp_params_p))
npc_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.npc_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.npc_w_v(npc_w_v)
,.npc_n(npc_n)
,.npc_r(npc_r)
,.expected_npc_o(expected_npc_o)
,.fe_cmd_i(fe_cmd)
,.fe_cmd_v(fe_cmd_v)
,.commit_pkt_i(commit_pkt)
);
*/
/* bind bp_be_dcache
bp_nonsynth_cache_tracer
#(.bp_params_p(bp_params_p)
,.assoc_p(dcache_assoc_p)
,.sets_p(dcache_sets_p)
,.block_width_p(dcache_block_width_p)
,.trace_file_p("dcache"))
dcache_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.dcache_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.v_tl_r(v_tl_r)
,.v_tv_r(v_tv_r)
,.addr_tv_r(paddr_tv_r)
,.lr_miss_tv(lr_miss_tv)
,.sc_op_tv_r(sc_op_tv_r)
,.sc_success(sc_success)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_o(cache_req_o)
,.cache_req_metadata_o(cache_req_metadata_o)
,.cache_req_metadata_v_o(cache_req_metadata_v_o)
,.cache_req_complete_i(cache_req_complete_i)
,.v_o(v_o)
,.load_data(data_o)
,.cache_miss_o(dcache_miss_o)
,.wt_req(wt_req)
,.store_data(data_tv_r)
,.data_mem_pkt_v_i(data_mem_pkt_v_i)
,.data_mem_pkt_i(data_mem_pkt_i)
,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o)
,.tag_mem_pkt_v_i(tag_mem_pkt_v_i)
,.tag_mem_pkt_i(tag_mem_pkt_i)
,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o)
,.stat_mem_pkt_v_i(stat_mem_pkt_v_i)
,.stat_mem_pkt_i(stat_mem_pkt_i)
,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o)
);
*/
/* bind bp_fe_icache
bp_nonsynth_cache_tracer
#(.bp_params_p(bp_params_p)
,.assoc_p(icache_assoc_p)
,.sets_p(icache_sets_p)
,.block_width_p(icache_block_width_p)
,.trace_file_p("icache"))
icache_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.icache_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.v_tl_r(v_tl_r)
,.v_tv_r(v_tv_r)
,.addr_tv_r(addr_tv_r)
,.lr_miss_tv(1'b0)
,.sc_op_tv_r(1'b0)
,.sc_success(1'b0)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_o(cache_req_o)
,.cache_req_metadata_o(cache_req_metadata_o)
,.cache_req_metadata_v_o(cache_req_metadata_v_o)
,.cache_req_complete_i(cache_req_complete_i)
,.v_o(data_v_o)
,.load_data(dword_width_p'(data_o))
,.cache_miss_o(miss_o)
,.wt_req()
,.store_data(dword_width_p'(0))
,.data_mem_pkt_v_i(data_mem_pkt_v_i)
,.data_mem_pkt_i(data_mem_pkt_i)
,.data_mem_pkt_yumi_o(data_mem_pkt_yumi_o)
,.tag_mem_pkt_v_i(tag_mem_pkt_v_i)
,.tag_mem_pkt_i(tag_mem_pkt_i)
,.tag_mem_pkt_yumi_o(tag_mem_pkt_yumi_o)
,.stat_mem_pkt_v_i(stat_mem_pkt_v_i)
,.stat_mem_pkt_i(stat_mem_pkt_i)
,.stat_mem_pkt_yumi_o(stat_mem_pkt_yumi_o)
);
*/
/* bind bp_core_minimal
bp_be_nonsynth_vm_tracer
#(.bp_params_p(bp_params_p))
vm_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.vm_trace_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.itlb_clear_i(fe.mem.itlb.flush_i)
,.itlb_fill_v_i(fe.mem.itlb.v_i & fe.mem.itlb.w_i)
,.itlb_vtag_i(fe.mem.itlb.vtag_i)
,.itlb_entry_i(fe.mem.itlb.entry_i)
,.dtlb_clear_i(be.be_mem.dtlb.flush_i)
,.dtlb_fill_v_i(be.be_mem.dtlb.v_i & be.be_mem.dtlb.w_i)
,.dtlb_vtag_i(be.be_mem.dtlb.vtag_i)
,.dtlb_entry_i(be.be_mem.dtlb.entry_i)
);
*/
bp_mem_nonsynth_tracer
#(.bp_params_p(bp_params_p))
bp_mem_tracer
(.clk_i(clk_i & (ExampleBlackParrotSystem.dram_trace_p == 1))
,.reset_i(reset_i)
,.mem_cmd_i(proc_mem_cmd_lo)
,.mem_cmd_v_i(proc_mem_cmd_v_lo & proc_mem_cmd_ready_li)
,.mem_cmd_ready_and_i(proc_mem_cmd_ready_li)
,.mem_resp_i(proc_mem_resp_li)
,.mem_resp_v_i(proc_mem_resp_v_li)
,.mem_resp_yumi_i(proc_mem_resp_yumi_lo)
);
/* bind bp_core_minimal
bp_nonsynth_core_profiler
#(.bp_params_p(bp_params_p))
core_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.fe_wait_stall(fe.pc_gen.is_wait)
,.fe_queue_stall(~fe.pc_gen.fe_queue_ready_i)
,.itlb_miss(fe.mem.itlb_miss_r)
,.icache_miss(~fe.mem.icache.vaddr_ready_o | fe.pc_gen.icache_miss)
,.icache_fence(fe.mem.icache.fencei_req)
,.branch_override(fe.pc_gen.ovr_taken & ~fe.pc_gen.ovr_ret)
,.ret_override(fe.pc_gen.ovr_ret)
,.fe_cmd(fe.pc_gen.fe_cmd_yumi_o & ~fe.pc_gen.attaboy_v)
,.mispredict(be.be_checker.director.npc_mismatch_v)
,.target(be.be_checker.director.isd_status.isd_pc)
,.dtlb_miss(be.be_mem.dtlb_miss_r)
,.dcache_miss(~be.be_mem.dcache.ready_o)
,.long_haz(be.be_checker.detector.long_haz_v)
,.exception(be.be_checker.director.trap_pkt.exception)
,.eret(be.be_checker.director.trap_pkt.eret)
,._interrupt(be.be_checker.director.trap_pkt._interrupt)
,.control_haz(be.be_checker.detector.control_haz_v)
,.data_haz(be.be_checker.detector.data_haz_v)
,.load_dep((be.be_checker.detector.dep_status_li[0].mem_iwb_v
| be.be_checker.detector.dep_status_li[1].mem_iwb_v
) & be.be_checker.detector.data_haz_v
)
,.mul_dep((be.be_checker.detector.dep_status_li[0].mul_iwb_v
| be.be_checker.detector.dep_status_li[1].mul_iwb_v
| be.be_checker.detector.dep_status_li[2].mul_iwb_v
) & be.be_checker.detector.data_haz_v
)
,.struct_haz(be.be_checker.detector.struct_haz_v)
,.reservation(be.be_calculator.reservation_n)
,.commit_pkt(be.be_calculator.commit_pkt)
,.trap_pkt(be.be_mem.csr.trap_pkt_o)
);
*/
/* bind bp_core_minimal
bp_nonsynth_pc_profiler
#(.bp_params_p(bp_params_p))
pc_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(be.be_checker.scheduler.int_regfile.cfg_bus.freeze)
,.mhartid_i(be.be_checker.scheduler.int_regfile.cfg_bus.core_id)
,.commit_pkt(be.be_calculator.commit_pkt)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
);
*/
/* bind bp_be_director
bp_nonsynth_branch_profiler
#(.bp_params_p(bp_params_p))
pc_profiler
(.clk_i(clk_i & (ExampleBlackParrotSystem.core_profile_p == 1))
,.reset_i(reset_i)
,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)
,.fe_cmd_o(fe_cmd_o)
,.fe_cmd_v_o(fe_cmd_v_o)
,.fe_cmd_ready_i(fe_cmd_ready_i)
,.commit_v_i(commit_pkt.instret)
,.program_finish_i(ExampleBlackParrotSystem.program_finish_lo)
);
*/
/* bp_nonsynth_if_verif
#(.bp_params_p(bp_params_p))
if_verif
();
*/
endmodule
|
/*
* File: pippo_div_uu.v
* Project: pippo
* Designer:
* Mainteiner:
* Checker:
* Description: implmentation of 64/32 divider using non-restoring algorithm
Detailed algorithm see [Computer Arithmetic - Algorithms and Hardware designs] chapter 13
* Task.II
* optimize the implementation: reusing the pipelined register and logic to reduce size
*/
module pippo_div_uu(
clk, ena,
z, d, q, s,
div0, ovf
);
//
// parameters
//
parameter z_width = 64;
parameter d_width = z_width /2;
//
// inputs & outputs
//
input clk;
input ena;
input [z_width -1:0] z; // divident
input [d_width -1:0] d; // divisor
output [d_width -1:0] q; // quotient
output [d_width -1:0] s; // remainder
output div0;
output ovf;
//
//
//
reg [d_width-1:0] q;
reg [d_width-1:0] s;
reg div0;
reg ovf;
//
// functions
//
// temporal remainder
function [z_width:0] gen_s;
input [z_width:0] si;
input [z_width:0] di;
begin
if(si[z_width])
gen_s = {si[z_width-1:0], 1'b0} + di;
else
gen_s = {si[z_width-1:0], 1'b0} - di;
end
endfunction
// generate 1-bit quotient per stage
function [d_width-1:0] gen_q;
input [d_width-1:0] qi;
input [z_width:0] si;
begin
gen_q = {qi[d_width-2:0], ~si[z_width]};
end
endfunction
// last quotient
function [d_width-1:0] assign_s;
input [z_width:0] si;
input [z_width:0] di;
reg [z_width:0] tmp;
begin
if(si[z_width])
tmp = si + di;
else
tmp = si;
assign_s = tmp[z_width-1:z_width-d_width];
end
endfunction
//
// divide
//
reg [d_width-1:0] q_pipe [d_width-1:0];
reg [z_width:0] s_pipe [d_width:0];
reg [z_width:0] d_pipe [d_width:0];
reg [d_width:0] div0_pipe, ovf_pipe;
integer n0, n1, n2, n3;
// generate divisor (d) pipe
always @(d)
d_pipe[0] <= {1'b0, d, {(z_width-d_width){1'b0}} };
always @(posedge clk)
if(ena)
for(n0=1; n0 <= d_width; n0=n0+1)
d_pipe[n0] <= d_pipe[n0-1];
// generate internal remainder pipe
always @(z)
s_pipe[0] <= z;
always @(posedge clk)
if(ena)
for(n1=1; n1 <= d_width; n1=n1+1)
s_pipe[n1] <= gen_s(s_pipe[n1-1], d_pipe[n1-1]);
// generate quotient pipe
always @(posedge clk)
q_pipe[0] <= 0;
always @(posedge clk)
if(ena)
for(n2=1; n2 < d_width; n2=n2+1)
q_pipe[n2] <= gen_q(q_pipe[n2-1], s_pipe[n2]);
//
// divider results
//
always @(posedge clk)
if(ena)
q <= gen_q(q_pipe[d_width-1], s_pipe[d_width]);
always @(posedge clk)
if(ena)
s <= assign_s(s_pipe[d_width], d_pipe[d_width]);
//
// flags (divide_by_zero, overflow)
//
always @(z or d)
begin
// ovf_pipe[0] <= !(z[z_width-1:d_width] < d);
ovf_pipe[0] <= ~|d; // [TBD]there is no need to check overflow, coz the high part bits is just signed-extend
div0_pipe[0] <= ~|d;
end
always @(posedge clk)
if(ena)
for(n3=1; n3 <= d_width; n3=n3+1)
begin
ovf_pipe[n3] <= ovf_pipe[n3-1];
div0_pipe[n3] <= div0_pipe[n3-1];
end
always @(posedge clk)
if(ena)
ovf <= ovf_pipe[d_width];
always @(posedge clk)
if(ena)
div0 <= div0_pipe[d_width];
endmodule
|
//
// Copyright (c) 2000 Steve Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// force3.17A - Template 1 - force reg_lvalue = constant.
//
module test ;
reg [3:0] val1;
reg [3:0] val2;
initial
begin
val2 = 0;
#50 ;
if(val2 !== 4'b1010)
$display("FAILED");
else
$display("PASSED");
end
initial
begin
#20;
force val2 = 4'b1010;
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Create tags for the non-posted packet generators.
// Uses a simple 5-bit counter which rolls over
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tag_generator(
input clk,
input rst,
output reg np_tag_gnt,
input np_tag_inc,
output [7:0] tag_value,
input [31:0] completion_pending);
reg rst_reg;
reg [4:0] tag_value_i;
always@(posedge clk) rst_reg <= rst;
//check to see if the tag is already in use
//assert the grant signal if it is not
always@(posedge clk)begin
if(completion_pending[tag_value_i[4:0]])
np_tag_gnt <= 1'b0;
else
np_tag_gnt <= 1'b1;
end
assign tag_value[7:0] = {3'b000,tag_value_i[4:0]};
//tag generator is simply a counter with enable
always@(posedge clk)begin
if(rst_reg)begin
tag_value_i[4:0] <= 5'b00000;
end else if(np_tag_inc)begin
tag_value_i <= tag_value_i + 1;
end
end
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2018 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file dec_table.v when simulating
// the core, dec_table. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module dec_table(
clka,
addra,
douta
);
input clka;
input [7 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan3"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("dec_table.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan3")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ICACHE.v
// Version: 1.0
// Date: 30 May 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// ICACHE the instruction cache of M32632
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module ICACHE( BCLK, MCLK, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR,
KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR, WADDR,
WCTRL, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV,
DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM );
input BCLK;
input MCLK;
input MDONE;
input BRESET;
input READ_I;
input IO_READY;
input PSR_USER;
input DATA_HOLD;
input PTB_WR;
input PTB_SEL;
input DRAM_WR;
input KDET;
input HOLD;
input [1:0] CFG;
input [31:0] DRAM_Q;
input [1:0] CINVAL;
input [1:0] IC_SIGS;
input [31:0] IO_Q;
input [1:0] IVAR;
input [27:4] KOLLI_A;
input [3:0] MCR_FLAGS;
input [23:0] MMU_DIN;
input [31:0] VADR;
input [11:2] WADDR;
input [2:0] WCTRL;
input ENA_HK;
input ENDRAM;
output IO_RD;
output DRAM_ACC;
output INIT_RUN;
output PROT_ERROR;
output ACC_OK;
output IC_PREQ;
output KOLLISION;
output STOP_CINV;
output [31:0] IC_DQ;
output [31:12] IC_VA;
output [3:0] ICTODC;
output reg [27:0] DRAM_A;
output reg [31:0] IO_A;
reg [31:0] VADR_R;
reg [31:0] CAPDAT;
reg [31:0] DFFE_IOR;
reg HOLD_ON;
reg DFF_HDFF1;
reg DFF_IRD_REG;
wire [4:0] A_CV;
wire ACOK;
wire [4:0] ACV;
wire AUX_DAT;
wire CA_HIT;
wire CA_SET;
wire CUPDATE;
wire [23:0] D_CV;
wire HIT_ALL;
wire INIT_CA_RUN;
wire IO_ACC;
wire KILL;
wire NEW_PTB;
wire PTB_ONE;
wire [31:12] RADR;
wire READ;
wire RUN_ICRD;
wire STOP_ICRD;
wire [23:0] UPCD;
wire [23:0] UPDATE_C;
wire [31:0] UPDATE_M;
wire USE_CA;
wire USER;
wire [11:7] V_ADR;
wire WE_CV;
wire WEMV;
wire WRCRAM0;
wire WRCRAM1;
wire WRSET0;
wire WRSET1;
wire WRITE;
wire [11:7] KILLADR;
wire AUX_ALT;
wire VIRT_A;
wire CI;
wire MMU_HIT;
wire LD_DRAM_A;
wire IO_SPACE;
wire LAST_MUX;
wire VIRTUELL;
wire NEW_PTB_RUN;
wire [31:0] SET_DAT;
wire [31:0] ALT_DAT;
wire [31:0] DAT_MV;
wire [3:0] RADR_MV;
wire [3:0] WADR_MV;
wire [23:0] NEWCVAL;
wire KILL_C,KILL_K;
wire RMW;
// +++++++++++++++++++ Memories ++++++++++++++++++++
reg [31:0] DATA0 [0:1023]; // Data Set 0 : 4 kBytes
reg [31:0] SET_DAT0;
reg [31:0] DATA1 [0:1023]; // Data Set 1 : 4 kBytes
reg [31:0] SET_DAT1;
reg [15:0] TAGSET_0 [0:255]; // Tag Set for Data Set 0 : 256 entries of 16 bits
reg [15:0] TAG0;
reg [15:0] TAGSET_1 [0:255]; // Tag Set for Data Set 1 : 256 entries of 16 bits
reg [15:0] TAG1;
reg [23:0] CA_VALID [0:31]; // Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
reg [23:0] CVALID;
reg [35:0] MMU_TAGS [0:255]; // Tag Set for MMU : 256 entries of 36 bits
reg [35:0] MMU_Q;
reg [31:0] MMU_VALID [0:15]; // Valid bits for MMU Tag Set : 16 entries of 32 bits
reg [31:0] MVALID;
reg [15:0] KTAGSET_0 [0:255]; // Kollision Tag Set for Data Set 0 : 256 entries of 16 bits
reg [15:0] KTAG0;
reg [15:0] KTAGSET_1 [0:255]; // Kollision Tag Set for Data Set 1 : 256 entries of 16 bits
reg [15:0] KTAG1;
reg [23:0] KCA_VALID [0:31]; // Kollision Valid bits for Data Set 0 and 1 : 32 entries of 24 bits
reg [23:0] KCVALID;
assign READ = READ_I & ~HOLD_ON & RUN_ICRD;
assign WRITE = 1'b0;
assign RMW = 1'b0;
assign ALT_DAT = AUX_ALT ? DFFE_IOR : CAPDAT ;
assign RADR = VIRT_A ? MMU_Q[19:0] : VADR_R[31:12] ;
assign V_ADR = STOP_ICRD ? KILLADR : VADR[11:7] ;
assign ACV = STOP_ICRD ? KILLADR : A_CV ;
assign UPCD = STOP_ICRD ? NEWCVAL : UPDATE_C ;
assign IC_DQ = LAST_MUX ? ALT_DAT : SET_DAT ;
assign SET_DAT = CA_SET ? SET_DAT1 : SET_DAT0 ;
assign KILL = KILL_C | KILL_K;
assign IC_VA = VADR_R[31:12];
assign VIRT_A = ~CINVAL[0] & VIRTUELL;
assign ACC_OK = HOLD_ON | ACOK;
assign USER = ~MCR_FLAGS[3] & PSR_USER;
assign AUX_ALT = HOLD_ON | DFF_IRD_REG;
assign LAST_MUX = AUX_ALT | AUX_DAT;
assign INIT_RUN = NEW_PTB_RUN | INIT_CA_RUN;
assign LD_DRAM_A = ~DRAM_ACC | MDONE;
assign ICTODC[3] = USER;
always @(posedge BCLK) VADR_R <= VADR;
always @(posedge BCLK) DFF_IRD_REG <= IO_RD;
always @(posedge BCLK) DFF_HDFF1 <= IO_READY;
always @(posedge BCLK) if (LD_DRAM_A) DRAM_A[27:0] <= {RADR[27:12],VADR_R[11:2],USE_CA,CA_SET};
always @(posedge BCLK) if (IO_ACC) IO_A <= {RADR[31:12],VADR_R[11:0]};
always @(posedge BCLK) if (IO_RD) DFFE_IOR <= IO_Q;
always @(posedge BCLK or negedge BRESET)
if (!BRESET) HOLD_ON <= 1'b0;
else HOLD_ON <= (DATA_HOLD & DFF_HDFF1) | (HOLD_ON & DATA_HOLD);
always @(posedge MCLK) if (WCTRL[2]) CAPDAT <= DRAM_Q;
// +++++++++++++++++++++++++ Cache Valid +++++++++++++++++++
always @(posedge BCLK) CVALID <= CA_VALID[V_ADR[11:7]];
always @(negedge BCLK) if (WE_CV) CA_VALID[ACV] <= D_CV;
// +++++++++++++++++++++++++ Tag Set 0 +++++++++++++++++++++
always @(posedge BCLK) TAG0 <= TAGSET_0[VADR[11:4]];
always @(negedge BCLK) if (WRCRAM0) TAGSET_0[VADR_R[11:4]] <= RADR[27:12];
// +++++++++++++++++++++++++ Tag Set 1 +++++++++++++++++++++
always @(posedge BCLK) TAG1 <= TAGSET_1[VADR[11:4]];
always @(negedge BCLK) if (WRCRAM1) TAGSET_1[VADR_R[11:4]] <= RADR[27:12];
// +++++++++++++++++++++++++ Data Set 0 ++++++++++++++++++++
always @(posedge BCLK) SET_DAT0 <= DATA0[VADR[11:2]];
always @(posedge MCLK) if (WRSET0) DATA0[WADDR] <= DRAM_Q;
// +++++++++++++++++++++++++ Data Set 1 ++++++++++++++++++++
always @(posedge BCLK) SET_DAT1 <= DATA1[VADR[11:2]];
always @(posedge MCLK) if (WRSET1) DATA1[WADDR] <= DRAM_Q;
CA_MATCH DCA_COMPARE(
.INVAL_L(CINVAL[0]),
.CI(CI),
.MMU_HIT(MMU_HIT),
.WRITE(WRITE),
.KDET(1'b0),
.ADDR({RADR[27:12],VADR_R[11:4]}),
.CFG(CFG),
.ENDRAM(ENDRAM),
.CVALID(CVALID),
.TAG0(TAG0),
.TAG1(TAG1),
.CA_HIT(CA_HIT),
.CA_SET(CA_SET),
.WB_ACC(),
.USE_CA(USE_CA),
.IOSEL(RADR[31:28]),
.IO_SPACE(IO_SPACE),
.DC_ILO(1'b0),
.KILL(KILL_C),
.UPDATE(UPDATE_C));
DCA_CONTROL DCA_CTRL(
.BCLK(BCLK),
.MCLK(1'b0),
.WRCFG(1'b1),
.BRESET(BRESET),
.CA_SET(CA_SET),
.HIT_ALL(HIT_ALL),
.UPDATE(UPCD),
.VADR_R(VADR_R[11:7]),
.DRAM_ACC(DRAM_ACC),
.CUPDATE(CUPDATE),
.KILL(KILL),
.WRITE(WRITE),
.WCTRL(WCTRL[1:0]),
.INVAL_A(CINVAL[1]),
.DAT_CV(D_CV),
.WADR_CV(A_CV),
.WE_CV(WE_CV),
.INIT_CA_RUN(INIT_CA_RUN),
.WRCRAM0(WRCRAM0),
.WRCRAM1(WRCRAM1),
.WRSET0(WRSET0),
.WRSET1(WRSET1));
ICACHE_SM IC_SM(
.BCLK(BCLK),
.BRESET(BRESET),
.IO_SPACE(IO_SPACE),
.READ(READ),
.MDONE(MDONE),
.IO_READY(IO_READY),
.MMU_HIT(MMU_HIT),
.CA_HIT(CA_HIT),
.USE_CA(USE_CA),
.PTB_WR(PTB_WR),
.PTB_SEL(PTB_SEL),
.USER(USER),
.PROT_ERROR(PROT_ERROR),
.PTE_ACC(IC_SIGS[1]),
.ACC_OK(ACOK),
.PTB_ONE(PTB_ONE),
.NEW_PTB(NEW_PTB),
.AUX_DAT(AUX_DAT),
.CUPDATE(CUPDATE),
.IO_RD(IO_RD),
.IO_ACC(IO_ACC),
.DRAM_ACC(DRAM_ACC),
.IC_PREQ(IC_PREQ),
.HIT_ALL(HIT_ALL));
// +++++++++++++++++++++++++ Kollision Valid +++++++++++++++
always @(posedge BCLK) KCVALID <= KCA_VALID[KOLLI_A[11:7]];
always @(negedge BCLK) if (WE_CV) KCA_VALID[ACV] <= D_CV;
// +++++++++++++++++++++++++ Kollision Tag Set 0 +++++++++++
always @(posedge BCLK) KTAG0 <= KTAGSET_0[KOLLI_A[11:4]];
always @(negedge BCLK) if (WRCRAM0) KTAGSET_0[VADR_R[11:4]] <= RADR[27:12];
// +++++++++++++++++++++++++ Kollision Tag Set 1 +++++++++++
always @(posedge BCLK) KTAG1 <= KTAGSET_1[KOLLI_A[11:4]];
always @(negedge BCLK) if (WRCRAM1) KTAGSET_1[VADR_R[11:4]] <= RADR[27:12];
KOLDETECT KOLLOGIK(
.DRAM_WR(DRAM_WR),
.BCLK(BCLK),
.READ_I(READ_I),
.ACC_OK(ACC_OK),
.BRESET(BRESET),
.INVAL_A(CINVAL[1]),
.KDET(KDET),
.HOLD(HOLD),
.ENA_HK(ENA_HK),
.STOP_CINV(STOP_CINV),
.ADDR(KOLLI_A),
.C_VALID(KCVALID),
.CFG(CFG),
.CVALID(CVALID),
.TAG0(KTAG0),
.TAG1(KTAG1),
.KOLLISION(KOLLISION),
.STOP_ICRD(STOP_ICRD),
.RUN_ICRD(RUN_ICRD),
.KILL(KILL_K),
.ICTODC(ICTODC[2:0]),
.KILLADR(KILLADR),
.NEWCVAL(NEWCVAL));
MMU_MATCH MMU_COMPARE(
.USER(USER),
.READ(READ),
.WRITE(WRITE),
.RMW(RMW),
.IVAR(IVAR),
.MCR_FLAGS(MCR_FLAGS[2:0]),
.MMU_VA(MMU_Q[35:20]),
.MVALID(MVALID),
.VADR_R(VADR_R[31:12]),
.MMU_HIT(MMU_HIT),
.PROT_ERROR(PROT_ERROR),
.VIRTUELL(VIRTUELL),
.CI(CI),
.SEL_PTB1(),
.UPDATE(UPDATE_M));
MMU_UP MMU_CTRL(
.NEW_PTB(NEW_PTB),
.IVAR(IVAR[1]),
.BRESET(BRESET),
.PTB1(PTB_ONE),
.BCLK(BCLK),
.WR_MRAM(IC_SIGS[0]),
.MVALID(MVALID),
.UPDATE(UPDATE_M),
.VADR(VADR[19:16]),
.VADR_R(VADR_R[19:16]),
.WE_MV(WEMV),
.NEW_PTB_RUN(NEW_PTB_RUN),
.DAT_MV(DAT_MV),
.RADR_MV(RADR_MV),
.WADR_MV(WADR_MV));
// +++++++++++++++++++++++++ MMU Valid +++++++++++++++++++++
always @(posedge BCLK) MVALID <= MMU_VALID[RADR_MV];
always @(negedge BCLK) if (WEMV) MMU_VALID[WADR_MV] <= DAT_MV;
// +++++++++++++++++++++++++ MMU Tags ++++++++++++++++++++++
always @(posedge BCLK) MMU_Q <= MMU_TAGS[VADR[19:12]];
always @(negedge BCLK) if (IC_SIGS[0]) MMU_TAGS[VADR_R[19:12]] <= {VADR_R[31:20],MMU_DIN[23:0]};
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
module add_compare_select (npm, d, pm1, bm1, pm2, bm2);
/**
* WARNING TO DEVELOPER(S)!!!
*
* CHECK/VERIFY THAT THE WIDTH OF ALL THE PATH METRIC BUSES
* ARE THE SAME
*
* SUCH BUSES INCLUDE npm, pm1, pm2, add1, and add2
*
* THE FOLLOWING BUSES ARE NOT INCLUDED: bm1, bm2, add_temp1,
* and add_temp2
*
* NOTE THAT THE WIDTHS OF add_temp1 AND add_temp2 ARE ONE GREATER
* THAN THOSE OF THE PATH METRIC BUSES
*/
// Output signals for the design module
/**
* New path metric - It keeps growing, so reasonable number
* of bits have to be chosen so that npm is unlikely to overflow
* Number of bits chosen = 4
*
* To handle overflows, I have decided to saturate the result
* of the computation at 2^n - 1 = 2^4 - 1 = 15
*/
output [3:0] npm;
// Decision bit from the add-compare-select unit
output d;
// Input signals for the design module
// Current path metric #1 for a set of addition
input [3:0] pm1;
// Branch metric #1 for a set of addition
input [1:0] bm1;
// Current path metric #2 for another set of addition
input [3:0] pm2;
// Branch metric #2 for another set of addition
input [1:0] bm2;
// Declare "reg" signals... that will be assigned values
reg [3:0] npm;
reg d;
/**
* Result of the additions in the first stage of the
* add-compare-select unit
*/
// Result of a set of addition
reg [3:0] add1;
// Result of another set of addition
reg [3:0] add2;
// Temporary storage for a set of addition to check for overflow
reg [4:0] add_temp1;
// Temporary storage for another set of addition to check for overflow
reg [4:0] add_temp2;
// Declare "wire" signals...
// Defining constants: parameter [name_of_constant] = value;
// Maximum value that can be stored in a 4-bit bus
parameter max_add = 4'd15;
/**
* Perform the addition stage of the add-compare-select unit
* Result of a set of addition
*/
always @ (pm1 or bm1)
begin
// Add the operands and temporary store them
add_temp1 = pm1 + bm1;
// Did the (temporary) addition cause an overflow
if(add_temp1 > max_add)
begin
/**
* Yes... An overflow has occurred.
* Saturate the addition to max_add
*/
add1 = max_add;
end
else
begin
/**
* An overflow did not occur with the addition of 2
* numbers. Hence, the result of the addition is the
* sum of the 2 numbers.
*/
add1 = pm1 + bm1;
end
end
/**
* Perform the addition stage of the add-compare-select unit
* Result of another set of addition
*/
always @ (pm2 or bm2)
begin
// Add the operands and temporary store them
add_temp2 = pm2 + bm2;
// Did the (temporary) addition cause an overflow
if(add_temp2 > max_add)
begin
/**
* Yes... An overflow has occurred.
* Saturate the addition to max_add
*/
add2 = max_add;
end
else
begin
/**
* An overflow did not occur with the addition of 2
* numbers. Hence, the result of the addition is the
* sum of the 2 numbers.
*/
add2 = pm2 + bm2;
end
end
// ========================================================
// Perform the compare stage of the add-compare-select unit
always @ (add1 or add2)
begin
if(add1 <= add2)
begin
// Select path 1 ==> d=0
d = 1'b0;
end
else
begin
// Select path 2 ==> d=1
d = 1'b1;
end
end
// ========================================================
// Perform the select stage of the add-compare-select unit
always @ (d or add1 or add2)
begin
if(d)
begin
// Select path 2... add1 < add2
npm = add2;
end
else
begin
// Select path 1... add1 >= add2
npm = add1;
end
end
endmodule
///////////////////////////////////////////////////////////////////////////////
/// Andrew Mattheisen
/// Zhiyang Ong
///
/// EE-577b 2007 fall
/// VITERBI DECODER
/// bmu module
///
///////////////////////////////////////////////////////////////////////////////
module bmu (cx0, cx1, bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7);
// outputs
output [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
// inputs
input cx0, cx1;
// registers
reg [1:0] bm0, bm1, bm2, bm3, bm4, bm5, bm6, bm7;
always@ (cx0 or cx1)
begin
if (cx0==0 && cx1==0)
begin
bm0 <= 2'd0; // this is going from 00 to 00
bm1 <= 2'd2; // this is going from 00 to 10
bm2 <= 2'd2; // this is going from 01 to 00
bm3 <= 2'd0; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
else if (cx0==0 && cx1==1)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd2; // this is going from 10 to 01
bm5 <= 2'd0; // this is going from 10 to 11
bm6 <= 2'd0; // this is going from 11 to 01
bm7 <= 2'd2; // this is going from 11 to 11
end
else if (cx0==1 && cx1==0)
begin
bm0 <= 2'd1; // this is going from 00 to 00
bm1 <= 2'd1; // this is going from 00 to 10
bm2 <= 2'd1; // this is going from 01 to 00
bm3 <= 2'd1; // this is going from 01 to 10
bm4 <= 2'd0; // this is going from 10 to 01
bm5 <= 2'd2; // this is going from 10 to 11
bm6 <= 2'd2; // this is going from 11 to 01
bm7 <= 2'd0; // this is going from 11 to 11
end
else if (cx0==1 && cx1==1)
begin
bm0 <= 2'd2; // this is going from 00 to 00
bm1 <= 2'd0; // this is going from 00 to 10
bm2 <= 2'd0; // this is going from 01 to 00
bm3 <= 2'd2; // this is going from 01 to 10
bm4 <= 2'd1; // this is going from 10 to 01
bm5 <= 2'd1; // this is going from 10 to 11
bm6 <= 2'd1; // this is going from 11 to 01
bm7 <= 2'd1; // this is going from 11 to 11
end
end // always @ (posedge clk)
endmodule
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
2-4demux module used in spdu module
*/
module demux (in0, in1, in2, in3, d0, d1, out);
// outputs
output out;
// inputs
input in0, in1, in2, in3;
input d0, d1;
// registers
reg temp1, temp2, out;
always@(in0 or in1 or in2 or in3 or d0 or d1)
begin
temp1 = d0?in1:in0;
temp2 = d0?in3:in2;
out = d1?temp2:temp1;
end // always@(in0 or in1 or in2 or in3 or d0 or d1)
endmodule
///////////////////////////////////////////////////////////////////////////////
/// Andrew Mattheisen
/// Zhiyang Ong
///
/// EE-577b 2007 fall
/// VITERBI DECODER
/// pmsm module (Path Metric State Memory)
///
/**
* @modified by Zhiyang Ong on November 1, 2007
* The reset values for the 2nd to the 4th
* registers are modified to achieve a unique solution,
* and avoid a set of equivalent paths for the solution.
* See subsequent comments in the code for further
* elaboration
*/
/// @modified by AJM - uncommented the change mentioned above
///////////////////////////////////////////////////////////////////////////////
module pmsm (npm0, npm1, npm2, npm3, pm0, pm1, pm2, pm3, clk, reset);
// outputs
output [3:0] pm0, pm1, pm2, pm3;
// inputs
input clk, reset;
input [3:0] npm0, npm1, npm2, npm3;
reg [3:0] pm0, pm1, pm2, pm3;
reg [3:0] npm0norm, npm1norm, npm2norm, npm3norm;
// Defining constants: parameter [name_of_constant] = value;
parameter saturating_value = 4'd15;
always @ (npm0 or npm1 or npm2 or npm3)
begin
if ((npm0 <= npm1)&&(npm0 <= npm2)&&(npm0 <= npm3))
begin
npm0norm <= 0;
npm1norm <= npm1-npm0;
npm2norm <= npm2-npm0;
npm3norm <= npm3-npm0;
end
else if ((npm1 <= npm0)&&(npm1 <= npm2)&&(npm1 <= npm3))
begin
npm0norm <= npm0-npm1;
npm1norm <= 0;
npm2norm <= npm2-npm1;
npm3norm <= npm3-npm1;
end
else if ((npm2 <= npm0)&&(npm2 <= npm1)&&(npm2 <= npm3))
begin
npm0norm <= npm0-npm2;
npm1norm <= npm1-npm2;
npm2norm <= 0;
npm3norm <= npm3-npm2;
end
else if ((npm3 <= npm0)&&(npm3 <= npm1)&&(npm3 <= npm2))
begin
npm0norm <= npm0-npm3;
npm1norm <= npm1-npm3;
npm2norm <= npm2-npm3;
npm3norm <= 0;
end
end // always @ (npm0 or npm1 or npm2 or npm3)
/**
* @modified by Zhiyang Ong, November 1, 2007
* Note that the first register is reset to zero,
* and the rest are reset to infinity, which is
* represented by the saturating value of 15
* = 2^n - 1 = 2^4 - 1.
*
* This prevents the solution from arriving at a
* set of false/incorrect set of equivalent
* paths in the Trellis diagram. Multiple paths
* with zero costs indicate no unique solution.
* Also, these infinite/saturated values will be
* "removed"/diminished in 2 clock cycles.
*/
always @ (posedge clk)
begin
if (reset)
begin
pm0 <= 4'd0;
pm1 <= saturating_value;
pm2 <= saturating_value;
pm3 <= saturating_value;
end
else
begin
pm0 <= npm0norm;
pm1 <= npm1norm;
pm2 <= npm2norm;
pm3 <= npm3norm;
end
end // always @ (posedge clk)
endmodule
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
selector module
*/
module selector (pm0, pm1, pm2, pm3, d0, d1);
// outputs
output d0, d1;
// inputs
input [3:0] pm0, pm1, pm2, pm3;
// registers
reg d0, d1;
reg [1:0] int0, int1;
reg [3:0] pm_int0, pm_int1;
always @ (pm0 or pm1 or pm2 or pm3)
begin
int0 = (pm0<=pm1)?2'd0:2'd1; // select smaller of pm0 or pm1
int1 = (pm2<=pm3)?2'd2:2'd3; // select smaller of pm2 or pm3
pm_int0 = (pm0<=pm1)?pm0:pm1; // select smaller of pm0 or pm1
pm_int1 = (pm2<=pm3)?pm2:pm3; // select smaller of pm2 or pm3
{d1,d0} = (pm_int0<=pm_int1)?int0:int1; // create control signals d0 and d1
end // always @ (pm0 or pm1 or pm2 or pm3)
endmodule
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
spd module
@modified by Zhiyang Ong on November 1, 2007
The output out signal must be of the data type reg
I had to reallocate this data-type reg.
Correction: It is relabelled to the wire data type since
it is not used again, or explicitly assigned a value in
this module
*/
module spd (d0, d1, d2, d3, pm0, pm1, pm2, pm3, out, clk, reset);
// outputs
output out;
// inputs
input d0, d1, d2, d3;
input [3:0] pm0, pm1, pm2, pm3;
input clk, reset;
// @modified by Zhiyang Ong on November 1, 2007
// Registers...
// reg out;
/*
reg selectord0, selectord1;
reg spdu0out0, spdu0out1, spdu0out2, spdu0out3;
reg spdu1out0, spdu1out1, spdu1out2, spdu1out3;
reg spdu2out0, spdu2out1, spdu2out2, spdu2out3;
reg spdu3out0, spdu3out1, spdu3out2, spdu3out3;
reg spdu4out0, spdu4out1, spdu4out2, spdu4out3;
reg spdu5out0, spdu5out1, spdu5out2, spdu5out3;
reg spdu6out0, spdu6out1, spdu6out2, spdu6out3;
reg spdu7out0, spdu7out1, spdu7out2, spdu7out3;
reg spdu8out0, spdu8out1, spdu8out2, spdu8out3;
reg spdu9out0, spdu9out1, spdu9out2, spdu9out3;
reg spdu10out0, spdu10out1, spdu10out2, spdu10out3;
reg spdu11out0, spdu11out1, spdu11out2, spdu11out3;
reg spdu12out0, spdu12out1, spdu12out2, spdu12out3;
reg spdu13out0, spdu13out1, spdu13out2, spdu13out3;
reg spdu14out0, spdu14out1, spdu14out2, spdu14out3;
*/
// wires
// @Modified by Zhiyang Ong on November 1, 2007
wire out;
wire selectord0, selectord1;
wire spdu0out0, spdu0out1, spdu0out2, spdu0out3;
wire spdu1out0, spdu1out1, spdu1out2, spdu1out3;
wire spdu2out0, spdu2out1, spdu2out2, spdu2out3;
wire spdu3out0, spdu3out1, spdu3out2, spdu3out3;
wire spdu4out0, spdu4out1, spdu4out2, spdu4out3;
wire spdu5out0, spdu5out1, spdu5out2, spdu5out3;
wire spdu6out0, spdu6out1, spdu6out2, spdu6out3;
wire spdu7out0, spdu7out1, spdu7out2, spdu7out3;
wire spdu8out0, spdu8out1, spdu8out2, spdu8out3;
wire spdu9out0, spdu9out1, spdu9out2, spdu9out3;
wire spdu10out0, spdu10out1, spdu10out2, spdu10out3;
wire spdu11out0, spdu11out1, spdu11out2, spdu11out3;
wire spdu12out0, spdu12out1, spdu12out2, spdu12out3;
wire spdu13out0, spdu13out1, spdu13out2, spdu13out3;
wire spdu14out0, spdu14out1, spdu14out2, spdu14out3;
spdu spdu0(1'b0,
1'b0,
1'b1,
1'b1, d0, d1, d2, d3,
spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, clk, reset);
spdu spdu1(spdu0out0,
spdu0out1,
spdu0out2,
spdu0out3, d0, d1, d2, d3,
spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, clk, reset);
spdu spdu2(spdu1out0,
spdu1out1,
spdu1out2,
spdu1out3, d0, d1, d2, d3,
spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, clk, reset);
spdu spdu3(spdu2out0,
spdu2out1,
spdu2out2,
spdu2out3, d0, d1, d2, d3,
spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, clk, reset);
spdu spdu4(spdu3out0,
spdu3out1,
spdu3out2,
spdu3out3, d0, d1, d2, d3,
spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, clk, reset);
spdu spdu5(spdu4out0,
spdu4out1,
spdu4out2,
spdu4out3, d0, d1, d2, d3,
spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, clk, reset);
spdu spdu6(spdu5out0,
spdu5out1,
spdu5out2,
spdu5out3, d0, d1, d2, d3,
spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, clk, reset);
spdu spdu7(spdu6out0,
spdu6out1,
spdu6out2,
spdu6out3, d0, d1, d2, d3,
spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, clk, reset);
spdu spdu8(spdu7out0,
spdu7out1,
spdu7out2,
spdu7out3, d0, d1, d2, d3,
spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, clk, reset);
spdu spdu9(spdu8out0,
spdu8out1,
spdu8out2,
spdu8out3, d0, d1, d2, d3,
spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, clk, reset);
spdu spdu10(spdu9out0,
spdu9out1,
spdu9out2,
spdu9out3, d0, d1, d2, d3,
spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, clk, reset);
spdu spdu11(spdu10out0,
spdu10out1,
spdu10out2,
spdu10out3, d0, d1, d2, d3,
spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, clk, reset);
spdu spdu12(spdu11out0,
spdu11out1,
spdu11out2,
spdu11out3, d0, d1, d2, d3,
spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, clk, reset);
spdu spdu13(spdu12out0,
spdu12out1,
spdu12out2,
spdu12out3, d0, d1, d2, d3,
spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, clk, reset);
spdu spdu14(spdu13out0,
spdu13out1,
spdu13out2,
spdu13out3, d0, d1, d2, d3,
spdu14out0,
spdu14out1,
spdu14out2,
spdu14out3, clk, reset);
selector selector1 (pm0, pm1, pm2, pm3, selectord0, selectord1);
demux demux1 (spdu14out0, spdu14out1, spdu14out2, spdu14out3,
selectord0, selectord1, out);
endmodule
/*
Andrew Mattheisen
Zhiyang Ong
EE-577b 2007 fall
VITERBI DECODER
spdu module
*/
module spdu (in0, in1, in2, in3, d0, d1, d2, d3,
out0, out1, out2, out3, clk, reset);
// outputs
output out0, out1, out2, out3;
// inputs
input in0, in1, in2, in3;
input d0, d1, d2, d3;
input clk, reset;
// registers
reg w0, w1, w2, w3;
reg out0, out1, out2, out3;
always @ (d0 or d1 or d2 or d3 or in0 or in1 or in2 or in3)
begin
w0 <= d0?in1:in0; // select 0 or 1
w1 <= d1?in3:in2; // select 2 or 3
w2 <= d2?in1:in0; // select 0 or 1
w3 <= d3?in3:in2; // select 2 or 3
end // always @ (d0 or d1 or d2 or d3 or in0 or in1 or in2 or in3)
always @ (posedge clk)
begin
if (reset)
begin
out0 <= 1'b0;
out1 <= 1'b0;
out2 <= 1'b0;
out3 <= 1'b0;
end
else
begin
out0 <= w0;
out1 <= w1;
out2 <= w2;
out3 <= w3;
end
end // always @ (posedge clk)
endmodule
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
*/
/**
* Import the design modules for other design submodules
*
* Include statements for design modules/files need to be commented
* out when I use the Make environment - similar to that in
* Assignment/Homework 3.
*
* Else, the Make/Cadence environment will not be able to locate
* the files that need to be included.
*
* The Make/Cadence environment will automatically search all
* files in the design/ and include/ directories of the working
* directory for this project that uses the Make/Cadence
* environment for the design modules
*
* If the ".f" files are used to run NC-Verilog to compile and
* simulate the Verilog testbench modules, use this include
* statement
*/
// Design of the Viterbi decoder
module viterbi_decoder (d, cx, clk, reset);
// Output signals for the design module
// Decoded output signal from the Viterbi decoder
output d;
// Input signals for the design module
// Received encoded signal that may have corrupted bits
input [1:0] cx;
// Input clock signal for the Viterbi decoder
input clk;
// Reset signal for the Viterbi decoder
input reset;
// Declare "reg" signals... that will be assigned values
// reg d;
// Set of branch metric outputs from the BMU
// reg [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
// reg [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
// reg d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
// reg [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
// reg [3:0] p_m0, p_m1, p_m2, p_m3;
// Declare "wire" signals...
wire d;
// Set of branch metric outputs from the BMU
wire [1:0] brch_met0,brch_met1,brch_met2,brch_met3;
wire [1:0] brch_met4,brch_met5,brch_met6,brch_met7;
// Outputs from the ACS units
// Decision bit output from the ACS units
wire d0,d1,d2,d3;
// Output from the ACS that indicates the new path metric
wire [3:0] n_pm0,n_pm1,n_pm2,n_pm3;
// Outputs from the PMSM units
wire [3:0] p_m0, p_m1, p_m2, p_m3;
// Defining constants: parameter [name_of_constant] = value;
/*******************************************************
*
* Connecting the modules of the Viterbi decoder together
* That is, link the following modules together:
* # Branch Metric calculation Unit (BMU)
* # Add-Compare-Select unit (ACS)
* # Survivor Path Decoding Unit (SPDU)
* # Survivor Path Decoder (SPD)
* # Path Metric State Memory (PMSM)
*
* Note that the SPD module includes the demux (2-to-4
* DEMUX/demultiplexer) and selector.
*
* The selector chooses the smallest path metric to
* create the control signal to select the smallest path
*
* In addition, note that the SPD module includes 15 SPDU
* units.
*
*
*
* Basic architecture of the Viterbi decoder:
*
* (1) (4) (1) (1)
* BMU->ACS->PMSM->SPD
* v ^ V ^
* | | | |
* | ----- |
* | |
* ------------|
*
*******************************************************
*/
// =====================================================
/**
* Instantiate the BMU to receive inputs for the Viterbi
* decoder, and produce outputs for the ACS units
*
* There is only one BMU for the Viterbi decoder
*/
bmu brch_met (cx[0], cx[1],
brch_met0,brch_met1,brch_met2,brch_met3,
brch_met4,brch_met5,brch_met6,brch_met7);
// =====================================================
/**
* Instantiate the 4 ACS units to receive inputs from
* the BMU and the PMSM, and produce outputs for the SPD
* and the PMSM
*
* The assignment of branch and path metrics to each
* state is based on the Trellis diagrams for different
* inputs for the input code(s), cx or cin
*
* See the BMU module for the interconnections.
*/
// Instantiate the 1st ACS unit
add_compare_select acs0 (n_pm0, d0,
p_m0, brch_met0, p_m1, brch_met2);
// Instantiate the 2nd ACS unit
add_compare_select acs1 (n_pm1, d1,
p_m2, brch_met4, p_m3, brch_met6);
// Instantiate the 3rd ACS unit
add_compare_select acs2 (n_pm2, d2,
p_m0, brch_met1, p_m1, brch_met3);
// Instantiate the 4th ACS unit
add_compare_select acs3 (n_pm3, d3,
p_m2, brch_met5, p_m3, brch_met7);
// =====================================================
/**
* Instantiate the PMSM that contains a set of 4
* registers, and circuitry to normalize the path metrics
* by subtracting the smallest path metric from all of
* the path metrics
*
* There is only one PMSM for the Viterbi decoder
*/
pmsm path_metric_sm (n_pm0, n_pm1, n_pm2, n_pm3,
p_m0, p_m1, p_m2, p_m3, clk, reset);
// =====================================================
/**
* Instantiate the SPD that uses the current path metric
* and the decision bits to determine the optimal path
* for Viterbi decoding using dynamic programming
*
* There is only one SPD for the Viterbi decoder
*/
spd survivor_path_dec (d0, d1, d2, d3, p_m0, p_m1, p_m2, p_m3,
d, clk, reset);
endmodule
|
// Icarus 0.6, snapshot 20020907
// ==================================================
// -- confused by disables from within a fork -- vvp fails
//
// -- to run, incant
// iverilog tt.v
// vvp a.out
//
// Veriwell
// ========
// -- OK
//
module top;
integer simple_fail, loop_fail, fork_fail, tlp_fail;
integer tfk_fail, tfk2_fail, tfk3_fail;
integer tfk2pos, tfk2nega, tfk2negb;
integer tfk3pos, tfk3nega, tfk3negb;
integer loop_cntr, tlp_cntr;
reg fred, abort;
initial begin
#1;
simple_fail = 0;
loop_fail = 0;
fork_fail = 0;
tlp_fail = 0;
tfk_fail = 0;
tfk2_fail = 0;
tfk2pos = 0;
tfk2nega = 1;
tfk2negb = 1;
tfk3pos = 0;
tfk3nega = 1;
tfk3negb = 1;
fred = 0;
abort = 1;
#4;
fred = 1;
#4
$display("Check disable:");
if(simple_fail) $display("***** simple block FAILED *****");
else $display("***** simple block PASSED *****");
if(loop_fail) $display("***** block with loop FAILED *****");
else $display("***** block with loop PASSED *****");
if(fork_fail) $display("***** forked block FAILED *****");
else $display("***** forked block PASSED *****");
if(tlp_fail) $display("***** task with loop FAILED *****");
else $display("***** task with loop PASSED *****");
if(tfk_fail) $display("***** task with forked block FAILED *****");
else $display("***** task with forked block PASSED *****");
if(tfk2_fail) $display("***** one forked block FAILED *****");
else $display("***** one forked block PASSED *****");
if(tfk3_fail) $display("***** the other forked block FAILED *****");
else $display("***** the other forked block PASSED *****");
$display("");
$finish(0);
end
// simple block disable
initial begin: block_name
#2;
disable block_name;
simple_fail = 1;
end
// more complex: block disable inside for-loop
initial begin
#2;
begin: configloop
for (loop_cntr = 0; loop_cntr < 3; loop_cntr=loop_cntr+1) begin
wait (fred);
if (abort) begin
disable configloop;
end
loop_fail = 1;
end
end // configloop block
if (loop_fail) $display("\n\ttime: %0t, loop_cntr: %0d",$time,loop_cntr);
end
// still more complex: disable from within a forked block
initial begin
#2;
begin: forked_tasks
fork
begin
#5;
fork_fail = 1;
end
begin
@(fred);
disable forked_tasks;
fork_fail = 1;
end
join
fork_fail = 1;
end //forked_tasks
end
// disables inside tasks
initial begin
task_with_loop;
end
initial begin
task_with_fork;
end
initial begin
task_with_fork2;
if(tfk2pos || tfk2nega || tfk2negb) tfk2_fail = 1;
end
initial begin
task_with_fork3;
if(tfk3pos || tfk3nega || tfk3negb) tfk3_fail = 1;
end
task task_with_loop;
begin
#2;
begin: configtlp
for (tlp_cntr = 0; tlp_cntr < 3; tlp_cntr=tlp_cntr+1) begin
wait (fred);
if (abort) begin
disable configtlp;
end
tlp_fail = 1;
end
end // configloop block
end
endtask // task_with_loop
task task_with_fork; // disable block whick calls fork
begin
#2;
begin: forked_tasks_in_task
fork
begin: alf
#5;
tfk_fail = 1;
end
begin: bet
@(fred);
disable forked_tasks_in_task;
tfk_fail = 1;
end
join
tfk_fail = 1;
end //forked_tasks_in_task
end
endtask // task_with_fork
task task_with_fork2; // disable *one* of the forked blocks
begin
#2;
begin: forked_tasks_in_task2
fork
begin: gam
#5;
tfk2pos = 1;
end
begin: delt
@(fred);
disable gam;
tfk2nega = 0;
end
join
tfk2negb = 0;
end //forked_tasks_in_task
end
endtask // task_with_fork
task task_with_fork3; // disable *one* of the forked blocks
begin
#2;
begin: forked_tasks_in_task3
fork
begin: eps
#5;
tfk3nega = 0;
end
begin: zet
@(fred);
disable zet;
tfk3pos = 1;
end
join
tfk3negb = 0;
end //forked_tasks_in_task
end
endtask // task_with_fork
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Dispatcher for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Dispatcher
// Module Name: Dispatcher
// File Name: Dispatcher.v
//
// Version: v1.0.0
//
// Description: Central way controller
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
// * v1.1.0
// - external brom interface
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module Dispatcher
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter NumberOfWays = 4 ,
parameter ProgWordWidth = 64 ,
parameter UProgSize = 256
)
(
iClock ,
iReset ,
iWriteAddress ,
iReadAddress ,
iWriteData ,
oReadData ,
iWriteValid ,
iReadValid ,
oWriteAck ,
oReadAck ,
oDstWOpcode ,
oDstWTargetID ,
oDstWSourceID ,
oDstWAddress ,
oDstWLength ,
oDstWCmdValid ,
iDstWCmdReady ,
oDstWriteData ,
oDstWriteValid ,
oDstWriteLast ,
iDstWriteReady ,
oDstROpcode ,
oDstRTargetID ,
oDstRSourceID ,
oDstRAddress ,
oDstRLength ,
oDstRCmdValid ,
iDstRCmdReady ,
iDstReadData ,
iDstReadValid ,
iDstReadLast ,
oDstReadReady ,
oPCGWOpcode ,
oPCGWTargetID ,
oPCGWSourceID ,
oPCGWAddress ,
oPCGWLength ,
oPCGWCmdValid ,
iPCGWCmdReady ,
oPCGWriteData ,
oPCGWriteValid ,
oPCGWriteLast ,
iPCGWriteReady ,
oPCGROpcode ,
oPCGRTargetID ,
oPCGRSourceID ,
oPCGRAddress ,
oPCGRLength ,
oPCGRCmdValid ,
iPCGRCmdReady ,
iPCGReadData ,
iPCGReadValid ,
iPCGReadLast ,
oPCGReadReady ,
iWaysReadybusy ,
oROMClock ,
oROMReset ,
oROMAddr ,
oROMRW ,
oROMEnable ,
oROMWData ,
iROMRData
);
input iClock ;
input iReset ;
// Command Interface
input [AddressWidth - 1:0] iWriteAddress ;
input [AddressWidth - 1:0] iReadAddress ;
input [DataWidth - 1:0] iWriteData ;
output [DataWidth - 1:0] oReadData ;
input iWriteValid ;
input iReadValid ;
output oWriteAck ;
output oReadAck ;
// Data Cascade Layer Interface
output [5:0] oDstWOpcode ;
output [4:0] oDstWTargetID ;
output [4:0] oDstWSourceID ;
output [AddressWidth - 1:0] oDstWAddress ;
output [InnerIFLengthWidth - 1:0] oDstWLength ;
output oDstWCmdValid ;
input iDstWCmdReady ;
output [DataWidth - 1:0] oDstWriteData ;
output oDstWriteValid ;
output oDstWriteLast ;
input iDstWriteReady ;
output [5:0] oDstROpcode ;
output [4:0] oDstRTargetID ;
output [4:0] oDstRSourceID ;
output [AddressWidth - 1:0] oDstRAddress ;
output [InnerIFLengthWidth - 1:0] oDstRLength ;
output oDstRCmdValid ;
input iDstRCmdReady ;
input [DataWidth - 1:0] iDstReadData ;
input iDstReadValid ;
input iDstReadLast ;
output oDstReadReady ;
// PCG Interface
output [5:0] oPCGWOpcode ;
output [4:0] oPCGWTargetID ;
output [4:0] oPCGWSourceID ;
output [39:0] oPCGWAddress ;
output [InnerIFLengthWidth - 1:0] oPCGWLength ;
output oPCGWCmdValid ;
input iPCGWCmdReady ;
output [DataWidth - 1:0] oPCGWriteData ;
output oPCGWriteValid ;
output oPCGWriteLast ;
input iPCGWriteReady ;
output [5:0] oPCGROpcode ;
output [4:0] oPCGRTargetID ;
output [4:0] oPCGRSourceID ;
output [39:0] oPCGRAddress ;
output [InnerIFLengthWidth - 1:0] oPCGRLength ;
output oPCGRCmdValid ;
input iPCGRCmdReady ;
input [DataWidth - 1:0] iPCGReadData ;
input iPCGReadValid ;
input iPCGReadLast ;
output oPCGReadReady ;
input [NumberOfWays - 1:0] iWaysReadybusy ;
output oROMClock ;
output oROMReset ;
output [$clog2(UProgSize) - 1:0] oROMAddr ;
output oROMRW ;
output oROMEnable ;
output [ProgWordWidth - 1:0] oROMWData ;
input [ProgWordWidth - 1:0] iROMRData ;
// internal signals
// muxed command channel
wire wMuxSelect ;
wire [5:0] wMuxedWOpcode ;
wire [4:0] wMuxedWTargetID ;
wire [4:0] wMuxedWSourceID ;
wire [39:0] wMuxedWAddress ;
wire [InnerIFLengthWidth - 1:0] wMuxedWLength ;
wire wMuxedWCmdValid ;
wire wMuxedWCmdReady ;
wire [5:0] wMuxedROpcode ;
wire [4:0] wMuxedRTargetID ;
wire [4:0] wMuxedRSourceID ;
wire [39:0] wMuxedRAddress ;
wire [InnerIFLengthWidth - 1:0] wMuxedRLength ;
wire wMuxedRCmdValid ;
wire wMuxedRCmdReady ;
// registers
localparam NumberOfRegs = 9;
parameter UProgSizeWidth = $clog2(UProgSize);
reg [AddressWidth - 1:0] rDataAddress ;
reg [AddressWidth - 1:0] rSpareAddress ;
reg [AddressWidth - 1:0] rErrCntAddress ;
reg [AddressWidth - 1:0] rCmpltAddress ;
reg [23:0] rRowAddress ;
reg [15:0] rColAddress ;
reg [DataWidth - 1:0] rUserData ;
reg [NumberOfWays - 1:0] rWaySelection ;
reg [31:0] rUProgramSelect ;
wire [AddressWidth - 1:0] wLPQDataAddress ;
wire [AddressWidth - 1:0] wLPQSpareAddress ;
wire [AddressWidth - 1:0] wLPQErrCntAddress ;
wire [AddressWidth - 1:0] wLPQCmpltAddress ;
wire [23:0] wLPQRowAddress ;
wire [15:0] wLPQColAddress ;
wire [DataWidth - 1:0] wLPQUserData ;
wire [NumberOfWays - 1:0] wLPQWaySelection ;
wire [UProgSizeWidth - 1:0] wLPQUProgramSelect ;
wire [AddressWidth - 1:0] wDataAddress ;
wire [AddressWidth - 1:0] wSpareAddress ;
wire [AddressWidth - 1:0] wErrCntAddress ;
wire [AddressWidth - 1:0] wCmpltAddress ;
wire [23:0] wRowAddress ;
wire [15:0] wColAddress ;
wire [DataWidth - 1:0] wUserData ;
wire [NumberOfWays - 1:0] wWaySelection ;
wire [UProgSizeWidth - 1:0] wUProgramSelect ;
wire [AddressWidth - 1:0] wHPQDataAddress ;
wire [AddressWidth - 1:0] wHPQSpareAddress ;
wire [AddressWidth - 1:0] wHPQErrCntAddress ;
wire [AddressWidth - 1:0] wHPQCmpltAddress ;
wire [23:0] wHPQRowAddress ;
wire [15:0] wHPQColAddress ;
wire [DataWidth - 1:0] wHPQUserData ;
wire [NumberOfWays - 1:0] wHPQWaySelection ;
wire [UProgSizeWidth - 1:0] wHPQUProgramSelect ;
wire wDispatchFSMTrigger ;
reg rUProgSelValid ;
// 0: ready/busy
reg rChStatus ;
wire [NumberOfWays - 1:0] wSelectedWay ;
reg [DataWidth - 1:0] rReadDataOut ;
reg [DataWidth - 1:0] rRegDataOut ;
//
wire [ProgWordWidth - 1:0] wUProgData ;
reg [ProgWordWidth - 1:0] rUProgData ;
wire wUProgDataValid ;
wire wUProgDataReady ;
wire [5:0] wDPQWOpcode ;
wire [4:0] wDPQWTargetID ;
wire [4:0] wDPQWSourceID ;
wire [AddressWidth - 1:0] wDPQWAddress ;
wire [InnerIFLengthWidth - 1:0] wDPQWLength ;
wire wDPQWCmdValid ;
wire wDPQWCmdReady ;
wire [5:0] wDPQROpcode ;
wire [4:0] wDPQRTargetID ;
wire [4:0] wDPQRSourceID ;
wire [AddressWidth - 1:0] wDPQRAddress ;
wire [InnerIFLengthWidth - 1:0] wDPQRLength ;
wire wDPQRCmdValid ;
wire wDPQRCmdReady ;
wire [DataWidth - 1:0] wDPQWriteData ;
wire wDPQWriteValid ;
wire wDPQWriteLast ;
wire wDPQWriteReady ;
wire [DataWidth - 1:0] wDPQReadData ;
wire wDPQReadValid ;
wire wDPQReadLast ;
wire wDPQReadReady ;
reg rPipeliningMode ;
localparam State_Halt = 3'b000 ;
localparam State_FirstFetch = 3'b001 ;
localparam State_Decode = 3'b011 ;
localparam State_WritecmdToModule = 3'b010 ;
localparam State_ReadcmdToModule = 3'b110 ;
localparam State_UpTransfer = 3'b111 ;
localparam State_DownTransfer = 3'b101 ;
localparam State_NextRequest = 3'b100 ;
V2DatapathClockConverter32
DatapathQueue
(
.iSClock (iClock ),
.iSReset (iReset ),
.iSWOpcode (wDPQWOpcode ),
.iSWTargetID (wDPQWTargetID ),
.iSWSourceID (wDPQWSourceID ),
.iSWAddress (wDPQWAddress ),
.iSWLength (wDPQWLength ),
.iSWCMDValid (wDPQWCmdValid ),
.oSWCMDReady (wDPQWCmdReady ),
.iSWriteData (wDPQWriteData ),
.iSWriteLast (wDPQWriteLast ),
.iSWriteValid (wDPQWriteValid ),
.oSWriteReady (wDPQWriteReady ),
.iSROpcode (wDPQROpcode ),
.iSRTargetID (wDPQRTargetID ),
.iSRSourceID (wDPQRSourceID ),
.iSRAddress (wDPQRAddress ),
.iSRLength (wDPQRLength ),
.iSRCMDValid (wDPQRCmdValid ),
.oSRCMDReady (wDPQRCmdReady ),
.oSReadData (wDPQReadData ),
.oSReadLast (wDPQReadLast ),
.oSReadValid (wDPQReadValid ),
.iSReadReady (wDPQReadReady ),
.iMClock (iClock ),
.iMReset (iReset ),
.oMWOpcode (oDstWOpcode ),
.oMWTargetID (oDstWTargetID ),
.oMWSourceID (oDstWSourceID ),
.oMWAddress (oDstWAddress ),
.oMWLength (oDstWLength ),
.oMWCMDValid (oDstWCmdValid ),
.iMWCMDReady (iDstWCmdReady ),
.oMWriteData (oDstWriteData ),
.oMWriteLast (oDstWriteLast ),
.oMWriteValid (oDstWriteValid ),
.iMWriteReady (iDstWriteReady ),
.oMROpcode (oDstROpcode ),
.oMRTargetID (oDstRTargetID ),
.oMRSourceID (oDstRSourceID ),
.oMRAddress (oDstRAddress ),
.oMRLength (oDstRLength ),
.oMRCMDValid (oDstRCmdValid ),
.iMRCMDReady (iDstRCmdReady ),
.iMReadData (iDstReadData ),
.iMReadLast (iDstReadLast ),
.iMReadValid (iDstReadValid ),
.oMReadReady (oDstReadReady )
);
// Mux
CommandChannelMux
Inst_CommandChannelMux
(
.iClock (iClock ),
.iReset (iReset ),
.oDstWOpcode (wDPQWOpcode ),
.oDstWTargetID (wDPQWTargetID ),
.oDstWSourceID (wDPQWSourceID ),
.oDstWAddress (wDPQWAddress ),
.oDstWLength (wDPQWLength ),
.oDstWCmdValid (wDPQWCmdValid ),
.iDstWCmdReady (wDPQWCmdReady ),
.oDstROpcode (wDPQROpcode ),
.oDstRTargetID (wDPQRTargetID ),
.oDstRSourceID (wDPQRSourceID ),
.oDstRAddress (wDPQRAddress ),
.oDstRLength (wDPQRLength ),
.oDstRCmdValid (wDPQRCmdValid ),
.iDstRCmdReady (wDPQRCmdReady ),
.oPCGWOpcode (oPCGWOpcode ),
.oPCGWTargetID (oPCGWTargetID ),
.oPCGWSourceID (oPCGWSourceID ),
.oPCGWAddress (oPCGWAddress ),
.oPCGWLength (oPCGWLength ),
.oPCGWCmdValid (oPCGWCmdValid ),
.iPCGWCmdReady (iPCGWCmdReady ),
.oPCGROpcode (oPCGROpcode ),
.oPCGRTargetID (oPCGRTargetID ),
.oPCGRSourceID (oPCGRSourceID ),
.oPCGRAddress (oPCGRAddress ),
.oPCGRLength (oPCGRLength ),
.oPCGRCmdValid (oPCGRCmdValid ),
.iPCGRCmdReady (iPCGRCmdReady ),
.iMuxSelect (wMuxSelect ),
.iMuxedWOpcode (wMuxedWOpcode ),
.iMuxedWTargetID(wMuxedWTargetID),
.iMuxedWSourceID(wMuxedWSourceID),
.iMuxedWAddress (wMuxedWAddress ),
.iMuxedWLength (wMuxedWLength ),
.iMuxedWCmdValid(wMuxedWCmdValid),
.oMuxedWCmdReady(wMuxedWCmdReady),
.iMuxedROpcode (wMuxedROpcode ),
.iMuxedRTargetID(wMuxedRTargetID),
.iMuxedRSourceID(wMuxedRSourceID),
.iMuxedRAddress (wMuxedRAddress ),
.iMuxedRLength (wMuxedRLength ),
.iMuxedRCmdValid(wMuxedRCmdValid),
.oMuxedRCmdReady(wMuxedRCmdReady)
);
// RegisterFile
Decoder
#
(
.OutputWidth(NumberOfWays)
)
Inst_WaySelector
(
.I(iWriteData ),
.O(wSelectedWay )
);
assign oReadData = rReadDataOut;
wire wReqQPushSignal ;
wire wReqLPQFull ;
wire wReqLPQPopSignal ;
wire wReqLPQEmpty ;
wire wReqLPQValid ;
wire wReqLPQReady ;
wire wReqHPQFull ;
wire wReqHPQPopSignal ;
wire wReqHPQEmpty ;
wire wReqHPQValid ;
wire wReqHPQReady ;
wire wReqQValid ;
wire wReqQReady ;
wire wReqQFull ;
wire wReqQEmpty ;
wire [7:0] wReqQCount ;
wire [3:0] wReqLPQCount;
wire [3:0] wReqHPQCount;
assign wReqQCount = {wReqHPQCount, wReqLPQCount};
localparam ReqQState_Idle = 1'b0 ;
localparam ReqQState_Push = 1'b1 ;
reg rReqQNextState;
reg rReqQCurState;
always @ (posedge iClock)
if (iReset)
rReqQCurState <= ReqQState_Idle;
else
rReqQCurState <= rReqQNextState;
always @ (*)
case (rReqQCurState)
ReqQState_Idle:
rReqQNextState <= (iWriteValid && (iWriteAddress[7:0] == 8'h00))?ReqQState_Push:ReqQState_Idle;
ReqQState_Push:
rReqQNextState <= (!wReqQFull)?ReqQState_Idle:ReqQState_Push;
endcase
assign oWriteAck = (rReqQCurState == ReqQState_Idle);
assign wReqQFull = (rUProgramSelect[31])?wReqHPQFull:wReqLPQFull;
assign wReqQPushSignal = !wReqQFull && (rReqQCurState == ReqQState_Push);
always @ (*)
if (rReqQCurState == ReqQState_Idle)
rChStatus <= 1'b0;
else
rChStatus <= 1'b1;
DRSCFIFO_288x16_withCount
Inst_ReqQ_Low_Priority
(
.iClock (iClock ),
.iReset (iReset ),
.iPushData ({
rDataAddress ,
rSpareAddress ,
rErrCntAddress ,
rCmpltAddress ,
rRowAddress ,
rColAddress ,
rUserData ,
rWaySelection ,
rUProgramSelect[UProgSizeWidth - 1:0]
}),
.iPushEnable (wReqQPushSignal & !rUProgramSelect[31]),
.oIsFull (wReqLPQFull ),
.oPopData ({
wLPQDataAddress ,
wLPQSpareAddress ,
wLPQErrCntAddress ,
wLPQCmpltAddress ,
wLPQRowAddress ,
wLPQColAddress ,
wLPQUserData ,
wLPQWaySelection ,
wLPQUProgramSelect[UProgSizeWidth - 1:0]
}),
.iPopEnable (wReqLPQPopSignal ),
.oIsEmpty (wReqLPQEmpty ),
.oDataCount (wReqLPQCount )
);
AutoFIFOPopControl
Inst_ReqQ_Low_Priority_PopControl
(
.iClock (iClock ),
.iReset (iReset ),
.oPopSignal (wReqLPQPopSignal ),
.iEmpty (wReqLPQEmpty ),
.oValid (wReqLPQValid ),
.iReady (wReqLPQReady )
);
DRSCFIFO_288x16_withCount
Inst_ReqQ_High_Priority
(
.iClock (iClock ),
.iReset (iReset ),
.iPushData ({
rDataAddress ,
rSpareAddress ,
rErrCntAddress ,
rCmpltAddress ,
rRowAddress ,
rColAddress ,
rUserData ,
rWaySelection ,
rUProgramSelect[UProgSizeWidth - 1:0]
}),
.iPushEnable (wReqQPushSignal & rUProgramSelect[31]),
.oIsFull (wReqHPQFull ),
.oPopData ({
wHPQDataAddress ,
wHPQSpareAddress ,
wHPQErrCntAddress ,
wHPQCmpltAddress ,
wHPQRowAddress ,
wHPQColAddress ,
wHPQUserData ,
wHPQWaySelection ,
wHPQUProgramSelect[UProgSizeWidth - 1:0]
}),
.iPopEnable (wReqHPQPopSignal ),
.oIsEmpty (wReqHPQEmpty ),
.oDataCount (wReqHPQCount )
);
AutoFIFOPopControl
Inst_ReqQ_High_Priority_PopControl
(
.iClock (iClock ),
.iReset (iReset ),
.oPopSignal (wReqHPQPopSignal ),
.iEmpty (wReqHPQEmpty ),
.oValid (wReqHPQValid ),
.iReady (wReqHPQReady )
);
assign wDataAddress = (wReqHPQValid)?wHPQDataAddress :wLPQDataAddress ;
assign wSpareAddress = (wReqHPQValid)?wHPQSpareAddress :wLPQSpareAddress ;
assign wErrCntAddress = (wReqHPQValid)?wHPQErrCntAddress :wLPQErrCntAddress ;
assign wCmpltAddress = (wReqHPQValid)?wHPQCmpltAddress :wLPQCmpltAddress ;
assign wRowAddress = (wReqHPQValid)?wHPQRowAddress :wLPQRowAddress ;
assign wColAddress = (wReqHPQValid)?wHPQColAddress :wLPQColAddress ;
assign wUserData = (wReqHPQValid)?wHPQUserData :wLPQUserData ;
assign wWaySelection = (wReqHPQValid)?wHPQWaySelection :wLPQWaySelection ;
assign wUProgramSelect = (wReqHPQValid)?wHPQUProgramSelect:wLPQUProgramSelect;
assign wReqQValid = (wReqHPQValid)?wReqHPQValid:wReqLPQValid;
assign wReqHPQReady = (wReqHPQValid)?wReqQReady:0;
assign wReqLPQReady = (wReqHPQValid)?0:wReqQReady;
assign wReqQEmpty = (wReqHPQValid)?wReqHPQEmpty:wReqLPQEmpty;
wire [31:0] wIdleTimeCounter;
TimeCounter
LLNFCIdleTimeCounter
(
.iClock (iClock ),
.iReset (iReset ),
.iEnabled (1'b1 ),
.iPeriodSetting (iWriteData ),
.iSettingValid (iWriteValid && oWriteAck & (iWriteAddress == 8'h30)),
.iProbe (iPCGWCmdReady ),
.oCountValue (wIdleTimeCounter )
);
always @ (posedge iClock)
if (iReset)
begin
rUProgramSelect <= {(UProgSizeWidth){1'b0}};
rRowAddress <= 24'b0;
rColAddress <= 16'b0;
rUserData <= 32'h12341234;
rDataAddress <= {(AddressWidth){1'b0}};
rSpareAddress <= {(AddressWidth){1'b0}};
rErrCntAddress <= {(AddressWidth){1'b0}};
rCmpltAddress <= {(AddressWidth){1'b0}};
rWaySelection <= 1'b1;
rPipeliningMode <= 1'b0;
end
else
begin
if (iWriteValid && oWriteAck)
case (iWriteAddress[7:0])
1'h00:
rUProgramSelect <= iWriteData;
8'h04:
rRowAddress <= iWriteData;
8'h08:
rUserData <= iWriteData;
8'h0C:
rDataAddress <= iWriteData;
8'h10:
rSpareAddress <= iWriteData;
8'h14:
rErrCntAddress <= iWriteData;
8'h18:
rCmpltAddress <= iWriteData;
8'h1C:
rWaySelection <= wSelectedWay;
8'h28:
rColAddress <= iWriteData;
8'h38:
rPipeliningMode <= iWriteData[0];
endcase
end
always @ (posedge iClock)
if (iReset)
rReadDataOut <= {(DataWidth){1'b0}};
else
if (iReadValid)
begin
case (iReadAddress[7:0])
8'h00:
rReadDataOut <= rUProgramSelect ;
8'h04:
rReadDataOut <= rRowAddress ;
8'h08:
rReadDataOut <= rUserData ;
8'h0C:
rReadDataOut <= rDataAddress ;
8'h10:
rReadDataOut <= rSpareAddress ;
8'h14:
rReadDataOut <= rErrCntAddress ;
8'h18:
rReadDataOut <= rCmpltAddress ;
8'h1C:
rReadDataOut <= rWaySelection ;
8'h20:
rReadDataOut <= rChStatus ;
8'h24:
rReadDataOut <= iWaysReadybusy ;
8'h28:
rReadDataOut <= rColAddress ;
8'h2C:
rReadDataOut <= !rChStatus & wReqQEmpty & (iPCGWCmdReady != 1'b0);
8'h30:
rReadDataOut <= wIdleTimeCounter ;
8'h34:
rReadDataOut <= wReqQCount ;
8'h38:
rReadDataOut <= rPipeliningMode ;
endcase
end
reg rReadAck ;
always @ (posedge iClock)
if (iReset)
rReadAck <= 1'b0;
else
if (!rReadAck && iReadValid)
rReadAck <= 1'b1;
else
rReadAck <= 1'b0;
assign oReadAck = rReadAck;
uProgROM
#
(
.ProgWordWidth (ProgWordWidth ),
.UProgSize (UProgSize )
)
Inst_uProgROM
(
.iClock (iClock ),
.iReset (iReset ),
.iNewProgCursor (wUProgramSelect),
.iNewProgCursorValid (rUProgSelValid ),
.oProgData (wUProgData ),
.oProgDataValid (wUProgDataValid),
.iProgDataReady (wUProgDataReady),
.oROMClock (oROMClock ),
.oROMReset (oROMReset ),
.oROMAddr (oROMAddr ),
.oROMRW (oROMRW ),
.oROMEnable (oROMEnable ),
.oROMWData (oROMWData ),
.iROMRData (iROMRData )
);
reg [2:0] rCurState ;
reg [2:0] rNextState ;
localparam UPFunc_Halt = 4'b0000;
localparam UPFunc_WriteCmd = 4'b0001;
localparam UPFunc_ReadCmd = 4'b0010;
localparam UPFunc_Uptrans = 4'b0100;
localparam UPFunc_Downtrans = 4'b1000;
wire [3:0] wRegdUPFunc ;
wire wRegdUPChSelect ;
wire [5:0] wRegdUPOpcode ;
wire [4:0] wRegdUPSourceID ;
wire [4:0] wRegdUPTargetID ;
wire [InnerIFLengthWidth - 1:0] wRegdUPLength ;
wire [3:0] wRegdUPAddrSrcRegSel ;
wire [3:0] wUPFunc ;
wire wUPChSelect ;
wire [5:0] wUPOpcode ;
wire [4:0] wUPSourceID ;
wire [4:0] wUPTargetID ;
wire [InnerIFLengthWidth - 1:0] wUPLength ;
wire [3:0] wUPAddrSrcRegSel ;
wire wUptrfLenQPushSignal ;
wire wUptrfLenQFull ;
wire wUptrfLenQPopSignal ;
wire wUptrfLenQEmpty ;
wire [InnerIFLengthWidth - 1:0] wUptrfLenQLength ;
wire wUptrfLenQValid ;
wire wUptrfLenQReady ;
wire wDntrfLenQPushSignal ;
wire wDntrfLenQFull ;
wire wDntrfLenQPopSignal ;
wire wDntrfLenQEmpty ;
wire [InnerIFLengthWidth - 1:0] wDntrfLenQLength ;
wire wDntrfLenQValid ;
wire wDntrfLenQReady ;
assign
{
wRegdUPChSelect ,
wRegdUPAddrSrcRegSel,
wRegdUPOpcode ,
wRegdUPSourceID ,
wRegdUPTargetID ,
wRegdUPLength ,
wRegdUPFunc
} = rUProgData;
assign
{
wUPChSelect ,
wUPAddrSrcRegSel,
wUPOpcode ,
wUPSourceID ,
wUPTargetID ,
wUPLength ,
wUPFunc
} = wUProgData;
assign wMuxSelect = wRegdUPChSelect;
always @ (posedge iClock)
if (iReset)
rCurState <= State_Halt;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Halt:
rNextState <= (wReqQValid)?State_FirstFetch:State_Halt;
State_FirstFetch:
rNextState <= State_Decode;
State_Decode:
begin
if (wUProgDataValid)
case (wUPFunc)
UPFunc_WriteCmd:
rNextState <= State_WritecmdToModule;
UPFunc_ReadCmd:
rNextState <= State_ReadcmdToModule;
UPFunc_Uptrans:
rNextState <= State_UpTransfer;
UPFunc_Downtrans:
rNextState <= State_DownTransfer;
default:
rNextState <= State_NextRequest;
endcase
else
rNextState <= State_Decode;
end
State_WritecmdToModule:
rNextState <= (wMuxedWCmdReady)?State_Decode:State_WritecmdToModule;
State_ReadcmdToModule:
rNextState <= (wMuxedRCmdReady)?State_Decode:State_ReadcmdToModule;
State_UpTransfer:
rNextState <= (!wUptrfLenQFull)?State_Decode:State_UpTransfer;
State_DownTransfer:
rNextState <= (!wDntrfLenQFull)?State_Decode:State_DownTransfer;
State_NextRequest:
rNextState <= (rPipeliningMode | iPCGWCmdReady)?State_Halt:State_NextRequest;
default:
rNextState <= State_Halt;
endcase
assign wReqQReady = (rNextState == State_Halt);
always @ (posedge iClock)
if (iReset)
rUProgSelValid <= 1'b0;
else
if (!rUProgSelValid && rCurState == State_Halt && wReqQValid)
rUProgSelValid <= 1'b1;
else
rUProgSelValid <= 1'b0;
assign wUProgDataReady = (rCurState == State_Decode);
always @ (posedge iClock)
if (iReset)
rUProgData <= {(ProgWordWidth){1'b0}};
else
case (rCurState)
State_Decode:
if (wUProgDataValid)
rUProgData <= wUProgData;
endcase
always @ (posedge iClock)
if (iReset)
rRegDataOut <= {(DataWidth){1'b0}};
else
begin
if (rCurState == State_Decode)
case (wUPAddrSrcRegSel)
0:
rRegDataOut <= {(DataWidth){1'b0}} ;
1:
rRegDataOut <= wRowAddress ; // Row Address
2:
rRegDataOut <= wUserData ;
3:
rRegDataOut <= wDataAddress ;
4:
rRegDataOut <= wSpareAddress ;
5:
rRegDataOut <= wErrCntAddress ;
6:
rRegDataOut <= wCmpltAddress ;
7:
rRegDataOut <= wWaySelection ;
8:
rRegDataOut <= wColAddress ;
endcase
end
assign wMuxedWOpcode = wRegdUPOpcode ;
assign wMuxedWTargetID = wRegdUPTargetID ;
assign wMuxedWSourceID = wRegdUPSourceID ;
assign wMuxedWAddress = rRegDataOut ;
assign wMuxedWLength = wRegdUPLength ;
assign wMuxedWCmdValid = (rCurState == State_WritecmdToModule);
assign wMuxedROpcode = wRegdUPOpcode ;
assign wMuxedRTargetID = wRegdUPTargetID ;
assign wMuxedRSourceID = wRegdUPSourceID ;
assign wMuxedRAddress = rRegDataOut ;
assign wMuxedRLength = wRegdUPLength ;
assign wMuxedRCmdValid = (rCurState == State_ReadcmdToModule);
assign wUptrfLenQPushSignal = (rCurState == State_UpTransfer) && !wUptrfLenQFull;
SCFIFO_64x64_withCount
Inst_UptrfLenQ
(
.iClock (iClock ),
.iReset (iReset ),
.iPushData (wRegdUPLength ),
.iPushEnable (wUptrfLenQPushSignal ),
.oIsFull (wUptrfLenQFull ),
.oPopData (wUptrfLenQLength ),
.iPopEnable (wUptrfLenQPopSignal ),
.oIsEmpty (wUptrfLenQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_UptrfLenQAutoPop
(
.iClock (iClock ),
.iReset (iReset ),
.oPopSignal (wUptrfLenQPopSignal ),
.iEmpty (wUptrfLenQEmpty ),
.oValid (wUptrfLenQValid ),
.iReady (wUptrfLenQReady )
);
DataDriver
#
(
.DataWidth (32 ),
.LengthWidth (InnerIFLengthWidth )
)
Inst_UptrfDataDriver
(
.CLK (iClock ),
.RESET (iReset ),
.SRCLEN (wUptrfLenQLength ),
.SRCVALID (wUptrfLenQValid ),
.SRCREADY (wUptrfLenQReady ),
.DATA (iPCGReadData ),
.DVALID (iPCGReadValid ),
.DREADY (oPCGReadReady ),
.XDATA (wDPQWriteData ),
.XDVALID (wDPQWriteValid ),
.XDREADY (wDPQWriteReady ),
.XDLAST (wDPQWriteLast )
);
assign wDntrfLenQPushSignal = (rCurState == State_DownTransfer) && !wDntrfLenQFull;
SCFIFO_64x64_withCount
Inst_DntrfLenQ
(
.iClock (iClock ),
.iReset (iReset ),
.iPushData (wRegdUPLength ),
.iPushEnable (wDntrfLenQPushSignal ),
.oIsFull (wDntrfLenQFull ),
.oPopData (wDntrfLenQLength ),
.iPopEnable (wDntrfLenQPopSignal ),
.oIsEmpty (wDntrfLenQEmpty ),
.oDataCount ( )
);
AutoFIFOPopControl
Inst_DntrfLenQAutoPop
(
.iClock (iClock ),
.iReset (iReset ),
.oPopSignal (wDntrfLenQPopSignal ),
.iEmpty (wDntrfLenQEmpty ),
.oValid (wDntrfLenQValid ),
.iReady (wDntrfLenQReady )
);
DataDriver
#
(
.DataWidth (32 ),
.LengthWidth (InnerIFLengthWidth )
)
Inst_DntrfDataDriver
(
.CLK (iClock ),
.RESET (iReset ),
.SRCLEN (wDntrfLenQLength ),
.SRCVALID (wDntrfLenQValid ),
.SRCREADY (wDntrfLenQReady ),
.DATA (wDPQReadData ),
.DVALID (wDPQReadValid ),
.DREADY (wDPQReadReady ),
.XDATA (oPCGWriteData ),
.XDVALID (oPCGWriteValid ),
.XDREADY (iPCGWriteReady ),
.XDLAST (oPCGWriteLast )
);
endmodule |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 25100 $
// $Date: 2011-09-01 18:44:19 +0000 (Thu, 01 Sep 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (WRITE FIRST)
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
DOA_R <= `BSV_ASSIGNMENT_DELAY DIA;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
DOB_R <= `BSV_ASSIGNMENT_DELAY DIB;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
// Output drivers
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule // BRAM2
|
module soc_system (
clk_clk,
hps_0_f2h_cold_reset_req_reset_n,
hps_0_f2h_debug_reset_req_reset_n,
hps_0_f2h_stm_hw_events_stm_hwevents,
hps_0_f2h_warm_reset_req_reset_n,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n);
input clk_clk;
input hps_0_f2h_cold_reset_req_reset_n;
input hps_0_f2h_debug_reset_req_reset_n;
input [27:0] hps_0_f2h_stm_hw_events_stm_hwevents;
input hps_0_f2h_warm_reset_req_reset_n;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.0 Build 214 3/25/2004 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.fbin (),
.pllena (),
.clkswitch (),
.areset (),
.pfdena (),
.clkena (),
.extclkena (),
.scanclk (),
.scanaclr (),
.scandata (),
.scanread (),
.scanwrite (),
.extclk (),
.clkbad (),
.activeclock (),
.locked (),
.clkloss (),
.scandataout (),
.scandone (),
.sclkout1 (),
.sclkout0 (),
.enable0 (),
.enable1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 1,
altpll_component.inclk0_input_frequency = 20833,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.clk0_time_delay = "0",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "-3000";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: TIME_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_0 STRING "inclk;fbin;pllena;clkswitch;areset"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_1 STRING "pfdena;clkena;extclkena;scanclk;scanaclr"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_2 STRING "scandata;scanread;scanwrite;clk;extclk"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "528.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_3 STRING "clkbad;activeclock;locked;clkloss;scandataout"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "48.000"
// Retrieval info: PRIVATE: MEGAFN_PORT_INFO_4 STRING "scandone;sclkout1;sclkout0;enable0;enable1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20833"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_TIME_DELAY STRING "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_4_V
`define SKY130_FD_SC_MS__A21BOI_4_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a21boi_4 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_4_V
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_log CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=34 WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="LEFT" WIDTH=64 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources = reg 65
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altbarrel_shift_qud
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [63:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 64'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[383:320];
assign
dir_w = {dir_pipe[0], dir_w[4:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {sbit_piper1d, smux_w[319:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_s5_double_altbarrel_shift_qud
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" SHIFTDIR="LEFT" WIDTH=128 WIDTHDIST=7 data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altbarrel_shift_edb
(
data,
distance,
result) ;
input [127:0] data;
input [6:0] distance;
output [127:0] result;
wire [7:0] dir_w;
wire direction_w;
wire [63:0] pad_w;
wire [1023:0] sbit_w;
wire [6:0] sel_w;
wire [895:0] smux_w;
assign
dir_w = {dir_w[6:0], direction_w},
direction_w = 1'b0,
pad_w = {64{1'b0}},
result = sbit_w[1023:896],
sbit_w = {smux_w[895:0], data},
sel_w = {distance[6:0]},
smux_w = {((({128{(sel_w[6] & (~ dir_w[6]))}} & {sbit_w[831:768], pad_w[63:0]}) | ({128{(sel_w[6] & dir_w[6])}} & {pad_w[63:0], sbit_w[895:832]})) | ({128{(~ sel_w[6])}} & sbit_w[895:768])), ((({128{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[735:640], pad_w[31:0]}) | ({128{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[767:672]})) | ({128{(~ sel_w[5])}} & sbit_w[767:640])), ((({128{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[623:512], pad_w[15:0]}) | ({128{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[639:528]})) | ({128{(~ sel_w[4])}} & sbit_w[639:512])), ((({128{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[503:384], pad_w[7:0]}) | ({128{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[511:392]})) | ({128{(~ sel_w[3])}} & sbit_w[511:384])), ((({128{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[379:256], pad_w[3:0]}) | ({128{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[383:260]})) | ({128{(~ sel_w[2])}} & sbit_w[383:256])), ((({128{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[253:128], pad_w[1:0]}) | ({128{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[255:130]})) | ({128{(~ sel_w[1])}} & sbit_w[255:128])), ((({128{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[126:0], pad_w[0]}) | ({128{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[127:1]})) | ({128{(~ sel_w[0])}} & sbit_w[127:0]))};
endmodule //acl_fp_log_s5_double_altbarrel_shift_edb
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=1 SHIFTDIR="RIGHT" WIDTH=64 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources = reg 65
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altbarrel_shift_d2e
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [63:0] data;
input [5:0] distance;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [0:0] dir_pipe;
reg [63:0] sbit_piper1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [447:0] sbit_w;
wire [5:0] sel_w;
wire [383:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 1'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 64'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[383:320];
assign
dir_w = {dir_pipe[0], dir_w[4:0], direction_w},
direction_w = 1'b1,
pad_w = {32{1'b0}},
result = sbit_w[447:384],
sbit_w = {sbit_piper1d, smux_w[319:0], data},
sel_w = {distance[5:0]},
smux_w = {((({64{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[351:320], pad_w[31:0]}) | ({64{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[383:352]})) | ({64{(~ sel_w[5])}} & sbit_w[383:320])), ((({64{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[303:256], pad_w[15:0]}) | ({64{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[319:272]})) | ({64{(~ sel_w[4])}} & sbit_w[319:256])), ((({64{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[247:192], pad_w[7:0]}) | ({64{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[255:200]})) | ({64{(~ sel_w[3])}} & sbit_w[255:192])), ((({64{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[187:128], pad_w[3:0]}) | ({64{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[191:132]})) | ({64{(~ sel_w[2])}} & sbit_w[191:128])), ((({64{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[125:64], pad_w[1:0]}) | ({64{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[127:66]})) | ({64{(~ sel_w[1])}} & sbit_w[127:64])), ((({64{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[62:0], pad_w[0]}) | ({64{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[63:1]})) | ({64{(~ sel_w[0])}} & sbit_w[63:0]))};
endmodule //acl_fp_log_s5_double_altbarrel_shift_d2e
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="AND" PIPELINE=3 WIDTH=11 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_and_or_rab
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [10:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [10:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [10:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[10], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[9] & connection_r0_w[10]), (operation_r1_w[8] & connection_r0_w[9]), (operation_r1_w[7] & connection_r0_w[8]), (operation_r1_w[6] & connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] & connection_r0_w[5]), (operation_r1_w[3] & connection_r0_w[4]), (operation_r1_w[2] & connection_r0_w[3]), (operation_r1_w[1] & connection_r0_w[2]), (operation_r1_w[0] & connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] & connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_s5_double_altfp_log_and_or_rab
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=11 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 4
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_and_or_98b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [10:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] connection_dffe0;
reg [0:0] connection_dffe1;
reg connection_dffe2;
wire [10:0] connection_r0_w;
wire [1:0] connection_r1_w;
wire [0:0] connection_r2_w;
wire [10:0] operation_r1_w;
wire [1:0] operation_r2_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 2'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[10], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 1'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[1]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= connection_r2_w[0];
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
operation_r1_w = {(operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
result = connection_dffe2;
endmodule //acl_fp_log_s5_double_altfp_log_and_or_98b
//altfp_log_and_or CBX_AUTO_BLACKBOX="ALL" LUT_INPUT_COUNT=6 OPERATION="OR" PIPELINE=3 WIDTH=52 aclr clken clock data result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = reg 12
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_and_or_e8b
(
aclr,
clken,
clock,
data,
result) ;
input aclr;
input clken;
input clock;
input [51:0] data;
output result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [51:0] data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [8:0] connection_dffe0;
reg [1:0] connection_dffe1;
reg [0:0] connection_dffe2;
wire [51:0] connection_r0_w;
wire [8:0] connection_r1_w;
wire [1:0] connection_r2_w;
wire [0:0] connection_r3_w;
wire [51:0] operation_r1_w;
wire [8:0] operation_r2_w;
wire [1:0] operation_r3_w;
// synopsys translate_off
initial
connection_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe0 <= 9'b0;
else if (clken == 1'b1) connection_dffe0 <= {operation_r1_w[51], operation_r1_w[47], operation_r1_w[41], operation_r1_w[35], operation_r1_w[29], operation_r1_w[23], operation_r1_w[17], operation_r1_w[11], operation_r1_w[5]};
// synopsys translate_off
initial
connection_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe1 <= 2'b0;
else if (clken == 1'b1) connection_dffe1 <= {operation_r2_w[8], operation_r2_w[5]};
// synopsys translate_off
initial
connection_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) connection_dffe2 <= 1'b0;
else if (clken == 1'b1) connection_dffe2 <= {operation_r3_w[1]};
assign
connection_r0_w = data,
connection_r1_w = connection_dffe0,
connection_r2_w = connection_dffe1,
connection_r3_w = connection_dffe2,
operation_r1_w = {(operation_r1_w[50] | connection_r0_w[51]), (operation_r1_w[49] | connection_r0_w[50]), (operation_r1_w[48] | connection_r0_w[49]), connection_r0_w[48], (operation_r1_w[46] | connection_r0_w[47]), (operation_r1_w[45] | connection_r0_w[46]), (operation_r1_w[44] | connection_r0_w[45]), (operation_r1_w[43] | connection_r0_w[44]), (operation_r1_w[42] | connection_r0_w[43]), connection_r0_w[42], (operation_r1_w[40] | connection_r0_w[41]), (operation_r1_w[39] | connection_r0_w[40]), (operation_r1_w[38] | connection_r0_w[39]), (operation_r1_w[37] | connection_r0_w[38]), (operation_r1_w[36] | connection_r0_w[37]), connection_r0_w[36], (operation_r1_w[34] | connection_r0_w[35]), (operation_r1_w[33] | connection_r0_w[34]), (operation_r1_w[32] | connection_r0_w[33]), (operation_r1_w[31] | connection_r0_w[32]), (operation_r1_w[30] | connection_r0_w[31]), connection_r0_w[30], (operation_r1_w[28] | connection_r0_w[29]), (operation_r1_w[27] | connection_r0_w[28]), (operation_r1_w[26] | connection_r0_w[27]), (operation_r1_w[25] | connection_r0_w[26]), (operation_r1_w[24] | connection_r0_w[25]), connection_r0_w[24], (operation_r1_w[22] | connection_r0_w[23]), (operation_r1_w[21] | connection_r0_w[22]), (operation_r1_w[20] | connection_r0_w[21]), (operation_r1_w[19] | connection_r0_w[20]), (operation_r1_w[18] | connection_r0_w[19]), connection_r0_w[18], (operation_r1_w[16] | connection_r0_w[17]), (operation_r1_w[15] | connection_r0_w[16]), (operation_r1_w[14] | connection_r0_w[15]), (operation_r1_w[13] | connection_r0_w[14]), (operation_r1_w[12] | connection_r0_w[13]), connection_r0_w[12], (operation_r1_w[10] | connection_r0_w[11]), (operation_r1_w[9] | connection_r0_w[10]), (operation_r1_w[8] | connection_r0_w[9]), (operation_r1_w[7] | connection_r0_w[8]), (operation_r1_w[6] | connection_r0_w[7]), connection_r0_w[6], (operation_r1_w[4] | connection_r0_w[5]), (operation_r1_w[3] | connection_r0_w[4]), (operation_r1_w[2] | connection_r0_w[3]), (operation_r1_w[1] | connection_r0_w[2]), (operation_r1_w[0] | connection_r0_w[1]
), connection_r0_w[0]},
operation_r2_w = {(operation_r2_w[7] | connection_r1_w[8]), (operation_r2_w[6] | connection_r1_w[7]), connection_r1_w[6], (operation_r2_w[4] | connection_r1_w[5]), (operation_r2_w[3] | connection_r1_w[4]), (operation_r2_w[2] | connection_r1_w[3]), (operation_r2_w[1] | connection_r1_w[2]), (operation_r2_w[0] | connection_r1_w[1]), connection_r1_w[0]},
operation_r3_w = {(operation_r3_w[0] | connection_r2_w[1]), connection_r2_w[0]},
result = connection_r3_w[0];
endmodule //acl_fp_log_s5_double_altfp_log_and_or_e8b
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=83 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_r0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [82:0] dataa;
input [82:0] datab;
output [82:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [82:0] dataa;
tri0 [82:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [41:0] wire_csa_lower_result;
wire [40:0] wire_csa_upper0_result;
wire [40:0] wire_csa_upper1_result;
wire [82:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[41:0]),
.datab(datab[41:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 42,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[82:42]),
.datab(datab[82:42]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 41,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[82:42]),
.datab(datab[82:42]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 41,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({41{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({41{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_r0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=63 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_p0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [62:0] dataa;
input [62:0] datab;
output [62:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [62:0] dataa;
tri0 [62:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [30:0] wire_csa_upper0_result;
wire [30:0] wire_csa_upper1_result;
wire [62:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[62:32]),
.datab(datab[62:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 31,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[62:32]),
.datab(datab[62:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 31,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({31{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({31{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_p0e
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=11 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_aoc
(
dataa,
datab,
result) ;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [10:0] dataa;
tri0 [10:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [10:0] wire_add_sub1_result;
wire [10:0] result_w;
lpm_add_sub add_sub1
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "SUB",
add_sub1.lpm_representation = "UNSIGNED",
add_sub1.lpm_width = 11,
add_sub1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub1_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_aoc
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=26 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_i4b
(
dataa,
datab,
result) ;
input [25:0] dataa;
input [25:0] datab;
output [25:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [25:0] dataa;
tri0 [25:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [12:0] wire_csa_lower_result;
wire [12:0] wire_csa_upper0_result;
wire [12:0] wire_csa_upper1_result;
wire [25:0] result_w;
lpm_add_sub csa_lower
(
.cout(wire_csa_lower_cout),
.dataa(dataa[12:0]),
.datab(datab[12:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 13,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.cin(1'b0),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 13,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.cin(1'b1),
.cout(),
.dataa(dataa[25:13]),
.datab(datab[25:13]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 13,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({13{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({13{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_i4b
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=7 dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_vmc
(
dataa,
datab,
result) ;
input [6:0] dataa;
input [6:0] datab;
output [6:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [6:0] dataa;
tri0 [6:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] wire_add_sub2_result;
wire [6:0] result_w;
lpm_add_sub add_sub2
(
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "SUB",
add_sub2.lpm_representation = "UNSIGNED",
add_sub2.lpm_width = 7,
add_sub2.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub2_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_vmc
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_plf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [54:0] wire_add_sub3_result;
wire [54:0] result_w;
lpm_add_sub add_sub3
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_pipeline = 1,
add_sub3.lpm_representation = "UNSIGNED",
add_sub3.lpm_width = 55,
add_sub3.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub3_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_plf
//altfp_log_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=11 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_ilf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [10:0] dataa;
input [10:0] datab;
output [10:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [10:0] dataa;
tri0 [10:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [10:0] wire_add_sub4_result;
wire [10:0] result_w;
lpm_add_sub add_sub4
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "SUB",
add_sub4.lpm_pipeline = 2,
add_sub4.lpm_representation = "UNSIGNED",
add_sub4.lpm_width = 11,
add_sub4.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub4_result;
endmodule //acl_fp_log_s5_double_altfp_log_csa_ilf
//altfp_log_rr_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" WIDTH_ALMOSTLOG=83 WIDTH_Y0=54 WIDTH_Z=55 a0_in aclr almostlog clk_en clock y0_in z
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=60 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_m0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [59:0] dataa;
input [59:0] datab;
output [59:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [59:0] dataa;
tri0 [59:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [29:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [59:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[29:0]),
.datab(datab[29:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 30,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_m0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=69 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_v0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [68:0] dataa;
input [68:0] datab;
output [68:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [68:0] dataa;
tri0 [68:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [33:0] wire_csa_upper0_result;
wire [33:0] wire_csa_upper1_result;
wire [68:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 34,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 34,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({34{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({34{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_v0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=70 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_n0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [69:0] dataa;
input [69:0] datab;
output [69:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [69:0] dataa;
tri0 [69:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [34:0] wire_csa_upper0_result;
wire [34:0] wire_csa_upper1_result;
wire [69:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 35,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 35,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({35{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({35{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_n0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=67 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_t0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [66:0] dataa;
input [66:0] datab;
output [66:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [66:0] dataa;
tri0 [66:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [33:0] wire_csa_lower_result;
wire [32:0] wire_csa_upper0_result;
wire [32:0] wire_csa_upper1_result;
wire [66:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[33:0]),
.datab(datab[33:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 34,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 33,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 33,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({33{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({33{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_t0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=64 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_q0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [63:0] dataa;
tri0 [63:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [31:0] wire_csa_upper0_result;
wire [31:0] wire_csa_upper1_result;
wire [63:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 32,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 32,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({32{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({32{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_q0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=61 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_o0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [60:0] datab;
output [60:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [60:0] dataa;
tri0 [60:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [30:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [60:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[30:0]),
.datab(datab[30:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 31,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_o0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=58 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_u0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [57:0] dataa;
input [57:0] datab;
output [57:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [57:0] dataa;
tri0 [57:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [28:0] wire_csa_lower_result;
wire [28:0] wire_csa_upper0_result;
wire [28:0] wire_csa_upper1_result;
wire [57:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[28:0]),
.datab(datab[28:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 29,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 29,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 29,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({29{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({29{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_u0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_s0e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [27:0] wire_csa_lower_result;
wire [26:0] wire_csa_upper0_result;
wire [26:0] wire_csa_upper1_result;
wire [54:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[27:0]),
.datab(datab[27:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "ADD",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 28,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "ADD",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 27,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "ADD",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 27,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({27{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({27{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_s0e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=60 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_n1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [59:0] dataa;
input [59:0] datab;
output [59:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [59:0] dataa;
tri0 [59:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [29:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [59:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[29:0]),
.datab(datab[29:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 30,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[59:30]),
.datab(datab[59:30]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_n1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=69 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_02e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [68:0] dataa;
input [68:0] datab;
output [68:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [68:0] dataa;
tri0 [68:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [33:0] wire_csa_upper0_result;
wire [33:0] wire_csa_upper1_result;
wire [68:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 34,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[68:35]),
.datab(datab[68:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 34,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({34{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({34{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_02e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=70 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_o1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [69:0] dataa;
input [69:0] datab;
output [69:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [69:0] dataa;
tri0 [69:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [34:0] wire_csa_lower_result;
wire [34:0] wire_csa_upper0_result;
wire [34:0] wire_csa_upper1_result;
wire [69:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[34:0]),
.datab(datab[34:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 35,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 35,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[69:35]),
.datab(datab[69:35]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 35,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({35{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({35{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_o1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=67 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_u1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [66:0] dataa;
input [66:0] datab;
output [66:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [66:0] dataa;
tri0 [66:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [33:0] wire_csa_lower_result;
wire [32:0] wire_csa_upper0_result;
wire [32:0] wire_csa_upper1_result;
wire [66:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[33:0]),
.datab(datab[33:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 34,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 33,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[66:34]),
.datab(datab[66:34]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 33,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({33{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({33{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_u1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=64 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_r1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [63:0] dataa;
input [63:0] datab;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [63:0] dataa;
tri0 [63:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [31:0] wire_csa_lower_result;
wire [31:0] wire_csa_upper0_result;
wire [31:0] wire_csa_upper1_result;
wire [63:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[31:0]),
.datab(datab[31:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 32,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 32,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[63:32]),
.datab(datab[63:32]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 32,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({32{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({32{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_r1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=61 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_p1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [60:0] datab;
output [60:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [60:0] dataa;
tri0 [60:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [30:0] wire_csa_lower_result;
wire [29:0] wire_csa_upper0_result;
wire [29:0] wire_csa_upper1_result;
wire [60:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[30:0]),
.datab(datab[30:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 31,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 30,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[60:31]),
.datab(datab[60:31]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 30,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({30{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({30{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_p1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=58 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_v1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [57:0] dataa;
input [57:0] datab;
output [57:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [57:0] dataa;
tri0 [57:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [28:0] wire_csa_lower_result;
wire [28:0] wire_csa_upper0_result;
wire [28:0] wire_csa_upper1_result;
wire [57:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[28:0]),
.datab(datab[28:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 29,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 29,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[57:29]),
.datab(datab[57:29]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 29,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({29{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({29{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_v1e
//altfp_log_csa CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="SUB" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=55 aclr clken clock dataa datab result
//VERSION_BEGIN 12.0 cbx_altbarrel_shift 2012:05:31:20:08:02:SJ cbx_altfp_log 2012:05:31:20:08:02:SJ cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_altsquare 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_lpm_compare 2012:05:31:20:08:02:SJ cbx_lpm_mult 2012:05:31:20:08:02:SJ cbx_lpm_mux 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_padd 2012:05:31:20:08:02:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ cbx_util_mgl 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_csa_s1e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [54:0] dataa;
input [54:0] datab;
output [54:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [54:0] dataa;
tri0 [54:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_csa_lower_cout;
wire [27:0] wire_csa_lower_result;
wire [26:0] wire_csa_upper0_result;
wire [26:0] wire_csa_upper1_result;
wire [54:0] result_w;
lpm_add_sub csa_lower
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(wire_csa_lower_cout),
.dataa(dataa[27:0]),
.datab(datab[27:0]),
.overflow(),
.result(wire_csa_lower_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_lower.lpm_direction = "SUB",
csa_lower.lpm_pipeline = 1,
csa_lower.lpm_representation = "UNSIGNED",
csa_lower.lpm_width = 28,
csa_lower.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper0
(
.aclr(aclr),
.cin(1'b0),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper0.lpm_direction = "SUB",
csa_upper0.lpm_pipeline = 1,
csa_upper0.lpm_representation = "UNSIGNED",
csa_upper0.lpm_width = 27,
csa_upper0.lpm_type = "lpm_add_sub";
lpm_add_sub csa_upper1
(
.aclr(aclr),
.cin(1'b1),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa[54:28]),
.datab(datab[54:28]),
.overflow(),
.result(wire_csa_upper1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
csa_upper1.lpm_direction = "SUB",
csa_upper1.lpm_pipeline = 1,
csa_upper1.lpm_representation = "UNSIGNED",
csa_upper1.lpm_width = 27,
csa_upper1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = {(({27{(~ wire_csa_lower_cout)}} & wire_csa_upper0_result) | ({27{wire_csa_lower_cout}} & wire_csa_upper1_result)), wire_csa_lower_result};
endmodule //acl_fp_log_s5_double_altfp_log_csa_s1e
//synthesis_resources = lpm_add_sub 72 lpm_mult 9 lpm_mux 10 reg 2344
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_range_reduction_3sd
(
a0_in,
aclr,
almostlog,
clk_en,
clock,
y0_in,
z) ;
input [4:0] a0_in;
input aclr;
output [82:0] almostlog;
input clk_en;
input clock;
input [53:0] y0_in;
output [54:0] z;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [82:0] wire_add0_1_result;
wire [82:0] wire_add0_2_result;
wire [82:0] wire_add0_3_result;
wire [82:0] wire_add0_4_result;
wire [82:0] wire_add0_5_result;
wire [82:0] wire_add0_6_result;
wire [82:0] wire_add0_7_result;
wire [82:0] wire_add0_8_result;
wire [59:0] wire_add1_1_result;
wire [68:0] wire_add1_2_result;
wire [69:0] wire_add1_3_result;
wire [66:0] wire_add1_4_result;
wire [63:0] wire_add1_5_result;
wire [60:0] wire_add1_6_result;
wire [57:0] wire_add1_7_result;
wire [54:0] wire_add1_8_result;
wire [59:0] wire_sub1_1_result;
wire [68:0] wire_sub1_2_result;
wire [69:0] wire_sub1_3_result;
wire [66:0] wire_sub1_4_result;
wire [63:0] wire_sub1_5_result;
wire [60:0] wire_sub1_6_result;
wire [57:0] wire_sub1_7_result;
wire [54:0] wire_sub1_8_result;
reg [4:0] A_pipe0_reg0;
reg [4:0] A_pipe0_reg1;
reg [3:0] A_wire1_reg0;
reg [3:0] A_wire2_reg0;
reg [3:0] A_wire3_reg0;
reg [3:0] A_wire4_reg0;
reg [3:0] A_wire5_reg0;
reg [3:0] A_wire6_reg0;
reg [3:0] A_wire7_reg0;
reg [3:0] A_wire8_reg0;
reg [49:0] B_wire1_reg0;
reg [55:0] B_wire2_reg0;
reg [64:0] B_wire3_reg0;
reg [65:0] B_wire4_reg0;
reg [62:0] B_wire5_reg0;
reg [59:0] B_wire6_reg0;
reg [56:0] B_wire7_reg0;
reg [53:0] B_wire8_reg0;
reg [82:0] S_pipe22_reg0;
reg [82:0] S_pipe23_reg0;
reg [82:0] S_pipe24_reg0;
reg [82:0] S_pipe25_reg0;
reg [82:0] S_pipe26_reg0;
reg [82:0] S_pipe27_reg0;
reg [82:0] S_pipe28_reg0;
reg [82:0] S_pipe29_reg0;
reg [82:0] S_wire1_reg0;
reg [82:0] S_wire2_reg0;
reg [82:0] S_wire3_reg0;
reg [82:0] S_wire4_reg0;
reg [82:0] S_wire5_reg0;
reg [82:0] S_wire6_reg0;
reg [82:0] S_wire7_reg0;
reg [82:0] S_wire8_reg0;
reg [53:0] Z_wire1_reg0;
reg [59:0] Z_wire2_reg0;
reg [68:0] Z_wire3_reg0;
reg [69:0] Z_wire4_reg0;
reg [66:0] Z_wire5_reg0;
reg [63:0] Z_wire6_reg0;
reg [60:0] Z_wire7_reg0;
reg [57:0] Z_wire8_reg0;
wire [59:0] wire_mult0_result;
wire [57:0] wire_mult1_result;
wire [63:0] wire_mult2_result;
wire [66:0] wire_mult3_result;
wire [60:0] wire_mult4_result;
wire [54:0] wire_mult5_result;
wire [48:0] wire_mult6_result;
wire [42:0] wire_mult7_result;
wire [36:0] wire_mult8_result;
wire [5:0] wire_InvTable0_result;
wire [82:0] wire_LogTable0_result;
wire [78:0] wire_LogTable1_result;
wire [75:0] wire_LogTable2_result;
wire [72:0] wire_LogTable3_result;
wire [69:0] wire_LogTable4_result;
wire [66:0] wire_LogTable5_result;
wire [63:0] wire_LogTable6_result;
wire [60:0] wire_LogTable7_result;
wire [57:0] wire_LogTable8_result;
wire [3:0] A1_is_all_zero;
wire [3:0] A1_is_not_zero;
wire [3:0] A_all_zero2;
wire [3:0] A_all_zero3;
wire [3:0] A_all_zero4;
wire [3:0] A_all_zero5;
wire [3:0] A_all_zero6;
wire [3:0] A_all_zero7;
wire [3:0] A_all_zero8;
wire [4:0] A_pipe0;
wire [3:0] A_pipe11;
wire [3:0] A_pipe12;
wire [3:0] A_pipe13;
wire [3:0] A_pipe14;
wire [3:0] A_pipe15;
wire [3:0] A_pipe16;
wire [3:0] A_pipe17;
wire [3:0] A_pipe18;
wire [4:0] A_wire0;
wire [3:0] A_wire1;
wire [3:0] A_wire2;
wire [3:0] A_wire3;
wire [3:0] A_wire4;
wire [3:0] A_wire5;
wire [3:0] A_wire6;
wire [3:0] A_wire7;
wire [3:0] A_wire8;
wire [59:0] B_pad_wire1;
wire [68:0] B_pad_wire2;
wire [69:0] B_pad_wire3;
wire [66:0] B_pad_wire4;
wire [63:0] B_pad_wire5;
wire [60:0] B_pad_wire6;
wire [57:0] B_pad_wire7;
wire [54:0] B_pad_wire8;
wire [49:0] B_pipe1;
wire [55:0] B_pipe2;
wire [64:0] B_pipe3;
wire [65:0] B_pipe4;
wire [62:0] B_pipe5;
wire [59:0] B_pipe6;
wire [56:0] B_pipe7;
wire [53:0] B_pipe8;
wire [49:0] B_wire1;
wire [55:0] B_wire2;
wire [64:0] B_wire3;
wire [65:0] B_wire4;
wire [62:0] B_wire5;
wire [59:0] B_wire6;
wire [56:0] B_wire7;
wire [53:0] B_wire8;
wire [59:0] epsZ_pad_wire1;
wire [68:0] epsZ_pad_wire2;
wire [69:0] epsZ_pad_wire3;
wire [66:0] epsZ_pad_wire4;
wire [63:0] epsZ_pad_wire5;
wire [60:0] epsZ_pad_wire6;
wire [57:0] epsZ_pad_wire7;
wire [54:0] epsZ_pad_wire8;
wire [59:0] epsZ_wire1;
wire [68:0] epsZ_wire2;
wire [80:0] epsZ_wire3;
wire [84:0] epsZ_wire4;
wire [84:0] epsZ_wire5;
wire [84:0] epsZ_wire6;
wire [84:0] epsZ_wire7;
wire [84:0] epsZ_wire8;
wire [5:0] InvA0;
wire [82:0] L_wire0;
wire [78:0] L_wire1;
wire [75:0] L_wire2;
wire [72:0] L_wire3;
wire [69:0] L_wire4;
wire [66:0] L_wire5;
wire [63:0] L_wire6;
wire [60:0] L_wire7;
wire [57:0] L_wire8;
wire [59:0] mux0_data0;
wire [59:0] mux0_data1;
wire [59:0] P_pad_wire1;
wire [68:0] P_pad_wire2;
wire [69:0] P_pad_wire3;
wire [66:0] P_pad_wire4;
wire [63:0] P_pad_wire5;
wire [60:0] P_pad_wire6;
wire [57:0] P_pad_wire7;
wire [54:0] P_pad_wire8;
wire [59:0] P_wire0;
wire [57:0] P_wire1;
wire [63:0] P_wire2;
wire [66:0] P_wire3;
wire [60:0] P_wire4;
wire [54:0] P_wire5;
wire [48:0] P_wire6;
wire [42:0] P_wire7;
wire [36:0] P_wire8;
wire [82:0] S_pipe11;
wire [82:0] S_pipe12;
wire [82:0] S_pipe13;
wire [82:0] S_pipe14;
wire [82:0] S_pipe15;
wire [82:0] S_pipe16;
wire [82:0] S_pipe17;
wire [82:0] S_pipe18;
wire [82:0] S_pipe22;
wire [82:0] S_pipe23;
wire [82:0] S_pipe24;
wire [82:0] S_pipe25;
wire [82:0] S_pipe26;
wire [82:0] S_pipe27;
wire [82:0] S_pipe28;
wire [82:0] S_pipe29;
wire [82:0] S_wire1;
wire [82:0] S_wire2;
wire [82:0] S_wire3;
wire [82:0] S_wire4;
wire [82:0] S_wire5;
wire [82:0] S_wire6;
wire [82:0] S_wire7;
wire [82:0] S_wire8;
wire [82:0] S_wire9;
wire [53:0] Z_pipe1;
wire [59:0] Z_pipe2;
wire [68:0] Z_pipe3;
wire [69:0] Z_pipe4;
wire [66:0] Z_pipe5;
wire [63:0] Z_pipe6;
wire [60:0] Z_pipe7;
wire [57:0] Z_pipe8;
wire [53:0] Z_wire1;
wire [59:0] Z_wire2;
wire [68:0] Z_wire3;
wire [69:0] Z_wire4;
wire [66:0] Z_wire5;
wire [63:0] Z_wire6;
wire [60:0] Z_wire7;
wire [57:0] Z_wire8;
wire [54:0] Z_wire9;
wire [53:0] ZM_wire1;
wire [59:0] ZM_wire2;
wire [62:0] ZM_wire3;
wire [56:0] ZM_wire4;
wire [50:0] ZM_wire5;
wire [44:0] ZM_wire6;
wire [38:0] ZM_wire7;
wire [32:0] ZM_wire8;
acl_fp_log_s5_double_altfp_log_csa_r0e add0_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe11),
.datab({{4{1'b0}}, L_wire1}),
.result(wire_add0_1_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe12),
.datab({{7{1'b0}}, L_wire2}),
.result(wire_add0_2_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe13),
.datab({{10{1'b0}}, L_wire3}),
.result(wire_add0_3_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe14),
.datab({{13{1'b0}}, L_wire4}),
.result(wire_add0_4_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe15),
.datab({{16{1'b0}}, L_wire5}),
.result(wire_add0_5_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe16),
.datab({{19{1'b0}}, L_wire6}),
.result(wire_add0_6_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe17),
.datab({{22{1'b0}}, L_wire7}),
.result(wire_add0_7_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add0_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(S_pipe18),
.datab({{25{1'b0}}, L_wire8}),
.result(wire_add0_8_result));
acl_fp_log_s5_double_altfp_log_csa_m0e add1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire1),
.datab(epsZ_pad_wire1),
.result(wire_add1_1_result));
acl_fp_log_s5_double_altfp_log_csa_v0e add1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire2),
.datab(epsZ_pad_wire2),
.result(wire_add1_2_result));
acl_fp_log_s5_double_altfp_log_csa_n0e add1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire3),
.datab(epsZ_pad_wire3),
.result(wire_add1_3_result));
acl_fp_log_s5_double_altfp_log_csa_t0e add1_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire4),
.datab(epsZ_pad_wire4),
.result(wire_add1_4_result));
acl_fp_log_s5_double_altfp_log_csa_q0e add1_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire5),
.datab(epsZ_pad_wire5),
.result(wire_add1_5_result));
acl_fp_log_s5_double_altfp_log_csa_o0e add1_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire6),
.datab(epsZ_pad_wire6),
.result(wire_add1_6_result));
acl_fp_log_s5_double_altfp_log_csa_u0e add1_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire7),
.datab(epsZ_pad_wire7),
.result(wire_add1_7_result));
acl_fp_log_s5_double_altfp_log_csa_s0e add1_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(B_pad_wire8),
.datab(epsZ_pad_wire8),
.result(wire_add1_8_result));
acl_fp_log_s5_double_altfp_log_csa_n1e sub1_1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_1_result),
.datab(P_pad_wire1),
.result(wire_sub1_1_result));
acl_fp_log_s5_double_altfp_log_csa_02e sub1_2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_2_result),
.datab(P_pad_wire2),
.result(wire_sub1_2_result));
acl_fp_log_s5_double_altfp_log_csa_o1e sub1_3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_3_result),
.datab(P_pad_wire3),
.result(wire_sub1_3_result));
acl_fp_log_s5_double_altfp_log_csa_u1e sub1_4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_4_result),
.datab(P_pad_wire4),
.result(wire_sub1_4_result));
acl_fp_log_s5_double_altfp_log_csa_r1e sub1_5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_5_result),
.datab(P_pad_wire5),
.result(wire_sub1_5_result));
acl_fp_log_s5_double_altfp_log_csa_p1e sub1_6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_6_result),
.datab(P_pad_wire6),
.result(wire_sub1_6_result));
acl_fp_log_s5_double_altfp_log_csa_v1e sub1_7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_7_result),
.datab(P_pad_wire7),
.result(wire_sub1_7_result));
acl_fp_log_s5_double_altfp_log_csa_s1e sub1_8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_add1_8_result),
.datab(P_pad_wire8),
.result(wire_sub1_8_result));
// synopsys translate_off
initial
A_pipe0_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg0 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg0 <= A_pipe0;
// synopsys translate_off
initial
A_pipe0_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_pipe0_reg1 <= 5'b0;
else if (clk_en == 1'b1) A_pipe0_reg1 <= A_pipe0_reg0;
// synopsys translate_off
initial
A_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire1_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire1_reg0 <= A_wire1;
// synopsys translate_off
initial
A_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire2_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire2_reg0 <= A_wire2;
// synopsys translate_off
initial
A_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire3_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire3_reg0 <= A_wire3;
// synopsys translate_off
initial
A_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire4_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire4_reg0 <= A_wire4;
// synopsys translate_off
initial
A_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire5_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire5_reg0 <= A_wire5;
// synopsys translate_off
initial
A_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire6_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire6_reg0 <= A_wire6;
// synopsys translate_off
initial
A_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire7_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire7_reg0 <= A_wire7;
// synopsys translate_off
initial
A_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) A_wire8_reg0 <= 4'b0;
else if (clk_en == 1'b1) A_wire8_reg0 <= A_wire8;
// synopsys translate_off
initial
B_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire1_reg0 <= 50'b0;
else if (clk_en == 1'b1) B_wire1_reg0 <= B_wire1;
// synopsys translate_off
initial
B_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire2_reg0 <= 56'b0;
else if (clk_en == 1'b1) B_wire2_reg0 <= B_wire2;
// synopsys translate_off
initial
B_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire3_reg0 <= 65'b0;
else if (clk_en == 1'b1) B_wire3_reg0 <= B_wire3;
// synopsys translate_off
initial
B_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire4_reg0 <= 66'b0;
else if (clk_en == 1'b1) B_wire4_reg0 <= B_wire4;
// synopsys translate_off
initial
B_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire5_reg0 <= 63'b0;
else if (clk_en == 1'b1) B_wire5_reg0 <= B_wire5;
// synopsys translate_off
initial
B_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire6_reg0 <= 60'b0;
else if (clk_en == 1'b1) B_wire6_reg0 <= B_wire6;
// synopsys translate_off
initial
B_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire7_reg0 <= 57'b0;
else if (clk_en == 1'b1) B_wire7_reg0 <= B_wire7;
// synopsys translate_off
initial
B_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) B_wire8_reg0 <= 54'b0;
else if (clk_en == 1'b1) B_wire8_reg0 <= B_wire8;
// synopsys translate_off
initial
S_pipe22_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe22_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe22_reg0 <= S_pipe22;
// synopsys translate_off
initial
S_pipe23_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe23_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe23_reg0 <= S_pipe23;
// synopsys translate_off
initial
S_pipe24_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe24_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe24_reg0 <= S_pipe24;
// synopsys translate_off
initial
S_pipe25_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe25_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe25_reg0 <= S_pipe25;
// synopsys translate_off
initial
S_pipe26_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe26_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe26_reg0 <= S_pipe26;
// synopsys translate_off
initial
S_pipe27_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe27_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe27_reg0 <= S_pipe27;
// synopsys translate_off
initial
S_pipe28_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe28_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe28_reg0 <= S_pipe28;
// synopsys translate_off
initial
S_pipe29_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_pipe29_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_pipe29_reg0 <= S_pipe29;
// synopsys translate_off
initial
S_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire1_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire1_reg0 <= S_wire1;
// synopsys translate_off
initial
S_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire2_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire2_reg0 <= S_wire2;
// synopsys translate_off
initial
S_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire3_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire3_reg0 <= S_wire3;
// synopsys translate_off
initial
S_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire4_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire4_reg0 <= S_wire4;
// synopsys translate_off
initial
S_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire5_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire5_reg0 <= S_wire5;
// synopsys translate_off
initial
S_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire6_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire6_reg0 <= S_wire6;
// synopsys translate_off
initial
S_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire7_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire7_reg0 <= S_wire7;
// synopsys translate_off
initial
S_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) S_wire8_reg0 <= 83'b0;
else if (clk_en == 1'b1) S_wire8_reg0 <= S_wire8;
// synopsys translate_off
initial
Z_wire1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire1_reg0 <= 54'b0;
else if (clk_en == 1'b1) Z_wire1_reg0 <= Z_wire1;
// synopsys translate_off
initial
Z_wire2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire2_reg0 <= 60'b0;
else if (clk_en == 1'b1) Z_wire2_reg0 <= Z_wire2;
// synopsys translate_off
initial
Z_wire3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire3_reg0 <= 69'b0;
else if (clk_en == 1'b1) Z_wire3_reg0 <= Z_wire3;
// synopsys translate_off
initial
Z_wire4_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire4_reg0 <= 70'b0;
else if (clk_en == 1'b1) Z_wire4_reg0 <= Z_wire4;
// synopsys translate_off
initial
Z_wire5_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire5_reg0 <= 67'b0;
else if (clk_en == 1'b1) Z_wire5_reg0 <= Z_wire5;
// synopsys translate_off
initial
Z_wire6_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire6_reg0 <= 64'b0;
else if (clk_en == 1'b1) Z_wire6_reg0 <= Z_wire6;
// synopsys translate_off
initial
Z_wire7_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire7_reg0 <= 61'b0;
else if (clk_en == 1'b1) Z_wire7_reg0 <= Z_wire7;
// synopsys translate_off
initial
Z_wire8_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z_wire8_reg0 <= 58'b0;
else if (clk_en == 1'b1) Z_wire8_reg0 <= Z_wire8;
lpm_mult mult0
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(InvA0),
.datab(y0_in),
.result(wire_mult0_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult0.lpm_pipeline = 2,
mult0.lpm_representation = "UNSIGNED",
mult0.lpm_widtha = 6,
mult0.lpm_widthb = 54,
mult0.lpm_widthp = 60,
mult0.lpm_type = "lpm_mult";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire1),
.datab(ZM_wire1),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 2,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 4,
mult1.lpm_widthb = 54,
mult1.lpm_widthp = 58,
mult1.lpm_type = "lpm_mult";
lpm_mult mult2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire2),
.datab(ZM_wire2),
.result(wire_mult2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult2.lpm_pipeline = 2,
mult2.lpm_representation = "UNSIGNED",
mult2.lpm_widtha = 4,
mult2.lpm_widthb = 60,
mult2.lpm_widthp = 64,
mult2.lpm_type = "lpm_mult";
lpm_mult mult3
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire3),
.datab(ZM_wire3),
.result(wire_mult3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult3.lpm_pipeline = 2,
mult3.lpm_representation = "UNSIGNED",
mult3.lpm_widtha = 4,
mult3.lpm_widthb = 63,
mult3.lpm_widthp = 67,
mult3.lpm_type = "lpm_mult";
lpm_mult mult4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire4),
.datab(ZM_wire4),
.result(wire_mult4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult4.lpm_pipeline = 2,
mult4.lpm_representation = "UNSIGNED",
mult4.lpm_widtha = 4,
mult4.lpm_widthb = 57,
mult4.lpm_widthp = 61,
mult4.lpm_type = "lpm_mult";
lpm_mult mult5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire5),
.datab(ZM_wire5),
.result(wire_mult5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult5.lpm_pipeline = 2,
mult5.lpm_representation = "UNSIGNED",
mult5.lpm_widtha = 4,
mult5.lpm_widthb = 51,
mult5.lpm_widthp = 55,
mult5.lpm_type = "lpm_mult";
lpm_mult mult6
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire6),
.datab(ZM_wire6),
.result(wire_mult6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult6.lpm_pipeline = 2,
mult6.lpm_representation = "UNSIGNED",
mult6.lpm_widtha = 4,
mult6.lpm_widthb = 45,
mult6.lpm_widthp = 49,
mult6.lpm_type = "lpm_mult";
lpm_mult mult7
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire7),
.datab(ZM_wire7),
.result(wire_mult7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult7.lpm_pipeline = 2,
mult7.lpm_representation = "UNSIGNED",
mult7.lpm_widtha = 4,
mult7.lpm_widthb = 39,
mult7.lpm_widthp = 43,
mult7.lpm_type = "lpm_mult";
lpm_mult mult8
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(A_wire8),
.datab(ZM_wire8),
.result(wire_mult8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult8.lpm_pipeline = 2,
mult8.lpm_representation = "UNSIGNED",
mult8.lpm_widtha = 4,
mult8.lpm_widthb = 33,
mult8.lpm_widthp = 37,
mult8.lpm_type = "lpm_mult";
lpm_mux InvTable0
(
.data({6'b100001, {2{6'b100010}}, {2{6'b100011}}, {2{6'b100100}}, 6'b100101, {2{6'b100110}}, 6'b100111, 6'b101000, {2{6'b101001}}, 6'b101010, 6'b101011, 6'b010110, {2{6'b010111}}, {2{6'b011000}}, {2{6'b011001}}, 6'b011010, {2{6'b011011}}, 6'b011100, 6'b011101, 6'b011110, 6'b011111, {2{6'b100000}}}),
.result(wire_InvTable0_result),
.sel(a0_in)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
InvTable0.lpm_size = 32,
InvTable0.lpm_width = 6,
InvTable0.lpm_widths = 5,
InvTable0.lpm_type = "lpm_mux";
lpm_mux LogTable0
(
.data({83'b11111000000111110101100100111100011000011111001100111111111011001100000111000001000, {2{83'b11110000011110101110011110011111111101110100111010101100110011110100000110011011011}}, {2{83'b11101001000011110010110101110101000110101001010010110100011001000001101101100110011}}, {2{83'b11100001110110001111100010010001110101010000110100011010000101100001010101111000001}}, 83'b11011010110101010101101000001111110000000001010110111001011001111111010001000111001, {2{83'b11010100000000011001111100011110101100001101100001011000011011110001100000111100000}}, 83'b11001101010110110100101011000110000101110101001010010111000100110111110110011111001, 83'b11000110111000000001000001110000110010101100101110111100101001111011010001001111111, {2{83'b11000000100011011100111100100101010000111000001110101010111001010101010101110011010}}, 83'b10111010011000101000110101010001010100010110011111000111111100011000110011100000110, 83'b10110100010111000111010100010100011110111000101100111101100011110100110011011011101, 83'b01011111111010111110100011101111011000000101010001101111101101111001101111110110110, {2{83'b01010100100010101011100000011100111000101000111101011111001110000100000010110010011}}, {2{83'b01001001101001011000100001000100110100110110111001001001111000001110111110101101110}}, {2{83'b00111111001100100011100011011001011001110110011011110010111110110011001010000011001}}, 83'b00110101001001111101101001111001000101011011001111000110110111100101011111010100111, {2{83'b00101011011111101000000011010110101010000111101101100011111101110000010100100101110}}, 83'b00100010001011110001110100000100010011111100100011110111101111000110011100010110100, 83'b00011001001100110101111001011101010110010100100110001000101011100001110101011110101, 83'b00010000100001011001100010110101100111100011101000000110100010001010001111111101100, 83'b00001000001000001010111011000100111100111010001000100010001110000000101110011110001, {2{{83{1'b0}}}}}),
.result(wire_LogTable0_result),
.sel(A_wire0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable0.lpm_size = 32,
LogTable0.lpm_width = 83,
LogTable0.lpm_widths = 5,
LogTable0.lpm_type = "lpm_mux";
lpm_mux LogTable1
(
.data({79'b1110011001011011100111100110111011101101100101100101110000110110111000001001111, 79'b1101010101110111100101101000011111011000100001111110000011010001101010011101110, 79'b1100010010100101010100001010010011111101100110100001100110101000101111101001011, 79'b1011001111100100101001111001011010100101110110101100001000001000001001111100110, 79'b1010001100110101011101101010000101101111000111110100110001100100010100100001000, 79'b1001001010010111100110010111110001101000110000011111010011010111000000010000110, 79'b1000001000001010111011000100111100111010001000100010001110000000101110011110001, 79'b0111000110001111010010111011000001010010101010111100011000110001111111001111010, 79'b0110100101010111110101010010001100010111000100001111110001111011000001101001011, 79'b0101100011110101100001011110000110100100001011110101011111100111000100101011001, 79'b0100100010100011111011000111111110101000101110001001111100011001010000100100110, 79'b0011100001100010111001110000100110001110101111100000110011000000001100010000010, 79'b0010100000110010010100111111001011010000011001011101111100011101010101110100000, 79'b0001100000010010000100100001010001011000011010110101010000001110000010100101110, 79'b0000100000000010000000001010101011101010110001000100111011110011100000110011100, {79{1'b0}}}),
.result(wire_LogTable1_result),
.sel(A_pipe11)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable1.lpm_size = 16,
LogTable1.lpm_width = 79,
LogTable1.lpm_widths = 4,
LogTable1.lpm_type = "lpm_mux";
lpm_mux LogTable2
(
.data({76'b1110100011010011001111110110100010100111001100001111110101111111001001110100, 76'b1101100010110111000011100000110011011110011000000001100101010100010111011111, 76'b1100100010011100111000111000001001010110011011011110010110000111001001101001, 76'b1011100010000100101111110100011010010111010101011001111111111010110110101110, 76'b1010100001101110101000001101011101011010010000110010101110000000011000110100, 76'b1001100001011010100001111011001010001001011110100101100010011110100100010001, 76'b1000100001001000011100110101011001000000001111100011110111011110011100000010, 76'b0111100000111000011000110100000011001010101110001001111110001111111000010011, 76'b0110100000101010010101101111000010100101111000010110011011111010110110000100, 76'b0101100000011110010011011110010001111111011001100010100011110001101001010111, 76'b0100100000010100010001111001101100110101100100011011101110111000101110000001, 76'b0011100000001100010000111001001111010111001100111101110000111000010101010011, 76'b0010100000000110010000010100110110100011100010001110001001101100110001111100, 76'b0001100000000010010000000100100000001010001000011000010100001001100101101001, 76'b0000100000000000010000000000001010101010110010101010110001000100010110011001, {76{1'b0}}}),
.result(wire_LogTable2_result),
.sel(A_pipe12)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable2.lpm_size = 16,
LogTable2.lpm_width = 76,
LogTable2.lpm_widths = 4,
LogTable2.lpm_type = "lpm_mux";
lpm_mux LogTable3
(
.data({73'b1110100000011010010010111111100011100010001000011011011101101010000110000, 73'b1101100000010110110010110011010010100001110101001111100011100100101010000, 73'b1100100000010011100010101000101101101010000101111010001111001010011101000, 73'b1011100000010000100010011111101100111001101100010011100100000000010101011, 73'b1010100000001101110010011000001000001111100000010100110000110100010101011, 73'b1001100000001011010010010001110111101010011111111000001001011100010001010, 73'b1000100000001001000010001100110011001001101110111001000000110100011100100, 73'b0111100000000111000010001000110010101100010111010011100010111110011110101, 73'b0110100000000101010010000101101110010001101001000100101111000000001111101, 73'b0101100000000011110010000011011101111000111010001010010001000010111100001, 73'b0100100000000010100010000001111001100001100110100010011100010010010000000, 73'b0011100000000001100010000000111001001011010000001100000100111011101010100, 73'b0010100000000000110010000000010100110101011111000110011010001101110111111, 73'b0001100000000000010010000000000100100000000001010001000000011000010011010, 73'b0000100000000000000010000000000000001010101010101011101010101010110001000, {73{1'b0}}}),
.result(wire_LogTable3_result),
.sel(A_pipe13)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable3.lpm_size = 16,
LogTable3.lpm_width = 73,
LogTable3.lpm_widths = 4,
LogTable3.lpm_type = "lpm_mux";
lpm_mux LogTable4
(
.data({70'b1110100000000011010010010000111111100001001010111010110111010010001000, 70'b1101100000000010110110010000110011010000110000001110000011100110010110, 70'b1100100000000010011100010000101000101100010110100101101010100001000110, 70'b1011100000000010000100010000011111101011111101110111111011111010011110, 70'b1010100000000001101110010000011000000111100101111011110111101011101101, 70'b1001100000000001011010010000010001110111001110101001001101101111000111, 70'b1000100000000001001000010000001100110010110111111000011101111111111111, 70'b0111100000000000111000010000001000110010100001100010111000011010100010, 70'b0110100000000000101010010000000101101110001011100010011100111011101110, 70'b0101100000000000011110010000000011011101110101110001111011100001010000, 70'b0100100000000000010100010000000001111001100000001100110100001001011100, 70'b0011100000000000001100010000000000111001001010101111010110110011000100, 70'b0010100000000000000110010000000000010100110101010110100011011101011010, 70'b0001100000000000000010010000000000000100100000000000001010001000000000, 70'b0000100000000000000000010000000000000000001010101010101010110010101010, {70{1'b0}}}),
.result(wire_LogTable4_result),
.sel(A_pipe14)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable4.lpm_size = 16,
LogTable4.lpm_width = 70,
LogTable4.lpm_widths = 4,
LogTable4.lpm_type = "lpm_mux";
lpm_mux LogTable5
(
.data({67'b1110100000000000011010010010000000111111100000111000000010000000101, 67'b1101100000000000010110110010000000110011010000100010000001101111110, 67'b1100100000000000010011100010000000101000101100001100001010000010001, 67'b1011100000000000010000100010000000011111101011110110011001101001111, 67'b1010100000000000001101110010000000011000000111100000101111011110110, 67'b1001100000000000001011010010000000010001110111001011001010011110111, 67'b1000100000000000001001000010000000001100110010110101101001101110010, 67'b0111100000000000000111000010000000001000110010100000001100010111000, 67'b0110100000000000000101010010000000000101101110001010110001101000111, 67'b0101100000000000000011110010000000000011011101110101011000111010000, 67'b0100100000000000000010100010000000000001111001100000000001100110100, 67'b0011100000000000000001100010000000000000111001001010101011010000001, 67'b0010100000000000000000110010000000000000010100110101010101011111000, 67'b0001100000000000000000010010000000000000000100100000000000000001010, 67'b0000100000000000000000000010000000000000000000001010101010101010101, {67{1'b0}}}),
.result(wire_LogTable5_result),
.sel(A_pipe15)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable5.lpm_size = 16,
LogTable5.lpm_width = 67,
LogTable5.lpm_widths = 4,
LogTable5.lpm_type = "lpm_mux";
lpm_mux LogTable6
(
.data({64'b1110100000000000000011010010010000000000111111100000110101101010, 64'b1101100000000000000010110110010000000000110011010000100000010000, 64'b1100100000000000000010011100010000000000101000101100001010110110, 64'b1011100000000000000010000100010000000000011111101011110101011101, 64'b1010100000000000000001101110010000000000011000000111100000000101, 64'b1001100000000000000001011010010000000000010001110111001010101110, 64'b1000100000000000000001001000010000000000001100110010110101010111, 64'b0111100000000000000000111000010000000000001000110010100000000001, 64'b0110100000000000000000101010010000000000000101101110001010101011, 64'b0101100000000000000000011110010000000000000011011101110101010101, 64'b0100100000000000000000010100010000000000000001111001100000000000, 64'b0011100000000000000000001100010000000000000000111001001010101010, 64'b0010100000000000000000000110010000000000000000010100110101010101, 64'b0001100000000000000000000010010000000000000000000100100000000000, 64'b0000100000000000000000000000010000000000000000000000001010101010, {64{1'b0}}}),
.result(wire_LogTable6_result),
.sel(A_pipe16)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable6.lpm_size = 16,
LogTable6.lpm_width = 64,
LogTable6.lpm_widths = 4,
LogTable6.lpm_type = "lpm_mux";
lpm_mux LogTable7
(
.data({61'b1110100000000000000000011010010010000000000000111111100000110, 61'b1101100000000000000000010110110010000000000000110011010000100, 61'b1100100000000000000000010011100010000000000000101000101100001, 61'b1011100000000000000000010000100010000000000000011111101011110, 61'b1010100000000000000000001101110010000000000000011000000111100, 61'b1001100000000000000000001011010010000000000000010001110111001, 61'b1000100000000000000000001001000010000000000000001100110010110, 61'b0111100000000000000000000111000010000000000000001000110010100, 61'b0110100000000000000000000101010010000000000000000101101110001, 61'b0101100000000000000000000011110010000000000000000011011101110, 61'b0100100000000000000000000010100010000000000000000001111001100, 61'b0011100000000000000000000001100010000000000000000000111001001, 61'b0010100000000000000000000000110010000000000000000000010100110, 61'b0001100000000000000000000000010010000000000000000000000100100, 61'b0000100000000000000000000000000010000000000000000000000000001, {61{1'b0}}}),
.result(wire_LogTable7_result),
.sel(A_pipe17)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable7.lpm_size = 16,
LogTable7.lpm_width = 61,
LogTable7.lpm_widths = 4,
LogTable7.lpm_type = "lpm_mux";
lpm_mux LogTable8
(
.data({58'b1110100000000000000000000011010010010000000000000000111111, 58'b1101100000000000000000000010110110010000000000000000110011, 58'b1100100000000000000000000010011100010000000000000000101000, 58'b1011100000000000000000000010000100010000000000000000011111, 58'b1010100000000000000000000001101110010000000000000000011000, 58'b1001100000000000000000000001011010010000000000000000010001, 58'b1000100000000000000000000001001000010000000000000000001100, 58'b0111100000000000000000000000111000010000000000000000001000, 58'b0110100000000000000000000000101010010000000000000000000101, 58'b0101100000000000000000000000011110010000000000000000000011, 58'b0100100000000000000000000000010100010000000000000000000001, 58'b0011100000000000000000000000001100010000000000000000000000, 58'b0010100000000000000000000000000110010000000000000000000000, 58'b0001100000000000000000000000000010010000000000000000000000, 58'b0000100000000000000000000000000000010000000000000000000000, {58{1'b0}}}),
.result(wire_LogTable8_result),
.sel(A_pipe18)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
LogTable8.lpm_size = 16,
LogTable8.lpm_width = 58,
LogTable8.lpm_widths = 4,
LogTable8.lpm_type = "lpm_mux";
assign
A1_is_all_zero = {(A_pipe11[3] | A1_is_all_zero[2]), (A_pipe11[2] | A1_is_all_zero[1]), (A_pipe11[1] | A1_is_all_zero[0]), A_pipe11[0]},
A1_is_not_zero = {((~ A_pipe11[3]) & A1_is_not_zero[2]), (A_pipe11[2] | A1_is_not_zero[1]), (A_pipe11[1] | A1_is_not_zero[0]), A_pipe11[0]},
A_all_zero2 = {((~ A_pipe12[3]) & A_all_zero2[2]), ((~ A_pipe12[2]) & A_all_zero2[1]), ((~ A_pipe12[1]) & A_all_zero2[0]), (~ A_pipe12[0])},
A_all_zero3 = {((~ A_pipe13[3]) & A_all_zero3[2]), ((~ A_pipe13[2]) & A_all_zero3[1]), ((~ A_pipe13[1]) & A_all_zero3[0]), (~ A_pipe13[0])},
A_all_zero4 = {((~ A_pipe14[3]) & A_all_zero4[2]), ((~ A_pipe14[2]) & A_all_zero4[1]), ((~ A_pipe14[1]) & A_all_zero4[0]), (~ A_pipe14[0])},
A_all_zero5 = {((~ A_pipe15[3]) & A_all_zero5[2]), ((~ A_pipe15[2]) & A_all_zero5[1]), ((~ A_pipe15[1]) & A_all_zero5[0]), (~ A_pipe15[0])},
A_all_zero6 = {((~ A_pipe16[3]) & A_all_zero6[2]), ((~ A_pipe16[2]) & A_all_zero6[1]), ((~ A_pipe16[1]) & A_all_zero6[0]), (~ A_pipe16[0])},
A_all_zero7 = {((~ A_pipe17[3]) & A_all_zero7[2]), ((~ A_pipe17[2]) & A_all_zero7[1]), ((~ A_pipe17[1]) & A_all_zero7[0]), (~ A_pipe17[0])},
A_all_zero8 = {((~ A_pipe18[3]) & A_all_zero8[2]), ((~ A_pipe18[2]) & A_all_zero8[1]), ((~ A_pipe18[1]) & A_all_zero8[0]), (~ A_pipe18[0])},
A_pipe0 = a0_in,
A_pipe11 = A_wire1_reg0,
A_pipe12 = A_wire2_reg0,
A_pipe13 = A_wire3_reg0,
A_pipe14 = A_wire4_reg0,
A_pipe15 = A_wire5_reg0,
A_pipe16 = A_wire6_reg0,
A_pipe17 = A_wire7_reg0,
A_pipe18 = A_wire8_reg0,
A_wire0 = A_pipe0_reg1,
A_wire1 = Z_wire1[53:50],
A_wire2 = Z_wire2[59:56],
A_wire3 = Z_wire3[68:65],
A_wire4 = Z_wire4[69:66],
A_wire5 = Z_wire5[66:63],
A_wire6 = Z_wire6[63:60],
A_wire7 = Z_wire7[60:57],
A_wire8 = Z_wire8[57:54],
almostlog = S_wire9,
B_pad_wire1 = {1'b0, B_pipe1, {9{1'b0}}},
B_pad_wire2 = {1'b0, B_pipe2, {12{1'b0}}},
B_pad_wire3 = {1'b0, B_pipe3, {4{1'b0}}},
B_pad_wire4 = {1'b0, B_pipe4},
B_pad_wire5 = {1'b0, B_pipe5},
B_pad_wire6 = {1'b0, B_pipe6},
B_pad_wire7 = {1'b0, B_pipe7},
B_pad_wire8 = {1'b0, B_pipe8},
B_pipe1 = B_wire1_reg0,
B_pipe2 = B_wire2_reg0,
B_pipe3 = B_wire3_reg0,
B_pipe4 = B_wire4_reg0,
B_pipe5 = B_wire5_reg0,
B_pipe6 = B_wire6_reg0,
B_pipe7 = B_wire7_reg0,
B_pipe8 = B_wire8_reg0,
B_wire1 = Z_wire1[49:0],
B_wire2 = Z_wire2[55:0],
B_wire3 = Z_wire3[64:0],
B_wire4 = Z_wire4[65:0],
B_wire5 = Z_wire5[62:0],
B_wire6 = Z_wire6[59:0],
B_wire7 = Z_wire7[56:0],
B_wire8 = Z_wire8[53:0],
epsZ_pad_wire1 = epsZ_wire1[59:0],
epsZ_pad_wire2 = epsZ_wire2[68:0],
epsZ_pad_wire3 = epsZ_wire3[80:11],
epsZ_pad_wire4 = epsZ_wire4[84:18],
epsZ_pad_wire5 = epsZ_wire5[84:21],
epsZ_pad_wire6 = epsZ_wire6[84:24],
epsZ_pad_wire7 = epsZ_wire7[84:27],
epsZ_pad_wire8 = epsZ_wire8[84:30],
epsZ_wire1 = ({60{A1_is_all_zero[3]}} & (({60{(~ A1_is_not_zero[3])}} & mux0_data0) | ({60{A1_is_not_zero[3]}} & mux0_data1))),
epsZ_wire2 = {1'b0, (~ A_all_zero2[3]), {7{1'b0}}, ({60{(~ A_all_zero2[3])}} & Z_pipe2)},
epsZ_wire3 = {1'b0, (~ A_all_zero3[3]), {10{1'b0}}, ({69{(~ A_all_zero3[3])}} & Z_pipe3)},
epsZ_wire4 = {1'b0, (~ A_all_zero4[3]), {13{1'b0}}, ({70{(~ A_all_zero4[3])}} & Z_pipe4)},
epsZ_wire5 = {1'b0, (~ A_all_zero5[3]), {16{1'b0}}, ({67{(~ A_all_zero5[3])}} & Z_pipe5)},
epsZ_wire6 = {1'b0, (~ A_all_zero6[3]), {19{1'b0}}, ({64{(~ A_all_zero6[3])}} & Z_pipe6)},
epsZ_wire7 = {1'b0, (~ A_all_zero7[3]), {22{1'b0}}, ({61{(~ A_all_zero7[3])}} & Z_pipe7)},
epsZ_wire8 = {1'b0, (~ A_all_zero8[3]), {25{1'b0}}, ({58{(~ A_all_zero8[3])}} & Z_pipe8)},
InvA0 = wire_InvTable0_result,
L_wire0 = wire_LogTable0_result,
L_wire1 = wire_LogTable1_result,
L_wire2 = wire_LogTable2_result,
L_wire3 = wire_LogTable3_result,
L_wire4 = wire_LogTable4_result,
L_wire5 = wire_LogTable5_result,
L_wire6 = wire_LogTable6_result,
L_wire7 = wire_LogTable7_result,
L_wire8 = wire_LogTable8_result,
mux0_data0 = {1'b1, {4{1'b0}}, Z_pipe1, 1'b0},
mux0_data1 = {1'b0, 1'b1, {4{1'b0}}, Z_pipe1},
P_pad_wire1 = {1'b0, P_wire1, 1'b0},
P_pad_wire2 = {{4{1'b0}}, P_wire2, 1'b0},
P_pad_wire3 = {{7{1'b0}}, P_wire3[66:4]},
P_pad_wire4 = {{10{1'b0}}, P_wire4[60:4]},
P_pad_wire5 = {{13{1'b0}}, P_wire5[54:4]},
P_pad_wire6 = {{16{1'b0}}, P_wire6[48:4]},
P_pad_wire7 = {{19{1'b0}}, P_wire7[42:4]},
P_pad_wire8 = {{22{1'b0}}, P_wire8[36:4]},
P_wire0 = wire_mult0_result,
P_wire1 = wire_mult1_result,
P_wire2 = wire_mult2_result,
P_wire3 = wire_mult3_result,
P_wire4 = wire_mult4_result,
P_wire5 = wire_mult5_result,
P_wire6 = wire_mult6_result,
P_wire7 = wire_mult7_result,
P_wire8 = wire_mult8_result,
S_pipe11 = S_wire1_reg0,
S_pipe12 = S_wire2_reg0,
S_pipe13 = S_wire3_reg0,
S_pipe14 = S_wire4_reg0,
S_pipe15 = S_wire5_reg0,
S_pipe16 = S_wire6_reg0,
S_pipe17 = S_wire7_reg0,
S_pipe18 = S_wire8_reg0,
S_pipe22 = wire_add0_1_result,
S_pipe23 = wire_add0_2_result,
S_pipe24 = wire_add0_3_result,
S_pipe25 = wire_add0_4_result,
S_pipe26 = wire_add0_5_result,
S_pipe27 = wire_add0_6_result,
S_pipe28 = wire_add0_7_result,
S_pipe29 = wire_add0_8_result,
S_wire1 = L_wire0,
S_wire2 = S_pipe22_reg0,
S_wire3 = S_pipe23_reg0,
S_wire4 = S_pipe24_reg0,
S_wire5 = S_pipe25_reg0,
S_wire6 = S_pipe26_reg0,
S_wire7 = S_pipe27_reg0,
S_wire8 = S_pipe28_reg0,
S_wire9 = S_pipe29_reg0,
z = Z_wire9,
Z_pipe1 = Z_wire1_reg0,
Z_pipe2 = Z_wire2_reg0,
Z_pipe3 = Z_wire3_reg0,
Z_pipe4 = Z_wire4_reg0,
Z_pipe5 = Z_wire5_reg0,
Z_pipe6 = Z_wire6_reg0,
Z_pipe7 = Z_wire7_reg0,
Z_pipe8 = Z_wire8_reg0,
Z_wire1 = P_wire0[53:0],
Z_wire2 = wire_sub1_1_result,
Z_wire3 = wire_sub1_2_result,
Z_wire4 = wire_sub1_3_result,
Z_wire5 = wire_sub1_4_result,
Z_wire6 = wire_sub1_5_result,
Z_wire7 = wire_sub1_6_result,
Z_wire8 = wire_sub1_7_result,
Z_wire9 = wire_sub1_8_result,
ZM_wire1 = Z_wire1,
ZM_wire2 = Z_wire2,
ZM_wire3 = Z_wire3[68:6],
ZM_wire4 = Z_wire4[69:13],
ZM_wire5 = Z_wire5[66:16],
ZM_wire6 = Z_wire6[63:19],
ZM_wire7 = Z_wire7[60:22],
ZM_wire8 = Z_wire8[57:25];
endmodule //acl_fp_log_s5_double_range_reduction_3sd
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=1 WIDTH=128 WIDTHAD=7 aclr clk_en clock data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_log_s5_double_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [0:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
acl_fp_log_s5_double_altpriority_encoder_3e8 altpriority_encoder15
(
.data(data[1:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
acl_fp_log_s5_double_altpriority_encoder_3e8 altpriority_encoder16
(
.data(data[3:2]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), ((wire_altpriority_encoder16_zero & wire_altpriority_encoder15_q) | ((~ wire_altpriority_encoder16_zero) & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [1:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
acl_fp_log_s5_double_altpriority_encoder_6e8 altpriority_encoder13
(
.data(data[3:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
acl_fp_log_s5_double_altpriority_encoder_6e8 altpriority_encoder14
(
.data(data[7:4]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({2{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({2{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [2:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
acl_fp_log_s5_double_altpriority_encoder_be8 altpriority_encoder11
(
.data(data[7:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
acl_fp_log_s5_double_altpriority_encoder_be8 altpriority_encoder12
(
.data(data[15:8]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({3{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({3{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_rf8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_log_s5_double_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder21_q;
wire [0:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
acl_fp_log_s5_double_altpriority_encoder_3v7 altpriority_encoder21
(
.data(data[1:0]),
.q(wire_altpriority_encoder21_q));
acl_fp_log_s5_double_altpriority_encoder_3e8 altpriority_encoder22
(
.data(data[3:2]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), ((wire_altpriority_encoder22_zero & wire_altpriority_encoder21_q) | ((~ wire_altpriority_encoder22_zero) & wire_altpriority_encoder22_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder19_q;
wire [1:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
acl_fp_log_s5_double_altpriority_encoder_6v7 altpriority_encoder19
(
.data(data[3:0]),
.q(wire_altpriority_encoder19_q));
acl_fp_log_s5_double_altpriority_encoder_6e8 altpriority_encoder20
(
.data(data[7:4]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({2{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({2{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder17_q;
wire [2:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
acl_fp_log_s5_double_altpriority_encoder_bv7 altpriority_encoder17
(
.data(data[7:0]),
.q(wire_altpriority_encoder17_q));
acl_fp_log_s5_double_altpriority_encoder_be8 altpriority_encoder18
(
.data(data[15:8]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), (({3{wire_altpriority_encoder18_zero}} & wire_altpriority_encoder17_q) | ({3{(~ wire_altpriority_encoder18_zero)}} & wire_altpriority_encoder18_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_r08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [3:0] wire_altpriority_encoder9_q;
acl_fp_log_s5_double_altpriority_encoder_rf8 altpriority_encoder10
(
.data(data[31:16]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
acl_fp_log_s5_double_altpriority_encoder_r08 altpriority_encoder9
(
.data(data[15:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({4{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({4{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_q08
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder23_q;
wire wire_altpriority_encoder23_zero;
wire [3:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
acl_fp_log_s5_double_altpriority_encoder_rf8 altpriority_encoder23
(
.data(data[15:0]),
.q(wire_altpriority_encoder23_q),
.zero(wire_altpriority_encoder23_zero));
acl_fp_log_s5_double_altpriority_encoder_rf8 altpriority_encoder24
(
.data(data[31:16]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
assign
q = {(~ wire_altpriority_encoder24_zero), (({4{wire_altpriority_encoder24_zero}} & wire_altpriority_encoder23_q) | ({4{(~ wire_altpriority_encoder24_zero)}} & wire_altpriority_encoder24_q))},
zero = (wire_altpriority_encoder23_zero & wire_altpriority_encoder24_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_qf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_309
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder7_q;
wire [4:0] wire_altpriority_encoder8_q;
wire wire_altpriority_encoder8_zero;
acl_fp_log_s5_double_altpriority_encoder_q08 altpriority_encoder7
(
.data(data[31:0]),
.q(wire_altpriority_encoder7_q));
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder8
(
.data(data[63:32]),
.q(wire_altpriority_encoder8_q),
.zero(wire_altpriority_encoder8_zero));
assign
q = {(~ wire_altpriority_encoder8_zero), (({5{wire_altpriority_encoder8_zero}} & wire_altpriority_encoder7_q) | ({5{(~ wire_altpriority_encoder8_zero)}} & wire_altpriority_encoder8_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_309
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" PIPELINE=0 WIDTH=64 WIDTHAD=6 data q zero
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_3f9
(
data,
q,
zero) ;
input [63:0] data;
output [5:0] q;
output zero;
wire [4:0] wire_altpriority_encoder25_q;
wire wire_altpriority_encoder25_zero;
wire [4:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder25
(
.data(data[31:0]),
.q(wire_altpriority_encoder25_q),
.zero(wire_altpriority_encoder25_zero));
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder26
(
.data(data[63:32]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero));
assign
q = {(~ wire_altpriority_encoder26_zero), (({5{wire_altpriority_encoder26_zero}} & wire_altpriority_encoder25_q) | ({5{(~ wire_altpriority_encoder26_zero)}} & wire_altpriority_encoder26_q))},
zero = (wire_altpriority_encoder25_zero & wire_altpriority_encoder26_zero);
endmodule //acl_fp_log_s5_double_altpriority_encoder_3f9
//synthesis_resources = reg 7
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_gla
(
aclr,
clk_en,
clock,
data,
q) ;
input aclr;
input clk_en;
input clock;
input [127:0] data;
output [6:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] wire_altpriority_encoder5_q;
wire [5:0] wire_altpriority_encoder6_q;
wire wire_altpriority_encoder6_zero;
reg [6:0] pipeline_q_dffe;
wire [6:0] tmp_q_wire;
acl_fp_log_s5_double_altpriority_encoder_309 altpriority_encoder5
(
.data(data[63:0]),
.q(wire_altpriority_encoder5_q));
acl_fp_log_s5_double_altpriority_encoder_3f9 altpriority_encoder6
(
.data(data[127:64]),
.q(wire_altpriority_encoder6_q),
.zero(wire_altpriority_encoder6_zero));
// synopsys translate_off
initial
pipeline_q_dffe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) pipeline_q_dffe <= 7'b0;
else if (clk_en == 1'b1) pipeline_q_dffe <= tmp_q_wire;
assign
q = pipeline_q_dffe,
tmp_q_wire = {(~ wire_altpriority_encoder6_zero), (({6{wire_altpriority_encoder6_zero}} & wire_altpriority_encoder5_q) | ({6{(~ wire_altpriority_encoder6_zero)}} & wire_altpriority_encoder6_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_gla
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 12.0 cbx_altpriority_encoder 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altpriority_encoder_018
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder27_q;
wire [4:0] wire_altpriority_encoder28_q;
wire wire_altpriority_encoder28_zero;
acl_fp_log_s5_double_altpriority_encoder_q08 altpriority_encoder27
(
.data(data[31:0]),
.q(wire_altpriority_encoder27_q));
acl_fp_log_s5_double_altpriority_encoder_qf8 altpriority_encoder28
(
.data(data[63:32]),
.q(wire_altpriority_encoder28_q),
.zero(wire_altpriority_encoder28_zero));
assign
q = {(~ wire_altpriority_encoder28_zero), (({5{wire_altpriority_encoder28_zero}} & wire_altpriority_encoder27_q) | ({5{(~ wire_altpriority_encoder28_zero)}} & wire_altpriority_encoder28_q))};
endmodule //acl_fp_log_s5_double_altpriority_encoder_018
//synthesis_resources = altsquare 1 lpm_add_sub 89 lpm_mult 10 lpm_mux 10 mux21 63 reg 4847
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_log_s5_double_altfp_log_o3b
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [63:0] wire_Lshiftsmall_result;
wire [127:0] wire_lzc_norm_L_result;
wire [63:0] wire_Rshiftsmall_result;
wire wire_exp_nan_result;
wire wire_exp_zero_result;
wire wire_man_inf_result;
wire wire_man_nan_result;
wire [82:0] wire_add1_result;
wire [62:0] wire_add2_result;
wire [10:0] wire_exp_biase_sub_result;
wire [25:0] wire_sub1_result;
wire [10:0] wire_sub2_result;
wire [6:0] wire_sub3_result;
wire [54:0] wire_sub4_result;
wire [10:0] wire_sub5_result;
wire [10:0] wire_sub6_result;
wire [82:0] wire_range_reduction_almostlog;
wire [54:0] wire_range_reduction_z;
wire [6:0] wire_lzc_norm_E_q;
wire [5:0] wire_lzoc_q;
wire [27:0] wire_squarer_result;
reg [67:0] absELog2_pipe_reg0;
reg [67:0] absELog2_pipe_reg1;
reg [67:0] absELog2_pipe_reg2;
reg [25:0] absZ0_pipe_reg0;
reg [25:0] absZ0_pipe_reg1;
reg [25:0] absZ0_pipe_reg10;
reg [25:0] absZ0_pipe_reg11;
reg [25:0] absZ0_pipe_reg12;
reg [25:0] absZ0_pipe_reg13;
reg [25:0] absZ0_pipe_reg14;
reg [25:0] absZ0_pipe_reg15;
reg [25:0] absZ0_pipe_reg16;
reg [25:0] absZ0_pipe_reg17;
reg [25:0] absZ0_pipe_reg18;
reg [25:0] absZ0_pipe_reg19;
reg [25:0] absZ0_pipe_reg2;
reg [25:0] absZ0_pipe_reg20;
reg [25:0] absZ0_pipe_reg21;
reg [25:0] absZ0_pipe_reg22;
reg [25:0] absZ0_pipe_reg23;
reg [25:0] absZ0_pipe_reg3;
reg [25:0] absZ0_pipe_reg4;
reg [25:0] absZ0_pipe_reg5;
reg [25:0] absZ0_pipe_reg6;
reg [25:0] absZ0_pipe_reg7;
reg [25:0] absZ0_pipe_reg8;
reg [25:0] absZ0_pipe_reg9;
reg [25:0] absZ0s_pipe1_reg0;
reg [25:0] absZ0s_pipe1_reg1;
reg [25:0] absZ0s_pipe1_reg2;
reg [25:0] absZ0s_pipe1_reg3;
reg [25:0] absZ0s_reg0;
reg [82:0] almostLog_pipe_reg0;
reg [82:0] almostLog_pipe_reg1;
reg [82:0] almostLog_pipe_reg2;
reg [0:0] doRR_reg0;
reg [0:0] doRR_reg1;
reg [10:0] E0_pipe_reg0;
reg [10:0] E0_pipe_reg1;
reg [10:0] E0_pipe_reg10;
reg [10:0] E0_pipe_reg11;
reg [10:0] E0_pipe_reg12;
reg [10:0] E0_pipe_reg13;
reg [10:0] E0_pipe_reg14;
reg [10:0] E0_pipe_reg15;
reg [10:0] E0_pipe_reg16;
reg [10:0] E0_pipe_reg17;
reg [10:0] E0_pipe_reg18;
reg [10:0] E0_pipe_reg19;
reg [10:0] E0_pipe_reg2;
reg [10:0] E0_pipe_reg20;
reg [10:0] E0_pipe_reg21;
reg [10:0] E0_pipe_reg22;
reg [10:0] E0_pipe_reg23;
reg [10:0] E0_pipe_reg3;
reg [10:0] E0_pipe_reg4;
reg [10:0] E0_pipe_reg5;
reg [10:0] E0_pipe_reg6;
reg [10:0] E0_pipe_reg7;
reg [10:0] E0_pipe_reg8;
reg [10:0] E0_pipe_reg9;
reg [5:0] E_normal_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg0;
reg [0:0] exp_is_ebiase_pipe_reg1;
reg [0:0] exp_is_ebiase_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg0;
reg [0:0] input_is_infinity_pipe_reg1;
reg [0:0] input_is_infinity_pipe_reg10;
reg [0:0] input_is_infinity_pipe_reg11;
reg [0:0] input_is_infinity_pipe_reg12;
reg [0:0] input_is_infinity_pipe_reg13;
reg [0:0] input_is_infinity_pipe_reg14;
reg [0:0] input_is_infinity_pipe_reg15;
reg [0:0] input_is_infinity_pipe_reg16;
reg [0:0] input_is_infinity_pipe_reg17;
reg [0:0] input_is_infinity_pipe_reg18;
reg [0:0] input_is_infinity_pipe_reg19;
reg [0:0] input_is_infinity_pipe_reg2;
reg [0:0] input_is_infinity_pipe_reg20;
reg [0:0] input_is_infinity_pipe_reg21;
reg [0:0] input_is_infinity_pipe_reg22;
reg [0:0] input_is_infinity_pipe_reg23;
reg [0:0] input_is_infinity_pipe_reg24;
reg [0:0] input_is_infinity_pipe_reg25;
reg [0:0] input_is_infinity_pipe_reg26;
reg [0:0] input_is_infinity_pipe_reg27;
reg [0:0] input_is_infinity_pipe_reg28;
reg [0:0] input_is_infinity_pipe_reg29;
reg [0:0] input_is_infinity_pipe_reg3;
reg [0:0] input_is_infinity_pipe_reg30;
reg [0:0] input_is_infinity_pipe_reg4;
reg [0:0] input_is_infinity_pipe_reg5;
reg [0:0] input_is_infinity_pipe_reg6;
reg [0:0] input_is_infinity_pipe_reg7;
reg [0:0] input_is_infinity_pipe_reg8;
reg [0:0] input_is_infinity_pipe_reg9;
reg [0:0] input_is_nan_pipe_reg0;
reg [0:0] input_is_nan_pipe_reg1;
reg [0:0] input_is_nan_pipe_reg10;
reg [0:0] input_is_nan_pipe_reg11;
reg [0:0] input_is_nan_pipe_reg12;
reg [0:0] input_is_nan_pipe_reg13;
reg [0:0] input_is_nan_pipe_reg14;
reg [0:0] input_is_nan_pipe_reg15;
reg [0:0] input_is_nan_pipe_reg16;
reg [0:0] input_is_nan_pipe_reg17;
reg [0:0] input_is_nan_pipe_reg18;
reg [0:0] input_is_nan_pipe_reg19;
reg [0:0] input_is_nan_pipe_reg2;
reg [0:0] input_is_nan_pipe_reg20;
reg [0:0] input_is_nan_pipe_reg21;
reg [0:0] input_is_nan_pipe_reg22;
reg [0:0] input_is_nan_pipe_reg23;
reg [0:0] input_is_nan_pipe_reg24;
reg [0:0] input_is_nan_pipe_reg25;
reg [0:0] input_is_nan_pipe_reg26;
reg [0:0] input_is_nan_pipe_reg27;
reg [0:0] input_is_nan_pipe_reg28;
reg [0:0] input_is_nan_pipe_reg29;
reg [0:0] input_is_nan_pipe_reg3;
reg [0:0] input_is_nan_pipe_reg30;
reg [0:0] input_is_nan_pipe_reg4;
reg [0:0] input_is_nan_pipe_reg5;
reg [0:0] input_is_nan_pipe_reg6;
reg [0:0] input_is_nan_pipe_reg7;
reg [0:0] input_is_nan_pipe_reg8;
reg [0:0] input_is_nan_pipe_reg9;
reg [0:0] input_is_one_pipe_reg0;
reg [0:0] input_is_one_pipe_reg1;
reg [0:0] input_is_one_pipe_reg10;
reg [0:0] input_is_one_pipe_reg11;
reg [0:0] input_is_one_pipe_reg12;
reg [0:0] input_is_one_pipe_reg13;
reg [0:0] input_is_one_pipe_reg14;
reg [0:0] input_is_one_pipe_reg15;
reg [0:0] input_is_one_pipe_reg16;
reg [0:0] input_is_one_pipe_reg17;
reg [0:0] input_is_one_pipe_reg18;
reg [0:0] input_is_one_pipe_reg19;
reg [0:0] input_is_one_pipe_reg2;
reg [0:0] input_is_one_pipe_reg20;
reg [0:0] input_is_one_pipe_reg21;
reg [0:0] input_is_one_pipe_reg22;
reg [0:0] input_is_one_pipe_reg23;
reg [0:0] input_is_one_pipe_reg24;
reg [0:0] input_is_one_pipe_reg25;
reg [0:0] input_is_one_pipe_reg26;
reg [0:0] input_is_one_pipe_reg27;
reg [0:0] input_is_one_pipe_reg28;
reg [0:0] input_is_one_pipe_reg29;
reg [0:0] input_is_one_pipe_reg3;
reg [0:0] input_is_one_pipe_reg30;
reg [0:0] input_is_one_pipe_reg4;
reg [0:0] input_is_one_pipe_reg5;
reg [0:0] input_is_one_pipe_reg6;
reg [0:0] input_is_one_pipe_reg7;
reg [0:0] input_is_one_pipe_reg8;
reg [0:0] input_is_one_pipe_reg9;
reg [0:0] input_is_zero_pipe_reg0;
reg [0:0] input_is_zero_pipe_reg1;
reg [0:0] input_is_zero_pipe_reg10;
reg [0:0] input_is_zero_pipe_reg11;
reg [0:0] input_is_zero_pipe_reg12;
reg [0:0] input_is_zero_pipe_reg13;
reg [0:0] input_is_zero_pipe_reg14;
reg [0:0] input_is_zero_pipe_reg15;
reg [0:0] input_is_zero_pipe_reg16;
reg [0:0] input_is_zero_pipe_reg17;
reg [0:0] input_is_zero_pipe_reg18;
reg [0:0] input_is_zero_pipe_reg19;
reg [0:0] input_is_zero_pipe_reg2;
reg [0:0] input_is_zero_pipe_reg20;
reg [0:0] input_is_zero_pipe_reg21;
reg [0:0] input_is_zero_pipe_reg22;
reg [0:0] input_is_zero_pipe_reg23;
reg [0:0] input_is_zero_pipe_reg24;
reg [0:0] input_is_zero_pipe_reg25;
reg [0:0] input_is_zero_pipe_reg26;
reg [0:0] input_is_zero_pipe_reg27;
reg [0:0] input_is_zero_pipe_reg28;
reg [0:0] input_is_zero_pipe_reg29;
reg [0:0] input_is_zero_pipe_reg3;
reg [0:0] input_is_zero_pipe_reg30;
reg [0:0] input_is_zero_pipe_reg4;
reg [0:0] input_is_zero_pipe_reg5;
reg [0:0] input_is_zero_pipe_reg6;
reg [0:0] input_is_zero_pipe_reg7;
reg [0:0] input_is_zero_pipe_reg8;
reg [0:0] input_is_zero_pipe_reg9;
reg [93:0] Log_normal_normd_pipe_reg0;
reg [93:0] Log_normal_reg0;
reg [56:0] Log_small_normd_pipe_reg0;
reg [56:0] Log_small_normd_pipe_reg1;
reg [6:0] Lshiftval_reg0;
reg [6:0] Lshiftval_reg1;
reg [6:0] Lshiftval_reg2;
reg [6:0] Lshiftval_reg3;
reg [5:0] lzo_pipe1_reg0;
reg [5:0] lzo_pipe1_reg1;
reg [5:0] lzo_pipe1_reg10;
reg [5:0] lzo_pipe1_reg11;
reg [5:0] lzo_pipe1_reg12;
reg [5:0] lzo_pipe1_reg13;
reg [5:0] lzo_pipe1_reg14;
reg [5:0] lzo_pipe1_reg15;
reg [5:0] lzo_pipe1_reg16;
reg [5:0] lzo_pipe1_reg17;
reg [5:0] lzo_pipe1_reg18;
reg [5:0] lzo_pipe1_reg19;
reg [5:0] lzo_pipe1_reg2;
reg [5:0] lzo_pipe1_reg20;
reg [5:0] lzo_pipe1_reg21;
reg [5:0] lzo_pipe1_reg22;
reg [5:0] lzo_pipe1_reg23;
reg [5:0] lzo_pipe1_reg3;
reg [5:0] lzo_pipe1_reg4;
reg [5:0] lzo_pipe1_reg5;
reg [5:0] lzo_pipe1_reg6;
reg [5:0] lzo_pipe1_reg7;
reg [5:0] lzo_pipe1_reg8;
reg [5:0] lzo_pipe1_reg9;
reg [5:0] lzo_reg0;
reg [5:0] lzo_reg1;
reg [5:0] lzo_reg2;
reg [5:0] lzo_reg3;
reg [5:0] lzo_reg4;
reg [5:0] lzo_reg5;
reg [5:0] lzo_reg6;
reg [0:0] sign_data_reg0;
reg [0:0] sign_data_reg1;
reg [0:0] sign_data_reg2;
reg [0:0] small_flag_pipe_reg0;
reg [0:0] small_flag_pipe_reg1;
reg [0:0] small_flag_pipe_reg2;
reg [0:0] small_flag_pipe_reg3;
reg [0:0] small_flag_pipe_reg4;
reg [0:0] small_flag_pipe_reg5;
reg [0:0] small_flag_pipe_reg6;
reg [0:0] small_flag_pipe_reg7;
reg [0:0] small_flag_pipe_reg8;
reg [0:0] sR_pipe1_reg0;
reg [0:0] sR_pipe1_reg1;
reg [0:0] sR_pipe1_reg10;
reg [0:0] sR_pipe1_reg11;
reg [0:0] sR_pipe1_reg12;
reg [0:0] sR_pipe1_reg13;
reg [0:0] sR_pipe1_reg14;
reg [0:0] sR_pipe1_reg15;
reg [0:0] sR_pipe1_reg16;
reg [0:0] sR_pipe1_reg17;
reg [0:0] sR_pipe1_reg18;
reg [0:0] sR_pipe1_reg19;
reg [0:0] sR_pipe1_reg2;
reg [0:0] sR_pipe1_reg20;
reg [0:0] sR_pipe1_reg21;
reg [0:0] sR_pipe1_reg22;
reg [0:0] sR_pipe1_reg23;
reg [0:0] sR_pipe1_reg3;
reg [0:0] sR_pipe1_reg4;
reg [0:0] sR_pipe1_reg5;
reg [0:0] sR_pipe1_reg6;
reg [0:0] sR_pipe1_reg7;
reg [0:0] sR_pipe1_reg8;
reg [0:0] sR_pipe1_reg9;
reg [0:0] sR_pipe2_reg0;
reg [0:0] sR_pipe2_reg1;
reg [0:0] sR_pipe2_reg2;
reg [0:0] sR_pipe2_reg3;
reg [0:0] sR_pipe2_reg4;
reg [0:0] sR_pipe2_reg5;
reg [0:0] sR_pipe3_reg0;
reg [0:0] sR_pipe3_reg1;
reg [0:0] sR_pipe3_reg2;
reg [0:0] sR_pipe3_reg3;
reg [27:0] Z2o2_pipe_reg0;
reg [27:0] Z2o2_small_s_pipe_reg0;
reg [54:0] Zfinal_reg0;
reg [54:0] Zfinal_reg1;
wire [58:0] wire_addsub1_result;
wire [93:0] wire_addsub2_result;
wire [67:0] wire_mult1_result;
wire [62:0]wire_mux_result0a_dataout;
wire [10:0] absE;
wire [67:0] absELog2;
wire [93:0] absELog2_pad;
wire [67:0] absELog2_pipe;
wire [25:0] absZ0;
wire [25:0] absZ0_pipe;
wire [25:0] absZ0s;
wire [25:0] absZ0s_pipe1;
wire [25:0] absZ0s_pipe2;
wire aclr;
wire [82:0] almostLog;
wire [82:0] almostLog_pipe;
wire [10:0] data_exp_is_ebiase;
wire doRR;
wire doRR_pipe;
wire [10:0] E0;
wire [10:0] E0_is_zero;
wire [10:0] E0_pipe;
wire [1:0] E0_sub;
wire [10:0] E0offset;
wire [5:0] E_normal;
wire [5:0] E_normal_pipe;
wire [10:0] E_small;
wire [62:0] EFR;
wire [10:0] ER;
wire exp_all_one;
wire exp_all_zero;
wire [10:0] exp_biase;
wire [10:0] exp_data;
wire exp_is_ebiase;
wire exp_is_ebiase_pipe;
wire First_bit;
wire input_is_infinity;
wire input_is_infinity_pipe;
wire input_is_nan;
wire input_is_nan_pipe;
wire input_is_one;
wire input_is_one_pipe;
wire input_is_zero;
wire input_is_zero_pipe;
wire [54:0] Log1p_normal;
wire [56:0] Log2;
wire [56:0] Log_g;
wire [93:0] Log_normal;
wire [93:0] Log_normal_normd;
wire [93:0] Log_normal_normd_pipe;
wire [93:0] Log_normal_pipe;
wire [58:0] Log_small;
wire [56:0] Log_small1;
wire [56:0] Log_small2;
wire [56:0] Log_small_normd;
wire [56:0] Log_small_normd_pipe;
wire [82:0] LogF_normal;
wire [93:0] LogF_normal_pad;
wire [6:0] Lshiftval;
wire [5:0] lzo;
wire [5:0] lzo_pipe1;
wire [5:0] lzo_pipe2;
wire [53:0] man_above_half;
wire man_all_zero;
wire [53:0] man_below_half;
wire [51:0] man_data;
wire man_not_zero;
wire [5:0] pfinal_s;
wire round;
wire [6:0] Rshiftval;
wire sign_data;
wire sign_data_pipe;
wire small_flag;
wire small_flag_pipe;
wire [26:0] squarerIn;
wire [26:0] squarerIn0;
wire [26:0] squarerIn1;
wire sR;
wire sR_pipe1;
wire sR_pipe2;
wire sR_pipe3;
wire [3:0] sticky;
wire [53:0] Y0;
wire [27:0] Z2o2;
wire [27:0] Z2o2_pipe;
wire [58:0] Z2o2_small;
wire [27:0] Z2o2_small_s;
wire [27:0] Z2o2_small_s_pipe;
wire [58:0] Z_small;
wire [54:0] Zfinal;
wire [54:0] Zfinal_pipe;
acl_fp_log_s5_double_altbarrel_shift_qud Lshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({absZ0, {38{1'b0}}}),
.distance(Lshiftval[5:0]),
.result(wire_Lshiftsmall_result));
acl_fp_log_s5_double_altbarrel_shift_edb lzc_norm_L
(
.data({Log_normal_pipe, {34{1'b0}}}),
.distance((~ wire_lzc_norm_E_q)),
.result(wire_lzc_norm_L_result));
acl_fp_log_s5_double_altbarrel_shift_d2e Rshiftsmall
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Z2o2, {36{1'b0}}}),
.distance(Rshiftval[5:0]),
.result(wire_Rshiftsmall_result));
acl_fp_log_s5_double_altfp_log_and_or_rab exp_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_nan_result));
acl_fp_log_s5_double_altfp_log_and_or_98b exp_zero
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(exp_data),
.result(wire_exp_zero_result));
acl_fp_log_s5_double_altfp_log_and_or_e8b man_inf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_inf_result));
acl_fp_log_s5_double_altfp_log_and_or_e8b man_nan
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(man_data),
.result(wire_man_nan_result));
acl_fp_log_s5_double_altfp_log_csa_r0e add1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({{28{1'b0}}, Log1p_normal}),
.datab(almostLog),
.result(wire_add1_result));
acl_fp_log_s5_double_altfp_log_csa_p0e add2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({ER, Log_g[56:5]}),
.datab({{62{1'b0}}, round}),
.result(wire_add2_result));
acl_fp_log_s5_double_altfp_log_csa_aoc exp_biase_sub
(
.dataa(exp_data),
.datab(exp_biase),
.result(wire_exp_biase_sub_result));
acl_fp_log_s5_double_altfp_log_csa_i4b sub1
(
.dataa({26{1'b0}}),
.datab(Y0[25:0]),
.result(wire_sub1_result));
acl_fp_log_s5_double_altfp_log_csa_aoc sub2
(
.dataa({11{1'b0}}),
.datab(E0),
.result(wire_sub2_result));
acl_fp_log_s5_double_altfp_log_csa_vmc sub3
(
.dataa({1'b0, lzo}),
.datab({1'b0, pfinal_s}),
.result(wire_sub3_result));
acl_fp_log_s5_double_altfp_log_csa_plf sub4
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(Zfinal_pipe),
.datab({{29{1'b0}}, Z2o2[27:2]}),
.result(wire_sub4_result));
acl_fp_log_s5_double_altfp_log_csa_ilf sub5
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa({1'b0, {8{1'b1}}, E0_sub}),
.datab({{5{1'b0}}, lzo_pipe2}),
.result(wire_sub5_result));
acl_fp_log_s5_double_altfp_log_csa_aoc sub6
(
.dataa(E0offset),
.datab({{5{1'b0}}, (~ E_normal)}),
.result(wire_sub6_result));
acl_fp_log_s5_double_range_reduction_3sd range_reduction
(
.a0_in(man_data[51:47]),
.aclr(aclr),
.almostlog(wire_range_reduction_almostlog),
.clk_en(clk_en),
.clock(clock),
.y0_in(Y0),
.z(wire_range_reduction_z));
acl_fp_log_s5_double_altpriority_encoder_gla lzc_norm_E
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({Log_normal, 34'b0000000000000000000000000000000001}),
.q(wire_lzc_norm_E_q));
acl_fp_log_s5_double_altpriority_encoder_018 lzoc
(
.data({({52{First_bit}} ^ Y0[52:1]), 12'b000000000001}),
.q(wire_lzoc_q));
altsquare squarer
(
.aclr(aclr),
.clock(clock),
.data(squarerIn),
.ena(clk_en),
.result(wire_squarer_result));
defparam
squarer.data_width = 27,
squarer.pipeline = 1,
squarer.representation = "UNSIGNED",
squarer.result_alignment = "MSB",
squarer.result_width = 28,
squarer.lpm_type = "altsquare";
// synopsys translate_off
initial
absELog2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg0 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg0 <= absELog2_pipe;
// synopsys translate_off
initial
absELog2_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg1 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg1 <= absELog2_pipe_reg0;
// synopsys translate_off
initial
absELog2_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absELog2_pipe_reg2 <= 68'b0;
else if (clk_en == 1'b1) absELog2_pipe_reg2 <= absELog2_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg0 <= absZ0_pipe;
// synopsys translate_off
initial
absZ0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg1 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg1 <= absZ0_pipe_reg0;
// synopsys translate_off
initial
absZ0_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg10 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg10 <= absZ0_pipe_reg9;
// synopsys translate_off
initial
absZ0_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg11 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg11 <= absZ0_pipe_reg10;
// synopsys translate_off
initial
absZ0_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg12 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg12 <= absZ0_pipe_reg11;
// synopsys translate_off
initial
absZ0_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg13 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg13 <= absZ0_pipe_reg12;
// synopsys translate_off
initial
absZ0_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg14 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg14 <= absZ0_pipe_reg13;
// synopsys translate_off
initial
absZ0_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg15 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg15 <= absZ0_pipe_reg14;
// synopsys translate_off
initial
absZ0_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg16 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg16 <= absZ0_pipe_reg15;
// synopsys translate_off
initial
absZ0_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg17 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg17 <= absZ0_pipe_reg16;
// synopsys translate_off
initial
absZ0_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg18 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg18 <= absZ0_pipe_reg17;
// synopsys translate_off
initial
absZ0_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg19 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg19 <= absZ0_pipe_reg18;
// synopsys translate_off
initial
absZ0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg2 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg2 <= absZ0_pipe_reg1;
// synopsys translate_off
initial
absZ0_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg20 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg20 <= absZ0_pipe_reg19;
// synopsys translate_off
initial
absZ0_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg21 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg21 <= absZ0_pipe_reg20;
// synopsys translate_off
initial
absZ0_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg22 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg22 <= absZ0_pipe_reg21;
// synopsys translate_off
initial
absZ0_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg23 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg23 <= absZ0_pipe_reg22;
// synopsys translate_off
initial
absZ0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg3 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg3 <= absZ0_pipe_reg2;
// synopsys translate_off
initial
absZ0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg4 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg4 <= absZ0_pipe_reg3;
// synopsys translate_off
initial
absZ0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg5 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg5 <= absZ0_pipe_reg4;
// synopsys translate_off
initial
absZ0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg6 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg6 <= absZ0_pipe_reg5;
// synopsys translate_off
initial
absZ0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg7 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg7 <= absZ0_pipe_reg6;
// synopsys translate_off
initial
absZ0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg8 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg8 <= absZ0_pipe_reg7;
// synopsys translate_off
initial
absZ0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0_pipe_reg9 <= 26'b0;
else if (clk_en == 1'b1) absZ0_pipe_reg9 <= absZ0_pipe_reg8;
// synopsys translate_off
initial
absZ0s_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg0 <= absZ0s_pipe1;
// synopsys translate_off
initial
absZ0s_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg1 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg1 <= absZ0s_pipe1_reg0;
// synopsys translate_off
initial
absZ0s_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg2 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg2 <= absZ0s_pipe1_reg1;
// synopsys translate_off
initial
absZ0s_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_pipe1_reg3 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_pipe1_reg3 <= absZ0s_pipe1_reg2;
// synopsys translate_off
initial
absZ0s_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) absZ0s_reg0 <= 26'b0;
else if (clk_en == 1'b1) absZ0s_reg0 <= absZ0s;
// synopsys translate_off
initial
almostLog_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg0 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg0 <= almostLog_pipe;
// synopsys translate_off
initial
almostLog_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg1 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg1 <= almostLog_pipe_reg0;
// synopsys translate_off
initial
almostLog_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) almostLog_pipe_reg2 <= 83'b0;
else if (clk_en == 1'b1) almostLog_pipe_reg2 <= almostLog_pipe_reg1;
// synopsys translate_off
initial
doRR_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg0 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg0 <= doRR;
// synopsys translate_off
initial
doRR_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) doRR_reg1 <= 1'b0;
else if (clk_en == 1'b1) doRR_reg1 <= doRR_reg0;
// synopsys translate_off
initial
E0_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg0 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg0 <= E0_pipe;
// synopsys translate_off
initial
E0_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg1 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg1 <= E0_pipe_reg0;
// synopsys translate_off
initial
E0_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg10 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg10 <= E0_pipe_reg9;
// synopsys translate_off
initial
E0_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg11 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg11 <= E0_pipe_reg10;
// synopsys translate_off
initial
E0_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg12 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg12 <= E0_pipe_reg11;
// synopsys translate_off
initial
E0_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg13 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg13 <= E0_pipe_reg12;
// synopsys translate_off
initial
E0_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg14 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg14 <= E0_pipe_reg13;
// synopsys translate_off
initial
E0_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg15 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg15 <= E0_pipe_reg14;
// synopsys translate_off
initial
E0_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg16 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg16 <= E0_pipe_reg15;
// synopsys translate_off
initial
E0_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg17 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg17 <= E0_pipe_reg16;
// synopsys translate_off
initial
E0_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg18 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg18 <= E0_pipe_reg17;
// synopsys translate_off
initial
E0_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg19 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg19 <= E0_pipe_reg18;
// synopsys translate_off
initial
E0_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg2 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg2 <= E0_pipe_reg1;
// synopsys translate_off
initial
E0_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg20 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg20 <= E0_pipe_reg19;
// synopsys translate_off
initial
E0_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg21 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg21 <= E0_pipe_reg20;
// synopsys translate_off
initial
E0_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg22 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg22 <= E0_pipe_reg21;
// synopsys translate_off
initial
E0_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg23 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg23 <= E0_pipe_reg22;
// synopsys translate_off
initial
E0_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg3 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg3 <= E0_pipe_reg2;
// synopsys translate_off
initial
E0_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg4 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg4 <= E0_pipe_reg3;
// synopsys translate_off
initial
E0_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg5 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg5 <= E0_pipe_reg4;
// synopsys translate_off
initial
E0_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg6 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg6 <= E0_pipe_reg5;
// synopsys translate_off
initial
E0_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg7 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg7 <= E0_pipe_reg6;
// synopsys translate_off
initial
E0_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg8 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg8 <= E0_pipe_reg7;
// synopsys translate_off
initial
E0_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E0_pipe_reg9 <= 11'b0;
else if (clk_en == 1'b1) E0_pipe_reg9 <= E0_pipe_reg8;
// synopsys translate_off
initial
E_normal_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) E_normal_pipe_reg0 <= 6'b0;
else if (clk_en == 1'b1) E_normal_pipe_reg0 <= E_normal_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg0 <= exp_is_ebiase_pipe;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg1 <= exp_is_ebiase_pipe_reg0;
// synopsys translate_off
initial
exp_is_ebiase_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_is_ebiase_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) exp_is_ebiase_pipe_reg2 <= exp_is_ebiase_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg0 <= input_is_infinity_pipe;
// synopsys translate_off
initial
input_is_infinity_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg1 <= input_is_infinity_pipe_reg0;
// synopsys translate_off
initial
input_is_infinity_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg10 <= input_is_infinity_pipe_reg9;
// synopsys translate_off
initial
input_is_infinity_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg11 <= input_is_infinity_pipe_reg10;
// synopsys translate_off
initial
input_is_infinity_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg12 <= input_is_infinity_pipe_reg11;
// synopsys translate_off
initial
input_is_infinity_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg13 <= input_is_infinity_pipe_reg12;
// synopsys translate_off
initial
input_is_infinity_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg14 <= input_is_infinity_pipe_reg13;
// synopsys translate_off
initial
input_is_infinity_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg15 <= input_is_infinity_pipe_reg14;
// synopsys translate_off
initial
input_is_infinity_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg16 <= input_is_infinity_pipe_reg15;
// synopsys translate_off
initial
input_is_infinity_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg17 <= input_is_infinity_pipe_reg16;
// synopsys translate_off
initial
input_is_infinity_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg18 <= input_is_infinity_pipe_reg17;
// synopsys translate_off
initial
input_is_infinity_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg19 <= input_is_infinity_pipe_reg18;
// synopsys translate_off
initial
input_is_infinity_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg2 <= input_is_infinity_pipe_reg1;
// synopsys translate_off
initial
input_is_infinity_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg20 <= input_is_infinity_pipe_reg19;
// synopsys translate_off
initial
input_is_infinity_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg21 <= input_is_infinity_pipe_reg20;
// synopsys translate_off
initial
input_is_infinity_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg22 <= input_is_infinity_pipe_reg21;
// synopsys translate_off
initial
input_is_infinity_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg23 <= input_is_infinity_pipe_reg22;
// synopsys translate_off
initial
input_is_infinity_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg24 <= input_is_infinity_pipe_reg23;
// synopsys translate_off
initial
input_is_infinity_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg25 <= input_is_infinity_pipe_reg24;
// synopsys translate_off
initial
input_is_infinity_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg26 <= input_is_infinity_pipe_reg25;
// synopsys translate_off
initial
input_is_infinity_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg27 <= input_is_infinity_pipe_reg26;
// synopsys translate_off
initial
input_is_infinity_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg28 <= input_is_infinity_pipe_reg27;
// synopsys translate_off
initial
input_is_infinity_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg29 <= input_is_infinity_pipe_reg28;
// synopsys translate_off
initial
input_is_infinity_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg3 <= input_is_infinity_pipe_reg2;
// synopsys translate_off
initial
input_is_infinity_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg30 <= input_is_infinity_pipe_reg29;
// synopsys translate_off
initial
input_is_infinity_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg4 <= input_is_infinity_pipe_reg3;
// synopsys translate_off
initial
input_is_infinity_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg5 <= input_is_infinity_pipe_reg4;
// synopsys translate_off
initial
input_is_infinity_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg6 <= input_is_infinity_pipe_reg5;
// synopsys translate_off
initial
input_is_infinity_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg7 <= input_is_infinity_pipe_reg6;
// synopsys translate_off
initial
input_is_infinity_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg8 <= input_is_infinity_pipe_reg7;
// synopsys translate_off
initial
input_is_infinity_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_pipe_reg9 <= input_is_infinity_pipe_reg8;
// synopsys translate_off
initial
input_is_nan_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg0 <= input_is_nan_pipe;
// synopsys translate_off
initial
input_is_nan_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg1 <= input_is_nan_pipe_reg0;
// synopsys translate_off
initial
input_is_nan_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg10 <= input_is_nan_pipe_reg9;
// synopsys translate_off
initial
input_is_nan_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg11 <= input_is_nan_pipe_reg10;
// synopsys translate_off
initial
input_is_nan_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg12 <= input_is_nan_pipe_reg11;
// synopsys translate_off
initial
input_is_nan_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg13 <= input_is_nan_pipe_reg12;
// synopsys translate_off
initial
input_is_nan_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg14 <= input_is_nan_pipe_reg13;
// synopsys translate_off
initial
input_is_nan_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg15 <= input_is_nan_pipe_reg14;
// synopsys translate_off
initial
input_is_nan_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg16 <= input_is_nan_pipe_reg15;
// synopsys translate_off
initial
input_is_nan_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg17 <= input_is_nan_pipe_reg16;
// synopsys translate_off
initial
input_is_nan_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg18 <= input_is_nan_pipe_reg17;
// synopsys translate_off
initial
input_is_nan_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg19 <= input_is_nan_pipe_reg18;
// synopsys translate_off
initial
input_is_nan_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg2 <= input_is_nan_pipe_reg1;
// synopsys translate_off
initial
input_is_nan_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg20 <= input_is_nan_pipe_reg19;
// synopsys translate_off
initial
input_is_nan_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg21 <= input_is_nan_pipe_reg20;
// synopsys translate_off
initial
input_is_nan_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg22 <= input_is_nan_pipe_reg21;
// synopsys translate_off
initial
input_is_nan_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg23 <= input_is_nan_pipe_reg22;
// synopsys translate_off
initial
input_is_nan_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg24 <= input_is_nan_pipe_reg23;
// synopsys translate_off
initial
input_is_nan_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg25 <= input_is_nan_pipe_reg24;
// synopsys translate_off
initial
input_is_nan_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg26 <= input_is_nan_pipe_reg25;
// synopsys translate_off
initial
input_is_nan_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg27 <= input_is_nan_pipe_reg26;
// synopsys translate_off
initial
input_is_nan_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg28 <= input_is_nan_pipe_reg27;
// synopsys translate_off
initial
input_is_nan_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg29 <= input_is_nan_pipe_reg28;
// synopsys translate_off
initial
input_is_nan_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg3 <= input_is_nan_pipe_reg2;
// synopsys translate_off
initial
input_is_nan_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg30 <= input_is_nan_pipe_reg29;
// synopsys translate_off
initial
input_is_nan_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg4 <= input_is_nan_pipe_reg3;
// synopsys translate_off
initial
input_is_nan_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg5 <= input_is_nan_pipe_reg4;
// synopsys translate_off
initial
input_is_nan_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg6 <= input_is_nan_pipe_reg5;
// synopsys translate_off
initial
input_is_nan_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg7 <= input_is_nan_pipe_reg6;
// synopsys translate_off
initial
input_is_nan_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg8 <= input_is_nan_pipe_reg7;
// synopsys translate_off
initial
input_is_nan_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_pipe_reg9 <= input_is_nan_pipe_reg8;
// synopsys translate_off
initial
input_is_one_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg0 <= input_is_one_pipe;
// synopsys translate_off
initial
input_is_one_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg1 <= input_is_one_pipe_reg0;
// synopsys translate_off
initial
input_is_one_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg10 <= input_is_one_pipe_reg9;
// synopsys translate_off
initial
input_is_one_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg11 <= input_is_one_pipe_reg10;
// synopsys translate_off
initial
input_is_one_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg12 <= input_is_one_pipe_reg11;
// synopsys translate_off
initial
input_is_one_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg13 <= input_is_one_pipe_reg12;
// synopsys translate_off
initial
input_is_one_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg14 <= input_is_one_pipe_reg13;
// synopsys translate_off
initial
input_is_one_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg15 <= input_is_one_pipe_reg14;
// synopsys translate_off
initial
input_is_one_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg16 <= input_is_one_pipe_reg15;
// synopsys translate_off
initial
input_is_one_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg17 <= input_is_one_pipe_reg16;
// synopsys translate_off
initial
input_is_one_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg18 <= input_is_one_pipe_reg17;
// synopsys translate_off
initial
input_is_one_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg19 <= input_is_one_pipe_reg18;
// synopsys translate_off
initial
input_is_one_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg2 <= input_is_one_pipe_reg1;
// synopsys translate_off
initial
input_is_one_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg20 <= input_is_one_pipe_reg19;
// synopsys translate_off
initial
input_is_one_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg21 <= input_is_one_pipe_reg20;
// synopsys translate_off
initial
input_is_one_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg22 <= input_is_one_pipe_reg21;
// synopsys translate_off
initial
input_is_one_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg23 <= input_is_one_pipe_reg22;
// synopsys translate_off
initial
input_is_one_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg24 <= input_is_one_pipe_reg23;
// synopsys translate_off
initial
input_is_one_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg25 <= input_is_one_pipe_reg24;
// synopsys translate_off
initial
input_is_one_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg26 <= input_is_one_pipe_reg25;
// synopsys translate_off
initial
input_is_one_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg27 <= input_is_one_pipe_reg26;
// synopsys translate_off
initial
input_is_one_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg28 <= input_is_one_pipe_reg27;
// synopsys translate_off
initial
input_is_one_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg29 <= input_is_one_pipe_reg28;
// synopsys translate_off
initial
input_is_one_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg3 <= input_is_one_pipe_reg2;
// synopsys translate_off
initial
input_is_one_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg30 <= input_is_one_pipe_reg29;
// synopsys translate_off
initial
input_is_one_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg4 <= input_is_one_pipe_reg3;
// synopsys translate_off
initial
input_is_one_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg5 <= input_is_one_pipe_reg4;
// synopsys translate_off
initial
input_is_one_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg6 <= input_is_one_pipe_reg5;
// synopsys translate_off
initial
input_is_one_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg7 <= input_is_one_pipe_reg6;
// synopsys translate_off
initial
input_is_one_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg8 <= input_is_one_pipe_reg7;
// synopsys translate_off
initial
input_is_one_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_one_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_one_pipe_reg9 <= input_is_one_pipe_reg8;
// synopsys translate_off
initial
input_is_zero_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg0 <= input_is_zero_pipe;
// synopsys translate_off
initial
input_is_zero_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg1 <= input_is_zero_pipe_reg0;
// synopsys translate_off
initial
input_is_zero_pipe_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg10 <= input_is_zero_pipe_reg9;
// synopsys translate_off
initial
input_is_zero_pipe_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg11 <= input_is_zero_pipe_reg10;
// synopsys translate_off
initial
input_is_zero_pipe_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg12 <= input_is_zero_pipe_reg11;
// synopsys translate_off
initial
input_is_zero_pipe_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg13 <= input_is_zero_pipe_reg12;
// synopsys translate_off
initial
input_is_zero_pipe_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg14 <= input_is_zero_pipe_reg13;
// synopsys translate_off
initial
input_is_zero_pipe_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg15 <= input_is_zero_pipe_reg14;
// synopsys translate_off
initial
input_is_zero_pipe_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg16 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg16 <= input_is_zero_pipe_reg15;
// synopsys translate_off
initial
input_is_zero_pipe_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg17 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg17 <= input_is_zero_pipe_reg16;
// synopsys translate_off
initial
input_is_zero_pipe_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg18 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg18 <= input_is_zero_pipe_reg17;
// synopsys translate_off
initial
input_is_zero_pipe_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg19 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg19 <= input_is_zero_pipe_reg18;
// synopsys translate_off
initial
input_is_zero_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg2 <= input_is_zero_pipe_reg1;
// synopsys translate_off
initial
input_is_zero_pipe_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg20 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg20 <= input_is_zero_pipe_reg19;
// synopsys translate_off
initial
input_is_zero_pipe_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg21 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg21 <= input_is_zero_pipe_reg20;
// synopsys translate_off
initial
input_is_zero_pipe_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg22 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg22 <= input_is_zero_pipe_reg21;
// synopsys translate_off
initial
input_is_zero_pipe_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg23 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg23 <= input_is_zero_pipe_reg22;
// synopsys translate_off
initial
input_is_zero_pipe_reg24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg24 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg24 <= input_is_zero_pipe_reg23;
// synopsys translate_off
initial
input_is_zero_pipe_reg25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg25 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg25 <= input_is_zero_pipe_reg24;
// synopsys translate_off
initial
input_is_zero_pipe_reg26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg26 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg26 <= input_is_zero_pipe_reg25;
// synopsys translate_off
initial
input_is_zero_pipe_reg27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg27 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg27 <= input_is_zero_pipe_reg26;
// synopsys translate_off
initial
input_is_zero_pipe_reg28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg28 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg28 <= input_is_zero_pipe_reg27;
// synopsys translate_off
initial
input_is_zero_pipe_reg29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg29 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg29 <= input_is_zero_pipe_reg28;
// synopsys translate_off
initial
input_is_zero_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg3 <= input_is_zero_pipe_reg2;
// synopsys translate_off
initial
input_is_zero_pipe_reg30 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg30 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg30 <= input_is_zero_pipe_reg29;
// synopsys translate_off
initial
input_is_zero_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg4 <= input_is_zero_pipe_reg3;
// synopsys translate_off
initial
input_is_zero_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg5 <= input_is_zero_pipe_reg4;
// synopsys translate_off
initial
input_is_zero_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg6 <= input_is_zero_pipe_reg5;
// synopsys translate_off
initial
input_is_zero_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg7 <= input_is_zero_pipe_reg6;
// synopsys translate_off
initial
input_is_zero_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg8 <= input_is_zero_pipe_reg7;
// synopsys translate_off
initial
input_is_zero_pipe_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_pipe_reg9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_pipe_reg9 <= input_is_zero_pipe_reg8;
// synopsys translate_off
initial
Log_normal_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_normd_pipe_reg0 <= 94'b0;
else if (clk_en == 1'b1) Log_normal_normd_pipe_reg0 <= Log_normal_normd_pipe;
// synopsys translate_off
initial
Log_normal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_normal_reg0 <= 94'b0;
else if (clk_en == 1'b1) Log_normal_reg0 <= Log_normal;
// synopsys translate_off
initial
Log_small_normd_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg0 <= 57'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg0 <= Log_small_normd_pipe;
// synopsys translate_off
initial
Log_small_normd_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Log_small_normd_pipe_reg1 <= 57'b0;
else if (clk_en == 1'b1) Log_small_normd_pipe_reg1 <= Log_small_normd_pipe_reg0;
// synopsys translate_off
initial
Lshiftval_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg0 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg0 <= Lshiftval;
// synopsys translate_off
initial
Lshiftval_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg1 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg1 <= Lshiftval_reg0;
// synopsys translate_off
initial
Lshiftval_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg2 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg2 <= Lshiftval_reg1;
// synopsys translate_off
initial
Lshiftval_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Lshiftval_reg3 <= 7'b0;
else if (clk_en == 1'b1) Lshiftval_reg3 <= Lshiftval_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg0 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg0 <= lzo_pipe1;
// synopsys translate_off
initial
lzo_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg1 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg1 <= lzo_pipe1_reg0;
// synopsys translate_off
initial
lzo_pipe1_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg10 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg10 <= lzo_pipe1_reg9;
// synopsys translate_off
initial
lzo_pipe1_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg11 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg11 <= lzo_pipe1_reg10;
// synopsys translate_off
initial
lzo_pipe1_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg12 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg12 <= lzo_pipe1_reg11;
// synopsys translate_off
initial
lzo_pipe1_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg13 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg13 <= lzo_pipe1_reg12;
// synopsys translate_off
initial
lzo_pipe1_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg14 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg14 <= lzo_pipe1_reg13;
// synopsys translate_off
initial
lzo_pipe1_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg15 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg15 <= lzo_pipe1_reg14;
// synopsys translate_off
initial
lzo_pipe1_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg16 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg16 <= lzo_pipe1_reg15;
// synopsys translate_off
initial
lzo_pipe1_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg17 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg17 <= lzo_pipe1_reg16;
// synopsys translate_off
initial
lzo_pipe1_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg18 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg18 <= lzo_pipe1_reg17;
// synopsys translate_off
initial
lzo_pipe1_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg19 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg19 <= lzo_pipe1_reg18;
// synopsys translate_off
initial
lzo_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg2 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg2 <= lzo_pipe1_reg1;
// synopsys translate_off
initial
lzo_pipe1_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg20 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg20 <= lzo_pipe1_reg19;
// synopsys translate_off
initial
lzo_pipe1_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg21 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg21 <= lzo_pipe1_reg20;
// synopsys translate_off
initial
lzo_pipe1_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg22 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg22 <= lzo_pipe1_reg21;
// synopsys translate_off
initial
lzo_pipe1_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg23 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg23 <= lzo_pipe1_reg22;
// synopsys translate_off
initial
lzo_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg3 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg3 <= lzo_pipe1_reg2;
// synopsys translate_off
initial
lzo_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg4 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg4 <= lzo_pipe1_reg3;
// synopsys translate_off
initial
lzo_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg5 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg5 <= lzo_pipe1_reg4;
// synopsys translate_off
initial
lzo_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg6 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg6 <= lzo_pipe1_reg5;
// synopsys translate_off
initial
lzo_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg7 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg7 <= lzo_pipe1_reg6;
// synopsys translate_off
initial
lzo_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg8 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg8 <= lzo_pipe1_reg7;
// synopsys translate_off
initial
lzo_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_pipe1_reg9 <= 6'b0;
else if (clk_en == 1'b1) lzo_pipe1_reg9 <= lzo_pipe1_reg8;
// synopsys translate_off
initial
lzo_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg0 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg0 <= lzo;
// synopsys translate_off
initial
lzo_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg1 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg1 <= lzo_reg0;
// synopsys translate_off
initial
lzo_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg2 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg2 <= lzo_reg1;
// synopsys translate_off
initial
lzo_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg3 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg3 <= lzo_reg2;
// synopsys translate_off
initial
lzo_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg4 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg4 <= lzo_reg3;
// synopsys translate_off
initial
lzo_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg5 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg5 <= lzo_reg4;
// synopsys translate_off
initial
lzo_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lzo_reg6 <= 6'b0;
else if (clk_en == 1'b1) lzo_reg6 <= lzo_reg5;
// synopsys translate_off
initial
sign_data_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg0 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg0 <= sign_data;
// synopsys translate_off
initial
sign_data_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg1 <= sign_data_reg0;
// synopsys translate_off
initial
sign_data_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_data_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_data_reg2 <= sign_data_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg0 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg0 <= small_flag_pipe;
// synopsys translate_off
initial
small_flag_pipe_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg1 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg1 <= small_flag_pipe_reg0;
// synopsys translate_off
initial
small_flag_pipe_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg2 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg2 <= small_flag_pipe_reg1;
// synopsys translate_off
initial
small_flag_pipe_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg3 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg3 <= small_flag_pipe_reg2;
// synopsys translate_off
initial
small_flag_pipe_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg4 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg4 <= small_flag_pipe_reg3;
// synopsys translate_off
initial
small_flag_pipe_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg5 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg5 <= small_flag_pipe_reg4;
// synopsys translate_off
initial
small_flag_pipe_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg6 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg6 <= small_flag_pipe_reg5;
// synopsys translate_off
initial
small_flag_pipe_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg7 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg7 <= small_flag_pipe_reg6;
// synopsys translate_off
initial
small_flag_pipe_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) small_flag_pipe_reg8 <= 1'b0;
else if (clk_en == 1'b1) small_flag_pipe_reg8 <= small_flag_pipe_reg7;
// synopsys translate_off
initial
sR_pipe1_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg0 <= sR_pipe1;
// synopsys translate_off
initial
sR_pipe1_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg1 <= sR_pipe1_reg0;
// synopsys translate_off
initial
sR_pipe1_reg10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg10 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg10 <= sR_pipe1_reg9;
// synopsys translate_off
initial
sR_pipe1_reg11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg11 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg11 <= sR_pipe1_reg10;
// synopsys translate_off
initial
sR_pipe1_reg12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg12 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg12 <= sR_pipe1_reg11;
// synopsys translate_off
initial
sR_pipe1_reg13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg13 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg13 <= sR_pipe1_reg12;
// synopsys translate_off
initial
sR_pipe1_reg14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg14 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg14 <= sR_pipe1_reg13;
// synopsys translate_off
initial
sR_pipe1_reg15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg15 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg15 <= sR_pipe1_reg14;
// synopsys translate_off
initial
sR_pipe1_reg16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg16 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg16 <= sR_pipe1_reg15;
// synopsys translate_off
initial
sR_pipe1_reg17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg17 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg17 <= sR_pipe1_reg16;
// synopsys translate_off
initial
sR_pipe1_reg18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg18 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg18 <= sR_pipe1_reg17;
// synopsys translate_off
initial
sR_pipe1_reg19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg19 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg19 <= sR_pipe1_reg18;
// synopsys translate_off
initial
sR_pipe1_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg2 <= sR_pipe1_reg1;
// synopsys translate_off
initial
sR_pipe1_reg20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg20 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg20 <= sR_pipe1_reg19;
// synopsys translate_off
initial
sR_pipe1_reg21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg21 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg21 <= sR_pipe1_reg20;
// synopsys translate_off
initial
sR_pipe1_reg22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg22 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg22 <= sR_pipe1_reg21;
// synopsys translate_off
initial
sR_pipe1_reg23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg23 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg23 <= sR_pipe1_reg22;
// synopsys translate_off
initial
sR_pipe1_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg3 <= sR_pipe1_reg2;
// synopsys translate_off
initial
sR_pipe1_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg4 <= sR_pipe1_reg3;
// synopsys translate_off
initial
sR_pipe1_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg5 <= sR_pipe1_reg4;
// synopsys translate_off
initial
sR_pipe1_reg6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg6 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg6 <= sR_pipe1_reg5;
// synopsys translate_off
initial
sR_pipe1_reg7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg7 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg7 <= sR_pipe1_reg6;
// synopsys translate_off
initial
sR_pipe1_reg8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg8 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg8 <= sR_pipe1_reg7;
// synopsys translate_off
initial
sR_pipe1_reg9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe1_reg9 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe1_reg9 <= sR_pipe1_reg8;
// synopsys translate_off
initial
sR_pipe2_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg0 <= sR_pipe2;
// synopsys translate_off
initial
sR_pipe2_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg1 <= sR_pipe2_reg0;
// synopsys translate_off
initial
sR_pipe2_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg2 <= sR_pipe2_reg1;
// synopsys translate_off
initial
sR_pipe2_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg3 <= sR_pipe2_reg2;
// synopsys translate_off
initial
sR_pipe2_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg4 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg4 <= sR_pipe2_reg3;
// synopsys translate_off
initial
sR_pipe2_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe2_reg5 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe2_reg5 <= sR_pipe2_reg4;
// synopsys translate_off
initial
sR_pipe3_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg0 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg0 <= sR_pipe3;
// synopsys translate_off
initial
sR_pipe3_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg1 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg1 <= sR_pipe3_reg0;
// synopsys translate_off
initial
sR_pipe3_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg2 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg2 <= sR_pipe3_reg1;
// synopsys translate_off
initial
sR_pipe3_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sR_pipe3_reg3 <= 1'b0;
else if (clk_en == 1'b1) sR_pipe3_reg3 <= sR_pipe3_reg2;
// synopsys translate_off
initial
Z2o2_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_pipe_reg0 <= 28'b0;
else if (clk_en == 1'b1) Z2o2_pipe_reg0 <= Z2o2_pipe;
// synopsys translate_off
initial
Z2o2_small_s_pipe_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Z2o2_small_s_pipe_reg0 <= 28'b0;
else if (clk_en == 1'b1) Z2o2_small_s_pipe_reg0 <= Z2o2_small_s_pipe;
// synopsys translate_off
initial
Zfinal_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg0 <= 55'b0;
else if (clk_en == 1'b1) Zfinal_reg0 <= Zfinal;
// synopsys translate_off
initial
Zfinal_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) Zfinal_reg1 <= 55'b0;
else if (clk_en == 1'b1) Zfinal_reg1 <= Zfinal_reg0;
lpm_add_sub addsub1
(
.add_sub(sR_pipe3),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(Z_small),
.datab(Z2o2_small),
.overflow(),
.result(wire_addsub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub1.lpm_pipeline = 1,
addsub1.lpm_representation = "UNSIGNED",
addsub1.lpm_width = 59,
addsub1.lpm_type = "lpm_add_sub";
lpm_add_sub addsub2
(
.add_sub((~ sR_pipe3)),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(absELog2_pad),
.datab(LogF_normal_pad),
.overflow(),
.result(wire_addsub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addsub2.lpm_pipeline = 1,
addsub2.lpm_representation = "UNSIGNED",
addsub2.lpm_width = 94,
addsub2.lpm_type = "lpm_add_sub";
lpm_mult mult1
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(absE),
.datab(Log2),
.result(wire_mult1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mult1.lpm_pipeline = 3,
mult1.lpm_representation = "UNSIGNED",
mult1.lpm_widtha = 11,
mult1.lpm_widthb = 57,
mult1.lpm_widthp = 68,
mult1.lpm_type = "lpm_mult";
assign wire_mux_result0a_dataout = ((((input_is_zero | input_is_infinity) | input_is_nan) | input_is_one) === 1'b1) ? {{11{((~ input_is_one) | input_is_nan)}}, input_is_nan, {51{1'b0}}} : EFR;
assign
absE = (({11{(~ sR_pipe2)}} & E0) | ({11{sR_pipe2}} & wire_sub2_result)),
absELog2 = absELog2_pipe_reg2,
absELog2_pad = {absELog2, {26{1'b0}}},
absELog2_pipe = wire_mult1_result,
absZ0 = absZ0_pipe_reg23,
absZ0_pipe = (({26{(~ sR_pipe1)}} & Y0[25:0]) | ({26{sR_pipe1}} & wire_sub1_result)),
absZ0s = wire_Lshiftsmall_result[63:38],
absZ0s_pipe1 = absZ0s_reg0,
absZ0s_pipe2 = absZ0s_pipe1_reg3,
aclr = 1'b0,
almostLog = almostLog_pipe_reg2,
almostLog_pipe = wire_range_reduction_almostlog,
data_exp_is_ebiase = {((~ exp_data[10]) & data_exp_is_ebiase[9]), (exp_data[9] & data_exp_is_ebiase[8]), (exp_data[8] & data_exp_is_ebiase[7]), (exp_data[7] & data_exp_is_ebiase[6]), (exp_data[6] & data_exp_is_ebiase[5]), (exp_data[5] & data_exp_is_ebiase[4]), (exp_data[4] & data_exp_is_ebiase[3]), (exp_data[3] & data_exp_is_ebiase[2]), (exp_data[2] & data_exp_is_ebiase[1]), (exp_data[1] & data_exp_is_ebiase[0]), exp_data[0]},
doRR = Lshiftval[6],
doRR_pipe = doRR_reg1,
E0 = E0_pipe_reg23,
E0_is_zero = {((~ E0[10]) & E0_is_zero[9]), ((~ E0[9]) & E0_is_zero[8]), ((~ E0[8]) & E0_is_zero[7]), ((~ E0[7]) & E0_is_zero[6]), ((~ E0[6]) & E0_is_zero[5]), ((~ E0[5]) & E0_is_zero[4]), ((~ E0[4]) & E0_is_zero[3]), ((~ E0[3]) & E0_is_zero[2]), ((~ E0[2]) & E0_is_zero[1]), ((~ E0[1]) & E0_is_zero[0]), (~ E0[0])},
E0_pipe = wire_exp_biase_sub_result,
E0_sub = {(Log_small[58] | Log_small[57]), (Log_small[58] | (~ Log_small[57]))},
E0offset = 11'b10000001001,
E_normal = E_normal_pipe_reg0,
E_normal_pipe = wire_lzc_norm_E_q[5:0],
E_small = wire_sub5_result,
EFR = wire_add2_result,
ER = (({11{(~ small_flag)}} & wire_sub6_result) | ({11{small_flag}} & E_small)),
exp_all_one = wire_exp_nan_result,
exp_all_zero = wire_exp_zero_result,
exp_biase = {10'b0111111111, (~ First_bit)},
exp_data = data[62:52],
exp_is_ebiase = exp_is_ebiase_pipe_reg2,
exp_is_ebiase_pipe = data_exp_is_ebiase[10],
First_bit = man_data[51],
input_is_infinity = input_is_infinity_pipe_reg30,
input_is_infinity_pipe = (exp_all_one & (~ man_all_zero)),
input_is_nan = input_is_nan_pipe_reg30,
input_is_nan_pipe = ((exp_all_one & man_not_zero) | sign_data_pipe),
input_is_one = input_is_one_pipe_reg30,
input_is_one_pipe = (exp_is_ebiase & (~ man_all_zero)),
input_is_zero = input_is_zero_pipe_reg30,
input_is_zero_pipe = (~ exp_all_zero),
Log1p_normal = wire_sub4_result,
Log2 = 57'b101100010111001000010111111101111101000111001111011110011,
Log_g = (({57{(~ small_flag)}} & Log_normal_normd[92:36]) | ({57{small_flag}} & {Log_small_normd[55:0], 1'b0})),
Log_normal = wire_addsub2_result,
Log_normal_normd = Log_normal_normd_pipe_reg0,
Log_normal_normd_pipe = wire_lzc_norm_L_result[127:34],
Log_normal_pipe = Log_normal_reg0,
Log_small = wire_addsub1_result,
Log_small1 = (({57{(~ Log_small[57])}} & Log_small[56:0]) | ({57{Log_small[57]}} & Log_small[57:1])),
Log_small2 = (({57{(~ Log_small[58])}} & Log_small1) | ({57{Log_small[58]}} & Log_small[58:2])),
Log_small_normd = Log_small_normd_pipe_reg1,
Log_small_normd_pipe = Log_small2,
LogF_normal = wire_add1_result,
LogF_normal_pad = {{11{LogF_normal[82]}}, LogF_normal},
Lshiftval = wire_sub3_result,
lzo = lzo_pipe1_reg23,
lzo_pipe1 = (~ wire_lzoc_q),
lzo_pipe2 = lzo_reg6,
man_above_half = {1'b0, 1'b1, man_data},
man_all_zero = wire_man_inf_result,
man_below_half = {1'b1, man_data, 1'b0},
man_data = data[51:0],
man_not_zero = wire_man_nan_result,
pfinal_s = 6'b011100,
result = {(((sR | input_is_zero) | input_is_nan) & (~ input_is_one)), wire_mux_result0a_dataout},
round = (Log_g[4] & (Log_g[5] | sticky[3])),
Rshiftval = Lshiftval_reg3,
sign_data = data[63],
sign_data_pipe = sign_data_reg2,
small_flag = small_flag_pipe_reg8,
small_flag_pipe = ((~ doRR) & E0_is_zero[10]),
squarerIn = (({27{(~ doRR_pipe)}} & squarerIn0) | ({27{doRR_pipe}} & squarerIn1)),
squarerIn0 = {absZ0s_pipe1, 1'b0},
squarerIn1 = Zfinal[54:28],
sR = sR_pipe3_reg3,
sR_pipe1 = (~ (data_exp_is_ebiase[10] | exp_data[10])),
sR_pipe2 = sR_pipe1_reg23,
sR_pipe3 = sR_pipe2_reg5,
sticky = {(Log_g[3] | sticky[2]), (Log_g[2] | sticky[1]), (Log_g[1] | sticky[0]), Log_g[0]},
Y0 = (({54{(~ First_bit)}} & man_below_half) | ({54{First_bit}} & man_above_half)),
Z2o2 = Z2o2_pipe_reg0,
Z2o2_pipe = wire_squarer_result,
Z2o2_small = {{28{1'b0}}, Z2o2_small_s, {3{1'b0}}},
Z2o2_small_s = Z2o2_small_s_pipe_reg0,
Z2o2_small_s_pipe = wire_Rshiftsmall_result[63:36],
Z_small = {absZ0s_pipe2, {33{1'b0}}},
Zfinal = wire_range_reduction_z,
Zfinal_pipe = Zfinal_reg1;
endmodule //acl_fp_log_s5_double_altfp_log_o3b
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_log_s5_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_log_s5_double_altfp_log_o3b acl_fp_log_s5_double_altfp_log_o3b_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_log"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "34"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_log_s5_double.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
module etx_fifo(/*AUTOARG*/
// Outputs
txrd_wait, txwr_wait, txrr_wait, txrd_fifo_access,
txrd_fifo_packet, txrr_fifo_access, txrr_fifo_packet,
txwr_fifo_access, txwr_fifo_packet,
// Inputs
sys_nreset, sys_clk, tx_lclk_div4, txrd_access, txrd_packet,
txwr_access, txwr_packet, txrr_access, txrr_packet, txrd_fifo_wait,
txrr_fifo_wait, txwr_fifo_wait
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104;
parameter RFAW = 6;
parameter ID = 12'h000;
parameter TARGET = "GENERIC";
//Clocks,reset,config
input sys_nreset;
input sys_clk;
input tx_lclk_div4; // slow speed parallel clock
//Read Request Channel Input
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Write Channel Input
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Response Channel Input
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Read request for pins
output txrd_fifo_access;
output [PW-1:0] txrd_fifo_packet;
input txrd_fifo_wait;
//Read response for pins
output txrr_fifo_access;
output [PW-1:0] txrr_fifo_packet;
input txrr_fifo_wait;
//Write for pins
output txwr_fifo_access;
output [PW-1:0] txwr_fifo_packet;
input txwr_fifo_wait;
/*AUTOOUTPUT*/
/*AUTOINPUT*/
/*AUTOWIRE*/
/************************************************************/
/*FIFOs */
/************************************************************/
//TODO: Minimize depth and width
/*fifo_cdc AUTO_TEMPLATE (
// Outputs
.access_out (@"(substring vl-cell-name 0 4)"_fifo_access),
.packet_out (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
.wait_out (@"(substring vl-cell-name 0 4)"_wait),
.wait_in (@"(substring vl-cell-name 0 4)"_fifo_wait),
.clk_out (tx_lclk_div4),
.clk_in (sys_clk),
.access_in (@"(substring vl-cell-name 0 4)"_access),
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
.nreset (sys_nreset),
.packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
);
*/
//Write fifo (from slave)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
txwr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txwr_wait), // Templated
.access_out (txwr_fifo_access), // Templated
.packet_out (txwr_fifo_packet[PW-1:0]), // Templated
// Inputs
.nreset (sys_nreset), // Templated
.clk_in (sys_clk), // Templated
.access_in (txwr_access), // Templated
.packet_in (txwr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.wait_in (txwr_fifo_wait)); // Templated
//Read request fifo (from slave)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
txrd_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrd_wait), // Templated
.access_out (txrd_fifo_access), // Templated
.packet_out (txrd_fifo_packet[PW-1:0]), // Templated
// Inputs
.nreset (sys_nreset), // Templated
.clk_in (sys_clk), // Templated
.access_in (txrd_access), // Templated
.packet_in (txrd_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.wait_in (txrd_fifo_wait)); // Templated
//Read response fifo (from master)
oh_fifo_cdc #(.DW(104), .DEPTH(32), .TARGET(TARGET))
txrr_fifo(
/*AUTOINST*/
// Outputs
.wait_out (txrr_wait), // Templated
.access_out (txrr_fifo_access), // Templated
.packet_out (txrr_fifo_packet[PW-1:0]), // Templated
// Inputs
.nreset (sys_nreset), // Templated
.clk_in (sys_clk), // Templated
.access_in (txrr_access), // Templated
.packet_in (txrr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.wait_in (txrr_fifo_wait)); // Templated
endmodule // elink
// Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
// End:
|
// WARNING: FULLY ASYNCHRONOUS DESIGN !
module i2c_slave (sda, scl, ioout, adr, reset, debug);
inout sda; // address or data input on sda is sampled on posedge of scl
input scl;
input reset;
input [6:0] adr; // the device address is always 7 bits wide !
output reg [7:0] ioout;
output debug;
reg start = 1; // l-active, must default to 1 on power up !
reg adr_match = 1; // defaults to 1 on power up
reg [4:0] ct = -1; // must default to -1 on power up (all bit set) !
reg [6:0] address = -1;
reg [7:0] data_rx = -1;
// delay m1_pre by 2 negator propagation delays
wire ct_reset;
wire m1_pre_neg /* synthesis keep = 1 */;
assign m1_pre_neg = !ct_reset;
wire m1 /* synthesis keep = 1 */;
assign m1 = !m1_pre_neg;
always @(negedge sda or negedge m1)
if (!m1) begin // !m1 sets start register
start <= 1'b1;
end else
begin
start <= !scl; // on bus starting, start goes low for a very short time until set back to high by negedge of m1
end
//assign debug = start;
//reg debug;
//always @*
// begin
// if (ct == 5'h1f) debug <= 1;
// else debug <= 0;
// end
always @(posedge scl or negedge reset) // or negedge start)
begin
if (!reset)
begin
ioout <= -1;
address <= -1;
data_rx <= -1;
end
else
begin
case (ct)
5'h00 : address[6] <= sda;
5'h01 : address[5] <= sda;
5'h02 : address[4] <= sda;
5'h03 : address[3] <= sda;
5'h04 : address[2] <= sda;
5'h05 : address[1] <= sda;
5'h06 : address[0] <= sda;
//5'h07 : rw_bit <= sda;
5'h09 : data_rx[7] <= sda;
5'h0a : data_rx[6] <= sda;
5'h0b : data_rx[5] <= sda;
5'h0c : data_rx[4] <= sda;
5'h0d : data_rx[3] <= sda;
5'h0e : data_rx[2] <= sda;
5'h0f : data_rx[1] <= sda;
5'h10 : data_rx[0] <= sda;
5'h11 : if (address == adr) ioout <= data_rx;
endcase
end
end
assign ct_reset = start & reset; // ored zeroes
always @(negedge scl or negedge ct_reset)
begin
if (!ct_reset) ct <= -1;
else ct <= ct +1; // posedge scl increments counter ct
end
always @(ct, adr, address)
begin
case (ct)
5'h08 : if (address == adr) adr_match <= 0; // address acknowledge
5'h11 : if (address == adr) adr_match <= 0; // data acknowledge
default : adr_match <= 1;
endcase
end
assign debug = adr_match;
assign sda = adr_match ? 1'bz : 1'b0;
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate continuous <= in assignment.
//
module main;
reg globvar;
reg [3:0] var1;
reg error;
wire var2 = (4'h02 >= var1);
initial
begin
error = 0;
var1 = 4'h0 ;
#1 ;
if(var2 !== 1'b1)
begin
$display("FAILED continuous >= logical op (1)");
error = 1;
end
#1 ;
var1 = 4'h2;
#1 ;
if(var2 !== 1'b1)
begin
$display("FAILED continuos <= logical op (2)");
error = 1;
end
#1 ;
var1 = 4'h4;
#1 ;
if(var2 !== 1'b0)
begin
$display("FAILED continuos <= logical op (3)");
error = 1;
end
if(error == 0)
$display("PASSED");
end
endmodule // main
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: rulefifo_64_32.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Standard Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rulefifo_64_32 (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [31:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [31:0] q;
output [5:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [31:0] sub_wire2;
wire [5:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [31:0] q = sub_wire2[31:0];
wire [5:0] usedw = sub_wire3[5:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.eccstatus (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix V",
scfifo_component.lpm_numwords = 64,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 32,
scfifo_component.lpm_widthu = 6,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 6 0 OUTPUT NODEFVAL "usedw[5..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 6 0 @usedw 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rulefifo_64_32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rulefifo_64_32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rulefifo_64_32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rulefifo_64_32.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rulefifo_64_32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rulefifo_64_32_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
`define RESET_ORIGIN 16'h0000
module test_S16X4();
reg [15:0] story_o;
reg clk_o;
reg res_o;
reg ack_o;
reg [15:0] dat_o;
wire [15:1] adr_i;
wire we_i;
wire cyc_i;
wire stb_i;
wire [1:0] sel_i;
wire vda_i;
wire vpa_i;
wire [15:0] dat_i;
wire bus_accessed = cyc_i & stb_i;
S16X4 cpu(
.res_i(res_o),
.clk_i(clk_o),
.adr_o(adr_i),
.we_o(we_i),
.cyc_o(cyc_i),
.stb_o(stb_i),
.sel_o(sel_i),
.vpa_o(vpa_i),
.vda_o(vda_i),
.dat_o(dat_i),
.ack_i(ack_o),
.dat_i(dat_o)
);
always begin
#50 clk_o <= ~clk_o;
end
initial begin
clk_o <= 0;
res_o <= 0;
ack_o <= 0;
dat_o <= 16'hDEAD;
wait(clk_o); wait(~clk_o);
// AS A hardware engineer
// I WANT the CPU to start execution at address $...000
// SO THAT I can jump to the appropriate initialization code.
story_o <= 16'h0000;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
if(cyc_i) begin
$display("Per Wishbone B3 standards, bus must be idle for one cycle after reset."); $stop;
end
if(stb_i) begin
$display("Per Wishbone B3 standards, bus must be idle for one cycle after reset."); $stop;
end
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN >> 1)) begin
$display("CPU should fetch its first instruction at $..FF0"); $stop;
end
if(we_i != 0) begin
$display("CPU should not be writing after a reset."); $stop;
end
if(bus_accessed != 1) begin
$display("CPU should be in a bus cycle while fetching its first instructions."); $stop;
end
if(sel_i != 2'h3) begin
$display("CPU should be fetching a full word."); $stop;
end
if(vpa_i != 1) begin
$display("CPU should be trying to fetch from program space right now."); $stop;
end
if(vda_i != 0) begin
$display("CPU should not be fetching an operand to an instruction."); $stop;
end
// AS A hardware engineer
// I WANT the CPU to pause on a fetch when ACK_I is negated
// SO THAT I can handle synchronous memories or slow peripherals.
story_o <= 16'h0010;
res_o <= 1;
ack_o <= 0;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN >> 1)) begin
$display("CPU should be fetching first instruction here."); $stop;
end
ack_o <= 1;
dat_o <= 16'h1000;
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN>>1)+1) begin
$display("CPU should have advanced to the first operand here."); $stop;
end
// AS A software engineer
// I WANT the CPU to fetch a literal value in response to the LIT opcode
// SO THAT I can perform fetches and stores to program variables.
story_o <= 16'h0020;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
if(vpa_i != 1) begin
$display("CPU should be trying to fetch from program space right now."); $stop;
end
if(vda_i != 0) begin
$display("CPU should not be fetching an operand to an instruction."); $stop;
end
dat_o <= 16'h1000;
wait(clk_o); wait(~clk_o);
if(vpa_i != 1) begin
$display("CPU should still be trying to fetch from program space."); $stop;
end
if(vda_i != 1) begin
$display("CPU should now be fetching an operand."); $stop;
end
dat_o <= 16'h1234;
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN >> 1)+2) begin
$display("CPU should have fetched opcode and operand by now."); $stop;
end
if(vda_i != 0) begin
$display("It's exhausted its instruction stream. It should be getting another instruction."); $stop;
end
// AS A software engineer
// I WANT predictable NOP timing
// SO THAT I can have cycle-accurate control over timing loops.
story_o <= 16'h0030;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
if(vpa_i != 1) begin
$display("CPU should be trying to fetch from program space right now."); $stop;
end
if(vda_i != 0) begin
$display("CPU should not be fetching an operand to an instruction."); $stop;
end
dat_o <= 16'h0010;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("CPU should never engage the bus during a NOP."); $stop;
end
if(vda_i) begin
$display("CPU should not be accessing data space here."); $stop;
end
if(vpa_i) begin
$display("CPU should not be accessing program space here."); $stop;
end
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("CPU should never engage the bus during a NOP."); $stop;
end
if(vda_i) begin
$display("CPU should not be accessing data space here."); $stop;
end
if(vpa_i) begin
$display("CPU should not be accessing program space here."); $stop;
end
wait(clk_o); wait(~clk_o);
if(~bus_accessed) begin
$display("CPU should try fetching an operand here."); $stop;
end
if(~vda_i) begin
$display("CPU should be accessing an operand here."); $stop;
end
if(~vpa_i) begin
$display("CPU should be accessing program space here."); $stop;
end
if(sel_i != 2'b11) begin
$display("Fetching a full word here."); $stop;
end
if(adr_i != (`RESET_ORIGIN>>1)+1) begin
$display("Fetching operand from wrong address"); $stop;
end
wait(clk_o); wait(~clk_o);
if(~bus_accessed) begin
$display("CPU should try fetching an opcode here."); $stop;
end
if(vda_i) begin
$display("CPU should be accessing an opcode here."); $stop;
end
if(~vpa_i) begin
$display("CPU should be accessing program space here."); $stop;
end
if(sel_i != 2'b11) begin
$display("Fetching a full word here."); $stop;
end
if(adr_i != (`RESET_ORIGIN>>1)+2) begin
$display("Fetching opcode from wrong address"); $stop;
end
// AS A software engineer
// I WANT the ability to store a word to memory
// SO THAT I can update program state.
story_o <= 16'h0040;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1130; // LI $BBBB:LI $AAAA:SWM:NOP
wait(clk_o); wait(~clk_o);
dat_o <= 16'hBBBB;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'h5555) begin
$display("CPU should be addressing memory location $AAAA right now."); $stop;
end
if(sel_i != 2'b11) begin
$display("CPU should be addressing a full word right now."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be engaging the bus during this cycle."); $stop;
end
if(~we_i) begin
$display("CPU should be writing during this cycle."); $stop;
end
if(~vda_i) begin
$display("CPU should be addressing data space during this cycle."); $stop;
end
if(vpa_i) begin
$display("CPU can never write to program space. EVER."); $stop;
end
if(dat_i != 16'hBBBB) begin
$display("CPU should be writing $BBBB during this cycle."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Expected P value mismatch."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be jonsing for an opcode fetch here."); $stop;
end
if(~vpa_i) begin
$display("Opcodes live in program space, yo."); $stop;
end
if(vda_i) begin
$display("Opcodes aren't operands, however."); $stop;
end
// AS A software engineer
// I WANT the ability to store a byte to an even memory address
// SO THAT I can update program state or, probably, I/O peripherals.
story_o <= 16'h0050;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h11B0; // LI $BBBB:LI $AAAA:SBM:NOP
wait(clk_o); wait(~clk_o);
dat_o <= 16'hBBBB;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'h5555) begin
$display("CPU should be addressing memory location $AAAA right now."); $stop;
end
if(sel_i != 2'b01) begin
$display("CPU should be addressing the low byte right now."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be engaging the bus during this cycle."); $stop;
end
if(~we_i) begin
$display("CPU should be writing during this cycle."); $stop;
end
if(~vda_i) begin
$display("CPU should be addressing data space during this cycle."); $stop;
end
if(vpa_i) begin
$display("CPU can never write to program space. EVER."); $stop;
end
if(dat_i != 16'h00BB) begin
$display("CPU should be writing $00BB during this cycle."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Expected P value mismatch."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be jonsing for an opcode fetch here."); $stop;
end
if(~vpa_i) begin
$display("Opcodes live in program space, yo."); $stop;
end
if(vda_i) begin
$display("Opcodes aren't operands, however."); $stop;
end
// AS A software engineer
// I WANT the ability to store a byte to an odd memory address
// SO THAT I can update program state or, probably, I/O peripherals.
story_o <= 16'h0060;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h11B0; // LI $BBBB:LI $AAAB:SBM:NOP
wait(clk_o); wait(~clk_o);
dat_o <= 16'hBBBB;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAB;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'h5555) begin
$display("CPU should be addressing memory location $AAAB right now."); $stop;
end
if(sel_i != 2'b10) begin
$display("CPU should be addressing the high byte right now."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be engaging the bus during this cycle."); $stop;
end
if(~we_i) begin
$display("CPU should be writing during this cycle."); $stop;
end
if(~vda_i) begin
$display("CPU should be addressing data space during this cycle."); $stop;
end
if(vpa_i) begin
$display("CPU can never write to program space. EVER."); $stop;
end
if(dat_i != 16'hBB00) begin
$display("CPU should be writing $BB00 during this cycle."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Expected P value mismatch."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be jonsing for an opcode fetch here."); $stop;
end
if(~vpa_i) begin
$display("Opcodes live in program space, yo."); $stop;
end
if(vda_i) begin
$display("Opcodes aren't operands, however."); $stop;
end
// AS A hardware engineer
// I WANT the ACKI_I input to be honored during memory write cycles
// SO THAT I can enjoy using this CPU with synchronous or slow devices.
story_o <= 16'h0070;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h11B0; // LI $BBBB:LI $AAAB:SBM:NOP
wait(clk_o); wait(~clk_o);
dat_o <= 16'hBBBB;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAB;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'h5555) begin
$display("CPU should be addressing memory location $AAAB right now."); $stop;
end
if(sel_i != 2'b10) begin
$display("CPU should be addressing the high byte right now."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be engaging the bus during this cycle."); $stop;
end
if(~we_i) begin
$display("CPU should be writing during this cycle."); $stop;
end
if(~vda_i) begin
$display("CPU should be addressing data space during this cycle."); $stop;
end
if(vpa_i) begin
$display("CPU can never write to program space. EVER."); $stop;
end
if(dat_i != 16'hBB00) begin
$display("CPU should be writing $BB00 during this cycle."); $stop;
end
ack_o <= 0;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'h5555) begin
$display("CPU should still be addressing memory location $AAAB right now."); $stop;
end
if(sel_i != 2'b10) begin
$display("CPU should still be addressing the high byte right now."); $stop;
end
if(~bus_accessed) begin
$display("CPU should still be engaging the bus during this cycle."); $stop;
end
if(~we_i) begin
$display("CPU should still be writing during this cycle."); $stop;
end
if(~vda_i) begin
$display("CPU should still be addressing data space during this cycle."); $stop;
end
if(vpa_i) begin
$display("CPU can never write to program space. EVER."); $stop;
end
if(dat_i != 16'hBB00) begin
$display("CPU should still be writing $BB00 during this cycle."); $stop;
end
ack_o <= 1;
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Expected P value mismatch."); $stop;
end
if(~bus_accessed) begin
$display("CPU should be jonsing for an opcode fetch here."); $stop;
end
if(~vpa_i) begin
$display("Opcodes live in program space, yo."); $stop;
end
if(vda_i) begin
$display("Opcodes aren't operands, however."); $stop;
end
// AS A software engineer
// I WANT to fetch words from memory
// SO THAT I can respond to previously established program state.
story_o <= 16'h0080;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1213; // LI $BBBB:FWM:LI $AAAA:SWM
wait(clk_o); wait(~clk_o);
dat_o <= 16'hBBBB;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'b101110111011101) begin
$display("Peek address not what I expected"); $stop;
end
if(we_i) begin
$display("We should be fetching, not storing."); $stop;
end
if(sel_i != 2'b11) begin
$display("We should be fetching a full word."); $stop;
end
if(vpa_i) begin
$display("We should be fetching from data memory."); $stop;
end
if(~vda_i) begin
$display("We should be fetching from data memory."); $stop;
end
if(~bus_accessed) begin
$display("We should be engaging the bus to fetch."); $stop;
end
dat_o <= 16'hBEEF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'b101010101010101) begin
$display("Poke address not what I expected"); $stop;
end
if(~we_i) begin
$display("We should be storing, not fetching."); $stop;
end
if(sel_i != 2'b11) begin
$display("We should be storing a full word."); $stop;
end
if(vpa_i) begin
$display("We should be storing to data memory."); $stop;
end
if(~vda_i) begin
$display("We should be storing to data memory."); $stop;
end
if(~bus_accessed) begin
$display("We should be engaging the bus to store."); $stop;
end
if(dat_i != 16'hBEEF) begin
$display("The value we just fetched should be on the output bus right now."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Poke address not what I expected"); $stop;
end
if(we_i) begin
$display("We should be fetching."); $stop;
end
if(sel_i != 2'b11) begin
$display("We should be fetching a full word."); $stop;
end
if(~vpa_i) begin
$display("We should be fetching the next opcode."); $stop;
end
if(vda_i) begin
$display("We should be fetching the next opcode."); $stop;
end
if(~bus_accessed) begin
$display("We should be engaging the bus to store."); $stop;
end
// AS A software engineer
// I WANT to fetch bytes from memory
// SO THAT I can look up LED segment values in a simple table.
story_o <= 16'h0090;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1A13; // LI $BBBB:FBM:LI $AAAA:SWM
wait(clk_o); wait(~clk_o);
dat_o <= 16'hBBBB;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'b101110111011101) begin
$display("Peek address not what I expected"); $stop;
end
if(we_i) begin
$display("We should be fetching, not storing."); $stop;
end
if(sel_i != 2'b10) begin
$display("We should be fetching a byte at an odd address."); $stop;
end
if(vpa_i) begin
$display("We should be fetching from data memory."); $stop;
end
if(~vda_i) begin
$display("We should be fetching from data memory."); $stop;
end
if(~bus_accessed) begin
$display("We should be engaging the bus to fetch."); $stop;
end
dat_o <= 16'hBEEF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(adr_i != 15'b101010101010101) begin
$display("Poke address not what I expected"); $stop;
end
if(~we_i) begin
$display("We should be storing, not fetching."); $stop;
end
if(sel_i != 2'b11) begin
$display("We should be storing a full word."); $stop;
end
if(vpa_i) begin
$display("We should be storing to data memory."); $stop;
end
if(~vda_i) begin
$display("We should be storing to data memory."); $stop;
end
if(~bus_accessed) begin
$display("We should be engaging the bus to store."); $stop;
end
if(dat_i != 16'h00BE) begin
$display("The value we just fetched should be on the output bus right now."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Poke address not what I expected"); $stop;
end
if(we_i) begin
$display("We should be fetching."); $stop;
end
if(sel_i != 2'b11) begin
$display("We should be fetching a full word."); $stop;
end
if(~vpa_i) begin
$display("We should be fetching the next opcode."); $stop;
end
if(vda_i) begin
$display("We should be fetching the next opcode."); $stop;
end
if(~bus_accessed) begin
$display("We should be engaging the bus to store."); $stop;
end
// AS A software engineer
// I WANT the ability to add numbers
// SO THAT I can index into an array and maintain count-down loops.
story_o <= 16'h00A0;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1141; // LI $7FFF:LI $0001:ADD:LI $xxxx
wait(clk_o); wait(~clk_o);
dat_o <= 16'h7FFF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'h0001;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ADD or XOR ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
dat_o <= 16'h7FFF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'h3000; // SWM:NOP:NOP:NOP
wait(clk_o); wait(~clk_o);
if(dat_i != 16'h8000) begin
$display("Addition appears broken somehow."); $stop;
end
// AS A software engineer
// I WANT the ability to mask bits
// SO THAT I can ignore don't-care bits when reading I/O registers.
story_o <= 16'h00B0;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1151; // LI $7FFF:LI $0001:AND:LI $xxxx
wait(clk_o); wait(~clk_o);
dat_o <= 16'h7FFF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'h0FF0;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ADD or XOR ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
dat_o <= 16'h7FFF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'h3000; // SWM:NOP:NOP:NOP
wait(clk_o); wait(~clk_o);
if(dat_i != 16'h0FF0) begin
$display("AND appears broken somehow."); $stop;
end
// AS A software engineer
// I WANT the ability to invert bits
// SO THAT I can subtract, logically-OR, test for opposing conditions, etc.
story_o <= 16'h00C0;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1161; // LI $7FFF:LI $0001:XOR:LI $xxxx
wait(clk_o); wait(~clk_o);
dat_o <= 16'h7FFF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'h0FF0;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ADD or XOR ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
dat_o <= 16'h7FFF;
wait(clk_o); wait(~clk_o);
dat_o <= 16'h3000; // SWM:NOP:NOP:NOP
wait(clk_o); wait(~clk_o);
if(dat_i != 16'h700F) begin
$display("AND appears broken somehow."); $stop;
end
// AS A software engineer
// I WANT the ability to branch on a false condition
// SO THAT I can make decisions during run-time.
story_o <= 16'h00D0;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1173; // LI 0:LI $AAAA:ZGO:SWM (Avoiding early instruction fetch ensures ZGO is the cause of immediate instruction fetch.)
wait(clk_o); wait(~clk_o);
dat_o <= 16'h0000;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ZGO, NZGO, and GO ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != 15'b101010101010101) begin
$display("ZGO should have branched when Y is zero."); $stop;
end
// AS A software engineer
// I WANT the ability to not branch on a true condition
// SO THAT I can make decisions during run-time.
story_o <= 16'h00E0;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1173; // LI 1:LI $AAAA:ZGO:SWM (Avoiding early instruction fetch ensures ZGO is the cause of immediate instruction fetch.)
wait(clk_o); wait(~clk_o);
dat_o <= 16'h0001;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ZGO, NZGO, and GO ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
if(~we_i) begin
$display("ZGO should not have branched; expected execution of SWM."); $stop;
end
wait(clk_o); wait(~clk_o);
if(vda_i) begin
$display("Should be fetching next opcode here"); $stop;
end
if(~vpa_i) begin
$display("In program space, that is."); $stop;
end
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Next instruction expected at $FFF6."); $stop;
end
// AS A software engineer
// I WANT the ability to skip a branch on a false condition
// SO THAT I can make decisions during run-time.
story_o <= 16'h00F0;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h11F3; // LI 0:LI $AAAA:NZGO:SWM (Avoiding early instruction fetch ensures ZGO is the cause of immediate instruction fetch.)
wait(clk_o); wait(~clk_o);
dat_o <= 16'h0000;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ZGO, NZGO, and GO ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
if(~we_i) begin
$display("NZGO should not have branched; expected execution of SWM."); $stop;
end
wait(clk_o); wait(~clk_o);
if(vda_i) begin
$display("Should be fetching next opcode here"); $stop;
end
if(~vpa_i) begin
$display("In program space, that is."); $stop;
end
if(adr_i != (`RESET_ORIGIN>>1)+3) begin
$display("Next instruction expected at $FFF6."); $stop;
end
// AS A software engineer
// I WANT the ability to branch on a true condition
// SO THAT I can make decisions during run-time.
story_o <= 16'h0100;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h11F3; // LI 1:LI $AAAA:NZGO:SWM (Avoiding early instruction fetch ensures ZGO is the cause of immediate instruction fetch.)
wait(clk_o); wait(~clk_o);
dat_o <= 16'h0001;
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ZGO, NZGO, and GO ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != 15'b101010101010101) begin
$display("NZGO should have branched when Y is non-zero."); $stop;
end
// AS A software engineer
// I WANT occasionally to branch unconditionally
// SO THAT I can create loops or jump vectors.
story_o <= 16'h0110;
res_o <= 1;
ack_o <= 1;
wait(clk_o); wait(~clk_o);
res_o <= 0;
wait(clk_o); wait(~clk_o);
wait(clk_o); wait(~clk_o);
dat_o <= 16'h1E33; // LI $AAAA:GO:SWM:SWM (Avoiding early instruction fetch ensures ZGO is the cause of immediate instruction fetch.)
wait(clk_o); wait(~clk_o);
dat_o <= 16'hAAAA;
wait(clk_o); wait(~clk_o);
if(bus_accessed) begin
$display("Internal operations like ZGO, NZGO, and GO ought not engage the bus."); $stop;
end
wait(clk_o); wait(~clk_o);
if(adr_i != 15'b101010101010101) begin
$display("GO should have branched."); $stop;
end
story_o <= 16'hFFFF;
$stop;
end
endmodule
|
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR2_1_V
`define SKY130_FD_SC_LP__XNOR2_1_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_1 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xnor2_1 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR2_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_BLACKBOX_V
`define SKY130_FD_SC_HVL__AND3_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_BLACKBOX_V
|
module SortX16 # (
parameter DSIZE = 18,
parameter OFFSET = 8
)(
input [DSIZE-1:0] a0,
input [DSIZE-1:0] a1,
input [DSIZE-1:0] a2,
input [DSIZE-1:0] a3,
input [DSIZE-1:0] a4,
input [DSIZE-1:0] a5,
input [DSIZE-1:0] a6,
input [DSIZE-1:0] a7,
input [DSIZE-1:0] a8,
input [DSIZE-1:0] a9,
input [DSIZE-1:0] a10,
input [DSIZE-1:0] a11,
input [DSIZE-1:0] a12,
input [DSIZE-1:0] a13,
input [DSIZE-1:0] a14,
input [DSIZE-1:0] a15,
output wire [DSIZE-1:0] sort0,
output wire [DSIZE-1:0] sort1,
output wire [DSIZE-1:0] sort2,
output wire [DSIZE-1:0] sort3,
output wire [DSIZE-1:0] sort4,
output wire [DSIZE-1:0] sort5,
output wire [DSIZE-1:0] sort6,
output wire [DSIZE-1:0] sort7,
output wire [DSIZE-1:0] sort8,
output wire [DSIZE-1:0] sort9,
output wire [DSIZE-1:0] sort10,
output wire [DSIZE-1:0] sort11,
output wire [DSIZE-1:0] sort12,
output wire [DSIZE-1:0] sort13,
output wire [DSIZE-1:0] sort14,
output wire [DSIZE-1:0] sort15
);
wire [DSIZE-1:0] sortX8_0_0;
wire [DSIZE-1:0] sortX8_0_1;
wire [DSIZE-1:0] sortX8_0_2;
wire [DSIZE-1:0] sortX8_0_3;
wire [DSIZE-1:0] sortX8_0_4;
wire [DSIZE-1:0] sortX8_0_5;
wire [DSIZE-1:0] sortX8_0_6;
wire [DSIZE-1:0] sortX8_0_7;
wire [DSIZE-1:0] sortX8_1_0;
wire [DSIZE-1:0] sortX8_1_1;
wire [DSIZE-1:0] sortX8_1_2;
wire [DSIZE-1:0] sortX8_1_3;
wire [DSIZE-1:0] sortX8_1_4;
wire [DSIZE-1:0] sortX8_1_5;
wire [DSIZE-1:0] sortX8_1_6;
wire [DSIZE-1:0] sortX8_1_7;
wire [DSIZE-1:0] sort0_0;
wire [DSIZE-1:0] sort0_1;
wire [DSIZE-1:0] sort1_0;
wire [DSIZE-1:0] sort1_1;
wire [DSIZE-1:0] sort2_0;
wire [DSIZE-1:0] sort2_1;
wire [DSIZE-1:0] sort3_0;
wire [DSIZE-1:0] sort3_1;
wire [DSIZE-1:0] sort4_0;
wire [DSIZE-1:0] sort4_1;
wire [DSIZE-1:0] sort5_0;
wire [DSIZE-1:0] sort5_1;
wire [DSIZE-1:0] sort6_0;
wire [DSIZE-1:0] sort6_1;
wire [DSIZE-1:0] sort7_0;
wire [DSIZE-1:0] sort7_1;
// divide sort
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst0 (
.a0 (a0),
.a1 (a1),
.a2 (a2),
.a3 (a3),
.a4 (a4),
.a5 (a5),
.a6 (a6),
.a7 (a7),
.sort0 (sortX8_0_0),
.sort1 (sortX8_0_1),
.sort2 (sortX8_0_2),
.sort3 (sortX8_0_3),
.sort4 (sortX8_0_4),
.sort5 (sortX8_0_5),
.sort6 (sortX8_0_6),
.sort7 (sortX8_0_7)
);
SortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sortX8_inst1 (
.a0 (a8),
.a1 (a9),
.a2 (a10),
.a3 (a11),
.a4 (a12),
.a5 (a13),
.a6 (a14),
.a7 (a15),
.sort0 (sortX8_1_0),
.sort1 (sortX8_1_1),
.sort2 (sortX8_1_2),
.sort3 (sortX8_1_3),
.sort4 (sortX8_1_4),
.sort5 (sortX8_1_5),
.sort6 (sortX8_1_6),
.sort7 (sortX8_1_7)
);
// merge
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst0 (
.a(sortX8_0_0),
.b(sortX8_1_7),
.sort0(sort0_0),
.sort1(sort0_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst1 (
.a(sortX8_0_1),
.b(sortX8_1_6),
.sort0(sort1_0),
.sort1(sort1_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst2 (
.a(sortX8_0_2),
.b(sortX8_1_5),
.sort0(sort2_0),
.sort1(sort2_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst3 (
.a(sortX8_0_3),
.b(sortX8_1_4),
.sort0(sort3_0),
.sort1(sort3_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst4 (
.a(sortX8_0_4),
.b(sortX8_1_3),
.sort0(sort4_0),
.sort1(sort4_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst5 (
.a(sortX8_0_5),
.b(sortX8_1_2),
.sort0(sort5_0),
.sort1(sort5_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst6 (
.a(sortX8_0_6),
.b(sortX8_1_1),
.sort0(sort6_0),
.sort1(sort6_1)
);
SortElement # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) sort_inst7 (
.a(sortX8_0_7),
.b(sortX8_1_0),
.sort0(sort7_0),
.sort1(sort7_1)
);
// bitonic
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst0 (
.a0 (sort0_0),
.a1 (sort1_0),
.a2 (sort2_0),
.a3 (sort3_0),
.a4 (sort4_0),
.a5 (sort5_0),
.a6 (sort6_0),
.a7 (sort7_0),
.sort0 (sort0),
.sort1 (sort1),
.sort2 (sort2),
.sort3 (sort3),
.sort4 (sort4),
.sort5 (sort5),
.sort6 (sort6),
.sort7 (sort7)
);
BitonicSortX8 # (
.DSIZE (DSIZE),
.OFFSET(OFFSET)
) bitonicsortx8_inst1 (
.a0 (sort7_1),
.a1 (sort6_1),
.a2 (sort5_1),
.a3 (sort4_1),
.a4 (sort3_1),
.a5 (sort2_1),
.a6 (sort1_1),
.a7 (sort0_1),
.sort0 (sort8),
.sort1 (sort9),
.sort2 (sort10),
.sort3 (sort11),
.sort4 (sort12),
.sort5 (sort13),
.sort6 (sort14),
.sort7 (sort15)
);
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller wrapper
//
// File : alt_ddrx_controller_wrapper.v
//
// Abstract : This file is a wrapper that configures DDRx controller
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//
module ddr3_int_alt_ddrx_controller_wrapper (
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
local_ready,
local_read_req,
local_write_req,
local_wdata_req,
local_size,
local_burstbegin,
local_addr,
local_rdata_valid,
local_rdata_error,
local_rdata,
local_wdata,
local_be,
local_autopch_req,
local_multicast,
local_init_done,
local_refresh_req,
local_refresh_chip,
local_refresh_ack,
local_self_rfsh_req,
local_self_rfsh_chip,
local_self_rfsh_ack,
local_power_down_ack,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_odt,
afi_rst_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_doing_read,
afi_rdata,
afi_rdata_valid,
csr_write_req,
csr_read_req,
csr_addr,
csr_be,
csr_wdata,
csr_waitrequest,
csr_rdata,
csr_rdata_valid,
ecc_interrupt,
bank_information,
bank_open
);
//Inserted Generics
localparam MEM_TYPE = "DDR3";
localparam LOCAL_SIZE_WIDTH = 7;
localparam LOCAL_ADDR_WIDTH = 25;
localparam LOCAL_DATA_WIDTH = 128;
localparam LOCAL_IF_TYPE = "AVALON";
localparam MEM_IF_CS_WIDTH = 1;
localparam MEM_IF_CHIP_BITS = 1;
localparam MEM_IF_CKE_WIDTH = 1;
localparam MEM_IF_ODT_WIDTH = 1;
localparam MEM_IF_ADDR_WIDTH = 14;
localparam MEM_IF_ROW_WIDTH = 14;
localparam MEM_IF_COL_WIDTH = 10;
localparam MEM_IF_BA_WIDTH = 3;
localparam MEM_IF_DQS_WIDTH = 4;
localparam MEM_IF_DQ_WIDTH = 32;
localparam MEM_IF_DM_WIDTH = 4;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_CS_PER_DIMM = 1;
localparam DWIDTH_RATIO = 4;
localparam CTL_LOOK_AHEAD_DEPTH = 8;
localparam CTL_CMD_QUEUE_DEPTH = 8;
localparam CTL_HRB_ENABLED = 0;
localparam CTL_ECC_ENABLED = 0;
localparam CTL_ECC_RMW_ENABLED = 0;
localparam CTL_ECC_CSR_ENABLED = 0;
localparam CTL_CSR_ENABLED = 0;
localparam CTL_ODT_ENABLED = 0;
localparam CSR_ADDR_WIDTH = 16;
localparam CSR_DATA_WIDTH = 32;
localparam CTL_OUTPUT_REGD = 0;
localparam MEM_CAS_WR_LAT = 5;
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 6;
localparam MEM_TRRD = 4;
localparam MEM_TFAW = 13;
localparam MEM_TRFC = 34;
localparam MEM_TREFI = 2341;
localparam MEM_TRCD = 5;
localparam MEM_TRP = 5;
localparam MEM_TWR = 5;
localparam MEM_TWTR = 4;
localparam MEM_TRTP = 4;
localparam MEM_TRAS = 12;
localparam MEM_TRC = 16;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 2;
localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
localparam CTL_ECC_MULTIPLES_40_72 = 0;
localparam CTL_USR_REFRESH = 0;
localparam CTL_REGDIMM_ENABLED = 0;
localparam MULTICAST_WR_EN = 0;
localparam LOW_LATENCY = 0;
localparam CTL_DYNAMIC_BANK_ALLOCATION = 0;
localparam CTL_DYNAMIC_BANK_NUM = 4;
localparam ENABLE_BURST_MERGE = 0;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output local_ready;
input local_read_req;
input local_write_req;
output local_wdata_req;
input [LOCAL_SIZE_WIDTH-1:0] local_size;
input local_burstbegin;
input [LOCAL_ADDR_WIDTH-1:0] local_addr;
output local_rdata_valid;
output local_rdata_error;
output [LOCAL_DATA_WIDTH-1:0] local_rdata;
input [LOCAL_DATA_WIDTH-1:0] local_wdata;
input [LOCAL_DATA_WIDTH/8-1:0] local_be;
input local_autopch_req;
input local_multicast;
output local_init_done;
input local_refresh_req;
input [MEM_IF_CS_WIDTH-1:0] local_refresh_chip;
output local_refresh_ack;
input local_self_rfsh_req;
input [MEM_IF_CS_WIDTH-1:0] local_self_rfsh_chip;
output local_self_rfsh_ack;
output local_power_down_ack;
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1:0] ctl_mem_clk_disable;
output [(MEM_IF_DQS_WIDTH*MEM_IF_CS_WIDTH) - 1:0] ctl_cal_byte_lane_sel_n;
output [(MEM_IF_CKE_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_odt;
output [(DWIDTH_RATIO/2) - 1:0] afi_rst_n;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_dqs_burst;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_wdata_valid;
output [(MEM_IF_DQ_WIDTH*DWIDTH_RATIO) - 1:0] afi_wdata;
output [(MEM_IF_DM_WIDTH*DWIDTH_RATIO) - 1:0] afi_dm;
input [4:0] afi_wlat;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_doing_read;
input [(MEM_IF_DQ_WIDTH * DWIDTH_RATIO) - 1:0] afi_rdata;
input [(DWIDTH_RATIO/2) - 1:0] afi_rdata_valid;
input csr_write_req;
input csr_read_req;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [(CSR_DATA_WIDTH / 8) - 1 : 0] csr_be;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output csr_waitrequest;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
output csr_rdata_valid;
output ecc_interrupt;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH) - 1:0] bank_information;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH)) - 1:0] bank_open;
alt_ddrx_controller # (
.MEM_TYPE ( MEM_TYPE ),
.LOCAL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ),
.LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ),
.LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ),
.LOCAL_IF_TYPE ( LOCAL_IF_TYPE ),
.MEM_IF_CS_WIDTH ( MEM_IF_CS_WIDTH ),
.MEM_IF_CHIP_BITS ( MEM_IF_CHIP_BITS ),
.MEM_IF_CKE_WIDTH ( MEM_IF_CKE_WIDTH ),
.MEM_IF_ODT_WIDTH ( MEM_IF_ODT_WIDTH ),
.MEM_IF_ADDR_WIDTH ( MEM_IF_ADDR_WIDTH ),
.MEM_IF_ROW_WIDTH ( MEM_IF_ROW_WIDTH ),
.MEM_IF_COL_WIDTH ( MEM_IF_COL_WIDTH ),
.MEM_IF_BA_WIDTH ( MEM_IF_BA_WIDTH ),
.MEM_IF_DQS_WIDTH ( MEM_IF_DQS_WIDTH ),
.MEM_IF_DQ_WIDTH ( MEM_IF_DQ_WIDTH ),
.MEM_IF_DM_WIDTH ( MEM_IF_DM_WIDTH ),
.MEM_IF_CLK_PAIR_COUNT ( MEM_IF_CLK_PAIR_COUNT ),
.MEM_IF_CS_PER_DIMM ( MEM_IF_CS_PER_DIMM ),
.DWIDTH_RATIO ( DWIDTH_RATIO ),
.CTL_LOOK_AHEAD_DEPTH ( CTL_LOOK_AHEAD_DEPTH ),
.CTL_CMD_QUEUE_DEPTH ( CTL_CMD_QUEUE_DEPTH ),
.CTL_HRB_ENABLED ( CTL_HRB_ENABLED ),
.CTL_ECC_ENABLED ( CTL_ECC_ENABLED ),
.CTL_ECC_RMW_ENABLED ( CTL_ECC_RMW_ENABLED ),
.CTL_ECC_CSR_ENABLED ( CTL_ECC_CSR_ENABLED ),
.CTL_ECC_MULTIPLES_40_72 ( CTL_ECC_MULTIPLES_40_72 ),
.CTL_CSR_ENABLED ( CTL_CSR_ENABLED ),
.CTL_ODT_ENABLED ( CTL_ODT_ENABLED ),
.CTL_REGDIMM_ENABLED ( CTL_REGDIMM_ENABLED ),
.CSR_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CSR_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CTL_OUTPUT_REGD ( CTL_OUTPUT_REGD ),
.CTL_USR_REFRESH ( CTL_USR_REFRESH ),
.MEM_CAS_WR_LAT ( MEM_CAS_WR_LAT ),
.MEM_ADD_LAT ( MEM_ADD_LAT ),
.MEM_TCL ( MEM_TCL ),
.MEM_TRRD ( MEM_TRRD ),
.MEM_TFAW ( MEM_TFAW ),
.MEM_TRFC ( MEM_TRFC ),
.MEM_TREFI ( MEM_TREFI ),
.MEM_TRCD ( MEM_TRCD ),
.MEM_TRP ( MEM_TRP ),
.MEM_TWR ( MEM_TWR ),
.MEM_TWTR ( MEM_TWTR ),
.MEM_TRTP ( MEM_TRTP ),
.MEM_TRAS ( MEM_TRAS ),
.MEM_TRC ( MEM_TRC ),
.MEM_AUTO_PD_CYCLES ( MEM_AUTO_PD_CYCLES ),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT ( MEM_IF_RD_TO_WR_TURNAROUND_OCT ),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT ( MEM_IF_WR_TO_RD_TURNAROUND_OCT ),
.ADDR_ORDER ( ADDR_ORDER ),
.MULTICAST_WR_EN ( MULTICAST_WR_EN ),
.LOW_LATENCY ( LOW_LATENCY ),
.CTL_DYNAMIC_BANK_ALLOCATION ( CTL_DYNAMIC_BANK_ALLOCATION ),
.CTL_DYNAMIC_BANK_NUM ( CTL_DYNAMIC_BANK_NUM ),
.ENABLE_BURST_MERGE ( ENABLE_BURST_MERGE )
) alt_ddrx_controller_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_half_clk ( ctl_half_clk ),
.ctl_half_clk_reset_n ( ctl_half_clk_reset_n ),
.local_ready ( local_ready ),
.local_read_req ( local_read_req ),
.local_write_req ( local_write_req ),
.local_wdata_req ( local_wdata_req ),
.local_size ( local_size ),
.local_burstbegin ( local_burstbegin ),
.local_addr ( local_addr ),
.local_rdata_valid ( local_rdata_valid ),
.local_rdata_error ( local_rdata_error ),
.local_rdata ( local_rdata ),
.local_wdata ( local_wdata ),
.local_be ( local_be ),
.local_autopch_req ( local_autopch_req ),
.local_multicast ( local_multicast ),
.local_init_done ( local_init_done ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_power_down_ack ( local_power_down_ack ),
.ctl_cal_success ( ctl_cal_success ),
.ctl_cal_fail ( ctl_cal_fail ),
.ctl_cal_req ( ctl_cal_req ),
.ctl_mem_clk_disable ( ctl_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( ctl_cal_byte_lane_sel_n ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_doing_read ( afi_doing_read ),
.afi_doing_read_full ( ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.csr_write_req ( csr_write_req ),
.csr_read_req ( csr_read_req ),
.csr_addr ( csr_addr ),
.csr_be ( csr_be ),
.csr_wdata ( csr_wdata ),
.csr_waitrequest ( csr_waitrequest ),
.csr_rdata ( csr_rdata ),
.csr_rdata_valid ( csr_rdata_valid ),
.ecc_interrupt ( ecc_interrupt ),
.bank_information ( bank_information ),
.bank_open ( bank_open )
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.7
// \ \ Application: MIG
// / / Filename: infrastructure.v
// /___/ /\ Date Last Modified: $Date: 2010/10/29 15:22:39 $
// \ \ / \ Date Created:Tue Jun 30 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: infrastructure.v,v 1.2 2010/10/29 15:22:39 pboya Exp $
**$Date: 2010/10/29 15:22:39 $
**$Author: pboya $
**$Revision: 1.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_7/data/dlib/virtex6/ddr3_sdram/verilog/rtl/ip_top/infrastructure.v,v $
******************************************************************************/
`timescale 1ps/1ps
module infrastructure #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter CLK_PERIOD = 3000, // Internal (fabric) clk period
parameter nCK_PER_CLK = 2, // External (memory) clock period =
// CLK_PERIOD/nCK_PER_CLK
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter MMCM_ADV_BANDWIDTH = "OPTIMIZED", // MMCM programming algorithm
parameter CLKFBOUT_MULT_F = 2, // write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor
parameter CLKOUT_DIVIDE = 2, // VCO output divisor for fast
// (memory) clocks
parameter RST_ACT_LOW = 1
)
(
// Clock inputs
input mmcm_clk, // System clock diff input
// System reset input
input sys_rst, // core reset from user application
// MMCM/IDELAYCTRL Lock status
input iodelay_ctrl_rdy, // IDELAYCTRL lock status
// Clock outputs
output clk_mem, // 2x logic clock
output clk, // 1x logic clock
output clk_rd_base, // 2x base read clock
// Reset outputs
output rstdiv0, // Reset CLK and CLKDIV logic (incl I/O),
// Phase Shift Interface
input PSEN, // For enabling fine-phase shift
input PSINCDEC, // = 1 increment phase shift, = 0
output PSDONE
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
// Round up for clk reset delay to ensure that CLKDIV reset deassertion
// occurs at same time or after CLK reset deassertion (still need to
// consider route delay - add one or two extra cycles to be sure!)
localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2;
localparam real CLKIN1_PERIOD
= (CLKFBOUT_MULT_F * CLK_PERIOD)/
(DIVCLK_DIVIDE * CLKOUT_DIVIDE * nCK_PER_CLK * 1000.0); // in ns
localparam integer VCO_PERIOD
= (DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK);
localparam CLKOUT0_DIVIDE_F = CLKOUT_DIVIDE;
localparam CLKOUT1_DIVIDE = CLKOUT_DIVIDE * nCK_PER_CLK;
localparam CLKOUT2_DIVIDE = CLKOUT_DIVIDE;
localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE_F;
localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE;
localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE;
//synthesis translate_off
initial begin
$display("############# Write Clocks MMCM_ADV Parameters #############\n");
$display("nCK_PER_CLK = %7d", nCK_PER_CLK );
$display("CLK_PERIOD = %7d", CLK_PERIOD );
$display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD );
$display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE );
$display("CLKFBOUT_MULT_F = %7d", CLKFBOUT_MULT_F );
$display("VCO_PERIOD = %7d", VCO_PERIOD );
$display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE_F);
$display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE );
$display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE );
$display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD );
$display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD );
$display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD );
$display("############################################################\n");
end
//synthesis translate_on
wire clk_bufg;
wire clk_mem_bufg;
wire clk_mem_pll;
wire clk_pll;
wire clkfbout_pll;
wire pll_lock
/* synthesis syn_maxfan = 10 */;
reg [RST_DIV_SYNC_NUM-1:0] rstdiv0_sync_r
/* synthesis syn_maxfan = 10 */;
wire rst_tmp;
wire sys_rst_act_hi;
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Assign global clocks:
// 1. clk_mem : Full rate (used only for IOB)
// 2. clk : Half rate (used for majority of internal logic)
//***************************************************************************
assign clk_mem = clk_mem_bufg;
assign clk = clk_bufg;
//***************************************************************************
// Global base clock generation and distribution
//***************************************************************************
//*****************************************************************
// NOTES ON CALCULTING PROPER VCO FREQUENCY
// 1. VCO frequency =
// 1/((DIVCLK_DIVIDE * CLK_PERIOD)/(CLKFBOUT_MULT_F * nCK_PER_CLK))
// 2. VCO frequency must be in the range [800MHz, 1.2MHz] for -1 part.
// The lower limit of 800MHz is greater than the lower supported
// frequency of 400MHz according to the datasheet because the MMCM
// jitter performance improves significantly when the VCO is operatin
// above 800MHz. For speed grades faster than -1, the max VCO frequency
// will be highe, and the multiply and divide factors can be adjusted
// according (in general to run the VCO as fast as possible).
//*****************************************************************
MMCM_ADV #
(
.BANDWIDTH (MMCM_ADV_BANDWIDTH),
.CLOCK_HOLD ("FALSE"),
.COMPENSATION ("INTERNAL"),
.REF_JITTER1 (0.005),
.REF_JITTER2 (0.005),
.STARTUP_WAIT ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.CLKIN2_PERIOD (10.000),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_USE_FINE_PS ("TRUE"),
.CLKOUT3_DIVIDE (1),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_CASCADE ("FALSE"),
.CLKOUT4_DIVIDE (1),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKOUT5_DIVIDE (1),
.CLKOUT5_DUTY_CYCLE (0.500),
.CLKOUT5_PHASE (0.000),
.CLKOUT5_USE_FINE_PS ("FALSE"),
.CLKOUT6_DIVIDE (1),
.CLKOUT6_DUTY_CYCLE (0.500),
.CLKOUT6_PHASE (0.000),
.CLKOUT6_USE_FINE_PS ("FALSE")
)
u_mmcm_adv
(
.CLKFBOUT (clkfbout_pll),
.CLKFBOUTB (),
.CLKFBSTOPPED (),
.CLKINSTOPPED (),
.CLKOUT0 (clk_mem_pll),
.CLKOUT0B (),
.CLKOUT1 (clk_pll),
.CLKOUT1B (),
.CLKOUT2 (clk_rd_base),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.DO (),
.DRDY (),
.LOCKED (pll_lock),
.PSDONE (PSDONE),
.CLKFBIN (clkfbout_pll),
.CLKIN1 (mmcm_clk),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.DADDR (7'b0000000),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0000),
.DWE (1'b0),
.PSCLK (clk_bufg),
.PSEN (PSEN),
.PSINCDEC (PSINCDEC),
.PWRDWN (1'b0),
.RST (sys_rst_act_hi)
);
BUFG u_bufg_clk0
(
.O (clk_mem_bufg),
.I (clk_mem_pll)
);
BUFG u_bufg_clkdiv0
(
.O (clk_bufg),
.I (clk_pll)
);
//***************************************************************************
// RESET SYNCHRONIZATION DESCRIPTION:
// Various resets are generated to ensure that:
// 1. All resets are synchronously deasserted with respect to the clock
// domain they are interfacing to. There are several different clock
// domains - each one will receive a synchronized reset.
// 2. The reset deassertion order starts with deassertion of SYS_RST,
// followed by deassertion of resets for various parts of the design
// (see "RESET ORDER" below) based on the lock status of MMCMs.
// RESET ORDER:
// 1. User deasserts SYS_RST
// 2. Reset MMCM and IDELAYCTRL
// 3. Wait for MMCM and IDELAYCTRL to lock
// 4. Release reset for all I/O primitives and internal logic
// OTHER NOTES:
// 1. Asynchronously assert reset. This way we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers
// to prevent initial bus contention). Reset deassertion is synchronous.
//***************************************************************************
//*****************************************************************
// CLKDIV logic reset
//*****************************************************************
// Wait for MMCM and IDELAYCTRL to lock before releasing reset
assign rst_tmp = sys_rst_act_hi | ~pll_lock | ~iodelay_ctrl_rdy;
always @(posedge clk_bufg or posedge rst_tmp)
if (rst_tmp)
rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}};
else
rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1;
assign rstdiv0 = rstdiv0_sync_r[RST_DIV_SYNC_NUM-1];
endmodule
|