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/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
// This is the top level of token ring interconnect for global memory access.
// It has two modes: default (with data reordering block) and sw-dimm-partition (without data reordering; slow switch between banks).
module lsu_ic_top (
clk,
resetn,
// from LSUs
i_rd_byteenable,
i_rd_address,
i_rd_request,
i_rd_burstcount,
i_wr_byteenable,
i_wr_address,
i_wr_request,
i_wr_burstcount,
i_wr_writedata,
// from MEM
i_avm_waitrequest,
i_avm_readdata,
i_avm_readdatavalid,
// to MEM
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_burstcount,
o_avm_writedata,
// to LSUs
o_rd_waitrequest,
o_wr_waitrequest,
o_avm_readdata,
o_avm_readdatavalid,
o_avm_writeack
);
parameter AWIDTH = 32; // memory address width
parameter SHIFT = 10; // for address permutation
parameter ENABLE_PERMUTE = 1; // enable address permutation
parameter MWIDTH_BYTES = 64; // memory bus width
parameter BURST_CNT_W = 5; // max burst number width
parameter NUM_RD_PORT = 2; // number of read ports
parameter NUM_WR_PORT = 2; // number of write ports
parameter NUM_DIMM = 1; // number of physical banks
parameter RETURN_DATA_FIFO_DEPTH = 512; // data reordering FIFO depth per bank
// parameter MAX_MEM_DELAY is used as Read ID/burstcount FIFO depth, to generate o_avm_readdatavalid
// Almost-full threshold is set to (MAX_MEM_DELAY - NUM_RD_PORT*2-5); stall is generated to read ring when the threshold is hit
// It selects (NUM_RD_PORT*2+6) as depth when this number is greater than 512, to gurantee a positive Almost-full threshold
parameter MAX_MEM_DELAY = ((NUM_RD_PORT*2+6) > 512)? (NUM_RD_PORT*2+6) : 512;
parameter ENABLE_REORDER = 0; // set it to 0 in SW_DIMM_PARTITION mode
parameter DISABLE_ROOT_FIFO = 0; // disable root fifo if token ring's root FIFO is merged in iface
parameter ENABLE_READ_FAST = NUM_RD_PORT<10; // if set to 1, read latency is decreased, lower Fmax
parameter ENABLE_DUAL_RING = 1;
parameter ENABLE_MULTIPLE_WR_RING = 0; // enable N write rings; N == number of banks
localparam NUM_ID = NUM_RD_PORT+NUM_WR_PORT; // number of LSUs
parameter ROOT_FIFO_DEPTH = 512; // Token root FIFO depth
parameter NUM_REORDER = 1; // Number of reordering blocks for burst interleaved mode
parameter DEVICE = "Stratix V"; // Device name
parameter ENABLE_LAST_WAIT = 0; // A temperary fix for global const_cache, which needs avm_waitrequest == 0 to send load request in some cases
localparam RD_ROOT_FIFO_DEPTH = MAX_MEM_DELAY; // Read only root FIFO depth
localparam MWIDTH=8*MWIDTH_BYTES;
localparam ID_WIDTH = $clog2(NUM_ID);
localparam NUM_DIMM_W = $clog2(NUM_DIMM);
localparam MAX_BURST = 2 ** (BURST_CNT_W-1);
localparam ROOT_FIFO_AW = (ROOT_FIFO_DEPTH >= (5+NUM_WR_PORT*2+MAX_BURST))? $clog2(ROOT_FIFO_DEPTH) : $clog2(5+NUM_WR_PORT*2+MAX_BURST);
localparam ROOT_RD_FIFO_AW = $clog2(RD_ROOT_FIFO_DEPTH);
localparam LOG2BYTES = $clog2(MWIDTH_BYTES);
localparam PAGE_ADDR_WIDTH = AWIDTH - LOG2BYTES;
// avoid modelsim compile error
localparam P_NUM_RD_PORT = (NUM_RD_PORT > 0)? NUM_RD_PORT : 1;
localparam P_NUM_WR_PORT = (NUM_WR_PORT > 0)? NUM_WR_PORT : 1;
input clk;
input resetn;
// from LSU
input [MWIDTH_BYTES-1:0] i_rd_byteenable [P_NUM_RD_PORT];
input [AWIDTH-1:0] i_rd_address [P_NUM_RD_PORT];
input i_rd_request [P_NUM_RD_PORT];
input [BURST_CNT_W-1:0] i_rd_burstcount [P_NUM_RD_PORT];
input [MWIDTH_BYTES-1:0] i_wr_byteenable [P_NUM_WR_PORT];
input [AWIDTH-1:0] i_wr_address [P_NUM_WR_PORT];
input i_wr_request [P_NUM_WR_PORT];
input [BURST_CNT_W-1:0] i_wr_burstcount [P_NUM_WR_PORT];
input [MWIDTH-1:0] i_wr_writedata [P_NUM_WR_PORT];
// from MEM
input i_avm_waitrequest [NUM_DIMM];
input [MWIDTH-1:0] i_avm_readdata [NUM_DIMM];
input i_avm_readdatavalid [NUM_DIMM];
// to MEM
output [MWIDTH_BYTES-1:0] o_avm_byteenable [NUM_DIMM];
output [AWIDTH-NUM_DIMM_W-1:0] o_avm_address [NUM_DIMM];
output o_avm_read [NUM_DIMM];
output o_avm_write [NUM_DIMM];
output [BURST_CNT_W-1:0] o_avm_burstcount [NUM_DIMM];
output [MWIDTH-1:0] o_avm_writedata [NUM_DIMM];
// to LSU
output o_rd_waitrequest [P_NUM_RD_PORT];
output o_wr_waitrequest [P_NUM_WR_PORT];
output [MWIDTH-1:0] o_avm_readdata [P_NUM_RD_PORT];
output o_avm_readdatavalid [P_NUM_RD_PORT];
output logic o_avm_writeack [P_NUM_WR_PORT];
integer i, j;
genvar z;
wire[ID_WIDTH-1:0] o_id [NUM_DIMM];
wire [PAGE_ADDR_WIDTH-1:0] ci_avm_rd_addr [P_NUM_RD_PORT];
wire [PAGE_ADDR_WIDTH-1:0] ci_avm_wr_addr [P_NUM_WR_PORT];
wire [PAGE_ADDR_WIDTH-NUM_DIMM_W-1:0] co_avm_address [NUM_DIMM];
// help timing; reduce the high fanout of global reset from iface
reg [1:0] sync_rst_MS /* synthesis syn_preserve = 1 */ ;
wire sync_rst;
assign sync_rst = sync_rst_MS[1];
always @(posedge clk or negedge resetn) begin
if(!resetn) sync_rst_MS <= 2'b11;
else sync_rst_MS <= {sync_rst_MS[0], 1'b0};
end
`ifdef GEN_ACCESS_CNT
// This part is used to trace the number of requests received from LSUs and sent to global memory
// for simulation or signalTap mem access analysis
// add /* synthesis syn_noprune syn_preserve = 1 */ for signalTap
logic [31:0] i_receive_cnt [NUM_ID]; // num of requests received from LSUs
logic [31:0] o_return_to_lsu_cnt [NUM_ID]; // returned to LSUs
logic [8:0] err_cnt_lsu [NUM_ID];
logic [0:NUM_ID-1] err_lsu;
logic [31:0] o_rd_to_mem_cnt, i_return_cnt;
logic [8:0] err_cnt_global;
logic [31:0] sum_receive [NUM_RD_PORT];
logic [31:0] sum_return [NUM_RD_PORT];
debug_io_cnt #(.WIDTH(6)) globl_mem_io_checker (
.rst(!resetn),
.clk(clk),
.i_0(((o_avm_read[0] & !i_avm_waitrequest[0])? o_avm_burstcount[0] : 0) + ((o_avm_read[1] & !i_avm_waitrequest[1])? o_avm_burstcount[1] : 0)),
.i_1(i_avm_readdatavalid[0] + i_avm_readdatavalid[1] + 6'd0),
.o_cnt_0(o_rd_to_mem_cnt),
.o_cnt_1(i_return_cnt),
.o_mismatch_cnt(err_cnt_global)
);
generate
always @(posedge clk) begin
for(i=0; i<NUM_ID; i=i+1) err_lsu[i] <= |err_cnt_lsu[i];
end
for(z=0; z<NUM_RD_PORT; z=z+1) begin : GEN_RD_LSU_IO_CNT
assign sum_receive[z] = (z==0)? i_receive_cnt[0] : i_receive_cnt[z] + sum_receive[z-1];
assign sum_return[z] = (z==0)? o_return_to_lsu_cnt[0] : o_return_to_lsu_cnt[z] + sum_return[z-1];
debug_io_cnt #(.WIDTH(6)) lsu_io_checker (
.rst(!resetn),
.clk(clk),
.i_0(((i_rd_request[z] & !o_rd_waitrequest[z])? i_rd_burstcount[z] : 0)),
.i_1(o_avm_readdatavalid[z] + 0),
.o_cnt_0(i_receive_cnt[z]),
.o_cnt_1(o_return_to_lsu_cnt[z]),
.o_mismatch_cnt(err_cnt_lsu[z])
);
end
for(z=0; z<NUM_WR_PORT; z=z+1) begin : GEN_WR_LSU_IO_CNT
debug_io_cnt #(.WIDTH(6)) lsu_io_checker (
.rst(!resetn),
.clk(clk),
.i_0((i_wr_request[z] & !o_wr_waitrequest[z]) + 6'd0),
.i_1(o_avm_writeack[z] + 6'd0),
.o_cnt_0(i_receive_cnt[z+NUM_RD_PORT]),
.o_cnt_1(o_return_to_lsu_cnt[z+NUM_RD_PORT]),
.o_mismatch_cnt(err_cnt_lsu[z+NUM_RD_PORT])
);
end
endgenerate
`endif
generate
if(ENABLE_PERMUTE && ENABLE_REORDER && NUM_DIMM > 1) begin : GEN_ENABLE_ADDR_PERMUTE
for(z=0; z<NUM_RD_PORT; z=z+1) begin : PERMUTE_RD_ADDR
assign ci_avm_rd_addr[z] = {i_rd_address[z][SHIFT], i_rd_address[z][AWIDTH-1:SHIFT+1], i_rd_address[z][SHIFT-1:LOG2BYTES]};
end
for(z=0; z<NUM_WR_PORT; z=z+1) begin : PERMUTE_WR_ADDR
assign ci_avm_wr_addr[z] = {i_wr_address[z][SHIFT], i_wr_address[z][AWIDTH-1:SHIFT+1], i_wr_address[z][SHIFT-1:LOG2BYTES]};
end
end
else begin : GEN_DISABLE_ADDR_PERMUTE
for(z=0; z<NUM_RD_PORT; z=z+1) begin : PERMUTE_RD_ADDR
assign ci_avm_rd_addr[z] = i_rd_address[z][AWIDTH-1:LOG2BYTES];
end
for(z=0; z<NUM_WR_PORT; z=z+1) begin : PERMUTE_WR_ADDR
assign ci_avm_wr_addr[z] = i_wr_address[z][AWIDTH-1:LOG2BYTES];
end
end
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_PAD_O_ADDR
assign o_avm_address[z] = {co_avm_address[z], {LOG2BYTES{1'b0}}};
end
if(ENABLE_REORDER == 0 && NUM_DIMM > 1) begin : GEN_SW_DIMM
lsu_swdimm_token_ring #(
.AWIDTH(PAGE_ADDR_WIDTH),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W (BURST_CNT_W),
.NUM_RD_PORT(NUM_RD_PORT),
.NUM_WR_PORT(NUM_WR_PORT),
.MAX_MEM_DELAY(MAX_MEM_DELAY),
.DISABLE_ROOT_FIFO(DISABLE_ROOT_FIFO),
.ENABLE_READ_FAST(ENABLE_READ_FAST),
.NUM_DIMM(NUM_DIMM),
.ROOT_FIFO_AW(ROOT_FIFO_AW),
.RD_ROOT_FIFO_AW(ROOT_RD_FIFO_AW),
.ENABLE_LAST_WAIT(ENABLE_LAST_WAIT),
.ENABLE_MULTIPLE_WR_RING(ENABLE_MULTIPLE_WR_RING),
.ENABLE_DUAL_RING(1),
.DEVICE(DEVICE)
)lsu_ic (
.clk (clk ),
.reset (sync_rst ),
.i_rd_byteenable (i_rd_byteenable ),
.i_rd_address (ci_avm_rd_addr ),
.i_rd_request (i_rd_request ),
.i_rd_burstcount (i_rd_burstcount ),
.i_wr_byteenable (i_wr_byteenable ),
.i_wr_address (ci_avm_wr_addr ),
.i_wr_request (i_wr_request ),
.i_wr_burstcount (i_wr_burstcount ),
.i_wr_writedata (i_wr_writedata ),
.i_avm_waitrequest (i_avm_waitrequest ),
.i_avm_readdata (i_avm_readdata ),
.i_avm_return_valid (i_avm_readdatavalid),
.o_id (o_id),
.o_avm_byteenable (o_avm_byteenable ),
.o_avm_address (co_avm_address ),
.o_avm_read (o_avm_read ),
.o_avm_write (o_avm_write ),
.o_avm_burstcount (o_avm_burstcount ),
.o_avm_writedata (o_avm_writedata ),
.o_rd_waitrequest (o_rd_waitrequest ),
.o_wr_waitrequest (o_wr_waitrequest ),
.o_avm_readdata (o_avm_readdata ),
.o_avm_readdatavalid(o_avm_readdatavalid),
.o_avm_writeack (o_avm_writeack )
);
end
else begin : GEN_SIMPLE
lsu_token_ring #(
.AWIDTH(PAGE_ADDR_WIDTH),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W (BURST_CNT_W),
.NUM_RD_PORT(NUM_RD_PORT),
.NUM_WR_PORT(NUM_WR_PORT),
.NUM_DIMM(NUM_DIMM),
.RETURN_DATA_FIFO_DEPTH(RETURN_DATA_FIFO_DEPTH),
.PIPELINE_RD_RETURN(0),
.MAX_MEM_DELAY(MAX_MEM_DELAY),
.ENABLE_MULTIPLE_WR_RING(ENABLE_MULTIPLE_WR_RING),
.ENABLE_READ_FAST(ENABLE_READ_FAST),
.DISABLE_ROOT_FIFO(DISABLE_ROOT_FIFO),
.ROOT_FIFO_AW(ROOT_FIFO_AW),
.RD_ROOT_FIFO_AW(ROOT_RD_FIFO_AW),
.ENABLE_DATA_REORDER(ENABLE_REORDER),
.NUM_REORDER(NUM_REORDER),
.ENABLE_LAST_WAIT(ENABLE_LAST_WAIT),
.ENABLE_DUAL_RING(1),
.DEVICE(DEVICE)
)lsu_ic (
.clk (clk ),
.reset (sync_rst ),
.i_rd_byteenable (i_rd_byteenable ),
.i_rd_address (ci_avm_rd_addr ),
.i_rd_request (i_rd_request ),
.i_rd_burstcount (i_rd_burstcount ),
.i_wr_byteenable (i_wr_byteenable ),
.i_wr_address (ci_avm_wr_addr ),
.i_wr_request (i_wr_request ),
.i_wr_burstcount (i_wr_burstcount ),
.i_wr_writedata (i_wr_writedata ),
.i_avm_waitrequest (i_avm_waitrequest ),
.i_avm_readdata (i_avm_readdata ),
.i_avm_return_valid (i_avm_readdatavalid),
.o_avm_byteenable (o_avm_byteenable ),
.o_avm_address (co_avm_address ),
.o_avm_read (o_avm_read ),
.o_avm_write (o_avm_write ),
.o_avm_burstcount (o_avm_burstcount ),
.o_avm_writedata (o_avm_writedata ),
.o_rd_waitrequest (o_rd_waitrequest ),
.o_wr_waitrequest (o_wr_waitrequest ),
.o_avm_readdata (o_avm_readdata ),
.o_avm_readdatavalid(o_avm_readdatavalid),
.o_avm_writeack (o_avm_writeack )
);
end
endgenerate
endmodule
// This is a basic block in token ring. It has two sets of input signals: one set is from a LSU; and the other is from the previous lsu_ic_token it connects to.
// The output is registered. It selects the input based on if it owns token.
// Token is passed to the next lsu_ic_token block if it owns th token and the LSU it serves has no active request.
module lsu_ic_token (
clk,
reset,
i_token,
i_id,
i_avm_waitrequest, // backpressure from root FIFO
i_avm_byteenable,
i_avm_address,
i_avm_read,
i_avm_write,
i_avm_burstcount,
o_avm_waitrequest_0,
o_avm_waitrequest_1,
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_burstcount,
o_id,
o_index,
o_token,
o_active,
// write
i_avm_writedata,
o_avm_writedata
);
parameter AWIDTH=32;
parameter NUM_DIMM = 1;
parameter MWIDTH_BYTES=64;
parameter BURST_CNT_W=6;
parameter READ = 1;
parameter START_ACTIVE = 0;
parameter ID_WIDTH = 1;
parameter FIFO_DEPTH = 64;
parameter ENABLE_LAST_WAIT = 0;
parameter ENABLE_DATA_REORDER = 0;
parameter DEVICE = "Stratix V";
localparam FIFO_AW = $clog2(FIFO_DEPTH);
localparam MWIDTH=8*MWIDTH_BYTES;
localparam REQUEST_FIFO_AW = 8;
localparam REQUEST_FIFO_DEPTH = 2**REQUEST_FIFO_AW;
localparam REQ_WIDTH_READ = AWIDTH + BURST_CNT_W + ID_WIDTH;
localparam REQ_WIDTH_WRITE = AWIDTH + BURST_CNT_W + MWIDTH + MWIDTH_BYTES + ID_WIDTH;
localparam REQ_WIDTH_WIDER = (REQ_WIDTH_WRITE > REQ_WIDTH_READ)? REQ_WIDTH_WRITE : REQ_WIDTH_READ;
localparam REQ_WIDTH = (READ? REQ_WIDTH_READ : REQ_WIDTH_WRITE);
localparam DIMM_W = $clog2(NUM_DIMM);
input clk;
input reset;
input i_token;
input [ID_WIDTH-1:0] i_id [2];
input i_avm_waitrequest [NUM_DIMM];
input [MWIDTH_BYTES-1:0] i_avm_byteenable [2];
input [AWIDTH-1:0] i_avm_address [2];
input i_avm_read [2];
input i_avm_write [2];
input [BURST_CNT_W-1:0] i_avm_burstcount [2];
output reg o_avm_waitrequest_0 [NUM_DIMM];
output reg o_avm_waitrequest_1;
output [MWIDTH_BYTES-1:0] o_avm_byteenable;
output [AWIDTH-1:0] o_avm_address;
output reg o_avm_read;
output reg o_avm_write;
output [BURST_CNT_W-1:0] o_avm_burstcount;
input [MWIDTH-1:0] i_avm_writedata[2];
output [MWIDTH-1:0] o_avm_writedata;
output [ID_WIDTH-1:0] o_id;
output reg o_token;
output o_active;
output reg [ID_WIDTH-1:0] o_index;
integer i;
genvar z;
reg active;
wire [REQ_WIDTH-1:0] i_req [2];
reg [REQ_WIDTH-1:0] request_dout;
wire [0:NUM_DIMM-1] backpressure;
wire backpressure_stall;
wire pass_token;
assign o_active = active;
assign backpressure_stall = |backpressure;
always @(posedge clk) begin
request_dout <= active? i_req[1] : i_req[0];
end
always @(posedge clk or posedge reset) begin
if(reset) begin
for(i=0; i<NUM_DIMM; i=i+1) o_avm_waitrequest_0[i] <= 1'b0;
o_avm_waitrequest_1 <= !START_ACTIVE;
o_avm_read <= 1'b0;
o_avm_write <= 1'b0;
active <= START_ACTIVE;
o_token <= 1'b0;
o_index <= '0;
end
else begin
o_token <= 1'b0;
if(ENABLE_LAST_WAIT) begin
if(i_token) begin
active <= 1'b1;
o_index <= i_id[1];
end
else if(active) begin
o_token <= pass_token;
active <= !pass_token;
if(pass_token) o_index <= '0;
end
end
else begin
if(pass_token) begin
active <= 1'b0;
o_token <= active | i_token;
o_index <= '0;
end
else if(i_token) begin
active <= 1'b1;
o_index <= i_id[1];
end
end
o_avm_waitrequest_0 <= i_avm_waitrequest; // pass backpressure to the next node
o_avm_waitrequest_1 <= !active & (!i_token | ENABLE_LAST_WAIT == 0) | backpressure_stall | pass_token & active;
o_avm_read <= active & !o_avm_waitrequest_1 & i_avm_read[1] | i_avm_read[0];
o_avm_write <= active & !o_avm_waitrequest_1 & i_avm_write[1] | i_avm_write[0];
end
end
generate
if(NUM_DIMM > 1 & !ENABLE_DATA_REORDER & READ) begin : GEN_MULTIPLE_STALL
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_
assign backpressure[z] = i_avm_waitrequest[z] & i_avm_address[1][AWIDTH-1:AWIDTH-DIMM_W] == z;
end
end
else begin : GEN_SINGLE_STALL
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_
assign backpressure[z] = i_avm_waitrequest[z];
end
end
if(READ) begin : ENABLE_READ
assign pass_token = !i_avm_read[1] | backpressure_stall;
assign i_req[0] = {i_avm_address[0], i_avm_burstcount[0], i_id[0]};
assign i_req[1] = {i_avm_address[1], i_avm_burstcount[1], i_id[1]};
assign {o_avm_address, o_avm_burstcount, o_id} = request_dout;
assign o_avm_byteenable = {MWIDTH_BYTES{1'b1}};
end
else begin : ENABLE_WRITE
assign pass_token = !i_avm_write[1];
assign i_req[0] = {i_avm_address[0], i_avm_burstcount[0], i_avm_writedata[0], i_avm_byteenable[0], i_id[0]} ;
assign i_req[1] = {i_avm_address[1], i_avm_burstcount[1], i_avm_writedata[1], i_avm_byteenable[1], i_id[1]} ;
assign {o_avm_address, o_avm_burstcount, o_avm_writedata, o_avm_byteenable, o_id} = request_dout;
end
endgenerate
endmodule
// A group of the basic unit lsu_ic_token
module lsu_n_token (
clk,
reset,
i_token,
i_id,
i_ext_address,
i_ext_read,
i_ext_burstcount,
o_ext_waitrequest,
i_avm_waitrequest,
i_avm_byteenable,
i_avm_address,
i_avm_read,
i_avm_write,
i_avm_burstcount,
o_avm_waitrequest,
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_burstcount,
o_id,
o_token,
o_active,
// write
i_avm_writedata,
o_avm_writedata
);
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter MWIDTH_BYTES=64; // Width of the global memory bus (bytes)
parameter BURST_CNT_W=6;
parameter NUM_PORT = 10;
parameter START_ID = 0;
parameter READ = 1;
parameter ENABLE_FAST = 0;
parameter OPEN_RING = 0;
parameter START_ACTIVE = 0;
parameter NUM_DIMM = 1;
parameter ENABLE_DATA_REORDER = 0;
parameter ROOT_FIFO_AW = 8;
parameter ROOT_FIFO_THRESH = (NUM_PORT+START_ID)*2;
parameter ENABLE_LAST_WAIT = 0;
parameter ID_WIDTH = (NUM_PORT+START_ID == 1 )? 1 : $clog2(NUM_PORT+START_ID);
parameter SINGLE_STALL = 0;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam REQ_WIDTH_READ = AWIDTH + BURST_CNT_W + ID_WIDTH;
localparam REQ_WIDTH_WRITE = AWIDTH + BURST_CNT_W + MWIDTH + MWIDTH_BYTES + ID_WIDTH;
localparam REQ_WIDTH = READ? REQ_WIDTH_READ : REQ_WIDTH_WRITE;
localparam ROOT_FIFO_DEPTH = 2 ** ROOT_FIFO_AW;
localparam NUM_DIMM_INT = SINGLE_STALL? 1 : NUM_DIMM;
input clk;
input reset;
// from another open ring part
input [ID_WIDTH-1:0] i_id;
input i_token;
input [AWIDTH-1:0] i_ext_address;
input i_ext_read;
input [BURST_CNT_W-1:0] i_ext_burstcount;
output o_ext_waitrequest [NUM_DIMM];
// from LSUs
input [MWIDTH_BYTES-1:0] i_avm_byteenable [NUM_PORT];
input [AWIDTH-1:0] i_avm_address [NUM_PORT];
input i_avm_read [NUM_PORT];
input i_avm_write [NUM_PORT];
input [BURST_CNT_W-1:0] i_avm_burstcount [NUM_PORT];
// to LSUs
output o_avm_waitrequest [NUM_PORT];
output o_token;
output o_active [NUM_PORT];
// from memory
input i_avm_waitrequest [NUM_DIMM];
// to memory
output [MWIDTH_BYTES-1:0] o_avm_byteenable;
output [AWIDTH-1:0] o_avm_address;
output o_avm_read;
output o_avm_write;
output [BURST_CNT_W-1:0] o_avm_burstcount;
output [ID_WIDTH-1:0] o_id;
// write
input [MWIDTH-1:0] i_avm_writedata [NUM_PORT];
output [MWIDTH-1:0] o_avm_writedata;
genvar z, z0;
wire [ID_WIDTH-1:0] ci_id [NUM_PORT][2];
wire [MWIDTH_BYTES-1:0] ci_byteenable [NUM_PORT][2];
wire [AWIDTH-1:0] ci_address [NUM_PORT][2];
wire ci_read [NUM_PORT][2];
wire ci_write [NUM_PORT][2];
wire [BURST_CNT_W-1:0] ci_burstcount [NUM_PORT][2];
wire ci_token [NUM_PORT];
wire ci_waitrequest [NUM_PORT][NUM_DIMM_INT];
wire co_waitrequest_0 [NUM_PORT][NUM_DIMM_INT];
wire co_waitrequest_1 [NUM_PORT];
wire [MWIDTH-1:0] co_readdata [NUM_PORT];
wire co_return_valid [NUM_PORT][2];
wire [MWIDTH_BYTES-1:0] co_byteenable [NUM_PORT];
wire [AWIDTH-1:0] co_address [NUM_PORT];
wire co_read [NUM_PORT];
wire co_write [NUM_PORT];
wire [BURST_CNT_W-1:0] co_burstcount [NUM_PORT];
wire [ID_WIDTH-1:0] co_id [NUM_PORT];
wire co_token [NUM_PORT];
wire [ID_WIDTH-1:0] co_index [NUM_PORT];
wire [MWIDTH-1:0] ci_writedata [NUM_PORT][2];
wire [MWIDTH-1:0] co_writedata [NUM_PORT];
generate
if(ENABLE_FAST) begin : GEN_ENABLE_FAST
wire i_avm_wait_int [NUM_DIMM_INT];
if(NUM_DIMM_INT > 1) begin
assign i_avm_wait_int = i_avm_waitrequest;
end
else begin
assign i_avm_wait_int[0] = i_avm_waitrequest[0];
end
lsu_n_fast #(
.AWIDTH(AWIDTH),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W(BURST_CNT_W),
.NUM_PORT(NUM_PORT),
.START_ID(START_ID),
.ID_WIDTH(ID_WIDTH),
.OPEN_RING(OPEN_RING),
.NUM_DIMM(NUM_DIMM_INT),
.ENABLE_DATA_REORDER(ENABLE_DATA_REORDER),
.START_ACTIVE(START_ACTIVE|!OPEN_RING),
.ENABLE_LAST_WAIT(ENABLE_LAST_WAIT),
.READ(READ)
) lsu_n_fast (
.clk (clk),
.reset (reset),
.i_ext_read (1'b0),
.i_avm_write (i_avm_write),
.i_token (i_token),
.i_avm_address (i_avm_address),
.i_avm_read (i_avm_read),
.i_avm_burstcount (i_avm_burstcount),
.o_avm_waitrequest(o_avm_waitrequest),
.i_avm_waitrequest(i_avm_wait_int),
.o_avm_address (o_avm_address),
.o_avm_read (o_avm_read),
.o_avm_burstcount (o_avm_burstcount),
.o_token (o_token),
.o_id (o_id)
);
end
else begin : GEN_DISABLE_FAST
assign o_avm_byteenable = co_byteenable [NUM_PORT-1];
assign o_avm_address = co_address [NUM_PORT-1];
assign o_avm_read = co_read [NUM_PORT-1];
assign o_avm_write = co_write [NUM_PORT-1];
assign o_avm_burstcount = co_burstcount [NUM_PORT-1];
assign o_id = co_id [NUM_PORT-1];
assign o_token = co_token [NUM_PORT-1];
assign o_avm_writedata = co_writedata [NUM_PORT-1];
if(NUM_DIMM_INT > 1) begin
assign ci_waitrequest[NUM_PORT-1] = i_avm_waitrequest;
assign o_ext_waitrequest = co_waitrequest_0[0];
end
else begin
assign ci_waitrequest[NUM_PORT-1][0] = i_avm_waitrequest[0];
assign o_ext_waitrequest[0] = co_waitrequest_0[0][0];
end
for(z=0; z<NUM_PORT; z=z+1) begin : GEN_IC
if(z==0) begin
assign ci_token[z] = OPEN_RING? i_token : co_token [NUM_PORT - 1];
assign ci_read [z][0] = OPEN_RING? i_ext_read : 1'b0;
assign ci_write [z][0] = 1'b0;
assign ci_id [z][0] = i_id;
assign ci_byteenable [z][0] = '1;
assign ci_address [z][0] = i_ext_address;
assign ci_burstcount [z][0] = i_ext_burstcount;
assign ci_read [z][1] = i_avm_read [0];
assign ci_write [z][1] = i_avm_write[0];
assign ci_id [z][1] = START_ID;
assign ci_byteenable [z][1] = i_avm_byteenable [0];
assign ci_address [z][1] = i_avm_address [0];
assign ci_burstcount [z][1] = i_avm_burstcount [0];
assign ci_writedata [z][1] = i_avm_writedata [0];
end
else begin
assign ci_token[z] = co_token [z-1];
assign ci_read [z][0] = co_read [z-1];
assign ci_write [z][0] = co_write [z-1];
assign ci_id [z][0] = co_id [z-1];
assign ci_byteenable [z][0] = co_byteenable [z-1];
assign ci_address [z][0] = co_address [z-1];
assign ci_burstcount [z][0] = co_burstcount [z-1];
assign ci_writedata [z][0] = co_writedata [z-1];
assign ci_id [z][1] = START_ID+z;
assign ci_byteenable [z][1] = i_avm_byteenable [z];
assign ci_address [z][1] = i_avm_address [z];
assign ci_read [z][1] = i_avm_read [z];
assign ci_write [z][1] = i_avm_write [z];
assign ci_burstcount [z][1] = i_avm_burstcount [z];
assign ci_writedata [z][1] = i_avm_writedata [z];
end
assign o_avm_waitrequest[z] = co_waitrequest_1[z];
if(z < NUM_PORT - 1) assign ci_waitrequest[z] = co_waitrequest_0[z+1];
lsu_ic_token #(
.AWIDTH(AWIDTH),
.START_ACTIVE(z==0 & (START_ACTIVE|!OPEN_RING)),
.ENABLE_DATA_REORDER(ENABLE_DATA_REORDER),
.MWIDTH_BYTES(MWIDTH_BYTES),
.READ(READ),
.ENABLE_LAST_WAIT(ENABLE_LAST_WAIT & (z == NUM_PORT - 1)),
.ID_WIDTH(ID_WIDTH),
.NUM_DIMM(NUM_DIMM_INT),
.BURST_CNT_W(BURST_CNT_W)
) ic (
.clk(clk),
.reset(reset),
.i_token(ci_token[z]),
.i_id(ci_id[z]),
.i_avm_waitrequest(ci_waitrequest[z]),
.i_avm_byteenable(ci_byteenable[z]),
.i_avm_address(ci_address[z]),
.i_avm_read(ci_read[z]),
.i_avm_write(ci_write[z]),
.i_avm_burstcount(ci_burstcount[z]),
.i_avm_writedata(ci_writedata[z]),
.o_avm_writedata(co_writedata[z]),
.o_avm_waitrequest_0(co_waitrequest_0[z]),
.o_avm_waitrequest_1(co_waitrequest_1[z]),
.o_avm_byteenable(co_byteenable[z]),
.o_avm_address(co_address[z]),
.o_avm_read(co_read[z]),
.o_avm_write(co_write[z]),
.o_avm_burstcount(co_burstcount[z]),
.o_token(co_token[z]),
.o_index(co_index[z]),
.o_active(o_active[z]),
.o_id(co_id[z])
);
end // end GEN_MULTIPLE_PORT
`ifdef SIM_ONLY
reg burst_done;
reg [BURST_CNT_W-1:0] cnt;
reg [AWIDTH-1:0] R_address;
reg error;
if(READ == 0) begin : GEN_WRITE_DEBUG
always @(posedge clk or posedge reset) begin
if(reset) begin
cnt <= 1;
burst_done <= 1'b0;
error <= 1'b0;
end
else begin
if(o_avm_write) begin
R_address <= o_avm_address;
cnt <= (cnt == o_avm_burstcount)? 1 : cnt + 1;
burst_done <= cnt == o_avm_burstcount;
error <= (R_address != o_avm_address) & !burst_done;
if(error) begin
$display("write ring error");
$stop;
end
end
end
end
end
`endif
end
endgenerate
endmodule
// This block is used for load ring.
// The datapath for load ring is much narrower compared with store ring
// In most cases, it does not need a group of 2-to-1 MUX to pipeline the selected request.
// Instead, a N-to-1 one clock cycle delay MUX is enough.
// It is optional, enabled by setting lsu_ic_top.ENABLE_READ_FAST
module lsu_n_fast (
clk,
reset,
i_token,
i_ext_id,
i_ext_address,
i_ext_read,
i_ext_burstcount,
o_ext_waitrequest,
i_avm_waitrequest,
i_avm_byteenable,
i_avm_address,
i_avm_read,
i_avm_write,
i_avm_burstcount,
o_avm_waitrequest,
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_request,
o_avm_burstcount,
o_id,
o_token,
// write
i_avm_writedata,
o_avm_writedata
);
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter MWIDTH_BYTES=64; // Width of the global memory bus (bytes)
parameter BURST_CNT_W=6;
parameter NUM_PORT = 10;
parameter NUM_DIMM = 2;
parameter START_ID = 0;
parameter READ = 1;
parameter ENABLE_DATA_REORDER = 0;
parameter OPEN_RING = 0;
parameter START_ACTIVE = 0;
parameter ID_WIDTH = (NUM_PORT+START_ID == 1 )? 1 : $clog2(NUM_PORT+START_ID);
parameter ENABLE_LAST_WAIT = 0;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam DIMM_W = $clog2(NUM_DIMM);
localparam REQ_WIDTH_READ = AWIDTH + BURST_CNT_W + ID_WIDTH;
localparam REQ_WIDTH_WRITE = AWIDTH + BURST_CNT_W + MWIDTH + MWIDTH_BYTES + ID_WIDTH;
localparam REQ_WIDTH = READ? REQ_WIDTH_READ : REQ_WIDTH_WRITE;
input clk;
input reset;
// from another open ring part
input [ID_WIDTH-1:0] i_ext_id;
input [AWIDTH-1:0] i_ext_address;
input i_ext_read;
input [BURST_CNT_W-1:0] i_ext_burstcount;
// from LSUs
input i_token;
input [MWIDTH_BYTES-1:0] i_avm_byteenable [NUM_PORT];
input [AWIDTH-1:0] i_avm_address [NUM_PORT];
input i_avm_read [NUM_PORT];
input i_avm_write [NUM_PORT];
input [BURST_CNT_W-1:0] i_avm_burstcount [NUM_PORT];
// to LSUs
output reg o_avm_waitrequest [NUM_PORT];
output reg o_token;
// from memory
input i_avm_waitrequest [NUM_DIMM];
// to another open ring
output reg o_ext_waitrequest [NUM_DIMM]; // delayed i_avm_waitrequest
// to memory
output [MWIDTH_BYTES-1:0] o_avm_byteenable;
output [AWIDTH-1:0] o_avm_address;
output o_avm_read;
output o_avm_write;
output o_avm_request;
output [BURST_CNT_W-1:0] o_avm_burstcount;
output [ID_WIDTH-1:0] o_id;
// write
input [MWIDTH-1:0] i_avm_writedata [NUM_PORT];
output [MWIDTH-1:0] o_avm_writedata;
integer i;
genvar z, z0;
wire i_avm_request [NUM_PORT];
wire [ID_WIDTH-1:0] i_id [NUM_PORT];
wire [REQ_WIDTH-1:0] i_req [NUM_PORT];
wire [REQ_WIDTH-1:0] ext_req;
reg active;
reg [ID_WIDTH-1:0] ptr;
wire [REQ_WIDTH-1:0] request_dout;
wire [0:NUM_DIMM-1] backpressure_stall [NUM_PORT];
wire backpressure [NUM_PORT];
reg avm_read [NUM_PORT];
reg avm_write [NUM_PORT];
reg avm_request [NUM_PORT];
wire avm_read_wire;
wire avm_write_wire;
wire avm_request_wire;
reg avm_read_p;
reg avm_write_p;
reg avm_request_p;
reg [BURST_CNT_W-1:0] wr_cnt;
reg wr_burst_done;
wire pass_token;
assign avm_read_wire = active & !o_avm_waitrequest[ptr] & i_avm_read[ptr];
assign avm_write_wire = active & !o_avm_waitrequest[ptr] & i_avm_write[ptr];
assign avm_request_wire = active & !o_avm_waitrequest[ptr] & i_avm_request[ptr];
assign ext_req = {i_ext_address, i_ext_burstcount, {MWIDTH{1'b0}}, {MWIDTH_BYTES{1'b1}}, i_ext_id};
always @(posedge clk or posedge reset) begin
if(reset) begin
avm_read_p <= 1'b0;
avm_write_p <= 1'b0;
avm_request_p <= 1'b0;
for(i=0; i<NUM_DIMM; i=i+1) begin
o_ext_waitrequest[i] <= 1'b0;
end
for(i=0; i<NUM_PORT; i=i+1) begin
avm_read[i] <= 0;
avm_write[i] <= 0;
avm_request[i] <= 0;
end
end
else begin
avm_read_p <= avm_read_wire;
avm_write_p <= avm_write_wire;
avm_request_p <= avm_request_wire;
for(i=0; i<NUM_DIMM; i=i+1) begin
o_ext_waitrequest[i] <= i_avm_waitrequest[i];
end
for(i=0; i<NUM_PORT; i=i+1) begin
if(active & i==ptr) begin
avm_read[i] <= avm_read_wire;
avm_write[i] <= avm_write_wire;
avm_request[i] <= avm_request_wire;
end
else if(i>0) begin
avm_read[i] <= avm_read[i-1];
avm_write[i] <= avm_write[i-1];
avm_request[i] <= avm_request[i-1];
end
else begin
avm_read[0] <= i_ext_read;
avm_write[0] <= 1'b0;
avm_request[0] <= i_ext_read;
end
end
end
end
generate
if(ENABLE_LAST_WAIT) begin : GEN_ENABLE_LAST_WAIT
always @(posedge clk or posedge reset) begin
if(reset) begin
ptr <= 0;
active <= START_ACTIVE;
o_avm_waitrequest[0] <= !START_ACTIVE;
for(i=1; i<NUM_PORT; i=i+1) o_avm_waitrequest[i] <= 1'b1;
o_token <= 1'b0;
end
else begin
o_token <= 1'b0;
if(i_token) active <= 1'b1;
if(pass_token) begin
if(ptr == NUM_PORT-1) begin if (!o_avm_waitrequest[NUM_PORT-1] | !active & !i_token) ptr <= '0;end
else if(active) ptr <= ptr + 1'b1;
if(ptr == NUM_PORT-1 & !o_avm_waitrequest[NUM_PORT-1]) begin
o_token <= active;
active <= !OPEN_RING;
end
end
for(i=0; i<NUM_PORT; i=i+1) begin
if(i==ptr) o_avm_waitrequest[i] <= !active & !i_token | backpressure[i] | ((ptr < NUM_PORT - 1)? !i_avm_request[i] : !i_avm_request[i] & !o_avm_waitrequest[i]);
else o_avm_waitrequest[i] <= 1'b1;
end
end
end
end
else begin : GEN_DISABLE_LAST_WAIT
always @(posedge clk or posedge reset) begin
if(reset) begin
ptr <= 0;
active <= START_ACTIVE;
o_avm_waitrequest[0] <= !START_ACTIVE;
for(i=1; i<NUM_PORT; i=i+1) o_avm_waitrequest[i] <= 1'b1;
o_token <= 1'b0;
end
else begin
o_token <= 1'b0;
if(i_token) active <= 1'b1;
if(pass_token) begin
if(ptr == NUM_PORT - 1) begin
o_token <= active | i_token;
active <= !OPEN_RING;
ptr <= '0;
end
else if(active) ptr <= ptr + 1'b1;
end
for(i=0; i<NUM_PORT; i=i+1) begin
if(i==ptr) o_avm_waitrequest[i] <= !active & !i_token | backpressure[i] | pass_token;
else o_avm_waitrequest[i] <= 1'b1;
end
end
end
end
for(z=0; z<NUM_PORT; z=z+1) begin : GEN_STALL
if(NUM_DIMM > 1 & !ENABLE_DATA_REORDER) begin : GEN_MULTIPLE_DIMM
for(z0=0; z0<NUM_DIMM; z0=z0+1) begin : GEN_
assign backpressure_stall[z][z0] = i_avm_waitrequest[z0] & i_avm_address[z][AWIDTH-1:AWIDTH-DIMM_W] == z0;
end
end
else begin : GEN_SINGLE_DIMM
for(z0=0; z0<NUM_DIMM; z0=z0+1) begin : GEN_
assign backpressure_stall[z][z0] = i_avm_waitrequest[z0];
end
end
assign backpressure[z] = |backpressure_stall[z];
assign i_avm_request[z] = i_avm_read[z] | i_avm_write[z];
end
if(READ) begin : ENABLE_READ
assign pass_token = !i_avm_request[ptr] | backpressure[ptr];
for(z=0; z<NUM_PORT; z=z+1) begin : GEN_I_DATA
assign i_id[z] = START_ID + z;
assign i_req[z] = {i_avm_address[z], i_avm_burstcount[z], i_id[z]};
assign {o_avm_address, o_avm_burstcount, o_id} = request_dout;
assign o_avm_byteenable = {MWIDTH_BYTES{1'b1}};
end
end
else begin : ENABLE_WRITE
assign pass_token = active & (!i_avm_request[ptr] | backpressure[ptr] & wr_burst_done);
for(z=0; z<NUM_PORT; z=z+1) begin : GEN_I_DATA
assign i_id[z] = START_ID + z;
assign i_req[z] = {i_avm_address[z], i_avm_burstcount[z], i_avm_writedata[z], i_avm_byteenable[z], i_id[z]};
assign {o_avm_address, o_avm_burstcount, o_avm_writedata, o_avm_byteenable, o_id} = request_dout;
end
always @(posedge clk or posedge reset) begin
if(reset) begin
wr_cnt <= 1;
wr_burst_done <= 1'b1;
end
else begin
if(avm_write_wire) begin
wr_cnt <= (wr_cnt == i_avm_burstcount[ptr])? 1 : wr_cnt + 1'b1;
if(!o_avm_waitrequest[ptr] & wr_cnt == i_avm_burstcount[ptr] & backpressure[ptr]) wr_burst_done <= 1'b1; // make sure that token is not passed to the next LSU until the burst write is fully processed for the current one
else wr_burst_done <= 1'b0;
end
else if(!backpressure[ptr] & i_token) begin
wr_burst_done <= 1'b0;
end
end
end // end always
end
reg [REQ_WIDTH-1:0] R_req;
assign request_dout = R_req;
assign o_avm_read = avm_read_p;
assign o_avm_write = avm_write_p;
assign o_avm_request = avm_request_p;
always @(posedge clk) begin
R_req <= i_req[ptr]; // N-to-1 MUX
end
endgenerate
endmodule
// the top MUX that selects requests between load and store
module lsu_ic_hybrid (
clk,
reset,
i_id,
i_avm_waitrequest,
i_avm_byteenable,
i_avm_address,
i_avm_read,
i_avm_write,
i_avm_burstcount,
i_avm_readdata,
i_avm_return_valid,
o_avm_waitrequest,
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_burstcount,
o_avm_readdata,
o_avm_readdatavalid,
o_id,
// write
i_avm_writedata,
o_avm_writedata
);
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter MWIDTH_BYTES=64; // Width of the global memory bus (bytes)
parameter BURST_CNT_W=6;
parameter ID_WIDTH = 1;
parameter FIFO_DEPTH = 64;
parameter FIFO_AF_THRESH = FIFO_DEPTH - 8;
parameter PIPELINE_RD_RETURN = 0;
parameter UNBALANCE = 0;
parameter DEVICE = "Stratix V";
localparam FIFO_AW = $clog2(FIFO_DEPTH);
localparam MWIDTH=8*MWIDTH_BYTES;
localparam REQUEST_FIFO_AW = 8;
localparam REQUEST_FIFO_DEPTH = 2**REQUEST_FIFO_AW;
localparam REQ_WIDTH_READ = AWIDTH + BURST_CNT_W;
localparam REQ_WIDTH_WRITE = AWIDTH + BURST_CNT_W + MWIDTH + MWIDTH_BYTES + ID_WIDTH;
localparam REQ_WIDTH_WIDER = (REQ_WIDTH_WRITE > REQ_WIDTH_READ)? REQ_WIDTH_WRITE : REQ_WIDTH_READ;
localparam REQ_WIDTH = REQ_WIDTH_WIDER;
input clk;
input reset;
input [ID_WIDTH-1:0] i_id [2];
input i_avm_waitrequest;
input [MWIDTH_BYTES-1:0] i_avm_byteenable [2];
input [AWIDTH-1:0] i_avm_address [2];
input i_avm_read [2];
input i_avm_write [2];
input [BURST_CNT_W-1:0] i_avm_burstcount [2];
input [MWIDTH-1:0] i_avm_readdata;
input i_avm_return_valid;
output o_avm_waitrequest [2];
output [MWIDTH_BYTES-1:0] o_avm_byteenable;
output [AWIDTH-1:0] o_avm_address;
output o_avm_read;
output o_avm_write;
output [BURST_CNT_W-1:0] o_avm_burstcount;
output [MWIDTH-1:0] o_avm_readdata;
output o_avm_readdatavalid [2];
input [MWIDTH-1:0] i_avm_writedata [2];
output [MWIDTH-1:0] o_avm_writedata;
output [ID_WIDTH-1:0] o_id;
generate
if(UNBALANCE) begin : GEN_UNBALANCE
lsu_ic_unbalance #(
.AWIDTH(AWIDTH),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W(BURST_CNT_W),
.ID_WIDTH(ID_WIDTH),
.FIFO_DEPTH(FIFO_DEPTH),
.FIFO_AF_THRESH(FIFO_AF_THRESH),
.PIPELINE_RD_RETURN(PIPELINE_RD_RETURN),
.DEVICE(DEVICE)
) lsu_ic_unbalance (
.clk (clk),
.reset (reset),
.i_id (i_id),
.i_avm_waitrequest (i_avm_waitrequest),
.i_avm_byteenable (i_avm_byteenable),
.i_avm_address (i_avm_address),
.i_avm_read (i_avm_read),
.i_avm_write (i_avm_write),
.i_avm_burstcount (i_avm_burstcount),
.i_avm_readdata (i_avm_readdata),
.i_avm_return_valid (i_avm_return_valid),
.o_avm_waitrequest (o_avm_waitrequest),
.o_avm_byteenable (o_avm_byteenable),
.o_avm_address (o_avm_address),
.o_avm_read (o_avm_read),
.o_avm_write (o_avm_write),
.o_avm_burstcount (o_avm_burstcount),
.o_avm_readdata (o_avm_readdata),
.o_avm_readdatavalid(o_avm_readdatavalid),
.i_avm_writedata (i_avm_writedata),
.o_avm_writedata (o_avm_writedata),
.o_id (o_id)
);
end
else begin : GEN_NORMAL
wire [REQ_WIDTH-1:0] i_req [2];
wire i_avm_request [2];
wire switch;
reg wr_port;
wire [BURST_CNT_W-1:0] wr_burstcount;
wire rd_en;
wire [AWIDTH-1:0] fin_avm_address ;
wire [BURST_CNT_W-1:0] fin_avm_burstcount ;
wire [MWIDTH-1:0] fin_avm_data ;
wire [MWIDTH_BYTES-1:0] fin_avm_byteenable ;
wire [ID_WIDTH-1:0] fin_id;
reg [REQ_WIDTH-1:0] fin ;
reg fin_valid;
wire valid_request;
reg o_avm_request;
reg avm_read, avm_write;
reg [0:1] avm_waitrequest;
reg [REQ_WIDTH-1:0] request_dout;
assign rd_en = !o_avm_request | i_avm_waitrequest === 1'b0; // "===" is used to avoid 'X' propagation in datapath when i_avm_waitrequest from other module is 'x'
assign switch = !i_avm_request[wr_port];
assign valid_request = fin_valid | i_avm_request[wr_port];
assign i_avm_request[0] = i_avm_read[0];
assign i_avm_request[1] = i_avm_write[1];
assign o_avm_waitrequest[0] = avm_waitrequest[0];
assign o_avm_waitrequest[1] = avm_waitrequest[1];
assign o_avm_read = avm_read;
assign o_avm_write = avm_write;
assign i_req[0] = {i_avm_address[0], i_avm_burstcount[0], i_avm_writedata[0], i_avm_byteenable[0], i_id[0]};
assign i_req[1] = {i_avm_address[1], i_avm_burstcount[1], i_avm_writedata[1], i_avm_byteenable[1], i_id[1]};
assign {fin_avm_address, fin_avm_burstcount, fin_avm_data, fin_avm_byteenable, fin_id} = fin;
assign {o_avm_address, o_avm_burstcount, o_avm_writedata, o_avm_byteenable, o_id} = request_dout;
always @(posedge clk) begin
if(i_avm_request[wr_port] & !avm_waitrequest[wr_port]) fin <= i_req[wr_port];
if(rd_en & valid_request) request_dout <= fin_valid? fin : i_req[wr_port];
end
always @(posedge clk or posedge reset) begin
if(reset) begin
wr_port <= 1'b0;
avm_read <= 1'b0;
avm_write <= 1'b0;
fin_valid <= 1'b0;
o_avm_request <= 1'b0;
avm_waitrequest <= 2'b0;
end
else begin
if(!rd_en & i_avm_request[wr_port] & !avm_waitrequest[wr_port]) fin_valid <= 1'b1;
else if(rd_en) fin_valid <= 1'b0;
if(rd_en) begin
avm_read <= valid_request & !wr_port;
avm_write <= valid_request & wr_port;
o_avm_request <= valid_request;
end
if(!rd_en & valid_request) avm_waitrequest[wr_port] <= 1'b1;
else if(!switch) avm_waitrequest[wr_port] <= 1'b0;
else begin
wr_port <= !wr_port;
avm_waitrequest[wr_port] <= 1'b1;
avm_waitrequest[!wr_port] <= 1'b0;
end
end
end
end
endgenerate
endmodule
module lsu_ic_unbalance (
clk,
reset,
i_id,
i_avm_waitrequest,
i_avm_byteenable,
i_avm_address,
i_avm_read,
i_avm_write,
i_avm_burstcount,
i_avm_readdata,
i_avm_return_valid,
o_avm_waitrequest,
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_burstcount,
o_avm_readdata,
o_avm_readdatavalid,
o_id,
// write
i_avm_writedata,
o_avm_writedata
);
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter MWIDTH_BYTES=64; // Width of the global memory bus (bytes)
parameter BURST_CNT_W=6;
parameter ID_WIDTH = 1;
parameter FIFO_DEPTH = 64;
parameter FIFO_AF_THRESH = FIFO_DEPTH - 8;
parameter PIPELINE_RD_RETURN = 0;
parameter DEVICE = "Stratix V";
localparam FIFO_AW = $clog2(FIFO_DEPTH);
localparam MWIDTH=8*MWIDTH_BYTES;
localparam REQUEST_FIFO_AW = 8;
localparam REQUEST_FIFO_DEPTH = 2**REQUEST_FIFO_AW;
localparam REQ_WIDTH_READ = AWIDTH + BURST_CNT_W;
localparam REQ_WIDTH_WRITE = AWIDTH + BURST_CNT_W + MWIDTH + MWIDTH_BYTES + ID_WIDTH;
localparam REQ_WIDTH_WIDER = (REQ_WIDTH_WRITE > REQ_WIDTH_READ)? REQ_WIDTH_WRITE : REQ_WIDTH_READ;
localparam REQ_WIDTH = REQ_WIDTH_WIDER + 1;
input clk;
input reset;
input [ID_WIDTH-1:0] i_id [2];
input i_avm_waitrequest;
input [MWIDTH_BYTES-1:0] i_avm_byteenable [2];
input [AWIDTH-1:0] i_avm_address [2];
input i_avm_read [2];
input i_avm_write [2];
input [BURST_CNT_W-1:0] i_avm_burstcount [2];
input [MWIDTH-1:0] i_avm_readdata;
input i_avm_return_valid;
output o_avm_waitrequest [2];
output [MWIDTH_BYTES-1:0] o_avm_byteenable;
output [AWIDTH-1:0] o_avm_address;
output reg o_avm_read;
output reg o_avm_write;
output [BURST_CNT_W-1:0] o_avm_burstcount;
output reg [MWIDTH-1:0] o_avm_readdata;
output reg o_avm_readdatavalid [2];
input [MWIDTH-1:0] i_avm_writedata [2];
output [MWIDTH-1:0] o_avm_writedata;
output [ID_WIDTH-1:0] o_id;
wire [REQ_WIDTH-1:0] i_req [2];
wire i_avm_request [2];
reg R_i_waitrequest, port_to_fifo;
reg [BURST_CNT_W-1:0] wr_cnt;
reg wr_finish;
reg wr_port;
reg [BURST_CNT_W-1:0] cnt;
wire rd_enable;
wire fifo_stall;
reg R_rd_fifo, port_valid;
wire rd_fifo;
wire port;
wire [BURST_CNT_W-1:0] burst_cnt;
wire fifo_empty, fifo_af;
wire o_avm_read_en;
reg [REQ_WIDTH-1:0] request_dout;
assign i_avm_request[0] = i_avm_read[0] | i_avm_write[0];
assign i_avm_request[1] = i_avm_read[1] | i_avm_write[1];
assign fifo_stall = !i_avm_return_valid;
assign rd_enable = cnt == burst_cnt & !(R_rd_fifo & burst_cnt > 1);
assign i_req[0] = {i_avm_address[0], i_avm_burstcount[0], i_avm_writedata[0], i_avm_byteenable[0], i_id[0], i_avm_read[0]} ;
assign i_req[1] = {i_avm_address[1], i_avm_burstcount[1], i_avm_writedata[1], i_avm_byteenable[1], i_id[1], i_avm_read[1]} ;
assign {o_avm_address, o_avm_burstcount, o_avm_writedata, o_avm_byteenable, o_id} = request_dout[REQ_WIDTH-1:1];
assign o_avm_waitrequest[0] = wr_port | i_avm_request[1] | R_i_waitrequest;
assign o_avm_waitrequest[1] = R_i_waitrequest; // port [1] has priority
always @(posedge clk) begin
o_avm_readdata <= i_avm_readdata;
request_dout <= i_avm_request[1]? i_req[1] : i_req[0];
port_to_fifo <= i_avm_request[1];
end
always @(posedge clk or posedge reset) begin
if(reset) begin
wr_port <= 1'b1;
wr_cnt <= 1;
wr_finish <= 1'b1;
R_i_waitrequest <= 1'b0;
o_avm_read <= 1'b0;
o_avm_write <= 1'b0;
end
else begin
R_i_waitrequest <= i_avm_waitrequest | fifo_af;
if(i_avm_request[1]) begin
if(i_avm_write[1]) begin
wr_cnt <= (wr_cnt == i_avm_burstcount[1])? 1 : wr_cnt + 1'b1;
wr_finish <= wr_cnt == i_avm_burstcount[1];
end
wr_port <= 1'b1;
end
else if(wr_finish & i_avm_request[0]) begin
wr_port <= 1'b0;
end
o_avm_read <= i_avm_read[1] | i_avm_read[0] & !o_avm_waitrequest[0];
o_avm_write <= i_avm_write[1] | i_avm_write[0] & !o_avm_waitrequest[0];
end
end
// read back
always @(posedge clk or posedge reset) begin
if(reset) begin
cnt <= 0;
R_rd_fifo <= 1'b0;
port_valid <= 1'b0;
o_avm_readdatavalid[0] <= 1'b0;
o_avm_readdatavalid[1] <= 1'b0;
end
else begin
R_rd_fifo <= rd_fifo & !fifo_empty;
if(rd_fifo & !fifo_empty) port_valid <= 1'b1;
else if(cnt == burst_cnt & i_avm_return_valid & fifo_empty) port_valid <= 1'b0;
if(rd_fifo & !fifo_empty) begin cnt <= 1; end
else if(i_avm_return_valid & cnt < burst_cnt) cnt <= cnt + 1;
o_avm_readdatavalid[0] <= i_avm_return_valid === 1'b1 & !port;
o_avm_readdatavalid[1] <= i_avm_return_valid === 1'b1 & port;
end
end
generate
if(PIPELINE_RD_RETURN) begin : GEN_PIPELINE_RETURN
assign rd_fifo = i_avm_return_valid & cnt == burst_cnt | !port_valid;
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (FIFO_DEPTH),
.lpm_widthu (FIFO_AW),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (1+BURST_CNT_W),
.almost_full_value(FIFO_AF_THRESH),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON")
) burst_cnt_fifo (
.clock (clk),
.data ({port_to_fifo, o_avm_burstcount}),
.wrreq (o_avm_read),
.rdreq (rd_fifo),
.empty (fifo_empty),
.q ({port, burst_cnt}),
.almost_full (fifo_af),
.aclr (reset)
);
end
else begin : GEN_DISABLE_PIPELINE_RD_RETURN
assign fifo_af = 1'b0;
end
endgenerate
endmodule
// This module is a token ring that includes the following major sub-blocks
// [1] read ring / write ring, connected to LSUs
// [2] one root FIFO per bank; root FIFO buffers memory access requests and generate backpressure
// [3] data reordering block - optional
module lsu_token_ring (
clk,
reset,
// from LSU
i_rd_byteenable,
i_rd_address,
i_rd_request,
i_rd_burstcount,
i_wr_byteenable,
i_wr_address,
i_wr_request,
i_wr_burstcount,
i_wr_writedata,
// from MEM
i_avm_waitrequest,
i_avm_readdata,
i_avm_return_valid,
// to MEM
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_burstcount,
o_avm_writedata,
o_id,
// to kernel
o_rd_waitrequest,
o_wr_waitrequest,
o_avm_writeack,
o_avm_readdata,
o_avm_readdatavalid
);
parameter AWIDTH = 32;
parameter MWIDTH_BYTES = 64;
parameter BURST_CNT_W = 5;
parameter NUM_RD_PORT = 2;
parameter NUM_WR_PORT = 2;
parameter START_ID = 0;
parameter ENABLE_READ_FAST = 0;
parameter DEVICE = "Stratix V";
parameter DISABLE_ROOT_FIFO = 0;
parameter ROOT_FIFO_AW = 8; // Token root FIFO address width; FIFO depth = 2**ROOT_FIFO_AW
parameter RD_ROOT_FIFO_AW = 7;
parameter ENABLE_LAST_WAIT = 0;
parameter MAX_MEM_DELAY = 128;
parameter RETURN_DATA_FIFO_DEPTH = 128; // Read data reordering FIFO depth
parameter PIPELINE_RD_RETURN = 0;
parameter ENABLE_DATA_REORDER = 0;
parameter NUM_DIMM = 2;
parameter ENABLE_DUAL_RING = 0;
parameter ENABLE_MULTIPLE_WR_RING = 0;
parameter NUM_REORDER = 1;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam NUM_ID = NUM_RD_PORT+NUM_WR_PORT;
localparam DISABLE_WR_RING = NUM_WR_PORT==0;
localparam ENABLE_MULTIPLE_WR_RING_INT = ENABLE_MULTIPLE_WR_RING & ENABLE_DUAL_RING & !DISABLE_WR_RING & NUM_DIMM > 1;
localparam WR_ENABLE = NUM_WR_PORT > 0;
localparam RD_ID_WIDTH = (NUM_RD_PORT==1)? 1 : $clog2(NUM_RD_PORT);
localparam WR_ID_WIDTH = (NUM_WR_PORT==1)? 1 : $clog2(NUM_WR_PORT);
localparam ID_WIDTH = (RD_ID_WIDTH > WR_ID_WIDTH)? RD_ID_WIDTH : WR_ID_WIDTH;
localparam WR_RING_ID_WIDTH = ENABLE_DUAL_RING? WR_ID_WIDTH : ID_WIDTH;
localparam DIMM_W = $clog2(NUM_DIMM);
localparam MAX_BURST = 2 ** (BURST_CNT_W-1);
localparam WR_WIDTH = AWIDTH - DIMM_W + BURST_CNT_W + MWIDTH + MWIDTH_BYTES;
localparam ROOT_FIFO_DEPTH = 2 ** ROOT_FIFO_AW;
localparam RD_ROOT_FIFO_DEPTH = 2 ** RD_ROOT_FIFO_AW;
localparam NUM_REORDER_INT = (NUM_REORDER > NUM_RD_PORT)? NUM_RD_PORT : NUM_REORDER;
localparam PENDING_CNT_W = $clog2(RETURN_DATA_FIFO_DEPTH);
localparam RD_WIDTH = (NUM_REORDER == 1)? 1 :$clog2(NUM_RD_PORT%NUM_REORDER + NUM_RD_PORT/NUM_REORDER +1);
// avoid modelsim compile error
localparam P_NUM_RD_PORT = (NUM_RD_PORT > 0)? NUM_RD_PORT : 1;
localparam P_NUM_WR_PORT = (NUM_WR_PORT > 0)? NUM_WR_PORT : 1;
input clk;
input reset;
// from LSU
input [MWIDTH_BYTES-1:0] i_rd_byteenable [P_NUM_RD_PORT];
input [AWIDTH-1:0] i_rd_address [P_NUM_RD_PORT];
input i_rd_request [P_NUM_RD_PORT];
input [BURST_CNT_W-1:0] i_rd_burstcount [P_NUM_RD_PORT];
input [MWIDTH_BYTES-1:0] i_wr_byteenable [P_NUM_WR_PORT];
input [AWIDTH-1:0] i_wr_address [P_NUM_WR_PORT];
input i_wr_request [P_NUM_WR_PORT];
input [BURST_CNT_W-1:0] i_wr_burstcount [P_NUM_WR_PORT];
input [MWIDTH-1:0] i_wr_writedata [P_NUM_WR_PORT];
// from MEM
input i_avm_waitrequest [NUM_DIMM];
input [MWIDTH-1:0] i_avm_readdata [NUM_DIMM];
input i_avm_return_valid [NUM_DIMM];
// to MEM
output [MWIDTH_BYTES-1:0] o_avm_byteenable [NUM_DIMM];
output [AWIDTH-DIMM_W-1:0] o_avm_address [NUM_DIMM];
output o_avm_read [NUM_DIMM];
output o_avm_write [NUM_DIMM];
output [BURST_CNT_W-1:0] o_avm_burstcount [NUM_DIMM];
output [MWIDTH-1:0] o_avm_writedata [NUM_DIMM];
output [ID_WIDTH-1:0] o_id [NUM_DIMM];
// to kernel
output o_rd_waitrequest [P_NUM_RD_PORT];
output o_wr_waitrequest [P_NUM_WR_PORT];
output reg o_avm_writeack [P_NUM_WR_PORT];
output [MWIDTH-1:0] o_avm_readdata [P_NUM_RD_PORT];
output o_avm_readdatavalid [P_NUM_RD_PORT];
integer i, j;
wire rd_o_token;
wire [RD_ID_WIDTH-1:0] rd_o_id;
wire [AWIDTH-1:0] rd_address;
wire rd_request;
wire rd_waitrequest [NUM_DIMM];
wire rd_root_af [NUM_DIMM];
wire [BURST_CNT_W-1:0] rd_burstcount;
wire ic_read [P_NUM_WR_PORT];
wire ic_write [P_NUM_RD_PORT];
wire [MWIDTH_BYTES-1:0] wr_byteenable;
wire [AWIDTH-1:0] wr_address;
wire wr_read;
wire wr_write;
wire wr_request;
wire [BURST_CNT_W-1:0] wr_burstcount;
wire [WR_ID_WIDTH-1:0] wr_id;
wire [MWIDTH-1:0] wr_writedata;
wire [WR_WIDTH-1:0] wr_fin [NUM_DIMM];
wire [WR_WIDTH-1:0] wr_fout [NUM_DIMM];
wire wr_fifo_empty [NUM_DIMM];
wire wr_root_af [NUM_DIMM];
wire wr_wr_root_en [NUM_DIMM];
wire rd_wr_root_en [NUM_DIMM];
reg wr_out_en [NUM_DIMM];
wire rd_fifo_empty [NUM_DIMM];
wire wr_rd_root_en [NUM_DIMM];
wire rd_rd_root_en [NUM_DIMM];
reg rd_out_en [NUM_DIMM];
wire [RD_ID_WIDTH-1:0] fout_id[NUM_DIMM];
wire wr_dimm_en [NUM_DIMM];
wire [AWIDTH-DIMM_W-1:0] top_rd_address [NUM_DIMM];
wire [BURST_CNT_W-1:0] top_rd_burstcount [NUM_DIMM];
wire [RD_ID_WIDTH-1:0] fout_rd_id [NUM_DIMM];
wire [0:NUM_DIMM-1] id_af;
wire [RD_WIDTH-1:0]rd_bank[NUM_DIMM];
logic [0:NUM_DIMM-1] data_af;
wire [MWIDTH-1:0] rd_data [NUM_DIMM][P_NUM_RD_PORT];
reg [MWIDTH-1:0] R_avm_readdata [P_NUM_RD_PORT];
reg R_avm_readdatavalid [P_NUM_RD_PORT];
wire rd_data_valid [NUM_DIMM][P_NUM_RD_PORT];
wire [0:NUM_DIMM-1] v_rd_data_en [P_NUM_RD_PORT];
wire [AWIDTH-DIMM_W-1:0] wr_ring_o_addr [NUM_DIMM];
wire [BURST_CNT_W-1:0] wr_ring_o_burstcount [NUM_DIMM];
wire [MWIDTH-1:0] wr_ring_o_writedata [NUM_DIMM];
wire [MWIDTH_BYTES-1:0] wr_ring_o_byteenable [NUM_DIMM];
reg [PENDING_CNT_W-1:0] max_pending [NUM_DIMM];
reg [BURST_CNT_W-1:0] wr_cnt [NUM_DIMM];
logic [0:NUM_DIMM-1] wr_done, wr_en, error_0, error_1;
logic [0:NUM_DIMM-1] debug_bubble;
assign wr_request = wr_read | wr_write;
genvar z, z0;
generate
if(NUM_ID == 1) begin : GEN_SINGLE_PORT
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_
assign o_avm_byteenable[z] = (NUM_RD_PORT == 1)? '1 : i_wr_byteenable[0];
assign o_avm_address[z] = (NUM_RD_PORT == 1)? i_rd_address[0][AWIDTH-DIMM_W-1:0] : i_wr_address[0][AWIDTH-DIMM_W-1:0];
assign o_avm_burstcount[z] = (NUM_RD_PORT == 1)? i_rd_burstcount[0] : i_wr_burstcount[0];
assign o_avm_writedata[z] = i_wr_writedata[0];
assign o_id[z] = START_ID;
end
assign o_avm_read[0] = (NUM_RD_PORT == 1)? i_rd_request[0] & !i_rd_address[0][AWIDTH-1] : 1'b0;
assign o_avm_write[0] = (NUM_RD_PORT == 1)? 1'b0 : i_wr_request[0] & !i_wr_address[0][AWIDTH-1];
assign o_avm_read[1] = (NUM_RD_PORT == 1)? i_rd_request[0] & i_rd_address[0][AWIDTH-1] : 1'b0;
assign o_avm_write[1] = (NUM_RD_PORT == 1)? 1'b0 : i_wr_request[0] & i_wr_address[0][AWIDTH-1];
assign o_rd_waitrequest[0] = i_avm_waitrequest[0] & !i_rd_address[0][AWIDTH-1] | i_avm_waitrequest[1] & i_rd_address[0][AWIDTH-1];
assign o_wr_waitrequest[0] = i_avm_waitrequest[0] & !i_wr_address[0][AWIDTH-1] | i_avm_waitrequest[1] & i_wr_address[0][AWIDTH-1];
assign rd_burstcount = i_rd_burstcount[0];
assign rd_o_id = 1'b0;
assign rd_request = (o_avm_read[0] | o_avm_read[1]) & !o_rd_waitrequest[0];
assign rd_address = i_rd_address[0];
end
else begin : GEN_MULTIPLE_PORT
for(z=0; z<NUM_WR_PORT; z=z+1) begin : GEN_WR_DUMMY
assign ic_read[z] = 1'b0;
end
for(z=0; z<NUM_RD_PORT; z=z+1) begin : GEN_RD_DUMMY
assign ic_write[z] = 1'b0;
end
if(NUM_RD_PORT > 0) begin : GEN_ENABLE_RD
lsu_n_token #(
.AWIDTH(AWIDTH),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W(BURST_CNT_W),
.NUM_PORT(NUM_RD_PORT),
.START_ID(START_ID),
.OPEN_RING(!DISABLE_WR_RING & !ENABLE_DUAL_RING),
.SINGLE_STALL((DISABLE_WR_RING | ENABLE_DUAL_RING) & ENABLE_DATA_REORDER), // wr_root_af is from the single ID FIFO; sw-dimm-partion has N ID FIFOs
.ENABLE_DATA_REORDER(ENABLE_DATA_REORDER),
.START_ACTIVE(1),
.ENABLE_FAST(ENABLE_READ_FAST),
.NUM_DIMM(NUM_DIMM),
.ENABLE_LAST_WAIT(ENABLE_LAST_WAIT),
.READ(1)
) rd_ring (
.clk (clk),
.reset (reset),
.i_ext_read (1'b0),
.i_avm_write (ic_write),
.i_token (),
.i_avm_address (i_rd_address),
.i_avm_read (i_rd_request),
.i_avm_burstcount (i_rd_burstcount),
.i_avm_waitrequest(rd_waitrequest),
.o_avm_waitrequest(o_rd_waitrequest),
.o_avm_address (rd_address),
.o_avm_read (rd_request),
.o_avm_burstcount (rd_burstcount),
.o_token (rd_o_token),
.o_id (rd_o_id)
);
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_RD_SET
assign rd_rd_root_en[z] = !rd_out_en[z] | !i_avm_waitrequest[z] & !wr_en[z];
assign o_avm_read[z] = rd_out_en[z] & !wr_en[z];
if(NUM_DIMM > 1) assign wr_rd_root_en[z] = rd_request & rd_address[AWIDTH-1:AWIDTH-DIMM_W] == z;
else assign wr_rd_root_en[z] = rd_request;
always @(posedge clk or posedge reset) begin
if(reset) rd_out_en[z] <= 1'b0;
else if(rd_rd_root_en[z]) rd_out_en[z] <= !rd_fifo_empty[z] & !data_af[z];
end
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family (DEVICE),
.lpm_numwords (RD_ROOT_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (AWIDTH-DIMM_W+BURST_CNT_W),
.lpm_widthu (RD_ROOT_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON"),
.almost_full_value(RD_ROOT_FIFO_DEPTH-5-NUM_RD_PORT*2)
) rd_fifo (
.clock (clk),
.data ({rd_address[AWIDTH-DIMM_W-1:0],rd_burstcount}),
.wrreq (wr_rd_root_en[z]),
.rdreq (rd_rd_root_en[z] & !data_af[z]),
.empty (rd_fifo_empty[z]),
.q ({top_rd_address[z],top_rd_burstcount[z]}),
.almost_full (rd_root_af[z]),
.aclr (reset)
);
// wr_root_af to ring pipelined nodes
assign rd_waitrequest[z] = id_af[z];
end
end //end if(NUM_RD_PORT > 0) begin : GEN_ENABLE_RD
else begin : GEN_DISABLE_RD
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_DI
assign o_avm_read[z] = 1'b0;
end
end // end GEN_DISABLE_RD
if(!DISABLE_WR_RING) begin : GEN_ENABLE_WRITE_RING
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_WR_ROOT_FIFOS
assign o_avm_writedata[z] = wr_fout[z][MWIDTH-1:0];
assign {o_avm_byteenable[z], o_avm_address[z], o_avm_burstcount[z]} = o_avm_write[z]? wr_fout[z][WR_WIDTH-1:MWIDTH] : {{MWIDTH_BYTES{1'b1}},top_rd_address[z], top_rd_burstcount[z]};
assign o_avm_write[z] = wr_out_en[z] & wr_en[z];
assign rd_wr_root_en[z] = !wr_out_en[z] | !i_avm_waitrequest[z] & wr_en[z];
assign wr_done[z] = o_avm_write[z] & !i_avm_waitrequest[z] & wr_cnt[z] == wr_fout[z][MWIDTH+BURST_CNT_W-1:MWIDTH];
`ifdef SIM_ONLY // check bubble or error
reg [AWIDTH-DIMM_W-1:0] R_addr;
reg not_wr_empty, not_rd_empty;
reg freeze_read, freeze_write;
assign debug_bubble[z] = !i_avm_waitrequest[z] & (!o_avm_write[z] & not_wr_empty) & (!o_avm_read[z] & not_rd_empty); // check if there is switch bubble
always @(posedge clk) begin
if(o_avm_write[z]) R_addr <= o_avm_address[z];
not_wr_empty <= !wr_fifo_empty[z];
not_rd_empty <= !rd_fifo_empty[z];
freeze_read <= i_avm_waitrequest[z] & o_avm_read[z];
freeze_write <= i_avm_waitrequest[z] & o_avm_write[z];
error_0[z] <= R_addr !== o_avm_address[z] & wr_cnt[z] < wr_fout[z][MWIDTH+BURST_CNT_W-1:MWIDTH] & wr_cnt[z] != 1 & (o_avm_read[z] | o_avm_write[z]) ; // switch to rd when wr has not finished
error_1[z] <= freeze_read & !o_avm_read[z] | freeze_write & !o_avm_write[z] | o_avm_read[z] & o_avm_write[z]; // output request changes during i_avm_waitrequest
end
`endif
always @(posedge clk or posedge reset) begin
if(reset) begin
wr_out_en[z] <= 1'b0;
wr_cnt[z] <= 1;
wr_en[z] <= 1'b0;
end
else begin
if(rd_wr_root_en[z]) wr_out_en[z] <= !wr_fifo_empty[z];
if(o_avm_write[z] & !i_avm_waitrequest[z]) wr_cnt[z] <= (wr_cnt[z] == wr_fout[z][MWIDTH+BURST_CNT_W-1:MWIDTH])? 1 : wr_cnt[z] + 1'b1;
if(wr_done[z]) wr_en[z] <= !wr_fifo_empty[z];
else if((!wr_fifo_empty[z] | wr_out_en[z]) & !(i_avm_waitrequest[z] & o_avm_read[z])) wr_en[z] <= 1'b1;
end
end
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family (DEVICE),
.lpm_numwords (ROOT_FIFO_DEPTH),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (WR_WIDTH),
.lpm_widthu (ROOT_FIFO_AW),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON"),
.almost_full_value(ROOT_FIFO_DEPTH-5-NUM_WR_PORT*2)
) wr_fifo (
.clock (clk),
.data (wr_fin[z]),
.wrreq (wr_wr_root_en[z]),
.rdreq (rd_wr_root_en[z]),
.empty (wr_fifo_empty[z]),
.q (wr_fout[z]),
.almost_full (wr_root_af[z]),
.aclr (reset)
);
end // end GEN_WR_ROOT_FIFOS z-loop
if(ENABLE_MULTIPLE_WR_RING_INT) begin : GEN_MULTIPLE_WR_RING
wire [AWIDTH-DIMM_W-1:0] wr_ring_i_addr [NUM_WR_PORT];
wire wr_ring_i_write [NUM_DIMM] [NUM_WR_PORT];
wire wr_ring_o_waitrequest [NUM_DIMM][NUM_WR_PORT];
wire [0:NUM_DIMM-1] v_wr_stall [NUM_WR_PORT];
wire [0:NUM_DIMM-1] wr_accept [NUM_WR_PORT];
wire [WR_RING_ID_WIDTH-1:0] wr_o_id [NUM_DIMM];
for(z0=0; z0<NUM_WR_PORT; z0=z0+1) begin : GEN_WR_STALL
assign o_wr_waitrequest[z0] = |v_wr_stall[z0];
assign wr_ring_i_addr[z0] = i_wr_address[z0][AWIDTH-DIMM_W-1:0];
end
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_
wire wr_i_waitrequest [1];
assign wr_i_waitrequest[0] = wr_root_af[z];
for(z0=0; z0<NUM_WR_PORT; z0=z0+1) begin : GEN_WR_ENABLE
assign wr_ring_i_write[z][z0] = i_wr_request[z0] & i_wr_address[z0][AWIDTH-1:AWIDTH-DIMM_W] == z;
assign v_wr_stall[z0][z] = wr_ring_o_waitrequest[z][z0] & i_wr_address[z0][AWIDTH-1:AWIDTH-DIMM_W] == z;
assign wr_accept[z0][z] = wr_dimm_en[z] & wr_o_id[z] == z0;
end
lsu_n_token #(
.AWIDTH(AWIDTH - DIMM_W),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W(BURST_CNT_W),
.NUM_PORT(NUM_WR_PORT),
.ID_WIDTH(WR_RING_ID_WIDTH),
.ENABLE_DATA_REORDER(ENABLE_DATA_REORDER),
.OPEN_RING(0),
.START_ACTIVE(1),
.NUM_DIMM(1),
.ENABLE_LAST_WAIT(0),
.START_ID(0),
.READ(0)
) wr_ring (
.clk (clk),
.reset (reset),
.i_token (1'b0),
.i_id (),
.i_ext_address (),
.i_ext_read (1'b0),
.i_ext_burstcount (),
.o_ext_waitrequest(),
.i_avm_byteenable (i_wr_byteenable),
.i_avm_address (wr_ring_i_addr),
.i_avm_read (ic_read),
.i_avm_write (wr_ring_i_write[z]),
.i_avm_writedata (i_wr_writedata),
.i_avm_burstcount (i_wr_burstcount),
.i_avm_waitrequest(wr_i_waitrequest),
.o_avm_waitrequest(wr_ring_o_waitrequest[z]),
.o_avm_byteenable (wr_ring_o_byteenable[z]),
.o_avm_address (wr_ring_o_addr[z]),
.o_avm_read (),
.o_avm_write (wr_dimm_en[z]),
.o_avm_burstcount (wr_ring_o_burstcount[z]),
.o_id (wr_o_id[z]),
.o_token (),
.o_avm_writedata (wr_ring_o_writedata[z])
);
assign wr_fin[z] = {
//wr_o_id[z],
wr_ring_o_byteenable[z],
wr_ring_o_addr[z],
wr_ring_o_burstcount[z],
wr_ring_o_writedata[z]
};
assign wr_wr_root_en[z] = wr_dimm_en[z];
end
// ------------------
// Generate write ACK
// ------------------
always @(posedge clk or posedge reset) begin
if(reset) begin
for(i=0; i<NUM_WR_PORT; i=i+1) o_avm_writeack[i] <= 1'b0;
end
else begin
for(i=0; i<NUM_WR_PORT; i=i+1) o_avm_writeack[i] <= |wr_accept[i];
end
end // end always
end
else begin : GEN_SINGLE_WR_RING
lsu_n_token #(
.AWIDTH(AWIDTH),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W(BURST_CNT_W),
.NUM_PORT(NUM_WR_PORT),
.ID_WIDTH(WR_RING_ID_WIDTH),
.ENABLE_DATA_REORDER(ENABLE_DATA_REORDER),
.OPEN_RING(NUM_RD_PORT > 0 & !ENABLE_DUAL_RING),
.START_ACTIVE(NUM_RD_PORT == 0 | ENABLE_DUAL_RING),
.NUM_DIMM(NUM_DIMM),
.ENABLE_LAST_WAIT(0),
.START_ID(0),
.READ(0)
) wr_ring (
.clk (clk),
.reset (reset),
.i_token (1'b0),
.i_id (),
.i_ext_address (),
.i_ext_read (1'b0),
.i_ext_burstcount (rd_burstcount),
.o_ext_waitrequest(),
.i_avm_byteenable (i_wr_byteenable),
.i_avm_address (i_wr_address),
.i_avm_read (ic_read),
.i_avm_write (i_wr_request),
.i_avm_writedata (i_wr_writedata),
.i_avm_burstcount (i_wr_burstcount),
.i_avm_waitrequest(wr_root_af),
.o_avm_waitrequest(o_wr_waitrequest),
.o_avm_byteenable (wr_byteenable),
.o_avm_address (wr_address),
.o_avm_read (wr_read),
.o_avm_write (wr_write),
.o_avm_burstcount (wr_burstcount),
.o_id (wr_id),
.o_token (),
.o_avm_writedata (wr_writedata)
);
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_
assign wr_fin[z] = {
//wr_id,
wr_byteenable,
wr_address[AWIDTH-DIMM_W-1:0],
wr_burstcount,
wr_writedata
};
if(NUM_DIMM > 1) assign wr_wr_root_en[z] = wr_request & wr_address[AWIDTH-1:AWIDTH-DIMM_W] == z;
else assign wr_wr_root_en[z] = wr_request;
end
// ------------------
// Generate write ACK
// ------------------
always @(posedge clk or posedge reset) begin
if(reset) begin
for(i=0; i<NUM_WR_PORT; i=i+1) o_avm_writeack[i] <= 1'b0;
end
else begin
for(i=0; i<NUM_WR_PORT; i=i+1) o_avm_writeack[i] <= wr_write & wr_id == i;
end
end // end GEN_SINGLE_WR_RING
end
end // end GEN_ENABLE_WRITE_RING
else begin
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_
assign o_avm_write[z] = 1'b0;
assign wr_en[z] = 1'b0;
assign {o_avm_byteenable[z], o_avm_address[z], o_avm_burstcount[z]} = {{MWIDTH_BYTES{1'b1}},top_rd_address[z], top_rd_burstcount[z]};
end
end
end // end MULTIPLE PORTS
wire [DIMM_W:0] to_avm_port_num;
if(NUM_DIMM > 1) assign to_avm_port_num = rd_address[AWIDTH-1:AWIDTH-DIMM_W];
else assign to_avm_port_num = 1'b0;
if(ENABLE_DATA_REORDER & NUM_RD_PORT > 0) begin : GEN_DATA_REORDER
lsu_rd_back_n #(
.NUM_DIMM (NUM_DIMM),
.NUM_RD_PORT (NUM_RD_PORT),
.NUM_REORDER(NUM_REORDER_INT),
.BURST_CNT_W (BURST_CNT_W),
.MWIDTH (MWIDTH),
.DATA_FIFO_DEPTH(RETURN_DATA_FIFO_DEPTH),
.MAX_MEM_DELAY (MAX_MEM_DELAY),
.PIPELINE (PIPELINE_RD_RETURN),
.DEVICE (DEVICE)
) lsu_rd_back (
.clk (clk),
.reset (reset),
.i_to_avm_port_num (to_avm_port_num),
.i_to_avm_burstcount(rd_burstcount),
.i_to_avm_id (rd_o_id),
.i_to_avm_valid (rd_request),
.i_data (i_avm_readdata),
.i_data_valid (i_avm_return_valid),
.o_data (o_avm_readdata),
.o_data_valid (o_avm_readdatavalid),
.o_rd_bank (rd_bank),
.o_id_af (id_af[0])
);
if(NUM_DIMM > 1) assign id_af[1:NUM_DIMM-1] = '0;
reg [PENDING_CNT_W-1:0] pending_rd [NUM_DIMM];
reg [0:NUM_DIMM-1] R_o_avm_read;
reg [BURST_CNT_W-1:0] R_o_avm_burstcnt [NUM_DIMM];
always @(posedge clk) begin
for(i=0; i<NUM_DIMM; i=i+1) R_o_avm_burstcnt[i] <= o_avm_burstcount[i];
end
always @(posedge clk or posedge reset) begin
if(reset) begin
for(i=0; i<NUM_DIMM; i=i+1) begin
pending_rd[i] <= '0;
max_pending[i] <= '0;
data_af[i] <= 1'b0;
R_o_avm_read[i] <= 1'b0;
end
end
else begin
for(i=0; i<NUM_DIMM; i=i+1) begin
R_o_avm_read[i] <= o_avm_read[i] & !i_avm_waitrequest[i];
pending_rd[i] <= pending_rd[i] + (R_o_avm_burstcnt[i] & {BURST_CNT_W{R_o_avm_read[i]}}) - rd_bank[i];
data_af[i] <= pending_rd[i] >= (RETURN_DATA_FIFO_DEPTH - MAX_BURST * 5);
`ifdef SIM_ONLY
if(max_pending[i] < pending_rd[i]) max_pending[i] <= pending_rd[i];
`endif
end
end
end
end
else if(NUM_RD_PORT > 0) begin : GEN_DISABLE_DATA_REORDER
for(z=0; z<NUM_RD_PORT; z=z+1) begin : GEN_RD_DOUT
assign o_avm_readdata[z] = R_avm_readdata[z];
assign o_avm_readdatavalid[z] = R_avm_readdatavalid[z];
end
always @(posedge clk) begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
for(j=0; j<NUM_DIMM; j=j+1) if(rd_data_valid[j][i]) R_avm_readdata[i] <= rd_data[j][0];
R_avm_readdatavalid[i] <= |v_rd_data_en[i];
end
end
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_DATA_VALID
wire to_avm_valid;
wire [MWIDTH-1:0] i_data [1];
wire i_data_valid [1];
assign data_af[z] = 1'b0;
for(z0=0; z0<NUM_RD_PORT; z0=z0+1) begin : GEN_
assign v_rd_data_en[z0][z] = rd_data_valid[z][z0];
end
assign i_data[0] = i_avm_readdata[z];
assign i_data_valid[0] = i_avm_return_valid[z];
if(NUM_DIMM > 1) assign to_avm_valid = rd_request & rd_address[AWIDTH-1:AWIDTH-DIMM_W] == z;
else assign to_avm_valid = rd_request;
lsu_rd_back #(
.NUM_DIMM (1), // NUM_DIMM == 1 : reordering is disabled
.NUM_RD_PORT (NUM_RD_PORT),
.BURST_CNT_W (BURST_CNT_W),
.MWIDTH (MWIDTH),
.MAX_MEM_DELAY(MAX_MEM_DELAY),
.PIPELINE (0),
.DEVICE (DEVICE)
) lsu_rd_back(
.clk (clk),
.reset (reset),
.i_to_avm_port_num (),
.i_to_avm_burstcount(rd_burstcount),
.i_to_avm_id (rd_o_id),
.i_to_avm_valid (to_avm_valid),
.i_data (i_data),
.i_data_valid (i_data_valid),
.o_id_af (id_af[z]),
.o_data (rd_data[z]),
.o_data_valid (rd_data_valid[z])
);
end
end
endgenerate
endmodule
// This module is used for sw-dimm-partiton.
// It has two features:
// [1] data reordering is disabled
// [2] each load LSU has a counter to make sure bank switch is allowed to happen only when all the previous requests have returned.
module lsu_swdimm_token_ring (
clk,
reset,
// from LSU
i_rd_byteenable,
i_rd_address,
i_rd_request,
i_rd_burstcount,
i_wr_byteenable,
i_wr_address,
i_wr_request,
i_wr_burstcount,
i_wr_writedata,
// from MEM
i_avm_waitrequest,
i_avm_readdata,
i_avm_return_valid,
// to MEM
o_id,
o_avm_byteenable,
o_avm_address,
o_avm_read,
o_avm_write,
o_avm_burstcount,
o_avm_writedata,
// to kernel
o_rd_waitrequest,
o_wr_waitrequest,
o_avm_readdata,
o_avm_readdatavalid,
o_avm_writeack
);
parameter AWIDTH = 32;
parameter MWIDTH_BYTES = 64;
parameter BURST_CNT_W = 5;
parameter NUM_RD_PORT = 2;
parameter NUM_WR_PORT = 2;
parameter NUM_DIMM = 1;
parameter DISABLE_ROOT_FIFO = 0;
parameter MAX_MEM_DELAY = 64;
parameter ENABLE_READ_FAST = 0;
parameter DEVICE = "Stratix V";
parameter ROOT_FIFO_AW = 8; // Token root FIFO address width; FIFO depth = 2**ROOT_FIFO_AW
parameter RD_ROOT_FIFO_AW = 7;
parameter ENABLE_DUAL_RING = 0;
parameter ENABLE_MULTIPLE_WR_RING = 0;
parameter ENABLE_LAST_WAIT = 0;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam NUM_ID = NUM_RD_PORT+NUM_WR_PORT;
localparam NUM_DIMM_W = $clog2(NUM_DIMM);
localparam RD_ID_WIDTH = (NUM_RD_PORT==1)? 1 : $clog2(NUM_RD_PORT);
localparam WR_ID_WIDTH = (NUM_WR_PORT==1)? 1 : $clog2(NUM_WR_PORT);
localparam ID_WIDTH = (RD_ID_WIDTH > WR_ID_WIDTH)? RD_ID_WIDTH : WR_ID_WIDTH;
localparam CNT_WIDTH = 8;
// avoid modelsim compile error
localparam P_NUM_RD_PORT = (NUM_RD_PORT > 0)? NUM_RD_PORT : 1;
localparam P_NUM_WR_PORT = (NUM_WR_PORT > 0)? NUM_WR_PORT : 1;
input clk;
input reset;
// from LSU
input [MWIDTH_BYTES-1:0] i_rd_byteenable [P_NUM_RD_PORT];
input [AWIDTH-1:0] i_rd_address [P_NUM_RD_PORT];
input i_rd_request [P_NUM_RD_PORT];
input [BURST_CNT_W-1:0] i_rd_burstcount [P_NUM_RD_PORT];
input [MWIDTH_BYTES-1:0] i_wr_byteenable [P_NUM_WR_PORT];
input [AWIDTH-1:0] i_wr_address [P_NUM_WR_PORT];
input i_wr_request [P_NUM_WR_PORT];
input [BURST_CNT_W-1:0] i_wr_burstcount [P_NUM_WR_PORT];
input [MWIDTH-1:0] i_wr_writedata [P_NUM_WR_PORT];
// from MEM
input i_avm_waitrequest [NUM_DIMM];
input [MWIDTH-1:0] i_avm_readdata [NUM_DIMM];
input i_avm_return_valid [NUM_DIMM];
// to MEM
output [ID_WIDTH-1:0] o_id [NUM_DIMM];
output [MWIDTH_BYTES-1:0] o_avm_byteenable [NUM_DIMM];
output [AWIDTH-NUM_DIMM_W-1:0] o_avm_address [NUM_DIMM];
output o_avm_read [NUM_DIMM];
output o_avm_write [NUM_DIMM];
output [BURST_CNT_W-1:0] o_avm_burstcount [NUM_DIMM];
output [MWIDTH-1:0] o_avm_writedata [NUM_DIMM];
// to kernel
output o_rd_waitrequest [P_NUM_RD_PORT];
output o_wr_waitrequest [P_NUM_WR_PORT];
output [MWIDTH-1:0] o_avm_readdata [P_NUM_RD_PORT];
output o_avm_readdatavalid [P_NUM_RD_PORT];
output o_avm_writeack [P_NUM_WR_PORT];
integer i, j;
wire i_read [P_NUM_RD_PORT];
wire to_lsu_rd_waitrequest [P_NUM_RD_PORT];
wire avm_read [NUM_DIMM];
// dimm switch guard
wire [0:NUM_RD_PORT-1] rd_accept;
wire [0:NUM_RD_PORT-1] switch_wait;
reg [CNT_WIDTH-1:0] pending_rd [P_NUM_RD_PORT];
reg [0:NUM_RD_PORT-1] pending_af;
reg [NUM_DIMM_W-1:0] pending_dimm_num [P_NUM_RD_PORT];
reg [0:NUM_RD_PORT-1] wait_rd;
// read back data
wire id_af [NUM_DIMM];
wire ring_i_stall [NUM_DIMM];
reg [MWIDTH-1:0] rd_data [NUM_DIMM];
wire avm_writeack [NUM_DIMM][P_NUM_WR_PORT];
wire [0:NUM_DIMM-1] v_avm_writeack [P_NUM_WR_PORT];
reg [0:NUM_DIMM-1] R_valid;
always @(posedge clk) begin
for(i=0; i<NUM_DIMM; i=i+1) rd_data[i] <= i_avm_readdata[i];
for(i=0; i<NUM_RD_PORT; i=i+1) begin
if(rd_accept[i]) pending_dimm_num[i] <= i_rd_address[i][AWIDTH-1:AWIDTH-NUM_DIMM_W];
end
end
genvar z, z0;
generate
for(z=0; z<NUM_RD_PORT; z=z+1) begin : GEN_MERGE_RD
assign i_read[z] = i_rd_request[z] & !switch_wait[z];
assign o_rd_waitrequest[z] = to_lsu_rd_waitrequest[z] | switch_wait[z];
assign rd_accept[z] = i_rd_request[z] & !o_rd_waitrequest[z];
assign switch_wait[z] = wait_rd[z] & pending_dimm_num[z] !== i_rd_address[z][AWIDTH-1:AWIDTH-NUM_DIMM_W] | pending_af[z];// may not need pending_af
end
endgenerate
lsu_token_ring #(
.AWIDTH(AWIDTH),
.MWIDTH_BYTES(MWIDTH_BYTES),
.BURST_CNT_W(BURST_CNT_W),
.NUM_RD_PORT(NUM_RD_PORT),
.NUM_WR_PORT(NUM_WR_PORT),
.NUM_DIMM(NUM_DIMM),
.DEVICE(DEVICE),
.MAX_MEM_DELAY(MAX_MEM_DELAY),
.ENABLE_LAST_WAIT(ENABLE_LAST_WAIT),
.ENABLE_DUAL_RING(ENABLE_DUAL_RING),
.ENABLE_MULTIPLE_WR_RING(ENABLE_MULTIPLE_WR_RING),
.ROOT_FIFO_AW(ROOT_FIFO_AW),
.RD_ROOT_FIFO_AW(RD_ROOT_FIFO_AW),
.ENABLE_READ_FAST(ENABLE_READ_FAST),
.DISABLE_ROOT_FIFO(DISABLE_ROOT_FIFO)
) lsu_token_ring (
.clk (clk),
.reset (reset),
.i_rd_byteenable (i_rd_byteenable),
.i_rd_address (i_rd_address),
.i_rd_request (i_read),
.i_rd_burstcount (i_rd_burstcount),
.i_wr_byteenable (i_wr_byteenable),
.i_wr_address (i_wr_address),
.i_wr_request (i_wr_request),
.i_wr_burstcount (i_wr_burstcount),
.i_wr_writedata (i_wr_writedata),
.i_avm_waitrequest(i_avm_waitrequest),
.i_avm_readdata (i_avm_readdata),
.i_avm_return_valid(i_avm_return_valid),
.o_avm_byteenable (o_avm_byteenable),
.o_avm_address (o_avm_address),
.o_avm_read (o_avm_read),
.o_avm_write (o_avm_write),
.o_avm_burstcount (o_avm_burstcount),
.o_avm_writedata (o_avm_writedata),
.o_avm_readdata (o_avm_readdata),
.o_avm_readdatavalid(o_avm_readdatavalid),
.o_id (o_id),
.o_avm_writeack (o_avm_writeack),
.o_rd_waitrequest (to_lsu_rd_waitrequest),
.o_wr_waitrequest (o_wr_waitrequest)
);
// ----------------------------
// Generate read pending count
// ----------------------------
always @(posedge clk or posedge reset) begin
if(reset) begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
pending_rd[i] <= 0;
wait_rd[i] <= 1'b0;
pending_af[i] <= 1'b0;
end
end
else begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
pending_af[i] <= pending_rd[i][CNT_WIDTH-1];
case({rd_accept[i], o_avm_readdatavalid[i]})
2'b01: begin pending_rd[i] <= pending_rd[i] - 1'b1; wait_rd[i] <= pending_rd[i] > 1; end
2'b10: begin pending_rd[i] <= pending_rd[i] + i_rd_burstcount[i]; wait_rd[i] <= 1'b1; end
2'b11: begin pending_rd[i] <= pending_rd[i] + i_rd_burstcount[i] - 1'b1; wait_rd[i] <= 1'b1; end
endcase
end
end
end
endmodule
// Burst interleaved style needs to handle two problems:
// 1) Data is returned in a different bank order than the order in which
// the banks were issued.
// 2) Multiple data words arrive in the same cycle (from different banks).
//
// This module solves the problem by storing data from different banks in seperate RAMs, and
// only one RAM's data is sent to LSUs in every clock cycle according to the request order that is buffered.
// Considering the memory bandwidth is data_width x N banks, and one data reordering block sends
// data_width bits per clock cycle, it might not saturate the available bandwidth. Therefore,
// module lsu_rd_back_n allows multiple data reordering blocks to be instantiated by setting the
// parameter NUM_REORDER.
module lsu_rd_back_n (
clk,
reset,
// from LSU to MEM
i_to_avm_port_num,
i_to_avm_burstcount,
i_to_avm_id,
i_to_avm_valid,
// from MEM to LSU
i_data,
i_data_valid,
// to Kernel LSUs
o_data,
o_data_valid,
// ID FIFO status
o_id_af,
// data FIFO status, used to stall input requests from LSUs
o_rd_bank
);
parameter NUM_DIMM = 1;
parameter NUM_RD_PORT = 1;
parameter ID_WIDTH = $clog2(NUM_RD_PORT);
parameter BURST_CNT_W = 1;
parameter MWIDTH = 512;
parameter MAX_MEM_DELAY = 64;
parameter DATA_FIFO_DEPTH = 64;
parameter PIPELINE = 0;
parameter NUM_REORDER = 2;
parameter DEVICE = "Stratix V";
localparam REMAINDER = NUM_RD_PORT%NUM_REORDER;
localparam NUM_PORT_PER = NUM_RD_PORT/NUM_REORDER;
localparam NUM_PORT_LAST = NUM_PORT_PER + REMAINDER;
localparam NUM_DIMM_W = $clog2(NUM_DIMM);
localparam PORT_FIFO_WIDTH = NUM_DIMM_W + BURST_CNT_W + ID_WIDTH;
localparam MAX_BURST = 2**(BURST_CNT_W-1);
localparam THRESHOLD = DATA_FIFO_DEPTH - MAX_BURST * 4;
localparam FIFO_AW = $clog2(DATA_FIFO_DEPTH);
localparam P_ID_WIDTH = (ID_WIDTH == 0)? 1 : ID_WIDTH;
localparam PORT_NUM_DEPTH = MAX_MEM_DELAY;
localparam PORT_NUM_AW = $clog2(PORT_NUM_DEPTH);
localparam P_NUM_DIMM_W = (NUM_DIMM_W == 0)? 1 :NUM_DIMM_W;
localparam RD_WIDTH = (NUM_REORDER == 1)? 1 :$clog2(NUM_PORT_LAST+1);
parameter FIFO_AF_THRESH = PORT_NUM_DEPTH - 5 - 2*NUM_RD_PORT;
input clk;
input reset;
input [P_NUM_DIMM_W-1:0] i_to_avm_port_num;
input [BURST_CNT_W-1:0] i_to_avm_burstcount;
input [P_ID_WIDTH-1:0] i_to_avm_id;
input i_to_avm_valid;
input [MWIDTH-1:0] i_data [NUM_DIMM];
input i_data_valid [NUM_DIMM];
output reg [MWIDTH-1:0] o_data [NUM_RD_PORT] /* synthesis syn_preserve = 1 */;
output reg o_data_valid [NUM_RD_PORT];
output [RD_WIDTH-1:0] o_rd_bank [NUM_DIMM];
output o_id_af;
genvar z, z0;
generate
if(NUM_REORDER == 1) begin : GEN_SINGLE_REORDER
wire [NUM_DIMM-1:0] rd_bank;
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_RD
assign o_rd_bank[z][0] = rd_bank[z];
end
lsu_rd_back #(
.NUM_DIMM (NUM_DIMM),
.NUM_RD_PORT (NUM_RD_PORT),
.BURST_CNT_W (BURST_CNT_W),
.ID_WIDTH(ID_WIDTH),
.MWIDTH (MWIDTH),
.DATA_FIFO_DEPTH(DATA_FIFO_DEPTH),
.MAX_MEM_DELAY (MAX_MEM_DELAY),
.PIPELINE (PIPELINE),
.DEVICE (DEVICE)
) lsu_rd_back (
.clk (clk),
.reset (reset),
.i_to_avm_port_num (i_to_avm_port_num),
.i_to_avm_burstcount(i_to_avm_burstcount),
.i_to_avm_id (i_to_avm_id),
.i_to_avm_valid (i_to_avm_valid),
.i_data (i_data),
.i_data_valid (i_data_valid),
.o_data (o_data),
.o_data_valid (o_data_valid),
.o_id_af (o_id_af),
.o_rd_bank (rd_bank)
);
end
else begin : GEN_N_REORDER
wire [0:NUM_REORDER-1] i_group_en;
wire [NUM_DIMM-1:0] id_af;
wire [NUM_REORDER-1:0] af;
wire [NUM_DIMM-1:0] rd_bank [NUM_REORDER];
wire goup_i_data_en [NUM_REORDER][NUM_DIMM];
wire [0:NUM_REORDER-1] o_group_en [NUM_DIMM];
wire [MWIDTH-1:0] group_o_data [NUM_REORDER][NUM_RD_PORT];
wire group_o_data_en [NUM_REORDER][NUM_RD_PORT];
logic [RD_WIDTH-1:0] sum [NUM_DIMM];
integer i, j;
// bit add
always @(*) begin
for(i=0; i<NUM_DIMM; i=i+1) begin
sum[i] = '0;
for(j=0; j<NUM_REORDER; j=j+1) begin
sum[i] += rd_bank[j][i];
end
end
end
assign o_rd_bank = sum;
for(z=0; z<NUM_REORDER; z=z+1) begin : GEN_DATA_REORDER
if(z < NUM_REORDER-1) begin
assign i_group_en[z] = i_to_avm_id >= z*NUM_PORT_PER & i_to_avm_id < (z+1)*NUM_PORT_PER;
for(z0=0; z0<NUM_PORT_PER; z0=z0+1) begin : GEN_
assign o_data[z*NUM_PORT_PER+z0] = group_o_data[z][z*NUM_PORT_PER+z0];
assign o_data_valid[z*NUM_PORT_PER+z0] = group_o_data_en[z][z*NUM_PORT_PER+z0];
end
end
else begin
assign i_group_en[z] = i_to_avm_id >= z*NUM_PORT_PER & i_to_avm_id < NUM_RD_PORT;
for(z0=0; z0<NUM_PORT_LAST; z0=z0+1) begin : GEN_
assign o_data[z*NUM_PORT_PER+z0] = group_o_data[z][z*NUM_PORT_PER+z0];
assign o_data_valid[z*NUM_PORT_PER+z0] = group_o_data_en[z][z*NUM_PORT_PER+z0];
end
end
for(z0=0; z0<NUM_DIMM; z0=z0+1) begin : GEN_DATA_VALID
assign goup_i_data_en[z][z0] = i_data_valid[z0] & o_group_en[z0][z];
end
assign o_id_af = |{af, id_af};
lsu_rd_back #(
.NUM_DIMM (NUM_DIMM),
.NUM_RD_PORT (NUM_RD_PORT),
.BURST_CNT_W (BURST_CNT_W),
.ID_WIDTH(ID_WIDTH),
.MWIDTH (MWIDTH),
.DATA_FIFO_DEPTH(DATA_FIFO_DEPTH),
.MAX_MEM_DELAY (MAX_MEM_DELAY),
.PIPELINE (PIPELINE),
.DEVICE (DEVICE)
) lsu_rd_back (
.clk (clk),
.reset (reset),
.i_to_avm_port_num (i_to_avm_port_num),
.i_to_avm_burstcount(i_to_avm_burstcount),
.i_to_avm_id (i_to_avm_id),
.i_to_avm_valid (i_group_en[z] & i_to_avm_valid),
.i_data (i_data),
.i_data_valid (goup_i_data_en[z]),
.o_data (group_o_data[z]),
.o_data_valid (group_o_data_en[z]),
.o_id_af (af[z]),
.o_rd_bank (rd_bank[z])
);
end // end GEN_DATA_REORDER
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_GROUP_INFO_FIFO
wire [BURST_CNT_W-1:0] rd_burstcount;
reg [BURST_CNT_W-1:0] cnt;
wire rd_group_info, empty;
reg fout_valid;
assign rd_group_info = !fout_valid | i_data_valid[z] & rd_burstcount == cnt;
always @(posedge clk or posedge reset) begin
if(reset) begin
fout_valid <= 1'b0;
cnt <= '0;
end
else begin
if(rd_group_info & !empty) fout_valid <= 1'b1;
else if(i_data_valid[z] & empty & rd_burstcount == cnt) fout_valid <= 1'b0;
if(rd_group_info & !empty)cnt <= 1;
else if(i_data_valid[z] & cnt < rd_burstcount) cnt <= cnt + 1;
end
end
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (PORT_NUM_DEPTH),
.lpm_widthu (PORT_NUM_AW),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (NUM_REORDER+BURST_CNT_W),
.almost_full_value(FIFO_AF_THRESH),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON")
) group_info_fifo (
.clock (clk),
.data ({i_group_en, i_to_avm_burstcount}),
.wrreq (i_to_avm_valid & i_to_avm_port_num == z),
.rdreq (rd_group_info),
.empty (empty),
.almost_full(id_af[z]),
.q ({o_group_en[z], rd_burstcount}),
.aclr (reset)
);
end // end GEN_GROUP_INFO_FIFO
end
endgenerate
endmodule
// This module does data reordering for load LSUs
// Need to handle the two problems:
// 1) Data is returned in a different bank order than the order in which
// the banks were issued.
// 2) Multiple data words arrive in the same cycle (from different banks).
module lsu_rd_back (
clk,
reset,
// from LSU to MEM
i_to_avm_port_num,
i_to_avm_burstcount,
i_to_avm_id,
i_to_avm_valid,
// from MEM to LSU
i_data,
i_data_valid,
// to Kernel LSUs
o_data,
o_data_valid,
// read data FIFO
o_rd_bank,
// ID FIFO status
o_id_af
);
parameter NUM_DIMM = 1;
parameter NUM_RD_PORT = 1;
parameter ID_WIDTH = $clog2(NUM_RD_PORT);
parameter BURST_CNT_W = 1;
parameter MWIDTH = 512;
parameter MAX_MEM_DELAY = 64;
parameter DATA_FIFO_DEPTH = 64;
parameter PIPELINE = 0;
parameter DEVICE = "Stratix V";
localparam NUM_DIMM_W = $clog2(NUM_DIMM);
localparam PORT_FIFO_WIDTH = NUM_DIMM_W + BURST_CNT_W + ID_WIDTH;
localparam MAX_BURST = 2**(BURST_CNT_W-1);
localparam THRESHOLD = DATA_FIFO_DEPTH - MAX_BURST * 4;
localparam FIFO_AW = $clog2(DATA_FIFO_DEPTH);
localparam P_ID_WIDTH = (ID_WIDTH == 0)? 1 : ID_WIDTH;
localparam PORT_NUM_DEPTH = MAX_MEM_DELAY;
localparam PORT_NUM_AW = $clog2(PORT_NUM_DEPTH);
localparam P_NUM_DIMM_W = (NUM_DIMM_W == 0)? 1 :NUM_DIMM_W;
parameter FIFO_AF_THRESH = PORT_NUM_DEPTH - 5 - 2*NUM_RD_PORT;
input clk;
input reset;
input [P_NUM_DIMM_W-1:0] i_to_avm_port_num;
input [BURST_CNT_W-1:0] i_to_avm_burstcount;
input [P_ID_WIDTH-1:0] i_to_avm_id;
input i_to_avm_valid;
input [MWIDTH-1:0] i_data [NUM_DIMM];
input i_data_valid [NUM_DIMM];
output reg [MWIDTH-1:0] o_data [NUM_RD_PORT] /* synthesis syn_preserve = 1 */;
output reg o_data_valid [NUM_RD_PORT];
output reg [NUM_DIMM-1:0] o_rd_bank;
output o_id_af;
integer i;
genvar z;
wire [PORT_FIFO_WIDTH-1:0] fin, fout;
wire rd_port_num;
wire port_num_empty;
wire [P_NUM_DIMM_W-1:0] port_num;
wire [BURST_CNT_W-1:0] rd_burstcount;
reg [BURST_CNT_W-1:0] cnt;
wire [ID_WIDTH-1:0] return_id;
wire [NUM_DIMM-1:0] rd_data_en, data_empty;
wire [MWIDTH-1:0] data_out [NUM_DIMM];
reg R_rd_port_num;
reg [P_NUM_DIMM_W-1:0] R_port_num;
reg [ID_WIDTH-1:0] R_id;
reg [MWIDTH-1:0] data_to_ic;
reg data_to_ic_en;
reg [BURST_CNT_W-1:0] R_o_avm_burstcnt;
reg port_num_valid;
reg data_out_valid;
reg [0:NUM_RD_PORT-1] data_id_en [NUM_RD_PORT];
wire id_af;
wire [0:NUM_DIMM-1] data_overflow;
assign o_id_af = id_af;
// to avoid 'X' in datapath in simulation
initial begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
data_id_en[i] = 0;
o_data_valid[i] = 0;
end
end
always @(posedge clk) begin
R_port_num <= port_num;
R_id <= return_id; // return_id is aligned with port_num; R_id ~ R_port_num
data_to_ic <= (NUM_DIMM == 1)? i_data[0] : data_out[R_port_num];
R_o_avm_burstcnt <= i_to_avm_burstcount;
`ifdef SIM_ONLY
if(data_overflow) begin
$display("data overflow");
$stop;
end
`endif
end
always @(posedge clk or posedge reset) begin
if(reset) begin
data_to_ic_en <= 1'b0;
R_rd_port_num <= 1'b0;
port_num_valid <= 1'b0;
data_out_valid <= 1'b0;
o_rd_bank <= 0;
end
else begin
data_out_valid <= !data_empty[port_num];
data_to_ic_en <= data_out_valid;
R_rd_port_num <= rd_port_num & !port_num_empty;
if(NUM_DIMM == 1)begin
if(rd_port_num & !port_num_empty) port_num_valid <= 1'b1;
else if(i_data_valid[0] & port_num_empty & rd_burstcount == cnt) port_num_valid <= 1'b0;
if(rd_port_num & !port_num_empty)cnt <= 1;
else if(i_data_valid[0] & cnt < rd_burstcount) cnt <= cnt + 1;
end
else begin
if(rd_port_num & !port_num_empty) port_num_valid <= 1'b1;
else if(!data_empty[port_num] & port_num_empty & rd_burstcount == cnt) port_num_valid <= 1'b0;
if(rd_port_num & !port_num_empty)cnt <= 1;
else if(!data_empty[port_num] & cnt < rd_burstcount) cnt <= cnt + 1;
end
for(i=0; i<NUM_DIMM; i=i+1) begin
o_rd_bank[i] <= rd_data_en[i] & !data_empty[i];
end
end
end
generate
if(PIPELINE) begin : GEN_PENDING_DATA
always @(posedge clk) begin
o_data[NUM_RD_PORT-1] <= data_to_ic;
for(i=0; i<NUM_RD_PORT-1; i=i+1) begin
o_data[i] <= o_data[i+1];
end
end
always @(posedge clk or posedge reset) begin
if(reset) begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
o_data_valid[i] <= 1'b0;
data_id_en[i] <= 0;
end
end
else begin
if(NUM_RD_PORT > 1) begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
data_id_en[NUM_RD_PORT-1][i] <= (NUM_DIMM == 1)? (i_data_valid[0] & return_id == i) : (data_out_valid & R_id == i);// data_id_en[0] is aligned with data_to_ic
if(i<NUM_RD_PORT-1) data_id_en[i] <= data_id_en[i+1];
o_data_valid[i] <= data_id_en[i][i];
end
end
else begin
data_id_en[0][0] <= (NUM_DIMM == 1)? i_data_valid[0] : data_out_valid;
o_data_valid[0] <= data_id_en[0][0];
end
end
end
end // end GEN_PENDING_DATA
else begin : GEN_FAST_DATA
always @(posedge clk) begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
o_data[i] <= (NUM_DIMM == 1)? i_data[0] : data_to_ic;
end
end
always @(posedge clk or posedge reset) begin
if(reset) begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin
o_data_valid[i] <= 1'b0;
data_id_en[i] <= 0;
end
end
else begin
if(NUM_RD_PORT > 1) begin
for(i=0; i<NUM_RD_PORT; i=i+1) begin // data_id_en[0] is aligned with data_to_ic
data_id_en[0][i] <= (NUM_DIMM == 1)? (i_data_valid[0] & return_id == i) : (data_out_valid & R_id == i);// data_id_en[0] is aligned with data_to_ic
o_data_valid[i] <= (NUM_DIMM == 1)? (i_data_valid[0] & return_id == i) : data_id_en[0][i];
end
end
else begin
data_id_en[0][0] <= (NUM_DIMM == 1)? i_data_valid[0] : data_out_valid;
o_data_valid[0] <= (NUM_DIMM == 1)? i_data_valid[0] : data_id_en[0][0];
end
end
end
end
if(NUM_DIMM == 1) begin : GEN_SINGLE_DIMM
assign rd_port_num = !port_num_valid | i_data_valid[0] & (rd_burstcount == cnt);
assign fin = (ID_WIDTH == 0)? i_to_avm_burstcount : {i_to_avm_burstcount, i_to_avm_id};
assign return_id = fout[P_ID_WIDTH-1:0];
assign rd_burstcount = fout[PORT_FIFO_WIDTH-1:ID_WIDTH];
end
else begin : GEN_MULTIPLE_DIMM
assign rd_port_num = !port_num_valid | !data_empty[port_num] & (rd_burstcount == cnt);
assign fin = (ID_WIDTH == 0)? {i_to_avm_port_num[NUM_DIMM_W-1:0], i_to_avm_burstcount} : {i_to_avm_port_num[NUM_DIMM_W-1:0], i_to_avm_burstcount, i_to_avm_id};
assign return_id = fout[P_ID_WIDTH-1:0];
assign rd_burstcount = fout[ID_WIDTH+BURST_CNT_W-1:ID_WIDTH];
assign port_num = fout[PORT_FIFO_WIDTH-1:PORT_FIFO_WIDTH-NUM_DIMM_W];
for(z=0; z<NUM_DIMM; z=z+1) begin : GEN_DATA_FIFO
assign rd_data_en[z] = port_num == z[NUM_DIMM_W-1:0];
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (DATA_FIFO_DEPTH),
.lpm_widthu (FIFO_AW),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (MWIDTH),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON")
) return_data_fifo (
.clock (clk),
.data (i_data[z]),
.wrreq (i_data_valid[z]),
.rdreq (rd_data_en[z]),
.empty (data_empty[z]),
.q (data_out[z]),
.full(data_overflow[z]),
.aclr (reset)
);
end
end
endgenerate
scfifo #(
.add_ram_output_register ( "ON"),
.intended_device_family ( DEVICE),
.lpm_numwords (PORT_NUM_DEPTH),
.lpm_widthu (PORT_NUM_AW),
.lpm_showahead ( "OFF"),
.lpm_type ( "scfifo"),
.lpm_width (PORT_FIFO_WIDTH),
.almost_full_value(FIFO_AF_THRESH),
.overflow_checking ( "OFF"),
.underflow_checking ( "ON"),
.use_eab ( "ON")
) port_num_fifo (
.clock (clk),
.data (fin),
.wrreq (i_to_avm_valid),
.rdreq (rd_port_num),
.empty (port_num_empty),
.almost_full(id_af),
.q (fout),
.aclr (reset)
);
endmodule
module debug_io_cnt #(
parameter WIDTH = 1
)(
input rst,
input clk,
input [WIDTH-1:0] i_0,
input [WIDTH-1:0] i_1,
output reg [31:0] o_cnt_0,
output reg [31:0] o_cnt_1,
output reg o_mismatch,
output reg [15:0] o_mismatch_cnt
);
always @(posedge clk or posedge rst) begin
if(rst) begin
o_cnt_0 <= '0;
o_cnt_1 <= '0;
o_mismatch_cnt <= '0;
o_mismatch <= '0;
end
else begin
o_cnt_0 <= o_cnt_0 + i_0;
o_cnt_1 <= o_cnt_1 + i_1;
if(o_cnt_0 == o_cnt_1) o_mismatch_cnt <= '0;
else if(!(&o_mismatch_cnt)) o_mismatch_cnt <= o_mismatch_cnt + 1;
o_mismatch <= |o_mismatch_cnt;
end
end
endmodule
|
///
/// I2C Controller
/// --------------
///
module I2C_Controller (
input CLOCK,
input RESET,
input [31:0] I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
input GO, //GO transfor
output I2C_SCLK, //I2C CLOCK
inout I2C_SDAT, //I2C DATA
output reg END, //END transfor
output ACK //ACK
);
reg SDO;
reg SCLK;
reg [31:0]SD;
reg [6:0]SD_COUNTER;
assign I2C_SCLK = SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <= 39))? ~CLOCK : 1'b0);
assign I2C_SDAT = SDO ? 1'bz : 1'b0;
reg ACK1,ACK2,ACK3,ACK4;
assign ACK = ACK1 | ACK2 |ACK3 |ACK4;
//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 41) SD_COUNTER[6:0] = SD_COUNTER[6:0] + 7'd1;
end
end
//----
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[31];
6'd4 : SDO=SD[30];
6'd5 : SDO=SD[29];
6'd6 : SDO=SD[28];
6'd7 : SDO=SD[27];
6'd8 : SDO=SD[26];
6'd9 : SDO=SD[25];
6'd10 : SDO=SD[24];
6'd11 : SDO=1'b1;//ACK
//SUB ADDR
6'd12 : begin SDO=SD[23]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[22];
6'd14 : SDO=SD[21];
6'd15 : SDO=SD[20];
6'd16 : SDO=SD[19];
6'd17 : SDO=SD[18];
6'd18 : SDO=SD[17];
6'd19 : SDO=SD[16];
6'd20 : SDO=1'b1;//ACK
//DATA
6'd21 : begin SDO=SD[15]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[14];
6'd23 : SDO=SD[13];
6'd24 : SDO=SD[12];
6'd25 : SDO=SD[11];
6'd26 : SDO=SD[10];
6'd27 : SDO=SD[9];
6'd28 : SDO=SD[8];
6'd29 : SDO=1'b1;//ACK
//DATA
6'd30 : begin SDO=SD[7]; ACK3=I2C_SDAT; end
6'd31 : SDO=SD[6];
6'd32 : SDO=SD[5];
6'd33 : SDO=SD[4];
6'd34 : SDO=SD[3];
6'd35 : SDO=SD[2];
6'd36 : SDO=SD[1];
6'd37 : SDO=SD[0];
6'd38 : SDO=1'b1;//ACK
//stop
6'd39 : begin SDO=1'b0; SCLK=1'b0; ACK4=I2C_SDAT; end
6'd40 : SCLK=1'b1;
6'd41 : begin SDO=1'b1; END=1; end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSBP_TB_V
`define SKY130_FD_SC_LS__DFSBP_TB_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dfsbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SET_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 SET_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 SET_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SET_B = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SET_B = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__dfsbp dut (.D(D), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O221AI_SYMBOL_V
`define SKY130_FD_SC_HD__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O221AI_SYMBOL_V
|
// Copyright 2019 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
`timescale 1ns/100ps
`include "qpi_flash.v"
`define assert(condition, message) if(!(condition)) begin $display("ASSERTION FAILED: %s", message); $finish(1); end
module qpi_flash_test;
// test clock
reg clk;
// inputs to the module under test
wire ready;
reg reset = 0;
reg read = 0;
reg [23:0] addr = 0;
reg passthrough = 0;
reg passthrough_nCE;
reg passthrough_SCK;
reg passthrough_MOSI;
// outputs from the module under test
wire [7:0] data_out;
// connections to the outside world
wire flash_SCK;
wire flash_nCE;
wire flash_IO0;
wire flash_IO1;
wire flash_IO2;
wire flash_IO3;
reg driving_IO = 0;
reg [3:0] output_IO = 4'bz;
assign flash_IO3 = output_IO[3];
assign flash_IO2 = output_IO[2];
assign flash_IO1 = output_IO[1];
assign flash_IO0 = output_IO[0];
// test spi feeder
reg spi_ss = 1'b1;
reg spi_sck = 1'b0;
reg spi_mosi = 1'b0;
wire spi_miso;
`define SHIFT_HIGH 63
reg [`SHIFT_HIGH:0] spi_shift;
reg [8:0] shift_count = 0;
reg waiting_for_reset = 0;
reg reset_wait_finished = 0;
reg [31:0] reset_wait_count = 0;
// module under test
qpi_flash dut(
.clk(clk),
.ready(ready),
.reset(reset),
.read(read),
.addr(addr),
.data_out(data_out),
.passthrough(passthrough),
.passthrough_nCE(passthrough_nCE),
.passthrough_SCK(passthrough_SCK),
.passthrough_MOSI(passthrough_MOSI),
.flash_nCE(flash_nCE),
.flash_SCK(flash_SCK),
.flash_IO0(flash_IO0),
.flash_IO1(flash_IO1),
.flash_IO2(flash_IO2),
.flash_IO3(flash_IO3)
);
// clock driver
initial begin
clk = 1'b0;
forever #9 clk = ~clk;
end
always @(posedge dut.ready) begin
$display("rising edge on ready");
end
always @(negedge dut.reset) begin
$display("falling edge on reset");
end
always @(negedge dut.read) begin
$display("falling edge on read");
end
always @(negedge flash_nCE) begin
$display("falling edge on flash_nCE");
shift_count <= 0;
end
always @(posedge flash_SCK) begin
if (dut.qpi_mode == 1) begin
spi_shift <= {spi_shift[`SHIFT_HIGH-4:0], flash_IO3, flash_IO2, flash_IO1, flash_IO0};
$display("rising QPI edge with output nybble %x", {flash_IO3, flash_IO2, flash_IO1, flash_IO0});
shift_count <= shift_count + 4;
end else begin
spi_shift <= {spi_shift[`SHIFT_HIGH-1:0], flash_IO0};
// $display("rising SPI edge with MOSI %x", flash_IO0);
shift_count <= shift_count + 1;
end
end
always @(negedge flash_SCK) begin
if (shift_count == 8) begin
$display("-> output byte %x", spi_shift[7:0]);
shift_count <= 0;
end
end
always @(posedge clk) begin
if (ready == 1 || reset_wait_count > 10000) begin
reset_wait_finished <= 1;
end else if (reset_wait_finished == 0) begin
reset_wait_count <= reset_wait_count + 1;
end
end
initial begin
$display("running qpi_flash_test");
$dumpfile("qpi_flash_test.vcd");
$dumpvars(0, qpi_flash_test);
$display("start");
reset <= 1;
repeat(10) @(posedge clk);
reset <= 0;
waiting_for_reset <= 1;
reset_wait_count <= 0;
reset_wait_finished <= 0;
@(posedge reset_wait_finished);
`assert(ready == 1'b1, "FAIL: device not ready");
$display("\n\nReset successful; trying a read (0 alignment)");
addr <= 24'h123454;
read <= 1;
@(posedge clk);
read <= 0;
// wait for 4 qpi bytes
repeat(8) @(negedge flash_SCK);
// now push some data
output_IO <= 4'hA;
@(negedge flash_SCK);
output_IO <= 4'hB;
@(negedge flash_SCK);
// output_IO <= 4'hC;
// @(negedge flash_SCK);
// output_IO <= 4'hD;
// @(negedge flash_SCK);
// output_IO <= 4'hE;
// @(negedge flash_SCK);
// output_IO <= 4'hF;
// @(negedge flash_SCK);
// output_IO <= 4'h1;
// @(negedge flash_SCK);
// output_IO <= 4'h2;
// @(negedge flash_SCK);
output_IO <= 4'bz;
// wait for end of txn
@(posedge flash_nCE);
$display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// `assert(dut.shifter[31:0] == 32'habcdef12, "shift value incorrect");
$display("data_out == %x", data_out);
`assert(data_out == 8'hab, "data_out incorrect");
// $finish;
// $display("\n\nReset successful; trying a read (1 alignment)");
// addr <= 24'h000005;
// read <= 1;
// @(posedge clk);
// read <= 0;
// // wait for 4 qpi bytes
// repeat(8) @(negedge flash_SCK);
// // now push some data
// output_IO <= 4'h1;
// @(negedge flash_SCK);
// output_IO <= 4'h2;
// @(negedge flash_SCK);
// output_IO <= 4'h3;
// @(negedge flash_SCK);
// output_IO <= 4'h4;
// @(negedge flash_SCK);
// // output_IO <= 4'h5;
// // @(negedge flash_SCK);
// // output_IO <= 4'h6;
// // @(negedge flash_SCK);
// // output_IO <= 4'h7;
// // @(negedge flash_SCK);
// // output_IO <= 4'h8;
// // @(negedge flash_SCK);
// output_IO <= 4'bz;
// // wait for end of txn
// @(posedge flash_nCE);
// $display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// // `assert(dut.shifter[31:0] == 32'h12345678, "shift value incorrect");
// $display("data_out == %x", data_out);
// `assert(data_out == 8'h34, "data_out incorrect");
// $display("\n\nReset successful; trying a read (2 alignment)");
// addr <= 24'hfffff2;
// read <= 1;
// @(posedge clk);
// read <= 0;
// // wait for 4 qpi bytes
// repeat(8) @(negedge flash_SCK);
// // now push some data
// output_IO <= 4'h1;
// @(negedge flash_SCK);
// output_IO <= 4'ha;
// @(negedge flash_SCK);
// output_IO <= 4'h2;
// @(negedge flash_SCK);
// output_IO <= 4'hb;
// @(negedge flash_SCK);
// output_IO <= 4'h3;
// @(negedge flash_SCK);
// output_IO <= 4'hc;
// @(negedge flash_SCK);
// // output_IO <= 4'h4;
// // @(negedge flash_SCK);
// // output_IO <= 4'hd;
// // @(negedge flash_SCK);
// output_IO <= 4'bz;
// // wait for end of txn
// @(posedge flash_nCE);
// $display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// // `assert(dut.shifter[31:0] == 32'h1a2b3c4d, "shift value incorrect");
// $display("data_out == %x", data_out);
// `assert(data_out == 8'h3c, "data_out incorrect");
// $display("\n\nReset successful; trying a read (3 alignment)");
// addr <= 24'hcccc5b;
// read <= 1;
// @(posedge clk);
// read <= 0;
// // wait for 4 qpi bytes
// repeat(8) @(negedge flash_SCK);
// // now push some data
// output_IO <= 4'hf;
// @(negedge flash_SCK);
// output_IO <= 4'h9;
// @(negedge flash_SCK);
// output_IO <= 4'he;
// @(negedge flash_SCK);
// output_IO <= 4'h8;
// @(negedge flash_SCK);
// output_IO <= 4'hd;
// @(negedge flash_SCK);
// output_IO <= 4'h7;
// @(negedge flash_SCK);
// output_IO <= 4'hc;
// @(negedge flash_SCK);
// output_IO <= 4'h6;
// @(negedge flash_SCK);
// output_IO <= 4'bz;
// // wait for end of txn
// @(posedge flash_nCE);
// $display("Read transaction finished, by the looks of things; shifter == %x", dut.shifter);
// // `assert(dut.shifter[31:0] == 32'hf9e8d7c6, "shift value incorrect");
// $display("data_out == %x", data_out);
// `assert(data_out == 8'hc6, "data_out incorrect");
// finish off
$display("running out the clock");
repeat(32) @(posedge clk);
$display("PASS");
$finish;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_fptoui(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter LATENCY = 3;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] fifo_dataout;
wire fifo_dataout_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_in ( .clock(clock), .resetn(resetn),
.data_in(i_datain), .data_out(fifo_dataout), .valid_in(i_datain_valid),
.valid_out( fifo_dataout_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datain_stall) );
defparam fifo_in.DATA_WIDTH = DATA_WIDTH;
defparam fifo_in.DEPTH = FIFO_DEPTH;
acl_fp_fptoui fp2ui( .clock(clock), .enable(~is_stalled),
.resetn(resetn), .dataa(fifo_dataout), .result(o_dataout));
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { fifo_dataout_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_dataout_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_dataout_stall) | ~fifo_dataout_valid;
assign o_dataout_valid = shift_reg_valid[0];
endmodule
|
//#############################################################################
//# Function: Clock 'OR' gate #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockor #(parameter N = 1) // number of clock inputs
(
input [N-1:0] clkin,// one hot clock inputs (only one is active!)
output clkout
);
`ifdef CFG_ASIC
generate
if((N==4))
begin : asic
asic_clockor4 ior (/*AUTOINST*/
// Outputs
.clkout (clkout),
// Inputs
.clkin (clkin[3:0]));
end // block: g0
else if((N==2))
begin : asic
asic_clockor2 ior (/*AUTOINST*/
// Outputs
.clkout (clkout),
// Inputs
.clkin (clkin[1:0]));
end
endgenerate
`else
assign clkout = |(clkin[N-1:0]);
`endif
endmodule // oh_clockmux
|
`timescale 1 ns / 1 ps
module sample_generator_v1_0_M_AXIS #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
parameter integer C_M_AXIS_TDATA_WIDTH = 32,
// Start count is the numeber of clock cycles the master will wait before initiating/issuing any transaction.
parameter integer C_M_START_COUNT = 32
)
(
// Users to add ports here
input wire [7:0] FrameSize,
input wire En,
// User ports ends
// Do not modify the ports beyond this line
// Global ports
input wire M_AXIS_ACLK,
//
input wire M_AXIS_ARESETN,
// Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
output wire M_AXIS_TVALID,
// TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
// TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
// TLAST indicates the boundary of a packet.
output wire M_AXIS_TLAST,
// TREADY indicates that the slave can accept a transfer in the current cycle.
input wire M_AXIS_TREADY
);
// sample generator -counter
reg [C_M_AXIS_TDATA_WIDTH-1 : 0] counterR;
assign M_AXIS_TDATA = counterR;
assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
// counter R circuit
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
counterR<=0;
end
else begin
if( M_AXIS_TVALID && M_AXIS_TREADY)
counterR<= counterR+1;
end
// wait for counter number of clock cycle after reset
reg sampleGeneratorEnR;
reg [7:0] afterResetCycleCounterR;
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
sampleGeneratorEnR<= 0;
afterResetCycleCounterR<=0;
end
else begin
afterResetCycleCounterR <= afterResetCycleCounterR + 1;
if(afterResetCycleCounterR == C_M_START_COUNT)
sampleGeneratorEnR <= 1;
end
// M_AXIS_TVALID circuit
reg tValidR;
assign M_AXIS_TVALID = tValidR;
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
tValidR<= 0;
end
else begin
if(!En)
tValidR<=0;
else if (sampleGeneratorEnR)
tValidR <= 1;
end
// M_AXIS_TLAST ckt
reg [7:0] packetCounter;
always @(posedge M_AXIS_ACLK)
if(!M_AXIS_ARESETN) begin
packetCounter <= 8'hff ;
end
else begin
if(M_AXIS_TVALID && M_AXIS_TREADY ) begin
if(packetCounter== (FrameSize - 1 ))
packetCounter <= 8'hff;
else
packetCounter <= packetCounter + 1;
// end
end
end
assign M_AXIS_TLAST = (packetCounter == (FrameSize -2 )) ?1:0;
//end of custom module now!
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// verilator lint_off UNOPT
// verilator lint_off UNOPTFLAT
reg [31:0] runner; initial runner = 5;
reg [31:0] runnerm1;
reg [59:0] runnerq;
reg [89:0] runnerw;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
`ifdef verilator
if (runner != 0) $stop; // Initial settlement failed
`endif
end
if (cyc==2) begin
runner = 20;
runnerq = 60'h0;
runnerw = 90'h0;
end
if (cyc==3) begin
if (runner != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
// This forms a "loop" where we keep going through the always till runner=0
// This isn't "regular" beh code, but insures our change detection is working properly
always @ (/*AS*/runner) begin
runnerm1 = runner - 32'd1;
end
always @ (/*AS*/runnerm1) begin
if (runner > 0) begin
runner = runnerm1;
runnerq = runnerq - 60'd1;
runnerw = runnerw - 90'd1;
$write ("[%0t] runner=%d\n", $time, runner);
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
module cf_hdmi (
// hdmi interface
hdmi_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
hdmi_fs_toggle,
hdmi_raddr_g,
hdmi_tpm_oos,
// vdma interface
vdma_clk,
vdma_wr,
vdma_waddr,
vdma_wdata,
vdma_fs_ret_toggle,
vdma_fs_waddr,
// processor interface
up_enable,
up_tpg_enable,
up_csc_bypass,
up_hs_width,
up_hs_count,
up_hs_de_min,
up_hs_de_max,
up_vs_width,
up_vs_count,
up_vs_de_min,
up_vs_de_max,
up_cp_en,
up_cp,
// debug interface (chipscope)
debug_data,
debug_trigger);
// hdmi interface
input hdmi_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [35:0] hdmi_data;
output hdmi_fs_toggle;
output [ 8:0] hdmi_raddr_g;
output hdmi_tpm_oos;
// vdma interface
input vdma_clk;
input vdma_wr;
input [ 8:0] vdma_waddr;
input [47:0] vdma_wdata;
input vdma_fs_ret_toggle;
input [ 8:0] vdma_fs_waddr;
// processor interface
input up_enable;
input up_tpg_enable;
input up_csc_bypass;
input [15:0] up_hs_width;
input [15:0] up_hs_count;
input [15:0] up_hs_de_min;
input [15:0] up_hs_de_max;
input [15:0] up_vs_width;
input [15:0] up_vs_count;
input [15:0] up_vs_de_min;
input [15:0] up_vs_de_max;
input up_cp_en;
input [23:0] up_cp;
// debug interface (chipscope)
output [63:0] debug_data;
output [ 7:0] debug_trigger;
reg hdmi_up_enable_m1 = 'd0;
reg hdmi_up_enable_m2 = 'd0;
reg hdmi_up_enable_m3 = 'd0;
reg hdmi_up_enable = 'd0;
reg hdmi_up_tpg_enable = 'd0;
reg hdmi_up_csc_bypass = 'd0;
reg [15:0] hdmi_up_hs_width = 'd0;
reg [15:0] hdmi_up_hs_count = 'd0;
reg [15:0] hdmi_up_hs_de_min = 'd0;
reg [15:0] hdmi_up_hs_de_max = 'd0;
reg [15:0] hdmi_up_vs_width = 'd0;
reg [15:0] hdmi_up_vs_count = 'd0;
reg [15:0] hdmi_up_vs_de_min = 'd0;
reg [15:0] hdmi_up_vs_de_max = 'd0;
reg hdmi_up_cp_en_m1 = 'd0;
reg hdmi_up_cp_en_m2 = 'd0;
reg hdmi_up_cp_en_m3 = 'd0;
reg hdmi_up_cp_en = 'd0;
reg [23:0] hdmi_up_cp = 'd0;
reg [15:0] hdmi_hs_count = 'd0;
reg [15:0] hdmi_vs_count = 'd0;
reg hdmi_fs_ret_toggle_m1 = 'd0;
reg hdmi_fs_ret_toggle_m2 = 'd0;
reg hdmi_fs_ret_toggle_m3 = 'd0;
reg hdmi_fs_ret = 'd0;
reg [ 8:0] hdmi_fs_waddr = 'd0;
reg hdmi_fs_toggle = 'd0;
reg [ 8:0] hdmi_raddr_g = 'd0;
reg hdmi_vs = 'd0;
reg hdmi_hs = 'd0;
reg hdmi_de = 'd0;
reg [ 9:0] hdmi_raddr = 'd0;
reg hdmi_vs_d = 'd0;
reg hdmi_hs_d = 'd0;
reg hdmi_de_d = 'd0;
reg hdmi_data_sel_d = 'd0;
reg hdmi_vs_2d = 'd0;
reg hdmi_hs_2d = 'd0;
reg hdmi_de_2d = 'd0;
reg hdmi_data_sel_2d = 'd0;
reg [47:0] hdmi_data_2d = 'd0;
reg [23:0] hdmi_tpm_data = 'd0;
reg [ 4:0] hdmi_tpm_mismatch_count = 'd0;
reg hdmi_tpm_oos = 'd0;
reg hdmi_vs_444 = 'd0;
reg hdmi_hs_444 = 'd0;
reg hdmi_de_444 = 'd0;
reg [23:0] hdmi_data_444 = 'd0;
reg hdmi_vsync = 'd0;
reg hdmi_hsync = 'd0;
reg hdmi_data_e = 'd0;
reg [35:0] hdmi_data = 'd0;
wire [15:0] hdmi_up_hs_count_s;
wire [15:0] hdmi_up_vs_count_s;
wire hdmi_fs_s;
wire hdmi_hs_s;
wire hdmi_vs_s;
wire hdmi_hs_de_s;
wire hdmi_vs_de_s;
wire hdmi_fs_ret_s;
wire [47:0] hdmi_rdata_s;
wire [23:0] hdmi_data_2d_s;
wire hdmi_tpm_mismatch_s;
wire [23:0] hdmi_tpg_data_s;
// binary to grey conversion
function [8:0] b2g;
input [8:0] b;
reg [8:0] g;
begin
g[8] = b[8];
g[7] = b[8] ^ b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// debug ports
assign debug_data[63:61] = 'd0;
assign debug_data[60:60] = hdmi_fs_s;
assign debug_data[59:59] = hdmi_fs_ret_s;
assign debug_data[58:58] = hdmi_hs_s;
assign debug_data[57:57] = hdmi_hs_de_s;
assign debug_data[56:56] = hdmi_vs_s;
assign debug_data[55:55] = hdmi_vs_de_s;
assign debug_data[54:54] = hdmi_tpm_mismatch_s;
assign debug_data[53:53] = hdmi_vs;
assign debug_data[52:52] = hdmi_hs;
assign debug_data[51:51] = hdmi_de;
assign debug_data[50:50] = hdmi_vsync;
assign debug_data[49:49] = hdmi_hsync;
assign debug_data[48:48] = hdmi_data_e;
assign debug_data[47:32] = hdmi_hs_count;
assign debug_data[31:16] = hdmi_vs_count;
assign debug_data[15: 0] = hdmi_data[15:0];
assign debug_trigger[7] = hdmi_fs_s;
assign debug_trigger[6] = hdmi_fs_ret_s;
assign debug_trigger[5] = hdmi_hs_s;
assign debug_trigger[4] = hdmi_hs_de_s;
assign debug_trigger[3] = hdmi_vs_s;
assign debug_trigger[2] = hdmi_vs_de_s;
assign debug_trigger[1] = hdmi_tpm_mismatch_s;
assign debug_trigger[0] = hdmi_data_e;
// get useful values from the programmed counters, these registers control the
// video frame size, the timing signals (sync/enable)
assign hdmi_up_hs_count_s = hdmi_up_hs_count - 1'b1;
assign hdmi_up_vs_count_s = hdmi_up_vs_count - 1'b1;
always @(posedge hdmi_clk) begin
hdmi_up_enable_m1 <= up_enable;
hdmi_up_enable_m2 <= hdmi_up_enable_m1;
hdmi_up_enable_m3 <= hdmi_up_enable_m2;
hdmi_up_enable <= hdmi_up_enable_m3;
if ((hdmi_up_enable_m2 == 1'b1) && (hdmi_up_enable_m3 == 1'b0)) begin
hdmi_up_tpg_enable <= up_tpg_enable;
hdmi_up_csc_bypass <= up_csc_bypass;
hdmi_up_hs_width <= up_hs_width;
hdmi_up_hs_count <= up_hs_count;
hdmi_up_hs_de_min <= up_hs_de_min;
hdmi_up_hs_de_max <= up_hs_de_max;
hdmi_up_vs_width <= up_vs_width;
hdmi_up_vs_count <= up_vs_count;
hdmi_up_vs_de_min <= up_vs_de_min;
hdmi_up_vs_de_max <= up_vs_de_max;
end
hdmi_up_cp_en_m1 <= up_cp_en;
hdmi_up_cp_en_m2 <= hdmi_up_cp_en_m1;
hdmi_up_cp_en_m3 <= hdmi_up_cp_en_m2;
hdmi_up_cp_en <= hdmi_up_cp_en_m3;
if ((hdmi_up_cp_en_m2 == 1'b1) && (hdmi_up_cp_en_m3 == 1'b0)) begin
hdmi_up_cp <= up_cp;
end
end
// hdmi start of frame, this triggers vdma to reading the frame buffers
assign hdmi_fs_s = ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_up_vs_width)) ?
hdmi_up_enable : 1'b0;
assign hdmi_hs_s = (hdmi_hs_count < hdmi_up_hs_width) ? hdmi_up_enable : 1'b0;
assign hdmi_vs_s = (hdmi_vs_count < hdmi_up_vs_width) ? hdmi_up_enable : 1'b0;
assign hdmi_hs_de_s = ((hdmi_hs_count < hdmi_up_hs_de_min) ||
(hdmi_hs_count >= hdmi_up_hs_de_max)) ? 1'b0 : hdmi_up_enable;
assign hdmi_vs_de_s = ((hdmi_vs_count < hdmi_up_vs_de_min) ||
(hdmi_vs_count >= hdmi_up_vs_de_max)) ? 1'b0 : hdmi_up_enable;
always @(posedge hdmi_clk) begin
if (hdmi_hs_count >= hdmi_up_hs_count_s) begin
hdmi_hs_count <= 0;
end else begin
hdmi_hs_count <= hdmi_hs_count + 1'b1;
end
if (hdmi_hs_count >= hdmi_up_hs_count_s) begin
if (hdmi_vs_count >= hdmi_up_vs_count_s) begin
hdmi_vs_count <= 0;
end else begin
hdmi_vs_count <= hdmi_vs_count + 1'b1;
end
end
end
// returned frame sync from the vdma side is used to reset the start address.
assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3;
always @(posedge hdmi_clk) begin
hdmi_fs_ret_toggle_m1 <= vdma_fs_ret_toggle;
hdmi_fs_ret_toggle_m2 <= hdmi_fs_ret_toggle_m1;
hdmi_fs_ret_toggle_m3 <= hdmi_fs_ret_toggle_m2;
hdmi_fs_ret <= hdmi_fs_ret_s;
if (hdmi_fs_ret_s == 1'b1) begin
hdmi_fs_waddr <= vdma_fs_waddr;
end
if (hdmi_fs_s == 1'b1) begin
hdmi_fs_toggle <= ~hdmi_fs_toggle;
end
hdmi_raddr_g <= b2g(hdmi_raddr[9:1]);
end
// control and data pipe line
always @(posedge hdmi_clk) begin
hdmi_vs <= hdmi_vs_s;
hdmi_hs <= hdmi_hs_s;
hdmi_de <= hdmi_hs_de_s & hdmi_vs_de_s;
if (hdmi_fs_ret == 1'b1) begin
hdmi_raddr <= {hdmi_fs_waddr, 1'b0};
end else if (hdmi_de == 1'b1) begin
hdmi_raddr <= hdmi_raddr + 1;
end
hdmi_vs_d <= hdmi_vs;
hdmi_hs_d <= hdmi_hs;
hdmi_de_d <= hdmi_de;
hdmi_data_sel_d <= hdmi_raddr[0];
hdmi_vs_2d <= hdmi_vs_d;
hdmi_hs_2d <= hdmi_hs_d;
hdmi_de_2d <= hdmi_de_d;
hdmi_data_sel_2d <= hdmi_data_sel_d;
hdmi_data_2d <= hdmi_rdata_s;
end
// hdmi data count (may be used to monitor or insert)
assign hdmi_data_2d_s = (hdmi_data_sel_2d == 1'b1) ? hdmi_data_2d[47:24] : hdmi_data_2d[23:0];
assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d;
assign hdmi_tpg_data_s = hdmi_tpm_data;
always @(posedge hdmi_clk) begin
if (hdmi_fs_ret == 1'b1) begin
hdmi_tpm_data <= 'd0;
end else if (hdmi_de_2d == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
end
if (hdmi_tpm_mismatch_s == 1'b1) begin
hdmi_tpm_mismatch_count <= 5'h10;
end else if (hdmi_tpm_mismatch_count[4] == 1'b1) begin
hdmi_tpm_mismatch_count <= hdmi_tpm_mismatch_count + 1'b1;
end
hdmi_tpm_oos <= hdmi_tpm_mismatch_count[4];
end
// select test data or dma data before csc/422
always @(posedge hdmi_clk) begin
hdmi_vs_444 <= hdmi_vs_2d;
hdmi_hs_444 <= hdmi_hs_2d;
hdmi_de_444 <= hdmi_de_2d;
if (hdmi_up_cp_en == 1'b1) begin
hdmi_data_444 <= hdmi_up_cp;
end else if (hdmi_up_tpg_enable == 1'b1) begin
hdmi_data_444 <= hdmi_tpg_data_s;
end else begin
hdmi_data_444 <= hdmi_data_2d_s;
end
if (hdmi_up_csc_bypass == 1'b1) begin
end else begin
end
hdmi_vsync <= hdmi_vs_444;
hdmi_hsync <= hdmi_hs_444;
hdmi_data_e <= hdmi_de_444;
hdmi_data <= {hdmi_data_444[23:16], hdmi_data_444[23:20],
hdmi_data_444[15:8], hdmi_data_444[15:12],
hdmi_data_444[7:0], hdmi_data_444[7:4]};
end
// data memory
cf_mem i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (hdmi_clk),
.addrb (hdmi_raddr[9:1]),
.doutb (hdmi_rdata_s));
defparam i_mem.DW = 48;
defparam i_mem.AW = 9;
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXTP_TB_V
`define SKY130_FD_SC_HD__SDFXTP_TB_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__sdfxtp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 SCD = 1'b1;
#200 SCE = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 SCD = 1'b0;
#340 SCE = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SCE = 1'b1;
#540 SCD = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SCE = 1'bx;
#680 SCD = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hd__sdfxtp dut (.D(D), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXTP_TB_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V
`define SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ms__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_ms__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////
//
// Kuba top for Mexiko
//
// Copyright (C) 2014 Christian Svensson <[email protected]>
//
//////////////////////////////////////////////////////////////////////
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 3 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
//////////////////////////////////////////////////////////////////////
module kuba (
input sys_clk_i,
input sys_rst_i,
output wb_clk_o,
input [3:0] gic_dat_i,
output [3:0] gic_dat_o,
input eth0_tx_clk,
output [3:0] eth0_tx_data,
output eth0_tx_en,
output eth0_tx_er,
input eth0_rx_clk,
input [3:0] eth0_rx_data,
input eth0_dv,
input eth0_rx_er,
input eth0_col,
input eth0_crs,
output eth0_mdc_pad_o,
inout eth0_md_pad_io,
output eth0_rst_n_o
);
////////////////////////////////////////////////////////////////////////
// Clock and reset generation module
////////////////////////////////////////////////////////////////////////
wire wb_clk;
wire wb_rst /* verilator public */;
assign wb_clk_o = wb_clk;
clkgen clkgen_i (
.sys_clk_i(sys_clk_i),
.sys_rst_i(sys_rst_i),
.wb_clk_o(wb_clk),
.wb_rst_o(wb_rst)
);
////////////////////////////////////////////////////////////////////////
// Wishbone bus
////////////////////////////////////////////////////////////////////////
`include "wb_intercon_kuba.vh"
gic_slave gic_i (
.wbm_clk_i(wb_clk),
.wbm_rst_i(wb_rst),
.wbm_adr_o(wb_m2s_gic_adr),
.wbm_stb_o(wb_m2s_gic_stb),
.wbm_cyc_o(wb_m2s_gic_cyc),
.wbm_sel_o(wb_m2s_gic_sel),
.wbm_we_o (wb_m2s_gic_we),
.wbm_cti_o(wb_m2s_gic_cti),
.wbm_bte_o(wb_m2s_gic_bte),
.wbm_dat_o(wb_m2s_gic_dat),
.wbm_err_i(wb_s2m_gic_err),
.wbm_ack_i(wb_s2m_gic_ack),
.wbm_rty_i(wb_s2m_gic_rty),
.wbm_dat_i(wb_s2m_gic_dat),
.gic_dat_i(gic_dat_i),
.gic_dat_o(gic_dat_o)
);
////////////////////////////////////////////////////////////////////////
// Expansion Memory
////////////////////////////////////////////////////////////////////////
wb_ram #(
.depth(32*1024)
) expram_i (
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_dat_i (wb_m2s_expram_dat),
.wb_adr_i (wb_m2s_expram_adr[14:0]),
.wb_sel_i (wb_m2s_expram_sel),
.wb_cti_i (wb_m2s_expram_cti),
.wb_bte_i (wb_m2s_expram_bte),
.wb_we_i (wb_m2s_expram_we),
.wb_cyc_i (wb_m2s_expram_cyc),
.wb_stb_i (wb_m2s_expram_stb),
.wb_dat_o (wb_s2m_expram_dat),
.wb_ack_o (wb_s2m_expram_ack)
);
////////////////////////////////////////////////////////////////////////
// Management Ethernet
////////////////////////////////////////////////////////////////////////
wire eth0_irq;
wire [3:0] eth0_mtxd;
wire eth0_mtxen;
wire eth0_mtxerr;
wire eth0_mtx_clk;
wire eth0_mrx_clk;
wire [3:0] eth0_mrxd;
wire eth0_mrxdv;
wire eth0_mrxerr;
wire eth0_mcoll;
wire eth0_mcrs;
wire eth0_speed;
wire eth0_duplex;
wire eth0_link;
// Management interface wires
wire eth0_md_i;
wire eth0_md_o;
wire eth0_md_oe;
// Hook up MII wires
assign eth0_mtx_clk = eth0_tx_clk;
assign eth0_tx_data = eth0_mtxd[3:0];
assign eth0_tx_en = eth0_mtxen;
assign eth0_tx_er = eth0_mtxerr;
assign eth0_mrxd[3:0] = eth0_rx_data;
assign eth0_mrxdv = eth0_dv;
assign eth0_mrxerr = eth0_rx_er;
assign eth0_mrx_clk = eth0_rx_clk;
assign eth0_mcoll = eth0_col;
assign eth0_mcrs = eth0_crs;
// Tristate control for management interface
assign eth0_md_pad_io = eth0_md_oe ? eth0_md_o : 1'bz;
assign eth0_md_i = eth0_md_pad_io;
assign eth0_rst_n_o = !wb_rst;
ethmac ethmac_i (
// Wishbone Slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_m2s_eth0_adr[11:2]),
.wb_dat_i (wb_m2s_eth0_dat),
.wb_sel_i (wb_m2s_eth0_sel),
.wb_we_i (wb_m2s_eth0_we),
.wb_cyc_i (wb_m2s_eth0_cyc),
.wb_stb_i (wb_m2s_eth0_stb),
.wb_dat_o (wb_s2m_eth0_dat),
.wb_err_o (wb_s2m_eth0_err),
.wb_ack_o (wb_s2m_eth0_ack),
// Wishbone Master Interface
.m_wb_adr_o (wb_m2s_eth0_master_adr),
.m_wb_sel_o (wb_m2s_eth0_master_sel),
.m_wb_we_o (wb_m2s_eth0_master_we),
.m_wb_dat_o (wb_m2s_eth0_master_dat),
.m_wb_cyc_o (wb_m2s_eth0_master_cyc),
.m_wb_stb_o (wb_m2s_eth0_master_stb),
.m_wb_cti_o (wb_m2s_eth0_master_cti),
.m_wb_bte_o (wb_m2s_eth0_master_bte),
.m_wb_dat_i (wb_s2m_eth0_master_dat),
.m_wb_ack_i (wb_s2m_eth0_master_ack),
.m_wb_err_i (wb_s2m_eth0_master_err),
// Ethernet MII interface
// Transmit
.mtxd_pad_o (eth0_mtxd[3:0]),
.mtxen_pad_o (eth0_mtxen),
.mtxerr_pad_o (eth0_mtxerr),
.mtx_clk_pad_i (eth0_mtx_clk),
// Receive
.mrx_clk_pad_i (eth0_mrx_clk),
.mrxd_pad_i (eth0_mrxd[3:0]),
.mrxdv_pad_i (eth0_mrxdv),
.mrxerr_pad_i (eth0_mrxerr),
.mcoll_pad_i (eth0_mcoll),
.mcrs_pad_i (eth0_mcrs),
// Management interface
.md_pad_i (eth0_md_i),
.mdc_pad_o (eth0_mdc_pad_o),
.md_pad_o (eth0_md_o),
.md_padoe_o (eth0_md_oe),
// Processor interrupt
.int_o (eth0_irq)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
generate
for (genvar width=1; width<=16; width++) begin
for (genvar amt=1; amt<=width; amt++) begin
Test #(.WIDTH(width),
.AMT(amt))
test (.ins(crc[width-1:0]));
end
end
endgenerate
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x\n",
$time, cyc, crc);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Inputs
ins
);
parameter WIDTH = 1;
parameter AMT = 1;
input [WIDTH-1:0] ins;
reg [WIDTH-1:0] got;
reg [WIDTH-1:0] expec;
int istart;
int bitn;
int ostart;
always @* begin
got = { << AMT {ins}};
// Note always starts with right-most bit
expec = 0;
for (istart=0; istart<WIDTH; istart+=AMT) begin
ostart = WIDTH - AMT - istart;
if (ostart<0) ostart = 0;
for (bitn=0; bitn<AMT; bitn++) begin
if ((istart+bitn) < WIDTH
&& (istart+bitn) >= 0
&& (ostart+bitn) < WIDTH
&& (ostart+bitn) >= 0) begin
expec[ostart+bitn] = ins[istart+bitn];
end
end
end
`ifdef TEST_VERBOSE
$write("[%0t] exp %0d'b%b got %0d'b%b = { << %0d { %0d'b%b }}\n", $time, WIDTH, expec, WIDTH, got, AMT, WIDTH, ins);
`endif
`checkh(got, expec);
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:04:13
// Design Name:
// Module Name: pm0
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pc_ctrl_pm0 #(
parameter DATA_W_IN_BYTES = 4,
parameter ADDR_W_IN_BITS = 32,
parameter DCADDR_LOW_BIT_W = 8
) (
input wire [31:0] accum_low_period,
input wire [15:0] pulse_per_second,
input wire ready_to_read ,
output reg [31:0] clk_freq = 32'd100000000,
output reg [31:0] clk_subsample = 32'd0,
output reg enable = 1'd1,
output reg use_one_pps_in = 1'd0,
input wire reg_bank_rd_start, // read start strobe
output wire reg_bank_rd_done, // read done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_rd_addr, // read address bus
output reg [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_rd_data=0,// read data bus
input wire reg_bank_wr_start, // write start strobe
output wire reg_bank_wr_done, // write done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_wr_addr, // write address bus
input wire [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_wr_data, // write data bus
input wire ACLK , // Clock source
input wire ARESETn // Reset source
);
//------------------------------------------------------------------------------
// Declare registers
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// In the basic bank these are completed straight away. Recall ....XX_start is
// a registered signal.
//------------------------------------------------------------------------------
assign reg_bank_wr_done = reg_bank_wr_start;
assign reg_bank_rd_done = reg_bank_rd_start;
//------------------------------------------------------------------------------
// Write logic
//------------------------------------------------------------------------------
always @(posedge ACLK) begin
if(!ARESETn) begin
clk_freq <= 32'd100000000;
clk_subsample <= 32'd0;
enable <= 1'd1;
use_one_pps_in <= 1'd0;
end else begin
if(reg_bank_wr_start) begin
case (reg_bank_wr_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
enable <= reg_bank_wr_data[0:0];
end
1 : begin
use_one_pps_in <= reg_bank_wr_data[0:0];
end
2 : begin
clk_freq <= reg_bank_wr_data[31:0];
end
3 : begin
clk_subsample <= reg_bank_wr_data[31:0];
end
endcase
end
end
end
//------------------------------------------------------------------------------
// READ logic
//------------------------------------------------------------------------------
always @(*) begin
// Zero the complete bus. We will set specific bits in the case
reg_bank_rd_data = 'd0;
case (reg_bank_rd_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
reg_bank_rd_data[0:0] = enable;
end
1 : begin
reg_bank_rd_data[0:0] = use_one_pps_in;
end
2 : begin
reg_bank_rd_data[31:0] = clk_freq;
end
3 : begin
reg_bank_rd_data[31:0] = clk_subsample;
end
4 : begin
reg_bank_rd_data[15:0] = pulse_per_second;
end
5 : begin
reg_bank_rd_data[31:0] = accum_low_period;
end
6 : begin
reg_bank_rd_data[0:0] = ready_to_read;
end
endcase
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:21:14 11/01/2013
// Design Name:
// Module Name: clock_divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module clock_divider(input clock, input reset, input[5:0] counter, output reg clock_out);
reg[5:0] temp_counter;
initial
begin
temp_counter <= 6'b0;
clock_out <= 1'b0;
end
always @(posedge clock or posedge reset)
begin
if(reset)
begin
temp_counter <= 6'b0;
clock_out <= 1'b0;
end
else
if(temp_counter == counter) //va convertir un clk de 50MHz a 1Hz
begin
temp_counter <= 6'b0;
clock_out <= ~clock_out;
end
else
begin
temp_counter <= temp_counter + 1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__TAPVGND_FUNCTIONAL_V
`define SKY130_FD_SC_HS__TAPVGND_FUNCTIONAL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection 1
* row down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hs__tapvgnd (
VGND,
VPWR
);
// Module ports
input VGND;
input VPWR;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__TAPVGND_FUNCTIONAL_V |
module Datapath(
output [3:0] FLAG_out, // Flag Bus
output [WORD_WIDTH-1:0] A_bus, // Address out Bus
output [WORD_WIDTH-1:0] D_bus, // Data out Bus
input [WORD_WIDTH-1:0] D_in, // Data in bus
input [15:0] CNTRL_in, // Instruction Bus
input [WORD_WIDTH-1:0] CONST_in, // Constant In Bus
input CLK
);
parameter WORD_WIDTH = 16;
Datapath_RegisterFile RF0 (
.A_data(A_bus),
.B_data(RF0_out_B),
.D_data(BMD_out),
.AA(CNTRL_in[9:7]),
.BA(CNTRL_in[12:10]),
.DA(CNTRL_in[15:13]),
.RW(CNTRL_in[0]),
.CLK(CLK)
);
Datapath_BusMuxer BMB(
.out(D_bus),
.A_in(RF0_out_B),
.B_in(CONST_in),
.S(CNTRL_in[6])
);
Datapath_BusMuxer BMD(
.out(BMD_out),
.A_in(FU0_out),
.B_in(D_in),
.S(CNTRL_in[1])
);
Datapath_FunctionUnit FU0(
.F(FU0_out),
.V(FLAG_out[3]),
.C(FLAG_out[2]),
.N(FLAG_out[1]),
.Z(FLAG_out[0]),
.A(A_bus),
.B(D_bus),
.FS(FS)
);
defparam FU0.WORD_WIDTH = WORD_WIDTH;
defparam BMD.WORD_WIDTH = WORD_WIDTH;
defparam BMB.WORD_WIDTH = WORD_WIDTH;
defparam RF0.WORD_WIDTH = WORD_WIDTH;
endmodule |
/*
*
* Copyright (c) 2011 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module e0 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[1:0],x[31:2]} ^ {x[12:0],x[31:13]} ^ {x[21:0],x[31:22]};
endmodule
module e1 (x, y);
input [31:0] x;
output [31:0] y;
assign y = {x[5:0],x[31:6]} ^ {x[10:0],x[31:11]} ^ {x[24:0],x[31:25]};
endmodule
module ch (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = z ^ (x & (y ^ z));
endmodule
module maj (x, y, z, o);
input [31:0] x, y, z;
output [31:0] o;
assign o = (x & y) | (z & (x | y));
endmodule
module s0 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:29] = x[6:4] ^ x[17:15];
assign y[28:0] = {x[3:0], x[31:7]} ^ {x[14:0],x[31:18]} ^ x[31:3];
endmodule
module s1 (x, y);
input [31:0] x;
output [31:0] y;
assign y[31:22] = x[16:7] ^ x[18:9];
assign y[21:0] = {x[6:0],x[31:17]} ^ {x[8:0],x[31:19]} ^ x[31:10];
endmodule
|
module top(
input REFERENCECLK,
output PLLOUTCORE,
output PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
//Test Pins
output SDO,
input SDI,
input SCLK
);
SB_PLL40_CORE #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
// .FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
// .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT("GENCLK"),
// .PLLOUT_SELECT("GENCLK_HALF"),
// .PLLOUT_SELECT("SHIFTREG_90deg"),
// .PLLOUT_SELECT("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
.ENABLE_ICEGATE(1'b0),
.TEST_MODE(1'b0)
) uut (
.REFERENCECLK (REFERENCECLK ),
.PLLOUTCORE (PLLOUTCORE ),
.PLLOUTGLOBAL (PLLOUTGLOBAL ),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
.BYPASS (BYPASS ),
.RESETB (RESETB ),
.LATCHINPUTVALUE(LATCHINPUTVALUE),
.SDO (SDO ),
.SDI (SDI ),
.SCLK (SCLK )
);
endmodule
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the time is 0
//--------------------------------------------------------------------------------
//-- (c) BQ. December 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//----------------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_tx when to transmit the next bit
//-- __ __
//-- __| |________________________________________________________| |________________
//-- -> <- 1 clock cycle
//--
//---------------------------------------------------------------------------------------
module baudgen_tx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire rstn, //-- Reset (active low)
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
localparam N = $clog2(BAUDRATE);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
always @(posedge clk)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is 0, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == 0) ? clk_ena : 0;
endmodule
|
//% @file Top_SR.v
//% @brief TMIIa shift register control module.
//% @author pyxiong
//%
//% This module generates shift register control signals,
//% and receives the output data of TMIIa shift register .
//% This module is controlled by a high frequency clock clk_in,
//% it sends parallized data(din) to shift register chip,
//% and receives data(data_in_p,data_in_n) from shift register chip,
//% then output parallized data(dout) from shift register.
//% Clock_Div.v: generates a divided clock which acts as the control
//% clock of some submodules(SR_Control.v, Receive_Data.v), the divided clock
//% frequency is clk_in/2**div.
//% SR_Control.v: generates signals sent to shift
//% register. When start is asserted, data(data_out_p,data_out_n) will sent to
//% shift register one by one, after finishing sending data, the load_sr is
//% asserted.
//% Clock_SR.v: generates shift register's control
//% clock(clk_sr), clk_sr starts running after start signal is asserted,
//% and after the last bit is written into shift register, clk_sr
//% must stop until next assertion of start signal.
//% Receive_Data.v: When start is asserted, the data(data_in_p,data_in_n)
//% stored in shift register will be sent to this module, when 170-bit
//% data are received, a 170-bit width data(dout) will come to the output
//% port of this module.
//%
`timescale 1ns / 1ps
module Top_SR #(parameter WIDTH=170, //% @param Width of data input and output
parameter CNT_WIDTH=8, //% @param WIDTH must be no greater than 2**CNT_WIDTH
parameter DIV_WIDTH=6, //% @param width of division factor.
parameter COUNT_WIDTH=64, //% @param Width of clock division counter, it must be greater than 2**DIV_WIDTH.
parameter SHIFT_DIRECTION=1, //% @param 1: MSB out first, 0: LSB out first
parameter READ_TRIG_SRC=0, //% @param 0:start act as trig, 1: load_sr act as trig
parameter READ_DELAY=1 //% @param state machine delay period
) (
input clk_in, //% clock input is synchronised with input signals' control clock.
input rst, //% module reset
input start, //% start signal
input [WIDTH-1:0] din, //% 170-bit data input, to be sent to shift register.
input data_in_p, //% data from shift register
input data_in_n, //% data from shift register
input [DIV_WIDTH-1:0] div, //% clock frequency division factor 2**div
output clk, //% sub modules' control clock
output clk_sr_p, //% control clock send to shift register
output clk_sr_n, //% control clock send to shift register
output data_out_p, //% data send to shift register
output data_out_n, //% data send to shift register
output load_sr_p, //% load signal send to shift register
output load_sr_n, //% load signal send to shift register
output valid, //% valid is asserted when 170-bit dout is on the output port
output [WIDTH-1:0] dout //% parallized captured data (170-bit) from shift register
);
wire data_in;
wire data_out;
wire clk_sr;
wire load_sr;
wire trig;
wire [CNT_WIDTH-1:0] count_delay;
wire [COUNT_WIDTH-1:0] counter;
IBUFDS #(.DIFF_TERM("TRUE"))
IBUFDS_inst (
.O(data_in),
.I(data_in_p),
.IB(data_in_n)
);
OBUFDS OBUFDS_inst1 (
.I(data_out),
.O(data_out_p),
.OB(data_out_n)
);
OBUFDS OBUFDS_inst2 (
.I(clk_sr),
.O(clk_sr_p),
.OB(clk_sr_n)
);
OBUFDS OBUFDS_inst3 (
.I(load_sr),
// .I(start),
.O(load_sr_p),
.OB(load_sr_n)
);
Clock_Div #(.DIV_WIDTH(DIV_WIDTH), .COUNT_WIDTH(COUNT_WIDTH))
clock_div_0(
.clk_in(clk_in),
.rst(rst),
.div(div),
.counter(counter),
.clk_out(clk)
);
SR_Control #(.DATA_WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .SHIFT_DIRECTION(SHIFT_DIRECTION))
sr_control_0(
.din(din),
.clk(clk),
.rst(rst),
.start(start),
.data_out(data_out),
.load_sr(load_sr),
.count_delay(count_delay)
//.clk_sr(clk_sr)
);
reg start_reg;
wire start_tmp;
assign start_tmp=start_reg;
always@(posedge clk or posedge rst)
begin
if(rst)
begin
start_reg<=0;
end
else
begin
start_reg<=start;
end
end
Clock_SR #(.WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .COUNT_WIDTH(COUNT_WIDTH), .DIV_WIDTH(DIV_WIDTH))
clock_sr_0(
.clk_in(clk_in),
.rst(rst),
.count(count_delay),
.counter(counter),
.start(start),
.start_tmp(start_tmp),
.div(div),
.clk_sr(clk_sr)
);
assign trig= (READ_TRIG_SRC==1)? load_sr: start;
Receive_Data #(.DATA_WIDTH(WIDTH), .CNT_WIDTH(CNT_WIDTH), .SHIFT_DIRECTION(SHIFT_DIRECTION), .READ_DELAY(READ_DELAY))
receive_data_0(
.data_in(data_in),
.clk(clk),
.rst(rst),
.start(trig),
.valid(valid),
.dout(dout)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`define INT_RANGE 31:0
`define INT_RANGE 31:0 // Duplicate identical defs are OK
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 511:0
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
`include "assert.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 3;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("drop.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
reg reset = 0;
wire [63:0] result;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("drop_tb.vcd");
$dumpvars(0, cpu_tb);
#18
`assert(result_empty, 1);
$finish;
end
endmodule
|
`include "../network_params.h"
module pipeline_tb();
reg clock;
reg reset;
reg [`SCREEN_X_BITWIDTH:0] screen_x;
reg [`SCREEN_Y_BITWIDTH:0] screen_y;
wire [`CAMERA_PIXEL_BITWIDTH:0] pixel;
wire [`RECT_OUT_BITWIDTH:0] rect1;
wire [`RECT_OUT_BITWIDTH:0] rect2;
wire [`RECT_OUT_BITWIDTH:0] rect3;
wire [`RECT_OUT_BITWIDTH:0] rect4;
wire [`RECT_OUT_BITWIDTH:0] rect5;
wire [`RECT_OUT_BITWIDTH:0] rect6;
wire [`RECT_OUT_BITWIDTH:0] rect7;
wire [`RECT_OUT_BITWIDTH:0] rect0;
parameter X_RES_MAX = 600;
parameter Y_RES_MAX = 800;
// DUT
top top_inst(
.clock(clock),
.reset(reset),
.screen_x_pos(screen_x),
.screen_y_pos(screen_y),
.test_pixel(pixel),
.rect1(rect1),
.rect2(rect2),
.rect3(rect3),
.rect4(rect4),
.rect5(rect5),
.rect6(rect6),
.rect7(rect7),
.rect0(rect0)
);
always begin
#5 clock <= ~clock;
end
initial begin
clock = 1'b0;
reset = 1'b1;
//pixel = 9'b001000000; // 0.25
#1000000 $stop;
end
assign pixel = screen_x;
always@(posedge clock) begin
if(screen_x < X_RES_MAX) begin
screen_x <= screen_x + 1;
end else begin
screen_x <= 0;
if (screen_y < Y_RES_MAX)
screen_y <= screen_y+1;
else
screen_y <= 0;
end // reset
end // always
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`resetall
`timescale 1 ns / 1 ps
`default_nettype none
/*
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
* two registers.
*/
module sync_signal #(
parameter WIDTH=1, // width of the input and output signals
parameter N=2 // depth of synchronizer
)(
input wire clk,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [WIDTH-1:0] sync_reg[N-1:0];
/*
* The synchronized output is the last register in the pipeline.
*/
assign out = sync_reg[N-1];
integer k;
always @(posedge clk) begin
sync_reg[0] <= in;
for (k = 1; k < N; k = k + 1) begin
sync_reg[k] <= sync_reg[k-1];
end
end
endmodule
`resetall
|
`timescale 1ns / 1ps
// vga controller module that generates signals to drive a monitor
// pixel and line counts are the current position on the display that should be output
module vga_controller(pixel_clock, reset, hsync, vsync, pixel_count, line_count);
input pixel_clock;
input reset;
output hsync;
output vsync;
output [9:0] pixel_count;
output [9:0] line_count;
// output registers
reg hsync, vsync;
reg [9:0] pixel_count, line_count;
wire [9:0] next_pixel, next_line;
// parameters
// 800x525 pixels for 640x480 display
parameter NUM_LINES = 525;
parameter NUM_PIXELS = 800;
// visible parameters
parameter WIDTH = 640;
parameter HEIGHT = 480;
// horizontal parameters (pixels)
parameter H_FRONT_PORCH = 16;
parameter H_SYNC = 96;
parameter H_BACK_PORCH = 48;
// vertical parameters (lines)
parameter V_FRONT_PORCH = 11;
parameter V_SYNC = 2;
parameter V_BACK_PORCH = 32;
always @(posedge pixel_clock) begin
if(reset) begin
pixel_count <= 10'b0;
line_count <= 10'b0;
hsync <= 1;
vsync <= 1;
end else begin
pixel_count <= next_pixel;
line_count <= next_line;
// output synchronization signals
hsync <= ~((next_pixel >= WIDTH + H_FRONT_PORCH) &
(next_pixel < WIDTH + H_FRONT_PORCH + H_SYNC));
vsync <= ~((next_line >= HEIGHT + V_FRONT_PORCH) &
(next_line < HEIGHT + V_FRONT_PORCH + V_SYNC));
end
end
// next pixel and line
assign next_pixel = (pixel_count >= NUM_PIXELS - 1) ? 1'b0 : pixel_count + 1'b1;
assign next_line = (pixel_count >= NUM_PIXELS - 1) ?
((line_count >= NUM_LINES - 1) ? 1'b0 : line_count + 1'b1) : line_count;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A31O_2_V
`define SKY130_FD_SC_LS__A31O_2_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_2 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a31o_2 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A31O_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A222OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A222OI_BLACKBOX_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A222OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_TB_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_TB_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__schmittbuf.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hvl__schmittbuf dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_TB_V
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for i2s_tx
*/
module test_i2s_tx;
// Parameters
parameter WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_l_tdata = 0;
reg [WIDTH-1:0] input_r_tdata = 0;
reg input_tvalid = 0;
reg sck = 0;
reg ws = 0;
// Outputs
wire input_tready;
wire sd;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_l_tdata,
input_r_tdata,
input_tvalid,
sck,
ws);
$to_myhdl(input_tready,
sd);
// dump file
$dumpfile("test_i2s_tx.lxt");
$dumpvars(0, test_i2s_tx);
end
i2s_tx #(
.WIDTH(WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.input_l_tdata(input_l_tdata),
.input_r_tdata(input_r_tdata),
.input_tvalid(input_tvalid),
.input_tready(input_tready),
.sck(sck),
.ws(ws),
.sd(sd)
);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright 2007 Free Software Foundation, Inc.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
//input wire [11:0] rx_a_b,
//input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
//output wire [13:0] tx_b,
output wire TXSYNC_A,
//output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [5:0] usbctl,
output wire [1:0] usbrdy,
input wire [3:0] usbrdy2,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
//inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
//inout wire [15:0] io_rx_b
output wire test_bit0,
output wire test_bit1
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64;
assign clk64 = master_clk;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = (tx_underrun == 0);
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
wire rx_WR_done;
wire rx_WR_enabled;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
wire [15:0] reg_0,reg_1,reg_2,reg_3;
wire [6:0] reg_addr;
wire [31:0] reg_data_out;
wire [31:0] reg_data_in;
wire [1:0] reg_io_enable;
wire [31:0] rssi_threshhold;
wire [31:0] rssi_wait;
wire [6:0] addr_wr;
wire [31:0] data_wr;
wire strobe_wr;
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (data_wr);
//assign serial_strobe = strobe_db;
//assign serial_data = data_db;
//assign serial_addr = addr_db;
//wires for register connection
wire [11:0] atr_tx_delay;
wire [11:0] atr_rx_delay;
wire [7:0] master_controls;
wire [3:0] debug_en;
wire [15:0] atr_mask_0;
wire [15:0] atr_txval_0;
wire [15:0] atr_rxval_0;
wire [15:0] atr_mask_1;
wire [15:0] atr_txval_1;
wire [15:0] atr_rxval_1;
wire [15:0] atr_mask_2;
wire [15:0] atr_txval_2;
wire [15:0] atr_rxval_2;
wire [15:0] atr_mask_3;
wire [15:0] atr_txval_3;
wire [15:0] atr_rxval_3;
wire [7:0] txa_refclk;
wire [7:0] txb_refclk;
wire [7:0] rxa_refclk;
wire [7:0] rxb_refclk;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr), .strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.interp_rate(interp_rate), .decim_rate(decim_rate), .misc(settings),
.txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay), .master_controls(master_controls),
.debug_en(debug_en), .atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
wire stop;
wire [15:0] stop_time;
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.reg_addr(reg_addr),
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time),
.test_bit0(test_bit0),
.test_bit1(test_bit1));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0011111111111111;
//wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
//wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
//assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
//assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
assign ch0rx = bb_rx_i0;
assign ch1rx = bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_a),.rx_b_b(rx_b_a),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_a,io_tx_a}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
//implementing freeze mode
/*
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
assign clk64 = (timestop == 0) ? master_clk : 0;
always @(posedge master_clk)
if (timestop[15:0] != 0)
timestop <= timestop - 16'd1;
else if (stop)
timestop <= stop_time;
*/
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty), .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.atr_tx_delay(atr_tx_delay), .atr_rx_delay(atr_rx_delay),
.master_controls(master_controls), .debug_en(debug_en),
.atr_mask_0(atr_mask_0), .atr_txval_0(atr_txval_0), .atr_rxval_0(atr_rxval_0),
.atr_mask_1(atr_mask_1), .atr_txval_1(atr_txval_1), .atr_rxval_1(atr_rxval_1),
.atr_mask_2(atr_mask_2), .atr_txval_2(atr_txval_2), .atr_rxval_2(atr_rxval_2),
.atr_mask_3(atr_mask_3), .atr_txval_3(atr_txval_3), .atr_rxval_3(atr_rxval_3),
.txa_refclk(txa_refclk), .txb_refclk(txb_refclk), .rxa_refclk(rxa_refclk), .rxb_refclk(rxb_refclk),
.debug_0(tx_debugbus), .debug_1(rx_debugbus));
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),
.reg_0(reg_0),.reg_1(reg_1),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
reg forb;
always @(posedge usbclk)
begin
if (strobe_db) forb <= 1;
end
endmodule // usrp_inband_usb
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008-2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire [9:0] I1 = crc[9:0];
wire [9:0] I2 = crc[19:10];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [9:0] S; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.S (S[9:0]),
// Inputs
.I1 (I1[9:0]),
.I2 (I2[9:0]));
wire [63:0] result = {32'h0, 22'h0, S};
`define EXPECTED_SUM 64'h24c38b77b0fcc2e7
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
S,
// Inputs
I1, I2
);
input [9:0] I1/*verilator public*/;
input [9:0] I2/*verilator public*/;
output reg [9:0] S/*verilator public*/;
always @(I1 or I2)
t2(I1,I2,S);
task t1;
input In1,In2;
output Sum;
Sum = In1 ^ In2;
endtask
task t2;
input[9:0] In1,In2;
output [9:0] Sum;
integer I;
begin
for (I=0;I<10;I=I+1)
t1(In1[I],In2[I],Sum[I]);
end
endtask
endmodule
|
module PS_flops_rd_ex_lsu(
in_vector_source_a,
in_vector_source_b,
in_scalar_source_a,
in_scalar_source_b,
in_imm_value0,
in_opcode,
in_lddst_stsrc_addr,
in_rd_en,
in_wr_en,
in_wfid,
in_instr_pc,
in_lds_base,
in_exec_value,
out_vector_source_a,
out_vector_source_b,
out_scalar_source_a,
out_scalar_source_b,
out_imm_value0,
out_opcode,
out_lddst_stsrc_addr,
out_rd_en,
out_wr_en,
out_wfid,
out_instr_pc,
out_lds_base,
out_exec_value,
clk,
rst
);
input clk;
input rst;
input [8191:0] in_vector_source_a;
input [2047:0] in_vector_source_b;
input [127:0] in_scalar_source_a;
input [31:0] in_scalar_source_b;
input [15:0] in_imm_value0;
input [31:0] in_opcode;
input [11:0] in_lddst_stsrc_addr;
input [3:0] in_rd_en;
input [3:0] in_wr_en;
input [5:0] in_wfid;
input [31:0] in_instr_pc;
input [15:0] in_lds_base;
input [63:0] in_exec_value;
output [8191:0] out_vector_source_a;
output [2047:0] out_vector_source_b;
output [127:0] out_scalar_source_a;
output [31:0] out_scalar_source_b;
output [15:0] out_imm_value0;
output [31:0] out_opcode;
output [11:0] out_lddst_stsrc_addr;
output [3:0] out_rd_en;
output [3:0] out_wr_en;
output [5:0] out_wfid;
output [31:0] out_instr_pc;
output [15:0] out_lds_base;
output [63:0] out_exec_value;
dff flop_vector_source_a[8191:0](
.q(out_vector_source_a),
.d(in_vector_source_a),
.clk(clk),
.rst(rst)
);
dff flop_vector_source_b[2047:0](
.q(out_vector_source_b),
.d(in_vector_source_b),
.clk(clk),
.rst(rst)
);
dff flop_scalar_source_a[127:0](
.q(out_scalar_source_a),
.d(in_scalar_source_a),
.clk(clk),
.rst(rst)
);
dff flop_scalar_source_b[31:0](
.q(out_scalar_source_b),
.d(in_scalar_source_b),
.clk(clk),
.rst(rst)
);
dff flop_imm_value0[15:0](
.q(out_imm_value0),
.d(in_imm_value0),
.clk(clk),
.rst(rst)
);
dff flop_opcode[31:0](
.q(out_opcode),
.d(in_opcode),
.clk(clk),
.rst(rst)
);
dff flop_lddst_stsrc_add[11:0](
.q(out_lddst_stsrc_addr),
.d(in_lddst_stsrc_addr),
.clk(clk),
.rst(rst)
);
dff flop_rd_en[3:0](
.q(out_rd_en),
.d(in_rd_en),
.clk(clk),
.rst(rst)
);
dff flop_wr_en[3:0](
.q(out_wr_en),
.d(in_wr_en),
.clk(clk),
.rst(rst)
);
dff flop_wfid[5:0](
.q(out_wfid),
.d(in_wfid),
.clk(clk),
.rst(rst)
);
dff flop_instr_pc[31:0](
.q(out_instr_pc),
.d(in_instr_pc),
.clk(clk),
.rst(rst)
);
dff flop_lds_base[15:0](
.q(out_lds_base),
.d(in_lds_base),
.clk(clk),
.rst(rst)
);
dff flop_exec_value[63:0](
.q(out_exec_value),
.d(in_exec_value),
.clk(clk),
.rst(rst)
);
endmodule
|
// TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_017.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 222
`timescale 1 ps / 1 ps
module TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_017 #(
parameter inBitsPerSymbol = 18,
parameter inUsePackets = 0,
parameter inDataWidth = 18,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 18,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [17:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [17:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 18)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
TimeHoldOver_Qsys_mm_interconnect_0_avalon_st_adapter_017_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPM_Toggle_CAL_DDR100 for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPM_Toggle_CAL_DDR100
// Module Name: NPM_Toggle_CAL_DDR100
// File Name: NPM_Toggle_CAL_DDR100.v
//
// Version: v1.0.0
//
// Description: Toggle NAND command and address output FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPM_Toggle_CAL_DDR100
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
oReady ,
oLastStep ,
iStart ,
iTargetWay ,
iNumOfData ,
iCASelect ,
iCAData ,
oPO_DQStrobe ,
oPO_DQ ,
oPO_ChipEnable ,
oPO_WriteEnable ,
oPO_AddressLatchEnable ,
oPO_CommandLatchEnable ,
oDQSOutEnable ,
oDQOutEnable
);
input iSystemClock ;
input iReset ;
output oReady ;
output oLastStep ;
input iStart ;
input [NumberOfWays - 1:0] iTargetWay ;
input [3:0] iNumOfData ;
input iCASelect ;
input [7:0] iCAData ;
output [7:0] oPO_DQStrobe ;
output [31:0] oPO_DQ ;
output [2*NumberOfWays - 1:0] oPO_ChipEnable ;
output [3:0] oPO_WriteEnable ;
output [3:0] oPO_AddressLatchEnable ;
output [3:0] oPO_CommandLatchEnable ;
output oDQSOutEnable ;
output oDQOutEnable ;
// FSM Parameters/Wires/Regs
localparam CPT_FSM_BIT = 5; // CaPTure
localparam CPT_RESET = 5'b00001;
localparam CPT_READY = 5'b00010; // Ready
localparam CPT_SFRST = 5'b00100; // Command/Address capture: first
localparam CPT_SLOOP = 5'b01000; // Command/Address capture: loop
localparam CPT_WAITS = 5'b10000;
reg [CPT_FSM_BIT-1:0] rCPT_cur_state ;
reg [CPT_FSM_BIT-1:0] rCPT_nxt_state ;
localparam LCH_FSM_BIT = 8; // LatCH with PI buffer reset function
localparam LCH_RESET = 8'b0000_0001;
localparam LCH_READY = 8'b0000_0010; // Ready
localparam LCH_PREST = 8'b0000_0100; // prefaring state
localparam LCH_WDQSH = 8'b0000_1000; // DQS hold for program operation tWPSTH, wait BRAM buffer
localparam LCH_ST001 = 8'b0001_0000; // LOOP state 01:
localparam LCH_ST002 = 8'b0010_0000; // LOOP state 02:
localparam LCH_ST003 = 8'b0100_0000; // LOOP state 03:
localparam LCH_ST004 = 8'b1000_0000; // LOOP state 04:
reg [LCH_FSM_BIT-1:0] rLCH_cur_state ;
reg [LCH_FSM_BIT-1:0] rLCH_nxt_state ;
// Internal Wires/Regs
reg rReady ;
reg rLastStep ;
reg [3:0] rNumOfCommand ;
reg [1:0] rLCHSubCounter ;
reg [3:0] rLCHCounter ;
reg rCABufferWEnable ;
reg [3:0] rCABufferWAddr ;
reg rCABufferREnable ;
reg [3:0] rCABufferRAddr ;
wire wCABufferRSelect ;
wire [7:0] wCABufferRData ;
reg rCASelect_B ;
reg [7:0] rCAData_B ;
wire [2*NumberOfWays - 1:0] wPO_ChipEnable ;
wire wCPTDone ;
wire wtWPSTHStart ;
wire wtWPSTHDone ;
wire wLCHLoopDone ;
reg [31:0] rPO_DQ ;
reg [2*NumberOfWays - 1:0] rPO_ChipEnable ;
reg [3:0] rPO_WriteEnable ;
reg [3:0] rPO_AddressLatchEnable ;
reg [3:0] rPO_CommandLatchEnable ;
reg rDQOutEnable ;
// PI buffer reset
//reg rPI_BUFF_Reset ;
//reg rPI_BUFF_RE ;
//reg rPI_BUFF_WE ;
reg [7:0] rPO_DQStrobe ; // tWPSTH
reg rDQSOutEnable ; // tWPSTH
// Control Signals
// Target Way Decoder
assign wPO_ChipEnable = { iTargetWay[NumberOfWays - 1:0], iTargetWay[NumberOfWays - 1:0] };
// Flow Control
assign wCPTDone = (rCABufferWAddr[3:0] == rNumOfCommand[3:0]);
assign wtWPSTHStart = (rLCHSubCounter[1:0] == 2'b00);
assign wtWPSTHDone = (rLCHSubCounter[1:0] == 2'b11);
assign wLCHLoopDone = (rLCHCounter[3:0] == rNumOfCommand[3:0]);
// BRAM: Command/Address Buffer
SDPRAM_9A16x9B16
CABuffer
(
.clka(iSystemClock), // input wire clka
.ena(rCABufferWEnable), // input wire ena
.wea(rCABufferWEnable), // input wire [0 : 0] wea
.addra(rCABufferWAddr), // input wire [3 : 0] addra
.dina({ iCASelect, iCAData[7:0] }), // input wire [8 : 0] dina
.clkb(iSystemClock), // input wire clkb
.enb(rCABufferREnable), // input wire enb
.addrb(rCABufferRAddr), // input wire [3 : 0] addrb
.doutb({ wCABufferRSelect, wCABufferRData[7:0] }) // output wire [8 : 0] doutb
);
// FSM: Command/Address CaPTure (CPT)
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rCPT_cur_state <= CPT_RESET;
end else begin
rCPT_cur_state <= rCPT_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (rCPT_cur_state)
CPT_RESET: begin
rCPT_nxt_state <= CPT_READY;
end
CPT_READY: begin
rCPT_nxt_state <= (iStart)? CPT_SFRST:CPT_READY;
end
CPT_SFRST: begin
rCPT_nxt_state <= (wCPTDone)? CPT_WAITS:CPT_SLOOP;
end
CPT_SLOOP: begin
rCPT_nxt_state <= (wCPTDone)? CPT_WAITS:CPT_SLOOP;
end
CPT_WAITS: begin
rCPT_nxt_state <= (rLastStep)? ((iStart)? CPT_SFRST:CPT_READY):CPT_WAITS;
end
default:
rCPT_nxt_state <= CPT_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rCABufferWEnable <= 0;
rCABufferWAddr[3:0] <= 0;
end else begin
case (rCPT_nxt_state)
CPT_RESET: begin
rCABufferWEnable <= 0;
rCABufferWAddr[3:0] <= 0;
end
CPT_READY: begin
rCABufferWEnable <= 0;
rCABufferWAddr[3:0] <= 0;
end
CPT_SFRST: begin
rCABufferWEnable <= 1;
rCABufferWAddr[3:0] <= 4'b0000;
end
CPT_SLOOP: begin
rCABufferWEnable <= 1;
rCABufferWAddr[3:0] <= rCABufferWAddr[3:0] + 1'b1;
end
CPT_WAITS: begin
rCABufferWEnable <= 0;
rCABufferWAddr[3:0] <= 0;
end
endcase
end
end
// FSM: Command/Address LatCH (LCH) with PI buffer reset function
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rLCH_cur_state <= LCH_RESET;
end else begin
rLCH_cur_state <= rLCH_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (rLCH_cur_state)
LCH_RESET: begin
rLCH_nxt_state <= LCH_READY;
end
LCH_READY: begin
rLCH_nxt_state <= (iStart)? LCH_PREST:LCH_READY;
end
LCH_PREST: begin
rLCH_nxt_state <= LCH_WDQSH;
end
LCH_WDQSH: begin
rLCH_nxt_state <= (wtWPSTHDone)? LCH_ST001:LCH_WDQSH;
end
LCH_ST001: begin
rLCH_nxt_state <= LCH_ST002;
end
LCH_ST002: begin
rLCH_nxt_state <= LCH_ST003;
end
LCH_ST003: begin
rLCH_nxt_state <= LCH_ST004;
end
LCH_ST004: begin
rLCH_nxt_state <= (rLastStep)? ((iStart)? LCH_PREST:LCH_READY):LCH_ST001;
end
default:
rLCH_nxt_state <= LCH_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rReady <= 0;
rLastStep <= 0;
rNumOfCommand[3:0] <= 0;
rLCHSubCounter[1:0] <= 0;
rLCHCounter[3:0] <= 0;
rCABufferREnable <= 0;
rCABufferRAddr[3:0] <= 0;
rCASelect_B <= 0;
rCAData_B[7:0] <= 0;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQOutEnable <= 0;
// tWPSTH
rPO_DQStrobe[7:0] <= 0;
rDQSOutEnable <= 0;
end else begin
case (rLCH_nxt_state)
LCH_RESET: begin
rReady <= 0;
rLastStep <= 0;
rNumOfCommand[3:0] <= 0;
rLCHSubCounter[1:0] <= 0;
rLCHCounter[3:0] <= 0;
rCABufferREnable <= 0;
rCABufferRAddr[3:0] <= 0;
rCASelect_B <= 0;
rCAData_B[7:0] <= 0;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQOutEnable <= 0;
// tWPSTH
rPO_DQStrobe[7:0] <= 0;
rDQSOutEnable <= 0;
end
LCH_READY: begin
rReady <= 1;
rLastStep <= 0;
rNumOfCommand[3:0] <= 0;
rLCHSubCounter[1:0] <= 0;
rLCHCounter[3:0] <= 0;
rCABufferREnable <= 0;
rCABufferRAddr[3:0] <= 0;
rCASelect_B <= 0;
rCAData_B[7:0] <= 0;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQOutEnable <= 0;
// tWPSTH
rPO_DQStrobe[7:0] <= 0;
rDQSOutEnable <= 0;
end
LCH_PREST: begin
rReady <= 0;
rLastStep <= 0;
rNumOfCommand[3:0] <= iNumOfData[3:0];
rLCHSubCounter[1:0] <= 0;
rLCHCounter[3:0] <= 0;
rCABufferREnable <= 0;
rCABufferRAddr[3:0] <= 0;
rCASelect_B <= 0;
rCAData_B[7:0] <= 0;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= wPO_ChipEnable;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQOutEnable <= 1;
// tWPSTH
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rDQSOutEnable <= 1'b1;
end
LCH_WDQSH: begin
rReady <= 0;
rLastStep <= 0;
rNumOfCommand[3:0] <= rNumOfCommand[3:0];
rLCHSubCounter[1:0] <= rLCHSubCounter[1:0] + 1'b1;
rLCHCounter[3:0] <= 0;
rCABufferREnable <= 1'b1;
rCABufferRAddr[3:0] <= 4'b0000;
rCASelect_B <= 0;
rCAData_B[7:0] <= 0;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= (wtWPSTHStart)? ((iCASelect)? 4'b1111:4'b0000):(rPO_AddressLatchEnable[3:0]);
rPO_CommandLatchEnable[3:0] <= (wtWPSTHStart)? ((iCASelect)? 4'b0000:4'b1111):(rPO_CommandLatchEnable[3:0]);
rDQOutEnable <= 1;
// tWPSTH
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rDQSOutEnable <= 1'b1;
end
LCH_ST001: begin
rReady <= 0;
rLastStep <= 0;
rNumOfCommand[3:0] <= rNumOfCommand[3:0];
rLCHSubCounter[1:0] <= rLCHSubCounter[1:0];
rLCHCounter[3:0] <= rCABufferRAddr[3:0];
rCABufferREnable <= 0;
rCABufferRAddr[3:0] <= rCABufferRAddr[3:0];
rCASelect_B <= wCABufferRSelect;
rCAData_B[7:0] <= wCABufferRData[7:0];
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b1111;
rPO_AddressLatchEnable[3:0] <= (wCABufferRSelect)? 4'b1111:4'b0000;
rPO_CommandLatchEnable[3:0] <= (wCABufferRSelect)? 4'b0000:4'b1111;
rDQOutEnable <= 1;
// tWPSTH
rPO_DQStrobe[7:0] <= 8'b0000_0000;//8'b1111_1111;
rDQSOutEnable <= 1'b1;
end
LCH_ST002: begin
rReady <= 0;
rLastStep <= 0;
rNumOfCommand[3:0] <= rNumOfCommand[3:0];
rLCHSubCounter[1:0] <= rLCHSubCounter[1:0];
rLCHCounter[3:0] <= rLCHCounter[3:0];
rCABufferREnable <= 0;
rCABufferRAddr[3:0] <= rCABufferRAddr[3:0];
rCASelect_B <= rCASelect_B;
rCAData_B[7:0] <= rCAData_B[7:0];
rPO_DQ[31:0] <= { 4{ rCAData_B[7:0] } };
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b1111;
rPO_AddressLatchEnable[3:0] <= rPO_AddressLatchEnable[3:0];
rPO_CommandLatchEnable[3:0] <= rPO_CommandLatchEnable[3:0];
rDQOutEnable <= 1;
// tWPSTH
rPO_DQStrobe[7:0] <= 8'b0000_0000;//8'b1111_1111;
rDQSOutEnable <= 1'b1;
end
LCH_ST003: begin
rReady <= 0;
rLastStep <= 0;
rNumOfCommand[3:0] <= rNumOfCommand[3:0];
rLCHSubCounter[1:0] <= rLCHSubCounter[1:0];
rLCHCounter[3:0] <= rLCHCounter[3:0];
rCABufferREnable <= ~wLCHLoopDone;
rCABufferRAddr[3:0] <= rCABufferRAddr[3:0] + 1'b1;
rCASelect_B <= rCASelect_B;
rCAData_B[7:0] <= rCAData_B[7:0];
rPO_DQ[31:0] <= { 4{ rCAData_B[7:0] } };
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= rPO_AddressLatchEnable[3:0];
rPO_CommandLatchEnable[3:0] <= rPO_CommandLatchEnable[3:0];
rDQOutEnable <= 1;
// tWPSTH
rPO_DQStrobe[7:0] <= 8'b0000_0000;//8'b1111_1111;
rDQSOutEnable <= 1'b1;
end
LCH_ST004: begin
rReady <= wLCHLoopDone;
rLastStep <= wLCHLoopDone;
rNumOfCommand[3:0] <= rNumOfCommand[3:0];
rLCHSubCounter[1:0] <= rLCHSubCounter[1:0];
rLCHCounter[3:0] <= rLCHCounter[3:0];
rCABufferREnable <= 0;
rCABufferRAddr[3:0] <= rCABufferRAddr[3:0];
rCASelect_B <= rCASelect_B;
rCAData_B[7:0] <= rCAData_B[7:0];
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= rPO_AddressLatchEnable[3:0];
rPO_CommandLatchEnable[3:0] <= rPO_CommandLatchEnable[3:0];
rDQOutEnable <= 1;
// tWPSTH
rPO_DQStrobe[7:0] <= 8'b0000_0000;//8'b1111_1111;
rDQSOutEnable <= 1'b1;
end
endcase
end
end
// Output
assign oReady = rReady ;
assign oLastStep = rLastStep ;
assign oPO_DQ = rPO_DQ ;
assign oPO_ChipEnable = rPO_ChipEnable ;
assign oPO_WriteEnable = rPO_WriteEnable ;
assign oPO_AddressLatchEnable = rPO_AddressLatchEnable;
assign oPO_CommandLatchEnable = rPO_CommandLatchEnable;
assign oDQOutEnable = rDQOutEnable ;
assign oPO_DQStrobe = rPO_DQStrobe ; // tWPSTH
assign oDQSOutEnable = rDQSOutEnable ; // tWPSTH
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright (C) 2008 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Top level module for a full setup with DUCs and DDCs
// Define DEBUG_OWNS_IO_PINS if we're using the daughterboard i/o pins
// for debugging info. NB, This can kill the m'board and/or d'board if you
// have anything except basic d'boards installed.
// Uncomment the following to include optional circuitry
`include "../top/config.vh"
`include "../../../../usrp/firmware/include/fpga_regs_common.v"
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module usrp_gpio
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
input wire [11:0] rx_a_b,
input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
output wire [13:0] tx_b,
output wire TXSYNC_A,
output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [2:0] usbctl,
output wire [1:0] usbrdy,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
inout wire [15:0] io_rx_b
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64,clk128;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire tx_underrun, rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = tx_underrun;
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [31:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
assign clk64 = master_clk;
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
wire [15:0] ch0rx_ext,ch1rx_ext;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;//analog signals
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//TX_DIG streaming digital IO signals
wire i_out_dig_0,i_out_dig_1,q_out_dig_0,q_out_dig_1;
wire rx_dig0_i, rx_dig0_q,rx_dig1_i,rx_dig1_q;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
tx_buffer tx_buffer
( .usbclk(usbclk), .bus_reset(tx_bus_reset),
.usbdata(usbdata),.WR(WR), .have_space(have_space),
.tx_underrun(tx_underrun), .clear_status(clear_status),
.txclk(clk64), .reset(tx_dsp_reset),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.txstrobe(strobe_interp),
.tx_empty(tx_empty),
.debugbus(tx_debugbus) );
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0));
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire tx_dig_a_a = (dac0mux[1] ? (dac0mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac0mux[0] ? q_out_dig_0 : i_out_dig_0));
wire tx_dig_b_a = (dac1mux[1] ? (dac1mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac1mux[0] ? q_out_dig_0 : i_out_dig_0));
wire tx_dig_a_b = (dac2mux[1] ? (dac2mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac2mux[0] ? q_out_dig_0 : i_out_dig_0));
wire tx_dig_b_b = (dac3mux[1] ? (dac3mux[0] ? q_out_dig_1 : i_out_dig_1) : (dac3mux[0] ? q_out_dig_0 : i_out_dig_0));
//wire [1:0] tx_dig_a = {tx_dig_a_a,tx_dig_b_a};
//wire [1:0] tx_dig_b = {tx_dig_a_b,tx_dig_b_b};
//wire tx_dig_a_chan = (dac0mux[1] | dac1mux[1] );
//wire tx_dig_b_chan = (dac2mux[1] | dac3mux[1] );
//TODO make enabling tx_dig configurable through register
wire enable_tx_dig_a = 1'b1 & enable_tx;
wire enable_tx_dig_b = 1'b1 & enable_tx;
wire tx_dig_a_a_en = dac0mux[3] & enable_tx_dig_a;
wire tx_dig_b_a_en = dac1mux[3] & enable_tx_dig_a;
wire tx_dig_a_b_en = dac2mux[3] & enable_tx_dig_b;
wire tx_dig_b_b_en = dac3mux[3] & enable_tx_dig_b;
//TODO make gpio bits used for tx_dig configurable through register
assign io_tx_a_out = {tx_dig_a_a_en?tx_dig_a_a:reg_0[15],tx_dig_b_a_en?tx_dig_b_a:reg_0[14],reg_0[13:0]};
assign io_tx_b_out = {tx_dig_a_b_en?tx_dig_a_b:reg_2[15],tx_dig_b_b_en?tx_dig_b_b:reg_2[14],reg_2[13:0]};
assign io_tx_a_force_output = {tx_dig_a_a_en,tx_dig_b_a_en,14'b0};
assign io_tx_b_force_output = {tx_dig_a_b_en,tx_dig_b_b_en,14'b0};
`ifdef TX_EN_DIG_0
//TODO make enabling tx_dig configurable through register
//tx_chain_dig tx_chain_dig_0
// ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
// .i_in(ch0tx), q_in(ch1tx),
// .i_out_ana(bb_tx_i0),
// .q_out_ana(bb_tx_q0),
// .i_out_dig(i_out_dig_0),
// .q_out_dig(q_out_dig_0)
// );
tx_chain_dig tx_chain_dig_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.i_in(ch0tx),.q_in(ch1tx),
.i_out_ana(bb_tx_i0),.q_out_ana(bb_tx_q0),
.i_out_dig(i_out_dig_0),.q_out_dig(q_out_dig_0));
`else
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign i_out_dig_0=1'b0;
assign q_out_dig_0=1'b0;
`endif
`ifdef TX_EN_DIG_1
//TODO make enabling tx_dig configurable through register
tx_chain_dig tx_chain_dig_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.i_in(ch2tx),.q_in(ch3tx),
.i_out_ana(bb_tx_i1),.q_out_ana(bb_tx_q1),
.i_out_dig(i_out_dig_1),.q_out_dig(q_out_dig_1));
// tx_chain_dig tx_chain_dig_1
// ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
// .i_in(ch2tx), q_in(ch3tx),
// .i_out_ana(bb_tx_i1),
// .q_out_ana(bb_tx_q1),
// .i_out_dig(i_out_dig_1),
// .q_out_dig(q_out_dig_1)
// );
`else
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
assign i_out_dig_1=1'b0;
assign q_out_dig_1=1'b0;
`endif
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`else // `ifdef TX_ON
assign io_tx_a_out = reg_0;
assign io_tx_b_out = reg_2;
assign io_tx_a_force_output=16'b0;
assign io_tx_b_force_output=16'b0;
`endif
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx_ext),.ch_1(ch1rx_ext),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.debugbus(rx_debugbus) );
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`ifdef RX_DIG_ON
wire enable_rx_dig = 1'b1 & enable_rx;//TODO make enabling rx_dig configurable through register
assign io_rx_a_force_input = {enable_rx_dig,enable_rx_dig,14'b0};
assign io_rx_b_force_input = {enable_rx_dig,enable_rx_dig,14'b0};
gpio_input gpio_input(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.out_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.io_rx_a_in(io_rx_a),.io_rx_b_in(io_rx_b),
//.io_tx_a_in(io_tx_a),.io_tx_b_in(io_tx_b),
.rx_dig0_i(rx_dig0_i),.rx_dig0_q(rx_dig0_q),
.rx_dig1_i(rx_dig1_i),.rx_dig1_q(rx_dig1_q) );
`ifdef RX_EN_DIG_0
rx_chain_dig rx_chain_dig_0
( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig),
.i_in_ana(bb_rx_i0),.q_in_ana(bb_rx_q0),
.i_in_dig(rx_dig0_i),.q_in_dig(rx_dig0_q),
.i_out(ch0rx),.q_out(ch1rx));
`else
assign ch0rx = bb_rx_i0;
assign ch1rx = bb_rx_q0;
`endif
assign ch0rx_ext = counter ? debug_counter : loopback ? loopback_i_0 : ch0rx;
assign ch1rx_ext = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : ch1rx;
`ifdef RX_EN_DIG_1
rx_chain_dig rx_chain_dig_1
( .clock(clk64),.reset(rx_dsp_reset),.enable(enable_rx_dig),
.i_in_ana(bb_rx_i1),.q_in_ana(bb_rx_q1),
.i_in_dig(rx_dig1_i),.q_in_dig(rx_dig1_q),
.i_out(ch2rx),.q_out(ch3rx));
`else
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
`endif
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
`else // `ifdef RX_DIG_ON
assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
`endif // `ifdef RX_DIG_ON
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
wire [15:0] reg_0,reg_1,reg_2,reg_3;
wire [15:0] io_tx_a_out;
wire [15:0] io_tx_b_out;
wire [15:0] io_tx_a_force_output;
wire [15:0] io_tx_b_force_output;
wire [15:0] io_rx_a_force_input;
wire [15:0] io_rx_b_force_input;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
.debug_0(tx_debugbus[15:0]),.debug_1(tx_debugbus[31:16]),
.debug_2(rx_debugbus[15:0]),.debug_3(rx_debugbus[31:16]),
//.tx_dig_a(tx_dig_a),tx_dig_b(tx_dig_b),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
.reg_0(io_tx_a_out),.reg_1(reg_1),.reg_2(io_tx_b_out),.reg_3(reg_3),
.io_0_force_output(io_tx_a_force_output), .io_2_force_output(io_tx_b_force_output),
.io_1_force_input(io_rx_a_force_input), .io_3_force_input(io_rx_b_force_input),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
endmodule // usrp_gpio
|
//////////////////////////////////////////////////////////////////
// //
// Amber 25 Core top-Level module //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Instantiates the core consisting of fetch, instruction //
// decode, execute, memory access and write back. The //
// Wishbone interface and Co-Processor modules are also //
// instantiated here. //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a25_core
(
input i_clk,
input i_irq, // Interrupt request, active high
input i_firq, // Fast Interrupt request, active high
input i_system_rdy, // Amber is stalled when this is low
// Wishbone Master I/F
output [31:0] o_wb_adr,
output [15:0] o_wb_sel,
output o_wb_we,
input [127:0] i_wb_dat,
output [127:0] o_wb_dat,
output o_wb_cyc,
output o_wb_stb,
input i_wb_ack,
input i_wb_err
);
wire [31:0] execute_iaddress;
wire execute_iaddress_valid;
wire [31:0] execute_iaddress_nxt; // un-registered version of execute_address
// to the instruction cache rams
wire [31:0] execute_daddress;
wire execute_daddress_valid;
wire [31:0] execute_daddress_nxt; // un-registered version of execute_daddress
// to the data cache rams
wire [31:0] write_data;
wire write_enable;
wire [31:0] fetch_instruction;
wire decode_exclusive;
wire decode_iaccess;
wire decode_daccess;
wire [3:0] byte_enable;
wire exclusive; // swap access
wire cache_enable; // Enabel the cache
wire cache_flush; // Flush the cache
wire [31:0] cacheable_area;
wire fetch_stall;
wire mem_stall;
wire exec_stall;
wire core_stall;
wire [1:0] status_bits_mode;
wire status_bits_irq_mask;
wire status_bits_firq_mask;
wire status_bits_flags_wen;
wire status_bits_mode_wen;
wire status_bits_irq_mask_wen;
wire status_bits_firq_mask_wen;
wire [31:0] execute_status_bits;
wire [31:0] imm32;
wire [4:0] imm_shift_amount;
wire shift_imm_zero;
wire [3:0] condition;
wire [3:0] rm_sel;
wire [3:0] rs_sel;
wire [7:0] decode_load_rd;
wire [8:0] exec_load_rd;
wire [3:0] rn_sel;
wire [1:0] barrel_shift_amount_sel;
wire [1:0] barrel_shift_data_sel;
wire [1:0] barrel_shift_function;
wire [8:0] alu_function;
wire [1:0] multiply_function;
wire [2:0] interrupt_vector_sel;
wire [3:0] iaddress_sel;
wire [3:0] daddress_sel;
wire [2:0] pc_sel;
wire [1:0] byte_enable_sel;
wire [2:0] status_bits_sel;
wire [2:0] reg_write_sel;
wire user_mode_regs_store_nxt;
wire firq_not_user_mode;
wire write_data_wen;
wire copro_write_data_wen;
wire base_address_wen;
wire pc_wen;
wire [14:0] reg_bank_wen;
wire [2:0] copro_opcode1;
wire [2:0] copro_opcode2;
wire [3:0] copro_crn;
wire [3:0] copro_crm;
wire [3:0] copro_num;
wire [1:0] copro_operation;
wire [31:0] copro_read_data;
wire [31:0] copro_write_data;
wire multiply_done;
wire decode_fault;
wire iabt_trigger;
wire dabt_trigger;
wire [7:0] decode_fault_status;
wire [7:0] iabt_fault_status;
wire [7:0] dabt_fault_status;
wire [31:0] decode_fault_address;
wire [31:0] iabt_fault_address;
wire [31:0] dabt_fault_address;
wire adex;
wire [31:0] mem_read_data;
wire mem_read_data_valid;
wire [10:0] mem_load_rd;
wire [31:0] wb_read_data;
wire wb_read_data_valid;
wire [10:0] wb_load_rd;
wire dcache_wb_cached_req;
wire dcache_wb_uncached_req;
wire dcache_wb_write;
wire [15:0] dcache_wb_byte_enable;
wire [31:0] dcache_wb_address;
wire [127:0] dcache_wb_cached_rdata;
wire [127:0] dcache_wb_write_data;
wire dcache_wb_cached_ready;
wire dcache_wb_uncached_ready;
wire [31:0] icache_wb_address;
wire icache_wb_req;
wire [31:0] icache_wb_adr;
wire [127:0] icache_wb_read_data;
wire icache_wb_ready;
wire conflict;
wire rn_use_read;
wire rm_use_read;
wire rs_use_read;
wire rd_use_read;
// data abort has priority
assign decode_fault_status = dabt_trigger ? dabt_fault_status : iabt_fault_status;
assign decode_fault_address = dabt_trigger ? dabt_fault_address : iabt_fault_address;
assign decode_fault = dabt_trigger | iabt_trigger;
assign core_stall = fetch_stall || mem_stall || exec_stall;
// ======================================
// Fetch Stage
// ======================================
a25_fetch u_fetch (
.i_clk ( i_clk ),
.i_mem_stall ( mem_stall ),
.i_exec_stall ( exec_stall ),
.i_conflict ( conflict ),
.i_system_rdy ( i_system_rdy ),
.o_fetch_stall ( fetch_stall ),
.i_iaddress ( {execute_iaddress[31:2], 2'd0} ),
.i_iaddress_valid ( execute_iaddress_valid ),
.i_iaddress_nxt ( execute_iaddress_nxt ),
.o_fetch_instruction ( fetch_instruction ),
.i_cache_enable ( cache_enable ),
.i_cache_flush ( cache_flush ),
.i_cacheable_area ( cacheable_area ),
.o_wb_req ( icache_wb_req ),
.o_wb_address ( icache_wb_address ),
.i_wb_read_data ( icache_wb_read_data ),
.i_wb_ready ( icache_wb_ready )
);
// ======================================
// Decode Stage
// ======================================
a25_decode u_decode (
.i_clk ( i_clk ),
.i_core_stall ( core_stall ),
// Instruction fetch or data read signals
.i_fetch_instruction ( fetch_instruction ),
.i_execute_iaddress ( execute_iaddress ),
.i_execute_daddress ( execute_daddress ),
.i_adex ( adex ),
.i_iabt ( 1'd0 ),
.i_dabt ( 1'd0 ),
.i_abt_status ( 8'd0 ),
.i_irq ( i_irq ),
.i_firq ( i_firq ),
.i_execute_status_bits ( execute_status_bits ),
.i_multiply_done ( multiply_done ),
.o_status_bits_mode ( status_bits_mode ),
.o_status_bits_irq_mask ( status_bits_irq_mask ),
.o_status_bits_firq_mask ( status_bits_firq_mask ),
.o_imm32 ( imm32 ),
.o_imm_shift_amount ( imm_shift_amount ),
.o_shift_imm_zero ( shift_imm_zero ),
.o_condition ( condition ),
.o_decode_exclusive ( decode_exclusive ),
.o_decode_iaccess ( decode_iaccess ),
.o_decode_daccess ( decode_daccess ),
.o_rm_sel ( rm_sel ),
.o_rs_sel ( rs_sel ),
.o_load_rd ( decode_load_rd ),
.o_rn_sel ( rn_sel ),
.o_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
.o_barrel_shift_data_sel ( barrel_shift_data_sel ),
.o_barrel_shift_function ( barrel_shift_function ),
.o_alu_function ( alu_function ),
.o_multiply_function ( multiply_function ),
.o_interrupt_vector_sel ( interrupt_vector_sel ),
.o_iaddress_sel ( iaddress_sel ),
.o_daddress_sel ( daddress_sel ),
.o_pc_sel ( pc_sel ),
.o_byte_enable_sel ( byte_enable_sel ),
.o_status_bits_sel ( status_bits_sel ),
.o_reg_write_sel ( reg_write_sel ),
.o_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
.o_firq_not_user_mode ( firq_not_user_mode ),
.o_write_data_wen ( write_data_wen ),
.o_base_address_wen ( base_address_wen ),
.o_pc_wen ( pc_wen ),
.o_reg_bank_wen ( reg_bank_wen ),
.o_status_bits_flags_wen ( status_bits_flags_wen ),
.o_status_bits_mode_wen ( status_bits_mode_wen ),
.o_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
.o_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
.o_copro_opcode1 ( copro_opcode1 ),
.o_copro_opcode2 ( copro_opcode2 ),
.o_copro_crn ( copro_crn ),
.o_copro_crm ( copro_crm ),
.o_copro_num ( copro_num ),
.o_copro_operation ( copro_operation ),
.o_copro_write_data_wen ( copro_write_data_wen ),
.o_iabt_trigger ( iabt_trigger ),
.o_iabt_address ( iabt_fault_address ),
.o_iabt_status ( iabt_fault_status ),
.o_dabt_trigger ( dabt_trigger ),
.o_dabt_address ( dabt_fault_address ),
.o_dabt_status ( dabt_fault_status ),
.o_conflict ( conflict ),
.o_rn_use_read ( rn_use_read ),
.o_rm_use_read ( rm_use_read ),
.o_rs_use_read ( rs_use_read ),
.o_rd_use_read ( rd_use_read )
);
// ======================================
// Execute Stage
// ======================================
a25_execute u_execute (
.i_clk ( i_clk ),
.i_core_stall ( core_stall ),
.i_mem_stall ( mem_stall ),
.o_exec_stall ( exec_stall ),
.i_wb_read_data ( wb_read_data ),
.i_wb_read_data_valid ( wb_read_data_valid ),
.i_wb_load_rd ( wb_load_rd ),
.i_copro_read_data ( copro_read_data ),
.o_write_data ( write_data ),
.o_copro_write_data ( copro_write_data ),
.o_iaddress ( execute_iaddress ),
.o_iaddress_valid ( execute_iaddress_valid ),
.o_iaddress_nxt ( execute_iaddress_nxt ),
.o_daddress ( execute_daddress ),
.o_daddress_nxt ( execute_daddress_nxt ),
.o_daddress_valid ( execute_daddress_valid ),
.o_byte_enable ( byte_enable ),
.o_write_enable ( write_enable ),
.o_exclusive ( exclusive ),
.o_priviledged ( ),
.o_exec_load_rd ( exec_load_rd ),
.o_adex ( adex ),
.o_status_bits ( execute_status_bits ),
.o_multiply_done ( multiply_done ),
.i_status_bits_mode ( status_bits_mode ),
.i_status_bits_irq_mask ( status_bits_irq_mask ),
.i_status_bits_firq_mask ( status_bits_firq_mask ),
.i_imm32 ( imm32 ),
.i_imm_shift_amount ( imm_shift_amount ),
.i_shift_imm_zero ( shift_imm_zero ),
.i_condition ( condition ),
.i_decode_exclusive ( decode_exclusive ),
.i_decode_iaccess ( decode_iaccess ),
.i_decode_daccess ( decode_daccess ),
.i_rm_sel ( rm_sel ),
.i_rs_sel ( rs_sel ),
.i_decode_load_rd ( decode_load_rd ),
.i_rn_sel ( rn_sel ),
.i_barrel_shift_amount_sel ( barrel_shift_amount_sel ),
.i_barrel_shift_data_sel ( barrel_shift_data_sel ),
.i_barrel_shift_function ( barrel_shift_function ),
.i_alu_function ( alu_function ),
.i_multiply_function ( multiply_function ),
.i_interrupt_vector_sel ( interrupt_vector_sel ),
.i_iaddress_sel ( iaddress_sel ),
.i_daddress_sel ( daddress_sel ),
.i_pc_sel ( pc_sel ),
.i_byte_enable_sel ( byte_enable_sel ),
.i_status_bits_sel ( status_bits_sel ),
.i_reg_write_sel ( reg_write_sel ),
.i_user_mode_regs_store_nxt ( user_mode_regs_store_nxt ),
.i_firq_not_user_mode ( firq_not_user_mode ),
.i_write_data_wen ( write_data_wen ),
.i_base_address_wen ( base_address_wen ),
.i_pc_wen ( pc_wen ),
.i_reg_bank_wen ( reg_bank_wen ),
.i_status_bits_flags_wen ( status_bits_flags_wen ),
.i_status_bits_mode_wen ( status_bits_mode_wen ),
.i_status_bits_irq_mask_wen ( status_bits_irq_mask_wen ),
.i_status_bits_firq_mask_wen ( status_bits_firq_mask_wen ),
.i_copro_write_data_wen ( copro_write_data_wen ),
.i_conflict ( conflict ),
.i_rn_use_read ( rn_use_read ),
.i_rm_use_read ( rm_use_read ),
.i_rs_use_read ( rs_use_read ),
.i_rd_use_read ( rd_use_read )
);
// ======================================
// Memory access stage with data cache
// ======================================
a25_mem u_mem (
.i_clk ( i_clk ),
.i_fetch_stall ( fetch_stall ),
.i_exec_stall ( exec_stall ),
.o_mem_stall ( mem_stall ),
.i_daddress ( execute_daddress ),
.i_daddress_valid ( execute_daddress_valid ),
.i_daddress_nxt ( execute_daddress_nxt ),
.i_write_data ( write_data ),
.i_write_enable ( write_enable ),
.i_byte_enable ( byte_enable ),
.i_exclusive ( exclusive ),
.i_exec_load_rd ( exec_load_rd ),
.o_mem_read_data ( mem_read_data ),
.o_mem_read_data_valid ( mem_read_data_valid ),
.o_mem_load_rd ( mem_load_rd ),
.i_cache_enable ( cache_enable ),
.i_cache_flush ( cache_flush ),
.i_cacheable_area ( cacheable_area ),
.o_wb_cached_req ( dcache_wb_cached_req ),
.o_wb_uncached_req ( dcache_wb_uncached_req ),
.o_wb_write ( dcache_wb_write ),
.o_wb_write_data ( dcache_wb_write_data ),
.o_wb_byte_enable ( dcache_wb_byte_enable ),
.o_wb_address ( dcache_wb_address ),
.i_wb_cached_ready ( dcache_wb_cached_ready ),
.i_wb_cached_rdata ( dcache_wb_cached_rdata ),
.i_wb_uncached_ready ( dcache_wb_uncached_ready ),
.i_wb_uncached_rdata ( dcache_wb_cached_rdata )
);
// ======================================
// Write back stage with data cache
// ======================================
a25_write_back u_write_back (
.i_clk ( i_clk ),
.i_mem_stall ( mem_stall ),
.i_daddress ( execute_daddress ),
.i_daddress_valid ( execute_daddress_valid ),
.i_mem_read_data ( mem_read_data ),
.i_mem_read_data_valid ( mem_read_data_valid ),
.i_mem_load_rd ( mem_load_rd ),
.o_wb_read_data ( wb_read_data ),
.o_wb_read_data_valid ( wb_read_data_valid ),
.o_wb_load_rd ( wb_load_rd )
);
// ======================================
// Wishbone Master I/F
// ======================================
a25_wishbone u_wishbone (
// CPU Side
.i_clk ( i_clk ),
// Port 0 - dcache uncached
.i_port0_req ( dcache_wb_uncached_req ),
.o_port0_ack ( dcache_wb_uncached_ready ),
.i_port0_write ( dcache_wb_write ),
.i_port0_wdata ( dcache_wb_write_data ),
.i_port0_be ( dcache_wb_byte_enable ),
.i_port0_addr ( dcache_wb_address ),
.o_port0_rdata ( ),
// Port 1 - dcache cached
.i_port1_req ( dcache_wb_cached_req ),
.o_port1_ack ( dcache_wb_cached_ready ),
.i_port1_write ( dcache_wb_write ),
.i_port1_wdata ( dcache_wb_write_data ),
.i_port1_be ( dcache_wb_byte_enable ),
.i_port1_addr ( dcache_wb_address ),
.o_port1_rdata ( dcache_wb_cached_rdata ),
// Port 2 - instruction cache accesses, read only
.i_port2_req ( icache_wb_req ),
.o_port2_ack ( icache_wb_ready ),
.i_port2_write ( 1'd0 ),
.i_port2_wdata ( 128'd0 ),
.i_port2_be ( 16'd0 ),
.i_port2_addr ( icache_wb_address ),
.o_port2_rdata ( icache_wb_read_data ),
// Wishbone
.o_wb_adr ( o_wb_adr ),
.o_wb_sel ( o_wb_sel ),
.o_wb_we ( o_wb_we ),
.i_wb_dat ( i_wb_dat ),
.o_wb_dat ( o_wb_dat ),
.o_wb_cyc ( o_wb_cyc ),
.o_wb_stb ( o_wb_stb ),
.i_wb_ack ( i_wb_ack ),
.i_wb_err ( i_wb_err )
);
// ======================================
// Co-Processor #15
// ======================================
a25_coprocessor u_coprocessor (
.i_clk ( i_clk ),
.i_core_stall ( core_stall ),
.i_copro_opcode1 ( copro_opcode1 ),
.i_copro_opcode2 ( copro_opcode2 ),
.i_copro_crn ( copro_crn ),
.i_copro_crm ( copro_crm ),
.i_copro_num ( copro_num ),
.i_copro_operation ( copro_operation ),
.i_copro_write_data ( copro_write_data ),
.i_fault ( decode_fault ),
.i_fault_status ( decode_fault_status ),
.i_fault_address ( decode_fault_address ),
.o_copro_read_data ( copro_read_data ),
.o_cache_enable ( cache_enable ),
.o_cache_flush ( cache_flush ),
.o_cacheable_area ( cacheable_area )
);
endmodule
|
`timescale 1ns/1ns
module fsusb
(input c, // bus clock = 100 mhz
input c_48, // usb clock
input en, // enable input: otherwise it just sits in idle
inout vp,
inout vm,
input dont_respond, // for debugging poll-path stalls
output oe_n,
output [7:0] ep1_rxd,
output ep1_rxdv,
output pwr);
`include "usb_pids.v"
localparam ST_IDLE = 4'd0;
localparam ST_PWR_OFF = 4'd1;
localparam ST_PWR_ON = 4'd2;
localparam ST_DETECT = 4'd3;
localparam ST_RESET = 4'd4;
localparam ST_POST_RESET = 4'd5;
localparam ST_ENABLED = 4'd6;
localparam ST_SOF_START = 4'd7;
localparam ST_SOF_WAIT = 4'd8;
localparam ST_ENUM = 4'd9;
localparam ST_POLL = 4'ha;
localparam SW=4, CW=7;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c), .rst(~en), .en(1'b1), .d(next_state), .q(state));
wire cnt_rst;
wire cnt_en = 1'b1;
wire [31:0] cnt; // counter used by many states
r #(32) cnt_r(.c(c), .rst(cnt_rst), .en(cnt_en), .d(cnt + 1'b1), .q(cnt));
wire vp_i48, vm_i48, vp_i, vm_i;
sync vp_sync48(.in(vp), .clk(c_48), .out(vp_i48));
sync vm_sync48(.in(vm), .clk(c_48), .out(vm_i48));
sync vp_sync (.in(vp), .clk(c), .out(vp_i));
sync vm_sync (.in(vm), .clk(c), .out(vm_i));
`ifndef SIM
localparam PWR_OFF_CNT = 32'd050_000_000; // 0.5-second power-off delay
localparam PWR_ON_CNT = 32'd100_000_000; // 1-second power-on delay for BL
localparam RESET_CNT = 32'd002_000_000; // 20ms reset period
localparam POST_RESET_CNT = 32'd001_000_000; // 10ms reset-recovery period
`else
// these timeouts take forever to simulate. let's make it lots faster...
localparam PWR_OFF_CNT = 32'd125;
localparam PWR_ON_CNT = 32'd062;
localparam RESET_CNT = 32'd050;
localparam POST_RESET_CNT = 32'd080;
`endif
`ifndef SIM
localparam FRAME_TRAFFIC_START = 17'h200;
localparam FRAME_LENGTH = 17'd100_000; // every millisecond
localparam FRAME_END_QUIET = 17'd005_000; // don't clobber SOF
localparam NUM_WAKEUP_FRAMES = 11'd68; // sort of what linux does
`else
localparam FRAME_TRAFFIC_START = 17'h200;
localparam FRAME_LENGTH = 17'd010_000; // every 100 us, to speed up sim.
localparam FRAME_END_QUIET = 17'd001_000; // don't clobber SOF
localparam NUM_WAKEUP_FRAMES = 11'd2; // save time in simulation
`endif
wire [16:0] frame_time;
r #(17) frame_time_r
(.c(c), .rst(frame_time == FRAME_LENGTH), .en(1'b1),
.d(frame_time+1'b1), .q(frame_time));
wire sof = frame_time == 17'h0 & state >= ST_ENABLED;
wire sof_d1 = frame_time == 17'h1 & state >= ST_ENABLED;
wire [10:0] frame_number;
r #(11, 11'd0) frame_number_r
(.c(c), .en(sof), .rst(state == ST_RESET),
.d(frame_number+1'b1), .q(frame_number));
wire [18:0] sof_token = { frame_number, PID_SOF };
wire [18:0] enum_token, poll_token;
wire [1:0] token_sel;
wire [18:0] token_d;
gmux #(.DWIDTH(19), .SELWIDTH(2)) token_gmux
(.d({19'h0, poll_token, enum_token, sof_token}),
.sel(token_sel), .z(token_d));
wire tx_token_start;
wire [7:0] tx_token_sie_d;
wire tx_token_sie_dv;
usb_tx_token usb_tx_token_inst
(.c(c), .d(token_d), .start(tx_token_start),
.sie_d(tx_token_sie_d), .sie_dv(tx_token_sie_dv));
wire enum_en, enum_done;
wire [7:0] enum_data_d;
wire enum_data_dv, enum_token_start;
wire [7:0] tx_data_sie_d;
wire tx_data_sie_dv;
usb_tx_data usb_tx_data_inst
(.c(c),
.d(enum_data_d),
.dv(enum_data_dv),
.sie_d(tx_data_sie_d), .sie_dv(tx_data_sie_dv));
wire [7:0] tx_ack_sie_d;
wire tx_ack_sie_dv;
wire enum_ack_start, poll_ack_start;
usb_tx_ack usb_tx_ack_inst
(.c(c),
.start(enum_ack_start | poll_ack_start),
.sie_d(tx_ack_sie_d), .sie_dv(tx_ack_sie_dv));
wire reset_48;
sync reset_sync(.in(state == ST_RESET), .clk(c_48), .out(reset_48));
wire tx_sie_done;
usb_tx_sie tx_sie_inst
(.c(c), .c_48(c_48),
.d(tx_token_sie_d | tx_data_sie_d | tx_ack_sie_d ),
.dv(tx_token_sie_dv | tx_data_sie_dv | tx_ack_sie_dv),
.oe_n(oe_n), .done(tx_sie_done),
.vp(vp), .vm(vm),
.rst(reset_48));
wire [7:0] rx_sie_d;
wire rx_sie_dv;
usb_rx_sie rx_sie_inst
(.c(c), .c_48(c_48), .oe(~oe_n), .vp(vp_i48), .vm(vm_i48),
.d(rx_sie_d), .dv(rx_sie_dv));
/*
assign oe_n = state == ST_RESET ? 1'b0 : tx_sie_oe_n; // assert OE during reset
assign vp = state == ST_RESET ? 1'b0 : tx_sie_vp; // assert SE0 during reset
assign vm = state == ST_RESET ? 1'b0 : tx_sie_vm;
*/
usb_enum enum_inst
(.c(c), .rst(state == ST_RESET), .en(enum_en), .done(enum_done),
.token_d(enum_token), .token_start(enum_token_start),
.ack_start(enum_ack_start),
.data_d(enum_data_d), .data_dv(enum_data_dv),
.tx_sie_done(tx_sie_done),
.rxd(rx_sie_d), .rxdv(rx_sie_dv));
wire poll_start, poll_token_start;
wire [7:0] poll_rxd;
wire poll_rxdv;
usb_poll poll_inst
(.c(c), .start(poll_start), .ack_start(poll_ack_start),
.token_d(poll_token), .token_start(poll_token_start),
.payload_d(poll_rxd), .payload_dv(poll_rxdv),
.sie_rxd(rx_sie_d), .sie_rxdv(rx_sie_dv),
.dont_respond(dont_respond),
.tx_sie_done(tx_sie_done));
assign ep1_rxd = poll_rxd;
assign ep1_rxdv = poll_rxdv;
always @* begin
case (state)
ST_IDLE: ctrl = { ST_PWR_OFF , 2'b00, 5'b00001 };
ST_PWR_OFF:
if (cnt == PWR_OFF_CNT) ctrl = { ST_PWR_ON , 2'b00, 5'b00001 };
else ctrl = { ST_PWR_OFF , 2'b00, 5'b00000 };
ST_PWR_ON:
if (cnt == PWR_ON_CNT) ctrl = { ST_DETECT , 2'b00, 5'b00001 };
else ctrl = { ST_PWR_ON , 2'b00, 5'b00000 };
ST_DETECT: ctrl = { ST_RESET , 2'b00, 5'b00001 };
/*
ST_DETECT: // add timeout?
if (vp_i & ~vm_i) ctrl = { ST_RESET , 2'b00, 5'b00001 };
else ctrl = { ST_DETECT , 2'b00, 5'b00000 };
*/
ST_RESET:
if (cnt == RESET_CNT) ctrl = { ST_ENABLED , 2'b00, 5'b00001 };
else ctrl = { ST_RESET , 2'b00, 5'b00000 };
ST_ENABLED:
if (sof_d1) ctrl = { ST_SOF_START , 2'b00, 5'b00101 };
else ctrl = { ST_ENABLED , 2'b00, 5'b00000 };
ST_SOF_START: ctrl = { ST_SOF_WAIT , 2'b00, 5'b01000 };
ST_SOF_WAIT:
if (frame_time > FRAME_TRAFFIC_START)
if (enum_done) ctrl = { ST_POLL , 2'b00, 5'b00000 };
else if (frame_number < NUM_WAKEUP_FRAMES)
ctrl = { ST_ENABLED , 2'b00, 5'b00000 };
else ctrl = { ST_ENUM , 2'b00, 5'b00000 };
else ctrl = { ST_SOF_WAIT , 2'b00, 5'b00000 };
ST_ENUM:
if (frame_time > FRAME_LENGTH - FRAME_END_QUIET)
ctrl = { ST_ENABLED , 2'b01, 5'b00000 };
else ctrl = { ST_ENUM , 2'b01, 5'b00000 };
ST_POLL:
if (frame_time > FRAME_LENGTH - FRAME_END_QUIET)
ctrl = { ST_ENABLED , 2'b00, 5'b00000 };
else if (frame_time[12:0] == 11'h500) // todo: smarter regular schedule
ctrl = { ST_POLL , 2'b10, 5'b00010 };
else ctrl = { ST_POLL , 2'b10, 5'b00000 };
default: ctrl = { ST_IDLE , 2'b00, 5'b00000 };
endcase
end
// register the power signal to help timing
wire pwr_next = (state != ST_IDLE) & (state != ST_PWR_OFF);
wire pwr_d1, pwr_d2;
d1 pwr_d1_r(.c(c), .d(pwr_next), .q(pwr_d1));
d1 pwr_d2_r(.c(c), .d(pwr_d1), .q(pwr_d2));
d1 pwr_d3_r(.c(c), .d(pwr_d2), .q(pwr));
assign cnt_rst = ctrl[0];
assign tx_token_start = ctrl[2] | enum_token_start | poll_token_start;
assign token_sel = ctrl[6:5];
assign enum_en = state == ST_ENUM;
assign poll_start = ctrl[1];
endmodule
`ifdef TEST_FSUSB
module tb();
wire c, c_48;
sim_clk #(100) clk_100_inst(c);
sim_clk #( 48) clk_48_inst (c_48);
wire dp, dm, vp, vm, oe_n, pwr;
reg dont_respond;
sim_fsusb_phy sim_phy(.*);
sim_fsusb_encoder sim_enc(.*);
fsusb fsusb_inst
(.c(c), .c_48(c_48), .en(1'b1), .dont_respond(dont_respond),
.vp(vp), .vm(vm), .oe_n(oe_n), .pwr(pwr));
initial begin
$dumpfile("fsusb.lxt");
$dumpvars();
dont_respond = 1'b1;
#2_000_000;
//#10_400_000;
$finish();
end
endmodule
`endif
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Wrap_2pi_Once.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Wrap_2pi_Once
// Source Path: controllerHdl/Field_Oriented_Control/Open_Loop_Control/Generate_Position_And_Voltage_Ramp/Electrical_Velocity_To_Position/Wrap_2pi_Once
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Wrap_2pi_Once
(
x,
wrap
);
input signed [31:0] x; // sfix32_En27
output signed [31:0] wrap; // sfix32_En27
wire signed [31:0] Two_Pi1_out1; // sfix32_En27
wire Relational_Operator_relop1;
wire signed [31:0] Two_Pi3_out1; // sfix32_En27
wire Relational_Operator1_relop1;
wire signed [31:0] Two_Pi2_out1; // sfix32_En27
wire signed [31:0] Add2_out1; // sfix32_En27
wire signed [31:0] Switch1_out1; // sfix32_En27
wire signed [31:0] Two_Pi_out1; // sfix32_En27
wire signed [31:0] Add1_out1; // sfix32_En27
wire signed [31:0] Switch_out1; // sfix32_En27
// Wrap 2pi Once
// <S25>/Two Pi1
assign Two_Pi1_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Relational Operator
assign Relational_Operator_relop1 = (x >= Two_Pi1_out1 ? 1'b1 :
1'b0);
// <S25>/Two Pi3
assign Two_Pi3_out1 = 32'sb00000000000000000000000000000000;
// <S25>/Relational Operator1
assign Relational_Operator1_relop1 = (x < Two_Pi3_out1 ? 1'b1 :
1'b0);
// <S25>/Two Pi2
assign Two_Pi2_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Add2
assign Add2_out1 = x + Two_Pi2_out1;
// <S25>/Switch1
assign Switch1_out1 = (Relational_Operator1_relop1 == 1'b0 ? x :
Add2_out1);
// <S25>/Two Pi
assign Two_Pi_out1 = 32'sb00110010010000111111011010101001;
// <S25>/Add1
//
// <S25>/Position_Hi_Data_Type
assign Add1_out1 = x - Two_Pi_out1;
// <S25>/Switch
assign Switch_out1 = (Relational_Operator_relop1 == 1'b0 ? Switch1_out1 :
Add1_out1);
assign wrap = Switch_out1;
endmodule // controllerHdl_Wrap_2pi_Once
|
//*************************************************************************
// > ÎļþÃû: regfile_display.v
// > ÃèÊö £º¼Ä´æÆ÷¶ÑÏÔʾģ¿é£¬µ÷ÓÃFPGA°åÉϵÄIO½Ó¿ÚºÍ´¥ÃþÆÁ
// > ×÷Õß : LOONGSON
// > ÈÕÆÚ : 2016-04-14
//*************************************************************************
module regfile_display(
//ʱÖÓÓ븴λÐźÅ
input clk,
input resetn, //ºó׺"n"´ú±íµÍµçƽÓÐЧ
//²¦Â뿪¹Ø£¬ÓÃÓÚ²úÉúдʹÄܺÍÑ¡ÔñÊäÈëÊý
input wen,
input [1:0] input_sel,
//ledµÆ£¬ÓÃÓÚָʾдʹÄÜÐźţ¬ºÍÕýÔÚÊäÈëʲôÊý¾Ý
output led_wen,
output led_waddr, //ָʾÊäÈëдµØÖ·
output led_wdata, //ָʾÊäÈëдÊý¾Ý
output led_raddr1, //ָʾÊäÈë¶ÁµØÖ·1
output led_raddr2, //ָʾÊäÈë¶ÁµØÖ·2
//´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
output lcd_rst,
output lcd_cs,
output lcd_rs,
output lcd_wr,
output lcd_rd,
inout[15:0] lcd_data_io,
output lcd_bl_ctr,
inout ct_int,
inout ct_sda,
output ct_scl,
output ct_rstn
);
//-----{LEDÏÔʾ}begin
assign led_wen = wen;
assign led_raddr1 = (input_sel==2'd0);
assign led_raddr2 = (input_sel==2'd1);
assign led_waddr = (input_sel==2'd2);
assign led_wdata = (input_sel==2'd3);
//-----{LEDÏÔʾ}end
//-----{µ÷ÓüĴæÆ÷¶ÑÄ£¿é}begin
//¼Ä´æÆ÷¶Ñ¶àÔö¼ÓÒ»¸ö¶Á¶Ë¿Ú£¬ÓÃÓÚÔÚ´¥ÃþÆÁÉÏÏÔʾ32¸ö¼Ä´æÆ÷Öµ
wire [31:0] test_data;
wire [4 :0] test_addr;
reg [4 :0] raddr1;
reg [4 :0] raddr2;
reg [4 :0] waddr;
reg [31:0] wdata;
wire [31:0] rdata1;
wire [31:0] rdata2;
regfile rf_module(
.clk (clk ),
.wen (wen ),
.raddr1(raddr1),
.raddr2(raddr2),
.waddr (waddr ),
.wdata (wdata ),
.rdata1(rdata1),
.rdata2(rdata2),
.test_addr(test_addr),
.test_data(test_data)
);
//-----{µ÷ÓüĴæÆ÷¶ÑÄ£¿é}end
//---------------------{µ÷Óô¥ÃþÆÁÄ£¿é}begin--------------------//
//-----{ʵÀý»¯´¥ÃþÆÁ}begin
//´ËС½Ú²»ÐèÒª¸ü¸Ä
reg display_valid;
reg [39:0] display_name;
reg [31:0] display_value;
wire [5 :0] display_number;
wire input_valid;
wire [31:0] input_value;
lcd_module lcd_module(
.clk (clk ), //10Mhz
.resetn (resetn ),
//µ÷Óô¥ÃþÆÁµÄ½Ó¿Ú
.display_valid (display_valid ),
.display_name (display_name ),
.display_value (display_value ),
.display_number (display_number),
.input_valid (input_valid ),
.input_value (input_value ),
//lcd´¥ÃþÆÁÏà¹Ø½Ó¿Ú£¬²»ÐèÒª¸ü¸Ä
.lcd_rst (lcd_rst ),
.lcd_cs (lcd_cs ),
.lcd_rs (lcd_rs ),
.lcd_wr (lcd_wr ),
.lcd_rd (lcd_rd ),
.lcd_data_io (lcd_data_io ),
.lcd_bl_ctr (lcd_bl_ctr ),
.ct_int (ct_int ),
.ct_sda (ct_sda ),
.ct_scl (ct_scl ),
.ct_rstn (ct_rstn )
);
//-----{ʵÀý»¯´¥ÃþÆÁ}end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}begin
//¸ù¾Ýʵ¼ÊÐèÒªÊäÈëµÄÊýÐ޸ĴËС½Ú£¬
//½¨Òé¶Ôÿһ¸öÊýµÄÊäÈ룬±àдµ¥¶ÀÒ»¸öalways¿é
//32¸ö¼Ä´æÆ÷ÏÔʾÔÚ7~38ºÅµÄÏÔʾ¿é£¬¹Ê¶ÁµØַΪ£¨display_number-1£©
assign test_addr = display_number-5'd7;
//µ±input_selΪ2'b00ʱ£¬±íʾÊäÈëÊýΪ¶ÁµØÖ·1£¬¼´raddr1
always @(posedge clk)
begin
if (!resetn)
begin
raddr1 <= 5'd0;
end
else if (input_valid && input_sel==2'd0)
begin
raddr1 <= input_value[4:0];
end
end
//µ±input_selΪ2'b01ʱ£¬±íʾÊäÈëÊýΪ¶ÁµØÖ·2£¬¼´raddr2
always @(posedge clk)
begin
if (!resetn)
begin
raddr2 <= 5'd0;
end
else if (input_valid && input_sel==2'd1)
begin
raddr2 <= input_value[4:0];
end
end
//µ±input_selΪ2'b10ʱ£¬±íʾÊäÈëÊýΪдµØÖ·£¬¼´waddr
always @(posedge clk)
begin
if (!resetn)
begin
waddr <= 5'd0;
end
else if (input_valid && input_sel==2'd2)
begin
waddr <= input_value[4:0];
end
end
//µ±input_selΪ2'b11ʱ£¬±íʾÊäÈëÊýΪдÊý¾Ý£¬¼´wdata
always @(posedge clk)
begin
if (!resetn)
begin
wdata <= 32'd0;
end
else if (input_valid && input_sel==2'd3)
begin
wdata <= input_value;
end
end
//-----{´Ó´¥ÃþÆÁ»ñÈ¡ÊäÈë}end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}begin
//¸ù¾ÝÐèÒªÏÔʾµÄÊýÐ޸ĴËС½Ú£¬
//´¥ÃþÆÁÉϹ²ÓÐ44¿éÏÔʾÇøÓò£¬¿ÉÏÔʾ44×é32λÊý¾Ý
//44¿éÏÔʾÇøÓò´Ó1¿ªÊ¼±àºÅ£¬±àºÅΪ1~44£¬
always @(posedge clk)
begin
if (display_number >6'd6 && display_number <6'd39 )
begin //¿éºÅ7~38ÏÔʾ32¸öͨÓüĴæÆ÷µÄÖµ
display_valid <= 1'b1;
display_name[39:16] <= "REG";
display_name[15: 8] <= {4'b0011,3'b000,test_addr[4]};
display_name[7 : 0] <= {4'b0011,test_addr[3:0]};
display_value <= test_data;
end
else
begin
case(display_number)
6'd1 : //ÏÔʾ¶Á¶Ë¿Ú1µÄµØÖ·
begin
display_valid <= 1'b1;
display_name <= "RADD1";
display_value <= raddr1;
end
6'd2 : //ÏÔʾ¶Á¶Ë¿Ú1¶Á³öµÄÊý¾Ý
begin
display_valid <= 1'b1;
display_name <= "RDAT1";
display_value <= rdata1;
end
6'd3 : //ÏÔʾ¶Á¶Ë¿Ú2µÄµØÖ·
begin
display_valid <= 1'b1;
display_name <= "RADD2";
display_value <= raddr2;
end
6'd4 : //ÏÔʾ¶Á¶Ë¿Ú2¶Á³öµÄÊý¾Ý
begin
display_valid <= 1'b1;
display_name <= "RDAT2";
display_value <= rdata2;
end
6'd5 : //ÏÔʾд¶Ë¿ÚµÄµØÖ·
begin
display_valid <= 1'b1;
display_name <= "WADDR";
display_value <= waddr;
end
6'd6 : //ÏÔʾд¶Ë¿ÚдÈëµÄÊý¾Ý
begin
display_valid <= 1'b1;
display_name <= "WDATA";
display_value <= wdata;
end
default :
begin
display_valid <= 1'b0;
display_name <= 40'd0;
display_value <= 32'd0;
end
endcase
end
end
//-----{Êä³öµ½´¥ÃþÆÁÏÔʾ}end
//----------------------{µ÷Óô¥ÃþÆÁÄ£¿é}end---------------------//
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eac_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eac_e.v,v 1.1 2006/04/10 15:42:08 wig Exp $
// $Date: 2006/04/10 15:42:08 $
// $Log: inst_eac_e.v,v $
// Revision 1.1 2006/04/10 15:42:08 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_eac_e
//
// No user `defines in this module
module inst_eac_e
//
// Generated module inst_eac
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eac_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_3_bhv_ver_as
* |
* +-fifo_generator_v13_1_3_bhv_ver_ss
* |
* +-fifo_generator_v13_1_3_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
wire wr_rst_busy_o;
wire wr_rst_busy_ntve;
wire wr_rst_busy_axis;
wire wr_rst_busy_wach;
wire wr_rst_busy_wdch;
wire wr_rst_busy_wrch;
wire wr_rst_busy_rach;
wire wr_rst_busy_rdch;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
// assign wr_rst_busy = WR_RST_BUSY | wr_rst_busy_o;
assign wr_rst_busy = wr_rst_busy_o;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_3_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_3_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy_o (wr_rst_busy_o),
.wr_rst_busy (wr_rst_busy_i),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
reg [3:0] axi_rst = 4'h0 ;
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
axi_rst <= 4'hf;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
axi_rst <= #`TCQ {axi_rst[2:0],1'b0};
end
end
assign axi_rs_rst = axi_rst[3];//rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 : 0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_3_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 : 0),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_3_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_3_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_3
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_3_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy_o,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
wire rst_asreg_d1;
wire rst_asreg_d2;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
reg [2:0] sckt_ff0_bsy_o_i = {3{1'b0}};
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire fifo_empty_fb;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire safety_ckt_wr_rst;
wire safety_ckt_rd_rst;
reg sckt_wr_rst_i_q = 1'b0;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
assign wr_rst_busy_o = wr_rst_busy | rst_full_gen_i | sckt_ff0_bsy_o_i[2];
generate if (C_FULL_FLAGS_RST_VAL == 0 && C_EN_SAFETY_CKT == 1) begin : gsckt_bsy_o
wire clk_i = C_COMMON_CLOCK ? CLK : WR_CLK;
always @ (posedge clk_i)
sckt_ff0_bsy_o_i <= {sckt_ff0_bsy_o_i[1:0],wr_rst_busy};
end endgenerate
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_3_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_3_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_3_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.SAFETY_CKT_WR_RST (safety_ckt_wr_rst),
.SAFETY_CKT_RD_RST (safety_ckt_rd_rst),
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.EMPTY_FB (fifo_empty_fb),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = C_EN_SAFETY_CKT ? fifo_empty_fb : EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= 1;
ALMOSTEMPTY_P0_OUT_Q <= 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_3_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.SAFETY_CKT_RD_RST(safety_ckt_rd_rst),
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? rst_delayed : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
localparam RST_SYNC_STAGES = (C_EN_SAFETY_CKT == 0) ? C_SYNCHRONIZER_STAGE :
(C_COMMON_CLOCK == 1) ? 3 : C_SYNCHRONIZER_STAGE+2;
reg [RST_SYNC_STAGES-1:0] wrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_reg = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] arst_sync_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_q = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] rrst_wr = {RST_SYNC_STAGES{1'b0}};
reg [RST_SYNC_STAGES-1:0] wrst_ext = {RST_SYNC_STAGES{1'b0}};
reg [1:0] wrst_cc = {2{1'b0}};
reg [1:0] rrst_cc = {2{1'b0}};
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
reg safety_ckt_wr_rst_i = 1'b0;
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? wr_rst_delayed : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rd_rst_delayed : 1'b0;
// end : gnrst_sync
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
reg fifo_wrst_done = 1'b0;
reg fifo_rrst_done = 1'b0;
reg sckt_wrst_i = 1'b0;
reg sckt_wrst_i_q = 1'b0;
reg rd_rst_active = 1'b0;
reg rd_rst_middle = 1'b0;
reg sckt_rd_rst_d1 = 1'b0;
reg [1:0] rst_delayed_ic_w = 2'h0;
wire rst_delayed_ic_w_i;
reg [1:0] rst_delayed_ic_r = 2'h0;
wire rst_delayed_ic_r_i;
wire arst_sync_rst;
wire fifo_rst_done;
wire fifo_rst_active;
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = C_EN_SAFETY_CKT ? (!rd_rst_asreg_d2 && rd_rst_asreg) || rd_rst_active : !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed_ic_w_i;
assign arst_sync_rst = arst_sync_q[RST_SYNC_STAGES-1];
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | fifo_rst_active : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? safety_ckt_rd_rst : 1'b0;
assign fifo_rst_done = fifo_wrst_done & fifo_rrst_done;
assign fifo_rst_active = sckt_wrst_i | wrst_ext[RST_SYNC_STAGES-1] | rrst_wr[RST_SYNC_STAGES-1];
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_w <= 2'b11;
else
rst_delayed_ic_w <= #`TCQ {rst_delayed_ic_w[0],1'b0};
end
assign rst_delayed_ic_w_i = rst_delayed_ic_w[1];
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1 && C_HAS_RST)
rst_delayed_ic_r <= 2'b11;
else
rst_delayed_ic_r <= #`TCQ {rst_delayed_ic_r[0],1'b0};
end
assign rst_delayed_ic_r_i = rst_delayed_ic_r[1];
always @(posedge WR_CLK) begin
sckt_wrst_i_q <= #`TCQ sckt_wrst_i;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ sckt_wrst_i | wr_rst_busy | sckt_wr_rst_i_q;
if (arst_sync_rst && ~fifo_rst_active)
sckt_wrst_i <= #`TCQ 1'b1;
else if (sckt_wrst_i && fifo_rst_done)
sckt_wrst_i <= #`TCQ 1'b0;
else
sckt_wrst_i <= #`TCQ sckt_wrst_i;
if (rrst_wr[RST_SYNC_STAGES-2] & ~rrst_wr[RST_SYNC_STAGES-1])
fifo_rrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_rrst_done <= #`TCQ 1'b0;
else
fifo_rrst_done <= #`TCQ fifo_rrst_done;
if (wrst_ext[RST_SYNC_STAGES-2] & ~wrst_ext[RST_SYNC_STAGES-1])
fifo_wrst_done <= #`TCQ 1'b1;
else if (fifo_rst_done)
fifo_wrst_done <= #`TCQ 1'b0;
else
fifo_wrst_done <= #`TCQ fifo_wrst_done;
end
always @(posedge WR_CLK or posedge rst_delayed_ic_w_i) begin
if (rst_delayed_ic_w_i == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],wr_rst_asreg};
wrst_ext <= #`TCQ {wrst_ext[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_wr <= #`TCQ {rrst_wr[RST_SYNC_STAGES-2:0],safety_ckt_rd_rst};
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_ic_w_i};
end
assign wr_rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign wr_rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed_ic_r_i) begin
if (rst_delayed_ic_r_i == 1'b1) begin
rd_rst_asreg <= 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rrst_reg <= #`TCQ {rrst_reg[RST_SYNC_STAGES-2:0],rd_rst_asreg};
rrst_q <= #`TCQ {rrst_q[RST_SYNC_STAGES-2:0],sckt_wrst_i};
rrst_cc <= #`TCQ {rrst_cc[0],rd_rst_asreg_d2};
sckt_rd_rst_d1 <= #`TCQ safety_ckt_rd_rst;
if (!rd_rst_middle && rrst_reg[1] && !rrst_reg[2]) begin
rd_rst_active <= #`TCQ 1'b1;
rd_rst_middle <= #`TCQ 1'b1;
end else if (safety_ckt_rd_rst)
rd_rst_active <= #`TCQ 1'b0;
else if (sckt_rd_rst_d1 && !safety_ckt_rd_rst)
rd_rst_middle <= #`TCQ 1'b0;
end
assign rd_rst_asreg_d1 = rrst_reg[RST_SYNC_STAGES-2];
assign rd_rst_asreg_d2 = C_EN_SAFETY_CKT ? rrst_reg[RST_SYNC_STAGES-1] : rrst_reg[1];
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rrst_q[2] : 1'b0;
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_ic_rst
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
reg [1:0] rst_delayed_cc = 2'h0;
wire rst_delayed_cc_i;
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed_cc_i;
assign wr_rst_busy = C_EN_SAFETY_CKT ? |arst_sync_q[RST_SYNC_STAGES-1:1] | wrst_cc[1] : 1'b0;
assign rd_rst_busy = C_EN_SAFETY_CKT ? arst_sync_q[1] | arst_sync_q[RST_SYNC_STAGES-1] | wrst_cc[1] : 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1)
rst_delayed_cc <= 2'b11;
else
rst_delayed_cc <= #`TCQ {rst_delayed_cc,1'b0};
end
assign rst_delayed_cc_i = rst_delayed_cc[1];
always @(posedge CLK or posedge rst_delayed_cc_i) begin
if (rst_delayed_cc_i == 1'b1) begin
rst_asreg <= 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
wrst_reg <= #`TCQ {wrst_reg[RST_SYNC_STAGES-2:0],rst_asreg};
wrst_cc <= #`TCQ {wrst_cc[0],arst_sync_q[RST_SYNC_STAGES-1]};
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
safety_ckt_wr_rst_i <= #`TCQ wrst_cc[1] | wr_rst_busy | sckt_wr_rst_i_q;
arst_sync_q <= #`TCQ {arst_sync_q[RST_SYNC_STAGES-2:0],rst_delayed_cc_i};
end
assign rst_asreg_d1 = wrst_reg[RST_SYNC_STAGES-2];
assign rst_asreg_d2 = C_EN_SAFETY_CKT ? wrst_reg[RST_SYNC_STAGES-1] : wrst_reg[1];
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? safety_ckt_wr_rst_i : 1'b0;
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
// end : g7s_cc_rst
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
assign safety_ckt_wr_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
assign safety_ckt_rd_rst = C_EN_SAFETY_CKT ? rst_reg | wr_rst_busy | sckt_wr_rst_i_q : 1'b0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
sckt_wr_rst_i_q <= #`TCQ wr_rst_busy;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
// end : g8s_cc_rst
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
assign safety_ckt_wr_rst = 1'b0;
assign safety_ckt_rd_rst = 1'b0;
end
endgenerate
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ wr_rst_busy;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2 | safety_ckt_wr_rst;
rst_d4 <= #`TCQ rst_d3;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
always @* rst_full_gen_i <= rst_d3;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
endmodule //fifo_generator_v13_1_3_conv_ver
module fifo_generator_v13_1_3_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_3_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input SAFETY_CKT_WR_RST,
input SAFETY_CKT_RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg EMPTY_FB = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= 1'b1;
ALMOST_EMPTY <= 1'b1;
rd_data_count_int <= {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (SAFETY_CKT_RD_RST && C_EN_SAFETY_CKT)
EMPTY_FB <= #`TCQ 1'b1;
else if (empty_int)
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ 1'b0;
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= 0;
stage2_valid <= 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK) begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else begin
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_d2 <= 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_3_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_wp
if (wr_rst_i == 1'b1 && C_EN_SAFETY_CKT == 0)
wr_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_WR_RST == 1'b1)
wr_pntr <= #`TCQ 0;
end
always @(posedge WR_CLK or posedge wr_rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= 0;
next_num_wr_bits = 0;
wr_ptr <= C_WR_DEPTH - 1;
rd_ptr_wrclk <= C_RD_DEPTH - 1;
ideal_wr_ack <= 0;
ideal_wr_count <= 0;
tmp_wr_listsize = 0;
rd_ptr_wrclk_next <= 0;
wr_pntr_rd1 <= 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= 0;
ideal_prog_empty <= 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_rp
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
rd_pntr <= 0;
else if (C_EN_SAFETY_CKT == 1 && SAFETY_CKT_RD_RST == 1'b1)
rd_pntr <= #`TCQ 0;
end
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_fifo_r_as
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i) begin
num_rd_bits <= 0;
next_num_rd_bits = 0;
rd_ptr <= C_RD_DEPTH -1;
rd_pntr_wr1 <= 0;
wr_ptr_rdclk <= C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= 1'b0;
ideal_rd_count <= 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always gen_fifo_r_as
endmodule // fifo_generator_v13_1_3_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_3_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_3_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input SAFETY_CKT_WR_RST,
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output reg EMPTY_FB = 1'b1,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
err_type_d1 = 0;
err_type_both = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK) begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK) begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_WR_RST : C_HAS_SRST ? (SRST | WR_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
assign srst_wrst_busy = srst_i;
assign srst_rrst_busy = srst_i;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= 1'b0;
valid_both <= 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i) begin
wr_pntr <= #`TCQ 0;
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1) begin
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= 0;
err_type_both <= 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type <= #`TCQ 0;
err_type_d1 <= #`TCQ 0;
err_type_both <= #`TCQ 0;
end
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
always @(posedge CLK or posedge rst_i) begin
if (rst_i && C_EN_SAFETY_CKT == 0) begin
EMPTY_FB <= 1'b1;
end else begin
if (srst_rrst_busy || (SAFETY_CKT_WR_RST && C_EN_SAFETY_CKT))
EMPTY_FB <= #`TCQ 1'b1;
else
EMPTY_FB <= #`TCQ ram_empty_comb;
end
end // always
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_3_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_3_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input SAFETY_CKT_RD_RST,
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output USERVALID,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_sckt = 1'b1;
reg sckt_rrst_q = 1'b0;
reg sckt_rrst_done = 1'b0;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
reg [C_DOUT_WIDTH-1:0] userdata_both;
wire uservalid_both;
wire uservalid_one;
reg user_sbiterr_both = 1'b0;
reg user_dbiterr_both = 1'b0;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
userdata_both = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
user_sbiterr_both = 1'b0;
user_dbiterr_both = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_EN_SAFETY_CKT ? SAFETY_CKT_RD_RST : C_HAS_SRST ? SRST : 0;
reg sckt_rd_rst_fwft = 1'b0;
reg fwft_rst_done_i = 1'b0;
wire fwft_rst_done;
assign fwft_rst_done = C_EN_SAFETY_CKT ? fwft_rst_done_i : 1'b1;
always @ (posedge RD_CLK) begin
sckt_rd_rst_fwft <= #`TCQ SAFETY_CKT_RD_RST;
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
fwft_rst_done_i <= 1'b0;
else if (sckt_rd_rst_fwft & ~SAFETY_CKT_RD_RST)
fwft_rst_done_i <= #`TCQ 1'b1;
end
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
ram_valid_i <= #`TCQ next_state;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0) begin
curr_state <= 1'b0;
end else if (srst_i) begin
curr_state <= #`TCQ 1'b0;
end else begin
curr_state <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i && C_EN_SAFETY_CKT == 0)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_sckt <= #`TCQ 1'b1;
sckt_rrst_q <= #`TCQ 1'b0;
sckt_rrst_done <= #`TCQ 1'b0;
end else begin
sckt_rrst_q <= #`TCQ SAFETY_CKT_RD_RST;
if (sckt_rrst_q && ~SAFETY_CKT_RD_RST) begin
sckt_rrst_done <= #`TCQ 1'b1;
end else if (sckt_rrst_done) begin
// rising clock edge
empty_sckt <= #`TCQ 1'b0;
end
end
end //always
// assign USEREMPTY = C_EN_SAFETY_CKT ? (sckt_rrst_done ? empty_i : empty_sckt) : empty_i;
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign uservalid_both = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign uservalid_one = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? uservalid_both : uservalid_one;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin
if (fwft_rst_done) begin
if (ram_regout_en) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK) begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK) begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
userdata_both <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
user_sbiterr_both <= #`TCQ 0;
user_dbiterr_both <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else if (fwft_rst_done) begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
userdata_both <= #`TCQ FIFODATA;
user_dbiterr_both <= #`TCQ FIFODBITERR;
user_sbiterr_both <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ userdata_both;
USERDBITERR <= #`TCQ user_dbiterr_both;
USERSBITERR <= #`TCQ user_sbiterr_both;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_3_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_3_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_cmd_fifo # (
parameter P_FIFO_DATA_WIDTH = 34,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 1; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// -*- Mode: Verilog -*-
// Filename : uart_tasks.v
// Description : UART Tasks
// Author : Philip Tracton
// Created On : Mon Apr 20 16:12:43 2015
// Last Modified By: Philip Tracton
// Last Modified On: Mon Apr 20 16:12:43 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
`include "includes.v"
module uart_tasks;
// Configure WB UART in testbench
// 115200, 8N1
//
task uart_config;
begin
$display("\033[93mTASK: UART Configure\033[0m");
@(posedge `UART_CLK);
//Turn on receive data interrupt
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00010000);
@(posedge `UART_CLK);
//FIFO Control, interrupt for each byte, clear fifos and enable
`UART_MASTER0.wb_wr1(32'hFFFF0002, 4'h2, 32'h00000700);
@(posedge `UART_CLK);
//Line Control, enable writting to the baud rate registers
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000080);
@(posedge `UART_CLK);
//Baud Rate LSB
//`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h0000001A); //115200bps from 50 MHz
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, 32'h00000035); //115200bps from 100 MHz
@(posedge `UART_CLK);
//Baud Rate MSB
`UART_MASTER0.wb_wr1(32'hFFFF0001, 4'h4, 32'h00000000);
@(posedge `UART_CLK);
//Line Control, 8 bits data, 1 stop bit, no parity
`UART_MASTER0.wb_wr1(32'hFFFF0003, 4'h1, 32'h00000003);
end
endtask // uart_config
//
// Write a character to WB UART and catch with FPGA UART
//
task uart_write_char;
input [7:0] char;
begin
//
// Write the character to the WB UART to send to FPGA UART
//
@(posedge `UART_CLK);
$display("TASK: UART Write = %c @ %d", char, $time);
`UART_MASTER0.wb_wr1(32'hFFFF0000, 4'h0, {24'h000000, char});
end
endtask // uart_write_char
//
// Read a character with WB UART that was sent from FPGA UART
//
task uart_read_char;
input [7:0] expected;
begin
$display("Reading 0x%x @ %d", expected, $time);
if (!testbench.uart0_int)
@(posedge testbench.uart0_int);
`UART_MASTER0.wb_rd1(32'hFFFF0000, 4'h0, testbench.read_word);
$display("TASK: UART Read = %c @ %d", testbench.read_word, $time);
if (testbench.read_word != expected)
begin
$display("\033[1;31mFAIL: UART Read = 0x%h NOT 0x%h @ %d\033[0m", testbench.read_word[7:0], expected, $time);
`TEST_FAILED <= 1;
end
@(posedge testbench.CLK_IN);
end
endtask // uart_read_char
endmodule // uart_tasks
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:49 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_low_1/bg_low_sim_netlist.v
// Design : bg_low
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bg_low,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bg_low
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [10:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [10:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [10:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "11" *)
(* C_ADDRB_WIDTH = "11" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5912999999999999 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bg_low.mem" *)
(* C_INIT_FILE_NAME = "bg_low.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1092" *)
(* C_READ_DEPTH_B = "1092" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1092" *)
(* C_WRITE_DEPTH_B = "1092" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
bg_low_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[10:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[10:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bg_low_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_low_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_low_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:16]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED ;
wire [3:2]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(1),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h1C001C001C001C0024001C001C001C001C001C001C001C001C001C001C001C00),
.INIT_01(256'h1D041D041D041D041D041D041C001C0024001C001C001C001C001C001C001C00),
.INIT_02(256'h1D041D041D041D041D041D041D041D041D041D041D041D041D041D041D041D04),
.INIT_03(256'h2C001D041D0434001D041D0434001D041D0434001D041D041D041D041D041D04),
.INIT_04(256'h353735371D041D042C001D041D0434001D041D0434001D041D0434001D041D04),
.INIT_05(256'h3E0835373E083E0835373537353735373E083E0835373E083E0835373E083E08),
.INIT_06(256'h1D373E081D373E081D371D371D373E0835373537353735373E083E0835373E08),
.INIT_07(256'h35373E081D371D371D373E081D373E081D371D371D373E0835373E081D371D37),
.INIT_08(256'h35371D373E081D37353735373537261935373E081D37353735371D371D373E08),
.INIT_09(256'h353700002619353735371D373E081D37353735373537261935373E081D373537),
.INIT_0A(256'h1D371D3735373537353700002619353704011D3735371D371D371D3735373537),
.INIT_0B(256'h2619261926193E0826192619261926193E0826192619353704011D3735371D37),
.INIT_0C(256'h3E08261926193E082619261926193E0826192619261926193E08261926193E08),
.INIT_0D(256'h3E083E0826192E3B3E0826192E3B3E0826193E082E3B26193E083E0826192E3B),
.INIT_0E(256'h2E3B2E3B2E3B2E3B2E3B2E3B26192E3B3E0826192E3B3E0826193E082E3B2619),
.INIT_0F(256'h2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B),
.INIT_10(256'h2E3B2E3B3F382E3B0C002E3B2E3B2E3B2E3B2E3B2E3B04002E3B2E3B2E3B2E3B),
.INIT_11(256'h3F382E3B2E3B04002E3B2E3B3F382E3B0C002E3B2E3B2E3B2E3B2E3B2E3B0400),
.INIT_12(256'h3E0804002E3B2E3B3F382E3B2E3B3E08371D2E3B2E3B2E3B3E0804002E3B2E3B),
.INIT_13(256'h2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F382E3B2E3B3E08371D2E3B2E3B2E3B),
.INIT_14(256'h2E3B2E3B3F383E082E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F383E08),
.INIT_15(256'h3F3F3F3F3F3F040026192619261926192619261926192619261926192E3B2E3B),
.INIT_16(256'h371D0400371D371D3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_17(256'h2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B2E3B3F3F3F3F0400371D371D371D371D),
.INIT_18(256'h3F3F3F3F371D3F38371D371D371D371D371D371D2E3B2E3B2E3B2E3B2E3B2E3B),
.INIT_19(256'h371D371D371D0400371D371D371D371D371D371D371D371D371D371D371D0000),
.INIT_1A(256'h371D371D371D371D371D371D00003F3F00003F3800003F3800003F383F381400),
.INIT_1B(256'h3F383F383F383F383F383F38371D371D371D371D371D371D371D371D371D371D),
.INIT_1C(256'h3E083E083F383F383F383E083F383E083F383F383F383F383F3800003F3F0001),
.INIT_1D(256'h3E083F383F383F3800003F3F3F3F3F383F383F383F383F383F383F383F383E08),
.INIT_1E(256'h3E083F383F383F383E083F383F383E083E083F383F383F383F383F383F383F38),
.INIT_1F(256'h3E0800013E083E083F383F383E083F383F383E083F3800003F3F00013F380001),
.INIT_20(256'h3F383F3800003F3F00013F303F383F383F383F383E083F383E083F383F383E08),
.INIT_21(256'h3F383F3F3F383F383F3F3F383F383F383F383F383F3F3F383F383F383F3F3F38),
.INIT_22(256'h3F383F383F303E083F303F383F383E083F383F3F3F3F000114003F383F3F3F38),
.INIT_23(256'h00003F3F00003F383F383F383F303E083F303F383F303F383F383E083F383F38),
.INIT_24(256'h3F383F383F303F303F383F303F303F383F303F303F303F383F303F383F303F38),
.INIT_25(256'h000100000001000000000000000000003F3F00003F303F383F303F303F383F38),
.INIT_26(256'h0001000000000000000000000000000000000000000000000001000000000000),
.INIT_27(256'h3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_28(256'h3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_29(256'h3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F),
.INIT_2A(256'h3E083F3F3E083F383E083F383F383F383E083F3F3F3F3F383F3F3F3F3F3F3F3F),
.INIT_2B(256'h3F3F3F383F3F3F383E083F3F3E083F383E083F383F383F383E083F3F3F3F3F38),
.INIT_2C(256'h3F383F383F383F383F3F3F383F383F383F383F383F3F3F383F383F383F383F38),
.INIT_2D(256'h3F383F3F3F383F383F3F3F383E083F383F3F3F383F383F383F383F383F3F3F38),
.INIT_2E(256'h3F383F383F383F383F383F3F3F383F383F3F3F383E083F383F383F383F383F38),
.INIT_2F(256'h3F3F3F383F383F383F383F3F3F383F3F3F383E083F3814003F3F3F383E083F38),
.INIT_30(256'h3E083F3F3E083F383F3F3F383F383F383F383F3F3F383F3F3F383E083F381400),
.INIT_31(256'h3F3F3F383F383F383E083F3F3E083F383E083F383F383F383F3F3F383F383F38),
.INIT_32(256'h3F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3E083F383E083F383F383F38),
.INIT_33(256'h3F383F3F3F383E083F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3F383E08),
.INIT_34(256'h3F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F3F383F383F3F1400),
.INIT_35(256'h3E083F3F3F383F383F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F),
.INIT_36(256'h3E083F383F383F383E083F3F3F383F383F383F383F3F3F383E083F383F383F38),
.INIT_37(256'h3F383F3F3F3F3F383F3F3F383F383F383F383F3F3F383F3F3F383F383F3F3F38),
.INIT_38(256'h3F383F3F3F3F3F3F3F383F3F3F3F3F3F3F3F3F383F383F3F3F383F3F3F3F3F3F),
.INIT_39(256'h3F383F3F000D3F383F38000D3F383F3F3F3F3F3F3F3F3F3F3F383F3F3F3F3F38),
.INIT_3A(256'h3F3F3F3F3F3F3F3F3F3F3F383F3F3F383F38000D3F383F3F3F3F3F3F3F3F3F3F),
.INIT_3B(256'h3E083F3F3F38000D371D3F3F3F3F3F3F3F3F1D373F3F3F383E083E083F383F3F),
.INIT_3C(256'h3F383F3F3F383F383F3F3F3F3F3F3F3F3F383F3F000D3F383F38000D3F3F3F38),
.INIT_3D(256'h3F3F3E083F383F3F3F383F3F3F383F38233F3F3F3F3F000D3F383F3F3F3F3F38),
.INIT_3E(256'h3F38233F3E083E08233F3E083F38233F3F383E08233F3F3F3F38000D3E083E08),
.INIT_3F(256'h3E08233F3E083F38233F3F383E08233F233F3F383F38233F3F383E08000D3F3F),
.INIT_40(256'h3F3F3F383F3F233F3E08233F371D3F38000D1D373E08000D3F3F3F383F3F3F3F),
.INIT_41(256'h233F3F383F3F371D3F383F38000D3F383F3F233F3F383F38233F3F383F3F233F),
.INIT_42(256'h000D1D373F3F000D3E083F383F3F371D3F383F38000D3F383F3F233F3F383F38),
.INIT_43(256'h3F38233F3F383F3F3F3F220F220F233F233F3F38371D233F3F38233F371D3F3F),
.INIT_44(256'h000000000000000000000000000000000000000000000000233F3F38371D233F),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,addra,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[11:6],1'b0,1'b0,dina[5:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:16],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38 ,douta[11:6],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46 ,douta[5:0]}),
.DOBDO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED [31:0]),
.DOPADOP({\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88 }),
.DOPBDOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED [3:0]),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b1),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({wea,wea,wea,wea}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bg_low_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "11" *) (* C_ADDRB_WIDTH = "11" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "0" *)
(* C_COUNT_36K_BRAM = "1" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.5912999999999999 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bg_low.mem" *)
(* C_INIT_FILE_NAME = "bg_low.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "1092" *) (* C_READ_DEPTH_B = "1092" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "1092" *) (* C_WRITE_DEPTH_B = "1092" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bg_low_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [10:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [10:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [10:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [10:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[10] = \<const0> ;
assign rdaddrecc[9] = \<const0> ;
assign rdaddrecc[8] = \<const0> ;
assign rdaddrecc[7] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[10] = \<const0> ;
assign s_axi_rdaddrecc[9] = \<const0> ;
assign s_axi_rdaddrecc[8] = \<const0> ;
assign s_axi_rdaddrecc[7] = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bg_low_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bg_low_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [10:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [10:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_low_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module simd_tb;
//wires
reg clk;
reg rst;
reg issue_alu_select, exec_rd_scc_value, rfa_queue_entry_serviced;
reg [5:0] issue_wfid;
reg [11:0] issue_source_reg1, issue_source_reg2, issue_source_reg3,
issue_dest_reg1, issue_dest_reg2;
reg [15:0] issue_imm_value0;
reg [31:0] issue_imm_value1, issue_opcode, sgpr_rd_data, exec_rd_m0_value,
issue_instr_pc;
reg [63:0] exec_rd_exec_value, exec_rd_vcc_value;
reg [2047:0] vgpr_source1_data, vgpr_source2_data, vgpr_source3_data;
wire vgpr_source1_rd_en, vgpr_source2_rd_en, vgpr_source3_rd_en, vgpr_wr_en,
exec_rd_en, exec_wr_vcc_en, sgpr_rd_en, sgpr_wr_en, issue_alu_ready,
vgpr_instr_done, rfa_queue_entry_valid;
wire [5:0] exec_rd_wfid, exec_wr_vcc_wfid, vgpr_instr_done_wfid;
wire [8:0] sgpr_rd_addr, sgpr_wr_addr;
wire [9:0] vgpr_source1_addr, vgpr_source2_addr, vgpr_source3_addr,
vgpr_dest_addr;
wire [31:0] tracemon_retire_pc;
wire [63:0] vgpr_wr_mask, exec_wr_vcc_value, sgpr_wr_data;
wire [2047:0] vgpr_dest_data;
//instantiation of dut
simd simd(
.issue_source_reg1(issue_source_reg1),
.issue_source_reg2(issue_source_reg2),
.issue_source_reg3(issue_source_reg3), //TODO implement this.
.issue_dest_reg1(issue_dest_reg1),
.issue_dest_reg2(issue_dest_reg2), //TODO implement this
.issue_imm_value0(issue_imm_value0),
.issue_imm_value1(issue_imm_value1),
.issue_opcode(issue_opcode),
.issue_wfid(issue_wfid),
.issue_alu_select(issue_alu_select),
.vgpr_source1_data(vgpr_source1_data),
.vgpr_source2_data(vgpr_source2_data),
.vgpr_source3_data(vgpr_source3_data), //TODO implement this
.sgpr_rd_data(sgpr_rd_data),
.exec_rd_exec_value(exec_rd_exec_value),
.exec_rd_vcc_value(exec_rd_vcc_value),
.exec_rd_m0_value(exec_rd_m0_value), //TODO implement this
.exec_rd_scc_value(exec_rd_scc_value),
.issue_instr_pc(issue_instr_pc),
.rfa_queue_entry_serviced(rfa_queue_entry_serviced),
.vgpr_source1_rd_en(vgpr_source1_rd_en),
.vgpr_source2_rd_en(vgpr_source2_rd_en),
.vgpr_source3_rd_en(vgpr_source3_rd_en), //TODO
.vgpr_source1_addr(vgpr_source1_addr),
.vgpr_source2_addr(vgpr_source2_addr),
.vgpr_source3_addr(vgpr_source3_addr), //TODO implement
.vgpr_dest_addr(vgpr_dest_addr),
.vgpr_dest_data(vgpr_dest_data),
.vgpr_wr_en(vgpr_wr_en),
.vgpr_wr_mask(vgpr_wr_mask),
.exec_rd_wfid(exec_rd_wfid),
.exec_rd_en(exec_rd_en),
.exec_wr_vcc_wfid(exec_wr_vcc_wfid),
.exec_wr_vcc_en(exec_wr_vcc_en),
.exec_wr_vcc_value(exec_wr_vcc_value),
.sgpr_rd_en(sgpr_rd_en),
.sgpr_rd_addr(sgpr_rd_addr),
.sgpr_wr_addr(sgpr_wr_addr), //TODO
.sgpr_wr_en(sgpr_wr_en), //TODO
.sgpr_wr_data(sgpr_wr_data), //TODO
.issue_alu_ready(issue_alu_ready),
.vgpr_instr_done_wfid(vgpr_instr_done_wfid),
.vgpr_instr_done(vgpr_instr_done),
.rfa_queue_entry_valid(rfa_queue_entry_valid),
.tracemon_retire_pc(tracemon_retire_pc),
.clk(clk),
.rst(rst)
);
//stimulii
initial begin
forever #5 clk = ~clk;
end
initial begin
#3 clk = 1'b0;
#16 rst = 1'b1;
issue_alu_select = 1'b0;
rfa_queue_entry_serviced = 1'b0;
#10 rst = 1'b0;
#2000;
$finish;
end
initial begin
#31;
$display("ISSUING AND\n");
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_source_reg3 = {32{1'bx}};
issue_dest_reg1 = {2'b10,10'd31};
issue_dest_reg2 = {12{1'bx}};
issue_imm_value0 = {16{1'bx}};
issue_imm_value1 = {32{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h01B}; //AND
issue_wfid = 6'd15;
issue_alu_select = 1'b1;
sgpr_rd_data = {32{1'bx}};
exec_rd_exec_value = 64'hffff_ffff_ffff_ff0f;
exec_rd_vcc_value = {64{1'bx}};
exec_rd_m0_value = {32{1'bx}};
exec_rd_scc_value = 1'bx;
issue_instr_pc = 32'hdead_f00d;
rfa_queue_entry_serviced = 1'b0;
vgpr_source1_data = {64{32'h0000_ffff}};
vgpr_source2_data = {64{32'h00ff_f0f0}};
vgpr_source3_data = {64{32'hx}};
#10;
issue_alu_select = 1'b0;
#40;
$display("ISSUING ADD\n");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP2_FORMAT, 12'h0, 12'h025}; //ADD
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h8000_0708}};
vgpr_source2_data = {64{32'h80ff_f0f0}};
//1|00ff_f7f7
#10;
issue_alu_select = 1'b0;
#10;
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#60;
$display("ISSUING MUL");
issue_alu_select = 1'b1;
issue_wfid = 6'd15;
issue_source_reg1 = {2'b10,10'd23};
issue_source_reg2 = {2'b10,10'd27};
issue_dest_reg1 = {2'b10,10'd31};
issue_imm_value0 = {32{1'bx}};
issue_imm_value1 = {16{1'bx}};
issue_opcode = {`ALU_VOP3A_FORMAT, 12'h0, 12'h16B}; //MUL_LO
sgpr_rd_data = {32{1'bx}};
issue_instr_pc = 32'hdead_f00d;
exec_rd_exec_value = 64'hffff_ffff_ffff_ffff;
exec_rd_vcc_value = {64{1'bx}};
vgpr_source1_data = {64{32'h0000_0007}};
vgpr_source2_data = {64{32'h0000_0005}};
//1|0000_0023
#10;
issue_alu_select = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
#100;
if (rfa_queue_entry_valid)
rfa_queue_entry_serviced = 1'b1;
#10;
rfa_queue_entry_serviced = 1'b0;
end
//monitors
initial begin
if ($test$plusargs("print_outputs")) begin
$monitor($time, ": issue_alu_select = %b, issue_alu_ready = %b \n \
rfa_queue_entry_serviced = %h, rfa_queue_entry_valid = %h \n \
vgpr_dest_data = %h",
issue_alu_select, issue_alu_ready,
rfa_queue_entry_serviced, rfa_queue_entry_valid,
vgpr_dest_data[31:0]
);
// $monitor("$time: vgpr_dest_data = %h", vgpr_dest_data);
//$monitor("$time: rfa_queue_entry_serviced = %b", rfa_queue_entry_serviced);
end
end
//waveforms
initial begin
if ($test$plusargs("dump_waveforms")) begin
$vcdpluson(0,simd_tb);
//$vcdpluson(<level>,scope,<signal>);
//Lots of options for dumping waves
//(both system calls and run time arguments)
// http://read.pudn.com/downloads97/sourcecode/others/399556/vcs_0123.pdf
end
end
endmodule
|
module adc_ltc2308(
clk, // max 40mhz
// start measure
measure_start, // posedge triggle
measure_ch,
measure_done,
measure_dataread,
// adc interface
ADC_CONVST,
ADC_SCK,
ADC_SDI,
ADC_SDO
);
input clk;
// start measure
input measure_start;
input [2:0] measure_ch;
output reg measure_done;
output [11:0] measure_dataread;
output ADC_CONVST;
output ADC_SCK;
output reg ADC_SDI;
input ADC_SDO;
/////////////////////////////////
// Timing definition
// using 40MHz clock
// to acheive fsample = 500KHz
// ntcyc = 2us / 25ns = 80
`define DATA_BITS_NUM 12
`define CMD_BITS_NUM 6
`define CH_NUM 8
`define tWHCONV 3 // CONVST High Time, min 20 ns
`define tCONV 64 //52 // tCONV: type 1.3 us, MAX 1.6 us, 1600/25(assumed clk is 40mhz)=64 -> 1.3us/25ns = 52
// set 64 for suite for 1.6 us max
// +12 //data
`define tHCONVST 320 // 12 // here set 320（ fsample = 100KHz） for if ADC input impedance is high, see below
// If the source impedance of the driving circuit is low, the ADC inputs can be driven directly.
//Otherwise, more acquisition time should be allowed for a source with higher impedance.
// for acheiving 500KHz fmax. set n cyc = 80.
`define tCONVST_HIGH_START 0
`define tCONVST_HIGH_END (`tCONVST_HIGH_START+`tWHCONV)
`define tCONFIG_START (`tCONVST_HIGH_END)
`define tCONFIG_END (`tCLK_START+`CMD_BITS_NUM - 1)
`define tCLK_START (`tCONVST_HIGH_START+`tCONV)
`define tCLK_END (`tCLK_START+`DATA_BITS_NUM)
`define tDONE (`tCLK_END+`tHCONVST)
// create triggle message: reset_n
reg pre_measure_start;
always @ (posedge clk)
begin
pre_measure_start <= measure_start;
end
wire reset_n;
assign reset_n = (~pre_measure_start & measure_start)?1'b0:1'b1;
// tick
reg [15:0] tick;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
tick <= 0;
else if (tick < `tDONE)
tick <= tick + 1;
end
/////////////////////////////////
// ADC_CONVST
assign ADC_CONVST = (tick >= `tCONVST_HIGH_START && tick < `tCONVST_HIGH_END)?1'b1:1'b0;
/////////////////////////////////
// ADC_SCK
reg clk_enable; // must sync to clk in clk low
always @ (negedge clk or negedge reset_n)
begin
if (~reset_n)
clk_enable <= 1'b0;
else if ((tick >= `tCLK_START && tick < `tCLK_END))
clk_enable <= 1'b1;
else
clk_enable <= 1'b0;
end
assign ADC_SCK = clk_enable?clk:1'b0;
///////////////////////////////
// read data
reg [(`DATA_BITS_NUM-1):0] read_data;
reg [3:0] write_pos;
assign measure_dataread = read_data;
always @ (negedge clk or negedge reset_n)
begin
if (~reset_n)
begin
read_data <= 0;
write_pos <= `DATA_BITS_NUM-1;
end
else if (clk_enable)
begin
read_data[write_pos] <= ADC_SDO;
write_pos <= write_pos - 1;
end
end
///////////////////////////////
// measure done
wire read_ch_done;
assign read_ch_done = (tick == `tDONE)?1'b1:1'b0;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
measure_done <= 1'b0;
else if (read_ch_done)
measure_done <= 1'b1;
end
///////////////////////////////
// adc channel config
// pre-build config command
reg [(`CMD_BITS_NUM-1):0] config_cmd;
`define UNI_MODE 1'b1 //1: Unipolar, 0:Bipolar
`define SLP_MODE 1'b0 //1: enable sleep
always @(negedge reset_n)
begin
if (~reset_n)
begin
case (measure_ch)
0 : config_cmd <= {4'h8, `UNI_MODE, `SLP_MODE};
1 : config_cmd <= {4'hC, `UNI_MODE, `SLP_MODE};
2 : config_cmd <= {4'h9, `UNI_MODE, `SLP_MODE};
3 : config_cmd <= {4'hD, `UNI_MODE, `SLP_MODE};
4 : config_cmd <= {4'hA, `UNI_MODE, `SLP_MODE};
5 : config_cmd <= {4'hE, `UNI_MODE, `SLP_MODE};
6 : config_cmd <= {4'hB, `UNI_MODE, `SLP_MODE};
7 : config_cmd <= {4'hF, `UNI_MODE, `SLP_MODE};
default : config_cmd <= {4'hF, 2'b00};
endcase
end
end
// serial config command to adc chip
wire config_init;
wire config_enable;
wire config_done;
reg [2:0] sdi_index;
assign config_init = (tick == `tCONFIG_START)?1'b1:1'b0;
assign config_enable = (tick > `tCLK_START && tick <= `tCONFIG_END)?1'b1:1'b0; // > because this is negative edge triggle
assign config_done = (tick > `tCONFIG_END)?1'b1:1'b0;
always @(negedge clk)
begin
if (config_init)
begin
ADC_SDI <= config_cmd[`CMD_BITS_NUM-1];
sdi_index <= `CMD_BITS_NUM-2;
end
else if (config_enable)
begin
ADC_SDI <= config_cmd[sdi_index];
sdi_index <= sdi_index - 1;
end
else if (config_done)
ADC_SDI <= 1'b0; //
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2007 Corgan Enterprises LLC
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../lib/radar_config.vh"
module radar(clk_i,saddr_i,sdata_i,s_strobe_i,
tx_side_o,tx_strobe_o,tx_dac_i_o,tx_dac_q_o,
rx_adc_i_i,rx_adc_q_i,
rx_strobe_o,rx_ech_i_o,rx_ech_q_o,io_tx_ena_o);
// System interface
input clk_i; // Master clock @ 64 MHz
input [6:0] saddr_i; // Configuration bus address
input [31:0] sdata_i; // Configuration bus data
input s_strobe_i; // Configuration bus write
// Transmit subsystem
output tx_side_o; // Transmitter slot
output tx_strobe_o; // Generate an transmitter output sample
output [13:0] tx_dac_i_o; // I channel transmitter output to DAC
output [13:0] tx_dac_q_o; // Q channel transmitter output to DAC
output io_tx_ena_o; // Transmit/Receive switching
// Receive subsystem
input [15:0] rx_adc_i_i; // I channel input from ADC
input [15:0] rx_adc_q_i; // Q channel input from ADC
output rx_strobe_o; // Indicates output samples ready for Rx FIFO
output [15:0] rx_ech_i_o; // I channel processed echos to Rx FIFO
output [15:0] rx_ech_q_o; // Q channel processed echos to Rx FIFO
// Application control
wire reset; // Master application reset
wire tx_side; // Transmitter slot
wire debug_enabled; // Enable debugging mode;
wire tx_enable; // Transmitter enable
wire rx_enable; // Receiver enable
wire tx_ctrl; // Transmitter on control
wire rx_ctrl; // Receiver on control
wire [15:0] pulse_num; // Count of pulses since tx_enabled
// Configuration
wire [15:0] ampl; // Pulse amplitude
wire [31:0] fstart; // Chirp start frequency
wire [31:0] fincr; // Chirp per strobe frequency increment
radar_control controller
(.clk_i(clk_i),.saddr_i(saddr_i),.sdata_i(sdata_i),.s_strobe_i(s_strobe_i),
.reset_o(reset),.tx_side_o(tx_side_o),.dbg_o(debug_enabled),
.tx_strobe_o(tx_strobe_o),.tx_ctrl_o(tx_ctrl),.rx_ctrl_o(rx_ctrl),
.ampl_o(ampl),.fstart_o(fstart),.fincr_o(fincr),.pulse_num_o(pulse_num),
.io_tx_ena_o(io_tx_ena_o));
radar_tx transmitter
( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_ctrl),.strobe_i(tx_strobe_o),
.ampl_i(ampl),.fstart_i(fstart),.fincr_i(fincr),
.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
radar_rx receiver
( .clk_i(clk_i),.rst_i(reset),.ena_i(rx_ctrl),.dbg_i(debug_enabled),
.pulse_num_i(pulse_num),.rx_in_i_i(rx_adc_i_i),.rx_in_q_i(rx_adc_q_i),
.rx_strobe_o(rx_strobe_o),.rx_i_o(rx_ech_i_o),.rx_q_o(rx_ech_q_o) );
endmodule // radar
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX2_1_V
`define SKY130_FD_SC_HVL__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX2_1_V
|
`ifdef __ICARUS__
`define SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
`endif
//
// Copyright (c) 1999 Steve Tell ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Concat in fopen not substituted correctly.
module write_sp_vectors(Clk, a, b, c);
input Clk, a, b, c;
parameter fname = "PhCount.unnamed";
parameter source_id = "(unknown source module RCSID)$";
integer fp;
initial
begin
// fails at runtime: "ERROR: $fopen parameter must be a constant"
fp = $fopen({"work/",fname,".inv"});
// this fails too
// fp = $fopen({"blurfl", ".inv"});
`ifdef SUPPORT_CONST_OUT_OF_RANGE_IN_IVTEST
$fdisplay(fp, "# captured from: %0s\n", source_id[8*80:8]);
`else
$fdisplay(fp, "# captured from: %0s\n", source_id[$bits(source_id)-1:8]);
`endif
end
endmodule
module main;
parameter fname = "PhCount.unnamed";
reg clk;
reg a,b,c;
write_sp_vectors #("sp2", "foo") v0 (clk,a, b, c);
initial
begin
#10 $finish;
end
endmodule
|
// // (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_mul_ll(
// this interface matches what hdlgen expects
input logic clock,
input logic resetn,
input logic enable,
input logic [31:0] dataa,
input logic [31:0] datab,
output logic [31:0] result
);
acl_fp_custom_mul_ll_hc_core #(
.HIGH_CAPACITY(0)
)
core(
.clock(clock),
.resetn(resetn),
.enable(enable),
.dataa(dataa),
.datab(datab),
.result(result)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRBP_1_V
`define SKY130_FD_SC_MS__SDFRBP_1_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfrbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfrbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfrbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRBP_1_V
|
/*
*******************************************************************************
* File Name : ada_memwb_stage.v
* Project : ADA processor
* Version : 0.1
* Date : Aug 8th, 2014
* Author : Angel Terrones <[email protected]>
*
* Disclaimer : Copyright © 2014 Angel Terrones
* Release under the MIT License.
*
* Description : Pipeline register: from Memory Access to Write Back
*******************************************************************************
*/
`include "ada_defines.v"
module ada_memwb_stage(
input clk, // main clock
input rst, // main reset
input [31:0] mem_gpr_wd, // data to GPR
input [4:0] mem_gpr_wa, // GPR write address
input mem_gpr_we, // GPR write enable
input mem_flush, // flush MEM stage
input mem_stall, // stall MEM stage
input wb_stall, // stall WB stage
output reg [31:0] wb_gpr_wd, // data to GPR
output reg [4:0] wb_gpr_wa, // GPR write address
output reg wb_gpr_we // GPR write enable
);
//--------------------------------------------------------------------------
// Propagate signals
// Stall WB only if MEM is stalled, and MEM needs data forwarded from WB.
//--------------------------------------------------------------------------
always @(posedge clk) begin
wb_gpr_wd <= (rst) ? 31'b0 : ((wb_stall) ? wb_gpr_wd : mem_gpr_wd);
wb_gpr_wa <= (rst) ? 5'b0 : ((wb_stall) ? wb_gpr_wa :((mem_stall | mem_flush) ? 5'b0 : mem_gpr_wa));
wb_gpr_we <= (rst) ? 1'b0 : ((wb_stall) ? wb_gpr_we :((mem_stall | mem_flush) ? 1'b0 : mem_gpr_we));
end
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// RDY_set_addr_map O 1
// slave_awready O 1 reg
// slave_wready O 1 reg
// slave_bvalid O 1 reg
// slave_bid O 4 reg
// slave_bresp O 2 reg
// slave_arready O 1 reg
// slave_rvalid O 1 reg
// slave_rid O 4 reg
// slave_rdata O 64 reg
// slave_rresp O 2 reg
// slave_rlast O 1 reg
// to_raw_mem_request_get O 353
// RDY_to_raw_mem_request_get O 1
// RDY_to_raw_mem_response_put O 1
// status O 8 reg
// RDY_set_watch_tohost O 1 const
// CLK I 1 clock
// RST_N I 1 reset
// set_addr_map_addr_base I 64 reg
// set_addr_map_addr_lim I 64 reg
// slave_awvalid I 1
// slave_awid I 4 reg
// slave_awaddr I 64 reg
// slave_awlen I 8 reg
// slave_awsize I 3 reg
// slave_awburst I 2 reg
// slave_awlock I 1 reg
// slave_awcache I 4 reg
// slave_awprot I 3 reg
// slave_awqos I 4 reg
// slave_awregion I 4 reg
// slave_wvalid I 1
// slave_wdata I 64 reg
// slave_wstrb I 8 reg
// slave_wlast I 1 reg
// slave_bready I 1
// slave_arvalid I 1
// slave_arid I 4 reg
// slave_araddr I 64 reg
// slave_arlen I 8 reg
// slave_arsize I 3 reg
// slave_arburst I 2 reg
// slave_arlock I 1 reg
// slave_arcache I 4 reg
// slave_arprot I 3 reg
// slave_arqos I 4 reg
// slave_arregion I 4 reg
// slave_rready I 1
// to_raw_mem_response_put I 256
// set_watch_tohost_watch_tohost I 1 reg
// set_watch_tohost_tohost_addr I 64 reg
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_set_addr_map I 1
// EN_to_raw_mem_response_put I 1
// EN_set_watch_tohost I 1
// EN_to_raw_mem_request_get I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMem_Controller(CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
set_addr_map_addr_base,
set_addr_map_addr_lim,
EN_set_addr_map,
RDY_set_addr_map,
slave_awvalid,
slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion,
slave_awready,
slave_wvalid,
slave_wdata,
slave_wstrb,
slave_wlast,
slave_wready,
slave_bvalid,
slave_bid,
slave_bresp,
slave_bready,
slave_arvalid,
slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion,
slave_arready,
slave_rvalid,
slave_rid,
slave_rdata,
slave_rresp,
slave_rlast,
slave_rready,
EN_to_raw_mem_request_get,
to_raw_mem_request_get,
RDY_to_raw_mem_request_get,
to_raw_mem_response_put,
EN_to_raw_mem_response_put,
RDY_to_raw_mem_response_put,
status,
set_watch_tohost_watch_tohost,
set_watch_tohost_tohost_addr,
EN_set_watch_tohost,
RDY_set_watch_tohost);
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method set_addr_map
input [63 : 0] set_addr_map_addr_base;
input [63 : 0] set_addr_map_addr_lim;
input EN_set_addr_map;
output RDY_set_addr_map;
// action method slave_m_awvalid
input slave_awvalid;
input [3 : 0] slave_awid;
input [63 : 0] slave_awaddr;
input [7 : 0] slave_awlen;
input [2 : 0] slave_awsize;
input [1 : 0] slave_awburst;
input slave_awlock;
input [3 : 0] slave_awcache;
input [2 : 0] slave_awprot;
input [3 : 0] slave_awqos;
input [3 : 0] slave_awregion;
// value method slave_m_awready
output slave_awready;
// action method slave_m_wvalid
input slave_wvalid;
input [63 : 0] slave_wdata;
input [7 : 0] slave_wstrb;
input slave_wlast;
// value method slave_m_wready
output slave_wready;
// value method slave_m_bvalid
output slave_bvalid;
// value method slave_m_bid
output [3 : 0] slave_bid;
// value method slave_m_bresp
output [1 : 0] slave_bresp;
// value method slave_m_buser
// action method slave_m_bready
input slave_bready;
// action method slave_m_arvalid
input slave_arvalid;
input [3 : 0] slave_arid;
input [63 : 0] slave_araddr;
input [7 : 0] slave_arlen;
input [2 : 0] slave_arsize;
input [1 : 0] slave_arburst;
input slave_arlock;
input [3 : 0] slave_arcache;
input [2 : 0] slave_arprot;
input [3 : 0] slave_arqos;
input [3 : 0] slave_arregion;
// value method slave_m_arready
output slave_arready;
// value method slave_m_rvalid
output slave_rvalid;
// value method slave_m_rid
output [3 : 0] slave_rid;
// value method slave_m_rdata
output [63 : 0] slave_rdata;
// value method slave_m_rresp
output [1 : 0] slave_rresp;
// value method slave_m_rlast
output slave_rlast;
// value method slave_m_ruser
// action method slave_m_rready
input slave_rready;
// actionvalue method to_raw_mem_request_get
input EN_to_raw_mem_request_get;
output [352 : 0] to_raw_mem_request_get;
output RDY_to_raw_mem_request_get;
// action method to_raw_mem_response_put
input [255 : 0] to_raw_mem_response_put;
input EN_to_raw_mem_response_put;
output RDY_to_raw_mem_response_put;
// value method status
output [7 : 0] status;
// action method set_watch_tohost
input set_watch_tohost_watch_tohost;
input [63 : 0] set_watch_tohost_tohost_addr;
input EN_set_watch_tohost;
output RDY_set_watch_tohost;
// signals for module outputs
wire [352 : 0] to_raw_mem_request_get;
wire [63 : 0] slave_rdata;
wire [7 : 0] status;
wire [3 : 0] slave_bid, slave_rid;
wire [1 : 0] slave_bresp, slave_rresp;
wire RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_addr_map,
RDY_set_watch_tohost,
RDY_to_raw_mem_request_get,
RDY_to_raw_mem_response_put,
slave_arready,
slave_awready,
slave_bvalid,
slave_rlast,
slave_rvalid,
slave_wready;
// inlined wires
reg [353 : 0] f_raw_mem_reqs_rv$port1__write_1;
wire [353 : 0] f_raw_mem_reqs_rv$port1__read,
f_raw_mem_reqs_rv$port2__read,
f_raw_mem_reqs_rv$port3__read;
wire [256 : 0] f_raw_mem_rsps_rv$port1__read,
f_raw_mem_rsps_rv$port1__write_1,
f_raw_mem_rsps_rv$port2__read,
f_raw_mem_rsps_rv$port3__read;
wire [170 : 0] f_reqs_rv$port1__read,
f_reqs_rv$port1__write_1,
f_reqs_rv$port2__read;
wire f_raw_mem_reqs_rv$EN_port1__write,
f_reqs_rv$EN_port0__write,
f_reqs_rv$EN_port1__write;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register f_raw_mem_reqs_rv
reg [353 : 0] f_raw_mem_reqs_rv;
wire [353 : 0] f_raw_mem_reqs_rv$D_IN;
wire f_raw_mem_reqs_rv$EN;
// register f_raw_mem_rsps_rv
reg [256 : 0] f_raw_mem_rsps_rv;
wire [256 : 0] f_raw_mem_rsps_rv$D_IN;
wire f_raw_mem_rsps_rv$EN;
// register f_reqs_rv
reg [170 : 0] f_reqs_rv;
wire [170 : 0] f_reqs_rv$D_IN;
wire f_reqs_rv$EN;
// register rg_addr_base
reg [63 : 0] rg_addr_base;
wire [63 : 0] rg_addr_base$D_IN;
wire rg_addr_base$EN;
// register rg_addr_lim
reg [63 : 0] rg_addr_lim;
wire [63 : 0] rg_addr_lim$D_IN;
wire rg_addr_lim$EN;
// register rg_cached_clean
reg rg_cached_clean;
wire rg_cached_clean$D_IN, rg_cached_clean$EN;
// register rg_cached_raw_mem_addr
reg [63 : 0] rg_cached_raw_mem_addr;
wire [63 : 0] rg_cached_raw_mem_addr$D_IN;
wire rg_cached_raw_mem_addr$EN;
// register rg_cached_raw_mem_word
reg [255 : 0] rg_cached_raw_mem_word;
wire [255 : 0] rg_cached_raw_mem_word$D_IN;
wire rg_cached_raw_mem_word$EN;
// register rg_state
reg [1 : 0] rg_state;
reg [1 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_status
reg [7 : 0] rg_status;
wire [7 : 0] rg_status$D_IN;
wire rg_status$EN;
// register rg_tohost_addr
reg [63 : 0] rg_tohost_addr;
wire [63 : 0] rg_tohost_addr$D_IN;
wire rg_tohost_addr$EN;
// register rg_watch_tohost
reg rg_watch_tohost;
wire rg_watch_tohost$D_IN, rg_watch_tohost$EN;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule slave_xactor_f_rd_addr
wire [96 : 0] slave_xactor_f_rd_addr$D_IN, slave_xactor_f_rd_addr$D_OUT;
wire slave_xactor_f_rd_addr$CLR,
slave_xactor_f_rd_addr$DEQ,
slave_xactor_f_rd_addr$EMPTY_N,
slave_xactor_f_rd_addr$ENQ,
slave_xactor_f_rd_addr$FULL_N;
// ports of submodule slave_xactor_f_rd_data
wire [70 : 0] slave_xactor_f_rd_data$D_IN, slave_xactor_f_rd_data$D_OUT;
wire slave_xactor_f_rd_data$CLR,
slave_xactor_f_rd_data$DEQ,
slave_xactor_f_rd_data$EMPTY_N,
slave_xactor_f_rd_data$ENQ,
slave_xactor_f_rd_data$FULL_N;
// ports of submodule slave_xactor_f_wr_addr
wire [96 : 0] slave_xactor_f_wr_addr$D_IN, slave_xactor_f_wr_addr$D_OUT;
wire slave_xactor_f_wr_addr$CLR,
slave_xactor_f_wr_addr$DEQ,
slave_xactor_f_wr_addr$EMPTY_N,
slave_xactor_f_wr_addr$ENQ,
slave_xactor_f_wr_addr$FULL_N;
// ports of submodule slave_xactor_f_wr_data
wire [72 : 0] slave_xactor_f_wr_data$D_IN, slave_xactor_f_wr_data$D_OUT;
wire slave_xactor_f_wr_data$CLR,
slave_xactor_f_wr_data$DEQ,
slave_xactor_f_wr_data$EMPTY_N,
slave_xactor_f_wr_data$ENQ,
slave_xactor_f_wr_data$FULL_N;
// ports of submodule slave_xactor_f_wr_resp
wire [5 : 0] slave_xactor_f_wr_resp$D_IN, slave_xactor_f_wr_resp$D_OUT;
wire slave_xactor_f_wr_resp$CLR,
slave_xactor_f_wr_resp$DEQ,
slave_xactor_f_wr_resp$EMPTY_N,
slave_xactor_f_wr_resp$ENQ,
slave_xactor_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_rl_external_reset,
CAN_FIRE_RL_rl_invalid_rd_address,
CAN_FIRE_RL_rl_invalid_wr_address,
CAN_FIRE_RL_rl_merge_rd_req,
CAN_FIRE_RL_rl_merge_wr_req,
CAN_FIRE_RL_rl_miss_clean_req,
CAN_FIRE_RL_rl_power_on_reset,
CAN_FIRE_RL_rl_process_rd_req,
CAN_FIRE_RL_rl_process_wr_req,
CAN_FIRE_RL_rl_reload,
CAN_FIRE_RL_rl_reset_reload_cache,
CAN_FIRE_RL_rl_writeback_dirty,
CAN_FIRE_RL_rl_writeback_dirty_idle,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_addr_map,
CAN_FIRE_set_watch_tohost,
CAN_FIRE_slave_m_arvalid,
CAN_FIRE_slave_m_awvalid,
CAN_FIRE_slave_m_bready,
CAN_FIRE_slave_m_rready,
CAN_FIRE_slave_m_wvalid,
CAN_FIRE_to_raw_mem_request_get,
CAN_FIRE_to_raw_mem_response_put,
WILL_FIRE_RL_rl_external_reset,
WILL_FIRE_RL_rl_invalid_rd_address,
WILL_FIRE_RL_rl_invalid_wr_address,
WILL_FIRE_RL_rl_merge_rd_req,
WILL_FIRE_RL_rl_merge_wr_req,
WILL_FIRE_RL_rl_miss_clean_req,
WILL_FIRE_RL_rl_power_on_reset,
WILL_FIRE_RL_rl_process_rd_req,
WILL_FIRE_RL_rl_process_wr_req,
WILL_FIRE_RL_rl_reload,
WILL_FIRE_RL_rl_reset_reload_cache,
WILL_FIRE_RL_rl_writeback_dirty,
WILL_FIRE_RL_rl_writeback_dirty_idle,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_addr_map,
WILL_FIRE_set_watch_tohost,
WILL_FIRE_slave_m_arvalid,
WILL_FIRE_slave_m_awvalid,
WILL_FIRE_slave_m_bready,
WILL_FIRE_slave_m_rready,
WILL_FIRE_slave_m_wvalid,
WILL_FIRE_to_raw_mem_request_get,
WILL_FIRE_to_raw_mem_response_put;
// inputs to muxes for submodule ports
wire [353 : 0] MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1,
MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3;
wire [255 : 0] MUX_rg_cached_raw_mem_word$write_1__VAL_1;
wire [170 : 0] MUX_f_reqs_rv$port1__write_1__VAL_1,
MUX_f_reqs_rv$port1__write_1__VAL_2;
wire [70 : 0] MUX_slave_xactor_f_rd_data$enq_1__VAL_1,
MUX_slave_xactor_f_rd_data$enq_1__VAL_2;
wire [5 : 0] MUX_slave_xactor_f_wr_resp$enq_1__VAL_1,
MUX_slave_xactor_f_wr_resp$enq_1__VAL_2;
wire MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1,
MUX_rg_state$write_1__SEL_1,
MUX_rg_state$write_1__SEL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h2421;
reg [31 : 0] v__h3360;
reg [31 : 0] v__h3856;
reg [31 : 0] v__h4337;
reg [31 : 0] v__h4626;
reg [31 : 0] v__h5342;
reg [31 : 0] v__h7563;
reg [31 : 0] v__h7771;
reg [31 : 0] v__h8284;
reg [31 : 0] v__h9087;
reg [31 : 0] v__h9718;
reg [31 : 0] v__h2729;
reg [31 : 0] v__h3055;
reg [31 : 0] v__h1680;
reg [31 : 0] v__h1988;
reg [31 : 0] v__h1674;
reg [31 : 0] v__h1982;
reg [31 : 0] v__h2415;
reg [31 : 0] v__h2723;
reg [31 : 0] v__h3049;
reg [31 : 0] v__h3354;
reg [31 : 0] v__h3850;
reg [31 : 0] v__h4331;
reg [31 : 0] v__h4620;
reg [31 : 0] v__h5336;
reg [31 : 0] v__h7557;
reg [31 : 0] v__h7765;
reg [31 : 0] v__h8278;
reg [31 : 0] v__h9081;
reg [31 : 0] v__h9712;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] rdata__h4997, word64_old__h5797;
wire [63 : 0] exit_value__h7817,
f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1,
mask__h5802,
req_raw_mem_addr__h3185,
updated_word64__h5803,
x__h6185,
y__h6186,
y__h6187;
wire [7 : 0] SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214,
SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211,
SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207,
SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204,
SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200,
SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197,
SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193,
SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190;
wire [4 : 0] n__h4996;
wire NOT_cfg_verbosity_read_ULE_1___d5,
NOT_cfg_verbosity_read_ULE_2_2___d33,
NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278,
f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127,
f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122,
rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125,
rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134,
rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283,
rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130,
rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method set_addr_map
assign RDY_set_addr_map = rg_state == 2'd3 ;
assign CAN_FIRE_set_addr_map = rg_state == 2'd3 ;
assign WILL_FIRE_set_addr_map = EN_set_addr_map ;
// action method slave_m_awvalid
assign CAN_FIRE_slave_m_awvalid = 1'd1 ;
assign WILL_FIRE_slave_m_awvalid = 1'd1 ;
// value method slave_m_awready
assign slave_awready = slave_xactor_f_wr_addr$FULL_N ;
// action method slave_m_wvalid
assign CAN_FIRE_slave_m_wvalid = 1'd1 ;
assign WILL_FIRE_slave_m_wvalid = 1'd1 ;
// value method slave_m_wready
assign slave_wready = slave_xactor_f_wr_data$FULL_N ;
// value method slave_m_bvalid
assign slave_bvalid = slave_xactor_f_wr_resp$EMPTY_N ;
// value method slave_m_bid
assign slave_bid = slave_xactor_f_wr_resp$D_OUT[5:2] ;
// value method slave_m_bresp
assign slave_bresp = slave_xactor_f_wr_resp$D_OUT[1:0] ;
// action method slave_m_bready
assign CAN_FIRE_slave_m_bready = 1'd1 ;
assign WILL_FIRE_slave_m_bready = 1'd1 ;
// action method slave_m_arvalid
assign CAN_FIRE_slave_m_arvalid = 1'd1 ;
assign WILL_FIRE_slave_m_arvalid = 1'd1 ;
// value method slave_m_arready
assign slave_arready = slave_xactor_f_rd_addr$FULL_N ;
// value method slave_m_rvalid
assign slave_rvalid = slave_xactor_f_rd_data$EMPTY_N ;
// value method slave_m_rid
assign slave_rid = slave_xactor_f_rd_data$D_OUT[70:67] ;
// value method slave_m_rdata
assign slave_rdata = slave_xactor_f_rd_data$D_OUT[66:3] ;
// value method slave_m_rresp
assign slave_rresp = slave_xactor_f_rd_data$D_OUT[2:1] ;
// value method slave_m_rlast
assign slave_rlast = slave_xactor_f_rd_data$D_OUT[0] ;
// action method slave_m_rready
assign CAN_FIRE_slave_m_rready = 1'd1 ;
assign WILL_FIRE_slave_m_rready = 1'd1 ;
// actionvalue method to_raw_mem_request_get
assign to_raw_mem_request_get = f_raw_mem_reqs_rv[352:0] ;
assign RDY_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ;
assign CAN_FIRE_to_raw_mem_request_get = f_raw_mem_reqs_rv[353] ;
assign WILL_FIRE_to_raw_mem_request_get = EN_to_raw_mem_request_get ;
// action method to_raw_mem_response_put
assign RDY_to_raw_mem_response_put = !f_raw_mem_rsps_rv$port1__read[256] ;
assign CAN_FIRE_to_raw_mem_response_put =
!f_raw_mem_rsps_rv$port1__read[256] ;
assign WILL_FIRE_to_raw_mem_response_put = EN_to_raw_mem_response_put ;
// value method status
assign status = rg_status ;
// action method set_watch_tohost
assign RDY_set_watch_tohost = 1'd1 ;
assign CAN_FIRE_set_watch_tohost = 1'd1 ;
assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;
// submodule f_reset_reqs
FIFO20 #(.guarded(1'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO20 #(.guarded(1'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule slave_xactor_f_rd_addr
FIFO2 #(.width(32'd97), .guarded(1'd1)) slave_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_addr$D_IN),
.ENQ(slave_xactor_f_rd_addr$ENQ),
.DEQ(slave_xactor_f_rd_addr$DEQ),
.CLR(slave_xactor_f_rd_addr$CLR),
.D_OUT(slave_xactor_f_rd_addr$D_OUT),
.FULL_N(slave_xactor_f_rd_addr$FULL_N),
.EMPTY_N(slave_xactor_f_rd_addr$EMPTY_N));
// submodule slave_xactor_f_rd_data
FIFO2 #(.width(32'd71), .guarded(1'd1)) slave_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_rd_data$D_IN),
.ENQ(slave_xactor_f_rd_data$ENQ),
.DEQ(slave_xactor_f_rd_data$DEQ),
.CLR(slave_xactor_f_rd_data$CLR),
.D_OUT(slave_xactor_f_rd_data$D_OUT),
.FULL_N(slave_xactor_f_rd_data$FULL_N),
.EMPTY_N(slave_xactor_f_rd_data$EMPTY_N));
// submodule slave_xactor_f_wr_addr
FIFO2 #(.width(32'd97), .guarded(1'd1)) slave_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_addr$D_IN),
.ENQ(slave_xactor_f_wr_addr$ENQ),
.DEQ(slave_xactor_f_wr_addr$DEQ),
.CLR(slave_xactor_f_wr_addr$CLR),
.D_OUT(slave_xactor_f_wr_addr$D_OUT),
.FULL_N(slave_xactor_f_wr_addr$FULL_N),
.EMPTY_N(slave_xactor_f_wr_addr$EMPTY_N));
// submodule slave_xactor_f_wr_data
FIFO2 #(.width(32'd73), .guarded(1'd1)) slave_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_data$D_IN),
.ENQ(slave_xactor_f_wr_data$ENQ),
.DEQ(slave_xactor_f_wr_data$DEQ),
.CLR(slave_xactor_f_wr_data$CLR),
.D_OUT(slave_xactor_f_wr_data$D_OUT),
.FULL_N(slave_xactor_f_wr_data$FULL_N),
.EMPTY_N(slave_xactor_f_wr_data$EMPTY_N));
// submodule slave_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(1'd1)) slave_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(slave_xactor_f_wr_resp$D_IN),
.ENQ(slave_xactor_f_wr_resp$ENQ),
.DEQ(slave_xactor_f_wr_resp$DEQ),
.CLR(slave_xactor_f_wr_resp$CLR),
.D_OUT(slave_xactor_f_wr_resp$D_OUT),
.FULL_N(slave_xactor_f_wr_resp$FULL_N),
.EMPTY_N(slave_xactor_f_wr_resp$EMPTY_N));
// rule RL_rl_reset_reload_cache
assign CAN_FIRE_RL_rl_reset_reload_cache =
!f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd1 ;
assign WILL_FIRE_RL_rl_reset_reload_cache =
CAN_FIRE_RL_rl_reset_reload_cache ;
// rule RL_rl_writeback_dirty_idle
assign CAN_FIRE_RL_rl_writeback_dirty_idle =
!f_raw_mem_reqs_rv$port1__read[353] && rg_state == 2'd3 &&
!f_reqs_rv[170] &&
!rg_cached_clean ;
assign WILL_FIRE_RL_rl_writeback_dirty_idle =
CAN_FIRE_RL_rl_writeback_dirty_idle ;
// rule RL_rl_writeback_dirty
assign CAN_FIRE_RL_rl_writeback_dirty =
!f_raw_mem_reqs_rv$port1__read[353] && f_reqs_rv[170] &&
rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 &&
!rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 &&
!rg_cached_clean ;
assign WILL_FIRE_RL_rl_writeback_dirty = CAN_FIRE_RL_rl_writeback_dirty ;
// rule RL_rl_miss_clean_req
assign CAN_FIRE_RL_rl_miss_clean_req =
f_reqs_rv[170] && !f_raw_mem_reqs_rv$port1__read[353] &&
rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 &&
!rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 &&
rg_cached_clean ;
assign WILL_FIRE_RL_rl_miss_clean_req =
CAN_FIRE_RL_rl_miss_clean_req &&
!WILL_FIRE_RL_rl_external_reset &&
!EN_set_addr_map ;
// rule RL_rl_reload
assign CAN_FIRE_RL_rl_reload = f_raw_mem_rsps_rv[256] && rg_state == 2'd2 ;
assign WILL_FIRE_RL_rl_reload = CAN_FIRE_RL_rl_reload ;
// rule RL_rl_process_rd_req
assign CAN_FIRE_RL_rl_process_rd_req =
f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N &&
rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 &&
rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 &&
!f_reqs_rv[169] ;
assign WILL_FIRE_RL_rl_process_rd_req = CAN_FIRE_RL_rl_process_rd_req ;
// rule RL_rl_process_wr_req
assign CAN_FIRE_RL_rl_process_wr_req =
f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N &&
rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 &&
rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 &&
f_reqs_rv[169] ;
assign WILL_FIRE_RL_rl_process_wr_req = CAN_FIRE_RL_rl_process_wr_req ;
// rule RL_rl_invalid_rd_address
assign CAN_FIRE_RL_rl_invalid_rd_address =
f_reqs_rv[170] && slave_xactor_f_rd_data$FULL_N &&
rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 &&
!f_reqs_rv[169] ;
assign WILL_FIRE_RL_rl_invalid_rd_address =
CAN_FIRE_RL_rl_invalid_rd_address ;
// rule RL_rl_invalid_wr_address
assign CAN_FIRE_RL_rl_invalid_wr_address =
f_reqs_rv[170] && slave_xactor_f_wr_resp$FULL_N &&
rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 &&
f_reqs_rv[169] ;
assign WILL_FIRE_RL_rl_invalid_wr_address =
CAN_FIRE_RL_rl_invalid_wr_address ;
// rule RL_rl_merge_rd_req
assign CAN_FIRE_RL_rl_merge_rd_req =
slave_xactor_f_rd_addr$EMPTY_N && !f_reqs_rv$port1__read[170] ;
assign WILL_FIRE_RL_rl_merge_rd_req = CAN_FIRE_RL_rl_merge_rd_req ;
// rule RL_rl_merge_wr_req
assign CAN_FIRE_RL_rl_merge_wr_req =
!f_reqs_rv$port1__read[170] && slave_xactor_f_wr_addr$EMPTY_N &&
slave_xactor_f_wr_data$EMPTY_N ;
assign WILL_FIRE_RL_rl_merge_wr_req =
CAN_FIRE_RL_rl_merge_wr_req && !WILL_FIRE_RL_rl_merge_rd_req ;
// rule RL_rl_power_on_reset
assign CAN_FIRE_RL_rl_power_on_reset = rg_state == 2'd0 ;
assign WILL_FIRE_RL_rl_power_on_reset = CAN_FIRE_RL_rl_power_on_reset ;
// rule RL_rl_external_reset
assign CAN_FIRE_RL_rl_external_reset =
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N && rg_state == 2'd3 ;
assign WILL_FIRE_RL_rl_external_reset = CAN_FIRE_RL_rl_external_reset ;
// inputs to muxes for submodule ports
assign MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 =
WILL_FIRE_RL_rl_writeback_dirty ||
WILL_FIRE_RL_rl_writeback_dirty_idle ;
assign MUX_rg_state$write_1__SEL_1 =
WILL_FIRE_RL_rl_external_reset ||
WILL_FIRE_RL_rl_power_on_reset ;
assign MUX_rg_state$write_1__SEL_2 =
WILL_FIRE_RL_rl_miss_clean_req ||
WILL_FIRE_RL_rl_reset_reload_cache ;
assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 =
{ 34'h3FFFFFFFF,
rg_cached_raw_mem_addr,
rg_cached_raw_mem_word } ;
assign MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3 =
{ 34'h2FFFFFFFF,
req_raw_mem_addr__h3185,
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
assign MUX_f_reqs_rv$port1__write_1__VAL_1 =
{ 2'd2, slave_xactor_f_rd_addr$D_OUT, 72'hAAAAAAAAAAAAAAAAAA } ;
assign MUX_f_reqs_rv$port1__write_1__VAL_2 =
{ 2'd3,
slave_xactor_f_wr_addr$D_OUT,
slave_xactor_f_wr_data$D_OUT[8:1],
slave_xactor_f_wr_data$D_OUT[72:9] } ;
assign MUX_rg_cached_raw_mem_word$write_1__VAL_1 =
{ (f_reqs_rv[105:104] == 2'd3) ?
updated_word64__h5803 :
rg_cached_raw_mem_word[255:192],
(f_reqs_rv[105:104] == 2'd2) ?
updated_word64__h5803 :
rg_cached_raw_mem_word[191:128],
(f_reqs_rv[105:104] == 2'd1) ?
updated_word64__h5803 :
rg_cached_raw_mem_word[127:64],
(f_reqs_rv[105:104] == 2'd0) ?
updated_word64__h5803 :
rg_cached_raw_mem_word[63:0] } ;
assign MUX_slave_xactor_f_rd_data$enq_1__VAL_1 =
{ f_reqs_rv[168:165], rdata__h4997, 3'd1 } ;
assign MUX_slave_xactor_f_rd_data$enq_1__VAL_2 =
{ f_reqs_rv[168:101], 3'd5 } ;
assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 =
{ f_reqs_rv[168:165], 2'd0 } ;
assign MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 =
{ f_reqs_rv[168:165], 2'd2 } ;
// inlined wires
assign f_reqs_rv$EN_port0__write =
WILL_FIRE_RL_rl_invalid_wr_address ||
WILL_FIRE_RL_rl_invalid_rd_address ||
WILL_FIRE_RL_rl_process_wr_req ||
WILL_FIRE_RL_rl_process_rd_req ;
assign f_reqs_rv$port1__read =
f_reqs_rv$EN_port0__write ?
171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
f_reqs_rv ;
assign f_reqs_rv$EN_port1__write =
WILL_FIRE_RL_rl_merge_rd_req || WILL_FIRE_RL_rl_merge_wr_req ;
assign f_reqs_rv$port1__write_1 =
WILL_FIRE_RL_rl_merge_rd_req ?
MUX_f_reqs_rv$port1__write_1__VAL_1 :
MUX_f_reqs_rv$port1__write_1__VAL_2 ;
assign f_reqs_rv$port2__read =
f_reqs_rv$EN_port1__write ?
f_reqs_rv$port1__write_1 :
f_reqs_rv$port1__read ;
assign f_raw_mem_reqs_rv$port1__read =
EN_to_raw_mem_request_get ?
354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
f_raw_mem_reqs_rv ;
assign f_raw_mem_reqs_rv$EN_port1__write =
WILL_FIRE_RL_rl_writeback_dirty ||
WILL_FIRE_RL_rl_writeback_dirty_idle ||
WILL_FIRE_RL_rl_reset_reload_cache ||
WILL_FIRE_RL_rl_miss_clean_req ;
always@(MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1 or
MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1 or
WILL_FIRE_RL_rl_reset_reload_cache or
WILL_FIRE_RL_rl_miss_clean_req or
MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_f_raw_mem_reqs_rv$port1__write_1__SEL_1:
f_raw_mem_reqs_rv$port1__write_1 =
MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_1;
WILL_FIRE_RL_rl_reset_reload_cache:
f_raw_mem_reqs_rv$port1__write_1 =
354'h2FFFFFFFF0000000000000000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_miss_clean_req:
f_raw_mem_reqs_rv$port1__write_1 =
MUX_f_raw_mem_reqs_rv$port1__write_1__VAL_3;
default: f_raw_mem_reqs_rv$port1__write_1 =
354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_raw_mem_reqs_rv$port2__read =
f_raw_mem_reqs_rv$EN_port1__write ?
f_raw_mem_reqs_rv$port1__write_1 :
f_raw_mem_reqs_rv$port1__read ;
assign f_raw_mem_reqs_rv$port3__read =
MUX_rg_state$write_1__SEL_1 ?
354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
f_raw_mem_reqs_rv$port2__read ;
assign f_raw_mem_rsps_rv$port1__read =
CAN_FIRE_RL_rl_reload ?
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
f_raw_mem_rsps_rv ;
assign f_raw_mem_rsps_rv$port1__write_1 =
{ 1'd1, to_raw_mem_response_put } ;
assign f_raw_mem_rsps_rv$port2__read =
EN_to_raw_mem_response_put ?
f_raw_mem_rsps_rv$port1__write_1 :
f_raw_mem_rsps_rv$port1__read ;
assign f_raw_mem_rsps_rv$port3__read =
MUX_rg_state$write_1__SEL_1 ?
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
f_raw_mem_rsps_rv$port2__read ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = 4'h0 ;
assign cfg_verbosity$EN = 1'b0 ;
// register f_raw_mem_reqs_rv
assign f_raw_mem_reqs_rv$D_IN = f_raw_mem_reqs_rv$port3__read ;
assign f_raw_mem_reqs_rv$EN = 1'b1 ;
// register f_raw_mem_rsps_rv
assign f_raw_mem_rsps_rv$D_IN = f_raw_mem_rsps_rv$port3__read ;
assign f_raw_mem_rsps_rv$EN = 1'b1 ;
// register f_reqs_rv
assign f_reqs_rv$D_IN = f_reqs_rv$port2__read ;
assign f_reqs_rv$EN = 1'b1 ;
// register rg_addr_base
assign rg_addr_base$D_IN = set_addr_map_addr_base ;
assign rg_addr_base$EN = EN_set_addr_map ;
// register rg_addr_lim
assign rg_addr_lim$D_IN = set_addr_map_addr_lim ;
assign rg_addr_lim$EN = EN_set_addr_map ;
// register rg_cached_clean
assign rg_cached_clean$D_IN = !WILL_FIRE_RL_rl_process_wr_req ;
assign rg_cached_clean$EN =
WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ||
WILL_FIRE_RL_rl_writeback_dirty ||
WILL_FIRE_RL_rl_writeback_dirty_idle ;
// register rg_cached_raw_mem_addr
assign rg_cached_raw_mem_addr$D_IN =
WILL_FIRE_RL_rl_miss_clean_req ?
req_raw_mem_addr__h3185 :
64'd0 ;
assign rg_cached_raw_mem_addr$EN = MUX_rg_state$write_1__SEL_2 ;
// register rg_cached_raw_mem_word
assign rg_cached_raw_mem_word$D_IN =
WILL_FIRE_RL_rl_process_wr_req ?
MUX_rg_cached_raw_mem_word$write_1__VAL_1 :
f_raw_mem_rsps_rv[255:0] ;
assign rg_cached_raw_mem_word$EN =
WILL_FIRE_RL_rl_process_wr_req || WILL_FIRE_RL_rl_reload ;
// register rg_state
always@(MUX_rg_state$write_1__SEL_1 or
MUX_rg_state$write_1__SEL_2 or WILL_FIRE_RL_rl_reload)
begin
case (1'b1) // synopsys parallel_case
MUX_rg_state$write_1__SEL_1: rg_state$D_IN = 2'd1;
MUX_rg_state$write_1__SEL_2: rg_state$D_IN = 2'd2;
WILL_FIRE_RL_rl_reload: rg_state$D_IN = 2'd3;
default: rg_state$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign rg_state$EN =
WILL_FIRE_RL_rl_external_reset ||
WILL_FIRE_RL_rl_power_on_reset ||
WILL_FIRE_RL_rl_miss_clean_req ||
WILL_FIRE_RL_rl_reset_reload_cache ||
WILL_FIRE_RL_rl_reload ;
// register rg_status
assign rg_status$D_IN =
(WILL_FIRE_RL_rl_external_reset ||
WILL_FIRE_RL_rl_power_on_reset) ?
8'd0 :
8'd1 ;
assign rg_status$EN =
WILL_FIRE_RL_rl_process_wr_req &&
rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 ||
WILL_FIRE_RL_rl_external_reset ||
WILL_FIRE_RL_rl_power_on_reset ;
// register rg_tohost_addr
assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ;
assign rg_tohost_addr$EN = EN_set_watch_tohost ;
// register rg_watch_tohost
assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ;
assign rg_watch_tohost$EN = EN_set_watch_tohost ;
// submodule f_reset_reqs
assign f_reset_reqs$ENQ = EN_server_reset_request_put ;
assign f_reset_reqs$DEQ = CAN_FIRE_RL_rl_external_reset ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$ENQ = CAN_FIRE_RL_rl_external_reset ;
assign f_reset_rsps$DEQ = EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule slave_xactor_f_rd_addr
assign slave_xactor_f_rd_addr$D_IN =
{ slave_arid,
slave_araddr,
slave_arlen,
slave_arsize,
slave_arburst,
slave_arlock,
slave_arcache,
slave_arprot,
slave_arqos,
slave_arregion } ;
assign slave_xactor_f_rd_addr$ENQ =
slave_arvalid && slave_xactor_f_rd_addr$FULL_N ;
assign slave_xactor_f_rd_addr$DEQ = CAN_FIRE_RL_rl_merge_rd_req ;
assign slave_xactor_f_rd_addr$CLR = MUX_rg_state$write_1__SEL_1 ;
// submodule slave_xactor_f_rd_data
assign slave_xactor_f_rd_data$D_IN =
WILL_FIRE_RL_rl_process_rd_req ?
MUX_slave_xactor_f_rd_data$enq_1__VAL_1 :
MUX_slave_xactor_f_rd_data$enq_1__VAL_2 ;
assign slave_xactor_f_rd_data$ENQ =
WILL_FIRE_RL_rl_process_rd_req ||
WILL_FIRE_RL_rl_invalid_rd_address ;
assign slave_xactor_f_rd_data$DEQ =
slave_rready && slave_xactor_f_rd_data$EMPTY_N ;
assign slave_xactor_f_rd_data$CLR = MUX_rg_state$write_1__SEL_1 ;
// submodule slave_xactor_f_wr_addr
assign slave_xactor_f_wr_addr$D_IN =
{ slave_awid,
slave_awaddr,
slave_awlen,
slave_awsize,
slave_awburst,
slave_awlock,
slave_awcache,
slave_awprot,
slave_awqos,
slave_awregion } ;
assign slave_xactor_f_wr_addr$ENQ =
slave_awvalid && slave_xactor_f_wr_addr$FULL_N ;
assign slave_xactor_f_wr_addr$DEQ = WILL_FIRE_RL_rl_merge_wr_req ;
assign slave_xactor_f_wr_addr$CLR = MUX_rg_state$write_1__SEL_1 ;
// submodule slave_xactor_f_wr_data
assign slave_xactor_f_wr_data$D_IN =
{ slave_wdata, slave_wstrb, slave_wlast } ;
assign slave_xactor_f_wr_data$ENQ =
slave_wvalid && slave_xactor_f_wr_data$FULL_N ;
assign slave_xactor_f_wr_data$DEQ = WILL_FIRE_RL_rl_merge_wr_req ;
assign slave_xactor_f_wr_data$CLR = MUX_rg_state$write_1__SEL_1 ;
// submodule slave_xactor_f_wr_resp
assign slave_xactor_f_wr_resp$D_IN =
WILL_FIRE_RL_rl_process_wr_req ?
MUX_slave_xactor_f_wr_resp$enq_1__VAL_1 :
MUX_slave_xactor_f_wr_resp$enq_1__VAL_2 ;
assign slave_xactor_f_wr_resp$ENQ =
WILL_FIRE_RL_rl_process_wr_req ||
WILL_FIRE_RL_rl_invalid_wr_address ;
assign slave_xactor_f_wr_resp$DEQ =
slave_bready && slave_xactor_f_wr_resp$EMPTY_N ;
assign slave_xactor_f_wr_resp$CLR = MUX_rg_state$write_1__SEL_1 ;
// remaining internal signals
assign NOT_cfg_verbosity_read_ULE_1___d5 = cfg_verbosity > 4'd1 ;
assign NOT_cfg_verbosity_read_ULE_2_2___d33 = cfg_verbosity > 4'd2 ;
assign NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278 =
f_reqs_rv[92:90] != 3'b0 &&
(f_reqs_rv[92:90] != 3'b001 || f_reqs_rv[101]) &&
(f_reqs_rv[92:90] != 3'b010 || f_reqs_rv[102:101] != 2'h0) &&
(f_reqs_rv[92:90] != 3'b011 || f_reqs_rv[103:101] != 3'h0) &&
(f_reqs_rv[92:90] != 3'b100 || f_reqs_rv[104:101] != 4'h0) &&
(f_reqs_rv[92:90] != 3'b101 || f_reqs_rv[105:101] != 5'h0) &&
(f_reqs_rv[92:90] != 3'b110 || f_reqs_rv[106:101] != 6'h0) &&
(f_reqs_rv[92:90] != 3'b111 || f_reqs_rv[107:101] != 7'h0) ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 = {8{f_reqs_rv[64]}} ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211 = {8{f_reqs_rv[65]}} ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207 = {8{f_reqs_rv[66]}} ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204 = {8{f_reqs_rv[67]}} ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200 = {8{f_reqs_rv[68]}} ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197 = {8{f_reqs_rv[69]}} ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193 = {8{f_reqs_rv[70]}} ;
assign SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190 = {8{f_reqs_rv[71]}} ;
assign exit_value__h7817 = { 1'd0, f_reqs_rv[63:1] } ;
assign f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1 =
f_reqs_rv[164:101] - rg_addr_base ;
assign f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127 =
f_reqs_rv[164:101] < rg_addr_lim ;
assign f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122 =
f_reqs_rv[92:90] == 3'b0 ||
f_reqs_rv[92:90] == 3'b001 && !f_reqs_rv[101] ||
f_reqs_rv[92:90] == 3'b010 && f_reqs_rv[102:101] == 2'h0 ||
f_reqs_rv[92:90] == 3'b011 && f_reqs_rv[103:101] == 3'h0 ||
f_reqs_rv[92:90] == 3'b100 && f_reqs_rv[104:101] == 4'h0 ||
f_reqs_rv[92:90] == 3'b101 && f_reqs_rv[105:101] == 5'h0 ||
f_reqs_rv[92:90] == 3'b110 && f_reqs_rv[106:101] == 6'h0 ||
f_reqs_rv[92:90] == 3'b111 && f_reqs_rv[107:101] == 7'h0 ;
assign mask__h5802 =
{ SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190,
SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193,
SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197,
SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200,
SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204,
SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207,
SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211,
SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 } ;
assign n__h4996 = { 3'd0, f_reqs_rv[105:104] } ;
assign req_raw_mem_addr__h3185 =
{ 5'd0,
f_reqs_rv_BITS_164_TO_101_MINUS_rg_addr_base__q1[63:5] } ;
assign rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 =
rg_addr_base <= f_reqs_rv[164:101] ;
assign rg_cached_raw_mem_addr_0_EQ_0_CONCAT_f_reqs_rv_ETC___d134 =
rg_cached_raw_mem_addr == req_raw_mem_addr__h3185 ;
assign rg_state_EQ_3_3_AND_NOT_f_reqs_rv_port0__read__ETC___d283 =
rg_state == 2'd3 &&
(NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278 ||
!rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 ||
!f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127) ;
assign rg_state_EQ_3_3_AND_f_reqs_rv_port0__read__2_B_ETC___d130 =
rg_state == 2'd3 &&
f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122 &&
rg_addr_base_23_ULE_f_reqs_rv_port0__read__2_B_ETC___d125 &&
f_reqs_rv_port0__read__2_BITS_164_TO_101_24_UL_ETC___d127 ;
assign rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 =
rg_watch_tohost && f_reqs_rv[164:101] == rg_tohost_addr &&
f_reqs_rv[63:0] != 64'd0 ;
assign updated_word64__h5803 = x__h6185 | y__h6186 ;
assign x__h6185 = word64_old__h5797 & y__h6187 ;
assign y__h6186 = f_reqs_rv[63:0] & mask__h5802 ;
assign y__h6187 =
{ ~SEXT_f_reqs_rv_port0__read__2_BIT_71_89___d190,
~SEXT_f_reqs_rv_port0__read__2_BIT_70_92___d193,
~SEXT_f_reqs_rv_port0__read__2_BIT_69_96___d197,
~SEXT_f_reqs_rv_port0__read__2_BIT_68_99___d200,
~SEXT_f_reqs_rv_port0__read__2_BIT_67_03___d204,
~SEXT_f_reqs_rv_port0__read__2_BIT_66_06___d207,
~SEXT_f_reqs_rv_port0__read__2_BIT_65_10___d211,
~SEXT_f_reqs_rv_port0__read__2_BIT_64_13___d214 } ;
always@(f_reqs_rv or rg_cached_raw_mem_word)
begin
case (f_reqs_rv[105:104])
2'd0: word64_old__h5797 = rg_cached_raw_mem_word[63:0];
2'd1: word64_old__h5797 = rg_cached_raw_mem_word[127:64];
2'd2: word64_old__h5797 = rg_cached_raw_mem_word[191:128];
2'd3: word64_old__h5797 = rg_cached_raw_mem_word[255:192];
endcase
end
always@(n__h4996 or rg_cached_raw_mem_word)
begin
case (n__h4996)
5'd0: rdata__h4997 = rg_cached_raw_mem_word[63:0];
5'd1: rdata__h4997 = rg_cached_raw_mem_word[127:64];
5'd2: rdata__h4997 = rg_cached_raw_mem_word[191:128];
5'd3: rdata__h4997 = rg_cached_raw_mem_word[255:192];
default: rdata__h4997 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY
354'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
f_reqs_rv <= `BSV_ASSIGNMENT_DELAY
171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_state <= `BSV_ASSIGNMENT_DELAY 2'd0;
rg_status <= `BSV_ASSIGNMENT_DELAY 8'd0;
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000;
rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (f_raw_mem_reqs_rv$EN)
f_raw_mem_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_reqs_rv$D_IN;
if (f_raw_mem_rsps_rv$EN)
f_raw_mem_rsps_rv <= `BSV_ASSIGNMENT_DELAY f_raw_mem_rsps_rv$D_IN;
if (f_reqs_rv$EN) f_reqs_rv <= `BSV_ASSIGNMENT_DELAY f_reqs_rv$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
if (rg_status$EN) rg_status <= `BSV_ASSIGNMENT_DELAY rg_status$D_IN;
if (rg_tohost_addr$EN)
rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN;
if (rg_watch_tohost$EN)
rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN;
end
if (rg_addr_base$EN)
rg_addr_base <= `BSV_ASSIGNMENT_DELAY rg_addr_base$D_IN;
if (rg_addr_lim$EN) rg_addr_lim <= `BSV_ASSIGNMENT_DELAY rg_addr_lim$D_IN;
if (rg_cached_clean$EN)
rg_cached_clean <= `BSV_ASSIGNMENT_DELAY rg_cached_clean$D_IN;
if (rg_cached_raw_mem_addr$EN)
rg_cached_raw_mem_addr <= `BSV_ASSIGNMENT_DELAY
rg_cached_raw_mem_addr$D_IN;
if (rg_cached_raw_mem_word$EN)
rg_cached_raw_mem_word <= `BSV_ASSIGNMENT_DELAY
rg_cached_raw_mem_word$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
f_raw_mem_reqs_rv =
354'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
f_raw_mem_rsps_rv =
257'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
f_reqs_rv = 171'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_addr_base = 64'hAAAAAAAAAAAAAAAA;
rg_addr_lim = 64'hAAAAAAAAAAAAAAAA;
rg_cached_clean = 1'h0;
rg_cached_raw_mem_addr = 64'hAAAAAAAAAAAAAAAA;
rg_cached_raw_mem_word =
256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
rg_state = 2'h2;
rg_status = 8'hAA;
rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA;
rg_watch_tohost = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_reload_cache &&
NOT_cfg_verbosity_read_ULE_1___d5)
begin
v__h2421 = $stime;
#0;
end
v__h2415 = v__h2421 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset_reload_cache &&
NOT_cfg_verbosity_read_ULE_1___d5)
$display("%0d: Mem_Controller.rl_reset_reload_cache => STATE_RELOADING",
v__h2415);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_dirty_idle &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
begin
v__h3360 = $stime;
#0;
end
v__h3354 = v__h3360 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_dirty_idle &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$display("%0d: Mem_Controller.rl_writeback_dirty_idle to raw addr 0x%0h",
v__h3354,
rg_cached_raw_mem_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_dirty &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
begin
v__h3856 = $stime;
#0;
end
v__h3850 = v__h3856 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_writeback_dirty &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$display("%0d: Mem_Controller.rl_writeback_dirty to raw addr 0x%0h",
v__h3850,
rg_cached_raw_mem_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_miss_clean_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
begin
v__h4337 = $stime;
#0;
end
v__h4331 = v__h4337 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_miss_clean_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$display("%0d: Mem_Controller.rl_miss_clean_req: read raw addr 0x%0h",
v__h4331,
req_raw_mem_addr__h3185);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33)
begin
v__h4626 = $stime;
#0;
end
v__h4620 = v__h4626 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33)
$display("%0d: Mem_Controller.rl_reload: raw addr 0x%0h",
v__h4620,
rg_cached_raw_mem_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", f_raw_mem_rsps_rv[255:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reload && NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
begin
v__h5342 = $stime;
#0;
end
v__h5336 = v__h5342 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$display("%0d: Mem_Controller.rl_process_rd_req: ", v__h5336);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("Req { ", "req_op: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("REQ_OP_RD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[164:101]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "len: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[100:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "size: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[92:90]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "burst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[89:88]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "lock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[87]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "cache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[86:83]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "prot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[82:80]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "qos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[79:76]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "region: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[75:72]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "user: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[71:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(" => ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", rdata__h4997);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", 2'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_rd_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
begin
v__h7563 = $stime;
#0;
end
v__h7557 = v__h7563 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$display("%0d: Mem_Controller.rl_process_wr_req: ", v__h7557);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("Req { ", "req_op: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("REQ_OP_WR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[164:101]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "len: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[100:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "size: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[92:90]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "burst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[89:88]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "lock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[87]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "cache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[86:83]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "prot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[82:80]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "qos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[79:76]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "region: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[75:72]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "user: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[71:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(" => ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", 2'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req && NOT_cfg_verbosity_read_ULE_1___d5)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242)
begin
v__h7771 = $stime;
#0;
end
v__h7765 = v__h7771 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242)
$display("%0d: Mem_Controller.rl_process_wr_req: addr 0x%0h (<tohost>) data 0x%0h",
v__h7765,
f_reqs_rv[164:101],
f_reqs_rv[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 &&
f_reqs_rv[63:1] == 63'd0)
$display("PASS");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_process_wr_req &&
rg_watch_tohost_36_AND_f_reqs_rv_port0__read___ETC___d242 &&
f_reqs_rv[63:1] != 63'd0)
$display("FAIL %0d", exit_value__h7817);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
begin
v__h8284 = $stime;
#0;
end
v__h8278 = v__h8284 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("%0d: ERROR: Mem_Controller:", v__h8278);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address &&
NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278)
$display(" read-addr is misaligned");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address &&
f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122)
$display(" read-addr is out of bounds");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h",
rg_addr_base,
rg_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("Req { ", "req_op: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("REQ_OP_RD");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[164:101]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "len: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[100:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "size: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[92:90]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "burst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[89:88]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "lock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", f_reqs_rv[87]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "cache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[86:83]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "prot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[82:80]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "qos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[79:76]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "region: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[75:72]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "user: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[71:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(" => ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address)
$write("'h%h", f_reqs_rv[164:101]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_rd_address) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
begin
v__h9087 = $stime;
#0;
end
v__h9081 = v__h9087 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("%0d: ERROR: Mem_Controller:", v__h9081);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address &&
NOT_f_reqs_rv_port0__read__2_BITS_92_TO_90_6_E_ETC___d278)
$display(" write-addr is misaligned");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address &&
f_reqs_rv_port0__read__2_BITS_92_TO_90_6_EQ_0b_ETC___d122)
$display(" write-addr is out of bounds");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$display(" rg_addr_base 0x%0h rg_addr_lim 0x%0h",
rg_addr_base,
rg_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("Req { ", "req_op: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("REQ_OP_WR");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "id: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "addr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[164:101]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "len: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[100:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "size: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[92:90]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "burst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[89:88]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "lock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", f_reqs_rv[87]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "cache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[86:83]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "prot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[82:80]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "qos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[79:76]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "region: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[75:72]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "user: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[71:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "data: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[63:0], " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(" => ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address)
$write("'h%h", f_reqs_rv[168:165]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_invalid_wr_address) $write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map)
begin
v__h9718 = $stime;
#0;
end
v__h9712 = v__h9718 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_set_addr_map)
$display("%0d: Mem_Controller.set_addr_map: addr_base 0x%0h addr_lim 0x%0h",
v__h9712,
set_addr_map_addr_base,
set_addr_map_addr_lim);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
begin
v__h2729 = $stime;
#0;
end
v__h2723 = v__h2729 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$display("%0d: Mem_Controller.rl_merge_rd_req", v__h2723);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_rd_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
begin
v__h3055 = $stime;
#0;
end
v__h3049 = v__h3055 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$display("%0d: Mem_Controller.rl_merge_wr_req", v__h3049);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[96:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", slave_xactor_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33 &&
slave_xactor_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33 &&
!slave_xactor_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_merge_wr_req &&
NOT_cfg_verbosity_read_ULE_2_2___d33)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5)
begin
v__h1680 = $stime;
#0;
end
v__h1674 = v__h1680 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_power_on_reset && NOT_cfg_verbosity_read_ULE_1___d5)
$display("%0d: Mem_Controller.rl_power_on_reset", v__h1674);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5)
begin
v__h1988 = $stime;
#0;
end
v__h1982 = v__h1988 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_external_reset && NOT_cfg_verbosity_read_ULE_1___d5)
$display("%0d: Mem_Controller.rl_external_reset => STATE_RESET_RELOAD_CACHE",
v__h1982);
end
// synopsys translate_on
endmodule // mkMem_Controller
|
//-----------------------------------------------------------------------------
// The FPGA is responsible for interfacing between the A/D, the coil drivers,
// and the ARM. In the low-frequency modes it passes the data straight
// through, so that the ARM gets raw A/D samples over the SSP. In the high-
// frequency modes, the FPGA might perform some demodulation first, to
// reduce the amount of data that we must send to the ARM.
//
// I am not really an FPGA/ASIC designer, so I am sure that a lot of this
// could be improved.
//
// Jonathan Westhues, March 2006
// Added ISO14443-A support by Gerhard de Koning Gans, April 2008
// iZsh <izsh at fail0verflow.com>, June 2014
//-----------------------------------------------------------------------------
// Defining commands, modes and options. This must be aligned to the definitions in fpgaloader.h
// Note: the definitions here are without shifts
// Commands:
`define FPGA_CMD_SET_CONFREG 1
`define FPGA_CMD_TRACE_ENABLE 2
// Major modes:
`define FPGA_MAJOR_MODE_LF_ADC 0
`define FPGA_MAJOR_MODE_LF_EDGE_DETECT 1
`define FPGA_MAJOR_MODE_LF_PASSTHRU 2
`define FPGA_MAJOR_MODE_HF_READER 0
`define FPGA_MAJOR_MODE_HF_SIMULATOR 1
`define FPGA_MAJOR_MODE_HF_ISO14443A 2
`define FPGA_MAJOR_MODE_HF_SNOOP 3
`define FPGA_MAJOR_MODE_HF_GET_TRACE 4
`define FPGA_MAJOR_MODE_OFF 7
// Options for the generic HF reader
`define FPGA_HF_READER_MODE_RECEIVE_IQ 0
`define FPGA_HF_READER_MODE_RECEIVE_AMPLITUDE 1
`define FPGA_HF_READER_MODE_RECEIVE_PHASE 2
`define FPGA_HF_READER_MODE_SEND_FULL_MOD 3
`define FPGA_HF_READER_MODE_SEND_SHALLOW_MOD 4
`define FPGA_HF_READER_MODE_SNIFF_IQ 5
`define FPGA_HF_READER_MODE_SNIFF_AMPLITUDE 6
`define FPGA_HF_READER_MODE_SNIFF_PHASE 7
`define FPGA_HF_READER_MODE_SEND_JAM 8
`define FPGA_HF_READER_SUBCARRIER_848_KHZ 0
`define FPGA_HF_READER_SUBCARRIER_424_KHZ 1
`define FPGA_HF_READER_SUBCARRIER_212_KHZ 2
// Options for the HF simulated tag, how to modulate
`define FPGA_HF_SIMULATOR_NO_MODULATION 0
`define FPGA_HF_SIMULATOR_MODULATE_BPSK 1
`define FPGA_HF_SIMULATOR_MODULATE_212K 2
`define FPGA_HF_SIMULATOR_MODULATE_424K 4
`define FPGA_HF_SIMULATOR_MODULATE_424K_8BIT 5
// Options for ISO14443A
`define FPGA_HF_ISO14443A_SNIFFER 0
`define FPGA_HF_ISO14443A_TAGSIM_LISTEN 1
`define FPGA_HF_ISO14443A_TAGSIM_MOD 2
`define FPGA_HF_ISO14443A_READER_LISTEN 3
`define FPGA_HF_ISO14443A_READER_MOD 4
`include "hi_reader.v"
`include "hi_simulate.v"
`include "hi_iso14443a.v"
`include "hi_sniffer.v"
`include "hi_get_trace.v"
`include "util.v"
module fpga_hf(
input spck, output miso, input mosi, input ncs,
input pck0, input ck_1356meg, input ck_1356megb,
output pwr_lo, output pwr_hi,
output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
input [7:0] adc_d, output adc_clk, output adc_noe,
output ssp_frame, output ssp_din, input ssp_dout, output ssp_clk,
input cross_hi, input cross_lo,
output dbg
);
//-----------------------------------------------------------------------------
// The SPI receiver. This sets up the configuration word, which the rest of
// the logic looks at to determine how to connect the A/D and the coil
// drivers (i.e., which section gets it). Also assign some symbolic names
// to the configuration bits, for use below.
//-----------------------------------------------------------------------------
reg [15:0] shift_reg;
reg [8:0] conf_word;
reg trace_enable;
// We switch modes between transmitting to the 13.56 MHz tag and receiving
// from it, which means that we must make sure that we can do so without
// glitching, or else we will glitch the transmitted carrier.
always @(posedge ncs)
begin
case(shift_reg[15:12])
`FPGA_CMD_SET_CONFREG: conf_word <= shift_reg[8:0];
`FPGA_CMD_TRACE_ENABLE: trace_enable <= shift_reg[0];
endcase
end
always @(posedge spck)
begin
if(~ncs)
begin
shift_reg[15:1] <= shift_reg[14:0];
shift_reg[0] <= mosi;
end
end
// select module (outputs) based on major mode
wire [2:0] major_mode = conf_word[8:6];
// configuring the HF reader
wire [1:0] subcarrier_frequency = conf_word[5:4];
wire [3:0] minor_mode = conf_word[3:0];
//-----------------------------------------------------------------------------
// And then we instantiate the modules corresponding to each of the FPGA's
// major modes, and use muxes to connect the outputs of the active mode to
// the output pins.
//-----------------------------------------------------------------------------
hi_reader hr(
ck_1356megb,
hr_pwr_lo, hr_pwr_hi, hr_pwr_oe1, hr_pwr_oe2, hr_pwr_oe3, hr_pwr_oe4,
adc_d, hr_adc_clk,
hr_ssp_frame, hr_ssp_din, ssp_dout, hr_ssp_clk,
hr_dbg,
subcarrier_frequency, minor_mode
);
hi_simulate hs(
ck_1356meg,
hs_pwr_lo, hs_pwr_hi, hs_pwr_oe1, hs_pwr_oe2, hs_pwr_oe3, hs_pwr_oe4,
adc_d, hs_adc_clk,
hs_ssp_frame, hs_ssp_din, ssp_dout, hs_ssp_clk,
hs_dbg,
minor_mode
);
hi_iso14443a hisn(
ck_1356meg,
hisn_pwr_lo, hisn_pwr_hi, hisn_pwr_oe1, hisn_pwr_oe2, hisn_pwr_oe3, hisn_pwr_oe4,
adc_d, hisn_adc_clk,
hisn_ssp_frame, hisn_ssp_din, ssp_dout, hisn_ssp_clk,
hisn_dbg,
minor_mode
);
hi_sniffer he(
ck_1356megb,
he_pwr_lo, he_pwr_hi, he_pwr_oe1, he_pwr_oe2, he_pwr_oe3, he_pwr_oe4,
adc_d, he_adc_clk,
he_ssp_frame, he_ssp_din, he_ssp_clk
);
hi_get_trace gt(
ck_1356megb,
adc_d, trace_enable, major_mode,
gt_ssp_frame, gt_ssp_din, gt_ssp_clk
);
// Major modes:
// 000 -- HF reader; subcarrier frequency and modulation depth selectable
// 001 -- HF simulated tag
// 010 -- HF ISO14443-A
// 011 -- HF Snoop
// 100 -- HF get trace
// 111 -- everything off
mux8 mux_ssp_clk (major_mode, ssp_clk, hr_ssp_clk, hs_ssp_clk, hisn_ssp_clk, he_ssp_clk, gt_ssp_clk, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_din (major_mode, ssp_din, hr_ssp_din, hs_ssp_din, hisn_ssp_din, he_ssp_din, gt_ssp_din, 1'b0, 1'b0, 1'b0);
mux8 mux_ssp_frame (major_mode, ssp_frame, hr_ssp_frame, hs_ssp_frame, hisn_ssp_frame, he_ssp_frame, gt_ssp_frame, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe1 (major_mode, pwr_oe1, hr_pwr_oe1, hs_pwr_oe1, hisn_pwr_oe1, he_pwr_oe1, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe2 (major_mode, pwr_oe2, hr_pwr_oe2, hs_pwr_oe2, hisn_pwr_oe2, he_pwr_oe2, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe3 (major_mode, pwr_oe3, hr_pwr_oe3, hs_pwr_oe3, hisn_pwr_oe3, he_pwr_oe3, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_oe4 (major_mode, pwr_oe4, hr_pwr_oe4, hs_pwr_oe4, hisn_pwr_oe4, he_pwr_oe4, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_lo (major_mode, pwr_lo, hr_pwr_lo, hs_pwr_lo, hisn_pwr_lo, he_pwr_lo, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_pwr_hi (major_mode, pwr_hi, hr_pwr_hi, hs_pwr_hi, hisn_pwr_hi, he_pwr_hi, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_adc_clk (major_mode, adc_clk, hr_adc_clk, hs_adc_clk, hisn_adc_clk, he_adc_clk, 1'b0, 1'b0, 1'b0, 1'b0);
mux8 mux_dbg (major_mode, dbg, hr_dbg, hs_dbg, hisn_dbg, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0);
// In all modes, let the ADC's outputs be enabled.
assign adc_noe = 1'b0;
// not used
assign miso = 1'b0;
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk or posedge rst) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O32AI_4_V
`define SKY130_FD_SC_LS__O32AI_4_V
/**
* o32ai: 3-input OR and 2-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & (B1 | B2))
*
* Verilog wrapper for o32ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o32ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o32ai_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o32ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O32AI_4_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:50:10 11/03/2014
// Design Name:
// Module Name: Output_2_Disp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Multi_8CH32(input clk,
input rst,
input EN, //Write EN
input[2:0]Test, //ALU&Clock,SW[7:5]
input[63:0]point_in, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öСÊýµã
input[63:0]LES, //Õë¶Ô8λÏÔʾÊäÈë¸÷8¸öÉÁ˸λ
input[31:0] Data0, //disp_cpudata
input[31:0] data1,
input[31:0] data2,
input[31:0] data3,
input[31:0] data4,
input[31:0] data5,
input[31:0] data6,
input[31:0] data7,
output [7:0] point_out,
output [7:0] LE_out,
output [31:0]Disp_num
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_1_V
`define SKY130_FD_SC_MS__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_1_V
|
/***********************************************************
-- (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/mc_phy.v#5 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is a parameterizable wrapper instantiating
// up to 5 memory banks of 4-lane phy primitives. There
// There are always 2 control banks leaving 18 lanes for data.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
////////////////////////////////////////////////////////////
***********************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_mc_phy
#(
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane data=1/ctl=0
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter RCLK_SELECT_BANK = 0,
parameter RCLK_SELECT_LANE = "B",
parameter RCLK_SELECT_EDGE = 4'b1111,
parameter GENERATE_DDR_CK_MAP = "0B",
parameter BYTELANES_DDR_CK = 72'h00_0000_0000_0000_0002,
parameter USE_PRE_POST_FIFO = "TRUE",
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PI_SEL_CLK_OFFSET = 6,
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter PHY_CLK_RATIO = 4, // phy to controller divide ratio
// common to all i/o banks
parameter PHY_FOUR_WINDOW_CLOCKS = 63,
parameter PHY_EVENTS_DELAY = 18,
parameter PHY_COUNT_EN = "TRUE",
parameter PHY_SYNC_MODE = "TRUE",
parameter PHY_DISABLE_SEQ_MATCH = "FALSE",
parameter MASTER_PHY_CTL = 0,
// common to instance 0
parameter PHY_0_BITLANES = 48'hdffd_fffe_dfff,
parameter PHY_0_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_0_LANE_REMAP = 16'h3210,
parameter PHY_0_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_0_IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter NUM_DDR_CK = 1,
parameter PHY_0_DATA_CTL = DATA_CTL_B0,
parameter PHY_0_CMD_OFFSET = 0,
parameter PHY_0_RD_CMD_OFFSET_0 = 0,
parameter PHY_0_RD_CMD_OFFSET_1 = 0,
parameter PHY_0_RD_CMD_OFFSET_2 = 0,
parameter PHY_0_RD_CMD_OFFSET_3 = 0,
parameter PHY_0_RD_DURATION_0 = 0,
parameter PHY_0_RD_DURATION_1 = 0,
parameter PHY_0_RD_DURATION_2 = 0,
parameter PHY_0_RD_DURATION_3 = 0,
parameter PHY_0_WR_CMD_OFFSET_0 = 0,
parameter PHY_0_WR_CMD_OFFSET_1 = 0,
parameter PHY_0_WR_CMD_OFFSET_2 = 0,
parameter PHY_0_WR_CMD_OFFSET_3 = 0,
parameter PHY_0_WR_DURATION_0 = 0,
parameter PHY_0_WR_DURATION_1 = 0,
parameter PHY_0_WR_DURATION_2 = 0,
parameter PHY_0_WR_DURATION_3 = 0,
parameter PHY_0_AO_WRLVL_EN = 0,
parameter PHY_0_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PHY_0_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_0_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_0_A_PI_FREQ_REF_DIV = "NONE",
parameter PHY_0_A_PI_CLKOUT_DIV = 2,
parameter PHY_0_A_PO_CLKOUT_DIV = 2,
parameter PHY_0_A_BURST_MODE = "TRUE",
parameter PHY_0_A_PI_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter PHY_0_A_PO_OCLK_DELAY = 25,
parameter PHY_0_B_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_C_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_D_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_0_A_PO_OCLKDELAY_INV = "FALSE",
parameter PHY_0_A_OF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_IF_ARRAY_MODE = "ARRAY_MODE_8_X_4",
parameter PHY_0_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_0_A_OSERDES_DATA_RATE = "UNDECLARED",
parameter PHY_0_A_OSERDES_DATA_WIDTH = "UNDECLARED",
parameter PHY_0_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_0_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_0_A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter PHY_0_A_IDELAYE2_IDELAY_VALUE = 00,
parameter PHY_0_B_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_B_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_C_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_C_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_D_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_0_D_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
// common to instance 1
parameter PHY_1_BITLANES = PHY_0_BITLANES,
parameter PHY_1_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_1_LANE_REMAP = 16'h3210,
parameter PHY_1_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_1_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_1_DATA_CTL = DATA_CTL_B1,
parameter PHY_1_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_1_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_1_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_1_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_1_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_1_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_1_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_1_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_1_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_1_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_1_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_1_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_1_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_1_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_1_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_1_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_1_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_1_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_1_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_1_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_1_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_1_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_1_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV,
parameter PHY_1_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_1_A_BURST_MODE = PHY_0_A_BURST_MODE,
parameter PHY_1_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_1_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC ,
parameter PHY_1_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_1_B_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_C_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_D_PO_OCLK_DELAY = PHY_1_A_PO_OCLK_DELAY,
parameter PHY_1_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_1_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_B_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_B_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_C_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_C_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_D_IDELAYE2_IDELAY_TYPE = PHY_1_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_1_D_IDELAYE2_IDELAY_VALUE = PHY_1_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_1_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_1_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_1_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_1_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_1_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
// common to instance 2
parameter PHY_2_BITLANES = PHY_0_BITLANES,
parameter PHY_2_BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter PHY_2_LANE_REMAP = 16'h3210,
parameter PHY_2_GENERATE_IDELAYCTRL = "FALSE",
parameter PHY_2_IODELAY_GRP = PHY_0_IODELAY_GRP,
parameter PHY_2_DATA_CTL = DATA_CTL_B2,
parameter PHY_2_CMD_OFFSET = PHY_0_CMD_OFFSET,
parameter PHY_2_RD_CMD_OFFSET_0 = PHY_0_RD_CMD_OFFSET_0,
parameter PHY_2_RD_CMD_OFFSET_1 = PHY_0_RD_CMD_OFFSET_1,
parameter PHY_2_RD_CMD_OFFSET_2 = PHY_0_RD_CMD_OFFSET_2,
parameter PHY_2_RD_CMD_OFFSET_3 = PHY_0_RD_CMD_OFFSET_3,
parameter PHY_2_RD_DURATION_0 = PHY_0_RD_DURATION_0,
parameter PHY_2_RD_DURATION_1 = PHY_0_RD_DURATION_1,
parameter PHY_2_RD_DURATION_2 = PHY_0_RD_DURATION_2,
parameter PHY_2_RD_DURATION_3 = PHY_0_RD_DURATION_3,
parameter PHY_2_WR_CMD_OFFSET_0 = PHY_0_WR_CMD_OFFSET_0,
parameter PHY_2_WR_CMD_OFFSET_1 = PHY_0_WR_CMD_OFFSET_1,
parameter PHY_2_WR_CMD_OFFSET_2 = PHY_0_WR_CMD_OFFSET_2,
parameter PHY_2_WR_CMD_OFFSET_3 = PHY_0_WR_CMD_OFFSET_3,
parameter PHY_2_WR_DURATION_0 = PHY_0_WR_DURATION_0,
parameter PHY_2_WR_DURATION_1 = PHY_0_WR_DURATION_1,
parameter PHY_2_WR_DURATION_2 = PHY_0_WR_DURATION_2,
parameter PHY_2_WR_DURATION_3 = PHY_0_WR_DURATION_3,
parameter PHY_2_AO_WRLVL_EN = PHY_0_AO_WRLVL_EN,
parameter PHY_2_AO_TOGGLE = PHY_0_AO_TOGGLE, // odd bits are toggle (CKE)
parameter PHY_2_OF_ALMOST_FULL_VALUE = 1,
parameter PHY_2_IF_ALMOST_EMPTY_VALUE = 1,
// per lane parameters
parameter PHY_2_A_PI_FREQ_REF_DIV = PHY_0_A_PI_FREQ_REF_DIV,
parameter PHY_2_A_PI_CLKOUT_DIV = PHY_0_A_PI_CLKOUT_DIV ,
parameter PHY_2_A_PO_CLKOUT_DIV = PHY_0_A_PO_CLKOUT_DIV,
parameter PHY_2_A_BURST_MODE = PHY_0_A_BURST_MODE ,
parameter PHY_2_A_PI_OUTPUT_CLK_SRC = PHY_0_A_PI_OUTPUT_CLK_SRC,
parameter PHY_2_A_PO_OUTPUT_CLK_SRC = PHY_0_A_PO_OUTPUT_CLK_SRC,
parameter PHY_2_A_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_B_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_OF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_IF_ARRAY_MODE = PHY_0_A_IF_ARRAY_MODE,
parameter PHY_2_B_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_C_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_D_IF_ARRAY_MODE = PHY_0_A_OF_ARRAY_MODE,
parameter PHY_2_A_PO_OCLK_DELAY = PHY_0_A_PO_OCLK_DELAY,
parameter PHY_2_B_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_C_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_D_PO_OCLK_DELAY = PHY_2_A_PO_OCLK_DELAY,
parameter PHY_2_A_PO_OCLKDELAY_INV = PHY_0_A_PO_OCLKDELAY_INV,
parameter PHY_2_A_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_A_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_B_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_B_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_C_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_C_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_D_OSERDES_DATA_RATE = PHY_0_A_OSERDES_DATA_RATE,
parameter PHY_2_D_OSERDES_DATA_WIDTH = PHY_0_A_OSERDES_DATA_WIDTH,
parameter PHY_2_A_IDELAYE2_IDELAY_TYPE = PHY_0_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_A_IDELAYE2_IDELAY_VALUE = PHY_0_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_B_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_B_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_C_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_C_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_2_D_IDELAYE2_IDELAY_TYPE = PHY_2_A_IDELAYE2_IDELAY_TYPE,
parameter PHY_2_D_IDELAYE2_IDELAY_VALUE = PHY_2_A_IDELAYE2_IDELAY_VALUE,
parameter PHY_0_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) || (BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : "TRUE",
parameter PHY_1_IS_LAST_BANK = ((BYTE_LANES_B1 != 0) && ((BYTE_LANES_B2 != 0) || (BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0))) ? "FALSE" : ((PHY_0_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter PHY_2_IS_LAST_BANK = (BYTE_LANES_B2 != 0) && ((BYTE_LANES_B3 != 0) || (BYTE_LANES_B4 != 0)) ? "FALSE" : ((PHY_0_IS_LAST_BANK || PHY_1_IS_LAST_BANK) ? "FALSE" : "TRUE"),
parameter TCK = 2500,
// local computational use, do not pass down
parameter N_LANES = (0+BYTE_LANES_B0[0]) + (0+BYTE_LANES_B0[1]) + (0+BYTE_LANES_B0[2]) + (0+BYTE_LANES_B0[3])
+ (0+BYTE_LANES_B1[0]) + (0+BYTE_LANES_B1[1]) + (0+BYTE_LANES_B1[2]) + (0+BYTE_LANES_B1[3]) + (0+BYTE_LANES_B2[0]) + (0+BYTE_LANES_B2[1]) + (0+BYTE_LANES_B2[2]) + (0+BYTE_LANES_B2[3])
, // must not delete comma for syntax
parameter HIGHEST_BANK = (BYTE_LANES_B4 != 0 ? 5 : (BYTE_LANES_B3 != 0 ? 4 : (BYTE_LANES_B2 != 0 ? 3 : (BYTE_LANES_B1 != 0 ? 2 : 1)))),
parameter HIGHEST_LANE_B0 = ((PHY_0_IS_LAST_BANK == "FALSE") ? 4 : BYTE_LANES_B0[3] ? 4 : BYTE_LANES_B0[2] ? 3 : BYTE_LANES_B0[1] ? 2 : BYTE_LANES_B0[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B1 = (HIGHEST_BANK > 2) ? 4 : ( BYTE_LANES_B1[3] ? 4 : BYTE_LANES_B1[2] ? 3 : BYTE_LANES_B1[1] ? 2 : BYTE_LANES_B1[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B2 = (HIGHEST_BANK > 3) ? 4 : ( BYTE_LANES_B2[3] ? 4 : BYTE_LANES_B2[2] ? 3 : BYTE_LANES_B2[1] ? 2 : BYTE_LANES_B2[0] ? 1 : 0) ,
parameter HIGHEST_LANE_B3 = 0,
parameter HIGHEST_LANE_B4 = 0,
parameter HIGHEST_LANE = (HIGHEST_LANE_B4 != 0) ? (HIGHEST_LANE_B4+16) : ((HIGHEST_LANE_B3 != 0) ? (HIGHEST_LANE_B3 + 12) : ((HIGHEST_LANE_B2 != 0) ? (HIGHEST_LANE_B2 + 8) : ((HIGHEST_LANE_B1 != 0) ? (HIGHEST_LANE_B1 + 4) : HIGHEST_LANE_B0))),
parameter LP_DDR_CK_WIDTH = 2,
parameter GENERATE_SIGNAL_SPLIT = "FALSE"
,parameter CKE_ODT_AUX = "FALSE"
)
(
input rst,
input ddr_rst_in_n ,
input phy_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input auxout_clk,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input [31:0] phy_ctl_wd,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input phy_ctl_wr,
input if_rst,
input if_empty_def,
input cke_in,
input idelay_ce,
input idelay_ld,
input idelay_inc,
input phyGo,
input input_sink,
output if_a_empty,
output if_empty /* synthesis syn_maxfan = 3 */,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0] phy_din,
output phy_ctl_a_full,
output wire [3:0] phy_ctl_full,
output [HIGHEST_LANE*12-1:0] mem_dq_out,
output [HIGHEST_LANE*12-1:0] mem_dq_ts,
input [HIGHEST_LANE*10-1:0] mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
(* IOB = "FORCE" *) output reg [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out, // to memory, odt , 4 per phy controller
output phy_ctl_ready, // to fabric
output reg rst_out, // to memory
output [(NUM_DDR_CK * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
// output rclk,
output mcGo,
output ref_dll_lock,
// calibration signals
input phy_write_calib,
input phy_read_calib,
input [5:0] calib_sel,
input [HIGHEST_BANK-1:0]calib_zero_inputs, // bit calib_sel[2], one per bank
input [HIGHEST_BANK-1:0]calib_zero_ctrl, // one bit per bank, zero's only control lane calibration inputs
input [HIGHEST_LANE-1:0] calib_zero_lanes, // one bit per lane
input calib_in_common,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
input po_counter_read_en,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_phase_locked,
output pi_phase_locked_all,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
input [29:0] fine_delay,
input fine_delay_sel
);
wire [7:0] calib_zero_inputs_int ;
wire [HIGHEST_BANK*4-1:0] calib_zero_lanes_int ;
//Added the temporary variable for concadination operation
wire [2:0] calib_sel_byte0 ;
wire [2:0] calib_sel_byte1 ;
wire [2:0] calib_sel_byte2 ;
wire [4:0] po_coarse_overflow_w;
wire [4:0] po_fine_overflow_w;
wire [8:0] po_counter_read_val_w[4:0];
wire [4:0] pi_fine_overflow_w;
wire [5:0] pi_counter_read_val_w[4:0];
wire [4:0] pi_dqs_found_w;
wire [4:0] pi_dqs_found_all_w;
wire [4:0] pi_dqs_found_any_w;
wire [4:0] pi_dqs_out_of_range_w;
wire [4:0] pi_phase_locked_w;
wire [4:0] pi_phase_locked_all_w;
wire [4:0] rclk_w;
wire [HIGHEST_BANK-1:0] phy_ctl_ready_w;
wire [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk_w [HIGHEST_BANK-1:0];
wire [(((HIGHEST_LANE+3)/4)*4)-1:0] aux_out_;
wire [3:0] if_q0;
wire [3:0] if_q1;
wire [3:0] if_q2;
wire [3:0] if_q3;
wire [3:0] if_q4;
wire [7:0] if_q5;
wire [7:0] if_q6;
wire [3:0] if_q7;
wire [3:0] if_q8;
wire [3:0] if_q9;
wire [31:0] _phy_ctl_wd;
wire [3:0] aux_in_[4:1];
wire [3:0] rst_out_w;
wire freq_refclk_split;
wire mem_refclk_split;
wire mem_refclk_div4_split;
wire sync_pulse_split;
wire phy_clk_split0;
wire phy_ctl_clk_split0;
wire [31:0] phy_ctl_wd_split0;
wire phy_ctl_wr_split0;
wire phy_ctl_clk_split1;
wire phy_clk_split1;
wire [31:0] phy_ctl_wd_split1;
wire phy_ctl_wr_split1;
wire [5:0] phy_data_offset_1_split1;
wire phy_ctl_clk_split2;
wire phy_clk_split2;
wire [31:0] phy_ctl_wd_split2;
wire phy_ctl_wr_split2;
wire [5:0] phy_data_offset_2_split2;
wire [HIGHEST_LANE*80-1:0] phy_dout_split0;
wire phy_cmd_wr_en_split0;
wire phy_data_wr_en_split0;
wire phy_rd_en_split0;
wire [HIGHEST_LANE*80-1:0] phy_dout_split1;
wire phy_cmd_wr_en_split1;
wire phy_data_wr_en_split1;
wire phy_rd_en_split1;
wire [HIGHEST_LANE*80-1:0] phy_dout_split2;
wire phy_cmd_wr_en_split2;
wire phy_data_wr_en_split2;
wire phy_rd_en_split2;
wire phy_ctl_mstr_empty;
wire [HIGHEST_BANK-1:0] phy_ctl_empty;
wire _phy_ctl_a_full_f;
wire _phy_ctl_a_empty_f;
wire _phy_ctl_full_f;
wire _phy_ctl_empty_f;
wire [HIGHEST_BANK-1:0] _phy_ctl_a_full_p;
wire [HIGHEST_BANK-1:0] _phy_ctl_full_p;
wire [HIGHEST_BANK-1:0] of_ctl_a_full_v;
wire [HIGHEST_BANK-1:0] of_ctl_full_v;
wire [HIGHEST_BANK-1:0] of_data_a_full_v;
wire [HIGHEST_BANK-1:0] of_data_full_v;
wire [HIGHEST_BANK-1:0] pre_data_a_full_v;
wire [HIGHEST_BANK-1:0] if_empty_v;
wire [HIGHEST_BANK-1:0] byte_rd_en_v;
wire [HIGHEST_BANK*2-1:0] byte_rd_en_oth_banks;
wire [HIGHEST_BANK-1:0] if_empty_or_v;
wire [HIGHEST_BANK-1:0] if_empty_and_v;
wire [HIGHEST_BANK-1:0] if_a_empty_v;
localparam IF_ARRAY_MODE = "ARRAY_MODE_4_X_4";
localparam IF_SYNCHRONOUS_MODE = "FALSE";
localparam IF_SLOW_WR_CLK = "FALSE";
localparam IF_SLOW_RD_CLK = "FALSE";
localparam PHY_MULTI_REGION = (HIGHEST_BANK > 1) ? "TRUE" : "FALSE";
localparam RCLK_NEG_EDGE = 3'b000;
localparam RCLK_POS_EDGE = 3'b111;
localparam LP_PHY_0_BYTELANES_DDR_CK = BYTELANES_DDR_CK & 24'hFF_FFFF;
localparam LP_PHY_1_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 24) & 24'hFF_FFFF;
localparam LP_PHY_2_BYTELANES_DDR_CK = (BYTELANES_DDR_CK >> 48) & 24'hFF_FFFF;
// hi, lo positions for data offset field, MIG doesn't allow defines
localparam PC_DATA_OFFSET_RANGE_HI = 22;
localparam PC_DATA_OFFSET_RANGE_LO = 17;
/* Phaser_In Output source coding table
"PHASE_REF" : 4'b0000;
"DELAYED_MEM_REF" : 4'b0101;
"DELAYED_PHASE_REF" : 4'b0011;
"DELAYED_REF" : 4'b0001;
"FREQ_REF" : 4'b1000;
"MEM_REF" : 4'b0010;
*/
localparam RCLK_PI_OUTPUT_CLK_SRC = "DELAYED_MEM_REF";
localparam DDR_TCK = TCK;
localparam real FREQ_REF_PERIOD = DDR_TCK / (PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
localparam real L_FREQ_REF_PERIOD_NS = FREQ_REF_PERIOD /1000.0;
localparam PO_S3_TAPS = 64 ; // Number of taps per clock cycle in OCLK_DELAYED delay line
localparam PI_S2_TAPS = 128 ; // Number of taps per clock cycle in stage 2 delay line
localparam PO_S2_TAPS = 128 ; // Number of taps per clock cycle in sta
/*
Intrinsic delay of Phaser In Stage 1
@3300ps - 1.939ns - 58.8%
@2500ps - 1.657ns - 66.3%
@1875ps - 1.263ns - 67.4%
@1500ps - 1.021ns - 68.1%
@1250ps - 0.868ns - 69.4%
@1072ps - 0.752ns - 70.1%
@938ps - 0.667ns - 71.1%
*/
// If we use the Delayed Mem_Ref_Clk in the RCLK Phaser_In, then the Stage 1 intrinsic delay is 0.0
// Fraction of a full DDR_TCK period
localparam real PI_STG1_INTRINSIC_DELAY = (RCLK_PI_OUTPUT_CLK_SRC == "DELAYED_MEM_REF") ? 0.0 :
((DDR_TCK < 1005) ? 0.667 :
(DDR_TCK < 1160) ? 0.752 :
(DDR_TCK < 1375) ? 0.868 :
(DDR_TCK < 1685) ? 1.021 :
(DDR_TCK < 2185) ? 1.263 :
(DDR_TCK < 2900) ? 1.657 :
(DDR_TCK < 3100) ? 1.771 : 1.939)*1000;
/*
Intrinsic delay of Phaser In Stage 2
@3300ps - 0.912ns - 27.6% - single tap - 13ps
@3000ps - 0.848ns - 28.3% - single tap - 11ps
@2500ps - 1.264ns - 50.6% - single tap - 19ps
@1875ps - 1.000ns - 53.3% - single tap - 15ps
@1500ps - 0.848ns - 56.5% - single tap - 11ps
@1250ps - 0.736ns - 58.9% - single tap - 9ps
@1072ps - 0.664ns - 61.9% - single tap - 8ps
@938ps - 0.608ns - 64.8% - single tap - 7ps
*/
// Intrinsic delay = (.4218 + .0002freq(MHz))period(ps)
localparam real PI_STG2_INTRINSIC_DELAY = (0.4218*FREQ_REF_PERIOD + 200) + 16.75; // 12ps fudge factor
/*
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 1
@3300ps - 1.294ns - 39.2%
@2500ps - 1.294ns - 51.8%
@1875ps - 1.030ns - 54.9%
@1500ps - 0.878ns - 58.5%
@1250ps - 0.766ns - 61.3%
@1072ps - 0.694ns - 64.7%
@938ps - 0.638ns - 68.0%
Intrinsic delay of Phaser Out Stage 2 - coarse bypass = 0
@3300ps - 2.084ns - 63.2% - single tap - 20ps
@2500ps - 2.084ns - 81.9% - single tap - 19ps
@1875ps - 1.676ns - 89.4% - single tap - 15ps
@1500ps - 1.444ns - 96.3% - single tap - 11ps
@1250ps - 1.276ns - 102.1% - single tap - 9ps
@1072ps - 1.164ns - 108.6% - single tap - 8ps
@938ps - 1.076ns - 114.7% - single tap - 7ps
*/
// Fraction of a full DDR_TCK period
localparam real PO_STG1_INTRINSIC_DELAY = 0;
localparam real PO_STG2_FINE_INTRINSIC_DELAY = 0.4218*FREQ_REF_PERIOD + 200 + 42; // 42ps fudge factor
localparam real PO_STG2_COARSE_INTRINSIC_DELAY = 0.2256*FREQ_REF_PERIOD + 200 + 29; // 29ps fudge factor
localparam real PO_STG2_INTRINSIC_DELAY = PO_STG2_FINE_INTRINSIC_DELAY +
(PO_CTL_COARSE_BYPASS == "TRUE" ? 30 : PO_STG2_COARSE_INTRINSIC_DELAY);
// When the PO_STG2_INTRINSIC_DELAY is approximately equal to tCK, then the Phaser Out's circular buffer can
// go metastable. The circular buffer must be prevented from getting into a metastable state. To accomplish this,
// a default programmed value must be programmed into the stage 2 delay. This delay is only needed at reset, adjustments
// to the stage 2 delay can be made after reset is removed.
localparam real PO_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PO_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PO_CIRC_BUF_META_ZONE = 200.0;
localparam PO_CIRC_BUF_EARLY = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? 1'b1 : 1'b0;
localparam real PO_CIRC_BUF_OFFSET = (PO_STG2_INTRINSIC_DELAY < DDR_TCK) ? DDR_TCK - PO_STG2_INTRINSIC_DELAY : PO_STG2_INTRINSIC_DELAY - DDR_TCK;
// If the stage 2 intrinsic delay is less than the clock period, then see if it is less than the threshold
// If it is not more than the threshold than we must push the delay after the clock period plus a guardband.
//A change in PO_CIRC_BUF_DELAY value will affect the localparam TAP_DEC value(=PO_CIRC_BUF_DELAY - 31) in ddr_phy_ck_addr_cmd_delay.v. Update TAP_DEC value when PO_CIRC_BUF_DELAY is updated.
localparam integer PO_CIRC_BUF_DELAY = 60;
//localparam integer PO_CIRC_BUF_DELAY = PO_CIRC_BUF_EARLY ? (PO_CIRC_BUF_OFFSET > PO_CIRC_BUF_META_ZONE) ? 0 :
// (PO_CIRC_BUF_META_ZONE + PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE :
// (PO_CIRC_BUF_META_ZONE - PO_CIRC_BUF_OFFSET) / PO_S2_TAPS_SIZE;
localparam real PI_S2_TAPS_SIZE = 1.0*FREQ_REF_PERIOD / PI_S2_TAPS ; // average delay of taps in stage 2 fine delay line
localparam real PI_MAX_STG2_DELAY = (PI_S2_TAPS/2 - 1) * PI_S2_TAPS_SIZE;
localparam real PI_INTRINSIC_DELAY = PI_STG1_INTRINSIC_DELAY + PI_STG2_INTRINSIC_DELAY;
localparam real PO_INTRINSIC_DELAY = PO_STG1_INTRINSIC_DELAY + PO_STG2_INTRINSIC_DELAY;
localparam real PO_DELAY = PO_INTRINSIC_DELAY + (PO_CIRC_BUF_DELAY*PO_S2_TAPS_SIZE);
localparam RCLK_BUFIO_DELAY = 1200; // estimate of clock insertion delay of rclk through BUFIO to ioi
// The PI_OFFSET is the difference between the Phaser Out delay path and the intrinsic delay path
// of the Phaser_In that drives the rclk. The objective is to align either the rising edges of the
// oserdes_oclk and the rclk or to align the rising to falling edges depending on which adjustment
// is within the range of the stage 2 delay line in the Phaser_In.
localparam integer RCLK_DELAY_INT= (PI_INTRINSIC_DELAY + RCLK_BUFIO_DELAY);
localparam integer PO_DELAY_INT = PO_DELAY;
localparam PI_OFFSET = (PO_DELAY_INT % DDR_TCK) - (RCLK_DELAY_INT % DDR_TCK);
// if pi_offset >= 0 align to oclk posedge by delaying pi path to where oclk is
// if pi_offset < 0 align to oclk negedge by delaying pi path the additional distance to next oclk edge.
// note that in this case PI_OFFSET is negative so invert before subtracting.
localparam real PI_STG2_DELAY_CAND = PI_OFFSET >= 0
? PI_OFFSET
: ((-PI_OFFSET) < DDR_TCK/2) ?
(DDR_TCK/2 - (- PI_OFFSET)) :
(DDR_TCK - (- PI_OFFSET)) ;
localparam real PI_STG2_DELAY =
(PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY ?
PI_MAX_STG2_DELAY : PI_STG2_DELAY_CAND);
localparam integer DEFAULT_RCLK_DELAY = PI_STG2_DELAY / PI_S2_TAPS_SIZE;
localparam LP_RCLK_SELECT_EDGE = (RCLK_SELECT_EDGE != 4'b1111 ) ? RCLK_SELECT_EDGE : (PI_OFFSET >= 0 ? RCLK_POS_EDGE : (PI_OFFSET <= TCK/2 ? RCLK_NEG_EDGE : RCLK_POS_EDGE));
localparam integer L_PHY_0_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_1_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam integer L_PHY_2_PO_FINE_DELAY = PO_CIRC_BUF_DELAY ;
localparam L_PHY_0_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 0 && ! DATA_CTL_B0[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_1_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 1 && ! DATA_CTL_B1[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_A_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[0]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_B_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[1]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_C_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[2]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_2_D_PI_FINE_DELAY = (RCLK_SELECT_BANK == 2 && ! DATA_CTL_B2[3]) ? DEFAULT_RCLK_DELAY : 33 ;
localparam L_PHY_0_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_0_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 0) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC : PHY_0_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_1_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 1) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC : PHY_1_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_A_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "A") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_B_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "B") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_C_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "C") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
localparam L_PHY_2_D_PI_OUTPUT_CLK_SRC = (RCLK_SELECT_BANK == 2) ? (RCLK_SELECT_LANE == "D") ? RCLK_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC : PHY_2_A_PI_OUTPUT_CLK_SRC;
wire _phy_clk;
wire [2:0] mcGo_w;
wire [HIGHEST_BANK-1:0] ref_dll_lock_w;
reg [15:0] mcGo_r;
assign ref_dll_lock = & ref_dll_lock_w;
initial begin
if ( SYNTHESIS == "FALSE" ) begin
$display("%m : BYTE_LANES_B0 = %x BYTE_LANES_B1 = %x DATA_CTL_B0 = %x DATA_CTL_B1 = %x", BYTE_LANES_B0, BYTE_LANES_B1, DATA_CTL_B0, DATA_CTL_B1);
$display("%m : HIGHEST_LANE = %d HIGHEST_LANE_B0 = %d HIGHEST_LANE_B1 = %d", HIGHEST_LANE, HIGHEST_LANE_B0, HIGHEST_LANE_B1);
$display("%m : HIGHEST_BANK = %d", HIGHEST_BANK);
$display("%m : FREQ_REF_PERIOD = %0.2f ", FREQ_REF_PERIOD);
$display("%m : DDR_TCK = %0d ", DDR_TCK);
$display("%m : PO_S2_TAPS_SIZE = %0.2f ", PO_S2_TAPS_SIZE);
$display("%m : PO_CIRC_BUF_EARLY = %0d ", PO_CIRC_BUF_EARLY);
$display("%m : PO_CIRC_BUF_OFFSET = %0.2f ", PO_CIRC_BUF_OFFSET);
$display("%m : PO_CIRC_BUF_META_ZONE = %0.2f ", PO_CIRC_BUF_META_ZONE);
$display("%m : PO_STG2_FINE_INTR_DLY = %0.2f ", PO_STG2_FINE_INTRINSIC_DELAY);
$display("%m : PO_STG2_COARSE_INTR_DLY = %0.2f ", PO_STG2_COARSE_INTRINSIC_DELAY);
$display("%m : PO_STG2_INTRINSIC_DELAY = %0.2f ", PO_STG2_INTRINSIC_DELAY);
$display("%m : PO_CIRC_BUF_DELAY = %0d ", PO_CIRC_BUF_DELAY);
$display("%m : PO_INTRINSIC_DELAY = %0.2f ", PO_INTRINSIC_DELAY);
$display("%m : PO_DELAY = %0.2f ", PO_DELAY);
$display("%m : PO_OCLK_DELAY = %0d ", PHY_0_A_PO_OCLK_DELAY);
$display("%m : L_PHY_0_PO_FINE_DELAY = %0d ", L_PHY_0_PO_FINE_DELAY);
$display("%m : PI_STG1_INTRINSIC_DELAY = %0.2f ", PI_STG1_INTRINSIC_DELAY);
$display("%m : PI_STG2_INTRINSIC_DELAY = %0.2f ", PI_STG2_INTRINSIC_DELAY);
$display("%m : PI_INTRINSIC_DELAY = %0.2f ", PI_INTRINSIC_DELAY);
$display("%m : PI_MAX_STG2_DELAY = %0.2f ", PI_MAX_STG2_DELAY);
$display("%m : PI_OFFSET = %0.2f ", PI_OFFSET);
if ( PI_OFFSET < 0) $display("%m : a negative PI_OFFSET means that rclk path is longer than oclk path so rclk will be delayed to next oclk edge and the negedge of rclk may be used.");
$display("%m : PI_STG2_DELAY = %0.2f ", PI_STG2_DELAY);
$display("%m :PI_STG2_DELAY_CAND = %0.2f ",PI_STG2_DELAY_CAND);
$display("%m : DEFAULT_RCLK_DELAY = %0d ", DEFAULT_RCLK_DELAY);
$display("%m : RCLK_SELECT_EDGE = %0b ", LP_RCLK_SELECT_EDGE);
end // SYNTHESIS
if ( PI_STG2_DELAY_CAND > PI_MAX_STG2_DELAY) $display("WARNING: %m: The required delay though the phaser_in to internally match the aux_out clock to ddr clock exceeds the maximum allowable delay. The clock edge will occur at the output registers of aux_out %0.2f ps before the ddr clock edge. If aux_out is used for memory inputs, this may violate setup or hold time.", PI_STG2_DELAY_CAND - PI_MAX_STG2_DELAY);
end
assign sync_pulse_split = sync_pulse;
assign mem_refclk_split = mem_refclk;
assign freq_refclk_split = freq_refclk;
assign mem_refclk_div4_split = mem_refclk_div4;
assign phy_ctl_clk_split0 = _phy_clk;
assign phy_ctl_wd_split0 = phy_ctl_wd;
assign phy_ctl_wr_split0 = phy_ctl_wr;
assign phy_clk_split0 = phy_clk;
assign phy_cmd_wr_en_split0 = phy_cmd_wr_en;
assign phy_data_wr_en_split0 = phy_data_wr_en;
assign phy_rd_en_split0 = phy_rd_en;
assign phy_dout_split0 = phy_dout;
assign phy_ctl_clk_split1 = phy_clk;
assign phy_ctl_wd_split1 = phy_ctl_wd;
assign phy_data_offset_1_split1 = data_offset_1;
assign phy_ctl_wr_split1 = phy_ctl_wr;
assign phy_clk_split1 = phy_clk;
assign phy_cmd_wr_en_split1 = phy_cmd_wr_en;
assign phy_data_wr_en_split1 = phy_data_wr_en;
assign phy_rd_en_split1 = phy_rd_en;
assign phy_dout_split1 = phy_dout;
assign phy_ctl_clk_split2 = phy_clk;
assign phy_ctl_wd_split2 = phy_ctl_wd;
assign phy_data_offset_2_split2 = data_offset_2;
assign phy_ctl_wr_split2 = phy_ctl_wr;
assign phy_clk_split2 = phy_clk;
assign phy_cmd_wr_en_split2 = phy_cmd_wr_en;
assign phy_data_wr_en_split2 = phy_data_wr_en;
assign phy_rd_en_split2 = phy_rd_en;
assign phy_dout_split2 = phy_dout;
// these wires are needed to coerce correct synthesis
// the synthesizer did not always see the widths of the
// parameters as 4 bits.
wire [3:0] blb0 = BYTE_LANES_B0;
wire [3:0] blb1 = BYTE_LANES_B1;
wire [3:0] blb2 = BYTE_LANES_B2;
wire [3:0] dcb0 = DATA_CTL_B0;
wire [3:0] dcb1 = DATA_CTL_B1;
wire [3:0] dcb2 = DATA_CTL_B2;
assign pi_dqs_found_all = & (pi_dqs_found_lanes | ~ {blb2, blb1, blb0} | ~ {dcb2, dcb1, dcb0});
assign pi_dqs_found_any = | (pi_dqs_found_lanes & {blb2, blb1, blb0} & {dcb2, dcb1, dcb0});
assign pi_phase_locked_all = & pi_phase_locked_all_w[HIGHEST_BANK-1:0];
assign calib_zero_inputs_int = {3'bxxx, calib_zero_inputs};
//Added to remove concadination in the instantiation
assign calib_sel_byte0 = {calib_zero_inputs_int[0], calib_sel[1:0]} ;
assign calib_sel_byte1 = {calib_zero_inputs_int[1], calib_sel[1:0]} ;
assign calib_sel_byte2 = {calib_zero_inputs_int[2], calib_sel[1:0]} ;
assign calib_zero_lanes_int = calib_zero_lanes;
assign phy_ctl_ready = &phy_ctl_ready_w[HIGHEST_BANK-1:0];
assign phy_ctl_mstr_empty = phy_ctl_empty[MASTER_PHY_CTL];
assign of_ctl_a_full = |of_ctl_a_full_v;
assign of_ctl_full = |of_ctl_full_v;
assign of_data_a_full = |of_data_a_full_v;
assign of_data_full = |of_data_full_v;
assign pre_data_a_full= |pre_data_a_full_v;
// if if_empty_def == 1, empty is asserted only if all are empty;
// this allows the user to detect a skewed fifo depth and self-clear
// if desired. It avoids a reset to clear the flags.
assign if_empty = !if_empty_def ? |if_empty_v : &if_empty_v;
assign if_empty_or = |if_empty_or_v;
assign if_empty_and = &if_empty_and_v;
assign if_a_empty = |if_a_empty_v;
generate
genvar i;
for (i = 0; i != NUM_DDR_CK; i = i + 1) begin : ddr_clk_gen
case ((GENERATE_DDR_CK_MAP >> (16*i)) & 16'hffff)
16'h3041: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3042: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3043: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3044: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[0] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3141: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3142: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3143: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3144: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[1] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
16'h3241: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i)) & 2'b11;
16'h3242: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+12)) & 2'b11;
16'h3243: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+24)) & 2'b11;
16'h3244: assign ddr_clk[(i+1)*LP_DDR_CK_WIDTH-1:(i*LP_DDR_CK_WIDTH)] = (ddr_clk_w[2] >> (LP_DDR_CK_WIDTH*i+36)) & 2'b11;
default : initial $display("ERROR: mc_phy ddr_clk_gen : invalid specification for parameter GENERATE_DDR_CK_MAP , clock index = %d, spec= %x (hex) ", i, (( GENERATE_DDR_CK_MAP >> (16 * i )) & 16'hffff ));
endcase
end
endgenerate
//assign rclk = rclk_w[RCLK_SELECT_BANK];
reg rst_auxout;
reg rst_auxout_r;
reg rst_auxout_rr;
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout_r <= #(1) 1'b1;
rst_auxout_rr <= #(1) 1'b1;
end
else begin
rst_auxout_r <= #(1) rst;
rst_auxout_rr <= #(1) rst_auxout_r;
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
else begin
always @(negedge auxout_clk or posedge rst) begin
if ( rst) begin
rst_auxout <= #(1) 1'b1;
end
else begin
rst_auxout <= #(1) rst_auxout_rr;
end
end
end
localparam L_RESET_SELECT_BANK =
(BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK) ? 0 : RCLK_SELECT_BANK;
always @(*) begin
rst_out = rst_out_w[L_RESET_SELECT_BANK] & ddr_rst_in_n;
end
always @(posedge phy_clk) begin
if ( rst)
mcGo_r <= #(1) 0;
else
mcGo_r <= #(1) (mcGo_r << 1) | &mcGo_w;
end
assign mcGo = mcGo_r[15];
generate
// this is an optional 1 clock delay to add latency to the phy_control programming path
if (PHYCTL_CMD_FIFO == "TRUE") begin : cmd_fifo_soft
reg [31:0] phy_wd_reg = 0;
reg [3:0] aux_in1_reg = 0;
reg [3:0] aux_in2_reg = 0;
reg sfifo_ready = 0;
assign _phy_ctl_wd = phy_wd_reg;
assign aux_in_[1] = aux_in1_reg;
assign aux_in_[2] = aux_in2_reg;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[1] = |_phy_ctl_full_p;
assign phy_ctl_full[2] = |_phy_ctl_full_p;
assign phy_ctl_full[3] = |_phy_ctl_full_p;
assign _phy_clk = phy_clk;
always @(posedge phy_clk) begin
phy_wd_reg <= #1 phy_ctl_wd;
aux_in1_reg <= #1 aux_in_1;
aux_in2_reg <= #1 aux_in_2;
sfifo_ready <= #1 phy_ctl_wr;
end
end
else if (PHYCTL_CMD_FIFO == "FALSE") begin
assign _phy_ctl_wd = phy_ctl_wd;
assign aux_in_[1] = aux_in_1;
assign aux_in_[2] = aux_in_2;
assign phy_ctl_a_full = |_phy_ctl_a_full_p;
assign phy_ctl_full[0] = |_phy_ctl_full_p;
assign phy_ctl_full[3:1] = 3'b000;
assign _phy_clk = phy_clk;
end
endgenerate
// instance of four-lane phy
generate
if (HIGHEST_BANK == 3) begin : banks_3
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],byte_rd_en_v[2]};
assign byte_rd_en_oth_banks[5:4] = {byte_rd_en_v[0],byte_rd_en_v[1]};
end
else if (HIGHEST_BANK == 2) begin : banks_2
assign byte_rd_en_oth_banks[1:0] = {byte_rd_en_v[1],1'b1};
assign byte_rd_en_oth_banks[3:2] = {byte_rd_en_v[0],1'b1};
end
else begin : banks_1
assign byte_rd_en_oth_banks[1:0] = {1'b1,1'b1};
end
if ( BYTE_LANES_B0 != 0) begin : ddr_phy_4lanes_0
mig_7series_v2_3_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B0), /* four bits, one per lanes */
.DATA_CTL_N (PHY_0_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_0_PO_FINE_DELAY),
.BITLANES (PHY_0_BITLANES),
.BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_0_BYTELANES_DDR_CK),
.LAST_BANK (PHY_0_IS_LAST_BANK),
.LANE_REMAP (PHY_0_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_0_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_0_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_0_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_0_IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_0_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_0_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_0_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_0_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_0_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_0_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_0_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_0_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_0_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_0_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_0_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_0_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_0_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_0_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_0_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_0_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_0_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_0_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_0_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_0_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_0_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_0_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_0_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_0_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_0_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_0_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_0_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_0_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_0_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_0_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_0_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_0_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_0_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_0_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_0_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_0_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split0),
.phy_ctl_clk (phy_ctl_clk_split0),
.phy_ctl_wd (phy_ctl_wd_split0),
.data_offset (phy_ctl_wd_split0[PC_DATA_OFFSET_RANGE_HI : PC_DATA_OFFSET_RANGE_LO]),
.phy_ctl_wr (phy_ctl_wr_split0),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split0[HIGHEST_LANE_B0*80-1:0]),
.phy_cmd_wr_en (phy_cmd_wr_en_split0),
.phy_data_wr_en (phy_data_wr_en_split0),
.phy_rd_en (phy_rd_en_split0),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[0]),
.rclk (),
.rst_out (rst_out_w[0]),
.mcGo (mcGo_w[0]),
.ref_dll_lock (ref_dll_lock_w[0]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[1:0]),
.if_a_empty (if_a_empty_v[0]),
.if_empty (if_empty_v[0]),
.byte_rd_en (byte_rd_en_v[0]),
.if_empty_or (if_empty_or_v[0]),
.if_empty_and (if_empty_and_v[0]),
.of_ctl_a_full (of_ctl_a_full_v[0]),
.of_data_a_full (of_data_a_full_v[0]),
.of_ctl_full (of_ctl_full_v[0]),
.of_data_full (of_data_full_v[0]),
.pre_data_a_full (pre_data_a_full_v[0]),
.phy_din (phy_din[HIGHEST_LANE_B0*80-1:0]),
.phy_ctl_a_full (_phy_ctl_a_full_p[0]),
.phy_ctl_full (_phy_ctl_full_p[0]),
.phy_ctl_empty (phy_ctl_empty[0]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B0*12-1:0]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B0*10-1:0]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B0-1:0]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B0-1:0]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B0-1:0]),
.aux_out (aux_out_[3:0]),
.phy_ctl_ready (phy_ctl_ready_w[0]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte0),
.calib_zero_ctrl (calib_zero_ctrl[0]),
.calib_zero_lanes (calib_zero_lanes_int[3:0]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[0]),
.po_fine_enable (po_fine_enable[0]),
.po_fine_inc (po_fine_inc[0]),
.po_coarse_inc (po_coarse_inc[0]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[0]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[0]),
.po_fine_overflow (po_fine_overflow_w[0]),
.po_counter_read_val (po_counter_read_val_w[0]),
.pi_rst_dqs_find (pi_rst_dqs_find[0]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[0]),
.pi_counter_read_val (pi_counter_read_val_w[0]),
.pi_dqs_found (pi_dqs_found_w[0]),
.pi_dqs_found_all (pi_dqs_found_all_w[0]),
.pi_dqs_found_any (pi_dqs_found_any_w[0]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[0]),
.pi_phase_locked (pi_phase_locked_w[0]),
.pi_phase_locked_all (pi_phase_locked_all_w[0]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[0] <= #100 0;
aux_out[2] <= #100 0;
end
else begin
aux_out[0] <= #100 aux_out_[0];
aux_out[2] <= #100 aux_out_[2];
end
end
if ( LP_RCLK_SELECT_EDGE[0]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[1] <= #100 0;
aux_out[3] <= #100 0;
end
else begin
aux_out[1] <= #100 aux_out_[1];
aux_out[3] <= #100 aux_out_[3];
end
end
end
end
else begin
if ( HIGHEST_BANK > 0) begin
assign phy_din[HIGHEST_LANE_B0*80-1:0] = 0;
assign _phy_ctl_a_full_p[0] = 0;
assign of_ctl_a_full_v[0] = 0;
assign of_ctl_full_v[0] = 0;
assign of_data_a_full_v[0] = 0;
assign of_data_full_v[0] = 0;
assign pre_data_a_full_v[0] = 0;
assign if_empty_v[0] = 0;
assign byte_rd_en_v[0] = 1;
always @(*)
aux_out[3:0] = 0;
end
assign pi_dqs_found_w[0] = 1;
assign pi_dqs_found_all_w[0] = 1;
assign pi_dqs_found_any_w[0] = 0;
assign pi_phase_locked_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B0-1:0] = 4'b1111;
assign pi_dqs_out_of_range_w[0] = 0;
assign pi_phase_locked_w[0] = 1;
assign po_fine_overflow_w[0] = 0;
assign po_coarse_overflow_w[0] = 0;
assign po_fine_overflow_w[0] = 0;
assign pi_fine_overflow_w[0] = 0;
assign po_counter_read_val_w[0] = 0;
assign pi_counter_read_val_w[0] = 0;
assign mcGo_w[0] = 1;
if ( RCLK_SELECT_BANK == 0)
always @(*)
aux_out[3:0] = 0;
end
if ( BYTE_LANES_B1 != 0) begin : ddr_phy_4lanes_1
mig_7series_v2_3_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B1), /* four bits, one per lanes */
.DATA_CTL_N (PHY_1_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_1_PO_FINE_DELAY),
.BITLANES (PHY_1_BITLANES),
.BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_1_BYTELANES_DDR_CK),
.LAST_BANK (PHY_1_IS_LAST_BANK ),
.LANE_REMAP (PHY_1_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_1_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_1_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_1_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_1_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_1_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_1_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_1_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_1_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_1_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_1_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_1_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_1_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_1_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_1_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_1_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_1_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_1_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_1_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_1_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_1_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_1_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_1_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_1_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_1_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_1_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_1_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_1_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_1_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_1_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_1_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_1_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_1_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_1_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_1_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_1_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_1_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_1_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_1_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_1_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_1_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_1_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_1_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_1_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_1_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_1_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_1_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_1_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_1_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_1_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_1_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_1_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_1_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_1_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_1_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_1_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split1),
.phy_ctl_clk (phy_ctl_clk_split1),
.phy_ctl_wd (phy_ctl_wd_split1),
.data_offset (phy_data_offset_1_split1),
.phy_ctl_wr (phy_ctl_wr_split1),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split1[HIGHEST_LANE_B1*80+320-1:320]),
.phy_cmd_wr_en (phy_cmd_wr_en_split1),
.phy_data_wr_en (phy_data_wr_en_split1),
.phy_rd_en (phy_rd_en_split1),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[1]),
.rclk (),
.rst_out (rst_out_w[1]),
.mcGo (mcGo_w[1]),
.ref_dll_lock (ref_dll_lock_w[1]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[3:2]),
.if_a_empty (if_a_empty_v[1]),
.if_empty (if_empty_v[1]),
.byte_rd_en (byte_rd_en_v[1]),
.if_empty_or (if_empty_or_v[1]),
.if_empty_and (if_empty_and_v[1]),
.of_ctl_a_full (of_ctl_a_full_v[1]),
.of_data_a_full (of_data_a_full_v[1]),
.of_ctl_full (of_ctl_full_v[1]),
.of_data_full (of_data_full_v[1]),
.pre_data_a_full (pre_data_a_full_v[1]),
.phy_din (phy_din[HIGHEST_LANE_B1*80+320-1:320]),
.phy_ctl_a_full (_phy_ctl_a_full_p[1]),
.phy_ctl_full (_phy_ctl_full_p[1]),
.phy_ctl_empty (phy_ctl_empty[1]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B1*12+48-1:48]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B1*10+40-1:40]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B1+4-1:4]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B1+4-1:4]),
.aux_out (aux_out_[7:4]),
.phy_ctl_ready (phy_ctl_ready_w[1]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte1),
.calib_zero_ctrl (calib_zero_ctrl[1]),
.calib_zero_lanes (calib_zero_lanes_int[7:4]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[1]),
.po_fine_enable (po_fine_enable[1]),
.po_fine_inc (po_fine_inc[1]),
.po_coarse_inc (po_coarse_inc[1]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[1]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[1]),
.po_fine_overflow (po_fine_overflow_w[1]),
.po_counter_read_val (po_counter_read_val_w[1]),
.pi_rst_dqs_find (pi_rst_dqs_find[1]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[1]),
.pi_counter_read_val (pi_counter_read_val_w[1]),
.pi_dqs_found (pi_dqs_found_w[1]),
.pi_dqs_found_all (pi_dqs_found_all_w[1]),
.pi_dqs_found_any (pi_dqs_found_any_w[1]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[1]),
.pi_phase_locked (pi_phase_locked_w[1]),
.pi_phase_locked_all (pi_phase_locked_all_w[1]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[4] <= #100 0;
aux_out[6] <= #100 0;
end
else begin
aux_out[4] <= #100 aux_out_[4];
aux_out[6] <= #100 aux_out_[6];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[5] <= #100 0;
aux_out[7] <= #100 0;
end
else begin
aux_out[5] <= #100 aux_out_[5];
aux_out[7] <= #100 aux_out_[7];
end
end
end
end
else begin
if ( HIGHEST_BANK > 1) begin
assign phy_din[HIGHEST_LANE_B1*80+320-1:320] = 0;
assign _phy_ctl_a_full_p[1] = 0;
assign of_ctl_a_full_v[1] = 0;
assign of_ctl_full_v[1] = 0;
assign of_data_a_full_v[1] = 0;
assign of_data_full_v[1] = 0;
assign pre_data_a_full_v[1] = 0;
assign if_empty_v[1] = 0;
assign byte_rd_en_v[1] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B1+4-1:4] = 4'b1111;
always @(*)
aux_out[7:4] = 0;
end
assign pi_dqs_found_w[1] = 1;
assign pi_dqs_found_all_w[1] = 1;
assign pi_dqs_found_any_w[1] = 0;
assign pi_dqs_out_of_range_w[1] = 0;
assign pi_phase_locked_w[1] = 1;
assign po_coarse_overflow_w[1] = 0;
assign po_fine_overflow_w[1] = 0;
assign pi_fine_overflow_w[1] = 0;
assign po_counter_read_val_w[1] = 0;
assign pi_counter_read_val_w[1] = 0;
assign mcGo_w[1] = 1;
end
if ( BYTE_LANES_B2 != 0) begin : ddr_phy_4lanes_2
mig_7series_v2_3_ddr_phy_4lanes #
(
.BYTE_LANES (BYTE_LANES_B2), /* four bits, one per lanes */
.DATA_CTL_N (PHY_2_DATA_CTL), /* four bits, one per lane */
.PO_CTL_COARSE_BYPASS (PO_CTL_COARSE_BYPASS),
.PO_FINE_DELAY (L_PHY_2_PO_FINE_DELAY),
.BITLANES (PHY_2_BITLANES),
.BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.BYTELANES_DDR_CK (LP_PHY_2_BYTELANES_DDR_CK),
.LAST_BANK (PHY_2_IS_LAST_BANK ),
.LANE_REMAP (PHY_2_LANE_REMAP),
.OF_ALMOST_FULL_VALUE (PHY_2_OF_ALMOST_FULL_VALUE),
.IF_ALMOST_EMPTY_VALUE (PHY_2_IF_ALMOST_EMPTY_VALUE),
.GENERATE_IDELAYCTRL (PHY_2_GENERATE_IDELAYCTRL),
.IODELAY_GRP (PHY_2_IODELAY_GRP),
.BANK_TYPE (BANK_TYPE),
.NUM_DDR_CK (NUM_DDR_CK),
.TCK (TCK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.PC_CLK_RATIO (PHY_CLK_RATIO),
.PC_EVENTS_DELAY (PHY_EVENTS_DELAY),
.PC_FOUR_WINDOW_CLOCKS (PHY_FOUR_WINDOW_CLOCKS),
.PC_BURST_MODE (PHY_2_A_BURST_MODE),
.PC_SYNC_MODE (PHY_SYNC_MODE),
.PC_MULTI_REGION (PHY_MULTI_REGION),
.PC_PHY_COUNT_EN (PHY_COUNT_EN),
.PC_DISABLE_SEQ_MATCH (PHY_DISABLE_SEQ_MATCH),
.PC_CMD_OFFSET (PHY_2_CMD_OFFSET),
.PC_RD_CMD_OFFSET_0 (PHY_2_RD_CMD_OFFSET_0),
.PC_RD_CMD_OFFSET_1 (PHY_2_RD_CMD_OFFSET_1),
.PC_RD_CMD_OFFSET_2 (PHY_2_RD_CMD_OFFSET_2),
.PC_RD_CMD_OFFSET_3 (PHY_2_RD_CMD_OFFSET_3),
.PC_RD_DURATION_0 (PHY_2_RD_DURATION_0),
.PC_RD_DURATION_1 (PHY_2_RD_DURATION_1),
.PC_RD_DURATION_2 (PHY_2_RD_DURATION_2),
.PC_RD_DURATION_3 (PHY_2_RD_DURATION_3),
.PC_WR_CMD_OFFSET_0 (PHY_2_WR_CMD_OFFSET_0),
.PC_WR_CMD_OFFSET_1 (PHY_2_WR_CMD_OFFSET_1),
.PC_WR_CMD_OFFSET_2 (PHY_2_WR_CMD_OFFSET_2),
.PC_WR_CMD_OFFSET_3 (PHY_2_WR_CMD_OFFSET_3),
.PC_WR_DURATION_0 (PHY_2_WR_DURATION_0),
.PC_WR_DURATION_1 (PHY_2_WR_DURATION_1),
.PC_WR_DURATION_2 (PHY_2_WR_DURATION_2),
.PC_WR_DURATION_3 (PHY_2_WR_DURATION_3),
.PC_AO_WRLVL_EN (PHY_2_AO_WRLVL_EN),
.PC_AO_TOGGLE (PHY_2_AO_TOGGLE),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.A_PI_FINE_DELAY (L_PHY_2_A_PI_FINE_DELAY),
.B_PI_FINE_DELAY (L_PHY_2_B_PI_FINE_DELAY),
.C_PI_FINE_DELAY (L_PHY_2_C_PI_FINE_DELAY),
.D_PI_FINE_DELAY (L_PHY_2_D_PI_FINE_DELAY),
.A_PI_FREQ_REF_DIV (PHY_2_A_PI_FREQ_REF_DIV),
.A_PI_BURST_MODE (PHY_2_A_BURST_MODE),
.A_PI_OUTPUT_CLK_SRC (L_PHY_2_A_PI_OUTPUT_CLK_SRC),
.B_PI_OUTPUT_CLK_SRC (L_PHY_2_B_PI_OUTPUT_CLK_SRC),
.C_PI_OUTPUT_CLK_SRC (L_PHY_2_C_PI_OUTPUT_CLK_SRC),
.D_PI_OUTPUT_CLK_SRC (L_PHY_2_D_PI_OUTPUT_CLK_SRC),
.A_PO_OUTPUT_CLK_SRC (PHY_2_A_PO_OUTPUT_CLK_SRC),
.A_PO_OCLK_DELAY (PHY_2_A_PO_OCLK_DELAY),
.A_PO_OCLKDELAY_INV (PHY_2_A_PO_OCLKDELAY_INV),
.A_OF_ARRAY_MODE (PHY_2_A_OF_ARRAY_MODE),
.B_OF_ARRAY_MODE (PHY_2_B_OF_ARRAY_MODE),
.C_OF_ARRAY_MODE (PHY_2_C_OF_ARRAY_MODE),
.D_OF_ARRAY_MODE (PHY_2_D_OF_ARRAY_MODE),
.A_IF_ARRAY_MODE (PHY_2_A_IF_ARRAY_MODE),
.B_IF_ARRAY_MODE (PHY_2_B_IF_ARRAY_MODE),
.C_IF_ARRAY_MODE (PHY_2_C_IF_ARRAY_MODE),
.D_IF_ARRAY_MODE (PHY_2_D_IF_ARRAY_MODE),
.A_OS_DATA_RATE (PHY_2_A_OSERDES_DATA_RATE),
.A_OS_DATA_WIDTH (PHY_2_A_OSERDES_DATA_WIDTH),
.B_OS_DATA_RATE (PHY_2_B_OSERDES_DATA_RATE),
.B_OS_DATA_WIDTH (PHY_2_B_OSERDES_DATA_WIDTH),
.C_OS_DATA_RATE (PHY_2_C_OSERDES_DATA_RATE),
.C_OS_DATA_WIDTH (PHY_2_C_OSERDES_DATA_WIDTH),
.D_OS_DATA_RATE (PHY_2_D_OSERDES_DATA_RATE),
.D_OS_DATA_WIDTH (PHY_2_D_OSERDES_DATA_WIDTH),
.A_IDELAYE2_IDELAY_TYPE (PHY_2_A_IDELAYE2_IDELAY_TYPE),
.A_IDELAYE2_IDELAY_VALUE (PHY_2_A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_phy_4lanes
(
.rst (rst),
.phy_clk (phy_clk_split2),
.phy_ctl_clk (phy_ctl_clk_split2),
.phy_ctl_wd (phy_ctl_wd_split2),
.data_offset (phy_data_offset_2_split2),
.phy_ctl_wr (phy_ctl_wr_split2),
.mem_refclk (mem_refclk_split),
.freq_refclk (freq_refclk_split),
.mem_refclk_div4 (mem_refclk_div4_split),
.sync_pulse (sync_pulse_split),
.phy_dout (phy_dout_split2[HIGHEST_LANE_B2*80+640-1:640]),
.phy_cmd_wr_en (phy_cmd_wr_en_split2),
.phy_data_wr_en (phy_data_wr_en_split2),
.phy_rd_en (phy_rd_en_split2),
.pll_lock (pll_lock),
.ddr_clk (ddr_clk_w[2]),
.rclk (),
.rst_out (rst_out_w[2]),
.mcGo (mcGo_w[2]),
.ref_dll_lock (ref_dll_lock_w[2]),
.idelayctrl_refclk (idelayctrl_refclk),
.idelay_inc (idelay_inc),
.idelay_ce (idelay_ce),
.idelay_ld (idelay_ld),
.phy_ctl_mstr_empty (phy_ctl_mstr_empty),
.if_rst (if_rst),
.if_empty_def (if_empty_def),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks[5:4]),
.if_a_empty (if_a_empty_v[2]),
.if_empty (if_empty_v[2]),
.byte_rd_en (byte_rd_en_v[2]),
.if_empty_or (if_empty_or_v[2]),
.if_empty_and (if_empty_and_v[2]),
.of_ctl_a_full (of_ctl_a_full_v[2]),
.of_data_a_full (of_data_a_full_v[2]),
.of_ctl_full (of_ctl_full_v[2]),
.of_data_full (of_data_full_v[2]),
.pre_data_a_full (pre_data_a_full_v[2]),
.phy_din (phy_din[HIGHEST_LANE_B2*80+640-1:640]),
.phy_ctl_a_full (_phy_ctl_a_full_p[2]),
.phy_ctl_full (_phy_ctl_full_p[2]),
.phy_ctl_empty (phy_ctl_empty[2]),
.mem_dq_out (mem_dq_out[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_ts (mem_dq_ts[HIGHEST_LANE_B2*12+96-1:96]),
.mem_dq_in (mem_dq_in[HIGHEST_LANE_B2*10+80-1:80]),
.mem_dqs_out (mem_dqs_out[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_ts (mem_dqs_ts[HIGHEST_LANE_B2-1+8:8]),
.mem_dqs_in (mem_dqs_in[HIGHEST_LANE_B2-1+8:8]),
.aux_out (aux_out_[11:8]),
.phy_ctl_ready (phy_ctl_ready_w[2]),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
// .scan_test_bus_A (scan_test_bus_A),
// .scan_test_bus_B (),
// .scan_test_bus_C (),
// .scan_test_bus_D (),
.phyGo (phyGo),
.input_sink (input_sink),
.calib_sel (calib_sel_byte2),
.calib_zero_ctrl (calib_zero_ctrl[2]),
.calib_zero_lanes (calib_zero_lanes_int[11:8]),
.calib_in_common (calib_in_common),
.po_coarse_enable (po_coarse_enable[2]),
.po_fine_enable (po_fine_enable[2]),
.po_fine_inc (po_fine_inc[2]),
.po_coarse_inc (po_coarse_inc[2]),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay[2]),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (po_coarse_overflow_w[2]),
.po_fine_overflow (po_fine_overflow_w[2]),
.po_counter_read_val (po_counter_read_val_w[2]),
.pi_rst_dqs_find (pi_rst_dqs_find[2]),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (pi_fine_overflow_w[2]),
.pi_counter_read_val (pi_counter_read_val_w[2]),
.pi_dqs_found (pi_dqs_found_w[2]),
.pi_dqs_found_all (pi_dqs_found_all_w[2]),
.pi_dqs_found_any (pi_dqs_found_any_w[2]),
.pi_phase_locked_lanes (pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_found_lanes (pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8]),
.pi_dqs_out_of_range (pi_dqs_out_of_range_w[2]),
.pi_phase_locked (pi_phase_locked_w[2]),
.pi_phase_locked_all (pi_phase_locked_all_w[2]),
.fine_delay (fine_delay),
.fine_delay_sel (fine_delay_sel)
);
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[8] <= #100 0;
aux_out[10] <= #100 0;
end
else begin
aux_out[8] <= #100 aux_out_[8];
aux_out[10] <= #100 aux_out_[10];
end
end
if ( LP_RCLK_SELECT_EDGE[1]) begin
always @(posedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
else begin
always @(negedge auxout_clk or posedge rst_auxout) begin
if (rst_auxout) begin
aux_out[9] <= #100 0;
aux_out[11] <= #100 0;
end
else begin
aux_out[9] <= #100 aux_out_[9];
aux_out[11] <= #100 aux_out_[11];
end
end
end
end
else begin
if ( HIGHEST_BANK > 2) begin
assign phy_din[HIGHEST_LANE_B2*80+640-1:640] = 0;
assign _phy_ctl_a_full_p[2] = 0;
assign of_ctl_a_full_v[2] = 0;
assign of_ctl_full_v[2] = 0;
assign of_data_a_full_v[2] = 0;
assign of_data_full_v[2] = 0;
assign pre_data_a_full_v[2] = 0;
assign if_empty_v[2] = 0;
assign byte_rd_en_v[2] = 1;
assign pi_phase_locked_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
assign pi_dqs_found_lanes[HIGHEST_LANE_B2+8-1:8] = 4'b1111;
always @(*)
aux_out[11:8] = 0;
end
assign pi_dqs_found_w[2] = 1;
assign pi_dqs_found_all_w[2] = 1;
assign pi_dqs_found_any_w[2] = 0;
assign pi_dqs_out_of_range_w[2] = 0;
assign pi_phase_locked_w[2] = 1;
assign po_coarse_overflow_w[2] = 0;
assign po_fine_overflow_w[2] = 0;
assign po_counter_read_val_w[2] = 0;
assign pi_counter_read_val_w[2] = 0;
assign mcGo_w[2] = 1;
end
endgenerate
generate
// for single bank , emit an extra phaser_in to generate rclk
// so that auxout can be placed in another region
// if desired
if ( BYTE_LANES_B1 == 0 && BYTE_LANES_B2 == 0 && RCLK_SELECT_BANK>0)
begin : phaser_in_rclk
localparam L_EXTRA_PI_FINE_DELAY = DEFAULT_RCLK_DELAY;
PHASER_IN_PHY #(
.BURST_MODE ( PHY_0_A_BURST_MODE),
.CLKOUT_DIV ( PHY_0_A_PI_CLKOUT_DIV),
.FREQ_REF_DIV ( PHY_0_A_PI_FREQ_REF_DIV),
.REFCLK_PERIOD ( L_FREQ_REF_PERIOD_NS),
.FINE_DELAY ( L_EXTRA_PI_FINE_DELAY),
.OUTPUT_CLK_SRC ( RCLK_PI_OUTPUT_CLK_SRC)
) phaser_in_rclk (
.DQSFOUND (),
.DQSOUTOFRANGE (),
.FINEOVERFLOW (),
.PHASELOCKED (),
.ISERDESRST (),
.ICLKDIV (),
.ICLK (),
.COUNTERREADVAL (),
.RCLK (),
.WRENABLE (),
.BURSTPENDINGPHY (),
.ENCALIBPHY (),
.FINEENABLE (0),
.FREQREFCLK (freq_refclk),
.MEMREFCLK (mem_refclk),
.RANKSELPHY (0),
.PHASEREFCLK (),
.RSTDQSFIND (0),
.RST (rst),
.FINEINC (),
.COUNTERLOADEN (),
.COUNTERREADEN (),
.COUNTERLOADVAL (),
.SYNCIN (sync_pulse),
.SYSCLK (phy_clk)
);
end
endgenerate
always @(*) begin
case (calib_sel[5:3])
3'b000: begin
po_coarse_overflow = po_coarse_overflow_w[0];
po_fine_overflow = po_fine_overflow_w[0];
po_counter_read_val = po_counter_read_val_w[0];
pi_fine_overflow = pi_fine_overflow_w[0];
pi_counter_read_val = pi_counter_read_val_w[0];
pi_phase_locked = pi_phase_locked_w[0];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[0];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[0];
end
3'b001: begin
po_coarse_overflow = po_coarse_overflow_w[1];
po_fine_overflow = po_fine_overflow_w[1];
po_counter_read_val = po_counter_read_val_w[1];
pi_fine_overflow = pi_fine_overflow_w[1];
pi_counter_read_val = pi_counter_read_val_w[1];
pi_phase_locked = pi_phase_locked_w[1];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[1];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[1];
end
3'b010: begin
po_coarse_overflow = po_coarse_overflow_w[2];
po_fine_overflow = po_fine_overflow_w[2];
po_counter_read_val = po_counter_read_val_w[2];
pi_fine_overflow = pi_fine_overflow_w[2];
pi_counter_read_val = pi_counter_read_val_w[2];
pi_phase_locked = pi_phase_locked_w[2];
if ( calib_in_common)
pi_dqs_found = pi_dqs_found_any;
else
pi_dqs_found = pi_dqs_found_w[2];
pi_dqs_out_of_range = pi_dqs_out_of_range_w[2];
end
default: begin
po_coarse_overflow = 0;
po_fine_overflow = 0;
po_counter_read_val = 0;
pi_fine_overflow = 0;
pi_counter_read_val = 0;
pi_phase_locked = 0;
pi_dqs_found = 0;
pi_dqs_out_of_range = 0;
end
endcase
end
endmodule // mc_phy
|
//phase 8: testing MOVEZ and overflow bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:81];
wire [63:0] iaddrbus, daddrbus;
reg [63:0] iaddrbusout[0:81], daddrbusout[0:81];
wire [63:0] databus;
reg [63:0] databusk, databusin[0:81], databusout[0:81];
reg clk, reset;
reg clkd;
reg [63:0] dontcare;
reg [24*8:1] iname[0:81];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
//register parameters
parameter R0 = 5'b00000;
parameter R15 = 5'b01111;
parameter R16 = 5'b10000;
parameter R17 = 5'b10001;
parameter R18 = 5'b10010;
parameter R19 = 5'b10011;
parameter R20 = 5'b10100;
parameter R21 = 5'b10101;
parameter R22 = 5'b10110;
parameter R23 = 5'b10111;
parameter R24 = 5'b11000;
parameter R25 = 5'b11001;
parameter R26 = 5'b11010;
parameter R27 = 5'b11011;
parameter R28 = 5'b11100;
parameter R29 = 5'b11101;
parameter R30 = 5'b11110;
parameter R31 = 5'b11111;
//other parameterz to be used
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
parameter move_0 = 2'b00;
parameter move_1 = 2'b01;
parameter move_2 = 2'b10;
parameter move_3 = 2'b11;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.daddrbus(daddrbus),.databus(databus));
initial begin
dontcare = 64'hx;
//phase 1: testing basic op commands
// op, rd, rn, rm
iname[0] ="ADDI, R20, R31, #AAA";//testing addi, result in R20 = 0000000000000AAA
iaddrbusout[0] = 64'h00000000;
// opcode rm/ALUImm rn rd
instrbusin[0] ={ADDI, 12'hAAA, R31, R20};
daddrbusout[0] = dontcare;
databusin[0] = 64'bz;
databusout[0] = dontcare;
// op, rd, rn, rm
iname[1] ="ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 0000000000000000
iaddrbusout[1] = 64'h00000004;
// opcode rm/ALUImm rn rd
instrbusin[1] ={ADDI, 12'h002, R23, R31};
daddrbusout[1] = dontcare;
databusin[1] = 64'bz;
databusout[1] = dontcare;
// op, rd, rn, rm
iname[2] ="ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 0000000000000002
iaddrbusout[2] = 64'h00000008;
// opcode rm/ALUImm rn rd
instrbusin[2] ={ADDI, 12'h002, R23, R0};
daddrbusout[2] = dontcare;
databusin[2] = 64'bz;
databusout[2] = dontcare;
// op, rd, rn, rm
iname[3] ="ORRI, R21, R24, #001";//testing ori, result in R21 = 0000000000000001
iaddrbusout[3] = 64'h0000000C;
// opcode rm/ALUImm rn rd
instrbusin[3] ={ORRI, 12'h001, R24, R21};
daddrbusout[3] = dontcare;
databusin[3] = 64'bz;
databusout[3] = dontcare;
// op, rd, rn, rm
iname[4] ="EORI, R22, R20, #000";//testing xori, result in R22 = 0000000000000AAA
iaddrbusout[4] = 64'h00000010;
// opcode rm/ALUImm rn rd
instrbusin[4] ={EORI, 12'h000, R20, R22};
daddrbusout[4] = dontcare;
databusin[4] = 64'bz;
databusout[4] = dontcare;
// op, rd, rn, rm
iname[5] ="ANDI, R23, R0, #003";//testing andi, result in R23 = 0000000000000002
iaddrbusout[5] = 64'h00000014;
// opcode rm/ALUImm rn rd
instrbusin[5] ={ANDI, 12'h003, R0, R23};
daddrbusout[5] = dontcare;
databusin[5] = 64'bz;
databusout[5] = dontcare;
// op, rd, rn, rm
iname[6] ="SUBI, R24, R20, #00A";//testing subi, result in R24 = 0000000000000AA0
iaddrbusout[6] = 64'h00000018;
// opcode rm/ALUImm rn rd
instrbusin[6] ={SUBI, 12'h00A, R20, R24};
daddrbusout[6] = dontcare;
databusin[6] = 64'bz;
databusout[6] = dontcare;
// op, rd, rn, rm
iname[7] ="ADD, R25, R20, R0";//testing add, result in R25 = 0000000000000AAC
iaddrbusout[7] = 64'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7] ={ADD, R0, zeroSham, R20, R25};
daddrbusout[7] = dontcare;
databusin[7] = 64'bz;
databusout[7] = dontcare;
// op, rd, rn, rm
iname[8] ="AND, R26, R20, R22";//testing and, result in R26 = 0000000000000AAA
iaddrbusout[8] = 64'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8] ={AND, R22, zeroSham, R20, R26};
daddrbusout[8] = dontcare;
databusin[8] = 64'bz;
databusout[8] = dontcare;
// op, rd, rn, rm
iname[9] ="EOR, R27, R23, R21";//testing xor, result in R27 = 0000000000000003
iaddrbusout[9] = 64'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9] ={EOR, R21, zeroSham, R23, R27};
daddrbusout[9] = dontcare;
databusin[9] = 64'bz;
databusout[9] = dontcare;
// op, rd, rn, rm
iname[10] ="ORR, R28, R25, R23";//testing or, result in R28 = 0000000000000AAE
iaddrbusout[10] = 64'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10] ={ORR, R23, zeroSham, R25, R28};
daddrbusout[10] = dontcare;
databusin[10] = 64'bz;
databusout[10] = dontcare;
// op, rd, rn, rm
iname[11] ="SUB, R29, R20, R22";//testing sub, result in R29 = 0000000000000000
iaddrbusout[11] = 64'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11] ={SUB, R22, zeroSham, R20, R29};
daddrbusout[11] = dontcare;
databusin[11] = 64'bz;
databusout[11] = dontcare;
// op, rd, rn, aluImm
iname[12] ="ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 0000000000000000
iaddrbusout[12] = 64'h00000030;
// opcode rm/ALUImm rn rd
instrbusin[12] ={ADDI, 12'h000, R31, R30};
daddrbusout[12] = dontcare;
databusin[12] = 64'bz;
databusout[12] = dontcare;
//phase 2: testing basic op codes with the set flags
// op, rd, rn, aluImm
iname[13] ="SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFFFFFFFFFF
iaddrbusout[13] = 64'h00000034;
// opcode rm/ALUImm rn rd
instrbusin[13] ={SUBIS, 12'h003, R0, R20};
daddrbusout[13] = dontcare;
databusin[13] = 64'bz;
databusout[13] = dontcare;
// op, rd, rn, rm
iname[14] ="SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFFFFFFFFFE
iaddrbusout[14] = 64'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] ={SUBS,R28,zeroSham, R25, R21};
daddrbusout[14] = dontcare;
databusin[14] = 64'bz;
databusout[14] = dontcare;
// op, rd, rn, aluImm
iname[15] ="ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 0000000000000000
iaddrbusout[15] = 64'h0000003C;
// opcode rm/ALUImm rn rd
instrbusin[15] ={ADDIS, 12'h000, R31, R22};
daddrbusout[15] = dontcare;
databusin[15] = 64'bz;
databusout[15] = dontcare;
// op, rd, rn, rm
iname[16] ="ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 0000000000000001
iaddrbusout[16] = 64'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] ={ADDS,R23,zeroSham, R20, R23};
daddrbusout[16] = dontcare;
databusin[16] = 64'bz;
databusout[16] = dontcare;
// op, rd, rn, aluImm
iname[17] ="ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 0000000000000002
iaddrbusout[17] = 64'h00000044;
// opcode rm/ALUImm rn rd
instrbusin[17] ={ANDIS, 12'h002, R20, R24};
daddrbusout[17] = dontcare;
databusin[17] = 64'bz;
databusout[17] = dontcare;
// op, rd, rn, rm
iname[18] ="ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFFFFFFFFFE
iaddrbusout[18] = 64'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] ={ANDS, R20, zeroSham, R21, R25};
daddrbusout[18] = dontcare;
databusin[18] = 64'bz;
databusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12'h007, R31, R20};
daddrbusout[19] = dontcare;
databusin[19] = 64'bz;
databusout[19] = dontcare;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12'h700, R31, R21};
daddrbusout[20] = dontcare;
databusin[20] = 64'bz;
databusout[20] = dontcare;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
daddrbusout[21] = dontcare;
databusin[21] = 64'bz;
databusout[21] = dontcare;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
daddrbusout[22] = dontcare;
databusin[22] = 64'bz;
databusout[22] = dontcare;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
daddrbusout[23] = dontcare;
databusin[23] = 64'bz;
databusout[23] = dontcare;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
daddrbusout[24] = dontcare;
databusin[24] = 64'bz;
databusout[24] = dontcare;
//phase 4: testing load and store
// op, rt, rn, DT_adr
iname[25] ="LDUR, R22, R31, #1";//testing load, result in R22 = 42069 (from memory,databusin) [yes, really]
iaddrbusout[25] = 64'h00000064;
// op, DT_ADDR, ?, rn, rt
instrbusin[25] ={LDUR, 9'b000000001, 2'b00, R31, R22};
daddrbusout[25] = 64'h0000000000000001;//used for LDUR
databusin[25] = 64'h0000000000042069;//used for LDUR
databusout[25] = dontcare;
// op, rn, DT_adr, rt
iname[26] ="STUR, R23, #068, R24";//testing story, result for databusout in R24 = 0000000000000002 (to memory)
//address is calculated from imm or 68, and R23, which is currently 1
iaddrbusout[26] = 64'h00000068;
// op, DT_ADDR, ?, rn, rt
instrbusin[26] ={STUR, 9'b001101000, 2'b00, R23, R24};
daddrbusout[26] = 64'h0000000000000069;//used for STUR
databusin[26] = 64'bz;
databusout[26] = 64'h0000000000000002;//used for STUR
// op, rd, rn, rm
iname[27] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[27] = 64'h0000006C;
// op, rm, shamt, rn, rd
instrbusin[27] ={AND, R31, zeroSham, R31, R19};
daddrbusout[27] = dontcare;
databusin[27] = 64'bz;
databusout[27] = dontcare;
// op, rd, rn, rm
iname[28] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[28] = 64'h00000070;
// op, rm, shamt, rn, rd
instrbusin[28] ={AND, R31, zeroSham, R31, R19};
daddrbusout[28] = dontcare;
databusin[28] = 64'bz;
databusout[28] = dontcare;
// op, rd, rn, rm
iname[29] ="AND, R17, R31, R31";//delay, result in R17 = 0000000000000000
iaddrbusout[29] = 64'h00000074;
// op, rm, shamt, rn, rd
instrbusin[29] ={AND, R31, zeroSham, R31, R19};
daddrbusout[29] = dontcare;
databusin[29] = 64'bz;
databusout[29] = dontcare;
//phase 5: testing B branch
// op, BR_address
iname[30] ="B, #EA";//testing branch, calculated branch address should be
// (64'h0000000000000078 + 64'h000000000000003A8 = 64'h0000000000000420)
iaddrbusout[30] = 64'h00000078;
// op, BR_address
instrbusin[30] ={B, 26'b00000000000000000011101010};
daddrbusout[30] = dontcare;
databusin[30] = 64'bz;
databusout[30] = dontcare;
// op, rd, rn, rm
iname[31] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[31] = 64'h0000007C;
// op, rm, shamt, rn, rd
instrbusin[31] ={AND, R31, zeroSham, R31, R19};
daddrbusout[31] = dontcare;
databusin[31] = 64'bz;
databusout[31] = dontcare;
// op, rd, rn, rm
iname[32] ="ADD, R20, R21, R20";//testing branch address result in R20 = 0000000000000707
iaddrbusout[32] = 64'h00000420;
// op, rm, shamt, rn, rd
instrbusin[32] ={ADD, R20, zeroSham, R21, R20};
daddrbusout[32] = dontcare;
databusin[32] = 64'bz;
databusout[32] = dontcare;
//phase 6: testing B.EQ and B.NE branch
// op, rd, rn, rm
iname[33] ="ADDI, R21, R31, #AAA";//testing addi, result in R21 = 0000000000000AAA
iaddrbusout[33] = 64'h00000424;
// opcode rm/ALUImm rn rd
instrbusin[33] ={ADDI, 12'hAAA, R31, R21};
daddrbusout[33] = dontcare;
databusin[33] = 64'bz;
databusout[33] = dontcare;
// op, rd, rn, rm
iname[34] ="ADDI, R22, R31, #AAA";//testing addi, result in R22 = 0000000000000AAA
iaddrbusout[34] = 64'h00000428;
// opcode rm/ALUImm rn rd
instrbusin[34] ={ADDI, 12'hAAA, R31, R22};
daddrbusout[34] = dontcare;
databusin[34] = 64'bz;
databusout[34] = dontcare;
//ADDIS for FAKE BRANCH
// op, rd, rn, aluImm
iname[35] ="ADDIS,R31, R31, #420";//testing fake branch, this should NOT set the Z high
iaddrbusout[35] = 64'h0000042C;
// opcode rm/ALUImm rn rd
instrbusin[35] ={ADDIS, 12'h420, R31, R31};
daddrbusout[35] = dontcare;
databusin[35] = 64'bz;
databusout[35] = dontcare;
//FAKE BRANCH
// op, COND_addr, rt
iname[36] ="B_EQ, #69420, RX";//testing to NOT take the branch, Z should be LOW
iaddrbusout[36] = 64'h00000430;
// op, COND_addr, rt
instrbusin[36] ={B_EQ, 19'b1101001010000100000, RX};
daddrbusout[36] = dontcare;
databusin[36] = 64'bz;
databusout[36] = dontcare;
iname[37] = "NOP";//nada
iaddrbusout[37] = 64'h00000434;
instrbusin[37] = 64'b0;
daddrbusout[37] = dontcare;
databusin[37] = 64'bz;
databusout[37] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[38] ="SUBS, R31, R21, R22";//set z flag for BEQ,
iaddrbusout[38] = 64'h00000438;
// op, rm, shamt, rn, rd
instrbusin[38] ={SUBS, R22, zeroSham, R21, R31};
daddrbusout[38] = dontcare;
databusin[38] = 64'bz;
databusout[38] = dontcare;
//real branch for B.EQ (I have the best branches)
// op, COND_addr, rt
iname[39] ="B_EQ, #69, RX";//take the branch to instruction count ?
iaddrbusout[39] = 64'h0000043C;
// op, COND_addr, rt
instrbusin[39] ={B_EQ, 19'b0000000000001101001, RX};
//19'b
daddrbusout[39] = dontcare;
databusin[39] = 64'bz;
databusout[39] = dontcare;
iname[40] = "NOP";//nada
iaddrbusout[40] = 64'h00000440;
instrbusin[40] = 64'b0;
daddrbusout[40] = dontcare;
databusin[40] = 64'bz;
databusout[40] = dontcare;
iname[41] = "NOP";//nada
iaddrbusout[41] = 64'h000005E0;
instrbusin[41] = 64'b0;
daddrbusout[41] = dontcare;
databusin[41] = 64'bz;
databusout[41] = dontcare;
//use SUBS for branch test
// op, rd, rn, rm
iname[42] ="SUBS, R31, R21, R20";//set z flag of NOT for BNE
iaddrbusout[42] = 64'h000005E4;
// op, rm, shamt, rn, rd
instrbusin[42] ={SUBS, R20, zeroSham, R21, R31};
daddrbusout[42] = dontcare;
databusin[42] = 64'bz;
databusout[42] = dontcare;
//test B.NE
// op, COND_addr, rt
iname[43] ="B_NE, #96, RX";//take the branch to instruction count 840
iaddrbusout[43] = 64'h000005E8;
// op, COND_addr, rt
instrbusin[43] ={B_NE, 19'b0000000000010010110, RX};
daddrbusout[43] = dontcare;
databusin[43] = 64'bz;
databusout[43] = dontcare;
iname[44] = "NOP";//nada
iaddrbusout[44] = 64'h000005EC;
instrbusin[44] = 64'b0;
daddrbusout[44] = dontcare;
databusin[44] = 64'bz;
databusout[44] = dontcare;
iname[45] = "NOP";//nada
iaddrbusout[45] = 64'h00000840;
instrbusin[45] = 64'b0;
daddrbusout[45] = dontcare;
databusin[45] = 64'bz;
databusout[45] = dontcare;
//phase 7: testing CBNZ and CBZ branch
//DONT take the CBZ
// op, COND_addr, rt
iname[46] ="CBZ, #F, R22";//take the branch to instruction count
iaddrbusout[46] = 64'h00000844;
// op, COND_addr, rt
instrbusin[46] ={CBZ, 19'b0000000000000001111, R22};
daddrbusout[46] = dontcare;
databusin[46] = 64'bz;
databusout[46] = dontcare;
iname[47] = "NOP";//nada
iaddrbusout[47] = 64'h00000848;
instrbusin[47] = 64'b0;
daddrbusout[47] = dontcare;
databusin[47] = 64'bz;
databusout[47] = dontcare;
iname[48] = "NOP";//nada
iaddrbusout[48] = 64'h0000084C;
instrbusin[48] = 64'b0;
daddrbusout[48] = dontcare;
databusin[48] = 64'bz;
databusout[48] = dontcare;
//TAKE the CBZ
// op, COND_addr, rt
iname[49] ="CBZ, #21, R19";//take the branch to instruction count
iaddrbusout[49] = 64'h00000850;
// op, COND_addr, rt
instrbusin[49] ={CBZ, 19'b0000000000000100001, R19};
daddrbusout[49] = dontcare;
databusin[49] = 64'bz;
databusout[49] = dontcare;
iname[50] = "NOP";//nada
iaddrbusout[50] = 64'h00000854;
instrbusin[50] = 64'b0;
daddrbusout[50] = dontcare;
databusin[50] = 64'bz;
databusout[50] = dontcare;
iname[51] = "NOP";//nada
iaddrbusout[51] = 64'h000008D4;
instrbusin[51] = 64'b0;
daddrbusout[51] = dontcare;
databusin[51] = 64'bz;
databusout[51] = dontcare;
//DONT take the CBNZ
// op, COND_addr, rt
iname[52] ="CBNZ, #FF, R31";//take the branch to instruction count
iaddrbusout[52] = 64'h000008D8;
// op, COND_addr, rt
instrbusin[52] ={CBNZ, 19'b0000000000011111111, R31};
daddrbusout[52] = dontcare;
databusin[52] = 64'bz;
databusout[52] = dontcare;
iname[53] = "NOP";//nada
iaddrbusout[53] = 64'h000008DC;
instrbusin[53] = 64'b0;
daddrbusout[53] = dontcare;
databusin[53] = 64'bz;
databusout[53] = dontcare;
iname[54] = "NOP";//nada
iaddrbusout[54] = 64'h000008E0;
instrbusin[54] = 64'b0;
daddrbusout[54] = dontcare;
databusin[54] = 64'bz;
databusout[54] = dontcare;
//TAKE the CBNZ
// op, COND_addr, rt
iname[55] ="CBNZ, #22, R20";//take the branch to instruction count
iaddrbusout[55] = 64'h000008E4;
// op, COND_addr, rt
instrbusin[55] ={CBNZ, 19'b0000000000000100010, R20};
daddrbusout[55] = dontcare;
databusin[55] = 64'bz;
databusout[55] = dontcare;
iname[56] = "NOP";//nada
iaddrbusout[56] = 64'h000008E8;
instrbusin[56] = 64'b0;
daddrbusout[56] = dontcare;
databusin[56] = 64'bz;
databusout[56] = dontcare;
iname[57] = "NOP";//nada
iaddrbusout[57] = 64'h0000096C;
instrbusin[57] = 64'b0;
daddrbusout[57] = dontcare;
databusin[57] = 64'bz;
databusout[57] = dontcare;
//phase 8: testing MOVEZ and overflow bit
//4 instructions to set registers to 0
// op, rd, rn, rm
iname[58] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[58] = 64'h00000970;
// op, rm, shamt, rn, rd
instrbusin[58] ={AND, R31, zeroSham, R31, R19};
daddrbusout[58] = dontcare;
databusin[58] = 64'bz;
databusout[58] = dontcare;
// op, rd, rn, rm
iname[59] ="AND, R20, R31, R31";//delay, result in R20 = 0000000000000000
iaddrbusout[59] = 64'h00000974;
// op, rm, shamt, rn, rd
instrbusin[59] ={AND, R31, zeroSham, R31, R20};
daddrbusout[59] = dontcare;
databusin[59] = 64'bz;
databusout[59] = dontcare;
// op, rd, rn, rm
iname[60] ="AND, R21, R31, R31";//delay, result in R21 = 0000000000000000
iaddrbusout[60] = 64'h00000978;
// op, rm, shamt, rn, rd
instrbusin[60] ={AND, R31, zeroSham, R31, R21};
daddrbusout[60] = dontcare;
databusin[60] = 64'bz;
databusout[60] = dontcare;
// op, rd, rn, rm
iname[61] ="AND, R22, R31, R31";//delay, result in R22 = 0000000000000000
iaddrbusout[61] = 64'h0000097C;
// op, rm, shamt, rn, rd
instrbusin[61] ={AND, R31, zeroSham, R31, R22};
daddrbusout[61] = dontcare;
databusin[61] = 64'bz;
databusout[61] = dontcare;
//4 MOVZ commands
//move 0 amt
// op, move_amt, MOV_imm, rd
iname[62] ="MOVZ, move_0, #FFFF, R19";//testing move, result in R19 = 000000000000FFFF
iaddrbusout[62] = 64'h00000980;
// op, move_amt, MOV_imm, rd
instrbusin[62] ={MOVZ, move_0, 16'hFFFF, R19};
daddrbusout[62] = dontcare;
databusin[62] = 64'bz;
databusout[62] = dontcare;
//move 1 amt
// op, move_amt, MOV_imm, rd
iname[63] ="MOVZ, move_1, #FFFF, R20";//testing move, result in R20 = 00000000FFFF0000
iaddrbusout[63] = 64'h00000984;
// op, move_amt, MOV_imm, rd
instrbusin[63] ={MOVZ, move_1, 16'hFFFF, R20};
daddrbusout[63] = dontcare;
databusin[63] = 64'bz;
databusout[63] = dontcare;
//move 2 amt
// op, move_amt, MOV_imm, rd
iname[64] ="MOVZ, move_2, #FFFF, R21";//testing move, result in R21 = 0000FFFF00000000
iaddrbusout[64] = 64'h00000988;
// op, move_amt, MOV_imm, rd
instrbusin[64] ={MOVZ, move_2, 16'hFFFF, R21};
daddrbusout[64] = dontcare;
databusin[64] = 64'bz;
databusout[64] = dontcare;
//move 3 amt
// op, move_amt, MOV_imm, rd
iname[65] ="MOVZ, move_3, #7FFF, R22";//testing move, result in R22 = 7FFF000000000000
iaddrbusout[65] = 64'h0000098C;
// op, move_amt, MOV_imm, rd
instrbusin[65] ={MOVZ, move_3, 16'h7FFF, R22};
daddrbusout[65] = dontcare;
databusin[65] = 64'bz;
databusout[65] = dontcare;
//have or for move 0 and move 1
// op, rd, rn, rm
iname[66] ="ORR, R23, R19, R20";//testing xor, result in R23 = 00000000FFFFFFFF
iaddrbusout[66] = 64'h00000990;
// op, rm, shamt, rn, rd
instrbusin[66] ={ORR, R20, zeroSham, R19, R23};
daddrbusout[66] = dontcare;
databusin[66] = 64'bz;
databusout[66] = dontcare;
//delay
iname[67] = "NOP";//nada
iaddrbusout[67] = 64'h00000994;
instrbusin[67] = 64'b0;
daddrbusout[67] = dontcare;
databusin[67] = 64'bz;
databusout[67] = dontcare;
//have or for move 2 and move 3
// op, rd, rn, rm
iname[68] ="ORR, R24, R21, R22";//testing xor, result in R27 = 7FFFFFFF00000000
iaddrbusout[68] = 64'h00000998;
// op, rm, shamt, rn, rd
instrbusin[68] ={ORR, R22, zeroSham, R21, R24};
daddrbusout[68] = dontcare;
databusin[68] = 64'bz;
databusout[68] = dontcare;
//delay
iname[69] = "NOP";//nada
iaddrbusout[69] = 64'h0000099C;
instrbusin[69] = 64'b0;
daddrbusout[69] = dontcare;
databusin[69] = 64'bz;
databusout[69] = dontcare;
//delay
iname[70] = "NOP";//nada
iaddrbusout[70] = 64'h000009A0;
instrbusin[70] = 64'b0;
daddrbusout[70] = dontcare;
databusin[70] = 64'bz;
databusout[70] = dontcare;
//have or for move(0|1) and move(2|3)
// op, rd, rn, rm
iname[71] ="ORR, R25, R23, R24";//testing xor, result in R25 = 7FFFFFFFFFFFFFFF
iaddrbusout[71] = 64'h000009A4;
// op, rm, shamt, rn, rd
instrbusin[71] ={ORR, R24, zeroSham, R23, R25};
daddrbusout[71] = dontcare;
databusin[71] = 64'bz;
databusout[71] = dontcare;
//dealy
iname[72] = "NOP";//nada
iaddrbusout[72] = 64'h000009A8;
instrbusin[72] = 64'b0;
daddrbusout[72] = dontcare;
databusin[72] = 64'bz;
databusout[72] = dontcare;
//delay
iname[73] = "NOP";//nada
iaddrbusout[73] = 64'h000009AC;
instrbusin[73] = 64'b0;
daddrbusout[73] = dontcare;
databusin[73] = 64'bz;
databusout[73] = dontcare;
//addis command to trigger the V bit
// op, rd, rn, aluImm
iname[74] ="ADDIS,R26, R25, #001";//testing xor and V bit, result in R26 = 8000000000000000
iaddrbusout[74] = 64'h000009B0;
// opcode rm/ALUImm rn rd
instrbusin[74] ={ADDIS, 12'h001, R25, R26};
daddrbusout[74] = dontcare;
databusin[74] = 64'bz;
databusout[74] = dontcare;
iname[75] = "NOP";//nada
iaddrbusout[75] = 64'h000009B4;
instrbusin[75] = 64'b0;
daddrbusout[75] = dontcare;
databusin[75] = 64'bz;
databusout[75] = dontcare;
iname[76] = "NOP";//nada
iaddrbusout[76] = 64'h000009B8;
instrbusin[76] = 64'b0;
daddrbusout[76] = dontcare;
databusin[76] = 64'bz;
databusout[76] = dontcare;
//finishing up
iname[77] = "NOP";//nada
iaddrbusout[77] = 64'h000009BC;
instrbusin[77] = 64'b0;
daddrbusout[77] = dontcare;
databusin[77] = 64'bz;
databusout[77] = dontcare;
iname[78] = "NOP";//nada
iaddrbusout[78] = 64'h000009C0;
instrbusin[78] = 64'b0;
daddrbusout[78] = dontcare;
databusin[78] = 64'bz;
databusout[78] = dontcare;
iname[79] = "NOP";//nada
iaddrbusout[79] = 64'h000009C4;
instrbusin[79] = 64'b0;
daddrbusout[79] = dontcare;
databusin[79] = 64'bz;
databusout[79] = dontcare;
iname[80] = "NOP";//nada
iaddrbusout[80] = 64'h000009C8;
instrbusin[80] = 64'b0;
daddrbusout[80] = dontcare;
databusin[80] = 64'bz;
databusout[80] = dontcare;
iname[81] = "NOP";//nada
iaddrbusout[81] = 64'h000009CC;
instrbusin[81] = 64'b0;
daddrbusout[81] = dontcare;
databusin[81] = 64'bz;
databusout[81] = dontcare;
//remember to set k down below to ntests - 1
ntests = 82;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
assign databus = clkd ? 64'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
databusk = 64'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 81; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set load data for 3rd previous instruction
if (k >=3)
databusk = databusin[k-3];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b %b %b %b %b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check data address from 3rd previous instruction
if ( (k >= 3) && (daddrbusout[k-3] !== dontcare) ) begin
$display (" Testing data address for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your daddrbus = %b", daddrbus);
$display (" Correct daddrbus = %b", daddrbusout[k-3]);
if (daddrbusout[k-3] !== daddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check store data from 3rd previous instruction
if ( (k >= 3) && (databusout[k-3] !== dontcare) ) begin
$display (" Testing store data for instruction %d:", k-3);
$display (" %s", iname[k-3]);
$display (" Your databus = %b", databus);
$display (" Correct databus = %b", databusout[k-3]);
if (databusout[k-3] !== databus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
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// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// possibility of the same.
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// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
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// applications related to the deployment of airbags, or any
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP0 = "IODELAY_MIG0",
// May be assigned unique name when
// multiple IP cores used in design
parameter IODELAY_GRP1 = "IODELAY_MIG1",
// May be assigned unique name when
// multiple IP cores used in design
parameter REFCLK_TYPE = "DIFFERENTIAL",
// Reference clock type
// "DIFFERENTIAL","SINGLE_ENDED"
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter RST_ACT_LOW = 1,
// Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination
parameter FPGA_SPEED_GRADE = 1,
// FPGA speed grade
parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE"
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output [1:0] clk_ref,
output sys_rst_o,
output [1:0] iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_ibufg;
wire clk_ref_mmcm_300;
wire clk_ref_mmcm_400;
wire mmcm_clkfbout;
wire mmcm_Locked;
wire [1:0] rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// If the pin is selected for sys_rst in GUI, IBUF will be instantiated.
// If the pin is not selected in GUI, sys_rst signal is expected to be
// driven internally.
generate
if (SYS_RST_PORT == "TRUE")
IBUF u_sys_rst_ibuf
(
.I (sys_rst),
.O (sys_rst_o)
);
else
assign sys_rst_o = sys_rst;
endgenerate
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;
//***************************************************************************
// 1) Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input. Global clock buffer is used to
// drive the rest of FPGA logic.
// 2) For NO_BUFFER option, Reference clock will be driven from internal
// clock i.e., clock is driven from fabric. Input buffers and Global
// clock buffers will not be instaitaed.
// 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used
// as the input reference clock. Global clock buffer is used to drive
// the rest of FPGA logic.
//***************************************************************************
generate
if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
end else if ((REFCLK_TYPE == "NO_BUFFER") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf
assign clk_ref_ibufg = clk_ref_i;
end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf
assign clk_ref_ibufg = clk_ref_i;
end
endgenerate
// reference clock 300MHz and 400MHz generation with MMCM
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (4),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (3),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5),
.REF_JITTER1 (0.000))
mmcm_i
// Output clocks
(.CLKFBOUT (mmcm_clkfbout),
.CLKFBOUTB (),
.CLKOUT0 (clk_ref_mmcm_300),
.CLKOUT0B (),
.CLKOUT1 (clk_ref_mmcm_400),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (mmcm_clkfbout),
.CLKIN1 (clk_ref_ibufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (mmcm_Locked),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (sys_rst_act_hi));
end
endgenerate
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en
if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300
BUFG u_bufg_clk_ref_300
(
.O (clk_ref[1]),
.I (clk_ref_mmcm_300)
);
end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400
BUFG u_bufg_clk_ref_400
(
.O (clk_ref[1]),
.I (clk_ref_mmcm_400)
);
end
end
endgenerate
generate
if ((REFCLK_TYPE == "DIFFERENTIAL") ||
(REFCLK_TYPE == "SINGLE_ENDED") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200
BUFG u_bufg_clk_ref
(
.O (clk_ref[0]),
.I (clk_ref_ibufg)
);
end else begin: clk_ref_200_no_buffer
assign clk_ref[0] = clk_ref_i;
end
endgenerate
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1
always @(posedge clk_ref[1] or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1;
assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1];
end
endgenerate
always @(posedge clk_ref[0] or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1;
assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1];
//*****************************************************************
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1
(* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400
(
.RDY (iodelay_ctrl_rdy[1]),
.REFCLK (clk_ref[1]),
.RST (rst_ref[1])
);
end
endgenerate
(* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200
(
.RDY (iodelay_ctrl_rdy[0]),
.REFCLK (clk_ref[0]),
.RST (rst_ref[0])
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/**********************
* Constant cache core
*
* This module replicates as many block RAMs as is necessary to achieve the
* desired NUMPORTS, each of which is read-only and referred to as rdports.
* All block RAMs are double-pumped to achieve 4 read ports, this results in a
* 4 cycle latency plus 1 to resolve hit/misses. The data must be present in
* the cache on the first cycle for it to be a cache hit.
*
* The cache is optimized for cache hits only. Requests flow through a given
* cache rdport in a fully pipelined fashion, however once there's a miss,
* that rdport (i) stalls; (ii) services all currently queued requests in
* order; (iii) resumes accepting requests once the queue is empty.
*
* Normally the requests are pipelined alongside the accesses to the cache's
* block RAMs, however once stalled (due to a miss) only the requests are
* stalled while the cache block RAMs are continuously fed the missed request
* until it hits. Then the pipeline drains the copies of these missed request
* and resumes pipelining the requests along with the block RAMs. Because of
* this, there's basically two pipelines you can think of. The request
* pipeline and the cache memory blocks pipeline. Illustrated below.
*
* For example let's say we have the following access pattern with lower case
* indicating a hit, and upper a miss: abCdefgh. Also let's assume the
* CACHE_LATENCY is 5 so that the 5th stage resolves hits/misses.
*
* Request Queue (5 stages) Cache Memory Blocks (4 stages)
* 12345 1234 state
* +-----+ +-----+
* t=0 a| | a| | PIPELINE
* t=1 b|a | b|a |
* t=2 C|ba | C|ba |
* ... d|Cba | d|Cba |
* e|dCba | e|dCba |
* f|edCba|a hits and returns f|edCb |
* g|fedCb|b hits and returns g|fedC |
* h|gfedC|!miss! stall! C|gfed |
* h|gfedC|stall! C|Cgfe | FILL
* h|gfedC|stall! C|CCgf |
* h|gfedC|stall! C|CCCg |
* h|gfedC|stall! C|CCCC | MISS
* h|gfedC|stall! C|CCCC |
* h|gfedC|stall! C arrives C|CCCC |
* h|gfedC|C hits and returns C|CCCC |
* h| gfed| d|CCCC | DRAIN
* h|d gfe| e|dCCC |
* h|ed gf| f|edCC |
* h|fed g| g|fedC |
* h|gfed | h|gfed | PIPELINE
* |hgfed|d hits and returns |hgfe |
* | hgfe|e hits and returns | hgf |
* | hgf|f hits and returns | hg |
* | hg|g hits and returns | h |
* t=n | h| | |
* +-----+ +-----+
*
*
* There is only one write port for the entire cache, it is used to receive
* and store data read from global memory. This is referred to as the fill
* port (fills the cache with data).
*
* The snoop support takes an incoming stream of snooped writes (in a separate
* clock domain), and buffers them in a dc_fifo which i) converts to the local
* clock domain; and ii) flushes the entire cache if it overflows. This means
* functionality is preserved in the case where we're receiving invalidations
* quicker than we can service them. More details about how the snooping
* actually works can be found in that module.
*
* Stages
* | 0 | 1 | 2 | 3 | 4 | 5 | 6 |
* rdport_ hit_comb hit
* cache_ cache_ miss
*
* WARNING - this module ASSUMES read_during_write_mode_mixed_ports is OLD_DATA
*
* TODO:
* a) Make sure flush doesn't hang outstanding requests by killing the fetch
* b) Add byteenable to fill port support cache width > mem width
* c) (optional) Support cache_waitrequest - right now doesn't work but is unused
**********************/
module acl_const_cache
#(
parameter NUMPORTS=13, // Number of ports desired
parameter LOG2SIZE=10, //in bytes
parameter LOG2WIDTH=5, //in bits
parameter AWIDTH=32, //Word address width
parameter WIDTH=2**LOG2WIDTH,
parameter MWIDTH=WIDTH,
parameter MAWIDTH=AWIDTH-$clog2(MWIDTH/WIDTH), //Word address width
parameter BURSTWIDTH=6
)
(
input clk,
input clk2x,
input resetn,
// Cache fill port interface
output [MAWIDTH-1:0] fill_addr, //word-address
output fill_read,
input fill_waitrequest,
input fill_readdatavalid,
input [MWIDTH-1:0] fill_readdata,
input tri0 flush_cache,
// Snoop port interface - if address is cached invalidate it
input snoop_clk,
input snoop_overflow,
input [MAWIDTH-1:0] snoop_addr, //word-address
input [BURSTWIDTH-1:0] snoop_burst,
input snoop_write,
output snoop_ready,
// Cache ports interfaces
input [NUMPORTS*AWIDTH-1:0] rdport_addr, //word-address
input [NUMPORTS-1:0] rdport_read,
output [NUMPORTS-1:0] rdport_waitrequest,
output [NUMPORTS-1:0] rdport_readdatavalid,
output reg [NUMPORTS*WIDTH-1:0] rdport_readdata
);
/******************
* LOCAL PARAMETERS
*******************/
localparam USE2XCLOCK=(NUMPORTS>1);
localparam CACHE_LATENCY=(USE2XCLOCK ? 4 : 2) + 1;
localparam LOG2NUMCACHEENTRIES=LOG2SIZE-(LOG2WIDTH-3);
// Address is byte address
//localparam TAGSIZE=AWIDTH-LOG2SIZE;
//`define TAGRANGE AWIDTH-1:LOG2SIZE
//`define OFFSETRANGE LOG2SIZE-1:LOG2WIDTH-3
// Address is word address (word size defined by WIDTH)
localparam TAGSIZE=AWIDTH-(LOG2SIZE-LOG2WIDTH+3);
`define TAGRANGE AWIDTH-1:LOG2SIZE-LOG2WIDTH+3
`define OFFSETRANGE LOG2SIZE-(LOG2WIDTH-3)-1:0
localparam DEVICE_BLOCKRAM_BITS = 8192; //Stratix IV M9Ks
localparam SNOOP_BURSTWIDTH = BURSTWIDTH + $clog2(MWIDTH/WIDTH);
/******************
* SIGNALS
*******************/
reg [NUMPORTS-1:0] _rdport_readdatavalid;
reg [NUMPORTS-1:0] hit; // Cache hit signal (registered)
reg [NUMPORTS-1:0] miss; // Cache miss signal (registered)
wire [NUMPORTS-1:0] hit_comb; // Cache hit signal
wire [NUMPORTS-1:0] miss_comb; // Cache miss signal
wire [NUMPORTS-1:0] en; // Pipeline enable signal for the cache
wire [NUMPORTS-1:0] rotate; // Rotate the pipeline to replay requests
wire [NUMPORTS-1:0] cache_valid;
wire [NUMPORTS-1:0] cache_read;
wire [NUMPORTS*AWIDTH-1:0] cache_addr_full;
wire [NUMPORTS*LOG2NUMCACHEENTRIES-1:0] cache_addr;
wire [NUMPORTS-1:0] cache_readdatavalid;
wire [NUMPORTS*WIDTH-1:0] cache_readdata;
wire [NUMPORTS-1:0] cache_waitrequest;
wire [NUMPORTS*TAGSIZE-1:0] cache_tagout;
wire [AWIDTH-1:0] fill_readdata_addr;
reg [AWIDTH-1:0] fill_readdata_addr_r;
reg fill_readdatavalid_r;
reg [WIDTH-1:0] fill_readdata_r;
wire [AWIDTH-1:0] fill_cc_addr; //word-address of cache
// Snoop signals
reg [AWIDTH-1:0] valid_addr;
reg valid_writedata;
reg valid_write;
wire [AWIDTH-1:0] invalidate_addr;
wire invalidate_en;
wire snoop_stall;
localparam [1:0] s_INVALIDATE=2'b00;
localparam [1:0] s_FILL=2'b01;
localparam [1:0] s_FLUSH=2'b10;
wire [1:0] valid_sel;
// Cache flush signals
reg [LOG2NUMCACHEENTRIES-1:0] flush_counter;
reg flushing;
wire flush_overflow;
wire do_flush; // one cycle pulse
wire [CACHE_LATENCY*AWIDTH-1:0] queued_addr[NUMPORTS-1:0];
wire [CACHE_LATENCY-1:0] queued_read[NUMPORTS-1:0];
wire [AWIDTH-1:0] _cache_addr_full[NUMPORTS-1:0];
wire [AWIDTH-1:0] compare_addr[NUMPORTS-1:0];
wire [NUMPORTS-1:0] compare_read;
wire [AWIDTH-1:0] miss_addr[NUMPORTS-1:0];
wire [NUMPORTS-1:0] miss_read;
reg [NUMPORTS-1:0] miss_issued;
reg [NUMPORTS*AWIDTH-1:0] upstream_arb_addr;
reg [NUMPORTS-1:0] upstream_arb_read;
wire [NUMPORTS-1:0] miss_waitrequest;
wire clockcross_overflow;
reg [1:0] state[NUMPORTS-1:0];
reg [3:0] count[NUMPORTS-1:0]; // Must be able to store CACHE_LATENCY
localparam p_PIPELINE=2'b00;
localparam p_FILL=2'b01;
localparam p_MISS=2'b10;
localparam p_DRAIN=2'b11;
/******************
* ARCHITECTURE
*******************/
/********************
* The cache accepts requests in a pipelined fashion. By the time a single
* request has been resolved (hit or miss) several requests are already in
* flight in the cache's pipeline. We have a few states to deal with this:
* PIPELINE - requests are being pipelined through, default behaviour
* FILL - A miss has occurred so we must fill the cache only with copies of
* the missed request. During this time we ignore hit/miss
* discoveries of the requests behind the miss and stall
* MISS - At this point the pipeline is filled with requests from the
* miss, we wait for one of these to hit to return the data
* DRAIN - The miss was completed, we rotate the unserved requests stalled
* behind it and ignore hits/misses from the copies of the miss
**********************/
generate
genvar p;
for (p=0; p<NUMPORTS; p=p+1)
begin : portgen
always@(posedge clk or negedge resetn)
begin
if (!resetn)
begin
state[p] <= p_PIPELINE;
count[p] <= {4{1'b0}};
end
else
begin
case (state[p])
p_PIPELINE:
begin
state[p]<= (miss[p]) ? p_FILL : p_PIPELINE;
count[p]<=CACHE_LATENCY-1;
end
p_FILL:
begin
state[p]<= (count[p]==0) ? p_MISS : p_FILL;
count[p]<=count[p]-2'b01;
end
p_MISS:
begin
state[p]<= (hit[p]) ? p_DRAIN : p_MISS;
count[p]<=CACHE_LATENCY-1;
end
p_DRAIN:
begin
state[p]<= (count[p]==0) ? p_PIPELINE : p_DRAIN;
count[p]<=count[p]-2'b01;
end
endcase
end
end
// State passed along in request pipeline
// addr - the address
// read - tells us if this is actually a read request vs nop
pipe # (.WIDTH(AWIDTH), .DEPTH(CACHE_LATENCY)) request_queue
( .clk(clk), .resetn(resetn),
.en({CACHE_LATENCY{en[p]}}),
.d( rotate[p] ? queued_addr[p][(CACHE_LATENCY-1)*AWIDTH +: AWIDTH] :
rdport_addr[p*AWIDTH +: AWIDTH]),
.q( queued_addr[p]));
pipe # (.WIDTH(1), .DEPTH(CACHE_LATENCY)) request_queue_read
( .clk(clk), .resetn(resetn),
.en({CACHE_LATENCY{en[p]}}),
.d( (!rotate[p]) ? rdport_read[p] :
queued_read[p][CACHE_LATENCY-1]),
.q( queued_read[p]));
assign en[p]=((state[p]==p_PIPELINE && !miss[p]) || (state[p]==p_MISS && hit[p]) || state[p]==p_DRAIN) && !cache_waitrequest[p];
assign rotate[p]=state[p]==p_DRAIN || flushing;
//These are the signals that actually feed the cache inputs
assign cache_read[p]=(state[p]==p_PIPELINE) ?
rdport_read[p] :
queued_read[p][CACHE_LATENCY-1] ;
assign cache_addr_full[p*AWIDTH +: AWIDTH]=(state[p]==p_PIPELINE) ?
rdport_addr[p*AWIDTH +: AWIDTH] :
queued_addr[p][(CACHE_LATENCY-1)*AWIDTH +: AWIDTH];
assign _cache_addr_full[p]=cache_addr_full[p*AWIDTH +: AWIDTH];
assign cache_addr[p*LOG2NUMCACHEENTRIES +: LOG2NUMCACHEENTRIES] = _cache_addr_full[p][`OFFSETRANGE];
//Get the addr of 2nd last stage to do tag comparison
assign compare_addr[p]= (state[p]==p_MISS || (state[p]==p_FILL && count[p]==0)) ?
queued_addr[p][(CACHE_LATENCY-1)*AWIDTH +: AWIDTH] :
queued_addr[p][(CACHE_LATENCY-2)*AWIDTH +: AWIDTH] ;
assign compare_read[p]= (state[p]==p_MISS || (state[p]==p_FILL && count[p]==0)) ?
queued_read[p][CACHE_LATENCY-1] :
queued_read[p][CACHE_LATENCY-2] ;
// The pipeline freezes when there is a miss, we need to track whether
// the miss was issued or not to re-issue if the arbitration stalls
always@(posedge clk or negedge resetn)
begin
if (!resetn)
miss_issued[p] <= 1'b0;
else if (state[p]==p_MISS && hit[p]) // Order matters!
miss_issued[p]=1'b0;
else if (miss_read[p] && !miss_waitrequest[p])
miss_issued[p]=1'b1;
end
//Get the last stage of the shift register to issue miss request
//Issue miss if it hasn't been issued already
assign miss_addr[p]=queued_addr[p][(CACHE_LATENCY-1)*AWIDTH +: AWIDTH];
assign miss_read[p]= queued_read[p][CACHE_LATENCY-1] &&
((miss[p] && state[p]==p_PIPELINE) ||
(!miss_issued[p] && (state[p]==p_FILL || (state[p]==p_MISS && !hit[p]))));
//Last stage of cache lookup computes hit or miss (registered)
always@(posedge clk or negedge resetn)
if (!resetn)
begin
hit[p]<=1'b0;
miss[p]<=1'b0;
end
else
begin
hit[p]<=hit_comb[p];
miss[p]<=miss_comb[p];
end
assign hit_comb[p]=cache_valid[p]===1'b1 && compare_read[p] &&
(cache_tagout[p*TAGSIZE +: TAGSIZE]==compare_addr[p][`TAGRANGE]);
assign miss_comb[p]=compare_read[p] && (cache_valid[p]!==1'b1 ||
(cache_tagout[p*TAGSIZE +: TAGSIZE]!=compare_addr[p][`TAGRANGE]));
assign rdport_waitrequest[p]=cache_waitrequest[p] || flushing ||
!((state[p]==p_PIPELINE && !miss[p]) || (state[p]==p_MISS && hit[p]));
assign rdport_readdatavalid[p]=_rdport_readdatavalid[p] &&
(state[p]==p_PIPELINE ||state[p]==p_MISS);
always@(posedge clk)
_rdport_readdatavalid[p]<=cache_readdatavalid[p] && hit_comb[p];
always@(posedge clk)
rdport_readdata[p*WIDTH +: WIDTH]<=cache_readdata[p*WIDTH +: WIDTH];
end
endgenerate
// Width Adapter on fill port
generate
if (MWIDTH > WIDTH)
begin
reg [AWIDTH-1:0] fill_readdata_addr_r0; // Width adapted signals
reg fill_readdatavalid_r0;
reg [MWIDTH-1:0] fill_readdata_r0;
//Register fill data before broadcasting it
always@(posedge clk)
fill_readdatavalid_r<=fill_readdatavalid_r0;
always@(posedge clk)
fill_readdata_r<=fill_readdata_r0[fill_readdata_addr_r0[$clog2(MWIDTH/WIDTH)-1:0]*WIDTH +: WIDTH];
always@(posedge clk)
fill_readdata_addr_r<=fill_readdata_addr_r0;
always@(posedge clk) fill_readdatavalid_r0<=fill_readdatavalid;
always@(posedge clk) fill_readdata_r0<=fill_readdata;
always@(posedge clk) fill_readdata_addr_r0<=fill_readdata_addr;
end
else
begin
//Register fill data before broadcasting it
always@(posedge clk)
fill_readdatavalid_r<=fill_readdatavalid;
always@(posedge clk)
fill_readdata_r<=fill_readdata;
always@(posedge clk)
fill_readdata_addr_r<=fill_readdata_addr;
end
endgenerate
assign fill_addr = fill_cc_addr >> $clog2(MWIDTH/WIDTH);
acl_multireadport_mem
#(
.LOG2DEPTH(LOG2NUMCACHEENTRIES),
.WIDTH(1),
.NUMPORTS(NUMPORTS),
.USE2XCLOCK(USE2XCLOCK),
.DEDICATED_BROADCAST_PORT(1)
)
valid (
.clk(clk),
.clk2x(clk2x),
.resetn(resetn),
.broadcast_addr(valid_addr),
.broadcast_writedata(valid_writedata),
.broadcast_read(),
.broadcast_write(valid_write),
.rdport_addr(cache_addr),
.rdport_read(cache_read),
.rdport_waitrequest(cache_waitrequest),
.rdport_readdatavalid(),
.rdport_readdata(cache_valid)
);
acl_multireadport_mem
#(
.LOG2DEPTH(LOG2NUMCACHEENTRIES),
.WIDTH(TAGSIZE),
.NUMPORTS(NUMPORTS),
.USE2XCLOCK(USE2XCLOCK),
.DEDICATED_BROADCAST_PORT(1)
)
tag (
.clk(clk),
.clk2x(clk2x),
.resetn(resetn),
.broadcast_addr(fill_readdata_addr_r[`OFFSETRANGE]),
.broadcast_writedata(fill_readdata_addr_r[`TAGRANGE]),
.broadcast_write(fill_readdatavalid_r),
.rdport_addr(cache_addr),
.rdport_read(cache_read),
.rdport_waitrequest(),
.rdport_readdatavalid(),
.rdport_readdata(cache_tagout)
);
acl_multireadport_mem
#(
.LOG2DEPTH(LOG2NUMCACHEENTRIES),
.WIDTH(WIDTH),
.NUMPORTS(NUMPORTS),
.USE2XCLOCK(USE2XCLOCK),
.DEDICATED_BROADCAST_PORT(1)
)
data (
.clk(clk),
.clk2x(clk2x),
.resetn(resetn),
.broadcast_addr(fill_readdata_addr_r[`OFFSETRANGE]),
.broadcast_writedata(fill_readdata_r),
.broadcast_write(fill_readdatavalid_r),
.rdport_addr(cache_addr),
.rdport_read(cache_read),
.rdport_waitrequest(),
.rdport_readdatavalid(cache_readdatavalid),
.rdport_readdata(cache_readdata)
);
// FIFO to store address of fetched data
scfifo scfifo_component (
.clock (clk),
.data (fill_cc_addr),
.rdreq ((fill_readdatavalid)),
.sclr (),
.wrreq ((fill_read&~fill_waitrequest)),
.empty (),
.full (),
.q (fill_readdata_addr),
.aclr (~resetn),
.almost_empty (),
.almost_full (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = DEVICE_BLOCKRAM_BITS/AWIDTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = AWIDTH,
scfifo_component.lpm_widthu = $clog2(DEVICE_BLOCKRAM_BITS/AWIDTH),
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
// Convert 2-D arrays into 1-D bit vector
integer pa;
always@*
begin
upstream_arb_addr={NUMPORTS*AWIDTH{1'b0}};
upstream_arb_read={NUMPORTS{1'b0}};
for (pa=NUMPORTS-1; pa>=0; pa=pa-1)
begin
upstream_arb_addr={NUMPORTS*AWIDTH{1'b0}} |
(upstream_arb_addr<<AWIDTH) |
miss_addr[pa];
upstream_arb_read={NUMPORTS{1'b0}} | (upstream_arb_read<<1) |
(miss_read[pa]);
end
end
/********************************************
* + Arbitrate between all fill requests - options:
* a) Push to SOPC - but then must arbitrate between readdata
* b) Build my own
*
* Do b) although simplified - don't have to steer data back to
* each requesting unit. Updates are global to all ports
*********************************************/
cachefill_arbiter #(.WIDTH(AWIDTH), .NUMPORTS(NUMPORTS)) arb (
.clk(clk),
.resetn(resetn),
.addr(upstream_arb_addr),
.read(upstream_arb_read),
.waitrequest(miss_waitrequest),
.fill_addr(fill_cc_addr),
.fill_read(fill_read),
.fill_waitrequest(fill_waitrequest));
// Flush logic - invalidate all entries in cache
// The cache gets flushed when the snoop fifo overflows
assign do_flush = (flush_counter==0 && (flush_cache || flush_overflow));
always@(posedge clk or negedge resetn)
if (!resetn)
flush_counter<={LOG2NUMCACHEENTRIES{1'b0}};
else if (do_flush)
flush_counter<={LOG2NUMCACHEENTRIES{1'b1}};
else if (flush_counter!=0 && valid_sel==s_FLUSH)
flush_counter<=flush_counter-1;
always@(posedge clk)
flushing<=do_flush || !(flush_counter==0);
// Snoop datapath - fifo, filter, burst chunks, tag check
acl_snoop
#(
.LOG2SIZE(LOG2SIZE),
.LOG2WIDTH(LOG2WIDTH),
.AWIDTH(AWIDTH),
.WIDTH(WIDTH),
.BURSTWIDTH(SNOOP_BURSTWIDTH)
) snoop_datapath (
.clk(clk),
.resetn(resetn),
.flush(flushing),
.fill_readdata_addr(fill_readdata_addr_r),
.fill_readdatavalid(fill_readdatavalid_r),
.snoop_clk(snoop_clk),
.snoop_overflow(snoop_overflow),
.snoop_addr({64'b0,snoop_addr} * MWIDTH/WIDTH),
.snoop_burst(snoop_burst * MWIDTH/WIDTH),
.snoop_valid(snoop_write),
.snoop_stall(snoop_stall),
.invalidate_addr(invalidate_addr),
.invalidate_en(invalidate_en),
.invalidate_waitrequest((valid_sel!=s_INVALIDATE)),
.overflow(flush_overflow));
assign snoop_ready = ~snoop_stall;
// Multiplexer for valid bit - between filldata, snoop invalidations, or flush
// We always service readdata coming in first, since user must ensure data is
// not modified while kernel active so these should be valid requests.
assign valid_sel = (fill_readdatavalid_r) ? s_FILL :
(flushing) ? s_FLUSH : s_INVALIDATE;
always@*
valid_addr<= (valid_sel==s_FLUSH) ? flush_counter :
(valid_sel==s_INVALIDATE) ? invalidate_addr :
fill_readdata_addr_r[`OFFSETRANGE];
always@*
valid_write<= (valid_sel==s_FLUSH) ? 1'b1 :
(valid_sel==s_INVALIDATE) ? invalidate_en :
fill_readdatavalid_r;
always@*
valid_writedata<= (valid_sel==s_FLUSH) ? 1'b0 :
(valid_sel==s_INVALIDATE) ? 1'b0 : 1'b1;
endmodule
/***************************************************************
* Simple (Shift Register) Arbiter
* Register all requests and shift out requests to global memory. Stall the port
* if the register is occupied.
**************************************************************/
module cachefill_arbiter #(parameter WIDTH=32, parameter NUMPORTS=4)
(
input clk,
input resetn,
input [NUMPORTS*WIDTH-1:0] addr,
input [NUMPORTS-1:0] read,
output [NUMPORTS-1:0] waitrequest,
output [WIDTH-1:0] fill_addr,
output fill_read,
input fill_waitrequest
);
reg [(NUMPORTS+1)*WIDTH-1:0] queued_addr;
reg [(NUMPORTS+1)-1:0] queued_read;
generate
genvar p;
for (p=0; p<NUMPORTS; p=p+1)
begin : port_gen
always@(posedge clk or negedge resetn)
if (!resetn)
begin
queued_addr[p*WIDTH +: WIDTH]<=0;
queued_read[p]<=0;
end
else if (fill_waitrequest && !queued_read[p])
begin
queued_addr[p*WIDTH +: WIDTH]<=addr[p*WIDTH +: WIDTH];
queued_read[p]<=read[p];
end
else if (!fill_waitrequest)
if (!queued_read[p+1])
begin
queued_addr[p*WIDTH +: WIDTH]<=addr[p*WIDTH +: WIDTH];
queued_read[p]<=read[p];
end
else
begin
queued_addr[p*WIDTH +: WIDTH]<=queued_addr[(p+1)*WIDTH +: WIDTH];
queued_read[p]<=queued_read[p+1];
end
end
endgenerate
always@(posedge clk) queued_read[NUMPORTS]=1'b0;
always@(posedge clk) queued_addr[NUMPORTS*WIDTH +: WIDTH]=0;
assign fill_addr=queued_addr[WIDTH-1:0];
assign fill_read=queued_read[0];
assign waitrequest=(fill_waitrequest) ? queued_read : queued_read>>1;
endmodule
/****************************************************************************
Pipeline register - for transmitting a signal down several stages
DEPTH - number of actual pipeline registers needed
****************************************************************************/
module pipe(
d,
clk,
resetn,
en,
squash,
q
);
parameter WIDTH=32;
parameter DEPTH=1;
parameter RESETVALUE={WIDTH{1'b0}};
input [WIDTH-1:0] d;
input clk;
input resetn;
input [DEPTH-1:0] en;
input [DEPTH-1:0] squash;
output [WIDTH*DEPTH-1:0] q;
reg [WIDTH*DEPTH-1:0] q;
integer i;
always@(posedge clk or negedge resetn)
begin
// 1st register
if ( !resetn )
q[ WIDTH-1:0 ]<=RESETVALUE;
else if ( squash[0] )
q[ WIDTH-1:0 ]<=RESETVALUE;
else if (en[0])
q[ WIDTH-1:0 ]<=d;
// All the rest registers
for (i=1; i<DEPTH; i=i+1)
if (!resetn)
q[i*WIDTH +: WIDTH ]<=RESETVALUE;
else if ( squash[i] )
q[i*WIDTH +: WIDTH ]<=RESETVALUE;
else if (en[i])
q[i*WIDTH +: WIDTH ]<=q[(i-1)*WIDTH +: WIDTH ];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_PP_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_SUM ;
wire pwrgood_pp0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn ;
wire pwrgood_pp1_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf0 (SUM , pwrgood_pp0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn , a_b, a_ci, b_ci );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_coutn, or0_out_coutn, VPWR, VGND);
buf buf1 (COUT_N , pwrgood_pp1_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAHCON_BEHAVIORAL_PP_V |
module uniphy_status
#(
parameter WIDTH=32,
parameter NUM_UNIPHYS=2
)
(
input clk,
input resetn,
// Slave port
input slave_read,
output [WIDTH-1:0] slave_readdata,
// hw.tcl won't let me index into a bit vector :(
input mem0_local_cal_success,
input mem0_local_cal_fail,
input mem0_local_init_done,
input mem1_local_cal_success,
input mem1_local_cal_fail,
input mem1_local_init_done,
input mem2_local_cal_success,
input mem2_local_cal_fail,
input mem2_local_init_done,
input mem3_local_cal_success,
input mem3_local_cal_fail,
input mem3_local_init_done,
input mem4_local_cal_success,
input mem4_local_cal_fail,
input mem4_local_init_done,
input mem5_local_cal_success,
input mem5_local_cal_fail,
input mem5_local_init_done,
input mem6_local_cal_success,
input mem6_local_cal_fail,
input mem6_local_init_done,
input mem7_local_cal_success,
input mem7_local_cal_fail,
input mem7_local_init_done,
output export_local_cal_success,
output export_local_cal_fail,
output export_local_init_done
);
reg [WIDTH-1:0] aggregate_uniphy_status;
wire local_cal_success;
wire local_cal_fail;
wire local_init_done;
wire [NUM_UNIPHYS-1:0] not_init_done;
wire [7:0] mask;
assign mask = (NUM_UNIPHYS < 1) ? 0 : ~(8'hff << NUM_UNIPHYS);
assign local_cal_success = &( ~mask | {mem7_local_cal_success,
mem6_local_cal_success,
mem5_local_cal_success,
mem4_local_cal_success,
mem3_local_cal_success,
mem2_local_cal_success,
mem1_local_cal_success,
mem0_local_cal_success});
assign local_cal_fail = mem0_local_cal_fail |
mem1_local_cal_fail |
mem2_local_cal_fail |
mem3_local_cal_fail |
mem4_local_cal_fail |
mem5_local_cal_fail |
mem6_local_cal_fail |
mem7_local_cal_fail;
assign local_init_done = &( ~mask |{mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done});
assign not_init_done = mask & ~{ mem7_local_init_done,
mem6_local_init_done,
mem5_local_init_done,
mem4_local_init_done,
mem3_local_init_done,
mem2_local_init_done,
mem1_local_init_done,
mem0_local_init_done};
// Desire status==0 to imply success - may cause false positives, but the
// alternative is headaches for non-uniphy memories.
// Status MSB-LSB: not_init_done, 0, !calsuccess, calfail, !initdone
always@(posedge clk or negedge resetn)
if (!resetn)
aggregate_uniphy_status <= {WIDTH{1'b0}};
else
aggregate_uniphy_status <= { not_init_done, 1'b0,
{~local_cal_success,local_cal_fail,~local_init_done}
};
assign slave_readdata = aggregate_uniphy_status;
assign export_local_cal_success = local_cal_success;
assign export_local_cal_fail = local_cal_fail;
assign export_local_init_done = local_init_done;
endmodule
|
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for lf_edge_detect
`include "lf_edge_detect.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
`define FOUT_STATE "tb_tmp/data.state"
`define FOUT_TOGGLE "tb_tmp/data.toggle"
`define FOUT_HIGH "tb_tmp/data.high"
`define FOUT_HIGHZ "tb_tmp/data.highz"
`define FOUT_LOWZ "tb_tmp/data.lowz"
`define FOUT_LOW "tb_tmp/data.low"
module lf_edge_detect_tb;
integer fin, fout_state, fout_toggle;
integer fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
integer r;
reg clk = 0;
reg [7:0] adc_d;
wire adc_clk;
wire data_rdy;
wire edge_state;
wire edge_toggle;
wire [7:0] high_threshold;
wire [7:0] highz_threshold;
wire [7:0] lowz_threshold;
wire [7:0] low_threshold;
wire [7:0] max;
wire [7:0] min;
initial
begin
clk = 0;
fin = $fopen(`FIN, "r");
if (!fin) begin
$display("ERROR: can't open the data file");
$finish;
end
fout_min = $fopen(`FOUT_MIN, "w+");
fout_max = $fopen(`FOUT_MAX, "w+");
fout_state = $fopen(`FOUT_STATE, "w+");
fout_toggle = $fopen(`FOUT_TOGGLE, "w+");
fout_high = $fopen(`FOUT_HIGH, "w+");
fout_highz = $fopen(`FOUT_HIGHZ, "w+");
fout_lowz = $fopen(`FOUT_LOWZ, "w+");
fout_low = $fopen(`FOUT_LOW, "w+");
if (!$feof(fin))
adc_d = $fgetc(fin); // read the first value
end
always
# 1 clk = !clk;
// input
initial
begin
while (!$feof(fin)) begin
@(negedge clk) adc_d <= $fgetc(fin);
end
if ($feof(fin))
begin
# 3 $fclose(fin);
$fclose(fout_state);
$fclose(fout_toggle);
$fclose(fout_high);
$fclose(fout_highz);
$fclose(fout_lowz);
$fclose(fout_low);
$fclose(fout_min);
$fclose(fout_max);
$finish;
end
end
initial
begin
// $monitor("%d\t S: %b, E: %b", $time, edge_state, edge_toggle);
end
// output
always @(negedge clk)
if ($time > 2) begin
r = $fputc(min, fout_min);
r = $fputc(max, fout_max);
r = $fputc(edge_state, fout_state);
r = $fputc(edge_toggle, fout_toggle);
r = $fputc(high_threshold, fout_high);
r = $fputc(highz_threshold, fout_highz);
r = $fputc(lowz_threshold, fout_lowz);
r = $fputc(low_threshold, fout_low);
end
// module to test
lf_edge_detect detect(clk, adc_d, 8'd127,
max, min,
high_threshold, highz_threshold,
lowz_threshold, low_threshold,
edge_state, edge_toggle);
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDLCLKP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SDLCLKP_PP_BLACKBOX_V
/**
* sdlclkp: Scan gated clock.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sdlclkp (
GCLK,
SCE ,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
output GCLK;
input SCE ;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDLCLKP_PP_BLACKBOX_V
|
/*
* Copyright (c) 2008 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
// IO Ports
input clk;
input rst;
input cs;
input we;
input [10:0] addr;
output [7:0] rdata;
input [7:0] wdata;
// Net declarations
wire dp;
// Module instantiations
RAMB16_S9 ram (.DO(rdata),
.DOP (dp),
.ADDR (addr),
.CLK (clk),
.DI (wdata),
.DIP (dp),
.EN (cs),
.SSR (rst),
.WE (we));
defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
/*
defparam ram.INIT_00 = 256'h31303938373635343332313039383736_35343332313039383736353433323130;
defparam ram.INIT_01 = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_02 = 256'h3139383736353433323130393837363534;
defparam ram.INIT_03 = 256'h43000000;
defparam ram.INIT_05 = 256'h32;
defparam ram.INIT_07 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_0A = 256'h34;
defparam ram.INIT_0C = 256'h3500000000000000000000000000000000;
defparam ram.INIT_0F = 256'h36;
defparam ram.INIT_11 = 256'h3700000000000000000000000000000000;
defparam ram.INIT_14 = 256'h38;
defparam ram.INIT_16 = 256'h3900000000000000000000000000000000;
defparam ram.INIT_19 = 256'h30;
defparam ram.INIT_1B = 256'h3100000000000000000000000000000000;
defparam ram.INIT_1E = 256'h32;
defparam ram.INIT_20 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_23 = 256'h34;
defparam ram.INIT_25 = 256'h3500000000000000000000000000000000;
defparam ram.INIT_28 = 256'h36;
defparam ram.INIT_2A = 256'h3700000000000000000000000000000000;
defparam ram.INIT_2D = 256'h38;
defparam ram.INIT_2F = 256'h3900000000000000000000000000000000;
defparam ram.INIT_32 = 256'h30;
defparam ram.INIT_34 = 256'h3100000000000000000000000000000000;
defparam ram.INIT_37 = 256'h32;
defparam ram.INIT_39 = 256'h3300000000000000000000000000000000;
defparam ram.INIT_3C = 256'h31303938373635343332313039383736_35343332313039383736353433323134;
defparam ram.INIT_3D = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
defparam ram.INIT_3E = 256'h35343332313039383736353433323130_39383736353433323130393837363534;
defparam ram.INIT_3F = 256'h37363534333231303938373635343332_31303938373635343332313039383736;
*/
endmodule |
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 665470729d63ff293f82037047a4ab71bed16398
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_ECALL 2'b10
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
wire CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
wire CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h10003050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00403040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
assign CsrPlugin_inWfi = 1'b0;
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign CsrPlugin_misa_base = 2'b01;
assign CsrPlugin_misa_extensions = 26'h0000042;
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_lastStageWasWfi = 1'b0;
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))) | ((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | _zz_CsrPlugin_csrMapping_readDataInit_12));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [7:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 7'bxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 7'bxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[6:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[7]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 8'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 8'h01);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 8'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [21:0] _zz_ways_0_tags_port1;
wire [21:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [7:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [6:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [19:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [9:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [19:0] fetchStage_read_waysValues_0_tag_address;
wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:1023];
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 8'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd_gen # (
parameter P_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output dma_cmd_rd_en,
input [49:0] dma_cmd_rd_data,
input dma_cmd_empty_n,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output pcie_cmd_wr_en,
output [33:0] pcie_cmd_wr_data,
input pcie_cmd_full_n,
output prp_pcie_alloc,
output [7:0] prp_pcie_alloc_tag,
output [5:4] prp_pcie_tag_alloc_len,
input pcie_tag_full_n,
input prp_fifo_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack
);
localparam LP_PRP_PCIE_TAG_PREFIX = 5'b00001;
localparam S_IDLE = 17'b00000000000000001;
localparam S_DMA_CMD0 = 17'b00000000000000010;
localparam S_DMA_CMD1 = 17'b00000000000000100;
localparam S_PRP_INFO0 = 17'b00000000000001000;
localparam S_PRP_INFO1 = 17'b00000000000010000;
localparam S_CALC_LEN0 = 17'b00000000000100000;
localparam S_CALC_LEN1 = 17'b00000000001000000;
localparam S_CALC_LEN2 = 17'b00000000010000000;
localparam S_CHECK_FIFO = 17'b00000000100000000;
localparam S_CMD0 = 17'b00000001000000000;
localparam S_CMD1 = 17'b00000010000000000;
localparam S_CMD2 = 17'b00000100000000000;
localparam S_CMD3 = 17'b00001000000000000;
localparam S_PCIE_MRD_CHECK = 17'b00010000000000000;
localparam S_PCIE_MRD_REQ = 17'b00100000000000000;
localparam S_PCIE_MRD_ACK = 17'b01000000000000000;
localparam S_PCIE_MRD_REQ_DONE = 17'b10000000000000000;
reg [16:0] cur_state;
reg [16:0] next_state;
reg r_pcie_rcb;
reg r_pcie_rcb_cross;
reg r_dma_cmd_type;
reg r_dma_cmd_dir;
reg [6:0] r_hcmd_slot_tag;
reg [31:2] r_dev_addr;
reg [12:2] r_dev_dma_len;
reg [8:0] r_4k_offset;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_1;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_prp_2;
reg [8:0] r_hcmd_nlb;
reg r_prp2_type;
reg [8:0] r_prp_offset;
reg r_prp_offset_is_0;
reg [11:2] r_prp_4b_offset;
reg [12:2] r_1st_prp_4b_len;
reg [12:2] r_1st_4b_len;
reg [12:2] r_2st_4b_len;
reg r_2st_valid;
reg r_1st_mrd_need;
reg r_2st_mrd_need;
wire w_2st_mrd_need;
reg [2:0] r_tx_prp_mrd_tag;
reg [4:3] r_pcie_mrd_len;
reg [C_PCIE_ADDR_WIDTH-1:2] r_tx_prp_mrd_addr;
wire [20:2] w_4b_offset;
wire w_dev_cmd_full_n;
reg r_dma_cmd_rd_en;
reg r_hcmd_prp_rd_sel;
reg r_dev_rx_cmd_wr_en;
reg r_dev_tx_cmd_wr_en;
reg r_dev_cmd_wr_data_sel;
reg r_pcie_cmd_wr_en;
reg [3:0] r_pcie_cmd_wr_data_sel;
reg r_prp_pcie_alloc;
reg r_tx_prp_mrd_req;
reg r_mrd_tag_update;
reg [29:0] r_dev_cmd_wr_data;
reg [33:0] r_pcie_cmd_wr_data;
assign dma_cmd_rd_en = r_dma_cmd_rd_en;
assign hcmd_prp_rd_addr = {r_hcmd_slot_tag, r_hcmd_prp_rd_sel};
assign dev_rx_cmd_wr_en = r_dev_rx_cmd_wr_en;
assign dev_rx_cmd_wr_data = r_dev_cmd_wr_data;
assign dev_tx_cmd_wr_en = r_dev_tx_cmd_wr_en;
assign dev_tx_cmd_wr_data = r_dev_cmd_wr_data;
assign pcie_cmd_wr_en = r_pcie_cmd_wr_en;
assign pcie_cmd_wr_data = r_pcie_cmd_wr_data;
assign prp_pcie_alloc = r_prp_pcie_alloc;
assign prp_pcie_alloc_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign prp_pcie_tag_alloc_len = (r_pcie_rcb_cross == 0) ? 2'b01 : 2'b10;
assign tx_prp_mrd_req = r_tx_prp_mrd_req;
assign tx_prp_mrd_tag = {LP_PRP_PCIE_TAG_PREFIX, r_tx_prp_mrd_tag};
assign tx_prp_mrd_len = {7'b0, r_pcie_mrd_len, 1'b0};
assign tx_prp_mrd_addr = r_tx_prp_mrd_addr;
always @ (posedge pcie_user_clk)
begin
r_pcie_rcb <= pcie_rcb;
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
assign w_dev_cmd_full_n = (r_dma_cmd_dir == 1'b1) ? dev_tx_cmd_full_n : dev_rx_cmd_full_n;
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(dma_cmd_empty_n == 1'b1)
next_state <= S_DMA_CMD0;
else
next_state <= S_IDLE;
end
S_DMA_CMD0: begin
next_state <= S_DMA_CMD1;
end
S_DMA_CMD1: begin
if(r_dma_cmd_type == 1'b1)
next_state <= S_CHECK_FIFO;
else
next_state <= S_PRP_INFO0;
end
S_PRP_INFO0: begin
next_state <= S_PRP_INFO1;
end
S_PRP_INFO1: begin
next_state <= S_CALC_LEN0;
end
S_CALC_LEN0: begin
next_state <= S_CALC_LEN1;
end
S_CALC_LEN1: begin
next_state <= S_CALC_LEN2;
end
S_CALC_LEN2: begin
next_state <= S_CHECK_FIFO;
end
S_CHECK_FIFO: begin
if(w_dev_cmd_full_n == 1'b1 && pcie_cmd_full_n == 1'b1)
next_state <= S_CMD0;
else
next_state <= S_CHECK_FIFO;
end
S_CMD0: begin
next_state <= S_CMD1;
end
S_CMD1: begin
next_state <= S_CMD2;
end
S_CMD2: begin
next_state <= S_CMD3;
end
S_CMD3: begin
if((r_1st_mrd_need | (r_2st_valid & r_2st_mrd_need)) == 1'b1)
next_state <= S_PCIE_MRD_CHECK;
else
next_state <= S_IDLE;
end
S_PCIE_MRD_CHECK: begin
if(pcie_tag_full_n == 1 && prp_fifo_full_n == 1)
next_state <= S_PCIE_MRD_REQ;
else
next_state <= S_PCIE_MRD_CHECK;
end
S_PCIE_MRD_REQ: begin
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_ACK: begin
if(tx_prp_mrd_req_ack == 1'b1)
next_state <= S_PCIE_MRD_REQ_DONE;
else
next_state <= S_PCIE_MRD_ACK;
end
S_PCIE_MRD_REQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_tx_prp_mrd_tag <= 0;
end
else begin
if(r_mrd_tag_update == 1)
r_tx_prp_mrd_tag <= r_tx_prp_mrd_tag + 1;
end
end
assign w_4b_offset[20:2] = {r_4k_offset, 10'b0} + r_hcmd_prp_1[11:2];
assign w_2st_mrd_need = r_2st_valid & r_2st_mrd_need;
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
r_2st_valid <= 0;
r_1st_mrd_need <= 0;
r_2st_mrd_need <= 0;
r_pcie_rcb_cross <= 0;
end
S_DMA_CMD0: begin
r_dev_addr <= dma_cmd_rd_data[29:0];
r_dev_dma_len <= dma_cmd_rd_data[40:30];
r_hcmd_slot_tag <= dma_cmd_rd_data[47:41];
r_dma_cmd_dir <= dma_cmd_rd_data[48];
r_dma_cmd_type <= dma_cmd_rd_data[49];
end
S_DMA_CMD1: begin
r_hcmd_prp_1 <= dma_cmd_rd_data[33:0];
r_4k_offset <= dma_cmd_rd_data[42:34];
r_1st_4b_len <= r_dev_dma_len;
end
S_PRP_INFO0: begin
r_hcmd_prp_1 <= hcmd_prp_rd_data[33:0];
end
S_PRP_INFO1: begin
r_hcmd_nlb <= {1'b0, hcmd_prp_rd_data[41:34]};
r_hcmd_prp_2 <= hcmd_prp_rd_data[33:0];
end
S_CALC_LEN0: begin
r_prp_offset <= w_4b_offset[20:12];
r_prp_4b_offset <= w_4b_offset[11:2];
r_hcmd_nlb <= r_hcmd_nlb + 1;
end
S_CALC_LEN1: begin
r_dev_addr[11:2] <= 0;
r_dev_dma_len <= 11'h400;
r_prp_offset_is_0 <= (r_prp_offset == 0);
r_1st_prp_4b_len <= 11'h400 - r_prp_4b_offset;
if((12'h800 - r_hcmd_prp_1[11:2]) >= {r_hcmd_nlb, 10'b0})
r_prp2_type <= 0;
else
r_prp2_type <= 1;
end
S_CALC_LEN2: begin
if(r_dev_dma_len > r_1st_prp_4b_len) begin
r_1st_4b_len <= r_1st_prp_4b_len;
r_2st_4b_len <= r_dev_dma_len - r_1st_prp_4b_len;
r_2st_valid <= 1;
end
else begin
r_1st_4b_len <= r_dev_dma_len;
r_2st_valid <= 0;
end
if(r_prp_offset_is_0 == 1) begin
r_1st_mrd_need <= 0;
r_2st_mrd_need <= r_prp2_type;
end
else begin
r_hcmd_prp_1[C_PCIE_ADDR_WIDTH-1:12] <= r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12];
r_1st_mrd_need <= r_prp2_type;
r_2st_mrd_need <= r_prp2_type;
r_prp_offset <= r_prp_offset - 1'b1;
end
r_hcmd_prp_1[11:2] <= r_prp_4b_offset;
end
S_CHECK_FIFO: begin
r_tx_prp_mrd_addr <= r_hcmd_prp_2 + {r_prp_offset, 1'b0};
r_pcie_mrd_len <= r_1st_mrd_need + w_2st_mrd_need;
end
S_CMD0: begin
if(r_pcie_mrd_len == 2 && r_tx_prp_mrd_addr[5:2] == 4'b1110) begin
if(r_pcie_rcb == 1)
r_pcie_rcb_cross <= r_tx_prp_mrd_addr[6];
else
r_pcie_rcb_cross <= 1;
end
else
r_pcie_rcb_cross <= 0;
end
S_CMD1: begin
end
S_CMD2: begin
end
S_CMD3: begin
end
S_PCIE_MRD_CHECK: begin
end
S_PCIE_MRD_REQ: begin
end
S_PCIE_MRD_ACK: begin
end
S_PCIE_MRD_REQ_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
if(r_dev_cmd_wr_data_sel == 0)
r_dev_cmd_wr_data <= {10'b0, r_dma_cmd_type, 1'b0, r_hcmd_slot_tag, r_dev_dma_len};
else
r_dev_cmd_wr_data <= r_dev_addr;
case(r_pcie_cmd_wr_data_sel) // synthesis parallel_case full_case
4'b0001: r_pcie_cmd_wr_data <= {22'b0, r_dma_cmd_type, r_dma_cmd_dir, r_2st_valid, r_1st_mrd_need, r_2st_mrd_need, r_hcmd_slot_tag};
4'b0010: r_pcie_cmd_wr_data <= {11'b0, r_pcie_rcb_cross, r_1st_4b_len, r_2st_4b_len};
4'b0100: r_pcie_cmd_wr_data <= r_hcmd_prp_1;
4'b1000: r_pcie_cmd_wr_data <= {r_hcmd_prp_2[C_PCIE_ADDR_WIDTH-1:12], 10'b0};
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD0: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_DMA_CMD1: begin
r_dma_cmd_rd_en <= 1;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 1;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PRP_INFO1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CALC_LEN2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CHECK_FIFO: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD0: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0001;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD1: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= ~r_dma_cmd_dir;
r_dev_tx_cmd_wr_en <= r_dma_cmd_dir;
r_dev_cmd_wr_data_sel <= 1;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0010;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD2: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b0100;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_CMD3: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 1;
r_pcie_cmd_wr_data_sel <= 4'b1000;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_CHECK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 1;
r_tx_prp_mrd_req <= 1;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_ACK: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
S_PCIE_MRD_REQ_DONE: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 1;
end
default: begin
r_dma_cmd_rd_en <= 0;
r_hcmd_prp_rd_sel <= 0;
r_dev_rx_cmd_wr_en <= 0;
r_dev_tx_cmd_wr_en <= 0;
r_dev_cmd_wr_data_sel <= 0;
r_pcie_cmd_wr_en <= 0;
r_pcie_cmd_wr_data_sel <= 4'b0;
r_prp_pcie_alloc <= 0;
r_tx_prp_mrd_req <= 0;
r_mrd_tag_update <= 0;
end
endcase
end
endmodule |
// megafunction wizard: %LPM_RAM_DP+%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram_64_32x32.v
// Megafunction Name(s):
// altsyncram
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 148 04/26/2005 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_64_32x32 (
data,
wren,
wraddress,
rdaddress,
wrclock,
rdclock,
q);
input [31:0] data;
input wren;
input [4:0] wraddress;
input [3:0] rdaddress;
input wrclock;
input rdclock;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0)
// synopsys translate_off
,
.aclr0 (),
.aclr1 (),
.addressstall_a (),
.addressstall_b (),
.byteena_a (),
.byteena_b (),
.clocken0 (),
.clocken1 (),
.data_b (),
.q_a (),
.rden_b (),
.wren_b ()
// synopsys translate_on
);
defparam
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.width_a = 32,
altsyncram_component.widthad_a = 5,
altsyncram_component.numwords_a = 32,
altsyncram_component.width_b = 64,
altsyncram_component.widthad_b = 4,
altsyncram_component.numwords_b = 16,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.width_byteena_a = 1,
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.power_up_uninitialized = "FALSE";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT NODEFVAL wrclock
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
// Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dpram_64_32x32_bb.v TRUE
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: pipemem.v
//
// Project: Zip CPU -- a small, lightweight, RISC CPU soft core
//
// Purpose: A memory unit to support a CPU, this time one supporting
// pipelined wishbone memory accesses. The goal is to be able
// to issue one pipelined wishbone access per clock, and (given the memory
// is fast enough) to be able to read the results back at one access per
// clock. This renders on-chip memory fast enough to handle single cycle
// (pipelined) access.
//
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2017, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
`default_nettype none
//
module pipemem(i_clk, i_rst, i_pipe_stb, i_lock,
i_op, i_addr, i_data, i_oreg,
o_busy, o_pipe_stalled, o_valid, o_err, o_wreg, o_result,
o_wb_cyc_gbl, o_wb_cyc_lcl,
o_wb_stb_gbl, o_wb_stb_lcl,
o_wb_we, o_wb_addr, o_wb_data, o_wb_sel,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data);
parameter ADDRESS_WIDTH=30;
parameter [0:0] IMPLEMENT_LOCK=1'b0,
WITH_LOCAL_BUS=1'b1;
localparam AW=ADDRESS_WIDTH;
input wire i_clk, i_rst;
input wire i_pipe_stb, i_lock;
// CPU interface
input wire [2:0] i_op;
input wire [31:0] i_addr;
input wire [31:0] i_data;
input wire [4:0] i_oreg;
// CPU outputs
output wire o_busy;
output wire o_pipe_stalled;
output reg o_valid;
output reg o_err;
output reg [4:0] o_wreg;
output reg [31:0] o_result;
// Wishbone outputs
output wire o_wb_cyc_gbl;
output reg o_wb_stb_gbl;
output wire o_wb_cyc_lcl;
output reg o_wb_stb_lcl, o_wb_we;
output reg [(AW-1):0] o_wb_addr;
output reg [31:0] o_wb_data;
output reg [3:0] o_wb_sel;
// Wishbone inputs
input wire i_wb_ack, i_wb_stall, i_wb_err;
input wire [31:0] i_wb_data;
reg cyc;
reg r_wb_cyc_gbl, r_wb_cyc_lcl;
reg [3:0] rdaddr, wraddr;
wire [3:0] nxt_rdaddr;
reg [(4+5-1):0] fifo_oreg [0:15];
initial rdaddr = 0;
initial wraddr = 0;
always @(posedge i_clk)
fifo_oreg[wraddr] <= { i_oreg, i_op[2:1], i_addr[1:0] };
always @(posedge i_clk)
if ((i_rst)||(i_wb_err))
wraddr <= 0;
else if (i_pipe_stb)
wraddr <= wraddr + 1'b1;
always @(posedge i_clk)
if ((i_rst)||(i_wb_err))
rdaddr <= 0;
else if ((i_wb_ack)&&(cyc))
rdaddr <= rdaddr + 1'b1;
assign nxt_rdaddr = rdaddr + 1'b1;
wire gbl_stb, lcl_stb;
assign lcl_stb = (i_addr[31:24]==8'hff)&&(WITH_LOCAL_BUS);
assign gbl_stb = (!lcl_stb)||(!WITH_LOCAL_BUS);
//= ((i_addr[31:8]!=24'hc00000)||(i_addr[7:5]!=3'h0));
initial cyc = 0;
initial r_wb_cyc_lcl = 0;
initial r_wb_cyc_gbl = 0;
always @(posedge i_clk)
if (i_rst)
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
cyc <= 1'b0;
end else if (cyc)
begin
if ((~i_wb_stall)&&(~i_pipe_stb))
begin
o_wb_stb_gbl <= 1'b0;
o_wb_stb_lcl <= 1'b0;
// end else if ((i_pipe_stb)&&(~i_wb_stall))
// begin
// o_wb_addr <= i_addr[(AW-1):0];
// o_wb_data <= i_data;
end
if (((i_wb_ack)&&(nxt_rdaddr == wraddr))||(i_wb_err))
begin
r_wb_cyc_gbl <= 1'b0;
r_wb_cyc_lcl <= 1'b0;
cyc <= 1'b0;
end
end else if (i_pipe_stb) // New memory operation
begin // Grab the wishbone
r_wb_cyc_lcl <= lcl_stb;
r_wb_cyc_gbl <= gbl_stb;
o_wb_stb_lcl <= lcl_stb;
o_wb_stb_gbl <= gbl_stb;
cyc <= 1'b1;
// o_wb_addr <= i_addr[(AW-1):0];
// o_wb_data <= i_data;
// o_wb_we <= i_op
end
always @(posedge i_clk)
if ((!cyc)||(!i_wb_stall))
begin
o_wb_addr <= i_addr[(AW+1):2];
if (!i_op[0]) // Always select everything on reads
o_wb_sel <= 4'b1111; // Op is even
else casez({ i_op[2:1], i_addr[1:0] })
4'b100?: o_wb_sel <= 4'b1100; // Op = 5
4'b101?: o_wb_sel <= 4'b0011; // Op = 5
4'b1100: o_wb_sel <= 4'b1000; // Op = 5
4'b1101: o_wb_sel <= 4'b0100; // Op = 7
4'b1110: o_wb_sel <= 4'b0010; // Op = 7
4'b1111: o_wb_sel <= 4'b0001; // Op = 7
default: o_wb_sel <= 4'b1111; // Op = 7
endcase
casez({ i_op[2:1], i_addr[1:0] })
4'b100?: o_wb_data <= { i_data[15:0], 16'h00 };
4'b101?: o_wb_data <= { 16'h00, i_data[15:0] };
4'b1100: o_wb_data <= { i_data[7:0], 24'h00 };
4'b1101: o_wb_data <= { 8'h00, i_data[7:0], 16'h00 };
4'b1110: o_wb_data <= { 16'h00, i_data[7:0], 8'h00 };
4'b1111: o_wb_data <= { 24'h00, i_data[7:0] };
default: o_wb_data <= i_data;
endcase
end
always @(posedge i_clk)
if ((i_pipe_stb)&&(~cyc))
o_wb_we <= i_op[0];
initial o_valid = 1'b0;
always @(posedge i_clk)
o_valid <= (cyc)&&(i_wb_ack)&&(~o_wb_we);
initial o_err = 1'b0;
always @(posedge i_clk)
o_err <= (cyc)&&(i_wb_err);
assign o_busy = cyc;
wire [8:0] w_wreg;
assign w_wreg = fifo_oreg[rdaddr];
always @(posedge i_clk)
o_wreg <= w_wreg[8:4];
always @(posedge i_clk)
casez(w_wreg[3:0])
4'b1100: o_result <= { 24'h00, i_wb_data[31:24] };
4'b1101: o_result <= { 24'h00, i_wb_data[23:16] };
4'b1110: o_result <= { 24'h00, i_wb_data[15: 8] };
4'b1111: o_result <= { 24'h00, i_wb_data[ 7: 0] };
4'b100?: o_result <= { 16'h00, i_wb_data[31:16] };
4'b101?: o_result <= { 16'h00, i_wb_data[15: 0] };
default: o_result <= i_wb_data[31:0];
endcase
assign o_pipe_stalled = (cyc)
&&((i_wb_stall)||((~o_wb_stb_lcl)&&(~o_wb_stb_gbl)));
generate
if (IMPLEMENT_LOCK != 0)
begin
reg lock_gbl, lock_lcl;
initial lock_gbl = 1'b0;
initial lock_lcl = 1'b0;
always @(posedge i_clk)
begin
lock_gbl <= (i_lock)&&((r_wb_cyc_gbl)||(lock_gbl));
lock_lcl <= (i_lock)&&((r_wb_cyc_lcl)||(lock_lcl));
end
assign o_wb_cyc_gbl = (r_wb_cyc_gbl)||(lock_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl)||(lock_lcl);
end else begin
assign o_wb_cyc_gbl = (r_wb_cyc_gbl);
assign o_wb_cyc_lcl = (r_wb_cyc_lcl);
end endgenerate
// Make verilator happy
// verilator lint_off UNUSED
wire unused;
assign unused = i_lock;
// verilator lint_on UNUSED
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_2.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_2) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_2_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_2_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_2_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_2" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_2_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
//assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
// To Fix CR855535
assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_2_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_2_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_2
#(parameter C_CORENAME = "blk_mem_gen_v8_3_2",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_2_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_2_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_2_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_2_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
`timescale 1ns/1ps
`default_nettype none
module inout_iii(SIM_RST, SIM_CLK, p4VDC, p4VSW, GND, GOJAM, STOP, T05, T11, F08B, FS09_n, F09A, F09B, F09B_n, F10A, F10A_n, F17A, F17B, SB0_n, SB2_n, F5ASB2_n, F5BSB2_n, CCH13, RCH13_n, WCH13_n, CHWL01_n, CHWL02_n, CHWL03_n, CHWL04_n, CHWL11_n, GTSET_n, GTRST_n, MKEY1, MKEY2, MKEY3, MKEY4, MKEY5, MAINRS, NKEY1, NKEY2, NKEY3, NKEY4, NKEY5, NAVRST, MARK, MRKREJ, MRKRST, SBYBUT, LRIN0, LRIN1, RRIN0, RRIN1, XT1_n, XB5_n, XB6_n, ALTEST, TPOR_n, SBY, STNDBY_n, SBYLIT, SBYREL_n, KYRPT1, KYRPT2, MKRPT, RADRPT, RNRADP, RNRADM, CH1301, CH1302, CH1303, CH1304, CH1311, CH1501, CH1502, CH1503, CH1504, CH1505, CH1601, CH1602, CH1603, CH1604, CH1605, CH1606, CH1607);
input wire SIM_RST;
input wire SIM_CLK;
input wire p4VDC;
input wire p4VSW;
input wire GND;
input wire ALTEST;
input wire CCH13;
output wire CH1301;
output wire CH1302;
output wire CH1303;
output wire CH1304;
output wire CH1311;
output wire CH1501;
output wire CH1502;
output wire CH1503;
output wire CH1504;
output wire CH1505;
output wire CH1601;
output wire CH1602;
output wire CH1603;
output wire CH1604;
output wire CH1605;
output wire CH1606;
output wire CH1607;
input wire CHWL01_n;
input wire CHWL02_n;
input wire CHWL03_n;
input wire CHWL04_n;
input wire CHWL11_n;
input wire F08B;
input wire F09A;
input wire F09B;
input wire F09B_n;
input wire F10A;
input wire F10A_n;
input wire F17A;
input wire F17B;
input wire F5ASB2_n;
input wire F5BSB2_n;
input wire FS09_n;
input wire GOJAM;
input wire GTRST_n;
input wire GTSET_n;
output wire KYRPT1;
output wire KYRPT2;
input wire LRIN0;
input wire LRIN1;
input wire MAINRS;
input wire MARK;
input wire MKEY1;
input wire MKEY2;
input wire MKEY3;
input wire MKEY4;
input wire MKEY5;
output wire MKRPT;
input wire MRKREJ;
input wire MRKRST;
input wire NAVRST;
input wire NKEY1;
input wire NKEY2;
input wire NKEY3;
input wire NKEY4;
input wire NKEY5;
output wire RADRPT;
input wire RCH13_n;
output wire RNRADM;
output wire RNRADP;
input wire RRIN0;
input wire RRIN1;
input wire SB0_n;
input wire SB2_n;
output wire SBY;
input wire SBYBUT;
output wire SBYLIT;
output wire SBYREL_n;
output wire STNDBY_n;
input wire STOP;
input wire T05;
input wire T11;
output wire TPOR_n;
input wire WCH13_n;
input wire XB5_n;
input wire XB6_n;
input wire XT1_n;
wire __A18_1__F08B_n;
wire __A18_1__F09A_n;
wire __A18_1__F09D;
wire __A18_1__F17A_n;
wire __A18_1__F17B_n;
wire __A18_1__RCH15_n;
wire __A18_1__RCH16_n;
wire __A18_1__STNDBY;
wire __A18_2__ACTV_n;
wire __A18_2__ADVCNT;
wire __A18_2__CNTOF9; //FPGA#wand
wire __A18_2__F10AS0;
wire __A18_2__HERB;
wire __A18_2__LRRANG;
wire __A18_2__LRSYNC;
wire __A18_2__LRXVEL;
wire __A18_2__LRYVEL;
wire __A18_2__LRZVEL;
wire __A18_2__RRRANG;
wire __A18_2__RRRARA;
wire __A18_2__RRSYNC;
wire net_R18001_Pad2; //FPGA#wand
wire net_R18002_Pad2; //FPGA#wand
wire net_U18001_Pad1;
wire net_U18001_Pad12;
wire net_U18001_Pad13;
wire net_U18001_Pad3;
wire net_U18001_Pad6;
wire net_U18002_Pad10;
wire net_U18002_Pad11;
wire net_U18002_Pad12;
wire net_U18002_Pad2;
wire net_U18002_Pad4;
wire net_U18002_Pad5;
wire net_U18002_Pad6;
wire net_U18002_Pad8;
wire net_U18002_Pad9;
wire net_U18003_Pad13;
wire net_U18004_Pad10;
wire net_U18005_Pad13;
wire net_U18005_Pad3;
wire net_U18006_Pad10;
wire net_U18006_Pad12;
wire net_U18006_Pad6;
wire net_U18007_Pad11;
wire net_U18007_Pad13;
wire net_U18007_Pad5;
wire net_U18007_Pad9;
wire net_U18008_Pad10;
wire net_U18008_Pad11;
wire net_U18008_Pad13;
wire net_U18008_Pad3;
wire net_U18008_Pad6;
wire net_U18009_Pad2;
wire net_U18009_Pad3;
wire net_U18009_Pad8;
wire net_U18010_Pad12;
wire net_U18010_Pad13;
wire net_U18010_Pad5;
wire net_U18011_Pad1;
wire net_U18011_Pad10;
wire net_U18012_Pad1;
wire net_U18012_Pad12;
wire net_U18012_Pad13;
wire net_U18012_Pad3;
wire net_U18013_Pad10;
wire net_U18013_Pad11;
wire net_U18013_Pad12;
wire net_U18013_Pad2;
wire net_U18013_Pad4;
wire net_U18013_Pad5;
wire net_U18013_Pad6;
wire net_U18013_Pad8;
wire net_U18013_Pad9;
wire net_U18014_Pad13;
wire net_U18015_Pad10;
wire net_U18016_Pad3;
wire net_U18017_Pad10;
wire net_U18017_Pad6;
wire net_U18018_Pad13;
wire net_U18018_Pad4;
wire net_U18023_Pad10;
wire net_U18023_Pad6;
wire net_U18025_Pad10;
wire net_U18025_Pad11;
wire net_U18025_Pad2;
wire net_U18025_Pad4;
wire net_U18025_Pad5;
wire net_U18025_Pad6;
wire net_U18025_Pad8;
wire net_U18025_Pad9;
wire net_U18026_Pad13;
wire net_U18026_Pad3;
wire net_U18027_Pad11;
wire net_U18027_Pad12;
wire net_U18027_Pad13;
wire net_U18028_Pad12;
wire net_U18028_Pad13;
wire net_U18028_Pad5;
wire net_U18028_Pad9;
wire net_U18029_Pad10;
wire net_U18029_Pad11;
wire net_U18029_Pad8;
wire net_U18029_Pad9;
wire net_U18030_Pad1;
wire net_U18030_Pad10;
wire net_U18030_Pad11;
wire net_U18031_Pad10;
wire net_U18031_Pad11;
wire net_U18031_Pad12;
wire net_U18031_Pad3;
wire net_U18031_Pad4;
wire net_U18031_Pad5;
wire net_U18031_Pad8;
wire net_U18031_Pad9;
wire net_U18032_Pad1;
wire net_U18032_Pad13;
wire net_U18033_Pad13;
wire net_U18034_Pad1;
wire net_U18034_Pad13;
wire net_U18034_Pad3;
wire net_U18035_Pad1;
wire net_U18035_Pad3;
wire net_U18036_Pad10;
wire net_U18036_Pad12;
wire net_U18036_Pad13;
wire net_U18036_Pad3;
wire net_U18037_Pad11;
wire net_U18037_Pad8;
wire net_U18037_Pad9;
wire net_U18038_Pad12;
wire net_U18038_Pad13;
wire net_U18038_Pad4;
wire net_U18039_Pad12;
wire net_U18039_Pad13;
wire net_U18039_Pad9;
wire net_U18040_Pad10;
wire net_U18040_Pad12;
wire net_U18040_Pad13;
wire net_U18041_Pad3;
wire net_U18041_Pad5;
wire net_U18041_Pad6;
wire net_U18042_Pad12;
wire net_U18042_Pad13;
wire net_U18042_Pad4;
wire net_U18044_Pad10;
wire net_U18044_Pad13;
wire net_U18044_Pad9;
wire net_U18048_Pad1;
wire net_U18048_Pad10;
wire net_U18048_Pad12;
wire net_U18048_Pad13;
wire net_U18048_Pad4;
wire net_U18048_Pad6;
wire net_U18049_Pad9;
wire net_U18050_Pad10;
wire net_U18050_Pad12;
wire net_U18050_Pad5;
wire net_U18050_Pad8;
wire net_U18051_Pad10;
wire net_U18051_Pad4;
wire net_U18051_Pad5;
wire net_U18051_Pad6;
wire net_U18051_Pad8;
wire net_U18119_Pad1;
wire net_U18119_Pad10;
wire net_U18119_Pad11;
wire net_U18120_Pad13;
wire net_U18120_Pad2;
wire net_U18121_Pad1;
wire net_U18121_Pad10;
wire net_U18121_Pad12;
wire net_U18121_Pad13;
wire net_U18122_Pad1;
wire net_U18122_Pad10;
wire net_U18122_Pad13;
wire net_U18122_Pad3;
wire net_U18122_Pad8;
wire net_U18124_Pad1;
wire net_U18124_Pad4;
pullup R18001(net_R18001_Pad2);
pullup R18002(net_R18002_Pad2);
pullup R18003(__A18_2__CNTOF9);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U18001(net_U18001_Pad1, MKEY1, net_U18001_Pad3, net_U18001_Pad3, net_U18001_Pad1, net_U18001_Pad6, GND, net_U18001_Pad1, __A18_1__RCH15_n, CH1501, MKEY2, net_U18001_Pad12, net_U18001_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1) U18002(net_U18001_Pad1, net_U18002_Pad2, net_U18001_Pad13, net_U18002_Pad4, net_U18002_Pad5, net_U18002_Pad6, GND, net_U18002_Pad8, net_U18002_Pad9, net_U18002_Pad10, net_U18002_Pad11, net_U18002_Pad12, MAINRS, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U18003(net_U18001_Pad12, net_U18001_Pad13, net_U18001_Pad6, CH1502, net_U18001_Pad13, __A18_1__RCH15_n, GND, MKEY3, net_U18003_Pad13, net_U18002_Pad5, net_U18002_Pad5, net_U18001_Pad6, net_U18003_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18004(CH1503, net_U18002_Pad5, __A18_1__RCH15_n, net_U18002_Pad9, MKEY4, net_U18004_Pad10, GND, net_U18002_Pad9, net_U18001_Pad6, net_U18004_Pad10, net_U18002_Pad9, __A18_1__RCH15_n, CH1504, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18005(net_U18002_Pad11, MKEY5, net_U18005_Pad3, net_U18005_Pad3, net_U18002_Pad11, net_U18001_Pad6, GND, net_U18002_Pad11, __A18_1__RCH15_n, CH1505, net_U18002_Pad8, net_U18002_Pad10, net_U18005_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18006(net_U18002_Pad2, net_U18002_Pad4, net_U18006_Pad10, net_R18001_Pad2, __A18_1__F09D, net_U18006_Pad6, GND, KYRPT1, TPOR_n, net_U18006_Pad10, F09B_n, net_U18006_Pad12, net_U18002_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74LVC07 U18007(net_U18006_Pad12, net_R18001_Pad2, net_U18005_Pad13, net_R18001_Pad2, net_U18007_Pad5, net_R18002_Pad2, GND, net_R18002_Pad2, net_U18007_Pad9, __A18_2__CNTOF9, net_U18007_Pad11, __A18_2__CNTOF9, net_U18007_Pad13, p4VSW, SIM_RST, SIM_CLK); //FPGA#OD:2,4,6,8,10,12
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0) U18008(net_U18002_Pad12, net_U18001_Pad6, net_U18008_Pad3, __A18_1__RCH15_n, net_R18001_Pad2, net_U18008_Pad6, GND, net_U18008_Pad11, NAVRST, net_U18008_Pad10, net_U18008_Pad11, __A18_1__RCH16_n, net_U18008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U18009(__A18_2__RRSYNC, net_U18009_Pad2, net_U18009_Pad3, net_U18008_Pad3, XT1_n, XB5_n, GND, net_U18009_Pad8, net_U18006_Pad6, net_U18006_Pad10, T05, T11, TPOR_n, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 U18010(net_U18009_Pad8, __A18_1__F09A_n, net_R18001_Pad2, net_U18001_Pad6, net_U18010_Pad5, , GND, , __A18_1__F09A_n, net_R18002_Pad2, net_U18008_Pad10, net_U18010_Pad12, net_U18010_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18011(net_U18011_Pad1, net_U18008_Pad6, net_U18002_Pad12, net_U18010_Pad5, net_U18011_Pad1, net_U18011_Pad10, GND, net_U18010_Pad5, KYRPT1, net_U18011_Pad10, XT1_n, XB6_n, net_U18008_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b1) U18012(net_U18012_Pad1, NKEY1, net_U18012_Pad3, net_U18012_Pad3, net_U18012_Pad1, net_U18008_Pad10, GND, net_U18012_Pad1, __A18_1__RCH16_n, CH1601, NKEY2, net_U18012_Pad12, net_U18012_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U18013(net_U18012_Pad1, net_U18013_Pad2, net_U18012_Pad13, net_U18013_Pad4, net_U18013_Pad5, net_U18013_Pad6, GND, net_U18013_Pad8, net_U18013_Pad9, net_U18013_Pad10, net_U18013_Pad11, net_U18013_Pad12, net_R18002_Pad2, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b1, 1'b0) U18014(net_U18012_Pad12, net_U18012_Pad13, net_U18008_Pad10, CH1602, net_U18012_Pad13, __A18_1__RCH16_n, GND, NKEY3, net_U18014_Pad13, net_U18013_Pad5, net_U18013_Pad5, net_U18008_Pad10, net_U18014_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18015(CH1603, net_U18013_Pad5, __A18_1__RCH16_n, net_U18013_Pad9, NKEY4, net_U18015_Pad10, GND, net_U18013_Pad9, net_U18008_Pad10, net_U18015_Pad10, net_U18013_Pad9, __A18_1__RCH16_n, CH1604, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18016(net_U18013_Pad11, NKEY5, net_U18016_Pad3, net_U18016_Pad3, net_U18013_Pad11, net_U18008_Pad10, GND, net_U18013_Pad11, __A18_1__RCH16_n, CH1605, net_U18013_Pad8, net_U18013_Pad10, net_U18007_Pad9, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18017(net_U18013_Pad2, net_U18013_Pad4, net_U18017_Pad10, net_R18002_Pad2, __A18_1__F09D, net_U18017_Pad6, GND, KYRPT2, TPOR_n, net_U18017_Pad10, F09B_n, net_U18007_Pad5, net_U18013_Pad6, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U18018(net_U18017_Pad10, net_U18010_Pad13, net_U18017_Pad6, net_U18018_Pad4, net_U18013_Pad12, net_U18008_Pad11, GND, net_U18018_Pad4, net_U18018_Pad13, net_U18010_Pad12, net_U18010_Pad12, KYRPT2, net_U18018_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18119(net_U18119_Pad1, WCH13_n, CHWL11_n, net_U18119_Pad11, net_U18119_Pad1, net_U18119_Pad10, GND, net_U18119_Pad11, CCH13, net_U18119_Pad10, net_U18119_Pad11, RCH13_n, CH1311, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b0, 1'b1, 1'b0, 1'b0) U18120(SBYBUT, net_U18120_Pad2, F17A, __A18_1__F17A_n, F17B, __A18_1__F17B_n, GND, STNDBY_n, __A18_1__STNDBY, SBY, STNDBY_n, SBYLIT, net_U18120_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18121(net_U18121_Pad1, __A18_1__F17A_n, net_U18120_Pad2, net_U18121_Pad12, net_U18121_Pad1, net_U18121_Pad10, GND, net_U18121_Pad12, net_U18120_Pad2, net_U18121_Pad10, __A18_1__F17B_n, net_U18121_Pad12, net_U18121_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U18122(net_U18122_Pad1, net_U18121_Pad13, net_U18122_Pad3, net_U18122_Pad3, net_U18122_Pad1, net_U18120_Pad2, GND, net_U18122_Pad8, net_U18122_Pad13, net_U18122_Pad10, net_U18122_Pad10, net_U18122_Pad1, net_U18122_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC27 U18023( , , __A18_2__ACTV_n, RADRPT, CCH13, net_U18023_Pad6, GND, __A18_2__ADVCNT, F10A_n, net_U18023_Pad10, SB2_n, , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18124(net_U18124_Pad1, net_U18122_Pad13, net_U18122_Pad1, net_U18124_Pad4, net_U18122_Pad13, __A18_1__STNDBY, GND, net_U18124_Pad4, net_U18124_Pad1, __A18_1__STNDBY, __A18_1__STNDBY, ALTEST, net_U18120_Pad13, p4VDC, SIM_RST, SIM_CLK);
U74HC04 #(1'b1, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0) U18025(MRKRST, net_U18025_Pad2, net_U18025_Pad2, net_U18025_Pad4, net_U18025_Pad5, net_U18025_Pad6, GND, net_U18025_Pad8, net_U18025_Pad9, net_U18025_Pad10, net_U18025_Pad11, __A18_1__F08B_n, F08B, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b0) U18026(net_U18025_Pad5, MARK, net_U18026_Pad3, net_U18026_Pad3, net_U18025_Pad5, net_U18025_Pad4, GND, MRKREJ, net_U18026_Pad13, net_U18025_Pad9, net_U18025_Pad9, net_U18025_Pad4, net_U18026_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b0, 1'b0, 1'b1) U18027(CH1606, net_U18025_Pad5, __A18_1__RCH16_n, CH1607, net_U18025_Pad9, __A18_1__RCH16_n, GND, net_U18025_Pad6, net_U18025_Pad8, net_U18025_Pad11, net_U18027_Pad11, net_U18027_Pad12, net_U18027_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b0, 1'b1) U18028(net_U18027_Pad11, __A18_1__F09A_n, net_U18025_Pad11, net_U18025_Pad4, net_U18028_Pad5, , GND, , net_U18028_Pad9, RADRPT, __A18_2__ADVCNT, net_U18028_Pad12, net_U18028_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18029(TPOR_n, net_U18027_Pad13, net_U18027_Pad13, net_U18025_Pad11, __A18_1__F09D, net_U18027_Pad12, GND, net_U18029_Pad8, net_U18029_Pad9, net_U18029_Pad10, net_U18029_Pad11, MKRPT, F09B_n, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18030(net_U18030_Pad1, net_U18025_Pad10, net_U18025_Pad2, net_U18028_Pad5, net_U18030_Pad1, net_U18030_Pad10, GND, net_U18028_Pad5, MKRPT, net_U18030_Pad10, net_U18030_Pad11, FS09_n, __A18_1__F09D, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b0, 1'b1, 1'b0, 1'b0, 1'b1) U18031(__A18_1__F08B_n, net_U18030_Pad11, net_U18031_Pad3, net_U18031_Pad4, net_U18031_Pad5, net_U18029_Pad9, GND, net_U18031_Pad8, net_U18031_Pad9, net_U18031_Pad10, net_U18031_Pad11, net_U18031_Pad12, __A18_2__CNTOF9, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b0) U18032(net_U18032_Pad1, CHWL04_n, WCH13_n, __A18_2__ACTV_n, net_U18032_Pad1, net_U18023_Pad6, GND, RCH13_n, __A18_2__ACTV_n, CH1304, CHWL03_n, WCH13_n, net_U18032_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18033(net_U18031_Pad3, net_U18032_Pad13, net_U18031_Pad5, net_U18031_Pad5, net_U18031_Pad3, CCH13, GND, RCH13_n, net_U18031_Pad3, CH1303, CHWL02_n, WCH13_n, net_U18033_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18034(net_U18034_Pad1, net_U18033_Pad13, net_U18034_Pad3, net_U18034_Pad3, net_U18034_Pad1, CCH13, GND, RCH13_n, net_U18034_Pad1, CH1302, CHWL01_n, WCH13_n, net_U18034_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18035(net_U18035_Pad1, net_U18034_Pad13, net_U18035_Pad3, net_U18035_Pad3, net_U18035_Pad1, CCH13, GND, RCH13_n, net_U18035_Pad1, CH1301, F10A_n, SB0_n, __A18_2__F10AS0, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18036(net_U18023_Pad10, __A18_2__F10AS0, net_U18036_Pad3, net_U18036_Pad3, net_U18023_Pad10, __A18_2__ACTV_n, GND, net_U18028_Pad12, net_U18036_Pad12, net_U18036_Pad10, net_U18028_Pad13, net_U18036_Pad12, net_U18036_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18037(net_U18028_Pad13, __A18_2__ADVCNT, net_U18036_Pad13, RADRPT, net_U18028_Pad13, net_U18028_Pad9, GND, net_U18037_Pad8, net_U18037_Pad9, net_U18028_Pad9, net_U18037_Pad11, net_U18028_Pad12, net_U18036_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18038(net_U18036_Pad12, net_U18036_Pad13, net_U18028_Pad12, net_U18038_Pad4, net_U18038_Pad13, net_U18037_Pad9, GND, net_U18037_Pad8, net_U18038_Pad12, net_U18037_Pad11, net_U18037_Pad9, net_U18038_Pad12, net_U18038_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b1) U18039(net_U18037_Pad9, net_U18038_Pad4, RADRPT, net_U18028_Pad9, net_U18037_Pad8, , GND, , net_U18039_Pad9, RADRPT, net_U18038_Pad4, net_U18039_Pad12, net_U18039_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18040(net_U18038_Pad12, net_U18038_Pad13, net_U18037_Pad8, net_U18039_Pad9, net_U18040_Pad13, net_U18039_Pad13, GND, net_U18039_Pad12, net_U18040_Pad12, net_U18040_Pad10, net_U18039_Pad13, net_U18040_Pad12, net_U18040_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18041(net_U18039_Pad13, net_U18038_Pad4, net_U18041_Pad3, net_U18039_Pad9, net_U18041_Pad5, net_U18041_Pad6, GND, net_U18007_Pad13, net_U18038_Pad12, net_U18036_Pad13, F10A, net_U18039_Pad12, net_U18040_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b0, 1'b0) U18042(net_U18040_Pad12, net_U18040_Pad13, net_U18039_Pad12, net_U18042_Pad4, net_U18042_Pad13, net_U18041_Pad3, GND, net_U18041_Pad6, net_U18042_Pad12, net_U18041_Pad5, net_U18041_Pad3, net_U18042_Pad12, net_U18042_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC4002 #(1'b1, 1'b0) U18043(net_U18041_Pad3, net_U18042_Pad4, RADRPT, net_U18039_Pad9, net_U18041_Pad6, , GND, , , , , , , p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b1, 1'b0, 1'b1, 1'b1) U18044(net_U18042_Pad12, net_U18042_Pad13, net_U18041_Pad6, net_U18007_Pad11, net_U18042_Pad13, net_U18040_Pad12, GND, __A18_2__ADVCNT, net_U18044_Pad9, net_U18044_Pad10, net_U18034_Pad3, net_U18035_Pad3, net_U18044_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18045(net_U18044_Pad10, __A18_2__CNTOF9, net_U18031_Pad4, net_U18044_Pad10, F5BSB2_n, net_U18031_Pad9, GND, net_U18031_Pad11, F5BSB2_n, net_U18044_Pad10, net_U18029_Pad9, net_U18044_Pad9, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18046(net_U18034_Pad3, net_U18035_Pad1, net_U18031_Pad8, net_U18035_Pad3, net_U18034_Pad1, __A18_2__RRRARA, GND, __A18_2__LRXVEL, net_U18035_Pad3, net_U18034_Pad3, net_U18031_Pad10, __A18_2__RRRANG, net_U18031_Pad8, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18047(net_U18031_Pad10, net_U18035_Pad1, net_U18031_Pad10, net_U18034_Pad1, net_U18035_Pad3, __A18_2__LRZVEL, GND, __A18_2__LRRANG, net_U18031_Pad10, net_U18034_Pad1, net_U18035_Pad1, __A18_2__LRYVEL, net_U18034_Pad3, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b0, 1'b1) U18048(net_U18048_Pad1, net_U18031_Pad12, GTSET_n, net_U18048_Pad4, net_U18048_Pad1, net_U18048_Pad6, GND, F5ASB2_n, net_U18048_Pad4, net_U18048_Pad10, net_U18048_Pad10, net_U18048_Pad12, net_U18048_Pad13, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18049(net_U18048_Pad4, RADRPT, net_U18048_Pad13, F09B, GOJAM, net_U18048_Pad12, GND, RADRPT, net_U18049_Pad9, net_U18048_Pad13, GTRST_n, net_U18048_Pad6, GOJAM, p4VSW, SIM_RST, SIM_CLK);
U74HC04 #(1'b0, 1'b1, 1'b1, 1'b0, 1'b0, 1'b0) U18050(TPOR_n, __A18_2__HERB, __A18_2__HERB, net_U18049_Pad9, net_U18050_Pad5, net_U18009_Pad2, GND, net_U18050_Pad8, RRIN1, net_U18050_Pad10, RRIN0, net_U18050_Pad12, LRIN1, p4VSW, SIM_RST, SIM_CLK);
U74HC02 #(1'b0, 1'b1, 1'b1, 1'b0) U18051(net_U18050_Pad5, net_U18044_Pad13, net_U18031_Pad4, net_U18051_Pad4, net_U18051_Pad5, net_U18051_Pad6, GND, net_U18051_Pad8, net_U18029_Pad8, net_U18051_Pad10, net_U18009_Pad3, net_U18029_Pad9, __A18_2__LRSYNC, p4VSW, SIM_RST, SIM_CLK);
U74HC27 U18052(net_U18009_Pad2, net_U18050_Pad8, net_U18009_Pad2, net_U18050_Pad10, net_U18029_Pad11, net_U18051_Pad8, GND, net_U18051_Pad6, net_U18029_Pad9, net_U18050_Pad12, net_U18029_Pad11, net_U18051_Pad5, net_U18029_Pad11, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U18053(LRIN0, net_U18029_Pad10, net_U18023_Pad6, net_U18029_Pad11, F09A, __A18_1__F09A_n, GND, RNRADP, net_U18051_Pad4, RNRADM, net_U18051_Pad10, net_U18009_Pad3, net_U18048_Pad10, p4VSW, SIM_RST, SIM_CLK);
U74HC04 U18154(SBY, SBYREL_n, , , , , GND, , , , , , , p4VDC, SIM_RST, SIM_CLK);
U74HC27 U18155(net_U18122_Pad1, STOP, , , , , GND, , , , , net_U18122_Pad8, net_U18119_Pad11, p4VDC, SIM_RST, SIM_CLK);
endmodule |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_edge.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Detects and stores edges as the test pattern is scanned via
// manipulating the phaser out stage 3 taps.
//
// Scanning always proceeds from the left to the right. For more
// on the scanning algorithm, see the _po_cntlr block.
//
// Four scan results are reported. The edges at fuzz2zero,
// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
// has a 6 bit stg3 tap value and a valid bit. The valid bits
// are reset before the scan starts.
//
// Once reset_scan is set low, this block waits for the first
// samp_done while scanning_right. This marks the left end
// of the scan, and initializes prev_samp_r with samp_result and
// sets the prev_samp_r valid bit to one.
//
// At each subesquent samp_done, the previous samp is compared
// to the current samp_result. The case statement details how
// edges are identified.
//
// Original design assumed fuzz between valid regions. Design
// has been updated to tolerate transitions from zero to oneeight
// and vice-versa without fuzz in between.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_edge #
(parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
oneeighty2fuzz, fuzz2oneeighty,
// Inputs
clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
samp_result, stg3
);
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input samp_done;
input phy_rddata_en_2;
wire samp_valid = samp_done && phy_rddata_en_2;
input reset_scan;
input scanning_right;
reg prev_samp_valid_ns, prev_samp_valid_r;
always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
always @(*) begin
prev_samp_valid_ns = prev_samp_valid_r;
if (reset_scan) prev_samp_valid_ns = 1'b0;
else if (samp_valid) prev_samp_valid_ns = 1'b1;
end
input [1:0] samp_result;
reg [1:0] prev_samp_ns, prev_samp_r;
always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
always @(*)
if (samp_valid) prev_samp_ns = samp_result;
else prev_samp_ns = prev_samp_r;
reg scan_right_ns, scan_right_r;
always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
output scan_right;
assign scan_right = scan_right_r;
input [5:0] stg3;
reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
always @(posedge clk) z2f_r <= #TCQ z2f_ns;
always @(posedge clk) f2z_r <= #TCQ f2z_ns;
always @(posedge clk) o2f_r <= #TCQ o2f_ns;
always @(posedge clk) f2o_r <= #TCQ f2o_ns;
output z2f, f2z, o2f, f2o;
assign z2f = z2f_r;
assign f2z = f2z_r;
assign o2f = o2f_r;
assign f2o = f2o_r;
reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
assign zero2fuzz = zero2fuzz_r;
assign fuzz2zero = fuzz2zero_r;
assign oneeighty2fuzz = oneeighty2fuzz_r;
assign fuzz2oneeighty = fuzz2oneeighty_r;
always @(*) begin
z2f_ns = z2f_r;
f2z_ns = f2z_r;
o2f_ns = o2f_r;
f2o_ns = f2o_r;
zero2fuzz_ns = zero2fuzz_r;
fuzz2zero_ns = fuzz2zero_r;
oneeighty2fuzz_ns = oneeighty2fuzz_r;
fuzz2oneeighty_ns = fuzz2oneeighty_r;
scan_right_ns = 1'b0;
if (reset_scan) begin
z2f_ns = 1'b0;
f2z_ns = 1'b0;
o2f_ns = 1'b0;
f2o_ns = 1'b0;
end
else if (samp_valid && prev_samp_valid_r)
case (prev_samp_r)
FUZZ :
if (scanning_right) begin
if (samp_result == ZERO) begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
ZERO : begin
if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
if (scanning_right) begin
if (samp_result == FUZZ) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
end
ONEEIGHTY :
if (scanning_right) begin
if (samp_result == FUZZ) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end
if (samp_result == ZERO)
if (f2o_r) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end else begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
end // if (scanning_right)
// NULL : // Should never happen
endcase
end
endmodule // mig_7series_v2_3_ddr_phy_ocd_edge
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI data fifo module:
// 5-channel memory-mapped AXI4 interfaces.
// SRL or BRAM based FIFO on AXI W and/or R channels.
// FIFO to accommodate various data flow rates through the AXI interconnect
//
// Verilog-standard: Verilog 2001
//-----------------------------------------------------------------------------
//
// Structure:
// axi_data_fifo
// fifo_generator
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_6_axi_data_fifo #
(
parameter C_FAMILY = "virtex7",
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_WRITE_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_WRITE_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_WRITE_FIFO_DELAY = 0, // 0 = No, 1 = Yes
// Indicates whether AWVALID and WVALID assertion is delayed until:
// a. the corresponding WLAST is stored in the FIFO, or
// b. no WLAST is stored and the FIFO is full.
// 0 means AW channel is pass-through and
// WVALID is asserted whenever FIFO is not empty.
parameter integer C_AXI_READ_FIFO_DEPTH = 0, // Range: (0, 32, 512)
parameter C_AXI_READ_FIFO_TYPE = "lut", // "lut" = LUT (SRL) based,
// "bram" = BRAM based
parameter integer C_AXI_READ_FIFO_DELAY = 0) // 0 = No, 1 = Yes
// Indicates whether ARVALID assertion is delayed until the
// the remaining vacancy of the FIFO is at least the burst length
// as indicated by ARLEN.
// 0 means AR channel is pass-through.
// System Signals
(input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready);
localparam integer P_WIDTH_RACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_ARUSER_WIDTH;
localparam integer P_WIDTH_WACH = 4+4+3+4+2+3+((C_AXI_PROTOCOL==1)?6:9)+C_AXI_ADDR_WIDTH+C_AXI_ID_WIDTH+C_AXI_AWUSER_WIDTH;
localparam integer P_WIDTH_RDCH = 1 + 2 + C_AXI_DATA_WIDTH + C_AXI_ID_WIDTH + C_AXI_RUSER_WIDTH;
localparam integer P_WIDTH_WDCH = 1+C_AXI_DATA_WIDTH+C_AXI_DATA_WIDTH/8+((C_AXI_PROTOCOL==1)?C_AXI_ID_WIDTH:0)+C_AXI_WUSER_WIDTH;
localparam integer P_WIDTH_WRCH = 2 + C_AXI_ID_WIDTH + C_AXI_BUSER_WIDTH;
localparam P_PRIM_FIFO_TYPE = "512x72" ;
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_WRITE_FIFO_DEPTH_LOG = (C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1;
localparam integer P_READ_FIFO_DEPTH_LOG = (C_AXI_READ_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1;
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
generate
if (((C_AXI_WRITE_FIFO_DEPTH == 0) && (C_AXI_READ_FIFO_DEPTH == 0)) || (C_AXI_PROTOCOL == P_AXILITE)) begin : gen_bypass
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_axi_awvalid;
assign s_axi_awready = m_axi_awready;
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_wready = m_axi_wready;
assign s_axi_bid = m_axi_bid;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_buser = m_axi_buser;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_axi_arvalid;
assign s_axi_arready = m_axi_arready;
assign s_axi_rid = m_axi_rid;
assign s_axi_rdata = m_axi_rdata;
assign s_axi_rresp = m_axi_rresp;
assign s_axi_rlast = m_axi_rlast;
assign s_axi_ruser = m_axi_ruser;
assign s_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = s_axi_rready;
end else begin : gen_fifo
wire [4-1:0] s_axi_awregion_i;
wire [4-1:0] s_axi_arregion_i;
wire [4-1:0] m_axi_awregion_i;
wire [4-1:0] m_axi_arregion_i;
wire [C_AXI_ID_WIDTH-1:0] s_axi_wid_i;
wire [C_AXI_ID_WIDTH-1:0] m_axi_wid_i;
assign s_axi_awregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_awregion;
assign s_axi_arregion_i = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : s_axi_arregion;
assign m_axi_awregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_awregion_i;
assign m_axi_arregion = (C_AXI_PROTOCOL == P_AXI3) ? 4'b0 : m_axi_arregion_i;
assign s_axi_wid_i = (C_AXI_PROTOCOL == P_AXI3) ? s_axi_wid : {C_AXI_ID_WIDTH{1'b0}};
assign m_axi_wid = (C_AXI_PROTOCOL == P_AXI3) ? m_axi_wid_i : {C_AXI_ID_WIDTH{1'b0}};
fifo_generator_v13_0_1 #(
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : 3),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),
.C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),
.C_HAS_AXI_ARUSER(1),
.C_HAS_AXI_AWUSER(1),
.C_HAS_AXI_BUSER(1),
.C_HAS_AXI_RUSER(1),
.C_HAS_AXI_WUSER(1),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),
.C_DIN_WIDTH_RACH(P_WIDTH_RACH),
.C_DIN_WIDTH_RDCH(P_WIDTH_RDCH),
.C_DIN_WIDTH_WACH(P_WIDTH_WACH),
.C_DIN_WIDTH_WDCH(P_WIDTH_WDCH),
.C_DIN_WIDTH_WRCH(P_WIDTH_WDCH),
.C_RACH_TYPE(((C_AXI_READ_FIFO_DEPTH != 0) && C_AXI_READ_FIFO_DELAY) ? 0 : 2),
.C_WACH_TYPE(((C_AXI_WRITE_FIFO_DEPTH != 0) && C_AXI_WRITE_FIFO_DELAY) ? 0 : 2),
.C_WDCH_TYPE((C_AXI_WRITE_FIFO_DEPTH != 0) ? 0 : 2),
.C_RDCH_TYPE((C_AXI_READ_FIFO_DEPTH != 0) ? 0 : 2),
.C_WRCH_TYPE(2),
.C_COMMON_CLOCK(1),
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(C_AXI_READ_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(C_AXI_WRITE_FIFO_DELAY ? 1 : 0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DIN_WIDTH_AXIS(1),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(2),
.C_IMPLEMENTATION_TYPE_RDCH((C_AXI_READ_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WACH(2),
.C_IMPLEMENTATION_TYPE_WDCH((C_AXI_WRITE_FIFO_TYPE == "bram") ? 1 : 2),
.C_IMPLEMENTATION_TYPE_WRCH(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE(P_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(510),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(511),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(C_AXI_READ_FIFO_DEPTH),
.C_WR_DEPTH_WACH(32),
.C_WR_DEPTH_WDCH(C_AXI_WRITE_FIFO_DEPTH),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH((C_AXI_READ_FIFO_DEPTH> 1) ? f_ceil_log2(C_AXI_READ_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WACH(5),
.C_WR_PNTR_WIDTH_WDCH((C_AXI_WRITE_FIFO_DEPTH > 1) ? f_ceil_log2(C_AXI_WRITE_FIFO_DEPTH) : 1),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1)
)
fifo_gen_inst (
.s_aclk(aclk),
.s_aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awregion(s_axi_awregion_i),
.s_axi_awuser(s_axi_awuser),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid_i),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awregion(m_axi_awregion_i),
.m_axi_awuser(m_axi_awuser),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid_i),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arregion(s_axi_arregion_i),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arregion(m_axi_arregion_i),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
.m_aclk(aclk),
.m_aclk_en(1'b1),
.s_aclk_en(1'b1),
.s_axi_wuser(s_axi_wuser),
.s_axi_buser(s_axi_buser),
.m_axi_wuser(m_axi_wuser),
.m_axi_buser(m_axi_buser),
.s_axi_aruser(s_axi_aruser),
.s_axi_ruser(s_axi_ruser),
.m_axi_aruser(m_axi_aruser),
.m_axi_ruser(m_axi_ruser),
.almost_empty(),
.almost_full(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(5'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(5'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_prog_full(),
.axi_r_prog_full_thresh({P_READ_FIFO_DEPTH_LOG{1'b0}}),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_prog_full(),
.axi_w_prog_full_thresh({P_WRITE_FIFO_DEPTH_LOG{1'b0}}),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(),
.dbiterr(),
.din(18'b0),
.dout(),
.empty(),
.full(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full(),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.rd_clk(1'b0),
.rd_data_count(),
.rd_en(1'b0),
.rd_rst(1'b0),
.rst(1'b0),
.sbiterr(),
.srst(1'b0),
.s_axis_tdata(64'b0),
.s_axis_tdest(4'b0),
.s_axis_tid(8'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(4'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_clk(1'b0),
.wr_data_count(),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
endgenerate
endmodule
|
// Certain arithmetic operations between a signal of width n and a constant can be directly mapped
// to a single k-LUT (where n <= k). This is preferable to normal alumacc techmapping process
// because for many targets, arithmetic techmapping creates hard logic (such as carry cells) which often
// cannot be optimized further.
//
// TODO: Currently, only comparisons with 1-bit output are mapped. Potentially, all arithmetic cells
// with n <= k inputs should be techmapped in this way, because this shortens the critical path
// from n to 1 by avoiding carry chains.
(* techmap_celltype = "$lt $le $gt $ge" *)
module _90_lut_cmp_ (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_CELLTYPE_ = "";
parameter _TECHMAP_CONSTMSK_A_ = 0;
parameter _TECHMAP_CONSTVAL_A_ = 0;
parameter _TECHMAP_CONSTMSK_B_ = 0;
parameter _TECHMAP_CONSTVAL_B_ = 0;
function automatic [(1 << `LUT_WIDTH)-1:0] gen_lut;
input integer width;
input integer operation;
input integer swap;
input integer sign;
input integer operand;
integer n, i_var, i_cst, lhs, rhs, o_bit;
begin
gen_lut = width'b0;
for (n = 0; n < (1 << width); n++) begin
if (sign)
i_var = n[width-1:0];
else
i_var = n;
i_cst = operand;
if (swap) begin
lhs = i_cst;
rhs = i_var;
end else begin
lhs = i_var;
rhs = i_cst;
end
if (operation == 0)
o_bit = (lhs < rhs);
if (operation == 1)
o_bit = (lhs <= rhs);
if (operation == 2)
o_bit = (lhs > rhs);
if (operation == 3)
o_bit = (lhs >= rhs);
gen_lut = gen_lut | (o_bit << n);
end
end
endfunction
generate
localparam operation =
_TECHMAP_CELLTYPE_ == "$lt" ? 0 :
_TECHMAP_CELLTYPE_ == "$le" ? 1 :
_TECHMAP_CELLTYPE_ == "$gt" ? 2 :
_TECHMAP_CELLTYPE_ == "$ge" ? 3 :
-1;
if (A_WIDTH > `LUT_WIDTH || B_WIDTH > `LUT_WIDTH || Y_WIDTH != 1)
wire _TECHMAP_FAIL_ = 1;
else if (&_TECHMAP_CONSTMSK_B_)
\$lut #(
.WIDTH(A_WIDTH),
.LUT({ gen_lut(A_WIDTH, operation, 0, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_B_) })
) _TECHMAP_REPLACE_ (
.A(A),
.Y(Y)
);
else if (&_TECHMAP_CONSTMSK_A_)
\$lut #(
.WIDTH(B_WIDTH),
.LUT({ gen_lut(B_WIDTH, operation, 1, A_SIGNED && B_SIGNED, _TECHMAP_CONSTVAL_A_) })
) _TECHMAP_REPLACE_ (
.A(B),
.Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_b_channel.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] s_bid,
output wire [1:0] s_bresp,
output wire s_bvalid,
input wire s_bready,
input wire [1:0] m_bresp,
input wire m_bvalid,
output wire m_bready,
// Signals to/from the axi_protocol_converter_v2_1_b2s_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire [7:0] b_awlen,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// AXI protocol responses:
localparam [1:0] LP_RESP_OKAY = 2'b00;
localparam [1:0] LP_RESP_EXOKAY = 2'b01;
localparam [1:0] LP_RESP_SLVERROR = 2'b10;
localparam [1:0] LP_RESP_DECERR = 2'b11;
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH + 8;
localparam P_DEPTH = 4;
localparam P_AWIDTH = 2;
localparam P_RWIDTH = 2;
localparam P_RDEPTH = 4;
localparam P_RAWIDTH = 2;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg bvalid_i;
wire [C_ID_WIDTH-1:0] bid_i;
wire shandshake;
reg shandshake_r;
wire mhandshake;
reg mhandshake_r;
wire b_empty;
wire bresp_full;
wire bresp_empty;
wire [7:0] b_awlen_i;
reg [7:0] bresp_cnt;
reg [1:0] s_bresp_acc;
wire [1:0] s_bresp_acc_r;
reg [1:0] s_bresp_i;
wire need_to_update_bresp;
wire bresp_push;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// assign AXI outputs
assign s_bid = bid_i;
assign s_bresp = s_bresp_acc_r;
assign s_bvalid = bvalid_i;
assign shandshake = s_bvalid & s_bready;
assign mhandshake = m_bvalid & m_bready;
always @(posedge clk) begin
if (reset | shandshake) begin
bvalid_i <= 1'b0;
end else if (~b_empty & ~shandshake_r & ~bresp_empty) begin
bvalid_i <= 1'b1;
end
end
always @(posedge clk) begin
shandshake_r <= shandshake;
mhandshake_r <= mhandshake;
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( shandshake_r ) ,
.din ( {b_awid, b_awlen} ) ,
.dout ( {bid_i, b_awlen_i}) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( b_empty )
);
assign m_bready = ~mhandshake_r & bresp_empty;
/////////////////////////////////////////////////////////////////////////////
// Update if more critical.
assign need_to_update_bresp = ( m_bresp > s_bresp_acc );
// Select accumultated or direct depending on setting.
always @( * ) begin
if ( need_to_update_bresp ) begin
s_bresp_i = m_bresp;
end else begin
s_bresp_i = s_bresp_acc;
end
end
/////////////////////////////////////////////////////////////////////////////
// Accumulate MI-side BRESP.
always @ (posedge clk) begin
if (reset | bresp_push ) begin
s_bresp_acc <= LP_RESP_OKAY;
end else if ( mhandshake ) begin
s_bresp_acc <= s_bresp_i;
end
end
assign bresp_push = ( mhandshake_r ) & (bresp_cnt == b_awlen_i) & ~b_empty;
always @ (posedge clk) begin
if (reset | bresp_push ) begin
bresp_cnt <= 8'h00;
end else if ( mhandshake_r ) begin
bresp_cnt <= bresp_cnt + 1'b1;
end
end
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_RWIDTH),
.C_AWIDTH (P_RAWIDTH),
.C_DEPTH (P_RDEPTH)
)
bresp_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( bresp_push ) ,
.rd_en ( shandshake_r ) ,
.din ( s_bresp_acc ) ,
.dout ( s_bresp_acc_r) ,
.a_full ( ) ,
.full ( bresp_full ) ,
.a_empty ( ) ,
.empty ( bresp_empty )
);
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: tg_status.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module.
// Error signal will be asserted if the comparsion is not equal.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_tg_status #(
parameter TCQ = 100,
parameter DWIDTH = 32
)
(
input clk_i ,
input rst_i ,
input manual_clear_error,
input data_error_i ,
input [DWIDTH-1:0] cmp_data_i,
input [DWIDTH-1:0] rd_data_i ,
input [31:0] cmp_addr_i ,
input [5:0] cmp_bl_i ,
input mcb_cmd_full_i ,
input mcb_wr_full_i,
input mcb_rd_empty_i,
output reg [64 + (2*DWIDTH - 1):0] error_status,
output error
);
reg data_error_r;
reg error_set;
assign error = error_set;
always @ (posedge clk_i)
data_error_r <= #TCQ data_error_i;
always @ (posedge clk_i)
begin
if (rst_i || manual_clear_error) begin
error_status <= #TCQ 'b0;
error_set <= #TCQ 1'b0;
end
else begin
// latch the first error only
if (data_error_i && ~data_error_r && ~error_set ) begin
error_status[31:0] <= #TCQ cmp_addr_i;
error_status[37:32] <= #TCQ cmp_bl_i;
error_status[40] <= #TCQ mcb_cmd_full_i;
error_status[41] <= #TCQ mcb_wr_full_i;
error_status[42] <= #TCQ mcb_rd_empty_i;
error_set <= #TCQ 1'b1;
error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i;
error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i;
end
error_status[39:38] <= #TCQ 'b0; // reserved
error_status[63:43] <= #TCQ 'b0; // reserved
end end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FILL_DIODE_8_V
`define SKY130_FD_SC_HS__FILL_DIODE_8_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_diode_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hs__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fill_diode_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hs__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FILL_DIODE_8_V
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
Lemma neq_sym : forall {X : Type} (n m : X),
n <> m -> m <> n.
Proof. unfold not. intros. symmetry in H0. apply H in H0. inversion H0. Qed.
Lemma func_refl : forall {X Y : Type} (f : X -> Y) (v1 v2 : X),
v1 = v2 -> f v1 = f v2.
Proof. intros. rewrite H. reflexivity. Qed.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* assertions :) *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
valid
2) {{X = 2}} X ::= X + 1 {{X = 3}}
valid
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
X <> Y -> not valid
X = Y -> functional_extensionality -> valid
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
not valid
5) {{True}} SKIP {{False}}
not valid
6) {{False}} SKIP {{True}}
valid
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
Example hoare_triple_ex1 : {{fun st => (True)}} X::=(ANum 5) {{fun st => (st X) = 5}}.
Proof. unfold hoare_triple. intros. inversion H; subst; clear H. rewrite update_eq. reflexivity. Qed.
Example hoare_triple_ex2 : {{fun st => (st X = 2)}} X ::= APlus (AId X) (ANum 1) {{fun st => (st X) = 3}}.
Proof. unfold hoare_triple. intros. inversion H; subst; clear H. rewrite update_eq. simpl. rewrite H0. reflexivity. Qed.
Example hoare_triple_ex3_neq : X <> Y -> {{fun st => (True)}} X ::= (ANum 5);; Y ::= (ANum 0) {{fun st => (st X) = 5}}.
Proof. unfold not, hoare_triple. intros. inversion H0; subst; clear H0. inversion H4; subst; clear H4. inversion H7; subst; clear H7. simpl. apply update_neq. apply neq_sym. assumption. Qed.
Example hoare_triple_ex3_eq : X = Y -> ~{{fun st => (True)}} X ::= (ANum 5);; Y ::= (ANum 0) {{fun st => (st X) = 5}}.
Proof. unfold not, hoare_triple. intros. rewrite <- H in H0.
assert(G : (update empty_state X 0) X = 5).
apply H0 with (empty_state).
apply E_Seq with (update empty_state X 5).
constructor. reflexivity.
replace (update empty_state X 0) with (update (update empty_state X 5) X 0).
constructor.
reflexivity.
(* apply functional_extensionality. *)
Abort.
Example hoare_triple_ex4 : {{fun st => (st X) = 2 /\ (st X) = 3}} X ::= (ANum 5);; Y ::= (ANum 0) {{fun st => (st X) = 0}}.
Proof. unfold hoare_triple. intros. inversion H0. rewrite H1 in H2. inversion H2. Qed.
Example hoare_triple_ex5 : ~{{fun st => True}} SKIP {{fun st => False}}.
Proof. unfold not, hoare_triple. intros. apply H with (st:=empty_state) (st':=empty_state). constructor. reflexivity. Qed.
Example hoare_triple_ex6 : {{fun st => False}} SKIP {{fun st => True}}.
Proof. unfold hoare_triple. intros. reflexivity. Qed.
Example hoare_triple_ex7 : {{fun st => True}} WHILE BTrue DO SKIP END {{fun st => False}}.
Proof. unfold hoare_triple. intros.
remember (WHILE BTrue DO SKIP END) as loop.
induction H; inversion Heqloop; subst; simpl. inversion H. apply IHceval2. reflexivity. Qed.
Example hoare_triple_ex8 : {{fun st => (st X) = 0}} WHILE BEq (AId X) (ANum 0) DO X ::= APlus (AId X) (ANum 1) END {{fun st => (st X) = 1}}.
Proof. unfold hoare_triple. intros.
remember (WHILE BEq (AId X) (ANum 0) DO X ::= APlus (AId X) (ANum 1) END) as c.
destruct H; inversion Heqc; simpl.
apply func_refl with (f:=beval st) in H2.
simpl in H2. rewrite H in H2. symmetry in H2. apply beq_nat_false in H2.
rewrite H0 in H2. contradiction H2. reflexivity.
subst.
assert(G : st' X = 1).
inversion H1; subst; simpl. rewrite update_eq. rewrite H0. reflexivity.
inversion H2; subst; simpl. assumption. inversion H5; subst; simpl.
apply beq_nat_true in H4. omega.
Qed.
Lemma hoare_triple_ex9_may_diverge : forall st st',
1 <= (st X) ->
~((WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END) / st || st').
Proof.
unfold not; intros.
remember (WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END) as loop.
induction H0; inversion Heqloop; subst; simpl; clear Heqloop.
simpl in H0.
apply func_refl with (f:=negb) in H0.
rewrite negb_involutive in H0. simpl in H0. apply beq_nat_true in H0.
rewrite H0 in H. inversion H.
apply IHceval2.
inversion H0_; subst; simpl; clear H0_.
inversion H; subst; simpl; clear H. rewrite update_eq. apply le_S. constructor.
rewrite update_eq. omega.
reflexivity.
Qed.
(*
it was quite hard to prove ...
Lemma ex9_may_diverge : forall st st',
~(X ::= ANum 1;; WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END) / st || st'.
Proof.
unfold not. intros.
(*
remember (X ::= ANum 1 ;; WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END) as c.
induction H; inversion Heqc; subst; simpl.
clear Heqc IHceval1 IHceval2.
*)
inversion H; subst; simpl; clear H.
remember (WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END) as loop.
induction H5; inversion Heqloop; subst; simpl; clear Heqloop.
admit.
inversion H; subst; simpl; clear H.
inversion H2; subst; simpl; clear H2.
simpl in H. inversion H.
inversion H5_; subst; simpl; clear H5_.
apply IHceval2.
unfold not. intros.
inversion H; subst; simpl; clear H.
remember (WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END) as loop.
induction H5; inversion Heqloop; subst; simpl; clear Heqloop.
inversion H2; subst; simpl; clear H2.
simpl in H. inversion H.
inversion H5_; subst; simpl; clear H5_.
apply IHceval2.
admit.
induction H; inversion Heqloop; subst; simpl.
inversion H. apply func_refl with (f:=negb) in H1. rewrite negb_involutive in H1.
simpl in H1. apply beq_nat_true in H1.
*)
Example hoare_triple_ex9 : {{fun st => (st X) = 1}} WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END {{fun st => (st X) = 100}}.
Proof.
unfold hoare_triple; intros.
assert(G : 1 <= st X). omega.
apply hoare_triple_ex9_may_diverge in H. inversion H. assumption.
(*
remember (WHILE BNot (BEq (AId X) (ANum 0)) DO X ::= APlus (AId X) (ANum 1) END) as loop.
destruct H; inversion Heqloop; subst; simpl. simpl in H. rewrite H0 in H. simpl in H. inversion H.
clear Heqloop.
inversion H; subst; simpl. apply func_refl with (f:=negb) in H4. rewrite negb_involutive in H4. simpl in H4. apply beq_nat_false in H4.
apply IHceval2. reflexivity.
unfold not, hoare_triple.
intros.
generalize (H empty_state empty); intro Hn.
*)
Qed.
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(**
(X=0, Y=1)
X ::= Y
post/Q : X+X+X = 3
pre/Q [X |-> Y] : Y+Y+Y = 3
pre/X+Y+X = 3, X+Y+Y = 3 ...
2*2*2 right equations.
Is it always true that all these can be deduced from post/Q and pre/Q [X |-> Y] ??
**)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] to prove them. *)
Example hoare_assgn_ex1 : {{ (fun st => st X <= 5) [X |-> APlus (AId X) (ANum 1)] }}
X ::= APlus (AId X) (ANum 1)
{{ fun st => st X <= 5 }}.
Proof.
apply hoare_asgn. Qed.
Example hoare_assgn_ex2 : {{ (fun st => 0 <= st X /\ st X <= 5) [X |-> (ANum 3)] }}
X ::= (ANum 3)
{{ fun st => 0 <= st X /\ st X <= 5 }}.
Proof.
unfold hoare_triple. unfold assn_sub. simpl. intros.
inversion H; subst; simpl. assumption.
(* apply hoare_asgn. *)
Qed.
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
Example hoare_assgn_wrong_ex1 :
~{{ fun st => True }} X ::= APlus (AId X) (ANum 1) {{ fun st => st X = st X + 1 }}.
Proof.
unfold hoare_triple, not; intros.
generalize (H empty_state
(update empty_state X
(aeval empty_state (APlus (AId X) (ANum 1))))); intros.
simpl in H0.
assert(G : (X ::= APlus (AId X) (ANum 1)) / empty_state || update empty_state X 1).
apply E_Ass. reflexivity.
apply H0 in G. inversion G. reflexivity.
Qed.
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality m a P.
unfold hoare_triple. intros.
inversion H0; clear H0.
inversion H; subst; simpl; clear H.
assert(G : update (update st X (aeval st a)) X (st X) = st).
apply functional_extensionality; intro.
destruct (eq_id_dec x X).
rewrite e. rewrite update_eq. reflexivity.
rewrite update_neq. rewrite update_neq. reflexivity.
apply neq_sym. assumption. apply neq_sym. assumption.
split.
rewrite G. assumption.
rewrite G. rewrite update_eq. reflexivity.
Qed.
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}
*)
(* This rule was proposed by Nick Giannarakis and Zoe Paraskevopoulou. *)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality a P.
unfold hoare_triple.
intros.
inversion H; subst; simpl; clear H.
exists (st X).
assert(G : update (update st X (aeval st a)) X (st X) = st).
apply functional_extensionality; intro.
destruct (eq_id_dec x X).
rewrite e. rewrite update_eq. reflexivity.
rewrite update_neq. rewrite update_neq. reflexivity.
apply neq_sym. assumption. apply neq_sym. assumption.
split. rewrite G. assumption.
rewrite G. rewrite update_eq. reflexivity.
Qed.
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP. (* with (y:=0) *)
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
(* intros. inversion H; subst; clear H. eapply H0. apply H1. *)
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(* difference..? existential variable (a target to be binded)
should exist at the moment of eapply? *)
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] and
[hoare_consequence_pre] to prove them. *)
Example hoare_asgn_examples_2 :
{{ fun st => (st X) + 1 <= 5 }}
X ::= APlus (AId X) (ANum 1)
{{ fun st => (st X) <= 5 }}.
Proof.
eapply hoare_consequence_pre.
eapply hoare_asgn.
unfold assert_implies, assn_sub.
intros. simpl. rewrite update_eq. assumption.
(*
(** needed to specify :state in first function!!
otherwise it considers st as (id->nat) **)
assert(G : (fun st:state => (st X) + 1 <= 5) =
(fun st => (st X) <= 5) [X |-> APlus (AId X) (ANum 1)]
).
admit.
rewrite G.
apply hoare_asgn.
*)
(*
apply hoare_asgn with .
eapply hoare_consequence_pre.
constructor.
inversion H; subst; clear H.
simpl. rewrite update_eq.
eapply hoare_asgn.
constructor. reflexivity.
unfold assn_sub.
eapply hoare_consequence_pre.
*)
Qed.
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
(* X <> Y -> *)
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* intro. *)
assert(G : X <> Y). unfold not. intros. inversion H.
eapply hoare_seq.
apply hoare_asgn.
eapply hoare_consequence_pre. apply hoare_asgn.
(* intros st H. unfold assn_sub, update. simpl. omega. *)
unfold assert_implies, assn_sub.
intros.
simpl.
split. rewrite update_permute. rewrite update_eq. reflexivity. assumption.
rewrite update_eq. reflexivity.
Qed.
(** !!!!!!!!!!!!!!! X <> Y was trivial !!!!!!! **)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
(*
without extra variable
X /Y
X+Y/Y
X+Y/X
Y /X
*)
Definition swap_program : com :=
X ::= APlus (AId X) (AId Y) ;;
Y ::= AMinus (AId X) (AId Y) ;;
X ::= AMinus (AId X) (AId Y)
.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
unfold swap_program.
eapply hoare_seq.
eapply hoare_seq.
apply hoare_asgn.
apply hoare_asgn.
(* eapply hoare_asgn. constructor. reflexivity.*)
unfold hoare_triple, assn_sub.
intros.
inversion H; subst; simpl; clear H.
repeat rewrite update_eq.
rewrite update_neq.
repeat rewrite update_eq.
rewrite update_neq.
rewrite update_neq.
repeat rewrite update_eq.
omega.
unfold not; intros; inversion H.
unfold not; intros; inversion H.
unfold not; intros; inversion H.
Qed.
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(*
a may contain X
*)
Example hoarestate1 :
~(forall a n,
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}).
Proof.
unfold not.
intros.
generalize (H (AId X) 42); intro.
unfold hoare_triple in H0.
remember (update empty_state X 42) as init_state.
generalize (H0 (init_state) (update (update init_state X 3) Y 3)); intro.
assert(G1 : (X ::= ANum 3;; Y ::= AId X) / init_state
|| update (update init_state X 3) Y 3).
eapply E_Seq. apply E_Ass. reflexivity. apply E_Ass. reflexivity.
assert(G2 : (aeval init_state (AId X) = 42)).
rewrite Heqinit_state. simpl. rewrite update_eq. reflexivity.
generalize (H1 G1 G2); intro.
inversion H2.
(* contradiction H0. *)
Qed.
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ####################################################### *)
(** * Hoare Logic: So Far *)
(**
Idea: create a _domain specific logic_ for reasoning about properties of Imp programs.
- This hides the low-level details of the semantics of the program
- Leads to a compositional reasoning process
The basic structure is given by _Hoare triples_ of the form:
{{P}} c {{Q}}
]]
- [P] and [Q] are predicates about the state of the Imp program
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
*)
(** ** Hoare Logic Rules (so far) *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
apply hoare_if.
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assert_implies, bassn, assn_sub.
unfold update.
simpl.
intros. inversion H; clear H H0.
apply ble_nat_true in H1. omega.
unfold assert_implies, bassn, not, hoare_triple.
intros.
inversion H0; clear H0 H1.
inversion H; subst; simpl; clear H.
unfold update; simpl. reflexivity.
Qed.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Tactic Notation "my_inversion" tactic(target) :=
inversion target; subst; simpl; clear target.
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_If1True : forall st st' b c,
beval st b = true ->
c / st || st' ->
(IF1 b THEN c FI) / st || st'
| E_If1False : forall b st c,
beval st b = false ->
(IF1 b THEN c FI) / st || st
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_If1True" | Case_aux c "E_If1False"
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
(*
: forall (P : state -> Prop) (Q : Assertion) (b : bexp)
(c1 c2 : Imp.com),
({{fun st : state => P st /\ bassn b st}} c1 {{Q}}) ->
({{fun st : state => P st /\ ~ bassn b st}} c2 {{Q}}) ->
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
Theorem hoare_if1 : forall P Q b c,
{{fun st => P st /\ bassn b st}} c {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} SKIP {{Q}} ->
{{P}} (IF1 b THEN c FI) {{Q}}.
Proof.
unfold hoare_triple.
intros.
inversion H1; subst; simpl; clear H1.
eapply H. apply H8. split. assumption. assumption.
eapply H0. constructor. split. assumption.
apply bexp_eval_false in H7. assumption.
(*
inversion H0; subst; simpl; clear H0.
apply H in H7. assumption. split. assumption. assumption.
assumption.
*)
Qed.
(** For full credit, prove formally that your rule is precise enough
to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
Example hoare_if1_ex :
{{ fun st => (st X) + (st Y) = (st Z) }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => (st X) = (st Z) }}.
Proof.
apply hoare_if1.
unfold hoare_triple.
intros.
inversion H; subst; simpl; clear H.
inversion H0; subst; simpl; clear H0.
unfold update. simpl. assumption.
(* eapply hoare_asgn. constructor; reflexivity. unfold assn_sub. *)
unfold hoare_triple.
intros.
inversion H0; subst; simpl; clear H0.
inversion H; subst; clear H.
unfold not, bassn in H2.
simpl in H2.
rewrite <- H1.
destruct (st' Y). omega.
contradiction H2. simpl. reflexivity.
(* eapply hoare_skip. constructor. *)
Qed.
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof.
apply hoare_if1.
unfold update, bassn, hoare_triple.
intros.
my_inversion H.
my_inversion H0.
unfold update; simpl; assumption.
unfold bassn, hoare_triple.
intros.
my_inversion H.
my_inversion H0.
simpl in H1.
destruct (st' Y).
omega.
contradiction H1.
simpl. reflexivity.
Qed.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** *** *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(**
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
*)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
*)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
(*
{{P}} c {{P}} ->
{{P /\ b}} c {{P}}
When "X -> Y" is always true,
which form is stronger?
X -> WTS
Y -> WTS
second form is better, because
X -> Y && Y -> WTS ==> X -> WTS
When "X -> Y" is alwas true,
which form is stronger?
hypo -> X
hypo -> Y
first form is better, because
hypo -> X && X -> Y ==> hypo -> Y
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(**
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** *** *)
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(*
intros.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_skip.
unfold assert_implies, bassn.
intros. my_inversion H. assumption.
unfold assert_implies, bassn.
intros.
my_inversion H.
contradiction H1.
simpl. reflexivity.
*)
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall st st' b c,
ceval st c st' ->
beval st' b = true ->
ceval st (REPEAT c UNTIL b END) st'
| E_RepeatLoop : forall st st' st'' b c,
ceval st c st' ->
beval st' b = false ->
ceval st' (REPEAT c UNTIL b END) st'' ->
ceval st (REPEAT c UNTIL b END) st''
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_RepeatEnd" | Case_aux c "E_RepeatLoop"
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
unfold ex1_repeat.
constructor.
eapply E_Seq.
constructor.
reflexivity.
constructor.
reflexivity.
reflexivity.
Qed.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
Lemma hoare_repeat_simple : forall P b c,
{{P}} c {{P}} ->
{{P}} REPEAT c UNTIL b END {{fun st => P st /\ (bassn b st)}}.
Proof.
unfold hoare_triple.
intros.
remember (REPEAT c UNTIL b END) as loop.
induction H0; my_inversion Heqloop.
split. eapply H. apply H0. assumption. assumption.
apply IHceval2. reflexivity. eapply H. apply H0_. assumption.
(*
my_inversion H0.
split. eapply H. apply H5. assumption. assumption.
my_inversion H8.
split. eapply H. apply H5. eapply H. apply H4. assumption.
assumption.
split.
my_inversion H5.
*)
Qed.
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
Lemma hoare_repeat2 : forall P Q b c,
{{P}} c {{Q}} ->
{{fun st : state => Q st /\ ~(bassn b st)}} c {{Q}} ->
{{P}} REPEAT c UNTIL b END {{fun st => Q st /\ (bassn b st)}}.
Proof.
unfold hoare_triple, bassn.
intros.
my_inversion H1.
split. eapply H. apply H6. assumption. assumption.
Abort.
(*
remember (REPEAT c UNTIL b END) as loop.
induction H1; inversion Heqloop; subst; simpl.
split. eapply H. apply H1. assumption. assumption.
apply IHceval2. reflexivity.
remember (REPEAT c UNTIL b END) as loop.
induction H1; inversion Heqloop; subst; simpl.
split. eapply H. apply H1. assumption. assumption.
apply IHceval2. reflexivity.
split. apply IHceval2. reflexivity.
Qed.
*)
(*
{{P}} c {{Q}} ->
{{fun st : state => Q st /\ ~(bassn b st)}} c {{Q}} ->
{{P}} REPEAT c UNTIL b END {{fun st => Q st /\ (bassn b st)}}.
*)
Lemma hoare_repeat3 : forall P Q b c,
{{P}} c {{Q}} ->
{{fun st : state => Q st /\ ~(bassn b st)}} c {{Q}} ->
{{P}} REPEAT c UNTIL b END {{Q}}.
Proof.
unfold hoare_triple, bassn.
intros.
remember (REPEAT c UNTIL b END) as loop.
induction H1; inversion Heqloop; subst; simpl.
eapply H. apply H1. assumption.
apply IHceval2. reflexivity.
(*
my_inversion H1.
eapply H. apply H6. assumption.
eapply H0.
Qed.
*)
Abort.
Lemma hoare_repeat4 : forall P Q b c,
{{P}} c {{Q}} ->
{{Q}} c {{Q}} ->
{{P}} REPEAT c UNTIL b END {{Q}}.
Proof.
(*
unfold hoare_triple.
intros.
remember (REPEAT c UNTIL b END) as loop.
induction H1; inversion Heqloop; subst; simpl.
eapply H. apply H1. assumption.
eapply IHceval2. reflexivity.
Abort.
*)
unfold hoare_triple.
intros.
my_inversion H1. admit.
remember (REPEAT c UNTIL b END) as loop.
induction H9; inversion Heqloop; subst; simpl.
Abort.
Lemma hoare_repeat5 : forall P Q b c,
{{P}} c {{Q}} ->
{{Q}} c {{Q}} ->
{{P}} REPEAT c UNTIL b END {{fun st => Q st /\ (bassn b st)}}.
Proof.
unfold hoare_triple.
intros.
remember (REPEAT c UNTIL b END) as loop.
induction H1; my_inversion Heqloop.
admit.
apply H with (st':=st') in H2.
my_inversion H1. admit.
apply H with (st':=st') in H2.
unfold hoare_triple.
intros.
remember (REPEAT c UNTIL b END) as loop.
induction H1; my_inversion Heqloop.
Abort.
Lemma hoare_repeat : forall P Q b c,
{{P}} c {{Q}} ->
(fun st : state => Q st /\ ~(bassn b st)) ->> P ->
{{P}} REPEAT c UNTIL b END {{fun st : state => Q st /\ (bassn b st)}}.
Proof.
unfold hoare_triple. intros.
remember (REPEAT c UNTIL b END) as loop.
induction H1; my_inversion Heqloop.
split. eapply H. apply H1. assumption. assumption.
apply IHceval2. reflexivity.
apply H0. split. eapply H.
apply H1_. assumption.
apply bexp_eval_false in H1. assumption.
Qed.
(**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
I NEEDED TO RE DECLARE THIS!!!!!!!!!!!!!
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
**)
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
Example hoare_repeat_ex1 :
{{ fun st => (st X) > 0 }}
REPEAT
Y ::= (AId X);;
X ::= AMinus (AId X) (ANum 1)
UNTIL BEq (AId X) (ANum 0) END
{{ fun st => (st X) = 0 /\ (st Y) > 0 }}.
Proof.
(*
apply hoare_consequence_post with
(P:=(fun st : state => (st X) > 0))
(c:= REPEAT
Y ::= (AId X);;
X ::= AMinus (AId X) (ANum 1)
UNTIL BEq (AId X) (ANum 0) END)
(Q:=(fun st : state => (st X) = 0 /\ (st Y) > 0))
(Q':=(fun st : state => (st X) = 0 /\ (st Y) > 0 /\ (bassn (BEq (AId X) (ANum 0)) st)))
.
{{P}} REPEAT c UNTIL b END {{fun st : state => Q st /\ (bassn b st)}}.
({{P}} c {{Q'}}) ->
Q' ->> Q ->
{{P}} c {{Q}}
*)
eapply hoare_consequence_post.
apply hoare_repeat.
unfold hoare_triple; intros.
assert(G : st' Y > 0).
my_inversion H. my_inversion H4. my_inversion H6.
unfold update. simpl. assumption.
apply G.
unfold hoare_triple, bassn, assert_implies; intros.
my_inversion H. destruct (st X) eqn:e. contradiction H1. simpl. rewrite e. reflexivity.
omega.
unfold hoare_triple, bassn, assert_implies; intros.
my_inversion H. my_inversion H1. apply beq_nat_true in H2.
omega.
(*
remember (fun st : state => (st X) > 0) as P.
(* without specifying "state", it recognizes st as "id -> nat" *)
remember (fun st : state => (st Y) > 0) as Q.
remember (
Y ::= (AId X);;
X ::= AMinus (AId X) (ANum 1)) as c.
remember (BEq (AId X) (ANum 0)) as b.
eapply hoare_consequence_post.
assert(G : {{P}} c {{Q}}).
unfold hoare_triple. rewrite HeqP. rewrite HeqQ. rewrite Heqc.
intros. my_inversion H. my_inversion H4. my_inversion H6.
unfold update. simpl. assumption.
apply (hoare_repeat P Q b c).
apply hoare_repeat with (P:=P) (Q:=Q) (b:=b) (c:=c).
assert(G : {{P}} REPEAT c UNTIL b END {{fun st => Q st /\ (bassn b st)}}).
apply hoare_repeat2.
unfold hoare_triple. rewrite HeqP. rewrite HeqQ.
intros. rewrite Heqc in H. my_inversion H. my_inversion H4. my_inversion H6.
unfold update. simpl. assumption.
unfold hoare_triple, bassn, not. rewrite HeqQ. intros.
my_inversion H0.
my_inversion H. my_inversion H5. my_inversion H7.
unfold update. simpl.
destruct (st X) eqn:e. contradiction H2. simpl. rewrite e. reflexivity.
omega.
rewrite HeqQ in G.
(*
assert(H : forall P Q, P /\ Q -> Q /\ P). intros; inversion H; split; assumption. *)
assert(I : (fun st : state => st Y > 0 /\ bassn b st) ->>
(fun st : state => st X = 0 /\ st Y > 0)).
unfold bassn, assert_implies; simpl; intros. my_inversion H. my_inversion H1. apply beq_nat_true in H2. split; assumption.
remember (fun st : state => (st Y) > 0 /\ bassn b st) as R.
remember (REPEAT c UNTIL b END) as loop.
(*
apply G.
replace (fun st => st X = 0 /\ st Y > 0) with (fun st => st Y > 0 /\ bassn b st).
*)
(*
apply hoare_repeat2.
*)
unfold hoare_triple. intros st st'.
apply hoare_consequence_post with
(Q :=(fun st : state => st Y > 0 /\ bassn b st))
(Q':=(fun st : state => st X = 0 /\ st Y > 0))
(c := REPEAT c UNTIL b END)
(st := st)
(st' := st')
in G.
apply H in G.
eapply hoare_consequence_post in G.
eapply hoare_consequence_post.
apply hoare_repeat2.
eapply hoare_consequence_pre.
eapply hoare_consequence_post.
apply hoare_repeat.
eapply hoare_repeat.
eapply hoare_consequence_post.
eapply hoare_repeat.
eapply hoare_consequence_pre.
eapply hoare_consequence_post.
apply hoare_repeat.
*)
Qed.
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
fun st => forall n, Q (update st X n).
(*
fun st => Q st.
*)
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
unfold hoare_triple, havoc_pre.
intros.
my_inversion H.
apply H0.
Qed.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Complete List of Hoare Logic Rules *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(* $Date: 2014-02-27 16:56:35 -0500 (Thu, 27 Feb 2014) $ *)
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sine.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sine (
address,
clock,
q);
input [7:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../../Samples/Sine/sine8x8.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../../Samples/Sine/sine8x8.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../../Samples/Sine/sine8x8.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sine_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/* Top level module for button demo WITH debouncing
This uses button 1 of the keypad when installed correctly.
*/
module top (
// input hardware clock (12 MHz)
hwclk,
// LED
led1,
// Keypad lines
keypad_r1,
keypad_c1,
);
/* Clock input */
input hwclk;
/* LED outputs */
output led1;
/* Numpad I/O */
output keypad_r1=0;
input keypad_c1;
/* LED register */
reg ledval = 1'b0;
/* Numpad pull-up settings for columns:
PIN_TYPE: <output_type=0>_<input=1>
PULLUP: <enable=1>
PACKAGE_PIN: <user pad name>
D_IN_0: <internal pin wire (data in)>
*/
wire keypad_c1_din;
SB_IO #(
.PIN_TYPE(6'b0000_01),
.PULLUP(1'b1)
) keypad_c1_config (
.PACKAGE_PIN(keypad_c1),
.D_IN_0(keypad_c1_din)
);
/* Debouncing timer and period = 10 ms */
reg [31:0] debounce_timer = 32'b0;
parameter DEBOUNCE_PERIOD = 32'd120000;
reg debouncing = 1'b0;
/* LED Wiring */
assign led1=ledval;
/* Our high speed clock will deal with debounce timing */
always @ (posedge hwclk) begin
// check for button presses
if (~debouncing && ~keypad_c1_din) begin
ledval <= ~ledval;
debouncing <= 1;
// reset debouncing if button is held low
end else if (debouncing && ~keypad_c1_din) begin
debounce_timer <= 32'b0;
// or if it's high, increment debounce timer
end else if (debouncing && debounce_timer < DEBOUNCE_PERIOD) begin
debounce_timer <= debounce_timer + 1;
// finally, if it's high and timer expired, debouncing done!
end else if (debouncing) begin
debounce_timer <= 32'b0;
debouncing <= 1'b0;
end
end
endmodule |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : PIO_TO_CTRL.v
// Version : 1.7
//--
//-- Description: Turn-off Control Unit.
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module PIO_TO_CTRL (
clk,
rst_n,
req_compl_i,
compl_done_i,
cfg_to_turnoff_n,
cfg_turnoff_ok_n
);
input clk;
input rst_n;
input req_compl_i;
input compl_done_i;
input cfg_to_turnoff_n;
output cfg_turnoff_ok_n;
reg trn_pending;
reg cfg_turnoff_ok_n;
// * Check if completion is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
trn_pending <= 0;
end else begin
if (!trn_pending && req_compl_i)
trn_pending <= 1'b1;
else if (compl_done_i)
trn_pending <= 1'b0;
end
end
// * Turn-off OK if requested and no transaction is pending
always @ ( posedge clk or negedge rst_n ) begin
if (!rst_n ) begin
cfg_turnoff_ok_n <= 1'b1;
end else begin
if ( !cfg_to_turnoff_n && !trn_pending)
cfg_turnoff_ok_n <= 1'b0;
else
cfg_turnoff_ok_n <= 1'b1;
end
end
endmodule // PIO_TO_CTRL
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog-2001
`timescale 1 ns / 1 ps
/*
* Synchronizes switch and button inputs with a slow sampled shift register
*/
module debounce_switch #(
parameter WIDTH=1, // width of the input and output signals
parameter N=3, // length of shift register
parameter RATE=125000 // clock division factor
)(
input wire clk,
input wire rst,
input wire [WIDTH-1:0] in,
output wire [WIDTH-1:0] out
);
reg [23:0] cnt_reg = 24'd0;
reg [N-1:0] debounce_reg[WIDTH-1:0];
reg [WIDTH-1:0] state;
/*
* The synchronized output is the state register
*/
assign out = state;
integer k;
always @(posedge clk) begin
if (rst) begin
cnt_reg <= 0;
state <= 0;
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= 0;
end
end else begin
if (cnt_reg < RATE) begin
cnt_reg <= cnt_reg + 24'd1;
end else begin
cnt_reg <= 24'd0;
end
if (cnt_reg == 24'd0) begin
for (k = 0; k < WIDTH; k = k + 1) begin
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
end
end
for (k = 0; k < WIDTH; k = k + 1) begin
if (|debounce_reg[k] == 0) begin
state[k] <= 0;
end else if (&debounce_reg[k] == 1) begin
state[k] <= 1;
end else begin
state[k] <= state[k];
end
end
end
end
endmodule
|
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for dsp_iq_mult
*/
module test_dsp_iq_mult;
// Parameters
parameter WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [WIDTH-1:0] input_a_i_tdata = 0;
reg [WIDTH-1:0] input_a_q_tdata = 0;
reg input_a_tvalid = 0;
reg [WIDTH-1:0] input_b_i_tdata = 0;
reg [WIDTH-1:0] input_b_q_tdata = 0;
reg input_b_tvalid = 0;
reg output_tready = 0;
// Outputs
wire input_a_tready;
wire input_b_tready;
wire [(WIDTH*2)-1:0] output_i_tdata;
wire [(WIDTH*2)-1:0] output_q_tdata;
wire output_tvalid;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_a_i_tdata,
input_a_q_tdata,
input_a_tvalid,
input_b_i_tdata,
input_b_q_tdata,
input_b_tvalid,
output_tready);
$to_myhdl(input_a_tready,
input_b_tready,
output_i_tdata,
output_q_tdata,
output_tvalid);
// dump file
$dumpfile("test_dsp_iq_mult.lxt");
$dumpvars(0, test_dsp_iq_mult);
end
dsp_iq_mult #(
.WIDTH(WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
.input_a_i_tdata(input_a_i_tdata),
.input_a_q_tdata(input_a_q_tdata),
.input_a_tvalid(input_a_tvalid),
.input_a_tready(input_a_tready),
.input_b_i_tdata(input_b_i_tdata),
.input_b_q_tdata(input_b_q_tdata),
.input_b_tvalid(input_b_tvalid),
.input_b_tready(input_b_tready),
.output_i_tdata(output_i_tdata),
.output_q_tdata(output_q_tdata),
.output_tvalid(output_tvalid),
.output_tready(output_tready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_V
`define SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND
);
// Module ports
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
// Local signals
wire B2 nand0_out ;
wire B2 or0_out ;
wire nand1_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
nand nand1 (nand1_out_Y , nand0_out, or0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand1_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2AI_BEHAVIORAL_V |
module Tx8b10b #(
parameter FILL_WORD_RD0 = 10'b0011111010, // Send when no data present & RD=-1
parameter FILL_WORD_RD1 = 10'b1100000101, // Send when no data present & RD=1
parameter FILL_WORD_FLIP = 1'b1, // Flip status of Running Disparity when using fill word
parameter LOG2_DEPTH = 4 // log2(depth of FIFO buffer). Must be an integer.
)
(
input clk, // System clock
input rst, // Reset, synchronous and active high
input en, // Enable strobe for transmitting
input [7:0] dataIn, // Data to transmit
input writeStrobe, // Write data to transmit FIFO
output dataPresent, // FIFO has data still in it
output halfFull, // FIFO halfway full
output full, // FIFO is completely full. Don't write to it.
output tx // Transmit bit
);
wire [7:0] dataToEncode;
reg [3:0] outCounter;
reg [1:9] shiftOut;
reg readStrobe;
reg runDisparity6b; // 1=RD is +1, 0=RD is -1
reg runDisparity4b; // 1=RD is +1, 0=RD is -1
reg useAlt;
reg dataPresentLatch;
reg busy; // Only used when no FIFO is present
if (LOG2_DEPTH > 0) begin
Fifo #(
.WIDTH(8), ///< Width of data word
.LOG2_DEPTH(LOG2_DEPTH) ///< log2(depth of FIFO). Must be an integer
)
txFifo
(
// Inputs
.clk(clk), ///< System clock
.rst(rst), ///< Reset FIFO pointer
.write(writeStrobe), ///< Write strobe (1 clk)
.read(readStrobe), ///< Read strobe (1 clk)
.dataIn(dataIn), ///< [WIDTH-1:0] Data to write
// Outputs
.dataOut(dataToEncode), ///< [WIDTH-1:0] Data from FIFO
.dataPresent(dataPresent), ///< Data is present in FIFO
.halfFull(halfFull), ///< FIFO is half full
.full(full) ///< FIFO is full
);
end
else begin
assign dataToEncode = dataIn;
always @(posedge clk) begin
if (rst) begin
busy <= 1'b0;
end
else begin
busy <= busy ? (~readStrobe & busy) : writeStrobe;
end
end
end
assign tx = shiftOut[1];
initial begin
busy = 1'b0;
runDisparity6b = 1'b0;
runDisparity4b = 1'b0;
outCounter = 'd0;
shiftOut = 'd0;
useAlt = 1'b0;
dataPresentLatch = 1'b0;
end
always @(posedge clk) begin
if (rst) begin
runDisparity6b <= 1'b0;
runDisparity4b <= 1'b0;
outCounter <= 'd0;
shiftOut <= 'd0;
useAlt <= 1'b0;
dataPresentLatch <= 1'b0;
end
else if (en) begin
if (outCounter == 'd0) begin
readStrobe <= 1'b0;
outCounter <= 'd9;
shiftOut[7:9] <= {shiftOut[8:9], 1'b0};
// 5b/6b Encoder
useAlt <= 1'b0;
dataPresentLatch <= dataPresent;
if (dataPresent) begin
case ({dataToEncode[4:0], runDisparity6b})
6'b000000 : begin shiftOut[1:6] <= 6'b100111; runDisparity4b <= 1'b1; end
6'b000001 : begin shiftOut[1:6] <= 6'b011000; runDisparity4b <= 1'b0; end
6'b000010 : begin shiftOut[1:6] <= 6'b011101; runDisparity4b <= 1'b1; end
6'b000011 : begin shiftOut[1:6] <= 6'b100010; runDisparity4b <= 1'b0; end
6'b000100 : begin shiftOut[1:6] <= 6'b101101; runDisparity4b <= 1'b1; end
6'b000101 : begin shiftOut[1:6] <= 6'b010010; runDisparity4b <= 1'b0; end
6'b000110 : begin shiftOut[1:6] <= 6'b110001; runDisparity4b <= 1'b0; end
6'b000111 : begin shiftOut[1:6] <= 6'b110001; runDisparity4b <= 1'b1; end
6'b001000 : begin shiftOut[1:6] <= 6'b110101; runDisparity4b <= 1'b1; end
6'b001001 : begin shiftOut[1:6] <= 6'b001010; runDisparity4b <= 1'b0; end
6'b001010 : begin shiftOut[1:6] <= 6'b101001; runDisparity4b <= 1'b0; end
6'b001011 : begin shiftOut[1:6] <= 6'b101001; runDisparity4b <= 1'b1; end
6'b001100 : begin shiftOut[1:6] <= 6'b011001; runDisparity4b <= 1'b0; end
6'b001101 : begin shiftOut[1:6] <= 6'b011001; runDisparity4b <= 1'b1; end
6'b001110 : begin shiftOut[1:6] <= 6'b111000; runDisparity4b <= 1'b0; end
6'b001111 : begin shiftOut[1:6] <= 6'b000111; runDisparity4b <= 1'b1; end
6'b010000 : begin shiftOut[1:6] <= 6'b111001; runDisparity4b <= 1'b1; end
6'b010001 : begin shiftOut[1:6] <= 6'b000110; runDisparity4b <= 1'b0; end
6'b010010 : begin shiftOut[1:6] <= 6'b100101; runDisparity4b <= 1'b0; end
6'b010011 : begin shiftOut[1:6] <= 6'b100101; runDisparity4b <= 1'b1; end
6'b010100 : begin shiftOut[1:6] <= 6'b010101; runDisparity4b <= 1'b0; end
6'b010101 : begin shiftOut[1:6] <= 6'b010101; runDisparity4b <= 1'b1; end
6'b010110 : begin shiftOut[1:6] <= 6'b110100; runDisparity4b <= 1'b0; end
6'b010111 : begin shiftOut[1:6] <= 6'b110100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011000 : begin shiftOut[1:6] <= 6'b001101; runDisparity4b <= 1'b0; end
6'b011001 : begin shiftOut[1:6] <= 6'b001101; runDisparity4b <= 1'b1; end
6'b011010 : begin shiftOut[1:6] <= 6'b101100; runDisparity4b <= 1'b0; end
6'b011011 : begin shiftOut[1:6] <= 6'b101100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011100 : begin shiftOut[1:6] <= 6'b011100; runDisparity4b <= 1'b0; end
6'b011101 : begin shiftOut[1:6] <= 6'b011100; runDisparity4b <= 1'b1; useAlt <= 1'b1; end
6'b011110 : begin shiftOut[1:6] <= 6'b010111; runDisparity4b <= 1'b1; end
6'b011111 : begin shiftOut[1:6] <= 6'b101000; runDisparity4b <= 1'b0; end
6'b100000 : begin shiftOut[1:6] <= 6'b011011; runDisparity4b <= 1'b1; end
6'b100001 : begin shiftOut[1:6] <= 6'b100100; runDisparity4b <= 1'b0; end
6'b100010 : begin shiftOut[1:6] <= 6'b100011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b100011 : begin shiftOut[1:6] <= 6'b100011; runDisparity4b <= 1'b1; end
6'b100100 : begin shiftOut[1:6] <= 6'b010011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b100101 : begin shiftOut[1:6] <= 6'b010011; runDisparity4b <= 1'b1; end
6'b100110 : begin shiftOut[1:6] <= 6'b110010; runDisparity4b <= 1'b0; end
6'b100111 : begin shiftOut[1:6] <= 6'b110010; runDisparity4b <= 1'b1; end
6'b101000 : begin shiftOut[1:6] <= 6'b001011; runDisparity4b <= 1'b0; useAlt <= 1'b1; end
6'b101001 : begin shiftOut[1:6] <= 6'b001011; runDisparity4b <= 1'b1; end
6'b101010 : begin shiftOut[1:6] <= 6'b101010; runDisparity4b <= 1'b0; end
6'b101011 : begin shiftOut[1:6] <= 6'b101010; runDisparity4b <= 1'b1; end
6'b101100 : begin shiftOut[1:6] <= 6'b011010; runDisparity4b <= 1'b0; end
6'b101101 : begin shiftOut[1:6] <= 6'b011010; runDisparity4b <= 1'b1; end
6'b101110 : begin shiftOut[1:6] <= 6'b111010; runDisparity4b <= 1'b1; end
6'b101111 : begin shiftOut[1:6] <= 6'b000101; runDisparity4b <= 1'b0; end
6'b110000 : begin shiftOut[1:6] <= 6'b110011; runDisparity4b <= 1'b1; end
6'b110001 : begin shiftOut[1:6] <= 6'b001100; runDisparity4b <= 1'b0; end
6'b110010 : begin shiftOut[1:6] <= 6'b100110; runDisparity4b <= 1'b0; end
6'b110011 : begin shiftOut[1:6] <= 6'b100110; runDisparity4b <= 1'b1; end
6'b110100 : begin shiftOut[1:6] <= 6'b010110; runDisparity4b <= 1'b0; end
6'b110101 : begin shiftOut[1:6] <= 6'b010110; runDisparity4b <= 1'b1; end
6'b110110 : begin shiftOut[1:6] <= 6'b110110; runDisparity4b <= 1'b1; end
6'b110111 : begin shiftOut[1:6] <= 6'b001001; runDisparity4b <= 1'b0; end
6'b111000 : begin shiftOut[1:6] <= 6'b001110; runDisparity4b <= 1'b0; end
6'b111001 : begin shiftOut[1:6] <= 6'b001110; runDisparity4b <= 1'b1; end
6'b111010 : begin shiftOut[1:6] <= 6'b101110; runDisparity4b <= 1'b1; end
6'b111011 : begin shiftOut[1:6] <= 6'b010001; runDisparity4b <= 1'b0; end
6'b111100 : begin shiftOut[1:6] <= 6'b011110; runDisparity4b <= 1'b1; end
6'b111101 : begin shiftOut[1:6] <= 6'b100001; runDisparity4b <= 1'b0; end
6'b111110 : begin shiftOut[1:6] <= 6'b101011; runDisparity4b <= 1'b1; end
6'b111111 : begin shiftOut[1:6] <= 6'b010100; runDisparity4b <= 1'b0; end
endcase
end
else begin
shiftOut[1:6] <= (runDisparity4b) ? FILL_WORD_RD1[9:4] : FILL_WORD_RD0[9:4];
runDisparity6b <= runDisparity4b;
end
end
else if (outCounter == 'd9) begin
outCounter <= outCounter - 2'd1;
shiftOut[1:5] <= shiftOut[2:6];
// 3b/4b Encoder
if (dataPresentLatch) begin
readStrobe <= 1'b1;
case ({dataToEncode[7:5], runDisparity4b})
4'b0000 : begin shiftOut[6:9] <= 4'b1011; runDisparity6b <= 1'b1; end
4'b0001 : begin shiftOut[6:9] <= 4'b0100; runDisparity6b <= 1'b0; end
4'b0010 : begin shiftOut[6:9] <= 4'b1001; runDisparity6b <= 1'b0; end
4'b0011 : begin shiftOut[6:9] <= 4'b1001; runDisparity6b <= 1'b1; end
4'b0100 : begin shiftOut[6:9] <= 4'b0101; runDisparity6b <= 1'b0; end
4'b0101 : begin shiftOut[6:9] <= 4'b0101; runDisparity6b <= 1'b1; end
4'b0110 : begin shiftOut[6:9] <= 4'b1100; runDisparity6b <= 1'b0; end
4'b0111 : begin shiftOut[6:9] <= 4'b0011; runDisparity6b <= 1'b1; end
4'b1000 : begin shiftOut[6:9] <= 4'b1101; runDisparity6b <= 1'b1; end
4'b1001 : begin shiftOut[6:9] <= 4'b0010; runDisparity6b <= 1'b0; end
4'b1010 : begin shiftOut[6:9] <= 4'b1010; runDisparity6b <= 1'b0; end
4'b1011 : begin shiftOut[6:9] <= 4'b1010; runDisparity6b <= 1'b1; end
4'b1100 : begin shiftOut[6:9] <= 4'b0110; runDisparity6b <= 1'b0; end
4'b1101 : begin shiftOut[6:9] <= 4'b0110; runDisparity6b <= 1'b1; end
4'b1110 : begin shiftOut[6:9] <= (useAlt) ? 4'b0111 : 4'b1110; runDisparity6b <= 1'b1; end
4'b1111 : begin shiftOut[6:9] <= (useAlt) ? 4'b1000 : 4'b0001; runDisparity6b <= 1'b0; end
endcase
end
else begin
readStrobe <= 1'b0;
shiftOut[6:9] <= (runDisparity4b) ? FILL_WORD_RD1[3:0] : FILL_WORD_RD0[3:0];
runDisparity4b <= FILL_WORD_FLIP ^ runDisparity6b;
end
end
else begin
readStrobe <= 1'b0;
outCounter <= outCounter - 2'd1;
shiftOut <= {shiftOut[2:9], 1'b0};
end
end
else begin
readStrobe <= 1'b0;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Static Synchronous RAM 512-Deep by 1-Wide
// /___/ /\ Filename : RAM512X1S.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/02/12 - Initial version, from RAM256X1S
// 09/17/12 - 678488 fix file name
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM512X1S #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [511:0] INIT = 512'h0,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output O,
input [8:0] A,
input D,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM512X1S";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire D_in;
wire WCLK_in;
wire WE_in;
wire [8:0] A_in;
wire D_dly;
wire WCLK_dly;
wire WE_dly;
wire [8:0] A_dly;
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_TIMING
assign A_dly = A;
assign D_dly = D;
assign WCLK_dly = WCLK;
assign WE_dly = WE;
`endif
assign A_in = A_dly;
assign D_in = D_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((INIT < 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000) || (INIT > 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF))) begin
$display("Error: [Unisim %s-101] INIT attribute is set to %h. Legal values for this attribute are 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 to 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF. Instance: %m", MODULE_NAME, INIT);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_WCLK_INVERTED !== 1'b0) && (IS_WCLK_INVERTED !== 1'b1))) begin
$display("Error: [Unisim %s-102] IS_WCLK_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_WCLK_INVERTED);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
reg [511:0] mem;
assign O = mem[A_in];
initial
mem = INIT;
always @(posedge WCLK_in)
if (WE_in == 1'b1) mem[A_in] <= #100 D_in;
`ifdef XIL_TIMING
always @(notifier) mem[A_in] <= 1'bx;
`endif
`ifdef XIL_TIMING
specify
(WCLK => O) = (0:0:0, 0:0:0);
(A *> O) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, negedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (negedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (negedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (negedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (negedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (negedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (negedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (negedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (negedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (negedge WCLK, posedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (negedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, negedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, negedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, negedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, negedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, negedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, negedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, negedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, negedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (posedge WCLK, negedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge A[0] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[0]);
$setuphold (posedge WCLK, posedge A[1] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[1]);
$setuphold (posedge WCLK, posedge A[2] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[2]);
$setuphold (posedge WCLK, posedge A[3] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[3]);
$setuphold (posedge WCLK, posedge A[4] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[4]);
$setuphold (posedge WCLK, posedge A[5] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[5]);
$setuphold (posedge WCLK, posedge A[6] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[6]);
$setuphold (posedge WCLK, posedge A[7] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[7]);
$setuphold (posedge WCLK, posedge A[8] &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,A_dly[8]);
$setuphold (posedge WCLK, posedge D &&& WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,D_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,,,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
* Copyright (c) 2000 Steven Wilson ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test looks for != operation in a continuous assignment.
*/
module test;
integer a;
integer b;
wire result;
integer error;
assign result = (a != b);
initial
begin
a = 0;
b = 0;
error = 0;
#5 ;
if( result === 1'b1)
error =1;
a = 1;
#5;
if( result === 1'b0)
error =1;
b = 1;
#5 ;
if( result === 1'b1)
error =1;
a = 1002;
b = 1001;
#5 ;
if( result === 1'b0)
error =1;
a = 1001;
#5 ;
if( result === 1'b1)
error =1;
if(error === 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003,2004 Matt Ettus
// Copyright 2007 Free Software Foundation, Inc.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`define TX_IN_BAND
`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
`include "../../../firmware/include/fpga_regs_standard.v"
module usrp_inband_usb
(output MYSTERY_SIGNAL,
input master_clk,
input SCLK,
input SDI,
inout SDO,
input SEN_FPGA,
input FX2_1,
output FX2_2,
output FX2_3,
input wire [11:0] rx_a_a,
input wire [11:0] rx_b_a,
input wire [11:0] rx_a_b,
input wire [11:0] rx_b_b,
output wire [13:0] tx_a,
output wire [13:0] tx_b,
output wire TXSYNC_A,
output wire TXSYNC_B,
// USB interface
input usbclk,
input wire [2:0] usbctl,
output wire [1:0] usbrdy,
inout [15:0] usbdata, // NB Careful, inout
// These are the general purpose i/o's that go to the daughterboard slots
inout wire [15:0] io_tx_a,
inout wire [15:0] io_tx_b,
inout wire [15:0] io_rx_a,
inout wire [15:0] io_rx_b
);
wire [15:0] debugdata,debugctrl;
assign MYSTERY_SIGNAL = 1'b0;
wire clk64,clk128;
wire WR = usbctl[0];
wire RD = usbctl[1];
wire OE = usbctl[2];
wire have_space, have_pkt_rdy;
assign usbrdy[0] = have_space;
assign usbrdy[1] = have_pkt_rdy;
wire rx_overrun;
wire clear_status = FX2_1;
assign FX2_2 = rx_overrun;
assign FX2_3 = (tx_underrun == 0);
wire [15:0] usbdata_out;
wire [3:0] dac0mux,dac1mux,dac2mux,dac3mux;
wire tx_realsignals;
wire [3:0] rx_numchan;
wire [2:0] tx_numchan;
wire [7:0] interp_rate, decim_rate;
wire [15:0] tx_debugbus, rx_debugbus;
wire enable_tx, enable_rx;
wire tx_dsp_reset, rx_dsp_reset, tx_bus_reset, rx_bus_reset;
wire [7:0] settings;
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
// TX
wire [15:0] i_out_0,i_out_1,q_out_0,q_out_1;
wire [15:0] bb_tx_i0,bb_tx_q0,bb_tx_i1,bb_tx_q1; // bb_tx_i2,bb_tx_q2,bb_tx_i3,bb_tx_q3;
wire strobe_interp, tx_sample_strobe;
wire tx_empty;
wire serial_strobe;
wire [6:0] serial_addr;
wire [31:0] serial_data;
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
//Connection RX inband <-> TX inband
wire rx_WR;
wire [15:0] rx_databus;
wire rx_WR_done;
wire rx_WR_enabled;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
assign bb_tx_i0 = ch0tx;
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
wire [1:0] tx_underrun;
`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),
.tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.reg_addr(reg_addr),
.reg_data_out(reg_data_out),
.reg_data_in(reg_data_in),
.reg_io_enable(reg_io_enable),
.debugbus(rx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.stop(stop), .stop_time(stop_time));
`ifdef TX_DUAL
defparam tx_buffer.NUM_CHAN=2;
`endif
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
.channels({tx_numchan,1'b0}),
.tx_i_0(ch0tx),.tx_q_0(ch1tx),
.tx_i_1(ch2tx),.tx_q_1(ch3tx),
.tx_i_2(),.tx_q_2(),
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
tx_chain tx_chain_0
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
`else
assign i_out_0=16'd0;
assign q_out_0=16'd0;
`endif
`ifdef TX_EN_1
tx_chain tx_chain_1
( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
.interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
.interpolator_strobe(strobe_interp),.freq(),
.i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
`else
assign i_out_1=16'd0;
assign q_out_1=16'd0;
`endif
setting_reg #(`FR_TX_MUX)
sr_txmux(.clock(clk64),.reset(tx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),
.out({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
wire [15:0] tx_a_a = dac0mux[3] ? (dac0mux[1] ? (dac0mux[0] ? q_out_1 : i_out_1) : (dac0mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_b_a = dac1mux[3] ? (dac1mux[1] ? (dac1mux[0] ? q_out_1 : i_out_1) : (dac1mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_a_b = dac2mux[3] ? (dac2mux[1] ? (dac2mux[0] ? q_out_1 : i_out_1) : (dac2mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire [15:0] tx_b_b = dac3mux[3] ? (dac3mux[1] ? (dac3mux[0] ? q_out_1 : i_out_1) : (dac3mux[0] ? q_out_0 : i_out_0)) : 16'b0;
wire txsync = tx_sample_strobe;
assign TXSYNC_A = txsync;
assign TXSYNC_B = txsync;
assign tx_a = txsync ? tx_b_a[15:2] : tx_a_a[15:2];
assign tx_b = txsync ? tx_b_b[15:2] : tx_a_b[15:2];
`endif // `ifdef TX_ON
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Receive Side
`ifdef RX_ON
wire rx_sample_strobe,strobe_decim,hb_strobe;
wire [15:0] bb_rx_i0,bb_rx_q0,bb_rx_i1,bb_rx_q1,
bb_rx_i2,bb_rx_q2,bb_rx_i3,bb_rx_q3;
wire loopback = settings[0];
wire counter = settings[1];
always @(posedge clk64)
if(rx_dsp_reset)
debug_counter <= #1 16'd0;
else if(~enable_rx)
debug_counter <= #1 16'd0;
else if(hb_strobe)
debug_counter <=#1 debug_counter + 16'd2;
always @(posedge clk64)
if(strobe_interp)
begin
loopback_i_0 <= #1 ch0tx;
loopback_q_0 <= #1 ch1tx;
end
assign ch0rx = counter ? debug_counter : loopback ? loopback_i_0 : bb_rx_i0;
assign ch1rx = counter ? debug_counter + 16'd1 : loopback ? loopback_q_0 : bb_rx_q0;
assign ch2rx = bb_rx_i1;
assign ch3rx = bb_rx_q1;
assign ch4rx = bb_rx_i2;
assign ch5rx = bb_rx_q2;
assign ch6rx = bb_rx_i3;
assign ch7rx = bb_rx_q3;
wire [15:0] ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
adc_interface adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
.rssi_0(rssi_0),.rssi_1(rssi_1),.rssi_2(rssi_2),.rssi_3(rssi_3),
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
`ifdef RX_IN_BAND
rx_buffer_inband rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.rx_WR(rx_WR),
.rx_databus(rx_databus),
.rx_WR_done(rx_WR_done),
.rx_WR_enabled(rx_WR_enabled),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
.tx_underrun(tx_underrun));
`ifdef RX_DUAL
defparam rx_buffer.NUM_CHAN=2;
`endif
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
.channels(rx_numchan),
.ch_0(ch0rx),.ch_1(ch1rx),
.ch_2(ch2rx),.ch_3(ch3rx),
.ch_4(ch4rx),.ch_5(ch5rx),
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
`endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(hb_strobe),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc0_in_i),.q_in(ddc0_in_q),.i_out(bb_rx_i0),.q_out(bb_rx_q0),.debugdata(debugdata),.debugctrl(debugctrl));
`else
assign bb_rx_i0=16'd0;
assign bb_rx_q0=16'd0;
`endif
`ifdef RX_EN_1
rx_chain #(`FR_RX_FREQ_1,`FR_RX_PHASE_1) rx_chain_1
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc1_in_i),.q_in(ddc1_in_q),.i_out(bb_rx_i1),.q_out(bb_rx_q1));
`else
assign bb_rx_i1=16'd0;
assign bb_rx_q1=16'd0;
`endif
`ifdef RX_EN_2
rx_chain #(`FR_RX_FREQ_2,`FR_RX_PHASE_2) rx_chain_2
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc2_in_i),.q_in(ddc2_in_q),.i_out(bb_rx_i2),.q_out(bb_rx_q2));
`else
assign bb_rx_i2=16'd0;
assign bb_rx_q2=16'd0;
`endif
`ifdef RX_EN_3
rx_chain #(`FR_RX_FREQ_3,`FR_RX_PHASE_3) rx_chain_3
( .clock(clk64),.reset(1'b0),.enable(enable_rx),
.decim_rate(decim_rate),.sample_strobe(rx_sample_strobe),.decimator_strobe(strobe_decim),.hb_strobe(),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.i_in(ddc3_in_i),.q_in(ddc3_in_q),.i_out(bb_rx_i3),.q_out(bb_rx_q3));
`else
assign bb_rx_i3=16'd0;
assign bb_rx_q3=16'd0;
`endif
`endif // `ifdef RX_ON
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Control Functions
wire [31:0] capabilities;
assign capabilities[7] = `TX_CAP_HB;
assign capabilities[6:4] = `TX_CAP_NCHAN;
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
.serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
wire [6:0] reg_addr;
wire [31:0] reg_data_out;
wire [31:0] reg_data_in;
wire [1:0] reg_io_enable;
wire [31:0] rssi_threshhold;
wire [31:0] rssi_wait;
wire [6:0] addr_wr;
wire [31:0] data_wr;
wire strobe_wr;
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
assign serial_strobe = strobe_db | strobe_wr;
assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
assign serial_data = (strobe_db)? (data_db) : (data_wr);
//assign serial_strobe = strobe_wr;
//assign serial_data = data_wr;
//assign serial_addr = addr_wr;
register_io register_control
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
.dataout(reg_data_out), .addr_wr(addr_wr), .data_wr(data_wr), .strobe_wr(strobe_wr),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
.rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.debug_en(debug_en), .misc(settings),
.txmux({dac3mux,dac2mux,dac1mux,dac0mux,tx_realsignals,tx_numchan}));
//implementing freeze mode
reg [15:0] timestop;
wire stop;
wire [15:0] stop_time;
assign clk64 = (timestop == 0) ? master_clk : 0;
always @(posedge master_clk)
if (timestop[15:0] != 0)
timestop <= timestop - 16'd1;
else if (stop)
timestop <= stop_time;
wire [15:0] reg_0,reg_1,reg_2,reg_3;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.tx_bus_reset(tx_bus_reset),.rx_bus_reset(rx_bus_reset),
.tx_dsp_reset(tx_dsp_reset),.rx_dsp_reset(rx_dsp_reset),
.enable_tx(enable_tx),.enable_rx(enable_rx),
.interp_rate(interp_rate),.decim_rate(decim_rate),
.tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
.debug_0(rx_debugbus),.debug_1(ddc0_in_i),
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,tx_underrun,rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
io_pins io_pins
(.io_0(io_tx_a),.io_1(io_rx_a),.io_2(io_tx_b),.io_3(io_rx_b),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3),
.clock(clk64),.rx_reset(rx_dsp_reset),.tx_reset(tx_dsp_reset),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe));
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Misc Settings
setting_reg #(`FR_MODE) sr_misc(.clock(clk64),.reset(rx_dsp_reset),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(settings));
endmodule // usrp_inband_usb
|
// $Id: c_diag_op.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
//==============================================================================
// perform binary operation across diagonals of a matrix
//==============================================================================
module c_diag_op
(data_in, data_out);
// input width
parameter width = 1;
// select operator
parameter op = `BINARY_OP_XOR;
// vector of inputs
input [0:width*width-1] data_in;
// result
output [0:width-1] data_out;
wire [0:width-1] data_out;
generate
genvar diag;
for(diag = 0; diag < width; diag = diag + 1)
begin:diags
wire [0:width-1] diag_elems;
genvar row;
for(row = 0; row < width; row = row + 1)
begin:rows
assign diag_elems[row]
= data_in[row*width+(width+diag-row)%width];
end
wire op_elem;
c_binary_op
#(.num_ports(width),
.width(1),
.op(op))
op_elem_bop
(.data_in(diag_elems),
.data_out(op_elem));
assign data_out[diag] = op_elem;
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 26 18:58:50 2016
/////////////////////////////////////////////////////////////
module Sgf_Multiplication_SW54 ( clk, rst, load_b_i, Data_A_i, Data_B_i,
sgf_result_o );
input [53:0] Data_A_i;
input [53:0] Data_B_i;
output [107:0] sgf_result_o;
input clk, rst, load_b_i;
wire n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
GEN1_middle_N55, GEN1_middle_N54, GEN1_middle_N53, GEN1_middle_N52,
GEN1_middle_N51, GEN1_middle_N50, GEN1_middle_N49, GEN1_middle_N48,
GEN1_middle_N47, GEN1_middle_N46, GEN1_middle_N45, GEN1_middle_N44,
GEN1_middle_N43, GEN1_middle_N42, GEN1_middle_N41, GEN1_middle_N40,
GEN1_middle_N39, GEN1_middle_N38, GEN1_middle_N37, GEN1_middle_N36,
GEN1_middle_N35, GEN1_middle_N34, GEN1_middle_N33, GEN1_middle_N32,
GEN1_middle_N31, GEN1_middle_N30, GEN1_middle_N29, GEN1_middle_N28,
GEN1_middle_N27, GEN1_middle_N26, GEN1_middle_N25, GEN1_middle_N24,
GEN1_middle_N23, GEN1_middle_N22, GEN1_middle_N21, GEN1_middle_N20,
GEN1_middle_N19, GEN1_middle_N18, GEN1_middle_N17, GEN1_middle_N16,
GEN1_middle_N15, GEN1_middle_N14, GEN1_middle_N13, GEN1_middle_N12,
GEN1_middle_N11, GEN1_middle_N10, GEN1_middle_N9, GEN1_middle_N8,
GEN1_middle_N7, GEN1_middle_N6, GEN1_middle_N5, GEN1_middle_N4,
GEN1_middle_N3, GEN1_middle_N2, GEN1_middle_N1, GEN1_middle_N0,
GEN1_right_N53, GEN1_right_N52, GEN1_right_N51, GEN1_right_N50,
GEN1_right_N49, GEN1_right_N48, GEN1_right_N47, GEN1_right_N46,
GEN1_right_N45, GEN1_right_N44, GEN1_right_N43, GEN1_right_N42,
GEN1_right_N41, GEN1_right_N40, GEN1_right_N39, GEN1_right_N38,
GEN1_right_N37, GEN1_right_N36, GEN1_right_N35, GEN1_right_N34,
GEN1_right_N33, GEN1_right_N32, GEN1_right_N31, GEN1_right_N30,
GEN1_right_N29, GEN1_right_N28, GEN1_right_N27, GEN1_right_N26,
GEN1_right_N25, GEN1_right_N24, GEN1_right_N23, GEN1_right_N22,
GEN1_right_N21, GEN1_right_N20, GEN1_right_N19, GEN1_right_N18,
GEN1_right_N17, GEN1_right_N16, GEN1_right_N15, GEN1_right_N14,
GEN1_right_N13, GEN1_right_N12, GEN1_right_N11, GEN1_right_N10,
GEN1_right_N9, GEN1_right_N8, GEN1_right_N7, GEN1_right_N6,
GEN1_right_N5, GEN1_right_N4, GEN1_right_N3, GEN1_right_N2,
GEN1_right_N1, GEN1_right_N0, GEN1_left_N53, GEN1_left_N52,
GEN1_left_N51, GEN1_left_N50, GEN1_left_N49, GEN1_left_N48,
GEN1_left_N47, GEN1_left_N46, GEN1_left_N45, GEN1_left_N44,
GEN1_left_N43, GEN1_left_N42, GEN1_left_N41, GEN1_left_N40,
GEN1_left_N39, GEN1_left_N38, GEN1_left_N37, GEN1_left_N36,
GEN1_left_N35, GEN1_left_N34, GEN1_left_N33, GEN1_left_N32,
GEN1_left_N31, GEN1_left_N30, GEN1_left_N29, GEN1_left_N28,
GEN1_left_N27, GEN1_left_N26, GEN1_left_N25, GEN1_left_N24,
GEN1_left_N23, GEN1_left_N22, GEN1_left_N21, GEN1_left_N20,
GEN1_left_N19, GEN1_left_N18, GEN1_left_N17, GEN1_left_N16,
GEN1_left_N15, GEN1_left_N14, GEN1_left_N13, GEN1_left_N12,
GEN1_left_N11, GEN1_left_N10, GEN1_left_N9, GEN1_left_N8,
GEN1_left_N7, GEN1_left_N6, GEN1_left_N5, GEN1_left_N4, GEN1_left_N3,
GEN1_left_N2, GEN1_left_N1, GEN1_left_N0, GEN1_Final_add_x_1_n388,
GEN1_Final_add_x_1_n386, GEN1_Final_add_x_1_n385,
GEN1_Final_add_x_1_n382, GEN1_Final_add_x_1_n381,
GEN1_Final_add_x_1_n379, GEN1_Final_add_x_1_n378,
GEN1_Final_add_x_1_n373, GEN1_Final_add_x_1_n372,
GEN1_Final_add_x_1_n368, GEN1_Final_add_x_1_n367,
GEN1_Final_add_x_1_n363, GEN1_Final_add_x_1_n362,
GEN1_Final_add_x_1_n360, GEN1_Final_add_x_1_n359,
GEN1_Final_add_x_1_n352, GEN1_Final_add_x_1_n351,
GEN1_Final_add_x_1_n349, GEN1_Final_add_x_1_n348,
GEN1_Final_add_x_1_n342, GEN1_Final_add_x_1_n341,
GEN1_Final_add_x_1_n337, GEN1_Final_add_x_1_n336,
GEN1_Final_add_x_1_n329, GEN1_Final_add_x_1_n328,
GEN1_Final_add_x_1_n324, GEN1_Final_add_x_1_n323,
GEN1_Final_add_x_1_n317, GEN1_Final_add_x_1_n316,
GEN1_Final_add_x_1_n312, GEN1_Final_add_x_1_n311,
GEN1_Final_add_x_1_n302, GEN1_Final_add_x_1_n301,
GEN1_Final_add_x_1_n297, GEN1_Final_add_x_1_n296,
GEN1_Final_add_x_1_n292, GEN1_Final_add_x_1_n291,
GEN1_Final_add_x_1_n289, GEN1_Final_add_x_1_n288,
GEN1_Final_add_x_1_n279, GEN1_Final_add_x_1_n278,
GEN1_Final_add_x_1_n276, GEN1_Final_add_x_1_n275,
GEN1_Final_add_x_1_n271, GEN1_Final_add_x_1_n270,
GEN1_Final_add_x_1_n268, GEN1_Final_add_x_1_n267,
GEN1_Final_add_x_1_n258, GEN1_Final_add_x_1_n257,
GEN1_Final_add_x_1_n255, GEN1_Final_add_x_1_n254,
GEN1_Final_add_x_1_n250, GEN1_Final_add_x_1_n249,
GEN1_Final_add_x_1_n247, GEN1_Final_add_x_1_n246,
GEN1_Final_add_x_1_n237, GEN1_Final_add_x_1_n236,
GEN1_Final_add_x_1_n234, GEN1_Final_add_x_1_n233,
GEN1_Final_add_x_1_n229, GEN1_Final_add_x_1_n228,
GEN1_Final_add_x_1_n226, GEN1_Final_add_x_1_n225,
GEN1_Final_add_x_1_n214, GEN1_Final_add_x_1_n213,
GEN1_Final_add_x_1_n211, GEN1_Final_add_x_1_n210,
GEN1_Final_add_x_1_n204, GEN1_Final_add_x_1_n203,
GEN1_Final_add_x_1_n199, GEN1_Final_add_x_1_n198,
GEN1_Final_add_x_1_n191, GEN1_Final_add_x_1_n190,
GEN1_Final_add_x_1_n186, GEN1_Final_add_x_1_n185,
GEN1_Final_add_x_1_n179, GEN1_Final_add_x_1_n178,
GEN1_Final_add_x_1_n174, GEN1_Final_add_x_1_n173,
GEN1_Final_add_x_1_n162, GEN1_Final_add_x_1_n161,
GEN1_Final_add_x_1_n157, GEN1_Final_add_x_1_n156,
GEN1_Final_add_x_1_n150, GEN1_Final_add_x_1_n149,
GEN1_Final_add_x_1_n145, GEN1_Final_add_x_1_n144,
GEN1_Final_add_x_1_n137, GEN1_Final_add_x_1_n136,
GEN1_Final_add_x_1_n132, GEN1_Final_add_x_1_n131,
GEN1_Final_add_x_1_n125, GEN1_Final_add_x_1_n124,
GEN1_Final_add_x_1_n120, GEN1_Final_add_x_1_n119,
GEN1_Final_add_x_1_n108, GEN1_Final_add_x_1_n103,
GEN1_Final_add_x_1_n96, GEN1_Final_add_x_1_n95,
GEN1_Final_add_x_1_n89, GEN1_Final_add_x_1_n81,
GEN1_Final_add_x_1_n80, GEN1_Final_add_x_1_n79,
GEN1_Final_add_x_1_n78, GEN1_Final_add_x_1_n77,
GEN1_Final_add_x_1_n76, GEN1_Final_add_x_1_n75,
GEN1_Final_add_x_1_n74, GEN1_Final_add_x_1_n73,
GEN1_Final_add_x_1_n72, GEN1_Final_add_x_1_n71,
GEN1_Final_add_x_1_n70, GEN1_Final_add_x_1_n69,
GEN1_Final_add_x_1_n68, GEN1_Final_add_x_1_n67,
GEN1_Final_add_x_1_n66, GEN1_Final_add_x_1_n65,
GEN1_Final_add_x_1_n64, GEN1_Final_add_x_1_n63,
GEN1_Final_add_x_1_n62, GEN1_Final_add_x_1_n61,
GEN1_Final_add_x_1_n60, GEN1_Final_add_x_1_n59,
GEN1_Final_add_x_1_n58, GEN1_Final_add_x_1_n57,
GEN1_Final_add_x_1_n56, GEN1_Final_add_x_1_n55,
GEN1_Final_add_x_1_n54, GEN1_Final_add_x_1_n53, n112, n113, n114,
n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125,
n126, n127, n128, n129, n130, n131, n132, n133, n134, n135, n136,
n137, n138, n139, n140, n141, n142, n143, n144, n145, n146, n147,
n148, n149, n150, n151, n152, n153, n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163, n164, n165, n166, n167, n168, n169,
n170, n171, n172, n173, n174, n175, n176, n177, n178, n179, n180,
n181, n182, n183, n184, n185, n186, n187, n188, n189, n190, n191,
n192, n193, n194, n195, n196, n197, n198, n199, n200, n201, n202,
n203, n204, n205, n206, n207, n208, n209, n210, n211, n212, n213,
n214, n215, n216, n217, n218, n219, n220, n221, n222, n223, n224,
n225, n226, n227, n228, n229, n230, n231, n232, n233, n234, n235,
n236, n237, n238, n239, n240, n241, n242, n243, n244, n245, n246,
n247, n248, n249, n250, n251, n252, n253, n254, n255, n256, n257,
n258, n259, n260, n261, n262, n263, n264, n265, n266, n267, n268,
n269, n270, n271, n272, n273, n274, n275, n276, n277, n278, n279,
n280, n281, n282, n283, n284, n285, n286, n287, n288, n289, n290,
n291, n292, n293, n294, n295, n296, n297, n298, n299, n300, n301,
n302, n303, n304, n305, n306, n307, n308, n309, n310, n311, n312,
n313, n314, n315, n316, n317, n318, n319, n320, n321, n322, n323,
n324, n325, n326, n327, n328, n329, n330, n331, n332, n333, n334,
n335, n336, n337, n338, n339, n340, n341, n342, n343, n344, n345,
n346, n347, n348, n349, n350, n351, n352, n353, n354, n355, n356,
n357, n358, n359, n360, n361, n362, n363, n364, n365, n366, n367,
n368, n369, n370, n371, n372, n373, n374, n375, n376, n377, n378,
n379, n380, n381, n382, n383, n384, n385, n386, n387, n388, n389,
n390, n391, n392, n393, n394, n395, n396, n397, n398, n399, n400,
n401, n402, n403, n404, n405, n406, n407, n408, n409, n410, n411,
n412, n413, n414, n415, n416, n417, n418, n419, n420, n421, n422,
n423, n424, n425, n426, n427, n428, n429, n430, n431, n432, n433,
n434, n435, n436, n437, n438, n439, n440, n441, n442, n443, n444,
n445, n446, n447, n448, n449, n450, n451, n452, n453, n454, n455,
n456, n457, n458, n459, n460, n461, n462, n463, n464, n465, n466,
n467, n468, n469, n470, n471, n472, n473, n474, n475, n476, n477,
n478, n479, n480, n481, n482, n483, n484, n485, n486, n487, n488,
n489, n490, n491, n492, n493, n494, n495, n496, n497, n498, n499,
n500, n501, n502, n503, n504, n505, n506, n507, n508, n509, n510,
n511, n512, n513, n514, n515, n516, n517, n518, n519, n520, n521,
n522, n523, n524, n525, n526, n527, n528, n529, n530, n531, n532,
n533, n534, n535, n536, n537, n538, n539, n540, n541, n542, n543,
n544, n545, n546, n547, n548, n549, n550, n551, n552, n553, n554,
n555, n556, n557, n558, n559, n560, n561, n562, n563, n564, n565,
n566, n567, n568, n569, n570, n571, n572, n573, n574, n575, n576,
n577, n578, n579, n580, n581, n582, n583, n584, n585, n586, n587,
n588, n589, n590, n591, n592, n593, n594, n595, n596, n597, n598,
n599, n600, n601, n602, n603, n604, n605, n606, n607, n608, n609,
n610, n611, n612, n613, n614, n615, n616, n617, n618, n619, n620,
n621, n622, n623, n624, n625, n626, n627, n628, n629, n630, n631,
n632, n633, n634, n635, n636, n637, n638, n639, n640, n641, n642,
n643, n644, n645, n646, n647, n648, n649, n650, n651, n652, n653,
n654, n655, n656, n657, n658, n659, n660, n661, n662, n663, n664,
n665, n666, n667, n668, n669, n670, n671, n672, n673, n674, n675,
n676, n677, n678, n679, n680, n681, n682, n683, n684, n685, n686,
n687, n688, n689, n690, n691, n692, n693, n694, n695, n696, n697,
n698, n699, n700, n701, n702, n703, n704, n705, n706, n707, n708,
n709, n710, n711, n712, n713, n714, n715, n716, n717, n718, n719,
n720, n721, n722, n723, n724, n725, n726, n727, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n898, n899, n900, n901, n902, n903, n904, n905, n906,
n907, n908, n909, n910, n911, n912, n913, n914, n915, n916, n917,
n918, n919, n920, n921, n922, n923, n924, n925, n926, n927, n928,
n929, n930, n931, n932, n933, n934, n935, n936, n937, n938, n939,
n940, n941, n942, n943, n944, n945, n946, n947, n948, n949, n950,
n951, n952, n953, n954, n955, n956, n957, n958, n959, n960, n961,
n962, n963, n964, n965, n966, n967, n968, n969, n970, n971, n972,
n973, n974, n975, n976, n977, n978, n979, n980, n981, n982, n983,
n984, n985, n986, n987, n988, n989, n990, n991, n992, n993, n994,
n995, n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004,
n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014,
n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024,
n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034,
n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044,
n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054,
n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064,
n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074,
n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084,
n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094,
n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104,
n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114,
n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124,
n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134,
n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144,
n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154,
n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164,
n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174,
n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214,
n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224,
n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234,
n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244,
n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254,
n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264,
n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274,
n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284,
n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294,
n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304,
n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314,
n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324,
n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334,
n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344,
n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354,
n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364,
n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374,
n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384,
n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394,
n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404,
n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414,
n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424,
n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434,
n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444,
n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454,
n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464,
n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474,
n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484,
n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494,
n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504,
n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514,
n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554,
n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564,
n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574,
n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584,
n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594,
n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604,
n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614,
n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624,
n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634,
n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644,
n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654,
n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664,
n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674,
n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684,
n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694,
n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704,
n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714,
n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724,
n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734,
n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744,
n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754,
n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764,
n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774,
n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784,
n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794,
n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804,
n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814,
n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824,
n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834,
n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844,
n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854,
n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864,
n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874,
n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884,
n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894,
n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904,
n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914,
n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924,
n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934,
n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944,
n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954,
n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964,
n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974,
n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984,
n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994,
n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004,
n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014,
n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024,
n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034,
n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044,
n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054,
n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064,
n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074,
n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084,
n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094,
n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104,
n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114,
n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124,
n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134,
n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154,
n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164,
n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174,
n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184,
n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194,
n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204,
n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214,
n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224,
n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234,
n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244,
n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254,
n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264,
n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274,
n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284,
n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294,
n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304,
n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314,
n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324,
n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334,
n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344,
n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354,
n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364,
n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374,
n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384,
n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394,
n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404,
n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414,
n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424,
n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434,
n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444,
n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454,
n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464,
n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474,
n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484,
n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494,
n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504,
n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514,
n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524,
n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534,
n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544,
n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554,
n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564,
n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574,
n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584,
n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594,
n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604,
n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614,
n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624,
n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634,
n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644,
n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654,
n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664,
n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674,
n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684,
n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694,
n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704,
n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714,
n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724,
n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784,
n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794,
n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804,
n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814,
n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824,
n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834,
n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844,
n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854,
n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864,
n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874,
n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884,
n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894,
n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904,
n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914,
n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924,
n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934,
n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944,
n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954,
n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964,
n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974,
n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984,
n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994,
n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004,
n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014,
n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024,
n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034,
n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044,
n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054,
n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064,
n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074,
n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084,
n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094,
n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104,
n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114,
n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124,
n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134,
n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144,
n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154,
n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164,
n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174,
n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184,
n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194,
n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204,
n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214,
n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224,
n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234,
n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244,
n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254,
n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264,
n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274,
n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284,
n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294,
n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304,
n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314,
n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324,
n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334,
n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344,
n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354,
n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364,
n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374,
n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384,
n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394,
n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404,
n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414,
n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424,
n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434,
n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444,
n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454,
n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464,
n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474,
n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484,
n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494,
n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504,
n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514,
n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524,
n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534,
n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544,
n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554,
n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564,
n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574,
n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584,
n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594,
n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604,
n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614,
n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624,
n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634,
n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644,
n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654,
n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664,
n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674,
n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684,
n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694,
n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704,
n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714,
n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724,
n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734,
n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744,
n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754,
n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764,
n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774,
n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784,
n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794,
n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804,
n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814,
n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824,
n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834,
n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844,
n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854,
n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864,
n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874,
n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884,
n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894,
n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904,
n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914,
n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924,
n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934,
n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944,
n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954,
n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964,
n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974,
n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984,
n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994,
n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004,
n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014,
n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024,
n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034,
n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044,
n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054,
n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064,
n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074,
n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084,
n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094,
n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104,
n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114,
n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124,
n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134,
n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144,
n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154,
n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164,
n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174,
n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184,
n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194,
n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204,
n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214,
n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224,
n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234,
n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244,
n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254,
n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264,
n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274,
n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284,
n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294,
n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304,
n5305, n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314,
n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324,
n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334,
n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344,
n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354,
n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364,
n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374,
n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384,
n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394,
n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404,
n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414,
n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424,
n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434,
n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444,
n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454,
n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464,
n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474,
n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484,
n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494,
n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504,
n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514,
n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524,
n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534,
n5535, n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544,
n5545, n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554,
n5555, n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564,
n5565, n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574,
n5575, n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584,
n5585, n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594,
n5595, n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604,
n5605, n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614,
n5615, n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624,
n5625, n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634,
n5635, n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644,
n5645, n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654,
n5655, n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664,
n5665, n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674,
n5675, n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684,
n5685, n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694,
n5695, n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704,
n5705, n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714,
n5715, n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724,
n5725, n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734,
n5735, n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744,
n5745, n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754,
n5755, n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764,
n5765, n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774,
n5775, n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784,
n5785, n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794,
n5795, n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804,
n5805, n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814,
n5815, n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824,
n5825, n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834,
n5835, n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844,
n5845, n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854,
n5855, n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864,
n5865, n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874,
n5875, n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884,
n5885, n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894,
n5895, n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904,
n5905, n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914,
n5915, n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924,
n5925, n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934,
n5935, n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944,
n5945, n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954,
n5955, n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964,
n5965, n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974,
n5975, n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984,
n5985, n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994,
n5995, n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004,
n6005, n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014,
n6015, n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024,
n6025, n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034,
n6035, n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044,
n6045, n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054,
n6055, n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064,
n6065, n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074,
n6075, n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084,
n6085, n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094,
n6095, n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104,
n6105, n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114,
n6115, n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124,
n6125, n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134,
n6135, n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144,
n6145, n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154,
n6155, n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164,
n6165, n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174,
n6175, n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184,
n6185, n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194,
n6195, n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204,
n6205, n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214,
n6215, n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224,
n6225, n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234,
n6235, n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244,
n6245, n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254,
n6255, n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264,
n6265, n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274,
n6275, n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284,
n6285, n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294,
n6295, n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304,
n6305, n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314,
n6315, n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324,
n6325, n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334,
n6335, n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344,
n6345, n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354,
n6355, n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364,
n6365, n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374,
n6375, n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384,
n6385, n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394,
n6395, n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404,
n6405, n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414,
n6415, n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424,
n6425, n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434,
n6435, n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444,
n6445, n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454,
n6455, n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464,
n6465, n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474,
n6475, n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484,
n6485, n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494,
n6495, n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504,
n6505, n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514,
n6515, n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524,
n6525, n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534,
n6535, n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544,
n6545, n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554,
n6555, n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564,
n6565, n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574,
n6575, n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584,
n6585, n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594,
n6595, n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604,
n6605, n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614,
n6615, n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624,
n6625, n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634,
n6635, n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644,
n6645, n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654,
n6655, n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664,
n6665, n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674,
n6675, n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684,
n6685, n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694,
n6695, n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704,
n6705, n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714,
n6715, n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724,
n6725, n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734,
n6735, n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744,
n6745, n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754,
n6755, n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764,
n6765, n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774,
n6775, n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784,
n6785, n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794,
n6795, n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804,
n6805, n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814,
n6815, n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824,
n6825, n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834,
n6835, n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844,
n6845, n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854,
n6855, n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864,
n6865, n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874,
n6875, n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884,
n6885, n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894,
n6895, n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904,
n6905, n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914,
n6915, n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924,
n6925, n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934,
n6935, n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944,
n6945, n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954,
n6955, n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964,
n6965, n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974,
n6975, n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984,
n6985, n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994,
n6995, n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004,
n7005, n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014,
n7015, n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024,
n7025, n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034,
n7035, n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044,
n7045, n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054,
n7055, n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064,
n7065, n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074,
n7075, n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084,
n7085, n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094,
n7095, n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104,
n7105, n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114,
n7115, n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124,
n7125, n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134,
n7135, n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144,
n7145, n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154,
n7155, n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164,
n7165, n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174,
n7175, n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184,
n7185, n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194,
n7195, n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204,
n7205, n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214,
n7215, n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224,
n7225, n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234,
n7235, n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244,
n7245, n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254,
n7255, n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264,
n7265, n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274,
n7275, n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284,
n7285, n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294,
n7295, n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304,
n7305, n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314,
n7315, n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324,
n7325, n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334,
n7335, n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344,
n7345, n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354,
n7355, n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364,
n7365, n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374,
n7375, n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384,
n7385, n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394,
n7395, n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404,
n7405, n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414,
n7415, n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424,
n7425, n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434,
n7435, n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444,
n7445, n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454,
n7455, n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464,
n7465, n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474,
n7475, n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484,
n7485, n7486, n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494,
n7495, n7496, n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504,
n7505, n7506, n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514,
n7515, n7516, n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524,
n7525, n7526, n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534,
n7535, n7536, n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544,
n7545, n7546, n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554,
n7555, n7556, n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564,
n7565, n7566, n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574,
n7575, n7576, n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584,
n7585, n7586, n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594,
n7595, n7596, n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604,
n7605, n7606, n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614,
n7615, n7616, n7617, n7618, n7619, n7620, n7621, n7622, n7623, n7624,
n7625, n7626, n7627, n7628, n7629, n7630, n7631, n7632, n7633, n7634,
n7635, n7636, n7637, n7638, n7639, n7640, n7641, n7642, n7643, n7644,
n7645, n7646, n7647, n7648, n7649, n7650, n7651, n7652, n7653, n7654,
n7655, n7656, n7657, n7658, n7659, n7660, n7661, n7662, n7663, n7664,
n7665, n7666, n7667, n7668, n7669, n7670, n7671, n7672, n7673, n7674,
n7675, n7676, n7677, n7678, n7679, n7680, n7681, n7682, n7683, n7684,
n7685, n7686, n7687, n7688, n7689, n7690, n7691, n7692, n7693, n7694,
n7695, n7696, n7697, n7698, n7699, n7700, n7701, n7702, n7703, n7704,
n7705, n7706, n7707, n7708, n7709, n7710, n7711, n7712, n7713, n7714,
n7715, n7716, n7717, n7718, n7719, n7720, n7721, n7722, n7723, n7724,
n7725, n7726, n7727, n7728, n7729, n7730, n7731, n7732, n7733, n7734,
n7735, n7736, n7737, n7738, n7739, n7740, n7741, n7742, n7743, n7744,
n7745, n7746, n7747, n7748, n7749, n7750, n7751, n7752, n7753, n7754,
n7755, n7756, n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764,
n7765, n7766, n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774,
n7775, n7776, n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784,
n7785, n7786, n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794,
n7795, n7796, n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7804,
n7805, n7806, n7807, n7808, n7809, n7810, n7811, n7812, n7813, n7814,
n7815, n7816, n7817, n7818, n7819, n7820, n7821, n7822, n7823, n7824,
n7825, n7826, n7827, n7828, n7829, n7830, n7831, n7832, n7833, n7834,
n7835, n7836, n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844,
n7845, n7846, n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854,
n7855, n7856, n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864,
n7865, n7866, n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874,
n7875, n7876, n7877, n7878, n7879, n7880, n7881, n7882, n7883, n7884,
n7885, n7886, n7887, n7888, n7889, n7890, n7891, n7892, n7893, n7894,
n7895, n7896, n7897, n7898, n7899, n7900, n7901, n7902, n7903, n7904,
n7905, n7906, n7907, n7908, n7909, n7910, n7911, n7912, n7913, n7914,
n7915, n7916, n7917, n7918, n7919, n7920, n7921, n7922, n7923, n7924,
n7925, n7926, n7927, n7928, n7929, n7930, n7931, n7932, n7933, n7934,
n7935, n7936, n7937, n7938, n7939, n7940, n7941, n7942, n7943, n7944,
n7945, n7946, n7947, n7948, n7949, n7950, n7951, n7952, n7953, n7954,
n7955, n7956, n7957, n7958, n7959, n7960, n7961, n7962, n7963, n7964,
n7965, n7966, n7967, n7968, n7969, n7970, n7971, n7972, n7973, n7974,
n7975, n7976, n7977, n7978, n7979, n7980, n7981, n7982, n7983, n7984,
n7985, n7986, n7987, n7988, n7989, n7990, n7991, n7992, n7993, n7994,
n7995, n7996, n7997, n7998, n7999, n8000, n8001, n8002, n8003, n8004,
n8005, n8006, n8007, n8008, n8009, n8010, n8011, n8012, n8013, n8014,
n8015, n8016, n8017, n8018, n8019, n8020, n8021, n8022, n8023, n8024,
n8025, n8026, n8027, n8028, n8029, n8030, n8031, n8032, n8033, n8034,
n8035, n8036, n8037, n8038, n8039, n8040, n8041, n8042, n8043, n8044,
n8045, n8046, n8047, n8048, n8049, n8050, n8051, n8052, n8053, n8054,
n8055, n8056, n8057, n8058, n8059, n8060, n8061, n8062, n8063, n8064,
n8065, n8066, n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074,
n8075, n8076, n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084,
n8085, n8086, n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094,
n8095, n8096, n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104,
n8105, n8106, n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114,
n8115, n8116, n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124,
n8125, n8126, n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134,
n8135, n8136, n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144,
n8145, n8146, n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8154,
n8155, n8156, n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164,
n8165, n8166, n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174,
n8175, n8176, n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184,
n8185, n8186, n8187, n8188, n8189, n8190, n8191, n8192, n8193, n8194,
n8195, n8196, n8197, n8198, n8199, n8200, n8201, n8202, n8203, n8204,
n8205, n8206, n8207, n8208, n8209, n8210, n8211, n8212, n8213, n8214,
n8215, n8216, n8217, n8218, n8219, n8220, n8221, n8222, n8223, n8224,
n8225, n8226, n8227, n8228, n8229, n8230, n8231, n8232, n8233, n8234,
n8235, n8236, n8237, n8238, n8239, n8240, n8241, n8242, n8243, n8244,
n8245, n8246, n8247, n8248, n8249, n8250, n8251, n8252, n8253, n8254,
n8255, n8256, n8257, n8258, n8259, n8260, n8261, n8262, n8263, n8264,
n8265, n8266, n8267, n8268, n8269, n8270, n8271, n8272, n8273, n8274,
n8275, n8276, n8277, n8278, n8279, n8280, n8281, n8282, n8283, n8284,
n8285, n8286, n8287, n8288, n8289, n8290, n8291, n8292, n8293, n8294,
n8295, n8296, n8297, n8298, n8299, n8300, n8301, n8302, n8303, n8304,
n8305, n8306, n8307, n8308, n8309, n8310, n8311, n8312, n8313, n8314,
n8315, n8316, n8317, n8318, n8319, n8320, n8321, n8322, n8323, n8324,
n8325, n8326, n8327, n8328, n8329, n8330, n8331, n8332, n8333;
wire [53:0] Q_left;
wire [53:27] Q_right;
wire [55:0] Q_middle;
wire [55:0] S_A;
wire [55:0] S_B;
wire [107:0] Result;
substractor GEN1_Subtr_1 ( .Data_A_i(Q_middle), .Data_B_i({1'b0, 1'b0,
Q_left}), .Data_S_o(S_A) );
substractor GEN1_Subtr_2 ( .Data_A_i(S_A), .Data_B_i({1'b0, 1'b0, Q_right,
Result[26:0]}), .Data_S_o(S_B) );
DFFQX1TS GEN1_middle_pdt_int_reg_0_ ( .D(GEN1_middle_N0), .CK(clk), .Q(
Q_middle[0]) );
DFFQX1TS GEN1_middle_pdt_int_reg_1_ ( .D(GEN1_middle_N1), .CK(clk), .Q(
Q_middle[1]) );
DFFQX1TS GEN1_middle_pdt_int_reg_2_ ( .D(GEN1_middle_N2), .CK(clk), .Q(
Q_middle[2]) );
DFFQX1TS GEN1_middle_pdt_int_reg_3_ ( .D(GEN1_middle_N3), .CK(clk), .Q(
Q_middle[3]) );
DFFQX1TS GEN1_middle_pdt_int_reg_4_ ( .D(GEN1_middle_N4), .CK(clk), .Q(
Q_middle[4]) );
DFFQX1TS GEN1_middle_pdt_int_reg_5_ ( .D(GEN1_middle_N5), .CK(clk), .Q(
Q_middle[5]) );
DFFQX1TS GEN1_middle_pdt_int_reg_6_ ( .D(GEN1_middle_N6), .CK(clk), .Q(
Q_middle[6]) );
DFFQX1TS GEN1_middle_pdt_int_reg_7_ ( .D(GEN1_middle_N7), .CK(clk), .Q(
Q_middle[7]) );
DFFQX1TS GEN1_middle_pdt_int_reg_8_ ( .D(GEN1_middle_N8), .CK(clk), .Q(
Q_middle[8]) );
DFFQX1TS GEN1_middle_pdt_int_reg_9_ ( .D(GEN1_middle_N9), .CK(clk), .Q(
Q_middle[9]) );
DFFQX1TS GEN1_middle_pdt_int_reg_10_ ( .D(GEN1_middle_N10), .CK(clk), .Q(
Q_middle[10]) );
DFFQX1TS GEN1_middle_pdt_int_reg_11_ ( .D(GEN1_middle_N11), .CK(clk), .Q(
Q_middle[11]) );
DFFQX1TS GEN1_middle_pdt_int_reg_12_ ( .D(GEN1_middle_N12), .CK(clk), .Q(
Q_middle[12]) );
DFFQX1TS GEN1_middle_pdt_int_reg_13_ ( .D(GEN1_middle_N13), .CK(clk), .Q(
Q_middle[13]) );
DFFQX1TS GEN1_middle_pdt_int_reg_14_ ( .D(GEN1_middle_N14), .CK(clk), .Q(
Q_middle[14]) );
DFFQX1TS GEN1_middle_pdt_int_reg_15_ ( .D(GEN1_middle_N15), .CK(clk), .Q(
Q_middle[15]) );
DFFQX1TS GEN1_middle_pdt_int_reg_16_ ( .D(GEN1_middle_N16), .CK(clk), .Q(
Q_middle[16]) );
DFFQX1TS GEN1_middle_pdt_int_reg_17_ ( .D(GEN1_middle_N17), .CK(clk), .Q(
Q_middle[17]) );
DFFQX1TS GEN1_middle_pdt_int_reg_18_ ( .D(GEN1_middle_N18), .CK(clk), .Q(
Q_middle[18]) );
DFFQX1TS GEN1_middle_pdt_int_reg_19_ ( .D(GEN1_middle_N19), .CK(clk), .Q(
Q_middle[19]) );
DFFQX1TS GEN1_middle_pdt_int_reg_20_ ( .D(GEN1_middle_N20), .CK(clk), .Q(
Q_middle[20]) );
DFFQX1TS GEN1_middle_pdt_int_reg_21_ ( .D(GEN1_middle_N21), .CK(clk), .Q(
Q_middle[21]) );
DFFQX1TS GEN1_middle_pdt_int_reg_22_ ( .D(GEN1_middle_N22), .CK(clk), .Q(
Q_middle[22]) );
DFFQX1TS GEN1_middle_pdt_int_reg_23_ ( .D(GEN1_middle_N23), .CK(clk), .Q(
Q_middle[23]) );
DFFQX1TS GEN1_middle_pdt_int_reg_24_ ( .D(GEN1_middle_N24), .CK(clk), .Q(
Q_middle[24]) );
DFFQX1TS GEN1_middle_pdt_int_reg_25_ ( .D(GEN1_middle_N25), .CK(clk), .Q(
Q_middle[25]) );
AFHCINX2TS GEN1_Final_add_x_1_U29 ( .CIN(GEN1_Final_add_x_1_n81), .B(
Q_left[25]), .A(S_B[52]), .S(Result[79]), .CO(GEN1_Final_add_x_1_n80)
);
AFHCONX2TS GEN1_Final_add_x_1_U28 ( .A(S_B[53]), .B(Q_left[26]), .CI(
GEN1_Final_add_x_1_n80), .CON(GEN1_Final_add_x_1_n79), .S(Result[80])
);
AFHCINX2TS GEN1_Final_add_x_1_U27 ( .CIN(GEN1_Final_add_x_1_n79), .B(
Q_left[27]), .A(S_B[54]), .S(Result[81]), .CO(GEN1_Final_add_x_1_n78)
);
AFHCONX2TS GEN1_Final_add_x_1_U26 ( .A(S_B[55]), .B(Q_left[28]), .CI(
GEN1_Final_add_x_1_n78), .CON(GEN1_Final_add_x_1_n77), .S(Result[82])
);
AHHCINX2TS GEN1_Final_add_x_1_U25 ( .A(Q_left[29]), .CIN(
GEN1_Final_add_x_1_n77), .S(Result[83]), .CO(GEN1_Final_add_x_1_n76)
);
AHHCONX2TS GEN1_Final_add_x_1_U24 ( .A(Q_left[30]), .CI(
GEN1_Final_add_x_1_n76), .CON(GEN1_Final_add_x_1_n75), .S(Result[84])
);
AHHCINX2TS GEN1_Final_add_x_1_U23 ( .A(Q_left[31]), .CIN(
GEN1_Final_add_x_1_n75), .S(Result[85]), .CO(GEN1_Final_add_x_1_n74)
);
AHHCONX2TS GEN1_Final_add_x_1_U22 ( .A(Q_left[32]), .CI(
GEN1_Final_add_x_1_n74), .CON(GEN1_Final_add_x_1_n73), .S(Result[86])
);
AHHCINX2TS GEN1_Final_add_x_1_U21 ( .A(Q_left[33]), .CIN(
GEN1_Final_add_x_1_n73), .S(Result[87]), .CO(GEN1_Final_add_x_1_n72)
);
AHHCONX2TS GEN1_Final_add_x_1_U20 ( .A(Q_left[34]), .CI(
GEN1_Final_add_x_1_n72), .CON(GEN1_Final_add_x_1_n71), .S(Result[88])
);
AHHCINX2TS GEN1_Final_add_x_1_U19 ( .A(Q_left[35]), .CIN(
GEN1_Final_add_x_1_n71), .S(Result[89]), .CO(GEN1_Final_add_x_1_n70)
);
AHHCONX2TS GEN1_Final_add_x_1_U18 ( .A(Q_left[36]), .CI(
GEN1_Final_add_x_1_n70), .CON(GEN1_Final_add_x_1_n69), .S(Result[90])
);
AHHCONX2TS GEN1_Final_add_x_1_U16 ( .A(Q_left[38]), .CI(
GEN1_Final_add_x_1_n68), .CON(GEN1_Final_add_x_1_n67), .S(Result[92])
);
AHHCONX2TS GEN1_Final_add_x_1_U14 ( .A(Q_left[40]), .CI(
GEN1_Final_add_x_1_n66), .CON(GEN1_Final_add_x_1_n65), .S(Result[94])
);
AHHCONX2TS GEN1_Final_add_x_1_U12 ( .A(Q_left[42]), .CI(
GEN1_Final_add_x_1_n64), .CON(GEN1_Final_add_x_1_n63), .S(Result[96])
);
AHHCONX2TS GEN1_Final_add_x_1_U10 ( .A(Q_left[44]), .CI(
GEN1_Final_add_x_1_n62), .CON(GEN1_Final_add_x_1_n61), .S(Result[98])
);
AHHCINX2TS GEN1_Final_add_x_1_U9 ( .A(Q_left[45]), .CIN(
GEN1_Final_add_x_1_n61), .S(Result[99]), .CO(GEN1_Final_add_x_1_n60)
);
DFFQX1TS GEN1_middle_pdt_int_reg_26_ ( .D(GEN1_middle_N26), .CK(clk), .Q(
Q_middle[26]) );
DFFQX1TS GEN1_middle_pdt_int_reg_27_ ( .D(GEN1_middle_N27), .CK(clk), .Q(
Q_middle[27]) );
DFFQX1TS GEN1_middle_pdt_int_reg_28_ ( .D(GEN1_middle_N28), .CK(clk), .Q(
Q_middle[28]) );
DFFQX1TS GEN1_middle_pdt_int_reg_29_ ( .D(GEN1_middle_N29), .CK(clk), .Q(
Q_middle[29]) );
DFFQX1TS GEN1_middle_pdt_int_reg_30_ ( .D(GEN1_middle_N30), .CK(clk), .Q(
Q_middle[30]) );
DFFQX1TS GEN1_middle_pdt_int_reg_31_ ( .D(GEN1_middle_N31), .CK(clk), .Q(
Q_middle[31]) );
DFFQX1TS GEN1_middle_pdt_int_reg_32_ ( .D(GEN1_middle_N32), .CK(clk), .Q(
Q_middle[32]) );
DFFQX1TS GEN1_middle_pdt_int_reg_33_ ( .D(GEN1_middle_N33), .CK(clk), .Q(
Q_middle[33]) );
DFFQX1TS GEN1_middle_pdt_int_reg_34_ ( .D(GEN1_middle_N34), .CK(clk), .Q(
Q_middle[34]) );
DFFQX1TS GEN1_middle_pdt_int_reg_37_ ( .D(GEN1_middle_N37), .CK(clk), .Q(
Q_middle[37]) );
DFFQX1TS GEN1_middle_pdt_int_reg_38_ ( .D(GEN1_middle_N38), .CK(clk), .Q(
Q_middle[38]) );
DFFQX1TS GEN1_right_pdt_int_reg_0_ ( .D(GEN1_right_N0), .CK(clk), .Q(
Result[0]) );
DFFQX1TS GEN1_right_pdt_int_reg_1_ ( .D(GEN1_right_N1), .CK(clk), .Q(
Result[1]) );
DFFQX1TS GEN1_right_pdt_int_reg_2_ ( .D(GEN1_right_N2), .CK(clk), .Q(
Result[2]) );
DFFQX1TS GEN1_right_pdt_int_reg_3_ ( .D(GEN1_right_N3), .CK(clk), .Q(
Result[3]) );
DFFQX1TS GEN1_right_pdt_int_reg_4_ ( .D(GEN1_right_N4), .CK(clk), .Q(
Result[4]) );
DFFQX1TS GEN1_right_pdt_int_reg_5_ ( .D(GEN1_right_N5), .CK(clk), .Q(
Result[5]) );
DFFQX1TS GEN1_right_pdt_int_reg_6_ ( .D(GEN1_right_N6), .CK(clk), .Q(
Result[6]) );
DFFQX1TS GEN1_right_pdt_int_reg_7_ ( .D(GEN1_right_N7), .CK(clk), .Q(
Result[7]) );
DFFQX1TS GEN1_right_pdt_int_reg_8_ ( .D(GEN1_right_N8), .CK(clk), .Q(
Result[8]) );
DFFQX1TS GEN1_right_pdt_int_reg_9_ ( .D(GEN1_right_N9), .CK(clk), .Q(
Result[9]) );
DFFQX1TS GEN1_right_pdt_int_reg_10_ ( .D(GEN1_right_N10), .CK(clk), .Q(
Result[10]) );
DFFQX1TS GEN1_right_pdt_int_reg_11_ ( .D(GEN1_right_N11), .CK(clk), .Q(
Result[11]) );
DFFQX1TS GEN1_right_pdt_int_reg_12_ ( .D(GEN1_right_N12), .CK(clk), .Q(
Result[12]) );
DFFQX1TS GEN1_right_pdt_int_reg_13_ ( .D(GEN1_right_N13), .CK(clk), .Q(
Result[13]) );
DFFQX1TS GEN1_right_pdt_int_reg_14_ ( .D(GEN1_right_N14), .CK(clk), .Q(
Result[14]) );
DFFQX1TS GEN1_right_pdt_int_reg_15_ ( .D(GEN1_right_N15), .CK(clk), .Q(
Result[15]) );
DFFQX1TS GEN1_right_pdt_int_reg_16_ ( .D(GEN1_right_N16), .CK(clk), .Q(
Result[16]) );
DFFQX1TS GEN1_right_pdt_int_reg_17_ ( .D(GEN1_right_N17), .CK(clk), .Q(
Result[17]) );
DFFQX1TS GEN1_right_pdt_int_reg_18_ ( .D(GEN1_right_N18), .CK(clk), .Q(
Result[18]) );
DFFQX1TS GEN1_right_pdt_int_reg_19_ ( .D(GEN1_right_N19), .CK(clk), .Q(
Result[19]) );
DFFQX1TS GEN1_right_pdt_int_reg_20_ ( .D(GEN1_right_N20), .CK(clk), .Q(
Result[20]) );
DFFQX1TS GEN1_right_pdt_int_reg_21_ ( .D(GEN1_right_N21), .CK(clk), .Q(
Result[21]) );
DFFQX1TS GEN1_right_pdt_int_reg_22_ ( .D(GEN1_right_N22), .CK(clk), .Q(
Result[22]) );
DFFQX1TS GEN1_right_pdt_int_reg_23_ ( .D(GEN1_right_N23), .CK(clk), .Q(
Result[23]) );
DFFQX1TS GEN1_right_pdt_int_reg_24_ ( .D(GEN1_right_N24), .CK(clk), .Q(
Result[24]) );
DFFQX1TS GEN1_right_pdt_int_reg_25_ ( .D(GEN1_right_N25), .CK(clk), .Q(
Result[25]) );
DFFQX1TS GEN1_right_pdt_int_reg_26_ ( .D(GEN1_right_N26), .CK(clk), .Q(
Result[26]) );
DFFQX1TS GEN1_left_pdt_int_reg_53_ ( .D(GEN1_left_N53), .CK(clk), .Q(
Q_left[53]) );
DFFQX1TS GEN1_left_pdt_int_reg_50_ ( .D(GEN1_left_N50), .CK(clk), .Q(
Q_left[50]) );
DFFRXLTS GEN1_finalreg_Q_reg_0_ ( .D(n110), .CK(clk), .RN(n8318), .Q(
sgf_result_o[0]) );
DFFRXLTS GEN1_finalreg_Q_reg_1_ ( .D(n109), .CK(clk), .RN(n8318), .Q(
sgf_result_o[1]) );
DFFRXLTS GEN1_finalreg_Q_reg_2_ ( .D(n108), .CK(clk), .RN(n8318), .Q(
sgf_result_o[2]) );
DFFRXLTS GEN1_finalreg_Q_reg_3_ ( .D(n107), .CK(clk), .RN(n8318), .Q(
sgf_result_o[3]) );
DFFRXLTS GEN1_finalreg_Q_reg_4_ ( .D(n106), .CK(clk), .RN(n8318), .Q(
sgf_result_o[4]) );
DFFRXLTS GEN1_finalreg_Q_reg_5_ ( .D(n105), .CK(clk), .RN(n8318), .Q(
sgf_result_o[5]) );
DFFRXLTS GEN1_finalreg_Q_reg_6_ ( .D(n104), .CK(clk), .RN(n8318), .Q(
sgf_result_o[6]) );
DFFRXLTS GEN1_finalreg_Q_reg_7_ ( .D(n103), .CK(clk), .RN(n8318), .Q(
sgf_result_o[7]) );
DFFRXLTS GEN1_finalreg_Q_reg_8_ ( .D(n102), .CK(clk), .RN(n8318), .Q(
sgf_result_o[8]) );
DFFRXLTS GEN1_finalreg_Q_reg_9_ ( .D(n101), .CK(clk), .RN(n8318), .Q(
sgf_result_o[9]) );
DFFRXLTS GEN1_finalreg_Q_reg_10_ ( .D(n100), .CK(clk), .RN(n8319), .Q(
sgf_result_o[10]) );
DFFRXLTS GEN1_finalreg_Q_reg_11_ ( .D(n99), .CK(clk), .RN(n8319), .Q(
sgf_result_o[11]) );
DFFRXLTS GEN1_finalreg_Q_reg_12_ ( .D(n98), .CK(clk), .RN(n8319), .Q(
sgf_result_o[12]) );
DFFRXLTS GEN1_finalreg_Q_reg_13_ ( .D(n97), .CK(clk), .RN(n8319), .Q(
sgf_result_o[13]) );
DFFRXLTS GEN1_finalreg_Q_reg_14_ ( .D(n96), .CK(clk), .RN(n8319), .Q(
sgf_result_o[14]) );
DFFRXLTS GEN1_finalreg_Q_reg_15_ ( .D(n95), .CK(clk), .RN(n8319), .Q(
sgf_result_o[15]) );
DFFRXLTS GEN1_finalreg_Q_reg_16_ ( .D(n94), .CK(clk), .RN(n8319), .Q(
sgf_result_o[16]) );
DFFRXLTS GEN1_finalreg_Q_reg_17_ ( .D(n93), .CK(clk), .RN(n8319), .Q(
sgf_result_o[17]) );
DFFRXLTS GEN1_finalreg_Q_reg_18_ ( .D(n92), .CK(clk), .RN(n8319), .Q(
sgf_result_o[18]) );
DFFRXLTS GEN1_finalreg_Q_reg_19_ ( .D(n91), .CK(clk), .RN(n8319), .Q(
sgf_result_o[19]) );
DFFRXLTS GEN1_finalreg_Q_reg_20_ ( .D(n90), .CK(clk), .RN(n8320), .Q(
sgf_result_o[20]) );
DFFRXLTS GEN1_finalreg_Q_reg_21_ ( .D(n89), .CK(clk), .RN(n8320), .Q(
sgf_result_o[21]) );
DFFRXLTS GEN1_finalreg_Q_reg_22_ ( .D(n88), .CK(clk), .RN(n8320), .Q(
sgf_result_o[22]) );
DFFRXLTS GEN1_finalreg_Q_reg_23_ ( .D(n87), .CK(clk), .RN(n8320), .Q(
sgf_result_o[23]) );
DFFRXLTS GEN1_finalreg_Q_reg_24_ ( .D(n86), .CK(clk), .RN(n8320), .Q(
sgf_result_o[24]) );
DFFRXLTS GEN1_finalreg_Q_reg_25_ ( .D(n85), .CK(clk), .RN(n8320), .Q(
sgf_result_o[25]) );
DFFRXLTS GEN1_finalreg_Q_reg_26_ ( .D(n84), .CK(clk), .RN(n8320), .Q(
sgf_result_o[26]) );
DFFRXLTS GEN1_finalreg_Q_reg_27_ ( .D(n83), .CK(clk), .RN(n8320), .Q(
sgf_result_o[27]) );
DFFRXLTS GEN1_finalreg_Q_reg_28_ ( .D(n82), .CK(clk), .RN(n8320), .Q(
sgf_result_o[28]) );
DFFRXLTS GEN1_finalreg_Q_reg_29_ ( .D(n81), .CK(clk), .RN(n8320), .Q(
sgf_result_o[29]) );
DFFRXLTS GEN1_finalreg_Q_reg_30_ ( .D(n80), .CK(clk), .RN(n8321), .Q(
sgf_result_o[30]) );
DFFRXLTS GEN1_finalreg_Q_reg_31_ ( .D(n79), .CK(clk), .RN(n8321), .Q(
sgf_result_o[31]) );
DFFRXLTS GEN1_finalreg_Q_reg_32_ ( .D(n78), .CK(clk), .RN(n8321), .Q(
sgf_result_o[32]) );
DFFRXLTS GEN1_finalreg_Q_reg_33_ ( .D(n77), .CK(clk), .RN(n8321), .Q(
sgf_result_o[33]) );
DFFRXLTS GEN1_finalreg_Q_reg_34_ ( .D(n76), .CK(clk), .RN(n8321), .Q(
sgf_result_o[34]) );
DFFRXLTS GEN1_finalreg_Q_reg_35_ ( .D(n75), .CK(clk), .RN(n8321), .Q(
sgf_result_o[35]) );
DFFRXLTS GEN1_finalreg_Q_reg_36_ ( .D(n74), .CK(clk), .RN(n8321), .Q(
sgf_result_o[36]) );
DFFRXLTS GEN1_finalreg_Q_reg_37_ ( .D(n73), .CK(clk), .RN(n8321), .Q(
sgf_result_o[37]) );
DFFRXLTS GEN1_finalreg_Q_reg_38_ ( .D(n72), .CK(clk), .RN(n8321), .Q(
sgf_result_o[38]) );
DFFRXLTS GEN1_finalreg_Q_reg_39_ ( .D(n71), .CK(clk), .RN(n8321), .Q(
sgf_result_o[39]) );
DFFRXLTS GEN1_finalreg_Q_reg_40_ ( .D(n70), .CK(clk), .RN(n8322), .Q(
sgf_result_o[40]) );
DFFRXLTS GEN1_finalreg_Q_reg_41_ ( .D(n69), .CK(clk), .RN(n8322), .Q(
sgf_result_o[41]) );
DFFRXLTS GEN1_finalreg_Q_reg_42_ ( .D(n68), .CK(clk), .RN(n8322), .Q(
sgf_result_o[42]) );
DFFRXLTS GEN1_finalreg_Q_reg_43_ ( .D(n67), .CK(clk), .RN(n8322), .Q(
sgf_result_o[43]) );
DFFRXLTS GEN1_finalreg_Q_reg_44_ ( .D(n66), .CK(clk), .RN(n8322), .Q(
sgf_result_o[44]) );
DFFRXLTS GEN1_finalreg_Q_reg_45_ ( .D(n65), .CK(clk), .RN(n8322), .Q(
sgf_result_o[45]) );
DFFRXLTS GEN1_finalreg_Q_reg_46_ ( .D(n64), .CK(clk), .RN(n8328), .Q(
sgf_result_o[46]) );
DFFRXLTS GEN1_finalreg_Q_reg_47_ ( .D(n63), .CK(clk), .RN(n8328), .Q(
sgf_result_o[47]) );
DFFRXLTS GEN1_finalreg_Q_reg_48_ ( .D(n62), .CK(clk), .RN(n8328), .Q(
sgf_result_o[48]) );
DFFRXLTS GEN1_finalreg_Q_reg_49_ ( .D(n61), .CK(clk), .RN(n8328), .Q(
sgf_result_o[49]) );
DFFRXLTS GEN1_finalreg_Q_reg_50_ ( .D(n60), .CK(clk), .RN(n8328), .Q(
sgf_result_o[50]) );
DFFRXLTS GEN1_finalreg_Q_reg_51_ ( .D(n59), .CK(clk), .RN(n8328), .Q(
sgf_result_o[51]) );
DFFRXLTS GEN1_finalreg_Q_reg_52_ ( .D(n58), .CK(clk), .RN(n8328), .Q(
sgf_result_o[52]) );
DFFRXLTS GEN1_finalreg_Q_reg_53_ ( .D(n57), .CK(clk), .RN(n8328), .Q(
sgf_result_o[53]) );
DFFRXLTS GEN1_finalreg_Q_reg_54_ ( .D(n56), .CK(clk), .RN(n8327), .Q(
sgf_result_o[54]) );
DFFRXLTS GEN1_finalreg_Q_reg_55_ ( .D(n55), .CK(clk), .RN(n8327), .Q(
sgf_result_o[55]) );
DFFRXLTS GEN1_finalreg_Q_reg_56_ ( .D(n54), .CK(clk), .RN(n8327), .Q(
sgf_result_o[56]) );
DFFRXLTS GEN1_finalreg_Q_reg_57_ ( .D(n53), .CK(clk), .RN(n8327), .Q(
sgf_result_o[57]) );
DFFRXLTS GEN1_finalreg_Q_reg_58_ ( .D(n52), .CK(clk), .RN(n8327), .Q(
sgf_result_o[58]) );
DFFRXLTS GEN1_finalreg_Q_reg_59_ ( .D(n51), .CK(clk), .RN(n8327), .Q(
sgf_result_o[59]) );
DFFRXLTS GEN1_finalreg_Q_reg_60_ ( .D(n50), .CK(clk), .RN(n8327), .Q(
sgf_result_o[60]) );
DFFRXLTS GEN1_finalreg_Q_reg_61_ ( .D(n49), .CK(clk), .RN(n8327), .Q(
sgf_result_o[61]) );
DFFRXLTS GEN1_finalreg_Q_reg_62_ ( .D(n48), .CK(clk), .RN(n8327), .Q(
sgf_result_o[62]) );
DFFRXLTS GEN1_finalreg_Q_reg_63_ ( .D(n47), .CK(clk), .RN(n8327), .Q(
sgf_result_o[63]) );
DFFRXLTS GEN1_finalreg_Q_reg_64_ ( .D(n46), .CK(clk), .RN(n8326), .Q(
sgf_result_o[64]) );
DFFRXLTS GEN1_finalreg_Q_reg_65_ ( .D(n45), .CK(clk), .RN(n8326), .Q(
sgf_result_o[65]) );
DFFRXLTS GEN1_finalreg_Q_reg_66_ ( .D(n44), .CK(clk), .RN(n8326), .Q(
sgf_result_o[66]) );
DFFRXLTS GEN1_finalreg_Q_reg_67_ ( .D(n43), .CK(clk), .RN(n8326), .Q(
sgf_result_o[67]) );
DFFRXLTS GEN1_finalreg_Q_reg_68_ ( .D(n42), .CK(clk), .RN(n8326), .Q(
sgf_result_o[68]) );
DFFRXLTS GEN1_finalreg_Q_reg_69_ ( .D(n41), .CK(clk), .RN(n8326), .Q(
sgf_result_o[69]) );
DFFRXLTS GEN1_finalreg_Q_reg_70_ ( .D(n40), .CK(clk), .RN(n8326), .Q(
sgf_result_o[70]) );
DFFRXLTS GEN1_finalreg_Q_reg_71_ ( .D(n39), .CK(clk), .RN(n8326), .Q(
sgf_result_o[71]) );
DFFRXLTS GEN1_finalreg_Q_reg_72_ ( .D(n38), .CK(clk), .RN(n8326), .Q(
sgf_result_o[72]) );
DFFRXLTS GEN1_finalreg_Q_reg_73_ ( .D(n37), .CK(clk), .RN(n8326), .Q(
sgf_result_o[73]) );
DFFRXLTS GEN1_finalreg_Q_reg_74_ ( .D(n36), .CK(clk), .RN(n8325), .Q(
sgf_result_o[74]) );
DFFRXLTS GEN1_finalreg_Q_reg_75_ ( .D(n35), .CK(clk), .RN(n8325), .Q(
sgf_result_o[75]) );
DFFRXLTS GEN1_finalreg_Q_reg_76_ ( .D(n34), .CK(clk), .RN(n8325), .Q(
sgf_result_o[76]) );
DFFRXLTS GEN1_finalreg_Q_reg_77_ ( .D(n33), .CK(clk), .RN(n8325), .Q(
sgf_result_o[77]) );
DFFRXLTS GEN1_finalreg_Q_reg_78_ ( .D(n32), .CK(clk), .RN(n8325), .Q(
sgf_result_o[78]) );
DFFRXLTS GEN1_finalreg_Q_reg_79_ ( .D(n31), .CK(clk), .RN(n8325), .Q(
sgf_result_o[79]) );
DFFRXLTS GEN1_finalreg_Q_reg_80_ ( .D(n30), .CK(clk), .RN(n8325), .Q(
sgf_result_o[80]) );
DFFRXLTS GEN1_finalreg_Q_reg_81_ ( .D(n29), .CK(clk), .RN(n8325), .Q(
sgf_result_o[81]) );
DFFRXLTS GEN1_finalreg_Q_reg_82_ ( .D(n28), .CK(clk), .RN(n8325), .Q(
sgf_result_o[82]) );
DFFRXLTS GEN1_finalreg_Q_reg_83_ ( .D(n27), .CK(clk), .RN(n8325), .Q(
sgf_result_o[83]) );
DFFRXLTS GEN1_finalreg_Q_reg_84_ ( .D(n26), .CK(clk), .RN(n8324), .Q(
sgf_result_o[84]) );
DFFRXLTS GEN1_finalreg_Q_reg_85_ ( .D(n25), .CK(clk), .RN(n8324), .Q(
sgf_result_o[85]) );
DFFRXLTS GEN1_finalreg_Q_reg_86_ ( .D(n24), .CK(clk), .RN(n8324), .Q(
sgf_result_o[86]) );
DFFRXLTS GEN1_finalreg_Q_reg_87_ ( .D(n23), .CK(clk), .RN(n8324), .Q(
sgf_result_o[87]) );
DFFRXLTS GEN1_finalreg_Q_reg_88_ ( .D(n22), .CK(clk), .RN(n8324), .Q(
sgf_result_o[88]) );
DFFRXLTS GEN1_finalreg_Q_reg_89_ ( .D(n21), .CK(clk), .RN(n8324), .Q(
sgf_result_o[89]) );
DFFRXLTS GEN1_finalreg_Q_reg_90_ ( .D(n20), .CK(clk), .RN(n8324), .Q(
sgf_result_o[90]) );
DFFRXLTS GEN1_finalreg_Q_reg_91_ ( .D(n19), .CK(clk), .RN(n8324), .Q(
sgf_result_o[91]) );
DFFRXLTS GEN1_finalreg_Q_reg_92_ ( .D(n18), .CK(clk), .RN(n8324), .Q(
sgf_result_o[92]) );
DFFRXLTS GEN1_finalreg_Q_reg_93_ ( .D(n17), .CK(clk), .RN(n8324), .Q(
sgf_result_o[93]) );
DFFRXLTS GEN1_finalreg_Q_reg_94_ ( .D(n16), .CK(clk), .RN(n8323), .Q(
sgf_result_o[94]) );
DFFRXLTS GEN1_finalreg_Q_reg_95_ ( .D(n15), .CK(clk), .RN(n8323), .Q(
sgf_result_o[95]) );
DFFRXLTS GEN1_finalreg_Q_reg_96_ ( .D(n14), .CK(clk), .RN(n8323), .Q(
sgf_result_o[96]) );
DFFRXLTS GEN1_finalreg_Q_reg_97_ ( .D(n13), .CK(clk), .RN(n8323), .Q(
sgf_result_o[97]) );
DFFRXLTS GEN1_finalreg_Q_reg_98_ ( .D(n12), .CK(clk), .RN(n8323), .Q(
sgf_result_o[98]) );
DFFRXLTS GEN1_finalreg_Q_reg_99_ ( .D(n11), .CK(clk), .RN(n8323), .Q(
sgf_result_o[99]) );
DFFRXLTS GEN1_finalreg_Q_reg_100_ ( .D(n10), .CK(clk), .RN(n8323), .Q(
sgf_result_o[100]) );
DFFRXLTS GEN1_finalreg_Q_reg_101_ ( .D(n9), .CK(clk), .RN(n8323), .Q(
sgf_result_o[101]) );
DFFRXLTS GEN1_finalreg_Q_reg_102_ ( .D(n8), .CK(clk), .RN(n8323), .Q(
sgf_result_o[102]) );
DFFRXLTS GEN1_finalreg_Q_reg_103_ ( .D(n7), .CK(clk), .RN(n8323), .Q(
sgf_result_o[103]) );
DFFRXLTS GEN1_finalreg_Q_reg_104_ ( .D(n6), .CK(clk), .RN(n8322), .Q(
sgf_result_o[104]) );
DFFRXLTS GEN1_finalreg_Q_reg_105_ ( .D(n5), .CK(clk), .RN(n8322), .Q(
sgf_result_o[105]) );
DFFRXLTS GEN1_finalreg_Q_reg_106_ ( .D(n4), .CK(clk), .RN(n8322), .Q(
sgf_result_o[106]) );
DFFRXLTS GEN1_finalreg_Q_reg_107_ ( .D(n3), .CK(clk), .RN(n8322), .Q(
sgf_result_o[107]) );
DFFQX1TS GEN1_left_pdt_int_reg_37_ ( .D(GEN1_left_N37), .CK(clk), .Q(
Q_left[37]) );
DFFQX1TS GEN1_left_pdt_int_reg_41_ ( .D(GEN1_left_N41), .CK(clk), .Q(
Q_left[41]) );
DFFQX1TS GEN1_left_pdt_int_reg_36_ ( .D(GEN1_left_N36), .CK(clk), .Q(
Q_left[36]) );
DFFQX1TS GEN1_left_pdt_int_reg_31_ ( .D(GEN1_left_N31), .CK(clk), .Q(
Q_left[31]) );
DFFQX1TS GEN1_left_pdt_int_reg_33_ ( .D(GEN1_left_N33), .CK(clk), .Q(
Q_left[33]) );
DFFQX1TS GEN1_left_pdt_int_reg_35_ ( .D(GEN1_left_N35), .CK(clk), .Q(
Q_left[35]) );
DFFQX1TS GEN1_left_pdt_int_reg_32_ ( .D(GEN1_left_N32), .CK(clk), .Q(
Q_left[32]) );
DFFQX1TS GEN1_left_pdt_int_reg_34_ ( .D(GEN1_left_N34), .CK(clk), .Q(
Q_left[34]) );
DFFQX1TS GEN1_left_pdt_int_reg_29_ ( .D(GEN1_left_N29), .CK(clk), .Q(
Q_left[29]) );
DFFQX1TS GEN1_left_pdt_int_reg_30_ ( .D(GEN1_left_N30), .CK(clk), .Q(
Q_left[30]) );
DFFQX1TS GEN1_left_pdt_int_reg_27_ ( .D(GEN1_left_N27), .CK(clk), .Q(
Q_left[27]) );
DFFQX1TS GEN1_left_pdt_int_reg_28_ ( .D(GEN1_left_N28), .CK(clk), .Q(
Q_left[28]) );
DFFQX1TS GEN1_left_pdt_int_reg_24_ ( .D(GEN1_left_N24), .CK(clk), .Q(
Q_left[24]) );
DFFQX1TS GEN1_left_pdt_int_reg_26_ ( .D(GEN1_left_N26), .CK(clk), .Q(
Q_left[26]) );
DFFQX1TS GEN1_right_pdt_int_reg_27_ ( .D(GEN1_right_N27), .CK(clk), .Q(
Q_right[27]) );
DFFQX1TS GEN1_left_pdt_int_reg_21_ ( .D(GEN1_left_N21), .CK(clk), .Q(
Q_left[21]) );
DFFQX1TS GEN1_left_pdt_int_reg_22_ ( .D(GEN1_left_N22), .CK(clk), .Q(
Q_left[22]) );
DFFQX1TS GEN1_right_pdt_int_reg_28_ ( .D(GEN1_right_N28), .CK(clk), .Q(
Q_right[28]) );
DFFQX1TS GEN1_right_pdt_int_reg_29_ ( .D(GEN1_right_N29), .CK(clk), .Q(
Q_right[29]) );
DFFQX1TS GEN1_right_pdt_int_reg_30_ ( .D(GEN1_right_N30), .CK(clk), .Q(
Q_right[30]) );
DFFQX1TS GEN1_right_pdt_int_reg_31_ ( .D(GEN1_right_N31), .CK(clk), .Q(
Q_right[31]) );
DFFQX1TS GEN1_right_pdt_int_reg_32_ ( .D(GEN1_right_N32), .CK(clk), .Q(
Q_right[32]) );
DFFQX1TS GEN1_right_pdt_int_reg_33_ ( .D(GEN1_right_N33), .CK(clk), .Q(
Q_right[33]) );
DFFQX1TS GEN1_right_pdt_int_reg_34_ ( .D(GEN1_right_N34), .CK(clk), .Q(
Q_right[34]) );
DFFQX1TS GEN1_right_pdt_int_reg_35_ ( .D(GEN1_right_N35), .CK(clk), .Q(
Q_right[35]) );
DFFQX1TS GEN1_right_pdt_int_reg_36_ ( .D(GEN1_right_N36), .CK(clk), .Q(
Q_right[36]) );
DFFQX1TS GEN1_right_pdt_int_reg_37_ ( .D(GEN1_right_N37), .CK(clk), .Q(
Q_right[37]) );
DFFQX1TS GEN1_right_pdt_int_reg_50_ ( .D(GEN1_right_N50), .CK(clk), .Q(
Q_right[50]) );
DFFQX1TS GEN1_left_pdt_int_reg_0_ ( .D(GEN1_left_N0), .CK(clk), .Q(Q_left[0]) );
DFFQX1TS GEN1_left_pdt_int_reg_1_ ( .D(GEN1_left_N1), .CK(clk), .Q(Q_left[1]) );
DFFQX1TS GEN1_left_pdt_int_reg_2_ ( .D(GEN1_left_N2), .CK(clk), .Q(Q_left[2]) );
DFFQX1TS GEN1_left_pdt_int_reg_3_ ( .D(GEN1_left_N3), .CK(clk), .Q(Q_left[3]) );
DFFQX1TS GEN1_left_pdt_int_reg_4_ ( .D(GEN1_left_N4), .CK(clk), .Q(Q_left[4]) );
DFFQX1TS GEN1_left_pdt_int_reg_5_ ( .D(GEN1_left_N5), .CK(clk), .Q(Q_left[5]) );
DFFQX1TS GEN1_left_pdt_int_reg_6_ ( .D(GEN1_left_N6), .CK(clk), .Q(Q_left[6]) );
DFFQX1TS GEN1_left_pdt_int_reg_7_ ( .D(GEN1_left_N7), .CK(clk), .Q(Q_left[7]) );
DFFQX1TS GEN1_left_pdt_int_reg_8_ ( .D(GEN1_left_N8), .CK(clk), .Q(Q_left[8]) );
DFFQX1TS GEN1_left_pdt_int_reg_9_ ( .D(GEN1_left_N9), .CK(clk), .Q(Q_left[9]) );
DFFQX1TS GEN1_left_pdt_int_reg_10_ ( .D(GEN1_left_N10), .CK(clk), .Q(
Q_left[10]) );
DFFQX1TS GEN1_left_pdt_int_reg_11_ ( .D(GEN1_left_N11), .CK(clk), .Q(
Q_left[11]) );
DFFQX1TS GEN1_left_pdt_int_reg_12_ ( .D(GEN1_left_N12), .CK(clk), .Q(
Q_left[12]) );
DFFQX1TS GEN1_left_pdt_int_reg_13_ ( .D(GEN1_left_N13), .CK(clk), .Q(
Q_left[13]) );
DFFQX1TS GEN1_left_pdt_int_reg_14_ ( .D(GEN1_left_N14), .CK(clk), .Q(
Q_left[14]) );
DFFQX1TS GEN1_left_pdt_int_reg_15_ ( .D(GEN1_left_N15), .CK(clk), .Q(
Q_left[15]) );
DFFQX1TS GEN1_left_pdt_int_reg_16_ ( .D(GEN1_left_N16), .CK(clk), .Q(
Q_left[16]) );
DFFQX1TS GEN1_left_pdt_int_reg_17_ ( .D(GEN1_left_N17), .CK(clk), .Q(
Q_left[17]) );
DFFQX1TS GEN1_left_pdt_int_reg_18_ ( .D(GEN1_left_N18), .CK(clk), .Q(
Q_left[18]) );
DFFQX1TS GEN1_left_pdt_int_reg_19_ ( .D(GEN1_left_N19), .CK(clk), .Q(
Q_left[19]) );
DFFQX1TS GEN1_left_pdt_int_reg_20_ ( .D(GEN1_left_N20), .CK(clk), .Q(
Q_left[20]) );
DFFQX1TS GEN1_left_pdt_int_reg_23_ ( .D(GEN1_left_N23), .CK(clk), .Q(
Q_left[23]) );
DFFHQX8TS GEN1_middle_pdt_int_reg_50_ ( .D(GEN1_middle_N50), .CK(clk), .Q(
Q_middle[50]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_52_ ( .D(GEN1_middle_N52), .CK(clk), .Q(
Q_middle[52]) );
DFFHQX4TS GEN1_left_pdt_int_reg_52_ ( .D(GEN1_left_N52), .CK(clk), .Q(
Q_left[52]) );
DFFHQX4TS GEN1_left_pdt_int_reg_49_ ( .D(GEN1_left_N49), .CK(clk), .Q(
Q_left[49]) );
DFFHQX4TS GEN1_left_pdt_int_reg_48_ ( .D(GEN1_left_N48), .CK(clk), .Q(
Q_left[48]) );
DFFHQX4TS GEN1_left_pdt_int_reg_46_ ( .D(GEN1_left_N46), .CK(clk), .Q(
Q_left[46]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_43_ ( .D(GEN1_middle_N43), .CK(clk), .Q(
Q_middle[43]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_44_ ( .D(GEN1_middle_N44), .CK(clk), .Q(
Q_middle[44]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_45_ ( .D(GEN1_middle_N45), .CK(clk), .Q(
Q_middle[45]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_47_ ( .D(GEN1_middle_N47), .CK(clk), .Q(
Q_middle[47]) );
DFFQX1TS GEN1_middle_pdt_int_reg_53_ ( .D(GEN1_middle_N53), .CK(clk), .Q(
Q_middle[53]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_54_ ( .D(GEN1_middle_N54), .CK(clk), .Q(
Q_middle[54]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_39_ ( .D(GEN1_middle_N39), .CK(clk), .Q(
Q_middle[39]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_40_ ( .D(GEN1_middle_N40), .CK(clk), .Q(
Q_middle[40]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_55_ ( .D(GEN1_middle_N55), .CK(clk), .Q(
Q_middle[55]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_46_ ( .D(GEN1_middle_N46), .CK(clk), .Q(
Q_middle[46]) );
DFFQX1TS GEN1_left_pdt_int_reg_25_ ( .D(GEN1_left_N25), .CK(clk), .Q(
Q_left[25]) );
DFFHQX4TS GEN1_right_pdt_int_reg_39_ ( .D(GEN1_right_N39), .CK(clk), .Q(
Q_right[39]) );
DFFHQX4TS GEN1_right_pdt_int_reg_38_ ( .D(GEN1_right_N38), .CK(clk), .Q(
Q_right[38]) );
DFFHQX4TS GEN1_right_pdt_int_reg_41_ ( .D(GEN1_right_N41), .CK(clk), .Q(
Q_right[41]) );
DFFQX1TS GEN1_right_pdt_int_reg_43_ ( .D(GEN1_right_N43), .CK(clk), .Q(
Q_right[43]) );
DFFHQX4TS GEN1_right_pdt_int_reg_48_ ( .D(GEN1_right_N48), .CK(clk), .Q(
Q_right[48]) );
DFFHQX4TS GEN1_right_pdt_int_reg_49_ ( .D(GEN1_right_N49), .CK(clk), .Q(
Q_right[49]) );
DFFHQX4TS GEN1_right_pdt_int_reg_51_ ( .D(GEN1_right_N51), .CK(clk), .Q(
Q_right[51]) );
DFFHQX4TS GEN1_right_pdt_int_reg_52_ ( .D(GEN1_right_N52), .CK(clk), .Q(
Q_right[52]) );
DFFHQX4TS GEN1_right_pdt_int_reg_40_ ( .D(GEN1_right_N40), .CK(clk), .Q(
Q_right[40]) );
DFFQX1TS GEN1_left_pdt_int_reg_47_ ( .D(GEN1_left_N47), .CK(clk), .Q(
Q_left[47]) );
DFFQX1TS GEN1_left_pdt_int_reg_45_ ( .D(GEN1_left_N45), .CK(clk), .Q(
Q_left[45]) );
DFFQX1TS GEN1_left_pdt_int_reg_39_ ( .D(GEN1_left_N39), .CK(clk), .Q(
Q_left[39]) );
DFFHQX4TS GEN1_right_pdt_int_reg_47_ ( .D(GEN1_right_N47), .CK(clk), .Q(
Q_right[47]) );
DFFHQX4TS GEN1_right_pdt_int_reg_46_ ( .D(GEN1_right_N46), .CK(clk), .Q(
Q_right[46]) );
DFFQX1TS GEN1_middle_pdt_int_reg_49_ ( .D(GEN1_middle_N49), .CK(clk), .Q(
Q_middle[49]) );
DFFQX1TS GEN1_left_pdt_int_reg_51_ ( .D(GEN1_left_N51), .CK(clk), .Q(
Q_left[51]) );
DFFQX1TS GEN1_left_pdt_int_reg_44_ ( .D(GEN1_left_N44), .CK(clk), .Q(
Q_left[44]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_51_ ( .D(GEN1_middle_N51), .CK(clk), .Q(
Q_middle[51]) );
DFFQX1TS GEN1_middle_pdt_int_reg_36_ ( .D(GEN1_middle_N36), .CK(clk), .Q(
Q_middle[36]) );
DFFQX1TS GEN1_right_pdt_int_reg_42_ ( .D(GEN1_right_N42), .CK(clk), .Q(
Q_right[42]) );
DFFQX1TS GEN1_right_pdt_int_reg_44_ ( .D(GEN1_right_N44), .CK(clk), .Q(
Q_right[44]) );
DFFQX1TS GEN1_right_pdt_int_reg_53_ ( .D(GEN1_right_N53), .CK(clk), .Q(
Q_right[53]) );
DFFQX1TS GEN1_right_pdt_int_reg_45_ ( .D(GEN1_right_N45), .CK(clk), .Q(
Q_right[45]) );
DFFQX1TS GEN1_left_pdt_int_reg_38_ ( .D(GEN1_left_N38), .CK(clk), .Q(
Q_left[38]) );
AHHCINX2TS GEN1_Final_add_x_1_U17 ( .A(Q_left[37]), .CIN(
GEN1_Final_add_x_1_n69), .S(Result[91]), .CO(GEN1_Final_add_x_1_n68)
);
DFFQX1TS GEN1_left_pdt_int_reg_40_ ( .D(GEN1_left_N40), .CK(clk), .Q(
Q_left[40]) );
AHHCINX2TS GEN1_Final_add_x_1_U15 ( .A(Q_left[39]), .CIN(
GEN1_Final_add_x_1_n67), .S(Result[93]), .CO(GEN1_Final_add_x_1_n66)
);
DFFQX1TS GEN1_left_pdt_int_reg_42_ ( .D(GEN1_left_N42), .CK(clk), .Q(
Q_left[42]) );
AHHCINX2TS GEN1_Final_add_x_1_U13 ( .A(Q_left[41]), .CIN(
GEN1_Final_add_x_1_n65), .S(Result[95]), .CO(GEN1_Final_add_x_1_n64)
);
DFFQX1TS GEN1_left_pdt_int_reg_43_ ( .D(GEN1_left_N43), .CK(clk), .Q(
Q_left[43]) );
DFFQX1TS GEN1_middle_pdt_int_reg_42_ ( .D(GEN1_middle_N42), .CK(clk), .Q(
Q_middle[42]) );
DFFQX1TS GEN1_middle_pdt_int_reg_48_ ( .D(GEN1_middle_N48), .CK(clk), .Q(
Q_middle[48]) );
DFFQX1TS GEN1_middle_pdt_int_reg_35_ ( .D(GEN1_middle_N35), .CK(clk), .Q(
Q_middle[35]) );
DFFHQX4TS GEN1_middle_pdt_int_reg_41_ ( .D(GEN1_middle_N41), .CK(clk), .Q(
Q_middle[41]) );
OAI21X1TS U113 ( .A0(n7141), .A1(n217), .B0(n7140), .Y(n7144) );
OAI21X1TS U114 ( .A0(n315), .A1(n5175), .B0(n5174), .Y(n350) );
CLKINVX2TS U115 ( .A(n641), .Y(n315) );
INVX2TS U116 ( .A(load_b_i), .Y(n8311) );
NOR2XLTS U117 ( .A(n7194), .B(n7193), .Y(n564) );
NOR2X1TS U118 ( .A(n7710), .B(n6571), .Y(n7166) );
NOR2X1TS U119 ( .A(n7185), .B(n7048), .Y(n7207) );
INVX2TS U120 ( .A(load_b_i), .Y(n8019) );
NAND2X1TS U121 ( .A(n490), .B(n6848), .Y(n476) );
NOR2X1TS U122 ( .A(n6765), .B(n6764), .Y(n7302) );
NAND2X1TS U123 ( .A(n7432), .B(n5046), .Y(n5019) );
NAND2X1TS U124 ( .A(n6848), .B(n492), .Y(n493) );
NAND2X1TS U125 ( .A(n4211), .B(n4210), .Y(n7559) );
NOR2X1TS U126 ( .A(n6440), .B(n6441), .Y(n7242) );
NOR2X1TS U127 ( .A(n6160), .B(n6159), .Y(n7319) );
NAND2X1TS U128 ( .A(n4213), .B(n4212), .Y(n7563) );
NAND2X1TS U129 ( .A(n6158), .B(n6157), .Y(n7328) );
NOR2X1TS U130 ( .A(n3205), .B(n3206), .Y(n6566) );
NOR2X1TS U131 ( .A(n4574), .B(n4575), .Y(n7493) );
NOR2BX1TS U132 ( .AN(n792), .B(n4211), .Y(n7498) );
NOR2X4TS U133 ( .A(n625), .B(n7152), .Y(n603) );
NOR2X6TS U134 ( .A(n7179), .B(n7173), .Y(n850) );
ADDFHX1TS U135 ( .A(n4764), .B(n4763), .CI(n4762), .CO(n4899), .S(n4896) );
NOR2X2TS U136 ( .A(n6579), .B(n3185), .Y(n6562) );
NAND2X1TS U137 ( .A(n3172), .B(n3171), .Y(n7162) );
NOR2X1TS U138 ( .A(n4585), .B(n4584), .Y(n7455) );
NAND2X1TS U139 ( .A(n4581), .B(n4580), .Y(n7477) );
NOR2X1TS U140 ( .A(n6450), .B(n6451), .Y(n6499) );
NAND2X1TS U141 ( .A(n3177), .B(n3178), .Y(n7149) );
NAND2X1TS U142 ( .A(n6771), .B(n6770), .Y(n7135) );
ADDFX1TS U143 ( .A(n5642), .B(n5641), .CI(n5640), .CO(n6155), .S(n6154) );
NAND2X1TS U144 ( .A(n2786), .B(n2785), .Y(n7879) );
NOR2X2TS U145 ( .A(n6447), .B(n6446), .Y(n7224) );
OAI21XLTS U146 ( .A0(n3119), .A1(n3121), .B0(n3122), .Y(n1487) );
NOR2X2TS U147 ( .A(n6453), .B(n6452), .Y(n6503) );
NOR2X2TS U148 ( .A(n3132), .B(n3133), .Y(n7862) );
NOR2X1TS U149 ( .A(n7371), .B(n7272), .Y(n417) );
INVX4TS U150 ( .A(n3160), .Y(n7723) );
NAND2X2TS U151 ( .A(n7143), .B(n1838), .Y(n3185) );
NAND2X2TS U152 ( .A(n7706), .B(n7711), .Y(n7152) );
NOR2X2TS U153 ( .A(n7354), .B(n7339), .Y(n373) );
NAND2X2TS U154 ( .A(n7771), .B(n7891), .Y(n7765) );
OAI21X1TS U155 ( .A0(n7372), .A1(n7272), .B0(n7273), .Y(n416) );
OAI21X1TS U156 ( .A0(n7339), .A1(n7355), .B0(n7340), .Y(n421) );
NAND2X1TS U157 ( .A(n3962), .B(n3961), .Y(n7584) );
NOR2X1TS U158 ( .A(n3737), .B(n3736), .Y(n7628) );
NOR2X1TS U159 ( .A(n6054), .B(n6055), .Y(n7272) );
OAI2BB1X1TS U160 ( .A0N(n4404), .A1N(n4403), .B0(n823), .Y(n4576) );
NAND2BX1TS U161 ( .AN(n372), .B(n6059), .Y(n7348) );
CMPR32X2TS U162 ( .A(n4966), .B(n4965), .C(n4964), .CO(n4986), .S(n4946) );
NOR2X1TS U163 ( .A(n7778), .B(n7920), .Y(n2328) );
CLKINVX2TS U164 ( .A(n7770), .Y(n2537) );
NOR2BX1TS U165 ( .AN(n418), .B(n6053), .Y(n7371) );
XOR2X1TS U166 ( .A(n801), .B(n5637), .Y(n5640) );
ADDFHX1TS U167 ( .A(n4401), .B(n4400), .CI(n4399), .CO(n4574), .S(n4217) );
XOR2X2TS U168 ( .A(n824), .B(n4402), .Y(n4575) );
CMPR32X2TS U169 ( .A(n6473), .B(n6472), .C(n6471), .CO(n6555), .S(n6491) );
CMPR32X2TS U170 ( .A(n4512), .B(n4511), .C(n4510), .CO(n4554), .S(n4568) );
CMPR32X2TS U171 ( .A(n4330), .B(n4329), .C(n4328), .CO(n4386), .S(n4389) );
CMPR32X2TS U172 ( .A(n4883), .B(n4882), .C(n4881), .CO(n4888), .S(n4891) );
NOR2X1TS U173 ( .A(n2534), .B(n2533), .Y(n7769) );
NAND2X1TS U174 ( .A(n147), .B(n148), .Y(n2758) );
NOR2X6TS U175 ( .A(n3172), .B(n3171), .Y(n7161) );
OAI2BB1X1TS U176 ( .A0N(n1767), .A1N(n1766), .B0(n784), .Y(n3162) );
CMPR32X2TS U177 ( .A(n6134), .B(n6133), .C(n6132), .CO(n6140), .S(n6139) );
CMPR32X2TS U178 ( .A(n6919), .B(n6918), .C(n6917), .CO(n7013), .S(n7004) );
NOR2X1TS U179 ( .A(n7633), .B(n7533), .Y(n3708) );
XOR2X2TS U180 ( .A(n785), .B(n1766), .Y(n3158) );
XOR2X2TS U181 ( .A(n4403), .B(n4404), .Y(n824) );
ADDFHX1TS U182 ( .A(n6137), .B(n6136), .CI(n6135), .CO(n6138), .S(n6063) );
ADDFX1TS U183 ( .A(n6753), .B(n6752), .CI(n6751), .CO(n6774), .S(n6755) );
CMPR32X2TS U184 ( .A(n6118), .B(n6117), .C(n6116), .CO(n6102), .S(n6119) );
CMPR32X2TS U185 ( .A(n4503), .B(n4502), .C(n4501), .CO(n4564), .S(n4560) );
CMPR32X2TS U186 ( .A(n5645), .B(n5644), .C(n5643), .CO(n5637), .S(n6066) );
CMPR32X2TS U187 ( .A(n6424), .B(n6423), .C(n6422), .CO(n6473), .S(n6420) );
CMPR32X2TS U188 ( .A(n4862), .B(n4861), .C(n4860), .CO(n4870), .S(n4883) );
OAI2BB1X2TS U189 ( .A0N(n3049), .A1N(n3048), .B0(n956), .Y(n3059) );
NOR2X1TS U190 ( .A(n3706), .B(n3705), .Y(n7533) );
INVX2TS U191 ( .A(n3119), .Y(n3120) );
OAI2BB1X2TS U192 ( .A0N(n133), .A1N(n2852), .B0(n901), .Y(n3055) );
NOR2X1TS U193 ( .A(n3710), .B(n3709), .Y(n7530) );
OAI21X1TS U194 ( .A0(n1766), .A1(n1767), .B0(n1765), .Y(n784) );
NOR2X2TS U195 ( .A(n3711), .B(n3712), .Y(n7616) );
NAND2BX2TS U196 ( .AN(n2304), .B(n689), .Y(n7928) );
XOR2X2TS U197 ( .A(n2919), .B(n2918), .Y(n746) );
ADDFHX1TS U198 ( .A(n4380), .B(n4379), .CI(n4378), .CO(n4559), .S(n4381) );
ADDFHX1TS U199 ( .A(n6436), .B(n6435), .CI(n6434), .CO(n6471), .S(n6439) );
ADDFHX1TS U200 ( .A(n6396), .B(n6395), .CI(n6394), .CO(n6419), .S(n6353) );
ADDFX1TS U201 ( .A(n6347), .B(n6346), .CI(n6345), .CO(n6371), .S(n6327) );
CMPR32X2TS U202 ( .A(n4500), .B(n4499), .C(n4498), .CO(n4532), .S(n4570) );
ADDFX1TS U203 ( .A(n5532), .B(n5531), .CI(n5530), .CO(n6252), .S(n5566) );
ADDFHX1TS U204 ( .A(n6476), .B(n6475), .CI(n6474), .CO(n6553), .S(n6472) );
ADDFHX1TS U205 ( .A(n4661), .B(n4660), .CI(n4659), .CO(n4671), .S(n4641) );
ADDFHX1TS U206 ( .A(n6036), .B(n6035), .CI(n6034), .CO(n6056), .S(n6055) );
OAI21X1TS U207 ( .A0(n7786), .A1(n7932), .B0(n7787), .Y(n690) );
ADDFHX1TS U208 ( .A(n4727), .B(n4726), .CI(n4725), .CO(n4757), .S(n4732) );
ADDFX1TS U209 ( .A(n6760), .B(n6759), .CI(n6758), .CO(n6769), .S(n6766) );
CMPR32X2TS U210 ( .A(n4317), .B(n4316), .C(n4315), .CO(n4380), .S(n4312) );
CMPR32X2TS U211 ( .A(n6215), .B(n6214), .C(n6213), .CO(n6266), .S(n6250) );
CMPR32X2TS U212 ( .A(n6192), .B(n6191), .C(n6190), .CO(n6251), .S(n6253) );
CMPR32X2TS U213 ( .A(n4085), .B(n4084), .C(n4083), .CO(n4395), .S(n4148) );
CMPR32X2TS U214 ( .A(n6242), .B(n6241), .C(n6240), .CO(n6263), .S(n6247) );
CMPR32X2TS U215 ( .A(n5546), .B(n5545), .C(n5544), .CO(n5530), .S(n5596) );
CMPR32X2TS U216 ( .A(n3851), .B(n3850), .C(n3849), .CO(n4200), .S(n3921) );
CMPR32X2TS U217 ( .A(n6356), .B(n6355), .C(n6354), .CO(n6436), .S(n6396) );
CMPR32X2TS U218 ( .A(n6320), .B(n6319), .C(n6318), .CO(n6395), .S(n6345) );
CMPR32X2TS U219 ( .A(n4291), .B(n4290), .C(n4289), .CO(n4363), .S(n4313) );
CMPR32X2TS U220 ( .A(n6299), .B(n6298), .C(n6297), .CO(n6346), .S(n6261) );
CMPR32X2TS U221 ( .A(n4537), .B(n4536), .C(n4535), .CO(n4606), .S(n4533) );
NAND2X1TS U222 ( .A(n2302), .B(n2301), .Y(n7783) );
OAI2BB1X1TS U223 ( .A0N(n2919), .A1N(n2918), .B0(n745), .Y(n3044) );
OAI2BB1X2TS U224 ( .A0N(n2520), .A1N(n2519), .B0(n726), .Y(n2530) );
OAI2BB1X1TS U225 ( .A0N(n2731), .A1N(n668), .B0(n667), .Y(n2720) );
OAI2BB1X2TS U226 ( .A0N(n1734), .A1N(n1733), .B0(n776), .Y(n1784) );
OAI2BB1X1TS U227 ( .A0N(n3092), .A1N(n3091), .B0(n859), .Y(n3113) );
CMPR32X2TS U228 ( .A(n4748), .B(n4747), .C(n4746), .CO(n4866), .S(n4734) );
ADDFX1TS U229 ( .A(n6335), .B(n6334), .CI(n6333), .CO(n6376), .S(n6332) );
OAI2BB1X1TS U230 ( .A0N(n6644), .A1N(n6643), .B0(n481), .Y(n6759) );
OAI2BB1X2TS U231 ( .A0N(n808), .A1N(n807), .B0(n3110), .Y(n806) );
NOR2X1TS U232 ( .A(n2297), .B(n2296), .Y(n7931) );
NOR2X2TS U233 ( .A(n2299), .B(n2298), .Y(n7786) );
XNOR2X1TS U234 ( .A(n2715), .B(n2717), .Y(n591) );
OAI21XLTS U235 ( .A0(n2426), .A1(n660), .B0(n659), .Y(n658) );
ADDFHX1TS U236 ( .A(n4333), .B(n4332), .CI(n4331), .CO(n4398), .S(n4394) );
XNOR2X2TS U237 ( .A(n594), .B(n1973), .Y(n2002) );
XOR2X2TS U238 ( .A(n2824), .B(n2825), .Y(n890) );
ADDFHX2TS U239 ( .A(n1654), .B(n1653), .CI(n1652), .CO(n1765), .S(n1657) );
ADDFHX1TS U240 ( .A(n4462), .B(n4461), .CI(n4460), .CO(n4557), .S(n4509) );
ADDFHX1TS U241 ( .A(n4366), .B(n4365), .CI(n4364), .CO(n4503), .S(n4362) );
ADDFX2TS U242 ( .A(n4494), .B(n4493), .CI(n4492), .CO(n4499), .S(n4556) );
ADDFX1TS U243 ( .A(n4353), .B(n4352), .CI(n4351), .CO(n4508), .S(n4378) );
CMPR32X2TS U244 ( .A(n4320), .B(n4319), .C(n4318), .CO(n4379), .S(n4328) );
CMPR32X2TS U245 ( .A(n4288), .B(n4287), .C(n4286), .CO(n4329), .S(n4390) );
ADDFX1TS U246 ( .A(n4747), .B(n4708), .CI(n4707), .CO(n4735), .S(n4729) );
CMPR32X2TS U247 ( .A(n4162), .B(n4161), .C(n4160), .CO(n4144), .S(n4188) );
CMPR32X2TS U248 ( .A(n5657), .B(n5656), .C(n5655), .CO(n6069), .S(n6106) );
CMPR32X2TS U249 ( .A(n5440), .B(n5439), .C(n5438), .CO(n6192), .S(n5436) );
CMPR32X2TS U250 ( .A(n5491), .B(n5490), .C(n5489), .CO(n5531), .S(n5567) );
OAI2BB1X2TS U251 ( .A0N(n2495), .A1N(n2494), .B0(n724), .Y(n2754) );
OAI2BB1X1TS U252 ( .A0N(n1753), .A1N(n1752), .B0(n780), .Y(n1776) );
CMPR32X2TS U253 ( .A(n3193), .B(n3192), .C(n3191), .CO(n5143), .S(n3194) );
NOR2X1TS U254 ( .A(n5997), .B(n5996), .Y(n7381) );
OAI21X1TS U255 ( .A0(n2716), .A1(n2717), .B0(n2715), .Y(n590) );
OAI21X1TS U256 ( .A0(n2918), .A1(n2919), .B0(n2917), .Y(n745) );
OAI2BB1X2TS U257 ( .A0N(n929), .A1N(n928), .B0(n1997), .Y(n927) );
OAI21X1TS U258 ( .A0(n668), .A1(n2731), .B0(n2730), .Y(n667) );
ADDFHX1TS U259 ( .A(n1436), .B(n1435), .CI(n1434), .CO(n1527), .S(n1460) );
ADDFHX1TS U260 ( .A(n2310), .B(n2309), .CI(n2308), .CO(n2056), .S(n2319) );
NAND2BXLTS U261 ( .AN(n510), .B(n6867), .Y(n6869) );
NAND2BXLTS U262 ( .AN(n518), .B(n6928), .Y(n6930) );
XOR2X2TS U263 ( .A(n150), .B(n2735), .Y(n2753) );
ADDFHX2TS U264 ( .A(n1640), .B(n1639), .CI(n1638), .CO(n1772), .S(n1654) );
ADDFHX1TS U265 ( .A(n2156), .B(n2155), .CI(n2154), .CO(n2298), .S(n2297) );
ADDFHX1TS U266 ( .A(n4120), .B(n4119), .CI(n4118), .CO(n4339), .S(n4146) );
XOR2X1TS U267 ( .A(n4355), .B(n4434), .Y(n4459) );
XOR2X1TS U268 ( .A(n6367), .B(n6611), .Y(n6408) );
XOR2X1TS U269 ( .A(n4358), .B(n4611), .Y(n4458) );
XOR2X1TS U270 ( .A(n3195), .B(n3196), .Y(n849) );
ADDFX1TS U271 ( .A(n5666), .B(n5665), .CI(n5664), .CO(n6068), .S(n6104) );
XOR2X2TS U272 ( .A(n595), .B(n1974), .Y(n594) );
ADDFHX2TS U273 ( .A(n2763), .B(n2762), .CI(n2761), .CO(n2756), .S(n2772) );
CMPR32X2TS U274 ( .A(n5608), .B(n5609), .C(n5610), .CO(n5611), .S(n5652) );
XOR2X1TS U275 ( .A(n1607), .B(n1606), .Y(n831) );
ADDFHX1TS U276 ( .A(n5810), .B(n5809), .CI(n5808), .CO(n6058), .S(n6057) );
CMPR32X2TS U277 ( .A(n4452), .B(n4437), .C(n4436), .CO(n4495), .S(n4505) );
CLKXOR2X2TS U278 ( .A(n4298), .B(n4242), .Y(n4365) );
CMPR32X2TS U279 ( .A(n2009), .B(n2008), .C(n2007), .CO(n2017), .S(n2044) );
CMPR32X2TS U280 ( .A(n3919), .B(n3918), .C(n3917), .CO(n3928), .S(n3946) );
CMPR32X2TS U281 ( .A(n3916), .B(n3915), .C(n3914), .CO(n3947), .S(n3936) );
CMPR32X2TS U282 ( .A(n1808), .B(n1807), .C(n1806), .CO(n1822), .S(n1817) );
CMPR32X2TS U283 ( .A(n4171), .B(n4170), .C(n4169), .CO(n4176), .S(n4195) );
NAND2X1TS U284 ( .A(n2286), .B(n2285), .Y(n7943) );
CMPR32X2TS U285 ( .A(n3681), .B(n3680), .C(n3679), .CO(n3682), .S(n3663) );
CMPR32X2TS U286 ( .A(n6641), .B(n6640), .C(n6639), .CO(n6760), .S(n6642) );
OAI2BB1X1TS U287 ( .A0N(n3071), .A1N(n803), .B0(n802), .Y(n3092) );
OAI2BB1X1TS U288 ( .A0N(n5828), .A1N(n5827), .B0(n443), .Y(n5809) );
CMPR32X2TS U289 ( .A(n3911), .B(n3910), .C(n3909), .CO(n3922), .S(n3940) );
NOR2BX2TS U290 ( .AN(n924), .B(n2286), .Y(n7942) );
OAI21X1TS U291 ( .A0(n2681), .A1(n2682), .B0(n2680), .Y(n635) );
OAI21X1TS U292 ( .A0(n1608), .A1(n1607), .B0(n1606), .Y(n830) );
XOR2X1TS U293 ( .A(n1753), .B(n1752), .Y(n357) );
ADDFHX1TS U294 ( .A(n1593), .B(n1592), .CI(n1591), .CO(n1621), .S(n1564) );
XNOR2X2TS U295 ( .A(n2424), .B(n680), .Y(n656) );
ADDFHX1TS U296 ( .A(n5807), .B(n5806), .CI(n5805), .CO(n5790), .S(n5808) );
ADDFHX2TS U297 ( .A(n3101), .B(n3100), .CI(n3099), .CO(n3111), .S(n3093) );
OAI21X1TS U298 ( .A0(n5109), .A1(n4296), .B0(n4295), .Y(n4298) );
ADDFHX1TS U299 ( .A(n3935), .B(n3934), .CI(n3933), .CO(n3941), .S(n3953) );
ADDFHX1TS U300 ( .A(n1473), .B(n1472), .CI(n1471), .CO(n1489), .S(n1436) );
ADDFHX1TS U301 ( .A(n1476), .B(n1475), .CI(n1474), .CO(n1488), .S(n1434) );
CMPR32X2TS U302 ( .A(n5396), .B(n5395), .C(n5394), .CO(n5435), .S(n5569) );
CMPR32X2TS U303 ( .A(n1542), .B(n1541), .C(n1540), .CO(n1568), .S(n1538) );
CMPR32X2TS U304 ( .A(n1617), .B(n1616), .C(n1615), .CO(n1628), .S(n1607) );
CMPR32X2TS U305 ( .A(n1602), .B(n1601), .C(n1600), .CO(n1639), .S(n1606) );
CMPR32X2TS U306 ( .A(n1445), .B(n1444), .C(n1443), .CO(n1481), .S(n1477) );
CMPR32X2TS U307 ( .A(n2054), .B(n2055), .C(n2053), .CO(n2310), .S(n2116) );
CMPR32X2TS U308 ( .A(n1725), .B(n1724), .C(n1723), .CO(n1749), .S(n1768) );
CMPR32X2TS U309 ( .A(n5769), .B(n5768), .C(n5767), .CO(n5787), .S(n5806) );
CMPR32X2TS U310 ( .A(n1682), .B(n1681), .C(n1680), .CO(n1729), .S(n1689) );
NOR2X1TS U311 ( .A(n5970), .B(n5969), .Y(n7287) );
CMPR32X2TS U312 ( .A(n1993), .B(n1992), .C(n1991), .CO(n2005), .S(n2038) );
OAI21X1TS U313 ( .A0(n2419), .A1(n2418), .B0(n2417), .Y(n678) );
OAI2BB1X2TS U314 ( .A0N(n700), .A1N(n699), .B0(n2512), .Y(n698) );
OAI21X1TS U315 ( .A0(n2833), .A1(n2834), .B0(n2832), .Y(n934) );
XNOR2X1TS U316 ( .A(n3071), .B(n805), .Y(n804) );
XOR2X2TS U317 ( .A(n669), .B(n2627), .Y(n668) );
XOR2X1TS U318 ( .A(n1587), .B(n1613), .Y(n1619) );
XOR2X1TS U319 ( .A(n818), .B(n2675), .Y(n2710) );
ADDFHX1TS U320 ( .A(n1720), .B(n1719), .CI(n1718), .CO(n1770), .S(n1759) );
ADDFHX1TS U321 ( .A(n1590), .B(n1589), .CI(n1588), .CO(n1618), .S(n1592) );
ADDFX2TS U322 ( .A(n2127), .B(n2126), .CI(n2125), .CO(n2308), .S(n2312) );
NOR2BX1TS U323 ( .AN(n5352), .B(n867), .Y(n866) );
ADDFX2TS U324 ( .A(n1637), .B(n1636), .CI(n1635), .CO(n1751), .S(n1638) );
ADDFHX1TS U325 ( .A(n1996), .B(n1995), .CI(n1994), .CO(n2004), .S(n2037) );
OAI21X1TS U326 ( .A0(n4431), .A1(n4519), .B0(n4430), .Y(n4432) );
CMPR32X2TS U327 ( .A(n2024), .B(n2023), .C(n2022), .CO(n2039), .S(n2309) );
XOR2X2TS U328 ( .A(n3867), .B(n3866), .Y(n4969) );
ADDFX2TS U329 ( .A(n1717), .B(n1716), .CI(n1715), .CO(n1728), .S(n1761) );
CMPR32X2TS U330 ( .A(n6744), .B(n6743), .C(n6742), .CO(n6799), .S(n6729) );
CMPR32X2TS U331 ( .A(n6743), .B(n6704), .C(n6703), .CO(n6730), .S(n6724) );
CMPR32X2TS U332 ( .A(n2069), .B(n2068), .C(n2067), .CO(n2118), .S(n2128) );
CMPR32X2TS U333 ( .A(n1677), .B(n1676), .C(n1675), .CO(n1731), .S(n1686) );
CMPR32X2TS U334 ( .A(n5995), .B(n5994), .C(n5993), .CO(n5996), .S(n5970) );
OAI2BB1X2TS U335 ( .A0N(n2951), .A1N(n2950), .B0(n978), .Y(n3083) );
NOR2XLTS U336 ( .A(n6383), .B(n6224), .Y(n867) );
XOR2X1TS U337 ( .A(n2628), .B(n2629), .Y(n669) );
OAI22X1TS U338 ( .A0(n2602), .A1(n1343), .B0(n1303), .B1(n231), .Y(n1410) );
OAI22X1TS U339 ( .A0(n127), .A1(n1959), .B0(n1958), .B1(n2962), .Y(n1995) );
OAI22X1TS U340 ( .A0(n949), .A1(n1642), .B0(n296), .B1(n1697), .Y(n1719) );
OAI22X1TS U341 ( .A0(n1586), .A1(n1452), .B0(n1497), .B1(n2641), .Y(n1492)
);
XOR2X1TS U342 ( .A(n2699), .B(n2698), .Y(n2708) );
OAI22X1TS U343 ( .A0(n142), .A1(n1415), .B0(n1414), .B1(n2962), .Y(n1445) );
ADDFHX2TS U344 ( .A(n2508), .B(n2507), .CI(n2506), .CO(n2521), .S(n2519) );
ADDFHX1TS U345 ( .A(n2723), .B(n2722), .CI(n2721), .CO(n2752), .S(n2735) );
OAI21X1TS U346 ( .A0(n308), .A1(n3865), .B0(n3864), .Y(n3867) );
ADDFHX1TS U347 ( .A(n2585), .B(n2584), .CI(n2583), .CO(n2804), .S(n2574) );
ADDFHX1TS U348 ( .A(n2091), .B(n2090), .CI(n2089), .CO(n2111), .S(n2137) );
ADDFHX1TS U349 ( .A(n3006), .B(n3005), .CI(n3004), .CO(n3084), .S(n3038) );
ADDFX2TS U350 ( .A(n2461), .B(n2460), .CI(n2459), .CO(n2670), .S(n2467) );
ADDFX1TS U351 ( .A(n1555), .B(n1554), .CI(n1553), .CO(n1593), .S(n1543) );
ADDFX2TS U352 ( .A(n1937), .B(n1936), .CI(n1935), .CO(n1919), .S(n1973) );
XOR2X2TS U353 ( .A(n3385), .B(n3384), .Y(n4665) );
CMPR32X2TS U354 ( .A(n1576), .B(n1575), .C(n1574), .CO(n1615), .S(n1580) );
ADDHX1TS U355 ( .A(Data_A_i[14]), .B(n3549), .CO(n3531), .S(n3561) );
CMPR32X2TS U356 ( .A(n2878), .B(n2877), .C(n2876), .CO(n3033), .S(n2915) );
CMPR32X2TS U357 ( .A(n2197), .B(n2196), .C(n2195), .CO(n2185), .S(n2203) );
CMPR32X2TS U358 ( .A(n2163), .B(n2162), .C(n2161), .CO(n2171), .S(n2186) );
CLKBUFX2TS U359 ( .A(n4321), .Y(n4623) );
CLKBUFX2TS U360 ( .A(n3553), .Y(n3522) );
INVX2TS U361 ( .A(n3318), .Y(n4431) );
INVX2TS U362 ( .A(n3270), .Y(n4370) );
CLKBUFX2TS U363 ( .A(n4465), .Y(n4308) );
AOI222XLTS U364 ( .A0(n4426), .A1(n3823), .B0(n3552), .B1(n4128), .C0(n4321),
.C1(n3644), .Y(n3533) );
BUFX6TS U365 ( .A(n317), .Y(n5106) );
OAI2BB1X1TS U366 ( .A0N(n2175), .A1N(n2177), .B0(n685), .Y(n2170) );
BUFX3TS U367 ( .A(n3199), .Y(n1833) );
NOR2BX1TS U368 ( .AN(n3267), .B(n3266), .Y(n3847) );
OAI22X1TS U369 ( .A0(n7674), .A1(n2976), .B0(n296), .B1(n2975), .Y(n3005) );
OAI22X1TS U370 ( .A0(n127), .A1(n1931), .B0(n1895), .B1(n2663), .Y(n1936) );
OA21XLTS U371 ( .A0(n6899), .A1(n6794), .B0(n6614), .Y(n479) );
OAI21X1TS U372 ( .A0(n344), .A1(n1610), .B0(n648), .Y(n1649) );
OAI22X1TS U373 ( .A0(n3204), .A1(n1432), .B0(n5149), .B1(n1431), .Y(n1439)
);
CMPR32X2TS U374 ( .A(n2985), .B(n2986), .C(n2987), .CO(n3012), .S(n3031) );
ADDFHX1TS U375 ( .A(n2954), .B(n2953), .CI(n2952), .CO(n3082), .S(n2983) );
OAI21X1TS U376 ( .A0(n308), .A1(n3412), .B0(n3413), .Y(n3224) );
ADDFX1TS U377 ( .A(n2947), .B(n2946), .CI(n2945), .CO(n2982), .S(n2979) );
XOR2X2TS U378 ( .A(n5507), .B(n5506), .Y(n6929) );
XOR2X2TS U379 ( .A(n4064), .B(n4063), .Y(n4995) );
XOR2X2TS U380 ( .A(n5251), .B(n5455), .Y(n498) );
CMPR32X2TS U381 ( .A(n2368), .B(n2367), .C(n2366), .CO(n2470), .S(n2414) );
INVX2TS U382 ( .A(n3198), .Y(n1809) );
INVX2TS U383 ( .A(n816), .Y(n3201) );
BUFX6TS U384 ( .A(n5182), .Y(n7674) );
BUFX3TS U385 ( .A(n2809), .Y(n2972) );
CLKBUFX2TS U386 ( .A(n4132), .Y(n4522) );
BUFX3TS U387 ( .A(n4810), .Y(n4613) );
NOR2X1TS U388 ( .A(n734), .B(n735), .Y(n1915) );
CLKBUFX2TS U389 ( .A(n5063), .Y(n4716) );
NAND2X1TS U390 ( .A(n1399), .B(n1398), .Y(n1419) );
CLKBUFX2TS U391 ( .A(n4810), .Y(n4749) );
INVX2TS U392 ( .A(n6984), .Y(n6963) );
BUFX4TS U393 ( .A(n5151), .Y(n826) );
BUFX3TS U394 ( .A(n4709), .Y(n4356) );
OAI22X1TS U395 ( .A0(n127), .A1(n2432), .B0(n2502), .B1(n2663), .Y(n2498) );
CLKXOR2X2TS U396 ( .A(n496), .B(n5429), .Y(n6856) );
OAI21X1TS U397 ( .A0(n3396), .A1(n3306), .B0(n3305), .Y(n787) );
OAI21X1TS U398 ( .A0(n308), .A1(n3365), .B0(n3364), .Y(n876) );
XOR2X2TS U399 ( .A(n5525), .B(n6546), .Y(n5624) );
XOR2X2TS U400 ( .A(n5267), .B(n5266), .Y(n6868) );
XOR2X1TS U401 ( .A(n3396), .B(n3269), .Y(n3270) );
ADDHXLTS U402 ( .A(n6829), .B(n5774), .CO(n5759), .S(n5819) );
XNOR2X1TS U403 ( .A(n3317), .B(n3316), .Y(n3318) );
XOR2X2TS U404 ( .A(n480), .B(n5298), .Y(n6899) );
INVX2TS U405 ( .A(n712), .Y(n309) );
CLKBUFX2TS U406 ( .A(n3447), .Y(n4348) );
BUFX3TS U407 ( .A(n2998), .Y(n2587) );
BUFX3TS U408 ( .A(n1955), .Y(n1586) );
BUFX3TS U409 ( .A(n4465), .Y(n4021) );
BUFX3TS U410 ( .A(n1598), .Y(n2641) );
INVX2TS U411 ( .A(n294), .Y(n295) );
INVX4TS U412 ( .A(n798), .Y(n308) );
CLKBUFX2TS U413 ( .A(n6850), .Y(n6268) );
CLKBUFX2TS U414 ( .A(n6705), .Y(n6323) );
BUFX4TS U415 ( .A(n2838), .Y(n5147) );
AO21XLTS U416 ( .A0(n2861), .A1(n2248), .B0(n2860), .Y(n2960) );
BUFX6TS U417 ( .A(n1296), .Y(n367) );
CLKBUFX2TS U418 ( .A(n297), .Y(n7034) );
INVX2TS U419 ( .A(n7202), .Y(n7199) );
CLKXOR2X2TS U420 ( .A(n5357), .B(n5356), .Y(n6522) );
OAI22X1TS U421 ( .A0(n312), .A1(n1906), .B0(n2444), .B1(n1905), .Y(n1940) );
OAI21X1TS U422 ( .A0(n5426), .A1(n5262), .B0(n5261), .Y(n5267) );
OAI21X1TS U423 ( .A0(n5426), .A1(n5407), .B0(n5406), .Y(n5412) );
XNOR2X1TS U424 ( .A(n314), .B(n262), .Y(n2664) );
XNOR2X1TS U425 ( .A(n3200), .B(n2596), .Y(n2597) );
XOR2X2TS U426 ( .A(n5312), .B(n5311), .Y(n6813) );
INVX2TS U427 ( .A(Data_A_i[17]), .Y(n4788) );
OAI21XLTS U428 ( .A0(n5447), .A1(n5379), .B0(n5378), .Y(n5384) );
ADDFHX1TS U429 ( .A(n2936), .B(n1401), .CI(n1400), .CO(n1421), .S(n3019) );
OAI21X1TS U430 ( .A0(n3396), .A1(n3314), .B0(n3313), .Y(n3317) );
INVX2TS U431 ( .A(n2101), .Y(n2911) );
CLKBUFX2TS U432 ( .A(n2352), .Y(n2361) );
INVX2TS U433 ( .A(n3198), .Y(n2866) );
INVX2TS U434 ( .A(n3198), .Y(n2503) );
CLKBUFX2TS U435 ( .A(n6970), .Y(n6484) );
INVX4TS U436 ( .A(n2398), .Y(n312) );
BUFX3TS U437 ( .A(n2809), .Y(n2444) );
CLKBUFX2TS U438 ( .A(n6923), .Y(n6312) );
NOR2X1TS U439 ( .A(n5180), .B(n164), .Y(n2936) );
BUFX3TS U440 ( .A(n6197), .Y(n6613) );
BUFX3TS U441 ( .A(n6960), .Y(n6815) );
INVX2TS U442 ( .A(n223), .Y(n224) );
BUFX3TS U443 ( .A(n2974), .Y(n2446) );
BUFX3TS U444 ( .A(n1858), .Y(n2941) );
NAND2X4TS U445 ( .A(n1494), .B(n862), .Y(n5182) );
BUFX3TS U446 ( .A(n1955), .Y(n2901) );
CLKINVX2TS U447 ( .A(n1494), .Y(n294) );
BUFX4TS U448 ( .A(n2809), .Y(n2869) );
BUFX4TS U449 ( .A(n1369), .Y(n2934) );
BUFX4TS U450 ( .A(n1494), .Y(n2578) );
BUFX3TS U451 ( .A(n2399), .Y(n2962) );
BUFX3TS U452 ( .A(n2655), .Y(n127) );
BUFX3TS U453 ( .A(n226), .Y(n2347) );
NOR2BX1TS U454 ( .AN(n3253), .B(n3252), .Y(n4463) );
XNOR2X1TS U455 ( .A(n1086), .B(n273), .Y(n2870) );
OAI21X1TS U456 ( .A0(n5426), .A1(n5307), .B0(n5306), .Y(n5312) );
NAND2BXLTS U457 ( .AN(n2481), .B(n131), .Y(n731) );
INVX2TS U458 ( .A(Data_A_i[47]), .Y(n6945) );
INVX2TS U459 ( .A(Data_A_i[50]), .Y(n6984) );
INVX2TS U460 ( .A(n2168), .Y(n2693) );
BUFX3TS U461 ( .A(n1369), .Y(n325) );
CLKBUFX2TS U462 ( .A(n2225), .Y(n2095) );
INVX6TS U463 ( .A(n816), .Y(n2862) );
CLKBUFX2TS U464 ( .A(n2352), .Y(n2927) );
BUFX3TS U465 ( .A(n2548), .Y(n2882) );
BUFX3TS U466 ( .A(n2548), .Y(n2568) );
CLKBUFX2TS U467 ( .A(n4438), .Y(n4823) );
BUFX3TS U468 ( .A(n1877), .Y(n2145) );
INVX4TS U469 ( .A(n598), .Y(n314) );
CLKBUFX2TS U470 ( .A(n2906), .Y(n2937) );
INVX2TS U471 ( .A(n2548), .Y(n7672) );
CLKBUFX2TS U472 ( .A(n3754), .Y(n4852) );
NOR2X1TS U473 ( .A(n3287), .B(n3219), .Y(n3221) );
NAND2BX1TS U474 ( .AN(n3320), .B(n3321), .Y(n3555) );
BUFX3TS U475 ( .A(n2861), .Y(n2246) );
CLKBUFX2TS U476 ( .A(n4438), .Y(n4976) );
BUFX3TS U477 ( .A(n6850), .Y(n6818) );
NOR2BX2TS U478 ( .AN(n3320), .B(n3319), .Y(n3552) );
BUFX3TS U479 ( .A(n2142), .Y(n2464) );
INVX2TS U480 ( .A(n2548), .Y(n5180) );
INVX2TS U481 ( .A(Data_A_i[23]), .Y(n5077) );
INVX2TS U482 ( .A(Data_A_i[20]), .Y(n4975) );
INVX2TS U483 ( .A(Data_A_i[44]), .Y(n6873) );
XNOR2X2TS U484 ( .A(Data_A_i[14]), .B(Data_A_i[15]), .Y(n3237) );
XNOR2X2TS U485 ( .A(Data_A_i[15]), .B(Data_A_i[16]), .Y(n3236) );
XNOR2X1TS U486 ( .A(Data_A_i[12]), .B(Data_A_i[13]), .Y(n3271) );
XOR2X2TS U487 ( .A(Data_A_i[17]), .B(Data_A_i[16]), .Y(n3238) );
INVX2TS U488 ( .A(n2212), .Y(n2894) );
BUFX3TS U489 ( .A(n2225), .Y(n2931) );
INVX3TS U490 ( .A(n2014), .Y(n2908) );
INVX2TS U491 ( .A(n2860), .Y(n2182) );
INVX2TS U492 ( .A(n665), .Y(n267) );
BUFX4TS U493 ( .A(n1816), .Y(n734) );
BUFX4TS U494 ( .A(n2795), .Y(n366) );
CLKINVX6TS U495 ( .A(n2912), .Y(n233) );
INVX4TS U496 ( .A(n2066), .Y(n2841) );
CLKBUFX2TS U497 ( .A(n4677), .Y(n4828) );
NAND2X4TS U498 ( .A(n2809), .B(n764), .Y(n2974) );
NOR2X2TS U499 ( .A(n5360), .B(n5359), .Y(n6414) );
NAND2BX2TS U500 ( .AN(n5359), .B(n5360), .Y(n5703) );
INVX2TS U501 ( .A(n160), .Y(n258) );
INVX4TS U502 ( .A(n1086), .Y(n1906) );
NAND2X2TS U503 ( .A(n1187), .B(n2225), .Y(n1369) );
INVX4TS U504 ( .A(n747), .Y(n598) );
CLKBUFX2TS U505 ( .A(n5695), .Y(n6465) );
NAND2X2TS U506 ( .A(n775), .B(n2399), .Y(n2655) );
NOR2X1TS U507 ( .A(n3412), .B(n3362), .Y(n3418) );
XOR2X2TS U508 ( .A(n1279), .B(n1288), .Y(n1289) );
XOR2X1TS U509 ( .A(n2838), .B(n2560), .Y(n894) );
INVX2TS U510 ( .A(Data_B_i[26]), .Y(n4091) );
INVX2TS U511 ( .A(Data_A_i[35]), .Y(n6544) );
XNOR2X1TS U512 ( .A(Data_A_i[48]), .B(Data_A_i[49]), .Y(n5290) );
NAND2XLTS U513 ( .A(n1867), .B(n2249), .Y(n1981) );
NOR2X1TS U514 ( .A(n5270), .B(n5269), .Y(n5746) );
NOR2X1TS U515 ( .A(n3315), .B(n3397), .Y(n3215) );
INVX6TS U516 ( .A(n1224), .Y(n2014) );
NOR2BX2TS U517 ( .AN(n3260), .B(n3259), .Y(n4677) );
CLKBUFX2TS U518 ( .A(Data_B_i[24]), .Y(n5074) );
INVX2TS U519 ( .A(n4807), .Y(n4712) );
NOR2X1TS U520 ( .A(n4714), .B(n4815), .Y(n3412) );
NAND2BX1TS U521 ( .AN(n5189), .B(n181), .Y(n5937) );
NOR2X1TS U522 ( .A(n6981), .B(n6967), .Y(n5333) );
NOR2X1TS U523 ( .A(n6981), .B(n6987), .Y(n5408) );
CLKBUFX2TS U524 ( .A(n6664), .Y(n6609) );
INVX4TS U525 ( .A(n4691), .Y(n4626) );
NAND2BX1TS U526 ( .AN(n5214), .B(n583), .Y(n5318) );
CLKBUFX2TS U527 ( .A(n2225), .Y(n2895) );
CLKBUFX2TS U528 ( .A(Data_B_i[25]), .Y(n5080) );
XOR2X2TS U529 ( .A(n747), .B(n1308), .Y(n775) );
NOR2X2TS U530 ( .A(n3242), .B(n3246), .Y(n3377) );
XNOR2X1TS U531 ( .A(Data_A_i[47]), .B(Data_A_i[48]), .Y(n5291) );
XOR2X1TS U532 ( .A(Data_A_i[50]), .B(Data_A_i[49]), .Y(n5292) );
XOR2X1TS U533 ( .A(Data_A_i[23]), .B(Data_A_i[22]), .Y(n3771) );
XNOR2X1TS U534 ( .A(Data_A_i[42]), .B(Data_A_i[43]), .Y(n5358) );
BUFX6TS U535 ( .A(n2248), .Y(n2609) );
INVX2TS U536 ( .A(n1867), .Y(n2961) );
BUFX8TS U537 ( .A(n5159), .Y(n816) );
NOR2X1TS U538 ( .A(n5238), .B(n5308), .Y(n5241) );
CLKBUFX2TS U539 ( .A(Data_B_i[51]), .Y(n6981) );
NOR2BX1TS U540 ( .AN(n5205), .B(n5204), .Y(n5699) );
CLKBUFX2TS U541 ( .A(Data_B_i[18]), .Y(n4785) );
NOR2X2TS U542 ( .A(n5206), .B(n5205), .Y(n6664) );
NOR2X1TS U543 ( .A(n4419), .B(n4483), .Y(n3352) );
BUFX3TS U544 ( .A(n5695), .Y(n6410) );
NOR2X1TS U545 ( .A(n5387), .B(n5397), .Y(n5301) );
NOR2X2TS U546 ( .A(n942), .B(n5337), .Y(n5840) );
BUFX3TS U547 ( .A(n986), .Y(n2249) );
CLKBUFX2TS U548 ( .A(Data_B_i[52]), .Y(n6968) );
NOR2BX1TS U549 ( .AN(n5254), .B(n5253), .Y(n5833) );
CLKBUFX2TS U550 ( .A(Data_B_i[52]), .Y(n6987) );
NOR2X1TS U551 ( .A(Data_B_i[10]), .B(Data_B_i[11]), .Y(n3397) );
XOR2X2TS U552 ( .A(n1322), .B(n1085), .Y(n1087) );
NAND2X1TS U553 ( .A(n305), .B(n717), .Y(n714) );
XNOR2X2TS U554 ( .A(Data_A_i[17]), .B(Data_A_i[18]), .Y(n3260) );
XOR2X2TS U555 ( .A(n1224), .B(n655), .Y(n654) );
NOR2X2TS U556 ( .A(n4688), .B(Data_B_i[11]), .Y(n3242) );
NOR2X2TS U557 ( .A(n4688), .B(Data_B_i[13]), .Y(n3246) );
XNOR2X2TS U558 ( .A(Data_A_i[32]), .B(Data_A_i[33]), .Y(n5269) );
BUFX3TS U559 ( .A(Data_B_i[16]), .Y(n4815) );
XOR2X1TS U560 ( .A(Data_A_i[35]), .B(Data_A_i[34]), .Y(n5270) );
XNOR2X2TS U561 ( .A(Data_A_i[45]), .B(Data_A_i[46]), .Y(n5277) );
CLKBUFX2TS U562 ( .A(Data_B_i[23]), .Y(n5060) );
CLKBUFX2TS U563 ( .A(Data_B_i[20]), .Y(n4934) );
CLKBUFX2TS U564 ( .A(Data_B_i[21]), .Y(n4972) );
XNOR2X2TS U565 ( .A(Data_A_i[18]), .B(Data_A_i[19]), .Y(n3259) );
NOR2X2TS U566 ( .A(Data_B_i[13]), .B(Data_B_i[14]), .Y(n3381) );
INVX2TS U567 ( .A(Data_A_i[11]), .Y(n4691) );
NOR2X1TS U568 ( .A(n5252), .B(n5254), .Y(n5870) );
NAND2X1TS U569 ( .A(n5381), .B(n5374), .Y(n5195) );
NAND3BX1TS U570 ( .AN(n503), .B(n5235), .C(n5234), .Y(n940) );
CLKINVX6TS U571 ( .A(n2168), .Y(n2905) );
CLKBUFX2TS U572 ( .A(n5219), .Y(n5913) );
BUFX3TS U573 ( .A(Data_B_i[50]), .Y(n6967) );
BUFX4TS U574 ( .A(Data_B_i[49]), .Y(n6959) );
CLKBUFX2TS U575 ( .A(Data_B_i[15]), .Y(n4714) );
XOR2X2TS U576 ( .A(n1178), .B(n1177), .Y(n1186) );
XNOR2X2TS U577 ( .A(Data_A_i[50]), .B(Data_A_i[51]), .Y(n5214) );
XNOR2X1TS U578 ( .A(Data_A_i[51]), .B(Data_A_i[52]), .Y(n5213) );
BUFX3TS U579 ( .A(Data_B_i[6]), .Y(n4301) );
BUFX3TS U580 ( .A(Data_B_i[9]), .Y(n4419) );
NAND2X1TS U581 ( .A(n1194), .B(n1193), .Y(n1195) );
NAND2XLTS U582 ( .A(n1010), .B(n1033), .Y(n1011) );
BUFX6TS U583 ( .A(Data_B_i[43]), .Y(n6825) );
OAI21X2TS U584 ( .A0(n1051), .A1(n704), .B0(n1050), .Y(n706) );
NAND2X2TS U585 ( .A(n305), .B(n755), .Y(n599) );
BUFX3TS U586 ( .A(Data_B_i[45]), .Y(n6870) );
NOR2X2TS U587 ( .A(Data_B_i[40]), .B(n6745), .Y(n5367) );
XNOR2X2TS U588 ( .A(Data_A_i[29]), .B(Data_A_i[30]), .Y(n5337) );
INVX4TS U589 ( .A(Data_A_i[53]), .Y(n7202) );
NAND2X1TS U590 ( .A(n1852), .B(n1851), .Y(n1853) );
NAND2XLTS U591 ( .A(n1077), .B(n1076), .Y(n1078) );
BUFX6TS U592 ( .A(Data_B_i[41]), .Y(n6745) );
BUFX6TS U593 ( .A(Data_B_i[42]), .Y(n6788) );
NOR2X1TS U594 ( .A(n1088), .B(n1109), .Y(n1093) );
INVX2TS U595 ( .A(Data_B_i[27]), .Y(n5219) );
BUFX4TS U596 ( .A(Data_B_i[39]), .Y(n6685) );
BUFX4TS U597 ( .A(Data_B_i[40]), .Y(n6659) );
NOR2X1TS U598 ( .A(Data_B_i[35]), .B(Data_B_i[34]), .Y(n5347) );
NOR2X1TS U599 ( .A(Data_B_i[31]), .B(Data_B_i[30]), .Y(n5283) );
NOR2X2TS U600 ( .A(n5472), .B(n5474), .Y(n5192) );
OR2X2TS U601 ( .A(Data_A_i[52]), .B(Data_A_i[25]), .Y(n1118) );
NOR2X1TS U602 ( .A(Data_B_i[29]), .B(Data_B_i[30]), .Y(n5209) );
INVX3TS U603 ( .A(n305), .Y(n597) );
INVX2TS U604 ( .A(n1332), .Y(n1866) );
OAI21X1TS U605 ( .A0(n1238), .A1(n1233), .B0(n1239), .Y(n1267) );
BUFX4TS U606 ( .A(Data_B_i[29]), .Y(n6168) );
OR2X2TS U607 ( .A(Data_B_i[52]), .B(Data_B_i[25]), .Y(n1294) );
OR2X2TS U608 ( .A(Data_A_i[51]), .B(Data_A_i[24]), .Y(n1114) );
OR2X2TS U609 ( .A(Data_B_i[51]), .B(Data_B_i[24]), .Y(n1302) );
NOR2X2TS U610 ( .A(Data_B_i[33]), .B(Data_B_i[32]), .Y(n5472) );
CLKINVX2TS U611 ( .A(n1248), .Y(n1198) );
NAND2X2TS U612 ( .A(n1122), .B(n1021), .Y(n535) );
NAND2X1TS U613 ( .A(Data_B_i[50]), .B(Data_B_i[23]), .Y(n1275) );
NAND2X1TS U614 ( .A(Data_A_i[51]), .B(Data_A_i[24]), .Y(n1045) );
NOR2X2TS U615 ( .A(Data_B_i[50]), .B(Data_B_i[23]), .Y(n1274) );
NAND2X2TS U616 ( .A(n812), .B(n811), .Y(n1315) );
NOR2X4TS U617 ( .A(n1126), .B(n1128), .Y(n1021) );
NOR2X1TS U618 ( .A(Data_A_i[50]), .B(Data_A_i[23]), .Y(n1052) );
NAND2X1TS U619 ( .A(Data_B_i[39]), .B(Data_B_i[12]), .Y(n1372) );
NAND2X1TS U620 ( .A(Data_A_i[48]), .B(Data_A_i[21]), .Y(n1076) );
NAND2X1TS U621 ( .A(Data_B_i[11]), .B(Data_B_i[38]), .Y(n1062) );
NOR2X4TS U622 ( .A(Data_B_i[36]), .B(Data_B_i[9]), .Y(n1385) );
NOR2X4TS U623 ( .A(Data_B_i[38]), .B(Data_B_i[11]), .Y(n1061) );
NOR2X4TS U624 ( .A(Data_B_i[33]), .B(Data_B_i[6]), .Y(n1126) );
NOR2X6TS U625 ( .A(Data_B_i[30]), .B(Data_B_i[3]), .Y(n1845) );
NOR2X6TS U626 ( .A(Data_B_i[32]), .B(Data_B_i[5]), .Y(n1364) );
NOR2X1TS U627 ( .A(Data_A_i[47]), .B(Data_A_i[20]), .Y(n1070) );
NOR2X2TS U628 ( .A(n847), .B(n846), .Y(n812) );
NOR2X2TS U629 ( .A(Data_A_i[48]), .B(Data_A_i[21]), .Y(n1075) );
NAND2X2TS U630 ( .A(Data_B_i[30]), .B(Data_B_i[3]), .Y(n1846) );
NAND2X2TS U631 ( .A(Data_B_i[33]), .B(Data_B_i[6]), .Y(n1125) );
NOR2X2TS U632 ( .A(Data_B_i[37]), .B(Data_B_i[10]), .Y(n1057) );
NOR2X2TS U633 ( .A(Data_B_i[31]), .B(Data_B_i[4]), .Y(n1358) );
NOR2X2TS U634 ( .A(Data_B_i[35]), .B(Data_B_i[8]), .Y(n1384) );
NOR2X2TS U635 ( .A(Data_A_i[49]), .B(Data_A_i[22]), .Y(n1318) );
NAND2X1TS U636 ( .A(Data_A_i[20]), .B(Data_A_i[47]), .Y(n1081) );
NOR2X4TS U637 ( .A(Data_B_i[29]), .B(Data_B_i[2]), .Y(n1843) );
NOR2X2TS U638 ( .A(n1031), .B(n1035), .Y(n1036) );
NOR2X4TS U639 ( .A(Data_B_i[40]), .B(Data_B_i[13]), .Y(n1378) );
NOR2X2TS U640 ( .A(Data_B_i[39]), .B(Data_B_i[12]), .Y(n1066) );
NOR2X2TS U641 ( .A(Data_A_i[45]), .B(Data_A_i[18]), .Y(n1031) );
OAI21X2TS U642 ( .A0(n1208), .A1(n1200), .B0(n1209), .Y(n609) );
NOR2X2TS U643 ( .A(n1188), .B(n1192), .Y(n1197) );
NAND2X4TS U644 ( .A(Data_A_i[2]), .B(Data_A_i[29]), .Y(n1863) );
NAND2X6TS U645 ( .A(Data_A_i[0]), .B(Data_A_i[27]), .Y(n640) );
NAND2X2TS U646 ( .A(Data_A_i[12]), .B(Data_A_i[39]), .Y(n1249) );
NOR2X4TS U647 ( .A(Data_A_i[40]), .B(Data_A_i[13]), .Y(n1192) );
NAND2X4TS U648 ( .A(n355), .B(Data_A_i[14]), .Y(n1200) );
NOR2X2TS U649 ( .A(Data_A_i[31]), .B(Data_A_i[4]), .Y(n1179) );
NOR2X4TS U650 ( .A(Data_A_i[42]), .B(Data_A_i[15]), .Y(n1208) );
NAND2X2TS U651 ( .A(Data_A_i[37]), .B(Data_A_i[10]), .Y(n1285) );
NOR2X2TS U652 ( .A(Data_A_i[39]), .B(Data_A_i[12]), .Y(n1188) );
NOR2X2TS U653 ( .A(Data_A_i[37]), .B(Data_A_i[10]), .Y(n1253) );
INVX2TS U654 ( .A(n2895), .Y(n112) );
INVX2TS U655 ( .A(n112), .Y(n113) );
INVX2TS U656 ( .A(n112), .Y(n114) );
INVX2TS U657 ( .A(n1199), .Y(n1202) );
INVX2TS U658 ( .A(n1318), .Y(n1320) );
NOR2XLTS U659 ( .A(n3381), .B(n3307), .Y(n3217) );
NOR2X1TS U660 ( .A(n1035), .B(n1034), .Y(n847) );
NOR2X1TS U661 ( .A(n6901), .B(Data_B_i[47]), .Y(n5259) );
INVX2TS U662 ( .A(n1027), .Y(n1025) );
INVX2TS U663 ( .A(n1304), .Y(n1306) );
INVX2TS U664 ( .A(n3871), .Y(n3872) );
NAND2X1TS U665 ( .A(Data_A_i[49]), .B(Data_A_i[22]), .Y(n1319) );
NOR2X1TS U666 ( .A(Data_A_i[43]), .B(Data_A_i[16]), .Y(n1304) );
INVX2TS U667 ( .A(n5456), .Y(n5239) );
OAI21XLTS U668 ( .A0(n5197), .A1(n5367), .B0(n5368), .Y(n5198) );
NAND2X1TS U669 ( .A(n6300), .B(n5936), .Y(n383) );
NAND2X1TS U670 ( .A(n5699), .B(n6281), .Y(n432) );
NAND2X1TS U671 ( .A(n6970), .B(n5912), .Y(n5222) );
AOI222XLTS U672 ( .A0(n6484), .A1(n5986), .B0(n6738), .B1(n288), .C0(n297),
.C1(n5936), .Y(n5220) );
NOR2X1TS U673 ( .A(n4815), .B(n4794), .Y(n3362) );
XNOR2X1TS U674 ( .A(Data_A_i[11]), .B(Data_A_i[12]), .Y(n3272) );
NAND2X1TS U675 ( .A(Data_A_i[46]), .B(Data_A_i[19]), .Y(n1033) );
NAND2X2TS U676 ( .A(Data_A_i[40]), .B(Data_A_i[13]), .Y(n1193) );
INVX2TS U677 ( .A(n1281), .Y(n1282) );
INVX2TS U678 ( .A(n4094), .Y(n4095) );
INVX2TS U679 ( .A(n1115), .Y(n1116) );
INVX2TS U680 ( .A(n5308), .Y(n5310) );
INVX2TS U681 ( .A(n5355), .Y(n5443) );
NAND2X1TS U682 ( .A(n5349), .B(n5346), .Y(n5377) );
OAI21XLTS U683 ( .A0(n4278), .A1(n4519), .B0(n4277), .Y(n4279) );
OAI2BB1X1TS U684 ( .A0N(n519), .A1N(n505), .B0(n5220), .Y(n5221) );
NAND2X1TS U685 ( .A(n6271), .B(n7033), .Y(n6272) );
INVX2TS U686 ( .A(n5470), .Y(n903) );
INVX2TS U687 ( .A(n5419), .Y(n5420) );
NOR2X1TS U688 ( .A(n5333), .B(n5408), .Y(n5456) );
OAI21XLTS U689 ( .A0(n3988), .A1(n5000), .B0(n3781), .Y(n3782) );
AOI222XLTS U690 ( .A0(n4262), .A1(n3644), .B0(n4522), .B1(n3772), .C0(n4613),
.C1(n3985), .Y(n3344) );
BUFX3TS U691 ( .A(n4709), .Y(n4448) );
INVX2TS U692 ( .A(n2066), .Y(n2899) );
XNOR2X2TS U693 ( .A(n2897), .B(n5179), .Y(n2898) );
XOR2X1TS U694 ( .A(n5179), .B(n2860), .Y(n2580) );
INVX2TS U695 ( .A(n2928), .Y(n2897) );
AND3X2TS U696 ( .A(n3261), .B(n3260), .C(n3259), .Y(n4850) );
BUFX3TS U697 ( .A(Data_B_i[12]), .Y(n4688) );
INVX2TS U698 ( .A(n1677), .Y(n1672) );
NAND2BX1TS U699 ( .AN(n1405), .B(n131), .Y(n739) );
OAI21X1TS U700 ( .A0(n5296), .A1(n5426), .B0(n5295), .Y(n480) );
OAI21X1TS U701 ( .A0(n5502), .A1(n5501), .B0(n5500), .Y(n5507) );
INVX2TS U702 ( .A(n5347), .Y(n5275) );
XNOR2X1TS U703 ( .A(Data_A_i[23]), .B(Data_A_i[24]), .Y(n3980) );
BUFX3TS U704 ( .A(Data_B_i[8]), .Y(n4483) );
OAI21XLTS U705 ( .A0(n4304), .A1(n4519), .B0(n4303), .Y(n4305) );
OAI21XLTS U706 ( .A0(n4621), .A1(n4812), .B0(n4089), .Y(n4090) );
NOR2XLTS U707 ( .A(n556), .B(n211), .Y(n5618) );
OAI21XLTS U708 ( .A0(n118), .A1(n5684), .B0(n5514), .Y(n5515) );
OAI21XLTS U709 ( .A0(n6740), .A1(n6623), .B0(n5392), .Y(n5393) );
OAI21XLTS U710 ( .A0(n6522), .A1(n5684), .B0(n5361), .Y(n5362) );
OAI21XLTS U711 ( .A0(n6780), .A1(n6707), .B0(n6229), .Y(n6230) );
OAI21XLTS U712 ( .A0(n6780), .A1(n6828), .B0(n6392), .Y(n6393) );
OAI21XLTS U713 ( .A0(n4304), .A1(n4269), .B0(n4139), .Y(n4140) );
OAI21XLTS U714 ( .A0(n4370), .A1(n4135), .B0(n3819), .Y(n3820) );
INVX2TS U715 ( .A(n3265), .Y(n3266) );
AOI222XLTS U716 ( .A0(n3447), .A1(n4618), .B0(n4309), .B1(n236), .C0(n4308),
.C1(n4133), .Y(n3292) );
OAI21XLTS U717 ( .A0(n3396), .A1(n3287), .B0(n3286), .Y(n3291) );
INVX2TS U718 ( .A(n3397), .Y(n3399) );
OAI22X1TS U719 ( .A0(n1453), .A1(n2939), .B0(n2938), .B1(n2937), .Y(n2953)
);
NOR2XLTS U720 ( .A(n7672), .B(n156), .Y(n2959) );
XNOR2X1TS U721 ( .A(n2483), .B(n2897), .Y(n2595) );
NAND2BX1TS U722 ( .AN(n2396), .B(n738), .Y(n737) );
BUFX3TS U723 ( .A(n1858), .Y(n2638) );
CLKBUFX2TS U724 ( .A(Data_B_i[17]), .Y(n4794) );
OAI21XLTS U725 ( .A0(n5109), .A1(n4776), .B0(n4775), .Y(n4777) );
OAI21XLTS U726 ( .A0(n4847), .A1(n4832), .B0(n4723), .Y(n4724) );
INVX2TS U727 ( .A(n1166), .Y(n1162) );
OAI21XLTS U728 ( .A0(n7036), .A1(n6828), .B0(n6827), .Y(n6830) );
XOR2X1TS U729 ( .A(n5335), .B(n5334), .Y(n6939) );
OAI21XLTS U730 ( .A0(n161), .A1(n5763), .B0(n5741), .Y(n5742) );
INVX2TS U731 ( .A(n500), .Y(n499) );
CLKBUFX2TS U732 ( .A(Data_B_i[25]), .Y(n5061) );
BUFX3TS U733 ( .A(n5063), .Y(n4993) );
OAI21XLTS U734 ( .A0(n4665), .A1(n5000), .B0(n4484), .Y(n4485) );
OAI21XLTS U735 ( .A0(n5109), .A1(n4408), .B0(n4407), .Y(n4409) );
OAI21XLTS U736 ( .A0(n6899), .A1(n6186), .B0(n5533), .Y(n5534) );
OAI21XLTS U737 ( .A0(n498), .A1(n6363), .B0(n6362), .Y(n6364) );
OAI21XLTS U738 ( .A0(n6939), .A1(n6363), .B0(n6188), .Y(n6189) );
INVX2TS U739 ( .A(n6873), .Y(n6829) );
OAI21XLTS U740 ( .A0(n6972), .A1(n6539), .B0(n6466), .Y(n6467) );
OAI21XLTS U741 ( .A0(GEN1_Final_add_x_1_n225), .A1(GEN1_Final_add_x_1_n229),
.B0(GEN1_Final_add_x_1_n226), .Y(n7985) );
XOR2X2TS U742 ( .A(n5412), .B(n5411), .Y(n6957) );
OAI21XLTS U743 ( .A0(n4744), .A1(n4408), .B0(n3765), .Y(n3766) );
OAI21XLTS U744 ( .A0(n4278), .A1(n4135), .B0(n3829), .Y(n3830) );
XOR2X2TS U745 ( .A(n787), .B(n3310), .Y(n4695) );
XOR2X2TS U746 ( .A(n3250), .B(n3249), .Y(n4621) );
OAI21XLTS U747 ( .A0(n3396), .A1(n3395), .B0(n3394), .Y(n3401) );
INVX2TS U748 ( .A(n3276), .Y(n3277) );
ADDFX2TS U749 ( .A(n2845), .B(n2844), .CI(n2843), .CO(n2892), .S(n2832) );
BUFX3TS U750 ( .A(n2399), .Y(n2663) );
BUFX4TS U751 ( .A(n1453), .Y(n2349) );
NAND2BX1TS U752 ( .AN(n2099), .B(n126), .Y(n872) );
CLKBUFX2TS U753 ( .A(n1981), .Y(n2562) );
OAI21XLTS U754 ( .A0(n5084), .A1(n4832), .B0(n4791), .Y(n4793) );
OAI21XLTS U755 ( .A0(n5028), .A1(n7120), .B0(n5029), .Y(n4920) );
OAI21XLTS U756 ( .A0(n5065), .A1(n4979), .B0(n4936), .Y(n4937) );
OAI21XLTS U757 ( .A0(n4847), .A1(n4979), .B0(n4799), .Y(n4800) );
OAI21XLTS U758 ( .A0(n4995), .A1(n4812), .B0(n4704), .Y(n4706) );
INVX2TS U759 ( .A(n1595), .Y(n628) );
ADDFX2TS U760 ( .A(n1651), .B(n1650), .CI(n1649), .CO(n1712), .S(n1645) );
OAI21XLTS U761 ( .A0(n6939), .A1(n6949), .B0(n6864), .Y(n6865) );
INVX2TS U762 ( .A(n1829), .Y(n1813) );
OAI21XLTS U763 ( .A0(n6780), .A1(n5941), .B0(n5716), .Y(n5717) );
INVX2TS U764 ( .A(n5828), .Y(n445) );
INVX2TS U765 ( .A(n5884), .Y(n944) );
XOR2X1TS U766 ( .A(n5779), .B(Data_A_i[41]), .Y(n415) );
CLKBUFX2TS U767 ( .A(Data_B_i[29]), .Y(n5986) );
OAI21XLTS U768 ( .A0(n5084), .A1(n4979), .B0(n4978), .Y(n4980) );
OAI21XLTS U769 ( .A0(GEN1_Final_add_x_1_n246), .A1(GEN1_Final_add_x_1_n250),
.B0(GEN1_Final_add_x_1_n247), .Y(n7983) );
INVX2TS U770 ( .A(Data_B_i[53]), .Y(n5455) );
OAI21XLTS U771 ( .A0(n4718), .A1(n3638), .B0(n3495), .Y(n3496) );
OAI21XLTS U772 ( .A0(n4621), .A1(n3671), .B0(n3536), .Y(n3537) );
OAI21XLTS U773 ( .A0(n3994), .A1(n4408), .B0(n191), .Y(n3604) );
INVX2TS U774 ( .A(n3233), .Y(n3296) );
OAI2BB1X1TS U775 ( .A0N(n2431), .A1N(n730), .B0(n728), .Y(n2511) );
BUFX4TS U776 ( .A(n2352), .Y(n2143) );
INVX2TS U777 ( .A(n6997), .Y(n6998) );
OAI21XLTS U778 ( .A0(n5109), .A1(n5108), .B0(n5107), .Y(n5111) );
NOR2XLTS U779 ( .A(n781), .B(n5148), .Y(n5185) );
XOR2X1TS U780 ( .A(n768), .B(n1722), .Y(n1769) );
OAI21XLTS U781 ( .A0(n567), .A1(n569), .B0(n565), .Y(n6668) );
XOR2X1TS U782 ( .A(n1765), .B(n1767), .Y(n785) );
INVX2TS U783 ( .A(n6584), .Y(n3183) );
OAI21XLTS U784 ( .A0(n6486), .A1(n5980), .B0(n5871), .Y(n5872) );
INVX2TS U785 ( .A(Data_A_i[32]), .Y(n6380) );
OAI21XLTS U786 ( .A0(n4605), .A1(n4606), .B0(n4604), .Y(n796) );
ADDFX2TS U787 ( .A(n6293), .B(n6292), .CI(n6291), .CO(n6328), .S(n6265) );
OAI21XLTS U788 ( .A0(GEN1_Final_add_x_1_n144), .A1(GEN1_Final_add_x_1_n150),
.B0(GEN1_Final_add_x_1_n145), .Y(n7999) );
OAI21XLTS U789 ( .A0(GEN1_Final_add_x_1_n336), .A1(GEN1_Final_add_x_1_n342),
.B0(GEN1_Final_add_x_1_n337), .Y(n7969) );
OAI21XLTS U790 ( .A0(n7045), .A1(n7044), .B0(n7060), .Y(n7046) );
NAND2X1TS U791 ( .A(n2756), .B(n146), .Y(n147) );
XOR2X2TS U792 ( .A(n725), .B(n2493), .Y(n2515) );
XOR2X1TS U793 ( .A(n1662), .B(n1663), .Y(n822) );
NAND2X1TS U794 ( .A(n7693), .B(n7697), .Y(n7157) );
OAI21X1TS U795 ( .A0(n3106), .A1(n696), .B0(n3105), .Y(n694) );
AOI21X1TS U796 ( .A0(n6581), .A1(n1838), .B0(n3183), .Y(n3184) );
OAI21XLTS U797 ( .A0(n4403), .A1(n4404), .B0(n4402), .Y(n823) );
OAI2BB1X1TS U798 ( .A0N(n5639), .A1N(n5638), .B0(n800), .Y(n5599) );
NOR2XLTS U799 ( .A(Q_left[20]), .B(S_B[47]), .Y(GEN1_Final_add_x_1_n119) );
INVX2TS U800 ( .A(n8136), .Y(n8139) );
NOR2XLTS U801 ( .A(Q_left[4]), .B(S_B[31]), .Y(GEN1_Final_add_x_1_n225) );
NOR2XLTS U802 ( .A(Q_right[43]), .B(S_B[16]), .Y(GEN1_Final_add_x_1_n301) );
NOR2XLTS U803 ( .A(Q_right[36]), .B(S_B[9]), .Y(GEN1_Final_add_x_1_n348) );
OAI21X1TS U804 ( .A0(n3125), .A1(n3124), .B0(n3126), .Y(n3116) );
OAI21X1TS U805 ( .A0(n3056), .A1(n3055), .B0(n3054), .Y(n743) );
INVX2TS U806 ( .A(n1869), .Y(n2860) );
NOR2XLTS U807 ( .A(n7021), .B(n7020), .Y(n7052) );
INVX2TS U808 ( .A(n6768), .Y(n478) );
INVX2TS U809 ( .A(n7407), .Y(n5098) );
INVX2TS U810 ( .A(n5021), .Y(n5032) );
INVX2TS U811 ( .A(n7188), .Y(n7027) );
NOR2XLTS U812 ( .A(n6057), .B(n6056), .Y(n7269) );
NOR2XLTS U813 ( .A(n5966), .B(n5965), .Y(n7391) );
AOI21X1TS U814 ( .A0(n373), .A1(n7351), .B0(n421), .Y(n368) );
ADDFX2TS U815 ( .A(n5566), .B(n5565), .CI(n5564), .CO(n6159), .S(n6158) );
OAI21X1TS U816 ( .A0(n6503), .A1(n7216), .B0(n6504), .Y(n6593) );
NOR2XLTS U817 ( .A(n6508), .B(n6586), .Y(n6512) );
OR2X1TS U818 ( .A(Q_left[24]), .B(S_B[51]), .Y(n8315) );
INVX2TS U819 ( .A(GEN1_Final_add_x_1_n119), .Y(n8184) );
INVX2TS U820 ( .A(n8149), .Y(n8152) );
INVX2TS U821 ( .A(n8121), .Y(n8124) );
NOR2XLTS U822 ( .A(Q_left[5]), .B(S_B[32]), .Y(GEN1_Final_add_x_1_n213) );
NOR2XLTS U823 ( .A(Q_left[1]), .B(S_B[28]), .Y(GEN1_Final_add_x_1_n236) );
INVX2TS U824 ( .A(GEN1_Final_add_x_1_n267), .Y(n8040) );
NOR2XLTS U825 ( .A(Q_right[45]), .B(S_B[18]), .Y(GEN1_Final_add_x_1_n291) );
OAI21XLTS U826 ( .A0(n8274), .A1(n8273), .B0(n8272), .Y(n8279) );
NOR2XLTS U827 ( .A(Q_right[35]), .B(S_B[8]), .Y(GEN1_Final_add_x_1_n351) );
NOR2XLTS U828 ( .A(GEN1_Final_add_x_1_n372), .B(GEN1_Final_add_x_1_n367),
.Y(n8239) );
NOR2X1TS U829 ( .A(n3973), .B(n7511), .Y(n3975) );
NOR2X1TS U830 ( .A(n3749), .B(n3748), .Y(n7592) );
NOR2X1TS U831 ( .A(n3663), .B(n3662), .Y(n7539) );
OAI21XLTS U832 ( .A0(n3994), .A1(n3638), .B0(n965), .Y(n3635) );
OAI2BB1X1TS U833 ( .A0N(n2778), .A1N(n2777), .B0(n2776), .Y(n2779) );
NAND2BX1TS U834 ( .AN(n7000), .B(n448), .Y(n7091) );
INVX2TS U835 ( .A(n5028), .Y(n5030) );
OR2X1TS U836 ( .A(n7424), .B(n7423), .Y(n7426) );
INVX2TS U837 ( .A(n5122), .Y(n5087) );
NAND2BX1TS U838 ( .AN(n770), .B(n3165), .Y(n7705) );
OR2X1TS U839 ( .A(n6806), .B(n6805), .Y(n6916) );
OR2X1TS U840 ( .A(n6841), .B(n6840), .Y(n6839) );
INVX2TS U841 ( .A(n7132), .Y(n7133) );
INVX2TS U842 ( .A(n7727), .Y(n7728) );
INVX2TS U843 ( .A(n641), .Y(n316) );
NAND2BX2TS U844 ( .AN(n422), .B(n6057), .Y(n7344) );
INVX2TS U845 ( .A(n7361), .Y(n7363) );
NOR2XLTS U846 ( .A(n5968), .B(n5967), .Y(n7386) );
OR2X1TS U847 ( .A(n5946), .B(n5945), .Y(n7296) );
NAND2X1TS U848 ( .A(n4585), .B(n4584), .Y(n7468) );
OAI21X2TS U849 ( .A0(n7562), .A1(n7559), .B0(n7563), .Y(n7576) );
INVX2TS U850 ( .A(n7327), .Y(n7329) );
INVX2TS U851 ( .A(n6586), .Y(n6496) );
INVX2TS U852 ( .A(n6589), .Y(n6559) );
OAI21XLTS U853 ( .A0(n8178), .A1(n8177), .B0(n8176), .Y(n8183) );
OAI21XLTS U854 ( .A0(n8164), .A1(n8152), .B0(n8151), .Y(n8157) );
OAI21XLTS U855 ( .A0(n8190), .A1(n8100), .B0(n8099), .Y(n8105) );
OAI21XLTS U856 ( .A0(n8288), .A1(n8287), .B0(n8286), .Y(n8293) );
INVX2TS U857 ( .A(n7208), .Y(n7209) );
NAND2X1TS U858 ( .A(n124), .B(n7585), .Y(n7511) );
INVX2TS U859 ( .A(n7608), .Y(n7610) );
INVX2TS U860 ( .A(n7633), .Y(n7635) );
NOR2XLTS U861 ( .A(n3650), .B(n3649), .Y(n7653) );
NAND2X1TS U862 ( .A(n2304), .B(n2303), .Y(n7927) );
NAND2X1TS U863 ( .A(n2292), .B(n2291), .Y(n7792) );
INVX2TS U864 ( .A(n7804), .Y(n2260) );
OAI21XLTS U865 ( .A0(n7558), .A1(n4927), .B0(n4926), .Y(n4949) );
OAI21XLTS U866 ( .A0(n7558), .A1(n5130), .B0(n5129), .Y(n5135) );
OAI21XLTS U867 ( .A0(n7375), .A1(n7371), .B0(n7372), .Y(n7276) );
INVX2TS U868 ( .A(n7277), .Y(n7367) );
NOR2XLTS U869 ( .A(n7402), .B(n7401), .Y(n7297) );
OAI21XLTS U870 ( .A0(n7440), .A1(n7497), .B0(n7439), .Y(n7445) );
OAI21XLTS U871 ( .A0(n7335), .A1(n7254), .B0(n7253), .Y(n7257) );
OAI21XLTS U872 ( .A0(n7246), .A1(n7242), .B0(n7243), .Y(n7241) );
OAI21XLTS U873 ( .A0(n7246), .A1(n7232), .B0(n7231), .Y(n7236) );
AHHCINX2TS U874 ( .A(Q_left[43]), .CIN(GEN1_Final_add_x_1_n63), .S(
Result[97]), .CO(GEN1_Final_add_x_1_n62) );
INVX2TS U875 ( .A(load_b_i), .Y(n8297) );
CLKBUFX2TS U876 ( .A(n8019), .Y(n8256) );
OAI21XLTS U877 ( .A0(n7587), .A1(n7516), .B0(n7584), .Y(n7519) );
INVX2TS U878 ( .A(n7532), .Y(n7637) );
INVX2TS U879 ( .A(Data_B_i[0]), .Y(n3262) );
OR2X1TS U880 ( .A(n2302), .B(n2301), .Y(n115) );
CLKINVX3TS U881 ( .A(n2655), .Y(n2885) );
XOR2X1TS U882 ( .A(n3296), .B(n3235), .Y(n116) );
XNOR2X1TS U883 ( .A(n3283), .B(n3282), .Y(n117) );
XOR2X1TS U884 ( .A(n5325), .B(n5324), .Y(n118) );
XOR2X1TS U885 ( .A(n5342), .B(n5317), .Y(n119) );
OR2X1TS U886 ( .A(n7185), .B(n7193), .Y(n120) );
AND2X4TS U887 ( .A(n7706), .B(n7701), .Y(n121) );
INVX2TS U888 ( .A(n4418), .Y(n4242) );
INVX2TS U889 ( .A(n1069), .Y(n128) );
XNOR2X2TS U890 ( .A(n1068), .B(n1067), .Y(n1069) );
INVX2TS U891 ( .A(n713), .Y(n1322) );
OR2X2TS U892 ( .A(n4900), .B(n4901), .Y(n122) );
OR2X2TS U893 ( .A(n4903), .B(n4902), .Y(n123) );
OR2X2TS U894 ( .A(n3964), .B(n3963), .Y(n124) );
NOR2X1TS U895 ( .A(n3178), .B(n3177), .Y(n6579) );
INVX2TS U896 ( .A(n1279), .Y(n2101) );
OR2X2TS U897 ( .A(n6145), .B(n6144), .Y(n125) );
INVX2TS U898 ( .A(n734), .Y(n131) );
OAI21X4TS U899 ( .A0(n1133), .A1(n1139), .B0(n1134), .Y(n1281) );
INVX2TS U900 ( .A(n2931), .Y(n126) );
XNOR2X2TS U901 ( .A(n1186), .B(n1327), .Y(n2225) );
OAI22X2TS U902 ( .A0(n1902), .A1(n2562), .B0(n2344), .B1(n7812), .Y(n2369)
);
XNOR2X2TS U903 ( .A(n1666), .B(n252), .Y(n2973) );
BUFX6TS U904 ( .A(n2452), .Y(n2846) );
OAI22X2TS U905 ( .A0(n2482), .A1(n326), .B0(n2597), .B1(n2609), .Y(n2594) );
INVX1TS U906 ( .A(n7166), .Y(n7169) );
NAND4X2TS U907 ( .A(n3161), .B(n603), .C(n7150), .D(n7717), .Y(n620) );
INVX2TS U908 ( .A(n882), .Y(n5172) );
NOR2X4TS U909 ( .A(n3166), .B(n121), .Y(n7154) );
CLKINVX2TS U910 ( .A(n7883), .Y(n7884) );
OAI21X1TS U911 ( .A0(n310), .A1(n7210), .B0(n7209), .Y(n909) );
NOR2BX1TS U912 ( .AN(n7192), .B(n564), .Y(n563) );
NAND2X4TS U913 ( .A(n7697), .B(n3174), .Y(n625) );
OAI21X1TS U914 ( .A0(n216), .A1(n5035), .B0(n5034), .Y(n5039) );
NOR2X6TS U915 ( .A(n7153), .B(n7161), .Y(n3174) );
OAI21X1TS U916 ( .A0(n216), .A1(n7127), .B0(n7126), .Y(n875) );
INVX2TS U917 ( .A(n7705), .Y(n3166) );
INVX2TS U918 ( .A(n7191), .Y(n7010) );
NOR2X2TS U919 ( .A(n7109), .B(n494), .Y(n490) );
OR2X4TS U920 ( .A(n3182), .B(n3181), .Y(n1838) );
INVX1TS U921 ( .A(n2825), .Y(n888) );
INVX2TS U922 ( .A(n7230), .Y(n7231) );
CLKINVX2TS U923 ( .A(n6844), .Y(n7107) );
ADDFHX1TS U924 ( .A(n1750), .B(n1749), .CI(n1748), .CO(n1764), .S(n1779) );
XNOR2X1TS U925 ( .A(n1732), .B(n779), .Y(n1745) );
INVX2TS U926 ( .A(n4951), .Y(n4957) );
ADDFHX2TS U927 ( .A(n1527), .B(n1526), .CI(n1525), .CO(n1534), .S(n3119) );
ADDFHX1TS U928 ( .A(n3190), .B(n3189), .CI(n3188), .CO(n3206), .S(n3181) );
CLKINVX1TS U929 ( .A(n6587), .Y(n6508) );
ADDFX1TS U930 ( .A(n1691), .B(n1690), .CI(n1689), .CO(n1732), .S(n1726) );
CLKAND2X2TS U931 ( .A(n7091), .B(n7090), .Y(n183) );
XOR2X2TS U932 ( .A(n3194), .B(n849), .Y(n3189) );
AND2X2TS U933 ( .A(n6848), .B(n6847), .Y(n171) );
AND2X2TS U934 ( .A(n7069), .B(n7068), .Y(n208) );
NAND2X2TS U935 ( .A(n4894), .B(n4895), .Y(n7555) );
OAI21X1TS U936 ( .A0(n1722), .A1(n769), .B0(n1721), .Y(n767) );
AND2X2TS U937 ( .A(n7024), .B(n7061), .Y(n7026) );
INVX1TS U938 ( .A(n7310), .Y(n7312) );
OAI21X1TS U939 ( .A0(n1752), .A1(n1753), .B0(n1751), .Y(n780) );
AOI21X1TS U940 ( .A0(n7621), .A1(n7625), .B0(n3715), .Y(n3716) );
CLKINVX1TS U941 ( .A(n7605), .Y(n7589) );
NOR2X2TS U942 ( .A(n6155), .B(n6156), .Y(n7310) );
CLKINVX2TS U943 ( .A(n7260), .Y(n7251) );
CLKAND2X2TS U944 ( .A(n7432), .B(n7431), .Y(n177) );
INVX2TS U945 ( .A(n6062), .Y(n374) );
NAND2X2TS U946 ( .A(n6154), .B(n6153), .Y(n7307) );
CLKINVX2TS U947 ( .A(n4984), .Y(n5011) );
OAI21X1TS U948 ( .A0(n1962), .A1(n1963), .B0(n1961), .Y(n930) );
XOR2XLTS U949 ( .A(n5157), .B(n5158), .Y(n582) );
OAI21X1TS U950 ( .A0(n6250), .A1(n6251), .B0(n6249), .Y(n907) );
CLKINVX1TS U951 ( .A(n5014), .Y(n5016) );
OAI2BB1X2TS U952 ( .A0N(n2834), .A1N(n2833), .B0(n934), .Y(n2890) );
NAND2BX2TS U953 ( .AN(n936), .B(n6029), .Y(n7358) );
XOR2X1TS U954 ( .A(n7395), .B(n7394), .Y(GEN1_left_N6) );
INVX2TS U955 ( .A(n6028), .Y(n936) );
ADDFHX1TS U956 ( .A(n5603), .B(n5602), .CI(n5601), .CO(n5595), .S(n5642) );
ADDFHX1TS U957 ( .A(n6069), .B(n6068), .CI(n6067), .CO(n5667), .S(n6103) );
ADDFHX1TS U958 ( .A(n5437), .B(n5436), .CI(n5435), .CO(n6254), .S(n5562) );
ADDFHX1TS U959 ( .A(n6550), .B(n6549), .CI(n6548), .CO(n6603), .S(n6556) );
ADDFHX1TS U960 ( .A(n3735), .B(n3734), .CI(n3733), .CO(n3736), .S(n3714) );
INVX1TS U961 ( .A(n7539), .Y(n7541) );
ADDFHX1TS U962 ( .A(n5594), .B(n5593), .CI(n5592), .CO(n5602), .S(n5643) );
INVX1TS U963 ( .A(n7381), .Y(n7383) );
XOR2X1TS U964 ( .A(n6990), .B(n6989), .Y(n7031) );
XOR2X1TS U965 ( .A(n5468), .B(n905), .Y(n5487) );
INVX1TS U966 ( .A(n5755), .Y(n835) );
XOR2X1TS U967 ( .A(n4752), .B(n4813), .Y(n4864) );
BUFX3TS U968 ( .A(n2863), .Y(n5160) );
XOR2X1TS U969 ( .A(n3799), .B(n4297), .Y(n3909) );
OAI21XLTS U970 ( .A0(n8059), .A1(GEN1_Final_add_x_1_n249), .B0(
GEN1_Final_add_x_1_n250), .Y(n8062) );
OAI21XLTS U971 ( .A0(n8039), .A1(GEN1_Final_add_x_1_n270), .B0(
GEN1_Final_add_x_1_n271), .Y(n8042) );
OAI21X1TS U972 ( .A0(n6712), .A1(n6273), .B0(n5727), .Y(n5728) );
CLKINVX1TS U973 ( .A(n6972), .Y(n515) );
XOR2X1TS U974 ( .A(n3768), .B(n4712), .Y(n4168) );
NOR2X1TS U975 ( .A(n5180), .B(n128), .Y(n1651) );
OAI21X1TS U976 ( .A0(n6957), .A1(n6186), .B0(n5484), .Y(n5485) );
OAI21X1TS U977 ( .A0(n6712), .A1(n6623), .B0(n5401), .Y(n5402) );
XOR2X1TS U978 ( .A(n5552), .B(n6708), .Y(n5594) );
OAI21X1TS U979 ( .A0(n4370), .A1(n3671), .B0(n3622), .Y(n206) );
XOR2X1TS U980 ( .A(n6487), .B(n6940), .Y(n6516) );
OAI21XLTS U981 ( .A0(n8310), .A1(GEN1_Final_add_x_1_n291), .B0(
GEN1_Final_add_x_1_n292), .Y(n8018) );
OAI21X1TS U982 ( .A0(n6486), .A1(n6004), .B0(n5891), .Y(n5892) );
XOR2XLTS U983 ( .A(n7659), .B(n7658), .Y(GEN1_right_N2) );
OAI21X1TS U984 ( .A0(n6522), .A1(n6521), .B0(n6520), .Y(n6523) );
OAI21X1TS U985 ( .A0(n6486), .A1(n6521), .B0(n6485), .Y(n6487) );
XOR2X1TS U986 ( .A(n5837), .B(n5989), .Y(n5866) );
INVX2TS U987 ( .A(n5510), .Y(n5224) );
INVX2TS U988 ( .A(n128), .Y(n273) );
OAI21X1TS U989 ( .A0(n6486), .A1(n5875), .B0(n5747), .Y(n5748) );
INVX4TS U990 ( .A(n458), .Y(n5426) );
OAI21X1TS U991 ( .A0(n161), .A1(n6386), .B0(n5293), .Y(n5294) );
OAI21X1TS U992 ( .A0(n6235), .A1(n6073), .B0(n5799), .Y(n5800) );
OAI21X1TS U993 ( .A0(n6235), .A1(n5875), .B0(n5836), .Y(n5837) );
OAI21X1TS U994 ( .A0(n179), .A1(n5980), .B0(n5918), .Y(n5919) );
OAI21X1TS U995 ( .A0(n161), .A1(n6224), .B0(n5578), .Y(n5579) );
XOR2X1TS U996 ( .A(n584), .B(n6940), .Y(n5510) );
INVX2TS U997 ( .A(n155), .Y(n269) );
INVX2TS U998 ( .A(n4099), .Y(n3864) );
INVX1TS U999 ( .A(n4093), .Y(n3865) );
CLKINVX2TS U1000 ( .A(n3855), .Y(n3870) );
XOR2X1TS U1001 ( .A(n5899), .B(n5989), .Y(n5924) );
OAI21X1TS U1002 ( .A0(n3994), .A1(n4625), .B0(n982), .Y(n3554) );
INVX1TS U1003 ( .A(n8064), .Y(n8067) );
CLKINVX1TS U1004 ( .A(n990), .Y(n505) );
OAI21X1TS U1005 ( .A0(n3994), .A1(n4852), .B0(n3231), .Y(n3232) );
NAND2XLTS U1006 ( .A(n424), .B(n6336), .Y(n429) );
OAI21X1TS U1007 ( .A0(n3302), .A1(n3381), .B0(n3382), .Y(n3303) );
NAND2XLTS U1008 ( .A(n4465), .B(n5105), .Y(n4407) );
INVX2TS U1009 ( .A(n8122), .Y(n8123) );
INVX2TS U1010 ( .A(n8150), .Y(n8151) );
NAND2XLTS U1011 ( .A(n6625), .B(n6194), .Y(n466) );
INVX1TS U1012 ( .A(n3389), .Y(n3314) );
INVX1TS U1013 ( .A(n3377), .Y(n3301) );
INVX1TS U1014 ( .A(n3422), .Y(n3364) );
INVX1TS U1015 ( .A(n3418), .Y(n3365) );
NAND2XLTS U1016 ( .A(n6180), .B(n6660), .Y(n387) );
CLKINVX1TS U1017 ( .A(n5458), .Y(n5459) );
INVX2TS U1018 ( .A(n6874), .Y(n339) );
INVX1TS U1019 ( .A(GEN1_Final_add_x_1_n144), .Y(n8158) );
INVX1TS U1020 ( .A(GEN1_Final_add_x_1_n131), .Y(n8170) );
INVX1TS U1021 ( .A(GEN1_Final_add_x_1_n233), .Y(n8074) );
INVX1TS U1022 ( .A(GEN1_Final_add_x_1_n228), .Y(n8081) );
INVX1TS U1023 ( .A(GEN1_Final_add_x_1_n225), .Y(n8085) );
NAND2X2TS U1024 ( .A(n1036), .B(n1037), .Y(n811) );
AND2X2TS U1025 ( .A(n6989), .B(n291), .Y(n6687) );
INVX1TS U1026 ( .A(n3352), .Y(n3354) );
AND2X2TS U1027 ( .A(n6989), .B(n289), .Y(n6543) );
INVX1TS U1028 ( .A(n3412), .Y(n3414) );
INVX1TS U1029 ( .A(n3362), .Y(n3222) );
AND2X2TS U1030 ( .A(n6902), .B(n6168), .Y(n6232) );
AND2X2TS U1031 ( .A(n7199), .B(n6959), .Y(n6977) );
INVX1TS U1032 ( .A(n5408), .Y(n5410) );
INVX1TS U1033 ( .A(n3336), .Y(n3209) );
NAND2X1TS U1034 ( .A(Q_left[13]), .B(S_B[40]), .Y(GEN1_Final_add_x_1_n162)
);
NAND2X1TS U1035 ( .A(Q_right[43]), .B(S_B[16]), .Y(GEN1_Final_add_x_1_n302)
);
NOR2X1TS U1036 ( .A(Q_left[15]), .B(S_B[42]), .Y(GEN1_Final_add_x_1_n149) );
NOR2X1TS U1037 ( .A(Q_left[13]), .B(S_B[40]), .Y(GEN1_Final_add_x_1_n161) );
NAND2X1TS U1038 ( .A(Q_left[11]), .B(S_B[38]), .Y(GEN1_Final_add_x_1_n179)
);
NOR2X1TS U1039 ( .A(Q_left[12]), .B(S_B[39]), .Y(GEN1_Final_add_x_1_n173) );
NAND2X1TS U1040 ( .A(Q_left[10]), .B(S_B[37]), .Y(GEN1_Final_add_x_1_n186)
);
NAND2X1TS U1041 ( .A(Q_left[9]), .B(S_B[36]), .Y(GEN1_Final_add_x_1_n191) );
NOR2X1TS U1042 ( .A(Q_left[10]), .B(S_B[37]), .Y(GEN1_Final_add_x_1_n185) );
NAND2X1TS U1043 ( .A(Q_left[7]), .B(S_B[34]), .Y(GEN1_Final_add_x_1_n204) );
NAND2X1TS U1044 ( .A(Q_left[5]), .B(S_B[32]), .Y(GEN1_Final_add_x_1_n214) );
NOR2X1TS U1045 ( .A(Q_left[7]), .B(S_B[34]), .Y(GEN1_Final_add_x_1_n203) );
NOR2XLTS U1046 ( .A(Q_right[29]), .B(S_B[2]), .Y(GEN1_Final_add_x_1_n381) );
NAND2X1TS U1047 ( .A(Q_right[27]), .B(S_B[0]), .Y(GEN1_Final_add_x_1_n388)
);
NOR2X1TS U1048 ( .A(Q_right[30]), .B(S_B[3]), .Y(GEN1_Final_add_x_1_n378) );
NAND2X1TS U1049 ( .A(Q_right[29]), .B(S_B[2]), .Y(GEN1_Final_add_x_1_n382)
);
NAND2X1TS U1050 ( .A(Q_right[30]), .B(S_B[3]), .Y(GEN1_Final_add_x_1_n379)
);
NOR2X1TS U1051 ( .A(Q_right[31]), .B(S_B[4]), .Y(GEN1_Final_add_x_1_n372) );
NOR2X1TS U1052 ( .A(Q_right[33]), .B(S_B[6]), .Y(GEN1_Final_add_x_1_n362) );
NOR2X1TS U1053 ( .A(Q_right[32]), .B(S_B[5]), .Y(GEN1_Final_add_x_1_n367) );
NAND2X1TS U1054 ( .A(Q_right[31]), .B(S_B[4]), .Y(GEN1_Final_add_x_1_n373)
);
NAND2X1TS U1055 ( .A(Q_right[32]), .B(S_B[5]), .Y(GEN1_Final_add_x_1_n368)
);
NOR2X1TS U1056 ( .A(Q_right[34]), .B(S_B[7]), .Y(GEN1_Final_add_x_1_n359) );
NAND2X1TS U1057 ( .A(Q_right[33]), .B(S_B[6]), .Y(GEN1_Final_add_x_1_n363)
);
NAND2X1TS U1058 ( .A(Q_right[34]), .B(S_B[7]), .Y(GEN1_Final_add_x_1_n360)
);
NOR2X1TS U1059 ( .A(Q_right[37]), .B(S_B[10]), .Y(GEN1_Final_add_x_1_n341)
);
NAND2X1TS U1060 ( .A(Q_right[35]), .B(S_B[8]), .Y(GEN1_Final_add_x_1_n352)
);
NAND2X1TS U1061 ( .A(Q_right[36]), .B(S_B[9]), .Y(GEN1_Final_add_x_1_n349)
);
NAND2X1TS U1062 ( .A(Q_left[19]), .B(S_B[46]), .Y(GEN1_Final_add_x_1_n125)
);
NAND2X1TS U1063 ( .A(Q_right[37]), .B(S_B[10]), .Y(GEN1_Final_add_x_1_n342)
);
NAND2X1TS U1064 ( .A(Q_left[17]), .B(S_B[44]), .Y(GEN1_Final_add_x_1_n137)
);
NOR2X1TS U1065 ( .A(Q_left[19]), .B(S_B[46]), .Y(GEN1_Final_add_x_1_n124) );
NOR2X1TS U1066 ( .A(Q_left[17]), .B(S_B[44]), .Y(GEN1_Final_add_x_1_n136) );
NAND2X1TS U1067 ( .A(Q_left[15]), .B(S_B[42]), .Y(GEN1_Final_add_x_1_n150)
);
INVX1TS U1068 ( .A(n1181), .Y(n1183) );
CLKINVX2TS U1069 ( .A(n3315), .Y(n3392) );
NOR2X4TS U1070 ( .A(n1364), .B(n1358), .Y(n1122) );
INVX4TS U1071 ( .A(n7202), .Y(n6989) );
INVX2TS U1072 ( .A(n5219), .Y(n5912) );
INVX4TS U1073 ( .A(n6380), .Y(n6274) );
NAND2X4TS U1074 ( .A(Data_B_i[29]), .B(Data_B_i[2]), .Y(n1842) );
NOR2X1TS U1075 ( .A(Data_B_i[4]), .B(Data_B_i[5]), .Y(n3279) );
XOR2X1TS U1076 ( .A(GEN1_Final_add_x_1_n53), .B(Q_left[53]), .Y(Result[107])
);
XOR2XLTS U1077 ( .A(n7144), .B(n173), .Y(GEN1_middle_N49) );
XOR2X1TS U1078 ( .A(n7182), .B(n959), .Y(GEN1_middle_N37) );
XOR2X1TS U1079 ( .A(n7866), .B(n7865), .Y(GEN1_middle_N30) );
AOI21X2TS U1080 ( .A0(n7139), .A1(n7143), .B0(n6581), .Y(n6582) );
INVX1TS U1081 ( .A(n7854), .Y(n7855) );
NAND3X4TS U1082 ( .A(n616), .B(n614), .C(n620), .Y(n7139) );
NAND2X4TS U1083 ( .A(n615), .B(n351), .Y(n614) );
CLKINVX1TS U1084 ( .A(n129), .Y(n7873) );
NAND2X4TS U1085 ( .A(n850), .B(n7830), .Y(n3146) );
XNOR2X1TS U1086 ( .A(n909), .B(n7213), .Y(GEN1_left_N50) );
INVX1TS U1087 ( .A(n7847), .Y(n7849) );
OAI21X1TS U1088 ( .A0(n310), .A1(n120), .B0(n563), .Y(n486) );
INVX1TS U1089 ( .A(n7660), .Y(n5173) );
CLKINVX1TS U1090 ( .A(n6564), .Y(n6567) );
INVX2TS U1091 ( .A(n7173), .Y(n7835) );
OAI21X1TS U1092 ( .A0(n310), .A1(n7185), .B0(n7194), .Y(n6807) );
XNOR2X1TS U1093 ( .A(n875), .B(n7130), .Y(GEN1_right_N50) );
XNOR2X1TS U1094 ( .A(n5135), .B(n5134), .Y(GEN1_right_N51) );
NAND2X4TS U1095 ( .A(n682), .B(n681), .Y(n7771) );
OAI21X2TS U1096 ( .A0(n7688), .A1(n7161), .B0(n7162), .Y(n3173) );
AND2X2TS U1097 ( .A(n7150), .B(n7149), .Y(n175) );
OAI21X1TS U1098 ( .A0(n7558), .A1(n7119), .B0(n7118), .Y(n7123) );
INVX2TS U1099 ( .A(n7207), .Y(n7210) );
XOR2X1TS U1100 ( .A(n7557), .B(n216), .Y(GEN1_right_N37) );
OAI2BB1X1TS U1101 ( .A0N(n1968), .A1N(n1969), .B0(n922), .Y(n2427) );
XOR2X1TS U1102 ( .A(n7930), .B(n7929), .Y(GEN1_middle_N15) );
NOR2X4TS U1103 ( .A(n3154), .B(n3155), .Y(n7735) );
INVX3TS U1104 ( .A(n2536), .Y(n682) );
NAND2BX1TS U1105 ( .AN(n3059), .B(n3060), .Y(n3063) );
AND2X2TS U1106 ( .A(n578), .B(n7170), .Y(n172) );
INVX1TS U1107 ( .A(n2777), .Y(n2775) );
NOR2X4TS U1108 ( .A(n6757), .B(n489), .Y(n488) );
NAND2X2TS U1109 ( .A(n3180), .B(n3179), .Y(n7142) );
NAND2BX2TS U1110 ( .AN(n476), .B(n6843), .Y(n7185) );
AND2X2TS U1111 ( .A(n1838), .B(n6584), .Y(n967) );
OAI2BB1X1TS U1112 ( .A0N(n1805), .A1N(n1804), .B0(n885), .Y(n3180) );
OAI21X1TS U1113 ( .A0(n7568), .A1(n7579), .B0(n7580), .Y(n7569) );
INVX1TS U1114 ( .A(n7116), .Y(n7119) );
NAND2X2TS U1115 ( .A(n490), .B(n6844), .Y(n489) );
INVX1TS U1116 ( .A(n910), .Y(n7578) );
INVX1TS U1117 ( .A(n5100), .Y(n4926) );
XOR2X1TS U1118 ( .A(n1763), .B(n1764), .Y(n601) );
NAND2XLTS U1119 ( .A(n7116), .B(n7121), .Y(n5027) );
OAI21X1TS U1120 ( .A0(n3091), .A1(n3092), .B0(n3090), .Y(n859) );
INVX1TS U1121 ( .A(n7125), .Y(n7126) );
NAND2XLTS U1122 ( .A(n5049), .B(n122), .Y(n5053) );
INVX1TS U1123 ( .A(n7124), .Y(n7127) );
ADDFHX2TS U1124 ( .A(n2002), .B(n2001), .CI(n2000), .CO(n2333), .S(n2332) );
NAND2X2TS U1125 ( .A(n493), .B(n6847), .Y(n491) );
INVX2TS U1126 ( .A(n7466), .Y(n7458) );
OAI21X1TS U1127 ( .A0(n1804), .A1(n1805), .B0(n1803), .Y(n885) );
XOR2X1TS U1128 ( .A(n7941), .B(n7940), .Y(GEN1_middle_N11) );
XOR2X1TS U1129 ( .A(n3089), .B(n3088), .Y(n919) );
XOR2X1TS U1130 ( .A(n7620), .B(n7619), .Y(GEN1_right_N13) );
OAI21X1TS U1131 ( .A0(n803), .A1(n3071), .B0(n3070), .Y(n802) );
CLKAND2X2TS U1132 ( .A(n7114), .B(n7113), .Y(n188) );
NAND2X2TS U1133 ( .A(n373), .B(n7352), .Y(n369) );
XOR2X1TS U1134 ( .A(n7370), .B(n7369), .Y(GEN1_left_N14) );
XOR2X1TS U1135 ( .A(n7627), .B(n7626), .Y(GEN1_right_N14) );
OAI21X2TS U1136 ( .A0(n1727), .A1(n1728), .B0(n1726), .Y(n926) );
INVX1TS U1137 ( .A(n6843), .Y(n7108) );
INVX1TS U1138 ( .A(n7523), .Y(n7632) );
OAI2BB1X1TS U1139 ( .A0N(n2039), .A1N(n2038), .B0(n651), .Y(n2031) );
OAI21X1TS U1140 ( .A0(n494), .A1(n7110), .B0(n7135), .Y(n492) );
CLKINVX1TS U1141 ( .A(n7351), .Y(n7336) );
OAI2BB1X1TS U1142 ( .A0N(n3196), .A1N(n3195), .B0(n848), .Y(n5142) );
XOR2X2TS U1143 ( .A(n676), .B(n1997), .Y(n2000) );
CLKINVX1TS U1144 ( .A(n6593), .Y(n6510) );
CLKINVX1TS U1145 ( .A(n7554), .Y(n7556) );
INVX1TS U1146 ( .A(n7233), .Y(n7221) );
NAND2X2TS U1147 ( .A(n6592), .B(n6587), .Y(n6595) );
INVX2TS U1148 ( .A(n661), .Y(n660) );
CLKINVX1TS U1149 ( .A(n7324), .Y(n7316) );
CLKINVX1TS U1150 ( .A(n7446), .Y(n7436) );
XOR2X1TS U1151 ( .A(n7365), .B(n7364), .Y(GEN1_left_N13) );
OAI21X1TS U1152 ( .A0(n2038), .A1(n2039), .B0(n2037), .Y(n651) );
CLKINVX1TS U1153 ( .A(n5166), .Y(n844) );
INVX1TS U1154 ( .A(n1733), .Y(n778) );
XNOR2X1TS U1155 ( .A(n1733), .B(n1734), .Y(n779) );
NAND2X2TS U1156 ( .A(n6443), .B(n6442), .Y(n7238) );
OAI21X1TS U1157 ( .A0(n3195), .A1(n3196), .B0(n3194), .Y(n848) );
NOR2BX1TS U1158 ( .AN(n520), .B(n7277), .Y(n376) );
NAND2X2TS U1159 ( .A(n4577), .B(n4576), .Y(n7489) );
INVX2TS U1160 ( .A(n7498), .Y(n7561) );
ADDFHX2TS U1161 ( .A(n3036), .B(n3035), .CI(n3034), .CO(n3042), .S(n3029) );
AO21X1TS U1162 ( .A0(n7024), .A1(n7023), .B0(n7022), .Y(n7025) );
CLKAND2X2TS U1163 ( .A(n7061), .B(n7060), .Y(n209) );
AND2X2TS U1164 ( .A(n6839), .B(n6997), .Y(n180) );
INVX1TS U1165 ( .A(n7371), .Y(n7373) );
AND2X2TS U1166 ( .A(n7082), .B(n7081), .Y(n184) );
INVX1TS U1167 ( .A(n7931), .Y(n7933) );
INVX2TS U1168 ( .A(n2425), .Y(n680) );
CLKAND2X2TS U1169 ( .A(n6916), .B(n6808), .Y(n182) );
CLKINVX1TS U1170 ( .A(n7056), .Y(n7045) );
INVX1TS U1171 ( .A(n7354), .Y(n423) );
INVX1TS U1172 ( .A(n7272), .Y(n7274) );
XOR2X1TS U1173 ( .A(n7946), .B(n7945), .Y(GEN1_middle_N8) );
CLKINVX1TS U1174 ( .A(n5117), .Y(n5118) );
INVX1TS U1175 ( .A(n7063), .Y(n7098) );
CLKINVX1TS U1176 ( .A(n5120), .Y(n5123) );
INVX1TS U1177 ( .A(n7368), .Y(n378) );
AO21X1TS U1178 ( .A0(n312), .A1(n2869), .B0(n1906), .Y(n1792) );
CLKINVX1TS U1179 ( .A(n7060), .Y(n7023) );
CLKINVX1TS U1180 ( .A(n7067), .Y(n7069) );
OAI21X1TS U1181 ( .A0(n7380), .A1(n7376), .B0(n7377), .Y(n7285) );
INVX1TS U1182 ( .A(n7606), .Y(n7588) );
XOR2X1TS U1183 ( .A(n5156), .B(n582), .Y(n5166) );
XOR2X2TS U1184 ( .A(n2736), .B(n2737), .Y(n150) );
INVX1TS U1185 ( .A(n7592), .Y(n7594) );
AO21X1TS U1186 ( .A0(n5095), .A1(n5094), .B0(n5093), .Y(n5096) );
INVX1TS U1187 ( .A(n7600), .Y(n7602) );
OR2X2TS U1188 ( .A(n2446), .B(n1397), .Y(n1399) );
OAI2BB1X2TS U1189 ( .A0N(n6251), .A1N(n6250), .B0(n907), .Y(n6308) );
INVX1TS U1190 ( .A(n7597), .Y(n7598) );
INVX1TS U1191 ( .A(n7521), .Y(n7599) );
OAI2BB1X1TS U1192 ( .A0N(n6699), .A1N(n6698), .B0(n546), .Y(n6761) );
AND2X2TS U1193 ( .A(n7054), .B(n7053), .Y(n210) );
XOR2X1TS U1194 ( .A(n4604), .B(n797), .Y(n4598) );
OAI21X1TS U1195 ( .A0(n6643), .A1(n6644), .B0(n6642), .Y(n481) );
INVX2TS U1196 ( .A(n7530), .Y(n7615) );
INVX1TS U1197 ( .A(n7533), .Y(n7535) );
AO21X1TS U1198 ( .A0(n3199), .A1(n2998), .B0(n3198), .Y(n5154) );
XOR2X1TS U1199 ( .A(n6697), .B(n549), .Y(n6758) );
INVX1TS U1200 ( .A(n7628), .Y(n7630) );
OAI2BB1X1TS U1201 ( .A0N(n548), .A1N(n547), .B0(n6697), .Y(n546) );
XOR2X1TS U1202 ( .A(n7956), .B(n7955), .Y(GEN1_middle_N5) );
CLKINVX1TS U1203 ( .A(n5121), .Y(n5094) );
XNOR2X1TS U1204 ( .A(n455), .B(n6823), .Y(n6837) );
INVX1TS U1205 ( .A(n7281), .Y(n7283) );
OAI2BB1X1TS U1206 ( .A0N(n6824), .A1N(n6823), .B0(n454), .Y(n6911) );
OAI2BB1X1TS U1207 ( .A0N(n879), .A1N(n878), .B0(n3939), .Y(n877) );
XOR2X2TS U1208 ( .A(n2438), .B(n2439), .Y(n703) );
OAI2BB1X1TS U1209 ( .A0N(n5787), .A1N(n5786), .B0(n947), .Y(n5757) );
XOR2X1TS U1210 ( .A(n6643), .B(n6644), .Y(n482) );
XNOR2X1TS U1211 ( .A(n6822), .B(n6824), .Y(n455) );
XOR2X1TS U1212 ( .A(n5868), .B(n410), .Y(n6029) );
INVX2TS U1213 ( .A(n4191), .Y(n4192) );
OAI21X1TS U1214 ( .A0(n6823), .A1(n6824), .B0(n6822), .Y(n454) );
OAI2BB1X1TS U1215 ( .A0N(n4197), .A1N(n4196), .B0(n836), .Y(n4187) );
OAI21X1TS U1216 ( .A0(n5638), .A1(n5639), .B0(n5637), .Y(n800) );
OAI21X1TS U1217 ( .A0(n2628), .A1(n2629), .B0(n2627), .Y(n891) );
XOR2X1TS U1218 ( .A(n3939), .B(n880), .Y(n3943) );
XOR2X1TS U1219 ( .A(n6698), .B(n6699), .Y(n549) );
INVX1TS U1220 ( .A(n6024), .Y(n525) );
XOR2X1TS U1221 ( .A(n3940), .B(n3941), .Y(n880) );
OAI21X1TS U1222 ( .A0(n4196), .A1(n4197), .B0(n4195), .Y(n836) );
OAI21X1TS U1223 ( .A0(n5786), .A1(n5787), .B0(n5785), .Y(n947) );
XNOR2X1TS U1224 ( .A(n834), .B(n5753), .Y(n5756) );
XOR2X1TS U1225 ( .A(n5869), .B(n5867), .Y(n410) );
XOR2X1TS U1226 ( .A(n4605), .B(n4606), .Y(n797) );
XOR2X1TS U1227 ( .A(n7961), .B(n7960), .Y(GEN1_middle_N3) );
OR2X2TS U1228 ( .A(n7204), .B(n7203), .Y(n7206) );
OAI21X1TS U1229 ( .A0(n8084), .A1(GEN1_Final_add_x_1_n228), .B0(
GEN1_Final_add_x_1_n229), .Y(n8087) );
ADDFX1TS U1230 ( .A(n6296), .B(n6295), .CI(n6294), .CO(n6347), .S(n6291) );
ADDFX1TS U1231 ( .A(n4868), .B(n4867), .CI(n4866), .CO(n4881), .S(n4885) );
ADDFHX1TS U1232 ( .A(n4865), .B(n4864), .CI(n4863), .CO(n4882), .S(n4884) );
INVX2TS U1233 ( .A(n8169), .Y(n8178) );
XOR2X1TS U1234 ( .A(n6277), .B(n6701), .Y(n6333) );
XOR2X1TS U1235 ( .A(n3228), .B(n4297), .Y(n3938) );
XOR2X1TS U1236 ( .A(n6230), .B(n6611), .Y(n6296) );
XOR2X1TS U1237 ( .A(n3473), .B(n4468), .Y(n3527) );
INVX1TS U1238 ( .A(n228), .Y(n1668) );
ADDFHX1TS U1239 ( .A(n3499), .B(n3498), .CI(n3497), .CO(n3508), .S(n3529) );
XOR2X1TS U1240 ( .A(n6304), .B(n6611), .Y(n6319) );
XOR2X1TS U1241 ( .A(n6302), .B(n6412), .Y(n6320) );
XOR2X1TS U1242 ( .A(n4136), .B(n4813), .Y(n4154) );
XOR2X1TS U1243 ( .A(n6290), .B(n6289), .Y(n6342) );
XOR2X1TS U1244 ( .A(n3908), .B(n3672), .Y(n3933) );
XOR2X1TS U1245 ( .A(n6612), .B(n6611), .Y(n6647) );
XOR2X1TS U1246 ( .A(n4650), .B(n4844), .Y(n4675) );
XOR2X1TS U1247 ( .A(n3913), .B(n4297), .Y(n3948) );
XOR2X1TS U1248 ( .A(n4432), .B(n5110), .Y(n4451) );
XOR2X1TS U1249 ( .A(n6083), .B(Data_A_i[29]), .Y(n6110) );
NAND3X6TS U1250 ( .A(n600), .B(n599), .C(n752), .Y(n747) );
XOR2X1TS U1251 ( .A(n5728), .B(n6090), .Y(n5736) );
XOR2X1TS U1252 ( .A(n6378), .B(n6412), .Y(n6424) );
XOR2X1TS U1253 ( .A(n5534), .B(n6090), .Y(n5582) );
XOR2X1TS U1254 ( .A(n4327), .B(n5001), .Y(n4359) );
NAND2BX1TS U1255 ( .AN(n2549), .B(n139), .Y(n1905) );
XOR2X1TS U1256 ( .A(n3468), .B(n4242), .Y(n3497) );
OAI21X1TS U1257 ( .A0(n6957), .A1(n6949), .B0(n6894), .Y(n6896) );
OAI21X1TS U1258 ( .A0(n4797), .A1(n4296), .B0(n3798), .Y(n3799) );
OAI21X1TS U1259 ( .A0(n6957), .A1(n338), .B0(n6819), .Y(n6821) );
OAI21X1TS U1260 ( .A0(n4797), .A1(n5108), .B0(n4796), .Y(n4798) );
OAI21X1TS U1261 ( .A0(n4744), .A1(n4852), .B0(n4424), .Y(n4425) );
OAI21X1TS U1262 ( .A0(n4744), .A1(n4296), .B0(n3227), .Y(n3228) );
OAI21X1TS U1263 ( .A0(n4744), .A1(n5000), .B0(n4649), .Y(n4650) );
OAI21X1TS U1264 ( .A0(n6957), .A1(n6794), .B0(n6700), .Y(n6702) );
XOR2X1TS U1265 ( .A(n206), .B(n3672), .Y(n3680) );
INVX1TS U1266 ( .A(n6899), .Y(n512) );
NAND2X4TS U1267 ( .A(n597), .B(n750), .Y(n600) );
OAI21X1TS U1268 ( .A0(n6780), .A1(n6273), .B0(n6089), .Y(n6091) );
OAI21X1TS U1269 ( .A0(n6957), .A1(n6679), .B0(n6610), .Y(n6612) );
OAI21X1TS U1270 ( .A0(n4826), .A1(n5083), .B0(n4783), .Y(n4784) );
XOR2X1TS U1271 ( .A(n3577), .B(n3796), .Y(n3699) );
XOR2X1TS U1272 ( .A(n3521), .B(n4468), .Y(n3589) );
XOR2X1TS U1273 ( .A(n5771), .B(n6402), .Y(n5813) );
OAI21X1TS U1274 ( .A0(n7036), .A1(n6623), .B0(n6622), .Y(n570) );
INVX1TS U1275 ( .A(n6957), .Y(n516) );
OAI21X1TS U1276 ( .A0(n6813), .A1(n337), .B0(n6628), .Y(n6629) );
OAI21X1TS U1277 ( .A0(n4820), .A1(n4296), .B0(n3912), .Y(n3913) );
OAI21X1TS U1278 ( .A0(n4797), .A1(n4852), .B0(n4632), .Y(n4633) );
XOR2X1TS U1279 ( .A(n3312), .B(n303), .Y(n3444) );
OAI21X1TS U1280 ( .A0(n6712), .A1(n5941), .B0(n5794), .Y(n5795) );
XOR2X1TS U1281 ( .A(n5619), .B(n6708), .Y(n5655) );
OAI21X1TS U1282 ( .A0(n6957), .A1(n6363), .B0(n6288), .Y(n6290) );
OAI21X1TS U1283 ( .A0(n4744), .A1(n4625), .B0(n4048), .Y(n4049) );
NAND2BX1TS U1284 ( .AN(n2549), .B(n2841), .Y(n2065) );
OAI21X1TS U1285 ( .A0(n6939), .A1(n6539), .B0(n6377), .Y(n6378) );
OAI21X1TS U1286 ( .A0(n6899), .A1(n6539), .B0(n6301), .Y(n6302) );
INVX1TS U1287 ( .A(n606), .Y(n1710) );
OAI21X1TS U1288 ( .A0(n5084), .A1(n4467), .B0(n4466), .Y(n4469) );
XOR2X1TS U1289 ( .A(n4374), .B(n4444), .Y(n4473) );
OAI21X1TS U1290 ( .A0(n6813), .A1(n6707), .B0(n6303), .Y(n6304) );
XOR2X1TS U1291 ( .A(n4112), .B(n4548), .Y(n4258) );
XOR2X1TS U1292 ( .A(n4371), .B(n4970), .Y(n4474) );
OAI21X1TS U1293 ( .A0(n6957), .A1(n6082), .B0(n5413), .Y(n5414) );
OAI21X1TS U1294 ( .A0(n6813), .A1(n6401), .B0(n5415), .Y(n5416) );
OAI21X1TS U1295 ( .A0(n6780), .A1(n6623), .B0(n5236), .Y(n5237) );
OAI21X1TS U1296 ( .A0(n4941), .A1(n4541), .B0(n4354), .Y(n4355) );
NOR2X1TS U1297 ( .A(n5180), .B(n261), .Y(n1576) );
XOR2X1TS U1298 ( .A(n3759), .B(n4813), .Y(n4157) );
XOR2X1TS U1299 ( .A(n6285), .B(n7037), .Y(n6344) );
XOR2X1TS U1300 ( .A(n4300), .B(n4705), .Y(n4364) );
OAI21X1TS U1301 ( .A0(n4744), .A1(n4711), .B0(n4232), .Y(n4233) );
XOR2X1TS U1302 ( .A(n4042), .B(n4813), .Y(n4086) );
NAND2BX1TS U1303 ( .AN(n2251), .B(n2636), .Y(n2100) );
OAI21X1TS U1304 ( .A0(n4421), .A1(n3901), .B0(n3357), .Y(n3358) );
XOR2X1TS U1305 ( .A(n5663), .B(n6708), .Y(n6095) );
XOR2X1TS U1306 ( .A(n6074), .B(Data_A_i[38]), .Y(n6112) );
AO21X1TS U1307 ( .A0(n2145), .A1(n2352), .B0(n2928), .Y(n2965) );
OAI21X1TS U1308 ( .A0(n4520), .A1(n3686), .B0(n3513), .Y(n3514) );
XOR2X1TS U1309 ( .A(n6220), .B(n6963), .Y(n6279) );
XNOR2X1TS U1310 ( .A(n883), .B(n6546), .Y(n6517) );
XOR2X1TS U1311 ( .A(n5892), .B(n6274), .Y(n6041) );
XOR2X1TS U1312 ( .A(n6218), .B(n6217), .Y(n6280) );
XOR2X1TS U1313 ( .A(n5693), .B(n6005), .Y(n5743) );
XOR2X1TS U1314 ( .A(n4020), .B(n4548), .Y(n4080) );
XOR2X1TS U1315 ( .A(n5804), .B(n6402), .Y(n6037) );
XOR2X1TS U1316 ( .A(n5748), .B(n6402), .Y(n5793) );
INVX6TS U1317 ( .A(n705), .Y(n3198) );
OAI21X1TS U1318 ( .A0(n6284), .A1(n6224), .B0(n5518), .Y(n5519) );
XOR2X1TS U1319 ( .A(n6523), .B(n7037), .Y(n6632) );
XOR2X1TS U1320 ( .A(n5766), .B(n6274), .Y(n5796) );
OAI21X1TS U1321 ( .A0(n118), .A1(n5875), .B0(n5770), .Y(n5771) );
XOR2X1TS U1322 ( .A(n3524), .B(n3761), .Y(n3588) );
OAI21X1TS U1323 ( .A0(n4421), .A1(n4135), .B0(n3758), .Y(n3759) );
OAI21X1TS U1324 ( .A0(n4304), .A1(n3686), .B0(n3685), .Y(n3687) );
OAI21X1TS U1325 ( .A0(n118), .A1(n6004), .B0(n5843), .Y(n5844) );
OAI21XLTS U1326 ( .A0(n8190), .A1(GEN1_Final_add_x_1_n213), .B0(
GEN1_Final_add_x_1_n214), .Y(n8095) );
OAI21X1TS U1327 ( .A0(n6522), .A1(n6386), .B0(n6385), .Y(n6387) );
OR2X2TS U1328 ( .A(n2254), .B(n2253), .Y(n7809) );
INVX2TS U1329 ( .A(n128), .Y(n274) );
OAI21X1TS U1330 ( .A0(n6383), .A1(n6386), .B0(n6219), .Y(n6220) );
OAI21X1TS U1331 ( .A0(n308), .A1(n4059), .B0(n4058), .Y(n4064) );
OAI21X1TS U1332 ( .A0(n117), .A1(n4440), .B0(n4019), .Y(n4020) );
XOR2X1TS U1333 ( .A(n5345), .B(n6546), .Y(n5440) );
OAI21X1TS U1334 ( .A0(n6383), .A1(n5875), .B0(n5803), .Y(n5804) );
XOR2XLTS U1335 ( .A(n7402), .B(n7401), .Y(GEN1_left_N2) );
OAI21X1TS U1336 ( .A0(n6662), .A1(n5941), .B0(n5888), .Y(n5890) );
OAI21X1TS U1337 ( .A0(n6383), .A1(n5980), .B0(n5979), .Y(n5982) );
XOR2X1TS U1338 ( .A(n5685), .B(n6217), .Y(n6092) );
INVX1TS U1339 ( .A(n6619), .Y(n511) );
INVX1TS U1340 ( .A(n6662), .Y(n508) );
OAI21X1TS U1341 ( .A0(n117), .A1(n3671), .B0(n3651), .Y(n3652) );
INVX1TS U1342 ( .A(n3518), .Y(n3485) );
OAI21X1TS U1343 ( .A0(n6692), .A1(n6623), .B0(n5540), .Y(n5541) );
OAI21X1TS U1344 ( .A0(n6383), .A1(n6521), .B0(n6382), .Y(n6384) );
XOR2X1TS U1345 ( .A(n5511), .B(n5510), .Y(n5537) );
OAI21X2TS U1346 ( .A0(n308), .A1(n3876), .B0(n3875), .Y(n840) );
OAI21X1TS U1347 ( .A0(n117), .A1(n3901), .B0(n3523), .Y(n3524) );
XOR2X1TS U1348 ( .A(n5659), .B(n6217), .Y(n6097) );
XOR2X1TS U1349 ( .A(n5863), .B(n5989), .Y(n5879) );
INVX1TS U1350 ( .A(n5672), .Y(n5633) );
INVX1TS U1351 ( .A(n3814), .Y(n3783) );
XOR2X1TS U1352 ( .A(n5911), .B(n6005), .Y(n5953) );
OAI21X1TS U1353 ( .A0(n119), .A1(n6521), .B0(n5319), .Y(n5320) );
OAI21X1TS U1354 ( .A0(n4278), .A1(n3686), .B0(n3666), .Y(n3667) );
OAI21X1TS U1355 ( .A0(n6235), .A1(n6004), .B0(n5974), .Y(n5975) );
OAI21X1TS U1356 ( .A0(n119), .A1(n5763), .B0(n5762), .Y(n5764) );
OAI21X1TS U1357 ( .A0(n116), .A1(n3671), .B0(n3645), .Y(n3646) );
OAI21X1TS U1358 ( .A0(n5937), .A1(n6623), .B0(n970), .Y(n5850) );
NAND2X2TS U1359 ( .A(n461), .B(n459), .Y(n458) );
AND2X2TS U1360 ( .A(n5939), .B(n5981), .Y(n7300) );
OAI21X1TS U1361 ( .A0(n3326), .A1(n3325), .B0(n3324), .Y(n3331) );
INVX1TS U1362 ( .A(n5457), .Y(n5332) );
INVX4TS U1363 ( .A(n3241), .Y(n3396) );
AND2X2TS U1364 ( .A(n3636), .B(n3672), .Y(n7552) );
INVX2TS U1365 ( .A(n3837), .Y(n330) );
NOR2BX2TS U1366 ( .AN(n1316), .B(n1321), .Y(n717) );
XNOR2X1TS U1367 ( .A(n1368), .B(n1367), .Y(n155) );
INVX1TS U1368 ( .A(n6484), .Y(n562) );
NAND2BX1TS U1369 ( .AN(n560), .B(n298), .Y(n559) );
OAI21X1TS U1370 ( .A0(n3988), .A1(n4852), .B0(n3263), .Y(n3264) );
NOR2X1TS U1371 ( .A(n8273), .B(n7974), .Y(n7976) );
INVX1TS U1372 ( .A(n8065), .Y(n8066) );
INVX1TS U1373 ( .A(n8022), .Y(n8023) );
OAI21X1TS U1374 ( .A0(n3286), .A1(n3219), .B0(n3218), .Y(n3220) );
NAND2XLTS U1375 ( .A(n6300), .B(n5978), .Y(n401) );
OAI21X1TS U1376 ( .A0(n5937), .A1(n5941), .B0(n197), .Y(n5938) );
NAND2XLTS U1377 ( .A(n6300), .B(n5917), .Y(n404) );
XOR2X1TS U1378 ( .A(n5900), .B(n5989), .Y(n5905) );
NAND2XLTS U1379 ( .A(n6300), .B(n5984), .Y(n392) );
NAND2XLTS U1380 ( .A(n6300), .B(n6267), .Y(n386) );
NAND2BXLTS U1381 ( .AN(n560), .B(n6323), .Y(n557) );
INVX4TS U1382 ( .A(n1315), .Y(n1079) );
INVX1TS U1383 ( .A(n8174), .Y(n8177) );
NOR2X1TS U1384 ( .A(n1015), .B(n1013), .Y(n748) );
INVX1TS U1385 ( .A(n5305), .Y(n5232) );
NAND2BX1TS U1386 ( .AN(n560), .B(n6735), .Y(n555) );
NAND2XLTS U1387 ( .A(n4103), .B(n5105), .Y(n4104) );
NAND2XLTS U1388 ( .A(n6078), .B(n7033), .Y(n5466) );
NOR2X2TS U1389 ( .A(n1040), .B(n1080), .Y(n1347) );
NAND2XLTS U1390 ( .A(n5699), .B(n242), .Y(n427) );
AND2X2TS U1391 ( .A(n3297), .B(n3324), .Y(n3298) );
OAI21X2TS U1392 ( .A0(n1866), .A1(n1862), .B0(n1863), .Y(n1337) );
INVX1TS U1393 ( .A(GEN1_Final_add_x_1_n95), .Y(n8201) );
OAI21X1TS U1394 ( .A0(GEN1_Final_add_x_1_n311), .A1(GEN1_Final_add_x_1_n317),
.B0(GEN1_Final_add_x_1_n312), .Y(n7971) );
OAI21X1TS U1395 ( .A0(GEN1_Final_add_x_1_n288), .A1(GEN1_Final_add_x_1_n292),
.B0(GEN1_Final_add_x_1_n289), .Y(n7977) );
OAI21XLTS U1396 ( .A0(GEN1_Final_add_x_1_n385), .A1(GEN1_Final_add_x_1_n388),
.B0(GEN1_Final_add_x_1_n386), .Y(n8220) );
OAI21X1TS U1397 ( .A0(GEN1_Final_add_x_1_n378), .A1(GEN1_Final_add_x_1_n382),
.B0(GEN1_Final_add_x_1_n379), .Y(n7963) );
NOR2X1TS U1398 ( .A(GEN1_Final_add_x_1_n362), .B(GEN1_Final_add_x_1_n359),
.Y(n7966) );
OAI21X1TS U1399 ( .A0(GEN1_Final_add_x_1_n359), .A1(GEN1_Final_add_x_1_n363),
.B0(GEN1_Final_add_x_1_n360), .Y(n7965) );
OAI21X1TS U1400 ( .A0(GEN1_Final_add_x_1_n119), .A1(GEN1_Final_add_x_1_n125),
.B0(GEN1_Final_add_x_1_n120), .Y(n8001) );
CLKINVX2TS U1401 ( .A(GEN1_Final_add_x_1_n89), .Y(n8008) );
NAND2XLTS U1402 ( .A(n8315), .B(GEN1_Final_add_x_1_n89), .Y(n8210) );
OAI21X1TS U1403 ( .A0(GEN1_Final_add_x_1_n267), .A1(GEN1_Final_add_x_1_n271),
.B0(GEN1_Final_add_x_1_n268), .Y(n7979) );
NOR2X1TS U1404 ( .A(GEN1_Final_add_x_1_n190), .B(GEN1_Final_add_x_1_n185),
.Y(n8121) );
INVX1TS U1405 ( .A(GEN1_Final_add_x_1_n246), .Y(n8060) );
INVX2TS U1406 ( .A(GEN1_Final_add_x_1_n213), .Y(n8090) );
NAND2XLTS U1407 ( .A(n4018), .B(n3978), .Y(n3778) );
NAND2BXLTS U1408 ( .AN(n560), .B(n6339), .Y(n551) );
OR2X2TS U1409 ( .A(Data_B_i[28]), .B(n5912), .Y(n181) );
AND2X2TS U1410 ( .A(n7199), .B(n6942), .Y(n6983) );
AND2X2TS U1411 ( .A(n1111), .B(n1110), .Y(n168) );
NAND2BX1TS U1412 ( .AN(n5189), .B(n5217), .Y(n5212) );
AND2X2TS U1413 ( .A(n7419), .B(n4688), .Y(n4806) );
INVX1TS U1414 ( .A(n4060), .Y(n4062) );
CLKAND2X2TS U1415 ( .A(n4849), .B(Data_B_i[13]), .Y(n4748) );
AND2X2TS U1416 ( .A(n5085), .B(n4301), .Y(n4546) );
INVX1TS U1417 ( .A(n5495), .Y(n5297) );
INVX1TS U1418 ( .A(n1164), .Y(n1159) );
AND2X2TS U1419 ( .A(n1210), .B(n1209), .Y(n1211) );
AND2X2TS U1420 ( .A(n7419), .B(n5074), .Y(n7420) );
INVX1TS U1421 ( .A(n3325), .Y(n3297) );
INVX2TS U1422 ( .A(n1845), .Y(n1847) );
INVX2TS U1423 ( .A(n1096), .Y(n1098) );
INVX2TS U1424 ( .A(n1385), .Y(n1387) );
INVX2TS U1425 ( .A(n1035), .Y(n1010) );
INVX1TS U1426 ( .A(n1372), .Y(n1373) );
NAND2X1TS U1427 ( .A(n6942), .B(n6959), .Y(n5494) );
INVX1TS U1428 ( .A(n3234), .Y(n3278) );
NOR2X1TS U1429 ( .A(n5074), .B(n5080), .Y(n4060) );
NAND2BX1TS U1430 ( .AN(n5254), .B(n5252), .Y(n5832) );
INVX1TS U1431 ( .A(n5285), .Y(n5287) );
INVX1TS U1432 ( .A(n1052), .Y(n1054) );
INVX2TS U1433 ( .A(n1033), .Y(n846) );
INVX1TS U1434 ( .A(n3307), .Y(n3309) );
BUFX6TS U1435 ( .A(Data_B_i[48]), .Y(n6942) );
OR2X2TS U1436 ( .A(Data_B_i[2]), .B(Data_B_i[3]), .Y(n3338) );
NAND2X2TS U1437 ( .A(Data_A_i[42]), .B(Data_A_i[15]), .Y(n1209) );
XOR2XLTS U1438 ( .A(n6578), .B(n968), .Y(GEN1_middle_N53) );
INVX1TS U1439 ( .A(n7145), .Y(n7148) );
INVX1TS U1440 ( .A(n7726), .Y(n7729) );
OAI21X1TS U1441 ( .A0(n7894), .A1(n7760), .B0(n7759), .Y(n7763) );
XOR2X1TS U1442 ( .A(n7894), .B(n7893), .Y(GEN1_middle_N22) );
OAI21X1TS U1443 ( .A0(n7894), .A1(n7765), .B0(n7764), .Y(n7768) );
OAI21X1TS U1444 ( .A0(n7894), .A1(n7769), .B0(n7892), .Y(n7773) );
NOR2X4TS U1445 ( .A(n7746), .B(n3146), .Y(n3131) );
XOR2X1TS U1446 ( .A(n7897), .B(n7896), .Y(GEN1_middle_N20) );
XOR2X1TS U1447 ( .A(n7910), .B(n7909), .Y(GEN1_middle_N21) );
INVX1TS U1448 ( .A(n7765), .Y(n7756) );
XOR2XLTS U1449 ( .A(n486), .B(n214), .Y(GEN1_left_N53) );
XOR2XLTS U1450 ( .A(n7115), .B(n188), .Y(GEN1_left_N38) );
XOR2XLTS U1451 ( .A(n7137), .B(n189), .Y(GEN1_left_N40) );
XOR2X1TS U1452 ( .A(n7042), .B(n213), .Y(GEN1_left_N52) );
XOR2X1TS U1453 ( .A(n7062), .B(n209), .Y(GEN1_left_N49) );
OAI21X1TS U1454 ( .A0(n7175), .A1(n7173), .B0(n7834), .Y(n7176) );
NAND2X2TS U1455 ( .A(n2788), .B(n7872), .Y(n2790) );
XOR2X1TS U1456 ( .A(n7070), .B(n208), .Y(GEN1_left_N48) );
XOR2XLTS U1457 ( .A(n6807), .B(n182), .Y(GEN1_left_N42) );
XOR2XLTS U1458 ( .A(n571), .B(n171), .Y(GEN1_left_N41) );
OAI21X2TS U1459 ( .A0(n3185), .A1(n7149), .B0(n3184), .Y(n6564) );
INVX1TS U1460 ( .A(n7094), .Y(n7095) );
XOR2X1TS U1461 ( .A(n7246), .B(n7245), .Y(GEN1_left_N29) );
XNOR2X1TS U1462 ( .A(n5008), .B(n5007), .Y(GEN1_right_N49) );
OAI21X1TS U1463 ( .A0(n7246), .A1(n6502), .B0(n6501), .Y(n6507) );
OAI21X1TS U1464 ( .A0(n7246), .A1(n6455), .B0(n6454), .Y(n6498) );
OAI21X1TS U1465 ( .A0(n7246), .A1(n7215), .B0(n7214), .Y(n7219) );
NOR2X4TS U1466 ( .A(n7878), .B(n7874), .Y(n2788) );
OAI21X1TS U1467 ( .A0(n7246), .A1(n7223), .B0(n7222), .Y(n7228) );
AOI21X1TS U1468 ( .A0(n7208), .A1(n7212), .B0(n7049), .Y(n7050) );
INVX1TS U1469 ( .A(n7101), .Y(n7102) );
XNOR2X1TS U1470 ( .A(n5048), .B(n5047), .Y(GEN1_right_N43) );
XOR2X1TS U1471 ( .A(n7919), .B(n7918), .Y(GEN1_middle_N19) );
OAI21X2TS U1472 ( .A0(n3118), .A1(n3117), .B0(n3116), .Y(n3144) );
INVX6TS U1473 ( .A(n572), .Y(n7306) );
OAI21X1TS U1474 ( .A0(n6515), .A1(n7246), .B0(n6514), .Y(n6561) );
INVX1TS U1475 ( .A(n7688), .Y(n7158) );
INVX1TS U1476 ( .A(n7093), .Y(n7096) );
INVX1TS U1477 ( .A(n7100), .Y(n7103) );
NOR2X4TS U1478 ( .A(n3138), .B(n3139), .Y(n7747) );
XOR2X1TS U1479 ( .A(n7335), .B(n7334), .Y(GEN1_left_N21) );
XOR2X1TS U1480 ( .A(n7497), .B(n7496), .Y(GEN1_right_N29) );
OAI21X1TS U1481 ( .A0(n7497), .A1(n7483), .B0(n7482), .Y(n7487) );
OAI21X1TS U1482 ( .A0(n7497), .A1(n7467), .B0(n7466), .Y(n7471) );
OAI21X1TS U1483 ( .A0(n7497), .A1(n7493), .B0(n7494), .Y(n7492) );
NOR2X2TS U1484 ( .A(n6566), .B(n5170), .Y(n5171) );
OAI21X1TS U1485 ( .A0(n7497), .A1(n7460), .B0(n7459), .Y(n7465) );
OAI21X1TS U1486 ( .A0(n7497), .A1(n7475), .B0(n7474), .Y(n7480) );
AND2X2TS U1487 ( .A(n7143), .B(n7142), .Y(n173) );
NAND2X2TS U1488 ( .A(n3154), .B(n3155), .Y(n7736) );
OAI2BB1X2TS U1489 ( .A0N(n1663), .A1N(n1662), .B0(n821), .Y(n3157) );
XOR2X1TS U1490 ( .A(n7350), .B(n7349), .Y(GEN1_left_N18) );
XOR2X1TS U1491 ( .A(n7357), .B(n7356), .Y(GEN1_left_N19) );
XOR2X1TS U1492 ( .A(n7343), .B(n7342), .Y(GEN1_left_N20) );
OAI2BB1X2TS U1493 ( .A0N(n2742), .A1N(n2743), .B0(n664), .Y(n2785) );
OAI21X1TS U1494 ( .A0(n5170), .A1(n6565), .B0(n577), .Y(n576) );
XOR2X1TS U1495 ( .A(n7924), .B(n7923), .Y(GEN1_middle_N16) );
OAI21X1TS U1496 ( .A0(n7497), .A1(n7449), .B0(n7448), .Y(n7454) );
CLKINVX2TS U1497 ( .A(n7185), .Y(n7084) );
OR2X4TS U1498 ( .A(n3180), .B(n3179), .Y(n7143) );
AOI21X1TS U1499 ( .A0(n7191), .A1(n7047), .B0(n7046), .Y(n495) );
AND2X2TS U1500 ( .A(n3207), .B(n6565), .Y(n176) );
NAND2BX2TS U1501 ( .AN(n6575), .B(n578), .Y(n5170) );
NAND2X2TS U1502 ( .A(n221), .B(n222), .Y(n744) );
OAI2BB1X2TS U1503 ( .A0N(n660), .A1N(n2426), .B0(n658), .Y(n2535) );
INVX2TS U1504 ( .A(n3124), .Y(n3118) );
ADDFHX2TS U1505 ( .A(n1785), .B(n1784), .CI(n1783), .CO(n3178), .S(n3172) );
XOR2X1TS U1506 ( .A(n7604), .B(n7603), .Y(GEN1_right_N18) );
OAI21X1TS U1507 ( .A0(n7935), .A1(n7931), .B0(n7932), .Y(n7790) );
OAI21X1TS U1508 ( .A0(n7587), .A1(n7511), .B0(n7510), .Y(n7515) );
XOR2X2TS U1509 ( .A(n886), .B(n1804), .Y(n3177) );
NOR2X1TS U1510 ( .A(n7567), .B(n7579), .Y(n7570) );
XOR2X1TS U1511 ( .A(n7935), .B(n7934), .Y(GEN1_middle_N12) );
ADDFHX2TS U1512 ( .A(n3046), .B(n3045), .CI(n3044), .CO(n3052), .S(n3054) );
XOR2X1TS U1513 ( .A(n7587), .B(n7586), .Y(GEN1_right_N21) );
INVX1TS U1514 ( .A(n6566), .Y(n3207) );
AND2X2TS U1515 ( .A(n7131), .B(n7136), .Y(n573) );
XOR2X1TS U1516 ( .A(n7375), .B(n7374), .Y(GEN1_left_N15) );
OAI2BB1X2TS U1517 ( .A0N(n1596), .A1N(n1595), .B0(n626), .Y(n1661) );
XOR2X1TS U1518 ( .A(n7596), .B(n7595), .Y(GEN1_right_N20) );
INVX1TS U1519 ( .A(n5088), .Y(n4927) );
INVX1TS U1520 ( .A(n5051), .Y(n4952) );
INVX1TS U1521 ( .A(n5049), .Y(n4953) );
XOR2X1TS U1522 ( .A(n7612), .B(n7611), .Y(GEN1_right_N19) );
INVX1TS U1523 ( .A(n7131), .Y(n7134) );
INVX1TS U1524 ( .A(n7170), .Y(n6572) );
OAI21X1TS U1525 ( .A0(n7587), .A1(n7505), .B0(n7504), .Y(n7509) );
OAI2BB1X2TS U1526 ( .A0N(n1974), .A1N(n1973), .B0(n592), .Y(n1967) );
OAI2BB1X2TS U1527 ( .A0N(n2717), .A1N(n2716), .B0(n590), .Y(n2823) );
XOR2X2TS U1528 ( .A(n1594), .B(n629), .Y(n1658) );
NOR2BX1TS U1529 ( .AN(n477), .B(n7108), .Y(n7131) );
OAI2BB1X2TS U1530 ( .A0N(n628), .A1N(n627), .B0(n1594), .Y(n626) );
NAND2X2TS U1531 ( .A(n219), .B(n3049), .Y(n222) );
INVX1TS U1532 ( .A(n7271), .Y(n7375) );
XOR2X2TS U1533 ( .A(n919), .B(n3087), .Y(n3062) );
INVX1TS U1534 ( .A(n7430), .Y(n5040) );
XOR2X2TS U1535 ( .A(n1803), .B(n1805), .Y(n886) );
OAI21X2TS U1536 ( .A0(n1973), .A1(n1974), .B0(n593), .Y(n592) );
INVX1TS U1537 ( .A(n7577), .Y(n7567) );
AND2X2TS U1538 ( .A(n6577), .B(n6576), .Y(n968) );
INVX1TS U1539 ( .A(n7576), .Y(n7568) );
ADDFHX2TS U1540 ( .A(n2746), .B(n2745), .CI(n2744), .CO(n2718), .S(n2760) );
INVX1TS U1541 ( .A(n542), .Y(n540) );
INVX1TS U1542 ( .A(n2778), .Y(n2774) );
XOR2X1TS U1543 ( .A(n7632), .B(n7631), .Y(GEN1_right_N15) );
NOR2X4TS U1544 ( .A(n7498), .B(n7562), .Y(n7577) );
OAI21X1TS U1545 ( .A0(n7632), .A1(n7628), .B0(n7629), .Y(n7528) );
OAI2BB1X2TS U1546 ( .A0N(n778), .A1N(n777), .B0(n1732), .Y(n776) );
INVX1TS U1547 ( .A(n7481), .Y(n7483) );
INVX1TS U1548 ( .A(n4950), .Y(n4958) );
NAND2X2TS U1549 ( .A(n377), .B(n375), .Y(n7271) );
OAI21X1TS U1550 ( .A0(n7316), .A1(n7327), .B0(n7328), .Y(n7317) );
INVX1TS U1551 ( .A(n6575), .Y(n6577) );
INVX2TS U1552 ( .A(n7073), .Y(n7085) );
OAI2BB1X2TS U1553 ( .A0N(n1999), .A1N(n1998), .B0(n927), .Y(n1972) );
NOR2X1TS U1554 ( .A(n7315), .B(n7327), .Y(n7318) );
INVX1TS U1555 ( .A(n7183), .Y(n7028) );
NOR2X1TS U1556 ( .A(n7183), .B(n7187), .Y(n7190) );
OAI21X1TS U1557 ( .A0(n7336), .A1(n7354), .B0(n7355), .Y(n7337) );
INVX1TS U1558 ( .A(n7229), .Y(n7232) );
AND2X2TS U1559 ( .A(n7136), .B(n7135), .Y(n189) );
XOR2X2TS U1560 ( .A(n3070), .B(n804), .Y(n3102) );
INVX1TS U1561 ( .A(n7325), .Y(n7315) );
INVX1TS U1562 ( .A(n7579), .Y(n7581) );
AND2X2TS U1563 ( .A(n5188), .B(n7661), .Y(n165) );
INVX1TS U1564 ( .A(n7447), .Y(n7434) );
INVX1TS U1565 ( .A(n7511), .Y(n7501) );
INVX1TS U1566 ( .A(n7319), .Y(n7321) );
XOR2X2TS U1567 ( .A(n1596), .B(n1595), .Y(n629) );
INVX1TS U1568 ( .A(n7259), .Y(n7250) );
INVX1TS U1569 ( .A(n5136), .Y(n5138) );
INVX1TS U1570 ( .A(n7493), .Y(n7495) );
NOR2X1TS U1571 ( .A(n5169), .B(n5168), .Y(n6575) );
INVX1TS U1572 ( .A(n7112), .Y(n7114) );
INVX1TS U1573 ( .A(n7242), .Y(n7244) );
ADDFHX2TS U1574 ( .A(n1759), .B(n1758), .CI(n1757), .CO(n1774), .S(n1771) );
INVX1TS U1575 ( .A(n7135), .Y(n6845) );
INVX1TS U1576 ( .A(n2757), .Y(n539) );
INVX1TS U1577 ( .A(n7488), .Y(n7490) );
INVX1TS U1578 ( .A(n1596), .Y(n627) );
NAND2X2TS U1579 ( .A(n7507), .B(n7513), .Y(n3973) );
INVX1TS U1580 ( .A(n7237), .Y(n7239) );
INVX1TS U1581 ( .A(n7571), .Y(n7573) );
INVX1TS U1582 ( .A(n7468), .Y(n7457) );
XNOR2X1TS U1583 ( .A(n708), .B(n3039), .Y(n3041) );
NOR2X4TS U1584 ( .A(n7455), .B(n7461), .Y(n7447) );
INVX1TS U1585 ( .A(n7302), .Y(n7304) );
INVX1TS U1586 ( .A(n7247), .Y(n7309) );
INVX1TS U1587 ( .A(n7441), .Y(n7443) );
INVX1TS U1588 ( .A(n7216), .Y(n6500) );
INVX1TS U1589 ( .A(n7450), .Y(n7452) );
INVX1TS U1590 ( .A(n7484), .Y(n7473) );
INVX1TS U1591 ( .A(n7920), .Y(n7922) );
XNOR2X2TS U1592 ( .A(n1403), .B(n1419), .Y(n805) );
XOR2X2TS U1593 ( .A(n1999), .B(n1998), .Y(n676) );
INVX1TS U1594 ( .A(n7512), .Y(n7502) );
OAI21X1TS U1595 ( .A0(n2736), .A1(n2737), .B0(n2735), .Y(n544) );
XOR2X1TS U1596 ( .A(n1721), .B(n769), .Y(n768) );
NOR2X2TS U1597 ( .A(n6499), .B(n6503), .Y(n6587) );
AOI2BB1X2TS U1598 ( .A0N(n420), .A1N(n937), .B0(n378), .Y(n377) );
OAI21X1TS U1599 ( .A0(n7589), .A1(n7608), .B0(n7609), .Y(n7590) );
NOR2X1TS U1600 ( .A(n7588), .B(n7608), .Y(n7591) );
INVX1TS U1601 ( .A(n1734), .Y(n777) );
INVX2TS U1602 ( .A(n7339), .Y(n7341) );
XOR2X1TS U1603 ( .A(n7637), .B(n7636), .Y(GEN1_right_N10) );
INVX1TS U1604 ( .A(n7090), .Y(n7074) );
INVX1TS U1605 ( .A(n7662), .Y(n5188) );
INVX1TS U1606 ( .A(n7403), .Y(n5099) );
OAI21X1TS U1607 ( .A0(n5123), .A1(n5122), .B0(n5121), .Y(n5124) );
OAI21X1TS U1608 ( .A0(n7407), .A1(n7406), .B0(n7405), .Y(n7408) );
NOR2X1TS U1609 ( .A(n5118), .B(n5122), .Y(n5125) );
ADDFX1TS U1610 ( .A(n1503), .B(n1502), .CI(n1501), .CO(n1531), .S(n1525) );
NOR2X1TS U1611 ( .A(n7403), .B(n7406), .Y(n7409) );
INVX1TS U1612 ( .A(n7506), .Y(n3971) );
INVX1TS U1613 ( .A(n7517), .Y(n3965) );
INVX1TS U1614 ( .A(n7366), .Y(n420) );
INVX1TS U1615 ( .A(n7044), .Y(n7061) );
INVX1TS U1616 ( .A(n7269), .Y(n7346) );
INVX1TS U1617 ( .A(n7559), .Y(n7560) );
INVX1TS U1618 ( .A(n7080), .Y(n7082) );
OAI21X1TS U1619 ( .A0(n7080), .A1(n7104), .B0(n7081), .Y(n7006) );
INVX1TS U1620 ( .A(n7307), .Y(n7308) );
XOR2X1TS U1621 ( .A(n7380), .B(n7379), .Y(GEN1_left_N10) );
ADDFHX2TS U1622 ( .A(n203), .B(n1942), .CI(n1941), .CO(n1968), .S(n1999) );
NAND2X1TS U1623 ( .A(n5030), .B(n5029), .Y(n154) );
INVX1TS U1624 ( .A(n7255), .Y(n6148) );
INVX1TS U1625 ( .A(n7097), .Y(n7064) );
INVX1TS U1626 ( .A(n7104), .Y(n7077) );
ADDFHX1TS U1627 ( .A(n1459), .B(n1458), .CI(n1457), .CO(n1501), .S(n1462) );
INVX1TS U1628 ( .A(n4959), .Y(n4961) );
INVX1TS U1629 ( .A(n5054), .Y(n4904) );
OAI21X1TS U1630 ( .A0(n7946), .A1(n7942), .B0(n7943), .Y(n7799) );
NAND2BX1TS U1631 ( .AN(n7278), .B(n7363), .Y(n939) );
NOR2X2TS U1632 ( .A(n7005), .B(n7004), .Y(n7080) );
OAI21X1TS U1633 ( .A0(n4193), .A1(n4191), .B0(n4194), .Y(n4190) );
INVX1TS U1634 ( .A(n6153), .Y(n795) );
ADDFHX2TS U1635 ( .A(n6635), .B(n6634), .CI(n6633), .CO(n6764), .S(n6558) );
CLKINVX2TS U1636 ( .A(n7264), .Y(n6142) );
XOR2XLTS U1637 ( .A(n1962), .B(n1963), .Y(n931) );
ADDFHX2TS U1638 ( .A(n6353), .B(n6352), .CI(n6351), .CO(n6450), .S(n6447) );
INVX1TS U1639 ( .A(n7278), .Y(n7360) );
NOR2X2TS U1640 ( .A(n7592), .B(n7608), .Y(n3751) );
XOR2X1TS U1641 ( .A(n7642), .B(n7641), .Y(GEN1_right_N9) );
OAI21X1TS U1642 ( .A0(n7592), .A1(n7609), .B0(n7593), .Y(n3750) );
INVX1TS U1643 ( .A(n5157), .Y(n581) );
INVX1TS U1644 ( .A(n7584), .Y(n3966) );
OAI21X1TS U1645 ( .A0(n7646), .A1(n7643), .B0(n7644), .Y(n7543) );
XOR2X1TS U1646 ( .A(n7647), .B(n7646), .Y(GEN1_right_N7) );
OAI2BB1X1TS U1647 ( .A0N(n4606), .A1N(n4605), .B0(n796), .Y(n4638) );
INVX1TS U1648 ( .A(n5045), .Y(n4913) );
AND2X2TS U1649 ( .A(n7041), .B(n7186), .Y(n213) );
INVX1TS U1650 ( .A(n4210), .Y(n792) );
INVX1TS U1651 ( .A(n5009), .Y(n5010) );
INVX1TS U1652 ( .A(n7120), .Y(n5025) );
INVX1TS U1653 ( .A(n7211), .Y(n7049) );
INVX1TS U1654 ( .A(n5036), .Y(n5022) );
INVX1TS U1655 ( .A(n5158), .Y(n580) );
INVX1TS U1656 ( .A(n6032), .Y(n938) );
NOR2X1TS U1657 ( .A(n6029), .B(n6028), .Y(n7278) );
XOR2X1TS U1658 ( .A(n7390), .B(n7389), .Y(GEN1_left_N7) );
NOR2X1TS U1659 ( .A(n4947), .B(n4946), .Y(n4984) );
INVX1TS U1660 ( .A(n7128), .Y(n5128) );
INVX1TS U1661 ( .A(n7187), .Y(n7041) );
INVX1TS U1662 ( .A(n7052), .Y(n7054) );
XOR2X1TS U1663 ( .A(n482), .B(n6642), .Y(n6636) );
OAI21X1TS U1664 ( .A0(n7524), .A1(n7629), .B0(n7525), .Y(n3740) );
INVX1TS U1665 ( .A(n7524), .Y(n7526) );
OAI2BB1X2TS U1666 ( .A0N(n3941), .A1N(n3940), .B0(n877), .Y(n3925) );
OR2X2TS U1667 ( .A(n7679), .B(n7678), .Y(n7681) );
ADDFHX2TS U1668 ( .A(n6329), .B(n6328), .CI(n6327), .CO(n6352), .S(n6348) );
INVX1TS U1669 ( .A(n7624), .Y(n3715) );
OAI2BB1X2TS U1670 ( .A0N(n2629), .A1N(n2628), .B0(n891), .Y(n2682) );
ADDFX1TS U1671 ( .A(n4383), .B(n4382), .CI(n4381), .CO(n4565), .S(n4384) );
XOR2X1TS U1672 ( .A(n7385), .B(n7384), .Y(GEN1_left_N9) );
OAI21X1TS U1673 ( .A0(n7389), .A1(n7386), .B0(n7387), .Y(n7291) );
ADDFHX2TS U1674 ( .A(n6421), .B(n6420), .CI(n6419), .CO(n6492), .S(n6437) );
NOR2X1TS U1675 ( .A(n6141), .B(n6140), .Y(n6131) );
XOR2X1TS U1676 ( .A(n948), .B(n5786), .Y(n5788) );
NAND2X2TS U1677 ( .A(n737), .B(n731), .Y(n730) );
INVX1TS U1678 ( .A(n7947), .Y(n7949) );
INVX1TS U1679 ( .A(n7406), .Y(n5114) );
INVX1TS U1680 ( .A(n5131), .Y(n5133) );
NOR2X1TS U1681 ( .A(n5006), .B(n5005), .Y(n5122) );
ADDFHX2TS U1682 ( .A(n2045), .B(n2044), .CI(n2043), .CO(n2058), .S(n2315) );
OAI21X1TS U1683 ( .A0(n5596), .A1(n5597), .B0(n5595), .Y(n574) );
NOR2BX2TS U1684 ( .AN(n525), .B(n6025), .Y(n7281) );
ADDFHX1TS U1685 ( .A(n4339), .B(n4338), .CI(n4337), .CO(n4396), .S(n4401) );
ADDFX1TS U1686 ( .A(n4558), .B(n4557), .CI(n4556), .CO(n4510), .S(n4573) );
NOR2X1TS U1687 ( .A(n5090), .B(n5089), .Y(n5119) );
INVX1TS U1688 ( .A(n7376), .Y(n7378) );
NOR2X1TS U1689 ( .A(n7040), .B(n7039), .Y(n7187) );
INVX1TS U1690 ( .A(n7638), .Y(n7640) );
XOR2X1TS U1691 ( .A(n5785), .B(n5787), .Y(n948) );
INVX1TS U1692 ( .A(n7386), .Y(n7388) );
OAI21X1TS U1693 ( .A0(n5868), .A1(n5869), .B0(n5867), .Y(n409) );
OAI21X1TS U1694 ( .A0(n7287), .A1(n7387), .B0(n7288), .Y(n5971) );
INVX1TS U1695 ( .A(n5569), .Y(n522) );
INVX1TS U1696 ( .A(n6698), .Y(n548) );
INVX1TS U1697 ( .A(n6699), .Y(n547) );
ADDFHX1TS U1698 ( .A(n6722), .B(n6721), .CI(n6720), .CO(n6752), .S(n6727) );
NOR2X1TS U1699 ( .A(n5092), .B(n5091), .Y(n5131) );
NOR2X1TS U1700 ( .A(n5113), .B(n5112), .Y(n7406) );
INVX1TS U1701 ( .A(n5568), .Y(n523) );
OAI21X1TS U1702 ( .A0(n6724), .A1(n6725), .B0(n6723), .Y(n483) );
NAND2XLTS U1703 ( .A(n1952), .B(n1951), .Y(n673) );
XOR2X1TS U1704 ( .A(n7657), .B(n7656), .Y(GEN1_right_N4) );
INVX1TS U1705 ( .A(n7643), .Y(n7645) );
INVX1TS U1706 ( .A(n7952), .Y(n7954) );
NAND2X2TS U1707 ( .A(n722), .B(n2998), .Y(n2554) );
XOR2X1TS U1708 ( .A(n6930), .B(n6973), .Y(n6951) );
INVX6TS U1709 ( .A(n751), .Y(n2809) );
OAI21X1TS U1710 ( .A0(n2481), .A1(n732), .B0(n736), .Y(n2499) );
ADDFX1TS U1711 ( .A(n4642), .B(n4641), .CI(n4640), .CO(n4764), .S(n4643) );
ADDFHX2TS U1712 ( .A(n4177), .B(n4176), .CI(n4175), .CO(n4147), .S(n4191) );
INVX1TS U1713 ( .A(n7648), .Y(n7650) );
ADDFHX1TS U1714 ( .A(n3897), .B(n3896), .CI(n3895), .CO(n4198), .S(n3926) );
INVX1TS U1715 ( .A(n3941), .Y(n878) );
INVX1TS U1716 ( .A(n3940), .Y(n879) );
ADDFHX1TS U1717 ( .A(n4886), .B(n4885), .CI(n4884), .CO(n4890), .S(n4876) );
XOR2X2TS U1718 ( .A(n5638), .B(n5639), .Y(n801) );
XOR2X1TS U1719 ( .A(n6187), .B(Data_A_i[32]), .Y(n6298) );
XOR2X1TS U1720 ( .A(n6950), .B(n6963), .Y(n6965) );
XOR2X1TS U1721 ( .A(n6175), .B(n6289), .Y(n6245) );
XOR2X1TS U1722 ( .A(n6478), .B(n6611), .Y(n6535) );
XOR2X1TS U1723 ( .A(n5754), .B(n835), .Y(n834) );
ADDFHX1TS U1724 ( .A(n6532), .B(n6531), .CI(n6530), .CO(n6600), .S(n6548) );
XOR2X1TS U1725 ( .A(n6941), .B(n6940), .Y(n6993) );
ADDFX1TS U1726 ( .A(n4739), .B(n4738), .CI(n4737), .CO(n4886), .S(n4758) );
ADDFHX1TS U1727 ( .A(n3894), .B(n3893), .CI(n3892), .CO(n4185), .S(n3895) );
INVX1TS U1728 ( .A(n7544), .Y(n3657) );
INVX1TS U1729 ( .A(n5185), .Y(n5165) );
XOR2X1TS U1730 ( .A(n5509), .B(n6090), .Y(n5546) );
XOR2X1TS U1731 ( .A(n6974), .B(n6973), .Y(n6979) );
XOR2X1TS U1732 ( .A(n5605), .B(n5942), .Y(n5654) );
XOR2X1TS U1733 ( .A(n6814), .B(n6940), .Y(n6881) );
XOR2X1TS U1734 ( .A(n6869), .B(n6973), .Y(n6908) );
XOR2X1TS U1735 ( .A(n6900), .B(n6940), .Y(n6932) );
ADDFHX1TS U1736 ( .A(n4052), .B(n4051), .CI(n4050), .CO(n4083), .S(n4177) );
ADDFHX1TS U1737 ( .A(n5488), .B(n5487), .CI(n5486), .CO(n6212), .S(n5532) );
XOR2X1TS U1738 ( .A(n6657), .B(n6701), .Y(n6669) );
OAI2BB1X1TS U1739 ( .A0N(n5433), .A1N(n5434), .B0(n526), .Y(n5328) );
ADDFHX1TS U1740 ( .A(n3462), .B(n3461), .CI(n3460), .CO(n3454), .S(n3491) );
XOR2X1TS U1741 ( .A(n6540), .B(n6624), .Y(n6608) );
ADDFX1TS U1742 ( .A(n6086), .B(n6085), .CI(n6084), .CO(n6100), .S(n6117) );
OAI21X1TS U1743 ( .A0(n5827), .A1(n5828), .B0(n5826), .Y(n443) );
XOR2X1TS U1744 ( .A(n6958), .B(n6973), .Y(n6996) );
INVX1TS U1745 ( .A(n6725), .Y(n485) );
XOR2X1TS U1746 ( .A(n7400), .B(n7399), .Y(GEN1_left_N4) );
ADDFHX1TS U1747 ( .A(n3932), .B(n3931), .CI(n3930), .CO(n3954), .S(n3950) );
XOR2X1TS U1748 ( .A(n6781), .B(n7037), .Y(n6835) );
XOR2X1TS U1749 ( .A(n2149), .B(n870), .Y(n2169) );
NOR2X1TS U1750 ( .A(n7672), .B(n1668), .Y(n1676) );
ADDFHX1TS U1751 ( .A(n2061), .B(n2060), .CI(n2059), .CO(n2125), .S(n2130) );
XOR2X1TS U1752 ( .A(n6857), .B(n6973), .Y(n6887) );
INVX1TS U1753 ( .A(n7391), .Y(n7393) );
XOR2X1TS U1754 ( .A(n3411), .B(n3796), .Y(n3930) );
OAI21X1TS U1755 ( .A0(n6929), .A1(n338), .B0(n6749), .Y(n6750) );
ADDFHX1TS U1756 ( .A(n5549), .B(n5548), .CI(n5547), .CO(n5544), .S(n5603) );
OAI21X1TS U1757 ( .A0(n498), .A1(n6949), .B0(n6948), .Y(n6950) );
XOR2X1TS U1758 ( .A(n5300), .B(n6289), .Y(n6239) );
OAI21X1TS U1759 ( .A0(n498), .A1(n5318), .B0(n6988), .Y(n6990) );
XOR2X1TS U1760 ( .A(n6865), .B(n6895), .Y(n6909) );
OAI21X1TS U1761 ( .A0(n498), .A1(n6082), .B0(n5256), .Y(n5258) );
XOR2X1TS U1762 ( .A(n7038), .B(n7037), .Y(n7195) );
XOR2X1TS U1763 ( .A(n6964), .B(n6963), .Y(n6975) );
XOR2X1TS U1764 ( .A(n6182), .B(n6412), .Y(n6299) );
XOR2X1TS U1765 ( .A(n5314), .B(n6412), .Y(n6238) );
XOR2X1TS U1766 ( .A(n6784), .B(n6895), .Y(n6834) );
XOR2X1TS U1767 ( .A(n6702), .B(n6701), .Y(n6731) );
XOR2X1TS U1768 ( .A(n6427), .B(n6611), .Y(n6476) );
XOR2X1TS U1769 ( .A(n6787), .B(n6820), .Y(n6833) );
OAI21X1TS U1770 ( .A0(n498), .A1(n337), .B0(n6876), .Y(n6878) );
XOR2X1TS U1771 ( .A(n6189), .B(n6289), .Y(n6297) );
XOR2X1TS U1772 ( .A(n6311), .B(n6701), .Y(n6356) );
OAI21X1TS U1773 ( .A0(n6929), .A1(n6794), .B0(n6656), .Y(n6657) );
XOR2X1TS U1774 ( .A(n3431), .B(n3796), .Y(n3436) );
OAI21X1TS U1775 ( .A0(n6929), .A1(n6679), .B0(n6477), .Y(n6478) );
XOR2X1TS U1776 ( .A(n6480), .B(n6701), .Y(n6534) );
XOR2X1TS U1777 ( .A(n6821), .B(n6820), .Y(n6879) );
XOR2X1TS U1778 ( .A(n6925), .B(n6963), .Y(n6952) );
XNOR2X1TS U1779 ( .A(n568), .B(n6895), .Y(n567) );
INVX1TS U1780 ( .A(n7653), .Y(n7655) );
XNOR2X1TS U1781 ( .A(n570), .B(n6624), .Y(n569) );
XOR2X1TS U1782 ( .A(n3869), .B(n4106), .Y(n4180) );
XOR2X1TS U1783 ( .A(n6529), .B(n6820), .Y(n6630) );
OAI21X1TS U1784 ( .A0(n6929), .A1(n6186), .B0(n5508), .Y(n5509) );
XOR2X1TS U1785 ( .A(n6179), .B(n6412), .Y(n6243) );
XOR2X1TS U1786 ( .A(n6177), .B(n6611), .Y(n6244) );
XOR2X1TS U1787 ( .A(n6817), .B(n6895), .Y(n6880) );
XOR2X1TS U1788 ( .A(n6542), .B(n6611), .Y(n6607) );
XOR2X1TS U1789 ( .A(n6896), .B(n6895), .Y(n6933) );
XOR2X1TS U1790 ( .A(n3546), .B(n303), .Y(n3600) );
XOR2X1TS U1791 ( .A(n3453), .B(Data_A_i[2]), .Y(n3492) );
XOR2X1TS U1792 ( .A(n6406), .B(n6820), .Y(n6456) );
XOR2X1TS U1793 ( .A(n6317), .B(n6402), .Y(n6354) );
XOR2X1TS U1794 ( .A(n446), .B(n6829), .Y(n6797) );
XOR2X1TS U1795 ( .A(n3371), .B(Data_A_i[2]), .Y(n3460) );
XOR2X1TS U1796 ( .A(n6167), .B(n6274), .Y(n6242) );
XOR2X1TS U1797 ( .A(n4793), .B(n4792), .Y(n4841) );
XOR2X1TS U1798 ( .A(n4848), .B(n4970), .Y(n4944) );
XOR2X1TS U1799 ( .A(n4845), .B(n4844), .Y(n4945) );
NOR2X1TS U1800 ( .A(n412), .B(n411), .Y(n5855) );
INVX1TS U1801 ( .A(n5883), .Y(n945) );
XOR2X1TS U1802 ( .A(n4942), .B(n5066), .Y(n4981) );
XOR2X1TS U1803 ( .A(n4937), .B(n5001), .Y(n4982) );
XOR2X1TS U1804 ( .A(n4971), .B(n4970), .Y(n4991) );
XOR2X1TS U1805 ( .A(n4980), .B(n5001), .Y(n5003) );
INVX1TS U1806 ( .A(n1799), .Y(n1743) );
XOR2X1TS U1807 ( .A(n4996), .B(n5066), .Y(n5059) );
XOR2X1TS U1808 ( .A(n4755), .B(n4833), .Y(n4863) );
XOR2X1TS U1809 ( .A(n4025), .B(n4434), .Y(n4281) );
XOR2X1TS U1810 ( .A(n4036), .B(n303), .Y(n4085) );
XOR2X1TS U1811 ( .A(n4834), .B(n4833), .Y(n4878) );
XOR2X1TS U1812 ( .A(n4827), .B(n4844), .Y(n4879) );
XOR2X1TS U1813 ( .A(n6091), .B(n6090), .Y(n6124) );
XOR2X1TS U1814 ( .A(n4821), .B(n5110), .Y(n4880) );
XOR2X1TS U1815 ( .A(n5795), .B(n5889), .Y(n5828) );
XOR2X1TS U1816 ( .A(n3998), .B(n4434), .Y(n4118) );
XOR2X1TS U1817 ( .A(n5726), .B(n5889), .Y(n6107) );
XOR2X1TS U1818 ( .A(n4802), .B(n4833), .Y(n4857) );
XOR2X1TS U1819 ( .A(n4800), .B(n4844), .Y(n4858) );
XOR2X1TS U1820 ( .A(n4706), .B(n4705), .Y(n4736) );
XOR2X1TS U1821 ( .A(n5671), .B(n6090), .Y(n6115) );
XOR2X1TS U1822 ( .A(n4798), .B(n4970), .Y(n4859) );
XOR2X1TS U1823 ( .A(n4685), .B(n4844), .Y(n4725) );
XOR2X1TS U1824 ( .A(n4117), .B(n303), .Y(n4256) );
XOR2X1TS U1825 ( .A(n4687), .B(n4705), .Y(n4730) );
INVX1TS U1826 ( .A(n7957), .Y(n7959) );
XOR2X1TS U1827 ( .A(n4774), .B(n5066), .Y(n4837) );
XOR2X1TS U1828 ( .A(n4653), .B(n4833), .Y(n4674) );
XOR2X1TS U1829 ( .A(n5651), .B(n6090), .Y(n6084) );
XOR2X1TS U1830 ( .A(n4658), .B(n4705), .Y(n4672) );
XOR2X1TS U1831 ( .A(n5647), .B(n6289), .Y(n6086) );
XOR2X1TS U1832 ( .A(n4784), .B(n5066), .Y(n4855) );
XOR2X1TS U1833 ( .A(n4782), .B(n4844), .Y(n4856) );
XOR2X1TS U1834 ( .A(n5067), .B(n5066), .Y(n5072) );
XOR2X1TS U1835 ( .A(n4544), .B(n4611), .Y(n4608) );
XOR2X1TS U1836 ( .A(n4542), .B(n4626), .Y(n4609) );
XOR2X1TS U1837 ( .A(n5571), .B(n5942), .Y(n5613) );
XOR2X1TS U1838 ( .A(n4528), .B(n4833), .Y(n4634) );
XOR2X1TS U1839 ( .A(n4524), .B(n4705), .Y(n4635) );
ADDFX1TS U1840 ( .A(n4515), .B(n4514), .CI(n4513), .CO(n4603), .S(n4535) );
XOR2X1TS U1841 ( .A(n1874), .B(n1873), .Y(n1927) );
INVX1TS U1842 ( .A(n1651), .Y(n1614) );
ADDFHX1TS U1843 ( .A(n4475), .B(n4474), .CI(n4473), .CO(n4492), .S(n4502) );
XOR2X1TS U1844 ( .A(n4435), .B(n4434), .Y(n4506) );
INVX1TS U1845 ( .A(n7292), .Y(n5964) );
XOR2X1TS U1846 ( .A(n4450), .B(n4611), .Y(n4478) );
XOR2X1TS U1847 ( .A(n5883), .B(n5884), .Y(n946) );
XOR2X1TS U1848 ( .A(n5752), .B(n5981), .Y(n5791) );
XOR2X1TS U1849 ( .A(n5557), .B(n6289), .Y(n5592) );
NAND2BX1TS U1850 ( .AN(n2549), .B(n2866), .Y(n2393) );
XOR2X1TS U1851 ( .A(n4414), .B(n4434), .Y(n4497) );
XOR2X1TS U1852 ( .A(n5730), .B(n5889), .Y(n5735) );
XOR2X1TS U1853 ( .A(n4612), .B(n4611), .Y(n4648) );
ADDFX1TS U1854 ( .A(n5720), .B(n5719), .CI(n5718), .CO(n6127), .S(n5754) );
OAI21XLTS U1855 ( .A0(n8209), .A1(n8208), .B0(n8207), .Y(n8211) );
OAI21XLTS U1856 ( .A0(n8209), .A1(n8200), .B0(n8199), .Y(n8203) );
OAI21X1TS U1857 ( .A0(n8164), .A1(n8163), .B0(n8162), .Y(n8169) );
OAI21X1TS U1858 ( .A0(n8125), .A1(n8124), .B0(n8123), .Y(n8131) );
OAI21X1TS U1859 ( .A0(n5084), .A1(n5083), .B0(n5082), .Y(n5086) );
XOR2X1TS U1860 ( .A(n3514), .B(n4242), .Y(n3729) );
XOR2X1TS U1861 ( .A(n3451), .B(n303), .Y(n3493) );
OAI21X1TS U1862 ( .A0(n6740), .A1(n337), .B0(n6463), .Y(n6464) );
XOR2X1TS U1863 ( .A(n3503), .B(n3796), .Y(n3722) );
XOR2X1TS U1864 ( .A(n3293), .B(n4468), .Y(n3446) );
XOR2X1TS U1865 ( .A(n5111), .B(n5110), .Y(n7415) );
XOR2X1TS U1866 ( .A(n3505), .B(n4468), .Y(n3721) );
OAI21X1TS U1867 ( .A0(n6856), .A1(n6794), .B0(n6479), .Y(n6480) );
XOR2X1TS U1868 ( .A(n3358), .B(Data_A_i[11]), .Y(n3462) );
NOR2BX2TS U1869 ( .AN(n3519), .B(n3485), .Y(n3515) );
OAI21X1TS U1870 ( .A0(n6856), .A1(n338), .B0(n6651), .Y(n6652) );
XOR2X1TS U1871 ( .A(n3496), .B(n3796), .Y(n3530) );
OAI21X1TS U1872 ( .A0(n6780), .A1(n337), .B0(n6528), .Y(n6529) );
OAI21X1TS U1873 ( .A0(n4820), .A1(n3638), .B0(n3370), .Y(n3371) );
XOR2X1TS U1874 ( .A(n3475), .B(n3761), .Y(n3526) );
XOR2X1TS U1875 ( .A(n3388), .B(n3832), .Y(n3932) );
OAI21X1TS U1876 ( .A0(n6899), .A1(n6679), .B0(n6426), .Y(n6427) );
OAI21X1TS U1877 ( .A0(n6939), .A1(n6679), .B0(n6541), .Y(n6542) );
XOR2X1TS U1878 ( .A(n3519), .B(n3518), .Y(n3590) );
OAI21X1TS U1879 ( .A0(n6712), .A1(n338), .B0(n6405), .Y(n6406) );
XOR2X1TS U1880 ( .A(n4114), .B(n4611), .Y(n4257) );
INVX1TS U1881 ( .A(n6813), .Y(n514) );
OAI21X1TS U1882 ( .A0(n4773), .A1(n5083), .B0(n4772), .Y(n4774) );
OAI21X1TS U1883 ( .A0(n4773), .A1(n4541), .B0(n4234), .Y(n4235) );
OAI21X1TS U1884 ( .A0(n4969), .A1(n4979), .B0(n4781), .Y(n4782) );
OAI21X1TS U1885 ( .A0(n4826), .A1(n4541), .B0(n4236), .Y(n4237) );
OAI21X1TS U1886 ( .A0(n4941), .A1(n4241), .B0(n4124), .Y(n4125) );
OAI21X1TS U1887 ( .A0(n4995), .A1(n4979), .B0(n4843), .Y(n4845) );
XOR2X1TS U1888 ( .A(n4270), .B(n4792), .Y(n4289) );
OAI21X1TS U1889 ( .A0(n4941), .A1(n5083), .B0(n4940), .Y(n4942) );
OAI21X1TS U1890 ( .A0(n7036), .A1(n338), .B0(n6904), .Y(n6906) );
OAI21X1TS U1891 ( .A0(n4969), .A1(n5083), .B0(n4968), .Y(n4971) );
XOR2X1TS U1892 ( .A(n5002), .B(n5001), .Y(n5068) );
OAI21X1TS U1893 ( .A0(n4995), .A1(n5083), .B0(n4994), .Y(n4996) );
OAI21X1TS U1894 ( .A0(n6972), .A1(n6949), .B0(n6924), .Y(n6925) );
OAI21X1TS U1895 ( .A0(n4847), .A1(n4541), .B0(n4322), .Y(n4323) );
INVX1TS U1896 ( .A(n6939), .Y(n517) );
OAI21X1TS U1897 ( .A0(n4744), .A1(n4776), .B0(n4343), .Y(n4344) );
OAI21X1TS U1898 ( .A0(n4995), .A1(n331), .B0(n4610), .Y(n4612) );
OAI21X1TS U1899 ( .A0(n4969), .A1(n331), .B0(n4543), .Y(n4544) );
OAI21X1TS U1900 ( .A0(n7036), .A1(n6962), .B0(n6961), .Y(n6964) );
OAI21X1TS U1901 ( .A0(n5084), .A1(n4541), .B0(n4540), .Y(n4542) );
XOR2X1TS U1902 ( .A(n4485), .B(n4548), .Y(n4514) );
OAI21X1TS U1903 ( .A0(n4826), .A1(n330), .B0(n4471), .Y(n4472) );
OAI21X1TS U1904 ( .A0(n4941), .A1(n330), .B0(n4479), .Y(n4480) );
OAI21X1TS U1905 ( .A0(n4969), .A1(n4541), .B0(n4433), .Y(n4435) );
OAI21X1TS U1906 ( .A0(n4820), .A1(n4776), .B0(n4446), .Y(n4447) );
XOR2X1TS U1907 ( .A(n4406), .B(n5001), .Y(n4491) );
OAI21X1TS U1908 ( .A0(n4847), .A1(n330), .B0(n4449), .Y(n4450) );
XOR2X1TS U1909 ( .A(n4409), .B(n4468), .Y(n4490) );
XOR2X1TS U1910 ( .A(n4412), .B(n4833), .Y(n4489) );
XOR2X1TS U1911 ( .A(n6620), .B(n7037), .Y(n6653) );
XOR2X1TS U1912 ( .A(n3544), .B(n4242), .Y(n3569) );
XOR2X1TS U1913 ( .A(n3541), .B(n3796), .Y(n3570) );
XOR2X1TS U1914 ( .A(n3902), .B(Data_A_i[11]), .Y(n3935) );
INVX1TS U1915 ( .A(n5146), .Y(n3193) );
OAI21X1TS U1916 ( .A0(n6780), .A1(n6962), .B0(n6681), .Y(n6682) );
OAI21X1TS U1917 ( .A0(n4826), .A1(n4105), .B0(n3907), .Y(n3908) );
INVX1TS U1918 ( .A(n7396), .Y(n7398) );
OAI21X1TS U1919 ( .A0(n5065), .A1(n5083), .B0(n5064), .Y(n5067) );
XOR2X1TS U1920 ( .A(n3687), .B(Data_A_i[5]), .Y(n3702) );
OAI21X1TS U1921 ( .A0(n4941), .A1(n4812), .B0(n4657), .Y(n4658) );
XOR2X1TS U1922 ( .A(n3673), .B(n3672), .Y(n3695) );
OAI21X1TS U1923 ( .A0(n4847), .A1(n4105), .B0(n3795), .Y(n3797) );
OAI21X1TS U1924 ( .A0(n6899), .A1(n337), .B0(n6718), .Y(n6719) );
OAI21X1TS U1925 ( .A0(n4969), .A1(n4812), .B0(n4686), .Y(n4687) );
OAI21X1TS U1926 ( .A0(n6813), .A1(n6962), .B0(n6714), .Y(n6715) );
OAI21X1TS U1927 ( .A0(n6712), .A1(n5318), .B0(n6711), .Y(n6713) );
XOR2X1TS U1928 ( .A(n3977), .B(n4044), .Y(n4120) );
XOR2X1TS U1929 ( .A(n3609), .B(n3672), .Y(n3625) );
INVX1TS U1930 ( .A(n6856), .Y(n513) );
OAI21X1TS U1931 ( .A0(n4820), .A1(n4625), .B0(n3997), .Y(n3998) );
OAI21X1TS U1932 ( .A0(n6939), .A1(n338), .B0(n6786), .Y(n6787) );
OAI21X1TS U1933 ( .A0(n4969), .A1(n4241), .B0(n4035), .Y(n4036) );
OAI21X1TS U1934 ( .A0(n6972), .A1(n6794), .B0(n6747), .Y(n446) );
OAI21X1TS U1935 ( .A0(n4820), .A1(n4408), .B0(n3784), .Y(n3785) );
INVX1TS U1936 ( .A(n7547), .Y(n3643) );
OAI21X1TS U1937 ( .A0(n4797), .A1(n4625), .B0(n4024), .Y(n4025) );
OAI21X1TS U1938 ( .A0(n4969), .A1(n4105), .B0(n3868), .Y(n3869) );
OAI21X1TS U1939 ( .A0(n4969), .A1(n4832), .B0(n4831), .Y(n4834) );
OAI21X1TS U1940 ( .A0(n4995), .A1(n4832), .B0(n4801), .Y(n4802) );
XOR2X1TS U1941 ( .A(n4054), .B(n4434), .Y(n4171) );
OAI21X1TS U1942 ( .A0(n7036), .A1(n5318), .B0(n7035), .Y(n7038) );
OAI21X1TS U1943 ( .A0(n6780), .A1(n6401), .B0(n5556), .Y(n5557) );
OAI21X1TS U1944 ( .A0(n6740), .A1(n6273), .B0(n5670), .Y(n5671) );
OAI21X1TS U1945 ( .A0(n6856), .A1(n6363), .B0(n5430), .Y(n5431) );
OAI21X1TS U1946 ( .A0(n6939), .A1(n6082), .B0(n5570), .Y(n5571) );
OAI21X1TS U1947 ( .A0(n6972), .A1(n6186), .B0(n6166), .Y(n6167) );
OAI21X1TS U1948 ( .A0(n6740), .A1(n6401), .B0(n5590), .Y(n5591) );
OAI21X1TS U1949 ( .A0(n6712), .A1(n6828), .B0(n6276), .Y(n6277) );
OAI21X1TS U1950 ( .A0(n6972), .A1(n6082), .B0(n5422), .Y(n5423) );
OAI21X1TS U1951 ( .A0(n6868), .A1(n6082), .B0(n6081), .Y(n6083) );
XOR2X1TS U1952 ( .A(n5904), .B(n5981), .Y(n5925) );
INVX1TS U1953 ( .A(n5858), .Y(n411) );
ADDFHX2TS U1954 ( .A(n5942), .B(n6287), .CI(n6286), .CO(n6343), .S(n6294) );
ADDFX1TS U1955 ( .A(n6370), .B(n6369), .CI(n6368), .CO(n6407), .S(n6375) );
XOR2X1TS U1956 ( .A(n6006), .B(n6005), .Y(n6021) );
OAI21X1TS U1957 ( .A0(n6856), .A1(n6186), .B0(n5606), .Y(n5607) );
OAI21X1TS U1958 ( .A0(n6856), .A1(n6679), .B0(n6324), .Y(n6325) );
XOR2X1TS U1959 ( .A(n5773), .B(n5853), .Y(n5812) );
OAI21X1TS U1960 ( .A0(n4520), .A1(n4135), .B0(n4041), .Y(n4042) );
INVX1TS U1961 ( .A(n7677), .Y(n7671) );
OAI21X1TS U1962 ( .A0(n6284), .A1(n6073), .B0(n5772), .Y(n5773) );
OAI21X1TS U1963 ( .A0(n4421), .A1(n3671), .B0(n3670), .Y(n3673) );
XOR2X1TS U1964 ( .A(n5890), .B(n5889), .Y(n6042) );
XOR2X1TS U1965 ( .A(n6225), .B(n6877), .Y(n6278) );
XOR2X1TS U1966 ( .A(n5691), .B(n6402), .Y(n5744) );
OAI21X1TS U1967 ( .A0(n6284), .A1(n6004), .B0(n6003), .Y(n6006) );
XOR2X1TS U1968 ( .A(n5872), .B(n5889), .Y(n6018) );
XOR2X1TS U1969 ( .A(n5750), .B(n6005), .Y(n5792) );
INVX1TS U1970 ( .A(n7816), .Y(n7810) );
OAI21X1TS U1971 ( .A0(n5109), .A1(n5000), .B0(n4999), .Y(n5002) );
NOR2BX2TS U1972 ( .AN(n4127), .B(n3996), .Y(n4012) );
OAI21X1TS U1973 ( .A0(n4304), .A1(n4135), .B0(n3841), .Y(n3842) );
OAI21X1TS U1974 ( .A0(n118), .A1(n6224), .B0(n5326), .Y(n5327) );
XOR2X2TS U1975 ( .A(n5391), .B(n5390), .Y(n6740) );
XOR2X2TS U1976 ( .A(n3808), .B(n3807), .Y(n4941) );
XOR2X2TS U1977 ( .A(n447), .B(n5421), .Y(n6972) );
OAI21X1TS U1978 ( .A0(n6284), .A1(n5875), .B0(n5845), .Y(n5846) );
NOR2X1TS U1979 ( .A(n5955), .B(n5954), .Y(n7396) );
XOR2X1TS U1980 ( .A(n5816), .B(n6274), .Y(n6045) );
OAI21X1TS U1981 ( .A0(n4304), .A1(n3901), .B0(n3474), .Y(n3475) );
XOR2X1TS U1982 ( .A(n5362), .B(n6829), .Y(n5438) );
OAI21X1TS U1983 ( .A0(n4304), .A1(n3671), .B0(n3608), .Y(n3609) );
OAI21X1TS U1984 ( .A0(n118), .A1(n5763), .B0(n5618), .Y(n5619) );
OAI21X1TS U1985 ( .A0(n4520), .A1(n4440), .B0(n4439), .Y(n4441) );
XOR2X1TS U1986 ( .A(n5982), .B(n5981), .Y(n6014) );
OAI21X1TS U1987 ( .A0(n6284), .A1(n5980), .B0(n5903), .Y(n5904) );
XOR2X1TS U1988 ( .A(n3652), .B(n3672), .Y(n3656) );
ADDFX1TS U1989 ( .A(n5715), .B(n5714), .CI(n5713), .CO(n5718), .S(n5783) );
XOR2X1TS U1990 ( .A(n6270), .B(Data_A_i[47]), .Y(n6335) );
XOR2X1TS U1991 ( .A(n6314), .B(n6963), .Y(n6355) );
INVX1TS U1992 ( .A(n7808), .Y(n2255) );
XOR2X2TS U1993 ( .A(n3408), .B(n3407), .Y(n4773) );
INVX1TS U1994 ( .A(n7295), .Y(n5947) );
XOR2X1TS U1995 ( .A(n5722), .B(n5989), .Y(n6109) );
XOR2X1TS U1996 ( .A(n5802), .B(n5889), .Y(n6038) );
OAI21X1TS U1997 ( .A0(n4718), .A1(n5108), .B0(n4717), .Y(n4719) );
XOR2X2TS U1998 ( .A(n456), .B(n5233), .Y(n6780) );
XOR2X1TS U1999 ( .A(n3568), .B(n3832), .Y(n3585) );
INVX1TS U2000 ( .A(n248), .Y(n1548) );
OAI21X1TS U2001 ( .A0(n6284), .A1(n6386), .B0(n5480), .Y(n5481) );
XOR2X1TS U2002 ( .A(n5587), .B(n5853), .Y(n5636) );
XOR2X1TS U2003 ( .A(n5839), .B(n5889), .Y(n5865) );
OAI21X1TS U2004 ( .A0(n118), .A1(n5980), .B0(n5877), .Y(n5878) );
OAI21X1TS U2005 ( .A0(n4520), .A1(n3901), .B0(n3900), .Y(n3902) );
XOR2X1TS U2006 ( .A(n3285), .B(n4264), .Y(n3914) );
XOR2X1TS U2007 ( .A(n6547), .B(n6546), .Y(n6615) );
INVX1TS U2008 ( .A(n413), .Y(n412) );
XOR2X1TS U2009 ( .A(n3624), .B(n303), .Y(n3679) );
XOR2X1TS U2010 ( .A(n5454), .B(n6829), .Y(n6206) );
OAI21X1TS U2011 ( .A0(n4520), .A1(n3671), .B0(n3540), .Y(n3541) );
OAI21X1TS U2012 ( .A0(n8190), .A1(n8111), .B0(n8110), .Y(n8116) );
OAI21X1TS U2013 ( .A0(n8190), .A1(n8139), .B0(n8138), .Y(n8144) );
OAI21X1TS U2014 ( .A0(n8190), .A1(n8189), .B0(n8188), .Y(n8195) );
XOR2X1TS U2015 ( .A(n5919), .B(n5981), .Y(n5994) );
NOR2BX2TS U2016 ( .AN(n5673), .B(n5633), .Y(n5679) );
XOR2X1TS U2017 ( .A(n5860), .B(n6274), .Y(n5880) );
XOR2X1TS U2018 ( .A(n5959), .B(n5981), .Y(n5963) );
XOR2X1TS U2019 ( .A(n5975), .B(n6005), .Y(n6015) );
XOR2X1TS U2020 ( .A(n5932), .B(n5981), .Y(n5965) );
XOR2X1TS U2021 ( .A(n5902), .B(n6005), .Y(n5926) );
OAI21X1TS U2022 ( .A0(n6522), .A1(n6224), .B0(n6223), .Y(n6225) );
OAI21X1TS U2023 ( .A0(n6486), .A1(n5763), .B0(n5588), .Y(n5589) );
XOR2X1TS U2024 ( .A(n5800), .B(n5853), .Y(n6039) );
XOR2X1TS U2025 ( .A(n3667), .B(n303), .Y(n3696) );
OAI21X1TS U2026 ( .A0(n6383), .A1(n6073), .B0(n5711), .Y(n5712) );
OAI21X1TS U2027 ( .A0(n6383), .A1(n5684), .B0(n5542), .Y(n5543) );
OAI21X1TS U2028 ( .A0(n6486), .A1(n6073), .B0(n5723), .Y(n5724) );
OAI21X1TS U2029 ( .A0(n117), .A1(n4135), .B0(n3284), .Y(n3285) );
BUFX6TS U2030 ( .A(n5426), .Y(n5502) );
XOR2X1TS U2031 ( .A(n3646), .B(n3672), .Y(n3650) );
OAI21X1TS U2032 ( .A0(n6486), .A1(n6224), .B0(n6202), .Y(n6203) );
XOR2X1TS U2033 ( .A(n5849), .B(n5853), .Y(n5856) );
INVX1TS U2034 ( .A(n5469), .Y(n904) );
INVX4TS U2035 ( .A(n160), .Y(n257) );
XOR2X1TS U2036 ( .A(n3632), .B(n3672), .Y(n3658) );
XOR2X1TS U2037 ( .A(n3612), .B(n4242), .Y(n3629) );
XOR2X1TS U2038 ( .A(n3539), .B(n3832), .Y(n3571) );
OAI21X1TS U2039 ( .A0(n6486), .A1(n5684), .B0(n5385), .Y(n5386) );
OAI21X1TS U2040 ( .A0(n5426), .A1(n5418), .B0(n5417), .Y(n447) );
OAI21X1TS U2041 ( .A0(n6522), .A1(n6004), .B0(n5815), .Y(n5816) );
OAI21X1TS U2042 ( .A0(n6383), .A1(n5763), .B0(n5662), .Y(n5663) );
XOR2X1TS U2043 ( .A(n3607), .B(n4297), .Y(n3626) );
XOR2X1TS U2044 ( .A(n5823), .B(n6402), .Y(n5886) );
XOR2X1TS U2045 ( .A(n5951), .B(n5981), .Y(n5955) );
XOR2X1TS U2046 ( .A(n5825), .B(n5853), .Y(n5885) );
OAI21X1TS U2047 ( .A0(n6522), .A1(n6073), .B0(n6072), .Y(n6074) );
OAI21X1TS U2048 ( .A0(n5426), .A1(n5332), .B0(n5331), .Y(n5335) );
XOR2X1TS U2049 ( .A(n5617), .B(n6390), .Y(n5656) );
NOR2X1TS U2050 ( .A(n7659), .B(n7658), .Y(n7549) );
OAI21X1TS U2051 ( .A0(n179), .A1(n6073), .B0(n5739), .Y(n5740) );
OAI21X1TS U2052 ( .A0(n179), .A1(n5763), .B0(n5681), .Y(n5682) );
OAI21X1TS U2053 ( .A0(n4278), .A1(n3671), .B0(n3631), .Y(n3632) );
OAI21X1TS U2054 ( .A0(n6235), .A1(n5980), .B0(n5931), .Y(n5932) );
OAI21X1TS U2055 ( .A0(n6235), .A1(n6224), .B0(n5538), .Y(n5539) );
OAI21X1TS U2056 ( .A0(n6235), .A1(n5684), .B0(n5658), .Y(n5659) );
XOR2X2TS U2057 ( .A(n868), .B(n5351), .Y(n6383) );
OAI21X1TS U2058 ( .A0(n161), .A1(n6521), .B0(n6195), .Y(n6196) );
XOR2X1TS U2059 ( .A(n3815), .B(n3814), .Y(n3885) );
OAI21X1TS U2060 ( .A0(n179), .A1(n6224), .B0(n5280), .Y(n5281) );
INVX6TS U2061 ( .A(n630), .Y(n1224) );
ADDHX2TS U2062 ( .A(n4626), .B(n3674), .CO(n3578), .S(n3690) );
OAI21X1TS U2063 ( .A0(n6235), .A1(n5763), .B0(n5686), .Y(n5687) );
XOR2X1TS U2064 ( .A(n5907), .B(n6005), .Y(n5929) );
XOR2X1TS U2065 ( .A(n3995), .B(n4970), .Y(n4126) );
OAI21X1TS U2066 ( .A0(n8188), .A1(n8010), .B0(n8009), .Y(n8011) );
NOR2X1TS U2067 ( .A(n8189), .B(n8010), .Y(n8012) );
OAI21XLTS U2068 ( .A0(n8274), .A1(n8261), .B0(n8260), .Y(n8267) );
OAI21X1TS U2069 ( .A0(n5937), .A1(n6273), .B0(n979), .Y(n5911) );
XOR2X2TS U2070 ( .A(n3479), .B(n4044), .Y(n3532) );
XOR2X1TS U2071 ( .A(n5914), .B(n6005), .Y(n5944) );
ADDHX2TS U2072 ( .A(n6963), .B(n5624), .CO(n5615), .S(n6077) );
OAI21X1TS U2073 ( .A0(n562), .A1(n561), .B0(n559), .Y(n558) );
INVX1TS U2074 ( .A(n7551), .Y(n7553) );
NOR2X1TS U2075 ( .A(n473), .B(n198), .Y(n5686) );
INVX6TS U2076 ( .A(n1326), .Y(n2168) );
INVX1TS U2077 ( .A(n7299), .Y(n7301) );
AOI21X1TS U2078 ( .A0(n717), .A1(n1317), .B0(n716), .Y(n715) );
XOR2X1TS U2079 ( .A(n3782), .B(n4548), .Y(n3814) );
INVX1TS U2080 ( .A(n8137), .Y(n8138) );
INVX1TS U2081 ( .A(n8206), .Y(n8207) );
XOR2X1TS U2082 ( .A(n3639), .B(n4106), .Y(n3642) );
INVX1TS U2083 ( .A(GEN1_right_N0), .Y(n3636) );
XOR2X1TS U2084 ( .A(n3635), .B(n4106), .Y(n7551) );
INVX1TS U2085 ( .A(n7813), .Y(n735) );
NAND2BXLTS U2086 ( .AN(n475), .B(n298), .Y(n472) );
XOR2X1TS U2087 ( .A(n5943), .B(n5942), .Y(n5946) );
INVX1TS U2088 ( .A(GEN1_left_N0), .Y(n5939) );
XOR2X1TS U2089 ( .A(n5938), .B(n5942), .Y(n7299) );
XOR2X1TS U2090 ( .A(n3845), .B(n4444), .Y(n3905) );
XOR2X1TS U2091 ( .A(n3232), .B(n4444), .Y(n3265) );
OAI21X1TS U2092 ( .A0(n6186), .A1(n5913), .B0(n980), .Y(n5914) );
OAI21X1TS U2093 ( .A0(n8229), .A1(n7968), .B0(n7967), .Y(n8249) );
OAI21X1TS U2094 ( .A0(n8162), .A1(n8004), .B0(n8003), .Y(n8005) );
NOR2X1TS U2095 ( .A(n8163), .B(n8004), .Y(n8006) );
OAI21X1TS U2096 ( .A0(n8110), .A1(n7998), .B0(n7997), .Y(n8137) );
NOR2X1TS U2097 ( .A(n8111), .B(n7998), .Y(n8136) );
OAI21X1TS U2098 ( .A0(n8065), .A1(n7988), .B0(n7987), .Y(n7989) );
NOR2X1TS U2099 ( .A(n8064), .B(n7988), .Y(n7990) );
OAI21X1TS U2100 ( .A0(n8022), .A1(n7982), .B0(n7981), .Y(n8044) );
NOR2X1TS U2101 ( .A(n8021), .B(n7982), .Y(n8045) );
OAI21X1TS U2102 ( .A0(n8272), .A1(n7974), .B0(n7973), .Y(n7975) );
INVX1TS U2103 ( .A(n8205), .Y(n8208) );
OAI21X1TS U2104 ( .A0(n8199), .A1(GEN1_Final_add_x_1_n95), .B0(
GEN1_Final_add_x_1_n96), .Y(n8206) );
INVX1TS U2105 ( .A(n3859), .Y(n3801) );
INVX1TS U2106 ( .A(n3854), .Y(n3800) );
NAND2XLTS U2107 ( .A(n6300), .B(n289), .Y(n407) );
NAND2BXLTS U2108 ( .AN(n475), .B(n6425), .Y(n474) );
OAI21X1TS U2109 ( .A0(n3262), .A1(n3638), .B0(n966), .Y(GEN1_right_N0) );
NOR2X1TS U2110 ( .A(n3301), .B(n3381), .Y(n3304) );
OAI21X1TS U2111 ( .A0(n5219), .A1(n5941), .B0(n200), .Y(GEN1_left_N0) );
NAND2BX2TS U2112 ( .AN(n452), .B(n5243), .Y(n5245) );
CLKINVX2TS U2113 ( .A(n5425), .Y(n453) );
AO21XLTS U2114 ( .A0(n4096), .A1(Data_B_i[26]), .B0(n4095), .Y(n4097) );
BUFX3TS U2115 ( .A(n4027), .Y(n5083) );
NOR2X1TS U2116 ( .A(n4000), .B(n4072), .Y(n4003) );
OAI21X1TS U2117 ( .A0(n4001), .A1(n4072), .B0(n4094), .Y(n4002) );
OAI21X1TS U2118 ( .A0(n5246), .A1(n5419), .B0(n5458), .Y(n5247) );
NOR2X1TS U2119 ( .A(n5239), .B(n5419), .Y(n5248) );
OAI21X1TS U2120 ( .A0(n5937), .A1(n6401), .B0(n973), .Y(n5899) );
INVX1TS U2121 ( .A(n5318), .Y(n306) );
INVX1TS U2122 ( .A(n1347), .Y(n1044) );
NOR2X1TS U2123 ( .A(n762), .B(n761), .Y(n760) );
INVX1TS U2124 ( .A(n8175), .Y(n8176) );
NOR2X1TS U2125 ( .A(n8200), .B(GEN1_Final_add_x_1_n95), .Y(n8205) );
NAND2BX1TS U2126 ( .AN(n1304), .B(n1019), .Y(n756) );
INVX1TS U2127 ( .A(n5363), .Y(n5197) );
INVX1TS U2128 ( .A(n5364), .Y(n5194) );
INVX1TS U2129 ( .A(n5493), .Y(n5496) );
NOR2X1TS U2130 ( .A(n1046), .B(n1318), .Y(n1049) );
AND3X4TS U2131 ( .A(n942), .B(n5337), .C(n5336), .Y(n5999) );
OAI21X1TS U2132 ( .A0(n1047), .A1(n1318), .B0(n1319), .Y(n1048) );
INVX1TS U2133 ( .A(n1348), .Y(n1349) );
NAND2BXLTS U2134 ( .AN(n390), .B(n6536), .Y(n389) );
NAND2BXLTS U2135 ( .AN(n560), .B(n6197), .Y(n553) );
INVX1TS U2136 ( .A(n1015), .Y(n761) );
INVX1TS U2137 ( .A(n1012), .Y(n762) );
INVX1TS U2138 ( .A(n3425), .Y(n3427) );
NAND2BXLTS U2139 ( .AN(n475), .B(n6815), .Y(n464) );
INVX1TS U2140 ( .A(n4072), .Y(n4073) );
INVX1TS U2141 ( .A(n1167), .Y(n1158) );
INVX1TS U2142 ( .A(n3376), .Y(n3302) );
OAI21X1TS U2143 ( .A0(n1167), .A1(n1166), .B0(n1165), .Y(n1168) );
INVX1TS U2144 ( .A(n5460), .Y(n5246) );
INVX1TS U2145 ( .A(n4096), .Y(n4001) );
INVX1TS U2146 ( .A(n4092), .Y(n4000) );
NAND2X1TS U2147 ( .A(n5450), .B(n5449), .Y(n5451) );
NAND2XLTS U2148 ( .A(n5699), .B(n6482), .Y(n435) );
OAI21X1TS U2149 ( .A0(GEN1_Final_add_x_1_n131), .A1(GEN1_Final_add_x_1_n137),
.B0(GEN1_Final_add_x_1_n132), .Y(n8175) );
NOR2X1TS U2150 ( .A(GEN1_Final_add_x_1_n136), .B(GEN1_Final_add_x_1_n131),
.Y(n8174) );
NOR2X1TS U2151 ( .A(GEN1_Final_add_x_1_n228), .B(GEN1_Final_add_x_1_n225),
.Y(n7986) );
NOR2X1TS U2152 ( .A(GEN1_Final_add_x_1_n203), .B(GEN1_Final_add_x_1_n198),
.Y(n7994) );
NOR2X1TS U2153 ( .A(GEN1_Final_add_x_1_n213), .B(GEN1_Final_add_x_1_n210),
.Y(n8097) );
OAI21X1TS U2154 ( .A0(GEN1_Final_add_x_1_n173), .A1(GEN1_Final_add_x_1_n179),
.B0(GEN1_Final_add_x_1_n174), .Y(n7995) );
OAI21X1TS U2155 ( .A0(GEN1_Final_add_x_1_n210), .A1(GEN1_Final_add_x_1_n214),
.B0(GEN1_Final_add_x_1_n211), .Y(n8098) );
OAI21X1TS U2156 ( .A0(GEN1_Final_add_x_1_n185), .A1(GEN1_Final_add_x_1_n191),
.B0(GEN1_Final_add_x_1_n186), .Y(n8122) );
OAI21X1TS U2157 ( .A0(GEN1_Final_add_x_1_n233), .A1(GEN1_Final_add_x_1_n237),
.B0(GEN1_Final_add_x_1_n234), .Y(n8078) );
NOR2X1TS U2158 ( .A(GEN1_Final_add_x_1_n178), .B(GEN1_Final_add_x_1_n173),
.Y(n7996) );
OAI21X1TS U2159 ( .A0(GEN1_Final_add_x_1_n156), .A1(GEN1_Final_add_x_1_n162),
.B0(GEN1_Final_add_x_1_n157), .Y(n8150) );
NOR2X1TS U2160 ( .A(GEN1_Final_add_x_1_n161), .B(GEN1_Final_add_x_1_n156),
.Y(n8149) );
NOR2X1TS U2161 ( .A(GEN1_Final_add_x_1_n236), .B(GEN1_Final_add_x_1_n233),
.Y(n8079) );
OAI21X1TS U2162 ( .A0(GEN1_Final_add_x_1_n198), .A1(GEN1_Final_add_x_1_n204),
.B0(GEN1_Final_add_x_1_n199), .Y(n7993) );
NOR2X1TS U2163 ( .A(GEN1_Final_add_x_1_n149), .B(GEN1_Final_add_x_1_n144),
.Y(n8000) );
NOR2X1TS U2164 ( .A(GEN1_Final_add_x_1_n124), .B(GEN1_Final_add_x_1_n119),
.Y(n8002) );
NOR2X1TS U2165 ( .A(GEN1_Final_add_x_1_n351), .B(GEN1_Final_add_x_1_n348),
.Y(n8258) );
NOR2X1TS U2166 ( .A(GEN1_Final_add_x_1_n341), .B(GEN1_Final_add_x_1_n336),
.Y(n7970) );
OAI21X1TS U2167 ( .A0(GEN1_Final_add_x_1_n348), .A1(GEN1_Final_add_x_1_n352),
.B0(GEN1_Final_add_x_1_n349), .Y(n8259) );
NOR2X1TS U2168 ( .A(GEN1_Final_add_x_1_n328), .B(GEN1_Final_add_x_1_n323),
.Y(n8284) );
NOR2X1TS U2169 ( .A(GEN1_Final_add_x_1_n316), .B(GEN1_Final_add_x_1_n311),
.Y(n7972) );
OAI21X1TS U2170 ( .A0(GEN1_Final_add_x_1_n323), .A1(GEN1_Final_add_x_1_n329),
.B0(GEN1_Final_add_x_1_n324), .Y(n8285) );
NOR2X1TS U2171 ( .A(GEN1_Final_add_x_1_n301), .B(GEN1_Final_add_x_1_n296),
.Y(n8015) );
NOR2X1TS U2172 ( .A(GEN1_Final_add_x_1_n291), .B(GEN1_Final_add_x_1_n288),
.Y(n7978) );
OAI21X1TS U2173 ( .A0(GEN1_Final_add_x_1_n296), .A1(GEN1_Final_add_x_1_n302),
.B0(GEN1_Final_add_x_1_n297), .Y(n8014) );
NOR2X1TS U2174 ( .A(GEN1_Final_add_x_1_n278), .B(GEN1_Final_add_x_1_n275),
.Y(n8034) );
NOR2X1TS U2175 ( .A(GEN1_Final_add_x_1_n270), .B(GEN1_Final_add_x_1_n267),
.Y(n7980) );
OAI21X1TS U2176 ( .A0(GEN1_Final_add_x_1_n275), .A1(GEN1_Final_add_x_1_n279),
.B0(GEN1_Final_add_x_1_n276), .Y(n8033) );
NOR2X1TS U2177 ( .A(GEN1_Final_add_x_1_n257), .B(GEN1_Final_add_x_1_n254),
.Y(n8055) );
NOR2X1TS U2178 ( .A(GEN1_Final_add_x_1_n249), .B(GEN1_Final_add_x_1_n246),
.Y(n7984) );
OAI21X1TS U2179 ( .A0(GEN1_Final_add_x_1_n254), .A1(GEN1_Final_add_x_1_n258),
.B0(GEN1_Final_add_x_1_n255), .Y(n8054) );
OAI21X1TS U2180 ( .A0(GEN1_Final_add_x_1_n367), .A1(GEN1_Final_add_x_1_n373),
.B0(GEN1_Final_add_x_1_n368), .Y(n8238) );
INVX2TS U2181 ( .A(n3246), .Y(n3248) );
AND2X2TS U2182 ( .A(n7419), .B(n4972), .Y(n5076) );
AND2X2TS U2183 ( .A(n7199), .B(n6685), .Y(n6790) );
CLKAND2X2TS U2184 ( .A(n6902), .B(n6659), .Y(n6744) );
INVX1TS U2185 ( .A(n3288), .Y(n3243) );
AND2X2TS U2186 ( .A(n1135), .B(n1134), .Y(n971) );
INVX1TS U2187 ( .A(n5427), .Y(n5260) );
INVX1TS U2188 ( .A(n3852), .Y(n3806) );
INVX1TS U2189 ( .A(n5387), .Y(n5389) );
AND2X2TS U2190 ( .A(n4849), .B(n4785), .Y(n4974) );
AND2X2TS U2191 ( .A(n1286), .B(n1285), .Y(n969) );
INVX1TS U2192 ( .A(n5441), .Y(n5442) );
INVX1TS U2193 ( .A(n5263), .Y(n5265) );
NAND2X1TS U2194 ( .A(n1103), .B(n1102), .Y(n1104) );
INVX1TS U2195 ( .A(n5448), .Y(n5450) );
NAND2XLTS U2196 ( .A(n5746), .B(n5912), .Y(n974) );
INVX1TS U2197 ( .A(n5302), .Y(n5303) );
INVX1TS U2198 ( .A(n1388), .Y(n1391) );
INVX1TS U2199 ( .A(n1216), .Y(n1028) );
INVX1TS U2200 ( .A(n5373), .Y(n5322) );
AND2X2TS U2201 ( .A(n1276), .B(n1275), .Y(n957) );
INVX1TS U2202 ( .A(n5397), .Y(n5399) );
INVX1TS U2203 ( .A(n3877), .Y(n3879) );
INVX1TS U2204 ( .A(n1267), .Y(n1270) );
INVX1TS U2205 ( .A(n5225), .Y(n5202) );
INVX2TS U2206 ( .A(n5367), .Y(n5369) );
INVX1TS U2207 ( .A(n3351), .Y(n3268) );
INVX1TS U2208 ( .A(n1314), .Y(n1046) );
INVX1TS U2209 ( .A(n3853), .Y(n3791) );
INVX1TS U2210 ( .A(n1313), .Y(n1047) );
NOR2X1TS U2211 ( .A(n241), .B(n4934), .Y(n3788) );
AND2X2TS U2212 ( .A(n4849), .B(Data_B_i[15]), .Y(n4787) );
INVX1TS U2213 ( .A(n3404), .Y(n3421) );
INVX1TS U2214 ( .A(n4055), .Y(n4056) );
INVX1TS U2215 ( .A(n5503), .Y(n5505) );
CLKAND2X2TS U2216 ( .A(n4849), .B(n283), .Y(n4307) );
AND2X2TS U2217 ( .A(n7199), .B(n6981), .Y(n7200) );
BUFX3TS U2218 ( .A(n6960), .Y(n6735) );
AND2X2TS U2219 ( .A(n6902), .B(n6870), .Y(n6944) );
NOR2X2TS U2220 ( .A(n5259), .B(n5263), .Y(n5492) );
INVX1TS U2221 ( .A(n1197), .Y(n645) );
CLKAND2X2TS U2222 ( .A(n4849), .B(n3982), .Y(n4272) );
INVX1TS U2223 ( .A(n1032), .Y(n1013) );
INVX1TS U2224 ( .A(n5403), .Y(n5404) );
NOR2X2TS U2225 ( .A(n5355), .B(n5448), .Y(n5364) );
INVX1TS U2226 ( .A(n1106), .Y(n1088) );
AOI21X2TS U2227 ( .A0(n1039), .A1(n1313), .B0(n1038), .Y(n810) );
INVX1TS U2228 ( .A(n1105), .Y(n1091) );
INVX1TS U2229 ( .A(n1346), .Y(n1350) );
INVX1TS U2230 ( .A(n3419), .Y(n3420) );
OR2X2TS U2231 ( .A(n1855), .B(n1854), .Y(n986) );
INVX1TS U2232 ( .A(n4611), .Y(n153) );
NOR2X1TS U2233 ( .A(n4785), .B(n241), .Y(n3425) );
NAND2XLTS U2234 ( .A(n4750), .B(n3978), .Y(n199) );
AND2X2TS U2235 ( .A(n6902), .B(n6788), .Y(n6872) );
NOR2X1TS U2236 ( .A(Q_right[42]), .B(S_B[15]), .Y(GEN1_Final_add_x_1_n311)
);
NOR2X1TS U2237 ( .A(Q_right[40]), .B(S_B[13]), .Y(GEN1_Final_add_x_1_n323)
);
NOR2X1TS U2238 ( .A(Q_right[41]), .B(S_B[14]), .Y(GEN1_Final_add_x_1_n316)
);
NOR2X1TS U2239 ( .A(Q_right[39]), .B(S_B[12]), .Y(GEN1_Final_add_x_1_n328)
);
NOR2X1TS U2240 ( .A(Q_right[38]), .B(S_B[11]), .Y(GEN1_Final_add_x_1_n336)
);
NOR2XLTS U2241 ( .A(Q_right[28]), .B(S_B[1]), .Y(GEN1_Final_add_x_1_n385) );
NOR2X1TS U2242 ( .A(Q_left[23]), .B(S_B[50]), .Y(GEN1_Final_add_x_1_n95) );
NOR2X1TS U2243 ( .A(Q_left[18]), .B(S_B[45]), .Y(GEN1_Final_add_x_1_n131) );
NOR2X1TS U2244 ( .A(Q_left[16]), .B(S_B[43]), .Y(GEN1_Final_add_x_1_n144) );
NOR2X1TS U2245 ( .A(Q_left[14]), .B(S_B[41]), .Y(GEN1_Final_add_x_1_n156) );
NOR2X1TS U2246 ( .A(Q_right[52]), .B(S_B[25]), .Y(GEN1_Final_add_x_1_n254)
);
NOR2X1TS U2247 ( .A(Q_right[53]), .B(S_B[26]), .Y(GEN1_Final_add_x_1_n249)
);
NOR2X1TS U2248 ( .A(Q_left[0]), .B(S_B[27]), .Y(GEN1_Final_add_x_1_n246) );
NOR2X1TS U2249 ( .A(Q_right[51]), .B(S_B[24]), .Y(GEN1_Final_add_x_1_n257)
);
NOR2X1TS U2250 ( .A(Q_right[50]), .B(S_B[23]), .Y(GEN1_Final_add_x_1_n267)
);
NOR2X1TS U2251 ( .A(Q_left[3]), .B(S_B[30]), .Y(GEN1_Final_add_x_1_n228) );
NOR2X1TS U2252 ( .A(Q_left[2]), .B(S_B[29]), .Y(GEN1_Final_add_x_1_n233) );
NOR2X1TS U2253 ( .A(Q_right[48]), .B(S_B[21]), .Y(GEN1_Final_add_x_1_n275)
);
NOR2X1TS U2254 ( .A(Q_right[49]), .B(S_B[22]), .Y(GEN1_Final_add_x_1_n270)
);
NOR2X1TS U2255 ( .A(Q_left[6]), .B(S_B[33]), .Y(GEN1_Final_add_x_1_n210) );
NOR2X1TS U2256 ( .A(Q_right[47]), .B(S_B[20]), .Y(GEN1_Final_add_x_1_n278)
);
NOR2X1TS U2257 ( .A(Q_left[8]), .B(S_B[35]), .Y(GEN1_Final_add_x_1_n198) );
NOR2X1TS U2258 ( .A(Q_right[46]), .B(S_B[19]), .Y(GEN1_Final_add_x_1_n288)
);
NOR2X1TS U2259 ( .A(Q_left[11]), .B(S_B[38]), .Y(GEN1_Final_add_x_1_n178) );
NOR2X1TS U2260 ( .A(Q_left[9]), .B(S_B[36]), .Y(GEN1_Final_add_x_1_n190) );
NOR2X1TS U2261 ( .A(Q_right[44]), .B(S_B[17]), .Y(GEN1_Final_add_x_1_n296)
);
INVX1TS U2262 ( .A(n6428), .Y(n561) );
INVX2TS U2263 ( .A(n1192), .Y(n1194) );
INVX1TS U2264 ( .A(n1174), .Y(n1176) );
INVX2TS U2265 ( .A(n1378), .Y(n1380) );
NAND2BX1TS U2266 ( .AN(n3367), .B(n3369), .Y(n3535) );
INVX1TS U2267 ( .A(n5348), .Y(n5350) );
INVX2TS U2268 ( .A(n3381), .Y(n3383) );
INVX2TS U2269 ( .A(n1384), .Y(n1228) );
NOR2X2TS U2270 ( .A(n864), .B(n5219), .Y(n5189) );
INVX1TS U2271 ( .A(n3390), .Y(n3391) );
NOR2X1TS U2272 ( .A(n4972), .B(n4934), .Y(n3877) );
OAI21X2TS U2273 ( .A0(n1027), .A1(n1102), .B0(n1026), .Y(n1216) );
INVX1TS U2274 ( .A(n3327), .Y(n3329) );
INVX1TS U2275 ( .A(n1201), .Y(n1196) );
INVX1TS U2276 ( .A(n3279), .Y(n3281) );
CLKAND2X2TS U2277 ( .A(n3226), .B(n3225), .Y(n914) );
INVX1TS U2278 ( .A(n1109), .Y(n1111) );
NOR2X4TS U2279 ( .A(n1066), .B(n1378), .Y(n1106) );
INVX1TS U2280 ( .A(n5374), .Y(n5375) );
INVX1TS U2281 ( .A(n5380), .Y(n5382) );
INVX1TS U2282 ( .A(n1293), .Y(n1157) );
INVX1TS U2283 ( .A(n1233), .Y(n1234) );
OAI21X2TS U2284 ( .A0(n1075), .A1(n1081), .B0(n1076), .Y(n1313) );
INVX2TS U2285 ( .A(n5472), .Y(n5343) );
AND2X2TS U2286 ( .A(n1294), .B(n1293), .Y(n992) );
NOR2X1TS U2287 ( .A(n4785), .B(n4794), .Y(n3404) );
INVX1TS U2288 ( .A(n5315), .Y(n5284) );
INVX1TS U2289 ( .A(n1301), .Y(n1290) );
INVX1TS U2290 ( .A(n6519), .Y(n390) );
AND3X2TS U2291 ( .A(n5252), .B(n5253), .C(n5254), .Y(n5976) );
AND2X2TS U2292 ( .A(n1114), .B(n1045), .Y(n169) );
NOR2X1TS U2293 ( .A(Data_B_i[53]), .B(Data_B_i[26]), .Y(n1166) );
NOR2X1TS U2294 ( .A(Data_B_i[3]), .B(Data_B_i[4]), .Y(n3234) );
NOR2X1TS U2295 ( .A(Data_B_i[31]), .B(Data_B_i[32]), .Y(n5285) );
NOR2X4TS U2296 ( .A(Data_B_i[42]), .B(Data_B_i[15]), .Y(n1096) );
NOR2X1TS U2297 ( .A(Data_B_i[15]), .B(Data_B_i[14]), .Y(n3307) );
NAND2X1TS U2298 ( .A(n250), .B(n2548), .Y(n606) );
XNOR2X1TS U2299 ( .A(n250), .B(n2559), .Y(n1924) );
XNOR2X1TS U2300 ( .A(n2219), .B(n250), .Y(n2345) );
OAI21X1TS U2301 ( .A0(n1127), .A1(n1126), .B0(n1125), .Y(n1131) );
XOR2X1TS U2302 ( .A(n4090), .B(n4813), .Y(n4255) );
OAI21X1TS U2303 ( .A0(n2742), .A1(n2743), .B0(n2741), .Y(n664) );
OAI21X1TS U2304 ( .A0(n2771), .A1(n2772), .B0(n2770), .Y(n709) );
OAI2BB1X1TS U2305 ( .A0N(n2772), .A1N(n2771), .B0(n709), .Y(n2781) );
OAI22X2TS U2306 ( .A0(n3199), .A1(n2816), .B0(n309), .B1(n2867), .Y(n2880)
);
BUFX6TS U2307 ( .A(n2554), .Y(n3199) );
OAI21X1TS U2308 ( .A0(n4995), .A1(n4105), .B0(n4066), .Y(n4067) );
NOR2X1TS U2309 ( .A(n4997), .B(n5060), .Y(n3852) );
OAI2BB1X1TS U2310 ( .A0N(n7172), .A1N(n985), .B0(n7178), .Y(n7182) );
XOR2X2TS U2311 ( .A(n349), .B(n176), .Y(GEN1_middle_N51) );
OAI21X1TS U2312 ( .A0(n1939), .A1(n1940), .B0(n1938), .Y(n832) );
NAND2X2TS U2313 ( .A(n6482), .B(Data_B_i[38]), .Y(n5381) );
OA21X4TS U2314 ( .A0(n5230), .A1(n5353), .B0(n5229), .Y(n461) );
OAI21X1TS U2315 ( .A0(n6899), .A1(n6082), .B0(n5648), .Y(n5649) );
OAI22X2TS U2316 ( .A0(n312), .A1(n1896), .B0(n2869), .B1(n2372), .Y(n2383)
);
AOI21X1TS U2317 ( .A0(n5972), .A1(n7286), .B0(n5971), .Y(n7385) );
OAI21X4TS U2318 ( .A0(n7154), .A1(n625), .B0(n624), .Y(n7664) );
BUFX4TS U2319 ( .A(n1598), .Y(n2924) );
NAND2BX2TS U2320 ( .AN(n3714), .B(n912), .Y(n7625) );
XOR2X1TS U2321 ( .A(n3537), .B(n3796), .Y(n3595) );
NOR2XLTS U2322 ( .A(n7886), .B(n7856), .Y(n129) );
ADDFX2TS U2323 ( .A(n2806), .B(n2805), .CI(n2804), .CO(n2854), .S(n2821) );
XNOR2X1TS U2324 ( .A(n2862), .B(n270), .Y(n2812) );
ADDFHX2TS U2325 ( .A(n2404), .B(n2403), .CI(n2402), .CO(n2409), .S(n2412) );
NOR2X2TS U2326 ( .A(n4923), .B(n5019), .Y(n7404) );
XOR2X1TS U2327 ( .A(n4814), .B(n4813), .Y(n4860) );
AOI21X2TS U2328 ( .A0(n7936), .A1(n162), .B0(n2295), .Y(n691) );
OR2X6TS U2329 ( .A(n2294), .B(n2293), .Y(n162) );
XNOR2X2TS U2330 ( .A(n265), .B(n2182), .Y(n2146) );
CLKINVX3TS U2331 ( .A(n2868), .Y(n252) );
BUFX3TS U2332 ( .A(n1816), .Y(n130) );
OAI21X1TS U2333 ( .A0(n7886), .A1(n7883), .B0(n7887), .Y(n132) );
CLKINVX3TS U2334 ( .A(n1453), .Y(n2940) );
BUFX3TS U2335 ( .A(n2853), .Y(n133) );
ADDFHX2TS U2336 ( .A(n2828), .B(n2827), .CI(n2826), .CO(n2853), .S(n2824) );
XOR2X2TS U2337 ( .A(n1939), .B(n1940), .Y(n596) );
OAI2BB1X2TS U2338 ( .A0N(n1940), .A1N(n1939), .B0(n832), .Y(n1966) );
XNOR2X1TS U2339 ( .A(n1976), .B(n2440), .Y(n1982) );
OAI21X1TS U2340 ( .A0(n1392), .A1(n1095), .B0(n1094), .Y(n1100) );
OAI21X1TS U2341 ( .A0(n4304), .A1(n330), .B0(n3333), .Y(n3334) );
CLKINVX1TS U2342 ( .A(n5424), .Y(n5499) );
INVX2TS U2343 ( .A(n7410), .Y(n4924) );
OAI21X2TS U2344 ( .A0(n4923), .A1(n5021), .B0(n4922), .Y(n7410) );
NAND2X2TS U2345 ( .A(n2522), .B(n135), .Y(n136) );
NAND2X1TS U2346 ( .A(n134), .B(n2521), .Y(n137) );
NAND2X2TS U2347 ( .A(n136), .B(n137), .Y(n2524) );
INVX2TS U2348 ( .A(n2522), .Y(n134) );
INVX2TS U2349 ( .A(n2521), .Y(n135) );
XOR2X2TS U2350 ( .A(n2479), .B(n2478), .Y(n2477) );
INVX2TS U2351 ( .A(n138), .Y(n2501) );
NAND2X1TS U2352 ( .A(n2479), .B(n2478), .Y(n138) );
OAI21X1TS U2353 ( .A0(n2849), .A1(n2030), .B0(n638), .Y(n2845) );
OAI22X2TS U2354 ( .A0(n332), .A1(n2694), .B0(n2847), .B1(n226), .Y(n2844) );
XOR2X2TS U2355 ( .A(n350), .B(n165), .Y(GEN1_middle_N54) );
NOR2X4TS U2356 ( .A(n7886), .B(n7856), .Y(n7872) );
INVX4TS U2357 ( .A(n2909), .Y(n360) );
XOR2X1TS U2358 ( .A(n2909), .B(n2928), .Y(n2363) );
INVX4TS U2359 ( .A(n1906), .Y(n139) );
OAI21X1TS U2360 ( .A0(n6619), .A1(n338), .B0(n6269), .Y(n6270) );
ADDFHX2TS U2361 ( .A(n4314), .B(n4313), .CI(n4312), .CO(n4382), .S(n4341) );
XOR2X2TS U2362 ( .A(n3356), .B(n3355), .Y(n4421) );
OAI21X1TS U2363 ( .A0(n4421), .A1(n4440), .B0(n4266), .Y(n4267) );
OAI21XLTS U2364 ( .A0(n4826), .A1(n4241), .B0(n3881), .Y(n3882) );
OAI21X1TS U2365 ( .A0(n4826), .A1(n4832), .B0(n4679), .Y(n839) );
INVX3TS U2366 ( .A(n2944), .Y(n345) );
OAI22X1TS U2367 ( .A0(n333), .A1(n2148), .B0(n2937), .B1(n2104), .Y(n2158)
);
OAI2BB1X2TS U2368 ( .A0N(n3106), .A1N(n696), .B0(n694), .Y(n3140) );
NOR2X4TS U2369 ( .A(n3141), .B(n3140), .Y(n7823) );
OAI22X2TS U2370 ( .A0(n5151), .A1(n2648), .B0(n2570), .B1(n5149), .Y(n2679)
);
OAI21X4TS U2371 ( .A0(n1192), .A1(n1249), .B0(n1193), .Y(n1199) );
NAND2X4TS U2372 ( .A(n2539), .B(n2540), .Y(n841) );
OAI21X2TS U2373 ( .A0(n7950), .A1(n7947), .B0(n7948), .Y(n7794) );
OAI22X1TS U2374 ( .A0(n2246), .A1(n2224), .B0(n2191), .B1(n2453), .Y(n2209)
);
NAND2X2TS U2375 ( .A(n2536), .B(n2535), .Y(n7770) );
AOI21X2TS U2376 ( .A0(n7664), .A1(n6569), .B0(n6568), .Y(n6570) );
XNOR2X2TS U2377 ( .A(n5147), .B(n2899), .Y(n1452) );
INVX2TS U2378 ( .A(n2885), .Y(n140) );
INVX2TS U2379 ( .A(n2885), .Y(n141) );
INVX2TS U2380 ( .A(n2885), .Y(n142) );
INVX2TS U2381 ( .A(n2885), .Y(n143) );
INVX2TS U2382 ( .A(n2885), .Y(n144) );
INVX4TS U2383 ( .A(Data_A_i[14]), .Y(n4807) );
XOR2X2TS U2384 ( .A(n4712), .B(Data_A_i[13]), .Y(n3273) );
OAI21X1TS U2385 ( .A0(n330), .A1(n3779), .B0(n3481), .Y(n3482) );
OR2X4TS U2386 ( .A(n152), .B(n151), .Y(n2993) );
XOR2X2TS U2387 ( .A(n2431), .B(n730), .Y(n729) );
ADDFHX2TS U2388 ( .A(n2118), .B(n2117), .CI(n2116), .CO(n2314), .S(n2322) );
OAI22X2TS U2389 ( .A0(n2080), .A1(n326), .B0(n2050), .B1(n2798), .Y(n2063)
);
NAND2BX1TS U2390 ( .AN(n3060), .B(n3059), .Y(n3061) );
OAI21XLTS U2391 ( .A0(n1270), .A1(n1269), .B0(n1268), .Y(n1271) );
CLKINVX1TS U2392 ( .A(n1269), .Y(n589) );
NAND2X1TS U2393 ( .A(n1154), .B(n1264), .Y(n1156) );
ADDFHX2TS U2394 ( .A(n3929), .B(n3928), .CI(n3927), .CO(n3920), .S(n3945) );
OAI21X1TS U2395 ( .A0(n216), .A1(n4988), .B0(n4987), .Y(n5008) );
XOR2X1TS U2396 ( .A(n4629), .B(n4844), .Y(n4660) );
OAI21X1TS U2397 ( .A0(n4718), .A1(n5000), .B0(n4628), .Y(n4629) );
NOR2X6TS U2398 ( .A(Data_A_i[36]), .B(Data_A_i[9]), .Y(n1133) );
OR2X6TS U2399 ( .A(n3157), .B(n3156), .Y(n7715) );
OAI22X2TS U2400 ( .A0(n1857), .A1(n2562), .B0(n1902), .B1(n7812), .Y(n1860)
);
XNOR2X1TS U2401 ( .A(n1223), .B(n2693), .Y(n2614) );
OAI22X2TS U2402 ( .A0(n2934), .A1(n2839), .B0(n2896), .B1(n2931), .Y(n2875)
);
OAI22X2TS U2403 ( .A0(n5182), .A1(n2811), .B0(n2578), .B1(n2883), .Y(n2877)
);
OAI21X1TS U2404 ( .A0(n2030), .A1(n2019), .B0(n647), .Y(n2054) );
NOR2X1TS U2405 ( .A(n6788), .B(n6745), .Y(n5225) );
OAI21X1TS U2406 ( .A0(n6712), .A1(n6401), .B0(n5646), .Y(n5647) );
XNOR2X1TS U2407 ( .A(n228), .B(n2911), .Y(n2637) );
INVX4TS U2408 ( .A(n2027), .Y(n2868) );
ADDFHX2TS U2409 ( .A(n2856), .B(n2855), .CI(n2854), .CO(n3030), .S(n2919) );
ADDFHX2TS U2410 ( .A(n2229), .B(n2887), .CI(n2886), .CO(n2985), .S(n2857) );
OAI21X4TS U2411 ( .A0(n586), .A1(n1237), .B0(n1236), .Y(n843) );
BUFX12TS U2412 ( .A(n670), .Y(n586) );
XNOR2X4TS U2413 ( .A(n233), .B(n2894), .Y(n2566) );
ADDFHX2TS U2414 ( .A(n4600), .B(n4599), .CI(n4598), .CO(n4894), .S(n4591) );
NAND2X4TS U2415 ( .A(n2780), .B(n2779), .Y(n7883) );
OAI22X1TS U2416 ( .A0(n347), .A1(n2599), .B0(n301), .B1(n2616), .Y(n2604) );
OAI22X2TS U2417 ( .A0(n2611), .A1(n327), .B0(n2610), .B1(n2609), .Y(n2631)
);
NAND2X4TS U2418 ( .A(n1263), .B(n1598), .Y(n1955) );
XOR2X2TS U2419 ( .A(n2733), .B(n2734), .Y(n363) );
ADDFHX2TS U2420 ( .A(n4398), .B(n4397), .CI(n4396), .CO(n4388), .S(n4402) );
OAI21X1TS U2421 ( .A0(n6284), .A1(n5684), .B0(n5622), .Y(n5623) );
OAI2BB1X2TS U2422 ( .A0N(n2737), .A1N(n2736), .B0(n544), .Y(n2762) );
XOR2X4TS U2423 ( .A(n1505), .B(n1506), .Y(n1486) );
NAND2X1TS U2424 ( .A(n145), .B(n541), .Y(n148) );
INVX2TS U2425 ( .A(n2756), .Y(n145) );
INVX2TS U2426 ( .A(n541), .Y(n146) );
XOR2X4TS U2427 ( .A(n2647), .B(n2646), .Y(n2626) );
INVX2TS U2428 ( .A(n149), .Y(n2662) );
NAND2X1TS U2429 ( .A(n2647), .B(n2646), .Y(n149) );
OAI22X2TS U2430 ( .A0(n2555), .A1(n2561), .B0(n2562), .B1(n892), .Y(n2647)
);
OAI22X2TS U2431 ( .A0(n325), .A1(n2447), .B0(n2556), .B1(n2931), .Y(n2646)
);
ADDFHX4TS U2432 ( .A(n2626), .B(n2625), .CI(n2624), .CO(n2732), .S(n2749) );
NOR2X2TS U2433 ( .A(n232), .B(n2870), .Y(n151) );
NAND2X4TS U2434 ( .A(n305), .B(n760), .Y(n759) );
ADDFX2TS U2435 ( .A(n5654), .B(n5653), .CI(n5652), .CO(n5669), .S(n6099) );
XOR2X1TS U2436 ( .A(n5607), .B(n6090), .Y(n5653) );
XOR2X1TS U2437 ( .A(n5579), .B(n6390), .Y(n5608) );
CLKINVX1TS U2438 ( .A(n2452), .Y(n1830) );
NOR2X4TS U2439 ( .A(n7710), .B(n7157), .Y(n7684) );
NAND2X6TS U2440 ( .A(n7715), .B(n7723), .Y(n623) );
NOR2X6TS U2441 ( .A(n3136), .B(n3135), .Y(n7842) );
OAI2BB1X2TS U2442 ( .A0N(n674), .A1N(n1950), .B0(n673), .Y(n203) );
OAI22X2TS U2443 ( .A0(n323), .A1(n2608), .B0(n2607), .B1(n2927), .Y(n2632)
);
INVX4TS U2444 ( .A(n665), .Y(n266) );
XNOR2X2TS U2445 ( .A(n266), .B(n2441), .Y(n2447) );
OAI2BB1X4TS U2446 ( .A0N(n2513), .A1N(n702), .B0(n698), .Y(n2523) );
NOR2X4TS U2447 ( .A(n1862), .B(n1333), .Y(n995) );
ADDFHX2TS U2448 ( .A(n2474), .B(n2473), .CI(n2472), .CO(n2495), .S(n2437) );
AOI21X4TS U2449 ( .A0(n1144), .A1(n1330), .B0(n1143), .Y(n865) );
NAND2X2TS U2450 ( .A(n856), .B(n1175), .Y(n1143) );
INVX4TS U2451 ( .A(n816), .Y(n2553) );
ADDFHX2TS U2452 ( .A(n4199), .B(n4200), .CI(n4198), .CO(n4205), .S(n4207) );
NOR2X2TS U2453 ( .A(n7616), .B(n7530), .Y(n7622) );
NOR2X2TS U2454 ( .A(n3321), .B(n3320), .Y(n3553) );
INVX4TS U2455 ( .A(n1121), .Y(n1363) );
XNOR2X2TS U2456 ( .A(n264), .B(n2229), .Y(n2192) );
OAI22X2TS U2457 ( .A0(n2192), .A1(n2222), .B0(n2184), .B1(n2249), .Y(n2206)
);
CLKINVX1TS U2458 ( .A(n7878), .Y(n7880) );
NOR2X1TS U2459 ( .A(n7302), .B(n7112), .Y(n6843) );
OAI21X2TS U2460 ( .A0(n7112), .A1(n7303), .B0(n7113), .Y(n6844) );
OAI21XLTS U2461 ( .A0(n6957), .A1(n6539), .B0(n6411), .Y(n6413) );
NAND2BX1TS U2462 ( .AN(n503), .B(n502), .Y(n5694) );
ADDFHX2TS U2463 ( .A(n1325), .B(n1324), .CI(n1323), .CO(n1309), .S(n3079) );
ADDFHX2TS U2464 ( .A(n6127), .B(n6126), .CI(n6125), .CO(n6133), .S(n6135) );
XOR2X1TS U2465 ( .A(n5676), .B(n6217), .Y(n5732) );
NAND2X4TS U2466 ( .A(n1087), .B(n1816), .Y(n307) );
OAI21X1TS U2467 ( .A0(n2431), .A1(n730), .B0(n2430), .Y(n728) );
ADDFHX2TS U2468 ( .A(n6077), .B(n6076), .CI(n6075), .CO(n5664), .S(n6111) );
OAI21X1TS U2469 ( .A0(n5937), .A1(n338), .B0(n961), .Y(n5632) );
XOR2X1TS U2470 ( .A(n5632), .B(n6390), .Y(n5672) );
ADDFX2TS U2471 ( .A(n4336), .B(n4335), .CI(n4334), .CO(n4342), .S(n4397) );
ADDFHX2TS U2472 ( .A(n2990), .B(n2989), .CI(n2988), .CO(n3081), .S(n3011) );
OAI21X4TS U2473 ( .A0(n7476), .A1(n7484), .B0(n7477), .Y(n4582) );
OAI21X1TS U2474 ( .A0(n116), .A1(n4519), .B0(n4028), .Y(n4029) );
AOI222X1TS U2475 ( .A0(n5063), .A1(n4129), .B0(n4742), .B1(n283), .C0(n317),
.C1(n3982), .Y(n4028) );
ADDFHX2TS U2476 ( .A(n4189), .B(n4188), .CI(n4187), .CO(n4172), .S(n4194) );
ADDFHX2TS U2477 ( .A(n4206), .B(n4205), .CI(n4204), .CO(n4212), .S(n4211) );
XOR2X1TS U2478 ( .A(n4138), .B(Data_A_i[14]), .Y(n4165) );
CMPR22X2TS U2479 ( .A(n7199), .B(n5520), .CO(n5511), .S(n5555) );
OAI21X2TS U2480 ( .A0(n586), .A1(n1300), .B0(n1299), .Y(n684) );
OAI21X2TS U2481 ( .A0(n586), .A1(n1218), .B0(n1217), .Y(n545) );
OR2X1TS U2482 ( .A(n2949), .B(n2948), .Y(n2951) );
XNOR2X2TS U2483 ( .A(n1296), .B(n2894), .Y(n2933) );
ADDFHX4TS U2484 ( .A(n1747), .B(n1746), .CI(n1745), .CO(n3171), .S(n3170) );
ADDFHX2TS U2485 ( .A(n1688), .B(n1687), .CI(n1686), .CO(n1733), .S(n1727) );
ADDFHX2TS U2486 ( .A(n3491), .B(n3490), .CI(n3489), .CO(n3746), .S(n3745) );
AOI222X1TS U2487 ( .A0(n3835), .A1(n4128), .B0(n4470), .B1(n3982), .C0(n4448), .C1(n3772), .Y(n3477) );
NAND3X2TS U2488 ( .A(n1509), .B(n1508), .C(n1507), .Y(n1529) );
NAND2X4TS U2489 ( .A(n2809), .B(n764), .Y(n232) );
XOR2X2TS U2490 ( .A(n601), .B(n794), .Y(n3167) );
XOR2X2TS U2491 ( .A(n3793), .B(n3792), .Y(n4847) );
ADDFHX2TS U2492 ( .A(n2489), .B(n2488), .CI(n2487), .CO(n2728), .S(n2466) );
OAI22X2TS U2493 ( .A0(n2958), .A1(n2465), .B0(n2464), .B1(n2492), .Y(n2488)
);
AOI222X1TS U2494 ( .A0(n6484), .A1(n6193), .B0(n6738), .B1(n5761), .C0(n297),
.C1(n6168), .Y(n5319) );
NAND3X1TS U2495 ( .A(n5214), .B(n583), .C(n5213), .Y(n194) );
OAI22X1TS U2496 ( .A0(n2910), .A1(n345), .B0(n2943), .B1(n2941), .Y(n2946)
);
OAI22X2TS U2497 ( .A0(n2934), .A1(n2567), .B0(n2566), .B1(n2931), .Y(n2652)
);
NOR2X2TS U2498 ( .A(n2869), .B(n2973), .Y(n152) );
BUFX8TS U2499 ( .A(n5151), .Y(n3204) );
OAI22X2TS U2500 ( .A0(n826), .A1(n2977), .B0(n5149), .B1(n1407), .Y(n3017)
);
OAI21X1TS U2501 ( .A0(n4278), .A1(n4440), .B0(n4039), .Y(n4040) );
XOR2X2TS U2502 ( .A(n3326), .B(n3298), .Y(n4278) );
NOR2X2TS U2503 ( .A(n7467), .B(n4595), .Y(n4597) );
OAI21X1TS U2504 ( .A0(n3994), .A1(n5108), .B0(n3993), .Y(n3995) );
OAI21X2TS U2505 ( .A0(n7179), .A1(n7834), .B0(n7180), .Y(n900) );
NOR2X2TS U2506 ( .A(n6150), .B(n7259), .Y(n6152) );
NAND2X2TS U2507 ( .A(n1198), .B(n1250), .Y(n1191) );
ADDFHX4TS U2508 ( .A(n2726), .B(n2725), .CI(n2724), .CO(n2731), .S(n2751) );
OAI22X2TS U2509 ( .A0(n2096), .A1(n2566), .B0(n2686), .B1(n2931), .Y(n2589)
);
OAI21X1TS U2510 ( .A0(n5754), .A1(n5755), .B0(n5753), .Y(n833) );
NOR2BX4TS U2511 ( .AN(n374), .B(n6063), .Y(n7339) );
XOR2X1TS U2512 ( .A(n5709), .B(n6217), .Y(n5760) );
OAI21X1TS U2513 ( .A0(n5937), .A1(n6828), .B0(n5708), .Y(n5709) );
OAI22X4TS U2514 ( .A0(n3204), .A1(n2442), .B0(n3202), .B1(n2649), .Y(n2625)
);
OAI22X2TS U2515 ( .A0(n2391), .A1(n2564), .B0(n2449), .B1(n7812), .Y(n2479)
);
OAI21X2TS U2516 ( .A0(n2449), .A1(n2562), .B0(n893), .Y(n2457) );
XNOR2X1TS U2517 ( .A(n268), .B(n2560), .Y(n2449) );
XNOR2X2TS U2518 ( .A(n267), .B(n2440), .Y(n1908) );
CLKINVX1TS U2519 ( .A(n7886), .Y(n7888) );
OAI21X1TS U2520 ( .A0(n5424), .A1(n5245), .B0(n5244), .Y(n5463) );
OAI21X1TS U2521 ( .A0(n5426), .A1(n5425), .B0(n5424), .Y(n496) );
AOI21X1TS U2522 ( .A0(n5241), .A1(n5305), .B0(n5240), .Y(n5424) );
ADDFHX2TS U2523 ( .A(n5636), .B(n5635), .CI(n5634), .CO(n5644), .S(n6067) );
NOR2X2TS U2524 ( .A(n1225), .B(n1238), .Y(n1264) );
NOR2X4TS U2525 ( .A(Data_B_i[48]), .B(Data_B_i[21]), .Y(n1238) );
INVX2TS U2526 ( .A(n1238), .Y(n1240) );
NOR2X4TS U2527 ( .A(n4587), .B(n4586), .Y(n7461) );
AOI222X1TS U2528 ( .A0(n4716), .A1(n4429), .B0(n4817), .B1(n238), .C0(n5106),
.C1(n4483), .Y(n4430) );
NAND2X2TS U2529 ( .A(n1504), .B(n1505), .Y(n1508) );
AOI21X2TS U2530 ( .A0(n7167), .A1(n578), .B0(n6572), .Y(n6573) );
ADDFHX2TS U2531 ( .A(n2356), .B(n2355), .CI(n2354), .CO(n2438), .S(n2415) );
CLKINVX6TS U2532 ( .A(n2692), .Y(n2944) );
ADDFHX2TS U2533 ( .A(n3434), .B(n3433), .CI(n3432), .CO(n3937), .S(n3435) );
NOR2X4TS U2534 ( .A(n1057), .B(n1061), .Y(n1023) );
OAI22X2TS U2535 ( .A0(n323), .A1(n2929), .B0(n2928), .B1(n2927), .Y(n2949)
);
XOR2X1TS U2536 ( .A(n1849), .B(n1848), .Y(n156) );
XNOR2X2TS U2537 ( .A(n2846), .B(n2894), .Y(n2686) );
AOI222X1TS U2538 ( .A0(n6268), .A1(n5948), .B0(n339), .B1(n5933), .C0(n6716),
.C1(n5936), .Y(n5628) );
OAI22X2TS U2539 ( .A0(n3000), .A1(n2480), .B0(n2587), .B1(n2504), .Y(n2500)
);
OAI22X1TS U2540 ( .A0(n2994), .A1(n734), .B0(n2996), .B1(n2995), .Y(n3015)
);
OAI22X2TS U2541 ( .A0(n734), .A1(n2995), .B0(n2996), .B1(n2872), .Y(n2992)
);
OAI22X2TS U2542 ( .A0(n711), .A1(n2650), .B0(n2587), .B1(n2572), .Y(n2678)
);
NOR2X1TS U2543 ( .A(n7174), .B(n7173), .Y(n7177) );
NAND2X4TS U2544 ( .A(Data_A_i[43]), .B(Data_A_i[16]), .Y(n1305) );
NAND2X2TS U2545 ( .A(Data_A_i[44]), .B(Data_A_i[17]), .Y(n1017) );
XOR2X4TS U2546 ( .A(n3112), .B(n3111), .Y(n809) );
ADDFHX4TS U2547 ( .A(n3098), .B(n3097), .CI(n3096), .CO(n3114), .S(n3112) );
OAI21XLTS U2548 ( .A0(n6929), .A1(n6539), .B0(n6321), .Y(n6322) );
INVX4TS U2549 ( .A(n1142), .Y(n1330) );
AOI21X4TS U2550 ( .A0(n820), .A1(n4583), .B0(n4582), .Y(n7466) );
AOI222X1TS U2551 ( .A0(n4348), .A1(n3644), .B0(n4009), .B1(n3772), .C0(n4021), .C1(n3985), .Y(n3618) );
ADDFHX2TS U2552 ( .A(n2072), .B(n2071), .CI(n2070), .CO(n2129), .S(n2115) );
OAI22X1TS U2553 ( .A0(n299), .A1(n2883), .B0(n2578), .B1(n2976), .Y(n2987)
);
ADDFHX2TS U2554 ( .A(n3945), .B(n3944), .CI(n3943), .CO(n3967), .S(n3964) );
ADDFHX2TS U2555 ( .A(n3954), .B(n3953), .CI(n3952), .CO(n3944), .S(n3955) );
NAND2X2TS U2556 ( .A(n3353), .B(n3350), .Y(n3393) );
NAND2X2TS U2557 ( .A(Data_B_i[7]), .B(n4483), .Y(n3350) );
NAND2X2TS U2558 ( .A(n2784), .B(n2783), .Y(n7868) );
ADDFHX2TS U2559 ( .A(n1921), .B(n1920), .CI(n1919), .CO(n2385), .S(n1969) );
ADDFHX2TS U2560 ( .A(n2121), .B(n2120), .CI(n2119), .CO(n2321), .S(n2131) );
OAI22X2TS U2561 ( .A0(n2092), .A1(n2798), .B0(n2140), .B1(n2246), .Y(n2103)
);
XNOR2X2TS U2562 ( .A(n260), .B(n2182), .Y(n2140) );
CLKINVX6TS U2563 ( .A(n259), .Y(n260) );
ADDFHX2TS U2564 ( .A(n5600), .B(n5599), .CI(n5598), .CO(n6157), .S(n6156) );
AOI21X2TS U2565 ( .A0(n6162), .A1(n7324), .B0(n6161), .Y(n6163) );
AOI222X1TS U2566 ( .A0(n6312), .A1(n255), .B0(n6782), .B1(n5986), .C0(n6815),
.C1(n5933), .Y(n5521) );
XNOR2X4TS U2567 ( .A(n245), .B(n2894), .Y(n2932) );
INVX6TS U2568 ( .A(n955), .Y(n245) );
OAI21X4TS U2569 ( .A0(n933), .A1(n6164), .B0(n6163), .Y(n6598) );
AOI21X4TS U2570 ( .A0(n7249), .A1(n6152), .B0(n6151), .Y(n933) );
NOR2BX2TS U2571 ( .AN(n5269), .B(n5268), .Y(n5689) );
OAI21X1TS U2572 ( .A0(n217), .A1(n6574), .B0(n6573), .Y(n6578) );
AOI21X2TS U2573 ( .A0(n7829), .A1(n850), .B0(n900), .Y(n899) );
OAI22X2TS U2574 ( .A0(n3000), .A1(n2504), .B0(n309), .B1(n2651), .Y(n2722)
);
OAI2BB1X4TS U2575 ( .A0N(n889), .A1N(n888), .B0(n2823), .Y(n887) );
ADDFHX2TS U2576 ( .A(n2904), .B(n2903), .CI(n2902), .CO(n2980), .S(n2891) );
OAI22X2TS U2577 ( .A0(n2849), .A1(n344), .B0(n2030), .B1(n2910), .Y(n2903)
);
OAI21X2TS U2578 ( .A0(n1207), .A1(n1284), .B0(n1206), .Y(n631) );
ADDFHX4TS U2579 ( .A(n2387), .B(n2386), .CI(n2385), .CO(n2423), .S(n2429) );
OAI22X1TS U2580 ( .A0(n2555), .A1(n2564), .B0(n2565), .B1(n7812), .Y(n2618)
);
XOR2X1TS U2581 ( .A(n2697), .B(n2696), .Y(n2699) );
XNOR2X4TS U2582 ( .A(n5179), .B(n2560), .Y(n2565) );
ADDFHX2TS U2583 ( .A(n2691), .B(n2690), .CI(n2689), .CO(n2833), .S(n2683) );
OAI21X1TS U2584 ( .A0(n7558), .A1(n7414), .B0(n7413), .Y(n7428) );
OAI22X2TS U2585 ( .A0(n323), .A1(n2595), .B0(n2608), .B1(n2927), .Y(n2606)
);
NAND2X2TS U2586 ( .A(n749), .B(n748), .Y(n763) );
ADDFHX2TS U2587 ( .A(n1900), .B(n1899), .CI(n1898), .CO(n2374), .S(n1916) );
NOR2X4TS U2588 ( .A(n7906), .B(n7902), .Y(n2338) );
NOR2X4TS U2589 ( .A(n2336), .B(n2335), .Y(n7906) );
AOI21X2TS U2590 ( .A0(n1105), .A1(n533), .B0(n1024), .Y(n529) );
OAI22X2TS U2591 ( .A0(n2454), .A1(n2609), .B0(n327), .B1(n2359), .Y(n2435)
);
ADDFHX2TS U2592 ( .A(n2471), .B(n2470), .CI(n2469), .CO(n2516), .S(n2512) );
XOR2X4TS U2593 ( .A(n2519), .B(n2520), .Y(n727) );
OAI22X2TS U2594 ( .A0(n3000), .A1(n3198), .B0(n2587), .B1(n2393), .Y(n2476)
);
INVX12TS U2595 ( .A(n304), .Y(n305) );
OAI21X1TS U2596 ( .A0(n1231), .A1(n670), .B0(n1232), .Y(n842) );
OAI21X1TS U2597 ( .A0(n1161), .A1(n670), .B0(n1160), .Y(n1163) );
INVX4TS U2598 ( .A(n671), .Y(n3200) );
XNOR2X2TS U2599 ( .A(n3200), .B(n2894), .Y(n2839) );
ADDFHX2TS U2600 ( .A(n1456), .B(n1455), .CI(n1454), .CO(n1502), .S(n1480) );
OAI22X2TS U2601 ( .A0(n7674), .A1(n1449), .B0(n295), .B1(n1465), .Y(n1455)
);
OAI21X4TS U2602 ( .A0(n704), .A1(n1353), .B0(n1352), .Y(n607) );
AOI21X2TS U2603 ( .A0(n1351), .A1(n1350), .B0(n1349), .Y(n1352) );
OAI22X2TS U2604 ( .A0(n1875), .A1(n327), .B0(n1889), .B1(n2609), .Y(n1888)
);
BUFX16TS U2605 ( .A(n1073), .Y(n704) );
ADDFHX2TS U2606 ( .A(n3008), .B(n3009), .CI(n3007), .CO(n3037), .S(n3035) );
OAI21XLTS U2607 ( .A0(n7875), .A1(n7874), .B0(n7868), .Y(n7876) );
XOR2X2TS U2608 ( .A(n2757), .B(n542), .Y(n541) );
ADDFHX2TS U2609 ( .A(n2794), .B(n2560), .CI(n2793), .CO(n2859), .S(n2807) );
NOR2X1TS U2610 ( .A(n7672), .B(n157), .Y(n2794) );
NOR2X1TS U2611 ( .A(n3968), .B(n3967), .Y(n3942) );
ADDFHX2TS U2612 ( .A(n3926), .B(n3925), .CI(n3924), .CO(n3969), .S(n3968) );
NOR2X4TS U2613 ( .A(n3143), .B(n3142), .Y(n7173) );
ADDFHX4TS U2614 ( .A(n3130), .B(n3129), .CI(n3128), .CO(n3142), .S(n3141) );
OAI22X2TS U2615 ( .A0(n3000), .A1(n2999), .B0(n309), .B1(n2997), .Y(n3014)
);
BUFX4TS U2616 ( .A(n2554), .Y(n3000) );
OAI21X2TS U2617 ( .A0(n3094), .A1(n3095), .B0(n3093), .Y(n953) );
OAI21X1TS U2618 ( .A0(n5434), .A1(n5433), .B0(n5432), .Y(n526) );
XOR2X1TS U2619 ( .A(n5434), .B(n527), .Y(n5489) );
XOR2X1TS U2620 ( .A(n5294), .B(n6546), .Y(n5432) );
ADDFHX2TS U2621 ( .A(n3732), .B(n3731), .CI(n3730), .CO(n3738), .S(n3737) );
XOR2X2TS U2622 ( .A(n3984), .B(n5066), .Y(n4109) );
ADDFHX2TS U2623 ( .A(n4561), .B(n4560), .CI(n4559), .CO(n4572), .S(n4566) );
NAND2X2TS U2624 ( .A(n4593), .B(n7447), .Y(n4595) );
OAI21X1TS U2625 ( .A0(n4370), .A1(n4519), .B0(n4369), .Y(n4371) );
OAI22X2TS U2626 ( .A0(n324), .A1(n2840), .B0(n2898), .B1(n2927), .Y(n2874)
);
OAI22X2TS U2627 ( .A0(n324), .A1(n2898), .B0(n2929), .B1(n2927), .Y(n3002)
);
OAI21X2TS U2628 ( .A0(n1257), .A1(n1285), .B0(n1258), .Y(n1000) );
OAI21X2TS U2629 ( .A0(n644), .A1(n1284), .B0(n643), .Y(n642) );
XNOR2X2TS U2630 ( .A(n1330), .B(n1331), .Y(n1338) );
ADDFHX2TS U2631 ( .A(n2436), .B(n2435), .CI(n2434), .CO(n2496), .S(n2439) );
XNOR2X2TS U2632 ( .A(n266), .B(n2351), .Y(n2362) );
NAND2BX1TS U2633 ( .AN(n2543), .B(n7761), .Y(n7762) );
NOR2X1TS U2634 ( .A(n3853), .B(n3852), .Y(n3860) );
XOR2X1TS U2635 ( .A(n4469), .B(n4468), .Y(n4494) );
XNOR2X4TS U2636 ( .A(n1967), .B(n1968), .Y(n923) );
ADDFHX2TS U2637 ( .A(n2635), .B(n2634), .CI(n2633), .CO(n2684), .S(n2627) );
OAI22X2TS U2638 ( .A0(n2597), .A1(n327), .B0(n2611), .B1(n2609), .Y(n2605)
);
NOR2X4TS U2639 ( .A(n7472), .B(n7476), .Y(n4583) );
NOR2X4TS U2640 ( .A(n4581), .B(n4580), .Y(n7476) );
AOI21X2TS U2641 ( .A0(n7265), .A1(n6143), .B0(n6142), .Y(n7258) );
INVX2TS U2642 ( .A(n7332), .Y(n6143) );
ADDFHX2TS U2643 ( .A(n6130), .B(n6129), .CI(n6128), .CO(n6120), .S(n6132) );
BUFX4TS U2644 ( .A(n6339), .Y(n6716) );
XOR2X1TS U2645 ( .A(n5627), .B(n6390), .Y(n6076) );
CLKINVX1TS U2646 ( .A(n7117), .Y(n7118) );
CLKINVX1TS U2647 ( .A(n704), .Y(n720) );
OAI21X2TS U2648 ( .A0(n704), .A1(n1042), .B0(n1041), .Y(n608) );
INVX6TS U2649 ( .A(n704), .Y(n304) );
CLKINVX1TS U2650 ( .A(n704), .Y(n749) );
CLKINVX1TS U2651 ( .A(n1280), .Y(n1283) );
CLKINVX1TS U2652 ( .A(n7830), .Y(n7174) );
NAND3BX2TS U2653 ( .AN(n5230), .B(n5231), .C(n460), .Y(n459) );
XNOR2X4TS U2654 ( .A(n1382), .B(n1381), .Y(n2027) );
OAI21X2TS U2655 ( .A0(n1392), .A1(n1377), .B0(n1376), .Y(n1382) );
ADDFHX2TS U2656 ( .A(n3446), .B(n3445), .CI(n3444), .CO(n3456), .S(n3487) );
XOR2X1TS U2657 ( .A(n3300), .B(n4044), .Y(n3445) );
CLKINVX1TS U2658 ( .A(n7829), .Y(n7175) );
NAND2X2TS U2659 ( .A(n3215), .B(n3389), .Y(n3287) );
NOR2X2TS U2660 ( .A(n3351), .B(n3352), .Y(n3389) );
OAI21X4TS U2661 ( .A0(n7488), .A1(n7494), .B0(n7489), .Y(n820) );
NAND2X2TS U2662 ( .A(n4579), .B(n4578), .Y(n7484) );
OAI21X1TS U2663 ( .A0(n4665), .A1(n4776), .B0(n4249), .Y(n4250) );
XOR2X1TS U2664 ( .A(n5469), .B(n5470), .Y(n905) );
OAI21X1TS U2665 ( .A0(n6868), .A1(n6679), .B0(n6366), .Y(n6367) );
NOR2X2TS U2666 ( .A(n7215), .B(n6595), .Y(n6599) );
OAI21X1TS U2667 ( .A0(n6868), .A1(n338), .B0(n6674), .Y(n6675) );
NAND2X4TS U2668 ( .A(n3151), .B(n3150), .Y(n7859) );
OAI21X2TS U2669 ( .A0(n7709), .A1(n7157), .B0(n7156), .Y(n7685) );
ADDFHX4TS U2670 ( .A(n3030), .B(n3029), .CI(n3028), .CO(n3047), .S(n3056) );
XNOR2X1TS U2671 ( .A(n258), .B(n2596), .Y(n2800) );
OAI22X1TS U2672 ( .A0(n2096), .A1(n2448), .B0(n2447), .B1(n2931), .Y(n2458)
);
XOR2X4TS U2673 ( .A(n2680), .B(n2682), .Y(n636) );
NOR2BX4TS U2674 ( .AN(n7007), .B(n463), .Y(n462) );
NOR2X2TS U2675 ( .A(n7072), .B(n7080), .Y(n7007) );
XOR2X1TS U2676 ( .A(n6795), .B(n6829), .Y(n6831) );
OAI21X1TS U2677 ( .A0(n315), .A1(n7668), .B0(n989), .Y(n7683) );
NAND2X4TS U2678 ( .A(n1087), .B(n1816), .Y(n2996) );
XNOR2X2TS U2679 ( .A(n863), .B(n2548), .Y(n862) );
XOR2X4TS U2680 ( .A(n2532), .B(n2531), .Y(n2540) );
XNOR2X4TS U2681 ( .A(n591), .B(n2716), .Y(n2743) );
AOI21X2TS U2682 ( .A0(n2290), .A1(n7794), .B0(n2289), .Y(n7791) );
NAND2X4TS U2683 ( .A(n1870), .B(n2609), .Y(n2861) );
XNOR2X4TS U2684 ( .A(n1868), .B(n1867), .Y(n2248) );
AOI21X2TS U2685 ( .A0(n5196), .A1(n5377), .B0(n5195), .Y(n5353) );
OAI21X1TS U2686 ( .A0(n6868), .A1(n6794), .B0(n6525), .Y(n6526) );
AOI21X4TS U2687 ( .A0(n7230), .A1(n6449), .B0(n6448), .Y(n7214) );
OAI21X1TS U2688 ( .A0(n6712), .A1(n6962), .B0(n6626), .Y(n568) );
OAI21X1TS U2689 ( .A0(n6712), .A1(n6707), .B0(n5482), .Y(n5483) );
OAI21X4TS U2690 ( .A0(n7886), .A1(n7883), .B0(n7887), .Y(n7867) );
NAND2X2TS U2691 ( .A(n2782), .B(n2781), .Y(n7887) );
OAI2BB1X2TS U2692 ( .A0N(n2775), .A1N(n2774), .B0(n2773), .Y(n2776) );
NOR2X4TS U2693 ( .A(n1231), .B(n1156), .Y(n1297) );
OAI2BB1X2TS U2694 ( .A0N(n2418), .A1N(n2419), .B0(n678), .Y(n2518) );
XNOR2X4TS U2695 ( .A(n1338), .B(n1869), .Y(n2352) );
ADDFHX2TS U2696 ( .A(n6332), .B(n6331), .CI(n6330), .CO(n6373), .S(n6329) );
OAI21X2TS U2697 ( .A0(n7642), .A1(n7638), .B0(n7639), .Y(n7532) );
OAI21X2TS U2698 ( .A0(n7009), .A1(n7073), .B0(n7008), .Y(n7191) );
BUFX8TS U2699 ( .A(Data_B_i[46]), .Y(n6901) );
NOR2X2TS U2700 ( .A(n6942), .B(Data_B_i[47]), .Y(n5263) );
INVX2TS U2701 ( .A(n6596), .Y(n6597) );
OAI21X2TS U2702 ( .A0(n4906), .A1(n4960), .B0(n4905), .Y(n4907) );
NAND2X2TS U2703 ( .A(n122), .B(n123), .Y(n4906) );
ADDFHX4TS U2704 ( .A(n2766), .B(n2765), .CI(n2764), .CO(n2759), .S(n2771) );
XOR2X2TS U2705 ( .A(n2674), .B(n855), .Y(n854) );
OAI22X2TS U2706 ( .A0(n143), .A1(n2665), .B0(n2663), .B1(n2664), .Y(n855) );
ADDFHX4TS U2707 ( .A(n2740), .B(n2739), .CI(n2738), .CO(n2745), .S(n2761) );
OAI21X1TS U2708 ( .A0(n3396), .A1(n3351), .B0(n3350), .Y(n3356) );
OAI21X1TS U2709 ( .A0(n4421), .A1(n4269), .B0(n4037), .Y(n4038) );
XOR2X2TS U2710 ( .A(n702), .B(n2513), .Y(n701) );
XOR2X2TS U2711 ( .A(n703), .B(n2437), .Y(n702) );
OAI21X1TS U2712 ( .A0(n7441), .A1(n7451), .B0(n7442), .Y(n4592) );
NAND2X2TS U2713 ( .A(n4589), .B(n4588), .Y(n7451) );
OAI21X1TS U2714 ( .A0(n7558), .A1(n7430), .B0(n7429), .Y(n7433) );
XOR2X4TS U2715 ( .A(n3224), .B(n3223), .Y(n4744) );
XNOR2X1TS U2716 ( .A(n4472), .B(n153), .Y(n4493) );
XNOR2X1TS U2717 ( .A(n5031), .B(n154), .Y(GEN1_right_N46) );
ADDFHX2TS U2718 ( .A(n4552), .B(n4551), .CI(n4550), .CO(n4604), .S(n4555) );
XOR2X1TS U2719 ( .A(n4416), .B(n4705), .Y(n4496) );
OAI21X1TS U2720 ( .A0(n4797), .A1(n4776), .B0(n4415), .Y(n4416) );
OAI21X2TS U2721 ( .A0(n7878), .A1(n7868), .B0(n7879), .Y(n2787) );
XOR2X2TS U2722 ( .A(n2620), .B(n2619), .Y(n2734) );
ADDFHX4TS U2723 ( .A(n3077), .B(n3076), .CI(n3075), .CO(n3094), .S(n3087) );
ADDFHX4TS U2724 ( .A(n2923), .B(n2922), .CI(n2921), .CO(n3134), .S(n3133) );
XOR2X4TS U2725 ( .A(n336), .B(n366), .Y(n639) );
OAI2BB1X2TS U2726 ( .A0N(n2682), .A1N(n2681), .B0(n635), .Y(n2825) );
NOR2X1TS U2727 ( .A(n5367), .B(n5225), .Y(n5228) );
OAI21X4TS U2728 ( .A0(n7915), .A1(n7911), .B0(n7916), .Y(n7900) );
NOR2X4TS U2729 ( .A(n2332), .B(n2331), .Y(n7915) );
AOI21X2TS U2730 ( .A0(n6999), .A1(n6839), .B0(n6998), .Y(n7073) );
NOR2X1TS U2731 ( .A(n6685), .B(n6659), .Y(n5448) );
NOR2X1TS U2732 ( .A(n6685), .B(Data_B_i[38]), .Y(n5355) );
NAND2X2TS U2733 ( .A(n7184), .B(n7047), .Y(n7048) );
OAI21XLTS U2734 ( .A0(n6868), .A1(n6186), .B0(n5572), .Y(n5573) );
OAI21X1TS U2735 ( .A0(n6868), .A1(n6539), .B0(n6181), .Y(n6182) );
ADDFHX2TS U2736 ( .A(n6248), .B(n6247), .CI(n6246), .CO(n6264), .S(n6260) );
NOR2X2TS U2737 ( .A(n6157), .B(n6158), .Y(n7327) );
AOI222X1TS U2738 ( .A0(n6312), .A1(n5986), .B0(n6782), .B1(n288), .C0(n6815),
.C1(n5936), .Y(n5527) );
XOR2X1TS U2739 ( .A(n5528), .B(n6546), .Y(n5574) );
OAI21X1TS U2740 ( .A0(n990), .A1(n6962), .B0(n5527), .Y(n5528) );
OAI21X1TS U2741 ( .A0(n216), .A1(n5044), .B0(n5043), .Y(n5048) );
NOR2X2TS U2742 ( .A(n7450), .B(n7441), .Y(n4593) );
OAI21X1TS U2743 ( .A0(n4102), .A1(n3855), .B0(n3863), .Y(n3408) );
OAI21X1TS U2744 ( .A0(n4773), .A1(n331), .B0(n4357), .Y(n4358) );
XOR2X1TS U2745 ( .A(n6464), .B(n6820), .Y(n6532) );
XOR2X1TS U2746 ( .A(n6467), .B(n6624), .Y(n6531) );
ADDFHX2TS U2747 ( .A(n2984), .B(n2983), .CI(n2982), .CO(n3074), .S(n3026) );
XOR2X1TS U2748 ( .A(n2949), .B(n2948), .Y(n2935) );
OAI22X2TS U2749 ( .A0(n2934), .A1(n2933), .B0(n2932), .B1(n2931), .Y(n2948)
);
NAND2X4TS U2750 ( .A(n813), .B(n814), .Y(n7850) );
XNOR2X2TS U2751 ( .A(n3200), .B(n2905), .Y(n2939) );
OAI21X1TS U2752 ( .A0(n7306), .A1(n7051), .B0(n7050), .Y(n7055) );
OAI21X1TS U2753 ( .A0(n498), .A1(n6186), .B0(n6185), .Y(n6187) );
OAI21X1TS U2754 ( .A0(n6972), .A1(n337), .B0(n6851), .Y(n6852) );
NOR2X2TS U2755 ( .A(n7003), .B(n7002), .Y(n7072) );
NOR2BX2TS U2756 ( .AN(n453), .B(n5245), .Y(n5457) );
NAND2X4TS U2757 ( .A(n7847), .B(n3137), .Y(n7746) );
NOR2X8TS U2758 ( .A(n7838), .B(n7842), .Y(n3137) );
NOR2X4TS U2759 ( .A(n1109), .B(n1096), .Y(n533) );
NOR2X4TS U2760 ( .A(Data_B_i[41]), .B(Data_B_i[14]), .Y(n1109) );
ADDFHX2TS U2761 ( .A(n3010), .B(n3011), .CI(n3012), .CO(n3076), .S(n3025) );
ADDFHX2TS U2762 ( .A(n2993), .B(n2992), .CI(n2991), .CO(n3010), .S(n3034) );
OAI2BB1X2TS U2763 ( .A0N(n3089), .A1N(n3088), .B0(n918), .Y(n3105) );
OAI21X1TS U2764 ( .A0(n3088), .A1(n3089), .B0(n3087), .Y(n918) );
NAND2X2TS U2765 ( .A(n3048), .B(n220), .Y(n221) );
NOR2X2TS U2766 ( .A(n1201), .B(n1208), .Y(n1002) );
NOR2X4TS U2767 ( .A(Data_A_i[41]), .B(Data_A_i[14]), .Y(n1201) );
XNOR2X4TS U2768 ( .A(n1086), .B(n766), .Y(n764) );
NAND3X4TS U2769 ( .A(n763), .B(n759), .C(n757), .Y(n766) );
NOR2X4TS U2770 ( .A(n7862), .B(n7750), .Y(n7847) );
INVX2TS U2771 ( .A(n6688), .Y(n5853) );
XNOR2X2TS U2772 ( .A(n3198), .B(n723), .Y(n722) );
CLKBUFX2TS U2773 ( .A(n6664), .Y(n424) );
XOR2X1TS U2774 ( .A(n5281), .B(n6877), .Y(n5433) );
OAI21XLTS U2775 ( .A0(n5318), .A1(n991), .B0(n5215), .Y(n5216) );
AOI222XLTS U2776 ( .A0(n6484), .A1(n254), .B0(n6738), .B1(Data_B_i[29]),
.C0(n297), .C1(n5984), .Y(n5215) );
NAND2X1TS U2777 ( .A(n942), .B(n941), .Y(n5814) );
INVX2TS U2778 ( .A(n5337), .Y(n941) );
CLKAND2X2TS U2779 ( .A(n7419), .B(n4934), .Y(n4973) );
CLKAND2X2TS U2780 ( .A(n7199), .B(n292), .Y(n6943) );
INVX2TS U2781 ( .A(n194), .Y(n297) );
OAI21XLTS U2782 ( .A0(n3988), .A1(n4625), .B0(n3557), .Y(n3558) );
AOI222XLTS U2783 ( .A0(n4426), .A1(n3644), .B0(n3552), .B1(n3772), .C0(n3898), .C1(n3985), .Y(n3557) );
NAND2BX1TS U2784 ( .AN(n3226), .B(n915), .Y(n3512) );
OAI21XLTS U2785 ( .A0(n991), .A1(n6623), .B0(n5848), .Y(n5849) );
CLKBUFX2TS U2786 ( .A(n290), .Y(n6001) );
INVX2TS U2787 ( .A(Data_A_i[27]), .Y(n5254) );
CLKBUFX2TS U2788 ( .A(Data_B_i[3]), .Y(n3843) );
INVX8TS U2789 ( .A(Data_A_i[26]), .Y(n7422) );
NOR2BX2TS U2790 ( .AN(n372), .B(n6059), .Y(n7347) );
AOI21X1TS U2791 ( .A0(n6027), .A1(n7280), .B0(n6026), .Y(n7277) );
AOI21X1TS U2792 ( .A0(n7576), .A1(n4219), .B0(n4218), .Y(n4220) );
AOI21X2TS U2793 ( .A0(n7785), .A1(n2300), .B0(n690), .Y(n920) );
NOR2X4TS U2794 ( .A(Data_B_i[44]), .B(Data_B_i[17]), .Y(n1027) );
NOR2BX1TS U2795 ( .AN(n589), .B(n1265), .Y(n1272) );
CLKAND2X2TS U2796 ( .A(n4849), .B(n4275), .Y(n4417) );
XNOR2X1TS U2797 ( .A(Data_A_i[39]), .B(Data_A_i[40]), .Y(n5204) );
NOR2BX1TS U2798 ( .AN(n5235), .B(n5234), .Y(n5696) );
NAND2BX2TS U2799 ( .AN(n3260), .B(n3261), .Y(n3754) );
XOR2X1TS U2800 ( .A(n5710), .B(n6217), .Y(n5774) );
CLKBUFX2TS U2801 ( .A(Data_B_i[40]), .Y(n6617) );
CLKBUFX2TS U2802 ( .A(Data_B_i[39]), .Y(n6519) );
CLKBUFX2TS U2803 ( .A(Data_B_i[19]), .Y(n4795) );
CLKBUFX2TS U2804 ( .A(Data_B_i[40]), .Y(n6267) );
CLKBUFX2TS U2805 ( .A(n6414), .Y(n6198) );
NAND2X1TS U2806 ( .A(n502), .B(n503), .Y(n501) );
CLKBUFX2TS U2807 ( .A(Data_B_i[24]), .Y(n4829) );
CLKBUFX2TS U2808 ( .A(Data_B_i[23]), .Y(n4939) );
AOI21X1TS U2809 ( .A0(n6323), .A1(n290), .B0(n425), .Y(n5662) );
NAND2X1TS U2810 ( .A(n427), .B(n426), .Y(n425) );
NAND2X1TS U2811 ( .A(n424), .B(n6381), .Y(n426) );
CLKBUFX2TS U2812 ( .A(Data_B_i[46]), .Y(n6811) );
OAI21X1TS U2813 ( .A0(n7036), .A1(n6401), .B0(n6400), .Y(n6403) );
INVX2TS U2814 ( .A(n6688), .Y(n6412) );
CLKBUFX2TS U2815 ( .A(Data_B_i[50]), .Y(n6927) );
CLKAND2X2TS U2816 ( .A(n6902), .B(n293), .Y(n6686) );
AND3X2TS U2817 ( .A(n5206), .B(n5205), .C(n5204), .Y(n6705) );
CLKBUFX2TS U2818 ( .A(Data_B_i[41]), .Y(n6660) );
CLKBUFX2TS U2819 ( .A(n5696), .Y(n6536) );
INVX8TS U2820 ( .A(Data_A_i[38]), .Y(n6688) );
INVX4TS U2821 ( .A(Data_A_i[41]), .Y(n838) );
CLKBUFX2TS U2822 ( .A(n5694), .Y(n6539) );
BUFX3TS U2823 ( .A(n6705), .Y(n6425) );
CLKBUFX2TS U2824 ( .A(n5699), .Y(n6676) );
CLKBUFX2TS U2825 ( .A(n3754), .Y(n4269) );
CLKBUFX2TS U2826 ( .A(Data_B_i[21]), .Y(n4824) );
ADDHXLTS U2827 ( .A(n5001), .B(n3846), .CO(n3821), .S(n3904) );
CLKBUFX2TS U2828 ( .A(Data_B_i[13]), .Y(n4619) );
AO21XLTS U2829 ( .A0(n2349), .A1(n2906), .B0(n2168), .Y(n1491) );
OAI22X1TS U2830 ( .A0(n733), .A1(n2573), .B0(n130), .B1(n2586), .Y(n2703) );
CLKBUFX2TS U2831 ( .A(n3754), .Y(n4832) );
NAND2BX2TS U2832 ( .AN(n509), .B(n6779), .Y(n6781) );
CLKAND2X2TS U2833 ( .A(n6902), .B(n6825), .Y(n6860) );
CLKAND2X2TS U2834 ( .A(n7199), .B(n6849), .Y(n6871) );
CLKAND2X2TS U2835 ( .A(n7419), .B(n4794), .Y(n4786) );
CLKBUFX2TS U2836 ( .A(Data_B_i[23]), .Y(n4753) );
CLKBUFX2TS U2837 ( .A(Data_B_i[42]), .Y(n6690) );
CLKBUFX2TS U2838 ( .A(Data_B_i[39]), .Y(n6222) );
XOR2X1TS U2839 ( .A(n5778), .B(Data_A_i[41]), .Y(n5821) );
CLKBUFX2TS U2840 ( .A(Data_B_i[34]), .Y(n6282) );
CLKINVX6TS U2841 ( .A(n5231), .Y(n5447) );
CLKBUFX2TS U2842 ( .A(Data_B_i[42]), .Y(n6388) );
XOR2X1TS U2843 ( .A(n5575), .B(n5574), .Y(n5610) );
CLKBUFX2TS U2844 ( .A(Data_B_i[15]), .Y(n4693) );
CLKBUFX2TS U2845 ( .A(Data_B_i[14]), .Y(n4372) );
CLKBUFX2TS U2846 ( .A(Data_B_i[16]), .Y(n4410) );
INVX2TS U2847 ( .A(n4691), .Y(n3761) );
AOI21X1TS U2848 ( .A0(n3296), .A1(n3295), .B0(n3294), .Y(n3326) );
OAI2BB1X1TS U2849 ( .A0N(n2439), .A1N(n2438), .B0(n845), .Y(n2509) );
OAI21X1TS U2850 ( .A0(n325), .A1(n2160), .B0(n872), .Y(n871) );
CLKBUFX2TS U2851 ( .A(n1981), .Y(n2222) );
CLKAND2X2TS U2852 ( .A(n6902), .B(n6901), .Y(n6922) );
CLKAND2X2TS U2853 ( .A(n5095), .B(n5087), .Y(n5097) );
AOI21X2TS U2854 ( .A0(n1351), .A1(n1120), .B0(n1119), .Y(n782) );
XOR2X1TS U2855 ( .A(n413), .B(n5858), .Y(n5881) );
XNOR2X2TS U2856 ( .A(n5473), .B(n5344), .Y(n6235) );
CLKAND2X2TS U2857 ( .A(n7419), .B(n4997), .Y(n5070) );
INVX2TS U2858 ( .A(n7422), .Y(n5066) );
AOI21X2TS U2859 ( .A0(n5046), .A1(n5041), .B0(n4913), .Y(n5021) );
XOR2XLTS U2860 ( .A(n3548), .B(n3832), .Y(n3599) );
OAI21XLTS U2861 ( .A0(n4304), .A1(n3581), .B0(n3547), .Y(n3548) );
OAI21XLTS U2862 ( .A0(n117), .A1(n3581), .B0(n3567), .Y(n3568) );
XOR2XLTS U2863 ( .A(n3584), .B(n3796), .Y(n3691) );
OAI21XLTS U2864 ( .A0(n4431), .A1(n3671), .B0(n3583), .Y(n3584) );
CLKBUFX2TS U2865 ( .A(Data_B_i[6]), .Y(n4276) );
XOR2XLTS U2866 ( .A(n3604), .B(n3832), .Y(n3621) );
CLKBUFX2TS U2867 ( .A(Data_B_i[4]), .Y(n4129) );
CLKBUFX2TS U2868 ( .A(Data_B_i[5]), .Y(n3816) );
INVX2TS U2869 ( .A(Data_A_i[0]), .Y(n3367) );
OAI21X2TS U2870 ( .A0(n2494), .A1(n2495), .B0(n2493), .Y(n724) );
INVX2TS U2871 ( .A(n595), .Y(n593) );
XOR2XLTS U2872 ( .A(n5086), .B(n5085), .Y(n5103) );
ADDFHX2TS U2873 ( .A(n5790), .B(n5789), .CI(n5788), .CO(n6060), .S(n6059) );
OAI21XLTS U2874 ( .A0(n161), .A1(n5980), .B0(n5958), .Y(n5959) );
NOR2X2TS U2875 ( .A(n6770), .B(n6771), .Y(n494) );
XOR2X1TS U2876 ( .A(n837), .B(n4195), .Y(n4206) );
XOR2X1TS U2877 ( .A(n4196), .B(n4197), .Y(n837) );
AOI21X1TS U2878 ( .A0(n7507), .A1(n7502), .B0(n3971), .Y(n3972) );
ADDFHX2TS U2879 ( .A(n3960), .B(n3959), .CI(n3958), .CO(n3961), .S(n3749) );
OAI21XLTS U2880 ( .A0(n963), .A1(n4296), .B0(n3611), .Y(n3612) );
AOI21X1TS U2881 ( .A0(n7928), .A1(n7925), .B0(n687), .Y(n686) );
AOI21X1TS U2882 ( .A0(n123), .A1(n5050), .B0(n4904), .Y(n4905) );
NOR2XLTS U2883 ( .A(n7386), .B(n7287), .Y(n5972) );
OAI21X2TS U2884 ( .A0(n7616), .A1(n7613), .B0(n7617), .Y(n7621) );
INVX2TS U2885 ( .A(n7613), .Y(n7614) );
INVX2TS U2886 ( .A(n2078), .Y(n246) );
NOR2X2TS U2887 ( .A(Data_B_i[47]), .B(Data_B_i[20]), .Y(n1225) );
NOR2X4TS U2888 ( .A(n1843), .B(n1845), .Y(n537) );
NOR2X1TS U2889 ( .A(n5323), .B(n5380), .Y(n5196) );
OAI21X1TS U2890 ( .A0(n4621), .A1(n4832), .B0(n4293), .Y(n4294) );
NAND2X1TS U2891 ( .A(n6071), .B(n6483), .Y(n381) );
OAI21XLTS U2892 ( .A0(n179), .A1(n6521), .B0(n6337), .Y(n6338) );
AOI222XLTS U2893 ( .A0(n6312), .A1(n6381), .B0(n6625), .B1(n6336), .C0(n6735), .C1(n290), .Y(n6219) );
CLKAND2X2TS U2894 ( .A(n6902), .B(n255), .Y(n6287) );
CLKAND2X2TS U2895 ( .A(n6902), .B(n256), .Y(n6379) );
OAI21XLTS U2896 ( .A0(n4370), .A1(n4269), .B0(n4015), .Y(n4016) );
AOI222XLTS U2897 ( .A0(n4935), .A1(n4129), .B0(n4823), .B1(n4128), .C0(n342),
.C1(n3982), .Y(n4130) );
XNOR2X1TS U2898 ( .A(n1296), .B(n2440), .Y(n2555) );
XNOR2X1TS U2899 ( .A(n233), .B(n2560), .Y(n2344) );
XNOR2X1TS U2900 ( .A(n2846), .B(n2440), .Y(n2391) );
XNOR2X1TS U2901 ( .A(n2848), .B(n2894), .Y(n2392) );
OAI21X2TS U2902 ( .A0(n586), .A1(n1101), .B0(n1102), .Y(n677) );
NOR2X2TS U2903 ( .A(n1384), .B(n1385), .Y(n1388) );
CLKINVX3TS U2904 ( .A(n246), .Y(n247) );
INVX6TS U2905 ( .A(n1137), .Y(n1284) );
INVX1TS U2906 ( .A(n1839), .Y(n1844) );
CLKAND2X2TS U2907 ( .A(n4808), .B(n7418), .Y(n4809) );
CLKAND2X2TS U2908 ( .A(n4849), .B(n4692), .Y(n4805) );
CLKAND2X2TS U2909 ( .A(n4680), .B(n7418), .Y(n4681) );
AOI222XLTS U2910 ( .A0(n320), .A1(n4678), .B0(n4677), .B1(n4822), .C0(n4676),
.C1(n241), .Y(n4679) );
CLKAND2X2TS U2911 ( .A(n4849), .B(n4516), .Y(n4689) );
AOI21X1TS U2912 ( .A0(n1273), .A1(n1272), .B0(n1271), .Y(n672) );
NAND2X1TS U2913 ( .A(n1272), .B(n1266), .Y(n588) );
CLKINVX3TS U2914 ( .A(n249), .Y(n250) );
CLKAND2X2TS U2915 ( .A(n366), .B(n2548), .Y(n1711) );
BUFX4TS U2916 ( .A(n732), .Y(n733) );
NAND2X1TS U2917 ( .A(n6180), .B(n5933), .Y(n384) );
NAND2BX2TS U2918 ( .AN(n450), .B(n5341), .Y(n449) );
OAI21XLTS U2919 ( .A0(n4520), .A1(n4519), .B0(n4518), .Y(n4521) );
OAI21XLTS U2920 ( .A0(n4487), .A1(n4519), .B0(n4486), .Y(n4488) );
CLKAND2X2TS U2921 ( .A(n5085), .B(n4483), .Y(n4545) );
CLKAND2X2TS U2922 ( .A(n5085), .B(n286), .Y(n4453) );
CLKAND2X2TS U2923 ( .A(n4463), .B(n7418), .Y(n4464) );
OAI21XLTS U2924 ( .A0(n4421), .A1(n4519), .B0(n4420), .Y(n4422) );
CLKAND2X2TS U2925 ( .A(n5085), .B(n4026), .Y(n4229) );
CLKAND2X2TS U2926 ( .A(n5085), .B(n3978), .Y(n4110) );
OAI21XLTS U2927 ( .A0(n963), .A1(n5108), .B0(n3983), .Y(n3984) );
CLKAND2X2TS U2928 ( .A(n424), .B(n6428), .Y(n211) );
OAI21XLTS U2929 ( .A0(n119), .A1(n6224), .B0(n5616), .Y(n5617) );
NAND2X1TS U2930 ( .A(n402), .B(n401), .Y(n400) );
OAI21XLTS U2931 ( .A0(n179), .A1(n5684), .B0(n5576), .Y(n5577) );
CLKBUFX2TS U2932 ( .A(n5985), .Y(n6399) );
CLKAND2X2TS U2933 ( .A(n6989), .B(n5973), .Y(n212) );
OAI2BB1X1TS U2934 ( .A0N(n904), .A1N(n903), .B0(n5468), .Y(n902) );
CLKAND2X2TS U2935 ( .A(n6989), .B(n5912), .Y(n5470) );
NAND2X1TS U2936 ( .A(n6312), .B(n6233), .Y(n465) );
CLKAND2X2TS U2937 ( .A(n6989), .B(n288), .Y(n6173) );
CLKBUFX2TS U2938 ( .A(Data_B_i[45]), .Y(n6778) );
CLKBUFX2TS U2939 ( .A(Data_B_i[46]), .Y(n6627) );
CLKAND2X2TS U2940 ( .A(n6989), .B(n242), .Y(n178) );
CLKAND2X2TS U2941 ( .A(n6989), .B(n290), .Y(n6470) );
AOI21X1TS U2942 ( .A0(n5463), .A1(n5456), .B0(n5460), .Y(n5417) );
OAI21XLTS U2943 ( .A0(n116), .A1(n4269), .B0(n3824), .Y(n3825) );
ADDHXLTS U2944 ( .A(n3822), .B(n3821), .CO(n3815), .S(n3888) );
XOR2XLTS U2945 ( .A(n3777), .B(n4548), .Y(n3822) );
CLKBUFX2TS U2946 ( .A(Data_B_i[20]), .Y(n4651) );
CLKBUFX2TS U2947 ( .A(Data_B_i[22]), .Y(n4722) );
CLKBUFX2TS U2948 ( .A(Data_B_i[21]), .Y(n4678) );
OAI21XLTS U2949 ( .A0(n4487), .A1(n3901), .B0(n3402), .Y(n3403) );
OAI21XLTS U2950 ( .A0(n4665), .A1(n4408), .B0(n3387), .Y(n3388) );
CLKBUFX2TS U2951 ( .A(Data_B_i[19]), .Y(n4630) );
CLKBUFX2TS U2952 ( .A(Data_B_i[18]), .Y(n4818) );
OAI21XLTS U2953 ( .A0(n4695), .A1(n4296), .B0(n3311), .Y(n3312) );
CLKBUFX2TS U2954 ( .A(Data_B_i[14]), .Y(n4663) );
CLKBUFX2TS U2955 ( .A(Data_B_i[12]), .Y(n4517) );
CLKBUFX2TS U2956 ( .A(Data_B_i[13]), .Y(n4292) );
CLKBUFX2TS U2957 ( .A(n3834), .Y(n4680) );
INVX2TS U2958 ( .A(n4807), .Y(n4044) );
AOI21X1TS U2959 ( .A0(n3211), .A1(n3294), .B0(n3210), .Y(n3212) );
INVX2TS U2960 ( .A(n916), .Y(n915) );
OAI21X1TS U2961 ( .A0(n7674), .A1(n1495), .B0(n613), .Y(n612) );
OR2X1TS U2962 ( .A(n295), .B(n1552), .Y(n613) );
OAI22X1TS U2963 ( .A0(n127), .A1(n1402), .B0(n1415), .B1(n2962), .Y(n1420)
);
ADDFHX2TS U2964 ( .A(n2961), .B(n2960), .CI(n2959), .CO(n2989), .S(n3009) );
OAI21X1TS U2965 ( .A0(n2438), .A1(n2439), .B0(n2437), .Y(n845) );
XNOR2X1TS U2966 ( .A(n2909), .B(n2559), .Y(n1875) );
XNOR2X1TS U2967 ( .A(n2848), .B(n2440), .Y(n908) );
OAI21X1TS U2968 ( .A0(n1019), .A1(n754), .B0(n753), .Y(n752) );
OAI22X1TS U2969 ( .A0(n2028), .A1(n2564), .B0(n1982), .B1(n986), .Y(n2012)
);
XNOR2X1TS U2970 ( .A(n2813), .B(n2229), .Y(n2141) );
CLKAND2X2TS U2971 ( .A(n6791), .B(n7198), .Y(n6792) );
CLKAND2X2TS U2972 ( .A(n6902), .B(n6745), .Y(n6789) );
OAI2BB1X1TS U2973 ( .A0N(n567), .A1N(n569), .B0(n6658), .Y(n565) );
CLKBUFX2TS U2974 ( .A(Data_B_i[20]), .Y(n4822) );
CLKAND2X2TS U2975 ( .A(n4849), .B(n4815), .Y(n4804) );
CLKBUFX2TS U2976 ( .A(n4132), .Y(n4808) );
CLKBUFX2TS U2977 ( .A(n4750), .Y(n4703) );
CLKAND2X2TS U2978 ( .A(n5085), .B(n287), .Y(n4656) );
OAI22X1TS U2979 ( .A0(n143), .A1(n1692), .B0(n2796), .B1(n598), .Y(n774) );
XOR2X1TS U2980 ( .A(n774), .B(n1672), .Y(n773) );
NOR2XLTS U2981 ( .A(n1711), .B(n1710), .Y(n605) );
NAND2X1TS U2982 ( .A(n733), .B(n2547), .Y(n741) );
NAND2X1TS U2983 ( .A(n408), .B(n407), .Y(n406) );
AOI22X1TS U2984 ( .A0(n6791), .A1(n5910), .B0(n6746), .B1(n5984), .Y(n5708)
);
OAI2BB1X1TS U2985 ( .A0N(n6193), .A1N(n6664), .B0(n438), .Y(n437) );
NAND2X1TS U2986 ( .A(n6425), .B(n6168), .Y(n438) );
OAI21XLTS U2987 ( .A0(n6619), .A1(n6186), .B0(n5765), .Y(n5766) );
NAND2X1TS U2988 ( .A(n396), .B(n395), .Y(n394) );
OAI21XLTS U2989 ( .A0(n6692), .A1(n5941), .B0(n5801), .Y(n5802) );
CLKBUFX2TS U2990 ( .A(Data_B_i[37]), .Y(n6070) );
OAI21XLTS U2991 ( .A0(n179), .A1(n6004), .B0(n5859), .Y(n5860) );
INVX2TS U2992 ( .A(Data_A_i[28]), .Y(n5253) );
CLKAND2X2TS U2993 ( .A(n4538), .B(n5062), .Y(n4539) );
INVX2TS U2994 ( .A(n4807), .Y(n4611) );
CLKBUFX2TS U2995 ( .A(Data_B_i[43]), .Y(n6404) );
CLKBUFX2TS U2996 ( .A(Data_B_i[45]), .Y(n6527) );
CLKBUFX2TS U2997 ( .A(Data_B_i[44]), .Y(n6462) );
XOR2XLTS U2998 ( .A(n5678), .B(n6402), .Y(n5731) );
CLKBUFX2TS U2999 ( .A(Data_B_i[43]), .Y(n6710) );
OAI21XLTS U3000 ( .A0(n6692), .A1(n6273), .B0(n5692), .Y(n5693) );
CLKAND2X2TS U3001 ( .A(n424), .B(n6233), .Y(n198) );
NAND2X1TS U3002 ( .A(n457), .B(n5232), .Y(n456) );
NAND2X1TS U3003 ( .A(n399), .B(n398), .Y(n397) );
XOR2X1TS U3004 ( .A(n5661), .B(n5989), .Y(n6096) );
CLKBUFX2TS U3005 ( .A(Data_B_i[48]), .Y(n6673) );
CLKBUFX2TS U3006 ( .A(Data_B_i[50]), .Y(n6748) );
CLKBUFX2TS U3007 ( .A(n5999), .Y(n6271) );
CLKBUFX2TS U3008 ( .A(Data_B_i[47]), .Y(n6650) );
CLKBUFX2TS U3009 ( .A(Data_B_i[49]), .Y(n6717) );
XOR2X1TS U3010 ( .A(n5372), .B(n355), .Y(n5396) );
CLKBUFX2TS U3011 ( .A(n5674), .Y(n6791) );
BUFX3TS U3012 ( .A(n6197), .Y(n6826) );
CLKBUFX2TS U3013 ( .A(n6414), .Y(n6746) );
NAND2BX1TS U3014 ( .AN(n507), .B(n6691), .Y(n6693) );
CLKAND2X2TS U3015 ( .A(n6989), .B(n6482), .Y(n6655) );
CLKAND2X2TS U3016 ( .A(n6536), .B(n6969), .Y(n6537) );
INVX2TS U3017 ( .A(n6688), .Y(n6624) );
CLKAND2X2TS U3018 ( .A(n6946), .B(n7198), .Y(n6947) );
INVX2TS U3019 ( .A(n4691), .Y(n4434) );
OAI21XLTS U3020 ( .A0(n963), .A1(n4852), .B0(n3844), .Y(n3845) );
CLKBUFX2TS U3021 ( .A(Data_B_i[18]), .Y(n4526) );
CLKBUFX2TS U3022 ( .A(Data_B_i[17]), .Y(n4423) );
CLKBUFX2TS U3023 ( .A(Data_B_i[16]), .Y(n4715) );
CLKBUFX2TS U3024 ( .A(Data_B_i[15]), .Y(n4442) );
OAI21XLTS U3025 ( .A0(n4487), .A1(n3581), .B0(n3448), .Y(n3449) );
OAI21XLTS U3026 ( .A0(n4431), .A1(n3581), .B0(n3472), .Y(n3473) );
OAI21XLTS U3027 ( .A0(n4421), .A1(n3581), .B0(n3504), .Y(n3505) );
OAI21XLTS U3028 ( .A0(n3581), .A1(n4370), .B0(n3520), .Y(n3521) );
BUFX3TS U3029 ( .A(n4321), .Y(n3898) );
OAI21XLTS U3030 ( .A0(n4421), .A1(n3686), .B0(n3543), .Y(n3544) );
INVX2TS U3031 ( .A(n805), .Y(n803) );
OAI22X1TS U3032 ( .A0(n2996), .A1(n2586), .B0(n130), .B1(n2814), .Y(n2803)
);
XOR2X1TS U3033 ( .A(n2676), .B(n819), .Y(n818) );
INVX2TS U3034 ( .A(n2749), .Y(n897) );
OAI22X1TS U3035 ( .A0(n346), .A1(n1954), .B0(n2030), .B1(n1923), .Y(n1951)
);
XNOR2X2TS U3036 ( .A(n1186), .B(n2212), .Y(n1187) );
INVX2TS U3037 ( .A(n164), .Y(n275) );
INVX2TS U3038 ( .A(n7202), .Y(n6940) );
XOR2X1TS U3039 ( .A(n6852), .B(n6877), .Y(n6862) );
CLKBUFX2TS U3040 ( .A(Data_B_i[24]), .Y(n4967) );
INVX2TS U3041 ( .A(n7422), .Y(n4970) );
CLKAND2X2TS U3042 ( .A(n4849), .B(n241), .Y(n4933) );
OAI21XLTS U3043 ( .A0(n179), .A1(n5875), .B0(n5822), .Y(n5823) );
CLKBUFX2TS U3044 ( .A(Data_B_i[37]), .Y(n6428) );
OAI21XLTS U3045 ( .A0(n119), .A1(n6004), .B0(n5901), .Y(n5902) );
CLKBUFX2TS U3046 ( .A(Data_B_i[25]), .Y(n4992) );
ADDFHX2TS U3047 ( .A(n3508), .B(n3507), .CI(n3506), .CO(n3490), .S(n3509) );
XOR2XLTS U3048 ( .A(n3592), .B(n3796), .Y(n3726) );
XOR2XLTS U3049 ( .A(n3594), .B(n4242), .Y(n3725) );
OAI21XLTS U3050 ( .A0(n4665), .A1(n3638), .B0(n3591), .Y(n3592) );
OAI21XLTS U3051 ( .A0(n116), .A1(n3686), .B0(n3606), .Y(n3607) );
CLKBUFX2TS U3052 ( .A(Data_B_i[1]), .Y(n3991) );
CLKBUFX2TS U3053 ( .A(Data_B_i[2]), .Y(n3986) );
INVX2TS U3054 ( .A(Data_A_i[1]), .Y(n3368) );
XNOR2X1TS U3055 ( .A(n3038), .B(n3037), .Y(n708) );
OAI21X2TS U3056 ( .A0(n2522), .A1(n2521), .B0(n2523), .Y(n873) );
XOR2X2TS U3057 ( .A(n2748), .B(n2749), .Y(n898) );
INVX2TS U3058 ( .A(n1998), .Y(n929) );
OAI22X1TS U3059 ( .A0(n2222), .A1(n2184), .B0(n2561), .B1(n2147), .Y(n2164)
);
NAND2X1TS U3060 ( .A(n6916), .B(n6839), .Y(n7071) );
INVX2TS U3061 ( .A(n7429), .Y(n5042) );
NAND2X2TS U3062 ( .A(n603), .B(n6569), .Y(n6571) );
OAI21X1TS U3063 ( .A0(n1662), .A1(n1663), .B0(n1661), .Y(n821) );
NAND2X2TS U3064 ( .A(n603), .B(n7150), .Y(n6580) );
INVX2TS U3065 ( .A(n3164), .Y(n770) );
INVX2TS U3066 ( .A(n6058), .Y(n372) );
INVX2TS U3067 ( .A(n6052), .Y(n418) );
OAI2BB1X1TS U3068 ( .A0N(n5869), .A1N(n5868), .B0(n409), .Y(n6030) );
XOR2X1TS U3069 ( .A(n5882), .B(n946), .Y(n5896) );
OAI21XLTS U3070 ( .A0(n991), .A1(n6273), .B0(n5906), .Y(n5907) );
OAI21XLTS U3071 ( .A0(n119), .A1(n5980), .B0(n5950), .Y(n5951) );
ADDFHX2TS U3072 ( .A(n4555), .B(n4554), .CI(n4553), .CO(n4590), .S(n4589) );
OAI2BB1X2TS U3073 ( .A0N(n5597), .A1N(n5596), .B0(n574), .Y(n5565) );
XNOR2X1TS U3074 ( .A(n575), .B(n5595), .Y(n5598) );
XOR2X1TS U3075 ( .A(n5567), .B(n524), .Y(n5600) );
CLKAND2X2TS U3076 ( .A(n5456), .B(Data_B_i[53]), .Y(n5462) );
INVX2TS U3077 ( .A(n7202), .Y(n7037) );
ADDFHX2TS U3078 ( .A(n3459), .B(n3458), .CI(n3457), .CO(n3748), .S(n3747) );
OAI21XLTS U3079 ( .A0(n117), .A1(n3686), .B0(n3623), .Y(n3624) );
XOR2XLTS U3080 ( .A(n3614), .B(n4297), .Y(n3654) );
OAI21XLTS U3081 ( .A0(n3988), .A1(n4296), .B0(n3613), .Y(n3614) );
CLKBUFX2TS U3082 ( .A(Data_B_i[2]), .Y(n3644) );
CLKBUFX2TS U3083 ( .A(Data_B_i[1]), .Y(n3772) );
NAND2X2TS U3084 ( .A(n743), .B(n3057), .Y(n814) );
OAI2BB1X2TS U3085 ( .A0N(n2792), .A1N(n2791), .B0(n633), .Y(n3132) );
INVX2TS U3086 ( .A(n659), .Y(n663) );
OAI21X1TS U3087 ( .A0(n1969), .A1(n1968), .B0(n1967), .Y(n922) );
ADDFHX2TS U3088 ( .A(n2036), .B(n2034), .CI(n2035), .CO(n2331), .S(n2330) );
ADDFHX2TS U3089 ( .A(n2174), .B(n2173), .CI(n2172), .CO(n2296), .S(n2294) );
ADDFHX2TS U3090 ( .A(n2218), .B(n2217), .CI(n2216), .CO(n2287), .S(n2286) );
NAND2BXLTS U3091 ( .AN(n2251), .B(n2596), .Y(n2245) );
INVX2TS U3092 ( .A(n6769), .Y(n497) );
OAI21X1TS U3093 ( .A0(n7429), .A1(n5024), .B0(n5023), .Y(n7117) );
CLKAND2X2TS U3094 ( .A(n7419), .B(Data_B_i[25]), .Y(n7417) );
AOI21X1TS U3095 ( .A0(n7692), .A1(n7697), .B0(n7155), .Y(n7156) );
AO21XLTS U3096 ( .A0(n7674), .A1(n296), .B0(n7672), .Y(n7675) );
AOI21X1TS U3097 ( .A0(n7664), .A1(n7665), .B0(n7663), .Y(n7666) );
OAI21X1TS U3098 ( .A0(n882), .A1(n7662), .B0(n7661), .Y(n7663) );
INVX1TS U3099 ( .A(n7717), .Y(n7733) );
AOI21X1TS U3100 ( .A0(n7146), .A1(n6562), .B0(n6564), .Y(n3186) );
NOR2XLTS U3101 ( .A(n370), .B(n7354), .Y(n7338) );
INVX2TS U3102 ( .A(n6056), .Y(n422) );
NAND2BX1TS U3103 ( .AN(n418), .B(n6053), .Y(n7372) );
INVX1TS U3104 ( .A(n7280), .Y(n7380) );
NAND2X2TS U3105 ( .A(n6451), .B(n6450), .Y(n7216) );
INVX2TS U3106 ( .A(n494), .Y(n7136) );
OAI21X2TS U3107 ( .A0(n7194), .A1(n7048), .B0(n495), .Y(n7208) );
INVX2TS U3108 ( .A(n4213), .Y(n790) );
AOI21X1TS U3109 ( .A0(n124), .A1(n3966), .B0(n3965), .Y(n7510) );
INVX2TS U3110 ( .A(n3713), .Y(n912) );
INVX2TS U3111 ( .A(n3709), .Y(n913) );
INVX1TS U3112 ( .A(n7538), .Y(n7646) );
OR2X1TS U3113 ( .A(n3642), .B(n3641), .Y(n7548) );
INVX2TS U3114 ( .A(n2535), .Y(n681) );
INVX2TS U3115 ( .A(n7911), .Y(n7912) );
NAND2X2TS U3116 ( .A(n2330), .B(n2329), .Y(n7911) );
INVX1TS U3117 ( .A(n7774), .Y(n7914) );
INVX2TS U3118 ( .A(n2303), .Y(n689) );
NAND2X1TS U3119 ( .A(n2299), .B(n2298), .Y(n7787) );
INVX2TS U3120 ( .A(n2285), .Y(n924) );
NOR2X1TS U3121 ( .A(n2275), .B(n2274), .Y(n2273) );
NOR2XLTS U3122 ( .A(n2257), .B(n2256), .Y(n7957) );
NOR2BX1TS U3123 ( .AN(n1197), .B(n1201), .Y(n1204) );
NOR2BX1TS U3124 ( .AN(n1321), .B(n1317), .Y(n719) );
AOI222XLTS U3125 ( .A0(n4716), .A1(n4276), .B0(n4817), .B1(n4275), .C0(n318),
.C1(n284), .Y(n4277) );
OAI2BB1X1TS U3126 ( .A0N(n6233), .A1N(n6484), .B0(n472), .Y(n471) );
XNOR2X1TS U3127 ( .A(Data_A_i[36]), .B(Data_A_i[37]), .Y(n5234) );
INVX2TS U3128 ( .A(n1081), .Y(n1071) );
OAI2BB1X1TS U3129 ( .A0N(n1015), .A1N(n1013), .B0(n1012), .Y(n758) );
INVX2TS U3130 ( .A(n1037), .Y(n1012) );
INVX2TS U3131 ( .A(n1213), .Y(n1214) );
NOR2X4TS U3132 ( .A(Data_A_i[46]), .B(Data_A_i[19]), .Y(n1035) );
INVX2TS U3133 ( .A(n1034), .Y(n1007) );
AOI21X1TS U3134 ( .A0(n1205), .A1(n1197), .B0(n1199), .Y(n643) );
NAND2BX1TS U3135 ( .AN(n645), .B(n1198), .Y(n644) );
NOR2X4TS U3136 ( .A(Data_A_i[44]), .B(Data_A_i[17]), .Y(n1016) );
AOI21X1TS U3137 ( .A0(n1205), .A1(n1204), .B0(n1203), .Y(n1206) );
OAI21XLTS U3138 ( .A0(n1202), .A1(n1201), .B0(n1200), .Y(n1203) );
INVX2TS U3139 ( .A(n1208), .Y(n1210) );
NAND2X1TS U3140 ( .A(Data_B_i[13]), .B(Data_B_i[40]), .Y(n1379) );
INVX2TS U3141 ( .A(n1249), .Y(n1189) );
INVX2TS U3142 ( .A(n1285), .Y(n1254) );
NAND2X1TS U3143 ( .A(Data_B_i[7]), .B(Data_B_i[34]), .Y(n1129) );
NAND2X1TS U3144 ( .A(Data_B_i[17]), .B(Data_B_i[44]), .Y(n1026) );
INVX2TS U3145 ( .A(n1297), .Y(n1300) );
NAND2X1TS U3146 ( .A(Data_B_i[42]), .B(Data_B_i[15]), .Y(n1097) );
NAND2X1TS U3147 ( .A(Data_B_i[14]), .B(Data_B_i[41]), .Y(n1110) );
NOR2X4TS U3148 ( .A(Data_B_i[34]), .B(Data_B_i[7]), .Y(n1128) );
NAND2X1TS U3149 ( .A(Data_A_i[38]), .B(Data_A_i[11]), .Y(n1258) );
NOR2X4TS U3150 ( .A(Data_A_i[11]), .B(Data_A_i[38]), .Y(n1257) );
NOR2X1TS U3151 ( .A(n1138), .B(n1133), .Y(n1280) );
NOR2X2TS U3152 ( .A(n1253), .B(n1257), .Y(n1001) );
OAI21X2TS U3153 ( .A0(n586), .A1(n1029), .B0(n1028), .Y(n666) );
INVX2TS U3154 ( .A(n1212), .Y(n1029) );
INVX2TS U3155 ( .A(n1858), .Y(n650) );
NAND2BX1TS U3156 ( .AN(n1584), .B(n650), .Y(n649) );
NAND3X2TS U3157 ( .A(n718), .B(n715), .C(n714), .Y(n723) );
NAND2X1TS U3158 ( .A(n720), .B(n719), .Y(n718) );
INVX2TS U3159 ( .A(n5192), .Y(n450) );
AND2X2TS U3160 ( .A(n5085), .B(n238), .Y(n4690) );
OAI21XLTS U3161 ( .A0(n4695), .A1(n4852), .B0(n4443), .Y(n4445) );
OAI21XLTS U3162 ( .A0(n4487), .A1(n4269), .B0(n4251), .Y(n4252) );
OAI21XLTS U3163 ( .A0(n117), .A1(n4519), .B0(n4247), .Y(n4248) );
XNOR2X1TS U3164 ( .A(n6688), .B(n504), .Y(n503) );
INVX2TS U3165 ( .A(Data_A_i[37]), .Y(n504) );
AOI222XLTS U3166 ( .A0(n4716), .A1(n4128), .B0(n4742), .B1(n3982), .C0(n317),
.C1(n3991), .Y(n3983) );
NAND2X1TS U3167 ( .A(n6071), .B(n6428), .Y(n402) );
NAND2X1TS U3168 ( .A(n460), .B(n5443), .Y(n5446) );
AOI21X1TS U3169 ( .A0(n6381), .A1(n6625), .B0(n554), .Y(n6305) );
OAI2BB1X1TS U3170 ( .A0N(n6428), .A1N(n6312), .B0(n555), .Y(n554) );
INVX2TS U3171 ( .A(n5957), .Y(n475) );
AOI21X1TS U3172 ( .A0(n6070), .A1(n6268), .B0(n550), .Y(n5326) );
OAI2BB1X1TS U3173 ( .A0N(n6381), .A1N(n6221), .B0(n551), .Y(n550) );
NOR2X2TS U3174 ( .A(n6849), .B(n6870), .Y(n5238) );
NOR2X2TS U3175 ( .A(n6901), .B(n6870), .Y(n5308) );
OAI21XLTS U3176 ( .A0(n117), .A1(n4269), .B0(n3817), .Y(n3818) );
INVX2TS U3177 ( .A(n3287), .Y(n3375) );
XNOR2X1TS U3178 ( .A(n268), .B(n2899), .Y(n1303) );
INVX2TS U3179 ( .A(n1448), .Y(n1324) );
XNOR2X1TS U3180 ( .A(n257), .B(n2560), .Y(n2563) );
CLKBUFX2TS U3181 ( .A(n2554), .Y(n711) );
OAI21XLTS U3182 ( .A0(n2618), .A1(n2617), .B0(n2619), .Y(n2558) );
OAI22X1TS U3183 ( .A0(n2096), .A1(n2556), .B0(n114), .B1(n2567), .Y(n2617)
);
XNOR2X1TS U3184 ( .A(n2909), .B(n2441), .Y(n2448) );
NAND2BX1TS U3185 ( .AN(n2561), .B(n894), .Y(n893) );
INVX2TS U3186 ( .A(n732), .Y(n738) );
XNOR2X1TS U3187 ( .A(n2483), .B(n2559), .Y(n2454) );
XNOR2X1TS U3188 ( .A(n1223), .B(n2897), .Y(n2451) );
OAI21X1TS U3189 ( .A0(n1012), .A1(n761), .B0(n758), .Y(n757) );
INVX2TS U3190 ( .A(n1389), .Y(n1390) );
NAND2X1TS U3191 ( .A(Data_B_i[10]), .B(Data_B_i[37]), .Y(n1393) );
INVX2TS U3192 ( .A(n756), .Y(n750) );
NOR2BX1TS U3193 ( .AN(n1305), .B(n1019), .Y(n755) );
NAND2X1TS U3194 ( .A(n1018), .B(n1017), .Y(n1019) );
INVX2TS U3195 ( .A(n1016), .Y(n1018) );
NAND2X1TS U3196 ( .A(n1019), .B(n1305), .Y(n753) );
CLKAND2X2TS U3197 ( .A(n1304), .B(n1305), .Y(n754) );
OAI21X1TS U3198 ( .A0(n1392), .A1(n1060), .B0(n1059), .Y(n1065) );
INVX2TS U3199 ( .A(n1061), .Y(n1063) );
BUFX4TS U3200 ( .A(n1392), .Y(n362) );
NAND2X2TS U3201 ( .A(Data_B_i[35]), .B(Data_B_i[8]), .Y(n1383) );
NAND2X1TS U3202 ( .A(Data_B_i[36]), .B(Data_B_i[9]), .Y(n1386) );
INVX2TS U3203 ( .A(n1126), .Y(n1123) );
INVX2TS U3204 ( .A(n1364), .Y(n1366) );
NAND2X4TS U3205 ( .A(Data_B_i[31]), .B(Data_B_i[4]), .Y(n1360) );
INVX2TS U3206 ( .A(n1358), .Y(n1362) );
INVX2TS U3207 ( .A(n5259), .Y(n5428) );
NOR2X1TS U3208 ( .A(n1101), .B(n1027), .Y(n1212) );
NOR2X1TS U3209 ( .A(n1150), .B(n1219), .Y(n1152) );
NAND2X1TS U3210 ( .A(Data_B_i[47]), .B(Data_B_i[20]), .Y(n1233) );
NAND2X1TS U3211 ( .A(Data_B_i[48]), .B(Data_B_i[21]), .Y(n1239) );
NAND2X4TS U3212 ( .A(n1106), .B(n533), .Y(n532) );
AOI21X2TS U3213 ( .A0(n1199), .A1(n1002), .B0(n609), .Y(n1003) );
NAND2X1TS U3214 ( .A(n1118), .B(n1114), .Y(n1346) );
INVX2TS U3215 ( .A(n1351), .Y(n1043) );
INVX2TS U3216 ( .A(n1576), .Y(n1554) );
AOI21X1TS U3217 ( .A0(n1315), .A1(n1049), .B0(n1048), .Y(n1050) );
NAND2X1TS U3218 ( .A(Data_A_i[50]), .B(Data_A_i[23]), .Y(n1053) );
NAND2X1TS U3219 ( .A(n6071), .B(n6282), .Y(n408) );
NAND2X1TS U3220 ( .A(n6071), .B(n6233), .Y(n396) );
AO21X1TS U3221 ( .A0(n424), .A1(n254), .B0(n204), .Y(n436) );
CLKAND2X2TS U3222 ( .A(n6425), .B(n5933), .Y(n204) );
NAND2X1TS U3223 ( .A(n5373), .B(n5196), .Y(n5354) );
OAI2BB1X1TS U3224 ( .A0N(n5986), .A1N(n424), .B0(n440), .Y(n439) );
NAND2X1TS U3225 ( .A(n6425), .B(n5936), .Y(n440) );
INVX2TS U3226 ( .A(n415), .Y(n414) );
NOR2X1TS U3227 ( .A(n5347), .B(n5348), .Y(n5373) );
NOR2X1TS U3228 ( .A(n5283), .B(n5285), .Y(n5341) );
AOI21X2TS U3229 ( .A0(n5189), .A1(n5190), .B0(n451), .Y(n5282) );
NAND2X1TS U3230 ( .A(n5217), .B(n5210), .Y(n451) );
XNOR2X1TS U3231 ( .A(Data_A_i[24]), .B(Data_A_i[25]), .Y(n3979) );
INVX2TS U3232 ( .A(n3788), .Y(n3873) );
CLKAND2X2TS U3233 ( .A(n5085), .B(n284), .Y(n4360) );
OAI21XLTS U3234 ( .A0(n4487), .A1(n4440), .B0(n4346), .Y(n4347) );
XOR2X1TS U3235 ( .A(n4267), .B(n5001), .Y(n4290) );
CLKAND2X2TS U3236 ( .A(n334), .B(n7418), .Y(n4239) );
NAND2BX1TS U3237 ( .AN(n196), .B(n429), .Y(n428) );
CLKAND2X2TS U3238 ( .A(n5699), .B(n290), .Y(n196) );
OAI21XLTS U3239 ( .A0(n161), .A1(n5684), .B0(n5683), .Y(n5685) );
OAI21XLTS U3240 ( .A0(n6619), .A1(n6363), .B0(n5677), .Y(n5678) );
OAI21XLTS U3241 ( .A0(n119), .A1(n5684), .B0(n5675), .Y(n5676) );
AOI222XLTS U3242 ( .A0(n6414), .A1(n6193), .B0(n6524), .B1(n254), .C0(n6613),
.C1(n6168), .Y(n5675) );
NOR2X1TS U3243 ( .A(n6849), .B(n6825), .Y(n5387) );
NOR2X1TS U3244 ( .A(n6788), .B(n6825), .Y(n5397) );
INVX2TS U3245 ( .A(n5377), .Y(n5321) );
XOR2XLTS U3246 ( .A(n5631), .B(n6390), .Y(n5702) );
INVX2TS U3247 ( .A(n5238), .Y(n5304) );
NAND2X1TS U3248 ( .A(n458), .B(n5301), .Y(n457) );
CLKAND2X2TS U3249 ( .A(n4075), .B(n7418), .Y(n4006) );
NAND2X1TS U3250 ( .A(n435), .B(n434), .Y(n433) );
NAND2X1TS U3251 ( .A(n424), .B(n6483), .Y(n434) );
AOI21X1TS U3252 ( .A0(n6465), .A1(n6267), .B0(n388), .Y(n5620) );
OAI21XLTS U3253 ( .A0(n6692), .A1(n6401), .B0(n5660), .Y(n5661) );
AOI21X1TS U3254 ( .A0(n6613), .A1(n5973), .B0(n467), .Y(n5658) );
OAI2BB1X1TS U3255 ( .A0N(n6194), .A1N(n5674), .B0(n468), .Y(n467) );
NAND2X1TS U3256 ( .A(n6198), .B(n6281), .Y(n468) );
OAI21XLTS U3257 ( .A0(n6813), .A1(n6273), .B0(n5650), .Y(n5651) );
AOI21X1TS U3258 ( .A0(n6410), .A1(n6222), .B0(n379), .Y(n6072) );
NAND2X1TS U3259 ( .A(n381), .B(n380), .Y(n379) );
AOI21X1TS U3260 ( .A0(n6465), .A1(n6388), .B0(n385), .Y(n5540) );
NAND2X1TS U3261 ( .A(n387), .B(n386), .Y(n385) );
AOI21X1TS U3262 ( .A0(n6716), .A1(Data_B_i[31]), .B0(n469), .Y(n5538) );
OAI2BB1X1TS U3263 ( .A0N(n6194), .A1N(n6221), .B0(n470), .Y(n469) );
NAND2X1TS U3264 ( .A(n6268), .B(n6281), .Y(n470) );
OAI21XLTS U3265 ( .A0(n119), .A1(n6386), .B0(n5512), .Y(n5513) );
AOI222XLTS U3266 ( .A0(n6312), .A1(n5973), .B0(n6625), .B1(n255), .C0(n6815),
.C1(n6168), .Y(n5512) );
AOI21X1TS U3267 ( .A0(n6070), .A1(n6198), .B0(n552), .Y(n5514) );
OAI2BB1X1TS U3268 ( .A0N(n6381), .A1N(n5674), .B0(n553), .Y(n552) );
OAI2BB1X1TS U3269 ( .A0N(n5984), .A1N(n6955), .B0(n585), .Y(n584) );
XOR2X1TS U3270 ( .A(n5223), .B(n6973), .Y(n5520) );
OAI21XLTS U3271 ( .A0(n5318), .A1(n5913), .B0(n5222), .Y(n5223) );
OAI21XLTS U3272 ( .A0(n6522), .A1(n5763), .B0(n5551), .Y(n5552) );
CLKAND2X2TS U3273 ( .A(n6360), .B(n7198), .Y(n6361) );
XOR2XLTS U3274 ( .A(n6341), .B(n6390), .Y(n6368) );
XOR2X1TS U3275 ( .A(n6338), .B(n6940), .Y(n6369) );
OAI21XLTS U3276 ( .A0(n6692), .A1(n6707), .B0(n5207), .Y(n5208) );
OAI21XLTS U3277 ( .A0(n6868), .A1(n6363), .B0(n5271), .Y(n5272) );
CLKAND2X2TS U3278 ( .A(n5833), .B(n7198), .Y(n5255) );
CLKAND2X2TS U3279 ( .A(n6183), .B(n7198), .Y(n6184) );
OAI21X1TS U3280 ( .A0(n498), .A1(n6679), .B0(n6678), .Y(n6680) );
CLKAND2X2TS U3281 ( .A(n6676), .B(n7198), .Y(n6677) );
BUFX4TS U3282 ( .A(Data_B_i[44]), .Y(n6849) );
CLKBUFX2TS U3283 ( .A(n6782), .Y(n6625) );
OA21X2TS U3284 ( .A0(n6662), .A1(n6962), .B0(n6481), .Y(n883) );
NAND2X1TS U3285 ( .A(n5364), .B(n5228), .Y(n5230) );
OAI21XLTS U3286 ( .A0(n4487), .A1(n4135), .B0(n4046), .Y(n4047) );
OAI21XLTS U3287 ( .A0(n4665), .A1(n4711), .B0(n4043), .Y(n4045) );
CLKBUFX2TS U3288 ( .A(n4677), .Y(n4525) );
AOI222XLTS U3289 ( .A0(n4935), .A1(n4128), .B0(n4823), .B1(n3986), .C0(n342),
.C1(n3772), .Y(n3773) );
OAI21XLTS U3290 ( .A0(n4665), .A1(n4625), .B0(n3760), .Y(n3762) );
OAI21XLTS U3291 ( .A0(n4695), .A1(n4408), .B0(n3831), .Y(n3833) );
AOI222XLTS U3292 ( .A0(n4348), .A1(n4442), .B0(n4009), .B1(n4663), .C0(n4021), .C1(n4292), .Y(n3831) );
OAI21XLTS U3293 ( .A0(n4370), .A1(n331), .B0(n3274), .Y(n3275) );
OAI21XLTS U3294 ( .A0(n116), .A1(n4135), .B0(n3239), .Y(n3240) );
OAI21XLTS U3295 ( .A0(n4370), .A1(n3901), .B0(n3440), .Y(n3441) );
INVX2TS U3296 ( .A(n3242), .Y(n3289) );
AOI21X1TS U3297 ( .A0(n3378), .A1(n3289), .B0(n3243), .Y(n3244) );
INVX2TS U3298 ( .A(n3393), .Y(n3313) );
XNOR2X1TS U3299 ( .A(Data_A_i[6]), .B(Data_A_i[7]), .Y(n3252) );
XNOR2X1TS U3300 ( .A(Data_A_i[5]), .B(Data_A_i[6]), .Y(n3253) );
AOI21X1TS U3301 ( .A0(n3338), .A1(n3209), .B0(n3208), .Y(n3233) );
INVX2TS U3302 ( .A(n1518), .Y(n1473) );
OAI22X1TS U3303 ( .A0(n2096), .A1(n2896), .B0(n2933), .B1(n2095), .Y(n3003)
);
INVX2TS U3304 ( .A(n639), .Y(n637) );
ADDFX2TS U3305 ( .A(n2881), .B(n2880), .CI(n2879), .CO(n3032), .S(n2914) );
OAI22X1TS U3306 ( .A0(n734), .A1(n2872), .B0(n2814), .B1(n2996), .Y(n2881)
);
NAND2BXLTS U3307 ( .AN(n853), .B(n2674), .Y(n851) );
NAND2BXLTS U3308 ( .AN(n2674), .B(n853), .Y(n852) );
XOR2X1TS U3309 ( .A(n2618), .B(n2617), .Y(n2620) );
ADDFX2TS U3310 ( .A(n2623), .B(n2622), .CI(n2621), .CO(n2733), .S(n2727) );
INVX2TS U3311 ( .A(n894), .Y(n892) );
NAND2BXLTS U3312 ( .AN(n2549), .B(n2395), .Y(n1903) );
XNOR2X1TS U3313 ( .A(n2559), .B(n1227), .Y(n2359) );
XOR2X1TS U3314 ( .A(n2841), .B(n261), .Y(n2353) );
INVX2TS U3315 ( .A(n2014), .Y(n2485) );
OAI22X1TS U3316 ( .A0(n908), .A1(n2561), .B0(n2222), .B1(n1982), .Y(n2008)
);
NAND2BX1TS U3317 ( .AN(n2020), .B(n2944), .Y(n647) );
XNOR2X1TS U3318 ( .A(n274), .B(n2440), .Y(n2079) );
XNOR2X1TS U3319 ( .A(n2865), .B(n2182), .Y(n2092) );
NAND2X1TS U3320 ( .A(n1132), .B(n1139), .Y(n1140) );
INVX2TS U3321 ( .A(n1173), .Y(n1141) );
NAND2BX1TS U3322 ( .AN(n1174), .B(n1172), .Y(n856) );
NAND2X1TS U3323 ( .A(Data_A_i[34]), .B(Data_A_i[7]), .Y(n1146) );
NOR2X6TS U3324 ( .A(Data_A_i[32]), .B(Data_A_i[5]), .Y(n1181) );
INVX2TS U3325 ( .A(n1328), .Y(n1180) );
NAND2X2TS U3326 ( .A(Data_A_i[31]), .B(Data_A_i[4]), .Y(n1328) );
NAND2X1TS U3327 ( .A(n1840), .B(n1842), .Y(n1841) );
INVX2TS U3328 ( .A(n1843), .Y(n1840) );
NAND2X1TS U3329 ( .A(n1421), .B(n1419), .Y(n1424) );
OAI22X1TS U3330 ( .A0(n2446), .A1(n1429), .B0(n2444), .B1(n1428), .Y(n1437)
);
XOR2X1TS U3331 ( .A(n2950), .B(n2935), .Y(n2984) );
CLKBUFX2TS U3332 ( .A(n4850), .Y(n4790) );
CLKAND2X2TS U3333 ( .A(n4828), .B(n7418), .Y(n4789) );
CLKBUFX2TS U3334 ( .A(n6339), .Y(n6903) );
CLKAND2X2TS U3335 ( .A(n340), .B(n7198), .Y(n6875) );
INVX2TS U3336 ( .A(n7202), .Y(n6902) );
NAND2X1TS U3337 ( .A(n4997), .B(n5060), .Y(n3857) );
INVX2TS U3338 ( .A(n7422), .Y(n4849) );
XOR2X1TS U3339 ( .A(n839), .B(n4833), .Y(n4727) );
NAND2X1TS U3340 ( .A(Data_B_i[49]), .B(Data_B_i[22]), .Y(n1268) );
NOR2XLTS U3341 ( .A(Data_A_i[53]), .B(Data_A_i[26]), .Y(n1354) );
NAND2X1TS U3342 ( .A(Data_A_i[53]), .B(Data_A_i[26]), .Y(n1355) );
OAI21X2TS U3343 ( .A0(n586), .A1(n588), .B0(n672), .Y(n587) );
INVX2TS U3344 ( .A(n1274), .Y(n1276) );
AO21XLTS U3345 ( .A0(n140), .A1(n2663), .B0(n598), .Y(n1680) );
OAI22X1TS U3346 ( .A0(n312), .A1(n1695), .B0(n2972), .B1(n1694), .Y(n769) );
XOR2X1TS U3347 ( .A(n1710), .B(n788), .Y(n1755) );
XNOR2X1TS U3348 ( .A(n789), .B(n1711), .Y(n788) );
OAI2BB1X1TS U3349 ( .A0N(n1614), .A1N(n1613), .B0(n1612), .Y(n1644) );
OAI21XLTS U3350 ( .A0(n1613), .A1(n1614), .B0(n1611), .Y(n1612) );
OAI2BB1X1TS U3351 ( .A0N(n1559), .A1N(n612), .B0(n610), .Y(n1591) );
OAI21XLTS U3352 ( .A0(n1559), .A1(n612), .B0(n1558), .Y(n610) );
OAI22X1TS U3353 ( .A0(n7674), .A1(n1578), .B0(n295), .B1(n1604), .Y(n1601)
);
XOR2XLTS U3354 ( .A(n5707), .B(n6217), .Y(n5738) );
OAI2BB1X1TS U3355 ( .A0N(n6194), .A1N(n424), .B0(n442), .Y(n441) );
NAND2X1TS U3356 ( .A(n6425), .B(n255), .Y(n442) );
OAI21XLTS U3357 ( .A0(n161), .A1(n6073), .B0(n5824), .Y(n5825) );
OAI21XLTS U3358 ( .A0(n119), .A1(n6073), .B0(n5830), .Y(n5831) );
AOI222XLTS U3359 ( .A0(n6465), .A1(n6193), .B0(n6180), .B1(n255), .C0(n6300),
.C1(n5948), .Y(n5830) );
AOI21X1TS U3360 ( .A0(n6465), .A1(n5761), .B0(n391), .Y(n5848) );
NAND2X1TS U3361 ( .A(n393), .B(n392), .Y(n391) );
NAND2X1TS U3362 ( .A(n6180), .B(n5986), .Y(n393) );
OAI21XLTS U3363 ( .A0(n161), .A1(n5875), .B0(n5862), .Y(n5863) );
XOR2X1TS U3364 ( .A(n5854), .B(n5853), .Y(n413) );
AOI21X1TS U3365 ( .A0(n6465), .A1(n5948), .B0(n382), .Y(n5852) );
NAND2X1TS U3366 ( .A(n384), .B(n383), .Y(n382) );
OAI21XLTS U3367 ( .A0(n119), .A1(n5875), .B0(n5874), .Y(n5876) );
XOR2X1TS U3368 ( .A(n5850), .B(n5853), .Y(n500) );
INVX2TS U3369 ( .A(n5474), .Y(n5476) );
NAND2X1TS U3370 ( .A(Data_B_i[30]), .B(Data_B_i[31]), .Y(n5315) );
INVX2TS U3371 ( .A(n5282), .Y(n5342) );
INVX2TS U3372 ( .A(n5283), .Y(n5316) );
NAND2X2TS U3373 ( .A(n6168), .B(Data_B_i[30]), .Y(n5210) );
CLKAND2X2TS U3374 ( .A(n4976), .B(n7418), .Y(n4977) );
XOR2X1TS U3375 ( .A(n5085), .B(Data_A_i[25]), .Y(n3981) );
XOR2XLTS U3376 ( .A(n4521), .B(n5110), .Y(n4636) );
XOR2XLTS U3377 ( .A(n4488), .B(n4970), .Y(n4513) );
XOR2XLTS U3378 ( .A(n4023), .B(Data_A_i[8]), .Y(n4282) );
NAND2X1TS U3379 ( .A(n405), .B(n404), .Y(n403) );
NAND2X1TS U3380 ( .A(n6071), .B(n6381), .Y(n405) );
NAND2X1TS U3381 ( .A(n432), .B(n431), .Y(n430) );
NAND2X1TS U3382 ( .A(n424), .B(n6282), .Y(n431) );
XOR2X1TS U3383 ( .A(n5649), .B(n5889), .Y(n6085) );
ADDFHX2TS U3384 ( .A(n6112), .B(n6111), .CI(n6110), .CO(n6118), .S(n6129) );
XOR2X1TS U3385 ( .A(n5432), .B(n5433), .Y(n527) );
OAI21XLTS U3386 ( .A0(n6813), .A1(n6623), .B0(n5313), .Y(n5314) );
OAI2BB1X1TS U3387 ( .A0N(n5470), .A1N(n5469), .B0(n902), .Y(n6204) );
XNOR2X1TS U3388 ( .A(n866), .B(Data_A_i[47]), .Y(n5439) );
XOR2XLTS U3389 ( .A(n6398), .B(n6963), .Y(n6458) );
XOR2XLTS U3390 ( .A(n3756), .B(n4444), .Y(n4159) );
XNOR2X1TS U3391 ( .A(n786), .B(n3761), .Y(n4158) );
XOR2XLTS U3392 ( .A(n3882), .B(n4242), .Y(n4179) );
XOR2XLTS U3393 ( .A(n3827), .B(Data_A_i[14]), .Y(n3886) );
XOR2X1TS U3394 ( .A(n3842), .B(n4264), .Y(n3890) );
XOR2XLTS U3395 ( .A(n3840), .B(Data_A_i[11]), .Y(n3891) );
OAI21XLTS U3396 ( .A0(n4718), .A1(n4408), .B0(n3786), .Y(n3787) );
XOR2X1TS U3397 ( .A(n3343), .B(n4264), .Y(n3360) );
OAI21XLTS U3398 ( .A0(n4621), .A1(n4241), .B0(n3467), .Y(n3468) );
OAI21XLTS U3399 ( .A0(n4487), .A1(n3686), .B0(n3593), .Y(n3594) );
OAI21XLTS U3400 ( .A0(n4431), .A1(n3686), .B0(n3545), .Y(n3546) );
OAI21XLTS U3401 ( .A0(n4370), .A1(n3686), .B0(n3564), .Y(n3565) );
OAI21XLTS U3402 ( .A0(n116), .A1(n3581), .B0(n3580), .Y(n3582) );
INVX2TS U3403 ( .A(Data_A_i[4]), .Y(n917) );
CLKBUFX2TS U3404 ( .A(Data_B_i[8]), .Y(n4368) );
CLKBUFX2TS U3405 ( .A(Data_B_i[8]), .Y(n4014) );
XNOR2X2TS U3406 ( .A(n1559), .B(n611), .Y(n1561) );
XNOR2X1TS U3407 ( .A(n612), .B(n1558), .Y(n611) );
XOR2X1TS U3408 ( .A(n1421), .B(n1420), .Y(n1403) );
OAI21X1TS U3409 ( .A0(n2996), .A1(n2994), .B0(n739), .Y(n3018) );
OAI22X1TS U3410 ( .A0(n7674), .A1(n1406), .B0(n2578), .B1(n1430), .Y(n1426)
);
INVX2TS U3411 ( .A(n3048), .Y(n219) );
INVX2TS U3412 ( .A(n3049), .Y(n220) );
ADDFHX2TS U3413 ( .A(n3027), .B(n3026), .CI(n3025), .CO(n3088), .S(n3048) );
OAI21XLTS U3414 ( .A0(n2696), .A1(n2697), .B0(n2698), .Y(n2571) );
OAI2BB1X1TS U3415 ( .A0N(n2676), .A1N(n819), .B0(n817), .Y(n2714) );
OAI21XLTS U3416 ( .A0(n2676), .A1(n819), .B0(n2675), .Y(n817) );
INVX2TS U3417 ( .A(n2513), .Y(n699) );
NAND2BX1TS U3418 ( .AN(n2505), .B(n131), .Y(n736) );
CLKAND2X2TS U3419 ( .A(n1874), .B(n1873), .Y(n1898) );
OAI22X1TS U3420 ( .A0(n127), .A1(n1958), .B0(n1931), .B1(n2962), .Y(n1962)
);
INVX2TS U3421 ( .A(n2924), .Y(n230) );
CLKBUFX2TS U3422 ( .A(n2399), .Y(n2796) );
NAND2BXLTS U3423 ( .AN(n2549), .B(n747), .Y(n1960) );
ADDFHX2TS U3424 ( .A(n2017), .B(n2016), .CI(n2015), .CO(n2033), .S(n2057) );
NAND2BXLTS U3425 ( .AN(n2549), .B(n336), .Y(n2013) );
ADDFX2TS U3426 ( .A(n2083), .B(n2082), .CI(n2081), .CO(n2121), .S(n2114) );
INVX2TS U3427 ( .A(n2101), .Y(n2598) );
XOR2X1TS U3428 ( .A(n2150), .B(n871), .Y(n870) );
OAI22X1TS U3429 ( .A0(n2147), .A1(n2562), .B0(n2141), .B1(n2249), .Y(n2162)
);
XOR2X1TS U3430 ( .A(n2865), .B(n2961), .Y(n2147) );
INVX2TS U3431 ( .A(n2168), .Y(n2462) );
NAND2X1TS U3432 ( .A(n1329), .B(n1328), .Y(n1331) );
XOR2X1TS U3433 ( .A(n1866), .B(n1865), .Y(n1868) );
NAND2X1TS U3434 ( .A(n1864), .B(n1863), .Y(n1865) );
INVX2TS U3435 ( .A(n1880), .Y(n1881) );
XOR2X2TS U3436 ( .A(n3092), .B(n861), .Y(n860) );
INVX2TS U3437 ( .A(n3091), .Y(n861) );
ADDFHX2TS U3438 ( .A(n3074), .B(n3073), .CI(n3072), .CO(n3095), .S(n3089) );
OAI2BB1X2TS U3439 ( .A0N(n3038), .A1N(n3039), .B0(n707), .Y(n3077) );
OAI21X2TS U3440 ( .A0(n3039), .A1(n3038), .B0(n3037), .Y(n707) );
CLKAND2X2TS U3441 ( .A(n328), .B(n7198), .Y(n6986) );
INVX4TS U3442 ( .A(n7422), .Y(n5085) );
CLKAND2X2TS U3443 ( .A(n5078), .B(n7418), .Y(n5079) );
CLKBUFX2TS U3444 ( .A(Data_B_i[22]), .Y(n4997) );
INVX2TS U3445 ( .A(n5147), .Y(n5148) );
ADDFHX2TS U3446 ( .A(n1565), .B(n1564), .CI(n1563), .CO(n1663), .S(n1594) );
NAND2X1TS U3447 ( .A(n6562), .B(n5171), .Y(n7660) );
NOR2X2TS U3448 ( .A(n6566), .B(n604), .Y(n6569) );
INVX2TS U3449 ( .A(n6562), .Y(n604) );
AOI21X1TS U3450 ( .A0(n1351), .A1(n1114), .B0(n1117), .Y(n1041) );
ADDFHX2TS U3451 ( .A(n1788), .B(n1787), .CI(n1786), .CO(n1805), .S(n1800) );
OAI21X1TS U3452 ( .A0(n624), .A1(n6579), .B0(n7149), .Y(n617) );
NAND2X1TS U3453 ( .A(n7150), .B(n619), .Y(n618) );
INVX2TS U3454 ( .A(n625), .Y(n619) );
BUFX3TS U3455 ( .A(n621), .Y(n351) );
INVX2TS U3456 ( .A(n6580), .Y(n615) );
OAI2BB1X1TS U3457 ( .A0N(n772), .A1N(n1671), .B0(n771), .Y(n1690) );
NAND2X1TS U3458 ( .A(n774), .B(n1672), .Y(n771) );
NAND2BXLTS U3459 ( .AN(n774), .B(n1677), .Y(n772) );
OAI22X1TS U3460 ( .A0(n789), .A1(n605), .B0(n1708), .B1(n606), .Y(n1716) );
XOR2X1TS U3461 ( .A(n1671), .B(n773), .Y(n1715) );
XOR2X2TS U3462 ( .A(n602), .B(n1726), .Y(n794) );
XOR2X1TS U3463 ( .A(n1728), .B(n1727), .Y(n602) );
OAI2BB1X1TS U3464 ( .A0N(n1722), .A1N(n769), .B0(n767), .Y(n1750) );
NAND2X1TS U3465 ( .A(n741), .B(n740), .Y(n1823) );
OAI22X1TS U3466 ( .A0(n1833), .A1(n1810), .B0(n1831), .B1(n1832), .Y(n1827)
);
XOR2XLTS U3467 ( .A(n5764), .B(Data_A_i[41]), .Y(n5797) );
XOR2XLTS U3468 ( .A(n5842), .B(n6274), .Y(n5864) );
OAI21X1TS U3469 ( .A0(n5447), .A1(n5347), .B0(n5346), .Y(n868) );
OAI21XLTS U3470 ( .A0(n161), .A1(n6004), .B0(n5915), .Y(n5916) );
XOR2XLTS U3471 ( .A(n5922), .B(n5989), .Y(n5992) );
AOI222XLTS U3472 ( .A0(n6315), .A1(n5948), .B0(n5987), .B1(n5933), .C0(n5920), .C1(n5936), .Y(n5921) );
OAI21X1TS U3473 ( .A0(n4071), .A1(n308), .B0(n4070), .Y(n799) );
CLKAND2X2TS U3474 ( .A(n7419), .B(n5060), .Y(n5075) );
AOI21X1TS U3475 ( .A0(n7446), .A1(n4593), .B0(n4592), .Y(n4594) );
ADDFHX2TS U3476 ( .A(n4564), .B(n4563), .CI(n4562), .CO(n4569), .S(n4571) );
ADDFHX2TS U3477 ( .A(n4342), .B(n4341), .CI(n4340), .CO(n4385), .S(n4387) );
OAI21X1TS U3478 ( .A0(n7571), .A1(n7580), .B0(n7572), .Y(n4218) );
ADDFHX2TS U3479 ( .A(n4395), .B(n4394), .CI(n4393), .CO(n4403), .S(n4399) );
XOR2XLTS U3480 ( .A(n5687), .B(Data_A_i[41]), .Y(n5745) );
ADDFHX2TS U3481 ( .A(n4146), .B(n4145), .CI(n4144), .CO(n4393), .S(n4174) );
ADDFHX2TS U3482 ( .A(n4149), .B(n4148), .CI(n4147), .CO(n4400), .S(n4173) );
ADDFHX2TS U3483 ( .A(n6100), .B(n6099), .CI(n6098), .CO(n6065), .S(n6101) );
XOR2XLTS U3484 ( .A(n5573), .B(n6090), .Y(n5612) );
XOR2X1TS U3485 ( .A(n5568), .B(n5569), .Y(n524) );
XNOR2X1TS U3486 ( .A(n5597), .B(n5596), .Y(n575) );
AOI21X1TS U3487 ( .A0(n163), .A1(n7251), .B0(n6148), .Y(n6149) );
OAI2BB1X1TS U3488 ( .A0N(n5569), .A1N(n5568), .B0(n521), .Y(n5561) );
OAI2BB1X1TS U3489 ( .A0N(n523), .A1N(n522), .B0(n5567), .Y(n521) );
ADDFHX2TS U3490 ( .A(n6254), .B(n6253), .CI(n6252), .CO(n6258), .S(n6255) );
ADDFHX2TS U3491 ( .A(n6373), .B(n6372), .CI(n6371), .CO(n6438), .S(n6351) );
ADDFHX2TS U3492 ( .A(n6266), .B(n6265), .CI(n6264), .CO(n6349), .S(n6307) );
XNOR2X1TS U3493 ( .A(n6723), .B(n484), .Y(n6726) );
XOR2X1TS U3494 ( .A(n6724), .B(n485), .Y(n484) );
XOR2X1TS U3495 ( .A(n6658), .B(n566), .Y(n6640) );
XOR2X1TS U3496 ( .A(n569), .B(n567), .Y(n566) );
XNOR2X1TS U3497 ( .A(n479), .B(n6701), .Y(n6646) );
ADDFHX2TS U3498 ( .A(n6605), .B(n6604), .CI(n6603), .CO(n6637), .S(n6634) );
CLKBUFX2TS U3499 ( .A(Data_B_i[52]), .Y(n6954) );
NOR2X2TS U3500 ( .A(n5214), .B(n583), .Y(n6970) );
INVX2TS U3501 ( .A(n7202), .Y(n6973) );
CLKAND2X2TS U3502 ( .A(n7199), .B(n6967), .Y(n6982) );
AO21XLTS U3503 ( .A0(n5460), .A1(Data_B_i[53]), .B0(n5459), .Y(n5461) );
INVX2TS U3504 ( .A(n462), .Y(n7009) );
INVX2TS U3505 ( .A(n7091), .Y(n463) );
NOR2X2TS U3506 ( .A(n7071), .B(n7009), .Y(n7184) );
XOR2XLTS U3507 ( .A(n4069), .B(n302), .Y(n4169) );
XOR2X1TS U3508 ( .A(n4067), .B(n4106), .Y(n4170) );
XOR2XLTS U3509 ( .A(n3785), .B(n302), .Y(n4166) );
ADDFHX2TS U3510 ( .A(n4203), .B(n4202), .CI(n4201), .CO(n4193), .S(n4204) );
XOR2XLTS U3511 ( .A(n3417), .B(n4242), .Y(n3437) );
OAI21XLTS U3512 ( .A0(n4718), .A1(n4296), .B0(n3416), .Y(n3417) );
XOR2XLTS U3513 ( .A(n3449), .B(n4468), .Y(n3494) );
XOR2XLTS U3514 ( .A(n3501), .B(n3761), .Y(n3723) );
OAI21XLTS U3515 ( .A0(n963), .A1(n4625), .B0(n3550), .Y(n3551) );
NAND2X1TS U3516 ( .A(n3354), .B(n3353), .Y(n3355) );
ADDHXLTS U3517 ( .A(n3678), .B(n3677), .CO(n3688), .S(n3681) );
XOR2XLTS U3518 ( .A(n3619), .B(n3832), .Y(n3678) );
OAI21XLTS U3519 ( .A0(n3988), .A1(n4408), .B0(n3618), .Y(n3619) );
CLKBUFX2TS U3520 ( .A(Data_B_i[5]), .Y(n4246) );
CLKBUFX2TS U3521 ( .A(Data_B_i[6]), .Y(n3828) );
CLKBUFX2TS U3522 ( .A(n202), .Y(n4150) );
CLKBUFX2TS U3523 ( .A(Data_B_i[4]), .Y(n3823) );
CLKBUFX2TS U3524 ( .A(Data_B_i[3]), .Y(n4128) );
INVX2TS U3525 ( .A(n1535), .Y(n858) );
ADDFHX2TS U3526 ( .A(n1512), .B(n1511), .CI(n1510), .CO(n1536), .S(n1506) );
INVX2TS U3527 ( .A(n3111), .Y(n808) );
INVX2TS U3528 ( .A(n3112), .Y(n807) );
INVX2TS U3529 ( .A(n2824), .Y(n889) );
XOR2X1TS U3530 ( .A(n2807), .B(n951), .Y(n2822) );
XOR2X1TS U3531 ( .A(n2808), .B(n952), .Y(n951) );
OAI2BB1X2TS U3532 ( .A0N(n2757), .A1N(n542), .B0(n538), .Y(n2741) );
OAI2BB1X1TS U3533 ( .A0N(n540), .A1N(n539), .B0(n2756), .Y(n538) );
OAI2BB1X2TS U3534 ( .A0N(n896), .A1N(n2747), .B0(n895), .Y(n2766) );
NAND2BX1TS U3535 ( .AN(n897), .B(n2748), .Y(n895) );
NAND2BX2TS U3536 ( .AN(n2748), .B(n897), .Y(n896) );
OAI21X1TS U3537 ( .A0(n2425), .A1(n2424), .B0(n2423), .Y(n679) );
ADDFHX2TS U3538 ( .A(n2375), .B(n2374), .CI(n2373), .CO(n2425), .S(n2421) );
OR2X1TS U3539 ( .A(n1952), .B(n1951), .Y(n674) );
INVX2TS U3540 ( .A(n1999), .Y(n928) );
XOR2X1TS U3541 ( .A(n1950), .B(n675), .Y(n1986) );
XOR2X1TS U3542 ( .A(n1952), .B(n1951), .Y(n675) );
OAI2BB1X1TS U3543 ( .A0N(n1963), .A1N(n1962), .B0(n930), .Y(n1974) );
ADDFHX2TS U3544 ( .A(n2005), .B(n2004), .CI(n2003), .CO(n1997), .S(n2036) );
XOR2X1TS U3545 ( .A(n1961), .B(n931), .Y(n2003) );
ADDFHX2TS U3546 ( .A(n2313), .B(n2312), .CI(n2311), .CO(n2318), .S(n2320) );
ADDFHX2TS U3547 ( .A(n2130), .B(n2129), .CI(n2128), .CO(n2311), .S(n2133) );
ADDFHX2TS U3548 ( .A(n2115), .B(n2114), .CI(n2113), .CO(n2132), .S(n2134) );
OAI2BB1X1TS U3549 ( .A0N(n2150), .A1N(n871), .B0(n869), .Y(n2153) );
OAI21XLTS U3550 ( .A0(n2150), .A1(n871), .B0(n2149), .Y(n869) );
NAND2BXLTS U3551 ( .AN(n2251), .B(n2905), .Y(n2167) );
NAND2BXLTS U3552 ( .AN(n2251), .B(n2441), .Y(n2211) );
OAI22X1TS U3553 ( .A0(n2246), .A1(n2231), .B0(n2224), .B1(n2453), .Y(n2268)
);
CLKBUFX2TS U3554 ( .A(n2248), .Y(n2798) );
XNOR2X1TS U3555 ( .A(n2560), .B(n280), .Y(n2240) );
CLKBUFX2TS U3556 ( .A(n2248), .Y(n2453) );
NAND2X4TS U3557 ( .A(Data_B_i[0]), .B(Data_B_i[27]), .Y(n1883) );
INVX2TS U3558 ( .A(n7422), .Y(n7419) );
CLKAND2X2TS U3559 ( .A(n4092), .B(Data_B_i[26]), .Y(n4098) );
CLKBUFX2TS U3560 ( .A(n4027), .Y(n5108) );
INVX2TS U3561 ( .A(n7422), .Y(n5110) );
OAI21XLTS U3562 ( .A0(n7128), .A1(n5131), .B0(n5132), .Y(n5093) );
AOI21X2TS U3563 ( .A0(n5171), .A1(n6564), .B0(n576), .Y(n882) );
OA21XLTS U3564 ( .A0(n6575), .A1(n7170), .B0(n6576), .Y(n577) );
OAI2BB1X1TS U3565 ( .A0N(n5158), .A1N(n5157), .B0(n579), .Y(n5169) );
OAI2BB1X1TS U3566 ( .A0N(n581), .A1N(n580), .B0(n5156), .Y(n579) );
XNOR2X1TS U3567 ( .A(n444), .B(n5827), .Y(n6034) );
XOR2X1TS U3568 ( .A(n5826), .B(n445), .Y(n444) );
OAI2BB1X1TS U3569 ( .A0N(n945), .A1N(n944), .B0(n5882), .Y(n943) );
XOR2XLTS U3570 ( .A(n5909), .B(n6005), .Y(n5961) );
OAI21XLTS U3571 ( .A0(n991), .A1(n5941), .B0(n5940), .Y(n5943) );
CLKBUFX2TS U3572 ( .A(n6168), .Y(n5948) );
AOI21X1TS U3573 ( .A0(n6593), .A1(n6592), .B0(n6591), .Y(n6594) );
NOR2BX1TS U3574 ( .AN(n7057), .B(n7044), .Y(n7047) );
OAI21XLTS U3575 ( .A0(n7211), .A1(n7052), .B0(n7053), .Y(n7022) );
AOI21X1TS U3576 ( .A0(n7007), .A1(n7074), .B0(n7006), .Y(n7008) );
NAND2X1TS U3577 ( .A(n7184), .B(n7190), .Y(n7193) );
OAI21XLTS U3578 ( .A0(n4487), .A1(n3671), .B0(n3576), .Y(n3577) );
XOR2XLTS U3579 ( .A(n3616), .B(n4242), .Y(n3648) );
OAI21XLTS U3580 ( .A0(n963), .A1(n3638), .B0(n3637), .Y(n3639) );
INVX2TS U3581 ( .A(n3058), .Y(n3060) );
OAI2BB1X2TS U3582 ( .A0N(n3052), .A1N(n3051), .B0(n3050), .Y(n3136) );
XNOR2X1TS U3583 ( .A(n652), .B(n2037), .Y(n2307) );
XOR2X1TS U3584 ( .A(n2038), .B(n653), .Y(n652) );
INVX2TS U3585 ( .A(n2039), .Y(n653) );
ADDFHX2TS U3586 ( .A(n2136), .B(n2135), .CI(n2134), .CO(n2301), .S(n2299) );
ADDFHX2TS U3587 ( .A(n2204), .B(n2203), .CI(n2202), .CO(n2291), .S(n2288) );
NAND2BXLTS U3588 ( .AN(n2251), .B(n2351), .Y(n2234) );
NOR2XLTS U3589 ( .A(Data_A_i[27]), .B(Data_A_i[0]), .Y(n1855) );
INVX2TS U3590 ( .A(n7139), .Y(n7140) );
INVX2TS U3591 ( .A(GEN1_Final_add_x_1_n124), .Y(n8182) );
INVX2TS U3592 ( .A(GEN1_Final_add_x_1_n149), .Y(n8156) );
INVX2TS U3593 ( .A(GEN1_Final_add_x_1_n156), .Y(n8145) );
INVX2TS U3594 ( .A(GEN1_Final_add_x_1_n161), .Y(n8143) );
INVX2TS U3595 ( .A(GEN1_Final_add_x_1_n178), .Y(n8130) );
INVX2TS U3596 ( .A(GEN1_Final_add_x_1_n185), .Y(n8117) );
INVX2TS U3597 ( .A(GEN1_Final_add_x_1_n190), .Y(n8115) );
INVX2TS U3598 ( .A(GEN1_Final_add_x_1_n203), .Y(n8104) );
INVX2TS U3599 ( .A(GEN1_Final_add_x_1_n210), .Y(n8093) );
INVX2TS U3600 ( .A(GEN1_Final_add_x_1_n288), .Y(n8016) );
INVX2TS U3601 ( .A(GEN1_Final_add_x_1_n296), .Y(n8304) );
CLKAND2X2TS U3602 ( .A(n7199), .B(Data_B_i[52]), .Y(n7197) );
OAI21XLTS U3603 ( .A0(n3988), .A1(n3638), .B0(n3633), .Y(n3634) );
CLKAND2X2TS U3604 ( .A(n7828), .B(n7177), .Y(n985) );
INVX2TS U3605 ( .A(n7850), .Y(n7839) );
NOR2X4TS U3606 ( .A(n815), .B(n3134), .Y(n7750) );
NAND2BXLTS U3607 ( .AN(n2251), .B(n2560), .Y(n2252) );
CLKBUFX2TS U3608 ( .A(n986), .Y(n7812) );
OAI21XLTS U3609 ( .A0(n7866), .A1(n7833), .B0(n7832), .Y(n7837) );
OAI21XLTS U3610 ( .A0(n7866), .A1(n7822), .B0(n7821), .Y(n7827) );
INVX2TS U3611 ( .A(n7823), .Y(n7825) );
XOR2X1TS U3612 ( .A(n7083), .B(n184), .Y(GEN1_left_N46) );
OAI21X1TS U3613 ( .A0(n7306), .A1(n7079), .B0(n7078), .Y(n7083) );
OAI21XLTS U3614 ( .A0(n7306), .A1(n7089), .B0(n7088), .Y(n7092) );
XOR2X1TS U3615 ( .A(n7055), .B(n210), .Y(GEN1_left_N51) );
INVX2TS U3616 ( .A(n7138), .Y(n7141) );
OAI21XLTS U3617 ( .A0(n7558), .A1(n5027), .B0(n5026), .Y(n5031) );
XOR2X1TS U3618 ( .A(n7433), .B(n177), .Y(GEN1_right_N42) );
OAI21X1TS U3619 ( .A0(n7306), .A1(n7066), .B0(n7065), .Y(n7070) );
XOR2XLTS U3620 ( .A(n6842), .B(n180), .Y(GEN1_left_N43) );
OAI21X1TS U3621 ( .A0(n7306), .A1(n7059), .B0(n7058), .Y(n7062) );
OAI21X1TS U3622 ( .A0(n7306), .A1(n7030), .B0(n7029), .Y(n7042) );
CLKAND2X2TS U3623 ( .A(n477), .B(n7110), .Y(n187) );
OAI21XLTS U3624 ( .A0(n7306), .A1(n7108), .B0(n7107), .Y(n7111) );
CLKAND2X2TS U3625 ( .A(n7105), .B(n7104), .Y(n186) );
OAI21XLTS U3626 ( .A0(n7306), .A1(n7103), .B0(n7102), .Y(n7106) );
CLKAND2X2TS U3627 ( .A(n7098), .B(n7097), .Y(n185) );
OAI21XLTS U3628 ( .A0(n7306), .A1(n7096), .B0(n7095), .Y(n7099) );
XNOR2X1TS U3629 ( .A(n7428), .B(n7427), .Y(GEN1_right_N53) );
OAI21XLTS U3630 ( .A0(n7558), .A1(n4953), .B0(n4952), .Y(n4956) );
INVX2TS U3631 ( .A(n5050), .Y(n4954) );
OAI21XLTS U3632 ( .A0(n216), .A1(n5102), .B0(n5101), .Y(n5116) );
OAI21XLTS U3633 ( .A0(n216), .A1(n5013), .B0(n5012), .Y(n5018) );
XNOR2X1TS U3634 ( .A(n5039), .B(n5038), .Y(GEN1_right_N44) );
OAI21XLTS U3635 ( .A0(n216), .A1(n5053), .B0(n5052), .Y(n5056) );
OAI21XLTS U3636 ( .A0(n7558), .A1(n7554), .B0(n7555), .Y(n5140) );
OAI21XLTS U3637 ( .A0(n7558), .A1(n4958), .B0(n4957), .Y(n4963) );
XOR2X1TS U3638 ( .A(n7171), .B(n172), .Y(GEN1_middle_N52) );
XOR2XLTS U3639 ( .A(n7151), .B(n175), .Y(GEN1_middle_N48) );
OAI21XLTS U3640 ( .A0(n316), .A1(n7687), .B0(n7686), .Y(n7691) );
INVX2TS U3641 ( .A(n7685), .Y(n7686) );
OAI21XLTS U3642 ( .A0(n217), .A1(n7734), .B0(n7733), .Y(n7739) );
INVX2TS U3643 ( .A(n7735), .Y(n7737) );
OAI21XLTS U3644 ( .A0(n217), .A1(n7858), .B0(n7859), .Y(n7744) );
INVX2TS U3645 ( .A(n7740), .Y(n7742) );
XOR2X1TS U3646 ( .A(n6585), .B(n967), .Y(GEN1_middle_N50) );
XNOR2X1TS U3647 ( .A(n7165), .B(n7164), .Y(GEN1_middle_N47) );
OAI21XLTS U3648 ( .A0(n217), .A1(n7160), .B0(n7159), .Y(n7165) );
INVX2TS U3649 ( .A(n7161), .Y(n7163) );
OAI21XLTS U3650 ( .A0(n217), .A1(n7695), .B0(n7694), .Y(n7699) );
OAI21XLTS U3651 ( .A0(n316), .A1(n7704), .B0(n7703), .Y(n7708) );
OAI21XLTS U3652 ( .A0(n316), .A1(n7710), .B0(n7709), .Y(n7714) );
XNOR2X1TS U3653 ( .A(n7725), .B(n7724), .Y(GEN1_middle_N42) );
OAI21XLTS U3654 ( .A0(n7335), .A1(n7259), .B0(n7258), .Y(n7262) );
INVX2TS U3655 ( .A(n7344), .Y(n7345) );
INVX2TS U3656 ( .A(n7358), .Y(n7359) );
NAND2X1TS U3657 ( .A(n987), .B(n7292), .Y(n7294) );
INVX2TS U3658 ( .A(n7461), .Y(n7463) );
INVX2TS U3659 ( .A(n7476), .Y(n7478) );
INVX2TS U3660 ( .A(n820), .Y(n7482) );
XOR2XLTS U3661 ( .A(n7575), .B(n7574), .Y(GEN1_right_N28) );
OAI21XLTS U3662 ( .A0(n7335), .A1(n7263), .B0(n7332), .Y(n7267) );
XOR2XLTS U3663 ( .A(n7583), .B(n7582), .Y(GEN1_right_N27) );
XOR2XLTS U3664 ( .A(n7314), .B(n7313), .Y(GEN1_left_N26) );
NAND2X1TS U3665 ( .A(n7250), .B(n125), .Y(n7254) );
XOR2XLTS U3666 ( .A(n7323), .B(n7322), .Y(GEN1_left_N28) );
XOR2XLTS U3667 ( .A(n7331), .B(n7330), .Y(GEN1_left_N27) );
INVX2TS U3668 ( .A(n6503), .Y(n6505) );
INVX2TS U3669 ( .A(n7224), .Y(n7226) );
XOR2XLTS U3670 ( .A(n310), .B(n7305), .Y(GEN1_left_N37) );
MX2X1TS U3671 ( .A(sgf_result_o[107]), .B(Result[107]), .S0(n8329), .Y(n3)
);
MX2X1TS U3672 ( .A(sgf_result_o[106]), .B(Result[106]), .S0(n8329), .Y(n4)
);
MX2X1TS U3673 ( .A(sgf_result_o[105]), .B(Result[105]), .S0(n8215), .Y(n5)
);
MX2X1TS U3674 ( .A(sgf_result_o[104]), .B(Result[104]), .S0(n8215), .Y(n6)
);
MX2X1TS U3675 ( .A(sgf_result_o[103]), .B(Result[103]), .S0(n8215), .Y(n7)
);
MX2X1TS U3676 ( .A(sgf_result_o[102]), .B(Result[102]), .S0(n8215), .Y(n8)
);
MX2X1TS U3677 ( .A(sgf_result_o[101]), .B(Result[101]), .S0(n8215), .Y(n9)
);
MX2X1TS U3678 ( .A(sgf_result_o[100]), .B(Result[100]), .S0(n8215), .Y(n10)
);
MX2X1TS U3679 ( .A(sgf_result_o[99]), .B(Result[99]), .S0(n8215), .Y(n11) );
MX2X1TS U3680 ( .A(sgf_result_o[98]), .B(Result[98]), .S0(n8215), .Y(n12) );
MX2X1TS U3681 ( .A(sgf_result_o[97]), .B(Result[97]), .S0(n8215), .Y(n13) );
MX2X1TS U3682 ( .A(sgf_result_o[96]), .B(Result[96]), .S0(n8215), .Y(n14) );
MX2X1TS U3683 ( .A(sgf_result_o[95]), .B(Result[95]), .S0(n8214), .Y(n15) );
MX2X1TS U3684 ( .A(sgf_result_o[94]), .B(Result[94]), .S0(n8214), .Y(n16) );
MX2X1TS U3685 ( .A(sgf_result_o[93]), .B(Result[93]), .S0(n8214), .Y(n17) );
MX2X1TS U3686 ( .A(sgf_result_o[92]), .B(Result[92]), .S0(n8214), .Y(n18) );
MX2X1TS U3687 ( .A(sgf_result_o[91]), .B(Result[91]), .S0(n8214), .Y(n19) );
MX2X1TS U3688 ( .A(sgf_result_o[90]), .B(Result[90]), .S0(n8214), .Y(n20) );
XOR2XLTS U3689 ( .A(n8186), .B(n8185), .Y(n8187) );
XOR2XLTS U3690 ( .A(n8172), .B(n8171), .Y(n8173) );
XOR2XLTS U3691 ( .A(n8178), .B(n8165), .Y(n8166) );
XOR2XLTS U3692 ( .A(n8160), .B(n8159), .Y(n8161) );
XOR2XLTS U3693 ( .A(n8084), .B(n8082), .Y(n8083) );
OAI21XLTS U3694 ( .A0(n8073), .A1(GEN1_Final_add_x_1_n236), .B0(
GEN1_Final_add_x_1_n237), .Y(n8076) );
INVX2TS U3695 ( .A(GEN1_Final_add_x_1_n236), .Y(n8069) );
INVX2TS U3696 ( .A(GEN1_Final_add_x_1_n249), .Y(n8056) );
INVX2TS U3697 ( .A(GEN1_Final_add_x_1_n257), .Y(n8046) );
INVX2TS U3698 ( .A(GEN1_Final_add_x_1_n270), .Y(n8036) );
INVX2TS U3699 ( .A(GEN1_Final_add_x_1_n278), .Y(n8025) );
INVX2TS U3700 ( .A(GEN1_Final_add_x_1_n291), .Y(n8308) );
XOR2XLTS U3701 ( .A(n7566), .B(n7565), .Y(GEN1_right_N26) );
INVX2TS U3702 ( .A(n7562), .Y(n7564) );
NAND2X1TS U3703 ( .A(n7501), .B(n7513), .Y(n7505) );
INVX2TS U3704 ( .A(n7616), .Y(n7618) );
OAI21XLTS U3705 ( .A0(n7637), .A1(n7633), .B0(n7634), .Y(n7537) );
XOR2XLTS U3706 ( .A(n7652), .B(n7651), .Y(GEN1_right_N6) );
INVX2TS U3707 ( .A(n7858), .Y(n7860) );
INVX2TS U3708 ( .A(n7862), .Y(n7863) );
XOR2XLTS U3709 ( .A(n7882), .B(n7881), .Y(GEN1_middle_N29) );
XOR2XLTS U3710 ( .A(n7871), .B(n7870), .Y(GEN1_middle_N28) );
INVX2TS U3711 ( .A(n7874), .Y(n7869) );
XOR2XLTS U3712 ( .A(n7890), .B(n7889), .Y(GEN1_middle_N27) );
NAND2X1TS U3713 ( .A(n7756), .B(n7766), .Y(n7760) );
INVX2TS U3714 ( .A(n7906), .Y(n7908) );
INVX2TS U3715 ( .A(n7902), .Y(n7895) );
INVX2TS U3716 ( .A(n7915), .Y(n7917) );
OAI21XLTS U3717 ( .A0(n7924), .A1(n7920), .B0(n7921), .Y(n7782) );
INVX2TS U3718 ( .A(n7778), .Y(n7780) );
INVX2TS U3719 ( .A(n7786), .Y(n7788) );
INVX2TS U3720 ( .A(n7942), .Y(n7944) );
XOR2XLTS U3721 ( .A(n7951), .B(n7950), .Y(GEN1_middle_N7) );
OAI21X2TS U3722 ( .A0(n7791), .A1(n692), .B0(n691), .Y(n7785) );
OAI22X2TS U3723 ( .A0(n2687), .A1(n324), .B0(n2840), .B1(n2927), .Y(n2818)
);
ADDFHX2TS U3724 ( .A(n1972), .B(n1971), .CI(n1970), .CO(n2335), .S(n2334) );
OAI21XLTS U3725 ( .A0(n991), .A1(n6401), .B0(n5988), .Y(n5990) );
OAI21XLTS U3726 ( .A0(n5065), .A1(n4467), .B0(n4349), .Y(n4350) );
OAI21XLTS U3727 ( .A0(n4995), .A1(n4467), .B0(n4310), .Y(n4311) );
OAI21XLTS U3728 ( .A0(n4969), .A1(n4467), .B0(n4244), .Y(n4245) );
OAI21XLTS U3729 ( .A0(n4773), .A1(n4467), .B0(n4078), .Y(n4079) );
OAI21XLTS U3730 ( .A0(n4826), .A1(n4467), .B0(n4010), .Y(n4011) );
OAI21XLTS U3731 ( .A0(n4621), .A1(n4467), .B0(n3255), .Y(n3256) );
AND2X8TS U3732 ( .A(n3148), .B(n3149), .Y(n217) );
OAI21X1TS U3733 ( .A0(n5065), .A1(n331), .B0(n4668), .Y(n4669) );
AOI21X1TS U3734 ( .A0(n5695), .A1(n6001), .B0(n394), .Y(n5772) );
AOI21X1TS U3735 ( .A0(n5695), .A1(n5917), .B0(n406), .Y(n5739) );
AOI21X1TS U3736 ( .A0(n5695), .A1(n6201), .B0(n400), .Y(n5723) );
XOR2X1TS U3737 ( .A(n5829), .B(n415), .Y(n5895) );
NOR2BX1TS U3738 ( .AN(n5829), .B(n414), .Y(n5820) );
OAI21X1TS U3739 ( .A0(n7358), .A1(n7361), .B0(n7362), .Y(n7366) );
NAND2X2TS U3740 ( .A(n419), .B(n376), .Y(n375) );
ADDFHX2TS U3741 ( .A(n3066), .B(n3065), .CI(n3064), .CO(n3104), .S(n3075) );
NAND2X4TS U3742 ( .A(n3161), .B(n7716), .Y(n7710) );
ADDFHX2TS U3743 ( .A(n4534), .B(n4533), .CI(n4532), .CO(n4599), .S(n4553) );
OAI21X2TS U3744 ( .A0(n3048), .A1(n3049), .B0(n3047), .Y(n956) );
OAI21X2TS U3745 ( .A0(n4005), .A1(n308), .B0(n4004), .Y(n881) );
NOR2X2TS U3746 ( .A(n7786), .B(n7931), .Y(n2300) );
OAI22X2TS U3747 ( .A0(n2092), .A1(n326), .B0(n2080), .B1(n2798), .Y(n2090)
);
NAND2X2TS U3748 ( .A(n4575), .B(n4574), .Y(n7494) );
XNOR2X1TS U3749 ( .A(n4949), .B(n4948), .Y(GEN1_right_N47) );
OAI2BB1X1TS U3750 ( .A0N(n5755), .A1N(n5754), .B0(n833), .Y(n6136) );
INVX4TS U3751 ( .A(n955), .Y(n5179) );
NOR2X2TS U3752 ( .A(n3771), .B(n3770), .Y(n4018) );
OAI22X1TS U3753 ( .A0(n5151), .A1(n2864), .B0(n2863), .B1(n2978), .Y(n3008)
);
ADDFHX2TS U3754 ( .A(n6124), .B(n6123), .CI(n6122), .CO(n6116), .S(n6134) );
NAND2X2TS U3755 ( .A(n3134), .B(n815), .Y(n7751) );
OAI2BB1X1TS U3756 ( .A0N(n2808), .A1N(n952), .B0(n950), .Y(n2916) );
OAI21XLTS U3757 ( .A0(n2808), .A1(n952), .B0(n2807), .Y(n950) );
INVX8TS U3758 ( .A(n781), .Y(n2548) );
NOR2BX2TS U3759 ( .AN(n916), .B(n3226), .Y(n3542) );
XNOR2X1TS U3760 ( .A(n1884), .B(n1883), .Y(n157) );
XNOR2X1TS U3761 ( .A(n1844), .B(n1841), .Y(n158) );
XNOR2X1TS U3762 ( .A(n1131), .B(n170), .Y(n159) );
OA21X4TS U3763 ( .A0(n586), .A1(n1171), .B0(n1170), .Y(n160) );
CLKINVX3TS U3764 ( .A(n365), .Y(n229) );
INVX2TS U3765 ( .A(n1976), .Y(n249) );
BUFX3TS U3766 ( .A(n2142), .Y(n2955) );
XNOR2X1TS U3767 ( .A(n5289), .B(n5288), .Y(n161) );
CLKINVX3TS U3768 ( .A(n2974), .Y(n2398) );
OR2X2TS U3769 ( .A(n6147), .B(n6146), .Y(n163) );
INVX2TS U3770 ( .A(n1711), .Y(n1708) );
XNOR2X1TS U3771 ( .A(Data_A_i[35]), .B(Data_A_i[36]), .Y(n5235) );
XOR2X1TS U3772 ( .A(n1359), .B(n1363), .Y(n164) );
INVX2TS U3773 ( .A(n501), .Y(n5695) );
AND2X2TS U3774 ( .A(n1025), .B(n1026), .Y(n166) );
AND2X2TS U3775 ( .A(n1387), .B(n1386), .Y(n167) );
AND2X2TS U3776 ( .A(n1130), .B(n1129), .Y(n170) );
OR2X1TS U3777 ( .A(Data_B_i[28]), .B(n6168), .Y(n174) );
XNOR2X2TS U3778 ( .A(n5447), .B(n5276), .Y(n179) );
INVX2TS U3779 ( .A(n370), .Y(n7352) );
NAND2BX2TS U3780 ( .AN(n7269), .B(n371), .Y(n370) );
INVX4TS U3781 ( .A(n572), .Y(n310) );
AOI22X1TS U3782 ( .A0(n4680), .A1(n3992), .B0(n322), .B1(n4026), .Y(n190) );
AOI22X1TS U3783 ( .A0(n4463), .A1(n3992), .B0(n3447), .B1(n3991), .Y(n191)
);
OR2X1TS U3784 ( .A(n4026), .B(n3978), .Y(n192) );
XNOR2X1TS U3785 ( .A(n1065), .B(n1064), .Y(n2078) );
INVX2TS U3786 ( .A(n1223), .Y(n365) );
INVX2TS U3787 ( .A(n6757), .Y(n6848) );
OR2X1TS U3788 ( .A(n3656), .B(n3655), .Y(n193) );
INVX2TS U3789 ( .A(n671), .Y(n268) );
INVX2TS U3790 ( .A(n2961), .Y(n2229) );
XNOR2X1TS U3791 ( .A(n1127), .B(n1124), .Y(n195) );
NOR2X1TS U3792 ( .A(Data_B_i[49]), .B(Data_B_i[22]), .Y(n1269) );
NOR2BX1TS U3793 ( .AN(n844), .B(n5167), .Y(n6563) );
INVX2TS U3794 ( .A(n6563), .Y(n578) );
INVX2TS U3795 ( .A(n2928), .Y(n2351) );
INVX2TS U3796 ( .A(n1327), .Y(n2928) );
INVX2TS U3797 ( .A(n2848), .Y(n243) );
INVX2TS U3798 ( .A(n2860), .Y(n2596) );
AOI22X1TS U3799 ( .A0(n6080), .A1(n288), .B0(n5977), .B1(n5936), .Y(n197) );
NAND2X1TS U3800 ( .A(n6080), .B(n5912), .Y(n200) );
NAND2X1TS U3801 ( .A(n6414), .B(n5912), .Y(n201) );
AND2X4TS U3802 ( .A(n914), .B(n915), .Y(n202) );
NAND2X4TS U3803 ( .A(n2863), .B(n827), .Y(n5151) );
INVX2TS U3804 ( .A(n7172), .Y(n7866) );
INVX2TS U3805 ( .A(n5492), .Y(n452) );
NAND2X1TS U3806 ( .A(n1118), .B(n1115), .Y(n205) );
INVX2TS U3807 ( .A(n5354), .Y(n460) );
AND3X1TS U3808 ( .A(n466), .B(n465), .C(n464), .Y(n207) );
NAND2X1TS U3809 ( .A(n5241), .B(n5301), .Y(n5425) );
INVX2TS U3810 ( .A(n5235), .Y(n502) );
INVX2TS U3811 ( .A(n477), .Y(n7109) );
NAND2X2TS U3812 ( .A(n478), .B(n497), .Y(n477) );
BUFX6TS U3813 ( .A(Data_A_i[41]), .Y(n355) );
INVX2TS U3814 ( .A(Data_A_i[5]), .Y(n4418) );
INVX2TS U3815 ( .A(n6945), .Y(n6877) );
INVX2TS U3816 ( .A(n4975), .Y(n4792) );
NOR2X1TS U3817 ( .A(n6030), .B(n6031), .Y(n7361) );
NOR2X2TS U3818 ( .A(n6060), .B(n6061), .Y(n7354) );
NOR2BX2TS U3819 ( .AN(n938), .B(n6033), .Y(n937) );
INVX2TS U3820 ( .A(n939), .Y(n419) );
AND2X2TS U3821 ( .A(n7206), .B(n7205), .Y(n214) );
CLKBUFX2TS U3822 ( .A(n2548), .Y(n7673) );
NOR2X2TS U3823 ( .A(n3704), .B(n3703), .Y(n7633) );
CLKBUFX2TS U3824 ( .A(n233), .Y(n215) );
INVX4TS U3825 ( .A(n874), .Y(n216) );
INVX4TS U3826 ( .A(n874), .Y(n7558) );
OAI22X2TS U3827 ( .A0(n345), .A1(n1892), .B0(n2638), .B1(n2346), .Y(n2342)
);
ADDFHX2TS U3828 ( .A(n6094), .B(n6093), .CI(n6092), .CO(n6123), .S(n6113) );
AOI21X1TS U3829 ( .A0(n6365), .A1(n5973), .B0(n441), .Y(n5741) );
AOI222XLTS U3830 ( .A0(n6664), .A1(n6660), .B0(n6365), .B1(n6659), .C0(n6323), .C1(n6685), .Y(n5371) );
AOI21X1TS U3831 ( .A0(n6365), .A1(n5761), .B0(n437), .Y(n5762) );
OAI2BB1X1TS U3832 ( .A0N(n291), .A1N(n5699), .B0(n557), .Y(n556) );
AOI21X1TS U3833 ( .A0(n6365), .A1(Data_B_i[29]), .B0(n436), .Y(n5775) );
OAI2BB1X1TS U3834 ( .A0N(n256), .A1N(n5699), .B0(n474), .Y(n473) );
AOI21X1TS U3835 ( .A0(n6365), .A1(n5933), .B0(n439), .Y(n5777) );
NOR2X2TS U3836 ( .A(n3970), .B(n3969), .Y(n3923) );
XNOR2X2TS U3837 ( .A(Data_A_i[20]), .B(Data_A_i[21]), .Y(n3770) );
INVX2TS U3838 ( .A(n7347), .Y(n371) );
OAI21X2TS U3839 ( .A0(n7347), .A1(n7344), .B0(n7348), .Y(n7351) );
OAI21X1TS U3840 ( .A0(n1556), .A1(n344), .B0(n649), .Y(n1590) );
XNOR2X1TS U3841 ( .A(n2838), .B(n2596), .Y(n2611) );
XNOR2X1TS U3842 ( .A(n7123), .B(n7122), .Y(GEN1_right_N45) );
ADDFHX2TS U3843 ( .A(n5563), .B(n5562), .CI(n5561), .CO(n6256), .S(n5564) );
NOR2XLTS U3844 ( .A(n5318), .B(n5937), .Y(n506) );
NAND2X4TS U3845 ( .A(n7172), .B(n3131), .Y(n3149) );
INVX4TS U3846 ( .A(n598), .Y(n313) );
INVX2TS U3847 ( .A(n5323), .Y(n5376) );
OAI21X1TS U3848 ( .A0(n5366), .A1(n5447), .B0(n5365), .Y(n884) );
BUFX6TS U3849 ( .A(n1955), .Y(n2602) );
ADDFHX2TS U3850 ( .A(n6493), .B(n6492), .CI(n6491), .CO(n6494), .S(n6453) );
OAI22X2TS U3851 ( .A0(n333), .A1(n2615), .B0(n2614), .B1(n226), .Y(n2634) );
INVX4TS U3852 ( .A(n2014), .Y(n336) );
OAI21XLTS U3853 ( .A0(n990), .A1(n5941), .B0(n5934), .Y(n5935) );
ADDHX1TS U3854 ( .A(n5274), .B(n5273), .CO(n5468), .S(n5434) );
OAI21XLTS U3855 ( .A0(n990), .A1(n6273), .B0(n5908), .Y(n5909) );
OAI21XLTS U3856 ( .A0(n990), .A1(n6707), .B0(n5777), .Y(n5778) );
OAI21XLTS U3857 ( .A0(n990), .A1(n6828), .B0(n5706), .Y(n5707) );
ADDFHX2TS U3858 ( .A(n1629), .B(n1628), .CI(n1627), .CO(n1767), .S(n1652) );
ADDFHX2TS U3859 ( .A(n6206), .B(n6205), .CI(n6204), .CO(n6214), .S(n6191) );
NOR2X4TS U3860 ( .A(n6773), .B(n6772), .Y(n6757) );
ADDFHX2TS U3861 ( .A(n2981), .B(n2980), .CI(n2979), .CO(n3027), .S(n3023) );
OAI22X2TS U3862 ( .A0(n323), .A1(n2484), .B0(n2595), .B1(n2927), .Y(n2593)
);
ADDFHX2TS U3863 ( .A(n5981), .B(n6232), .CI(n6231), .CO(n6295), .S(n6241) );
OAI21XLTS U3864 ( .A0(n179), .A1(n6386), .B0(n6169), .Y(n6170) );
ADDFHX2TS U3865 ( .A(n1776), .B(n1775), .CI(n1774), .CO(n1778), .S(n1780) );
CLKBUFX2TS U3866 ( .A(n7838), .Y(n218) );
NOR2X4TS U3867 ( .A(n814), .B(n813), .Y(n7838) );
ADDFHX2TS U3868 ( .A(n2711), .B(n2710), .CI(n2709), .CO(n2716), .S(n2744) );
OAI2BB1X1TS U3869 ( .A0N(n2673), .A1N(n852), .B0(n851), .Y(n2711) );
OAI22X2TS U3870 ( .A0(n127), .A1(n1895), .B0(n1894), .B1(n2663), .Y(n1914)
);
AOI21X1TS U3871 ( .A0(n7685), .A1(n7689), .B0(n7158), .Y(n7159) );
INVX4TS U3872 ( .A(n2944), .Y(n344) );
OAI21X1TS U3873 ( .A0(n3052), .A1(n3051), .B0(n3053), .Y(n3050) );
NAND2X2TS U3874 ( .A(n1858), .B(n654), .Y(n2692) );
OAI2BB1X2TS U3875 ( .A0N(n359), .A1N(n1137), .B0(n1190), .Y(n646) );
CLKINVX1TS U3876 ( .A(n7146), .Y(n7147) );
AOI21X1TS U3877 ( .A0(n7146), .A1(n5173), .B0(n5172), .Y(n5174) );
OAI21X1TS U3878 ( .A0(n1763), .A1(n1764), .B0(n794), .Y(n793) );
OAI2BB1X1TS U3879 ( .A0N(n1764), .A1N(n1763), .B0(n793), .Y(n3169) );
INVX2TS U3880 ( .A(n5151), .Y(n223) );
INVX2TS U3881 ( .A(n2906), .Y(n225) );
INVX2TS U3882 ( .A(n225), .Y(n226) );
INVX2TS U3883 ( .A(n360), .Y(n227) );
INVX2TS U3884 ( .A(n360), .Y(n228) );
INVX2TS U3885 ( .A(n3262), .Y(n3978) );
INVX2TS U3886 ( .A(n230), .Y(n231) );
OAI22X1TS U3887 ( .A0(n232), .A1(n2810), .B0(n2809), .B1(n2870), .Y(n2878)
);
BUFX3TS U3888 ( .A(n2996), .Y(n732) );
INVX4TS U3889 ( .A(n2483), .Y(n2912) );
INVX2TS U3890 ( .A(Data_B_i[11]), .Y(n234) );
INVX2TS U3891 ( .A(n234), .Y(n235) );
INVX2TS U3892 ( .A(n234), .Y(n236) );
INVX2TS U3893 ( .A(n4419), .Y(n237) );
INVX2TS U3894 ( .A(n237), .Y(n238) );
INVX2TS U3895 ( .A(n237), .Y(n239) );
INVX2TS U3896 ( .A(Data_B_i[19]), .Y(n240) );
INVX2TS U3897 ( .A(n240), .Y(n241) );
CLKBUFX2TS U3898 ( .A(Data_B_i[31]), .Y(n5957) );
CLKBUFX2TS U3899 ( .A(Data_B_i[31]), .Y(n5973) );
INVX2TS U3900 ( .A(n560), .Y(n242) );
INVX2TS U3901 ( .A(Data_B_i[35]), .Y(n560) );
CLKBUFX2TS U3902 ( .A(Data_B_i[35]), .Y(n5917) );
CLKBUFX2TS U3903 ( .A(Data_B_i[35]), .Y(n6336) );
CLKINVX6TS U3904 ( .A(n243), .Y(n244) );
XOR2X2TS U3905 ( .A(Data_A_i[20]), .B(Data_A_i[19]), .Y(n3261) );
INVX2TS U3906 ( .A(n246), .Y(n248) );
INVX2TS U3907 ( .A(n249), .Y(n251) );
INVX2TS U3908 ( .A(n5761), .Y(n253) );
INVX2TS U3909 ( .A(n253), .Y(n254) );
INVX2TS U3910 ( .A(n253), .Y(n255) );
CLKBUFX2TS U3911 ( .A(Data_B_i[32]), .Y(n256) );
AOI21X1TS U3912 ( .A0(n6323), .A1(n256), .B0(n430), .Y(n5700) );
CLKBUFX2TS U3913 ( .A(n256), .Y(n5998) );
CLKBUFX2TS U3914 ( .A(Data_B_i[32]), .Y(n6194) );
NAND2X1TS U3915 ( .A(Data_B_i[32]), .B(Data_B_i[31]), .Y(n5286) );
INVX2TS U3916 ( .A(n2815), .Y(n259) );
INVX2TS U3917 ( .A(n2813), .Y(n261) );
INVX2TS U3918 ( .A(n261), .Y(n262) );
INVX2TS U3919 ( .A(n1789), .Y(n263) );
INVX2TS U3920 ( .A(n1227), .Y(n1789) );
INVX2TS U3921 ( .A(n159), .Y(n264) );
INVX2TS U3922 ( .A(n159), .Y(n265) );
INVX2TS U3923 ( .A(n155), .Y(n270) );
INVX2TS U3924 ( .A(n195), .Y(n271) );
INVX2TS U3925 ( .A(n195), .Y(n272) );
INVX2TS U3926 ( .A(n164), .Y(n276) );
INVX2TS U3927 ( .A(n158), .Y(n277) );
INVX2TS U3928 ( .A(n158), .Y(n278) );
INVX2TS U3929 ( .A(n156), .Y(n279) );
INVX2TS U3930 ( .A(n156), .Y(n280) );
INVX2TS U3931 ( .A(n157), .Y(n281) );
INVX2TS U3932 ( .A(n157), .Y(n282) );
CLKBUFX2TS U3933 ( .A(Data_B_i[3]), .Y(n283) );
CLKBUFX2TS U3934 ( .A(Data_B_i[4]), .Y(n284) );
NAND2X1TS U3935 ( .A(Data_B_i[4]), .B(Data_B_i[3]), .Y(n3276) );
INVX2TS U3936 ( .A(Data_B_i[7]), .Y(n285) );
INVX2TS U3937 ( .A(n285), .Y(n286) );
AOI222XLTS U3938 ( .A0(n4716), .A1(n238), .B0(n4817), .B1(Data_B_i[8]), .C0(
n5106), .C1(n286), .Y(n4420) );
NOR2X1TS U3939 ( .A(Data_B_i[6]), .B(Data_B_i[7]), .Y(n3327) );
CLKBUFX2TS U3940 ( .A(Data_B_i[10]), .Y(n287) );
CLKBUFX2TS U3941 ( .A(Data_B_i[10]), .Y(n4429) );
CLKBUFX2TS U3942 ( .A(Data_B_i[10]), .Y(n4133) );
INVX2TS U3943 ( .A(n864), .Y(n288) );
CLKBUFX2TS U3944 ( .A(Data_B_i[28]), .Y(n5933) );
CLKBUFX2TS U3945 ( .A(n288), .Y(n5984) );
NAND2X2TS U3946 ( .A(n6168), .B(Data_B_i[28]), .Y(n5217) );
NAND2X2TS U3947 ( .A(Data_B_i[28]), .B(Data_B_i[1]), .Y(n1882) );
NOR2X4TS U3948 ( .A(Data_B_i[28]), .B(Data_B_i[1]), .Y(n1880) );
CLKBUFX2TS U3949 ( .A(Data_B_i[33]), .Y(n289) );
AOI21X1TS U3950 ( .A0(n6323), .A1(n289), .B0(n428), .Y(n5681) );
AOI222XLTS U3951 ( .A0(n6312), .A1(n6336), .B0(n6625), .B1(n6282), .C0(n6735), .C1(Data_B_i[33]), .Y(n6169) );
CLKBUFX2TS U3952 ( .A(Data_B_i[33]), .Y(n6233) );
NAND2X1TS U3953 ( .A(Data_B_i[33]), .B(Data_B_i[32]), .Y(n5471) );
CLKBUFX2TS U3954 ( .A(Data_B_i[34]), .Y(n290) );
NOR2X2TS U3955 ( .A(Data_B_i[33]), .B(Data_B_i[34]), .Y(n5474) );
NAND2X1TS U3956 ( .A(Data_B_i[34]), .B(Data_B_i[35]), .Y(n5346) );
NAND2X1TS U3957 ( .A(Data_B_i[33]), .B(Data_B_i[34]), .Y(n5475) );
CLKBUFX2TS U3958 ( .A(Data_B_i[36]), .Y(n291) );
AOI21X1TS U3959 ( .A0(n6323), .A1(n291), .B0(n433), .Y(n5588) );
CLKBUFX2TS U3960 ( .A(Data_B_i[36]), .Y(n6381) );
CLKBUFX2TS U3961 ( .A(Data_B_i[36]), .Y(n5978) );
NOR2X1TS U3962 ( .A(Data_B_i[35]), .B(Data_B_i[36]), .Y(n5348) );
NAND2X1TS U3963 ( .A(Data_B_i[36]), .B(Data_B_i[35]), .Y(n5349) );
NAND2X1TS U3964 ( .A(Data_B_i[36]), .B(Data_B_i[37]), .Y(n5374) );
NOR2X1TS U3965 ( .A(Data_B_i[36]), .B(Data_B_i[37]), .Y(n5323) );
CLKBUFX2TS U3966 ( .A(Data_B_i[47]), .Y(n292) );
NAND2X1TS U3967 ( .A(n6901), .B(Data_B_i[47]), .Y(n5427) );
CLKBUFX2TS U3968 ( .A(Data_B_i[38]), .Y(n293) );
CLKBUFX2TS U3969 ( .A(Data_B_i[38]), .Y(n6483) );
CLKBUFX2TS U3970 ( .A(Data_B_i[38]), .Y(n6201) );
NAND2X1TS U3971 ( .A(n6685), .B(Data_B_i[38]), .Y(n5441) );
NOR2X1TS U3972 ( .A(Data_B_i[37]), .B(Data_B_i[38]), .Y(n5380) );
INVX2TS U3973 ( .A(n294), .Y(n296) );
INVX2TS U3974 ( .A(n194), .Y(n298) );
NAND2X1TS U3975 ( .A(n1494), .B(n862), .Y(n299) );
CLKBUFX2TS U3976 ( .A(n5182), .Y(n949) );
INVX2TS U3977 ( .A(n2955), .Y(n300) );
INVX2TS U3978 ( .A(n300), .Y(n301) );
INVX2TS U3979 ( .A(n3251), .Y(n302) );
XOR2X1TS U3980 ( .A(n302), .B(Data_A_i[7]), .Y(n3254) );
INVX2TS U3981 ( .A(n3251), .Y(n4468) );
INVX2TS U3982 ( .A(Data_A_i[8]), .Y(n3251) );
INVX2TS U3983 ( .A(n4418), .Y(n303) );
OAI22X1TS U3984 ( .A0(n826), .A1(n1467), .B0(n5149), .B1(n1520), .Y(n1514)
);
BUFX3TS U3985 ( .A(n2863), .Y(n5149) );
AO21X1TS U3986 ( .A0(n2602), .A1(n231), .B0(n2066), .Y(n1631) );
OAI22X1TS U3987 ( .A0(n2602), .A1(n2491), .B0(n2924), .B1(n2601), .Y(n2622)
);
OAI22X1TS U3988 ( .A0(n2602), .A1(n2601), .B0(n2924), .B1(n2612), .Y(n2644)
);
OAI22X1TS U3989 ( .A0(n2602), .A1(n1930), .B0(n2924), .B1(n1872), .Y(n1928)
);
OAI22X1TS U3990 ( .A0(n1955), .A1(n2350), .B0(n2924), .B1(n2353), .Y(n2367)
);
OAI2BB1X1TS U3991 ( .A0N(n306), .A1N(n517), .B0(n6938), .Y(n6941) );
OAI2BB1X1TS U3992 ( .A0N(n306), .A1N(n516), .B0(n6956), .Y(n6958) );
OAI2BB1X1TS U3993 ( .A0N(n306), .A1N(n515), .B0(n6971), .Y(n6974) );
OAI2BB1X1TS U3994 ( .A0N(n519), .A1N(n514), .B0(n6812), .Y(n6814) );
OAI2BB1X1TS U3995 ( .A0N(n519), .A1N(n513), .B0(n6855), .Y(n6857) );
NOR2BX1TS U3996 ( .AN(n519), .B(n6868), .Y(n510) );
NOR2BX1TS U3997 ( .AN(n519), .B(n6929), .Y(n518) );
OAI2BB1X1TS U3998 ( .A0N(n519), .A1N(n512), .B0(n6898), .Y(n6900) );
NOR2BX1TS U3999 ( .AN(n519), .B(n6780), .Y(n509) );
NOR2BX1TS U4000 ( .AN(n519), .B(n6692), .Y(n507) );
INVX2TS U4001 ( .A(n5318), .Y(n519) );
OAI21X1TS U4002 ( .A0(n4102), .A1(n3790), .B0(n3789), .Y(n3793) );
OAI21X1TS U4003 ( .A0(n4102), .A1(n3424), .B0(n3423), .Y(n3429) );
INVX2TS U4004 ( .A(n798), .Y(n4102) );
INVX2TS U4005 ( .A(n712), .Y(n2998) );
INVX2TS U4006 ( .A(n1906), .Y(n311) );
OAI22X1TS U4007 ( .A0(n312), .A1(n1648), .B0(n2972), .B1(n1695), .Y(n1713)
);
NAND2X4TS U4008 ( .A(n3148), .B(n3149), .Y(n641) );
OAI21X1TS U4009 ( .A0(n316), .A1(n6583), .B0(n6582), .Y(n6585) );
OAI21X1TS U4010 ( .A0(n316), .A1(n3187), .B0(n3186), .Y(n349) );
OAI21X1TS U4011 ( .A0(n217), .A1(n7148), .B0(n7147), .Y(n7151) );
OAI21X1TS U4012 ( .A0(n315), .A1(n7169), .B0(n7168), .Y(n7171) );
NAND3X1TS U4013 ( .A(n3981), .B(n3980), .C(n3979), .Y(n5081) );
INVX2TS U4014 ( .A(n5081), .Y(n317) );
INVX2TS U4015 ( .A(n5081), .Y(n318) );
INVX2TS U4016 ( .A(n940), .Y(n319) );
AOI222XLTS U4017 ( .A0(n5695), .A1(n6281), .B0(n6071), .B1(n6194), .C0(n319),
.C1(n6193), .Y(n5799) );
OAI2BB1X1TS U4018 ( .A0N(n6201), .A1N(n319), .B0(n389), .Y(n388) );
NAND2X1TS U4019 ( .A(n319), .B(n6001), .Y(n398) );
NAND2X1TS U4020 ( .A(n319), .B(n5998), .Y(n395) );
NAND2X1TS U4021 ( .A(n319), .B(n6070), .Y(n380) );
CLKBUFX2TS U4022 ( .A(n6300), .Y(n6621) );
INVX2TS U4023 ( .A(n940), .Y(n6300) );
OR2X2TS U4024 ( .A(n3261), .B(n3260), .Y(n4830) );
INVX2TS U4025 ( .A(n4830), .Y(n320) );
INVX2TS U4026 ( .A(n4830), .Y(n321) );
CLKBUFX2TS U4027 ( .A(n320), .Y(n4631) );
NOR2X2TS U4028 ( .A(n3273), .B(n3272), .Y(n322) );
NOR2X2TS U4029 ( .A(n3273), .B(n3272), .Y(n4667) );
INVX2TS U4030 ( .A(n1877), .Y(n2930) );
INVX2TS U4031 ( .A(n2930), .Y(n323) );
INVX2TS U4032 ( .A(n2930), .Y(n324) );
OAI22X1TS U4033 ( .A0(n2363), .A1(n2361), .B0(n323), .B1(n925), .Y(n2403) );
OAI22X1TS U4034 ( .A0(n324), .A1(n2363), .B0(n2361), .B1(n2362), .Y(n2406)
);
OAI22X1TS U4035 ( .A0(n323), .A1(n2362), .B0(n2927), .B1(n2451), .Y(n2436)
);
BUFX3TS U4036 ( .A(n1369), .Y(n2096) );
INVX2TS U4037 ( .A(n2861), .Y(n2799) );
INVX2TS U4038 ( .A(n2799), .Y(n326) );
INVX2TS U4039 ( .A(n2799), .Y(n327) );
OAI22X1TS U4040 ( .A0(n2029), .A1(n326), .B0(n1983), .B1(n2798), .Y(n2011)
);
OAI22X1TS U4041 ( .A0(n327), .A1(n2580), .B0(n2800), .B1(n2609), .Y(n2793)
);
INVX2TS U4042 ( .A(n6738), .Y(n6985) );
INVX2TS U4043 ( .A(n6985), .Y(n328) );
INVX2TS U4044 ( .A(n6985), .Y(n329) );
AOI21X1TS U4045 ( .A0(n328), .A1(n291), .B0(n558), .Y(n6429) );
AOI21X1TS U4046 ( .A0(n329), .A1(n256), .B0(n471), .Y(n6234) );
AOI21X1TS U4047 ( .A0(n328), .A1(n5910), .B0(n506), .Y(n585) );
INVX2TS U4048 ( .A(n3480), .Y(n3837) );
INVX2TS U4049 ( .A(n3837), .Y(n331) );
OAI21XLTS U4050 ( .A0(n4520), .A1(n330), .B0(n3767), .Y(n3768) );
OAI21XLTS U4051 ( .A0(n4431), .A1(n330), .B0(n3826), .Y(n3827) );
OAI21XLTS U4052 ( .A0(n4421), .A1(n331), .B0(n3836), .Y(n3838) );
OAI21XLTS U4053 ( .A0(n117), .A1(n330), .B0(n3442), .Y(n3443) );
OAI21XLTS U4054 ( .A0(n4487), .A1(n331), .B0(n3763), .Y(n3764) );
OAI21XLTS U4055 ( .A0(n4621), .A1(n330), .B0(n4137), .Y(n4138) );
OAI21XLTS U4056 ( .A0(n116), .A1(n331), .B0(n3465), .Y(n3466) );
NOR2XLTS U4057 ( .A(n781), .B(n955), .Y(n7677) );
NOR2XLTS U4058 ( .A(n781), .B(n1830), .Y(n5146) );
NOR2XLTS U4059 ( .A(n781), .B(n5161), .Y(n5184) );
OAI22X1TS U4060 ( .A0(n295), .A1(n2550), .B0(n5182), .B1(n781), .Y(n819) );
NOR2XLTS U4061 ( .A(n781), .B(n2912), .Y(n1828) );
NOR2XLTS U4062 ( .A(n781), .B(n1789), .Y(n1829) );
NOR2XLTS U4063 ( .A(n5180), .B(n665), .Y(n1799) );
INVX2TS U4064 ( .A(n2940), .Y(n332) );
INVX2TS U4065 ( .A(n2940), .Y(n333) );
INVX2TS U4066 ( .A(n3684), .Y(n4238) );
INVX2TS U4067 ( .A(n4238), .Y(n334) );
INVX2TS U4068 ( .A(n4238), .Y(n335) );
AOI222XLTS U4069 ( .A0(n4222), .A1(n4292), .B0(n334), .B1(n4517), .C0(n4115),
.C1(n4516), .Y(n3467) );
INVX2TS U4070 ( .A(n5625), .Y(n6905) );
INVX2TS U4071 ( .A(n6905), .Y(n337) );
INVX2TS U4072 ( .A(n6905), .Y(n338) );
OAI21XLTS U4073 ( .A0(n6692), .A1(n337), .B0(n6389), .Y(n6391) );
OAI21X1TS U4074 ( .A0(n337), .A1(n5913), .B0(n5630), .Y(n5631) );
XNOR2X1TS U4075 ( .A(n740), .B(n252), .Y(n1405) );
INVX2TS U4076 ( .A(n713), .Y(n2395) );
INVX2TS U4077 ( .A(n713), .Y(n2871) );
INVX2TS U4078 ( .A(n713), .Y(n740) );
INVX2TS U4079 ( .A(n6221), .Y(n6874) );
INVX2TS U4080 ( .A(n6874), .Y(n340) );
AOI222XLTS U4081 ( .A0(n6268), .A1(n254), .B0(n339), .B1(n5986), .C0(n6716),
.C1(n5984), .Y(n5626) );
NAND3X1TS U4082 ( .A(n3771), .B(n3770), .C(n3769), .Y(n4998) );
INVX2TS U4083 ( .A(n4998), .Y(n341) );
INVX2TS U4084 ( .A(n4998), .Y(n342) );
INVX2TS U4085 ( .A(n4998), .Y(n343) );
XNOR2X1TS U4086 ( .A(Data_A_i[21]), .B(Data_A_i[22]), .Y(n3769) );
INVX2TS U4087 ( .A(n2944), .Y(n346) );
OAI22X1TS U4088 ( .A0(n2030), .A1(n1954), .B0(n345), .B1(n1990), .Y(n1992)
);
OAI22X1TS U4089 ( .A0(n2030), .A1(n2013), .B0(n345), .B1(n2014), .Y(n2122)
);
OAI22X1TS U4090 ( .A0(n346), .A1(n2557), .B0(n2638), .B1(n2613), .Y(n2619)
);
AOI21X1TS U4091 ( .A0(n346), .A1(n2030), .B0(n2014), .Y(n789) );
OAI22X1TS U4092 ( .A0(n2639), .A1(n344), .B0(n2638), .B1(n637), .Y(n2690) );
NAND2X1TS U4093 ( .A(n2142), .B(n1289), .Y(n347) );
NAND2X1TS U4094 ( .A(n2142), .B(n1289), .Y(n348) );
OAI22X1TS U4095 ( .A0(n1957), .A1(n2958), .B0(n2464), .B1(n1926), .Y(n1948)
);
AO21X1TS U4096 ( .A0(n2958), .A1(n301), .B0(n2101), .Y(n1589) );
NAND2X2TS U4097 ( .A(n2142), .B(n1289), .Y(n2958) );
OAI2BB1X1TS U4098 ( .A0N(n6725), .A1N(n6724), .B0(n483), .Y(n6751) );
OAI2BB1X1TS U4099 ( .A0N(n5884), .A1N(n5883), .B0(n943), .Y(n6051) );
XNOR2X1TS U4100 ( .A(n5140), .B(n5139), .Y(GEN1_right_N38) );
XNOR2X1TS U4101 ( .A(n4956), .B(n4955), .Y(GEN1_right_N40) );
XNOR2X1TS U4102 ( .A(n5018), .B(n5017), .Y(GEN1_right_N48) );
XNOR2X1TS U4103 ( .A(n5056), .B(n5055), .Y(GEN1_right_N41) );
XNOR2X1TS U4104 ( .A(n5116), .B(n5115), .Y(GEN1_right_N52) );
XNOR2X1TS U4105 ( .A(n4963), .B(n4962), .Y(GEN1_right_N39) );
ADDFHX2TS U4106 ( .A(n2468), .B(n2467), .CI(n2466), .CO(n2747), .S(n2517) );
AOI21X2TS U4107 ( .A0(n7500), .A1(n3975), .B0(n3974), .Y(n910) );
ADDHX1TS U4108 ( .A(n5680), .B(n5679), .CO(n6075), .S(n6094) );
OAI21X4TS U4109 ( .A0(n2340), .A1(n7774), .B0(n2339), .Y(n7755) );
XNOR2X4TS U4110 ( .A(n352), .B(n1534), .Y(n1528) );
XOR2X4TS U4111 ( .A(n858), .B(n1536), .Y(n352) );
XOR2X4TS U4112 ( .A(n353), .B(n2852), .Y(n2921) );
XOR2X4TS U4113 ( .A(n2851), .B(n2853), .Y(n353) );
INVX2TS U4114 ( .A(n7716), .Y(n7734) );
AOI21X4TS U4115 ( .A0(n2546), .A1(n7755), .B0(n354), .Y(n7854) );
OAI21X4TS U4116 ( .A0(n2545), .A1(n7764), .B0(n2544), .Y(n354) );
NOR2X2TS U4117 ( .A(n3739), .B(n3738), .Y(n7524) );
INVX2TS U4118 ( .A(n4596), .Y(n356) );
OAI2BB1X4TS U4119 ( .A0N(n4597), .A1N(n7435), .B0(n356), .Y(n874) );
NOR2X2TS U4120 ( .A(n6586), .B(n6589), .Y(n6592) );
ADDHXLTS U4121 ( .A(n5738), .B(n5737), .CO(n5713), .S(n5769) );
XOR2X4TS U4122 ( .A(n357), .B(n1751), .Y(n1773) );
INVX2TS U4123 ( .A(n7664), .Y(n3175) );
NOR2X2TS U4124 ( .A(n7710), .B(n6580), .Y(n7138) );
OAI21X2TS U4125 ( .A0(n7429), .A1(n4925), .B0(n4924), .Y(n5100) );
AOI21X4TS U4126 ( .A0(n4908), .A1(n4951), .B0(n4907), .Y(n7429) );
AOI21X4TS U4127 ( .A0(n932), .A1(n3137), .B0(n358), .Y(n7745) );
OAI21X4TS U4128 ( .A0(n7850), .A1(n7842), .B0(n7843), .Y(n358) );
OAI21X4TS U4129 ( .A0(n7750), .A1(n7864), .B0(n7751), .Y(n932) );
INVX2TS U4130 ( .A(n1191), .Y(n359) );
ADDFHX2TS U4131 ( .A(n2822), .B(n2821), .CI(n2820), .CO(n2917), .S(n2829) );
INVX4TS U4132 ( .A(n2066), .Y(n2640) );
NOR2X2TS U4133 ( .A(n7600), .B(n7521), .Y(n7606) );
INVX4TS U4134 ( .A(n3147), .Y(n3148) );
ADDFHX2TS U4135 ( .A(n2413), .B(n2412), .CI(n2411), .CO(n2418), .S(n2422) );
ADDFHX4TS U4136 ( .A(n2831), .B(n2830), .CI(n2829), .CO(n2852), .S(n2792) );
OAI21X2TS U4137 ( .A0(n1243), .A1(n670), .B0(n1242), .Y(n1245) );
NAND2X1TS U4138 ( .A(n1120), .B(n1347), .Y(n783) );
INVX6TS U4139 ( .A(n1056), .Y(n1392) );
BUFX6TS U4140 ( .A(n2865), .Y(n361) );
OAI22X1TS U4141 ( .A0(n2349), .A1(n1953), .B0(n2347), .B1(n1922), .Y(n1952)
);
ADDFHX2TS U4142 ( .A(n6121), .B(n6120), .CI(n6119), .CO(n6144), .S(n6141) );
OAI21X4TS U4143 ( .A0(n7823), .A1(n7818), .B0(n7824), .Y(n7829) );
ADDFHX2TS U4144 ( .A(n3069), .B(n3068), .CI(n3067), .CO(n3096), .S(n3103) );
NOR2X4TS U4145 ( .A(n2786), .B(n2785), .Y(n7878) );
XOR2X4TS U4146 ( .A(n809), .B(n3110), .Y(n3128) );
INVX2TS U4147 ( .A(n7194), .Y(n7087) );
OAI21X4TS U4148 ( .A0(n369), .A1(n7268), .B0(n368), .Y(n7249) );
OAI21X2TS U4149 ( .A0(n7194), .A1(n7076), .B0(n7075), .Y(n7101) );
ADDFHX2TS U4150 ( .A(n1966), .B(n1965), .CI(n1964), .CO(n2420), .S(n1971) );
NAND2X2TS U4151 ( .A(n6162), .B(n7325), .Y(n6164) );
XOR2X4TS U4152 ( .A(n363), .B(n2732), .Y(n2763) );
XOR2X4TS U4153 ( .A(n2731), .B(n2730), .Y(n543) );
OAI2BB1X4TS U4154 ( .A0N(n2734), .A1N(n2733), .B0(n364), .Y(n2730) );
OAI21X4TS U4155 ( .A0(n2733), .A1(n2734), .B0(n2732), .Y(n364) );
ADDFX2TS U4156 ( .A(n2384), .B(n2383), .CI(n2382), .CO(n2388), .S(n2387) );
OAI22X1TS U4157 ( .A0(n1856), .A1(n2095), .B0(n2934), .B1(n1925), .Y(n1912)
);
BUFX3TS U4158 ( .A(n5523), .Y(n6949) );
AOI21X4TS U4159 ( .A0(n7271), .A1(n417), .B0(n416), .Y(n7268) );
AOI21X1TS U4160 ( .A0(n5695), .A1(n5978), .B0(n397), .Y(n5711) );
NAND2X1TS U4161 ( .A(n6071), .B(n6336), .Y(n399) );
AOI21X1TS U4162 ( .A0(n5695), .A1(n6070), .B0(n403), .Y(n5697) );
XOR2X4TS U4163 ( .A(n6688), .B(Data_A_i[39]), .Y(n5205) );
XOR2X4TS U4164 ( .A(n355), .B(Data_A_i[40]), .Y(n5206) );
NAND2X1TS U4165 ( .A(n6061), .B(n6060), .Y(n7355) );
INVX2TS U4166 ( .A(n7001), .Y(n448) );
OAI21X4TS U4167 ( .A0(n5282), .A1(n449), .B0(n5193), .Y(n5231) );
XOR2X4TS U4168 ( .A(n487), .B(n5203), .Y(n6692) );
OAI21X2TS U4169 ( .A0(n5447), .A1(n5201), .B0(n5200), .Y(n487) );
NOR2X8TS U4170 ( .A(n491), .B(n488), .Y(n7194) );
OAI21X1TS U4171 ( .A0(n498), .A1(n6794), .B0(n6793), .Y(n6795) );
OAI21X1TS U4172 ( .A0(n498), .A1(n6539), .B0(n6538), .Y(n6540) );
NOR2BX2TS U4173 ( .AN(n5873), .B(n499), .Y(n5858) );
XOR2X1TS U4174 ( .A(n5873), .B(n500), .Y(n6012) );
OAI2BB1X1TS U4175 ( .A0N(n519), .A1N(n508), .B0(n6661), .Y(n6663) );
OAI21X1TS U4176 ( .A0(n6740), .A1(n5318), .B0(n6739), .Y(n6741) );
OAI2BB1X1TS U4177 ( .A0N(n519), .A1N(n511), .B0(n6618), .Y(n6620) );
INVX2TS U4178 ( .A(n937), .Y(n520) );
AOI21X4TS U4179 ( .A0(n1056), .A1(n530), .B0(n528), .Y(n670) );
OAI21X4TS U4180 ( .A0(n1090), .A1(n532), .B0(n529), .Y(n528) );
AOI21X4TS U4181 ( .A0(n1389), .A1(n1023), .B0(n1022), .Y(n1090) );
NOR2BX4TS U4182 ( .AN(n531), .B(n1089), .Y(n530) );
INVX2TS U4183 ( .A(n532), .Y(n531) );
OAI21X4TS U4184 ( .A0(n1121), .A1(n535), .B0(n534), .Y(n1056) );
AOI21X4TS U4185 ( .A0(n911), .A1(n1021), .B0(n1020), .Y(n534) );
AOI21X4TS U4186 ( .A0(n1839), .A1(n537), .B0(n536), .Y(n1121) );
OAI21X4TS U4187 ( .A0(n1845), .A1(n1842), .B0(n1846), .Y(n536) );
OAI21X4TS U4188 ( .A0(n1880), .A1(n1883), .B0(n1882), .Y(n1839) );
XOR2X4TS U4189 ( .A(n543), .B(n668), .Y(n542) );
XNOR2X4TS U4190 ( .A(n545), .B(n1222), .Y(n1223) );
XNOR2X4TS U4191 ( .A(n5502), .B(n5400), .Y(n6712) );
OA21X4TS U4192 ( .A0(n5502), .A1(n5465), .B0(n5464), .Y(n7036) );
NAND2X4TS U4193 ( .A(n3133), .B(n3132), .Y(n7864) );
OAI2BB1X2TS U4194 ( .A0N(n573), .A1N(n572), .B0(n6846), .Y(n571) );
OAI2BB1X4TS U4195 ( .A0N(n6599), .A1N(n6598), .B0(n6597), .Y(n572) );
XOR2X4TS U4196 ( .A(n6989), .B(Data_A_i[52]), .Y(n583) );
XNOR2X4TS U4197 ( .A(n587), .B(n957), .Y(n671) );
NAND2X2TS U4198 ( .A(n2334), .B(n2333), .Y(n7901) );
XNOR2X4TS U4199 ( .A(n596), .B(n1938), .Y(n595) );
NOR2X8TS U4200 ( .A(n623), .B(n7735), .Y(n3161) );
XNOR2X4TS U4201 ( .A(n5159), .B(n863), .Y(n1494) );
XOR2X4TS U4202 ( .A(n607), .B(n1357), .Y(n863) );
XOR2X4TS U4203 ( .A(n608), .B(n205), .Y(n5159) );
AOI2BB1X4TS U4204 ( .A0N(n7154), .A1N(n618), .B0(n617), .Y(n616) );
AOI21X4TS U4205 ( .A0(n3161), .A1(n7717), .B0(n621), .Y(n7709) );
OAI21X4TS U4206 ( .A0(n623), .A1(n7736), .B0(n622), .Y(n621) );
AOI2BB1X4TS U4207 ( .A0N(n7730), .A1N(n3160), .B0(n7721), .Y(n622) );
AOI21X4TS U4208 ( .A0(n7155), .A1(n3174), .B0(n3173), .Y(n624) );
XNOR2X4TS U4209 ( .A(n631), .B(n1211), .Y(n630) );
XOR2X4TS U4210 ( .A(n632), .B(n634), .Y(n2786) );
XOR2X4TS U4211 ( .A(n890), .B(n2823), .Y(n634) );
XOR2X4TS U4212 ( .A(n2791), .B(n2792), .Y(n632) );
OAI21X1TS U4213 ( .A0(n2791), .A1(n2792), .B0(n634), .Y(n633) );
XOR2X4TS U4214 ( .A(n636), .B(n2681), .Y(n2719) );
NAND2X1TS U4215 ( .A(n2944), .B(n639), .Y(n638) );
CLKINVX1TS U4216 ( .A(n640), .Y(n1854) );
OAI21X4TS U4217 ( .A0(n1850), .A1(n640), .B0(n1851), .Y(n1332) );
OAI21X1TS U4218 ( .A0(n315), .A1(n7729), .B0(n7728), .Y(n7732) );
OAI21X1TS U4219 ( .A0(n217), .A1(n7720), .B0(n7719), .Y(n7725) );
XOR2XLTS U4220 ( .A(n315), .B(n7861), .Y(GEN1_middle_N38) );
XOR2X4TS U4221 ( .A(n1246), .B(n655), .Y(n1858) );
XOR2X4TS U4222 ( .A(n642), .B(n962), .Y(n655) );
XOR2X4TS U4223 ( .A(n646), .B(n1195), .Y(n1246) );
OAI22X1TS U4224 ( .A0(n1633), .A1(n344), .B0(n2030), .B1(n2014), .Y(n1709)
);
OAI22X1TS U4225 ( .A0(n2030), .A1(n1990), .B0(n345), .B1(n2019), .Y(n2022)
);
NAND2BX2TS U4226 ( .AN(n1633), .B(n650), .Y(n648) );
XOR2X4TS U4227 ( .A(n2423), .B(n656), .Y(n659) );
XOR2X4TS U4228 ( .A(n663), .B(n657), .Y(n2534) );
XOR2X4TS U4229 ( .A(n2426), .B(n661), .Y(n657) );
XOR2X4TS U4230 ( .A(n662), .B(n2418), .Y(n661) );
XNOR2X4TS U4231 ( .A(n2419), .B(n2417), .Y(n662) );
XOR2X4TS U4232 ( .A(n666), .B(n1030), .Y(n665) );
OAI22X4TS U4233 ( .A0(n908), .A1(n2222), .B0(n2561), .B1(n825), .Y(n1945) );
XOR2X4TS U4234 ( .A(n2961), .B(n227), .Y(n825) );
XOR2X4TS U4235 ( .A(n677), .B(n166), .Y(n2909) );
OAI2BB1X4TS U4236 ( .A0N(n2425), .A1N(n2424), .B0(n679), .Y(n2527) );
XOR2X4TS U4237 ( .A(n683), .B(n2742), .Y(n2784) );
XOR2X4TS U4238 ( .A(n2741), .B(n2743), .Y(n683) );
XOR2X4TS U4239 ( .A(n684), .B(n988), .Y(n2838) );
OAI21X1TS U4240 ( .A0(n2177), .A1(n2175), .B0(n2176), .Y(n685) );
OAI21X2TS U4241 ( .A0(n920), .A1(n688), .B0(n686), .Y(n7777) );
INVX2TS U4242 ( .A(n7927), .Y(n687) );
NAND2X2TS U4243 ( .A(n115), .B(n7928), .Y(n688) );
NAND2X2TS U4244 ( .A(n162), .B(n7937), .Y(n692) );
XOR2X4TS U4245 ( .A(n693), .B(n167), .Y(n2865) );
OAI21X4TS U4246 ( .A0(n362), .A1(n1384), .B0(n1383), .Y(n693) );
XOR2X2TS U4247 ( .A(n260), .B(n2961), .Y(n2184) );
XOR2X4TS U4248 ( .A(n362), .B(n1229), .Y(n2815) );
XOR2X4TS U4249 ( .A(n695), .B(n3105), .Y(n3139) );
XOR2X4TS U4250 ( .A(n696), .B(n3106), .Y(n695) );
XOR2X4TS U4251 ( .A(n954), .B(n3094), .Y(n696) );
XNOR2X4TS U4252 ( .A(n697), .B(n1395), .Y(n2813) );
OAI21X4TS U4253 ( .A0(n1392), .A1(n1391), .B0(n1390), .Y(n697) );
INVX2TS U4254 ( .A(n702), .Y(n700) );
XOR2X4TS U4255 ( .A(n2512), .B(n701), .Y(n2528) );
XNOR2X4TS U4256 ( .A(n706), .B(n1055), .Y(n705) );
OAI21X4TS U4257 ( .A0(n1181), .A1(n1328), .B0(n1182), .Y(n1172) );
NAND2X2TS U4258 ( .A(Data_A_i[32]), .B(Data_A_i[5]), .Y(n1182) );
XOR2X4TS U4259 ( .A(n710), .B(n2770), .Y(n2780) );
XOR2X4TS U4260 ( .A(n2771), .B(n2772), .Y(n710) );
NOR2BX1TS U4261 ( .AN(n1321), .B(n1316), .Y(n716) );
XOR2X4TS U4262 ( .A(n723), .B(n1322), .Y(n712) );
XOR2X4TS U4263 ( .A(n721), .B(n1078), .Y(n713) );
OAI21X2TS U4264 ( .A0(n1074), .A1(n1073), .B0(n1072), .Y(n721) );
XOR2X4TS U4265 ( .A(n2494), .B(n2495), .Y(n725) );
AOI222X1TS U4266 ( .A0(n4426), .A1(n4442), .B0(n3552), .B1(n4663), .C0(n3898), .C1(n4292), .Y(n3757) );
OAI21X1TS U4267 ( .A0(n4541), .A1(n3779), .B0(n977), .Y(n3556) );
ADDFHX2TS U4268 ( .A(n3603), .B(n3602), .CI(n3601), .CO(n3713), .S(n3712) );
OAI22X2TS U4269 ( .A0(n232), .A1(n2433), .B0(n2869), .B1(n2445), .Y(n2497)
);
ADDFHX2TS U4270 ( .A(n2153), .B(n2152), .CI(n2151), .CO(n2136), .S(n2154) );
AOI21X2TS U4271 ( .A0(n7777), .A1(n2328), .B0(n2327), .Y(n7774) );
BUFX8TS U4272 ( .A(n2941), .Y(n2030) );
ADDFHX2TS U4273 ( .A(n1779), .B(n1778), .CI(n1777), .CO(n3168), .S(n3165) );
NAND2X2TS U4274 ( .A(n2332), .B(n2331), .Y(n7916) );
CLKINVX6TS U4275 ( .A(n1906), .Y(n1666) );
ADDFHX2TS U4276 ( .A(n1756), .B(n1755), .CI(n1754), .CO(n1762), .S(n1775) );
XNOR2X4TS U4277 ( .A(n1337), .B(n1336), .Y(n1869) );
ADDFHX2TS U4278 ( .A(n3957), .B(n3956), .CI(n3955), .CO(n3963), .S(n3962) );
ADDFHX2TS U4279 ( .A(n3905), .B(n3904), .CI(n3903), .CO(n3889), .S(n3934) );
ADDFHX2TS U4280 ( .A(n6066), .B(n6065), .CI(n6064), .CO(n6153), .S(n6147) );
OAI21X2TS U4281 ( .A0(n7709), .A1(n6571), .B0(n6570), .Y(n7167) );
ADDFHX2TS U4282 ( .A(n1770), .B(n1769), .CI(n1768), .CO(n1760), .S(n1782) );
OAI22X2TS U4283 ( .A0(n1908), .A1(n2562), .B0(n1857), .B1(n7812), .Y(n1911)
);
ADDFHX2TS U4284 ( .A(n1485), .B(n1484), .CI(n1483), .CO(n3107), .S(n3090) );
ADDFHX4TS U4285 ( .A(n2528), .B(n2527), .CI(n2526), .CO(n2539), .S(n2536) );
OAI21X2TS U4286 ( .A0(n1392), .A1(n1089), .B0(n1090), .Y(n1068) );
ADDFHX2TS U4287 ( .A(n3922), .B(n3921), .CI(n3920), .CO(n4208), .S(n3924) );
ADDFHX2TS U4288 ( .A(n4573), .B(n4572), .CI(n4571), .CO(n4586), .S(n4585) );
ADDFHX2TS U4289 ( .A(n1837), .B(n1836), .CI(n1835), .CO(n3188), .S(n1821) );
OA21X2TS U4290 ( .A0(n7709), .A1(n7667), .B0(n7666), .Y(n989) );
XNOR2X4TS U4291 ( .A(n1854), .B(n1853), .Y(n1867) );
OAI21X2TS U4292 ( .A0(n2519), .A1(n2520), .B0(n2518), .Y(n726) );
XOR2X4TS U4293 ( .A(n727), .B(n2518), .Y(n2526) );
XOR2X4TS U4294 ( .A(n729), .B(n2430), .Y(n2507) );
NAND2X4TS U4295 ( .A(Data_A_i[28]), .B(Data_A_i[1]), .Y(n1851) );
NOR2X8TS U4296 ( .A(Data_A_i[28]), .B(Data_A_i[1]), .Y(n1850) );
XOR2X4TS U4297 ( .A(n742), .B(n3052), .Y(n813) );
XOR2X4TS U4298 ( .A(n3053), .B(n3051), .Y(n742) );
XOR2X4TS U4299 ( .A(n744), .B(n3047), .Y(n3053) );
XOR2X4TS U4300 ( .A(n746), .B(n2917), .Y(n2923) );
NAND2BX4TS U4301 ( .AN(n3165), .B(n770), .Y(n7706) );
XNOR2X4TS U4302 ( .A(n765), .B(n1011), .Y(n1086) );
OAI21X4TS U4303 ( .A0(n704), .A1(n1009), .B0(n1008), .Y(n765) );
XNOR2X4TS U4304 ( .A(n747), .B(n766), .Y(n751) );
OAI21X4TS U4305 ( .A0(n7859), .A1(n7740), .B0(n7741), .Y(n7717) );
XNOR2X4TS U4306 ( .A(n1224), .B(n1308), .Y(n2399) );
OA21X4TS U4307 ( .A0(n783), .A1(n1073), .B0(n782), .Y(n781) );
XOR2X4TS U4308 ( .A(n1112), .B(n168), .Y(n2795) );
OA21X2TS U4309 ( .A0(n4625), .A1(n4695), .B0(n3757), .Y(n786) );
NOR2BX4TS U4310 ( .AN(n790), .B(n4212), .Y(n7562) );
XNOR2X4TS U4311 ( .A(n791), .B(n4193), .Y(n4213) );
XOR2X4TS U4312 ( .A(n4194), .B(n4192), .Y(n791) );
NOR2X2TS U4313 ( .A(n7310), .B(n7247), .Y(n7325) );
NOR2BX1TS U4314 ( .AN(n795), .B(n6154), .Y(n7247) );
XOR2X4TS U4315 ( .A(n799), .B(n4074), .Y(n5065) );
AO21X4TS U4316 ( .A0(n3221), .A1(n3241), .B0(n3220), .Y(n798) );
NOR2X8TS U4317 ( .A(n7823), .B(n7747), .Y(n7830) );
OAI2BB1X4TS U4318 ( .A0N(n3112), .A1N(n3111), .B0(n806), .Y(n3125) );
OAI21X4TS U4319 ( .A0(n1079), .A1(n1040), .B0(n810), .Y(n1351) );
XOR2X4TS U4320 ( .A(n2920), .B(n3054), .Y(n815) );
AOI21X1TS U4321 ( .A0(n820), .A1(n7485), .B0(n7473), .Y(n7474) );
XOR2X4TS U4322 ( .A(n822), .B(n1661), .Y(n3154) );
OAI22X4TS U4323 ( .A0(n1908), .A1(n7812), .B0(n2562), .B1(n825), .Y(n1933)
);
XNOR2X4TS U4324 ( .A(n816), .B(n828), .Y(n827) );
XOR2X4TS U4325 ( .A(n3198), .B(n828), .Y(n2863) );
XOR2X4TS U4326 ( .A(n829), .B(n169), .Y(n828) );
OAI21X2TS U4327 ( .A0(n704), .A1(n1044), .B0(n1043), .Y(n829) );
OAI2BB1X4TS U4328 ( .A0N(n1607), .A1N(n1608), .B0(n830), .Y(n1653) );
XOR2X4TS U4329 ( .A(n831), .B(n1608), .Y(n1625) );
XNOR2X4TS U4330 ( .A(n308), .B(n3415), .Y(n4718) );
AND2X4TS U4331 ( .A(n4900), .B(n4901), .Y(n5050) );
XOR2X4TS U4332 ( .A(n838), .B(Data_A_i[42]), .Y(n5359) );
XOR2X4TS U4333 ( .A(n840), .B(n3880), .Y(n4826) );
INVX2TS U4334 ( .A(n841), .Y(n7757) );
NAND2X1TS U4335 ( .A(n7766), .B(n841), .Y(n7767) );
OA21X4TS U4336 ( .A0(n2543), .A1(n841), .B0(n7761), .Y(n2544) );
XNOR2X4TS U4337 ( .A(n842), .B(n1226), .Y(n1227) );
XNOR2X4TS U4338 ( .A(n843), .B(n1241), .Y(n2483) );
OAI21X4TS U4339 ( .A0(n1016), .A1(n1305), .B0(n1017), .Y(n1037) );
INVX2TS U4340 ( .A(n855), .Y(n853) );
XOR2X4TS U4341 ( .A(n2673), .B(n854), .Y(n2739) );
OAI2BB1X4TS U4342 ( .A0N(n1536), .A1N(n1535), .B0(n857), .Y(n1659) );
OAI21X4TS U4343 ( .A0(n1536), .A1(n1535), .B0(n1534), .Y(n857) );
XNOR2X4TS U4344 ( .A(n3090), .B(n860), .Y(n3130) );
INVX2TS U4345 ( .A(n2212), .Y(n2441) );
XOR2X4TS U4346 ( .A(n2212), .B(n1148), .Y(n2906) );
XOR2X4TS U4347 ( .A(n1284), .B(n1140), .Y(n1148) );
XOR2X4TS U4348 ( .A(n865), .B(n976), .Y(n2212) );
NAND2BX4TS U4349 ( .AN(n2543), .B(n7766), .Y(n2545) );
XOR2X1TS U4350 ( .A(n5218), .B(n5189), .Y(n990) );
INVX2TS U4351 ( .A(Data_B_i[28]), .Y(n864) );
XOR2X4TS U4352 ( .A(n2777), .B(n2778), .Y(n2514) );
OAI2BB1X4TS U4353 ( .A0N(n2521), .A1N(n2522), .B0(n873), .Y(n2777) );
XOR2X4TS U4354 ( .A(n876), .B(n3366), .Y(n4820) );
XOR2X4TS U4355 ( .A(n881), .B(n4091), .Y(n5084) );
XOR2X4TS U4356 ( .A(n884), .B(n5370), .Y(n6662) );
OAI2BB1X4TS U4357 ( .A0N(n2825), .A1N(n2824), .B0(n887), .Y(n2922) );
XOR2X4TS U4358 ( .A(n2747), .B(n898), .Y(n2768) );
OAI21X4TS U4359 ( .A0(n7745), .A1(n3146), .B0(n899), .Y(n3147) );
NOR2X4TS U4360 ( .A(n3145), .B(n3144), .Y(n7179) );
OAI21X4TS U4361 ( .A0(n2852), .A1(n133), .B0(n2851), .Y(n901) );
XOR2XLTS U4362 ( .A(n7092), .B(n183), .Y(GEN1_left_N44) );
XOR2XLTS U4363 ( .A(n7099), .B(n185), .Y(GEN1_left_N47) );
XOR2XLTS U4364 ( .A(n7106), .B(n186), .Y(GEN1_left_N45) );
XOR2XLTS U4365 ( .A(n7111), .B(n187), .Y(GEN1_left_N39) );
XNOR2X4TS U4366 ( .A(n906), .B(n6249), .Y(n6259) );
XNOR2X4TS U4367 ( .A(n6250), .B(n6251), .Y(n906) );
OAI21X2TS U4368 ( .A0(n4221), .A1(n910), .B0(n4220), .Y(n7435) );
AOI21X4TS U4369 ( .A0(n1363), .A1(n1122), .B0(n911), .Y(n1127) );
OAI21X4TS U4370 ( .A0(n1364), .A1(n1360), .B0(n1365), .Y(n911) );
NAND2X1TS U4371 ( .A(n3712), .B(n3711), .Y(n7617) );
NAND2BX4TS U4372 ( .AN(n913), .B(n3710), .Y(n7613) );
XOR2X4TS U4373 ( .A(n4297), .B(n917), .Y(n916) );
NOR2X8TS U4374 ( .A(Data_A_i[30]), .B(Data_A_i[3]), .Y(n1333) );
CLKINVX1TS U4375 ( .A(n920), .Y(n7926) );
NAND2BX4TS U4376 ( .AN(n3167), .B(n921), .Y(n7697) );
INVX2TS U4377 ( .A(n3168), .Y(n921) );
NOR2X4TS U4378 ( .A(n3170), .B(n3169), .Y(n7153) );
XNOR2X4TS U4379 ( .A(n923), .B(n1969), .Y(n1970) );
OAI22X1TS U4380 ( .A0(n1876), .A1(n1877), .B0(n2361), .B1(n925), .Y(n1887)
);
XNOR2X2TS U4381 ( .A(n244), .B(n2897), .Y(n925) );
OAI2BB1X4TS U4382 ( .A0N(n1728), .A1N(n1727), .B0(n926), .Y(n1747) );
XOR2X4TS U4383 ( .A(n586), .B(n1104), .Y(n2848) );
OAI21X4TS U4384 ( .A0(n1333), .A1(n1863), .B0(n1334), .Y(n994) );
CLKINVX1TS U4385 ( .A(n932), .Y(n7848) );
AOI21X1TS U4386 ( .A0(n7851), .A1(n932), .B0(n7839), .Y(n7840) );
CLKINVX1TS U4387 ( .A(n933), .Y(n7326) );
XNOR2X4TS U4388 ( .A(n935), .B(n2832), .Y(n2827) );
XNOR2X4TS U4389 ( .A(n2833), .B(n2834), .Y(n935) );
NAND2X1TS U4390 ( .A(n6031), .B(n6030), .Y(n7362) );
XOR2X4TS U4391 ( .A(n6274), .B(Data_A_i[31]), .Y(n942) );
OAI22X1TS U4392 ( .A0(n2578), .A1(n2811), .B0(n5182), .B1(n2579), .Y(n952)
);
OAI2BB1X4TS U4393 ( .A0N(n3095), .A1N(n3094), .B0(n953), .Y(n3129) );
XOR2X4TS U4394 ( .A(n3095), .B(n3093), .Y(n954) );
XNOR2X4TS U4395 ( .A(n1163), .B(n984), .Y(n955) );
ADDFHX2TS U4396 ( .A(n1632), .B(n1631), .CI(n1630), .CO(n1753), .S(n1640) );
XOR2X2TS U4397 ( .A(n5384), .B(n5383), .Y(n6486) );
ADDFHX2TS U4398 ( .A(n3885), .B(n3884), .CI(n3883), .CO(n4178), .S(n3849) );
ADDFHX2TS U4399 ( .A(n3374), .B(n3373), .CI(n3372), .CO(n3951), .S(n3455) );
OAI21XLTS U4400 ( .A0(n6383), .A1(n6004), .B0(n5841), .Y(n5842) );
ADDFHX2TS U4401 ( .A(n4165), .B(n4164), .CI(n4163), .CO(n4160), .S(n4197) );
ADDFHX2TS U4402 ( .A(n3109), .B(n3108), .CI(n3107), .CO(n1504), .S(n3124) );
ADDFHX2TS U4403 ( .A(n1479), .B(n1478), .CI(n1477), .CO(n3109), .S(n3091) );
ADDFHX2TS U4404 ( .A(n1482), .B(n1481), .CI(n1480), .CO(n1526), .S(n3108) );
ADDFHX2TS U4405 ( .A(n5669), .B(n5668), .CI(n5667), .CO(n5641), .S(n6064) );
OAI21X2TS U4406 ( .A0(n6949), .A1(n5913), .B0(n5524), .Y(n5525) );
NOR2X2TS U4407 ( .A(n7660), .B(n7662), .Y(n7665) );
ADDFHX2TS U4408 ( .A(n4699), .B(n4698), .CI(n4697), .CO(n4728), .S(n4670) );
AOI21X2TS U4409 ( .A0(n7532), .A1(n3708), .B0(n3707), .Y(n7529) );
NOR2X4TS U4410 ( .A(n5279), .B(n5278), .Y(n6850) );
ADDFHX2TS U4411 ( .A(n1743), .B(n1742), .CI(n1741), .CO(n1787), .S(n1730) );
OAI22X2TS U4412 ( .A0(n312), .A1(n1678), .B0(n2972), .B1(n1906), .Y(n1742)
);
XNOR2X4TS U4413 ( .A(n1245), .B(n1244), .Y(n2452) );
ADDFHX2TS U4414 ( .A(n6439), .B(n6438), .CI(n6437), .CO(n6452), .S(n6451) );
OAI22X1TS U4415 ( .A0(n3000), .A1(n1522), .B0(n2587), .B1(n1550), .Y(n1544)
);
ADDFHX2TS U4416 ( .A(n2187), .B(n2186), .CI(n2185), .CO(n2173), .S(n2188) );
ADDFHX2TS U4417 ( .A(n6409), .B(n6408), .CI(n6407), .CO(n6489), .S(n6434) );
ADDFHX2TS U4418 ( .A(n3018), .B(n3017), .CI(n3016), .CO(n3071), .S(n3065) );
CMPR22X2TS U4419 ( .A(n3563), .B(n3562), .CO(n3559), .S(n3587) );
CMPR22X2TS U4420 ( .A(n3579), .B(n3578), .CO(n3563), .S(n3693) );
OAI21XLTS U4421 ( .A0(n6662), .A1(n6273), .B0(n5749), .Y(n5750) );
OAI21XLTS U4422 ( .A0(n6662), .A1(n6401), .B0(n5721), .Y(n5722) );
OAI21XLTS U4423 ( .A0(n6662), .A1(n6707), .B0(n5371), .Y(n5372) );
OAI21XLTS U4424 ( .A0(n6662), .A1(n6623), .B0(n5586), .Y(n5587) );
OAI21XLTS U4425 ( .A0(n6662), .A1(n337), .B0(n6340), .Y(n6341) );
OAI21XLTS U4426 ( .A0(n6662), .A1(n6828), .B0(n6199), .Y(n6200) );
ADDFHX2TS U4427 ( .A(n2190), .B(n2189), .CI(n2188), .CO(n2293), .S(n2292) );
ADDFHX2TS U4428 ( .A(n1782), .B(n1781), .CI(n1780), .CO(n3164), .S(n3163) );
ADDFHX4TS U4429 ( .A(n1773), .B(n1772), .CI(n1771), .CO(n1781), .S(n1766) );
ADDFHX2TS U4430 ( .A(n4377), .B(n4376), .CI(n4375), .CO(n4501), .S(n4361) );
ADDFHX2TS U4431 ( .A(n1620), .B(n1619), .CI(n1618), .CO(n1627), .S(n1622) );
ADDFHX2TS U4432 ( .A(n2058), .B(n2057), .CI(n2056), .CO(n2035), .S(n2305) );
ADDFHX2TS U4433 ( .A(n2662), .B(n2661), .CI(n2660), .CO(n2658), .S(n2740) );
ADDFHX2TS U4434 ( .A(n1518), .B(n1517), .CI(n1516), .CO(n1542), .S(n1490) );
ADDHX1TS U4435 ( .A(n1946), .B(n1945), .CO(n1950), .S(n1978) );
ADDFHX2TS U4436 ( .A(n2769), .B(n2768), .CI(n2767), .CO(n2770), .S(n2773) );
OAI22X2TS U4437 ( .A0(n3199), .A1(n2588), .B0(n2587), .B1(n2816), .Y(n2802)
);
XOR2X4TS U4438 ( .A(Data_A_i[44]), .B(Data_A_i[43]), .Y(n5360) );
ADDFHX2TS U4439 ( .A(n1462), .B(n1461), .CI(n1460), .CO(n1505), .S(n3115) );
OAI21XLTS U4440 ( .A0(n4278), .A1(n3901), .B0(n3500), .Y(n3501) );
OAI21XLTS U4441 ( .A0(n4278), .A1(n3581), .B0(n3538), .Y(n3539) );
OAI21XLTS U4442 ( .A0(n4278), .A1(n330), .B0(n3299), .Y(n3300) );
OAI21XLTS U4443 ( .A0(n4278), .A1(n4269), .B0(n3755), .Y(n3756) );
ADDFHX2TS U4444 ( .A(n2705), .B(n2704), .CI(n2703), .CO(n2836), .S(n2706) );
ADDFHX2TS U4445 ( .A(n4082), .B(n4081), .CI(n4080), .CO(n4032), .S(n4121) );
XNOR2X4TS U4446 ( .A(Data_A_i[44]), .B(Data_A_i[45]), .Y(n5278) );
ADDFHX2TS U4447 ( .A(n2416), .B(n2415), .CI(n2414), .CO(n2513), .S(n2417) );
ADDFHX2TS U4448 ( .A(n1714), .B(n1713), .CI(n1712), .CO(n1754), .S(n1757) );
ADDFHX2TS U4449 ( .A(n2729), .B(n2728), .CI(n2727), .CO(n2750), .S(n2755) );
ADDFHX2TS U4450 ( .A(n1568), .B(n1567), .CI(n1566), .CO(n1626), .S(n1595) );
ADDFHX2TS U4451 ( .A(n1545), .B(n1544), .CI(n1543), .CO(n1567), .S(n1537) );
ADDFHX2TS U4452 ( .A(n1533), .B(n1532), .CI(n1531), .CO(n1660), .S(n1530) );
ADDFHX2TS U4453 ( .A(n1562), .B(n1561), .CI(n1560), .CO(n1563), .S(n1532) );
ADDFHX2TS U4454 ( .A(n2112), .B(n2111), .CI(n2110), .CO(n2119), .S(n2135) );
NOR2X2TS U4455 ( .A(n3325), .B(n3327), .Y(n3211) );
NOR2X2TS U4456 ( .A(n4301), .B(Data_B_i[5]), .Y(n3325) );
ADDFHX2TS U4457 ( .A(n2632), .B(n2631), .CI(n2630), .CO(n2685), .S(n2628) );
ADDFHX2TS U4458 ( .A(n6350), .B(n6349), .CI(n6348), .CO(n6446), .S(n6445) );
XOR2X4TS U4459 ( .A(n3429), .B(n3428), .Y(n4797) );
ADDFHX2TS U4460 ( .A(n4088), .B(n4087), .CI(n4086), .CO(n4333), .S(n4084) );
ADDFHX2TS U4461 ( .A(n1646), .B(n1645), .CI(n1644), .CO(n1758), .S(n1629) );
ADDFHX2TS U4462 ( .A(n1912), .B(n1911), .CI(n1910), .CO(n1918), .S(n1938) );
OAI21X2TS U4463 ( .A0(n5502), .A1(n5250), .B0(n5249), .Y(n5251) );
ADDFHX2TS U4464 ( .A(n1311), .B(n1310), .CI(n1309), .CO(n1461), .S(n3098) );
ADDFHX2TS U4465 ( .A(n3086), .B(n3085), .CI(n3084), .CO(n3099), .S(n3072) );
ADDFHX2TS U4466 ( .A(n2343), .B(n2342), .CI(n2341), .CO(n2416), .S(n2411) );
OAI22X1TS U4467 ( .A0(n307), .A1(n2666), .B0(n734), .B1(n2573), .Y(n2676) );
ADDFHX2TS U4468 ( .A(n6801), .B(n6800), .CI(n6799), .CO(n6822), .S(n6803) );
XOR2X4TS U4469 ( .A(Data_A_i[47]), .B(Data_A_i[46]), .Y(n5279) );
ADDFHX2TS U4470 ( .A(n3003), .B(n3002), .CI(n3001), .CO(n3013), .S(n2981) );
ADDFHX2TS U4471 ( .A(n2679), .B(n2678), .CI(n2677), .CO(n2713), .S(n2709) );
OAI2BB1X1TS U4472 ( .A0N(n2618), .A1N(n2617), .B0(n2558), .Y(n2677) );
ADDFHX2TS U4473 ( .A(n2659), .B(n2657), .CI(n2658), .CO(n2680), .S(n2746) );
NAND2X2TS U4474 ( .A(n2297), .B(n2296), .Y(n7932) );
ADDFHX2TS U4475 ( .A(n1980), .B(n1979), .CI(n1978), .CO(n1988), .S(n2016) );
XNOR2X1TS U4476 ( .A(n1296), .B(n2559), .Y(n2610) );
OAI21X2TS U4477 ( .A0(n1284), .A1(n1248), .B0(n1247), .Y(n1252) );
ADDFHX2TS U4478 ( .A(n3672), .B(n4272), .CI(n4271), .CO(n4317), .S(n4284) );
ADDFHX2TS U4479 ( .A(n4156), .B(n4155), .CI(n4154), .CO(n4161), .S(n4182) );
OAI22X2TS U4480 ( .A0(n3204), .A1(n2649), .B0(n3202), .B1(n2648), .Y(n2661)
);
XOR2X1TS U4481 ( .A(n2176), .B(n2175), .Y(n2178) );
ADDFHX2TS U4482 ( .A(n1915), .B(n1914), .CI(n1913), .CO(n2375), .S(n1965) );
ADDFHX2TS U4483 ( .A(n4255), .B(n4254), .CI(n4253), .CO(n4335), .S(n4332) );
ADDFHX2TS U4484 ( .A(n2307), .B(n2306), .CI(n2305), .CO(n2329), .S(n2326) );
ADDFHX2TS U4485 ( .A(n2316), .B(n2314), .CI(n2315), .CO(n2306), .S(n2317) );
NAND2X4TS U4486 ( .A(n1149), .B(n2906), .Y(n1453) );
NOR2XLTS U4487 ( .A(n7899), .B(n7902), .Y(n7905) );
ADDFHX2TS U4488 ( .A(n4459), .B(n4458), .CI(n4457), .CO(n4558), .S(n4507) );
ADDFHX2TS U4489 ( .A(n2803), .B(n2802), .CI(n2801), .CO(n2855), .S(n2820) );
NAND2X2TS U4490 ( .A(n3170), .B(n3169), .Y(n7688) );
ADDFHX2TS U4491 ( .A(n6359), .B(n6358), .CI(n6357), .CO(n6435), .S(n6394) );
ADDFHX2TS U4492 ( .A(n2970), .B(n2969), .CI(n2968), .CO(n3069), .S(n3085) );
ADDFHX2TS U4493 ( .A(n2133), .B(n2132), .CI(n2131), .CO(n2303), .S(n2302) );
CMPR22X2TS U4494 ( .A(n5615), .B(n5614), .CO(n5575), .S(n5657) );
ADDFHX2TS U4495 ( .A(n2458), .B(n2457), .CI(n2456), .CO(n2671), .S(n2468) );
OAI21XLTS U4496 ( .A0(n5473), .A1(n5472), .B0(n5471), .Y(n5478) );
ADDFHX2TS U4497 ( .A(n1410), .B(n1409), .CI(n1408), .CO(n1435), .S(n1479) );
NAND2X2TS U4498 ( .A(n6441), .B(n6440), .Y(n7243) );
ADDFHX2TS U4499 ( .A(n6257), .B(n6256), .CI(n6255), .CO(n6440), .S(n6160) );
ADDFHX2TS U4500 ( .A(n6260), .B(n6259), .CI(n6258), .CO(n6442), .S(n6441) );
ADDFHX2TS U4501 ( .A(n2645), .B(n2644), .CI(n2643), .CO(n2659), .S(n2724) );
OAI21X1TS U4502 ( .A0(n4665), .A1(n5108), .B0(n4664), .Y(n4666) );
CMPR22X2TS U4503 ( .A(n3532), .B(n3531), .CO(n3519), .S(n3597) );
ADDFHX2TS U4504 ( .A(n3083), .B(n3082), .CI(n3081), .CO(n3100), .S(n3073) );
ADDFHX2TS U4505 ( .A(n1413), .B(n1412), .CI(n1411), .CO(n1478), .S(n3068) );
ADDFHX2TS U4506 ( .A(n6461), .B(n6460), .CI(n6459), .CO(n6549), .S(n6488) );
ADDFHX2TS U4507 ( .A(n2916), .B(n2915), .CI(n2914), .CO(n3022), .S(n2918) );
OAI21XLTS U4508 ( .A0(n963), .A1(n4776), .B0(n3342), .Y(n3343) );
ADDFHX2TS U4509 ( .A(n2890), .B(n2888), .CI(n2889), .CO(n3046), .S(n2851) );
ADDFHX2TS U4510 ( .A(n2702), .B(n2701), .CI(n2700), .CO(n2707), .S(n2657) );
ADDFHX2TS U4511 ( .A(n2086), .B(n2085), .CI(n2084), .CO(n2117), .S(n2120) );
ADDFHX2TS U4512 ( .A(n2837), .B(n2836), .CI(n2835), .CO(n2889), .S(n2830) );
ADDFHX2TS U4513 ( .A(n2967), .B(n2965), .CI(n2966), .CO(n3078), .S(n3086) );
ADDFHX2TS U4514 ( .A(n1861), .B(n1860), .CI(n1859), .CO(n2382), .S(n1917) );
ADDFHX2TS U4515 ( .A(n1539), .B(n1538), .CI(n1537), .CO(n1596), .S(n1535) );
ADDFHX2TS U4516 ( .A(n2685), .B(n2684), .CI(n2683), .CO(n2828), .S(n2681) );
AOI21X2TS U4517 ( .A0(n1330), .A1(n1173), .B0(n1172), .Y(n1178) );
ADDFHX4TS U4518 ( .A(n1657), .B(n1656), .CI(n1655), .CO(n3159), .S(n3156) );
XOR2X1TS U4519 ( .A(n1611), .B(n1614), .Y(n1587) );
ADDFHX2TS U4520 ( .A(n1888), .B(n1887), .CI(n1886), .CO(n2413), .S(n1920) );
ADDFHX4TS U4521 ( .A(n3115), .B(n3114), .CI(n3113), .CO(n3121), .S(n3126) );
XNOR2X1TS U4522 ( .A(n2838), .B(n2897), .Y(n2687) );
ADDHX1TS U4523 ( .A(n2209), .B(n2208), .CO(n2215), .S(n2228) );
ADDFHX2TS U4524 ( .A(n1929), .B(n1928), .CI(n1927), .CO(n1921), .S(n1941) );
ADDFHX2TS U4525 ( .A(n2859), .B(n2857), .CI(n2858), .CO(n3036), .S(n2856) );
ADDFHX2TS U4526 ( .A(n2500), .B(n2501), .CI(n2499), .CO(n2736), .S(n2493) );
ADDFHX2TS U4527 ( .A(n2498), .B(n2497), .CI(n2496), .CO(n2737), .S(n2510) );
ADDFHX2TS U4528 ( .A(n2672), .B(n2671), .CI(n2670), .CO(n2738), .S(n2748) );
OAI22X2TS U4529 ( .A0(n324), .A1(n2607), .B0(n2687), .B1(n2927), .Y(n2584)
);
ADDFHX2TS U4530 ( .A(n6309), .B(n6308), .CI(n6307), .CO(n6444), .S(n6443) );
ADDFHX2TS U4531 ( .A(n2390), .B(n2389), .CI(n2388), .CO(n2520), .S(n2424) );
ADDFHX2TS U4532 ( .A(n2378), .B(n2377), .CI(n2376), .CO(n2390), .S(n2373) );
ADDFHX2TS U4533 ( .A(n2381), .B(n2380), .CI(n2379), .CO(n2469), .S(n2389) );
OAI22X1TS U4534 ( .A0(n2901), .A1(n2075), .B0(n2641), .B1(n2074), .Y(n2082)
);
ADDFHX2TS U4535 ( .A(n2606), .B(n2605), .CI(n2604), .CO(n2629), .S(n2725) );
ADDFHX2TS U4536 ( .A(n2477), .B(n2476), .CI(n2475), .CO(n2494), .S(n2508) );
ADDFHX2TS U4537 ( .A(n1799), .B(n1798), .CI(n1797), .CO(n1806), .S(n1786) );
OAI21XLTS U4538 ( .A0(n7903), .A1(n7902), .B0(n7901), .Y(n7904) );
ADDFHX2TS U4539 ( .A(n2511), .B(n2510), .CI(n2509), .CO(n2769), .S(n2522) );
ADDFHX2TS U4540 ( .A(n1949), .B(n1948), .CI(n1947), .CO(n1942), .S(n1987) );
ADDFHX2TS U4541 ( .A(n2893), .B(n2892), .CI(n2891), .CO(n3024), .S(n2888) );
ADDFHX2TS U4542 ( .A(n3080), .B(n3079), .CI(n3078), .CO(n3097), .S(n3101) );
XNOR2X1TS U4543 ( .A(n2027), .B(n2182), .Y(n1983) );
ADDFHX2TS U4544 ( .A(n2410), .B(n2409), .CI(n2408), .CO(n2506), .S(n2419) );
BUFX12TS U4545 ( .A(n1246), .Y(n2066) );
XNOR2X2TS U4546 ( .A(n1100), .B(n1099), .Y(n1976) );
ADDFHX2TS U4547 ( .A(n3043), .B(n3042), .CI(n3041), .CO(n3058), .S(n3051) );
ADDFHX2TS U4548 ( .A(n3033), .B(n3032), .CI(n3031), .CO(n3043), .S(n3028) );
ADDFHX2TS U4549 ( .A(n2752), .B(n2751), .CI(n2750), .CO(n2757), .S(n2765) );
OAI22X1TS U4550 ( .A0(n732), .A1(n1669), .B0(n130), .B1(n1679), .Y(n1675) );
NAND2X2TS U4551 ( .A(n3153), .B(n3152), .Y(n7741) );
OR2X1TS U4552 ( .A(n4026), .B(n3982), .Y(n958) );
AND2X2TS U4553 ( .A(n7181), .B(n7180), .Y(n959) );
AOI22X1TS U4554 ( .A0(n6946), .A1(n5910), .B0(n6893), .B1(n288), .Y(n960) );
AOI22X1TS U4555 ( .A0(n339), .A1(n5910), .B0(n6818), .B1(n288), .Y(n961) );
AND2X2TS U4556 ( .A(n1196), .B(n1200), .Y(n962) );
XOR2X1TS U4557 ( .A(n3341), .B(n3340), .Y(n963) );
AOI22X1TS U4558 ( .A0(n6676), .A1(n5910), .B0(n6609), .B1(n288), .Y(n964) );
AOI22X1TS U4559 ( .A0(n4065), .A1(n4026), .B0(n4075), .B1(n3985), .Y(n965)
);
NAND2X1TS U4560 ( .A(n4065), .B(n3978), .Y(n966) );
AOI22X1TS U4561 ( .A0(n6536), .A1(n5910), .B0(n6410), .B1(n288), .Y(n970) );
NAND2X1TS U4562 ( .A(n6410), .B(n5910), .Y(n972) );
AOI22X1TS U4563 ( .A0(n6360), .A1(n5910), .B0(n5746), .B1(n5984), .Y(n973)
);
NAND2X1TS U4564 ( .A(n3447), .B(n3978), .Y(n975) );
AND2X2TS U4565 ( .A(n1147), .B(n1146), .Y(n976) );
NAND2X1TS U4566 ( .A(n3553), .B(n3992), .Y(n977) );
NAND2X1TS U4567 ( .A(n2949), .B(n2948), .Y(n978) );
AOI22X1TS U4568 ( .A0(n6183), .A1(n5910), .B0(n6002), .B1(n5984), .Y(n979)
);
NAND2X1TS U4569 ( .A(n5840), .B(n5912), .Y(n980) );
AOI22X1TS U4570 ( .A0(n4976), .A1(n3992), .B0(n4018), .B1(n4026), .Y(n981)
);
AOI22X1TS U4571 ( .A0(n4538), .A1(n3992), .B0(n3553), .B1(n4026), .Y(n982)
);
NAND2X1TS U4572 ( .A(n4151), .B(n3978), .Y(n983) );
AND2X2TS U4573 ( .A(n1162), .B(n1165), .Y(n984) );
OR2X1TS U4574 ( .A(n5963), .B(n5962), .Y(n987) );
AND2X2TS U4575 ( .A(n1302), .B(n1301), .Y(n988) );
INVX2TS U4576 ( .A(n7154), .Y(n7692) );
XOR2X1TS U4577 ( .A(n5212), .B(n5211), .Y(n991) );
OR2X1TS U4578 ( .A(Data_B_i[27]), .B(n3978), .Y(n993) );
INVX2TS U4579 ( .A(n3863), .Y(n3874) );
INVX2TS U4580 ( .A(n5209), .Y(n5190) );
XNOR2X1TS U4581 ( .A(n2485), .B(n250), .Y(n2849) );
OAI21XLTS U4582 ( .A0(n990), .A1(n337), .B0(n5628), .Y(n5629) );
OAI21XLTS U4583 ( .A0(n991), .A1(n338), .B0(n5626), .Y(n5627) );
OAI21XLTS U4584 ( .A0(n991), .A1(n6962), .B0(n5521), .Y(n5522) );
OAI21XLTS U4585 ( .A0(n963), .A1(n5000), .B0(n3773), .Y(n3774) );
OAI21XLTS U4586 ( .A0(n3994), .A1(n5000), .B0(n981), .Y(n3777) );
OAI22X1TS U4587 ( .A0(n332), .A1(n1341), .B0(n1230), .B1(n2937), .Y(n1446)
);
XNOR2X1TS U4588 ( .A(n267), .B(n2559), .Y(n1889) );
XNOR2X1TS U4589 ( .A(n1223), .B(n2440), .Y(n1857) );
OAI22X1TS U4590 ( .A0(n5182), .A1(n1604), .B0(n2578), .B1(n1642), .Y(n1636)
);
OAI21XLTS U4591 ( .A0(n991), .A1(n6828), .B0(n5704), .Y(n5705) );
OAI21XLTS U4592 ( .A0(n991), .A1(n6707), .B0(n5775), .Y(n5776) );
OAI21XLTS U4593 ( .A0(n990), .A1(n6623), .B0(n5852), .Y(n5854) );
CLKBUFX2TS U4594 ( .A(n5523), .Y(n6962) );
NOR2X1TS U4595 ( .A(n3234), .B(n3279), .Y(n3295) );
OAI22X2TS U4596 ( .A0(n332), .A1(n1230), .B0(n2937), .B1(n2168), .Y(n1472)
);
OAI21XLTS U4597 ( .A0(n6619), .A1(n5980), .B0(n5834), .Y(n5835) );
NOR2XLTS U4598 ( .A(n5119), .B(n5131), .Y(n5095) );
OAI21XLTS U4599 ( .A0(n963), .A1(n4408), .B0(n3675), .Y(n3676) );
OAI22X1TS U4600 ( .A0(n2996), .A1(n1790), .B0(n734), .B1(n713), .Y(n1812) );
OAI2BB1X1TS U4601 ( .A0N(n2697), .A1N(n2696), .B0(n2571), .Y(n2837) );
ADDFHX2TS U4602 ( .A(n5819), .B(n5818), .CI(n5817), .CO(n5811), .S(n6044) );
NOR2XLTS U4603 ( .A(n781), .B(n671), .Y(n5145) );
NOR2XLTS U4604 ( .A(GEN1_Final_add_x_1_n381), .B(GEN1_Final_add_x_1_n378),
.Y(n7964) );
XOR2XLTS U4605 ( .A(n2178), .B(n2177), .Y(n2190) );
XOR3X1TS U4606 ( .A(n7677), .B(n7676), .C(n7675), .Y(n7678) );
OAI2BB1X1TS U4607 ( .A0N(n4191), .A1N(n4193), .B0(n4190), .Y(n4214) );
INVX2TS U4608 ( .A(GEN1_Final_add_x_1_n136), .Y(n8168) );
INVX2TS U4609 ( .A(GEN1_Final_add_x_1_n198), .Y(n8106) );
INVX2TS U4610 ( .A(GEN1_Final_add_x_1_n254), .Y(n8050) );
INVX2TS U4611 ( .A(GEN1_Final_add_x_1_n275), .Y(n8029) );
INVX2TS U4612 ( .A(GEN1_Final_add_x_1_n301), .Y(n8302) );
OAI21X1TS U4613 ( .A0(n7385), .A1(n7381), .B0(n7382), .Y(n7280) );
OAI21XLTS U4614 ( .A0(n8028), .A1(GEN1_Final_add_x_1_n278), .B0(
GEN1_Final_add_x_1_n279), .Y(n8031) );
OAI21XLTS U4615 ( .A0(n8224), .A1(GEN1_Final_add_x_1_n381), .B0(
GEN1_Final_add_x_1_n382), .Y(n8227) );
NOR2XLTS U4616 ( .A(n7643), .B(n7539), .Y(n3665) );
NOR2XLTS U4617 ( .A(n7873), .B(n7874), .Y(n7877) );
INVX2TS U4618 ( .A(rst), .Y(n7962) );
AOI21X1TS U4619 ( .A0(n3665), .A1(n7538), .B0(n3664), .Y(n7642) );
NOR2X8TS U4620 ( .A(Data_A_i[29]), .B(Data_A_i[2]), .Y(n1862) );
NAND2X2TS U4621 ( .A(Data_A_i[30]), .B(Data_A_i[3]), .Y(n1334) );
AOI21X4TS U4622 ( .A0(n1332), .A1(n995), .B0(n994), .Y(n1142) );
NOR2X4TS U4623 ( .A(Data_A_i[33]), .B(Data_A_i[6]), .Y(n1174) );
NOR2X4TS U4624 ( .A(Data_A_i[34]), .B(Data_A_i[7]), .Y(n1145) );
NOR2X4TS U4625 ( .A(n1174), .B(n1145), .Y(n997) );
NOR2X4TS U4626 ( .A(n1181), .B(n1179), .Y(n1173) );
NAND2X2TS U4627 ( .A(n997), .B(n1173), .Y(n999) );
NAND2X2TS U4628 ( .A(Data_A_i[33]), .B(Data_A_i[6]), .Y(n1175) );
OAI21X2TS U4629 ( .A0(n1145), .A1(n1175), .B0(n1146), .Y(n996) );
AOI21X4TS U4630 ( .A0(n1172), .A1(n997), .B0(n996), .Y(n998) );
OAI21X4TS U4631 ( .A0(n999), .A1(n1142), .B0(n998), .Y(n1137) );
NOR2X4TS U4632 ( .A(Data_A_i[35]), .B(Data_A_i[8]), .Y(n1138) );
NAND2X2TS U4633 ( .A(n1280), .B(n1001), .Y(n1248) );
NAND2X2TS U4634 ( .A(n1002), .B(n1197), .Y(n1004) );
NOR2X2TS U4635 ( .A(n1248), .B(n1004), .Y(n1006) );
NAND2X4TS U4636 ( .A(Data_A_i[35]), .B(Data_A_i[8]), .Y(n1139) );
NAND2X2TS U4637 ( .A(Data_A_i[36]), .B(Data_A_i[9]), .Y(n1134) );
AOI21X4TS U4638 ( .A0(n1001), .A1(n1281), .B0(n1000), .Y(n1247) );
OAI21X2TS U4639 ( .A0(n1247), .A1(n1004), .B0(n1003), .Y(n1005) );
AOI21X4TS U4640 ( .A0(n1137), .A1(n1006), .B0(n1005), .Y(n1073) );
NOR2X2TS U4641 ( .A(n1016), .B(n1304), .Y(n1032) );
INVX2TS U4642 ( .A(n1031), .Y(n1014) );
NAND2X1TS U4643 ( .A(n1032), .B(n1014), .Y(n1009) );
NAND2X4TS U4644 ( .A(Data_A_i[45]), .B(Data_A_i[18]), .Y(n1034) );
AOI21X1TS U4645 ( .A0(n1014), .A1(n1037), .B0(n1007), .Y(n1008) );
NAND2X1TS U4646 ( .A(n1014), .B(n1034), .Y(n1015) );
NAND2X2TS U4647 ( .A(Data_B_i[32]), .B(Data_B_i[5]), .Y(n1365) );
OAI21X2TS U4648 ( .A0(n1128), .A1(n1125), .B0(n1129), .Y(n1020) );
NAND2X2TS U4649 ( .A(n1388), .B(n1023), .Y(n1089) );
OAI21X4TS U4650 ( .A0(n1385), .A1(n1383), .B0(n1386), .Y(n1389) );
OAI21X2TS U4651 ( .A0(n1393), .A1(n1061), .B0(n1062), .Y(n1022) );
OAI21X2TS U4652 ( .A0(n1378), .A1(n1372), .B0(n1379), .Y(n1105) );
OAI21X1TS U4653 ( .A0(n1096), .A1(n1110), .B0(n1097), .Y(n1024) );
NOR2X2TS U4654 ( .A(Data_B_i[43]), .B(Data_B_i[16]), .Y(n1101) );
NAND2X2TS U4655 ( .A(Data_B_i[43]), .B(Data_B_i[16]), .Y(n1102) );
XNOR2X1TS U4656 ( .A(n1666), .B(n227), .Y(n1428) );
NOR2X2TS U4657 ( .A(Data_B_i[45]), .B(Data_B_i[18]), .Y(n1150) );
INVX2TS U4658 ( .A(n1150), .Y(n1215) );
NAND2X1TS U4659 ( .A(Data_B_i[45]), .B(Data_B_i[18]), .Y(n1213) );
NAND2X1TS U4660 ( .A(n1215), .B(n1213), .Y(n1030) );
XNOR2X1TS U4661 ( .A(n1666), .B(n267), .Y(n1464) );
OAI22X1TS U4662 ( .A0(n2446), .A1(n1428), .B0(n2444), .B1(n1464), .Y(n1459)
);
NOR2X2TS U4663 ( .A(n1070), .B(n1075), .Y(n1314) );
NOR2X2TS U4664 ( .A(n1052), .B(n1318), .Y(n1039) );
NAND2X2TS U4665 ( .A(n1314), .B(n1039), .Y(n1040) );
NAND2X2TS U4666 ( .A(n1032), .B(n1036), .Y(n1080) );
NAND2X1TS U4667 ( .A(n1347), .B(n1114), .Y(n1042) );
OAI21X1TS U4668 ( .A0(n1052), .A1(n1319), .B0(n1053), .Y(n1038) );
INVX2TS U4669 ( .A(n1045), .Y(n1117) );
NAND2X1TS U4670 ( .A(Data_A_i[52]), .B(Data_A_i[25]), .Y(n1115) );
INVX2TS U4671 ( .A(n1080), .Y(n1312) );
NAND2X1TS U4672 ( .A(n1049), .B(n1312), .Y(n1051) );
NAND2X1TS U4673 ( .A(n1054), .B(n1053), .Y(n1055) );
INVX2TS U4674 ( .A(n1057), .Y(n1394) );
NAND2X1TS U4675 ( .A(n1388), .B(n1394), .Y(n1060) );
CLKINVX1TS U4676 ( .A(n1393), .Y(n1058) );
AOI21X1TS U4677 ( .A0(n1389), .A1(n1394), .B0(n1058), .Y(n1059) );
NAND2X1TS U4678 ( .A(n1063), .B(n1062), .Y(n1064) );
XNOR2X1TS U4679 ( .A(n2862), .B(n248), .Y(n1431) );
INVX2TS U4680 ( .A(n1066), .Y(n1374) );
NAND2X1TS U4681 ( .A(n1374), .B(n1372), .Y(n1067) );
XNOR2X1TS U4682 ( .A(n2553), .B(n274), .Y(n1467) );
OAI22X1TS U4683 ( .A0(n224), .A1(n1431), .B0(n5149), .B1(n1467), .Y(n1458)
);
INVX2TS U4684 ( .A(n1070), .Y(n1082) );
NAND2X1TS U4685 ( .A(n1312), .B(n1082), .Y(n1074) );
AOI21X1TS U4686 ( .A0(n1315), .A1(n1082), .B0(n1071), .Y(n1072) );
INVX2TS U4687 ( .A(n1075), .Y(n1077) );
OAI21X4TS U4688 ( .A0(n704), .A1(n1080), .B0(n1079), .Y(n1084) );
NAND2X1TS U4689 ( .A(n1082), .B(n1081), .Y(n1083) );
XNOR2X4TS U4690 ( .A(n1084), .B(n1083), .Y(n1085) );
XNOR2X4TS U4691 ( .A(n1086), .B(n1085), .Y(n1816) );
INVX2TS U4692 ( .A(n1089), .Y(n1371) );
NAND2X1TS U4693 ( .A(n1093), .B(n1371), .Y(n1095) );
INVX2TS U4694 ( .A(n1090), .Y(n1375) );
OAI21X1TS U4695 ( .A0(n1091), .A1(n1109), .B0(n1110), .Y(n1092) );
AOI21X1TS U4696 ( .A0(n1375), .A1(n1093), .B0(n1092), .Y(n1094) );
NAND2X1TS U4697 ( .A(n1098), .B(n1097), .Y(n1099) );
XNOR2X1TS U4698 ( .A(n2395), .B(n251), .Y(n1113) );
BUFX3TS U4699 ( .A(n1816), .Y(n2547) );
CLKINVX1TS U4700 ( .A(n1101), .Y(n1103) );
XNOR2X1TS U4701 ( .A(n740), .B(n244), .Y(n1466) );
OAI22X1TS U4702 ( .A0(n732), .A1(n1113), .B0(n130), .B1(n1466), .Y(n1457) );
NAND2X1TS U4703 ( .A(n1371), .B(n1106), .Y(n1108) );
AOI21X1TS U4704 ( .A0(n1375), .A1(n1106), .B0(n1105), .Y(n1107) );
OAI21X1TS U4705 ( .A0(n1392), .A1(n1108), .B0(n1107), .Y(n1112) );
XNOR2X1TS U4706 ( .A(n740), .B(n366), .Y(n1404) );
OAI22X1TS U4707 ( .A0(n733), .A1(n1404), .B0(n130), .B1(n1113), .Y(n1311) );
NOR2X1TS U4708 ( .A(n1346), .B(n1354), .Y(n1120) );
AOI21X1TS U4709 ( .A0(n1118), .A1(n1117), .B0(n1116), .Y(n1348) );
OAI21X1TS U4710 ( .A0(n1348), .A1(n1354), .B0(n1355), .Y(n1119) );
NAND2X1TS U4711 ( .A(n1123), .B(n1125), .Y(n1124) );
NOR2X1TS U4712 ( .A(n7672), .B(n195), .Y(n1448) );
CLKINVX1TS U4713 ( .A(n1128), .Y(n1130) );
NOR2X1TS U4714 ( .A(n5180), .B(n159), .Y(n1447) );
INVX2TS U4715 ( .A(n1138), .Y(n1132) );
OAI2BB1X2TS U4716 ( .A0N(n1132), .A1N(n1137), .B0(n1139), .Y(n1136) );
CLKINVX1TS U4717 ( .A(n1133), .Y(n1135) );
XOR2X4TS U4718 ( .A(n1136), .B(n971), .Y(n1326) );
XOR2X4TS U4719 ( .A(n2905), .B(n1148), .Y(n1149) );
NOR2X1TS U4720 ( .A(n1141), .B(n1174), .Y(n1144) );
CLKINVX1TS U4721 ( .A(n1145), .Y(n1147) );
NOR2X2TS U4722 ( .A(Data_B_i[46]), .B(Data_B_i[19]), .Y(n1219) );
NAND2X2TS U4723 ( .A(n1212), .B(n1152), .Y(n1231) );
NOR2X1TS U4724 ( .A(n1269), .B(n1274), .Y(n1154) );
NAND2X1TS U4725 ( .A(n1302), .B(n1294), .Y(n1164) );
NAND2X1TS U4726 ( .A(n1297), .B(n1159), .Y(n1161) );
NAND2X1TS U4727 ( .A(Data_B_i[46]), .B(Data_B_i[19]), .Y(n1220) );
OAI21X1TS U4728 ( .A0(n1219), .A1(n1213), .B0(n1220), .Y(n1151) );
AOI21X2TS U4729 ( .A0(n1152), .A1(n1216), .B0(n1151), .Y(n1232) );
OAI21X1TS U4730 ( .A0(n1274), .A1(n1268), .B0(n1275), .Y(n1153) );
AOI21X1TS U4731 ( .A0(n1154), .A1(n1267), .B0(n1153), .Y(n1155) );
OAI21X2TS U4732 ( .A0(n1232), .A1(n1156), .B0(n1155), .Y(n1298) );
NAND2X1TS U4733 ( .A(Data_B_i[51]), .B(Data_B_i[24]), .Y(n1301) );
NAND2X1TS U4734 ( .A(Data_B_i[52]), .B(Data_B_i[25]), .Y(n1293) );
AOI21X1TS U4735 ( .A0(n1294), .A1(n1290), .B0(n1157), .Y(n1167) );
AOI21X1TS U4736 ( .A0(n1159), .A1(n1298), .B0(n1158), .Y(n1160) );
NAND2X1TS U4737 ( .A(Data_B_i[53]), .B(Data_B_i[26]), .Y(n1165) );
XNOR2X1TS U4738 ( .A(n245), .B(n2693), .Y(n1341) );
NOR2X1TS U4739 ( .A(n1164), .B(n1166), .Y(n1169) );
NAND2X1TS U4740 ( .A(n1297), .B(n1169), .Y(n1171) );
AOI21X1TS U4741 ( .A0(n1298), .A1(n1169), .B0(n1168), .Y(n1170) );
XNOR2X1TS U4742 ( .A(n258), .B(n2905), .Y(n1230) );
NAND2X1TS U4743 ( .A(n1176), .B(n1175), .Y(n1177) );
INVX2TS U4744 ( .A(n1179), .Y(n1329) );
AOI21X4TS U4745 ( .A0(n1330), .A1(n1329), .B0(n1180), .Y(n1185) );
NAND2X1TS U4746 ( .A(n1183), .B(n1182), .Y(n1184) );
XOR2X4TS U4747 ( .A(n1185), .B(n1184), .Y(n1327) );
XNOR2X1TS U4748 ( .A(n258), .B(n2894), .Y(n1370) );
OAI22X1TS U4749 ( .A0(n1369), .A1(n1370), .B0(n114), .B1(n2212), .Y(n1325)
);
INVX2TS U4750 ( .A(n1188), .Y(n1250) );
INVX2TS U4751 ( .A(n1247), .Y(n1205) );
AOI21X1TS U4752 ( .A0(n1205), .A1(n1250), .B0(n1189), .Y(n1190) );
NAND2X1TS U4753 ( .A(n1204), .B(n1198), .Y(n1207) );
NAND2X1TS U4754 ( .A(n1212), .B(n1215), .Y(n1218) );
AOI21X1TS U4755 ( .A0(n1216), .A1(n1215), .B0(n1214), .Y(n1217) );
CLKINVX1TS U4756 ( .A(n1219), .Y(n1221) );
NAND2X1TS U4757 ( .A(n1221), .B(n1220), .Y(n1222) );
XNOR2X1TS U4758 ( .A(n1223), .B(n2908), .Y(n1340) );
INVX2TS U4759 ( .A(n1225), .Y(n1235) );
NAND2X1TS U4760 ( .A(n1235), .B(n1233), .Y(n1226) );
XNOR2X1TS U4761 ( .A(n1227), .B(n2485), .Y(n1278) );
OAI22X1TS U4762 ( .A0(n346), .A1(n1340), .B0(n1278), .B1(n2941), .Y(n1323)
);
NAND2X1TS U4763 ( .A(n1228), .B(n1383), .Y(n1229) );
NOR2X1TS U4764 ( .A(n5180), .B(n259), .Y(n1518) );
INVX2TS U4765 ( .A(n1231), .Y(n1266) );
NAND2X1TS U4766 ( .A(n1266), .B(n1235), .Y(n1237) );
INVX2TS U4767 ( .A(n1232), .Y(n1273) );
AOI21X1TS U4768 ( .A0(n1273), .A1(n1235), .B0(n1234), .Y(n1236) );
NAND2X1TS U4769 ( .A(n1240), .B(n1239), .Y(n1241) );
XNOR2X1TS U4770 ( .A(n233), .B(n2485), .Y(n1277) );
NAND2X1TS U4771 ( .A(n1266), .B(n1264), .Y(n1243) );
AOI21X1TS U4772 ( .A0(n1273), .A1(n1264), .B0(n1267), .Y(n1242) );
NAND2X1TS U4773 ( .A(n589), .B(n1268), .Y(n1244) );
XNOR2X1TS U4774 ( .A(n2452), .B(n336), .Y(n1451) );
OAI22X1TS U4775 ( .A0(n345), .A1(n1277), .B0(n1451), .B1(n2941), .Y(n1471)
);
NAND2X1TS U4776 ( .A(n1250), .B(n1249), .Y(n1251) );
XNOR2X4TS U4777 ( .A(n1252), .B(n1251), .Y(n1262) );
XNOR2X4TS U4778 ( .A(n2066), .B(n1262), .Y(n1263) );
INVX2TS U4779 ( .A(n1253), .Y(n1286) );
NAND2X1TS U4780 ( .A(n1280), .B(n1286), .Y(n1256) );
AOI21X1TS U4781 ( .A0(n1281), .A1(n1286), .B0(n1254), .Y(n1255) );
OAI21X4TS U4782 ( .A0(n1284), .A1(n1256), .B0(n1255), .Y(n1261) );
CLKINVX1TS U4783 ( .A(n1257), .Y(n1259) );
NAND2X1TS U4784 ( .A(n1259), .B(n1258), .Y(n1260) );
XNOR2X4TS U4785 ( .A(n1261), .B(n1260), .Y(n1279) );
XNOR2X4TS U4786 ( .A(n1262), .B(n1279), .Y(n1598) );
XNOR2X1TS U4787 ( .A(n2846), .B(n2899), .Y(n1343) );
CLKINVX1TS U4788 ( .A(n1264), .Y(n1265) );
OAI22X2TS U4789 ( .A0(n346), .A1(n1278), .B0(n1277), .B1(n2941), .Y(n1409)
);
AO21X1TS U4790 ( .A0(n325), .A1(n114), .B0(n2212), .Y(n1408) );
OAI21X4TS U4791 ( .A0(n1284), .A1(n1283), .B0(n1282), .Y(n1287) );
XOR2X4TS U4792 ( .A(n1287), .B(n969), .Y(n1288) );
XNOR2X4TS U4793 ( .A(n1326), .B(n1288), .Y(n2142) );
NAND2X1TS U4794 ( .A(n1297), .B(n1302), .Y(n1292) );
AOI21X1TS U4795 ( .A0(n1298), .A1(n1302), .B0(n1290), .Y(n1291) );
OAI21X2TS U4796 ( .A0(n586), .A1(n1292), .B0(n1291), .Y(n1295) );
XOR2X4TS U4797 ( .A(n1295), .B(n992), .Y(n1296) );
XNOR2X1TS U4798 ( .A(n367), .B(n2911), .Y(n1416) );
XNOR2X1TS U4799 ( .A(n245), .B(n2911), .Y(n1470) );
OAI22X1TS U4800 ( .A0(n2958), .A1(n1416), .B0(n1470), .B1(n301), .Y(n1476)
);
CLKINVX1TS U4801 ( .A(n1298), .Y(n1299) );
OAI22X1TS U4802 ( .A0(n1586), .A1(n1303), .B0(n1452), .B1(n2924), .Y(n1475)
);
NAND2X1TS U4803 ( .A(n1306), .B(n1305), .Y(n1307) );
XOR2X4TS U4804 ( .A(n305), .B(n1307), .Y(n1308) );
INVX4TS U4805 ( .A(n598), .Y(n1665) );
XNOR2X1TS U4806 ( .A(n1665), .B(n229), .Y(n1414) );
XNOR2X1TS U4807 ( .A(n263), .B(n1665), .Y(n1463) );
OAI22X1TS U4808 ( .A0(n141), .A1(n1414), .B0(n1463), .B1(n2796), .Y(n1474)
);
NAND2X1TS U4809 ( .A(n1312), .B(n1314), .Y(n1317) );
AOI21X1TS U4810 ( .A0(n1315), .A1(n1314), .B0(n1313), .Y(n1316) );
NAND2X1TS U4811 ( .A(n1320), .B(n1319), .Y(n1321) );
XNOR2X1TS U4812 ( .A(n2866), .B(n248), .Y(n1396) );
XNOR2X1TS U4813 ( .A(n2503), .B(n273), .Y(n1418) );
OAI22X1TS U4814 ( .A0(n3199), .A1(n1396), .B0(n309), .B1(n1418), .Y(n3080)
);
XNOR2X1TS U4815 ( .A(n2838), .B(n1326), .Y(n2938) );
XNOR2X1TS U4816 ( .A(n367), .B(n2905), .Y(n1342) );
OAI22X1TS U4817 ( .A0(n333), .A1(n2938), .B0(n1342), .B1(n2937), .Y(n2967)
);
XNOR2X1TS U4818 ( .A(n2846), .B(n2911), .Y(n2956) );
XNOR2X1TS U4819 ( .A(n3200), .B(n2911), .Y(n1345) );
OAI22X1TS U4820 ( .A0(n2958), .A1(n2956), .B0(n1345), .B1(n2955), .Y(n2966)
);
XOR2X1TS U4821 ( .A(n1327), .B(n1338), .Y(n1339) );
CLKINVX1TS U4822 ( .A(n1333), .Y(n1335) );
NAND2X1TS U4823 ( .A(n1335), .B(n1334), .Y(n1336) );
NAND2X2TS U4824 ( .A(n1339), .B(n2143), .Y(n1877) );
XNOR2X1TS U4825 ( .A(n1227), .B(n2899), .Y(n2925) );
XNOR2X1TS U4826 ( .A(n233), .B(n2899), .Y(n1344) );
OAI22X1TS U4827 ( .A0(n1586), .A1(n2925), .B0(n1344), .B1(n231), .Y(n2970)
);
XNOR2X1TS U4828 ( .A(n336), .B(n267), .Y(n2942) );
OAI22X1TS U4829 ( .A0(n346), .A1(n2942), .B0(n1340), .B1(n2941), .Y(n2969)
);
XNOR2X1TS U4830 ( .A(n314), .B(n244), .Y(n2963) );
XNOR2X1TS U4831 ( .A(n228), .B(n314), .Y(n1402) );
OAI22X1TS U4832 ( .A0(n143), .A1(n2963), .B0(n1402), .B1(n2962), .Y(n2968)
);
OAI22X1TS U4833 ( .A0(n1453), .A1(n1342), .B0(n1341), .B1(n226), .Y(n1413)
);
OAI22X1TS U4834 ( .A0(n1586), .A1(n1344), .B0(n1343), .B1(n231), .Y(n1412)
);
XNOR2X1TS U4835 ( .A(n5147), .B(n2911), .Y(n1417) );
OAI22X1TS U4836 ( .A0(n347), .A1(n1345), .B0(n1417), .B1(n2955), .Y(n1411)
);
XNOR2X1TS U4837 ( .A(n311), .B(n366), .Y(n2971) );
XNOR2X1TS U4838 ( .A(n1086), .B(n251), .Y(n1397) );
OAI22X1TS U4839 ( .A0(n312), .A1(n2971), .B0(n2444), .B1(n1397), .Y(n3021)
);
NAND2X1TS U4840 ( .A(n1347), .B(n1350), .Y(n1353) );
CLKINVX1TS U4841 ( .A(n1354), .Y(n1356) );
NAND2X1TS U4842 ( .A(n1356), .B(n1355), .Y(n1357) );
XNOR2X1TS U4843 ( .A(n2882), .B(n272), .Y(n2975) );
XNOR2X1TS U4844 ( .A(n2882), .B(n264), .Y(n1406) );
OAI22X1TS U4845 ( .A0(n7674), .A1(n2975), .B0(n295), .B1(n1406), .Y(n3020)
);
NAND2X1TS U4846 ( .A(n1362), .B(n1360), .Y(n1359) );
INVX2TS U4847 ( .A(n1360), .Y(n1361) );
AOI21X1TS U4848 ( .A0(n1363), .A1(n1362), .B0(n1361), .Y(n1368) );
NAND2X1TS U4849 ( .A(n1366), .B(n1365), .Y(n1367) );
NOR2X1TS U4850 ( .A(n7672), .B(n155), .Y(n1401) );
OAI22X1TS U4851 ( .A0(n325), .A1(n2932), .B0(n1370), .B1(n114), .Y(n1400) );
XNOR2X1TS U4852 ( .A(n2871), .B(n273), .Y(n2994) );
NAND2X1TS U4853 ( .A(n1371), .B(n1374), .Y(n1377) );
AOI21X1TS U4854 ( .A0(n1375), .A1(n1374), .B0(n1373), .Y(n1376) );
NAND2X1TS U4855 ( .A(n1380), .B(n1379), .Y(n1381) );
XNOR2X1TS U4856 ( .A(n2862), .B(n2815), .Y(n2977) );
XNOR2X1TS U4857 ( .A(n2862), .B(n361), .Y(n1407) );
NAND2X1TS U4858 ( .A(n1394), .B(n1393), .Y(n1395) );
XNOR2X1TS U4859 ( .A(n2866), .B(n262), .Y(n2997) );
OAI22X1TS U4860 ( .A0(n3199), .A1(n2997), .B0(n309), .B1(n1396), .Y(n3016)
);
XNOR2X1TS U4861 ( .A(n311), .B(n244), .Y(n1429) );
OR2X2TS U4862 ( .A(n2444), .B(n1429), .Y(n1398) );
XNOR2X1TS U4863 ( .A(n1665), .B(n266), .Y(n1415) );
OAI22X1TS U4864 ( .A0(n307), .A1(n1405), .B0(n2547), .B1(n1404), .Y(n1427)
);
XNOR2X1TS U4865 ( .A(n2882), .B(n2815), .Y(n1430) );
XNOR2X1TS U4866 ( .A(n2862), .B(n2813), .Y(n1432) );
OAI22X1TS U4867 ( .A0(n224), .A1(n1407), .B0(n5149), .B1(n1432), .Y(n1425)
);
OAI22X1TS U4868 ( .A0(n2958), .A1(n1417), .B0(n1416), .B1(n2955), .Y(n1444)
);
XNOR2X1TS U4869 ( .A(n2503), .B(n252), .Y(n1450) );
OAI22X1TS U4870 ( .A0(n3199), .A1(n1418), .B0(n309), .B1(n1450), .Y(n1443)
);
NAND2X1TS U4871 ( .A(n1420), .B(n1419), .Y(n1423) );
NAND2X1TS U4872 ( .A(n1421), .B(n1420), .Y(n1422) );
NAND3X1TS U4873 ( .A(n1424), .B(n1423), .C(n1422), .Y(n1485) );
CMPR32X2TS U4874 ( .A(n1427), .B(n1426), .C(n1425), .CO(n1484), .S(n3070) );
XNOR2X1TS U4875 ( .A(n2882), .B(n361), .Y(n1449) );
OAI22X1TS U4876 ( .A0(n7674), .A1(n1430), .B0(n296), .B1(n1449), .Y(n1438)
);
XOR2X1TS U4877 ( .A(n1438), .B(n1439), .Y(n1433) );
XOR2X1TS U4878 ( .A(n1437), .B(n1433), .Y(n1483) );
NAND2X1TS U4879 ( .A(n1439), .B(n1437), .Y(n1442) );
NAND2X1TS U4880 ( .A(n1438), .B(n1437), .Y(n1441) );
NAND2X1TS U4881 ( .A(n1439), .B(n1438), .Y(n1440) );
NAND3X1TS U4882 ( .A(n1442), .B(n1441), .C(n1440), .Y(n1482) );
ADDFHX2TS U4883 ( .A(n1448), .B(n1447), .CI(n1446), .CO(n1456), .S(n1310) );
XNOR2X1TS U4884 ( .A(n2882), .B(n2813), .Y(n1465) );
BUFX3TS U4885 ( .A(n309), .Y(n1831) );
XNOR2X1TS U4886 ( .A(n2503), .B(n366), .Y(n1468) );
OAI22X1TS U4887 ( .A0(n3199), .A1(n1450), .B0(n1831), .B1(n1468), .Y(n1454)
);
XNOR2X1TS U4888 ( .A(n268), .B(n336), .Y(n1524) );
OAI22X1TS U4889 ( .A0(n346), .A1(n1451), .B0(n1524), .B1(n2941), .Y(n1493)
);
XNOR2X1TS U4890 ( .A(n367), .B(n2899), .Y(n1497) );
XNOR2X1TS U4891 ( .A(n233), .B(n1665), .Y(n1496) );
OAI22X1TS U4892 ( .A0(n141), .A1(n1463), .B0(n1496), .B1(n2796), .Y(n1500)
);
XNOR2X1TS U4893 ( .A(n1666), .B(n229), .Y(n1519) );
OAI22X1TS U4894 ( .A0(n312), .A1(n1464), .B0(n2444), .B1(n1519), .Y(n1499)
);
XNOR2X1TS U4895 ( .A(n2882), .B(n248), .Y(n1495) );
OAI22X1TS U4896 ( .A0(n7674), .A1(n1465), .B0(n2578), .B1(n1495), .Y(n1498)
);
XNOR2X1TS U4897 ( .A(n740), .B(n228), .Y(n1521) );
OAI22X1TS U4898 ( .A0(n307), .A1(n1466), .B0(n130), .B1(n1521), .Y(n1515) );
XNOR2X1TS U4899 ( .A(n2553), .B(n252), .Y(n1520) );
XNOR2X1TS U4900 ( .A(n2503), .B(n251), .Y(n1522) );
OAI22X1TS U4901 ( .A0(n1833), .A1(n1468), .B0(n2587), .B1(n1522), .Y(n1513)
);
INVX2TS U4902 ( .A(n2865), .Y(n1469) );
NOR2X1TS U4903 ( .A(n5180), .B(n1469), .Y(n1517) );
XNOR2X1TS U4904 ( .A(n257), .B(n2911), .Y(n1523) );
OAI22X1TS U4905 ( .A0(n2958), .A1(n1470), .B0(n1523), .B1(n2955), .Y(n1516)
);
XOR2X2TS U4906 ( .A(n1486), .B(n1504), .Y(n3122) );
OAI2BB1X2TS U4907 ( .A0N(n3121), .A1N(n3119), .B0(n1487), .Y(n3150) );
CMPR32X2TS U4908 ( .A(n1490), .B(n1489), .C(n1488), .CO(n1533), .S(n1510) );
CMPR32X2TS U4909 ( .A(n1493), .B(n1492), .C(n1491), .CO(n1562), .S(n1503) );
XNOR2X1TS U4910 ( .A(n2568), .B(n1069), .Y(n1552) );
XNOR2X1TS U4911 ( .A(n1665), .B(n2452), .Y(n1557) );
OAI22X1TS U4912 ( .A0(n143), .A1(n1496), .B0(n1557), .B1(n2962), .Y(n1559)
);
XNOR2X1TS U4913 ( .A(n245), .B(n2899), .Y(n1549) );
OAI22X1TS U4914 ( .A0(n1586), .A1(n1497), .B0(n1549), .B1(n231), .Y(n1558)
);
CMPR32X2TS U4915 ( .A(n1500), .B(n1499), .C(n1498), .CO(n1560), .S(n1512) );
NAND2X1TS U4916 ( .A(n1506), .B(n1504), .Y(n1509) );
NAND2X1TS U4917 ( .A(n1506), .B(n1505), .Y(n1507) );
CMPR32X2TS U4918 ( .A(n1515), .B(n1514), .C(n1513), .CO(n1539), .S(n1511) );
XNOR2X1TS U4919 ( .A(n139), .B(n1227), .Y(n1546) );
OAI22X1TS U4920 ( .A0(n232), .A1(n1519), .B0(n2972), .B1(n1546), .Y(n1541)
);
XNOR2X1TS U4921 ( .A(n2553), .B(n366), .Y(n1551) );
OAI22X1TS U4922 ( .A0(n826), .A1(n1520), .B0(n5160), .B1(n1551), .Y(n1540)
);
XNOR2X1TS U4923 ( .A(n2395), .B(n267), .Y(n1547) );
OAI22X1TS U4924 ( .A0(n307), .A1(n1521), .B0(n734), .B1(n1547), .Y(n1545) );
XNOR2X1TS U4925 ( .A(n2503), .B(n244), .Y(n1550) );
OAI22X1TS U4926 ( .A0(n2958), .A1(n1523), .B0(n301), .B1(n2101), .Y(n1555)
);
XNOR2X1TS U4927 ( .A(n5147), .B(n2485), .Y(n1556) );
OAI22X1TS U4928 ( .A0(n344), .A1(n1524), .B0(n1556), .B1(n2941), .Y(n1553)
);
NOR2X2TS U4929 ( .A(n3150), .B(n3151), .Y(n7858) );
ADDFHX2TS U4930 ( .A(n1530), .B(n1529), .CI(n1528), .CO(n3152), .S(n3151) );
XNOR2X1TS U4931 ( .A(n1666), .B(n233), .Y(n1572) );
OAI22X1TS U4932 ( .A0(n2446), .A1(n1546), .B0(n2972), .B1(n1572), .Y(n1582)
);
XNOR2X1TS U4933 ( .A(n2395), .B(n229), .Y(n1579) );
OAI22X1TS U4934 ( .A0(n307), .A1(n1547), .B0(n2547), .B1(n1579), .Y(n1581)
);
NOR2X1TS U4935 ( .A(n5180), .B(n1548), .Y(n1575) );
XNOR2X1TS U4936 ( .A(n257), .B(n2899), .Y(n1585) );
OAI22X1TS U4937 ( .A0(n1586), .A1(n1549), .B0(n1585), .B1(n2641), .Y(n1574)
);
XNOR2X1TS U4938 ( .A(n2503), .B(n227), .Y(n1583) );
OAI22X1TS U4939 ( .A0(n3000), .A1(n1550), .B0(n2587), .B1(n1583), .Y(n1571)
);
BUFX4TS U4940 ( .A(n2863), .Y(n3202) );
XNOR2X1TS U4941 ( .A(n2553), .B(n251), .Y(n1577) );
OAI22X1TS U4942 ( .A0(n3204), .A1(n1551), .B0(n3202), .B1(n1577), .Y(n1570)
);
XNOR2X1TS U4943 ( .A(n2568), .B(n252), .Y(n1578) );
OAI22X1TS U4944 ( .A0(n7674), .A1(n1552), .B0(n296), .B1(n1578), .Y(n1569)
);
XNOR2X1TS U4945 ( .A(n1296), .B(n2485), .Y(n1584) );
XNOR2X1TS U4946 ( .A(n1665), .B(n268), .Y(n1573) );
OAI22X1TS U4947 ( .A0(n143), .A1(n1557), .B0(n1573), .B1(n2796), .Y(n1588)
);
NOR2X4TS U4948 ( .A(n3152), .B(n3153), .Y(n7740) );
NOR2X2TS U4949 ( .A(n7858), .B(n7740), .Y(n7716) );
CMPR32X2TS U4950 ( .A(n1571), .B(n1570), .C(n1569), .CO(n1608), .S(n1565) );
XNOR2X1TS U4951 ( .A(n2452), .B(n1666), .Y(n1599) );
OAI22X1TS U4952 ( .A0(n232), .A1(n1572), .B0(n2972), .B1(n1599), .Y(n1617)
);
XNOR2X1TS U4953 ( .A(n1665), .B(n5147), .Y(n1597) );
OAI22X1TS U4954 ( .A0(n144), .A1(n1573), .B0(n1597), .B1(n2796), .Y(n1616)
);
XNOR2X1TS U4955 ( .A(n2553), .B(n244), .Y(n1605) );
OAI22X1TS U4956 ( .A0(n5151), .A1(n1577), .B0(n3202), .B1(n1605), .Y(n1602)
);
XNOR2X1TS U4957 ( .A(n2568), .B(n366), .Y(n1604) );
XNOR2X1TS U4958 ( .A(n2395), .B(n1227), .Y(n1603) );
OAI22X1TS U4959 ( .A0(n732), .A1(n1579), .B0(n2547), .B1(n1603), .Y(n1600)
);
CMPR32X2TS U4960 ( .A(n1582), .B(n1581), .C(n1580), .CO(n1623), .S(n1566) );
XNOR2X1TS U4961 ( .A(n1809), .B(n266), .Y(n1609) );
OAI22X1TS U4962 ( .A0(n3000), .A1(n1583), .B0(n2587), .B1(n1609), .Y(n1620)
);
XNOR2X1TS U4963 ( .A(n5179), .B(n2485), .Y(n1610) );
OAI22X1TS U4964 ( .A0(n344), .A1(n1584), .B0(n1610), .B1(n2941), .Y(n1611)
);
OAI22X1TS U4965 ( .A0(n1586), .A1(n1585), .B0(n2641), .B1(n2066), .Y(n1613)
);
XNOR2X1TS U4966 ( .A(n1665), .B(n367), .Y(n1634) );
OAI22X1TS U4967 ( .A0(n127), .A1(n1597), .B0(n1634), .B1(n2796), .Y(n1632)
);
XNOR2X1TS U4968 ( .A(n139), .B(n268), .Y(n1648) );
OAI22X1TS U4969 ( .A0(n2974), .A1(n1599), .B0(n2972), .B1(n1648), .Y(n1630)
);
XNOR2X1TS U4970 ( .A(n2395), .B(n215), .Y(n1641) );
OAI22X1TS U4971 ( .A0(n307), .A1(n1603), .B0(n2547), .B1(n1641), .Y(n1637)
);
XNOR2X1TS U4972 ( .A(n2568), .B(n250), .Y(n1642) );
XNOR2X1TS U4973 ( .A(n2553), .B(n227), .Y(n1647) );
OAI22X1TS U4974 ( .A0(n224), .A1(n1605), .B0(n3202), .B1(n1647), .Y(n1635)
);
XNOR2X1TS U4975 ( .A(n1809), .B(n229), .Y(n1643) );
OAI22X1TS U4976 ( .A0(n3000), .A1(n1609), .B0(n2587), .B1(n1643), .Y(n1646)
);
NOR2X1TS U4977 ( .A(n5180), .B(n2868), .Y(n1650) );
XNOR2X1TS U4978 ( .A(n257), .B(n2908), .Y(n1633) );
ADDFHX2TS U4979 ( .A(n1623), .B(n1622), .CI(n1621), .CO(n1656), .S(n1624) );
ADDFHX2TS U4980 ( .A(n1626), .B(n1625), .CI(n1624), .CO(n1655), .S(n1662) );
XNOR2X1TS U4981 ( .A(n1665), .B(n245), .Y(n1693) );
OAI22X1TS U4982 ( .A0(n142), .A1(n1634), .B0(n1693), .B1(n2796), .Y(n1707)
);
XNOR2X1TS U4983 ( .A(n740), .B(n2452), .Y(n1699) );
OAI22X1TS U4984 ( .A0(n307), .A1(n1641), .B0(n2547), .B1(n1699), .Y(n1720)
);
XNOR2X1TS U4985 ( .A(n2568), .B(n244), .Y(n1697) );
XNOR2X1TS U4986 ( .A(n1809), .B(n263), .Y(n1703) );
OAI22X1TS U4987 ( .A0(n1833), .A1(n1643), .B0(n1831), .B1(n1703), .Y(n1718)
);
XNOR2X1TS U4988 ( .A(n3201), .B(n266), .Y(n1701) );
OAI22X1TS U4989 ( .A0(n224), .A1(n1647), .B0(n3202), .B1(n1701), .Y(n1714)
);
XNOR2X1TS U4990 ( .A(n1666), .B(n5147), .Y(n1695) );
NOR2X4TS U4991 ( .A(n3158), .B(n3159), .Y(n3160) );
ADDFHX2TS U4992 ( .A(n1660), .B(n1659), .CI(n1658), .CO(n3155), .S(n3153) );
XNOR2X1TS U4993 ( .A(n3201), .B(n229), .Y(n1700) );
XNOR2X1TS U4994 ( .A(n3201), .B(n263), .Y(n1673) );
OAI22X1TS U4995 ( .A0(n3204), .A1(n1700), .B0(n5160), .B1(n1673), .Y(n1717)
);
INVX2TS U4996 ( .A(n244), .Y(n1664) );
NOR2X1TS U4997 ( .A(n7672), .B(n1664), .Y(n1677) );
XNOR2X1TS U4998 ( .A(n1665), .B(n258), .Y(n1692) );
XNOR2X1TS U4999 ( .A(n139), .B(n367), .Y(n1694) );
XNOR2X1TS U5000 ( .A(n1666), .B(n245), .Y(n1667) );
OAI22X1TS U5001 ( .A0(n2974), .A1(n1694), .B0(n2972), .B1(n1667), .Y(n1671)
);
XNOR2X1TS U5002 ( .A(n139), .B(n258), .Y(n1678) );
OAI22X1TS U5003 ( .A0(n2974), .A1(n1667), .B0(n2972), .B1(n1678), .Y(n1688)
);
XNOR2X1TS U5004 ( .A(n1809), .B(n2452), .Y(n1670) );
XNOR2X1TS U5005 ( .A(n1809), .B(n268), .Y(n1685) );
OAI22X1TS U5006 ( .A0(n1833), .A1(n1670), .B0(n1831), .B1(n1685), .Y(n1687)
);
XNOR2X1TS U5007 ( .A(n2395), .B(n5147), .Y(n1669) );
XNOR2X1TS U5008 ( .A(n740), .B(n367), .Y(n1679) );
XNOR2X1TS U5009 ( .A(n2568), .B(n228), .Y(n1696) );
XNOR2X1TS U5010 ( .A(n2568), .B(n267), .Y(n1674) );
OAI22X1TS U5011 ( .A0(n5182), .A1(n1696), .B0(n296), .B1(n1674), .Y(n1706)
);
XNOR2X1TS U5012 ( .A(n740), .B(n268), .Y(n1698) );
OAI22X1TS U5013 ( .A0(n2996), .A1(n1698), .B0(n734), .B1(n1669), .Y(n1705)
);
XNOR2X1TS U5014 ( .A(n1809), .B(n215), .Y(n1702) );
OAI22X1TS U5015 ( .A0(n1833), .A1(n1702), .B0(n1831), .B1(n1670), .Y(n1704)
);
XNOR2X1TS U5016 ( .A(n3201), .B(n215), .Y(n1684) );
OAI22X1TS U5017 ( .A0(n3204), .A1(n1673), .B0(n5160), .B1(n1684), .Y(n1682)
);
XNOR2X1TS U5018 ( .A(n7673), .B(n229), .Y(n1683) );
OAI22X1TS U5019 ( .A0(n949), .A1(n1674), .B0(n2578), .B1(n1683), .Y(n1681)
);
XNOR2X1TS U5020 ( .A(n740), .B(n245), .Y(n1739) );
OAI22X1TS U5021 ( .A0(n732), .A1(n1679), .B0(n130), .B1(n1739), .Y(n1741) );
XNOR2X1TS U5022 ( .A(n7673), .B(n263), .Y(n1740) );
OAI22X1TS U5023 ( .A0(n299), .A1(n1683), .B0(n295), .B1(n1740), .Y(n1737) );
XNOR2X1TS U5024 ( .A(n3201), .B(n2452), .Y(n1738) );
OAI22X1TS U5025 ( .A0(n224), .A1(n1684), .B0(n5160), .B1(n1738), .Y(n1736)
);
XNOR2X1TS U5026 ( .A(n1809), .B(n5147), .Y(n1744) );
OAI22X1TS U5027 ( .A0(n1833), .A1(n1685), .B0(n1831), .B1(n1744), .Y(n1735)
);
OAI22X1TS U5028 ( .A0(n142), .A1(n1693), .B0(n1692), .B1(n2796), .Y(n1722)
);
OAI22X1TS U5029 ( .A0(n5182), .A1(n1697), .B0(n296), .B1(n1696), .Y(n1721)
);
OAI22X1TS U5030 ( .A0(n732), .A1(n1699), .B0(n734), .B1(n1698), .Y(n1725) );
OAI22X1TS U5031 ( .A0(n224), .A1(n1701), .B0(n3202), .B1(n1700), .Y(n1724)
);
OAI22X1TS U5032 ( .A0(n1833), .A1(n1703), .B0(n1831), .B1(n1702), .Y(n1723)
);
ADDFX1TS U5033 ( .A(n1706), .B(n1705), .CI(n1704), .CO(n1691), .S(n1748) );
CMPR32X2TS U5034 ( .A(n1709), .B(n1708), .C(n1707), .CO(n1756), .S(n1752) );
CMPR32X2TS U5035 ( .A(n1731), .B(n1730), .C(n1729), .CO(n1785), .S(n1746) );
CMPR32X2TS U5036 ( .A(n1737), .B(n1736), .C(n1735), .CO(n1802), .S(n1734) );
XNOR2X1TS U5037 ( .A(n3201), .B(n268), .Y(n1795) );
OAI22X1TS U5038 ( .A0(n3204), .A1(n1738), .B0(n5160), .B1(n1795), .Y(n1794)
);
XNOR2X1TS U5039 ( .A(n2395), .B(n257), .Y(n1790) );
OAI22X1TS U5040 ( .A0(n2996), .A1(n1739), .B0(n130), .B1(n1790), .Y(n1793)
);
XNOR2X1TS U5041 ( .A(n7673), .B(n215), .Y(n1796) );
OAI22X1TS U5042 ( .A0(n299), .A1(n1740), .B0(n296), .B1(n1796), .Y(n1788) );
NOR2X1TS U5043 ( .A(n781), .B(n365), .Y(n1798) );
XNOR2X1TS U5044 ( .A(n1809), .B(n367), .Y(n1791) );
OAI22X1TS U5045 ( .A0(n1833), .A1(n1744), .B0(n1831), .B1(n1791), .Y(n1797)
);
ADDFHX1TS U5046 ( .A(n1762), .B(n1761), .CI(n1760), .CO(n1763), .S(n1777) );
OR2X4TS U5047 ( .A(n3162), .B(n3163), .Y(n7711) );
INVX2TS U5048 ( .A(n603), .Y(n3176) );
NOR2X2TS U5049 ( .A(n7710), .B(n3176), .Y(n7145) );
XNOR2X1TS U5050 ( .A(n1809), .B(n245), .Y(n1810) );
OAI22X1TS U5051 ( .A0(n1833), .A1(n1791), .B0(n1831), .B1(n1810), .Y(n1811)
);
CMPR32X2TS U5052 ( .A(n1794), .B(n1793), .C(n1792), .CO(n1818), .S(n1801) );
XNOR2X1TS U5053 ( .A(n3201), .B(n5147), .Y(n1815) );
OAI22X1TS U5054 ( .A0(n3204), .A1(n1795), .B0(n5160), .B1(n1815), .Y(n1808)
);
XNOR2X1TS U5055 ( .A(n7673), .B(n2452), .Y(n1814) );
OAI22X1TS U5056 ( .A0(n299), .A1(n1796), .B0(n2578), .B1(n1814), .Y(n1807)
);
CMPR32X2TS U5057 ( .A(n1802), .B(n1801), .C(n1800), .CO(n1803), .S(n1783) );
XNOR2X1TS U5058 ( .A(n1809), .B(n258), .Y(n1832) );
CMPR32X2TS U5059 ( .A(n1813), .B(n1812), .C(n1811), .CO(n1836), .S(n1819) );
XNOR2X1TS U5060 ( .A(n7673), .B(n268), .Y(n1826) );
OAI22X1TS U5061 ( .A0(n299), .A1(n1814), .B0(n2578), .B1(n1826), .Y(n1825)
);
XNOR2X1TS U5062 ( .A(n3201), .B(n367), .Y(n1834) );
OAI22X1TS U5063 ( .A0(n3204), .A1(n1815), .B0(n5160), .B1(n1834), .Y(n1824)
);
CMPR32X2TS U5064 ( .A(n1819), .B(n1818), .C(n1817), .CO(n1820), .S(n1804) );
ADDFHX2TS U5065 ( .A(n1822), .B(n1821), .CI(n1820), .CO(n3182), .S(n3179) );
CMPR32X2TS U5066 ( .A(n1825), .B(n1824), .C(n1823), .CO(n3190), .S(n1835) );
XNOR2X1TS U5067 ( .A(n7673), .B(n5147), .Y(n3197) );
OAI22X1TS U5068 ( .A0(n299), .A1(n1826), .B0(n295), .B1(n3197), .Y(n3196) );
CMPR32X2TS U5069 ( .A(n1829), .B(n1828), .C(n1827), .CO(n3195), .S(n1837) );
OAI22X1TS U5070 ( .A0(n1833), .A1(n1832), .B0(n1831), .B1(n3198), .Y(n3192)
);
XNOR2X1TS U5071 ( .A(n3201), .B(n245), .Y(n3203) );
OAI22X1TS U5072 ( .A0(n224), .A1(n1834), .B0(n5160), .B1(n3203), .Y(n3191)
);
NAND2X1TS U5073 ( .A(n7145), .B(n6562), .Y(n3187) );
XNOR2X1TS U5074 ( .A(n314), .B(n276), .Y(n1894) );
XNOR2X1TS U5075 ( .A(n270), .B(n747), .Y(n2401) );
OAI22X1TS U5076 ( .A0(n142), .A1(n1894), .B0(n2401), .B1(n2962), .Y(n2384)
);
XNOR2X1TS U5077 ( .A(n311), .B(n278), .Y(n1896) );
OAI21X1TS U5078 ( .A0(n1844), .A1(n1843), .B0(n1842), .Y(n1849) );
NAND2X1TS U5079 ( .A(n1847), .B(n1846), .Y(n1848) );
XNOR2X1TS U5080 ( .A(n139), .B(n280), .Y(n2372) );
INVX2TS U5081 ( .A(n2212), .Y(n2219) );
XNOR2X1TS U5082 ( .A(n2219), .B(n2027), .Y(n1856) );
XNOR2X1TS U5083 ( .A(n2219), .B(n2795), .Y(n1901) );
OAI22X1TS U5084 ( .A0(n2934), .A1(n1856), .B0(n2931), .B1(n1901), .Y(n1861)
);
INVX2TS U5085 ( .A(n1850), .Y(n1852) );
INVX2TS U5086 ( .A(n2961), .Y(n2440) );
XNOR2X1TS U5087 ( .A(n1227), .B(n2440), .Y(n1902) );
INVX4TS U5088 ( .A(n2101), .Y(n2636) );
XNOR2X1TS U5089 ( .A(n2636), .B(n361), .Y(n1879) );
XNOR2X1TS U5090 ( .A(n2636), .B(n2813), .Y(n1890) );
OAI22X1TS U5091 ( .A0(n348), .A1(n1879), .B0(n2464), .B1(n1890), .Y(n1859)
);
XNOR2X1TS U5092 ( .A(n2219), .B(n1069), .Y(n1925) );
XNOR2X1TS U5093 ( .A(n2908), .B(n275), .Y(n1923) );
XNOR2X1TS U5094 ( .A(n2485), .B(n270), .Y(n1878) );
OAI22X1TS U5095 ( .A0(n345), .A1(n1923), .B0(n2638), .B1(n1878), .Y(n1910)
);
XNOR2X1TS U5096 ( .A(n2905), .B(n247), .Y(n1871) );
XNOR2X1TS U5097 ( .A(n2462), .B(n274), .Y(n1891) );
OAI22X1TS U5098 ( .A0(n2349), .A1(n1871), .B0(n2347), .B1(n1891), .Y(n1900)
);
XNOR2X1TS U5099 ( .A(n2841), .B(n264), .Y(n1872) );
XNOR2X1TS U5100 ( .A(n2841), .B(n2815), .Y(n1893) );
OAI22X1TS U5101 ( .A0(n2602), .A1(n1872), .B0(n2924), .B1(n1893), .Y(n1899)
);
INVX2TS U5102 ( .A(n2928), .Y(n2232) );
XNOR2X1TS U5103 ( .A(n2232), .B(n366), .Y(n1909) );
XNOR2X1TS U5104 ( .A(n2232), .B(n250), .Y(n1876) );
OAI22X1TS U5105 ( .A0(n324), .A1(n1909), .B0(n1876), .B1(n2361), .Y(n1874)
);
INVX2TS U5106 ( .A(n2860), .Y(n2559) );
INVX2TS U5107 ( .A(n1862), .Y(n1864) );
XNOR2X1TS U5108 ( .A(n2848), .B(n2559), .Y(n1907) );
XOR2X1TS U5109 ( .A(n1869), .B(n1868), .Y(n1870) );
OAI22X1TS U5110 ( .A0(n1875), .A1(n2798), .B0(n1907), .B1(n326), .Y(n1873)
);
XNOR2X1TS U5111 ( .A(n2693), .B(n2813), .Y(n1922) );
OAI22X1TS U5112 ( .A0(n2349), .A1(n1922), .B0(n2347), .B1(n1871), .Y(n1929)
);
XNOR2X1TS U5113 ( .A(n2841), .B(n272), .Y(n1930) );
XNOR2X1TS U5114 ( .A(n2908), .B(n272), .Y(n1892) );
OAI22X1TS U5115 ( .A0(n344), .A1(n1878), .B0(n2638), .B1(n1892), .Y(n1886)
);
XNOR2X1TS U5116 ( .A(n2636), .B(n260), .Y(n1926) );
OAI22X1TS U5117 ( .A0(n347), .A1(n1926), .B0(n2464), .B1(n1879), .Y(n1937)
);
XNOR2X1TS U5118 ( .A(n313), .B(n277), .Y(n1931) );
XNOR2X1TS U5119 ( .A(n313), .B(n280), .Y(n1895) );
CLKAND2X2TS U5120 ( .A(n993), .B(n1883), .Y(n2551) );
XNOR2X1TS U5121 ( .A(n311), .B(n2551), .Y(n1885) );
NAND2X1TS U5122 ( .A(n1882), .B(n1881), .Y(n1884) );
XNOR2X1TS U5123 ( .A(n139), .B(n281), .Y(n1897) );
OAI22X1TS U5124 ( .A0(n2974), .A1(n1885), .B0(n2444), .B1(n1897), .Y(n1935)
);
XNOR2X1TS U5125 ( .A(n1223), .B(n2559), .Y(n2360) );
OAI22X1TS U5126 ( .A0(n1889), .A1(n327), .B0(n2360), .B1(n2609), .Y(n2404)
);
XNOR2X1TS U5127 ( .A(n2636), .B(n248), .Y(n2365) );
OAI22X1TS U5128 ( .A0(n348), .A1(n1890), .B0(n2464), .B1(n2365), .Y(n2402)
);
XNOR2X1TS U5129 ( .A(n2462), .B(n2027), .Y(n2348) );
OAI22X1TS U5130 ( .A0(n2349), .A1(n1891), .B0(n2347), .B1(n2348), .Y(n2343)
);
XNOR2X1TS U5131 ( .A(n2908), .B(n264), .Y(n2346) );
XNOR2X1TS U5132 ( .A(n2841), .B(n2865), .Y(n2350) );
OAI22X1TS U5133 ( .A0(n2602), .A1(n1893), .B0(n2924), .B1(n2350), .Y(n2341)
);
CLKBUFX2TS U5134 ( .A(n2551), .Y(n7813) );
OAI22X1TS U5135 ( .A0(n2974), .A1(n1897), .B0(n2444), .B1(n1896), .Y(n1913)
);
OAI22X1TS U5136 ( .A0(n325), .A1(n1901), .B0(n113), .B1(n2345), .Y(n2370) );
INVX2TS U5137 ( .A(n2961), .Y(n2560) );
CLKBUFX2TS U5138 ( .A(n2551), .Y(n2549) );
OAI22X1TS U5139 ( .A0(n307), .A1(n713), .B0(n1816), .B1(n1903), .Y(n2377) );
XNOR2X1TS U5140 ( .A(n2395), .B(n2551), .Y(n1904) );
XNOR2X1TS U5141 ( .A(n2871), .B(n281), .Y(n2371) );
OAI22X1TS U5142 ( .A0(n732), .A1(n1904), .B0(n130), .B1(n2371), .Y(n2376) );
OAI22X1TS U5143 ( .A0(n1907), .A1(n2798), .B0(n1924), .B1(n326), .Y(n1934)
);
XNOR2X1TS U5144 ( .A(n2232), .B(n252), .Y(n1943) );
OAI22X1TS U5145 ( .A0(n2145), .A1(n1943), .B0(n1909), .B1(n2143), .Y(n1932)
);
ADDFHX2TS U5146 ( .A(n1918), .B(n1917), .CI(n1916), .CO(n2386), .S(n1964) );
XNOR2X1TS U5147 ( .A(n2905), .B(n2865), .Y(n1953) );
XNOR2X1TS U5148 ( .A(n2908), .B(n280), .Y(n1954) );
XNOR2X1TS U5149 ( .A(n2795), .B(n2182), .Y(n1975) );
OAI22X1TS U5150 ( .A0(n1975), .A1(n2246), .B0(n1924), .B1(n2453), .Y(n1946)
);
CLKBUFX2TS U5151 ( .A(n986), .Y(n2561) );
XNOR2X1TS U5152 ( .A(n2441), .B(n247), .Y(n1944) );
OAI22X1TS U5153 ( .A0(n325), .A1(n1944), .B0(n2095), .B1(n1925), .Y(n1949)
);
XNOR2X1TS U5154 ( .A(n2636), .B(n265), .Y(n1957) );
NOR2BX1TS U5155 ( .AN(n7813), .B(n2869), .Y(n1947) );
XNOR2X1TS U5156 ( .A(n2841), .B(n270), .Y(n1956) );
OAI22X1TS U5157 ( .A0(n2602), .A1(n1956), .B0(n231), .B1(n1930), .Y(n1963)
);
XNOR2X1TS U5158 ( .A(n313), .B(n281), .Y(n1958) );
ADDFHX2TS U5159 ( .A(n1934), .B(n1933), .CI(n1932), .CO(n1939), .S(n1961) );
XNOR2X1TS U5160 ( .A(n2232), .B(n273), .Y(n1977) );
OAI22X1TS U5161 ( .A0(n2145), .A1(n1977), .B0(n1943), .B1(n2143), .Y(n1980)
);
XNOR2X1TS U5162 ( .A(n2441), .B(n2813), .Y(n1989) );
OAI22X1TS U5163 ( .A0(n2934), .A1(n1989), .B0(n113), .B1(n1944), .Y(n1979)
);
XNOR2X1TS U5164 ( .A(n2693), .B(n2815), .Y(n1984) );
OAI22X1TS U5165 ( .A0(n2349), .A1(n1984), .B0(n2347), .B1(n1953), .Y(n1993)
);
XNOR2X1TS U5166 ( .A(n2485), .B(n277), .Y(n1990) );
XNOR2X1TS U5167 ( .A(n2640), .B(n276), .Y(n2006) );
OAI22X1TS U5168 ( .A0(n2901), .A1(n2006), .B0(n231), .B1(n1956), .Y(n1991)
);
XNOR2X1TS U5169 ( .A(n2636), .B(n272), .Y(n1985) );
OAI22X1TS U5170 ( .A0(n347), .A1(n1985), .B0(n2464), .B1(n1957), .Y(n1996)
);
CLKBUFX2TS U5171 ( .A(n2551), .Y(n2251) );
XNOR2X1TS U5172 ( .A(n314), .B(n2251), .Y(n1959) );
OAI22X1TS U5173 ( .A0(n144), .A1(n598), .B0(n2796), .B1(n1960), .Y(n1994) );
OAI22X1TS U5174 ( .A0(n1983), .A1(n326), .B0(n1975), .B1(n2453), .Y(n2009)
);
XNOR2X1TS U5175 ( .A(n2351), .B(n248), .Y(n2010) );
OAI22X1TS U5176 ( .A0(n2145), .A1(n2010), .B0(n1977), .B1(n2143), .Y(n2007)
);
XNOR2X1TS U5177 ( .A(n2795), .B(n2440), .Y(n2028) );
CLKBUFX2TS U5178 ( .A(n1981), .Y(n2564) );
XNOR2X1TS U5179 ( .A(n273), .B(n2559), .Y(n2029) );
XNOR2X1TS U5180 ( .A(n2693), .B(n265), .Y(n2025) );
OAI22X1TS U5181 ( .A0(n2349), .A1(n2025), .B0(n2347), .B1(n1984), .Y(n2041)
);
XNOR2X1TS U5182 ( .A(n2636), .B(n270), .Y(n2021) );
OAI22X1TS U5183 ( .A0(n347), .A1(n2021), .B0(n2464), .B1(n1985), .Y(n2040)
);
ADDFHX2TS U5184 ( .A(n1988), .B(n1987), .CI(n1986), .CO(n1998), .S(n2032) );
NOR2BX1TS U5185 ( .AN(n7813), .B(n2663), .Y(n2024) );
XNOR2X1TS U5186 ( .A(n2441), .B(n2865), .Y(n2018) );
OAI22X1TS U5187 ( .A0(n2934), .A1(n2018), .B0(n114), .B1(n1989), .Y(n2023)
);
XNOR2X1TS U5188 ( .A(n336), .B(n281), .Y(n2019) );
NOR2X2TS U5189 ( .A(n2334), .B(n2333), .Y(n7902) );
XNOR2X1TS U5190 ( .A(n2640), .B(n280), .Y(n2026) );
OAI22X1TS U5191 ( .A0(n2901), .A1(n2026), .B0(n2641), .B1(n2006), .Y(n2045)
);
XNOR2X1TS U5192 ( .A(n2351), .B(n262), .Y(n2046) );
OAI22X1TS U5193 ( .A0(n2145), .A1(n2046), .B0(n2010), .B1(n2143), .Y(n2124)
);
ADDHX1TS U5194 ( .A(n2012), .B(n2011), .CO(n2042), .S(n2123) );
XNOR2X1TS U5195 ( .A(n2441), .B(n260), .Y(n2047) );
OAI22X1TS U5196 ( .A0(n2096), .A1(n2047), .B0(n2095), .B1(n2018), .Y(n2055)
);
XNOR2X1TS U5197 ( .A(n336), .B(n2551), .Y(n2020) );
XNOR2X1TS U5198 ( .A(n2598), .B(n276), .Y(n2048) );
OAI22X1TS U5199 ( .A0(n348), .A1(n2048), .B0(n2464), .B1(n2021), .Y(n2053)
);
XNOR2X1TS U5200 ( .A(n2905), .B(n271), .Y(n2051) );
OAI22X1TS U5201 ( .A0(n2349), .A1(n2051), .B0(n2347), .B1(n2025), .Y(n2127)
);
XNOR2X1TS U5202 ( .A(n2640), .B(n277), .Y(n2052) );
OAI22X1TS U5203 ( .A0(n2901), .A1(n2052), .B0(n2641), .B1(n2026), .Y(n2126)
);
XNOR2X1TS U5204 ( .A(n2027), .B(n2229), .Y(n2049) );
OAI22X1TS U5205 ( .A0(n2049), .A1(n2222), .B0(n2028), .B1(n2561), .Y(n2061)
);
XNOR2X1TS U5206 ( .A(n247), .B(n2182), .Y(n2050) );
OAI22X1TS U5207 ( .A0(n2050), .A1(n326), .B0(n2029), .B1(n2798), .Y(n2060)
);
NOR2BX1TS U5208 ( .AN(n2549), .B(n2030), .Y(n2059) );
ADDFHX4TS U5209 ( .A(n2033), .B(n2032), .CI(n2031), .CO(n2001), .S(n2034) );
CMPR32X2TS U5210 ( .A(n2042), .B(n2041), .C(n2040), .CO(n2015), .S(n2316) );
XNOR2X1TS U5211 ( .A(n2351), .B(n361), .Y(n2062) );
OAI22X1TS U5212 ( .A0(n2145), .A1(n2062), .B0(n2046), .B1(n2143), .Y(n2069)
);
XNOR2X1TS U5213 ( .A(n2441), .B(n264), .Y(n2073) );
OAI22X1TS U5214 ( .A0(n2934), .A1(n2073), .B0(n2931), .B1(n2047), .Y(n2068)
);
XNOR2X1TS U5215 ( .A(n2598), .B(n279), .Y(n2076) );
OAI22X1TS U5216 ( .A0(n348), .A1(n2076), .B0(n2142), .B1(n2048), .Y(n2067)
);
OAI22X1TS U5217 ( .A0(n2079), .A1(n2222), .B0(n2049), .B1(n2249), .Y(n2064)
);
XNOR2X1TS U5218 ( .A(n262), .B(n2182), .Y(n2080) );
XNOR2X1TS U5219 ( .A(n2693), .B(n269), .Y(n2087) );
OAI22X1TS U5220 ( .A0(n2349), .A1(n2087), .B0(n2347), .B1(n2051), .Y(n2085)
);
XNOR2X1TS U5221 ( .A(n2640), .B(n281), .Y(n2074) );
OAI22X1TS U5222 ( .A0(n2901), .A1(n2074), .B0(n2641), .B1(n2052), .Y(n2084)
);
NOR2X2TS U5223 ( .A(n2330), .B(n2329), .Y(n7775) );
NOR2X2TS U5224 ( .A(n7915), .B(n7775), .Y(n7898) );
NAND2X2TS U5225 ( .A(n2338), .B(n7898), .Y(n2340) );
XNOR2X1TS U5226 ( .A(n2351), .B(n2815), .Y(n2077) );
OAI22X1TS U5227 ( .A0(n2145), .A1(n2077), .B0(n2062), .B1(n2143), .Y(n2072)
);
ADDHX1TS U5228 ( .A(n2064), .B(n2063), .CO(n2086), .S(n2071) );
OAI22X1TS U5229 ( .A0(n2901), .A1(n2066), .B0(n2641), .B1(n2065), .Y(n2070)
);
XNOR2X1TS U5230 ( .A(n2441), .B(n271), .Y(n2094) );
OAI22X1TS U5231 ( .A0(n325), .A1(n2094), .B0(n2095), .B1(n2073), .Y(n2083)
);
XNOR2X1TS U5232 ( .A(n2640), .B(n2251), .Y(n2075) );
XNOR2X1TS U5233 ( .A(n2598), .B(n278), .Y(n2097) );
OAI22X1TS U5234 ( .A0(n348), .A1(n2097), .B0(n301), .B1(n2076), .Y(n2081) );
XNOR2X1TS U5235 ( .A(n2351), .B(n265), .Y(n2098) );
OAI22X1TS U5236 ( .A0(n2145), .A1(n2098), .B0(n2077), .B1(n2143), .Y(n2139)
);
XNOR2X1TS U5237 ( .A(n2462), .B(n279), .Y(n2104) );
XNOR2X1TS U5238 ( .A(n2462), .B(n276), .Y(n2088) );
OAI22X1TS U5239 ( .A0(n1453), .A1(n2104), .B0(n2937), .B1(n2088), .Y(n2138)
);
XNOR2X1TS U5240 ( .A(n2078), .B(n2229), .Y(n2093) );
OAI22X1TS U5241 ( .A0(n2093), .A1(n2222), .B0(n2079), .B1(n2249), .Y(n2091)
);
NOR2BX1TS U5242 ( .AN(n7813), .B(n2924), .Y(n2089) );
OAI22X1TS U5243 ( .A0(n333), .A1(n2088), .B0(n2347), .B1(n2087), .Y(n2112)
);
OAI22X1TS U5244 ( .A0(n2141), .A1(n2562), .B0(n2093), .B1(n2249), .Y(n2102)
);
XNOR2X1TS U5245 ( .A(n2219), .B(n269), .Y(n2099) );
OAI22X1TS U5246 ( .A0(n2096), .A1(n2099), .B0(n114), .B1(n2094), .Y(n2108)
);
XNOR2X1TS U5247 ( .A(n2598), .B(n281), .Y(n2105) );
OAI22X1TS U5248 ( .A0(n347), .A1(n2105), .B0(n2142), .B1(n2097), .Y(n2107)
);
XNOR2X1TS U5249 ( .A(n2351), .B(n271), .Y(n2144) );
OAI22X1TS U5250 ( .A0(n2145), .A1(n2144), .B0(n2098), .B1(n2143), .Y(n2150)
);
XNOR2X1TS U5251 ( .A(n2219), .B(n275), .Y(n2160) );
OAI22X1TS U5252 ( .A0(n347), .A1(n2101), .B0(n301), .B1(n2100), .Y(n2149) );
ADDHX1TS U5253 ( .A(n2103), .B(n2102), .CO(n2109), .S(n2159) );
XNOR2X1TS U5254 ( .A(n2462), .B(n277), .Y(n2148) );
XNOR2X1TS U5255 ( .A(n2598), .B(n2251), .Y(n2106) );
OAI22X1TS U5256 ( .A0(n347), .A1(n2106), .B0(n301), .B1(n2105), .Y(n2157) );
CMPR32X2TS U5257 ( .A(n2109), .B(n2108), .C(n2107), .CO(n2110), .S(n2151) );
CMPR32X2TS U5258 ( .A(n2124), .B(n2123), .C(n2122), .CO(n2043), .S(n2313) );
CMPR32X2TS U5259 ( .A(n2139), .B(n2138), .C(n2137), .CO(n2113), .S(n2156) );
OAI22X1TS U5260 ( .A0(n2146), .A1(n327), .B0(n2140), .B1(n2453), .Y(n2163)
);
NOR2BX1TS U5261 ( .AN(n2549), .B(n2142), .Y(n2161) );
XNOR2X1TS U5262 ( .A(n2232), .B(n269), .Y(n2179) );
OAI22X1TS U5263 ( .A0(n2145), .A1(n2179), .B0(n2144), .B1(n2143), .Y(n2175)
);
XNOR2X1TS U5264 ( .A(n271), .B(n2182), .Y(n2183) );
OAI22X1TS U5265 ( .A0(n2146), .A1(n2798), .B0(n2246), .B1(n2183), .Y(n2165)
);
XNOR2X1TS U5266 ( .A(n2462), .B(n282), .Y(n2180) );
OAI22X1TS U5267 ( .A0(n332), .A1(n2180), .B0(n2937), .B1(n2148), .Y(n2176)
);
CMPR32X2TS U5268 ( .A(n2159), .B(n2158), .C(n2157), .CO(n2152), .S(n2174) );
XNOR2X1TS U5269 ( .A(n2219), .B(n279), .Y(n2166) );
OAI22X1TS U5270 ( .A0(n325), .A1(n2166), .B0(n114), .B1(n2160), .Y(n2187) );
ADDHX1TS U5271 ( .A(n2165), .B(n2164), .CO(n2177), .S(n2197) );
XNOR2X1TS U5272 ( .A(n2219), .B(n277), .Y(n2194) );
OAI22X1TS U5273 ( .A0(n2096), .A1(n2194), .B0(n2095), .B1(n2166), .Y(n2196)
);
OAI22X1TS U5274 ( .A0(n1453), .A1(n2168), .B0(n2937), .B1(n2167), .Y(n2195)
);
CMPR32X2TS U5275 ( .A(n2171), .B(n2170), .C(n2169), .CO(n2155), .S(n2172) );
XNOR2X1TS U5276 ( .A(n2232), .B(n276), .Y(n2193) );
OAI22X1TS U5277 ( .A0(n323), .A1(n2193), .B0(n2179), .B1(n2361), .Y(n2200)
);
XNOR2X1TS U5278 ( .A(n2462), .B(n2251), .Y(n2181) );
OAI22X1TS U5279 ( .A0(n332), .A1(n2181), .B0(n2937), .B1(n2180), .Y(n2199)
);
XNOR2X1TS U5280 ( .A(n269), .B(n2182), .Y(n2191) );
OAI22X1TS U5281 ( .A0(n2246), .A1(n2191), .B0(n2183), .B1(n2453), .Y(n2207)
);
NOR2BX1TS U5282 ( .AN(n7813), .B(n2906), .Y(n2205) );
XNOR2X1TS U5283 ( .A(n2596), .B(n275), .Y(n2224) );
XNOR2X1TS U5284 ( .A(n271), .B(n2229), .Y(n2223) );
OAI22X1TS U5285 ( .A0(n2192), .A1(n2561), .B0(n2223), .B1(n2222), .Y(n2208)
);
XNOR2X1TS U5286 ( .A(n2232), .B(n279), .Y(n2210) );
OAI22X1TS U5287 ( .A0(n324), .A1(n2210), .B0(n2193), .B1(n2361), .Y(n2214)
);
XNOR2X1TS U5288 ( .A(n2219), .B(n282), .Y(n2220) );
OAI22X1TS U5289 ( .A0(n2096), .A1(n2220), .B0(n2095), .B1(n2194), .Y(n2213)
);
CMPR32X2TS U5290 ( .A(n2200), .B(n2199), .C(n2198), .CO(n2189), .S(n2202) );
NOR2X1TS U5291 ( .A(n2292), .B(n2291), .Y(n2201) );
INVX2TS U5292 ( .A(n2201), .Y(n7937) );
CMPR32X2TS U5293 ( .A(n2207), .B(n2206), .C(n2205), .CO(n2198), .S(n2218) );
XNOR2X1TS U5294 ( .A(n2232), .B(n278), .Y(n2265) );
OAI22X1TS U5295 ( .A0(n324), .A1(n2265), .B0(n2210), .B1(n2361), .Y(n2227)
);
OAI22X1TS U5296 ( .A0(n2096), .A1(n2212), .B0(n114), .B1(n2211), .Y(n2226)
);
CMPR32X2TS U5297 ( .A(n2215), .B(n2214), .C(n2213), .CO(n2204), .S(n2216) );
NOR2X1TS U5298 ( .A(n2288), .B(n2287), .Y(n7795) );
CLKBUFX2TS U5299 ( .A(n2551), .Y(n2603) );
XNOR2X1TS U5300 ( .A(n2219), .B(n2603), .Y(n2221) );
OAI22X1TS U5301 ( .A0(n2096), .A1(n2221), .B0(n114), .B1(n2220), .Y(n2279)
);
XNOR2X1TS U5302 ( .A(n269), .B(n2229), .Y(n2230) );
OAI22X1TS U5303 ( .A0(n2223), .A1(n2561), .B0(n2230), .B1(n2222), .Y(n2269)
);
XNOR2X1TS U5304 ( .A(n2596), .B(n279), .Y(n2231) );
NOR2BX1TS U5305 ( .AN(n2603), .B(n114), .Y(n2267) );
CMPR32X2TS U5306 ( .A(n2228), .B(n2227), .C(n2226), .CO(n2217), .S(n2277) );
NOR2X1TS U5307 ( .A(n7795), .B(n7942), .Y(n2290) );
XNOR2X1TS U5308 ( .A(n275), .B(n2229), .Y(n2235) );
OAI22X1TS U5309 ( .A0(n2230), .A1(n2561), .B0(n2564), .B1(n2235), .Y(n2264)
);
XNOR2X1TS U5310 ( .A(n2596), .B(n278), .Y(n2236) );
OAI22X1TS U5311 ( .A0(n2246), .A1(n2236), .B0(n2231), .B1(n2453), .Y(n2263)
);
XNOR2X1TS U5312 ( .A(n2232), .B(n2603), .Y(n2233) );
XNOR2X1TS U5313 ( .A(n2232), .B(n282), .Y(n2266) );
OAI22X1TS U5314 ( .A0(n323), .A1(n2233), .B0(n2266), .B1(n2361), .Y(n2271)
);
OAI22X1TS U5315 ( .A0(n323), .A1(n2928), .B0(n2234), .B1(n2361), .Y(n2270)
);
OAI22X1TS U5316 ( .A0(n2564), .A1(n2240), .B0(n2235), .B1(n2249), .Y(n2239)
);
NOR2BX1TS U5317 ( .AN(n7813), .B(n2352), .Y(n2238) );
XNOR2X1TS U5318 ( .A(n2596), .B(n282), .Y(n2241) );
OAI22X1TS U5319 ( .A0(n2246), .A1(n2241), .B0(n2236), .B1(n2453), .Y(n2237)
);
NOR2X1TS U5320 ( .A(n2262), .B(n2261), .Y(n7952) );
CMPR32X2TS U5321 ( .A(n2239), .B(n2238), .C(n2237), .CO(n2261), .S(n2259) );
XNOR2X1TS U5322 ( .A(n2560), .B(n277), .Y(n2247) );
OAI22X1TS U5323 ( .A0(n2564), .A1(n2247), .B0(n2240), .B1(n2249), .Y(n2244)
);
XNOR2X1TS U5324 ( .A(n2596), .B(n2551), .Y(n2242) );
OAI22X1TS U5325 ( .A0(n2246), .A1(n2242), .B0(n2241), .B1(n2453), .Y(n2243)
);
OR2X2TS U5326 ( .A(n2259), .B(n2258), .Y(n7805) );
ADDHXLTS U5327 ( .A(n2244), .B(n2243), .CO(n2258), .S(n2257) );
OAI22X1TS U5328 ( .A0(n2246), .A1(n2860), .B0(n2798), .B1(n2245), .Y(n2256)
);
XNOR2X1TS U5329 ( .A(n2560), .B(n281), .Y(n2250) );
OAI22X1TS U5330 ( .A0(n2564), .A1(n2250), .B0(n2247), .B1(n2249), .Y(n2254)
);
NOR2BX1TS U5331 ( .AN(n7813), .B(n2248), .Y(n2253) );
OAI22X1TS U5332 ( .A0(n2564), .A1(n2603), .B0(n2250), .B1(n2249), .Y(n7815)
);
NAND2X1TS U5333 ( .A(n2252), .B(n2564), .Y(n7814) );
NAND2X1TS U5334 ( .A(n7815), .B(n7814), .Y(n7816) );
NAND2X1TS U5335 ( .A(n2254), .B(n2253), .Y(n7808) );
AOI21X1TS U5336 ( .A0(n7809), .A1(n7810), .B0(n2255), .Y(n7960) );
NAND2X1TS U5337 ( .A(n2257), .B(n2256), .Y(n7958) );
OAI21X1TS U5338 ( .A0(n7957), .A1(n7960), .B0(n7958), .Y(n7806) );
NAND2X1TS U5339 ( .A(n2259), .B(n2258), .Y(n7804) );
AOI21X1TS U5340 ( .A0(n7805), .A1(n7806), .B0(n2260), .Y(n7955) );
NAND2X1TS U5341 ( .A(n2262), .B(n2261), .Y(n7953) );
OAI21X1TS U5342 ( .A0(n7952), .A1(n7955), .B0(n7953), .Y(n7802) );
ADDHXLTS U5343 ( .A(n2264), .B(n2263), .CO(n2282), .S(n2272) );
OAI22X1TS U5344 ( .A0(n324), .A1(n2266), .B0(n2265), .B1(n2361), .Y(n2281)
);
CMPR32X2TS U5345 ( .A(n2269), .B(n2268), .C(n2267), .CO(n2278), .S(n2280) );
CMPR32X2TS U5346 ( .A(n2272), .B(n2271), .C(n2270), .CO(n2274), .S(n2262) );
INVX2TS U5347 ( .A(n2273), .Y(n7801) );
NAND2X1TS U5348 ( .A(n2275), .B(n2274), .Y(n7800) );
INVX1TS U5349 ( .A(n7800), .Y(n2276) );
AOI21X1TS U5350 ( .A0(n7802), .A1(n7801), .B0(n2276), .Y(n7950) );
CMPR32X2TS U5351 ( .A(n2279), .B(n2278), .C(n2277), .CO(n2285), .S(n2284) );
CMPR32X2TS U5352 ( .A(n2282), .B(n2281), .C(n2280), .CO(n2283), .S(n2275) );
NOR2X1TS U5353 ( .A(n2284), .B(n2283), .Y(n7947) );
NAND2X1TS U5354 ( .A(n2284), .B(n2283), .Y(n7948) );
NAND2X1TS U5355 ( .A(n2288), .B(n2287), .Y(n7796) );
OAI21X1TS U5356 ( .A0(n7795), .A1(n7943), .B0(n7796), .Y(n2289) );
INVX2TS U5357 ( .A(n7792), .Y(n7936) );
NAND2X1TS U5358 ( .A(n2294), .B(n2293), .Y(n7939) );
INVX2TS U5359 ( .A(n7939), .Y(n2295) );
INVX2TS U5360 ( .A(n7783), .Y(n7925) );
NOR2X2TS U5361 ( .A(n2326), .B(n2325), .Y(n7778) );
ADDFHX2TS U5362 ( .A(n2319), .B(n2318), .CI(n2317), .CO(n2325), .S(n2324) );
ADDFHX2TS U5363 ( .A(n2322), .B(n2321), .CI(n2320), .CO(n2323), .S(n2304) );
NOR2X1TS U5364 ( .A(n2324), .B(n2323), .Y(n7920) );
NAND2X1TS U5365 ( .A(n2324), .B(n2323), .Y(n7921) );
NAND2X1TS U5366 ( .A(n2326), .B(n2325), .Y(n7779) );
OAI21X1TS U5367 ( .A0(n7778), .A1(n7921), .B0(n7779), .Y(n2327) );
NAND2X1TS U5368 ( .A(n2336), .B(n2335), .Y(n7907) );
OAI21X2TS U5369 ( .A0(n7901), .A1(n7906), .B0(n7907), .Y(n2337) );
AOI21X2TS U5370 ( .A0(n7900), .A1(n2338), .B0(n2337), .Y(n2339) );
OAI22X1TS U5371 ( .A0(n2344), .A1(n2562), .B0(n2391), .B1(n7812), .Y(n2356)
);
OAI22X1TS U5372 ( .A0(n325), .A1(n2345), .B0(n2392), .B1(n2095), .Y(n2355)
);
XNOR2X1TS U5373 ( .A(n336), .B(n2815), .Y(n2358) );
OAI22X1TS U5374 ( .A0(n344), .A1(n2346), .B0(n2638), .B1(n2358), .Y(n2354)
);
XNOR2X1TS U5375 ( .A(n2462), .B(n2795), .Y(n2357) );
OAI22X1TS U5376 ( .A0(n2349), .A1(n2348), .B0(n2347), .B1(n2357), .Y(n2368)
);
NOR2BX1TS U5377 ( .AN(n7813), .B(n2998), .Y(n2366) );
XNOR2X1TS U5378 ( .A(n2841), .B(n247), .Y(n2455) );
OAI22X1TS U5379 ( .A0(n2602), .A1(n2353), .B0(n2924), .B1(n2455), .Y(n2434)
);
XNOR2X1TS U5380 ( .A(n2462), .B(n251), .Y(n2463) );
OAI22X1TS U5381 ( .A0(n333), .A1(n2357), .B0(n2937), .B1(n2463), .Y(n2474)
);
XNOR2X1TS U5382 ( .A(n336), .B(n2865), .Y(n2450) );
OAI22X1TS U5383 ( .A0(n345), .A1(n2358), .B0(n2638), .B1(n2450), .Y(n2473)
);
XNOR2X1TS U5384 ( .A(n2598), .B(n274), .Y(n2364) );
XNOR2X1TS U5385 ( .A(n2598), .B(n2027), .Y(n2465) );
OAI22X1TS U5386 ( .A0(n347), .A1(n2364), .B0(n2464), .B1(n2465), .Y(n2472)
);
OAI22X1TS U5387 ( .A0(n2360), .A1(n327), .B0(n2359), .B1(n2609), .Y(n2407)
);
OAI22X1TS U5388 ( .A0(n348), .A1(n2365), .B0(n2464), .B1(n2364), .Y(n2405)
);
ADDHX1TS U5389 ( .A(n2370), .B(n2369), .CO(n2381), .S(n2378) );
XNOR2X1TS U5390 ( .A(n2871), .B(n277), .Y(n2396) );
OAI22X1TS U5391 ( .A0(n307), .A1(n2371), .B0(n2547), .B1(n2396), .Y(n2380)
);
XNOR2X1TS U5392 ( .A(n1666), .B(n276), .Y(n2397) );
OAI22X1TS U5393 ( .A0(n2446), .A1(n2372), .B0(n2869), .B1(n2397), .Y(n2379)
);
OAI22X1TS U5394 ( .A0(n325), .A1(n2392), .B0(n2448), .B1(n2095), .Y(n2478)
);
XNOR2X1TS U5395 ( .A(n2503), .B(n2551), .Y(n2394) );
XNOR2X1TS U5396 ( .A(n2503), .B(n282), .Y(n2480) );
OAI22X1TS U5397 ( .A0(n3000), .A1(n2394), .B0(n2587), .B1(n2480), .Y(n2475)
);
XNOR2X1TS U5398 ( .A(n740), .B(n279), .Y(n2481) );
XNOR2X1TS U5399 ( .A(n313), .B(n272), .Y(n2400) );
XNOR2X1TS U5400 ( .A(n313), .B(n264), .Y(n2432) );
OAI22X1TS U5401 ( .A0(n143), .A1(n2400), .B0(n2432), .B1(n2962), .Y(n2431)
);
XNOR2X1TS U5402 ( .A(n139), .B(n270), .Y(n2433) );
OAI22X1TS U5403 ( .A0(n2446), .A1(n2397), .B0(n2444), .B1(n2433), .Y(n2430)
);
OAI22X1TS U5404 ( .A0(n127), .A1(n2401), .B0(n2400), .B1(n2399), .Y(n2410)
);
CMPR32X2TS U5405 ( .A(n2407), .B(n2406), .C(n2405), .CO(n2471), .S(n2408) );
ADDFHX2TS U5406 ( .A(n2422), .B(n2421), .CI(n2420), .CO(n2426), .S(n2428) );
ADDFHX2TS U5407 ( .A(n2429), .B(n2428), .CI(n2427), .CO(n2533), .S(n2336) );
INVX2TS U5408 ( .A(n7769), .Y(n7891) );
XNOR2X1TS U5409 ( .A(n313), .B(n2815), .Y(n2502) );
XNOR2X1TS U5410 ( .A(n1086), .B(n272), .Y(n2445) );
XNOR2X1TS U5411 ( .A(n1223), .B(n2894), .Y(n2556) );
XNOR2X1TS U5412 ( .A(n2553), .B(n2603), .Y(n2442) );
XNOR2X1TS U5413 ( .A(n2553), .B(n282), .Y(n2649) );
NAND2BX1TS U5414 ( .AN(n2549), .B(n2862), .Y(n2443) );
OAI22X1TS U5415 ( .A0(n224), .A1(n5159), .B0(n3202), .B1(n2443), .Y(n2624)
);
XNOR2X1TS U5416 ( .A(n1666), .B(n264), .Y(n2669) );
OAI22X1TS U5417 ( .A0(n2446), .A1(n2445), .B0(n2444), .B1(n2669), .Y(n2672)
);
XNOR2X1TS U5418 ( .A(n2485), .B(n262), .Y(n2486) );
OAI22X1TS U5419 ( .A0(n344), .A1(n2450), .B0(n2638), .B1(n2486), .Y(n2456)
);
XNOR2X1TS U5420 ( .A(n1227), .B(n2897), .Y(n2484) );
OAI22X1TS U5421 ( .A0(n323), .A1(n2451), .B0(n2484), .B1(n2927), .Y(n2461)
);
XNOR2X1TS U5422 ( .A(n2452), .B(n2559), .Y(n2482) );
OAI22X1TS U5423 ( .A0(n2454), .A1(n327), .B0(n2482), .B1(n2453), .Y(n2460)
);
XNOR2X1TS U5424 ( .A(n2640), .B(n273), .Y(n2491) );
OAI22X1TS U5425 ( .A0(n2602), .A1(n2455), .B0(n1598), .B1(n2491), .Y(n2459)
);
XNOR2X1TS U5426 ( .A(n2462), .B(n2848), .Y(n2490) );
OAI22X1TS U5427 ( .A0(n332), .A1(n2463), .B0(n2490), .B1(n226), .Y(n2489) );
XNOR2X1TS U5428 ( .A(n2598), .B(n366), .Y(n2492) );
NOR2BX1TS U5429 ( .AN(n7813), .B(n5160), .Y(n2487) );
XNOR2X1TS U5430 ( .A(n2503), .B(n278), .Y(n2504) );
XNOR2X1TS U5431 ( .A(n2395), .B(n276), .Y(n2505) );
XNOR2X1TS U5432 ( .A(n2485), .B(n248), .Y(n2557) );
OAI22X1TS U5433 ( .A0(n345), .A1(n2486), .B0(n2638), .B1(n2557), .Y(n2592)
);
XNOR2X1TS U5434 ( .A(n2909), .B(n2693), .Y(n2600) );
OAI22X1TS U5435 ( .A0(n2490), .A1(n333), .B0(n2600), .B1(n226), .Y(n2623) );
XNOR2X1TS U5436 ( .A(n2640), .B(n2027), .Y(n2601) );
XNOR2X1TS U5437 ( .A(n2598), .B(n251), .Y(n2599) );
OAI22X1TS U5438 ( .A0(n348), .A1(n2492), .B0(n2955), .B1(n2599), .Y(n2621)
);
XNOR2X1TS U5439 ( .A(n313), .B(n361), .Y(n2665) );
OAI22X1TS U5440 ( .A0(n140), .A1(n2502), .B0(n2665), .B1(n2663), .Y(n2723)
);
XNOR2X1TS U5441 ( .A(n2503), .B(n279), .Y(n2651) );
XNOR2X1TS U5442 ( .A(n2871), .B(n270), .Y(n2667) );
OAI22X1TS U5443 ( .A0(n732), .A1(n2505), .B0(n2547), .B1(n2667), .Y(n2721)
);
XOR2X4TS U5444 ( .A(n2773), .B(n2514), .Y(n2542) );
ADDFHX2TS U5445 ( .A(n2517), .B(n2516), .CI(n2515), .CO(n2767), .S(n2529) );
XOR2X4TS U5446 ( .A(n2524), .B(n2523), .Y(n2531) );
OAI21X1TS U5447 ( .A0(n2530), .A1(n2529), .B0(n2531), .Y(n2525) );
OAI2BB1X1TS U5448 ( .A0N(n2529), .A1N(n2530), .B0(n2525), .Y(n2541) );
NOR2X2TS U5449 ( .A(n2542), .B(n2541), .Y(n2543) );
XOR2X4TS U5450 ( .A(n2530), .B(n2529), .Y(n2532) );
OR2X4TS U5451 ( .A(n2539), .B(n2540), .Y(n7766) );
NOR2X4TS U5452 ( .A(n7765), .B(n2545), .Y(n2546) );
NAND2X2TS U5453 ( .A(n2534), .B(n2533), .Y(n7892) );
INVX2TS U5454 ( .A(n7892), .Y(n2538) );
AOI21X4TS U5455 ( .A0(n7771), .A1(n2538), .B0(n2537), .Y(n7764) );
NAND2X1TS U5456 ( .A(n2542), .B(n2541), .Y(n7761) );
XNOR2X1TS U5457 ( .A(n2871), .B(n272), .Y(n2666) );
XNOR2X1TS U5458 ( .A(n2871), .B(n264), .Y(n2573) );
NAND2BX1TS U5459 ( .AN(n2549), .B(n2548), .Y(n2550) );
XNOR2X1TS U5460 ( .A(n2568), .B(n2551), .Y(n2552) );
XNOR2X1TS U5461 ( .A(n2568), .B(n282), .Y(n2569) );
OAI22X1TS U5462 ( .A0(n949), .A1(n2552), .B0(n295), .B1(n2569), .Y(n2675) );
XNOR2X1TS U5463 ( .A(n2553), .B(n278), .Y(n2648) );
XNOR2X1TS U5464 ( .A(n2553), .B(n279), .Y(n2570) );
XNOR2X1TS U5465 ( .A(n2866), .B(n276), .Y(n2650) );
XNOR2X1TS U5466 ( .A(n2866), .B(n270), .Y(n2572) );
XNOR2X1TS U5467 ( .A(n1227), .B(n2894), .Y(n2567) );
XNOR2X1TS U5468 ( .A(n336), .B(n273), .Y(n2613) );
XNOR2X1TS U5469 ( .A(n139), .B(n361), .Y(n2656) );
XNOR2X1TS U5470 ( .A(n1086), .B(n262), .Y(n2581) );
OAI22X1TS U5471 ( .A0(n232), .A1(n2656), .B0(n2809), .B1(n2581), .Y(n2576)
);
OAI22X1TS U5472 ( .A0(n2610), .A1(n326), .B0(n2580), .B1(n2609), .Y(n2591)
);
OAI22X1TS U5473 ( .A0(n2563), .A1(n2562), .B0(n2961), .B1(n2561), .Y(n2590)
);
NOR2BX1TS U5474 ( .AN(n2603), .B(n5180), .Y(n2585) );
XNOR2X1TS U5475 ( .A(n3200), .B(n2897), .Y(n2607) );
XNOR2X1TS U5476 ( .A(n1227), .B(n2693), .Y(n2694) );
OAI22X1TS U5477 ( .A0(n333), .A1(n2614), .B0(n2694), .B1(n226), .Y(n2583) );
OAI22X1TS U5478 ( .A0(n2565), .A1(n2564), .B0(n2563), .B1(n7812), .Y(n2653)
);
XNOR2X1TS U5479 ( .A(n2568), .B(n278), .Y(n2579) );
OAI22X1TS U5480 ( .A0(n5182), .A1(n2569), .B0(n1494), .B1(n2579), .Y(n2696)
);
XNOR2X1TS U5481 ( .A(n2862), .B(n276), .Y(n2582) );
OAI22X1TS U5482 ( .A0(n826), .A1(n2570), .B0(n5149), .B1(n2582), .Y(n2698)
);
XNOR2X1TS U5483 ( .A(n314), .B(n248), .Y(n2654) );
XNOR2X1TS U5484 ( .A(n314), .B(n273), .Y(n2577) );
OAI22X1TS U5485 ( .A0(n140), .A1(n2654), .B0(n2577), .B1(n2663), .Y(n2705)
);
XNOR2X1TS U5486 ( .A(n2866), .B(n272), .Y(n2588) );
OAI22X2TS U5487 ( .A0(n3199), .A1(n2572), .B0(n309), .B1(n2588), .Y(n2704)
);
XNOR2X1TS U5488 ( .A(n2871), .B(n2815), .Y(n2586) );
ADDFHX2TS U5489 ( .A(n2576), .B(n2575), .CI(n2574), .CO(n2835), .S(n2712) );
XNOR2X1TS U5490 ( .A(n314), .B(n252), .Y(n2797) );
OAI22X1TS U5491 ( .A0(n144), .A1(n2577), .B0(n2797), .B1(n2663), .Y(n2808)
);
XNOR2X1TS U5492 ( .A(n2882), .B(n280), .Y(n2811) );
XNOR2X1TS U5493 ( .A(n1086), .B(n248), .Y(n2810) );
OAI22X1TS U5494 ( .A0(n232), .A1(n2581), .B0(n2810), .B1(n2809), .Y(n2806)
);
OAI22X1TS U5495 ( .A0(n5151), .A1(n2582), .B0(n3202), .B1(n2812), .Y(n2805)
);
XNOR2X1TS U5496 ( .A(n2871), .B(n2865), .Y(n2814) );
XNOR2X1TS U5497 ( .A(n2866), .B(n265), .Y(n2816) );
ADDFHX2TS U5498 ( .A(n2590), .B(n2589), .CI(n2591), .CO(n2801), .S(n2575) );
ADDFHX2TS U5499 ( .A(n2594), .B(n2593), .CI(n2592), .CO(n2726), .S(n2729) );
XNOR2X1TS U5500 ( .A(n2846), .B(n2897), .Y(n2608) );
XNOR2X1TS U5501 ( .A(n2598), .B(n244), .Y(n2616) );
XNOR2X1TS U5502 ( .A(n267), .B(n2905), .Y(n2615) );
OAI22X1TS U5503 ( .A0(n332), .A1(n2600), .B0(n2615), .B1(n226), .Y(n2645) );
XNOR2X1TS U5504 ( .A(n2640), .B(n2795), .Y(n2612) );
NOR2BX1TS U5505 ( .AN(n2603), .B(n2578), .Y(n2643) );
XNOR2X1TS U5506 ( .A(n2640), .B(n251), .Y(n2642) );
OAI22X1TS U5507 ( .A0(n1586), .A1(n2612), .B0(n2641), .B1(n2642), .Y(n2630)
);
XNOR2X1TS U5508 ( .A(n252), .B(n2908), .Y(n2639) );
OAI22X1TS U5509 ( .A0(n345), .A1(n2613), .B0(n2638), .B1(n2639), .Y(n2635)
);
OAI22X1TS U5510 ( .A0(n347), .A1(n2616), .B0(n2637), .B1(n301), .Y(n2633) );
XNOR2X1TS U5511 ( .A(n266), .B(n2636), .Y(n2695) );
OAI22X1TS U5512 ( .A0(n2958), .A1(n2637), .B0(n2695), .B1(n2955), .Y(n2691)
);
XNOR2X1TS U5513 ( .A(n2640), .B(n244), .Y(n2688) );
OAI22X1TS U5514 ( .A0(n2901), .A1(n2642), .B0(n2641), .B1(n2688), .Y(n2689)
);
OAI22X1TS U5515 ( .A0(n3000), .A1(n2651), .B0(n309), .B1(n2650), .Y(n2660)
);
ADDHX1TS U5516 ( .A(n2653), .B(n2652), .CO(n2697), .S(n2702) );
OAI22X2TS U5517 ( .A0(n144), .A1(n2664), .B0(n2654), .B1(n2663), .Y(n2701)
);
XNOR2X1TS U5518 ( .A(n311), .B(n260), .Y(n2668) );
OAI22X1TS U5519 ( .A0(n232), .A1(n2668), .B0(n2869), .B1(n2656), .Y(n2700)
);
OAI22X1TS U5520 ( .A0(n307), .A1(n2667), .B0(n2547), .B1(n2666), .Y(n2674)
);
OAI22X1TS U5521 ( .A0(n232), .A1(n2669), .B0(n2869), .B1(n2668), .Y(n2673)
);
OAI22X1TS U5522 ( .A0(n2934), .A1(n2686), .B0(n2839), .B1(n2931), .Y(n2819)
);
XNOR2X1TS U5523 ( .A(n1296), .B(n2897), .Y(n2840) );
XNOR2X1TS U5524 ( .A(n228), .B(n2899), .Y(n2842) );
OAI22X1TS U5525 ( .A0(n2901), .A1(n2688), .B0(n2842), .B1(n231), .Y(n2817)
);
XNOR2X1TS U5526 ( .A(n2483), .B(n2693), .Y(n2847) );
XNOR2X1TS U5527 ( .A(n229), .B(n2911), .Y(n2850) );
OAI22X1TS U5528 ( .A0(n348), .A1(n2695), .B0(n2850), .B1(n2142), .Y(n2843)
);
ADDFHX2TS U5529 ( .A(n2708), .B(n2707), .CI(n2706), .CO(n2826), .S(n2717) );
ADDFHX2TS U5530 ( .A(n2714), .B(n2713), .CI(n2712), .CO(n2831), .S(n2715) );
ADDFHX2TS U5531 ( .A(n2720), .B(n2719), .CI(n2718), .CO(n2791), .S(n2742) );
ADDFHX2TS U5532 ( .A(n2755), .B(n2754), .CI(n2753), .CO(n2764), .S(n2778) );
NOR2X2TS U5533 ( .A(n2784), .B(n2783), .Y(n7874) );
ADDFHX2TS U5534 ( .A(n2760), .B(n2759), .CI(n2758), .CO(n2783), .S(n2782) );
NOR2X4TS U5535 ( .A(n2782), .B(n2781), .Y(n7886) );
NOR2X2TS U5536 ( .A(n2780), .B(n2779), .Y(n7856) );
AOI21X2TS U5537 ( .A0(n7867), .A1(n2788), .B0(n2787), .Y(n2789) );
OAI21X4TS U5538 ( .A0(n7854), .A1(n2790), .B0(n2789), .Y(n7172) );
XNOR2X1TS U5539 ( .A(n314), .B(n366), .Y(n2884) );
OAI22X1TS U5540 ( .A0(n127), .A1(n2797), .B0(n2884), .B1(n2796), .Y(n2858)
);
NOR2X1TS U5541 ( .A(n7672), .B(n158), .Y(n2887) );
OAI22X1TS U5542 ( .A0(n2800), .A1(n326), .B0(n2798), .B1(n2860), .Y(n2886)
);
XNOR2X1TS U5543 ( .A(n2882), .B(n276), .Y(n2883) );
XNOR2X1TS U5544 ( .A(n2862), .B(n272), .Y(n2864) );
OAI22X1TS U5545 ( .A0(n5151), .A1(n2812), .B0(n5149), .B1(n2864), .Y(n2876)
);
XNOR2X1TS U5546 ( .A(n2871), .B(n2813), .Y(n2872) );
XNOR2X1TS U5547 ( .A(n2866), .B(n2815), .Y(n2867) );
ADDFHX2TS U5548 ( .A(n2819), .B(n2818), .CI(n2817), .CO(n2879), .S(n2834) );
XNOR2X1TS U5549 ( .A(n2838), .B(n2894), .Y(n2896) );
XNOR2X1TS U5550 ( .A(n266), .B(n2841), .Y(n2900) );
OAI22X1TS U5551 ( .A0(n2901), .A1(n2842), .B0(n2900), .B1(n231), .Y(n2873)
);
XNOR2X1TS U5552 ( .A(n2846), .B(n2905), .Y(n2907) );
OAI22X1TS U5553 ( .A0(n333), .A1(n2847), .B0(n2907), .B1(n226), .Y(n2904) );
XNOR2X1TS U5554 ( .A(n2908), .B(n2848), .Y(n2910) );
XNOR2X1TS U5555 ( .A(n263), .B(n2911), .Y(n2913) );
OAI22X1TS U5556 ( .A0(n348), .A1(n2850), .B0(n2913), .B1(n301), .Y(n2902) );
XNOR2X1TS U5557 ( .A(n2862), .B(n265), .Y(n2978) );
XNOR2X1TS U5558 ( .A(n2866), .B(n361), .Y(n2999) );
OAI22X1TS U5559 ( .A0(n3199), .A1(n2867), .B0(n309), .B1(n2999), .Y(n3007)
);
XNOR2X1TS U5560 ( .A(n2871), .B(n248), .Y(n2995) );
ADDFHX2TS U5561 ( .A(n2875), .B(n2874), .CI(n2873), .CO(n2991), .S(n2893) );
XNOR2X1TS U5562 ( .A(n2882), .B(n270), .Y(n2976) );
XNOR2X1TS U5563 ( .A(n314), .B(n251), .Y(n2964) );
OAI22X1TS U5564 ( .A0(n141), .A1(n2884), .B0(n2964), .B1(n2962), .Y(n2986)
);
XOR2X4TS U5565 ( .A(n3055), .B(n3056), .Y(n2920) );
XNOR2X1TS U5566 ( .A(n257), .B(n2897), .Y(n2929) );
XNOR2X1TS U5567 ( .A(n229), .B(n2899), .Y(n2926) );
OAI22X1TS U5568 ( .A0(n2901), .A1(n2900), .B0(n2926), .B1(n1598), .Y(n3001)
);
OAI22X1TS U5569 ( .A0(n333), .A1(n2907), .B0(n2939), .B1(n226), .Y(n2947) );
XNOR2X1TS U5570 ( .A(n2909), .B(n2908), .Y(n2943) );
XNOR2X1TS U5571 ( .A(n233), .B(n2911), .Y(n2957) );
OAI22X1TS U5572 ( .A0(n348), .A1(n2913), .B0(n2957), .B1(n2142), .Y(n2945)
);
OAI22X1TS U5573 ( .A0(n1586), .A1(n2926), .B0(n2925), .B1(n1598), .Y(n2950)
);
INVX2TS U5574 ( .A(n2936), .Y(n2954) );
OAI22X1TS U5575 ( .A0(n346), .A1(n2943), .B0(n2942), .B1(n2941), .Y(n2952)
);
OAI22X1TS U5576 ( .A0(n2958), .A1(n2957), .B0(n2956), .B1(n301), .Y(n2990)
);
OAI22X1TS U5577 ( .A0(n143), .A1(n2964), .B0(n2963), .B1(n2962), .Y(n2988)
);
OAI22X1TS U5578 ( .A0(n232), .A1(n2973), .B0(n2972), .B1(n2971), .Y(n3006)
);
OAI22X1TS U5579 ( .A0(n826), .A1(n2978), .B0(n5149), .B1(n2977), .Y(n3004)
);
ADDFHX2TS U5580 ( .A(n3015), .B(n3014), .CI(n3013), .CO(n3066), .S(n3039) );
CMPR32X2TS U5581 ( .A(n3021), .B(n3020), .C(n3019), .CO(n3067), .S(n3064) );
ADDFHX4TS U5582 ( .A(n3024), .B(n3023), .CI(n3022), .CO(n3049), .S(n3045) );
XOR2X4TS U5583 ( .A(n3059), .B(n3058), .Y(n3040) );
XOR2X4TS U5584 ( .A(n3062), .B(n3040), .Y(n3135) );
NAND2X1TS U5585 ( .A(n3056), .B(n3055), .Y(n3057) );
OAI2BB1X4TS U5586 ( .A0N(n3063), .A1N(n3062), .B0(n3061), .Y(n3138) );
ADDFHX4TS U5587 ( .A(n3104), .B(n3103), .CI(n3102), .CO(n3110), .S(n3106) );
INVX2TS U5588 ( .A(n3125), .Y(n3117) );
XOR2X4TS U5589 ( .A(n3121), .B(n3120), .Y(n3123) );
XNOR2X4TS U5590 ( .A(n3123), .B(n3122), .Y(n3145) );
XNOR2X4TS U5591 ( .A(n3125), .B(n3124), .Y(n3127) );
XNOR2X4TS U5592 ( .A(n3127), .B(n3126), .Y(n3143) );
NAND2X2TS U5593 ( .A(n3136), .B(n3135), .Y(n7843) );
NAND2X4TS U5594 ( .A(n3139), .B(n3138), .Y(n7818) );
NAND2X2TS U5595 ( .A(n3141), .B(n3140), .Y(n7824) );
NAND2X2TS U5596 ( .A(n3143), .B(n3142), .Y(n7834) );
NAND2X1TS U5597 ( .A(n3145), .B(n3144), .Y(n7180) );
NAND2X2TS U5598 ( .A(n3157), .B(n3156), .Y(n7730) );
AND2X4TS U5599 ( .A(n3159), .B(n3158), .Y(n7721) );
NAND2X2TS U5600 ( .A(n3163), .B(n3162), .Y(n7712) );
INVX2TS U5601 ( .A(n7712), .Y(n7701) );
NAND2X1TS U5602 ( .A(n3168), .B(n3167), .Y(n7696) );
INVX2TS U5603 ( .A(n7696), .Y(n7155) );
OAI21X2TS U5604 ( .A0(n7709), .A1(n3176), .B0(n3175), .Y(n7146) );
INVX2TS U5605 ( .A(n7142), .Y(n6581) );
NAND2X1TS U5606 ( .A(n3182), .B(n3181), .Y(n6584) );
XNOR2X1TS U5607 ( .A(n7673), .B(n367), .Y(n5152) );
OAI22X1TS U5608 ( .A0(n299), .A1(n3197), .B0(n296), .B1(n5152), .Y(n5155) );
XNOR2X1TS U5609 ( .A(n3201), .B(n258), .Y(n5150) );
OAI22X1TS U5610 ( .A0(n3204), .A1(n3203), .B0(n5150), .B1(n3202), .Y(n5144)
);
NAND2X1TS U5611 ( .A(n3206), .B(n3205), .Y(n6565) );
INVX2TS U5612 ( .A(Data_A_i[2]), .Y(n3410) );
XOR2X1TS U5613 ( .A(Data_A_i[2]), .B(Data_A_i[1]), .Y(n3369) );
CLKBUFX2TS U5614 ( .A(n3535), .Y(n3638) );
NOR2X1TS U5615 ( .A(n3369), .B(n3367), .Y(n3575) );
CLKBUFX2TS U5616 ( .A(n3575), .Y(n4065) );
NAND2X1TS U5617 ( .A(n3295), .B(n3211), .Y(n3213) );
BUFX8TS U5618 ( .A(Data_B_i[1]), .Y(n4026) );
NAND2X2TS U5619 ( .A(n4026), .B(Data_B_i[0]), .Y(n3336) );
NAND2X1TS U5620 ( .A(Data_B_i[2]), .B(Data_B_i[3]), .Y(n3339) );
NAND2X2TS U5621 ( .A(n4026), .B(Data_B_i[2]), .Y(n3337) );
NAND2X1TS U5622 ( .A(n3339), .B(n3337), .Y(n3208) );
NAND2X1TS U5623 ( .A(Data_B_i[4]), .B(Data_B_i[5]), .Y(n3280) );
NAND2X1TS U5624 ( .A(n3280), .B(n3276), .Y(n3294) );
NAND2X1TS U5625 ( .A(Data_B_i[6]), .B(n286), .Y(n3328) );
NAND2X2TS U5626 ( .A(Data_B_i[6]), .B(n4275), .Y(n3324) );
NAND2X1TS U5627 ( .A(n3328), .B(n3324), .Y(n3210) );
OAI21X2TS U5628 ( .A0(n3213), .A1(n3233), .B0(n3212), .Y(n3241) );
NOR2X1TS U5629 ( .A(Data_B_i[9]), .B(Data_B_i[10]), .Y(n3315) );
NOR2X1TS U5630 ( .A(Data_B_i[7]), .B(n4483), .Y(n3351) );
NAND2X1TS U5631 ( .A(n3377), .B(n3217), .Y(n3219) );
NAND2X1TS U5632 ( .A(Data_B_i[9]), .B(n4483), .Y(n3353) );
NAND2X1TS U5633 ( .A(Data_B_i[10]), .B(Data_B_i[11]), .Y(n3398) );
NAND2X1TS U5634 ( .A(Data_B_i[9]), .B(Data_B_i[10]), .Y(n3390) );
NAND2X1TS U5635 ( .A(n3398), .B(n3390), .Y(n3214) );
AOI21X2TS U5636 ( .A0(n3215), .A1(n3393), .B0(n3214), .Y(n3286) );
NAND2X1TS U5637 ( .A(n4688), .B(Data_B_i[13]), .Y(n3247) );
NAND2X1TS U5638 ( .A(n4688), .B(Data_B_i[11]), .Y(n3288) );
NAND2X1TS U5639 ( .A(n3247), .B(n3288), .Y(n3376) );
NAND2X1TS U5640 ( .A(n4714), .B(n4692), .Y(n3308) );
NAND2X1TS U5641 ( .A(n4662), .B(n4692), .Y(n3382) );
NAND2X1TS U5642 ( .A(n3308), .B(n3382), .Y(n3216) );
AOI21X1TS U5643 ( .A0(n3217), .A1(n3376), .B0(n3216), .Y(n3218) );
NAND2X1TS U5644 ( .A(n4714), .B(n4815), .Y(n3413) );
NAND2X1TS U5645 ( .A(n4815), .B(n4794), .Y(n3363) );
NAND2X1TS U5646 ( .A(n3222), .B(n3363), .Y(n3223) );
XNOR2X1TS U5647 ( .A(Data_A_i[2]), .B(Data_A_i[3]), .Y(n3226) );
INVX2TS U5648 ( .A(n4418), .Y(n4297) );
CLKBUFX2TS U5649 ( .A(n3512), .Y(n4296) );
CLKBUFX2TS U5650 ( .A(n3542), .Y(n4222) );
XNOR2X1TS U5651 ( .A(Data_A_i[3]), .B(Data_A_i[4]), .Y(n3225) );
NOR2BX1TS U5652 ( .AN(n3226), .B(n3225), .Y(n3684) );
AOI222XLTS U5653 ( .A0(n4222), .A1(n4423), .B0(n335), .B1(n4715), .C0(n4150),
.C1(n4442), .Y(n3227) );
CLKBUFX2TS U5654 ( .A(n3262), .Y(n3779) );
NAND2X1TS U5655 ( .A(n320), .B(n3978), .Y(n3229) );
OAI21X1TS U5656 ( .A0(n4832), .A1(n3779), .B0(n3229), .Y(n3230) );
INVX2TS U5657 ( .A(n4975), .Y(n4444) );
XOR2X1TS U5658 ( .A(n3230), .B(n4444), .Y(n3335) );
NAND2X1TS U5659 ( .A(n192), .B(n3336), .Y(n3994) );
INVX2TS U5660 ( .A(n3262), .Y(n3992) );
AOI22X1TS U5661 ( .A0(n4828), .A1(n3992), .B0(n320), .B1(n4026), .Y(n3231)
);
XOR2X1TS U5662 ( .A(n3267), .B(n3265), .Y(n3434) );
NAND2X1TS U5663 ( .A(n3278), .B(n3276), .Y(n3235) );
NAND2BX1TS U5664 ( .AN(n3237), .B(n3238), .Y(n3348) );
CLKBUFX2TS U5665 ( .A(n3348), .Y(n4135) );
NOR2X2TS U5666 ( .A(n3238), .B(n3237), .Y(n4750) );
NOR2BX2TS U5667 ( .AN(n3237), .B(n3236), .Y(n4132) );
AND3X2TS U5668 ( .A(n3238), .B(n3237), .C(n3236), .Y(n4810) );
AOI222XLTS U5669 ( .A0(n4750), .A1(n3823), .B0(n4522), .B1(n4128), .C0(n4613), .C1(n3982), .Y(n3239) );
INVX2TS U5670 ( .A(n4788), .Y(n4264) );
XOR2X1TS U5671 ( .A(n3240), .B(n4264), .Y(n3433) );
NAND2X1TS U5672 ( .A(n3375), .B(n3289), .Y(n3245) );
INVX2TS U5673 ( .A(n3286), .Y(n3378) );
OAI21X1TS U5674 ( .A0(n3396), .A1(n3245), .B0(n3244), .Y(n3250) );
NAND2X1TS U5675 ( .A(n3248), .B(n3247), .Y(n3249) );
NAND2BX1TS U5676 ( .AN(n3253), .B(n3254), .Y(n3386) );
CLKBUFX2TS U5677 ( .A(n3386), .Y(n4467) );
NOR2X2TS U5678 ( .A(n3253), .B(n3254), .Y(n3447) );
CLKBUFX2TS U5679 ( .A(n4463), .Y(n4309) );
AND3X2TS U5680 ( .A(n3254), .B(n3253), .C(n3252), .Y(n4465) );
AOI222XLTS U5681 ( .A0(n4348), .A1(n4292), .B0(n4309), .B1(n4517), .C0(n4308), .C1(n236), .Y(n3255) );
XOR2X1TS U5682 ( .A(n3256), .B(n4468), .Y(n3432) );
NAND2X1TS U5683 ( .A(n958), .B(n3337), .Y(n3257) );
XOR2X1TS U5684 ( .A(n3257), .B(n3336), .Y(n3258) );
INVX2TS U5685 ( .A(n3258), .Y(n3988) );
INVX2TS U5686 ( .A(n3262), .Y(n3985) );
AOI222X1TS U5687 ( .A0(n4631), .A1(n3644), .B0(n4677), .B1(n3772), .C0(n4790), .C1(n3985), .Y(n3263) );
XOR2X1TS U5688 ( .A(n3264), .B(n4444), .Y(n3848) );
NAND2X1TS U5689 ( .A(n3268), .B(n3350), .Y(n3269) );
NAND2BX1TS U5690 ( .AN(n3272), .B(n3273), .Y(n3480) );
CLKBUFX2TS U5691 ( .A(n4667), .Y(n3835) );
NOR2BX2TS U5692 ( .AN(n3272), .B(n3271), .Y(n3834) );
CLKBUFX2TS U5693 ( .A(n286), .Y(n4367) );
AND3X2TS U5694 ( .A(n3273), .B(n3272), .C(n3271), .Y(n4709) );
AOI222XLTS U5695 ( .A0(n3835), .A1(n4368), .B0(n3834), .B1(n4367), .C0(n4356), .C1(n4301), .Y(n3274) );
XOR2X1TS U5696 ( .A(n3275), .B(Data_A_i[14]), .Y(n3915) );
AOI21X1TS U5697 ( .A0(n3296), .A1(n3278), .B0(n3277), .Y(n3283) );
NAND2X1TS U5698 ( .A(n3281), .B(n3280), .Y(n3282) );
CLKBUFX2TS U5699 ( .A(n4750), .Y(n4262) );
AOI222XLTS U5700 ( .A0(n4262), .A1(n3816), .B0(n4522), .B1(n4129), .C0(n4613), .C1(n283), .Y(n3284) );
NAND2X1TS U5701 ( .A(n3289), .B(n3288), .Y(n3290) );
XOR2X2TS U5702 ( .A(n3291), .B(n3290), .Y(n4520) );
CLKBUFX2TS U5703 ( .A(n3386), .Y(n3581) );
OAI21X1TS U5704 ( .A0(n4520), .A1(n3581), .B0(n3292), .Y(n3293) );
CLKBUFX2TS U5705 ( .A(Data_B_i[5]), .Y(n4275) );
AOI222XLTS U5706 ( .A0(n3835), .A1(n4276), .B0(n3834), .B1(n4275), .C0(n4448), .C1(n284), .Y(n3299) );
NAND2X1TS U5707 ( .A(n3304), .B(n3375), .Y(n3306) );
AOI21X1TS U5708 ( .A0(n3378), .A1(n3304), .B0(n3303), .Y(n3305) );
NAND2X1TS U5709 ( .A(n3309), .B(n3308), .Y(n3310) );
AOI222XLTS U5710 ( .A0(n4222), .A1(n4442), .B0(n334), .B1(n4663), .C0(n4150),
.C1(n4292), .Y(n3311) );
NAND2X1TS U5711 ( .A(n3392), .B(n3390), .Y(n3316) );
XNOR2X1TS U5712 ( .A(Data_A_i[8]), .B(Data_A_i[9]), .Y(n3320) );
XOR2X4TS U5713 ( .A(n4626), .B(Data_A_i[10]), .Y(n3321) );
CLKBUFX2TS U5714 ( .A(n3555), .Y(n3901) );
XNOR2X1TS U5715 ( .A(Data_A_i[9]), .B(Data_A_i[10]), .Y(n3319) );
CLKBUFX2TS U5716 ( .A(n3552), .Y(n3899) );
AND3X2TS U5717 ( .A(n3321), .B(n3320), .C(n3319), .Y(n4321) );
AOI222XLTS U5718 ( .A0(n3522), .A1(n4133), .B0(n3899), .B1(n239), .C0(n3898),
.C1(n4014), .Y(n3322) );
OAI21X1TS U5719 ( .A0(n4431), .A1(n3901), .B0(n3322), .Y(n3323) );
XOR2X1TS U5720 ( .A(n3323), .B(Data_A_i[11]), .Y(n3374) );
NAND2X1TS U5721 ( .A(n3329), .B(n3328), .Y(n3330) );
XNOR2X1TS U5722 ( .A(n3331), .B(n3330), .Y(n3332) );
INVX2TS U5723 ( .A(n3332), .Y(n4304) );
CLKBUFX2TS U5724 ( .A(n286), .Y(n4302) );
AOI222XLTS U5725 ( .A0(n3835), .A1(n4302), .B0(n3834), .B1(n4301), .C0(n4356), .C1(n4275), .Y(n3333) );
XOR2X1TS U5726 ( .A(n3334), .B(n4044), .Y(n3373) );
ADDHXLTS U5727 ( .A(n3335), .B(Data_A_i[20]), .CO(n3267), .S(n3361) );
NAND2X1TS U5728 ( .A(n3337), .B(n3336), .Y(n3341) );
NAND2X1TS U5729 ( .A(n3338), .B(n3339), .Y(n3340) );
CLKBUFX2TS U5730 ( .A(n3348), .Y(n4776) );
AOI222XLTS U5731 ( .A0(n4262), .A1(n3843), .B0(n4522), .B1(n3986), .C0(n4613), .C1(n3772), .Y(n3342) );
OAI21X1TS U5732 ( .A0(n3988), .A1(n4776), .B0(n3344), .Y(n3345) );
XOR2X1TS U5733 ( .A(n3345), .B(n4264), .Y(n3439) );
AOI22X1TS U5734 ( .A0(n4808), .A1(n3992), .B0(n4703), .B1(n3991), .Y(n3346)
);
OAI21X1TS U5735 ( .A0(n3994), .A1(n4776), .B0(n3346), .Y(n3347) );
XOR2X1TS U5736 ( .A(n3347), .B(n4264), .Y(n3464) );
INVX2TS U5737 ( .A(n4788), .Y(n4813) );
BUFX3TS U5738 ( .A(n3348), .Y(n4812) );
OAI21X1TS U5739 ( .A0(n4812), .A1(n3779), .B0(n199), .Y(n3349) );
XOR2X1TS U5740 ( .A(n3349), .B(n4264), .Y(n3476) );
AOI222XLTS U5741 ( .A0(n3522), .A1(n4419), .B0(n3899), .B1(n4368), .C0(n3898), .C1(n4367), .Y(n3357) );
ADDFHX2TS U5742 ( .A(n3361), .B(n3360), .CI(n3359), .CO(n3372), .S(n3461) );
NAND2X1TS U5743 ( .A(n3363), .B(n3413), .Y(n3422) );
NAND2X1TS U5744 ( .A(n4785), .B(n4794), .Y(n3419) );
NAND2X1TS U5745 ( .A(n3421), .B(n3419), .Y(n3366) );
NOR2BX1TS U5746 ( .AN(n3367), .B(n3368), .Y(n4075) );
CLKBUFX2TS U5747 ( .A(n4075), .Y(n3906) );
AND3X2TS U5748 ( .A(n3369), .B(n3368), .C(n3367), .Y(n3668) );
CLKBUFX2TS U5749 ( .A(n3668), .Y(n3794) );
AOI222XLTS U5750 ( .A0(n4065), .A1(n4526), .B0(n3906), .B1(Data_B_i[17]),
.C0(n3794), .C1(n4410), .Y(n3370) );
NAND2X1TS U5751 ( .A(n3375), .B(n3377), .Y(n3380) );
AOI21X1TS U5752 ( .A0(n3378), .A1(n3377), .B0(n3376), .Y(n3379) );
OAI21X1TS U5753 ( .A0(n3396), .A1(n3380), .B0(n3379), .Y(n3385) );
NAND2X1TS U5754 ( .A(n3383), .B(n3382), .Y(n3384) );
CLKBUFX2TS U5755 ( .A(n3386), .Y(n4408) );
CLKBUFX2TS U5756 ( .A(n4463), .Y(n4009) );
AOI222XLTS U5757 ( .A0(n4348), .A1(n4372), .B0(n4009), .B1(n4619), .C0(n4465), .C1(n4618), .Y(n3387) );
INVX2TS U5758 ( .A(n3251), .Y(n3832) );
NAND2X1TS U5759 ( .A(n3389), .B(n3392), .Y(n3395) );
AOI21X1TS U5760 ( .A0(n3393), .A1(n3392), .B0(n3391), .Y(n3394) );
NAND2X1TS U5761 ( .A(n3399), .B(n3398), .Y(n3400) );
XOR2X1TS U5762 ( .A(n3401), .B(n3400), .Y(n4487) );
AOI222XLTS U5763 ( .A0(n3522), .A1(n4516), .B0(n3899), .B1(n4429), .C0(n3898), .C1(n4419), .Y(n3402) );
XOR2X1TS U5764 ( .A(n3403), .B(n4626), .Y(n3931) );
NOR2X1TS U5765 ( .A(n3404), .B(n3425), .Y(n3406) );
NAND2X1TS U5766 ( .A(n3418), .B(n3406), .Y(n3855) );
NAND2X1TS U5767 ( .A(n4785), .B(n241), .Y(n3426) );
NAND2X1TS U5768 ( .A(n3426), .B(n3419), .Y(n3405) );
AOI21X2TS U5769 ( .A0(n3406), .A1(n3422), .B0(n3405), .Y(n3863) );
NAND2X1TS U5770 ( .A(n241), .B(n4934), .Y(n3871) );
NAND2X1TS U5771 ( .A(n3873), .B(n3871), .Y(n3407) );
CLKBUFX2TS U5772 ( .A(n3535), .Y(n4105) );
CLKBUFX2TS U5773 ( .A(n4075), .Y(n3809) );
CLKBUFX2TS U5774 ( .A(n3668), .Y(n4103) );
AOI222XLTS U5775 ( .A0(n4065), .A1(n4651), .B0(n3809), .B1(n4795), .C0(n4103), .C1(n4526), .Y(n3409) );
OAI21X1TS U5776 ( .A0(n4773), .A1(n4105), .B0(n3409), .Y(n3411) );
INVX2TS U5777 ( .A(n3410), .Y(n3796) );
NAND2X1TS U5778 ( .A(n3414), .B(n3413), .Y(n3415) );
AOI222XLTS U5779 ( .A0(n4222), .A1(n4410), .B0(n335), .B1(n4693), .C0(n4150),
.C1(n4372), .Y(n3416) );
NAND2X1TS U5780 ( .A(n3418), .B(n3421), .Y(n3424) );
AOI21X1TS U5781 ( .A0(n3422), .A1(n3421), .B0(n3420), .Y(n3423) );
NAND2X1TS U5782 ( .A(n3427), .B(n3426), .Y(n3428) );
AOI222XLTS U5783 ( .A0(n3575), .A1(n4630), .B0(n3809), .B1(n4818), .C0(n4103), .C1(n4423), .Y(n3430) );
OAI21X1TS U5784 ( .A0(n4797), .A1(n3638), .B0(n3430), .Y(n3431) );
CMPR32X2TS U5785 ( .A(n3437), .B(n3436), .C(n3435), .CO(n3949), .S(n3459) );
ADDHX1TS U5786 ( .A(n3439), .B(n3438), .CO(n3359), .S(n3471) );
AOI222XLTS U5787 ( .A0(n3522), .A1(n4014), .B0(n3899), .B1(n4302), .C0(n3898), .C1(n3828), .Y(n3440) );
XOR2X1TS U5788 ( .A(n3441), .B(n4626), .Y(n3470) );
CLKBUFX2TS U5789 ( .A(n3834), .Y(n4470) );
AOI222XLTS U5790 ( .A0(n3835), .A1(n4246), .B0(n4470), .B1(n284), .C0(n4448),
.C1(n283), .Y(n3442) );
XOR2X1TS U5791 ( .A(n3443), .B(n4044), .Y(n3469) );
CLKBUFX2TS U5792 ( .A(n3447), .Y(n3566) );
AOI222XLTS U5793 ( .A0(n3566), .A1(n236), .B0(n4309), .B1(n4429), .C0(n4308),
.C1(n238), .Y(n3448) );
AOI222XLTS U5794 ( .A0(n4222), .A1(n4372), .B0(n335), .B1(n4619), .C0(n202),
.C1(n4618), .Y(n3450) );
OAI21X1TS U5795 ( .A0(n4665), .A1(n4296), .B0(n3450), .Y(n3451) );
AOI222XLTS U5796 ( .A0(n3575), .A1(n4423), .B0(n3906), .B1(n4715), .C0(n3794), .C1(n4442), .Y(n3452) );
OAI21X1TS U5797 ( .A0(n4744), .A1(n3638), .B0(n3452), .Y(n3453) );
CMPR32X2TS U5798 ( .A(n3456), .B(n3455), .C(n3454), .CO(n3959), .S(n3457) );
ADDHXLTS U5799 ( .A(n3464), .B(n3463), .CO(n3438), .S(n3499) );
AOI222XLTS U5800 ( .A0(n3835), .A1(n4129), .B0(n4470), .B1(n283), .C0(n4448),
.C1(n3982), .Y(n3465) );
XOR2X1TS U5801 ( .A(n3466), .B(n4044), .Y(n3498) );
CLKBUFX2TS U5802 ( .A(n3512), .Y(n4241) );
CLKBUFX2TS U5803 ( .A(n202), .Y(n4115) );
CMPR32X2TS U5804 ( .A(n3471), .B(n3470), .C(n3469), .CO(n3488), .S(n3507) );
AOI222XLTS U5805 ( .A0(n3566), .A1(n4133), .B0(n4309), .B1(n4419), .C0(n4308), .C1(n4014), .Y(n3472) );
AOI222XLTS U5806 ( .A0(n3522), .A1(n4367), .B0(n3899), .B1(n4276), .C0(n3898), .C1(n3816), .Y(n3474) );
ADDHXLTS U5807 ( .A(n4813), .B(n3476), .CO(n3463), .S(n3517) );
CLKBUFX2TS U5808 ( .A(n3480), .Y(n4711) );
CLKBUFX2TS U5809 ( .A(Data_B_i[2]), .Y(n3982) );
OAI21XLTS U5810 ( .A0(n963), .A1(n4711), .B0(n3477), .Y(n3478) );
XOR2X1TS U5811 ( .A(n3478), .B(n4044), .Y(n3516) );
OAI21X1TS U5812 ( .A0(n3994), .A1(n4711), .B0(n190), .Y(n3479) );
NAND2X1TS U5813 ( .A(n322), .B(n3992), .Y(n3481) );
XOR2X1TS U5814 ( .A(n3482), .B(n4044), .Y(n3549) );
AOI222X1TS U5815 ( .A0(n3835), .A1(n3986), .B0(n4470), .B1(n3772), .C0(n4448), .C1(n3985), .Y(n3483) );
OAI21X1TS U5816 ( .A0(n3988), .A1(n4711), .B0(n3483), .Y(n3484) );
XOR2X1TS U5817 ( .A(n3484), .B(n4044), .Y(n3518) );
CMPR32X2TS U5818 ( .A(n3487), .B(n3488), .C(n3486), .CO(n3458), .S(n3489) );
NOR2X2TS U5819 ( .A(n3747), .B(n3746), .Y(n7608) );
CMPR32X2TS U5820 ( .A(n3494), .B(n3493), .C(n3492), .CO(n3486), .S(n3511) );
AOI222XLTS U5821 ( .A0(n3575), .A1(n4410), .B0(n3906), .B1(n4693), .C0(n3794), .C1(n4372), .Y(n3495) );
AOI222XLTS U5822 ( .A0(n3522), .A1(n3828), .B0(n3899), .B1(n4246), .C0(n4321), .C1(n3823), .Y(n3500) );
AOI222XLTS U5823 ( .A0(n3669), .A1(n4442), .B0(n3906), .B1(n4663), .C0(n3794), .C1(n4292), .Y(n3502) );
OAI21X1TS U5824 ( .A0(n4695), .A1(n3638), .B0(n3502), .Y(n3503) );
AOI222XLTS U5825 ( .A0(n3566), .A1(n238), .B0(n4309), .B1(n4368), .C0(n4308),
.C1(n4367), .Y(n3504) );
NOR2X2TS U5826 ( .A(n3745), .B(n3744), .Y(n7600) );
CMPR32X2TS U5827 ( .A(n3511), .B(n3510), .C(n3509), .CO(n3744), .S(n3743) );
CLKBUFX2TS U5828 ( .A(n3512), .Y(n3686) );
CLKBUFX2TS U5829 ( .A(n3542), .Y(n4151) );
AOI222XLTS U5830 ( .A0(n4151), .A1(Data_B_i[12]), .B0(n3684), .B1(n235),
.C0(n4115), .C1(n4133), .Y(n3513) );
CMPR32X2TS U5831 ( .A(n3517), .B(n3516), .C(n3515), .CO(n3525), .S(n3728) );
AOI222XLTS U5832 ( .A0(n3566), .A1(n4014), .B0(n4309), .B1(n4302), .C0(n4308), .C1(n3828), .Y(n3520) );
AOI222XLTS U5833 ( .A0(n3522), .A1(n3816), .B0(n3552), .B1(n4129), .C0(n4321), .C1(n3843), .Y(n3523) );
CMPR32X2TS U5834 ( .A(n3527), .B(n3526), .C(n3525), .CO(n3506), .S(n3719) );
CMPR32X2TS U5835 ( .A(n3530), .B(n3529), .C(n3528), .CO(n3510), .S(n3718) );
NOR2X1TS U5836 ( .A(n3743), .B(n3742), .Y(n7521) );
NAND2X1TS U5837 ( .A(n3751), .B(n7606), .Y(n3753) );
CLKBUFX2TS U5838 ( .A(n3553), .Y(n4426) );
OAI21X1TS U5839 ( .A0(n116), .A1(n3901), .B0(n3533), .Y(n3534) );
XOR2X1TS U5840 ( .A(n3534), .B(n3761), .Y(n3596) );
CLKBUFX2TS U5841 ( .A(n3535), .Y(n3671) );
AOI222XLTS U5842 ( .A0(n3575), .A1(n4292), .B0(n4075), .B1(n4517), .C0(n3668), .C1(n236), .Y(n3536) );
AOI222XLTS U5843 ( .A0(n3566), .A1(n3828), .B0(n4309), .B1(n4246), .C0(n4021), .C1(n3823), .Y(n3538) );
AOI222XLTS U5844 ( .A0(n4065), .A1(n4618), .B0(n3809), .B1(n4516), .C0(n3668), .C1(n4133), .Y(n3540) );
AOI222XLTS U5845 ( .A0(n3542), .A1(n239), .B0(n3684), .B1(n4368), .C0(n4115),
.C1(n4367), .Y(n3543) );
AOI222XLTS U5846 ( .A0(n3542), .A1(n4133), .B0(n3684), .B1(n4419), .C0(n4115), .C1(n4014), .Y(n3545) );
AOI222XLTS U5847 ( .A0(n3566), .A1(n4367), .B0(n4309), .B1(n4276), .C0(n4308), .C1(n3816), .Y(n3547) );
CLKBUFX2TS U5848 ( .A(n3555), .Y(n4625) );
AOI222XLTS U5849 ( .A0(n4426), .A1(n3843), .B0(n3899), .B1(n3986), .C0(n3898), .C1(n3991), .Y(n3550) );
XOR2X1TS U5850 ( .A(n3551), .B(n3761), .Y(n3560) );
CLKBUFX2TS U5851 ( .A(n3552), .Y(n4538) );
XOR2X1TS U5852 ( .A(n3554), .B(n3761), .Y(n3579) );
CLKBUFX2TS U5853 ( .A(n3555), .Y(n4541) );
XOR2X1TS U5854 ( .A(n3556), .B(n3761), .Y(n3674) );
XOR2X1TS U5855 ( .A(n3558), .B(n3761), .Y(n3562) );
CMPR32X2TS U5856 ( .A(n3561), .B(n3560), .C(n3559), .CO(n3598), .S(n3574) );
AOI222XLTS U5857 ( .A0(n3542), .A1(n4014), .B0(n3684), .B1(n4302), .C0(n4115), .C1(n3828), .Y(n3564) );
XOR2X1TS U5858 ( .A(n3565), .B(n4242), .Y(n3586) );
AOI222XLTS U5859 ( .A0(n3566), .A1(n3816), .B0(n4009), .B1(n4129), .C0(n4021), .C1(n3843), .Y(n3567) );
CMPR32X2TS U5860 ( .A(n3571), .B(n3570), .C(n3569), .CO(n3602), .S(n3572) );
CMPR32X2TS U5861 ( .A(n3574), .B(n3573), .C(n3572), .CO(n3711), .S(n3710) );
CLKBUFX2TS U5862 ( .A(n3575), .Y(n3669) );
AOI222XLTS U5863 ( .A0(n3669), .A1(n236), .B0(n3809), .B1(n4429), .C0(n3668),
.C1(n238), .Y(n3576) );
AOI222XLTS U5864 ( .A0(n4348), .A1(n3823), .B0(n4009), .B1(n4128), .C0(n4021), .C1(n3644), .Y(n3580) );
XOR2X1TS U5865 ( .A(n3582), .B(n3832), .Y(n3692) );
AOI222XLTS U5866 ( .A0(n3669), .A1(n4133), .B0(n3809), .B1(n4419), .C0(n3668), .C1(n4014), .Y(n3583) );
CMPR32X2TS U5867 ( .A(n3587), .B(n3586), .C(n3585), .CO(n3573), .S(n3697) );
CMPR32X2TS U5868 ( .A(n3590), .B(n3589), .C(n3588), .CO(n3727), .S(n3735) );
AOI222XLTS U5869 ( .A0(n3669), .A1(n4372), .B0(n3906), .B1(n4619), .C0(n4103), .C1(n4618), .Y(n3591) );
AOI222XLTS U5870 ( .A0(n3542), .A1(n235), .B0(n3684), .B1(n4429), .C0(n4115),
.C1(n239), .Y(n3593) );
CMPR32X2TS U5871 ( .A(n3597), .B(n3596), .C(n3595), .CO(n3724), .S(n3603) );
CMPR32X2TS U5872 ( .A(n3600), .B(n3599), .C(n3598), .CO(n3733), .S(n3601) );
NAND2X1TS U5873 ( .A(n7622), .B(n7625), .Y(n3717) );
OAI21X1TS U5874 ( .A0(n4467), .A1(n3779), .B0(n975), .Y(n3605) );
XOR2X1TS U5875 ( .A(n3605), .B(n3832), .Y(n3610) );
AOI222XLTS U5876 ( .A0(n4222), .A1(n3823), .B0(n334), .B1(n4128), .C0(n4150),
.C1(n3644), .Y(n3606) );
AOI222XLTS U5877 ( .A0(n3669), .A1(n286), .B0(n3809), .B1(n4276), .C0(n3668),
.C1(n3816), .Y(n3608) );
INVX2TS U5878 ( .A(n3410), .Y(n3672) );
ADDHXLTS U5879 ( .A(n4468), .B(n3610), .CO(n3620), .S(n3630) );
AOI222XLTS U5880 ( .A0(n4222), .A1(n3843), .B0(n334), .B1(n3986), .C0(n4150),
.C1(n3991), .Y(n3611) );
AOI222XLTS U5881 ( .A0(n4222), .A1(n3644), .B0(n335), .B1(n3772), .C0(n4150),
.C1(n3985), .Y(n3613) );
AOI22X1TS U5882 ( .A0(n334), .A1(n3992), .B0(n4151), .B1(n3991), .Y(n3615)
);
OAI21XLTS U5883 ( .A0(n3994), .A1(n4296), .B0(n3615), .Y(n3616) );
OAI21X1TS U5884 ( .A0(n4241), .A1(n3779), .B0(n983), .Y(n3617) );
XOR2X1TS U5885 ( .A(n3617), .B(n303), .Y(n3640) );
NOR2X1TS U5886 ( .A(n3661), .B(n3660), .Y(n7643) );
ADDHXLTS U5887 ( .A(n3621), .B(n3620), .CO(n3677), .S(n3627) );
AOI222XLTS U5888 ( .A0(n3669), .A1(n4014), .B0(n3809), .B1(n4302), .C0(n3668), .C1(n3828), .Y(n3622) );
AOI222XLTS U5889 ( .A0(n3542), .A1(n3816), .B0(n334), .B1(n4129), .C0(n4150),
.C1(n3843), .Y(n3623) );
CMPR32X2TS U5890 ( .A(n3627), .B(n3626), .C(n3625), .CO(n3662), .S(n3661) );
CMPR32X2TS U5891 ( .A(n3630), .B(n3629), .C(n3628), .CO(n3660), .S(n3659) );
AOI222XLTS U5892 ( .A0(n3669), .A1(n3828), .B0(n3809), .B1(n4246), .C0(n3794), .C1(n3823), .Y(n3631) );
NOR2X1TS U5893 ( .A(n3659), .B(n3658), .Y(n7648) );
AOI222XLTS U5894 ( .A0(n3575), .A1(n3644), .B0(n3906), .B1(n3772), .C0(n3794), .C1(n3985), .Y(n3633) );
INVX2TS U5895 ( .A(n3410), .Y(n4106) );
XNOR2X1TS U5896 ( .A(n3634), .B(n4106), .Y(n7659) );
NAND2X1TS U5897 ( .A(n7551), .B(n7552), .Y(n7658) );
AOI222XLTS U5898 ( .A0(n3669), .A1(n3843), .B0(n3906), .B1(n3986), .C0(n3794), .C1(n3991), .Y(n3637) );
ADDHXLTS U5899 ( .A(n4297), .B(n3640), .CO(n3647), .S(n3641) );
NAND2X1TS U5900 ( .A(n3642), .B(n3641), .Y(n7547) );
AOI21X1TS U5901 ( .A0(n7549), .A1(n7548), .B0(n3643), .Y(n7657) );
AOI222XLTS U5902 ( .A0(n3575), .A1(n3823), .B0(n3906), .B1(n4128), .C0(n3794), .C1(n3644), .Y(n3645) );
ADDHXLTS U5903 ( .A(n3648), .B(n3647), .CO(n3653), .S(n3649) );
NAND2X1TS U5904 ( .A(n3650), .B(n3649), .Y(n7654) );
OAI21X1TS U5905 ( .A0(n7657), .A1(n7653), .B0(n7654), .Y(n7545) );
AOI222XLTS U5906 ( .A0(n3669), .A1(n3816), .B0(n3906), .B1(n4129), .C0(n3794), .C1(n3843), .Y(n3651) );
ADDHXLTS U5907 ( .A(n3654), .B(n3653), .CO(n3628), .S(n3655) );
NAND2X1TS U5908 ( .A(n3656), .B(n3655), .Y(n7544) );
AOI21X1TS U5909 ( .A0(n7545), .A1(n193), .B0(n3657), .Y(n7651) );
NAND2X1TS U5910 ( .A(n3659), .B(n3658), .Y(n7649) );
OAI21X1TS U5911 ( .A0(n7648), .A1(n7651), .B0(n7649), .Y(n7538) );
NAND2X1TS U5912 ( .A(n3661), .B(n3660), .Y(n7644) );
NAND2X1TS U5913 ( .A(n3663), .B(n3662), .Y(n7540) );
OAI21X1TS U5914 ( .A0(n7539), .A1(n7644), .B0(n7540), .Y(n3664) );
AOI222XLTS U5915 ( .A0(n3542), .A1(n3828), .B0(n3684), .B1(n4246), .C0(n4150), .C1(n3823), .Y(n3666) );
AOI222XLTS U5916 ( .A0(n3669), .A1(n239), .B0(n3809), .B1(n4368), .C0(n3668),
.C1(n4367), .Y(n3670) );
AOI222XLTS U5917 ( .A0(n4348), .A1(n3843), .B0(n4009), .B1(n3986), .C0(n4021), .C1(n3991), .Y(n3675) );
XOR2X1TS U5918 ( .A(n3676), .B(n3832), .Y(n3689) );
NOR2X1TS U5919 ( .A(n3683), .B(n3682), .Y(n7638) );
NAND2X1TS U5920 ( .A(n3683), .B(n3682), .Y(n7639) );
AOI222XLTS U5921 ( .A0(n3542), .A1(Data_B_i[7]), .B0(n3684), .B1(n4276),
.C0(n4115), .C1(n3816), .Y(n3685) );
CMPR32X2TS U5922 ( .A(n3690), .B(n3689), .C(n3688), .CO(n3701), .S(n3694) );
CMPR32X2TS U5923 ( .A(n3693), .B(n3692), .C(n3691), .CO(n3698), .S(n3700) );
CMPR32X2TS U5924 ( .A(n3696), .B(n3695), .C(n3694), .CO(n3703), .S(n3683) );
CMPR32X2TS U5925 ( .A(n3699), .B(n3698), .C(n3697), .CO(n3709), .S(n3706) );
CMPR32X2TS U5926 ( .A(n3702), .B(n3701), .C(n3700), .CO(n3705), .S(n3704) );
NAND2X1TS U5927 ( .A(n3704), .B(n3703), .Y(n7634) );
NAND2X1TS U5928 ( .A(n3706), .B(n3705), .Y(n7534) );
OAI21X1TS U5929 ( .A0(n7533), .A1(n7634), .B0(n7534), .Y(n3707) );
NAND2X1TS U5930 ( .A(n3714), .B(n3713), .Y(n7624) );
OAI21X2TS U5931 ( .A0(n3717), .A1(n7529), .B0(n3716), .Y(n7523) );
CMPR32X2TS U5932 ( .A(n3720), .B(n3719), .C(n3718), .CO(n3742), .S(n3739) );
CMPR32X2TS U5933 ( .A(n3723), .B(n3722), .C(n3721), .CO(n3528), .S(n3732) );
CMPR32X2TS U5934 ( .A(n3726), .B(n3725), .C(n3724), .CO(n3731), .S(n3734) );
CMPR32X2TS U5935 ( .A(n3729), .B(n3728), .C(n3727), .CO(n3720), .S(n3730) );
NOR2X1TS U5936 ( .A(n7524), .B(n7628), .Y(n3741) );
NAND2X1TS U5937 ( .A(n3737), .B(n3736), .Y(n7629) );
NAND2X1TS U5938 ( .A(n3739), .B(n3738), .Y(n7525) );
AOI21X2TS U5939 ( .A0(n7523), .A1(n3741), .B0(n3740), .Y(n7520) );
NAND2X2TS U5940 ( .A(n3743), .B(n3742), .Y(n7597) );
NAND2X1TS U5941 ( .A(n3745), .B(n3744), .Y(n7601) );
OAI21X2TS U5942 ( .A0(n7600), .A1(n7597), .B0(n7601), .Y(n7605) );
NAND2X1TS U5943 ( .A(n3747), .B(n3746), .Y(n7609) );
NAND2X1TS U5944 ( .A(n3749), .B(n3748), .Y(n7593) );
AOI21X1TS U5945 ( .A0(n3751), .A1(n7605), .B0(n3750), .Y(n3752) );
OAI21X2TS U5946 ( .A0(n3753), .A1(n7520), .B0(n3752), .Y(n7500) );
AOI222XLTS U5947 ( .A0(n4631), .A1(n3828), .B0(n4525), .B1(n4246), .C0(n4790), .C1(n284), .Y(n3755) );
AOI222XLTS U5948 ( .A0(n4262), .A1(n239), .B0(n4132), .B1(n4368), .C0(n4749),
.C1(n286), .Y(n3758) );
AOI222XLTS U5949 ( .A0(n4426), .A1(n4372), .B0(n3552), .B1(n4619), .C0(n4623), .C1(n4618), .Y(n3760) );
XOR2X1TS U5950 ( .A(n3762), .B(n3761), .Y(n3894) );
AOI222XLTS U5951 ( .A0(n3835), .A1(n4516), .B0(n3834), .B1(n287), .C0(n4356),
.C1(n239), .Y(n3763) );
XOR2X1TS U5952 ( .A(n3764), .B(Data_A_i[14]), .Y(n3893) );
AOI222XLTS U5953 ( .A0(n4348), .A1(n4423), .B0(n4009), .B1(n4715), .C0(n4021), .C1(n4442), .Y(n3765) );
XOR2X1TS U5954 ( .A(n3766), .B(n302), .Y(n3892) );
CLKBUFX2TS U5955 ( .A(Data_B_i[11]), .Y(n4516) );
AOI222XLTS U5956 ( .A0(n322), .A1(n4517), .B0(n3834), .B1(n235), .C0(n4356),
.C1(n287), .Y(n3767) );
NAND2BX1TS U5957 ( .AN(n3770), .B(n3771), .Y(n4017) );
BUFX3TS U5958 ( .A(n4017), .Y(n5000) );
CLKBUFX2TS U5959 ( .A(n4018), .Y(n4935) );
NOR2BX2TS U5960 ( .AN(n3770), .B(n3769), .Y(n4438) );
INVX2TS U5961 ( .A(n5077), .Y(n4548) );
XOR2X1TS U5962 ( .A(n3774), .B(n4548), .Y(n4143) );
NAND2BX1TS U5963 ( .AN(n3980), .B(n3981), .Y(n4027) );
NOR2X2TS U5964 ( .A(n3981), .B(n3980), .Y(n5063) );
NAND2X1TS U5965 ( .A(n5063), .B(n3978), .Y(n3775) );
OAI21X1TS U5966 ( .A0(n5083), .A1(n3779), .B0(n3775), .Y(n3776) );
XOR2X1TS U5967 ( .A(n3776), .B(n5066), .Y(n3990) );
INVX2TS U5968 ( .A(n5077), .Y(n5001) );
BUFX3TS U5969 ( .A(n4017), .Y(n4979) );
OAI21X1TS U5970 ( .A0(n4979), .A1(n3779), .B0(n3778), .Y(n3780) );
XOR2X1TS U5971 ( .A(n3780), .B(n4548), .Y(n3846) );
AOI222X1TS U5972 ( .A0(n4935), .A1(n3986), .B0(n4823), .B1(Data_B_i[1]),
.C0(n341), .C1(n3985), .Y(n3781) );
NOR2BX2TS U5973 ( .AN(n3815), .B(n3783), .Y(n4141) );
AOI222XLTS U5974 ( .A0(n3447), .A1(n4526), .B0(n4009), .B1(n4816), .C0(n4021), .C1(n4410), .Y(n3784) );
AOI222XLTS U5975 ( .A0(n4348), .A1(n4410), .B0(n4009), .B1(n4693), .C0(n4021), .C1(n4372), .Y(n3786) );
XOR2X1TS U5976 ( .A(n3787), .B(n302), .Y(n3911) );
NOR2X1TS U5977 ( .A(n3788), .B(n3877), .Y(n3854) );
NAND2X1TS U5978 ( .A(n3870), .B(n3854), .Y(n3790) );
NAND2X1TS U5979 ( .A(n4972), .B(n4934), .Y(n3878) );
NAND2X1TS U5980 ( .A(n3878), .B(n3871), .Y(n3859) );
AOI21X1TS U5981 ( .A0(n3874), .A1(n3854), .B0(n3859), .Y(n3789) );
NOR2X1TS U5982 ( .A(n4972), .B(n4997), .Y(n3853) );
NAND2X1TS U5983 ( .A(n4972), .B(n4997), .Y(n3856) );
NAND2X1TS U5984 ( .A(n3791), .B(n3856), .Y(n3792) );
AOI222XLTS U5985 ( .A0(n4065), .A1(n4722), .B0(n4075), .B1(n4824), .C0(n3794), .C1(n4651), .Y(n3795) );
XOR2X1TS U5986 ( .A(n3797), .B(n3796), .Y(n3910) );
AOI222XLTS U5987 ( .A0(n4222), .A1(n4630), .B0(n334), .B1(n4818), .C0(n202),
.C1(n4423), .Y(n3798) );
NOR2XLTS U5988 ( .A(n3800), .B(n3853), .Y(n3803) );
NAND2X1TS U5989 ( .A(n3803), .B(n3870), .Y(n3805) );
OAI21XLTS U5990 ( .A0(n3801), .A1(n3853), .B0(n3856), .Y(n3802) );
AOI21X1TS U5991 ( .A0(n3874), .A1(n3803), .B0(n3802), .Y(n3804) );
OAI21X1TS U5992 ( .A0(n308), .A1(n3805), .B0(n3804), .Y(n3808) );
NAND2X1TS U5993 ( .A(n3806), .B(n3857), .Y(n3807) );
AOI222XLTS U5994 ( .A0(n4065), .A1(n4753), .B0(n3809), .B1(n4938), .C0(n4103), .C1(n4678), .Y(n3810) );
OAI21X1TS U5995 ( .A0(n4941), .A1(n4105), .B0(n3810), .Y(n3811) );
XOR2X1TS U5996 ( .A(n3811), .B(n4106), .Y(n3851) );
AOI222XLTS U5997 ( .A0(n4151), .A1(n4651), .B0(n335), .B1(n4795), .C0(n4115),
.C1(n4526), .Y(n3812) );
OAI21X1TS U5998 ( .A0(n4773), .A1(n4241), .B0(n3812), .Y(n3813) );
XOR2X1TS U5999 ( .A(n3813), .B(n4297), .Y(n3850) );
AOI222XLTS U6000 ( .A0(n4631), .A1(n3816), .B0(n4677), .B1(n4129), .C0(n4790), .C1(n283), .Y(n3817) );
XOR2X1TS U6001 ( .A(n3818), .B(n4444), .Y(n3884) );
AOI222XLTS U6002 ( .A0(n4262), .A1(n4014), .B0(n4132), .B1(n4302), .C0(n4749), .C1(n4301), .Y(n3819) );
XOR2X1TS U6003 ( .A(n3820), .B(n4813), .Y(n3883) );
AOI222XLTS U6004 ( .A0(n4631), .A1(n3823), .B0(n4677), .B1(n4128), .C0(n4790), .C1(n3982), .Y(n3824) );
XOR2X1TS U6005 ( .A(n3825), .B(n4444), .Y(n3887) );
AOI222XLTS U6006 ( .A0(n3835), .A1(n4429), .B0(n3834), .B1(n239), .C0(n4356),
.C1(n4483), .Y(n3826) );
AOI222XLTS U6007 ( .A0(n4262), .A1(n3828), .B0(n4132), .B1(n4246), .C0(n4613), .C1(n284), .Y(n3829) );
XOR2X1TS U6008 ( .A(n3830), .B(n4264), .Y(n3919) );
XOR2X1TS U6009 ( .A(n3833), .B(n3832), .Y(n3918) );
AOI222XLTS U6010 ( .A0(n3835), .A1(n239), .B0(n3834), .B1(Data_B_i[8]), .C0(
n4356), .C1(n286), .Y(n3836) );
XOR2X1TS U6011 ( .A(n3838), .B(Data_A_i[14]), .Y(n3917) );
AOI222XLTS U6012 ( .A0(n4426), .A1(n4292), .B0(n4538), .B1(n4517), .C0(n3898), .C1(n235), .Y(n3839) );
OAI21X1TS U6013 ( .A0(n4621), .A1(n4541), .B0(n3839), .Y(n3840) );
AOI222XLTS U6014 ( .A0(n4262), .A1(n4367), .B0(n4132), .B1(n4276), .C0(n4749), .C1(n4275), .Y(n3841) );
AOI222XLTS U6015 ( .A0(n320), .A1(n3843), .B0(n4677), .B1(n3986), .C0(n4850),
.C1(n3991), .Y(n3844) );
ADDHX1TS U6016 ( .A(n3848), .B(n3847), .CO(n3903), .S(n3916) );
NAND2X1TS U6017 ( .A(n3854), .B(n3860), .Y(n3862) );
NOR2X2TS U6018 ( .A(n3855), .B(n3862), .Y(n4093) );
NAND2X1TS U6019 ( .A(n3857), .B(n3856), .Y(n3858) );
AOI21X1TS U6020 ( .A0(n3860), .A1(n3859), .B0(n3858), .Y(n3861) );
OAI21X2TS U6021 ( .A0(n3863), .A1(n3862), .B0(n3861), .Y(n4099) );
NOR2X1TS U6022 ( .A(n5074), .B(n5060), .Y(n3999) );
INVX2TS U6023 ( .A(n3999), .Y(n4057) );
NAND2X1TS U6024 ( .A(n5074), .B(n5060), .Y(n4055) );
NAND2X1TS U6025 ( .A(n4057), .B(n4055), .Y(n3866) );
AOI222XLTS U6026 ( .A0(n4065), .A1(n4829), .B0(n4075), .B1(n4939), .C0(n4103), .C1(n4722), .Y(n3868) );
NAND2X1TS U6027 ( .A(n3870), .B(n3873), .Y(n3876) );
AOI21X1TS U6028 ( .A0(n3874), .A1(n3873), .B0(n3872), .Y(n3875) );
NAND2X1TS U6029 ( .A(n3879), .B(n3878), .Y(n3880) );
AOI222XLTS U6030 ( .A0(n4151), .A1(n4678), .B0(n335), .B1(n4822), .C0(n4115),
.C1(n4630), .Y(n3881) );
CMPR32X2TS U6031 ( .A(n3888), .B(n3887), .C(n3886), .CO(n3897), .S(n3929) );
CMPR32X2TS U6032 ( .A(n3891), .B(n3890), .C(n3889), .CO(n3896), .S(n3927) );
AOI222XLTS U6033 ( .A0(n3553), .A1(n4618), .B0(n3899), .B1(n4516), .C0(n3898), .C1(n4133), .Y(n3900) );
AOI222XLTS U6034 ( .A0(n4065), .A1(n4678), .B0(n3906), .B1(n4822), .C0(n4103), .C1(n4630), .Y(n3907) );
AOI222XLTS U6035 ( .A0(n4151), .A1(n4526), .B0(n335), .B1(Data_B_i[17]),
.C0(n4150), .C1(n4410), .Y(n3912) );
INVX2TS U6036 ( .A(n3923), .Y(n7507) );
CMPR32X2TS U6037 ( .A(n3938), .B(n3937), .C(n3936), .CO(n3952), .S(n3960) );
INVX2TS U6038 ( .A(n3942), .Y(n7513) );
CMPR32X2TS U6039 ( .A(n3948), .B(n3947), .C(n3946), .CO(n3939), .S(n3957) );
CMPR32X2TS U6040 ( .A(n3951), .B(n3950), .C(n3949), .CO(n3956), .S(n3958) );
NOR2X1TS U6041 ( .A(n3962), .B(n3961), .Y(n7516) );
INVX2TS U6042 ( .A(n7516), .Y(n7585) );
NAND2X1TS U6043 ( .A(n3964), .B(n3963), .Y(n7517) );
NAND2X1TS U6044 ( .A(n3968), .B(n3967), .Y(n7512) );
NAND2X1TS U6045 ( .A(n3970), .B(n3969), .Y(n7506) );
OAI21X2TS U6046 ( .A0(n7510), .A1(n3973), .B0(n3972), .Y(n3974) );
CLKBUFX2TS U6047 ( .A(Data_B_i[14]), .Y(n4692) );
AOI222XLTS U6048 ( .A0(n322), .A1(n4693), .B0(n4470), .B1(n4692), .C0(n4448),
.C1(Data_B_i[13]), .Y(n3976) );
OAI21X1TS U6049 ( .A0(n4695), .A1(n4711), .B0(n3976), .Y(n3977) );
NOR2BX2TS U6050 ( .AN(n3980), .B(n3979), .Y(n4742) );
AOI222X1TS U6051 ( .A0(n5063), .A1(n3986), .B0(n4742), .B1(Data_B_i[1]),
.C0(n317), .C1(n3985), .Y(n3987) );
OAI21X1TS U6052 ( .A0(n3988), .A1(n5108), .B0(n3987), .Y(n3989) );
XOR2X1TS U6053 ( .A(n3989), .B(n5066), .Y(n4013) );
ADDHXLTS U6054 ( .A(n7419), .B(n3990), .CO(n4127), .S(n4142) );
CLKBUFX2TS U6055 ( .A(n4742), .Y(n5078) );
AOI22X1TS U6056 ( .A0(n5078), .A1(n3992), .B0(n4993), .B1(n3991), .Y(n3993)
);
INVX2TS U6057 ( .A(n4126), .Y(n3996) );
AOI222XLTS U6058 ( .A0(n3553), .A1(n4526), .B0(n3552), .B1(n4816), .C0(n4321), .C1(n4410), .Y(n3997) );
NOR2X1TS U6059 ( .A(n3999), .B(n4060), .Y(n4092) );
INVX2TS U6060 ( .A(n4091), .Y(n5105) );
NOR2X1TS U6061 ( .A(n5105), .B(n5080), .Y(n4072) );
NAND2X1TS U6062 ( .A(n4093), .B(n4003), .Y(n4005) );
NAND2X1TS U6063 ( .A(n5074), .B(n5061), .Y(n4061) );
NAND2X1TS U6064 ( .A(n4061), .B(n4055), .Y(n4096) );
NAND2X1TS U6065 ( .A(n5105), .B(n5061), .Y(n4094) );
AOI21X1TS U6066 ( .A0(n4099), .A1(n4003), .B0(n4002), .Y(n4004) );
INVX2TS U6067 ( .A(n4091), .Y(n7418) );
AOI21X1TS U6068 ( .A0(n4103), .A1(n5061), .B0(n4006), .Y(n4007) );
OAI21X1TS U6069 ( .A0(n5084), .A1(n4105), .B0(n4007), .Y(n4008) );
XOR2X1TS U6070 ( .A(n4008), .B(n4106), .Y(n4034) );
AOI222XLTS U6071 ( .A0(n3566), .A1(n4678), .B0(n4009), .B1(n4822), .C0(n4308), .C1(n4630), .Y(n4010) );
XOR2X1TS U6072 ( .A(n4011), .B(Data_A_i[8]), .Y(n4033) );
CMPR22X2TS U6073 ( .A(n4013), .B(n4012), .CO(n4108), .S(n4082) );
CLKBUFX2TS U6074 ( .A(n4850), .Y(n4676) );
AOI222XLTS U6075 ( .A0(n4631), .A1(n4014), .B0(n4525), .B1(n4302), .C0(n4676), .C1(n4301), .Y(n4015) );
XOR2X1TS U6076 ( .A(n4016), .B(Data_A_i[20]), .Y(n4081) );
CLKBUFX2TS U6077 ( .A(n4017), .Y(n4440) );
CLKBUFX2TS U6078 ( .A(n4018), .Y(n4345) );
AOI222XLTS U6079 ( .A0(n4345), .A1(n4246), .B0(n4823), .B1(n4129), .C0(n342),
.C1(n283), .Y(n4019) );
AOI222XLTS U6080 ( .A0(n3447), .A1(n4722), .B0(n4463), .B1(n4824), .C0(n4021), .C1(n4651), .Y(n4022) );
OAI21X1TS U6081 ( .A0(n4847), .A1(n4467), .B0(n4022), .Y(n4023) );
AOI222XLTS U6082 ( .A0(n4426), .A1(n4630), .B0(n4538), .B1(n4818), .C0(n4623), .C1(n4423), .Y(n4024) );
CLKBUFX2TS U6083 ( .A(n4027), .Y(n4519) );
XOR2X1TS U6084 ( .A(n4029), .B(n4970), .Y(n4228) );
AOI222XLTS U6085 ( .A0(n4631), .A1(n4133), .B0(n4525), .B1(n238), .C0(n4676),
.C1(n4483), .Y(n4030) );
OAI21X1TS U6086 ( .A0(n4431), .A1(n4269), .B0(n4030), .Y(n4031) );
XOR2X1TS U6087 ( .A(n4031), .B(Data_A_i[20]), .Y(n4227) );
CMPR32X2TS U6088 ( .A(n4034), .B(n4033), .C(n4032), .CO(n4338), .S(n4149) );
AOI222XLTS U6089 ( .A0(n4151), .A1(n4829), .B0(n335), .B1(n4939), .C0(n202),
.C1(n4722), .Y(n4035) );
AOI222XLTS U6090 ( .A0(n4631), .A1(n4419), .B0(n4525), .B1(n4368), .C0(n4676), .C1(n286), .Y(n4037) );
XOR2X1TS U6091 ( .A(n4038), .B(Data_A_i[20]), .Y(n4088) );
AOI222XLTS U6092 ( .A0(n4345), .A1(n4276), .B0(n4438), .B1(n4246), .C0(n343),
.C1(n284), .Y(n4039) );
XOR2X1TS U6093 ( .A(n4040), .B(n4548), .Y(n4087) );
AOI222XLTS U6094 ( .A0(n4703), .A1(Data_B_i[12]), .B0(n4132), .B1(n235),
.C0(n4749), .C1(n287), .Y(n4041) );
CLKBUFX2TS U6095 ( .A(Data_B_i[13]), .Y(n4662) );
AOI222XLTS U6096 ( .A0(n322), .A1(n4663), .B0(n4470), .B1(n4662), .C0(n4356),
.C1(n4688), .Y(n4043) );
XOR2X1TS U6097 ( .A(n4045), .B(n4044), .Y(n4052) );
AOI222XLTS U6098 ( .A0(n4262), .A1(n236), .B0(n4132), .B1(n4429), .C0(n4749),
.C1(n4419), .Y(n4046) );
XOR2X1TS U6099 ( .A(n4047), .B(n4813), .Y(n4051) );
AOI222XLTS U6100 ( .A0(n4426), .A1(n4423), .B0(n3899), .B1(n4715), .C0(n4321), .C1(n4442), .Y(n4048) );
XOR2X1TS U6101 ( .A(n4049), .B(n4434), .Y(n4050) );
AOI222XLTS U6102 ( .A0(n4426), .A1(n4410), .B0(n3552), .B1(n4693), .C0(n4321), .C1(n4372), .Y(n4053) );
OAI21X1TS U6103 ( .A0(n4718), .A1(n4625), .B0(n4053), .Y(n4054) );
NAND2X1TS U6104 ( .A(n4093), .B(n4057), .Y(n4059) );
AOI21X1TS U6105 ( .A0(n4099), .A1(n4057), .B0(n4056), .Y(n4058) );
NAND2X1TS U6106 ( .A(n4062), .B(n4061), .Y(n4063) );
AOI222XLTS U6107 ( .A0(n4065), .A1(n5061), .B0(n4075), .B1(n4967), .C0(n4103), .C1(n4753), .Y(n4066) );
AOI222XLTS U6108 ( .A0(n4348), .A1(n4630), .B0(n4463), .B1(n4818), .C0(n4465), .C1(n4423), .Y(n4068) );
OAI21X1TS U6109 ( .A0(n4797), .A1(n4408), .B0(n4068), .Y(n4069) );
NAND2X1TS U6110 ( .A(n4093), .B(n4092), .Y(n4071) );
AOI21X1TS U6111 ( .A0(n4099), .A1(n4092), .B0(n4096), .Y(n4070) );
NAND2X1TS U6112 ( .A(n4073), .B(n4094), .Y(n4074) );
INVX2TS U6113 ( .A(n4091), .Y(n5062) );
AOI222XLTS U6114 ( .A0(n3575), .A1(n5062), .B0(n4075), .B1(n4992), .C0(n4103), .C1(n4829), .Y(n4076) );
OAI21X1TS U6115 ( .A0(n5065), .A1(n4105), .B0(n4076), .Y(n4077) );
XOR2X1TS U6116 ( .A(n4077), .B(n4106), .Y(n4123) );
AOI222XLTS U6117 ( .A0(n3447), .A1(n4651), .B0(n4463), .B1(n4795), .C0(n4465), .C1(n4526), .Y(n4078) );
XOR2X1TS U6118 ( .A(n4079), .B(Data_A_i[8]), .Y(n4122) );
AOI222XLTS U6119 ( .A0(n4703), .A1(n4292), .B0(n4808), .B1(n4517), .C0(n4749), .C1(n236), .Y(n4089) );
NAND2X1TS U6120 ( .A(n4093), .B(n4098), .Y(n4101) );
AOI21X1TS U6121 ( .A0(n4099), .A1(n4098), .B0(n4097), .Y(n4100) );
OA21X4TS U6122 ( .A0(n308), .A1(n4101), .B0(n4100), .Y(n5109) );
OAI21X1TS U6123 ( .A0(n5109), .A1(n4105), .B0(n4104), .Y(n4107) );
XOR2X1TS U6124 ( .A(n4107), .B(n4106), .Y(n4254) );
ADDFHX2TS U6125 ( .A(n4110), .B(n4109), .CI(n4108), .CO(n4253), .S(n4119) );
AOI222XLTS U6126 ( .A0(n4345), .A1(n4302), .B0(n4438), .B1(n4276), .C0(n343),
.C1(n4275), .Y(n4111) );
OAI21X1TS U6127 ( .A0(n4304), .A1(n4440), .B0(n4111), .Y(n4112) );
AOI222XLTS U6128 ( .A0(n322), .A1(n4715), .B0(n4470), .B1(n4714), .C0(n4448),
.C1(Data_B_i[14]), .Y(n4113) );
OAI21X1TS U6129 ( .A0(n4718), .A1(n4711), .B0(n4113), .Y(n4114) );
AOI222XLTS U6130 ( .A0(n4151), .A1(n5061), .B0(n335), .B1(n4967), .C0(n4115),
.C1(n4753), .Y(n4116) );
OAI21X1TS U6131 ( .A0(n4995), .A1(n4241), .B0(n4116), .Y(n4117) );
CMPR32X2TS U6132 ( .A(n4123), .B(n4122), .C(n4121), .CO(n4145), .S(n4175) );
AOI222XLTS U6133 ( .A0(n4151), .A1(n4753), .B0(n334), .B1(n4938), .C0(n202),
.C1(n4678), .Y(n4124) );
XOR2X1TS U6134 ( .A(n4125), .B(n4297), .Y(n4162) );
XOR2X1TS U6135 ( .A(n4127), .B(n4126), .Y(n4156) );
OAI21X1TS U6136 ( .A0(n116), .A1(n4440), .B0(n4130), .Y(n4131) );
XOR2X1TS U6137 ( .A(n4131), .B(n4548), .Y(n4155) );
AOI222XLTS U6138 ( .A0(n4262), .A1(n4133), .B0(n4132), .B1(n238), .C0(n4749),
.C1(n4483), .Y(n4134) );
OAI21X1TS U6139 ( .A0(n4431), .A1(n4135), .B0(n4134), .Y(n4136) );
CLKBUFX2TS U6140 ( .A(Data_B_i[12]), .Y(n4618) );
AOI222XLTS U6141 ( .A0(n4667), .A1(n4619), .B0(n4680), .B1(n4618), .C0(n4356), .C1(n236), .Y(n4137) );
AOI222XLTS U6142 ( .A0(n4631), .A1(n4367), .B0(n4525), .B1(n4276), .C0(n4676), .C1(n4275), .Y(n4139) );
XOR2X1TS U6143 ( .A(n4140), .B(n4444), .Y(n4164) );
CMPR32X2TS U6144 ( .A(n4143), .B(n4142), .C(n4141), .CO(n4163), .S(n4167) );
AOI222XLTS U6145 ( .A0(n4151), .A1(n4722), .B0(n335), .B1(n4824), .C0(n4150),
.C1(n4651), .Y(n4152) );
OAI21X1TS U6146 ( .A0(n4847), .A1(n4241), .B0(n4152), .Y(n4153) );
XOR2X1TS U6147 ( .A(n4153), .B(n4297), .Y(n4183) );
CMPR32X2TS U6148 ( .A(n4159), .B(n4158), .C(n4157), .CO(n4181), .S(n4186) );
ADDFHX2TS U6149 ( .A(n4168), .B(n4167), .CI(n4166), .CO(n4196), .S(n4184) );
NOR2X2TS U6150 ( .A(n4217), .B(n4216), .Y(n7571) );
ADDFHX1TS U6151 ( .A(n4174), .B(n4173), .CI(n4172), .CO(n4216), .S(n4215) );
CMPR32X2TS U6152 ( .A(n4180), .B(n4179), .C(n4178), .CO(n4203), .S(n4199) );
CMPR32X2TS U6153 ( .A(n4183), .B(n4182), .C(n4181), .CO(n4189), .S(n4202) );
CMPR32X2TS U6154 ( .A(n4186), .B(n4185), .C(n4184), .CO(n4201), .S(n4209) );
NOR2X2TS U6155 ( .A(n4215), .B(n4214), .Y(n7579) );
NOR2X2TS U6156 ( .A(n7571), .B(n7579), .Y(n4219) );
ADDFHX2TS U6157 ( .A(n4209), .B(n4208), .CI(n4207), .CO(n4210), .S(n3970) );
NAND2X1TS U6158 ( .A(n4219), .B(n7577), .Y(n4221) );
NAND2X1TS U6159 ( .A(n4215), .B(n4214), .Y(n7580) );
NAND2X1TS U6160 ( .A(n4217), .B(n4216), .Y(n7572) );
AOI222XLTS U6161 ( .A0(n4222), .A1(n5062), .B0(n334), .B1(n4992), .C0(n202),
.C1(n4829), .Y(n4223) );
OAI21X1TS U6162 ( .A0(n5065), .A1(n4241), .B0(n4223), .Y(n4224) );
XOR2X1TS U6163 ( .A(n4224), .B(n303), .Y(n4285) );
AOI222XLTS U6164 ( .A0(n4345), .A1(n4368), .B0(n4438), .B1(n4302), .C0(n341),
.C1(Data_B_i[6]), .Y(n4225) );
OAI21X1TS U6165 ( .A0(n4370), .A1(n4440), .B0(n4225), .Y(n4226) );
XOR2X1TS U6166 ( .A(n4226), .B(n5001), .Y(n4271) );
CMPR32X2TS U6167 ( .A(n4229), .B(n4228), .C(n4227), .CO(n4283), .S(n4280) );
AOI222XLTS U6168 ( .A0(n3447), .A1(n4753), .B0(n4463), .B1(n4938), .C0(n4465), .C1(n4678), .Y(n4230) );
OAI21X1TS U6169 ( .A0(n4941), .A1(n4467), .B0(n4230), .Y(n4231) );
XOR2X1TS U6170 ( .A(n4231), .B(Data_A_i[8]), .Y(n4288) );
AOI222XLTS U6171 ( .A0(n4667), .A1(n4816), .B0(n4470), .B1(Data_B_i[16]),
.C0(n4448), .C1(Data_B_i[15]), .Y(n4232) );
XOR2X1TS U6172 ( .A(n4233), .B(n4611), .Y(n4287) );
AOI222XLTS U6173 ( .A0(n3553), .A1(n4651), .B0(n4538), .B1(n4795), .C0(n4623), .C1(n4526), .Y(n4234) );
XOR2X1TS U6174 ( .A(n4235), .B(n4434), .Y(n4286) );
AOI222XLTS U6175 ( .A0(n3553), .A1(n4678), .B0(n3552), .B1(n4822), .C0(n4623), .C1(n4630), .Y(n4236) );
XOR2X1TS U6176 ( .A(n4237), .B(n4434), .Y(n4320) );
AOI21X1TS U6177 ( .A0(n202), .A1(n5080), .B0(n4239), .Y(n4240) );
OAI21X1TS U6178 ( .A0(n5084), .A1(n4241), .B0(n4240), .Y(n4243) );
XOR2X1TS U6179 ( .A(n4243), .B(n303), .Y(n4319) );
AOI222XLTS U6180 ( .A0(n3566), .A1(n4829), .B0(n4309), .B1(n4939), .C0(n4308), .C1(n4722), .Y(n4244) );
XOR2X1TS U6181 ( .A(n4245), .B(Data_A_i[8]), .Y(n4318) );
AOI222XLTS U6182 ( .A0(n4716), .A1(n4246), .B0(n4742), .B1(n284), .C0(n317),
.C1(n283), .Y(n4247) );
XOR2X1TS U6183 ( .A(n4248), .B(n4970), .Y(n4261) );
AOI222XLTS U6184 ( .A0(n4750), .A1(n4372), .B0(n4522), .B1(n4619), .C0(n4749), .C1(n4688), .Y(n4249) );
XOR2X1TS U6185 ( .A(n4250), .B(n4264), .Y(n4260) );
AOI222XLTS U6186 ( .A0(n4631), .A1(n4516), .B0(n4525), .B1(n4429), .C0(n4676), .C1(n238), .Y(n4251) );
XOR2X1TS U6187 ( .A(n4252), .B(n4792), .Y(n4259) );
CMPR32X2TS U6188 ( .A(n4258), .B(n4257), .C(n4256), .CO(n4334), .S(n4331) );
CMPR32X2TS U6189 ( .A(n4261), .B(n4260), .C(n4259), .CO(n4314), .S(n4336) );
AOI222XLTS U6190 ( .A0(n4262), .A1(n4442), .B0(n4522), .B1(n4663), .C0(n4613), .C1(n4662), .Y(n4263) );
OAI21X1TS U6191 ( .A0(n4695), .A1(n4776), .B0(n4263), .Y(n4265) );
XOR2X1TS U6192 ( .A(n4265), .B(n4264), .Y(n4291) );
AOI222XLTS U6193 ( .A0(n4345), .A1(n239), .B0(n4438), .B1(n4368), .C0(n341),
.C1(n286), .Y(n4266) );
AOI222XLTS U6194 ( .A0(n321), .A1(n4618), .B0(n4525), .B1(n4516), .C0(n4676),
.C1(n287), .Y(n4268) );
OAI21X1TS U6195 ( .A0(n4520), .A1(n4269), .B0(n4268), .Y(n4270) );
CLKBUFX2TS U6196 ( .A(Data_B_i[17]), .Y(n4816) );
AOI222XLTS U6197 ( .A0(n4667), .A1(n4818), .B0(n4470), .B1(n4816), .C0(n4448), .C1(n4815), .Y(n4273) );
OAI21X1TS U6198 ( .A0(n4820), .A1(n4711), .B0(n4273), .Y(n4274) );
XOR2X1TS U6199 ( .A(n4274), .B(n4611), .Y(n4316) );
CLKBUFX2TS U6200 ( .A(n4742), .Y(n4817) );
XOR2X1TS U6201 ( .A(n4279), .B(n4970), .Y(n4306) );
CMPR32X2TS U6202 ( .A(n4282), .B(n4281), .C(n4280), .CO(n4392), .S(n4337) );
CMPR32X2TS U6203 ( .A(n4285), .B(n4284), .C(n4283), .CO(n4330), .S(n4391) );
AOI222XLTS U6204 ( .A0(n320), .A1(n4292), .B0(n4828), .B1(n4517), .C0(n4676),
.C1(n235), .Y(n4293) );
XOR2X1TS U6205 ( .A(n4294), .B(Data_A_i[20]), .Y(n4366) );
NAND2X1TS U6206 ( .A(n202), .B(n5105), .Y(n4295) );
AOI222XLTS U6207 ( .A0(n4750), .A1(n4410), .B0(n4522), .B1(n4693), .C0(n4613), .C1(n4692), .Y(n4299) );
OAI21X1TS U6208 ( .A0(n4718), .A1(n4776), .B0(n4299), .Y(n4300) );
INVX2TS U6209 ( .A(n4788), .Y(n4705) );
AOI222XLTS U6210 ( .A0(n4716), .A1(n4302), .B0(n4817), .B1(n4301), .C0(n5106), .C1(n4275), .Y(n4303) );
XOR2X1TS U6211 ( .A(n4305), .B(n5110), .Y(n4377) );
ADDFHX2TS U6212 ( .A(n3672), .B(n4307), .CI(n4306), .CO(n4376), .S(n4315) );
AOI222XLTS U6213 ( .A0(n3566), .A1(n5061), .B0(n4309), .B1(n4967), .C0(n4308), .C1(n4753), .Y(n4310) );
XOR2X1TS U6214 ( .A(n4311), .B(Data_A_i[8]), .Y(n4375) );
AOI222XLTS U6215 ( .A0(n3553), .A1(n4722), .B0(n4538), .B1(n4824), .C0(n4321), .C1(n4651), .Y(n4322) );
XOR2X1TS U6216 ( .A(n4323), .B(n4434), .Y(n4353) );
AOI222XLTS U6217 ( .A0(n4667), .A1(n4795), .B0(n4680), .B1(Data_B_i[18]),
.C0(n4356), .C1(n4794), .Y(n4324) );
OAI21X1TS U6218 ( .A0(n4797), .A1(n4711), .B0(n4324), .Y(n4325) );
XOR2X1TS U6219 ( .A(n4325), .B(n4611), .Y(n4352) );
AOI222XLTS U6220 ( .A0(n4345), .A1(n4429), .B0(n4438), .B1(n4419), .C0(n341),
.C1(n4483), .Y(n4326) );
OAI21X1TS U6221 ( .A0(n4431), .A1(n4440), .B0(n4326), .Y(n4327) );
NOR2X2TS U6222 ( .A(n4579), .B(n4578), .Y(n7472) );
AOI222XLTS U6223 ( .A0(n4750), .A1(n4423), .B0(n4522), .B1(n4715), .C0(n4613), .C1(n4714), .Y(n4343) );
XOR2X1TS U6224 ( .A(n4344), .B(n4705), .Y(n4462) );
AOI222XLTS U6225 ( .A0(n4345), .A1(n235), .B0(n4438), .B1(n4429), .C0(n342),
.C1(n238), .Y(n4346) );
XOR2X1TS U6226 ( .A(n4347), .B(n5001), .Y(n4461) );
AOI222XLTS U6227 ( .A0(n4348), .A1(n5062), .B0(n4463), .B1(n4992), .C0(n4465), .C1(n4829), .Y(n4349) );
XOR2X1TS U6228 ( .A(n4350), .B(n4468), .Y(n4460) );
AOI222XLTS U6229 ( .A0(n3522), .A1(n4753), .B0(n4538), .B1(n4938), .C0(n4623), .C1(n4678), .Y(n4354) );
AOI222XLTS U6230 ( .A0(n322), .A1(n4822), .B0(n4680), .B1(Data_B_i[19]),
.C0(n4356), .C1(n4785), .Y(n4357) );
CMPR32X2TS U6231 ( .A(n4106), .B(n4360), .C(n4359), .CO(n4457), .S(n4351) );
CMPR32X2TS U6232 ( .A(n4363), .B(n4362), .C(n4361), .CO(n4561), .S(n4383) );
AOI222XLTS U6233 ( .A0(n4716), .A1(n4368), .B0(n4817), .B1(n4367), .C0(n317),
.C1(Data_B_i[6]), .Y(n4369) );
AOI222XLTS U6234 ( .A0(n321), .A1(n4372), .B0(n4677), .B1(n4619), .C0(n4676),
.C1(n4688), .Y(n4373) );
OAI21X1TS U6235 ( .A0(n4665), .A1(n4852), .B0(n4373), .Y(n4374) );
ADDFHX2TS U6236 ( .A(n4386), .B(n4385), .CI(n4384), .CO(n4580), .S(n4579) );
ADDFHX2TS U6237 ( .A(n4389), .B(n4388), .CI(n4387), .CO(n4578), .S(n4577) );
CMPR32X2TS U6238 ( .A(n4392), .B(n4391), .C(n4390), .CO(n4340), .S(n4404) );
NOR2X2TS U6239 ( .A(n4577), .B(n4576), .Y(n7488) );
NOR2X2TS U6240 ( .A(n7488), .B(n7493), .Y(n7481) );
NAND2X2TS U6241 ( .A(n4583), .B(n7481), .Y(n7467) );
AOI222XLTS U6242 ( .A0(n4935), .A1(n4619), .B0(n4976), .B1(n4517), .C0(n342),
.C1(n4516), .Y(n4405) );
OAI21X1TS U6243 ( .A0(n4621), .A1(n4979), .B0(n4405), .Y(n4406) );
AOI222XLTS U6244 ( .A0(n321), .A1(n4410), .B0(n4525), .B1(n4693), .C0(n4790),
.C1(n4692), .Y(n4411) );
OAI21X1TS U6245 ( .A0(n4718), .A1(n4852), .B0(n4411), .Y(n4412) );
INVX2TS U6246 ( .A(n4975), .Y(n4833) );
AOI222XLTS U6247 ( .A0(n3553), .A1(n5061), .B0(n4538), .B1(n4967), .C0(n4623), .C1(n4753), .Y(n4413) );
OAI21X1TS U6248 ( .A0(n4995), .A1(n4541), .B0(n4413), .Y(n4414) );
AOI222XLTS U6249 ( .A0(n4750), .A1(n4630), .B0(n4808), .B1(n4818), .C0(n4749), .C1(n4794), .Y(n4415) );
INVX2TS U6250 ( .A(n4546), .Y(n4452) );
CMPR32X2TS U6251 ( .A(n4418), .B(n3410), .C(n4417), .CO(n4437), .S(n4475) );
XOR2X1TS U6252 ( .A(n4422), .B(n5110), .Y(n4436) );
AOI222XLTS U6253 ( .A0(n321), .A1(n4423), .B0(n4677), .B1(n4715), .C0(n4790),
.C1(n4714), .Y(n4424) );
XOR2X1TS U6254 ( .A(n4425), .B(n4833), .Y(n4531) );
AOI222XLTS U6255 ( .A0(n4426), .A1(n5062), .B0(n4538), .B1(n4992), .C0(n4623), .C1(n4829), .Y(n4427) );
OAI21X1TS U6256 ( .A0(n5065), .A1(n4541), .B0(n4427), .Y(n4428) );
XOR2X1TS U6257 ( .A(n4428), .B(n4626), .Y(n4530) );
AOI222XLTS U6258 ( .A0(n3522), .A1(n4829), .B0(n4538), .B1(n4939), .C0(n4623), .C1(n4722), .Y(n4433) );
AOI222XLTS U6259 ( .A0(n4018), .A1(n4517), .B0(n4438), .B1(n235), .C0(n343),
.C1(n287), .Y(n4439) );
XOR2X1TS U6260 ( .A(n4441), .B(n5001), .Y(n4456) );
AOI222XLTS U6261 ( .A0(n320), .A1(n4442), .B0(n4677), .B1(n4663), .C0(n4790),
.C1(n4662), .Y(n4443) );
XOR2X1TS U6262 ( .A(n4445), .B(n4444), .Y(n4455) );
AOI222XLTS U6263 ( .A0(n4703), .A1(n4526), .B0(n4522), .B1(n4816), .C0(n4613), .C1(n4815), .Y(n4446) );
XOR2X1TS U6264 ( .A(n4447), .B(n4705), .Y(n4454) );
AOI222XLTS U6265 ( .A0(n4667), .A1(Data_B_i[22]), .B0(n4680), .B1(
Data_B_i[21]), .C0(n4448), .C1(n4934), .Y(n4449) );
CMPR32X2TS U6266 ( .A(n4453), .B(n4452), .C(n4451), .CO(n4529), .S(n4477) );
CMPR32X2TS U6267 ( .A(n4456), .B(n4455), .C(n4454), .CO(n4476), .S(n4504) );
AOI21X1TS U6268 ( .A0(n4465), .A1(n5080), .B0(n4464), .Y(n4466) );
AOI222XLTS U6269 ( .A0(n322), .A1(n4824), .B0(n4470), .B1(Data_B_i[20]),
.C0(n4709), .C1(n241), .Y(n4471) );
CMPR32X2TS U6270 ( .A(n4478), .B(n4477), .C(n4476), .CO(n4534), .S(n4511) );
CLKBUFX2TS U6271 ( .A(Data_B_i[22]), .Y(n4938) );
AOI222XLTS U6272 ( .A0(n4667), .A1(n4939), .B0(n4680), .B1(n4938), .C0(n4709), .C1(n4972), .Y(n4479) );
XOR2X1TS U6273 ( .A(n4480), .B(n4611), .Y(n4537) );
AOI222XLTS U6274 ( .A0(n4703), .A1(n4651), .B0(n4808), .B1(n4795), .C0(n4810), .C1(n4785), .Y(n4481) );
OAI21X1TS U6275 ( .A0(n4773), .A1(n4812), .B0(n4481), .Y(n4482) );
XOR2X1TS U6276 ( .A(n4482), .B(n4705), .Y(n4536) );
AOI222XLTS U6277 ( .A0(n4935), .A1(n4663), .B0(n4823), .B1(n4619), .C0(n341),
.C1(n4688), .Y(n4484) );
AOI222XLTS U6278 ( .A0(n4716), .A1(n236), .B0(n4817), .B1(n287), .C0(n5106),
.C1(n239), .Y(n4486) );
CMPR32X2TS U6279 ( .A(n4491), .B(n4490), .C(n4489), .CO(n4552), .S(n4500) );
CMPR32X2TS U6280 ( .A(n4497), .B(n4496), .C(n4495), .CO(n4551), .S(n4498) );
CMPR32X2TS U6281 ( .A(n4506), .B(n4505), .C(n4504), .CO(n4512), .S(n4563) );
CMPR32X2TS U6282 ( .A(n4509), .B(n4508), .C(n4507), .CO(n4562), .S(n4567) );
NOR2X2TS U6283 ( .A(n4589), .B(n4588), .Y(n7450) );
AOI222XLTS U6284 ( .A0(n4993), .A1(n4517), .B0(n4817), .B1(n4516), .C0(n5106), .C1(n287), .Y(n4518) );
AOI222XLTS U6285 ( .A0(n4703), .A1(n4678), .B0(n4522), .B1(n4822), .C0(n4810), .C1(n241), .Y(n4523) );
OAI21X1TS U6286 ( .A0(n4826), .A1(n4812), .B0(n4523), .Y(n4524) );
AOI222XLTS U6287 ( .A0(n321), .A1(n4526), .B0(n4525), .B1(n4816), .C0(n4790),
.C1(n4815), .Y(n4527) );
OAI21X1TS U6288 ( .A0(n4820), .A1(n4852), .B0(n4527), .Y(n4528) );
CMPR32X2TS U6289 ( .A(n4531), .B(n4530), .C(n4529), .CO(n4601), .S(n4550) );
AOI21X1TS U6290 ( .A0(n4623), .A1(n5080), .B0(n4539), .Y(n4540) );
AOI222XLTS U6291 ( .A0(n4667), .A1(n4967), .B0(n4680), .B1(Data_B_i[23]),
.C0(n4709), .C1(n4997), .Y(n4543) );
INVX2TS U6292 ( .A(n4690), .Y(n4655) );
CMPR32X2TS U6293 ( .A(n3251), .B(n4546), .C(n4545), .CO(n4617), .S(n4515) );
AOI222XLTS U6294 ( .A0(n4935), .A1(n4693), .B0(n4823), .B1(n4663), .C0(n343),
.C1(n4662), .Y(n4547) );
OAI21X1TS U6295 ( .A0(n4695), .A1(n5000), .B0(n4547), .Y(n4549) );
XOR2X1TS U6296 ( .A(n4549), .B(n4548), .Y(n4616) );
NOR2X2TS U6297 ( .A(n4591), .B(n4590), .Y(n7441) );
ADDFHX2TS U6298 ( .A(n4567), .B(n4566), .CI(n4565), .CO(n4584), .S(n4581) );
ADDFHX2TS U6299 ( .A(n4570), .B(n4569), .CI(n4568), .CO(n4588), .S(n4587) );
NAND2X1TS U6300 ( .A(n4587), .B(n4586), .Y(n7462) );
OAI21X2TS U6301 ( .A0(n7461), .A1(n7468), .B0(n7462), .Y(n7446) );
NAND2X1TS U6302 ( .A(n4591), .B(n4590), .Y(n7442) );
OAI21X2TS U6303 ( .A0(n7466), .A1(n4595), .B0(n4594), .Y(n4596) );
CMPR32X2TS U6304 ( .A(n4603), .B(n4602), .C(n4601), .CO(n4639), .S(n4600) );
CMPR32X2TS U6305 ( .A(n4609), .B(n4608), .C(n4607), .CO(n4645), .S(n4605) );
AOI222XLTS U6306 ( .A0(n322), .A1(n4992), .B0(n4680), .B1(Data_B_i[24]),
.C0(n4709), .C1(n5060), .Y(n4610) );
AOI222XLTS U6307 ( .A0(n4703), .A1(n4722), .B0(n4808), .B1(n4824), .C0(n4613), .C1(n4934), .Y(n4614) );
OAI21X1TS U6308 ( .A0(n4847), .A1(n4812), .B0(n4614), .Y(n4615) );
XOR2X1TS U6309 ( .A(n4615), .B(n4705), .Y(n4647) );
CMPR32X2TS U6310 ( .A(n4655), .B(n4617), .C(n4616), .CO(n4646), .S(n4607) );
AOI222XLTS U6311 ( .A0(n5063), .A1(n4619), .B0(n5078), .B1(n4618), .C0(n5106), .C1(n236), .Y(n4620) );
OAI21X1TS U6312 ( .A0(n4621), .A1(n5083), .B0(n4620), .Y(n4622) );
XOR2X1TS U6313 ( .A(n4622), .B(n5110), .Y(n4654) );
NAND2X1TS U6314 ( .A(n4623), .B(n5105), .Y(n4624) );
OAI21X1TS U6315 ( .A0(n5109), .A1(n4625), .B0(n4624), .Y(n4627) );
XOR2X1TS U6316 ( .A(n4627), .B(n4626), .Y(n4661) );
AOI222XLTS U6317 ( .A0(n4935), .A1(n4715), .B0(n4823), .B1(n4693), .C0(n341),
.C1(Data_B_i[14]), .Y(n4628) );
INVX2TS U6318 ( .A(n5077), .Y(n4844) );
AOI222XLTS U6319 ( .A0(n4631), .A1(n4630), .B0(n4828), .B1(n4818), .C0(n4676), .C1(n4794), .Y(n4632) );
XOR2X1TS U6320 ( .A(n4633), .B(n4833), .Y(n4659) );
CMPR32X2TS U6321 ( .A(n4636), .B(n4635), .C(n4634), .CO(n4640), .S(n4602) );
NOR2X1TS U6322 ( .A(n4894), .B(n4895), .Y(n7554) );
CMPR32X2TS U6323 ( .A(n4639), .B(n4638), .C(n4637), .CO(n4897), .S(n4895) );
CMPR32X2TS U6324 ( .A(n4645), .B(n4644), .C(n4643), .CO(n4763), .S(n4637) );
CMPR32X2TS U6325 ( .A(n4648), .B(n4647), .C(n4646), .CO(n4702), .S(n4644) );
AOI222XLTS U6326 ( .A0(n4935), .A1(n4816), .B0(n4823), .B1(n4715), .C0(n343),
.C1(Data_B_i[15]), .Y(n4649) );
AOI222XLTS U6327 ( .A0(n321), .A1(n4651), .B0(n4828), .B1(n4795), .C0(n4850),
.C1(n4785), .Y(n4652) );
OAI21X1TS U6328 ( .A0(n4773), .A1(n4832), .B0(n4652), .Y(n4653) );
CMPR32X2TS U6329 ( .A(n4656), .B(n4655), .C(n4654), .CO(n4673), .S(n4642) );
AOI222XLTS U6330 ( .A0(n4703), .A1(n4753), .B0(n4808), .B1(n4938), .C0(n4810), .C1(n4972), .Y(n4657) );
AOI222XLTS U6331 ( .A0(n4716), .A1(n4663), .B0(n4742), .B1(n4662), .C0(n5106), .C1(n4688), .Y(n4664) );
XOR2X1TS U6332 ( .A(n4666), .B(n5110), .Y(n4698) );
AOI222XLTS U6333 ( .A0(n4667), .A1(n5062), .B0(n4680), .B1(n5061), .C0(n4709), .C1(n5074), .Y(n4668) );
XOR2X1TS U6334 ( .A(n4669), .B(n4712), .Y(n4697) );
NOR2X2TS U6335 ( .A(n4897), .B(n4896), .Y(n5136) );
NOR2X1TS U6336 ( .A(n7554), .B(n5136), .Y(n4950) );
CMPR32X2TS U6337 ( .A(n4672), .B(n4671), .C(n4670), .CO(n4767), .S(n4700) );
CMPR32X2TS U6338 ( .A(n4675), .B(n4674), .C(n4673), .CO(n4733), .S(n4701) );
AOI21X1TS U6339 ( .A0(n4709), .A1(n5080), .B0(n4681), .Y(n4682) );
OAI21X1TS U6340 ( .A0(n5084), .A1(n331), .B0(n4682), .Y(n4683) );
XOR2X1TS U6341 ( .A(n4683), .B(n4712), .Y(n4726) );
AOI222XLTS U6342 ( .A0(n4018), .A1(n4818), .B0(n4823), .B1(n4816), .C0(n342),
.C1(n4815), .Y(n4684) );
OAI21X1TS U6343 ( .A0(n4820), .A1(n5000), .B0(n4684), .Y(n4685) );
AOI222XLTS U6344 ( .A0(n4703), .A1(n4829), .B0(n4808), .B1(n4939), .C0(n4810), .C1(n4997), .Y(n4686) );
INVX2TS U6345 ( .A(n4806), .Y(n4747) );
CMPR32X2TS U6346 ( .A(n4691), .B(n4690), .C(n4689), .CO(n4708), .S(n4699) );
AOI222XLTS U6347 ( .A0(n5063), .A1(n4693), .B0(n4742), .B1(n4692), .C0(n317),
.C1(n4662), .Y(n4694) );
OAI21X1TS U6348 ( .A0(n4695), .A1(n5108), .B0(n4694), .Y(n4696) );
XOR2X1TS U6349 ( .A(n4696), .B(n5066), .Y(n4707) );
CMPR32X2TS U6350 ( .A(n4702), .B(n4701), .C(n4700), .CO(n4765), .S(n4762) );
AOI222XLTS U6351 ( .A0(n4703), .A1(n5061), .B0(n4808), .B1(n4967), .C0(n4810), .C1(n5060), .Y(n4704) );
NAND2X1TS U6352 ( .A(n4709), .B(n7418), .Y(n4710) );
OAI21X1TS U6353 ( .A0(n5109), .A1(n4711), .B0(n4710), .Y(n4713) );
XOR2X1TS U6354 ( .A(n4713), .B(n4712), .Y(n4746) );
AOI222XLTS U6355 ( .A0(n4716), .A1(n4715), .B0(n4742), .B1(n4714), .C0(n317),
.C1(Data_B_i[14]), .Y(n4717) );
XOR2X1TS U6356 ( .A(n4719), .B(n4970), .Y(n4739) );
AOI222XLTS U6357 ( .A0(n4935), .A1(n4795), .B0(n4976), .B1(n4818), .C0(n341),
.C1(n4794), .Y(n4720) );
OAI21X1TS U6358 ( .A0(n4797), .A1(n5000), .B0(n4720), .Y(n4721) );
XOR2X1TS U6359 ( .A(n4721), .B(n4844), .Y(n4738) );
AOI222XLTS U6360 ( .A0(n321), .A1(n4722), .B0(n4828), .B1(n4824), .C0(n4790),
.C1(n4934), .Y(n4723) );
XOR2X1TS U6361 ( .A(n4724), .B(n4833), .Y(n4737) );
CMPR32X2TS U6362 ( .A(n4730), .B(n4729), .C(n4728), .CO(n4756), .S(n4731) );
CMPR32X2TS U6363 ( .A(n4733), .B(n4732), .C(n4731), .CO(n4759), .S(n4766) );
CMPR32X2TS U6364 ( .A(n4736), .B(n4735), .C(n4734), .CO(n4877), .S(n4761) );
AOI222XLTS U6365 ( .A0(n4018), .A1(n4822), .B0(n4976), .B1(n4795), .C0(n343),
.C1(n4785), .Y(n4740) );
OAI21X1TS U6366 ( .A0(n4773), .A1(n4979), .B0(n4740), .Y(n4741) );
XOR2X1TS U6367 ( .A(n4741), .B(n4844), .Y(n4868) );
AOI222XLTS U6368 ( .A0(n5063), .A1(n4816), .B0(n4742), .B1(Data_B_i[16]),
.C0(n318), .C1(Data_B_i[15]), .Y(n4743) );
OAI21X1TS U6369 ( .A0(n4744), .A1(n5108), .B0(n4743), .Y(n4745) );
XOR2X1TS U6370 ( .A(n4745), .B(n5066), .Y(n4867) );
AOI222XLTS U6371 ( .A0(n4750), .A1(n5062), .B0(n4808), .B1(n4992), .C0(n4749), .C1(n5074), .Y(n4751) );
OAI21X1TS U6372 ( .A0(n5065), .A1(n4812), .B0(n4751), .Y(n4752) );
AOI222XLTS U6373 ( .A0(n321), .A1(n4753), .B0(n4828), .B1(n4938), .C0(n4850),
.C1(n4972), .Y(n4754) );
OAI21X1TS U6374 ( .A0(n4941), .A1(n4832), .B0(n4754), .Y(n4755) );
CMPR32X2TS U6375 ( .A(n4758), .B(n4757), .C(n4756), .CO(n4875), .S(n4760) );
CMPR32X2TS U6376 ( .A(n4761), .B(n4760), .C(n4759), .CO(n4902), .S(n4900) );
ADDFHX1TS U6377 ( .A(n4767), .B(n4766), .CI(n4765), .CO(n4901), .S(n4898) );
NOR2X2TS U6378 ( .A(n4899), .B(n4898), .Y(n4959) );
NOR2X2TS U6379 ( .A(n4906), .B(n4959), .Y(n4908) );
NAND2X2TS U6380 ( .A(n4950), .B(n4908), .Y(n7430) );
AOI222XLTS U6381 ( .A0(n320), .A1(n5062), .B0(n4828), .B1(n4992), .C0(n4850),
.C1(n5074), .Y(n4768) );
OAI21X1TS U6382 ( .A0(n5065), .A1(n4832), .B0(n4768), .Y(n4769) );
XOR2X1TS U6383 ( .A(n4769), .B(n4792), .Y(n4779) );
AOI222XLTS U6384 ( .A0(n4018), .A1(n4939), .B0(n4976), .B1(n4938), .C0(n342),
.C1(n4972), .Y(n4770) );
OAI21X1TS U6385 ( .A0(n4941), .A1(n4979), .B0(n4770), .Y(n4771) );
XOR2X1TS U6386 ( .A(n4771), .B(n4844), .Y(n4778) );
AOI222XLTS U6387 ( .A0(n4993), .A1(n4822), .B0(n5078), .B1(n241), .C0(n5106),
.C1(n4785), .Y(n4772) );
INVX2TS U6388 ( .A(n4787), .Y(n4862) );
NAND2X1TS U6389 ( .A(n4810), .B(n5105), .Y(n4775) );
XOR2X1TS U6390 ( .A(n4777), .B(n4813), .Y(n4803) );
CMPR32X2TS U6391 ( .A(n4780), .B(n4779), .C(n4778), .CO(n4840), .S(n4835) );
AOI222XLTS U6392 ( .A0(n4345), .A1(n4967), .B0(n4976), .B1(n4939), .C0(n342),
.C1(n4997), .Y(n4781) );
AOI222XLTS U6393 ( .A0(n4993), .A1(n4824), .B0(n4817), .B1(Data_B_i[20]),
.C0(n318), .C1(Data_B_i[19]), .Y(n4783) );
INVX2TS U6394 ( .A(n4974), .Y(n4932) );
CMPR32X2TS U6395 ( .A(n4788), .B(n4787), .C(n4786), .CO(n4842), .S(n4780) );
AOI21X1TS U6396 ( .A0(n4790), .A1(n5080), .B0(n4789), .Y(n4791) );
AOI222XLTS U6397 ( .A0(n5063), .A1(n4795), .B0(n5078), .B1(Data_B_i[18]),
.C0(n5106), .C1(n4794), .Y(n4796) );
AOI222XLTS U6398 ( .A0(n4345), .A1(Data_B_i[22]), .B0(n4976), .B1(n4824),
.C0(n343), .C1(n4934), .Y(n4799) );
AOI222XLTS U6399 ( .A0(n321), .A1(Data_B_i[25]), .B0(n4828), .B1(n4967),
.C0(n4850), .C1(n5060), .Y(n4801) );
CMPR32X2TS U6400 ( .A(n4804), .B(n4862), .C(n4803), .CO(n4836), .S(n4871) );
CMPR32X2TS U6401 ( .A(n4807), .B(n4806), .C(n4805), .CO(n4861), .S(n4865) );
AOI21X1TS U6402 ( .A0(n4810), .A1(n5080), .B0(n4809), .Y(n4811) );
OAI21X1TS U6403 ( .A0(n5084), .A1(n4812), .B0(n4811), .Y(n4814) );
AOI222XLTS U6404 ( .A0(n4993), .A1(n4818), .B0(n4817), .B1(n4816), .C0(n318),
.C1(n4815), .Y(n4819) );
OAI21X1TS U6405 ( .A0(n4820), .A1(n5108), .B0(n4819), .Y(n4821) );
AOI222XLTS U6406 ( .A0(n4018), .A1(n4824), .B0(n4823), .B1(n4822), .C0(n343),
.C1(n241), .Y(n4825) );
OAI21X1TS U6407 ( .A0(n4826), .A1(n4979), .B0(n4825), .Y(n4827) );
AOI222XLTS U6408 ( .A0(n321), .A1(n4829), .B0(n4828), .B1(n4939), .C0(n4850),
.C1(n4997), .Y(n4831) );
CMPR32X2TS U6409 ( .A(n4837), .B(n4836), .C(n4835), .CO(n4839), .S(n4872) );
NOR2X1TS U6410 ( .A(n4917), .B(n4916), .Y(n5020) );
CMPR32X2TS U6411 ( .A(n4840), .B(n4839), .C(n4838), .CO(n4919), .S(n4917) );
CMPR32X2TS U6412 ( .A(n4932), .B(n4842), .C(n4841), .CO(n4930), .S(n4854) );
AOI222XLTS U6413 ( .A0(n4018), .A1(n4992), .B0(n4976), .B1(n4967), .C0(n342),
.C1(n5060), .Y(n4843) );
AOI222XLTS U6414 ( .A0(n4993), .A1(n4938), .B0(n5078), .B1(Data_B_i[21]),
.C0(n318), .C1(n4934), .Y(n4846) );
OAI21X1TS U6415 ( .A0(n4847), .A1(n5083), .B0(n4846), .Y(n4848) );
NAND2X1TS U6416 ( .A(n4850), .B(n5105), .Y(n4851) );
OAI21X1TS U6417 ( .A0(n5109), .A1(n4852), .B0(n4851), .Y(n4853) );
XOR2X1TS U6418 ( .A(n4853), .B(n4792), .Y(n4931) );
CMPR32X2TS U6419 ( .A(n4856), .B(n4855), .C(n4854), .CO(n4928), .S(n4838) );
NOR2X1TS U6420 ( .A(n4919), .B(n4918), .Y(n5028) );
NOR2X1TS U6421 ( .A(n5020), .B(n5028), .Y(n4921) );
CMPR32X2TS U6422 ( .A(n4859), .B(n4858), .C(n4857), .CO(n4874), .S(n4889) );
CMPR32X2TS U6423 ( .A(n4871), .B(n4870), .C(n4869), .CO(n4873), .S(n4887) );
CMPR32X2TS U6424 ( .A(n4874), .B(n4873), .C(n4872), .CO(n4916), .S(n4914) );
OR2X2TS U6425 ( .A(n4915), .B(n4914), .Y(n5037) );
NAND2X1TS U6426 ( .A(n4921), .B(n5037), .Y(n4923) );
CMPR32X2TS U6427 ( .A(n4877), .B(n4876), .C(n4875), .CO(n4910), .S(n4903) );
CMPR32X2TS U6428 ( .A(n4880), .B(n4879), .C(n4878), .CO(n4869), .S(n4892) );
OR2X2TS U6429 ( .A(n4910), .B(n4909), .Y(n7432) );
CMPR32X2TS U6430 ( .A(n4889), .B(n4888), .C(n4887), .CO(n4915), .S(n4912) );
CMPR32X2TS U6431 ( .A(n4892), .B(n4891), .C(n4890), .CO(n4911), .S(n4909) );
NOR2X1TS U6432 ( .A(n4912), .B(n4911), .Y(n4893) );
INVX2TS U6433 ( .A(n4893), .Y(n5046) );
INVX2TS U6434 ( .A(n7404), .Y(n4925) );
NOR2X2TS U6435 ( .A(n7430), .B(n4925), .Y(n5088) );
NAND2X1TS U6436 ( .A(n4897), .B(n4896), .Y(n5137) );
OAI21X2TS U6437 ( .A0(n5136), .A1(n7555), .B0(n5137), .Y(n4951) );
NAND2X1TS U6438 ( .A(n4899), .B(n4898), .Y(n4960) );
NAND2X1TS U6439 ( .A(n4903), .B(n4902), .Y(n5054) );
NAND2X1TS U6440 ( .A(n4910), .B(n4909), .Y(n7431) );
INVX2TS U6441 ( .A(n7431), .Y(n5041) );
NAND2X1TS U6442 ( .A(n4912), .B(n4911), .Y(n5045) );
NAND2X1TS U6443 ( .A(n4915), .B(n4914), .Y(n5036) );
NAND2X1TS U6444 ( .A(n4917), .B(n4916), .Y(n7120) );
NAND2X1TS U6445 ( .A(n4919), .B(n4918), .Y(n5029) );
AOI21X1TS U6446 ( .A0(n4921), .A1(n5022), .B0(n4920), .Y(n4922) );
CMPR32X2TS U6447 ( .A(n4930), .B(n4929), .C(n4928), .CO(n4947), .S(n4918) );
CMPR32X2TS U6448 ( .A(n4933), .B(n4932), .C(n4931), .CO(n4966), .S(n4943) );
AOI222XLTS U6449 ( .A0(n4935), .A1(n5062), .B0(n4976), .B1(n4992), .C0(n343),
.C1(n5074), .Y(n4936) );
AOI222XLTS U6450 ( .A0(n4993), .A1(n4939), .B0(n5078), .B1(n4938), .C0(n318),
.C1(n4972), .Y(n4940) );
CMPR32X2TS U6451 ( .A(n4945), .B(n4944), .C(n4943), .CO(n4964), .S(n4929) );
NAND2X1TS U6452 ( .A(n4947), .B(n4946), .Y(n5009) );
NAND2X1TS U6453 ( .A(n5011), .B(n5009), .Y(n4948) );
NOR2X1TS U6454 ( .A(n4958), .B(n4959), .Y(n5049) );
OAI21X1TS U6455 ( .A0(n4957), .A1(n4959), .B0(n4960), .Y(n5051) );
NAND2X1TS U6456 ( .A(n122), .B(n4954), .Y(n4955) );
NAND2X1TS U6457 ( .A(n4961), .B(n4960), .Y(n4962) );
AOI222XLTS U6458 ( .A0(n4993), .A1(n4967), .B0(n5078), .B1(Data_B_i[23]),
.C0(n318), .C1(n4997), .Y(n4968) );
INVX2TS U6459 ( .A(n5076), .Y(n5069) );
CMPR32X2TS U6460 ( .A(n4975), .B(n4974), .C(n4973), .CO(n5004), .S(n4983) );
AOI21X1TS U6461 ( .A0(n343), .A1(n5080), .B0(n4977), .Y(n4978) );
CMPR32X2TS U6462 ( .A(n4983), .B(n4982), .C(n4981), .CO(n4989), .S(n4965) );
NOR2X1TS U6463 ( .A(n4986), .B(n4985), .Y(n5014) );
NOR2X1TS U6464 ( .A(n4984), .B(n5014), .Y(n5117) );
NAND2X1TS U6465 ( .A(n5088), .B(n5117), .Y(n4988) );
NAND2X1TS U6466 ( .A(n4986), .B(n4985), .Y(n5015) );
OAI21X1TS U6467 ( .A0(n5009), .A1(n5014), .B0(n5015), .Y(n5120) );
AOI21X1TS U6468 ( .A0(n5100), .A1(n5117), .B0(n5120), .Y(n4987) );
CMPR32X2TS U6469 ( .A(n4991), .B(n4990), .C(n4989), .CO(n5006), .S(n4985) );
AOI222XLTS U6470 ( .A0(n4993), .A1(n4992), .B0(n5078), .B1(Data_B_i[24]),
.C0(n318), .C1(n5060), .Y(n4994) );
NAND2X1TS U6471 ( .A(n342), .B(n5105), .Y(n4999) );
CMPR32X2TS U6472 ( .A(n5069), .B(n5004), .C(n5003), .CO(n5057), .S(n4990) );
NAND2X1TS U6473 ( .A(n5006), .B(n5005), .Y(n5121) );
NAND2X1TS U6474 ( .A(n5087), .B(n5121), .Y(n5007) );
NAND2X1TS U6475 ( .A(n5088), .B(n5011), .Y(n5013) );
AOI21X1TS U6476 ( .A0(n5100), .A1(n5011), .B0(n5010), .Y(n5012) );
NAND2X1TS U6477 ( .A(n5016), .B(n5015), .Y(n5017) );
INVX2TS U6478 ( .A(n5019), .Y(n5033) );
NAND2X1TS U6479 ( .A(n5033), .B(n5037), .Y(n5024) );
NOR2X1TS U6480 ( .A(n7430), .B(n5024), .Y(n7116) );
INVX1TS U6481 ( .A(n5020), .Y(n7121) );
AOI21X1TS U6482 ( .A0(n5032), .A1(n5037), .B0(n5022), .Y(n5023) );
AOI21X1TS U6483 ( .A0(n7117), .A1(n7121), .B0(n5025), .Y(n5026) );
NAND2X1TS U6484 ( .A(n5040), .B(n5033), .Y(n5035) );
AOI21X1TS U6485 ( .A0(n5042), .A1(n5033), .B0(n5032), .Y(n5034) );
NAND2X1TS U6486 ( .A(n5037), .B(n5036), .Y(n5038) );
NAND2X1TS U6487 ( .A(n5040), .B(n7432), .Y(n5044) );
AOI21X1TS U6488 ( .A0(n5042), .A1(n7432), .B0(n5041), .Y(n5043) );
NAND2X1TS U6489 ( .A(n5046), .B(n5045), .Y(n5047) );
AOI21X1TS U6490 ( .A0(n5051), .A1(n122), .B0(n5050), .Y(n5052) );
NAND2X1TS U6491 ( .A(n5054), .B(n123), .Y(n5055) );
CMPR32X2TS U6492 ( .A(n5059), .B(n5058), .C(n5057), .CO(n5090), .S(n5005) );
AOI222XLTS U6493 ( .A0(n5063), .A1(n5062), .B0(n5078), .B1(n5061), .C0(n318),
.C1(n5074), .Y(n5064) );
CMPR32X2TS U6494 ( .A(n5070), .B(n5069), .C(n5068), .CO(n5071), .S(n5058) );
CMPR32X2TS U6495 ( .A(n5073), .B(n5072), .C(n5071), .CO(n5092), .S(n5089) );
INVX2TS U6496 ( .A(n7420), .Y(n7416) );
CMPR32X2TS U6497 ( .A(n5077), .B(n5076), .C(n5075), .CO(n5104), .S(n5073) );
AOI21X1TS U6498 ( .A0(n318), .A1(n5080), .B0(n5079), .Y(n5082) );
NAND2X1TS U6499 ( .A(n5117), .B(n5097), .Y(n7403) );
NAND2X1TS U6500 ( .A(n5088), .B(n5099), .Y(n5102) );
NAND2X1TS U6501 ( .A(n5090), .B(n5089), .Y(n7128) );
NAND2X1TS U6502 ( .A(n5092), .B(n5091), .Y(n5132) );
AOI21X1TS U6503 ( .A0(n5120), .A1(n5097), .B0(n5096), .Y(n7407) );
AOI21X1TS U6504 ( .A0(n5100), .A1(n5099), .B0(n5098), .Y(n5101) );
CMPR32X2TS U6505 ( .A(n7416), .B(n5104), .C(n5103), .CO(n5113), .S(n5091) );
NAND2X1TS U6506 ( .A(n5106), .B(n5105), .Y(n5107) );
NAND2X1TS U6507 ( .A(n5113), .B(n5112), .Y(n7405) );
NAND2X1TS U6508 ( .A(n5114), .B(n7405), .Y(n5115) );
NAND2X1TS U6509 ( .A(n7404), .B(n5125), .Y(n5127) );
NOR2X1TS U6510 ( .A(n7430), .B(n5127), .Y(n7124) );
INVX2TS U6511 ( .A(n5119), .Y(n7129) );
NAND2X1TS U6512 ( .A(n7124), .B(n7129), .Y(n5130) );
AOI21X1TS U6513 ( .A0(n7410), .A1(n5125), .B0(n5124), .Y(n5126) );
OAI21X1TS U6514 ( .A0(n7429), .A1(n5127), .B0(n5126), .Y(n7125) );
AOI21X1TS U6515 ( .A0(n7125), .A1(n7129), .B0(n5128), .Y(n5129) );
NAND2X1TS U6516 ( .A(n5133), .B(n5132), .Y(n5134) );
NAND2X1TS U6517 ( .A(n5138), .B(n5137), .Y(n5139) );
ADDFHX1TS U6518 ( .A(n5143), .B(n5142), .CI(n5141), .CO(n5167), .S(n3205) );
CMPR32X2TS U6519 ( .A(n5146), .B(n5145), .C(n5144), .CO(n5158), .S(n5153) );
OAI22X1TS U6520 ( .A0(n224), .A1(n5150), .B0(n5149), .B1(n5159), .Y(n5164)
);
XNOR2X1TS U6521 ( .A(n7673), .B(n245), .Y(n5162) );
OAI22X1TS U6522 ( .A0(n299), .A1(n5152), .B0(n295), .B1(n5162), .Y(n5163) );
CMPR32X2TS U6523 ( .A(n5155), .B(n5154), .C(n5153), .CO(n5156), .S(n5141) );
AO21X1TS U6524 ( .A0(n224), .A1(n5160), .B0(n5159), .Y(n5178) );
CLKINVX1TS U6525 ( .A(n367), .Y(n5161) );
XNOR2X1TS U6526 ( .A(n7673), .B(n257), .Y(n5181) );
OAI22X1TS U6527 ( .A0(n299), .A1(n5162), .B0(n296), .B1(n5181), .Y(n5183) );
CMPR32X2TS U6528 ( .A(n5165), .B(n5164), .C(n5163), .CO(n5176), .S(n5157) );
NAND2X1TS U6529 ( .A(n7145), .B(n5173), .Y(n5175) );
NAND2X1TS U6530 ( .A(n5167), .B(n5166), .Y(n7170) );
NAND2X1TS U6531 ( .A(n5169), .B(n5168), .Y(n6576) );
CMPR32X2TS U6532 ( .A(n5178), .B(n5177), .C(n5176), .CO(n5187), .S(n5168) );
OAI22X1TS U6533 ( .A0(n299), .A1(n5181), .B0(n295), .B1(n7672), .Y(n7670) );
CMPR32X2TS U6534 ( .A(n5185), .B(n5184), .C(n5183), .CO(n7669), .S(n5177) );
NOR2X1TS U6535 ( .A(n5187), .B(n5186), .Y(n7662) );
NAND2X1TS U6536 ( .A(n5187), .B(n5186), .Y(n7661) );
INVX2TS U6537 ( .A(Data_A_i[29]), .Y(n5257) );
XOR2X1TS U6538 ( .A(Data_A_i[29]), .B(Data_A_i[28]), .Y(n5252) );
CLKBUFX2TS U6539 ( .A(n5832), .Y(n5941) );
CLKBUFX2TS U6540 ( .A(n5870), .Y(n6080) );
NAND2X1TS U6541 ( .A(n5286), .B(n5315), .Y(n5340) );
NAND2X1TS U6542 ( .A(n5475), .B(n5471), .Y(n5191) );
AOI21X1TS U6543 ( .A0(n5340), .A1(n5192), .B0(n5191), .Y(n5193) );
NOR2X1TS U6544 ( .A(n5194), .B(n5367), .Y(n5199) );
NAND2X1TS U6545 ( .A(n5199), .B(n460), .Y(n5201) );
INVX2TS U6546 ( .A(n5353), .Y(n5444) );
NAND2X1TS U6547 ( .A(n6685), .B(n6659), .Y(n5449) );
NAND2X1TS U6548 ( .A(n5449), .B(n5441), .Y(n5363) );
NAND2X1TS U6549 ( .A(n6659), .B(n6745), .Y(n5368) );
AOI21X1TS U6550 ( .A0(n5444), .A1(n5199), .B0(n5198), .Y(n5200) );
NAND2X1TS U6551 ( .A(n6788), .B(n6745), .Y(n5226) );
NAND2X1TS U6552 ( .A(n5202), .B(n5226), .Y(n5203) );
NAND2BX1TS U6553 ( .AN(n5205), .B(n5206), .Y(n5550) );
CLKBUFX2TS U6554 ( .A(n5550), .Y(n6707) );
CLKBUFX2TS U6555 ( .A(n5699), .Y(n6365) );
CLKBUFX2TS U6556 ( .A(Data_B_i[41]), .Y(n6689) );
AOI222XLTS U6557 ( .A0(n6664), .A1(n6690), .B0(n6365), .B1(n6689), .C0(n6425), .C1(n6659), .Y(n5207) );
XOR2X1TS U6558 ( .A(n5208), .B(n355), .Y(n5488) );
NAND2X1TS U6559 ( .A(n5190), .B(n5210), .Y(n5211) );
NOR2BX2TS U6560 ( .AN(n5214), .B(n5213), .Y(n6738) );
XOR2X1TS U6561 ( .A(n5216), .B(n6973), .Y(n5469) );
NAND2X1TS U6562 ( .A(n174), .B(n5217), .Y(n5218) );
INVX2TS U6563 ( .A(n5913), .Y(n5936) );
XOR2X1TS U6564 ( .A(n5221), .B(n6973), .Y(n5274) );
INVX2TS U6565 ( .A(n5913), .Y(n5910) );
CLKBUFX2TS U6566 ( .A(n6970), .Y(n6955) );
NOR2BX4TS U6567 ( .AN(n5511), .B(n5224), .Y(n5273) );
NAND2X1TS U6568 ( .A(n5226), .B(n5368), .Y(n5227) );
AOI21X1TS U6569 ( .A0(n5228), .A1(n5363), .B0(n5227), .Y(n5229) );
NAND2X1TS U6570 ( .A(n6825), .B(n6849), .Y(n5388) );
NAND2X1TS U6571 ( .A(n6788), .B(n6825), .Y(n5398) );
NAND2X1TS U6572 ( .A(n5388), .B(n5398), .Y(n5305) );
NAND2X1TS U6573 ( .A(n6870), .B(n6849), .Y(n5302) );
NAND2X1TS U6574 ( .A(n5304), .B(n5302), .Y(n5233) );
CLKBUFX2TS U6575 ( .A(n5694), .Y(n6623) );
CLKBUFX2TS U6576 ( .A(n5696), .Y(n6180) );
AOI222XLTS U6577 ( .A0(n6410), .A1(n6527), .B0(n6180), .B1(n6777), .C0(n319),
.C1(n6404), .Y(n5236) );
XOR2X1TS U6578 ( .A(n5237), .B(n6412), .Y(n5486) );
NOR2X1TS U6579 ( .A(n6942), .B(n6959), .Y(n5495) );
NOR2X1TS U6580 ( .A(n6959), .B(n6967), .Y(n5503) );
NOR2X1TS U6581 ( .A(n5495), .B(n5503), .Y(n5243) );
INVX2TS U6582 ( .A(n5455), .Y(n7033) );
NOR2X1TS U6583 ( .A(n7033), .B(n6987), .Y(n5419) );
NAND2X1TS U6584 ( .A(n5457), .B(n5248), .Y(n5250) );
NAND2X1TS U6585 ( .A(n6870), .B(n6901), .Y(n5309) );
NAND2X1TS U6586 ( .A(n5309), .B(n5302), .Y(n5240) );
NAND2X1TS U6587 ( .A(n6942), .B(Data_B_i[47]), .Y(n5264) );
NAND2X1TS U6588 ( .A(n5264), .B(n5427), .Y(n5493) );
NAND2X1TS U6589 ( .A(n6959), .B(n6967), .Y(n5504) );
NAND2X1TS U6590 ( .A(n5504), .B(n5494), .Y(n5242) );
AOI21X1TS U6591 ( .A0(n5243), .A1(n5493), .B0(n5242), .Y(n5244) );
NAND2X1TS U6592 ( .A(n6981), .B(n6968), .Y(n5409) );
NAND2X1TS U6593 ( .A(n6981), .B(n6967), .Y(n5403) );
NAND2X1TS U6594 ( .A(n5409), .B(n5403), .Y(n5460) );
NAND2X1TS U6595 ( .A(n7033), .B(n6968), .Y(n5458) );
AOI21X1TS U6596 ( .A0(n5463), .A1(n5248), .B0(n5247), .Y(n5249) );
CLKBUFX2TS U6597 ( .A(n5832), .Y(n6082) );
CLKBUFX2TS U6598 ( .A(n5976), .Y(n6078) );
INVX2TS U6599 ( .A(n5455), .Y(n7198) );
AOI21X1TS U6600 ( .A0(n6078), .A1(n6968), .B0(n5255), .Y(n5256) );
INVX2TS U6601 ( .A(n5257), .Y(n5942) );
XOR2X1TS U6602 ( .A(n5258), .B(n5942), .Y(n5330) );
NAND2X1TS U6603 ( .A(n453), .B(n5428), .Y(n5262) );
AOI21X1TS U6604 ( .A0(n5499), .A1(n5428), .B0(n5260), .Y(n5261) );
NAND2X1TS U6605 ( .A(n5265), .B(n5264), .Y(n5266) );
NAND2BX1TS U6606 ( .AN(n5269), .B(n5270), .Y(n5688) );
CLKBUFX2TS U6607 ( .A(n5688), .Y(n6363) );
XNOR2X1TS U6608 ( .A(Data_A_i[33]), .B(Data_A_i[34]), .Y(n5268) );
CLKBUFX2TS U6609 ( .A(n5689), .Y(n5987) );
AND3X2TS U6610 ( .A(n5270), .B(n5269), .C(n5268), .Y(n5985) );
AOI222XLTS U6611 ( .A0(n5861), .A1(n6673), .B0(n5987), .B1(n292), .C0(n6399),
.C1(n6627), .Y(n5271) );
INVX2TS U6612 ( .A(n6544), .Y(n6289) );
XOR2X1TS U6613 ( .A(n5272), .B(n6289), .Y(n5329) );
NAND2X1TS U6614 ( .A(n5275), .B(n5346), .Y(n5276) );
NAND2BX1TS U6615 ( .AN(n5278), .B(n5279), .Y(n5625) );
CLKBUFX2TS U6616 ( .A(n5625), .Y(n6224) );
NOR2BX2TS U6617 ( .AN(n5278), .B(n5277), .Y(n6221) );
AND3X2TS U6618 ( .A(n5279), .B(n5278), .C(n5277), .Y(n6339) );
AOI222XLTS U6619 ( .A0(n6268), .A1(n5917), .B0(n6221), .B1(n6282), .C0(n6339), .C1(n289), .Y(n5280) );
AOI21X1TS U6620 ( .A0(n5342), .A1(n5316), .B0(n5284), .Y(n5289) );
NAND2X1TS U6621 ( .A(n5287), .B(n5286), .Y(n5288) );
NAND2BX1TS U6622 ( .AN(n5291), .B(n5292), .Y(n5523) );
CLKBUFX2TS U6623 ( .A(n5523), .Y(n6386) );
NOR2X2TS U6624 ( .A(n5291), .B(n5292), .Y(n6923) );
NOR2BX2TS U6625 ( .AN(n5291), .B(n5290), .Y(n6782) );
AND3X2TS U6626 ( .A(n5292), .B(n5291), .C(n5290), .Y(n6960) );
AOI222XLTS U6627 ( .A0(n6312), .A1(n6194), .B0(n6625), .B1(n5957), .C0(n6815), .C1(n255), .Y(n5293) );
INVX2TS U6628 ( .A(n6984), .Y(n6546) );
NAND2X1TS U6629 ( .A(n453), .B(n5492), .Y(n5296) );
AOI21X1TS U6630 ( .A0(n5499), .A1(n5492), .B0(n5493), .Y(n5295) );
NAND2X1TS U6631 ( .A(n5297), .B(n5494), .Y(n5298) );
CLKBUFX2TS U6632 ( .A(n5689), .Y(n6360) );
BUFX3TS U6633 ( .A(n5985), .Y(n5920) );
AOI222XLTS U6634 ( .A0(n5861), .A1(n6717), .B0(n6360), .B1(n6897), .C0(n5920), .C1(n6650), .Y(n5299) );
OAI21X1TS U6635 ( .A0(n6899), .A1(n6363), .B0(n5299), .Y(n5300) );
NAND2X1TS U6636 ( .A(n5301), .B(n5304), .Y(n5307) );
AOI21X1TS U6637 ( .A0(n5305), .A1(n5304), .B0(n5303), .Y(n5306) );
NAND2X1TS U6638 ( .A(n5310), .B(n5309), .Y(n5311) );
AOI222XLTS U6639 ( .A0(n6465), .A1(n6627), .B0(n6536), .B1(n6778), .C0(n6621), .C1(n6462), .Y(n5313) );
NAND2X1TS U6640 ( .A(n5316), .B(n5315), .Y(n5317) );
CLKBUFX2TS U6641 ( .A(n5318), .Y(n6521) );
CLKBUFX2TS U6642 ( .A(Data_B_i[30]), .Y(n5761) );
XOR2X1TS U6643 ( .A(n5320), .B(n6940), .Y(n6172) );
OAI21X1TS U6644 ( .A0(n5447), .A1(n5322), .B0(n5321), .Y(n5325) );
NAND2X1TS U6645 ( .A(n5376), .B(n5374), .Y(n5324) );
XOR2X1TS U6646 ( .A(n5327), .B(Data_A_i[47]), .Y(n6171) );
CMPR32X2TS U6647 ( .A(n5330), .B(n5329), .C(n5328), .CO(n6211), .S(n5563) );
CLKINVX1TS U6648 ( .A(n5463), .Y(n5331) );
INVX2TS U6649 ( .A(n5333), .Y(n5405) );
NAND2X1TS U6650 ( .A(n5405), .B(n5403), .Y(n5334) );
CLKBUFX2TS U6651 ( .A(n5814), .Y(n6186) );
CLKBUFX2TS U6652 ( .A(Data_B_i[51]), .Y(n6785) );
XNOR2X1TS U6653 ( .A(Data_A_i[30]), .B(Data_A_i[31]), .Y(n5336) );
NOR2BX1TS U6654 ( .AN(n5337), .B(n5336), .Y(n6000) );
CLKBUFX2TS U6655 ( .A(n6000), .Y(n6183) );
AOI222XLTS U6656 ( .A0(n5840), .A1(n6785), .B0(n6183), .B1(n6927), .C0(n6271), .C1(n6717), .Y(n5338) );
OAI21X1TS U6657 ( .A0(n6939), .A1(n6186), .B0(n5338), .Y(n5339) );
INVX2TS U6658 ( .A(n6380), .Y(n6090) );
XOR2X1TS U6659 ( .A(n5339), .B(n6090), .Y(n5437) );
AOI21X1TS U6660 ( .A0(n5342), .A1(n5341), .B0(n5340), .Y(n5473) );
NAND2X1TS U6661 ( .A(n5343), .B(n5471), .Y(n5344) );
OAI21X1TS U6662 ( .A0(n6235), .A1(n6386), .B0(n207), .Y(n5345) );
NAND2X1TS U6663 ( .A(n5350), .B(n5349), .Y(n5351) );
AOI222XLTS U6664 ( .A0(n6268), .A1(n5978), .B0(n6221), .B1(n6336), .C0(n6339), .C1(Data_B_i[34]), .Y(n5352) );
OAI21X1TS U6665 ( .A0(n5447), .A1(n5354), .B0(n5353), .Y(n5357) );
NAND2X1TS U6666 ( .A(n5443), .B(n5441), .Y(n5356) );
CLKBUFX2TS U6667 ( .A(n5703), .Y(n5684) );
NOR2BX2TS U6668 ( .AN(n5359), .B(n5358), .Y(n5674) );
AND3X2TS U6669 ( .A(n5360), .B(n5359), .C(n5358), .Y(n6197) );
AOI222XLTS U6670 ( .A0(n6746), .A1(n6222), .B0(n5674), .B1(n6483), .C0(n6197), .C1(n6482), .Y(n5361) );
NAND2X1TS U6671 ( .A(n460), .B(n5364), .Y(n5366) );
AOI21X1TS U6672 ( .A0(n5444), .A1(n5364), .B0(n5363), .Y(n5365) );
NAND2X1TS U6673 ( .A(n5369), .B(n5368), .Y(n5370) );
NAND2X1TS U6674 ( .A(n5373), .B(n5376), .Y(n5379) );
AOI21X1TS U6675 ( .A0(n5377), .A1(n5376), .B0(n5375), .Y(n5378) );
NAND2X1TS U6676 ( .A(n5382), .B(n5381), .Y(n5383) );
AOI222XLTS U6677 ( .A0(n6198), .A1(n6201), .B0(n5674), .B1(n6428), .C0(n6197), .C1(Data_B_i[36]), .Y(n5385) );
XOR2X1TS U6678 ( .A(n5386), .B(n6829), .Y(n5395) );
OAI21X1TS U6679 ( .A0(n5426), .A1(n5397), .B0(n5398), .Y(n5391) );
NAND2X1TS U6680 ( .A(n5389), .B(n5388), .Y(n5390) );
AOI222XLTS U6681 ( .A0(n6465), .A1(n6462), .B0(n6180), .B1(n6710), .C0(n319),
.C1(n6388), .Y(n5392) );
XOR2X1TS U6682 ( .A(n5393), .B(n6412), .Y(n5394) );
NAND2X1TS U6683 ( .A(n5399), .B(n5398), .Y(n5400) );
AOI222XLTS U6684 ( .A0(n6465), .A1(n6404), .B0(n6180), .B1(n6690), .C0(n6300), .C1(n6689), .Y(n5401) );
XOR2X1TS U6685 ( .A(n5402), .B(n6412), .Y(n5560) );
NAND2X1TS U6686 ( .A(n5457), .B(n5405), .Y(n5407) );
AOI21X1TS U6687 ( .A0(n5463), .A1(n5405), .B0(n5404), .Y(n5406) );
NAND2X1TS U6688 ( .A(n5410), .B(n5409), .Y(n5411) );
CLKBUFX2TS U6689 ( .A(Data_B_i[51]), .Y(n6937) );
AOI222XLTS U6690 ( .A0(n6080), .A1(n6968), .B0(n5833), .B1(n6937), .C0(n6078), .C1(n6748), .Y(n5413) );
XOR2X1TS U6691 ( .A(n5414), .B(n5942), .Y(n5559) );
CLKBUFX2TS U6692 ( .A(n5688), .Y(n6401) );
CLKBUFX2TS U6693 ( .A(n5746), .Y(n6315) );
AOI222XLTS U6694 ( .A0(n6315), .A1(n6627), .B0(n6360), .B1(n6778), .C0(n6399), .C1(n6462), .Y(n5415) );
XOR2X1TS U6695 ( .A(n5416), .B(n6289), .Y(n5558) );
NAND2X1TS U6696 ( .A(n5457), .B(n5456), .Y(n5418) );
NAND2X1TS U6697 ( .A(n5420), .B(n5458), .Y(n5421) );
CLKBUFX2TS U6698 ( .A(n5870), .Y(n5949) );
INVX2TS U6699 ( .A(n5455), .Y(n6969) );
AOI222XLTS U6700 ( .A0(n5949), .A1(n6969), .B0(n5833), .B1(n6954), .C0(n6078), .C1(n6785), .Y(n5422) );
XOR2X1TS U6701 ( .A(n5423), .B(n5942), .Y(n5491) );
NAND2X1TS U6702 ( .A(n5428), .B(n5427), .Y(n5429) );
AOI222XLTS U6703 ( .A0(n5746), .A1(n6650), .B0(n6360), .B1(n6811), .C0(n6399), .C1(n6527), .Y(n5430) );
XOR2X1TS U6704 ( .A(n5431), .B(n6289), .Y(n5490) );
AOI21X1TS U6705 ( .A0(n5444), .A1(n5443), .B0(n5442), .Y(n5445) );
OAI21X1TS U6706 ( .A0(n5447), .A1(n5446), .B0(n5445), .Y(n5452) );
XOR2X4TS U6707 ( .A(n5452), .B(n5451), .Y(n6619) );
BUFX3TS U6708 ( .A(n5703), .Y(n6794) );
AOI222XLTS U6709 ( .A0(n6414), .A1(n6267), .B0(n6791), .B1(n6519), .C0(n6197), .C1(Data_B_i[38]), .Y(n5453) );
OAI21X1TS U6710 ( .A0(n6619), .A1(n6794), .B0(n5453), .Y(n5454) );
NAND2X1TS U6711 ( .A(n5457), .B(n5462), .Y(n5465) );
AOI21X1TS U6712 ( .A0(n5463), .A1(n5462), .B0(n5461), .Y(n5464) );
OAI21X1TS U6713 ( .A0(n7036), .A1(n6082), .B0(n5466), .Y(n5467) );
XOR2X1TS U6714 ( .A(n5467), .B(n5942), .Y(n6205) );
NAND2X1TS U6715 ( .A(n5476), .B(n5475), .Y(n5477) );
XNOR2X1TS U6716 ( .A(n5478), .B(n5477), .Y(n5479) );
INVX2TS U6717 ( .A(n5479), .Y(n6284) );
AOI222XLTS U6718 ( .A0(n6312), .A1(n6282), .B0(n6625), .B1(n6233), .C0(n6735), .C1(n256), .Y(n5480) );
XOR2X1TS U6719 ( .A(n5481), .B(n6546), .Y(n6209) );
AOI222XLTS U6720 ( .A0(n6664), .A1(n6710), .B0(n6365), .B1(Data_B_i[42]),
.C0(n6425), .C1(n6745), .Y(n5482) );
INVX2TS U6721 ( .A(n838), .Y(n6611) );
XOR2X1TS U6722 ( .A(n5483), .B(n6611), .Y(n6208) );
AOI222XLTS U6723 ( .A0(n6002), .A1(n6968), .B0(n6183), .B1(n6937), .C0(n6271), .C1(n6748), .Y(n5484) );
XOR2X1TS U6724 ( .A(n5485), .B(n6090), .Y(n6207) );
NOR2XLTS U6725 ( .A(n452), .B(n5495), .Y(n5498) );
NAND2X1TS U6726 ( .A(n5498), .B(n453), .Y(n5501) );
OAI21XLTS U6727 ( .A0(n5496), .A1(n5495), .B0(n5494), .Y(n5497) );
AOI21X1TS U6728 ( .A0(n5499), .A1(n5498), .B0(n5497), .Y(n5500) );
NAND2X1TS U6729 ( .A(n5505), .B(n5504), .Y(n5506) );
AOI222XLTS U6730 ( .A0(n5840), .A1(n6748), .B0(n6183), .B1(n6926), .C0(n6271), .C1(n6673), .Y(n5508) );
XOR2X1TS U6731 ( .A(n5513), .B(n6546), .Y(n5536) );
XOR2X1TS U6732 ( .A(n5515), .B(n6829), .Y(n5535) );
CLKBUFX2TS U6733 ( .A(n5550), .Y(n6679) );
AOI222XLTS U6734 ( .A0(n6664), .A1(n6617), .B0(n6676), .B1(Data_B_i[39]),
.C0(n6323), .C1(n293), .Y(n5516) );
OAI21X1TS U6735 ( .A0(n6619), .A1(n6679), .B0(n5516), .Y(n5517) );
INVX2TS U6736 ( .A(n838), .Y(n6708) );
XOR2X1TS U6737 ( .A(n5517), .B(n6708), .Y(n5549) );
AOI222XLTS U6738 ( .A0(n6268), .A1(n6001), .B0(n6221), .B1(n6233), .C0(n6339), .C1(n256), .Y(n5518) );
INVX2TS U6739 ( .A(n6945), .Y(n6390) );
XOR2X1TS U6740 ( .A(n5519), .B(n6390), .Y(n5548) );
XOR2X1TS U6741 ( .A(n5522), .B(n6546), .Y(n5554) );
BUFX4TS U6742 ( .A(n6923), .Y(n6893) );
NAND2X1TS U6743 ( .A(n6893), .B(n5912), .Y(n5524) );
BUFX3TS U6744 ( .A(n6782), .Y(n6946) );
OAI21X1TS U6745 ( .A0(n5937), .A1(n6962), .B0(n960), .Y(n5526) );
XOR2X1TS U6746 ( .A(n5526), .B(n6546), .Y(n5614) );
INVX1TS U6747 ( .A(n5574), .Y(n5529) );
NOR2BX2TS U6748 ( .AN(n5575), .B(n5529), .Y(n5553) );
CLKBUFX2TS U6749 ( .A(n5999), .Y(n6087) );
AOI222XLTS U6750 ( .A0(n5840), .A1(n6717), .B0(n6183), .B1(n6897), .C0(n6087), .C1(n6650), .Y(n5533) );
ADDFHX2TS U6751 ( .A(n5537), .B(n5536), .CI(n5535), .CO(n5545), .S(n5581) );
XOR2X1TS U6752 ( .A(n5539), .B(n6390), .Y(n5585) );
XOR2X1TS U6753 ( .A(n5541), .B(n5853), .Y(n5584) );
AOI222XLTS U6754 ( .A0(n6198), .A1(n5978), .B0(n5674), .B1(n6336), .C0(n6197), .C1(n290), .Y(n5542) );
XOR2X1TS U6755 ( .A(n5543), .B(n6829), .Y(n5583) );
CLKBUFX2TS U6756 ( .A(n5550), .Y(n5763) );
AOI222XLTS U6757 ( .A0(n6609), .A1(n6519), .B0(n5699), .B1(n293), .C0(n6323),
.C1(n6482), .Y(n5551) );
ADDFHX2TS U6758 ( .A(n5555), .B(n5554), .CI(n5553), .CO(n5547), .S(n5593) );
AOI222XLTS U6759 ( .A0(n5746), .A1(n6527), .B0(n5987), .B1(Data_B_i[44]),
.C0(n5985), .C1(n6404), .Y(n5556) );
CMPR32X2TS U6760 ( .A(n5560), .B(n5559), .C(n5558), .CO(n5568), .S(n5601) );
AOI222XLTS U6761 ( .A0(n6080), .A1(n6785), .B0(n5833), .B1(n6927), .C0(n6078), .C1(n6717), .Y(n5570) );
CLKBUFX2TS U6762 ( .A(n6000), .Y(n6088) );
AOI222XLTS U6763 ( .A0(n5840), .A1(n6673), .B0(n6088), .B1(n6866), .C0(n6271), .C1(n6627), .Y(n5572) );
AOI222XLTS U6764 ( .A0(n6198), .A1(n5917), .B0(n5674), .B1(n6282), .C0(n6197), .C1(n289), .Y(n5576) );
XOR2X1TS U6765 ( .A(n5577), .B(n6829), .Y(n5609) );
AOI222XLTS U6766 ( .A0(n6268), .A1(n5998), .B0(n339), .B1(n6193), .C0(n6716),
.C1(Data_B_i[30]), .Y(n5578) );
CMPR32X2TS U6767 ( .A(n5582), .B(n5581), .C(n5580), .CO(n5597), .S(n5638) );
CMPR32X2TS U6768 ( .A(n5585), .B(n5584), .C(n5583), .CO(n5580), .S(n5645) );
AOI222XLTS U6769 ( .A0(n6465), .A1(n6689), .B0(n6180), .B1(n6617), .C0(n6621), .C1(n6222), .Y(n5586) );
CLKBUFX2TS U6770 ( .A(Data_B_i[37]), .Y(n6482) );
XOR2X1TS U6771 ( .A(n5589), .B(n6708), .Y(n5635) );
AOI222XLTS U6772 ( .A0(n6315), .A1(n6462), .B0(n5987), .B1(n6710), .C0(n5985), .C1(n6388), .Y(n5590) );
XOR2X1TS U6773 ( .A(n5591), .B(n6289), .Y(n5634) );
NOR2X2TS U6774 ( .A(n7319), .B(n7327), .Y(n6162) );
CLKBUFX2TS U6775 ( .A(n5833), .Y(n5977) );
AOI222XLTS U6776 ( .A0(n6080), .A1(n6748), .B0(n5977), .B1(n6926), .C0(n6078), .C1(n6673), .Y(n5604) );
OAI21X1TS U6777 ( .A0(n6929), .A1(n6082), .B0(n5604), .Y(n5605) );
AOI222XLTS U6778 ( .A0(n6002), .A1(n6650), .B0(n6183), .B1(n6811), .C0(n6271), .C1(n6527), .Y(n5606) );
CMPR32X2TS U6779 ( .A(n5613), .B(n5612), .C(n5611), .CO(n5639), .S(n5668) );
AOI222XLTS U6780 ( .A0(n6850), .A1(n5957), .B0(n339), .B1(n255), .C0(n6716),
.C1(n6168), .Y(n5616) );
OAI21X1TS U6781 ( .A0(n6619), .A1(n6539), .B0(n5620), .Y(n5621) );
XOR2X1TS U6782 ( .A(n5621), .B(Data_A_i[38]), .Y(n5666) );
AOI222XLTS U6783 ( .A0(n6198), .A1(n6001), .B0(n5674), .B1(n6233), .C0(n6197), .C1(n256), .Y(n5622) );
INVX2TS U6784 ( .A(n6873), .Y(n6217) );
XOR2X1TS U6785 ( .A(n5623), .B(n6217), .Y(n5665) );
XOR2X1TS U6786 ( .A(n5629), .B(n6390), .Y(n5680) );
NAND2X1TS U6787 ( .A(n6818), .B(n5912), .Y(n5630) );
AOI222XLTS U6788 ( .A0(n6315), .A1(n6404), .B0(n5987), .B1(n6690), .C0(n5985), .C1(n6689), .Y(n5646) );
CLKBUFX2TS U6789 ( .A(n5976), .Y(n5956) );
AOI222XLTS U6790 ( .A0(n6080), .A1(n6717), .B0(n5833), .B1(n6897), .C0(n5956), .C1(n6650), .Y(n5648) );
INVX2TS U6791 ( .A(n5257), .Y(n5889) );
CLKBUFX2TS U6792 ( .A(n5814), .Y(n6273) );
CLKBUFX2TS U6793 ( .A(n5840), .Y(n6165) );
AOI222XLTS U6794 ( .A0(n6165), .A1(n6627), .B0(n6183), .B1(n6778), .C0(n6271), .C1(n6462), .Y(n5650) );
AOI222XLTS U6795 ( .A0(n6315), .A1(n6388), .B0(n5987), .B1(n6660), .C0(n5985), .C1(n6267), .Y(n5660) );
INVX2TS U6796 ( .A(n6544), .Y(n5989) );
AOI222XLTS U6797 ( .A0(n6165), .A1(n6462), .B0(n6088), .B1(n6710), .C0(n6087), .C1(n6388), .Y(n5670) );
XOR2X1TS U6798 ( .A(n5673), .B(n5672), .Y(n5733) );
CLKBUFX2TS U6799 ( .A(n5674), .Y(n6524) );
AOI222XLTS U6800 ( .A0(n6315), .A1(n6267), .B0(n6360), .B1(n6519), .C0(n5920), .C1(n6201), .Y(n5677) );
INVX2TS U6801 ( .A(n6544), .Y(n6402) );
XOR2X1TS U6802 ( .A(n5682), .B(n6708), .Y(n6093) );
AOI222XLTS U6803 ( .A0(n6198), .A1(n5998), .B0(n6524), .B1(n5957), .C0(n6613), .C1(Data_B_i[30]), .Y(n5683) );
CLKBUFX2TS U6804 ( .A(n5688), .Y(n5875) );
AOI222XLTS U6805 ( .A0(n5861), .A1(n6222), .B0(n5689), .B1(n6483), .C0(n5920), .C1(n6070), .Y(n5690) );
OAI21X1TS U6806 ( .A0(n6522), .A1(n5875), .B0(n5690), .Y(n5691) );
AOI222XLTS U6807 ( .A0(n6165), .A1(n6388), .B0(n6088), .B1(n6660), .C0(n6087), .C1(n6267), .Y(n5692) );
INVX2TS U6808 ( .A(n6380), .Y(n6005) );
CLKBUFX2TS U6809 ( .A(n5694), .Y(n6073) );
CLKBUFX2TS U6810 ( .A(n5696), .Y(n6071) );
OAI21X1TS U6811 ( .A0(n118), .A1(n6073), .B0(n5697), .Y(n5698) );
XOR2X1TS U6812 ( .A(n5698), .B(Data_A_i[38]), .Y(n5720) );
CLKBUFX2TS U6813 ( .A(n289), .Y(n6281) );
OAI21X1TS U6814 ( .A0(n6284), .A1(n5763), .B0(n5700), .Y(n5701) );
XOR2X1TS U6815 ( .A(n5701), .B(Data_A_i[41]), .Y(n5719) );
ADDHXLTS U6816 ( .A(Data_A_i[47]), .B(n5702), .CO(n5673), .S(n5715) );
CLKBUFX2TS U6817 ( .A(n5703), .Y(n6828) );
AOI222X1TS U6818 ( .A0(n6198), .A1(n254), .B0(n6524), .B1(n5986), .C0(n6613),
.C1(n5933), .Y(n5704) );
XOR2X1TS U6819 ( .A(n5705), .B(n6217), .Y(n5714) );
AOI222X1TS U6820 ( .A0(n6198), .A1(n5948), .B0(n6524), .B1(n5933), .C0(n6613), .C1(n5936), .Y(n5706) );
OAI21X1TS U6821 ( .A0(n6794), .A1(n5913), .B0(n201), .Y(n5710) );
XOR2X1TS U6822 ( .A(n5712), .B(Data_A_i[38]), .Y(n5784) );
CLKBUFX2TS U6823 ( .A(n5833), .Y(n6079) );
AOI222XLTS U6824 ( .A0(n6080), .A1(n6527), .B0(n6079), .B1(Data_B_i[44]),
.C0(n5956), .C1(n6404), .Y(n5716) );
XOR2X1TS U6825 ( .A(n5717), .B(Data_A_i[29]), .Y(n5782) );
AOI222XLTS U6826 ( .A0(n6315), .A1(n6689), .B0(n5987), .B1(n6617), .C0(n6399), .C1(n6222), .Y(n5721) );
XOR2X1TS U6827 ( .A(n5724), .B(n6624), .Y(n6108) );
AOI222XLTS U6828 ( .A0(n6080), .A1(n6650), .B0(n5833), .B1(n6811), .C0(n6078), .C1(n6527), .Y(n5725) );
OAI21X1TS U6829 ( .A0(n6856), .A1(n6082), .B0(n5725), .Y(n5726) );
AOI222XLTS U6830 ( .A0(n6165), .A1(n6404), .B0(n6088), .B1(n6690), .C0(n6087), .C1(n6689), .Y(n5727) );
AOI222XLTS U6831 ( .A0(n5949), .A1(n6627), .B0(n5833), .B1(n6778), .C0(n6078), .C1(n6462), .Y(n5729) );
OAI21X1TS U6832 ( .A0(n6813), .A1(n5941), .B0(n5729), .Y(n5730) );
CMPR32X2TS U6833 ( .A(n5733), .B(n5732), .C(n5731), .CO(n6114), .S(n5734) );
CMPR32X2TS U6834 ( .A(n5736), .B(n5735), .C(n5734), .CO(n6125), .S(n5758) );
XOR2X1TS U6835 ( .A(n5740), .B(Data_A_i[38]), .Y(n5768) );
CLKBUFX2TS U6836 ( .A(Data_B_i[31]), .Y(n6193) );
XOR2X1TS U6837 ( .A(n5742), .B(Data_A_i[41]), .Y(n5767) );
CMPR32X2TS U6838 ( .A(n5745), .B(n5744), .C(n5743), .CO(n5755), .S(n5786) );
CLKBUFX2TS U6839 ( .A(n5746), .Y(n5861) );
AOI222XLTS U6840 ( .A0(n5861), .A1(n6201), .B0(n5689), .B1(n6428), .C0(n5920), .C1(n5978), .Y(n5747) );
AOI222XLTS U6841 ( .A0(n6165), .A1(n6689), .B0(n6088), .B1(n6617), .C0(n6271), .C1(n6222), .Y(n5749) );
AOI222XLTS U6842 ( .A0(n5949), .A1(n6462), .B0(n6079), .B1(n6710), .C0(n5956), .C1(n6388), .Y(n5751) );
OAI21X1TS U6843 ( .A0(n6740), .A1(n5941), .B0(n5751), .Y(n5752) );
CMPR32X2TS U6844 ( .A(n5758), .B(n5757), .C(n5756), .CO(n6062), .S(n6061) );
ADDHXLTS U6845 ( .A(n5760), .B(n5759), .CO(n5737), .S(n5798) );
AOI222XLTS U6846 ( .A0(n6165), .A1(n6267), .B0(n6183), .B1(n6519), .C0(n5999), .C1(n6201), .Y(n5765) );
AOI222XLTS U6847 ( .A0(n5861), .A1(n6070), .B0(n5689), .B1(n6381), .C0(n5920), .C1(n5917), .Y(n5770) );
XOR2X1TS U6848 ( .A(n5776), .B(Data_A_i[41]), .Y(n5818) );
OAI21X1TS U6849 ( .A0(n5937), .A1(n6707), .B0(n964), .Y(n5779) );
NAND2X1TS U6850 ( .A(n6664), .B(n5910), .Y(n5780) );
OAI21X1TS U6851 ( .A0(n6679), .A1(n5913), .B0(n5780), .Y(n5781) );
XOR2X1TS U6852 ( .A(n5781), .B(n355), .Y(n5847) );
CMPR32X2TS U6853 ( .A(n5784), .B(n5783), .C(n5782), .CO(n5753), .S(n5789) );
CMPR32X2TS U6854 ( .A(n5793), .B(n5792), .C(n5791), .CO(n5785), .S(n5810) );
AOI222XLTS U6855 ( .A0(n5949), .A1(n6404), .B0(n6079), .B1(n6690), .C0(n5956), .C1(Data_B_i[41]), .Y(n5794) );
CMPR32X2TS U6856 ( .A(n5798), .B(n5797), .C(n5796), .CO(n5807), .S(n5827) );
AOI222XLTS U6857 ( .A0(n5949), .A1(n6388), .B0(n6079), .B1(n6660), .C0(n5956), .C1(n6267), .Y(n5801) );
AOI222XLTS U6858 ( .A0(n5861), .A1(n5978), .B0(n5689), .B1(n6336), .C0(n5920), .C1(n6001), .Y(n5803) );
CMPR32X2TS U6859 ( .A(n5813), .B(n5812), .C(n5811), .CO(n5805), .S(n6036) );
CLKBUFX2TS U6860 ( .A(n5814), .Y(n6004) );
AOI222XLTS U6861 ( .A0(n5840), .A1(n6222), .B0(n6000), .B1(n6483), .C0(n5999), .C1(n6070), .Y(n5815) );
ADDHX1TS U6862 ( .A(n5821), .B(n5820), .CO(n5817), .S(n5887) );
AOI222XLTS U6863 ( .A0(n5861), .A1(n5917), .B0(n5689), .B1(n6282), .C0(n5920), .C1(n289), .Y(n5822) );
AOI222XLTS U6864 ( .A0(n5695), .A1(n5998), .B0(n6180), .B1(n5973), .C0(n319),
.C1(n255), .Y(n5824) );
XOR2X1TS U6865 ( .A(n5831), .B(n5853), .Y(n5894) );
CLKBUFX2TS U6866 ( .A(n5832), .Y(n5980) );
AOI222XLTS U6867 ( .A0(n5949), .A1(n6267), .B0(n5833), .B1(n6519), .C0(n5976), .C1(n6201), .Y(n5834) );
XOR2X1TS U6868 ( .A(n5835), .B(n5889), .Y(n5893) );
AOI222XLTS U6869 ( .A0(n5861), .A1(n6281), .B0(n5689), .B1(n6194), .C0(n5985), .C1(n6193), .Y(n5836) );
AOI222XLTS U6870 ( .A0(n6080), .A1(n6222), .B0(n5977), .B1(n6483), .C0(n5976), .C1(n6070), .Y(n5838) );
OAI21X1TS U6871 ( .A0(n6522), .A1(n5980), .B0(n5838), .Y(n5839) );
CLKBUFX2TS U6872 ( .A(n5840), .Y(n6002) );
AOI222XLTS U6873 ( .A0(n6002), .A1(n5978), .B0(n6000), .B1(n6336), .C0(n5999), .C1(n6001), .Y(n5841) );
AOI222XLTS U6874 ( .A0(n6002), .A1(n6070), .B0(n6000), .B1(n6381), .C0(n5999), .C1(n5917), .Y(n5843) );
XOR2X1TS U6875 ( .A(n5844), .B(n6274), .Y(n5884) );
AOI222XLTS U6876 ( .A0(n5861), .A1(n6001), .B0(n5689), .B1(n6233), .C0(n5920), .C1(n5998), .Y(n5845) );
XOR2X1TS U6877 ( .A(n5846), .B(n5989), .Y(n5883) );
ADDHXLTS U6878 ( .A(n6708), .B(n5847), .CO(n5829), .S(n5857) );
OAI21X1TS U6879 ( .A0(n6539), .A1(n5913), .B0(n972), .Y(n5851) );
XOR2X1TS U6880 ( .A(n5851), .B(n5853), .Y(n5983) );
CMPR32X2TS U6881 ( .A(n5857), .B(n5856), .C(n5855), .CO(n5882), .S(n5869) );
AOI222XLTS U6882 ( .A0(n6002), .A1(n5917), .B0(n6000), .B1(n6282), .C0(n5999), .C1(n289), .Y(n5859) );
AOI222XLTS U6883 ( .A0(n5861), .A1(n5998), .B0(n5987), .B1(n5973), .C0(n5985), .C1(n5761), .Y(n5862) );
CMPR32X2TS U6884 ( .A(n5866), .B(n5865), .C(n5864), .CO(n5897), .S(n5867) );
AOI222XLTS U6885 ( .A0(n5870), .A1(n6201), .B0(n5977), .B1(n6428), .C0(n5976), .C1(n5978), .Y(n5871) );
AOI222XLTS U6886 ( .A0(n6315), .A1(n6193), .B0(n5987), .B1(n254), .C0(n5985),
.C1(n5948), .Y(n5874) );
XOR2X1TS U6887 ( .A(n5876), .B(n5989), .Y(n6011) );
AOI222XLTS U6888 ( .A0(n5870), .A1(n6070), .B0(n5977), .B1(n6381), .C0(n5976), .C1(n5917), .Y(n5877) );
XOR2X1TS U6889 ( .A(n5878), .B(n5889), .Y(n6010) );
CMPR32X2TS U6890 ( .A(n5881), .B(n5880), .C(n5879), .CO(n5868), .S(n6016) );
CMPR32X2TS U6891 ( .A(n5887), .B(n5886), .C(n5885), .CO(n6043), .S(n6050) );
AOI222XLTS U6892 ( .A0(n5949), .A1(Data_B_i[41]), .B0(n6079), .B1(n6617),
.C0(n6078), .C1(n6222), .Y(n5888) );
AOI222XLTS U6893 ( .A0(n6002), .A1(n6201), .B0(n6000), .B1(n6428), .C0(n5999), .C1(n5978), .Y(n5891) );
CMPR32X2TS U6894 ( .A(n5895), .B(n5894), .C(n5893), .CO(n6040), .S(n5898) );
CMPR32X2TS U6895 ( .A(n5898), .B(n5897), .C(n5896), .CO(n6032), .S(n6031) );
OAI21X1TS U6896 ( .A0(n6363), .A1(n5913), .B0(n974), .Y(n5900) );
AOI222XLTS U6897 ( .A0(n6165), .A1(n5973), .B0(n6088), .B1(n254), .C0(n6087),
.C1(n5948), .Y(n5901) );
AOI222XLTS U6898 ( .A0(n5870), .A1(n6001), .B0(n5977), .B1(n6233), .C0(n5976), .C1(n5998), .Y(n5903) );
INVX2TS U6899 ( .A(n5257), .Y(n5981) );
ADDHXLTS U6900 ( .A(n6402), .B(n5905), .CO(n5923), .S(n5930) );
AOI222XLTS U6901 ( .A0(n6165), .A1(n255), .B0(n6088), .B1(n5986), .C0(n6087),
.C1(n5984), .Y(n5906) );
AOI222XLTS U6902 ( .A0(n6165), .A1(n5948), .B0(n6088), .B1(n5933), .C0(n6087), .C1(n5936), .Y(n5908) );
AOI222XLTS U6903 ( .A0(n6002), .A1(n5998), .B0(n6088), .B1(n5973), .C0(n6087), .C1(n255), .Y(n5915) );
XOR2X1TS U6904 ( .A(n5916), .B(n6005), .Y(n5995) );
AOI222XLTS U6905 ( .A0(n5870), .A1(n5917), .B0(n5977), .B1(n6282), .C0(n5976), .C1(n289), .Y(n5918) );
OAI21XLTS U6906 ( .A0(n990), .A1(n6401), .B0(n5921), .Y(n5922) );
ADDHXLTS U6907 ( .A(n5924), .B(n5923), .CO(n5991), .S(n5927) );
CMPR32X2TS U6908 ( .A(n5927), .B(n5926), .C(n5925), .CO(n5969), .S(n5968) );
CMPR32X2TS U6909 ( .A(n5930), .B(n5929), .C(n5928), .CO(n5967), .S(n5966) );
AOI222XLTS U6910 ( .A0(n5870), .A1(n6281), .B0(n5977), .B1(n6194), .C0(n5956), .C1(n5973), .Y(n5931) );
AOI222XLTS U6911 ( .A0(n5949), .A1(n5948), .B0(n6079), .B1(n5933), .C0(n5956), .C1(n5936), .Y(n5934) );
XNOR2X1TS U6912 ( .A(n5935), .B(n5942), .Y(n7402) );
NAND2X1TS U6913 ( .A(n7299), .B(n7300), .Y(n7401) );
AOI222XLTS U6914 ( .A0(n5949), .A1(n254), .B0(n6079), .B1(n5986), .C0(n5956),
.C1(n5984), .Y(n5940) );
ADDHXLTS U6915 ( .A(n6274), .B(n5944), .CO(n5952), .S(n5945) );
NAND2X1TS U6916 ( .A(n5946), .B(n5945), .Y(n7295) );
AOI21X1TS U6917 ( .A0(n7297), .A1(n7296), .B0(n5947), .Y(n7400) );
AOI222XLTS U6918 ( .A0(n5949), .A1(n6193), .B0(n6079), .B1(n254), .C0(n5956),
.C1(n5948), .Y(n5950) );
ADDHXLTS U6919 ( .A(n5953), .B(n5952), .CO(n5960), .S(n5954) );
NAND2X1TS U6920 ( .A(n5955), .B(n5954), .Y(n7397) );
OAI21X1TS U6921 ( .A0(n7400), .A1(n7396), .B0(n7397), .Y(n7293) );
AOI222XLTS U6922 ( .A0(n5870), .A1(n5998), .B0(n6079), .B1(n6193), .C0(n5956), .C1(n5761), .Y(n5958) );
ADDHXLTS U6923 ( .A(n5961), .B(n5960), .CO(n5928), .S(n5962) );
NAND2X1TS U6924 ( .A(n5963), .B(n5962), .Y(n7292) );
AOI21X1TS U6925 ( .A0(n7293), .A1(n987), .B0(n5964), .Y(n7394) );
NAND2X1TS U6926 ( .A(n5966), .B(n5965), .Y(n7392) );
OAI21X1TS U6927 ( .A0(n7391), .A1(n7394), .B0(n7392), .Y(n7286) );
NAND2X1TS U6928 ( .A(n5968), .B(n5967), .Y(n7387) );
NAND2X1TS U6929 ( .A(n5970), .B(n5969), .Y(n7288) );
AOI222XLTS U6930 ( .A0(n6002), .A1(n6281), .B0(n6000), .B1(n6194), .C0(n6087), .C1(n5973), .Y(n5974) );
AOI222XLTS U6931 ( .A0(n5870), .A1(n5978), .B0(n5977), .B1(n6336), .C0(n5976), .C1(n6001), .Y(n5979) );
ADDHXLTS U6932 ( .A(n6624), .B(n5983), .CO(n5873), .S(n6009) );
AOI222XLTS U6933 ( .A0(n6315), .A1(n254), .B0(n5987), .B1(n5986), .C0(n5985),
.C1(n5984), .Y(n5988) );
XOR2X1TS U6934 ( .A(n5990), .B(n5989), .Y(n6008) );
ADDHXLTS U6935 ( .A(n5992), .B(n5991), .CO(n6007), .S(n5993) );
NAND2X1TS U6936 ( .A(n5997), .B(n5996), .Y(n7382) );
AOI222XLTS U6937 ( .A0(n6002), .A1(n6001), .B0(n6000), .B1(n6233), .C0(n5999), .C1(n5998), .Y(n6003) );
CMPR32X2TS U6938 ( .A(n6009), .B(n6008), .C(n6007), .CO(n6020), .S(n6013) );
CMPR32X2TS U6939 ( .A(n6012), .B(n6011), .C(n6010), .CO(n6017), .S(n6019) );
CMPR32X2TS U6940 ( .A(n6015), .B(n6014), .C(n6013), .CO(n6022), .S(n5997) );
NOR2X1TS U6941 ( .A(n6023), .B(n6022), .Y(n7376) );
CMPR32X2TS U6942 ( .A(n6018), .B(n6017), .C(n6016), .CO(n6028), .S(n6025) );
CMPR32X2TS U6943 ( .A(n6021), .B(n6020), .C(n6019), .CO(n6024), .S(n6023) );
NOR2X1TS U6944 ( .A(n7376), .B(n7281), .Y(n6027) );
NAND2X1TS U6945 ( .A(n6023), .B(n6022), .Y(n7377) );
NAND2X1TS U6946 ( .A(n6025), .B(n6024), .Y(n7282) );
OAI21X1TS U6947 ( .A0(n7281), .A1(n7377), .B0(n7282), .Y(n6026) );
NAND2X1TS U6948 ( .A(n6033), .B(n6032), .Y(n7368) );
CMPR32X2TS U6949 ( .A(n6039), .B(n6038), .C(n6037), .CO(n5826), .S(n6048) );
CMPR32X2TS U6950 ( .A(n6042), .B(n6041), .C(n6040), .CO(n6047), .S(n6049) );
CMPR32X2TS U6951 ( .A(n6045), .B(n6044), .C(n6043), .CO(n6035), .S(n6046) );
CMPR32X2TS U6952 ( .A(n6048), .B(n6047), .C(n6046), .CO(n6054), .S(n6053) );
CMPR32X2TS U6953 ( .A(n6051), .B(n6050), .C(n6049), .CO(n6052), .S(n6033) );
NAND2X1TS U6954 ( .A(n6055), .B(n6054), .Y(n7273) );
NAND2X1TS U6955 ( .A(n6063), .B(n6062), .Y(n7340) );
AOI222XLTS U6956 ( .A0(n6080), .A1(n6673), .B0(n6079), .B1(n6866), .C0(n6078), .C1(n6627), .Y(n6081) );
AOI222XLTS U6957 ( .A0(n5840), .A1(n6527), .B0(n6088), .B1(n6777), .C0(n6087), .C1(n6404), .Y(n6089) );
CMPR32X2TS U6958 ( .A(n6097), .B(n6096), .C(n6095), .CO(n6105), .S(n6122) );
ADDFHX2TS U6959 ( .A(n6103), .B(n6102), .CI(n6101), .CO(n6146), .S(n6145) );
CMPR32X2TS U6960 ( .A(n6106), .B(n6105), .C(n6104), .CO(n6098), .S(n6121) );
CMPR32X2TS U6961 ( .A(n6109), .B(n6108), .C(n6107), .CO(n6130), .S(n6126) );
CMPR32X2TS U6962 ( .A(n6115), .B(n6114), .C(n6113), .CO(n6128), .S(n6137) );
NAND2X2TS U6963 ( .A(n163), .B(n125), .Y(n6150) );
INVX2TS U6964 ( .A(n6131), .Y(n7265) );
NOR2X1TS U6965 ( .A(n6139), .B(n6138), .Y(n7263) );
INVX2TS U6966 ( .A(n7263), .Y(n7333) );
NAND2X2TS U6967 ( .A(n7265), .B(n7333), .Y(n7259) );
NAND2X2TS U6968 ( .A(n6139), .B(n6138), .Y(n7332) );
NAND2X1TS U6969 ( .A(n6141), .B(n6140), .Y(n7264) );
NAND2X1TS U6970 ( .A(n6145), .B(n6144), .Y(n7260) );
NAND2X1TS U6971 ( .A(n6147), .B(n6146), .Y(n7255) );
OAI21X1TS U6972 ( .A0(n7258), .A1(n6150), .B0(n6149), .Y(n6151) );
NAND2X1TS U6973 ( .A(n6156), .B(n6155), .Y(n7311) );
OAI21X2TS U6974 ( .A0(n7310), .A1(n7307), .B0(n7311), .Y(n7324) );
NAND2X1TS U6975 ( .A(n6160), .B(n6159), .Y(n7320) );
OAI21X1TS U6976 ( .A0(n7319), .A1(n7328), .B0(n7320), .Y(n6161) );
INVX2TS U6977 ( .A(n6598), .Y(n7246) );
AOI222XLTS U6978 ( .A0(n6165), .A1(n6969), .B0(n6183), .B1(n6954), .C0(n6271), .C1(n6785), .Y(n6166) );
XOR2X1TS U6979 ( .A(n6170), .B(n6963), .Y(n6231) );
CMPR32X2TS U6980 ( .A(n6173), .B(n6172), .C(n6171), .CO(n6240), .S(n6237) );
AOI222XLTS U6981 ( .A0(n5746), .A1(n6748), .B0(n6360), .B1(n6926), .C0(n6399), .C1(n6673), .Y(n6174) );
OAI21X1TS U6982 ( .A0(n6929), .A1(n6363), .B0(n6174), .Y(n6175) );
AOI222XLTS U6983 ( .A0(n6609), .A1(n6777), .B0(n6365), .B1(Data_B_i[43]),
.C0(n6425), .C1(n6788), .Y(n6176) );
OAI21X1TS U6984 ( .A0(n6740), .A1(n6707), .B0(n6176), .Y(n6177) );
AOI222XLTS U6985 ( .A0(n6410), .A1(n6650), .B0(n6536), .B1(n6811), .C0(n6621), .C1(n6527), .Y(n6178) );
OAI21X1TS U6986 ( .A0(n6856), .A1(n6539), .B0(n6178), .Y(n6179) );
AOI222XLTS U6987 ( .A0(n6410), .A1(n6673), .B0(n6180), .B1(n6866), .C0(n6621), .C1(n6627), .Y(n6181) );
AOI21X1TS U6988 ( .A0(n6271), .A1(n6987), .B0(n6184), .Y(n6185) );
AOI222XLTS U6989 ( .A0(n5746), .A1(n6785), .B0(n6360), .B1(n6927), .C0(n6399), .C1(n6717), .Y(n6188) );
AOI222XLTS U6990 ( .A0(n6484), .A1(n6194), .B0(n6738), .B1(n5957), .C0(n298),
.C1(Data_B_i[30]), .Y(n6195) );
XOR2X1TS U6991 ( .A(n6196), .B(n6940), .Y(n6228) );
AOI222XLTS U6992 ( .A0(n6198), .A1(n6689), .B0(n6524), .B1(n6617), .C0(n6826), .C1(n6685), .Y(n6199) );
XOR2X1TS U6993 ( .A(n6200), .B(n6217), .Y(n6227) );
AOI222XLTS U6994 ( .A0(n6268), .A1(n6201), .B0(n6221), .B1(n6428), .C0(n6339), .C1(n291), .Y(n6202) );
XOR2X1TS U6995 ( .A(n6203), .B(Data_A_i[47]), .Y(n6226) );
CMPR32X2TS U6996 ( .A(n6209), .B(n6208), .C(n6207), .CO(n6213), .S(n6190) );
CMPR32X2TS U6997 ( .A(n6212), .B(n6211), .C(n6210), .CO(n6249), .S(n6257) );
AOI222XLTS U6998 ( .A0(n6414), .A1(n6388), .B0(n6524), .B1(n6660), .C0(n6613), .C1(Data_B_i[40]), .Y(n6216) );
OAI21X1TS U6999 ( .A0(n6692), .A1(n6828), .B0(n6216), .Y(n6218) );
AOI222XLTS U7000 ( .A0(n6818), .A1(n6222), .B0(n6221), .B1(n6483), .C0(n6339), .C1(Data_B_i[37]), .Y(n6223) );
CMPR32X2TS U7001 ( .A(n6228), .B(n6227), .C(n6226), .CO(n6292), .S(n6215) );
CLKBUFX2TS U7002 ( .A(Data_B_i[44]), .Y(n6777) );
AOI222XLTS U7003 ( .A0(n6609), .A1(n6778), .B0(n6365), .B1(n6777), .C0(n6425), .C1(n6825), .Y(n6229) );
OAI21X1TS U7004 ( .A0(n6235), .A1(n6521), .B0(n6234), .Y(n6236) );
XOR2X1TS U7005 ( .A(n6236), .B(n6940), .Y(n6286) );
CMPR32X2TS U7006 ( .A(n6239), .B(n6238), .C(n6237), .CO(n6248), .S(n6210) );
CMPR32X2TS U7007 ( .A(n6245), .B(n6244), .C(n6243), .CO(n6262), .S(n6246) );
NOR2X2TS U7008 ( .A(n6443), .B(n6442), .Y(n7237) );
NOR2X2TS U7009 ( .A(n7237), .B(n7242), .Y(n7229) );
CMPR32X2TS U7010 ( .A(n6263), .B(n6262), .C(n6261), .CO(n6350), .S(n6309) );
AOI222XLTS U7011 ( .A0(n6268), .A1(n6267), .B0(n339), .B1(n6519), .C0(n6339),
.C1(n293), .Y(n6269) );
OAI21X1TS U7012 ( .A0(n7036), .A1(n6273), .B0(n6272), .Y(n6275) );
XOR2X1TS U7013 ( .A(n6275), .B(n6274), .Y(n6334) );
AOI222XLTS U7014 ( .A0(n6414), .A1(n6404), .B0(n6524), .B1(n6690), .C0(n6613), .C1(n6745), .Y(n6276) );
INVX2TS U7015 ( .A(n6873), .Y(n6701) );
CMPR32X2TS U7016 ( .A(n6280), .B(n6279), .C(n6278), .CO(n6331), .S(n6293) );
AOI222XLTS U7017 ( .A0(n6484), .A1(n6282), .B0(n328), .B1(n6281), .C0(n298),
.C1(n256), .Y(n6283) );
OAI21X1TS U7018 ( .A0(n6284), .A1(n6521), .B0(n6283), .Y(n6285) );
AOI222XLTS U7019 ( .A0(n5746), .A1(n6968), .B0(n6360), .B1(n6937), .C0(n6399), .C1(n6748), .Y(n6288) );
AOI222XLTS U7020 ( .A0(n6410), .A1(n6717), .B0(n6536), .B1(n6897), .C0(n6300), .C1(n6650), .Y(n6301) );
AOI222XLTS U7021 ( .A0(n6664), .A1(n6811), .B0(n6676), .B1(Data_B_i[45]),
.C0(n6323), .C1(n6849), .Y(n6303) );
OAI21X1TS U7022 ( .A0(n118), .A1(n6386), .B0(n6305), .Y(n6306) );
XOR2X1TS U7023 ( .A(n6306), .B(n6963), .Y(n6326) );
NOR2X2TS U7024 ( .A(n6445), .B(n6444), .Y(n7220) );
AOI222XLTS U7025 ( .A0(n6414), .A1(n6462), .B0(n6524), .B1(n6710), .C0(n6613), .C1(n6788), .Y(n6310) );
OAI21X1TS U7026 ( .A0(n6740), .A1(n6828), .B0(n6310), .Y(n6311) );
AOI222XLTS U7027 ( .A0(n6312), .A1(n6483), .B0(n6625), .B1(n6428), .C0(n6735), .C1(n291), .Y(n6313) );
OAI21X1TS U7028 ( .A0(n6486), .A1(n6386), .B0(n6313), .Y(n6314) );
AOI222XLTS U7029 ( .A0(n6315), .A1(n6969), .B0(n6360), .B1(n6954), .C0(n6399), .C1(n6785), .Y(n6316) );
OAI21X1TS U7030 ( .A0(n6972), .A1(n6363), .B0(n6316), .Y(n6317) );
AOI222XLTS U7031 ( .A0(n6410), .A1(n6748), .B0(n6536), .B1(n6926), .C0(n6621), .C1(n6673), .Y(n6321) );
XOR2X1TS U7032 ( .A(n6322), .B(n6412), .Y(n6359) );
AOI222XLTS U7033 ( .A0(n6609), .A1(n292), .B0(n6676), .B1(Data_B_i[46]),
.C0(n6323), .C1(n6870), .Y(n6324) );
XOR2X1TS U7034 ( .A(n6325), .B(n6611), .Y(n6358) );
CMPR32X2TS U7035 ( .A(n5981), .B(n212), .C(n6326), .CO(n6357), .S(n6318) );
AOI222XLTS U7036 ( .A0(n6484), .A1(n6336), .B0(n328), .B1(n290), .C0(n298),
.C1(n289), .Y(n6337) );
AOI222XLTS U7037 ( .A0(n6850), .A1(n6689), .B0(n339), .B1(n6617), .C0(n6903),
.C1(n6685), .Y(n6340) );
CMPR32X2TS U7038 ( .A(n6344), .B(n6343), .C(n6342), .CO(n6374), .S(n6330) );
NOR2X4TS U7039 ( .A(n7220), .B(n7224), .Y(n6449) );
NAND2X2TS U7040 ( .A(n7229), .B(n6449), .Y(n7215) );
INVX2TS U7041 ( .A(n7215), .Y(n6509) );
AOI21X1TS U7042 ( .A0(n6399), .A1(n6987), .B0(n6361), .Y(n6362) );
XOR2X1TS U7043 ( .A(n6364), .B(n6402), .Y(n6409) );
CLKBUFX2TS U7044 ( .A(Data_B_i[47]), .Y(n6866) );
AOI222XLTS U7045 ( .A0(n6609), .A1(n6897), .B0(n6365), .B1(n6866), .C0(n6705), .C1(n6901), .Y(n6366) );
CMPR32X2TS U7046 ( .A(n6376), .B(n6375), .C(n6374), .CO(n6421), .S(n6372) );
AOI222XLTS U7047 ( .A0(n6410), .A1(n6785), .B0(n6536), .B1(n6927), .C0(n6621), .C1(n6717), .Y(n6377) );
INVX2TS U7048 ( .A(n6543), .Y(n6469) );
CMPR32X2TS U7049 ( .A(n6380), .B(n5257), .C(n6379), .CO(n6418), .S(n6370) );
AOI222XLTS U7050 ( .A0(n6484), .A1(n6381), .B0(n329), .B1(n242), .C0(n298),
.C1(n290), .Y(n6382) );
XOR2X1TS U7051 ( .A(n6384), .B(n7037), .Y(n6417) );
AOI222XLTS U7052 ( .A0(n6893), .A1(n6519), .B0(n6625), .B1(n6483), .C0(n6735), .C1(n6482), .Y(n6385) );
XOR2X1TS U7053 ( .A(n6387), .B(n6963), .Y(n6433) );
AOI222XLTS U7054 ( .A0(n6850), .A1(n6388), .B0(n339), .B1(n6660), .C0(n6716),
.C1(Data_B_i[40]), .Y(n6389) );
XOR2X1TS U7055 ( .A(n6391), .B(n6390), .Y(n6432) );
AOI222XLTS U7056 ( .A0(n6746), .A1(n6527), .B0(n6524), .B1(n6777), .C0(n6613), .C1(n6825), .Y(n6392) );
XOR2X1TS U7057 ( .A(n6393), .B(n6701), .Y(n6431) );
AOI222XLTS U7058 ( .A0(n6923), .A1(n6617), .B0(n6946), .B1(n6519), .C0(n6735), .C1(n293), .Y(n6397) );
OAI21XLTS U7059 ( .A0(n6619), .A1(n6949), .B0(n6397), .Y(n6398) );
NAND2X1TS U7060 ( .A(n6399), .B(n7033), .Y(n6400) );
XOR2X1TS U7061 ( .A(n6403), .B(n6402), .Y(n6457) );
AOI222XLTS U7062 ( .A0(n6850), .A1(n6404), .B0(n340), .B1(n6690), .C0(n6716),
.C1(n6745), .Y(n6405) );
INVX2TS U7063 ( .A(n6945), .Y(n6820) );
AOI222XLTS U7064 ( .A0(n6410), .A1(n6968), .B0(n6536), .B1(n6937), .C0(n6621), .C1(n6748), .Y(n6411) );
XOR2X1TS U7065 ( .A(n6413), .B(n6412), .Y(n6461) );
AOI222XLTS U7066 ( .A0(n6414), .A1(n6627), .B0(n6791), .B1(n6778), .C0(n6826), .C1(n6849), .Y(n6415) );
OAI21X1TS U7067 ( .A0(n6813), .A1(n6828), .B0(n6415), .Y(n6416) );
XOR2X1TS U7068 ( .A(n6416), .B(n6701), .Y(n6460) );
CMPR32X2TS U7069 ( .A(n6469), .B(n6418), .C(n6417), .CO(n6459), .S(n6423) );
CLKBUFX2TS U7070 ( .A(Data_B_i[48]), .Y(n6897) );
AOI222XLTS U7071 ( .A0(n6609), .A1(n6926), .B0(n6676), .B1(n6897), .C0(n6425), .C1(n292), .Y(n6426) );
OAI21X1TS U7072 ( .A0(n118), .A1(n6521), .B0(n6429), .Y(n6430) );
XOR2X1TS U7073 ( .A(n6430), .B(n7037), .Y(n6468) );
CMPR32X2TS U7074 ( .A(n6433), .B(n6432), .C(n6431), .CO(n6474), .S(n6422) );
NAND2X1TS U7075 ( .A(n6509), .B(n6587), .Y(n6455) );
OAI21X4TS U7076 ( .A0(n7237), .A1(n7243), .B0(n7238), .Y(n7230) );
NAND2X2TS U7077 ( .A(n6445), .B(n6444), .Y(n7233) );
NAND2X1TS U7078 ( .A(n6447), .B(n6446), .Y(n7225) );
OAI21X2TS U7079 ( .A0(n7224), .A1(n7233), .B0(n7225), .Y(n6448) );
INVX2TS U7080 ( .A(n7214), .Y(n6513) );
NAND2X1TS U7081 ( .A(n6453), .B(n6452), .Y(n6504) );
AOI21X1TS U7082 ( .A0(n6513), .A1(n6587), .B0(n6593), .Y(n6454) );
CMPR32X2TS U7083 ( .A(n6458), .B(n6457), .C(n6456), .CO(n6550), .S(n6490) );
AOI222XLTS U7084 ( .A0(n6850), .A1(n6462), .B0(n340), .B1(n6710), .C0(n6716),
.C1(n6788), .Y(n6463) );
AOI222XLTS U7085 ( .A0(n6465), .A1(n6969), .B0(n6536), .B1(n6954), .C0(n6621), .C1(n6785), .Y(n6466) );
CMPR32X2TS U7086 ( .A(n6470), .B(n6469), .C(n6468), .CO(n6530), .S(n6475) );
CLKBUFX2TS U7087 ( .A(Data_B_i[49]), .Y(n6926) );
AOI222XLTS U7088 ( .A0(n6609), .A1(n6927), .B0(n6676), .B1(n6926), .C0(n6705), .C1(n6942), .Y(n6477) );
AOI222XLTS U7089 ( .A0(n6746), .A1(n6650), .B0(n6791), .B1(n6811), .C0(n6826), .C1(n6870), .Y(n6479) );
AOI222XLTS U7090 ( .A0(n6923), .A1(n6660), .B0(n6782), .B1(n6617), .C0(n6960), .C1(n6685), .Y(n6481) );
AOI222XLTS U7091 ( .A0(n6484), .A1(n6483), .B0(n329), .B1(n6482), .C0(n298),
.C1(n291), .Y(n6485) );
CMPR32X2TS U7092 ( .A(n6490), .B(n6489), .C(n6488), .CO(n6551), .S(n6493) );
NOR2X2TS U7093 ( .A(n6495), .B(n6494), .Y(n6586) );
NAND2X1TS U7094 ( .A(n6495), .B(n6494), .Y(n6590) );
NAND2X1TS U7095 ( .A(n6496), .B(n6590), .Y(n6497) );
XNOR2X1TS U7096 ( .A(n6498), .B(n6497), .Y(GEN1_left_N35) );
INVX2TS U7097 ( .A(n6499), .Y(n7217) );
NAND2X1TS U7098 ( .A(n6509), .B(n7217), .Y(n6502) );
AOI21X1TS U7099 ( .A0(n6513), .A1(n7217), .B0(n6500), .Y(n6501) );
NAND2X1TS U7100 ( .A(n6505), .B(n6504), .Y(n6506) );
XNOR2X1TS U7101 ( .A(n6507), .B(n6506), .Y(GEN1_left_N34) );
NAND2X1TS U7102 ( .A(n6512), .B(n6509), .Y(n6515) );
OAI21X1TS U7103 ( .A0(n6510), .A1(n6586), .B0(n6590), .Y(n6511) );
AOI21X1TS U7104 ( .A0(n6513), .A1(n6512), .B0(n6511), .Y(n6514) );
CMPR32X2TS U7105 ( .A(n6517), .B(n6518), .C(n6516), .CO(n6602), .S(n6533) );
AOI222XLTS U7106 ( .A0(n6955), .A1(n6519), .B0(n329), .B1(n293), .C0(n298),
.C1(Data_B_i[37]), .Y(n6520) );
AOI222XLTS U7107 ( .A0(n6746), .A1(n6673), .B0(n6524), .B1(n6866), .C0(n6826), .C1(n6901), .Y(n6525) );
XOR2X1TS U7108 ( .A(n6526), .B(n6701), .Y(n6631) );
AOI222XLTS U7109 ( .A0(n6818), .A1(n6527), .B0(n340), .B1(n6777), .C0(n6716),
.C1(n6825), .Y(n6528) );
CMPR32X2TS U7110 ( .A(n6535), .B(n6534), .C(n6533), .CO(n6605), .S(n6552) );
AOI21X1TS U7111 ( .A0(n6621), .A1(n6987), .B0(n6537), .Y(n6538) );
AOI222XLTS U7112 ( .A0(n6609), .A1(n6937), .B0(n6676), .B1(Data_B_i[50]),
.C0(n6705), .C1(n6959), .Y(n6541) );
INVX2TS U7113 ( .A(n6687), .Y(n6654) );
CMPR32X2TS U7114 ( .A(n6544), .B(n6543), .C(n178), .CO(n6616), .S(n6518) );
AOI222XLTS U7115 ( .A0(n6923), .A1(n6690), .B0(n6782), .B1(n6660), .C0(n6815), .C1(Data_B_i[40]), .Y(n6545) );
OAI21X1TS U7116 ( .A0(n6692), .A1(n6962), .B0(n6545), .Y(n6547) );
CMPR32X2TS U7117 ( .A(n6553), .B(n6552), .C(n6551), .CO(n6633), .S(n6554) );
ADDFHX2TS U7118 ( .A(n6556), .B(n6555), .CI(n6554), .CO(n6557), .S(n6495) );
NOR2X2TS U7119 ( .A(n6558), .B(n6557), .Y(n6589) );
NAND2X1TS U7120 ( .A(n6558), .B(n6557), .Y(n6588) );
NAND2X1TS U7121 ( .A(n6559), .B(n6588), .Y(n6560) );
XNOR2X1TS U7122 ( .A(n6561), .B(n6560), .Y(GEN1_left_N36) );
NAND2X1TS U7123 ( .A(n7166), .B(n578), .Y(n6574) );
OAI21X1TS U7124 ( .A0(n6567), .A1(n6566), .B0(n6565), .Y(n6568) );
INVX2TS U7125 ( .A(n6579), .Y(n7150) );
NAND2X1TS U7126 ( .A(n7138), .B(n7143), .Y(n6583) );
OAI21X1TS U7127 ( .A0(n6590), .A1(n6589), .B0(n6588), .Y(n6591) );
OAI21X2TS U7128 ( .A0(n7214), .A1(n6595), .B0(n6594), .Y(n6596) );
CMPR32X2TS U7129 ( .A(n6602), .B(n6601), .C(n6600), .CO(n6638), .S(n6635) );
CMPR32X2TS U7130 ( .A(n6608), .B(n6607), .C(n6606), .CO(n6644), .S(n6604) );
AOI222XLTS U7131 ( .A0(n6609), .A1(n6954), .B0(n6676), .B1(Data_B_i[51]),
.C0(n6705), .C1(n6967), .Y(n6610) );
AOI222XLTS U7132 ( .A0(n6746), .A1(n6717), .B0(n6791), .B1(n6897), .C0(n6613), .C1(n292), .Y(n6614) );
CMPR32X2TS U7133 ( .A(n6654), .B(n6616), .C(n6615), .CO(n6645), .S(n6606) );
AOI222XLTS U7134 ( .A0(n6970), .A1(n6617), .B0(n328), .B1(Data_B_i[39]),
.C0(n298), .C1(n293), .Y(n6618) );
NAND2X1TS U7135 ( .A(n6621), .B(n7033), .Y(n6622) );
AOI222XLTS U7136 ( .A0(n6923), .A1(n6710), .B0(n6625), .B1(n6690), .C0(n6815), .C1(n6745), .Y(n6626) );
INVX2TS U7137 ( .A(n6984), .Y(n6895) );
AOI222XLTS U7138 ( .A0(n6850), .A1(n6627), .B0(n340), .B1(n6778), .C0(n6903),
.C1(n6849), .Y(n6628) );
XOR2X1TS U7139 ( .A(n6629), .B(n6820), .Y(n6658) );
CMPR32X2TS U7140 ( .A(n6632), .B(n6631), .C(n6630), .CO(n6639), .S(n6601) );
CMPR32X2TS U7141 ( .A(n6638), .B(n6637), .C(n6636), .CO(n6767), .S(n6765) );
CMPR32X2TS U7142 ( .A(n6647), .B(n6646), .C(n6645), .CO(n6699), .S(n6643) );
AOI222XLTS U7143 ( .A0(n6923), .A1(n6777), .B0(n6782), .B1(n6710), .C0(n6815), .C1(n6788), .Y(n6648) );
OAI21X1TS U7144 ( .A0(n6740), .A1(n6962), .B0(n6648), .Y(n6649) );
XOR2X1TS U7145 ( .A(n6649), .B(n6895), .Y(n6672) );
AOI222XLTS U7146 ( .A0(n6818), .A1(n6650), .B0(n340), .B1(n6811), .C0(n6903),
.C1(n6870), .Y(n6651) );
XOR2X1TS U7147 ( .A(n6652), .B(n6820), .Y(n6671) );
CMPR32X2TS U7148 ( .A(n6655), .B(n6654), .C(n6653), .CO(n6670), .S(n6641) );
AOI222XLTS U7149 ( .A0(n6746), .A1(n6748), .B0(n6791), .B1(Data_B_i[49]),
.C0(n6826), .C1(n6942), .Y(n6656) );
AOI222XLTS U7150 ( .A0(n6970), .A1(n6660), .B0(n6738), .B1(n6659), .C0(n7034), .C1(n6685), .Y(n6661) );
XOR2X1TS U7151 ( .A(n6663), .B(n7037), .Y(n6695) );
AOI222XLTS U7152 ( .A0(n6664), .A1(n6969), .B0(n6676), .B1(n6968), .C0(n6705), .C1(n6981), .Y(n6665) );
OAI21X1TS U7153 ( .A0(n6972), .A1(n6679), .B0(n6665), .Y(n6666) );
XOR2X1TS U7154 ( .A(n6666), .B(n6708), .Y(n6694) );
NOR2X2TS U7155 ( .A(n6767), .B(n6766), .Y(n7112) );
CMPR32X2TS U7156 ( .A(n6669), .B(n6668), .C(n6667), .CO(n6763), .S(n6697) );
CMPR32X2TS U7157 ( .A(n6672), .B(n6671), .C(n6670), .CO(n6728), .S(n6698) );
AOI222XLTS U7158 ( .A0(n6818), .A1(n6673), .B0(n339), .B1(n6866), .C0(n6903),
.C1(n6901), .Y(n6674) );
XOR2X1TS U7159 ( .A(n6675), .B(n6820), .Y(n6722) );
AOI21X1TS U7160 ( .A0(n6705), .A1(n6987), .B0(n6677), .Y(n6678) );
XOR2X1TS U7161 ( .A(n6680), .B(n6708), .Y(n6721) );
AOI222XLTS U7162 ( .A0(n6893), .A1(n6778), .B0(n6782), .B1(n6777), .C0(n6815), .C1(n6825), .Y(n6681) );
XOR2X1TS U7163 ( .A(n6682), .B(n6895), .Y(n6720) );
AOI222XLTS U7164 ( .A0(n6746), .A1(n6785), .B0(n6791), .B1(n6927), .C0(n6826), .C1(n6959), .Y(n6683) );
OAI21X1TS U7165 ( .A0(n6939), .A1(n6794), .B0(n6683), .Y(n6684) );
XOR2X1TS U7166 ( .A(n6684), .B(n6701), .Y(n6725) );
INVX2TS U7167 ( .A(n6790), .Y(n6743) );
CMPR32X2TS U7168 ( .A(n6688), .B(n6687), .C(n6686), .CO(n6704), .S(n6696) );
AOI222XLTS U7169 ( .A0(n6970), .A1(n6690), .B0(n6738), .B1(n6689), .C0(n297),
.C1(Data_B_i[40]), .Y(n6691) );
XOR2X1TS U7170 ( .A(n6693), .B(n6973), .Y(n6703) );
CMPR32X2TS U7171 ( .A(n6696), .B(n6695), .C(n6694), .CO(n6723), .S(n6667) );
AOI222XLTS U7172 ( .A0(n6746), .A1(n6968), .B0(n6791), .B1(n6937), .C0(n6826), .C1(n6967), .Y(n6700) );
NAND2X1TS U7173 ( .A(n6705), .B(n7198), .Y(n6706) );
OAI21X1TS U7174 ( .A0(n7036), .A1(n6707), .B0(n6706), .Y(n6709) );
XOR2X1TS U7175 ( .A(n6709), .B(n6708), .Y(n6742) );
AOI222XLTS U7176 ( .A0(n6970), .A1(n6710), .B0(n6738), .B1(Data_B_i[42]),
.C0(n297), .C1(n6745), .Y(n6711) );
XOR2X1TS U7177 ( .A(n6713), .B(n6940), .Y(n6734) );
AOI222XLTS U7178 ( .A0(n6923), .A1(n6811), .B0(n6946), .B1(n6778), .C0(n6735), .C1(n6849), .Y(n6714) );
XOR2X1TS U7179 ( .A(n6715), .B(n6895), .Y(n6733) );
AOI222XLTS U7180 ( .A0(n6818), .A1(n6717), .B0(n340), .B1(n6897), .C0(n6716),
.C1(n292), .Y(n6718) );
XOR2X1TS U7181 ( .A(n6719), .B(n6820), .Y(n6732) );
CMPR32X2TS U7182 ( .A(n6728), .B(n6727), .C(n6726), .CO(n6754), .S(n6762) );
CMPR32X2TS U7183 ( .A(n6731), .B(n6730), .C(n6729), .CO(n6776), .S(n6756) );
CMPR32X2TS U7184 ( .A(n6734), .B(n6733), .C(n6732), .CO(n6804), .S(n6753) );
AOI222XLTS U7185 ( .A0(n6893), .A1(n292), .B0(n6946), .B1(n6811), .C0(n6735),
.C1(n6870), .Y(n6736) );
OAI21X1TS U7186 ( .A0(n6856), .A1(n6949), .B0(n6736), .Y(n6737) );
XOR2X1TS U7187 ( .A(n6737), .B(n6895), .Y(n6801) );
AOI222XLTS U7188 ( .A0(n6970), .A1(n6777), .B0(n6738), .B1(Data_B_i[43]),
.C0(n297), .C1(n6788), .Y(n6739) );
XOR2X1TS U7189 ( .A(n6741), .B(n6973), .Y(n6800) );
AOI222XLTS U7190 ( .A0(n6746), .A1(n6969), .B0(n6791), .B1(n6954), .C0(n6826), .C1(n6981), .Y(n6747) );
AOI222XLTS U7191 ( .A0(n6818), .A1(n6748), .B0(n340), .B1(n6926), .C0(n6903),
.C1(n6942), .Y(n6749) );
XOR2X1TS U7192 ( .A(n6750), .B(n6820), .Y(n6796) );
CMPR32X2TS U7193 ( .A(n6756), .B(n6755), .C(n6754), .CO(n6772), .S(n6770) );
ADDFHX1TS U7194 ( .A(n6763), .B(n6762), .CI(n6761), .CO(n6771), .S(n6768) );
NAND2X2TS U7195 ( .A(n6765), .B(n6764), .Y(n7303) );
NAND2X1TS U7196 ( .A(n6767), .B(n6766), .Y(n7113) );
NAND2X1TS U7197 ( .A(n6769), .B(n6768), .Y(n7110) );
NAND2X1TS U7198 ( .A(n6773), .B(n6772), .Y(n6847) );
CMPR32X2TS U7199 ( .A(n6776), .B(n6775), .C(n6774), .CO(n6806), .S(n6773) );
AOI222XLTS U7200 ( .A0(n6955), .A1(n6778), .B0(n329), .B1(n6777), .C0(n297),
.C1(n6825), .Y(n6779) );
AOI222XLTS U7201 ( .A0(n6893), .A1(n6897), .B0(n6782), .B1(n292), .C0(n6960),
.C1(n6901), .Y(n6783) );
OAI21X1TS U7202 ( .A0(n6868), .A1(n6949), .B0(n6783), .Y(n6784) );
AOI222XLTS U7203 ( .A0(n6818), .A1(n6785), .B0(n340), .B1(n6927), .C0(n6903),
.C1(n6959), .Y(n6786) );
INVX2TS U7204 ( .A(n6872), .Y(n6859) );
CMPR32X2TS U7205 ( .A(n838), .B(n6790), .C(n6789), .CO(n6832), .S(n6798) );
AOI21X1TS U7206 ( .A0(n6826), .A1(n6987), .B0(n6792), .Y(n6793) );
CMPR32X2TS U7207 ( .A(n6798), .B(n6797), .C(n6796), .CO(n6823), .S(n6802) );
CMPR32X2TS U7208 ( .A(n6804), .B(n6803), .C(n6802), .CO(n6836), .S(n6775) );
NAND2X1TS U7209 ( .A(n6806), .B(n6805), .Y(n6808) );
NAND2X1TS U7210 ( .A(n7084), .B(n6916), .Y(n6810) );
INVX2TS U7211 ( .A(n6808), .Y(n6999) );
AOI21X1TS U7212 ( .A0(n7087), .A1(n6916), .B0(n6999), .Y(n6809) );
OAI21X1TS U7213 ( .A0(n7306), .A1(n6810), .B0(n6809), .Y(n6842) );
AOI222XLTS U7214 ( .A0(n6970), .A1(n6811), .B0(n328), .B1(Data_B_i[45]),
.C0(n7034), .C1(n6849), .Y(n6812) );
AOI222XLTS U7215 ( .A0(n6893), .A1(n6926), .B0(n6946), .B1(Data_B_i[48]),
.C0(n6815), .C1(n292), .Y(n6816) );
OAI21X1TS U7216 ( .A0(n6899), .A1(n6949), .B0(n6816), .Y(n6817) );
AOI222XLTS U7217 ( .A0(n6818), .A1(Data_B_i[52]), .B0(n340), .B1(n6937),
.C0(n6903), .C1(n6967), .Y(n6819) );
NAND2X1TS U7218 ( .A(n6826), .B(n7033), .Y(n6827) );
XOR2X1TS U7219 ( .A(n6830), .B(n6829), .Y(n6858) );
CMPR32X2TS U7220 ( .A(n6859), .B(n6832), .C(n6831), .CO(n6883), .S(n6824) );
CMPR32X2TS U7221 ( .A(n6835), .B(n6834), .C(n6833), .CO(n6882), .S(n6838) );
CMPR32X2TS U7222 ( .A(n6838), .B(n6837), .C(n6836), .CO(n6840), .S(n6805) );
NAND2X1TS U7223 ( .A(n6841), .B(n6840), .Y(n6997) );
OAI21X1TS U7224 ( .A0(n7107), .A1(n7109), .B0(n7110), .Y(n7132) );
AOI21X1TS U7225 ( .A0(n7132), .A1(n7136), .B0(n6845), .Y(n6846) );
AOI222XLTS U7226 ( .A0(n6850), .A1(n6969), .B0(n339), .B1(n6954), .C0(n6903),
.C1(n6981), .Y(n6851) );
AOI222XLTS U7227 ( .A0(n6893), .A1(n6927), .B0(n6946), .B1(n6926), .C0(n6960), .C1(n6942), .Y(n6853) );
OAI21X1TS U7228 ( .A0(n6929), .A1(n6949), .B0(n6853), .Y(n6854) );
XOR2X1TS U7229 ( .A(n6854), .B(n6895), .Y(n6861) );
AOI222XLTS U7230 ( .A0(n6955), .A1(n6866), .B0(n329), .B1(Data_B_i[46]),
.C0(n7034), .C1(n6870), .Y(n6855) );
CMPR32X2TS U7231 ( .A(n6860), .B(n6859), .C(n6858), .CO(n6886), .S(n6884) );
CMPR32X2TS U7232 ( .A(n6863), .B(n6862), .C(n6861), .CO(n6890), .S(n6885) );
AOI222XLTS U7233 ( .A0(n6893), .A1(n6937), .B0(n6946), .B1(n6927), .C0(n6960), .C1(n6959), .Y(n6864) );
AOI222XLTS U7234 ( .A0(n6955), .A1(Data_B_i[48]), .B0(n328), .B1(n6866),
.C0(n7034), .C1(n6901), .Y(n6867) );
INVX2TS U7235 ( .A(n6944), .Y(n6921) );
CMPR32X2TS U7236 ( .A(n6873), .B(n6872), .C(n6871), .CO(n6892), .S(n6863) );
AOI21X1TS U7237 ( .A0(n6903), .A1(n6987), .B0(n6875), .Y(n6876) );
XOR2X1TS U7238 ( .A(n6878), .B(n6877), .Y(n6891) );
CMPR32X2TS U7239 ( .A(n6881), .B(n6880), .C(n6879), .CO(n6915), .S(n6912) );
CMPR32X2TS U7240 ( .A(n6884), .B(n6883), .C(n6882), .CO(n6914), .S(n6910) );
CMPR32X2TS U7241 ( .A(n6887), .B(n6886), .C(n6885), .CO(n6889), .S(n6913) );
CMPR32X2TS U7242 ( .A(n6890), .B(n6889), .C(n6888), .CO(n7005), .S(n7003) );
CMPR32X2TS U7243 ( .A(n6921), .B(n6892), .C(n6891), .CO(n6919), .S(n6907) );
AOI222XLTS U7244 ( .A0(n6893), .A1(n6954), .B0(n6946), .B1(n6937), .C0(n6960), .C1(n6967), .Y(n6894) );
AOI222XLTS U7245 ( .A0(n6955), .A1(Data_B_i[49]), .B0(n328), .B1(n6897),
.C0(n298), .C1(n292), .Y(n6898) );
NAND2X1TS U7246 ( .A(n6903), .B(n7033), .Y(n6904) );
XOR2X1TS U7247 ( .A(n6906), .B(n6877), .Y(n6920) );
CMPR32X2TS U7248 ( .A(n6909), .B(n6908), .C(n6907), .CO(n6917), .S(n6888) );
CMPR32X2TS U7249 ( .A(n6912), .B(n6911), .C(n6910), .CO(n7001), .S(n6841) );
CMPR32X2TS U7250 ( .A(n6915), .B(n6914), .C(n6913), .CO(n7002), .S(n7000) );
INVX2TS U7251 ( .A(n7184), .Y(n7011) );
NOR2X2TS U7252 ( .A(n7185), .B(n7011), .Y(n7093) );
CMPR32X2TS U7253 ( .A(n6922), .B(n6921), .C(n6920), .CO(n6936), .S(n6931) );
AOI222XLTS U7254 ( .A0(n6923), .A1(n6969), .B0(n6946), .B1(n6954), .C0(n6960), .C1(n6981), .Y(n6924) );
AOI222XLTS U7255 ( .A0(n6955), .A1(n6927), .B0(n329), .B1(n6926), .C0(n7034),
.C1(n6942), .Y(n6928) );
CMPR32X2TS U7256 ( .A(n6933), .B(n6932), .C(n6931), .CO(n6934), .S(n6918) );
NOR2X1TS U7257 ( .A(n7013), .B(n7012), .Y(n7063) );
CMPR32X2TS U7258 ( .A(n6936), .B(n6935), .C(n6934), .CO(n7015), .S(n7012) );
AOI222XLTS U7259 ( .A0(n6955), .A1(n6937), .B0(n329), .B1(Data_B_i[50]),
.C0(n7034), .C1(n6959), .Y(n6938) );
INVX2TS U7260 ( .A(n6983), .Y(n6976) );
CMPR32X2TS U7261 ( .A(n6945), .B(n6944), .C(n6943), .CO(n6966), .S(n6953) );
AOI21X1TS U7262 ( .A0(n6735), .A1(n6987), .B0(n6947), .Y(n6948) );
CMPR32X2TS U7263 ( .A(n6953), .B(n6952), .C(n6951), .CO(n6991), .S(n6935) );
NOR2X1TS U7264 ( .A(n7015), .B(n7014), .Y(n7067) );
NOR2X1TS U7265 ( .A(n7063), .B(n7067), .Y(n7057) );
AOI222XLTS U7266 ( .A0(n6955), .A1(n6954), .B0(n328), .B1(Data_B_i[51]),
.C0(n7034), .C1(n6967), .Y(n6956) );
NAND2X1TS U7267 ( .A(n6960), .B(n7033), .Y(n6961) );
CMPR32X2TS U7268 ( .A(n6976), .B(n6966), .C(n6965), .CO(n6994), .S(n6992) );
AOI222XLTS U7269 ( .A0(n6970), .A1(n6969), .B0(n329), .B1(n6968), .C0(n7034),
.C1(n6981), .Y(n6971) );
CMPR32X2TS U7270 ( .A(n6977), .B(n6976), .C(n6975), .CO(n6978), .S(n6995) );
NOR2X1TS U7271 ( .A(n7019), .B(n7018), .Y(n7043) );
CMPR32X2TS U7272 ( .A(n6980), .B(n6979), .C(n6978), .CO(n7021), .S(n7018) );
INVX2TS U7273 ( .A(n7200), .Y(n7196) );
CMPR32X2TS U7274 ( .A(n6984), .B(n6983), .C(n6982), .CO(n7032), .S(n6980) );
AOI21X1TS U7275 ( .A0(n7034), .A1(n6987), .B0(n6986), .Y(n6988) );
NOR2X1TS U7276 ( .A(n7043), .B(n7052), .Y(n7024) );
CMPR32X2TS U7277 ( .A(n6993), .B(n6992), .C(n6991), .CO(n7017), .S(n7014) );
CMPR32X2TS U7278 ( .A(n6996), .B(n6995), .C(n6994), .CO(n7019), .S(n7016) );
NOR2X1TS U7279 ( .A(n7017), .B(n7016), .Y(n7044) );
NAND2X1TS U7280 ( .A(n7057), .B(n7026), .Y(n7183) );
NAND2X1TS U7281 ( .A(n7093), .B(n7028), .Y(n7030) );
NAND2X1TS U7282 ( .A(n7001), .B(n7000), .Y(n7090) );
NAND2X1TS U7283 ( .A(n7003), .B(n7002), .Y(n7104) );
NAND2X1TS U7284 ( .A(n7005), .B(n7004), .Y(n7081) );
OAI21X2TS U7285 ( .A0(n7194), .A1(n7011), .B0(n7010), .Y(n7094) );
NAND2X1TS U7286 ( .A(n7013), .B(n7012), .Y(n7097) );
NAND2X1TS U7287 ( .A(n7015), .B(n7014), .Y(n7068) );
OAI21X1TS U7288 ( .A0(n7097), .A1(n7067), .B0(n7068), .Y(n7056) );
NAND2X1TS U7289 ( .A(n7017), .B(n7016), .Y(n7060) );
NAND2X1TS U7290 ( .A(n7019), .B(n7018), .Y(n7211) );
NAND2X1TS U7291 ( .A(n7021), .B(n7020), .Y(n7053) );
AOI21X1TS U7292 ( .A0(n7056), .A1(n7026), .B0(n7025), .Y(n7188) );
AOI21X1TS U7293 ( .A0(n7094), .A1(n7028), .B0(n7027), .Y(n7029) );
CMPR32X2TS U7294 ( .A(n7196), .B(n7032), .C(n7031), .CO(n7040), .S(n7020) );
NAND2X1TS U7295 ( .A(n7034), .B(n7033), .Y(n7035) );
NAND2X1TS U7296 ( .A(n7040), .B(n7039), .Y(n7186) );
INVX2TS U7297 ( .A(n7043), .Y(n7212) );
NAND2X1TS U7298 ( .A(n7207), .B(n7212), .Y(n7051) );
NAND2X1TS U7299 ( .A(n7093), .B(n7057), .Y(n7059) );
AOI21X1TS U7300 ( .A0(n7094), .A1(n7057), .B0(n7056), .Y(n7058) );
NAND2X1TS U7301 ( .A(n7093), .B(n7098), .Y(n7066) );
AOI21X1TS U7302 ( .A0(n7094), .A1(n7098), .B0(n7064), .Y(n7065) );
INVX2TS U7303 ( .A(n7071), .Y(n7086) );
NAND2X1TS U7304 ( .A(n7086), .B(n7091), .Y(n7076) );
NOR2X1TS U7305 ( .A(n7185), .B(n7076), .Y(n7100) );
INVX2TS U7306 ( .A(n7072), .Y(n7105) );
NAND2X1TS U7307 ( .A(n7100), .B(n7105), .Y(n7079) );
AOI21X1TS U7308 ( .A0(n7085), .A1(n7091), .B0(n7074), .Y(n7075) );
AOI21X1TS U7309 ( .A0(n7101), .A1(n7105), .B0(n7077), .Y(n7078) );
NAND2X1TS U7310 ( .A(n7084), .B(n7086), .Y(n7089) );
AOI21X1TS U7311 ( .A0(n7087), .A1(n7086), .B0(n7085), .Y(n7088) );
OAI21X1TS U7312 ( .A0(n310), .A1(n7302), .B0(n7303), .Y(n7115) );
NAND2X1TS U7313 ( .A(n7121), .B(n7120), .Y(n7122) );
NAND2X1TS U7314 ( .A(n7129), .B(n7128), .Y(n7130) );
OAI21X1TS U7315 ( .A0(n310), .A1(n7134), .B0(n7133), .Y(n7137) );
INVX2TS U7316 ( .A(n7152), .Y(n7693) );
INVX2TS U7317 ( .A(n7153), .Y(n7689) );
NAND2X1TS U7318 ( .A(n7684), .B(n7689), .Y(n7160) );
NAND2X1TS U7319 ( .A(n7163), .B(n7162), .Y(n7164) );
CLKINVX1TS U7320 ( .A(n7167), .Y(n7168) );
INVX2TS U7321 ( .A(n7746), .Y(n7828) );
CLKINVX1TS U7322 ( .A(n7745), .Y(n7831) );
AOI21X1TS U7323 ( .A0(n7831), .A1(n7177), .B0(n7176), .Y(n7178) );
CLKINVX1TS U7324 ( .A(n7179), .Y(n7181) );
OAI21X1TS U7325 ( .A0(n7188), .A1(n7187), .B0(n7186), .Y(n7189) );
AOI21X1TS U7326 ( .A0(n7191), .A1(n7190), .B0(n7189), .Y(n7192) );
CMPR32X2TS U7327 ( .A(n7197), .B(n7196), .C(n7195), .CO(n7204), .S(n7039) );
CLKAND2X2TS U7328 ( .A(n7199), .B(n7198), .Y(n7201) );
XOR3X1TS U7329 ( .A(n7202), .B(n7201), .C(n7200), .Y(n7203) );
NAND2X1TS U7330 ( .A(n7204), .B(n7203), .Y(n7205) );
NAND2X1TS U7331 ( .A(n7212), .B(n7211), .Y(n7213) );
NAND2X1TS U7332 ( .A(n7217), .B(n7216), .Y(n7218) );
XNOR2X1TS U7333 ( .A(n7219), .B(n7218), .Y(GEN1_left_N33) );
INVX2TS U7334 ( .A(n7220), .Y(n7234) );
NAND2X1TS U7335 ( .A(n7229), .B(n7234), .Y(n7223) );
AOI21X1TS U7336 ( .A0(n7230), .A1(n7234), .B0(n7221), .Y(n7222) );
NAND2X1TS U7337 ( .A(n7226), .B(n7225), .Y(n7227) );
XNOR2X1TS U7338 ( .A(n7228), .B(n7227), .Y(GEN1_left_N32) );
NAND2X1TS U7339 ( .A(n7234), .B(n7233), .Y(n7235) );
XNOR2X1TS U7340 ( .A(n7236), .B(n7235), .Y(GEN1_left_N31) );
NAND2X1TS U7341 ( .A(n7239), .B(n7238), .Y(n7240) );
XNOR2X1TS U7342 ( .A(n7241), .B(n7240), .Y(GEN1_left_N30) );
NAND2X1TS U7343 ( .A(n7244), .B(n7243), .Y(n7245) );
NAND2X1TS U7344 ( .A(n7309), .B(n7307), .Y(n7248) );
XNOR2X1TS U7345 ( .A(n7326), .B(n7248), .Y(GEN1_left_N25) );
INVX2TS U7346 ( .A(n7249), .Y(n7335) );
CLKINVX1TS U7347 ( .A(n7258), .Y(n7252) );
AOI21X1TS U7348 ( .A0(n7252), .A1(n125), .B0(n7251), .Y(n7253) );
NAND2X1TS U7349 ( .A(n163), .B(n7255), .Y(n7256) );
XNOR2X1TS U7350 ( .A(n7257), .B(n7256), .Y(GEN1_left_N24) );
NAND2X1TS U7351 ( .A(n125), .B(n7260), .Y(n7261) );
XNOR2X1TS U7352 ( .A(n7262), .B(n7261), .Y(GEN1_left_N23) );
NAND2X1TS U7353 ( .A(n7265), .B(n7264), .Y(n7266) );
XNOR2X1TS U7354 ( .A(n7267), .B(n7266), .Y(GEN1_left_N22) );
INVX2TS U7355 ( .A(n7268), .Y(n7353) );
NAND2X1TS U7356 ( .A(n7346), .B(n7344), .Y(n7270) );
XNOR2X1TS U7357 ( .A(n7353), .B(n7270), .Y(GEN1_left_N17) );
NAND2X1TS U7358 ( .A(n7274), .B(n7273), .Y(n7275) );
XNOR2X1TS U7359 ( .A(n7276), .B(n7275), .Y(GEN1_left_N16) );
NAND2X1TS U7360 ( .A(n7360), .B(n7358), .Y(n7279) );
XNOR2X1TS U7361 ( .A(n7367), .B(n7279), .Y(GEN1_left_N12) );
NAND2X1TS U7362 ( .A(n7283), .B(n7282), .Y(n7284) );
XNOR2X1TS U7363 ( .A(n7285), .B(n7284), .Y(GEN1_left_N11) );
INVX1TS U7364 ( .A(n7286), .Y(n7389) );
INVX2TS U7365 ( .A(n7287), .Y(n7289) );
NAND2X1TS U7366 ( .A(n7289), .B(n7288), .Y(n7290) );
XNOR2X1TS U7367 ( .A(n7291), .B(n7290), .Y(GEN1_left_N8) );
XNOR2X1TS U7368 ( .A(n7294), .B(n7293), .Y(GEN1_left_N5) );
NAND2X1TS U7369 ( .A(n7296), .B(n7295), .Y(n7298) );
XNOR2X1TS U7370 ( .A(n7298), .B(n7297), .Y(GEN1_left_N3) );
XNOR2X1TS U7371 ( .A(n7301), .B(n7300), .Y(GEN1_left_N1) );
NAND2X1TS U7372 ( .A(n7304), .B(n7303), .Y(n7305) );
AOI21X1TS U7373 ( .A0(n7326), .A1(n7309), .B0(n7308), .Y(n7314) );
NAND2X1TS U7374 ( .A(n7312), .B(n7311), .Y(n7313) );
AOI21X1TS U7375 ( .A0(n7326), .A1(n7318), .B0(n7317), .Y(n7323) );
NAND2X1TS U7376 ( .A(n7321), .B(n7320), .Y(n7322) );
AOI21X1TS U7377 ( .A0(n7326), .A1(n7325), .B0(n7324), .Y(n7331) );
NAND2X1TS U7378 ( .A(n7329), .B(n7328), .Y(n7330) );
NAND2X1TS U7379 ( .A(n7333), .B(n7332), .Y(n7334) );
AOI21X1TS U7380 ( .A0(n7338), .A1(n7353), .B0(n7337), .Y(n7343) );
NAND2X1TS U7381 ( .A(n7341), .B(n7340), .Y(n7342) );
AOI21X1TS U7382 ( .A0(n7353), .A1(n7346), .B0(n7345), .Y(n7350) );
NAND2X1TS U7383 ( .A(n371), .B(n7348), .Y(n7349) );
AOI21X1TS U7384 ( .A0(n7353), .A1(n7352), .B0(n7351), .Y(n7357) );
NAND2X1TS U7385 ( .A(n423), .B(n7355), .Y(n7356) );
AOI21X1TS U7386 ( .A0(n7367), .A1(n7360), .B0(n7359), .Y(n7365) );
NAND2X1TS U7387 ( .A(n7363), .B(n7362), .Y(n7364) );
AOI21X1TS U7388 ( .A0(n7367), .A1(n419), .B0(n7366), .Y(n7370) );
NAND2X1TS U7389 ( .A(n520), .B(n7368), .Y(n7369) );
NAND2X1TS U7390 ( .A(n7373), .B(n7372), .Y(n7374) );
NAND2X1TS U7391 ( .A(n7378), .B(n7377), .Y(n7379) );
NAND2X1TS U7392 ( .A(n7383), .B(n7382), .Y(n7384) );
NAND2X1TS U7393 ( .A(n7388), .B(n7387), .Y(n7390) );
NAND2X1TS U7394 ( .A(n7393), .B(n7392), .Y(n7395) );
NAND2X1TS U7395 ( .A(n7398), .B(n7397), .Y(n7399) );
NAND2X1TS U7396 ( .A(n7404), .B(n7409), .Y(n7412) );
OR2X2TS U7397 ( .A(n7430), .B(n7412), .Y(n7414) );
AOI21X1TS U7398 ( .A0(n7410), .A1(n7409), .B0(n7408), .Y(n7411) );
OA21XLTS U7399 ( .A0(n7429), .A1(n7412), .B0(n7411), .Y(n7413) );
CMPR32X2TS U7400 ( .A(n7417), .B(n7416), .C(n7415), .CO(n7424), .S(n5112) );
CLKAND2X2TS U7401 ( .A(n7419), .B(n7418), .Y(n7421) );
XOR3X1TS U7402 ( .A(n7422), .B(n7421), .C(n7420), .Y(n7423) );
NAND2X1TS U7403 ( .A(n7424), .B(n7423), .Y(n7425) );
NAND2X1TS U7404 ( .A(n7426), .B(n7425), .Y(n7427) );
NOR2X1TS U7405 ( .A(n7434), .B(n7450), .Y(n7438) );
INVX2TS U7406 ( .A(n7467), .Y(n7456) );
NAND2X1TS U7407 ( .A(n7438), .B(n7456), .Y(n7440) );
INVX2TS U7408 ( .A(n7435), .Y(n7497) );
OAI21X1TS U7409 ( .A0(n7436), .A1(n7450), .B0(n7451), .Y(n7437) );
AOI21X1TS U7410 ( .A0(n7458), .A1(n7438), .B0(n7437), .Y(n7439) );
NAND2X1TS U7411 ( .A(n7443), .B(n7442), .Y(n7444) );
XNOR2X1TS U7412 ( .A(n7445), .B(n7444), .Y(GEN1_right_N36) );
NAND2X1TS U7413 ( .A(n7456), .B(n7447), .Y(n7449) );
AOI21X1TS U7414 ( .A0(n7458), .A1(n7447), .B0(n7446), .Y(n7448) );
NAND2X1TS U7415 ( .A(n7452), .B(n7451), .Y(n7453) );
XNOR2X1TS U7416 ( .A(n7454), .B(n7453), .Y(GEN1_right_N35) );
INVX2TS U7417 ( .A(n7455), .Y(n7469) );
NAND2X1TS U7418 ( .A(n7456), .B(n7469), .Y(n7460) );
AOI21X1TS U7419 ( .A0(n7458), .A1(n7469), .B0(n7457), .Y(n7459) );
NAND2X1TS U7420 ( .A(n7463), .B(n7462), .Y(n7464) );
XNOR2X1TS U7421 ( .A(n7465), .B(n7464), .Y(GEN1_right_N34) );
NAND2X1TS U7422 ( .A(n7469), .B(n7468), .Y(n7470) );
XNOR2X1TS U7423 ( .A(n7471), .B(n7470), .Y(GEN1_right_N33) );
INVX2TS U7424 ( .A(n7472), .Y(n7485) );
NAND2X1TS U7425 ( .A(n7481), .B(n7485), .Y(n7475) );
NAND2X1TS U7426 ( .A(n7478), .B(n7477), .Y(n7479) );
XNOR2X1TS U7427 ( .A(n7480), .B(n7479), .Y(GEN1_right_N32) );
NAND2X1TS U7428 ( .A(n7485), .B(n7484), .Y(n7486) );
XNOR2X1TS U7429 ( .A(n7487), .B(n7486), .Y(GEN1_right_N31) );
NAND2X1TS U7430 ( .A(n7490), .B(n7489), .Y(n7491) );
XNOR2X1TS U7431 ( .A(n7492), .B(n7491), .Y(GEN1_right_N30) );
NAND2X1TS U7432 ( .A(n7495), .B(n7494), .Y(n7496) );
NAND2X1TS U7433 ( .A(n7561), .B(n7559), .Y(n7499) );
XNOR2X1TS U7434 ( .A(n7578), .B(n7499), .Y(GEN1_right_N25) );
INVX2TS U7435 ( .A(n7500), .Y(n7587) );
CLKINVX1TS U7436 ( .A(n7510), .Y(n7503) );
AOI21X1TS U7437 ( .A0(n7503), .A1(n7513), .B0(n7502), .Y(n7504) );
NAND2X1TS U7438 ( .A(n7507), .B(n7506), .Y(n7508) );
XNOR2X1TS U7439 ( .A(n7509), .B(n7508), .Y(GEN1_right_N24) );
NAND2X1TS U7440 ( .A(n7513), .B(n7512), .Y(n7514) );
XNOR2X1TS U7441 ( .A(n7515), .B(n7514), .Y(GEN1_right_N23) );
NAND2X1TS U7442 ( .A(n124), .B(n7517), .Y(n7518) );
XNOR2X1TS U7443 ( .A(n7519), .B(n7518), .Y(GEN1_right_N22) );
INVX2TS U7444 ( .A(n7520), .Y(n7607) );
NAND2X1TS U7445 ( .A(n7599), .B(n7597), .Y(n7522) );
XNOR2X1TS U7446 ( .A(n7607), .B(n7522), .Y(GEN1_right_N17) );
NAND2X1TS U7447 ( .A(n7526), .B(n7525), .Y(n7527) );
XNOR2X1TS U7448 ( .A(n7528), .B(n7527), .Y(GEN1_right_N16) );
INVX2TS U7449 ( .A(n7529), .Y(n7623) );
NAND2X1TS U7450 ( .A(n7615), .B(n7613), .Y(n7531) );
XNOR2X1TS U7451 ( .A(n7623), .B(n7531), .Y(GEN1_right_N12) );
NAND2X1TS U7452 ( .A(n7535), .B(n7534), .Y(n7536) );
XNOR2X1TS U7453 ( .A(n7537), .B(n7536), .Y(GEN1_right_N11) );
NAND2X1TS U7454 ( .A(n7541), .B(n7540), .Y(n7542) );
XNOR2X1TS U7455 ( .A(n7543), .B(n7542), .Y(GEN1_right_N8) );
NAND2X1TS U7456 ( .A(n193), .B(n7544), .Y(n7546) );
XNOR2X1TS U7457 ( .A(n7546), .B(n7545), .Y(GEN1_right_N5) );
NAND2X1TS U7458 ( .A(n7548), .B(n7547), .Y(n7550) );
XNOR2X1TS U7459 ( .A(n7550), .B(n7549), .Y(GEN1_right_N3) );
XNOR2X1TS U7460 ( .A(n7553), .B(n7552), .Y(GEN1_right_N1) );
NAND2X1TS U7461 ( .A(n7556), .B(n7555), .Y(n7557) );
AOI21X1TS U7462 ( .A0(n7578), .A1(n7561), .B0(n7560), .Y(n7566) );
NAND2X1TS U7463 ( .A(n7564), .B(n7563), .Y(n7565) );
AOI21X1TS U7464 ( .A0(n7578), .A1(n7570), .B0(n7569), .Y(n7575) );
NAND2X1TS U7465 ( .A(n7573), .B(n7572), .Y(n7574) );
AOI21X1TS U7466 ( .A0(n7578), .A1(n7577), .B0(n7576), .Y(n7583) );
NAND2X1TS U7467 ( .A(n7581), .B(n7580), .Y(n7582) );
NAND2X1TS U7468 ( .A(n7585), .B(n7584), .Y(n7586) );
AOI21X1TS U7469 ( .A0(n7591), .A1(n7607), .B0(n7590), .Y(n7596) );
NAND2X1TS U7470 ( .A(n7594), .B(n7593), .Y(n7595) );
AOI21X1TS U7471 ( .A0(n7607), .A1(n7599), .B0(n7598), .Y(n7604) );
NAND2X1TS U7472 ( .A(n7602), .B(n7601), .Y(n7603) );
AOI21X1TS U7473 ( .A0(n7607), .A1(n7606), .B0(n7605), .Y(n7612) );
NAND2X1TS U7474 ( .A(n7610), .B(n7609), .Y(n7611) );
AOI21X1TS U7475 ( .A0(n7623), .A1(n7615), .B0(n7614), .Y(n7620) );
NAND2X1TS U7476 ( .A(n7618), .B(n7617), .Y(n7619) );
AOI21X1TS U7477 ( .A0(n7623), .A1(n7622), .B0(n7621), .Y(n7627) );
NAND2X1TS U7478 ( .A(n7625), .B(n7624), .Y(n7626) );
NAND2X1TS U7479 ( .A(n7630), .B(n7629), .Y(n7631) );
NAND2X1TS U7480 ( .A(n7635), .B(n7634), .Y(n7636) );
NAND2X1TS U7481 ( .A(n7640), .B(n7639), .Y(n7641) );
NAND2X1TS U7482 ( .A(n7645), .B(n7644), .Y(n7647) );
NAND2X1TS U7483 ( .A(n7650), .B(n7649), .Y(n7652) );
NAND2X1TS U7484 ( .A(n7655), .B(n7654), .Y(n7656) );
NAND2X1TS U7485 ( .A(n603), .B(n7665), .Y(n7667) );
OR2X4TS U7486 ( .A(n7710), .B(n7667), .Y(n7668) );
CMPR32X2TS U7487 ( .A(n7671), .B(n7670), .C(n7669), .CO(n7679), .S(n5186) );
NOR2XLTS U7488 ( .A(n7672), .B(n160), .Y(n7676) );
NAND2X1TS U7489 ( .A(n7679), .B(n7678), .Y(n7680) );
NAND2X1TS U7490 ( .A(n7681), .B(n7680), .Y(n7682) );
XNOR2X1TS U7491 ( .A(n7683), .B(n7682), .Y(GEN1_middle_N55) );
CLKINVX1TS U7492 ( .A(n7684), .Y(n7687) );
NAND2X1TS U7493 ( .A(n7689), .B(n7688), .Y(n7690) );
XNOR2X1TS U7494 ( .A(n7691), .B(n7690), .Y(GEN1_middle_N46) );
CLKINVX2TS U7495 ( .A(n7710), .Y(n7700) );
NAND2X1TS U7496 ( .A(n7700), .B(n7693), .Y(n7695) );
INVX2TS U7497 ( .A(n7709), .Y(n7702) );
AOI21X1TS U7498 ( .A0(n7702), .A1(n7693), .B0(n7692), .Y(n7694) );
NAND2X1TS U7499 ( .A(n7697), .B(n7696), .Y(n7698) );
XNOR2X1TS U7500 ( .A(n7699), .B(n7698), .Y(GEN1_middle_N45) );
NAND2X1TS U7501 ( .A(n7700), .B(n7711), .Y(n7704) );
AOI21X1TS U7502 ( .A0(n7702), .A1(n7711), .B0(n7701), .Y(n7703) );
NAND2X1TS U7503 ( .A(n7706), .B(n7705), .Y(n7707) );
XNOR2X1TS U7504 ( .A(n7708), .B(n7707), .Y(GEN1_middle_N44) );
NAND2X1TS U7505 ( .A(n7712), .B(n7711), .Y(n7713) );
XNOR2X1TS U7506 ( .A(n7714), .B(n7713), .Y(GEN1_middle_N43) );
NOR2X1TS U7507 ( .A(n7734), .B(n7735), .Y(n7726) );
NAND2X1TS U7508 ( .A(n7715), .B(n7726), .Y(n7720) );
OAI21X1TS U7509 ( .A0(n7733), .A1(n7735), .B0(n7736), .Y(n7727) );
CLKINVX1TS U7510 ( .A(n7730), .Y(n7718) );
AOI21X1TS U7511 ( .A0(n7727), .A1(n7715), .B0(n7718), .Y(n7719) );
INVX2TS U7512 ( .A(n7721), .Y(n7722) );
NAND2X1TS U7513 ( .A(n7723), .B(n7722), .Y(n7724) );
NAND2X1TS U7514 ( .A(n7715), .B(n7730), .Y(n7731) );
XNOR2X1TS U7515 ( .A(n7732), .B(n7731), .Y(GEN1_middle_N41) );
NAND2X1TS U7516 ( .A(n7737), .B(n7736), .Y(n7738) );
XNOR2X1TS U7517 ( .A(n7739), .B(n7738), .Y(GEN1_middle_N40) );
NAND2X1TS U7518 ( .A(n7742), .B(n7741), .Y(n7743) );
XNOR2X1TS U7519 ( .A(n7744), .B(n7743), .Y(GEN1_middle_N39) );
OAI21X1TS U7520 ( .A0(n7866), .A1(n7746), .B0(n7745), .Y(n7749) );
INVX2TS U7521 ( .A(n7747), .Y(n7820) );
NAND2X1TS U7522 ( .A(n7820), .B(n7818), .Y(n7748) );
XNOR2X1TS U7523 ( .A(n7749), .B(n7748), .Y(GEN1_middle_N34) );
OAI21X1TS U7524 ( .A0(n7866), .A1(n7862), .B0(n7864), .Y(n7754) );
CLKINVX1TS U7525 ( .A(n7750), .Y(n7752) );
NAND2X1TS U7526 ( .A(n7752), .B(n7751), .Y(n7753) );
XNOR2X1TS U7527 ( .A(n7754), .B(n7753), .Y(GEN1_middle_N31) );
CLKINVX1TS U7528 ( .A(n7755), .Y(n7894) );
CLKINVX1TS U7529 ( .A(n7764), .Y(n7758) );
AOI21X1TS U7530 ( .A0(n7758), .A1(n7766), .B0(n7757), .Y(n7759) );
XNOR2X1TS U7531 ( .A(n7763), .B(n7762), .Y(GEN1_middle_N25) );
XNOR2X1TS U7532 ( .A(n7768), .B(n7767), .Y(GEN1_middle_N24) );
NAND2X1TS U7533 ( .A(n7771), .B(n7770), .Y(n7772) );
XNOR2X1TS U7534 ( .A(n7773), .B(n7772), .Y(GEN1_middle_N23) );
CLKINVX1TS U7535 ( .A(n7775), .Y(n7913) );
NAND2X1TS U7536 ( .A(n7913), .B(n7911), .Y(n7776) );
XNOR2X1TS U7537 ( .A(n7914), .B(n7776), .Y(GEN1_middle_N18) );
CLKINVX1TS U7538 ( .A(n7777), .Y(n7924) );
NAND2X1TS U7539 ( .A(n7780), .B(n7779), .Y(n7781) );
XNOR2X1TS U7540 ( .A(n7782), .B(n7781), .Y(GEN1_middle_N17) );
NAND2X1TS U7541 ( .A(n115), .B(n7783), .Y(n7784) );
XNOR2X1TS U7542 ( .A(n7926), .B(n7784), .Y(GEN1_middle_N14) );
INVX2TS U7543 ( .A(n7785), .Y(n7935) );
NAND2X1TS U7544 ( .A(n7788), .B(n7787), .Y(n7789) );
XNOR2X1TS U7545 ( .A(n7790), .B(n7789), .Y(GEN1_middle_N13) );
INVX1TS U7546 ( .A(n7791), .Y(n7938) );
NAND2X1TS U7547 ( .A(n7937), .B(n7792), .Y(n7793) );
XNOR2X1TS U7548 ( .A(n7938), .B(n7793), .Y(GEN1_middle_N10) );
INVX1TS U7549 ( .A(n7794), .Y(n7946) );
CLKINVX1TS U7550 ( .A(n7795), .Y(n7797) );
NAND2X1TS U7551 ( .A(n7797), .B(n7796), .Y(n7798) );
XNOR2X1TS U7552 ( .A(n7799), .B(n7798), .Y(GEN1_middle_N9) );
NAND2X1TS U7553 ( .A(n7801), .B(n7800), .Y(n7803) );
XNOR2X1TS U7554 ( .A(n7803), .B(n7802), .Y(GEN1_middle_N6) );
NAND2X1TS U7555 ( .A(n7805), .B(n7804), .Y(n7807) );
XNOR2X1TS U7556 ( .A(n7807), .B(n7806), .Y(GEN1_middle_N4) );
NAND2X1TS U7557 ( .A(n7809), .B(n7808), .Y(n7811) );
XNOR2X1TS U7558 ( .A(n7811), .B(n7810), .Y(GEN1_middle_N2) );
NOR2BX1TS U7559 ( .AN(n7813), .B(n7812), .Y(GEN1_middle_N0) );
OR2X1TS U7560 ( .A(n7815), .B(n7814), .Y(n7817) );
CLKAND2X2TS U7561 ( .A(n7817), .B(n7816), .Y(GEN1_middle_N1) );
NAND2X1TS U7562 ( .A(n7828), .B(n7820), .Y(n7822) );
CLKINVX1TS U7563 ( .A(n7818), .Y(n7819) );
AOI21X1TS U7564 ( .A0(n7831), .A1(n7820), .B0(n7819), .Y(n7821) );
NAND2X1TS U7565 ( .A(n7825), .B(n7824), .Y(n7826) );
XNOR2X1TS U7566 ( .A(n7827), .B(n7826), .Y(GEN1_middle_N35) );
NAND2X1TS U7567 ( .A(n7830), .B(n7828), .Y(n7833) );
AOI21X1TS U7568 ( .A0(n7831), .A1(n7830), .B0(n7829), .Y(n7832) );
NAND2X1TS U7569 ( .A(n7835), .B(n7834), .Y(n7836) );
XNOR2X1TS U7570 ( .A(n7837), .B(n7836), .Y(GEN1_middle_N36) );
INVX2TS U7571 ( .A(n218), .Y(n7851) );
NAND2X1TS U7572 ( .A(n7847), .B(n7851), .Y(n7841) );
OAI21X1TS U7573 ( .A0(n7866), .A1(n7841), .B0(n7840), .Y(n7846) );
CLKINVX1TS U7574 ( .A(n7842), .Y(n7844) );
NAND2X1TS U7575 ( .A(n7844), .B(n7843), .Y(n7845) );
XNOR2X1TS U7576 ( .A(n7846), .B(n7845), .Y(GEN1_middle_N33) );
OAI21X1TS U7577 ( .A0(n7866), .A1(n7849), .B0(n7848), .Y(n7853) );
NAND2X1TS U7578 ( .A(n7851), .B(n7850), .Y(n7852) );
XNOR2X1TS U7579 ( .A(n7853), .B(n7852), .Y(GEN1_middle_N32) );
CLKINVX1TS U7580 ( .A(n7856), .Y(n7885) );
NAND2X1TS U7581 ( .A(n7885), .B(n7883), .Y(n7857) );
XNOR2X1TS U7582 ( .A(n7855), .B(n7857), .Y(GEN1_middle_N26) );
NAND2X1TS U7583 ( .A(n7860), .B(n7859), .Y(n7861) );
NAND2X1TS U7584 ( .A(n7864), .B(n7863), .Y(n7865) );
AOI21X1TS U7585 ( .A0(n7855), .A1(n129), .B0(n132), .Y(n7871) );
NAND2X1TS U7586 ( .A(n7869), .B(n7868), .Y(n7870) );
CLKINVX1TS U7587 ( .A(n132), .Y(n7875) );
AOI21X1TS U7588 ( .A0(n7855), .A1(n7877), .B0(n7876), .Y(n7882) );
NAND2X1TS U7589 ( .A(n7880), .B(n7879), .Y(n7881) );
AOI21X1TS U7590 ( .A0(n7855), .A1(n7885), .B0(n7884), .Y(n7890) );
NAND2X1TS U7591 ( .A(n7887), .B(n7888), .Y(n7889) );
NAND2X1TS U7592 ( .A(n7892), .B(n7891), .Y(n7893) );
AOI21X1TS U7593 ( .A0(n7914), .A1(n7898), .B0(n7900), .Y(n7897) );
NAND2X1TS U7594 ( .A(n7895), .B(n7901), .Y(n7896) );
CLKINVX1TS U7595 ( .A(n7898), .Y(n7899) );
CLKINVX1TS U7596 ( .A(n7900), .Y(n7903) );
AOI21X1TS U7597 ( .A0(n7914), .A1(n7905), .B0(n7904), .Y(n7910) );
NAND2X1TS U7598 ( .A(n7907), .B(n7908), .Y(n7909) );
AOI21X1TS U7599 ( .A0(n7914), .A1(n7913), .B0(n7912), .Y(n7919) );
NAND2X1TS U7600 ( .A(n7917), .B(n7916), .Y(n7918) );
NAND2X1TS U7601 ( .A(n7922), .B(n7921), .Y(n7923) );
AOI21X1TS U7602 ( .A0(n7926), .A1(n115), .B0(n7925), .Y(n7930) );
NAND2X1TS U7603 ( .A(n7928), .B(n7927), .Y(n7929) );
NAND2X1TS U7604 ( .A(n7933), .B(n7932), .Y(n7934) );
AOI21X1TS U7605 ( .A0(n7938), .A1(n7937), .B0(n7936), .Y(n7941) );
NAND2X1TS U7606 ( .A(n162), .B(n7939), .Y(n7940) );
NAND2X1TS U7607 ( .A(n7944), .B(n7943), .Y(n7945) );
NAND2X1TS U7608 ( .A(n7949), .B(n7948), .Y(n7951) );
NAND2X1TS U7609 ( .A(n7954), .B(n7953), .Y(n7956) );
NAND2X1TS U7610 ( .A(n7959), .B(n7958), .Y(n7961) );
CLKBUFX2TS U7611 ( .A(n8311), .Y(n8333) );
CLKBUFX2TS U7612 ( .A(n8019), .Y(n8332) );
CLKBUFX2TS U7613 ( .A(n7962), .Y(n8324) );
CLKBUFX2TS U7614 ( .A(n7962), .Y(n8325) );
CLKBUFX2TS U7615 ( .A(n7962), .Y(n8326) );
CLKBUFX2TS U7616 ( .A(n7962), .Y(n8328) );
CLKBUFX2TS U7617 ( .A(n8328), .Y(n8327) );
CLKBUFX2TS U7618 ( .A(n7962), .Y(n8322) );
CLKBUFX2TS U7619 ( .A(n7962), .Y(n8323) );
CLKBUFX2TS U7620 ( .A(n7962), .Y(n8321) );
CLKBUFX2TS U7621 ( .A(n7962), .Y(n8320) );
CLKBUFX2TS U7622 ( .A(n7962), .Y(n8319) );
CLKBUFX2TS U7623 ( .A(n7962), .Y(n8318) );
INVX2TS U7624 ( .A(n8297), .Y(n8329) );
INVX2TS U7625 ( .A(n8311), .Y(n8331) );
INVX2TS U7626 ( .A(n8297), .Y(n8330) );
AOI21X1TS U7627 ( .A0(n7964), .A1(n8220), .B0(n7963), .Y(n8229) );
NAND2X1TS U7628 ( .A(n8239), .B(n7966), .Y(n7968) );
AOI21X1TS U7629 ( .A0(n7966), .A1(n8238), .B0(n7965), .Y(n7967) );
NAND2X1TS U7630 ( .A(n8258), .B(n7970), .Y(n8273) );
NAND2X1TS U7631 ( .A(n8284), .B(n7972), .Y(n7974) );
AOI21X1TS U7632 ( .A0(n7970), .A1(n8259), .B0(n7969), .Y(n8272) );
AOI21X1TS U7633 ( .A0(n7972), .A1(n8285), .B0(n7971), .Y(n7973) );
AOI21X1TS U7634 ( .A0(n8249), .A1(n7976), .B0(n7975), .Y(n8013) );
NAND2X1TS U7635 ( .A(n8015), .B(n7978), .Y(n8021) );
NAND2X1TS U7636 ( .A(n8034), .B(n7980), .Y(n7982) );
NAND2X1TS U7637 ( .A(n8055), .B(n7984), .Y(n8064) );
NAND2X1TS U7638 ( .A(n8079), .B(n7986), .Y(n7988) );
NAND2X1TS U7639 ( .A(n8045), .B(n7990), .Y(n7992) );
AOI21X1TS U7640 ( .A0(n7978), .A1(n8014), .B0(n7977), .Y(n8022) );
AOI21X1TS U7641 ( .A0(n7980), .A1(n8033), .B0(n7979), .Y(n7981) );
AOI21X1TS U7642 ( .A0(n7984), .A1(n8054), .B0(n7983), .Y(n8065) );
AOI21X1TS U7643 ( .A0(n7986), .A1(n8078), .B0(n7985), .Y(n7987) );
AOI21X1TS U7644 ( .A0(n8044), .A1(n7990), .B0(n7989), .Y(n7991) );
OAI21X1TS U7645 ( .A0(n8013), .A1(n7992), .B0(n7991), .Y(n8089) );
NAND2X1TS U7646 ( .A(n8097), .B(n7994), .Y(n8111) );
NAND2X1TS U7647 ( .A(n8121), .B(n7996), .Y(n7998) );
NAND2X1TS U7648 ( .A(n8149), .B(n8000), .Y(n8163) );
NAND2X1TS U7649 ( .A(n8174), .B(n8002), .Y(n8004) );
NAND2X1TS U7650 ( .A(n8136), .B(n8006), .Y(n8189) );
NAND2X1TS U7651 ( .A(n8316), .B(n8314), .Y(n8200) );
NAND2X1TS U7652 ( .A(n8205), .B(n8315), .Y(n8010) );
AOI21X1TS U7653 ( .A0(n7994), .A1(n8098), .B0(n7993), .Y(n8110) );
AOI21X1TS U7654 ( .A0(n7996), .A1(n8122), .B0(n7995), .Y(n7997) );
AOI21X1TS U7655 ( .A0(n8000), .A1(n8150), .B0(n7999), .Y(n8162) );
AOI21X1TS U7656 ( .A0(n8002), .A1(n8175), .B0(n8001), .Y(n8003) );
AOI21X1TS U7657 ( .A0(n8137), .A1(n8006), .B0(n8005), .Y(n8188) );
INVX2TS U7658 ( .A(GEN1_Final_add_x_1_n108), .Y(n8194) );
INVX2TS U7659 ( .A(GEN1_Final_add_x_1_n103), .Y(n8007) );
AOI21X1TS U7660 ( .A0(n8314), .A1(n8194), .B0(n8007), .Y(n8199) );
AOI21X1TS U7661 ( .A0(n8206), .A1(n8315), .B0(n8008), .Y(n8009) );
AOI21X1TS U7662 ( .A0(n8089), .A1(n8012), .B0(n8011), .Y(
GEN1_Final_add_x_1_n81) );
INVX2TS U7663 ( .A(n8013), .Y(n8303) );
AOI21X1TS U7664 ( .A0(n8303), .A1(n8015), .B0(n8014), .Y(n8310) );
NAND2X1TS U7665 ( .A(n8016), .B(GEN1_Final_add_x_1_n289), .Y(n8017) );
XNOR2X1TS U7666 ( .A(n8018), .B(n8017), .Y(n8020) );
INVX2TS U7667 ( .A(n8256), .Y(n8071) );
MX2X1TS U7668 ( .A(sgf_result_o[46]), .B(n8020), .S0(n8071), .Y(n64) );
INVX2TS U7669 ( .A(n8021), .Y(n8024) );
AOI21X1TS U7670 ( .A0(n8303), .A1(n8024), .B0(n8023), .Y(n8028) );
INVX2TS U7671 ( .A(n8028), .Y(n8035) );
NAND2X1TS U7672 ( .A(n8025), .B(GEN1_Final_add_x_1_n279), .Y(n8026) );
XNOR2X1TS U7673 ( .A(n8035), .B(n8026), .Y(n8027) );
MX2X1TS U7674 ( .A(sgf_result_o[47]), .B(n8027), .S0(n8071), .Y(n63) );
NAND2X1TS U7675 ( .A(n8029), .B(GEN1_Final_add_x_1_n276), .Y(n8030) );
XNOR2X1TS U7676 ( .A(n8031), .B(n8030), .Y(n8032) );
MX2X1TS U7677 ( .A(sgf_result_o[48]), .B(n8032), .S0(n8071), .Y(n62) );
AOI21X1TS U7678 ( .A0(n8035), .A1(n8034), .B0(n8033), .Y(n8039) );
NAND2X1TS U7679 ( .A(n8036), .B(GEN1_Final_add_x_1_n271), .Y(n8037) );
XOR2XLTS U7680 ( .A(n8039), .B(n8037), .Y(n8038) );
MX2X1TS U7681 ( .A(sgf_result_o[49]), .B(n8038), .S0(n8071), .Y(n61) );
NAND2X1TS U7682 ( .A(n8040), .B(GEN1_Final_add_x_1_n268), .Y(n8041) );
XNOR2X1TS U7683 ( .A(n8042), .B(n8041), .Y(n8043) );
MX2X1TS U7684 ( .A(sgf_result_o[50]), .B(n8043), .S0(n8071), .Y(n60) );
AOI21X1TS U7685 ( .A0(n8303), .A1(n8045), .B0(n8044), .Y(n8049) );
INVX2TS U7686 ( .A(n8049), .Y(n8068) );
NAND2X1TS U7687 ( .A(n8046), .B(GEN1_Final_add_x_1_n258), .Y(n8047) );
XNOR2X1TS U7688 ( .A(n8068), .B(n8047), .Y(n8048) );
MX2X1TS U7689 ( .A(sgf_result_o[51]), .B(n8048), .S0(n8071), .Y(n59) );
OAI21XLTS U7690 ( .A0(n8049), .A1(GEN1_Final_add_x_1_n257), .B0(
GEN1_Final_add_x_1_n258), .Y(n8052) );
NAND2X1TS U7691 ( .A(n8050), .B(GEN1_Final_add_x_1_n255), .Y(n8051) );
XNOR2X1TS U7692 ( .A(n8052), .B(n8051), .Y(n8053) );
MX2X1TS U7693 ( .A(sgf_result_o[52]), .B(n8053), .S0(n8071), .Y(n58) );
AOI21X1TS U7694 ( .A0(n8068), .A1(n8055), .B0(n8054), .Y(n8059) );
NAND2X1TS U7695 ( .A(n8056), .B(GEN1_Final_add_x_1_n250), .Y(n8057) );
XOR2XLTS U7696 ( .A(n8059), .B(n8057), .Y(n8058) );
MX2X1TS U7697 ( .A(sgf_result_o[53]), .B(n8058), .S0(n8071), .Y(n57) );
NAND2X1TS U7698 ( .A(n8060), .B(GEN1_Final_add_x_1_n247), .Y(n8061) );
XNOR2X1TS U7699 ( .A(n8062), .B(n8061), .Y(n8063) );
MX2X1TS U7700 ( .A(sgf_result_o[54]), .B(n8063), .S0(n8071), .Y(n56) );
AOI21X1TS U7701 ( .A0(n8068), .A1(n8067), .B0(n8066), .Y(n8073) );
INVX2TS U7702 ( .A(n8073), .Y(n8080) );
NAND2X1TS U7703 ( .A(n8069), .B(GEN1_Final_add_x_1_n237), .Y(n8070) );
XNOR2X1TS U7704 ( .A(n8080), .B(n8070), .Y(n8072) );
MX2X1TS U7705 ( .A(sgf_result_o[55]), .B(n8072), .S0(n8071), .Y(n55) );
NAND2X1TS U7706 ( .A(n8074), .B(GEN1_Final_add_x_1_n234), .Y(n8075) );
XNOR2X1TS U7707 ( .A(n8076), .B(n8075), .Y(n8077) );
INVX2TS U7708 ( .A(n8256), .Y(n8127) );
MX2X1TS U7709 ( .A(sgf_result_o[56]), .B(n8077), .S0(n8127), .Y(n54) );
AOI21X1TS U7710 ( .A0(n8080), .A1(n8079), .B0(n8078), .Y(n8084) );
NAND2X1TS U7711 ( .A(n8081), .B(GEN1_Final_add_x_1_n229), .Y(n8082) );
MX2X1TS U7712 ( .A(sgf_result_o[57]), .B(n8083), .S0(n8127), .Y(n53) );
NAND2X1TS U7713 ( .A(n8085), .B(GEN1_Final_add_x_1_n226), .Y(n8086) );
XNOR2X1TS U7714 ( .A(n8087), .B(n8086), .Y(n8088) );
MX2X1TS U7715 ( .A(sgf_result_o[58]), .B(n8088), .S0(n8127), .Y(n52) );
INVX2TS U7716 ( .A(n8089), .Y(n8190) );
NAND2X1TS U7717 ( .A(n8090), .B(GEN1_Final_add_x_1_n214), .Y(n8091) );
XOR2XLTS U7718 ( .A(n8190), .B(n8091), .Y(n8092) );
MX2X1TS U7719 ( .A(sgf_result_o[59]), .B(n8092), .S0(n8127), .Y(n51) );
NAND2X1TS U7720 ( .A(n8093), .B(GEN1_Final_add_x_1_n211), .Y(n8094) );
XNOR2X1TS U7721 ( .A(n8095), .B(n8094), .Y(n8096) );
MX2X1TS U7722 ( .A(sgf_result_o[60]), .B(n8096), .S0(n8127), .Y(n50) );
INVX2TS U7723 ( .A(n8097), .Y(n8100) );
INVX2TS U7724 ( .A(n8098), .Y(n8099) );
NAND2X1TS U7725 ( .A(n8104), .B(GEN1_Final_add_x_1_n204), .Y(n8101) );
XNOR2X1TS U7726 ( .A(n8105), .B(n8101), .Y(n8102) );
MX2X1TS U7727 ( .A(sgf_result_o[61]), .B(n8102), .S0(n8127), .Y(n49) );
INVX2TS U7728 ( .A(GEN1_Final_add_x_1_n204), .Y(n8103) );
AOI21X1TS U7729 ( .A0(n8105), .A1(n8104), .B0(n8103), .Y(n8108) );
NAND2X1TS U7730 ( .A(n8106), .B(GEN1_Final_add_x_1_n199), .Y(n8107) );
XOR2XLTS U7731 ( .A(n8108), .B(n8107), .Y(n8109) );
MX2X1TS U7732 ( .A(sgf_result_o[62]), .B(n8109), .S0(n8127), .Y(n48) );
INVX2TS U7733 ( .A(n8116), .Y(n8125) );
NAND2X1TS U7734 ( .A(n8115), .B(GEN1_Final_add_x_1_n191), .Y(n8112) );
XOR2XLTS U7735 ( .A(n8125), .B(n8112), .Y(n8113) );
MX2X1TS U7736 ( .A(sgf_result_o[63]), .B(n8113), .S0(n8127), .Y(n47) );
INVX2TS U7737 ( .A(GEN1_Final_add_x_1_n191), .Y(n8114) );
AOI21X1TS U7738 ( .A0(n8116), .A1(n8115), .B0(n8114), .Y(n8119) );
NAND2X1TS U7739 ( .A(n8117), .B(GEN1_Final_add_x_1_n186), .Y(n8118) );
XOR2XLTS U7740 ( .A(n8119), .B(n8118), .Y(n8120) );
MX2X1TS U7741 ( .A(sgf_result_o[64]), .B(n8120), .S0(n8127), .Y(n46) );
NAND2X1TS U7742 ( .A(n8130), .B(GEN1_Final_add_x_1_n179), .Y(n8126) );
XNOR2X1TS U7743 ( .A(n8131), .B(n8126), .Y(n8128) );
MX2X1TS U7744 ( .A(sgf_result_o[65]), .B(n8128), .S0(n8127), .Y(n45) );
INVX2TS U7745 ( .A(GEN1_Final_add_x_1_n179), .Y(n8129) );
AOI21X1TS U7746 ( .A0(n8131), .A1(n8130), .B0(n8129), .Y(n8134) );
INVX2TS U7747 ( .A(GEN1_Final_add_x_1_n173), .Y(n8132) );
NAND2X1TS U7748 ( .A(n8132), .B(GEN1_Final_add_x_1_n174), .Y(n8133) );
XOR2XLTS U7749 ( .A(n8134), .B(n8133), .Y(n8135) );
INVX2TS U7750 ( .A(n8297), .Y(n8192) );
MX2X1TS U7751 ( .A(sgf_result_o[66]), .B(n8135), .S0(n8192), .Y(n44) );
INVX2TS U7752 ( .A(n8144), .Y(n8164) );
NAND2X1TS U7753 ( .A(n8143), .B(GEN1_Final_add_x_1_n162), .Y(n8140) );
XOR2XLTS U7754 ( .A(n8164), .B(n8140), .Y(n8141) );
MX2X1TS U7755 ( .A(sgf_result_o[67]), .B(n8141), .S0(n8192), .Y(n43) );
INVX2TS U7756 ( .A(GEN1_Final_add_x_1_n162), .Y(n8142) );
AOI21X1TS U7757 ( .A0(n8144), .A1(n8143), .B0(n8142), .Y(n8147) );
NAND2X1TS U7758 ( .A(n8145), .B(GEN1_Final_add_x_1_n157), .Y(n8146) );
XOR2XLTS U7759 ( .A(n8147), .B(n8146), .Y(n8148) );
MX2X1TS U7760 ( .A(sgf_result_o[68]), .B(n8148), .S0(n8192), .Y(n42) );
NAND2X1TS U7761 ( .A(n8156), .B(GEN1_Final_add_x_1_n150), .Y(n8153) );
XNOR2X1TS U7762 ( .A(n8157), .B(n8153), .Y(n8154) );
MX2X1TS U7763 ( .A(sgf_result_o[69]), .B(n8154), .S0(n8192), .Y(n41) );
INVX2TS U7764 ( .A(GEN1_Final_add_x_1_n150), .Y(n8155) );
AOI21X1TS U7765 ( .A0(n8157), .A1(n8156), .B0(n8155), .Y(n8160) );
NAND2X1TS U7766 ( .A(n8158), .B(GEN1_Final_add_x_1_n145), .Y(n8159) );
MX2X1TS U7767 ( .A(sgf_result_o[70]), .B(n8161), .S0(n8192), .Y(n40) );
NAND2X1TS U7768 ( .A(n8168), .B(GEN1_Final_add_x_1_n137), .Y(n8165) );
MX2X1TS U7769 ( .A(sgf_result_o[71]), .B(n8166), .S0(n8192), .Y(n39) );
INVX2TS U7770 ( .A(GEN1_Final_add_x_1_n137), .Y(n8167) );
AOI21X1TS U7771 ( .A0(n8169), .A1(n8168), .B0(n8167), .Y(n8172) );
NAND2X1TS U7772 ( .A(n8170), .B(GEN1_Final_add_x_1_n132), .Y(n8171) );
MX2X1TS U7773 ( .A(sgf_result_o[72]), .B(n8173), .S0(n8192), .Y(n38) );
NAND2X1TS U7774 ( .A(n8182), .B(GEN1_Final_add_x_1_n125), .Y(n8179) );
XNOR2X1TS U7775 ( .A(n8183), .B(n8179), .Y(n8180) );
MX2X1TS U7776 ( .A(sgf_result_o[73]), .B(n8180), .S0(n8192), .Y(n37) );
INVX2TS U7777 ( .A(GEN1_Final_add_x_1_n125), .Y(n8181) );
AOI21X1TS U7778 ( .A0(n8183), .A1(n8182), .B0(n8181), .Y(n8186) );
NAND2X1TS U7779 ( .A(n8184), .B(GEN1_Final_add_x_1_n120), .Y(n8185) );
MX2X1TS U7780 ( .A(sgf_result_o[74]), .B(n8187), .S0(n8192), .Y(n36) );
INVX2TS U7781 ( .A(n8195), .Y(n8209) );
NAND2X1TS U7782 ( .A(n8316), .B(GEN1_Final_add_x_1_n108), .Y(n8191) );
XOR2XLTS U7783 ( .A(n8209), .B(n8191), .Y(n8193) );
MX2X1TS U7784 ( .A(sgf_result_o[75]), .B(n8193), .S0(n8192), .Y(n35) );
AOI21X1TS U7785 ( .A0(n8195), .A1(n8316), .B0(n8194), .Y(n8197) );
NAND2X1TS U7786 ( .A(n8314), .B(GEN1_Final_add_x_1_n103), .Y(n8196) );
XOR2XLTS U7787 ( .A(n8197), .B(n8196), .Y(n8198) );
INVX2TS U7788 ( .A(n8297), .Y(n8213) );
MX2X1TS U7789 ( .A(sgf_result_o[76]), .B(n8198), .S0(n8213), .Y(n34) );
NAND2X1TS U7790 ( .A(n8201), .B(GEN1_Final_add_x_1_n96), .Y(n8202) );
XNOR2X1TS U7791 ( .A(n8203), .B(n8202), .Y(n8204) );
MX2X1TS U7792 ( .A(sgf_result_o[77]), .B(n8204), .S0(n8213), .Y(n33) );
XNOR2X1TS U7793 ( .A(n8211), .B(n8210), .Y(n8212) );
MX2X1TS U7794 ( .A(sgf_result_o[78]), .B(n8212), .S0(n8213), .Y(n32) );
MX2X1TS U7795 ( .A(sgf_result_o[79]), .B(Result[79]), .S0(n8213), .Y(n31) );
MX2X1TS U7796 ( .A(sgf_result_o[80]), .B(Result[80]), .S0(n8213), .Y(n30) );
MX2X1TS U7797 ( .A(sgf_result_o[81]), .B(Result[81]), .S0(n8213), .Y(n29) );
MX2X1TS U7798 ( .A(sgf_result_o[82]), .B(Result[82]), .S0(n8213), .Y(n28) );
MX2X1TS U7799 ( .A(sgf_result_o[83]), .B(Result[83]), .S0(n8213), .Y(n27) );
MX2X1TS U7800 ( .A(sgf_result_o[84]), .B(Result[84]), .S0(n8213), .Y(n26) );
MX2X1TS U7801 ( .A(sgf_result_o[85]), .B(Result[85]), .S0(n8213), .Y(n25) );
INVX2TS U7802 ( .A(n8019), .Y(n8214) );
MX2X1TS U7803 ( .A(sgf_result_o[86]), .B(Result[86]), .S0(n8214), .Y(n24) );
MX2X1TS U7804 ( .A(sgf_result_o[87]), .B(Result[87]), .S0(n8214), .Y(n23) );
MX2X1TS U7805 ( .A(sgf_result_o[88]), .B(Result[88]), .S0(n8214), .Y(n22) );
MX2X1TS U7806 ( .A(sgf_result_o[89]), .B(Result[89]), .S0(n8214), .Y(n21) );
INVX2TS U7807 ( .A(n8297), .Y(n8215) );
CLKAND2X2TS U7808 ( .A(n8317), .B(GEN1_Final_add_x_1_n388), .Y(n8216) );
AO22XLTS U7809 ( .A0(n8331), .A1(n8216), .B0(n8332), .B1(sgf_result_o[27]),
.Y(n83) );
INVX2TS U7810 ( .A(n8311), .Y(n8264) );
INVX2TS U7811 ( .A(GEN1_Final_add_x_1_n385), .Y(n8217) );
NAND2X1TS U7812 ( .A(n8217), .B(GEN1_Final_add_x_1_n386), .Y(n8218) );
XOR2XLTS U7813 ( .A(n8218), .B(GEN1_Final_add_x_1_n388), .Y(n8219) );
AO22XLTS U7814 ( .A0(n8264), .A1(n8219), .B0(n8332), .B1(sgf_result_o[28]),
.Y(n82) );
INVX2TS U7815 ( .A(n8220), .Y(n8224) );
INVX2TS U7816 ( .A(GEN1_Final_add_x_1_n381), .Y(n8221) );
NAND2X1TS U7817 ( .A(n8221), .B(GEN1_Final_add_x_1_n382), .Y(n8222) );
XOR2XLTS U7818 ( .A(n8224), .B(n8222), .Y(n8223) );
AO22XLTS U7819 ( .A0(n8264), .A1(n8223), .B0(n8256), .B1(sgf_result_o[29]),
.Y(n81) );
INVX2TS U7820 ( .A(GEN1_Final_add_x_1_n378), .Y(n8225) );
NAND2X1TS U7821 ( .A(n8225), .B(GEN1_Final_add_x_1_n379), .Y(n8226) );
XNOR2X1TS U7822 ( .A(n8227), .B(n8226), .Y(n8228) );
AO22XLTS U7823 ( .A0(n8264), .A1(n8228), .B0(n8256), .B1(sgf_result_o[30]),
.Y(n80) );
INVX2TS U7824 ( .A(n8229), .Y(n8240) );
INVX2TS U7825 ( .A(GEN1_Final_add_x_1_n372), .Y(n8233) );
NAND2X1TS U7826 ( .A(n8233), .B(GEN1_Final_add_x_1_n373), .Y(n8230) );
XNOR2X1TS U7827 ( .A(n8240), .B(n8230), .Y(n8231) );
AO22XLTS U7828 ( .A0(n8264), .A1(n8231), .B0(n8256), .B1(sgf_result_o[31]),
.Y(n79) );
INVX2TS U7829 ( .A(GEN1_Final_add_x_1_n373), .Y(n8232) );
AOI21X1TS U7830 ( .A0(n8240), .A1(n8233), .B0(n8232), .Y(n8236) );
INVX2TS U7831 ( .A(GEN1_Final_add_x_1_n367), .Y(n8234) );
NAND2X1TS U7832 ( .A(n8234), .B(GEN1_Final_add_x_1_n368), .Y(n8235) );
XOR2XLTS U7833 ( .A(n8236), .B(n8235), .Y(n8237) );
AO22XLTS U7834 ( .A0(n8264), .A1(n8237), .B0(n8256), .B1(sgf_result_o[32]),
.Y(n78) );
AOI21X1TS U7835 ( .A0(n8240), .A1(n8239), .B0(n8238), .Y(n8244) );
INVX2TS U7836 ( .A(GEN1_Final_add_x_1_n362), .Y(n8241) );
NAND2X1TS U7837 ( .A(n8241), .B(GEN1_Final_add_x_1_n363), .Y(n8242) );
XOR2XLTS U7838 ( .A(n8244), .B(n8242), .Y(n8243) );
AO22XLTS U7839 ( .A0(n8264), .A1(n8243), .B0(n8256), .B1(sgf_result_o[33]),
.Y(n77) );
OAI21XLTS U7840 ( .A0(n8244), .A1(GEN1_Final_add_x_1_n362), .B0(
GEN1_Final_add_x_1_n363), .Y(n8247) );
INVX2TS U7841 ( .A(GEN1_Final_add_x_1_n359), .Y(n8245) );
NAND2X1TS U7842 ( .A(n8245), .B(GEN1_Final_add_x_1_n360), .Y(n8246) );
XNOR2X1TS U7843 ( .A(n8247), .B(n8246), .Y(n8248) );
AO22XLTS U7844 ( .A0(n8264), .A1(n8248), .B0(n8256), .B1(sgf_result_o[34]),
.Y(n76) );
INVX2TS U7845 ( .A(n8249), .Y(n8274) );
INVX2TS U7846 ( .A(GEN1_Final_add_x_1_n351), .Y(n8250) );
NAND2X1TS U7847 ( .A(n8250), .B(GEN1_Final_add_x_1_n352), .Y(n8251) );
XOR2XLTS U7848 ( .A(n8274), .B(n8251), .Y(n8252) );
AO22XLTS U7849 ( .A0(n8264), .A1(n8252), .B0(n8256), .B1(sgf_result_o[35]),
.Y(n75) );
OAI21XLTS U7850 ( .A0(n8274), .A1(GEN1_Final_add_x_1_n351), .B0(
GEN1_Final_add_x_1_n352), .Y(n8255) );
INVX2TS U7851 ( .A(GEN1_Final_add_x_1_n348), .Y(n8253) );
NAND2X1TS U7852 ( .A(n8253), .B(GEN1_Final_add_x_1_n349), .Y(n8254) );
XNOR2X1TS U7853 ( .A(n8255), .B(n8254), .Y(n8257) );
AO22XLTS U7854 ( .A0(n8264), .A1(n8257), .B0(n8256), .B1(sgf_result_o[36]),
.Y(n74) );
INVX2TS U7855 ( .A(n8258), .Y(n8261) );
INVX2TS U7856 ( .A(n8259), .Y(n8260) );
INVX2TS U7857 ( .A(GEN1_Final_add_x_1_n341), .Y(n8266) );
NAND2X1TS U7858 ( .A(n8266), .B(GEN1_Final_add_x_1_n342), .Y(n8262) );
XNOR2X1TS U7859 ( .A(n8267), .B(n8262), .Y(n8263) );
AO22XLTS U7860 ( .A0(n8264), .A1(n8263), .B0(n8297), .B1(sgf_result_o[37]),
.Y(n73) );
INVX2TS U7861 ( .A(n8311), .Y(n8313) );
INVX2TS U7862 ( .A(GEN1_Final_add_x_1_n342), .Y(n8265) );
AOI21X1TS U7863 ( .A0(n8267), .A1(n8266), .B0(n8265), .Y(n8270) );
INVX2TS U7864 ( .A(GEN1_Final_add_x_1_n336), .Y(n8268) );
NAND2X1TS U7865 ( .A(n8268), .B(GEN1_Final_add_x_1_n337), .Y(n8269) );
XOR2XLTS U7866 ( .A(n8270), .B(n8269), .Y(n8271) );
AO22XLTS U7867 ( .A0(n8313), .A1(n8271), .B0(n8019), .B1(sgf_result_o[38]),
.Y(n72) );
INVX2TS U7868 ( .A(n8279), .Y(n8288) );
INVX2TS U7869 ( .A(GEN1_Final_add_x_1_n328), .Y(n8278) );
NAND2X1TS U7870 ( .A(n8278), .B(GEN1_Final_add_x_1_n329), .Y(n8275) );
XOR2XLTS U7871 ( .A(n8288), .B(n8275), .Y(n8276) );
AO22XLTS U7872 ( .A0(n8313), .A1(n8276), .B0(n8297), .B1(sgf_result_o[39]),
.Y(n71) );
INVX2TS U7873 ( .A(GEN1_Final_add_x_1_n329), .Y(n8277) );
AOI21X1TS U7874 ( .A0(n8279), .A1(n8278), .B0(n8277), .Y(n8282) );
INVX2TS U7875 ( .A(GEN1_Final_add_x_1_n323), .Y(n8280) );
NAND2X1TS U7876 ( .A(n8280), .B(GEN1_Final_add_x_1_n324), .Y(n8281) );
XOR2XLTS U7877 ( .A(n8282), .B(n8281), .Y(n8283) );
AO22XLTS U7878 ( .A0(n8313), .A1(n8283), .B0(n8297), .B1(sgf_result_o[40]),
.Y(n70) );
INVX2TS U7879 ( .A(n8284), .Y(n8287) );
INVX2TS U7880 ( .A(n8285), .Y(n8286) );
INVX2TS U7881 ( .A(GEN1_Final_add_x_1_n316), .Y(n8292) );
NAND2X1TS U7882 ( .A(n8292), .B(GEN1_Final_add_x_1_n317), .Y(n8289) );
XNOR2X1TS U7883 ( .A(n8293), .B(n8289), .Y(n8290) );
AO22XLTS U7884 ( .A0(n8313), .A1(n8290), .B0(n8297), .B1(sgf_result_o[41]),
.Y(n69) );
INVX2TS U7885 ( .A(GEN1_Final_add_x_1_n317), .Y(n8291) );
AOI21X1TS U7886 ( .A0(n8293), .A1(n8292), .B0(n8291), .Y(n8296) );
INVX2TS U7887 ( .A(GEN1_Final_add_x_1_n311), .Y(n8294) );
NAND2X1TS U7888 ( .A(n8294), .B(GEN1_Final_add_x_1_n312), .Y(n8295) );
XOR2XLTS U7889 ( .A(n8296), .B(n8295), .Y(n8298) );
AO22XLTS U7890 ( .A0(n8313), .A1(n8298), .B0(n8297), .B1(sgf_result_o[42]),
.Y(n68) );
NAND2X1TS U7891 ( .A(n8302), .B(GEN1_Final_add_x_1_n302), .Y(n8299) );
XNOR2X1TS U7892 ( .A(n8303), .B(n8299), .Y(n8300) );
AO22XLTS U7893 ( .A0(n8313), .A1(n8300), .B0(n8311), .B1(sgf_result_o[43]),
.Y(n67) );
INVX2TS U7894 ( .A(GEN1_Final_add_x_1_n302), .Y(n8301) );
AOI21X1TS U7895 ( .A0(n8303), .A1(n8302), .B0(n8301), .Y(n8306) );
NAND2X1TS U7896 ( .A(n8304), .B(GEN1_Final_add_x_1_n297), .Y(n8305) );
XOR2XLTS U7897 ( .A(n8306), .B(n8305), .Y(n8307) );
AO22XLTS U7898 ( .A0(n8313), .A1(n8307), .B0(n8311), .B1(sgf_result_o[44]),
.Y(n66) );
NAND2X1TS U7899 ( .A(n8308), .B(GEN1_Final_add_x_1_n292), .Y(n8309) );
XOR2XLTS U7900 ( .A(n8310), .B(n8309), .Y(n8312) );
AO22XLTS U7901 ( .A0(n8313), .A1(n8312), .B0(n8311), .B1(sgf_result_o[45]),
.Y(n65) );
ADDHXLTS U7902 ( .A(Q_left[46]), .B(GEN1_Final_add_x_1_n60), .CO(
GEN1_Final_add_x_1_n59), .S(Result[100]) );
ADDHXLTS U7903 ( .A(Q_left[47]), .B(GEN1_Final_add_x_1_n59), .CO(
GEN1_Final_add_x_1_n58), .S(Result[101]) );
ADDHXLTS U7904 ( .A(Q_left[48]), .B(GEN1_Final_add_x_1_n58), .CO(
GEN1_Final_add_x_1_n57), .S(Result[102]) );
ADDHXLTS U7905 ( .A(Q_left[49]), .B(GEN1_Final_add_x_1_n57), .CO(
GEN1_Final_add_x_1_n56), .S(Result[103]) );
ADDHXLTS U7906 ( .A(Q_left[50]), .B(GEN1_Final_add_x_1_n56), .CO(
GEN1_Final_add_x_1_n55), .S(Result[104]) );
ADDHXLTS U7907 ( .A(Q_left[51]), .B(GEN1_Final_add_x_1_n55), .CO(
GEN1_Final_add_x_1_n54), .S(Result[105]) );
NAND2X1TS U7908 ( .A(Q_left[3]), .B(S_B[30]), .Y(GEN1_Final_add_x_1_n229) );
NAND2X1TS U7909 ( .A(Q_left[1]), .B(S_B[28]), .Y(GEN1_Final_add_x_1_n237) );
NAND2X1TS U7910 ( .A(Q_right[53]), .B(S_B[26]), .Y(GEN1_Final_add_x_1_n250)
);
NAND2X1TS U7911 ( .A(Q_right[51]), .B(S_B[24]), .Y(GEN1_Final_add_x_1_n258)
);
NAND2X1TS U7912 ( .A(Q_right[49]), .B(S_B[22]), .Y(GEN1_Final_add_x_1_n271)
);
NAND2X1TS U7913 ( .A(Q_right[47]), .B(S_B[20]), .Y(GEN1_Final_add_x_1_n279)
);
NAND2X1TS U7914 ( .A(Q_right[45]), .B(S_B[18]), .Y(GEN1_Final_add_x_1_n292)
);
NAND2X1TS U7915 ( .A(Q_right[41]), .B(S_B[14]), .Y(GEN1_Final_add_x_1_n317)
);
NAND2X1TS U7916 ( .A(Q_right[39]), .B(S_B[12]), .Y(GEN1_Final_add_x_1_n329)
);
NAND2X1TS U7917 ( .A(Q_left[20]), .B(S_B[47]), .Y(GEN1_Final_add_x_1_n120)
);
NAND2X1TS U7918 ( .A(Q_left[18]), .B(S_B[45]), .Y(GEN1_Final_add_x_1_n132)
);
NAND2X1TS U7919 ( .A(Q_left[16]), .B(S_B[43]), .Y(GEN1_Final_add_x_1_n145)
);
NAND2X1TS U7920 ( .A(Q_left[14]), .B(S_B[41]), .Y(GEN1_Final_add_x_1_n157)
);
NAND2X1TS U7921 ( .A(Q_left[12]), .B(S_B[39]), .Y(GEN1_Final_add_x_1_n174)
);
NAND2X1TS U7922 ( .A(Q_left[8]), .B(S_B[35]), .Y(GEN1_Final_add_x_1_n199) );
NAND2X1TS U7923 ( .A(Q_left[6]), .B(S_B[33]), .Y(GEN1_Final_add_x_1_n211) );
NAND2X1TS U7924 ( .A(Q_left[2]), .B(S_B[29]), .Y(GEN1_Final_add_x_1_n234) );
NAND2X1TS U7925 ( .A(Q_left[0]), .B(S_B[27]), .Y(GEN1_Final_add_x_1_n247) );
NAND2X1TS U7926 ( .A(Q_right[52]), .B(S_B[25]), .Y(GEN1_Final_add_x_1_n255)
);
NAND2X1TS U7927 ( .A(Q_right[50]), .B(S_B[23]), .Y(GEN1_Final_add_x_1_n268)
);
NAND2X1TS U7928 ( .A(Q_right[48]), .B(S_B[21]), .Y(GEN1_Final_add_x_1_n276)
);
NAND2X1TS U7929 ( .A(Q_right[46]), .B(S_B[19]), .Y(GEN1_Final_add_x_1_n289)
);
NAND2X1TS U7930 ( .A(Q_right[44]), .B(S_B[17]), .Y(GEN1_Final_add_x_1_n297)
);
NAND2X1TS U7931 ( .A(Q_right[42]), .B(S_B[15]), .Y(GEN1_Final_add_x_1_n312)
);
NAND2X1TS U7932 ( .A(Q_right[40]), .B(S_B[13]), .Y(GEN1_Final_add_x_1_n324)
);
NAND2X1TS U7933 ( .A(Q_right[38]), .B(S_B[11]), .Y(GEN1_Final_add_x_1_n337)
);
NAND2X1TS U7934 ( .A(Q_right[28]), .B(S_B[1]), .Y(GEN1_Final_add_x_1_n386)
);
NAND2X1TS U7935 ( .A(Q_left[22]), .B(S_B[49]), .Y(GEN1_Final_add_x_1_n103)
);
NAND2X1TS U7936 ( .A(Q_left[21]), .B(S_B[48]), .Y(GEN1_Final_add_x_1_n108)
);
ADDHXLTS U7937 ( .A(Q_left[52]), .B(GEN1_Final_add_x_1_n54), .CO(
GEN1_Final_add_x_1_n53), .S(Result[106]) );
NAND2X1TS U7938 ( .A(Q_left[23]), .B(S_B[50]), .Y(GEN1_Final_add_x_1_n96) );
NAND2X1TS U7939 ( .A(Q_left[4]), .B(S_B[31]), .Y(GEN1_Final_add_x_1_n226) );
NAND2X1TS U7940 ( .A(Q_left[24]), .B(S_B[51]), .Y(GEN1_Final_add_x_1_n89) );
OR2X1TS U7941 ( .A(Q_left[22]), .B(S_B[49]), .Y(n8314) );
OR2X1TS U7942 ( .A(Q_left[21]), .B(S_B[48]), .Y(n8316) );
OR2X1TS U7943 ( .A(Q_right[27]), .B(S_B[0]), .Y(n8317) );
AO22XLTS U7944 ( .A0(n8329), .A1(Result[0]), .B0(n8311), .B1(sgf_result_o[0]), .Y(n110) );
AO22XLTS U7945 ( .A0(n8329), .A1(Result[1]), .B0(n8311), .B1(sgf_result_o[1]), .Y(n109) );
AO22XLTS U7946 ( .A0(n8329), .A1(Result[2]), .B0(n8311), .B1(sgf_result_o[2]), .Y(n108) );
AO22XLTS U7947 ( .A0(n8329), .A1(Result[3]), .B0(n8019), .B1(sgf_result_o[3]), .Y(n107) );
AO22XLTS U7948 ( .A0(n8329), .A1(Result[4]), .B0(n8019), .B1(sgf_result_o[4]), .Y(n106) );
AO22XLTS U7949 ( .A0(n8329), .A1(Result[5]), .B0(n8019), .B1(sgf_result_o[5]), .Y(n105) );
AO22XLTS U7950 ( .A0(n8329), .A1(Result[6]), .B0(n8019), .B1(sgf_result_o[6]), .Y(n104) );
AO22XLTS U7951 ( .A0(n8329), .A1(Result[7]), .B0(n8019), .B1(sgf_result_o[7]), .Y(n103) );
AO22XLTS U7952 ( .A0(n8330), .A1(Result[8]), .B0(n8019), .B1(sgf_result_o[8]), .Y(n102) );
AO22XLTS U7953 ( .A0(n8330), .A1(Result[9]), .B0(n8333), .B1(sgf_result_o[9]), .Y(n101) );
AO22XLTS U7954 ( .A0(n8330), .A1(Result[10]), .B0(n8333), .B1(
sgf_result_o[10]), .Y(n100) );
AO22XLTS U7955 ( .A0(n8330), .A1(Result[11]), .B0(n8333), .B1(
sgf_result_o[11]), .Y(n99) );
AO22XLTS U7956 ( .A0(n8330), .A1(Result[12]), .B0(n8333), .B1(
sgf_result_o[12]), .Y(n98) );
AO22XLTS U7957 ( .A0(n8330), .A1(Result[13]), .B0(n8333), .B1(
sgf_result_o[13]), .Y(n97) );
AO22XLTS U7958 ( .A0(n8330), .A1(Result[14]), .B0(n8333), .B1(
sgf_result_o[14]), .Y(n96) );
AO22XLTS U7959 ( .A0(n8330), .A1(Result[15]), .B0(n8333), .B1(
sgf_result_o[15]), .Y(n95) );
AO22XLTS U7960 ( .A0(n8330), .A1(Result[16]), .B0(n8333), .B1(
sgf_result_o[16]), .Y(n94) );
AO22XLTS U7961 ( .A0(n8330), .A1(Result[17]), .B0(n8333), .B1(
sgf_result_o[17]), .Y(n93) );
AO22XLTS U7962 ( .A0(n8331), .A1(Result[18]), .B0(n8333), .B1(
sgf_result_o[18]), .Y(n92) );
AO22XLTS U7963 ( .A0(n8331), .A1(Result[19]), .B0(n8332), .B1(
sgf_result_o[19]), .Y(n91) );
AO22XLTS U7964 ( .A0(n8331), .A1(Result[20]), .B0(n8332), .B1(
sgf_result_o[20]), .Y(n90) );
AO22XLTS U7965 ( .A0(n8331), .A1(Result[21]), .B0(n8332), .B1(
sgf_result_o[21]), .Y(n89) );
AO22XLTS U7966 ( .A0(n8331), .A1(Result[22]), .B0(n8332), .B1(
sgf_result_o[22]), .Y(n88) );
AO22XLTS U7967 ( .A0(n8331), .A1(Result[23]), .B0(n8332), .B1(
sgf_result_o[23]), .Y(n87) );
AO22XLTS U7968 ( .A0(n8331), .A1(Result[24]), .B0(n8332), .B1(
sgf_result_o[24]), .Y(n86) );
AO22XLTS U7969 ( .A0(n8331), .A1(Result[25]), .B0(n8332), .B1(
sgf_result_o[25]), .Y(n85) );
AO22XLTS U7970 ( .A0(n8331), .A1(Result[26]), .B0(n8332), .B1(
sgf_result_o[26]), .Y(n84) );
initial $sdf_annotate("Sgf_Multiplication_syn.sdf");
initial $sdf_annotate("Sgf_Multiplication_syn.sdf");
initial $sdf_annotate("Sgf_Multiplication_syn.sdf");
endmodule
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